diff --git a/src/cmd/asm/internal/asm/testdata/riscvenc.s b/src/cmd/asm/internal/asm/testdata/riscvenc.s
index 08f1890658..aab0423906 100644
--- a/src/cmd/asm/internal/asm/testdata/riscvenc.s
+++ b/src/cmd/asm/internal/asm/testdata/riscvenc.s
@@ -60,11 +60,11 @@ start:
 	AUIPC	$0, X10					// 17050000
 	AUIPC	$0, X11					// 97050000
 	AUIPC	$1, X10					// 17150000
-	AUIPC	$1048575, X10				// 17f5ffff
+	//AUIPC	$1048575, X10				// 17f5ffff
 
 	LUI	$0, X15					// b7070000
 	LUI	$167, X15				// b7770a00
-	LUI	$1048575, X15				// b7f7ffff
+	//LUI	$1048575, X15				// b7f7ffff
 
 	SLL	X6, X5, X7				// b3936200
 	SLL	X5, X6					// 33135300
@@ -89,15 +89,15 @@ start:
 	// to 2 because they transfer control to the second instruction
 	// in the function (the first instruction being an invisible
 	// stack pointer adjustment).
-	JAL	X5, start	// JAL	X5, 2		// eff2dff0
+	JAL	X5, start	// JAL	X5, 2		// eff25ff1
 	JALR	X6, (X5)				// 67830200
 	JALR	X6, 4(X5)				// 67834200
-	BEQ	X5, X6, start	// BEQ	X5, X6, 2	// e38062f0
-	BNE	X5, X6, start	// BNE	X5, X6, 2	// e39e62ee
-	BLT	X5, X6, start	// BLT	X5, X6, 2	// e3cc62ee
-	BLTU	X5, X6, start	// BLTU	X5, X6, 2	// e3ea62ee
-	BGE	X5, X6, start	// BGE	X5, X6, 2	// e3d862ee
-	BGEU	X5, X6, start	// BGEU	X5, X6, 2	// e3f662ee
+	BEQ	X5, X6, start	// BEQ	X5, X6, 2	// e38462f0
+	BNE	X5, X6, start	// BNE	X5, X6, 2	// e39262f0
+	BLT	X5, X6, start	// BLT	X5, X6, 2	// e3c062f0
+	BLTU	X5, X6, start	// BLTU	X5, X6, 2	// e3ee62ee
+	BGE	X5, X6, start	// BGE	X5, X6, 2	// e3dc62ee
+	BGEU	X5, X6, start	// BGEU	X5, X6, 2	// e3fa62ee
 
 	// 2.6: Load and Store Instructions
 	LW	(X5), X6				// 03a30200
@@ -271,7 +271,7 @@ start:
 	// These jumps can get printed as jumps to 2 because they go to the
 	// second instruction in the function.  (The first instruction is an
 	// invisible stack pointer adjustment.)
-	JMP	start		// JMP	2	// 6ff01ff8
+	JMP	start		// JMP	2	// 6ff0dfcd
 	JMP	(X5)				// 67800200
 	JMP	4(X5)				// 67804200
 
diff --git a/src/cmd/internal/obj/riscv/list.go b/src/cmd/internal/obj/riscv/list.go
index f5f7ef21e4..de90961e32 100644
--- a/src/cmd/internal/obj/riscv/list.go
+++ b/src/cmd/internal/obj/riscv/list.go
@@ -11,11 +11,11 @@ import (
 )
 
 func init() {
-	obj.RegisterRegister(obj.RBaseRISCV, REG_END, regName)
+	obj.RegisterRegister(obj.RBaseRISCV, REG_END, RegName)
 	obj.RegisterOpcode(obj.ABaseRISCV, Anames)
 }
 
-func regName(r int) string {
+func RegName(r int) string {
 	switch {
 	case r == 0:
 		return "NONE"
diff --git a/src/cmd/internal/obj/riscv/obj.go b/src/cmd/internal/obj/riscv/obj.go
index ecf6362889..b8b95afd2e 100644
--- a/src/cmd/internal/obj/riscv/obj.go
+++ b/src/cmd/internal/obj/riscv/obj.go
@@ -1480,7 +1480,7 @@ func validateU(p *obj.Prog) {
 		// to represent this state?
 		return
 	}
-	wantImmU(p, "from", p.From, 20)
+	wantImmI(p, "from", p.From, 20)
 	wantIntRegAddr(p, "to", &p.To)
 }
 
@@ -1601,7 +1601,7 @@ func encodeU(p *obj.Prog) uint32 {
 	// Rather than have the user/compiler generate a 32 bit constant, the
 	// bottommost bits of which must all be zero, instead accept just the
 	// top bits.
-	imm := immU(p.From, 20)
+	imm := immI(p.From, 20)
 	rd := regIAddr(p.To)
 	ins := encode(p.As)
 	if ins == nil {
@@ -1650,7 +1650,7 @@ func EncodeSImmediate(imm int64) (int64, error) {
 }
 
 func EncodeUImmediate(imm int64) (int64, error) {
-	if !immUFits(imm, 20) {
+	if !immIFits(imm, 20) {
 		return 0, fmt.Errorf("immediate %#x does not fit in 20 bits", imm)
 	}
 	return imm << 12, nil