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arm_isa.cpp
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/**
* @file arm_isa.cpp
* @author Danilo Marcolin Caravana
* Rafael Auler
*
* The ArchC Team
* http://www.archc.org/
*
* Computer Systems Laboratory (LSC)
* IC-UNICAMP
* http://www.lsc.ic.unicamp.br/
*
* @version 1.0
* @date Apr 2012
*
* @brief The ArchC ARMv5e functional model.
*
* @attention Copyright (C) 2002-2012 --- The ArchC Team
*
*/
#include "arm_isa.H"
#include "arm_isa_init.cpp"
#include "arm_bhv_macros.H"
#include <stdint.h> // define types uint32_t, etc
using namespace arm_parms;
#define DEFAULT_STACK_SIZE (512 * 1024)
static int processors_started = 0;
//If you want debug information for this model, uncomment next line
//#define DEBUG_MODEL
//If you want the processor to operate in system model instead
//of user model, uncomment next line
//#define SYSTEM_MODEL
//This is a switch to turn unpredictable behavior for some
//instructions to be silently ignored. This is necessary for
//some gcc generated ARM user level code.
#define FORGIVE_UNPREDICTABLE
// If FORGIVE_UNPREDITABLE is turned on, necessarily turns off
// SYSTEM_MODEL, since the system model cannot work with this flag.
#ifdef FORGIVE_UNPREDITABLE
#undef SYSTEM_MODEL
#endif
#ifdef DEBUG_MODEL
#include <stdarg.h>
static inline int dprintf(const char *format, ...) {
int ret;
va_list args;
va_start(args, format);
ret = vfprintf(ac_err, format, args);
va_end(args);
return ret;
}
#else
inline void dprintf(const char *format, ...) {}
#endif
//! User defined macros to reference registers
#define LR 14 // link return
#define PC 15 // program counter
#ifdef SYSTEM_MODEL
#define RB_write bypass_write
#define RB_read bypass_read
#else
#define RB_write RB.write
#define RB_read RB.read
#endif
#ifdef SLEEP_AWAKE_MODE
/*********************************************************************************/
/* SLEEP / AWAKE mode control */
/* INTR_REG may store 1 (AWAKE MODE) or 0 (SLEEP MODE) */
/* if intr_reg == 0, the simulator will be suspended until it receives a */
/* interruption 1 */
/*********************************************************************************/
#define test_sleep() { if (intr_reg.read() == 0) ac_wait(); }
#else
#define test_sleep() {}
#endif
void ac_behavior( begin ) {
#ifdef SYSTEM_MODEL
arm_proc_mode.mode = processor_mode::SUPERVISOR_MODE;
arm_proc_mode.thumb = false;
arm_proc_mode.fiq = false;
arm_proc_mode.irq = false;
ac_pc = 0;
#endif
// Initializing flags and model variables
flags.Z = false;
flags.C = false;
flags.N = false;
flags.V = false;
flags.Q = false;
flags.T = false;
execute = false;
dpi_shiftop.entire = 0;
dpi_shiftopcarry = false;
ls_address.entire = 0;
lsm_startaddress.entire = 0;
lsm_endaddress.entire = 0;
OP1.entire = 0;
OP2.entire = 0;
RB.write(13, AC_RAM_END - 1024 - processors_started++ * DEFAULT_STACK_SIZE);
}
//!Generic instruction behavior method.
void ac_behavior( instruction ) {
test_sleep();
dprintf("-------------------- PC=%#x -------------------- %lld\n", (uint32_t)ac_pc, ac_instr_counter);
// Conditionally executes instruction based on COND field, common to all ARM instructions.
execute = false;
switch(cond) {
case 0: if (flags.Z == true) execute = true; break;
case 1: if (flags.Z == false) execute = true; break;
case 2: if (flags.C == true) execute = true; break;
case 3: if (flags.C == false) execute = true; break;
case 4: if (flags.N == true) execute = true; break;
case 5: if (flags.N == false) execute = true; break;
case 6: if (flags.V == true) execute = true; break;
case 7: if (flags.V == false) execute = true; break;
case 8: if ((flags.C == true)&&(flags.Z == false)) execute = true; break;
case 9: if ((flags.C == false)||(flags.Z == true)) execute = true; break;
case 10: if (flags.N == flags.V) execute = true; break;
case 11: if (flags.N != flags.V) execute = true; break;
case 12: if ((flags.Z == false)&&(flags.N == flags.V)) execute = true; break;
case 13: if ((flags.Z == true)||(flags.N != flags.V)) execute = true; break;
case 14: execute = true; break;
default: execute = false;
}
// PC increment
ac_pc += 4;
RB_write(PC, ac_pc);
if(!execute) {
dprintf("cond=0x%X\n", cond);
dprintf("Instruction will not be executed due to condition flags.\n");
ac_annul();
}
}
// Instruction Format behavior methods.
//!DPI1 - Second operand is register with imm shift
void ac_behavior( Type_DPI1 ) {
arm_isa::reg_t RM2;
// Special case: rm = 15
if (rm == 15) {
// PC is already incremented by four, so only add 4 again (not 8)
RM2.entire = RB_read(rm) + 4;
}
else RM2.entire = RB_read(rm);
switch(shift) {
case 0: // Logical shift left
if ((shiftamount >= 0) && (shiftamount <= 31)) {
if (shiftamount == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = flags.C;
} else {
dpi_shiftop.entire = RM2.entire << shiftamount;
dpi_shiftopcarry = getBit(RM2.entire, 32 - shiftamount);
}
}
break;
case 1: // Logical shift right
if ((shiftamount >= 0) && (shiftamount <= 31)) {
if (shiftamount == 0) {
dpi_shiftop.entire = 0;
dpi_shiftopcarry = getBit(RM2.entire, 31);
} else {
dpi_shiftop.entire = ((uint32_t) RM2.entire) >> shiftamount;
dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1);
}
}
break;
case 2: // Arithmetic shift right
if ((shiftamount >= 0) && (shiftamount <= 31)) {
if (shiftamount == 0) {
if (!isBitSet(RM2.entire, 31)) {
dpi_shiftop.entire = 0;
dpi_shiftopcarry = getBit(RM2.entire, 31);
} else {
dpi_shiftop.entire = 0xFFFFFFFF;
dpi_shiftopcarry = getBit(RM2.entire, 31);
}
} else {
dpi_shiftop.entire = ((int32_t) RM2.entire) >> shiftamount;
dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1);
}
}
break;
default: // Rotate right
if ((shiftamount >= 0) && (shiftamount <= 31)) {
if (shiftamount == 0) { //Rotate right with extend
dpi_shiftopcarry = getBit(RM2.entire, 0);
dpi_shiftop.entire = (((uint32_t)RM2.entire) >> 1);
if (flags.C) setBit(dpi_shiftop.entire, 31);
} else {
dpi_shiftop.entire = (RotateRight(shiftamount, RM2)).entire;
dpi_shiftopcarry = getBit(RM2.entire, shiftamount - 1);
}
}
}
}
//!DPI2 - Second operand is shifted (shift amount given by third register operand)
void ac_behavior( Type_DPI2 ) {
int rs40;
arm_isa::reg_t RS2, RM2;
// Special case: r* = 15
if ((rd == 15)||(rm == 15)||(rn == 15)||(rs == 15)) {
printf("Register 15 cannot be used in this instruction.\n");
ac_annul();
}
RM2.entire = RB_read(rm);
RS2.entire = RB_read(rs);
rs40 = ((uint32_t)RS2.entire) & 0x0000000F;
switch(shift){
case 0: // Logical shift left
if (RS2.byte[0] == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = flags.C;
}
else if (((uint8_t)RS2.byte[0]) < 32) {
dpi_shiftop.entire = RM2.entire << (uint8_t)RS2.byte[0];
dpi_shiftopcarry = getBit(RM2.entire, 32 - ((uint8_t)RS2.byte[0]));
}
else if (RS2.byte[0] == 32) {
dpi_shiftop.entire = 0;
dpi_shiftopcarry = getBit(RM2.entire, 0);
}
else { // rs > 32
dpi_shiftop.entire = 0;
dpi_shiftopcarry = 0;
}
break;
case 1: // Logical shift right
if (RS2.byte[0] == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = flags.C;
}
else if (((uint8_t)RS2.byte[0]) < 32) {
dpi_shiftop.entire = ((uint32_t) RM2.entire) >> ((uint8_t)RS2.byte[0]);
dpi_shiftopcarry = getBit(RM2.entire, (uint8_t)RS2.byte[0] - 1);
}
else if (RS2.byte[0] == 32) {
dpi_shiftop.entire = 0;
dpi_shiftopcarry = getBit(RM2.entire, 31);
}
else { // rs > 32
dpi_shiftop.entire = 0;
dpi_shiftopcarry = 0;
}
break;
case 2: // Arithmetical shift right
if (RS2.byte[0] == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = flags.C;
}
else if (((uint8_t)RS2.byte[0]) < 32) {
dpi_shiftop.entire = ((int32_t) RM2.entire) >> ((uint8_t)RS2.byte[0]);
dpi_shiftopcarry = getBit(RM2.entire, ((uint8_t)RS2.byte[0]) - 1);
} else { // rs >= 32
if (!isBitSet(RM2.entire, 31)) {
dpi_shiftop.entire = 0;
dpi_shiftopcarry = getBit(RM2.entire, 31);
}
else { // rm_31 == 1
dpi_shiftop.entire = 0xFFFFFFFF;
dpi_shiftopcarry = getBit(RM2.entire, 31);
}
}
break;
default: // Rotate right
if (RS2.byte[0] == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = flags.C;
}
else if (rs40 == 0) {
dpi_shiftop.entire = RM2.entire;
dpi_shiftopcarry = getBit(RM2.entire, 31);
}
else { // rs40 > 0
dpi_shiftop.entire = (RotateRight(rs40, RM2)).entire;
dpi_shiftopcarry = getBit(RM2.entire, rs40 - 1);
}
}
}
//!DPI3 - Second operand is immediate shifted by another imm
void ac_behavior( Type_DPI3 ){
int32_t tmp;
tmp = (uint32_t)imm8;
dpi_shiftop.entire = (((uint32_t)tmp) >> (2 * rotate)) | (((uint32_t)tmp) << (32 - (2 * rotate)));
if (rotate == 0)
dpi_shiftopcarry = flags.C;
else
dpi_shiftopcarry = getBit(dpi_shiftop.entire, 31);
}
void ac_behavior( Type_BBL ) {
// no special actions necessary
}
void ac_behavior( Type_BBLT ) {
// no special actions necessary
}
void ac_behavior( Type_MBXBLX ) {
// no special actions necessary
}
//!MULT1 - 32-bit result multiplication
void ac_behavior( Type_MULT1 ) {
// no special actions necessary
}
//!MULT2 - 64-bit result multiplication
void ac_behavior( Type_MULT2 ) {
// no special actions necessary
}
//!LSI - Load Store Immediate Offset/Index
void ac_behavior( Type_LSI ) {
arm_isa::reg_t RN2;
RN2.entire = RB_read(rn);
ls_address.entire = 0;
if((p == 1)&&(w == 0)) { // immediate pre-indexed without writeback
// Special case: Rn = PC
if (rn == PC)
ls_address.entire = 4;
if(u == 1) {
ls_address.entire += RN2.entire + (uint32_t) imm12;
} else {
ls_address.entire += RN2.entire - (uint32_t) imm12;
}
}
else if((p == 1)&&(w == 1)) { // immediate pre-indexed with writeback
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSI instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case: Rn = Rd
if (rn == rd) {
printf("Unpredictable LSI instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
if(u == 1) {
ls_address.entire = RN2.entire + (uint32_t) imm12;
} else {
ls_address.entire = RN2.entire - (uint32_t) imm12;
}
RB_write(rn,ls_address.entire);
}
else if((p == 0)&&(w == 0)) { // immediate post-indexed (writeback)
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSI instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSI instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
ls_address.entire = RN2.entire;
if(u == 1) {
//checar se imm12 soma direto
RB_write(rn, ls_address.entire + (uint32_t) imm12);
} else {
RB_write(rn, ls_address.entire - (uint32_t) imm12);
}
}
/* FIXME: Check word alignment (Rd = PC) Address[1:0] = 0b00 */
}
//!LSR - Scaled Register Offset/Index
void ac_behavior( Type_LSR ) {
arm_isa::reg_t RM2, RN2, index, tmp;
RM2.entire = RB_read(rm);
RN2.entire = RB_read(rn);
ls_address.entire = 0;
if ((p == 1)&&(w == 0)) { // offset
// Special case: PC
if(rn == PC)
ls_address.entire = 4;
if(rm == PC) {
printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n");
return;
}
switch(shift){
case 0:
if(shiftamount == 0) { // Register
index.entire = RM2.entire;
} else { // Scalled logical shift left
index.entire = RM2.entire << shiftamount;
}
break;
case 1: // logical shift right
if(shiftamount == 0) index.entire = 0;
else index.entire = ((uint32_t) RM2.entire) >> shiftamount;
break;
case 2: // arithmetic shift right
if(shiftamount == 0) {
if (isBitSet(RM2.entire, 31)) index.entire = 0xFFFFFFFF;
else index.entire = 0;
} else index.entire = ((int32_t) RM2.entire) >> shiftamount;
break;
default:
if(shiftamount == 0) { // RRX
tmp.entire = 0;
if(flags.C) setBit(tmp.entire, 31);
index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1);
} else { // rotate right
index.entire = (RotateRight(shiftamount, RM2)).entire;
}
}
if(u == 1) {
ls_address.entire += (RN2.entire + index.entire);
} else {
ls_address.entire += (RN2.entire - index.entire);
}
}
else if((p == 1)&&(w == 1)) { // pre-indexed
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSR instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSR instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
// Special case Rm = PC
if (rm == PC) {
printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rm
if (rn == rm) {
printf("Unpredictable LSR instruction result (Can't use the same register for Rn and Rm\n");
ac_annul();
return;
}
switch(shift){
case 0:
if(shiftamount == 0) { // Register
index.entire = RM2.entire;
} else { // Scaled logical shift left
index.entire = RM2.entire << shiftamount;
}
break;
case 1: // logical shift right
if(shiftamount == 0) index.entire = 0;
else index.entire = ((uint32_t) RM2.entire) >> shiftamount;
break;
case 2: // arithmetic shift right
if(shiftamount == 0) {
if (isBitSet(RM2.entire,31))
index.entire = 0xFFFFFFFF;
else
index.entire = 0;
} else index.entire = ((int32_t) RM2.entire) >> shiftamount;
break;
default:
if(shiftamount == 0) { // RRX
tmp.entire = 0;
if (flags.C) setBit(tmp.entire,31);
index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1);
} else { // rotate right
index.entire = (RotateRight(shiftamount, RM2)).entire;
}
}
if(u == 1) {
ls_address.entire = RN2.entire + index.entire;
} else {
ls_address.entire = RN2.entire - index.entire;
}
RB_write(rn, ls_address.entire);
}
else if((p == 0)&&(w == 0)) { // post-indexed
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSR instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSR instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
// Special case Rm = PC
if (rm == PC) {
printf("Unpredictable LSR instruction result (Illegal usage of PC, Rm = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rm
if (rn == rm) {
printf("Unpredictable LSR instruction result (Can't use the same register for Rn and Rm\n");
ac_annul();
return;
}
ls_address.entire = RN2.entire;
switch(shift) {
case 0:
if(shiftamount == 0) { // Register
index.entire = RM2.entire;
} else { // Scaled logical shift left
index.entire = RM2.entire << shiftamount;
}
break;
case 1: // logical shift right
if(shiftamount == 0) index.entire = 0;
else index.entire = ((uint32_t) RM2.entire) >> shiftamount;
break;
case 2: // arithmetic shift right
if(shiftamount == 0) {
if (isBitSet(RM2.entire, 31))
index.entire = 0xFFFFFFFF;
else
index.entire = 0;
} else index.entire = ((int32_t) RM2.entire) >> shiftamount;
break;
default:
if(shiftamount == 0) { // RRX
tmp.entire = 0;
if(flags.C) setBit(tmp.entire, 31);
index.entire = tmp.entire | (((uint32_t) RM2.entire) >> 1);
} else { // rotate right
index.entire = (RotateRight(shiftamount, RM2)).entire;
}
}
if(u == 1) {
RB_write(rn, RN2.entire + index.entire);
} else {
RB_write(rn, RN2.entire - index.entire);
}
}
}
//!LSE - Load Store HalfWord
void ac_behavior( Type_LSE ){
int32_t off8;
arm_isa::reg_t RM2, RN2;
// Special cases handling
if((p == 0)&&(w == 1)) {
printf("Unpredictable LSE instruction result");
ac_annul();
return;
}
if((ss == 0)&&(hh == 0)) {
printf("Decoding error: this is not a LSE instruction");
ac_annul();
return;
}
if((ss == 1)&&(l == 0))
dprintf("Special DSP\n");
// FIXME: Test LDRD and STRD second registers in case of writeback
RN2.entire = RB_read(rn);
// nos LSE's que usam registrador, o campo addr2 armazena Rm
RM2.entire = RB_read(addr2);
off8 = ((uint32_t)(addr1 << 4) | addr2);
ls_address.entire = 0;
if(p == 1) { // offset ou pre-indexed
if((i == 1)&&(w == 0)) { // immediate offset
if(rn == PC)
ls_address.entire = 4;
if(u == 1) {
ls_address.entire += (RN2.entire + off8);
} else {
ls_address.entire += (RN2.entire - off8);
}
}
else if((i == 0)&&(w == 0)) { // register offset
// Special case Rm = PC
if (addr2 == PC) {
printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n");
ac_annul();
return;
}
if(rn == PC)
ls_address.entire = 4;
if(u == 1) {
ls_address.entire += (RN2.entire + RM2.entire);
} else {
ls_address.entire += (RN2.entire - RM2.entire);
}
}
else if ((i == 1)&&(w == 1)) { // immediate pre-indexed
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
if(u == 1) {
ls_address.entire = (RN2.entire + off8);
} else {
ls_address.entire = (RN2.entire - off8);
}
RB_write(rn, ls_address.entire);
}
else { // i == 0 && w == 1: register pre-indexed
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
// Special case Rm = PC
if (addr2 == PC) {
printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rm
if (rn == addr2) {
printf("Unpredictable LSE instruction result (Can't use the same register for Rn and Rm\n");
ac_annul();
return;
}
if(u == 1) {
ls_address.entire = (RN2.entire + RM2.entire);
} else {
ls_address.entire = (RN2.entire - RM2.entire);
}
RB_write(rn, ls_address.entire);
}
} else { // p == 0: post-indexed
if((i == 1)&&(w == 0)) { // immediate post-indexed
if(rn == PC) {
printf("Unpredictable LSE instruction result");
ac_annul();
return;
}
ls_address.entire = RN2.entire;
if(u == 1) {
RB_write(rn, RN2.entire + off8);
} else {
RB_write(rn, RN2.entire - off8);
}
}
else if((i == 0)&&(w == 0)) { // register post-indexed
// Special case: Rn = PC
if (rn == PC) {
printf("Unpredictable LSE instruction result (Can't writeback to PC, Rn = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rd
if (rn == rd) {
printf("Unpredictable LSE instruction result (Can't writeback to loaded register, Rn = Rd)\n");
ac_annul();
return;
}
// Special case Rm = PC
if (addr2 == PC) {
printf("Unpredictable LSE instruction result (Illegal usage of PC, Rm = PC)\n");
ac_annul();
return;
}
// Special case Rn = Rm
if (rn == addr2) {
printf("Unpredictable LSE instruction result (Can't use the same register for Rn and Rm\n");
ac_annul();
return;
}
ls_address.entire = RN2.entire;
if(u == 1) {
RB_write(rn, RN2.entire + RM2.entire);
} else {
RB_write(rn, RN2.entire - RM2.entire);
}
}
}
}
//!LSM - Load Store Multiple
void ac_behavior( Type_LSM ){
arm_isa::reg_t RN2;
int setbits;
// Put registers list in a variable capable of addressing individual bits
arm_isa::reg_t registerList;
registerList.entire = (uint32_t) rlist;
// Special case - empty list
if (registerList.entire == 0) {
printf("Unpredictable LSM instruction result (No register specified)\n");
ac_annul();
return;
}
RN2.entire = RB_read(rn);
setbits = LSM_CountSetBits(registerList);
// Special case Rn in Rlist
if((w == 1)&&(isBitSet(rlist,rn))) {
lsm_oldrn.entire = RB_read(rn);
}
if((p == 0)&&(u == 1)) { // increment after
lsm_startaddress.entire = RN2.entire;
lsm_endaddress.entire = RN2.entire + (setbits * 4) - 4;
if(w == 1) RN2.entire += (setbits * 4);
}
else if((p == 1)&&(u == 1)) { // increment before
lsm_startaddress.entire = RN2.entire + 4;
lsm_endaddress.entire = RN2.entire + (setbits * 4);
if(w == 1) RN2.entire += (setbits * 4);
}
else if((p == 0)&&(u == 0)) { // decrement after
lsm_startaddress.entire = RN2.entire - (setbits * 4) + 4;
lsm_endaddress.entire = RN2.entire;
if(w == 1) RN2.entire -= (setbits * 4);
}
else { // decrement before
lsm_startaddress.entire = RN2.entire - (setbits * 4);
lsm_endaddress.entire = RN2.entire - 4;
if(w == 1) RN2.entire -= (setbits * 4);
}
RB_write(rn,RN2.entire);
}
void ac_behavior( Type_CDP ){
// no special actions necessary
}
void ac_behavior( Type_CRT ){
// no special actions necessary
}
void ac_behavior( Type_CLS ){
// no special actions necessary
}
void ac_behavior( Type_MBKPT ){
// no special actions necessary
}
void ac_behavior( Type_MSWI ){
// no special actions necessary
}
void ac_behavior( Type_MCLZ ){
// no special actions necessary
}
void ac_behavior( Type_MMSR1 ){
// no special actions necessary
}
void ac_behavior( Type_MMSR2 ){
// no special actions necessary
}
void ac_behavior( Type_DSPSM ){
arm_isa::reg_t RM2, RS2;
RM2.entire = RB_read(rm);
RS2.entire = RB_read(rs);
// Special cases
if((drd == PC)||(drn == PC)||(rm == PC)||(rs == PC)) {
printf("Unpredictable SMLA<y><x> instruction result\n");
return;
}
if(xx == 0)
OP1.entire = SignExtend(RM2.entire, 16);
else
OP1.entire = SignExtend((RM2.entire >> 16), 16);
if(yy == 0)
OP2.entire = SignExtend(RS2.entire, 16);
else
OP2.entire = SignExtend((RS2.entire >> 16), 16);
}
//! Behavior Methods
//------------------------------------------------------
void arm_isa::ADC(int rd, int rn, bool s) {
arm_isa::reg_t RD2, RN2;
arm_isa::r64bit_t soma;
dprintf("Instruction: ADC\n");
RN2.entire = RB_read(rn);
if(rn == PC) RN2.entire += 4;
dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n Carry=%d\n", RN2.entire,dpi_shiftop.entire,flags.C);
soma.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)dpi_shiftop.entire;
if (flags.C) soma.hilo++;
RD2.entire = soma.reg[0];
RB_write(rd, RD2.entire);
if ((s == 1)&&(rd == PC)) {
#ifndef FORGIVE_UNPREDICTABLE
printf("Unpredictable ADC instruction result\n");
return;
#endif
} else {
if (s == 1) {
flags.N = getBit(RD2.entire,31);
flags.Z = ((RD2.entire == 0) ? true : false);
flags.C = ((soma.reg[1] != 0) ? true : false);
flags.V = (((getBit(RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) ||
((!getBit(RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false);
}
}
dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire);
dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V);
ac_pc = RB_read(PC);
}
//------------------------------------------------------
void arm_isa::ADD(int rd, int rn, bool s) {
arm_isa::reg_t RD2, RN2;
arm_isa::r64bit_t soma;
dprintf("Instruction: ADD\n");
RN2.entire = RB_read(rn);
if(rn == PC) RN2.entire += 4;
dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire);
soma.hilo = (uint64_t)(uint32_t)RN2.entire + (uint64_t)(uint32_t)dpi_shiftop.entire;
RD2.entire = soma.reg[0];
RB_write(rd, RD2.entire);
if ((s == 1)&&(rd == PC)) {
#ifndef FORGIVE_UNPREDICTABLE
if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE ||
arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) {
printf("Unpredictable ADD instruction result\n");
return;
}
SPSRtoCPSR();
#endif
} else {
if (s == 1) {
flags.N = getBit(RD2.entire,31);
flags.Z = ((RD2.entire == 0) ? true : false);
flags.C = ((soma.reg[1] != 0) ? true : false);
flags.V = (((getBit(RN2.entire,31) && getBit(dpi_shiftop.entire,31) && (!getBit(RD2.entire,31))) ||
((!getBit(RN2.entire,31)) && (!getBit(dpi_shiftop.entire,31)) && getBit(RD2.entire,31))) ? true : false);
}
}
dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire);
dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V);
ac_pc = RB_read(PC);
}
//------------------------------------------------------
void arm_isa::AND(int rd, int rn, bool s) {
arm_isa::reg_t RD2, RN2;
dprintf("Instruction: AND\n");
RN2.entire = RB_read(rn);
dprintf("Operands:\n A = 0x%lX\n B = 0x%lX\n", RN2.entire,dpi_shiftop.entire);
RD2.entire = RN2.entire & dpi_shiftop.entire;
RB_write(rd, RD2.entire);
if ((s == 1)&&(rd == PC)) {
#ifndef FORGIVE_UNPREDICTABLE
if (arm_proc_mode.mode == arm_isa::processor_mode::USER_MODE ||
arm_proc_mode.mode == arm_isa::processor_mode::SYSTEM_MODE) {
printf("Unpredictable AND instruction result\n");
return;
}
SPSRtoCPSR();
#endif
} else {
if (s == 1) {
flags.N = getBit(RD2.entire, 31);
flags.Z = ((RD2.entire == 0) ? true : false);
flags.C = dpi_shiftopcarry;
// nothing happens with flags.V
}
}
dprintf(" * R%d <= 0x%08X (%d)\n", rd, RD2.entire, RD2.entire);
dprintf(" * Flags <= N=0x%X, Z=0x%X, C=0x%X, V=0x%X\n", flags.N,flags.Z,flags.C,flags.V);
ac_pc = RB_read(PC);
}
//------------------------------------------------------
void arm_isa::B(int h, int offset) {
uint32_t mem_pos, s_extend;
// Note that PC is already incremented by 4, i.e., pointing to the next instruction
if(h == 1)
{ // h? it is really "l"
dprintf("Instruction: BL\n");
RB_write(LR, RB_read(PC));
dprintf("Branch return address: 0x%lX\n", RB_read(LR));
} else {
dprintf("Instruction: B\n");
}
s_extend = arm_isa::SignExtend((int32_t)(offset << 2), 26);
mem_pos = (uint32_t)RB_read(PC) + 4 + s_extend;
dprintf("Calculated branch destination: 0x%X\n", mem_pos);
RB_write(PC, mem_pos);
//fprintf(stderr, "0x%X\n", (unsigned int)mem_pos);
ac_pc = RB_read(PC);
}
//------------------------------------------------------
void arm_isa::BX(int rm) {
dprintf("Instruction: BX\n");
if(isBitSet(rm,0)) {
dprintf("Change to thumb not implemented in this model. PC=%X\n", ac_pc.read());
// return;
}