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pfe_hif.t2t
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== Host Interface (HIF) ==[pfe_hif]
Manage and monitor a buffer descriptor pool and signal Rx/Tx events to the
host using interrupt requests.
=== HIF registers ===[pfe_hif_regs]
|| HIF instance | Base offset in CBUS ||
| HIF | 0x280000 |
|| Symbol | Offset | Description ||
| [VERSION #pfe_hif_reg_version] | 0x000 | Version register (reads 0x10 on my hardware) |
| [TX_CTRL #pfe_hif_reg_tx_ctrl] | 0x004 | Tx control register |
| [TX_CURR_BD_ADDR #pfe_hif_reg_tx_curr_bd_addr] | 0x008 | Tx current buffer descriptor address |
| [TX_ALLOC #pfe_hif_reg_tx_alloc] | 0x00c | Tx allocation register? |
| [TX_BDP_ADDR #pfe_hif_reg_tx_bdp_addr] | 0x010 | Tx buffer descriptor pool address |
| [TX_STATUS #pfe_hif_reg_tx_status] | 0x014 | Tx status register |
| [RX_CTRL #pfe_hif_reg_rx_ctrl] | 0x020 | Rx status register |
| [RX_BDP_ADDR #pfe_hif_reg_rx_bdp_addr] | 0x024 | Rx buffer descriptor pool address |
| [RX_STATUS #pfe_hif_reg_rx_status] | 0x030 | Rx status |
| [INT_SRC #pfe_hif_reg_int_src] | 0x034 | Interrupt source status register |
| [INT_ENABLE #pfe_hif_reg_int_enable] | 0x038 | Interrupt enable register |
| [POLL_CTRL #pfe_hif_reg_poll_ctrl] | 0x03c | Polling control register |
| [RX_CURR_BD_ADDR #pfe_hif_reg_rx_curr_bd_addr] | 0x040 | Rx current buffer descriptor address |
| [RX_ALLOC #pfe_hif_reg_rx_alloc] | 0x044 | Rx allocation register? |
| [TX_DMA_STATUS #pfe_hif_reg_tx_dma_status] | 0x048 | Tx DMA status register |
| [RX_DMA_STATUS #pfe_hif_reg_rx_dma_status] | 0x04c | Rx DMA status register |
| [INT_COAL #pfe_hif_reg_int_coal] | 0x050 | Interrupt coalesce control register |
==== VERSION (HIF_BASE + 0x000) ====[pfe_hif_reg_version]
HIF silicon revision. 0x10 on my c2k chip.
|| Symbol | Bit range | R/W | Description ||
| VERSION | ?-0 | R | HIF silicon revision |
==== TX_CTRL (HIF_BASE + 0x004) ====[pfe_hif_reg_tx_ctrl]
|| Symbol | Bit range | R/W | Description ||
| BDP_CH_START_WSTB | 2 | RW | Enable buffer descriptor pool start write strobe? |
| BDP_POLL_CTRL_EN | 1 | RW | Enable polling the buffer descriptor pool? |
| DMA_EN | 0 | RW | Enable DMA operation |
==== TX_CURR_BD_ADDR (HIF_BASE + 0x008) ====[pfe_hif_reg_tx_curr_bd_addr]
|| Symbol | Bit range | R/W | Description ||
| CURR_BD_ADDR | 31-0 | R | Address of the current buffer descriptor |
==== TX_ALLOC (HIF_BASE + 0x00c) ====[pfe_hif_reg_tx_alloc]
Purpose unknown.
|| Symbol | Bit range | R/W | Description ||
| ? | 31-0 | W | ? |
==== TX_BDP_ADDR (HIF_BASE + 0x010) ====[pfe_hif_reg_tx_bdp_addr]
Get or set the address of the Tx buffer descriptor pool.
Writing a new value will reset the Tx current buffer descriptor.
|| Symbol | Bit range | R/W | Description ||
| BDP_ADDR | 31-0 | RW | Address of the buffer descriptor pool |
==== TX_STATUS (HIF_BASE + 0x014) ====[pfe_hif_reg_tx_status]
Contents unknown.
|| Symbol | Bit range | R/W | Description ||
| BDP_CSR_TX_DMA_ACTV | 16 | R | Tx BDP busy (only in HIF_NOCPY?) |
| CTRL | 15-0 | R | Bit 31-16 from last Tx buffer descriptor control word |
==== RX_CTRL (HIF_BASE + 0x020) ====[pfe_hif_reg_rx_ctrl]
|| Symbol | Bit range | R/W | Description ||
| BDP_CH_START_WSTB | 2 | RW | Enable buffer descriptor pool start write strobe? Self-clearing. Can be set to resume Rx in case of overrun. |
| BDP_POLL_CTRL_EN | 1 | RW | Enable polling the buffer descriptor pool? |
| DMA_EN | 0 | RW | Enable DMA operation |
==== RX_BDP_ADDR (HIF_BASE + 0x024) ====[pfe_hif_reg_rx_bdp_addr]
Get or set the address of the Rx buffer descriptor pool.
Writing a new value will reset the Rx current buffer descriptor.
|| Symbol | Bit range | R/W | Description ||
| BDP_ADDR | 31-0 | RW | Address of the buffer descriptor pool |
==== RX_STATUS (HIF_BASE + 0x030) ====[pfe_hif_reg_rx_status]
Contents unknown.
|| Symbol | Bit range | R/W | Description ||
| BDP_CSR_RX_DMA_ACTV | 16 | R | Rx BDP busy |
| CTRL | 15-0 | R | Bit 31-16 from last Rx buffer descriptor control word |
==== INT_SRC (HIF_BASE + 0x034) ====[pfe_hif_reg_int_src]
Interrupt source status register.
An interrupt can be acknowledged by writing a value with the corresponding
bit set.
|| Symbol | Bit range | R/W | Description ||
| TXPKT_INT | 4 | R | Tx packet ??? interrupt |
| TXBD_INT | 3 | R | Tx buffer descriptor ??? interrupt |
| RXPKT_INT | 2 | R | Rx packet ??? interrupt |
| RXBD_INT | 1 | R | Rx buffer descriptor ??? interrupt |
| INT | 0 | R | Global interrupt? |
==== INT_ENABLE (HIF_BASE + 0x038) ====[pfe_hif_reg_int_enable]
Interrupt source enable register.
|| Symbol | Bit range | R/W | Description ||
| TXPKT_INT | 4 | RW | Tx packet ??? interrupt enable |
| TXBD_INT | 3 | RW | Tx buffer descriptor ??? interrupt enable |
| RXPKT_INT | 2 | RW | Rx packet ??? interrupt enable |
| RXBD_INT | 1 | RW | Rx buffer descriptor ??? interrupt enable |
| INT | 0 | RW | Global interrupt enable? |
==== POLL_CTRL (HIF_BASE + 0x03c) ====[pfe_hif_reg_poll_ctrl]
Polling control register
|| Symbol | Bit range | R/W | Description ||
| 31-16 | RX_POLL_CTRL_CYCLE | RW | Number of pfe_sys clock cycles between Rx buffer descriptor pool poll attempts |
| 15-0 | TX_POLL_CTRL_CYCLE | RW | Number of pfe_sys clock cycles between Tx buffer descriptor pool poll attempts |
==== RX_CURR_BD_ADDR (HIF_BASE + 0x040) ====[pfe_hif_reg_rx_curr_bd_addr]
|| Symbol | Bit range | R/W | Description ||
| CURR_BD_ADDR | 31-0 | R | Address of the current buffer descriptor |
==== RX_ALLOC (HIF_BASE + 0x044) ====[pfe_hif_reg_rx_alloc]
Purpose unknown.
|| Symbol | Bit range | R/W | Description ||
| ? | 31-0 | W | ? |
==== TX_DMA_STATUS (HIF_BASE + 0x048) ====[pfe_hif_reg_tx_dma_status]
Contents unknown.
|| Symbol | Bit range | R/W | Description ||
==== RX_DMA_STATUS (HIF_BASE + 0x04c) ====[pfe_hif_reg_rx_dma_status]
Contents unknown.
|| Symbol | Bit range | R/W | Description ||
| BUF_LEN | 13-0 | R | Length of last buffer transferred (same as the BUF_LEN value from the buffer descriptor) |
==== INT_COAL (HIF_BASE + 0x050) ====[pfe_hif_reg_int_coal]
Interrupt coalesce control register
|| Symbol | Bit range | R/W | Description ||
| 31 | INT_COAL_ENABLE | RW | Enable interrupt coalesce |
| 30-0 | TX_POLL_CTRL_CYCLE | RW | Minimum number of pfe_sys clock cycles between interrupts |