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usbphy_serdes.t2t
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usbphy_serdes.t2t
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= USB PHY and SerDes =[peri_usbphy_serdes]
USB 2.0 PHY and SerDes configuration and status registers.
The status registers collect the status lines coming out of the USB 2.0 PHY
and the SerDes PHYs IP blocks.
The control registers can set inputs of those PHYs IP blocks.
== Registers ==
|| Base address | 0x90410000 ||
|| Symbol | Offset | Description ||
| [USB0_PHY_CTRL_REG0 #peri_usbphy_serdes_usb0_phy_ctrl_reg0] | 0x0000 | USB PHY control register (USB 2.0) |
| [SD0_PHY_STS #peri_usbphy_serdes_sdx_phy_sts] | 0x002c | SerDes 0 PHY status register |
| SD0_PHY_CTRL1 | 0x0030 | SerDes 0 PHY control register 1 |
| [SD0_PHY_CTRL2 #peri_usbphy_serdes_sdx_phy_ctrl2] | 0x0034 | SerDes 0 PHY control register 2 |
| [SD0_PHY_CTRL3 #peri_usbphy_serdes_sdx_phy_ctrl3] | 0x0038 | SerDes 0 PHY control register 3 |
| [SD1_PHY_STS #peri_usbphy_serdes_sdx_phy_sts] | 0x003c | SerDes 1 PHY status register |
| SD1_PHY_CTRL1 | 0x0040 | SerDes 1 PHY control register 1 |
| [SD1_PHY_CTRL2 #peri_usbphy_serdes_sdx_phy_ctrl2] | 0x0044 | SerDes 1 PHY control register 2 |
| [SD1_PHY_CTRL3 #peri_usbphy_serdes_sdx_phy_ctrl3] | 0x0048 | SerDes 1 PHY control register 3 |
| [SD2_PHY_STS #peri_usbphy_serdes_sdx_phy_sts] | 0x004c | SerDes 2 PHY status register |
| SD2_PHY_CTRL1 | 0x0050 | SerDes 2 PHY control register 1 |
| [SD2_PHY_CTRL2 #peri_usbphy_serdes_sdx_phy_ctrl2] | 0x0054 | SerDes 2 PHY control register 2 |
| [SD2_PHY_CTRL3 #peri_usbphy_serdes_sdx_phy_ctrl3] | 0x0058 | SerDes 2 PHY control register 3 |
==== USB0_PHY_CTRL_REG0 (0x90410000) ====[peri_usbphy_serdes_usb0_phy_ctrl_reg0]
Register controlling the USB 2.0 PHY (usb0).
|| Symbol | Bit range | R/W | Description ||
| usb0_common_disable? | 24 | RW | Disable common blocks? Saves power. 0 = enabled, 1 = powered down |
| usb0_refclksel | 21-20 | RW | Reference clock selsction. 2 = 2.5V clock on XO pin. 0, 1, 3 = ? |
| usb0_refclkdiv | 17-16 | RW | Reference clock frequency select. 0 = ?, 1 = 24 MHz, 2 = 48 MHz, 3 = ? |
| usb0_analog_disable? | 6 | RW | Disable analog blocks?. Saves power. 0 = enabled, 1 = powered down |
| usb0_otgdisable | 4 | RW | Disable OTG block. 0 = enabled, 1 = powered down |
| usb0_vbusvldext | 3 | RW | VBUS signal valid. 0 = no, pull-up on D+ disabled, 1 = ? |
| usb0_vbusvldextsel | 2 | RW | OTG Session Valid comparator selection. 0 = internal (default), 1 = external (use value from bit 3) |
==== SDx_PHY_STS (0x9041002c + (x * 0x10)) ====[peri_usbphy_serdes_sdx_phy_sts]
Register showing the value of SerDes(x) status output signals.
|| Symbol | Bit range | R/W | Description ||
| cmu_ok_o | 14 | R | CMU is ready |
| lane_ok_o | 12 | R | All lanes are ready |
==== SDx_PHY_CTRL2 (0x90410034 + (x * 0x10)) ====[peri_usbphy_serdes_sdx_phy_ctrl2]
Configuration register 2 for SerDes(x) PHY.
|| Symbol | Bit range | R/W | Description ||
| cmu_rst | 16 | RW | CMU reset. 0=reset 1=normal operation |
| cmu_pd | 7 | RW | 0=CMU power up 1=CMU power down |
| lane_rst | 6 | RW | Lane reset. 0=reset 1=normal operation |
| ? | 3-2 | RW | 0=nominal 3=low power mode |
| ? | 1-0 | RW | Clock divider selection? 0=value from CTRL3? 1-3=??? |
==== SDx_PHY_CTRL3 (0x90410038 + (x * 0x10)) ====[peri_usbphy_serdes_sdx_phy_ctrl3]
Configuration register 3 for SerDes(x) PHY.
|| Symbol | Bit range | R/W | Description ||
| ck_soc_div_i | 15-0 | RW | Clock divider? Reset value: 0x33f Value set by driver: 0xff3c |