diff --git a/IceStick_Accelerometer/README.md b/IceStick_Accelerometer/README.md
new file mode 100644
index 0000000..b608a69
--- /dev/null
+++ b/IceStick_Accelerometer/README.md
@@ -0,0 +1,5 @@
+# IceStick-Accelerometer
+
+Loads SPI controller onto IceStick and reads accelerometer data. Leds will turn on/off according to orientation.
+
+Using open source toolchain, (Yosys, arachne-pnr, and IceStorm) load verilog files onto Icestick, and connect accelerometer. The leds on the IceStick should turn on/off to indicate the direction of tilt with respect to gravity.
\ No newline at end of file
diff --git a/IceStick_Accelerometer/src/PmodACL_Demo_pcf_sbt.pcf b/IceStick_Accelerometer/src/PmodACL_Demo_pcf_sbt.pcf
new file mode 100644
index 0000000..ded12b9
--- /dev/null
+++ b/IceStick_Accelerometer/src/PmodACL_Demo_pcf_sbt.pcf
@@ -0,0 +1,28 @@
+# ##############################################################################
+
+# iCEcube PCF
+
+# Version:            2012.09SP1.22498
+
+# File Generated:     Jun 13 2013 14:14:52
+
+# Family & Device:    iCE40HX1K
+
+# Package:            TQ144
+
+# ##############################################################################
+
+###IOSet List 12
+set_io clk_in 21
+set_io LED 95
+set_io LED_MINUS[0] 99
+set_io LED_PLUS[1] 96
+set_io SCLK 81 -pullup yes
+set_io SDI 80 -pullup yes
+set_io SDO 79 -pullup yes
+set_io test2 45
+set_io LED_MINUS[1] 98
+set_io LED_PLUS[0] 97
+set_io SS 78 -pullup yes
+set_io test1 47
+
diff --git a/IceStick_Accelerometer/src/clkdiv_5hz.v b/IceStick_Accelerometer/src/clkdiv_5hz.v
new file mode 100644
index 0000000..9e867a3
--- /dev/null
+++ b/IceStick_Accelerometer/src/clkdiv_5hz.v
@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    ClkDiv_5Hz
+// Project Name: 	 PmodACL_Demo
+
+// ====================================================================================
+// 										  Define Module
+// ====================================================================================
+module ClkDiv_5Hz(
+		CLK,
+		RST,
+		CLKOUT
+);
+
+// ====================================================================================
+// 										Port Declarations
+// ====================================================================================
+   input            CLK;		// 100MHz onboard clock
+   input            RST;		// Reset
+   output           CLKOUT;	// New clock output
+   
+   
+// ====================================================================================
+// 							   Parameters, Registers, and Wires
+// ====================================================================================
+   reg CLKOUT;
+	
+   // Current count value
+   reg [23:0]       clkCount = 24'h000000;
+   // Value to toggle output clock at
+   parameter [23:0] cntEndVal = 24'h989680;
+   
+//  ===================================================================================
+// 							  				Implementation
+//  ===================================================================================
+   
+		//------------------------------------------------
+		//	5Hz Clock Divider Generates Send/Receive signal
+		//------------------------------------------------
+		always @(posedge CLK or posedge RST)
+			
+			// Reset clock
+			if (RST == 1'b1) begin
+					CLKOUT <= 1'b0;
+					clkCount <= 24'h000000;
+			end
+			else begin
+					if (clkCount == cntEndVal) begin
+						CLKOUT <= (~CLKOUT);
+						clkCount <= 24'h000000;
+					end
+					else begin
+						clkCount <= clkCount + 1'b1;
+					end
+			end
+   
+endmodule
diff --git a/IceStick_Accelerometer/src/ice_pll.v b/IceStick_Accelerometer/src/ice_pll.v
new file mode 100644
index 0000000..1a25bbe
--- /dev/null
+++ b/IceStick_Accelerometer/src/ice_pll.v
@@ -0,0 +1,38 @@
+module ice_pll(REFERENCECLK,
+               PLLOUTCORE,
+               PLLOUTGLOBAL,
+               RESET);
+
+input REFERENCECLK;
+input RESET;    /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ 
+output PLLOUTCORE;
+output PLLOUTGLOBAL;
+
+SB_PLL40_CORE ice_pll_inst(.REFERENCECLK(REFERENCECLK),
+                           .PLLOUTCORE(PLLOUTCORE),
+                           .PLLOUTGLOBAL(PLLOUTGLOBAL),
+                           .EXTFEEDBACK(),
+                           .DYNAMICDELAY(),
+                           .RESETB(RESET),
+                           .BYPASS(1'b0),
+                           .LATCHINPUTVALUE(),
+                           .LOCK(),
+                           .SDI(),
+                           .SDO(),
+                           .SCLK());
+
+//\\ Fin=12, Fout=88;
+defparam ice_pll_inst.DIVR = 4'b0000;
+defparam ice_pll_inst.DIVF = 7'b0111010;
+defparam ice_pll_inst.DIVQ = 3'b011;
+defparam ice_pll_inst.FILTER_RANGE = 3'b001;
+defparam ice_pll_inst.FEEDBACK_PATH = "SIMPLE";
+defparam ice_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
+defparam ice_pll_inst.FDA_FEEDBACK = 4'b0000;
+defparam ice_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
+defparam ice_pll_inst.FDA_RELATIVE = 4'b0000;
+defparam ice_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
+defparam ice_pll_inst.PLLOUT_SELECT = "GENCLK";
+defparam ice_pll_inst.ENABLE_ICEGATE = 1'b0;
+
+endmodule
diff --git a/IceStick_Accelerometer/src/ice_pll_inst.v b/IceStick_Accelerometer/src/ice_pll_inst.v
new file mode 100644
index 0000000..e761cf9
--- /dev/null
+++ b/IceStick_Accelerometer/src/ice_pll_inst.v
@@ -0,0 +1,4 @@
+ice_pll ice_pll_inst(.REFERENCECLK(),
+                     .PLLOUTCORE(),
+                     .PLLOUTGLOBAL(),
+                     .RESET());
diff --git a/IceStick_Accelerometer/src/pmodacl.bin b/IceStick_Accelerometer/src/pmodacl.bin
new file mode 100644
index 0000000..30d5b6c
Binary files /dev/null and b/IceStick_Accelerometer/src/pmodacl.bin differ
diff --git a/IceStick_Accelerometer/src/pmodacl.blif b/IceStick_Accelerometer/src/pmodacl.blif
new file mode 100644
index 0000000..fb1b000
--- /dev/null
+++ b/IceStick_Accelerometer/src/pmodacl.blif
@@ -0,0 +1,2895 @@
+# Generated by Yosys 0.9+932 (git sha1 9e5ff30d, clang 6.0.0-1ubuntu2 -fPIC -Os)
+
+.model PmodACL_Demo
+.inputs clk_in SDI
+.outputs SDO SCLK SS test1 test2 LED_PLUS[0] LED_PLUS[1] LED_MINUS[0] LED_MINUS[1] LED
+.names $false
+.names $true
+1
+.names $undef
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.z_axis_data[9] I3=LED_MINUS_SB_LUT4_O_I3 O=LED_MINUS[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.x_axis_data[9] I3=LED_MINUS_SB_LUT4_O_1_I3 O=LED_MINUS[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4] CO=LED_MINUS_SB_LUT4_O_1_I3 I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1 I3=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3] CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4] I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2] CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3] I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2] I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI CO=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] I0=$false I1=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.x_axis_data[5] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2 I3=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.x_axis_data[6] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2 I3=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:125|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.x_axis_data[7] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.x_axis_data[8] O=LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4] CO=LED_MINUS_SB_LUT4_O_I3 I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1 I3=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3] CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4] I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2] CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3] I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2] I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI CO=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] I0=$false I1=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.z_axis_data[5] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2 I3=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.z_axis_data[6] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2 I3=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:131|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111000000001111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.z_axis_data[7] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.z_axis_data[8] O=LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.z_axis_data[9] I3=LED_PLUS_SB_LUT4_O_I3 O=LED_PLUS[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.x_axis_data[9] I3=LED_PLUS_SB_LUT4_O_1_I3 O=LED_PLUS[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111111110000
+.gate SB_LUT4 I0=SPI.C0.x_axis_data[5] I1=SPI.C0.x_axis_data[8] I2=SPI.C0.x_axis_data[7] I3=SPI.C0.x_axis_data[6] O=LED_PLUS_SB_LUT4_O_1_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=SPI.C0.z_axis_data[8] I1=SPI.C0.z_axis_data[7] I2=SPI.C0.z_axis_data[6] I3=SPI.C0.z_axis_data[5] O=LED_PLUS_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=LED_MINUS[1] I1=LED_MINUS[0] I2=LED_PLUS[1] I3=LED_PLUS[0] O=LED
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q O=SCLK
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=SDI I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[0] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SDI_SB_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.CONFIGUREsel_SB_DFF_Q_D Q=SPI.C0.CONFIGUREsel[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.CONFIGUREsel_SB_DFF_Q_1_D Q=SPI.C0.CONFIGUREsel[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.CONFIGUREsel[1] I2=SPI.C0.CONFIGUREsel[2] I3=SPI.C0.STATE[4] O=SPI.C0.CONFIGUREsel_SB_DFF_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010100010001000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.CONFIGUREsel_SB_DFF_Q_2_D Q=SPI.C0.CONFIGUREsel[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=$false I1=count[19] I2=SPI.C0.CONFIGUREsel[0] I3=SPI.C0.STATE[4] O=SPI.C0.CONFIGUREsel_SB_DFF_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001111110011
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE[4] I2=SPI.C0.CONFIGUREsel[0] I3=SPI.C0.CONFIGUREsel[2] O=SPI.C0.CONFIGUREsel_SB_DFF_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.DATA_SB_DFF_Q_D Q=SPI.C0.DATA[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.DATA_SB_DFF_Q_1_D Q=SPI.C0.DATA[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1 I2=SPI.C0.DATA[2] I3=SPI.C0.DATA[1] O=SPI.C0.DATA_SB_DFF_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.DATA_SB_DFF_Q_2_D Q=SPI.C0.DATA[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1 I2=SPI.C0.DATA[1] I3=SPI.C0.DATA[0] O=SPI.C0.DATA_SB_DFF_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111011111010101
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1 I2=SPI.C0.DATA[0] I3=SPI.C0.DATA[2] O=SPI.C0.DATA_SB_DFF_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.STATE[6] I3=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3 O=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.register_select I3=SPI.C1.done O=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_D Q=SPI.C0.STATE[6]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_1_D Q=SPI.C0.STATE[5]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.STATE_SB_DFF_Q_1_D_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=SPI.C0.STATE[5] I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I2=SPI.C0.STATE[1] I3=SPI.C1.done O=SPI.C0.STATE_SB_DFF_Q_1_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000110111011101
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_2_D Q=SPI.C0.STATE[4]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0 I1=count[19] I2=SPI.C0.done_configure I3=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I2=count[19] I3=SPI.C0.CONFIGUREsel[0] O=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[4] I2=SPI.C0.CONFIGUREsel[1] I3=SPI.C0.CONFIGUREsel[2] O=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000001100
+.gate SB_LUT4 I0=SPI.C0.STATE[0] I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O I2=SPI.C0.STATE[5] I3=SPI.C0.sample_done O=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101010100010101
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_3_D Q=SPI.C0.STATE[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=genStart.CLKOUT I1=count[19] I2=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2 I3=SPI.C0.STATE_SB_DFF_Q_3_D_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100010000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.sample_done I2=SPI.C0.STATE[5] I3=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O O=SPI.C0.STATE_SB_DFF_Q_3_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_4_D Q=SPI.C0.STATE[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1 I2=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O O=SPI.C0.STATE_SB_DFF_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001000100010
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0 I1=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 I3=SPI.C0.STATE[3] O=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0010101010101010
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I0 I1=SPI.C0.done_configure_SB_LUT4_I3_1_O I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 O=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001010101010101
+.gate SB_LUT4 I0=SPI.C0.STATE[2] I1=SPI.C0.DATA[2] I2=SPI.C0.DATA[1] I3=SPI.C0.DATA[0] O=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_LUT4 I0=$false I1=SPI.C0.done_configure I2=SPI.C0.STATE[5] I3=SPI.C0.sample_done O=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_5_D Q=SPI.C0.STATE[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0 I1=SPI.C0.STATE[1] I2=count[19] I3=SPI.C1.done O=SPI.C0.STATE_SB_DFF_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101010111010101
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I2=SPI.C0.STATE[4] I3=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0111011101010111
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C1.done I3=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0 O=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.CONFIGUREsel[0] I2=SPI.C0.CONFIGUREsel[1] I3=SPI.C0.CONFIGUREsel[2] O=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000000011
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.STATE_SB_DFF_Q_6_D Q=SPI.C0.STATE[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1 I2=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2 I3=genStart.CLKOUT O=SPI.C0.STATE_SB_DFF_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001111110011
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O I3=SPI.C0.STATE[5] O=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001000100010
+.gate SB_LUT4 I0=$false I1=SPI.C0.done_configure_SB_LUT4_I3_1_O I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000110011001100
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[3] I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000110011001100
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0 I1=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I1 I2=SPI.C0.STATE[6] I3=count[19] O=SPI.C0.STATE_SB_DFF_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1011000100010001
+.gate SB_LUT4 I0=$false I1=SPI.C0.DATA[2] I2=SPI.C0.DATA[1] I3=SPI.C0.DATA[0] O=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000000011
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE[2] I2=SPI.C0.STATE[6] I3=SPI.C1.done O=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0111011101010111
+.gate SB_CARRY CI=SPI.C0.break_count[0] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=SPI.C0.break_count[1]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[10] I0=$false I1=SPI.C0.break_count[9]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] I0=$false I1=SPI.C0.break_count[8]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] I0=$false I1=SPI.C0.break_count[7]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] I0=$false I1=SPI.C0.break_count[6]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] I0=$false I1=SPI.C0.break_count[5]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] I0=$false I1=SPI.C0.break_count[4]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] I0=$false I1=SPI.C0.break_count[3]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] I0=$false I1=SPI.C0.break_count[2]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[10] CO=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[11] I0=$false I1=SPI.C0.break_count[10]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[11] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_1_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[10] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_10_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[1] I3=SPI.C0.break_count[0] O=SPI.C0.break_count_SB_DFFESR_Q_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_11_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C0.break_count[0] O=SPI.C0.break_count_SB_DFFESR_Q_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[10] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[10] O=SPI.C0.break_count_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_2_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[9] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[9] O=SPI.C0.break_count_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_3_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[8] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[8] O=SPI.C0.break_count_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_4_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[7] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[7] O=SPI.C0.break_count_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_5_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[6] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[6] O=SPI.C0.break_count_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_6_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[5] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[5] O=SPI.C0.break_count_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_7_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[4] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[4] O=SPI.C0.break_count_SB_DFFESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_8_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[3] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] O=SPI.C0.break_count_SB_DFFESR_Q_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.break_count_SB_DFFESR_Q_9_D E=SPI.C0.break_count_SB_DFFESR_Q_E Q=SPI.C0.break_count[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I1=$false I2=SPI.C0.break_count[2] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] O=SPI.C0.break_count_SB_DFFESR_Q_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_LUT4 I0=$false I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O I2=SPI.C0.break_count[11] I3=SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[11] O=SPI.C0.break_count_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:391|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001100110000
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.STATE[5] O=SPI.C0.break_count_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_DFFE C=SPI.C0.clk D=count[19] E=SPI.C0.done_configure_SB_DFFE_Q_E Q=SPI.C0.done_configure
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.STATE[0] I3=SPI.C0.done_configure O=SPI.C0.finish_SB_LUT4_I0_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.STATE[0] I3=SPI.C0.done_configure O=SPI.C0.done_configure_SB_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFE C=SPI.C0.clk D=count[19] E=SPI.C0.end_configure_SB_DFFE_Q_E Q=SPI.C0.end_configure
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2 O=SPI.C0.end_configure_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE[1] I2=SPI.C1.done I3=SPI.C0.end_configure O=SPI.C0.done_configure_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1101010101010101
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.finish_SB_DFFESR_Q_D E=SPI.C0.finish_SB_DFFESR_Q_E Q=SPI.C0.finish R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.finish_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111111110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.CONFIGUREsel[1] I3=SPI.C0.STATE[4] O=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=count[19] I2=SPI.C0.STATE[0] I3=SPI.C0.STATE[4] O=SPI.C0.finish_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111111111110011
+.gate SB_LUT4 I0=SPI.C0.finish I1=SPI.C0.STATE[4] I2=SPI.C0.finish_SB_LUT4_I0_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3 O=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[0] I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 O=SPI.C0.finish_SB_LUT4_I0_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000110011001100
+.gate SB_LUT4 I0=$false I1=genStart.CLKOUT I2=SPI.C0.sample_done I3=SPI.C0.finish O=SPI.C0.finish_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001100110000
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0 I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2 I3=SPI.C0.finish_SB_LUT4_I3_O O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I0 I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2 I3=SPI.C0.finish_SB_LUT4_I3_O O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000010000000
+.gate SB_LUT4 I0=SPI.C0.break_count[6] I1=SPI.C0.break_count[5] I2=SPI.C0.break_count[3] I3=SPI.C0.break_count[0] O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.break_count[7] I1=SPI.C0.break_count[4] I2=SPI.C0.break_count[2] I3=SPI.C0.break_count[1] O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I1 I3=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2 O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=SPI.C0.break_count[3] I1=SPI.C0.break_count[2] I2=SPI.C0.break_count[1] I3=SPI.C0.break_count[0] O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.break_count[7] I1=SPI.C0.break_count[6] I2=SPI.C0.break_count[5] I3=SPI.C0.break_count[4] O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.break_count[11] I1=SPI.C0.break_count[10] I2=SPI.C0.break_count[9] I3=SPI.C0.break_count[8] O=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_CARRY CI=SPI.C0.hold_count[0] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] I0=$false I1=SPI.C0.hold_count[1]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[9] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[10] I0=$false I1=SPI.C0.hold_count[9]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[9] I0=$false I1=SPI.C0.hold_count[8]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[17] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[18] I0=$false I1=SPI.C0.hold_count[17]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[17] I0=$false I1=SPI.C0.hold_count[16]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[15] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16] I0=$false I1=SPI.C0.hold_count[15]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[14] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[15] I0=$false I1=SPI.C0.hold_count[14]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[13] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[14] I0=$false I1=SPI.C0.hold_count[13]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[12] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[13] I0=$false I1=SPI.C0.hold_count[12]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[11] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[12] I0=$false I1=SPI.C0.hold_count[11]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[10] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[11] I0=$false I1=SPI.C0.hold_count[10]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[7] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8] I0=$false I1=SPI.C0.hold_count[7]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[6] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[7] I0=$false I1=SPI.C0.hold_count[6]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[5] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[6] I0=$false I1=SPI.C0.hold_count[5]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[4] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[5] I0=$false I1=SPI.C0.hold_count[4]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[4] I0=$false I1=SPI.C0.hold_count[3]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] I0=$false I1=SPI.C0.hold_count[2]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[19] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[20] I0=$false I1=SPI.C0.hold_count[19]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[18] CO=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[19] I0=$false I1=SPI.C0.hold_count[18]
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[20] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_1_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[19] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_10_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[10] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_10_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[10] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[10] O=SPI.C0.hold_count_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_11_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_11_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[9] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[9] O=SPI.C0.hold_count_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_12_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_12_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[8] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8] O=SPI.C0.hold_count_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_13_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_13_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[7] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[7] O=SPI.C0.hold_count_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_14_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_14_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[6] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[6] O=SPI.C0.hold_count_SB_DFFESR_Q_14_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_15_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_15_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[5] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[5] O=SPI.C0.hold_count_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_16_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_16_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[4] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[4] O=SPI.C0.hold_count_SB_DFFESR_Q_16_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_17_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_17_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[3] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3] O=SPI.C0.hold_count_SB_DFFESR_Q_17_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_18_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_18_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[2] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2] O=SPI.C0.hold_count_SB_DFFESR_Q_18_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_19_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_19_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[1] I3=SPI.C0.hold_count[0] O=SPI.C0.hold_count_SB_DFFESR_Q_19_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[19] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[19] O=SPI.C0.hold_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_2_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[18] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_20_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=genStart.CLKOUT I3=SPI.C0.hold_count[0] O=SPI.C0.hold_count_SB_DFFESR_Q_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[18] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[18] O=SPI.C0.hold_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_3_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[17] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[17] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[17] O=SPI.C0.hold_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_4_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[16] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[16] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16] O=SPI.C0.hold_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_5_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[15] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[15] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[15] O=SPI.C0.hold_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_6_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[14] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[14] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[14] O=SPI.C0.hold_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_7_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[13] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[13] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[13] O=SPI.C0.hold_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_8_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[12] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_8_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[12] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[12] O=SPI.C0.hold_count_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.hold_count_SB_DFFESR_Q_9_D E=SPI.C0.hold_count_SB_DFFESR_Q_E Q=SPI.C0.hold_count[11] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_9_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[11] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[11] O=SPI.C0.hold_count_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=genStart.CLKOUT I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100010001000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.hold_count[20] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[20] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:405|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=SPI.C0.hold_count[1] I2=SPI.C0.hold_count[0] I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=SPI.C0.hold_count[5] I1=SPI.C0.hold_count[4] I2=SPI.C0.hold_count[3] I3=SPI.C0.hold_count[2] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3 O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.hold_count[17] I1=SPI.C0.hold_count[16] I2=SPI.C0.hold_count[15] I3=SPI.C0.hold_count[14] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.hold_count[20] I2=SPI.C0.hold_count[19] I3=SPI.C0.hold_count[18] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=SPI.C0.hold_count[9] I1=SPI.C0.hold_count[8] I2=SPI.C0.hold_count[7] I3=SPI.C0.hold_count[6] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C0.hold_count[13] I1=SPI.C0.hold_count[12] I2=SPI.C0.hold_count[11] I3=SPI.C0.hold_count[10] O=SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.STATE[3] O=SPI.C0.hold_count_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.prevstart[2] Q=SPI.C0.prevstart[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.prevstart[1] Q=SPI.C0.prevstart[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=SPI.C0.prevstart[0] Q=SPI.C0.prevstart[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_DFF C=SPI.C0.clk D=genStart.CLKOUT Q=SPI.C0.prevstart[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:2"
+.gate SB_LUT4 I0=$false I1=SPI.C0.prevstart[1] I2=SPI.C0.prevstart[0] I3=genStart.CLKOUT O=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.prevstart[3] I3=SPI.C0.prevstart[2] O=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000000001111
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.register_select_SB_DFFESR_Q_D E=SPI.C0.register_select_SB_DFFESR_Q_E Q=SPI.C0.register_select R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.register_select I3=SPI.C1.done O=SPI.C0.register_select_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000111111110000
+.gate SB_LUT4 I0=$false I1=count[19] I2=SPI.C0.STATE[6] I3=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0 O=SPI.C0.register_select_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001111110011
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.sample_done_SB_DFFESR_Q_D E=SPI.C0.sample_done_SB_DFFESR_Q_E Q=SPI.C0.sample_done R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C0.sample_done I2=SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2 O=SPI.C0.sample_done_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1110111010101110
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.DATA[1] I3=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1 O=SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C0.finish_SB_LUT4_I0_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3 O=SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000000011
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[0] I2=SPI.C0.STATE[6] I3=SPI.C0.hold_count_SB_DFFESR_Q_E O=SPI.C0.sample_done_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111111111111100
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.transmit_SB_DFFESR_Q_D E=SPI.C0.transmit_SB_DFFESR_Q_E Q=SPI.C0.transmit R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C0.STATE[2] I2=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0 I3=SPI.C0.transmit O=SPI.C0.transmit_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1101110101011101
+.gate SB_LUT4 I0=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0 I1=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O I3=SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2 O=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001000100010
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I0_I2 I1=SPI.C0.STATE[4] I2=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3 I3=SPI.C0.transmit O=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001000101010001
+.gate SB_LUT4 I0=SPI.C0.transmit I1=SPI.C0.STATE[0] I2=SPI.C0.STATE[5] I3=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I3 O=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C0.STATE[6] I1=SPI.C0.DATA[2] I2=SPI.C0.DATA[1] I3=SPI.C0.DATA[0] O=SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[2] I2=SPI.C0.STATE[1] I3=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O O=SPI.C0.transmit_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111111111111100
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[15] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_1_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[14] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_10_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[5] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_11_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[4] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_12_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[3] I2=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O I3=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101110111011101
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_13_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[2] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_14_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[1] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_15_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[0] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[14] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_2_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[13] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I0 I1=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2 I2=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2 I3=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0111011101111111
+.gate SB_LUT4 I0=SPI.C0.STATE[0] I1=SPI.C0.done_configure I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101110111011101
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2 O=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000111111111111
+.gate SB_LUT4 I0=SPI.C0.STATE[0] I1=SPI.C0.STATE[5] I2=SPI.C0.STATE[6] I3=SPI.C0.STATE[4] O=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=SPI.C0.txdata[13] I1=SPI.C0.STATE[4] I2=SPI.C0.CONFIGUREsel[1] I3=SPI.C0.CONFIGUREsel[2] O=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001000100010101
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_3_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[12] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2 I2=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I2 I3=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111111100111111
+.gate SB_LUT4 I0=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2 I1=SPI.C0.txdata[12] I2=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 I3=SPI.C0.STATE[5] O=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001000101010001
+.gate SB_LUT4 I0=$false I1=SPI.C0.done_configure_SB_LUT4_I3_1_O I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 O=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_4_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[11] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[11] I2=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O I3=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101110111011101
+.gate SB_LUT4 I0=$false I1=SPI.C0.finish_SB_LUT4_I0_I2 I2=SPI.C0.STATE[4] I3=SPI.C0.CONFIGUREsel[2] O=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000001100110011
+.gate SB_LUT4 I0=$false I1=SPI.C0.finish_SB_LUT4_I0_I3 I2=SPI.C0.STATE[4] I3=SPI.C0.CONFIGUREsel[1] O=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001100000011
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_5_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[10] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[10] I2=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O O=SPI.C0.txdata_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101110111011101
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0 I1=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I2=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I2 I3=SPI.C0.DATA[2] O=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100010101000
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C0.txdata[10] I3=SPI.C1.done O=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001100111111
+.gate SB_LUT4 I0=SPI.C1.done I1=SPI.C0.register_select I2=SPI.C0.DATA[1] I3=SPI.C0.DATA[0] O=SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001010001111
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_6_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0 I1=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1 I2=SPI.C0.txdata[9] I3=SPI.C1.done O=SPI.C0.txdata_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1101110111010101
+.gate SB_LUT4 I0=SPI.C0.txdata[9] I1=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I2=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O O=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0010000100110001
+.gate SB_LUT4 I0=SPI.C0.txdata[9] I1=SPI.C0.STATE[5] I2=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I3=SPI.C0.done_configure_SB_LUT4_I3_1_O O=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0100010001000110
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I2 I3=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000110011001100
+.gate SB_LUT4 I0=SPI.C0.DATA[1] I1=SPI.C0.txdata[9] I2=SPI.C0.DATA[2] I3=SPI.C0.DATA[0] O=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101010101010001
+.gate SB_LUT4 I0=SPI.C1.done I1=SPI.C0.register_select I2=SPI.C0.DATA[0] I3=SPI.C0.DATA[2] O=SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001010001111
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_7_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[8] I2=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101110111011101
+.gate SB_LUT4 I0=SPI.C0.finish_SB_LUT4_I0_I2 I1=SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2 I2=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I3=SPI.C0.register_select O=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001000100000001
+.gate SB_LUT4 I0=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 I1=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O I3=SPI.C0.STATE[5] O=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0010000000100010
+.gate SB_LUT4 I0=$false I1=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O I3=SPI.C0.STATE[5] O=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011000000110011
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0 I3=SPI.C1.done O=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100000011001100
+.gate SB_LUT4 I0=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I1=SPI.C0.done_configure_SB_LUT4_I3_1_O I2=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2 I3=SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101000100010001
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_8_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[7] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C0.txdata_SB_DFFESR_Q_9_D E=SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O Q=SPI.C0.txdata[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata[6] I3=SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O O=SPI.C0.txdata_SB_DFFESR_Q_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C0.txdata_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I2=SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O I3=SPI.C0.STATE[5] O=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000001100110011
+.gate SB_LUT4 I0=SPI.C0.txdata[15] I1=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 I3=SPI.C0.STATE[5] O=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1011101000110010
+.gate SB_LUT4 I0=$false I1=SPI.C0.STATE[6] I2=SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1 I3=SPI.C0.done_configure_SB_LUT4_I3_1_O O=SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000000011
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[1] E=SPI.C0.x_axis_data_SB_DFFESR_Q_E Q=SPI.C0.x_axis_data[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[0] E=SPI.C0.x_axis_data_SB_DFFESR_Q_E Q=SPI.C0.x_axis_data[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[7] E=SPI.C0.x_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.x_axis_data[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[6] E=SPI.C0.x_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.x_axis_data[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[5] E=SPI.C0.x_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.x_axis_data[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE[6] I2=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2 I3=SPI.C0.DATA[0] O=SPI.C0.x_axis_data_SB_DFFESR_Q_4_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1101010101010101
+.gate SB_LUT4 I0=$false I1=count[19] I2=SPI.C0.DATA[0] I3=SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1 O=SPI.C0.x_axis_data_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111001100110011
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[1] E=SPI.C0.z_axis_data_SB_DFFESR_Q_E Q=SPI.C0.z_axis_data[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[0] E=SPI.C0.z_axis_data_SB_DFFESR_Q_E Q=SPI.C0.z_axis_data[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[7] E=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.z_axis_data[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[6] E=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.z_axis_data[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register[5] E=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E Q=SPI.C0.z_axis_data[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:88|spimaster.v:132|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=count[19] I1=SPI.C0.STATE[6] I2=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2 I3=SPI.C0.DATA[1] O=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1101010101010101
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.done I3=SPI.C0.register_select O=SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0 O=SPI.C0.z_axis_data_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_DFFESR C=SPI.C0.clk D=$false E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.RxSTATE[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.RxSTATE[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.RxSTATE[0] I1=SPI.C1.RxSTATE[1] I2=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2 I3=SPI.C0.transmit O=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001001100000010
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 O=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=SPI.C1.RxSTATE[0] I1=SPI.C1.RxSTATE[1] I2=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 I3=SPI.C0.transmit O=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1111110111101100
+.gate SB_LUT4 I0=$false I1=SPI.C1.RxSTATE[0] I2=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3 I3=SPI.C1.RxSTATE[1] O=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.sdo_SB_LUT4_I2_I1 I3=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q O=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.RxSTATE[1] I3=count[19] O=SPI.C1.done_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000111111111111
+.gate SB_DFFESR C=SPI.C0.clk D=$false E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.SCLKSTATE[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.SCLKSTATE_SB_DFFESR_Q_1_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.SCLKSTATE[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.SCLKSTATE[0] I1=SPI.C1.SCLKSTATE[1] I2=SPI.C1.done I3=SPI.C0.transmit O=SPI.C1.SCLKSTATE_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001001100000010
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.SCLKSTATE[1] I3=count[19] O=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000111111111111
+.gate SB_DFFESR C=SPI.C0.clk D=$false E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.TxSTATE[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.TxSTATE_SB_DFFESR_Q_1_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.TxSTATE[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.TxSTATE[0] I1=SPI.C1.TxSTATE[1] I2=SPI.C1.TxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2 I3=SPI.C0.transmit O=SPI.C1.TxSTATE_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001001100000010
+.gate SB_LUT4 I0=$false I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I3=SPI.C1.sdo_SB_LUT4_I2_I1 O=SPI.C1.TxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_1_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I1=$false I2=SPI.C1.clk_count[6] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[6] O=SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000101010100000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[6] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_2_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I1=$false I2=SPI.C1.clk_count[5] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[5] O=SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000101010100000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[5] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_3_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I1=$false I2=SPI.C1.clk_count[4] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[4] O=SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000101010100000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[4] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_4_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I1=$false I2=SPI.C1.clk_count[3] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[3] O=SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000101010100000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[3] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_5_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I1=$false I2=SPI.C1.clk_count[2] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[2] O=SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000101010100000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[2] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_6_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I2=SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O O=SPI.C1.clk_count_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100110000001100
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2_SB_LUT4_O_I0 I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I2=SPI.C1.done I3=SPI.C1.clk_count[1] O=SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000011101110111
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[1] I3=SPI.C1.clk_count[0] O=SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.clk_count_SB_DFFESR_Q_7_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_count[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I3=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=SPI.C1.done I1=SPI.C1.clk_count[0] I2=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=SPI.C1.clk_edge_buffer O=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110011000000110
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=SPI.C1.clk_edge_buffer O=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2 I3=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1 O=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C1.clk_count_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101000
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.SCLKSTATE[0] I3=SPI.C1.SCLKSTATE[1] O=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=$false I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I2=SPI.C1.clk_count[7] I3=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[7] O=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000110011000000
+.gate SB_CARRY CI=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[6] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[7] I0=$false I1=SPI.C1.clk_count[6]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[5] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[6] I0=$false I1=SPI.C1.clk_count[5]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[4] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[5] I0=$false I1=SPI.C1.clk_count[4]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[3] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[4] I0=$false I1=SPI.C1.clk_count[3]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[2] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[3] I0=$false I1=SPI.C1.clk_count[2]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.clk_count[0] CO=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[2] I0=$false I1=SPI.C1.clk_count[1]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:247|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.clk_count[7] I3=SPI.C1.done O=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_DFFE C=SPI.C0.clk D=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D E=SPI.C1.clk_edge_buffer_SB_DFFE_Q_E Q=SPI.C1.clk_edge_buffer
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2 I3=SPI.C1.clk_edge_buffer O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1100110011000000
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2 I3=SPI.C1.clk_edge_buffer O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000001010100010
+.gate SB_LUT4 I0=count[19] I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O I2=SPI.C1.SCLKSTATE[1] I3=SPI.C1.SCLKSTATE[0] O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0010001000100000
+.gate SB_DFFE C=SPI.C0.clk D=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1 I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2 I3=SPI.C1.done O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000011000000
+.gate SB_LUT4 I0=$false I1=SPI.C1.done I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1 I3=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2 O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000001100110011
+.gate SB_LUT4 I0=SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I3=SPI.C1.sdo_SB_LUT4_I2_I1 O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I1_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000100000101010
+.gate SB_LUT4 I0=count[19] I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I1_O I2=SPI.C1.SCLKSTATE[1] I3=SPI.C1.SCLKSTATE[0] O=SPI.C1.sdo_SB_LUT4_I2_I1_SB_DFFE_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0010001000100000
+.gate SB_LUT4 I0=SPI.C1.clk_count[7] I1=SPI.C1.clk_count[6] I2=SPI.C1.clk_count[5] I3=SPI.C1.clk_count[4] O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=SPI.C1.clk_count[3] I1=SPI.C1.clk_count[2] I2=SPI.C1.clk_count[1] I3=SPI.C1.clk_count[0] O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C1.SCLKSTATE[1] O=SPI.C1.clk_edge_buffer_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.done_SB_DFFESR_Q_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.done R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I2 I3=SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I3 O=SPI.C1.done_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_LUT4 I0=SPI.C1.RxSTATE[1] I1=SPI.C1.done I2=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I3=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 O=SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101010001000100
+.gate SB_LUT4 I0=SPI.C1.SCLKSTATE[0] I1=SPI.C1.RxSTATE[0] I2=SPI.C0.transmit I3=SPI.C1.SCLKSTATE[1] O=SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_count_SB_DFFESR_Q_D E=SPI.C1.rx_count_SB_DFFESR_Q_E Q=SPI.C1.rx_count[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_count_SB_DFFESR_Q_1_D E=SPI.C1.rx_count_SB_DFFESR_Q_E Q=SPI.C1.rx_count[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I1=$false I2=SPI.C1.rx_count[2] I3=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] O=SPI.C1.rx_count_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:191|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_count_SB_DFFESR_Q_2_D E=SPI.C1.rx_count_SB_DFFESR_Q_E Q=SPI.C1.rx_count[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I1=$false I2=SPI.C1.rx_count[1] I3=SPI.C1.rx_count[0] O=SPI.C1.rx_count_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:191|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_count_SB_DFFESR_Q_3_D E=SPI.C1.rx_count_SB_DFFESR_Q_E Q=SPI.C1.rx_count[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C1.rx_count[0] O=SPI.C1.rx_count_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I2=SPI.C1.rx_count[3] I3=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] O=SPI.C1.rx_count_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:191|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001100110000
+.gate SB_LUT4 I0=SPI.C1.rx_count[3] I1=SPI.C1.rx_count[2] I2=SPI.C1.rx_count[1] I3=SPI.C1.rx_count[0] O=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_CARRY CI=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] CO=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] I0=$false I1=SPI.C1.rx_count[2]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:191|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.rx_count[0] CO=SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=SPI.C1.rx_count[1]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:191|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O O=SPI.C1.rx_count_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111111100001111
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_1_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[5] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[6] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_2_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[4] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[5] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_3_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[3] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[4] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_4_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[2] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[3] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_5_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[1] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[2] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.rx_shift_register_SB_DFFESR_Q_6_D E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[0] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[1] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESR C=SPI.C0.clk D=SDI_SB_LUT4_I0_O E=SPI.C1.done_SB_DFFESR_Q_E Q=SPI.C1.rx_shift_register[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:153|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.rx_shift_register[6] I1=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O I2=SPI.C1.rx_shift_register[7] I3=SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O O=SPI.C1.rx_shift_register_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000100011111000
+.gate SB_DFFESS C=SPI.C0.clk D=SPI.C1.sdo_SB_DFFESS_Q_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.sdo S=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.TxSTATE[0] I1=SPI.C1.TxSTATE[1] I2=SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I2 I3=SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I3 O=SPI.C1.sdo_SB_DFFESS_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000100100011
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.TxSTATE[1] I3=count[19] O=SPI.C1.sdo_SB_DFFESS_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000111111111111
+.gate SB_LUT4 I0=$false I1=SPI.C1.sdo I2=SPI.C1.done I3=SPI.C0.transmit O=SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0011001100000011
+.gate SB_LUT4 I0=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I1=SPI.C1.sdo_SB_LUT4_I2_I1 I2=SPI.C1.sdo I3=SPI.C1.tx_shift_register[15] O=SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000110100101111
+.gate SB_DFFE C=SPI.C0.clk D=SPI.C1.sdo_SB_LUT4_I2_I1_SB_DFFE_Q_D E=SPI.C1.SCLKSTATE_SB_DFFESR_Q_E Q=SPI.C1.sdo_SB_LUT4_I2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:202|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_count_SB_DFFESR_Q_D E=SPI.C1.tx_count_SB_DFFESR_Q_E Q=SPI.C1.tx_count[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_count_SB_DFFESR_Q_1_D E=SPI.C1.tx_count_SB_DFFESR_Q_E Q=SPI.C1.tx_count[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I1=$false I2=SPI.C1.tx_count[2] I3=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] O=SPI.C1.tx_count_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:141|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_count_SB_DFFESR_Q_2_D E=SPI.C1.tx_count_SB_DFFESR_Q_E Q=SPI.C1.tx_count[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I1=$false I2=SPI.C1.tx_count[1] I3=SPI.C1.tx_count[0] O=SPI.C1.tx_count_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:141|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_count_SB_DFFESR_Q_3_D E=SPI.C1.tx_count_SB_DFFESR_Q_E Q=SPI.C1.tx_count[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SPI.C1.tx_count[0] O=SPI.C1.tx_count_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 I2=SPI.C1.tx_count[3] I3=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] O=SPI.C1.tx_count_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:141|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001100110000
+.gate SB_LUT4 I0=$false I1=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I2=SPI.C1.sdo_SB_LUT4_I2_I1 I3=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1 O=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000001100
+.gate SB_LUT4 I0=SPI.C1.tx_count[3] I1=SPI.C1.tx_count[2] I2=SPI.C1.tx_count[1] I3=SPI.C1.tx_count[0] O=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_CARRY CI=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] CO=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3] I0=$false I1=SPI.C1.tx_count[2]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:141|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=SPI.C1.tx_count[0] CO=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=SPI.C1.tx_count[1]
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:141|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=count[19] I1=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I2=SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q I3=SPI.C1.sdo_SB_LUT4_I2_I1 O=SPI.C1.tx_count_SB_DFFESR_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0101010111010101
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[15] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[14] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[5] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[4] I3=SPI.C1.tx_shift_register[5] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[4] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[3] I3=SPI.C1.tx_shift_register[4] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[3] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[2] I3=SPI.C1.tx_shift_register[3] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[2] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[1] I3=SPI.C1.tx_shift_register[2] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.TxSTATE[0] I1=SPI.C1.TxSTATE[1] I2=SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D_SB_LUT4_O_I2 I3=SPI.C0.txdata[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0001001100000010
+.gate SB_LUT4 I0=$false I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[0] I3=SPI.C1.tx_shift_register[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000110000111111
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D_SB_LUT4_O_I0 I1=SPI.C1.tx_shift_register[0] I2=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I3=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O O=SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101011101010
+.gate SB_LUT4 I0=$false I1=SPI.C0.txdata[0] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000001100
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[14] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[13] I3=SPI.C1.tx_shift_register[14] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[13] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[13] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[12] I3=SPI.C1.tx_shift_register[13] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[12] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[12] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[11] I3=SPI.C1.tx_shift_register[12] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[11] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[11] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[10] I3=SPI.C1.tx_shift_register[11] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[10] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[10] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[9] I3=SPI.C1.tx_shift_register[10] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[9] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[8] I3=SPI.C1.tx_shift_register[9] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[8] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[7] I3=SPI.C1.tx_shift_register[8] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[7] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[6] I3=SPI.C1.tx_shift_register[7] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_DFFESR C=SPI.C0.clk D=SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D E=SPI.C1.sdo_SB_DFFESS_Q_E Q=SPI.C1.tx_shift_register[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:104|spiinterface.v:104|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[6] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[5] I3=SPI.C1.tx_shift_register[6] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_LUT4 I0=SPI.C1.tx_shift_register_SB_DFFESR_Q_D_SB_LUT4_O_I0 I1=SPI.C0.txdata[15] I2=SPI.C1.TxSTATE[0] I3=SPI.C1.TxSTATE[1] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010101010101110
+.gate SB_LUT4 I0=SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1 I1=SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O I2=SPI.C1.tx_shift_register[14] I3=SPI.C1.tx_shift_register[15] O=SPI.C1.tx_shift_register_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1010001010000000
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=SS_SB_LUT4_O_I3 O=SS
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_DFFE C=SPI.C0.clk D=SS_SB_LUT4_O_I3_SB_DFFE_Q_D E=SS_SB_LUT4_O_I3_SB_DFFE_Q_E Q=SS_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:97|spicomponent.v:119|slaveselect.v:60|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_LUT4 I0=$false I1=$false I2=SPI.C0.transmit I3=count[19] O=SS_SB_LUT4_O_I3_SB_DFFE_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=count[19] I2=SPI.C0.transmit I3=SPI.C1.done O=SS_SB_LUT4_O_I3_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 1111111111110011
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[26] E=count_SB_DFFE_Q_E Q=count[26]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[25] E=count_SB_DFFE_Q_E Q=count[25]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[16] E=count_SB_DFFE_Q_E Q=count[16]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[15] E=count_SB_DFFE_Q_E Q=count[15]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[14] E=count_SB_DFFE_Q_E Q=count[14]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[13] E=count_SB_DFFE_Q_E Q=count[13]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[12] E=count_SB_DFFE_Q_E Q=count[12]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[11] E=count_SB_DFFE_Q_E Q=count[11]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[10] E=count_SB_DFFE_Q_E Q=count[10]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[9] E=count_SB_DFFE_Q_E Q=count[9]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[8] E=count_SB_DFFE_Q_E Q=count[8]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[7] E=count_SB_DFFE_Q_E Q=count[7]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[24] E=count_SB_DFFE_Q_E Q=count[24]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[6] E=count_SB_DFFE_Q_E Q=count[6]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[5] E=count_SB_DFFE_Q_E Q=count[5]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[4] E=count_SB_DFFE_Q_E Q=count[4]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[3] E=count_SB_DFFE_Q_E Q=count[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[2] E=count_SB_DFFE_Q_E Q=count[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[1] E=count_SB_DFFE_Q_E Q=count[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[0] E=count_SB_DFFE_Q_E Q=count[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[23] E=count_SB_DFFE_Q_E Q=count[23]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[22] E=count_SB_DFFE_Q_E Q=count[22]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[21] E=count_SB_DFFE_Q_E Q=count[21]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[20] E=count_SB_DFFE_Q_E Q=count[20]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[19] E=count_SB_DFFE_Q_E Q=count[19]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[18] E=count_SB_DFFE_Q_E Q=count[18]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_DFFE C=clk_in D=count_SB_DFFE_Q_D[17] E=count_SB_DFFE_Q_E Q=count[17]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:85|/usr/local/bin/../share/yosys/ice40/cells_map.v:8"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D[0] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[2] I0=$false I1=count_SB_DFFE_Q_D_SB_CARRY_CI_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[1] O=count_SB_DFFE_Q_D_SB_CARRY_CI_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=count[9] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[9] O=count_SB_DFFE_Q_D[9]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[8] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[8] O=count_SB_DFFE_Q_D[8]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[24] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[24] O=count_SB_DFFE_Q_D[24]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[23] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[23] O=count_SB_DFFE_Q_D[23]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[22] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[22] O=count_SB_DFFE_Q_D[22]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[21] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[21] O=count_SB_DFFE_Q_D[21]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[20] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[20] O=count_SB_DFFE_Q_D[20]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[1] I3=count[0] O=count_SB_DFFE_Q_D[1]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[19] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[19] O=count_SB_DFFE_Q_D[19]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[18] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[18] O=count_SB_DFFE_Q_D[18]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[17] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[17] O=count_SB_DFFE_Q_D[17]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[16] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[16] O=count_SB_DFFE_Q_D[16]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[7] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[7] O=count_SB_DFFE_Q_D[7]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[15] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[15] O=count_SB_DFFE_Q_D[15]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[14] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[14] O=count_SB_DFFE_Q_D[14]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[13] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[13] O=count_SB_DFFE_Q_D[13]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[12] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[12] O=count_SB_DFFE_Q_D[12]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[11] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[11] O=count_SB_DFFE_Q_D[11]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[10] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[10] O=count_SB_DFFE_Q_D[10]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[0] O=count_SB_DFFE_Q_D[0]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=count[6] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[6] O=count_SB_DFFE_Q_D[6]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[5] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[5] O=count_SB_DFFE_Q_D[5]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[4] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[4] O=count_SB_DFFE_Q_D[4]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[3] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[3] O=count_SB_DFFE_Q_D[3]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[2] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[2] O=count_SB_DFFE_Q_D[2]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[26] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[26] O=count_SB_DFFE_Q_D[26]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_LUT4 I0=$false I1=$false I2=count[25] I3=count_SB_DFFE_Q_D_SB_LUT4_O_I3[25] O=count_SB_DFFE_Q_D[25]
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0110100110010110
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[9] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[10] I0=$false I1=count[9]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[8] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[9] I0=$false I1=count[8]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[23] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[24] I0=$false I1=count[23]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[22] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[23] I0=$false I1=count[22]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[21] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[22] I0=$false I1=count[21]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[20] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[21] I0=$false I1=count[20]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count[0] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[2] I0=$false I1=count[1]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[19] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[20] I0=$false I1=count[19]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[18] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[19] I0=$false I1=count[18]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[17] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[18] I0=$false I1=count[17]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[16] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[17] I0=$false I1=count[16]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[15] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[16] I0=$false I1=count[15]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[7] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[8] I0=$false I1=count[7]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[14] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[15] I0=$false I1=count[14]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[13] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[14] I0=$false I1=count[13]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[12] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[13] I0=$false I1=count[12]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[11] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[12] I0=$false I1=count[11]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[10] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[11] I0=$false I1=count[10]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[6] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[7] I0=$false I1=count[6]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[5] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[6] I0=$false I1=count[5]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[4] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[5] I0=$false I1=count[4]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[3] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[4] I0=$false I1=count[3]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[2] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[3] I0=$false I1=count[2]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[25] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[26] I0=$false I1=count[25]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_D_SB_LUT4_O_I3[24] CO=count_SB_DFFE_Q_D_SB_LUT4_O_I3[25] I0=$false I1=count[24]
+.attr src "pmodacl_demo.v:89|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=count_SB_DFFE_Q_E_SB_LUT4_O_I2 I3=count_SB_DFFE_Q_E_SB_LUT4_O_I3 O=count_SB_DFFE_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000011110000
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[26] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2 I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[9] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[10] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[8] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[9] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_1_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[23] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[24] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_10_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[23] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_10_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[22] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[23] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_11_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[22] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_11_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[21] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[22] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_12_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[21] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_12_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[20] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[21] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_13_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[20] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_13_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[19] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[20] I0=$true I1=genStart.RST
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[18] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[19] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_15_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[18] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_15_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[17] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[18] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_16_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[17] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_16_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[16] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[17] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_17_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[16] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_17_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[15] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[16] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_18_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[15] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_18_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[14] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[15] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_19_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[14] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_19_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[8] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_1_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[7] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[8] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_2_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[13] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[14] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_20_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[13] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_20_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[12] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[13] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_21_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[12] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_21_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[11] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[12] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_22_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[11] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_22_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[10] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[11] I0=$true I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_23_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[10] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_23_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[7] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_2_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[6] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[7] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_3_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[6] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_3_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[5] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[6] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_4_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[5] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_4_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[4] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[5] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_5_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[4] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_5_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[3] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[4] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_6_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[3] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_6_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[2] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[3] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_7_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[2] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_7_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[25] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[26] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_8_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[25] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_8_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[24] CO=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[25] I0=$false I1=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_9_I1
+.attr src "pmodacl_demo.v:87|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[24] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_9_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[9] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[26] O=count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3 O=count_SB_DFFE_Q_E_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=count[20] I1=count[16] I2=count[17] I3=count[18] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000010000000
+.gate SB_LUT4 I0=count[22] I1=count[4] I2=count[26] I3=count[21] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_LUT4 I0=$false I1=count[25] I2=count[24] I3=count[23] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:51"
+.param LUT_INIT 0000000000000011
+.gate SB_LUT4 I0=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I0 I1=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1 I2=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3 O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=count[11] I1=count[10] I2=count[8] I3=count[9] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000010000000
+.gate SB_LUT4 I0=count[15] I1=count[14] I2=count[13] I3=count[12] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_LUT4 I0=count[19] I1=count[2] I2=count[1] I3=count[0] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_LUT4 I0=count[7] I1=count[6] I2=count[5] I3=count[3] O=count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000010
+.gate SB_DFFER C=SPI.C0.clk D=genStart.CLKOUT_SB_DFFER_Q_D E=genStart.CLKOUT_SB_DFFER_Q_E Q=genStart.CLKOUT R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:27"
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=genStart.CLKOUT O=genStart.CLKOUT_SB_DFFER_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_LUT4 I0=$false I1=$false I2=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2 I3=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3 O=genStart.CLKOUT_SB_DFFER_Q_E
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=$false I1=$false I2=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2 I3=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3 O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I0 I1=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I1 I2=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I2 I3=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I3 O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=genStart.clkCount[12] I1=genStart.clkCount[10] I2=genStart.clkCount[9] I3=genStart.clkCount[7] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I0
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=genStart.clkCount[23] I1=genStart.clkCount[20] I2=genStart.clkCount[19] I3=genStart.clkCount[15] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I1
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 1000000000000000
+.gate SB_LUT4 I0=genStart.clkCount[16] I1=genStart.clkCount[14] I2=genStart.clkCount[13] I3=genStart.clkCount[11] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=genStart.clkCount[22] I1=genStart.clkCount[21] I2=genStart.clkCount[18] I3=genStart.clkCount[17] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=$false I1=$false I2=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2 I3=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3 O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 1111000000000000
+.gate SB_LUT4 I0=genStart.clkCount[3] I1=genStart.clkCount[2] I2=genStart.clkCount[1] I3=genStart.clkCount[0] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=genStart.clkCount[8] I1=genStart.clkCount[6] I2=genStart.clkCount[5] I3=genStart.clkCount[4] O=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000000000000001
+.gate SB_LUT4 I0=$false I1=$false I2=$false I3=count[19] O=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41"
+.param LUT_INIT 0000000011111111
+.gate SB_CARRY CI=genStart.clkCount[0] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[2] I0=$false I1=genStart.clkCount[1]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[9] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[10] I0=$false I1=genStart.clkCount[9]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[9] I0=$false I1=genStart.clkCount[8]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[20] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[21] I0=$false I1=genStart.clkCount[20]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[19] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[20] I0=$false I1=genStart.clkCount[19]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[18] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[19] I0=$false I1=genStart.clkCount[18]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[17] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[18] I0=$false I1=genStart.clkCount[17]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[17] I0=$false I1=genStart.clkCount[16]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[15] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16] I0=$false I1=genStart.clkCount[15]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[14] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[15] I0=$false I1=genStart.clkCount[14]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[13] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[14] I0=$false I1=genStart.clkCount[13]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[12] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[13] I0=$false I1=genStart.clkCount[12]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[11] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[12] I0=$false I1=genStart.clkCount[11]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[7] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8] I0=$false I1=genStart.clkCount[7]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[10] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[11] I0=$false I1=genStart.clkCount[10]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[6] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[7] I0=$false I1=genStart.clkCount[6]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[5] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[6] I0=$false I1=genStart.clkCount[5]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[4] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[5] I0=$false I1=genStart.clkCount[4]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[3] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[4] I0=$false I1=genStart.clkCount[3]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[2] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[3] I0=$false I1=genStart.clkCount[2]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[22] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[23] I0=$false I1=genStart.clkCount[22]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_CARRY CI=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[21] CO=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[22] I0=$false I1=genStart.clkCount[21]
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47"
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_D Q=genStart.clkCount[23] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_1_D Q=genStart.clkCount[22] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_10_D Q=genStart.clkCount[13] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[13] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[13] O=genStart.clkCount_SB_DFFR_Q_10_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_11_D Q=genStart.clkCount[12] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[12] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[12] O=genStart.clkCount_SB_DFFR_Q_11_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_12_D Q=genStart.clkCount[11] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[11] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[11] O=genStart.clkCount_SB_DFFR_Q_12_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_13_D Q=genStart.clkCount[10] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[10] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[10] O=genStart.clkCount_SB_DFFR_Q_13_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_14_D Q=genStart.clkCount[9] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[9] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[9] O=genStart.clkCount_SB_DFFR_Q_14_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_15_D Q=genStart.clkCount[8] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[8] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8] O=genStart.clkCount_SB_DFFR_Q_15_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_16_D Q=genStart.clkCount[7] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[7] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[7] O=genStart.clkCount_SB_DFFR_Q_16_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_17_D Q=genStart.clkCount[6] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[6] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[6] O=genStart.clkCount_SB_DFFR_Q_17_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_18_D Q=genStart.clkCount[5] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[5] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[5] O=genStart.clkCount_SB_DFFR_Q_18_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_19_D Q=genStart.clkCount[4] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[4] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[4] O=genStart.clkCount_SB_DFFR_Q_19_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[22] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[22] O=genStart.clkCount_SB_DFFR_Q_1_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_2_D Q=genStart.clkCount[21] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_20_D Q=genStart.clkCount[3] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[3] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[3] O=genStart.clkCount_SB_DFFR_Q_20_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_21_D Q=genStart.clkCount[2] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[2] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[2] O=genStart.clkCount_SB_DFFR_Q_21_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_22_D Q=genStart.clkCount[1] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[1] I3=genStart.clkCount[0] O=genStart.clkCount_SB_DFFR_Q_22_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_23_D Q=genStart.clkCount[0] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=$false I1=$false I2=genStart.clkCount[0] I3=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O O=genStart.clkCount_SB_DFFR_Q_23_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:46"
+.param LUT_INIT 0000000000001111
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[21] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[21] O=genStart.clkCount_SB_DFFR_Q_2_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_3_D Q=genStart.clkCount[20] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[20] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[20] O=genStart.clkCount_SB_DFFR_Q_3_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_4_D Q=genStart.clkCount[19] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[19] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[19] O=genStart.clkCount_SB_DFFR_Q_4_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_5_D Q=genStart.clkCount[18] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[18] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[18] O=genStart.clkCount_SB_DFFR_Q_5_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_6_D Q=genStart.clkCount[17] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[17] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[17] O=genStart.clkCount_SB_DFFR_Q_6_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_7_D Q=genStart.clkCount[16] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[16] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16] O=genStart.clkCount_SB_DFFR_Q_7_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_8_D Q=genStart.clkCount[15] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[15] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[15] O=genStart.clkCount_SB_DFFR_Q_8_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_DFFR C=SPI.C0.clk D=genStart.clkCount_SB_DFFR_Q_9_D Q=genStart.clkCount[14] R=genStart.RST
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:51|/usr/local/bin/../share/yosys/ice40/cells_map.v:17"
+.gate SB_LUT4 I0=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I1=$false I2=genStart.clkCount[14] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[14] O=genStart.clkCount_SB_DFFR_Q_9_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000010101010000
+.gate SB_LUT4 I0=$false I1=genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O I2=genStart.clkCount[23] I3=genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[23] O=genStart.clkCount_SB_DFFR_Q_D
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:113|clkdiv_5hz.v:64|/usr/local/bin/../share/yosys/ice40/arith_map.v:47|/usr/local/bin/../share/yosys/ice40/cells_map.v:56"
+.param LUT_INIT 0000001100110000
+.gate SB_PLL40_CORE BYPASS=$false PLLOUTCORE=SPI.C0.clk PLLOUTGLOBAL=ice_pll_inst.PLLOUTGLOBAL REFERENCECLK=clk_in RESETB=$true
+.attr module_not_derived 00000000000000000000000000000001
+.attr src "pmodacl_demo.v:75|ice_pll.v:11"
+.param DELAY_ADJUSTMENT_MODE_FEEDBACK "FIXED"
+.param DELAY_ADJUSTMENT_MODE_RELATIVE "FIXED"
+.param DIVF 0111010
+.param DIVQ 011
+.param DIVR 0000
+.param ENABLE_ICEGATE 0
+.param FDA_FEEDBACK 0000
+.param FDA_RELATIVE 0000
+.param FEEDBACK_PATH "SIMPLE"
+.param FILTER_RANGE 001
+.param PLLOUT_SELECT "GENCLK"
+.param SHIFTREG_DIV_MODE 00
+.names $true LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[0]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[1]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[5]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[6]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[7]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[8]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[9]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[10]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[11]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[12]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[13]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[14]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[15]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[16]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[17]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[18]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[19]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[20]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[21]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[22]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[23]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[24]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[25]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[26]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[27]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[28]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[29]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[30]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[31]
+1 1
+.names $true LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[0]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[1]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[5]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[6]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[7]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[8]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[9]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[10]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[11]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[12]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[13]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[14]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[15]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[16]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[17]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[18]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[19]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[20]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[21]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[22]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[23]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[24]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[25]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[26]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[27]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[28]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[29]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[30]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[31]
+1 1
+.names $true count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[0]
+1 1
+.names count_SB_DFFE_Q_D[0] count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[1]
+1 1
+.names $false count_SB_DFFE_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names count[0] count_SB_DFFE_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names $true LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[0]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[1]
+1 1
+.names LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[4]
+1 1
+.names $true LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[5]
+1 1
+.names $true LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[0]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[1]
+1 1
+.names LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[4]
+1 1
+.names $true LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[5]
+1 1
+.names $false SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names SPI.C0.break_count[0] SPI.C0.break_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names $false SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[0]
+1 1
+.names SPI.C0.hold_count[0] SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[1]
+1 1
+.names $false SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names SPI.C1.tx_count[0] SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names $false SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names SPI.C1.rx_count[0] SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names $false SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[0]
+1 1
+.names SPI.C1.clk_count[0] SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[1]
+1 1
+.names $false genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[0]
+1 1
+.names genStart.clkCount[0] genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[1]
+1 1
+.names SPI.C0.clk CLK
+1 1
+.names ice_pll_inst.PLLOUTGLOBAL PLLOUTGLOBAL
+1 1
+.names genStart.RST RST
+1 1
+.names SPI.C1.sdo SDO
+1 1
+.names SPI.C1.done SPI.C0.done
+1 1
+.names genStart.RST SPI.C0.rst
+1 1
+.names SPI.C1.rx_shift_register[0] SPI.C0.rxdata[0]
+1 1
+.names SPI.C1.rx_shift_register[1] SPI.C0.rxdata[1]
+1 1
+.names SPI.C1.rx_shift_register[2] SPI.C0.rxdata[2]
+1 1
+.names SPI.C1.rx_shift_register[3] SPI.C0.rxdata[3]
+1 1
+.names SPI.C1.rx_shift_register[4] SPI.C0.rxdata[4]
+1 1
+.names SPI.C1.rx_shift_register[5] SPI.C0.rxdata[5]
+1 1
+.names SPI.C1.rx_shift_register[6] SPI.C0.rxdata[6]
+1 1
+.names SPI.C1.rx_shift_register[7] SPI.C0.rxdata[7]
+1 1
+.names genStart.CLKOUT SPI.C0.start
+1 1
+.names $undef SPI.C0.x_axis_data[0]
+1 1
+.names $undef SPI.C0.x_axis_data[1]
+1 1
+.names $undef SPI.C0.x_axis_data[2]
+1 1
+.names $undef SPI.C0.x_axis_data[3]
+1 1
+.names $undef SPI.C0.x_axis_data[4]
+1 1
+.names $undef SPI.C0.z_axis_data[0]
+1 1
+.names $undef SPI.C0.z_axis_data[1]
+1 1
+.names $undef SPI.C0.z_axis_data[2]
+1 1
+.names $undef SPI.C0.z_axis_data[3]
+1 1
+.names $undef SPI.C0.z_axis_data[4]
+1 1
+.names SPI.C0.clk SPI.C1.clk
+1 1
+.names SPI.C1.done SPI.C1.done_out
+1 1
+.names genStart.RST SPI.C1.rst
+1 1
+.names SPI.C1.rx_shift_register[0] SPI.C1.rxbuffer[0]
+1 1
+.names SPI.C1.rx_shift_register[1] SPI.C1.rxbuffer[1]
+1 1
+.names SPI.C1.rx_shift_register[2] SPI.C1.rxbuffer[2]
+1 1
+.names SPI.C1.rx_shift_register[3] SPI.C1.rxbuffer[3]
+1 1
+.names SPI.C1.rx_shift_register[4] SPI.C1.rxbuffer[4]
+1 1
+.names SPI.C1.rx_shift_register[5] SPI.C1.rxbuffer[5]
+1 1
+.names SPI.C1.rx_shift_register[6] SPI.C1.rxbuffer[6]
+1 1
+.names SPI.C1.rx_shift_register[7] SPI.C1.rxbuffer[7]
+1 1
+.names SCLK SPI.C1.sck_buffer
+1 1
+.names SCLK SPI.C1.sclk
+1 1
+.names SDI SPI.C1.sdi
+1 1
+.names SPI.C0.transmit SPI.C1.transmit
+1 1
+.names SPI.C0.txdata[0] SPI.C1.txbuffer[0]
+1 1
+.names SPI.C0.txdata[1] SPI.C1.txbuffer[1]
+1 1
+.names SPI.C0.txdata[2] SPI.C1.txbuffer[2]
+1 1
+.names SPI.C0.txdata[3] SPI.C1.txbuffer[3]
+1 1
+.names SPI.C0.txdata[4] SPI.C1.txbuffer[4]
+1 1
+.names SPI.C0.txdata[5] SPI.C1.txbuffer[5]
+1 1
+.names SPI.C0.txdata[6] SPI.C1.txbuffer[6]
+1 1
+.names SPI.C0.txdata[7] SPI.C1.txbuffer[7]
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diff --git a/IceStick_Accelerometer/src/pmodacl.txt b/IceStick_Accelerometer/src/pmodacl.txt
new file mode 100644
index 0000000..3857a96
--- /dev/null
+++ b/IceStick_Accelerometer/src/pmodacl.txt
@@ -0,0 +1,6869 @@
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+.sym 8410 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I1_O
+.sym 8411 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 8412 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 8531 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 8534 SPI.C1.SCLKSTATE[0]
+.sym 8564 $true
+.sym 8601 SPI.C1.rx_count[0]$2
+.sym 8602 $false
+.sym 8603 SPI.C1.rx_count[0]
+.sym 8604 $false
+.sym 8605 $false
+.sym 8607 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 8609 $false
+.sym 8610 SPI.C1.rx_count[1]
+.sym 8613 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 8614 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 8615 $false
+.sym 8616 SPI.C1.rx_count[2]
+.sym 8617 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[2]
+.sym 8620 $false
+.sym 8621 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 8622 SPI.C1.rx_count[3]
+.sym 8623 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I3[3]
+.sym 8632 $false
+.sym 8633 $false
+.sym 8634 $false
+.sym 8635 SPI.C1.rx_count[0]
+.sym 8638 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 8639 $false
+.sym 8640 SPI.C1.rx_count[1]
+.sym 8641 SPI.C1.rx_count[0]
+.sym 8648 SPI.C1.rx_count_SB_DFFESR_Q_E
+.sym 8649 SPI.C0.clk$2
+.sym 8650 genStart.RST$2
+.sym 8653 SPI.C0.transmit_SB_DFFESR_Q_E
+.sym 8656 SPI.C0.transmit
+.sym 8725 SPI.C1.rx_count[3]
+.sym 8726 SPI.C1.rx_count[2]
+.sym 8727 SPI.C1.rx_count[1]
+.sym 8728 SPI.C1.rx_count[0]
+.sym 8731 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0
+.sym 8732 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I1
+.sym 8733 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2
+.sym 8734 SPI.C0.finish_SB_LUT4_I3_O
+.sym 8737 SPI.C1.SCLKSTATE[0]
+.sym 8738 SPI.C1.RxSTATE[0]
+.sym 8739 SPI.C0.transmit
+.sym 8740 SPI.C1.SCLKSTATE[1]
+.sym 8743 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I0
+.sym 8744 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_I1
+.sym 8745 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I2
+.sym 8746 SPI.C0.finish_SB_LUT4_I3_O
+.sym 8755 $false
+.sym 8756 $false
+.sym 8757 count[19]
+.sym 8758 SPI.C0.STATE[5]
+.sym 8761 count[19]
+.sym 8762 SPI.C0.STATE[1]
+.sym 8763 SPI.C1.done
+.sym 8764 SPI.C0.end_configure
+.sym 8767 $false
+.sym 8768 $false
+.sym 8769 count[19]
+.sym 8770 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 8775 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 8776 SPI.C0.STATE_SB_DFF_Q_1_D_SB_LUT4_O_I3
+.sym 8777 SPI.C0.STATE[5]
+.sym 8778 SPI.C0.STATE[6]
+.sym 8781 SPI.C0.STATE[1]
+.sym 8848 SPI.C1.RxSTATE[0]
+.sym 8849 SPI.C1.RxSTATE[1]
+.sym 8850 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 8851 SPI.C0.transmit
+.sym 8854 SPI.C1.RxSTATE[1]
+.sym 8855 SPI.C1.done
+.sym 8856 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 8857 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 8860 $false
+.sym 8861 $false
+.sym 8862 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 8863 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 8866 $false
+.sym 8867 $false
+.sym 8868 SPI.C1.rx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 8869 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 8878 $false
+.sym 8879 SPI.C1.RxSTATE[0]
+.sym 8880 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 8881 SPI.C1.RxSTATE[1]
+.sym 8884 SPI.C1.RxSTATE[0]
+.sym 8885 SPI.C1.RxSTATE[1]
+.sym 8886 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.sym 8887 SPI.C0.transmit
+.sym 8890 $false
+.sym 8891 $false
+.sym 8892 SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 8893 SPI.C1.done_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 8894 SPI.C1.done_SB_DFFESR_Q_E
+.sym 8895 SPI.C0.clk$2
+.sym 8896 genStart.RST$2
+.sym 8897 SPI.C0.register_select_SB_DFFESR_Q_E
+.sym 8904 SPI.C0.register_select
+.sym 8971 $false
+.sym 8972 $false
+.sym 8973 count[19]
+.sym 8974 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 9020 SPI.C1.rx_shift_register[1]
+.sym 9023 SPI.C1.rx_shift_register[2]
+.sym 9026 SPI.C1.rx_shift_register[0]
+.sym 9094 $false
+.sym 9095 SPI.C1.sdo
+.sym 9096 SPI.C1.done
+.sym 9097 SPI.C0.transmit
+.sym 9100 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 9101 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 9102 SPI.C1.tx_shift_register[14]
+.sym 9103 SPI.C1.tx_shift_register[15]
+.sym 9106 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 9107 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 9108 SPI.C1.sdo
+.sym 9109 SPI.C1.tx_shift_register[15]
+.sym 9112 $false
+.sym 9113 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1
+.sym 9114 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 9115 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 9118 count[19]
+.sym 9119 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 9120 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 9121 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 9124 SPI.C1.TxSTATE[0]
+.sym 9125 SPI.C1.TxSTATE[1]
+.sym 9126 SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I2
+.sym 9127 SPI.C1.sdo_SB_DFFESS_Q_D_SB_LUT4_O_I3
+.sym 9130 SPI.C1.TxSTATE[0]
+.sym 9131 SPI.C1.TxSTATE[1]
+.sym 9132 SPI.C1.TxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.sym 9133 SPI.C0.transmit
+.sym 9136 SPI.C1.tx_shift_register_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 9137 SPI.C0.txdata[15]
+.sym 9138 SPI.C1.TxSTATE[0]
+.sym 9139 SPI.C1.TxSTATE[1]
+.sym 9140 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 9141 SPI.C0.clk$2
+.sym 9142 genStart.RST$2
+.sym 9144 SPI.C1.rx_shift_register[4]
+.sym 9145 SPI.C1.rx_shift_register[3]
+.sym 9147 SPI.C1.rx_shift_register[7]
+.sym 9148 SPI.C1.rx_shift_register[5]
+.sym 9149 SPI.C1.rx_shift_register[6]
+.sym 9223 $false
+.sym 9224 $false
+.sym 9225 SPI.C1.TxSTATE[1]
+.sym 9226 count[19]
+.sym 9229 $false
+.sym 9230 $false
+.sym 9231 SPI.C1.TxSTATE[0]
+.sym 9232 SPI.C1.TxSTATE[1]
+.sym 9266 SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.sym 9267 SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.sym 9268 SPI.C1.tx_shift_register[4]
+.sym 9270 SPI.C1.tx_shift_register[3]
+.sym 9358 $false
+.sym 9359 $false
+.sym 9360 SPI.C0.txdata[4]
+.sym 9361 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 9386 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 9387 SPI.C0.clk$2
+.sym 9388 genStart.RST$2
+.sym 9389 SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D_SB_LUT4_O_I2
+.sym 9392 SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.sym 9393 SPI.C1.tx_shift_register[1]
+.sym 9395 SPI.C1.tx_shift_register[2]
+.sym 9396 SPI.C1.tx_shift_register[0]
+.sym 9463 $false
+.sym 9464 $false
+.sym 9465 SPI.C0.txdata[6]
+.sym 9466 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 9469 $false
+.sym 9470 $false
+.sym 9471 SPI.C0.txdata[2]
+.sym 9472 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 9481 $false
+.sym 9482 $false
+.sym 9483 SPI.C0.txdata[1]
+.sym 9484 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 9509 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 9510 SPI.C0.clk$2
+.sym 9511 genStart.RST$2
+.sym 9637 count[2]
+.sym 9638 count[3]
+.sym 9639 count[4]
+.sym 9640 count[5]
+.sym 9641 count[6]
+.sym 9642 count[7]
+.sym 9758 count[8]
+.sym 9759 count[9]
+.sym 9760 count[10]
+.sym 9761 count[11]
+.sym 9762 count[12]
+.sym 9763 count[13]
+.sym 9764 count[14]
+.sym 9765 count[15]
+.sym 9856 $false
+.sym 9857 $false
+.sym 9858 $false
+.sym 9859 count[21]
+.sym 9881 count[16]
+.sym 9882 count[17]
+.sym 9883 count[18]
+.sym 9884 count[19]
+.sym 9885 count[20]
+.sym 9886 count[21]
+.sym 9887 count[22]
+.sym 9888 count[23]
+.sym 9979 $false
+.sym 9980 $false
+.sym 9981 $false
+.sym 9982 count[24]
+.sym 10004 count[24]
+.sym 10005 count[25]
+.sym 10006 count[26]
+.sym 10201 SPI.C0.clk
+.sym 10228 SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I2
+.sym 10229 SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I2
+.sym 10230 SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.sym 10231 SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.sym 10232 SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.sym 10233 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 10301 $false
+.sym 10302 $false
+.sym 10303 SPI.C1.clk_count[5]
+.sym 10304 SPI.C1.done
+.sym 10313 $false
+.sym 10314 $false
+.sym 10315 SPI.C1.clk_count[3]
+.sym 10316 SPI.C1.done
+.sym 10319 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10320 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 10321 SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.sym 10322 SPI.C1.clk_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.sym 10331 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10332 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 10333 SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I2
+.sym 10334 SPI.C1.clk_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.sym 10347 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 10348 SPI.C0.clk$2
+.sym 10349 genStart.RST$2
+.sym 10352 SPI.C0.clk
+.sym 10354 SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2
+.sym 10355 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 10356 SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2_SB_LUT4_O_I0
+.sym 10357 SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
+.sym 10358 SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 10359 SPI.C1.clk_count[1]
+.sym 10360 SPI.C1.clk_count[2]
+.sym 10361 SPI.C1.clk_count[4]
+.sym 10464 SPI.C1.done
+.sym 10465 SPI.C1.clk_count[0]
+.sym 10466 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 10467 SPI.C1.clk_edge_buffer
+.sym 10470 $false
+.sym 10471 $false
+.sym 10472 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 10473 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 10476 $false
+.sym 10477 SPI.C1.done
+.sym 10478 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 10479 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 10488 $false
+.sym 10489 $false
+.sym 10490 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 10491 SPI.C1.clk_edge_buffer
+.sym 10500 $false
+.sym 10501 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 10502 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 10503 SPI.C1.done
+.sym 10506 $false
+.sym 10507 $false
+.sym 10508 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10509 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.sym 10510 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 10511 SPI.C0.clk$2
+.sym 10512 genStart.RST$2
+.sym 10516 SPI.C1.clk_edge_buffer
+.sym 10587 $false
+.sym 10588 $false
+.sym 10589 count[19]
+.sym 10590 SPI.C1.SCLKSTATE[1]
+.sym 10599 $false
+.sym 10600 $false
+.sym 10601 SPI.C1.SCLKSTATE[0]
+.sym 10602 SPI.C1.SCLKSTATE[1]
+.sym 10611 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10612 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 10613 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2
+.sym 10614 SPI.C1.clk_edge_buffer
+.sym 10617 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10618 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 10619 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 10620 SPI.C1.sdo_SB_LUT4_I2_I1
+.sym 10623 count[19]
+.sym 10624 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O_SB_LUT4_I1_O
+.sym 10625 SPI.C1.SCLKSTATE[1]
+.sym 10626 SPI.C1.SCLKSTATE[0]
+.sym 10629 count[19]
+.sym 10630 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 10631 SPI.C1.SCLKSTATE[1]
+.sym 10632 SPI.C1.SCLKSTATE[0]
+.sym 10633 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 10634 SPI.C0.clk$2
+.sym 10635 $false
+.sym 10637 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O
+.sym 10728 $false
+.sym 10729 $false
+.sym 10730 SPI.C1.SCLKSTATE[1]
+.sym 10731 count[19]
+.sym 10746 SPI.C1.SCLKSTATE[0]
+.sym 10747 SPI.C1.SCLKSTATE[1]
+.sym 10748 SPI.C1.done
+.sym 10749 SPI.C0.transmit
+.sym 10756 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 10757 SPI.C0.clk$2
+.sym 10758 genStart.RST$2
+.sym 10759 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 10760 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2
+.sym 10761 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 10762 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I3
+.sym 10763 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3
+.sym 10764 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0
+.sym 10765 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0
+.sym 10766 SPI.C0.STATE[4]
+.sym 10845 $false
+.sym 10846 SPI.C0.STATE[2]
+.sym 10847 SPI.C0.STATE[1]
+.sym 10848 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 10863 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 10864 SPI.C0.STATE[2]
+.sym 10865 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 10866 SPI.C0.transmit
+.sym 10879 SPI.C0.transmit_SB_DFFESR_Q_E
+.sym 10880 SPI.C0.clk$2
+.sym 10881 genStart.RST$2
+.sym 10882 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.sym 10883 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.sym 10884 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0
+.sym 10885 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 10886 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 10887 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 10888 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 10889 SPI.C0.txdata[13]
+.sym 10962 count[19]
+.sym 10963 SPI.C0.STATE[2]
+.sym 10964 SPI.C0.STATE[6]
+.sym 10965 SPI.C1.done
+.sym 10968 SPI.C0.STATE[5]
+.sym 10969 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_I0_SB_LUT4_I1_O
+.sym 10970 SPI.C0.STATE[1]
+.sym 10971 SPI.C1.done
+.sym 10974 $false
+.sym 10975 $false
+.sym 10976 count[19]
+.sym 10977 SPI.C0.STATE_SB_DFF_Q_1_D_SB_LUT4_O_I3
+.sym 10980 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 10981 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 10982 SPI.C0.STATE[6]
+.sym 10983 count[19]
+.sym 10998 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0
+.sym 10999 SPI.C0.STATE[1]
+.sym 11000 count[19]
+.sym 11001 SPI.C1.done
+.sym 11002 $true
+.sym 11003 SPI.C0.clk$2
+.sym 11004 $false
+.sym 11005 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 11006 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.sym 11007 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 11008 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 11009 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.sym 11010 SPI.C0.txdata[12]
+.sym 11011 SPI.C0.txdata[15]
+.sym 11012 SPI.C0.txdata[9]
+.sym 11079 $false
+.sym 11080 count[19]
+.sym 11081 SPI.C0.STATE[6]
+.sym 11082 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 11121 $false
+.sym 11122 $false
+.sym 11123 SPI.C0.register_select
+.sym 11124 SPI.C1.done
+.sym 11125 SPI.C0.register_select_SB_DFFESR_Q_E
+.sym 11126 SPI.C0.clk$2
+.sym 11127 genStart.RST$2
+.sym 11130 $true$2
+.sym 11134 SPI.C0.txdata[14]
+.sym 11202 SPI.C1.rx_shift_register[0]
+.sym 11203 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11204 SPI.C1.rx_shift_register[1]
+.sym 11205 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11220 SPI.C1.rx_shift_register[1]
+.sym 11221 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11222 SPI.C1.rx_shift_register[2]
+.sym 11223 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11238 SDI$2
+.sym 11239 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11240 SPI.C1.rx_shift_register[0]
+.sym 11241 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11248 SPI.C1.done_SB_DFFESR_Q_E
+.sym 11249 SPI.C0.clk$2
+.sym 11250 genStart.RST$2
+.sym 11251 SPI.C0.x_axis_data[6]
+.sym 11253 SPI.C0.x_axis_data[5]
+.sym 11254 SPI.C0.x_axis_data[7]
+.sym 11331 SPI.C1.rx_shift_register[3]
+.sym 11332 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11333 SPI.C1.rx_shift_register[4]
+.sym 11334 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11337 SPI.C1.rx_shift_register[2]
+.sym 11338 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11339 SPI.C1.rx_shift_register[3]
+.sym 11340 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11349 SPI.C1.rx_shift_register[6]
+.sym 11350 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11351 SPI.C1.rx_shift_register[7]
+.sym 11352 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11355 SPI.C1.rx_shift_register[4]
+.sym 11356 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11357 SPI.C1.rx_shift_register[5]
+.sym 11358 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11361 SPI.C1.rx_shift_register[5]
+.sym 11362 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_1_O
+.sym 11363 SPI.C1.rx_shift_register[6]
+.sym 11364 SPI.C1.RxSTATE_SB_DFFESR_Q_1_D_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_I2_O
+.sym 11371 SPI.C1.done_SB_DFFESR_Q_E
+.sym 11372 SPI.C0.clk$2
+.sym 11373 genStart.RST$2
+.sym 11374 SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.sym 11375 SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.sym 11376 SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 11377 SPI.C1.tx_shift_register[12]
+.sym 11378 SPI.C1.tx_shift_register[14]
+.sym 11379 SPI.C1.tx_shift_register[13]
+.sym 11448 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 11449 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 11450 SPI.C1.tx_shift_register[3]
+.sym 11451 SPI.C1.tx_shift_register[4]
+.sym 11454 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 11455 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 11456 SPI.C1.tx_shift_register[2]
+.sym 11457 SPI.C1.tx_shift_register[3]
+.sym 11460 SPI.C1.tx_shift_register_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.sym 11461 SPI.C0.txdata[4]
+.sym 11462 SPI.C1.TxSTATE[0]
+.sym 11463 SPI.C1.TxSTATE[1]
+.sym 11472 SPI.C1.tx_shift_register_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.sym 11473 SPI.C0.txdata[3]
+.sym 11474 SPI.C1.TxSTATE[0]
+.sym 11475 SPI.C1.TxSTATE[1]
+.sym 11494 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 11495 SPI.C0.clk$2
+.sym 11496 genStart.RST$2
+.sym 11500 SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.sym 11501 SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.sym 11503 SPI.C1.tx_shift_register[6]
+.sym 11504 SPI.C1.tx_shift_register[5]
+.sym 11571 $false
+.sym 11572 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 11573 SPI.C1.tx_shift_register[0]
+.sym 11574 SPI.C1.tx_shift_register[1]
+.sym 11589 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 11590 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 11591 SPI.C1.tx_shift_register[1]
+.sym 11592 SPI.C1.tx_shift_register[2]
+.sym 11595 SPI.C1.TxSTATE[0]
+.sym 11596 SPI.C1.TxSTATE[1]
+.sym 11597 SPI.C1.tx_shift_register_SB_DFFESR_Q_14_D_SB_LUT4_O_I2
+.sym 11598 SPI.C0.txdata[1]
+.sym 11607 SPI.C1.tx_shift_register_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.sym 11608 SPI.C0.txdata[2]
+.sym 11609 SPI.C1.TxSTATE[0]
+.sym 11610 SPI.C1.TxSTATE[1]
+.sym 11613 SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.sym 11614 SPI.C1.tx_shift_register[0]
+.sym 11615 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 11616 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 11617 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 11618 SPI.C0.clk$2
+.sym 11619 genStart.RST$2
+.sym 11620 count_SB_DFFE_Q_D[0]
+.sym 11621 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_4_I1
+.sym 11622 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_6_I1
+.sym 11623 count_SB_DFFE_Q_D_SB_CARRY_CI_I1
+.sym 11624 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_5_I1
+.sym 11625 count[0]
+.sym 11743 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_7_I1
+.sym 11744 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_22_I1
+.sym 11745 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_2_I1
+.sym 11746 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_3_I1
+.sym 11747 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 11748 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_1_I1
+.sym 11749 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_21_I1
+.sym 11750 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 11779 $true
+.sym 11816 count[0]$2
+.sym 11817 $false
+.sym 11818 count[0]
+.sym 11819 $false
+.sym 11820 $false
+.sym 11822 count_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 11824 $false
+.sym 11825 count[1]
+.sym 11828 count_SB_DFFE_Q_D_SB_LUT4_O_I3[3]
+.sym 11829 $false
+.sym 11830 $false
+.sym 11831 count[2]
+.sym 11832 count_SB_DFFE_Q_D_SB_LUT4_O_I3[2]
+.sym 11834 count_SB_DFFE_Q_D_SB_LUT4_O_I3[4]
+.sym 11835 $false
+.sym 11836 $false
+.sym 11837 count[3]
+.sym 11838 count_SB_DFFE_Q_D_SB_LUT4_O_I3[3]
+.sym 11840 count_SB_DFFE_Q_D_SB_LUT4_O_I3[5]
+.sym 11841 $false
+.sym 11842 $false
+.sym 11843 count[4]
+.sym 11844 count_SB_DFFE_Q_D_SB_LUT4_O_I3[4]
+.sym 11846 count_SB_DFFE_Q_D_SB_LUT4_O_I3[6]
+.sym 11847 $false
+.sym 11848 $false
+.sym 11849 count[5]
+.sym 11850 count_SB_DFFE_Q_D_SB_LUT4_O_I3[5]
+.sym 11852 count_SB_DFFE_Q_D_SB_LUT4_O_I3[7]
+.sym 11853 $false
+.sym 11854 $false
+.sym 11855 count[6]
+.sym 11856 count_SB_DFFE_Q_D_SB_LUT4_O_I3[6]
+.sym 11858 count_SB_DFFE_Q_D_SB_LUT4_O_I3[8]
+.sym 11859 $false
+.sym 11860 $false
+.sym 11861 count[7]
+.sym 11862 count_SB_DFFE_Q_D_SB_LUT4_O_I3[7]
+.sym 11863 count_SB_DFFE_Q_E$2
+.sym 11864 clk_in$2$2
+.sym 11865 $false
+.sym 11866 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 11867 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_19_I1
+.sym 11868 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_13_I1
+.sym 11869 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 11870 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_18_I1
+.sym 11871 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_I1
+.sym 11872 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 11873 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_20_I1
+.sym 11902 count_SB_DFFE_Q_D_SB_LUT4_O_I3[8]
+.sym 11939 count_SB_DFFE_Q_D_SB_LUT4_O_I3[9]
+.sym 11940 $false
+.sym 11941 $false
+.sym 11942 count[8]
+.sym 11943 count_SB_DFFE_Q_D_SB_LUT4_O_I3[8]
+.sym 11945 count_SB_DFFE_Q_D_SB_LUT4_O_I3[10]
+.sym 11946 $false
+.sym 11947 $false
+.sym 11948 count[9]
+.sym 11949 count_SB_DFFE_Q_D_SB_LUT4_O_I3[9]
+.sym 11951 count_SB_DFFE_Q_D_SB_LUT4_O_I3[11]
+.sym 11952 $false
+.sym 11953 $false
+.sym 11954 count[10]
+.sym 11955 count_SB_DFFE_Q_D_SB_LUT4_O_I3[10]
+.sym 11957 count_SB_DFFE_Q_D_SB_LUT4_O_I3[12]
+.sym 11958 $false
+.sym 11959 $false
+.sym 11960 count[11]
+.sym 11961 count_SB_DFFE_Q_D_SB_LUT4_O_I3[11]
+.sym 11963 count_SB_DFFE_Q_D_SB_LUT4_O_I3[13]
+.sym 11964 $false
+.sym 11965 $false
+.sym 11966 count[12]
+.sym 11967 count_SB_DFFE_Q_D_SB_LUT4_O_I3[12]
+.sym 11969 count_SB_DFFE_Q_D_SB_LUT4_O_I3[14]
+.sym 11970 $false
+.sym 11971 $false
+.sym 11972 count[13]
+.sym 11973 count_SB_DFFE_Q_D_SB_LUT4_O_I3[13]
+.sym 11975 count_SB_DFFE_Q_D_SB_LUT4_O_I3[15]
+.sym 11976 $false
+.sym 11977 $false
+.sym 11978 count[14]
+.sym 11979 count_SB_DFFE_Q_D_SB_LUT4_O_I3[14]
+.sym 11981 count_SB_DFFE_Q_D_SB_LUT4_O_I3[16]
+.sym 11982 $false
+.sym 11983 $false
+.sym 11984 count[15]
+.sym 11985 count_SB_DFFE_Q_D_SB_LUT4_O_I3[15]
+.sym 11986 count_SB_DFFE_Q_E$2
+.sym 11987 clk_in$2$2
+.sym 11988 $false
+.sym 11989 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 11990 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_I1
+.sym 11991 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 11992 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_17_I1
+.sym 11993 count_SB_DFFE_Q_E_SB_LUT4_O_I3
+.sym 11994 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_16_I1
+.sym 11995 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_8_I1
+.sym 11996 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 12025 count_SB_DFFE_Q_D_SB_LUT4_O_I3[16]
+.sym 12062 count_SB_DFFE_Q_D_SB_LUT4_O_I3[17]
+.sym 12063 $false
+.sym 12064 $false
+.sym 12065 count[16]
+.sym 12066 count_SB_DFFE_Q_D_SB_LUT4_O_I3[16]
+.sym 12068 count_SB_DFFE_Q_D_SB_LUT4_O_I3[18]
+.sym 12069 $false
+.sym 12070 $false
+.sym 12071 count[17]
+.sym 12072 count_SB_DFFE_Q_D_SB_LUT4_O_I3[17]
+.sym 12074 count_SB_DFFE_Q_D_SB_LUT4_O_I3[19]
+.sym 12075 $false
+.sym 12076 $false
+.sym 12077 count[18]
+.sym 12078 count_SB_DFFE_Q_D_SB_LUT4_O_I3[18]
+.sym 12080 count_SB_DFFE_Q_D_SB_LUT4_O_I3[20]
+.sym 12081 $false
+.sym 12082 $false
+.sym 12083 count[19]
+.sym 12084 count_SB_DFFE_Q_D_SB_LUT4_O_I3[19]
+.sym 12086 count_SB_DFFE_Q_D_SB_LUT4_O_I3[21]
+.sym 12087 $false
+.sym 12088 $false
+.sym 12089 count[20]
+.sym 12090 count_SB_DFFE_Q_D_SB_LUT4_O_I3[20]
+.sym 12092 count_SB_DFFE_Q_D_SB_LUT4_O_I3[22]
+.sym 12093 $false
+.sym 12094 $false
+.sym 12095 count[21]
+.sym 12096 count_SB_DFFE_Q_D_SB_LUT4_O_I3[21]
+.sym 12098 count_SB_DFFE_Q_D_SB_LUT4_O_I3[23]
+.sym 12099 $false
+.sym 12100 $false
+.sym 12101 count[22]
+.sym 12102 count_SB_DFFE_Q_D_SB_LUT4_O_I3[22]
+.sym 12104 count_SB_DFFE_Q_D_SB_LUT4_O_I3[24]
+.sym 12105 $false
+.sym 12106 $false
+.sym 12107 count[23]
+.sym 12108 count_SB_DFFE_Q_D_SB_LUT4_O_I3[23]
+.sym 12109 count_SB_DFFE_Q_E$2
+.sym 12110 clk_in$2$2
+.sym 12111 $false
+.sym 12148 count_SB_DFFE_Q_D_SB_LUT4_O_I3[24]
+.sym 12185 count_SB_DFFE_Q_D_SB_LUT4_O_I3[25]
+.sym 12186 $false
+.sym 12187 $false
+.sym 12188 count[24]
+.sym 12189 count_SB_DFFE_Q_D_SB_LUT4_O_I3[24]
+.sym 12191 count_SB_DFFE_Q_D_SB_LUT4_O_I3[26]
+.sym 12192 $false
+.sym 12193 $false
+.sym 12194 count[25]
+.sym 12195 count_SB_DFFE_Q_D_SB_LUT4_O_I3[25]
+.sym 12198 $false
+.sym 12199 $false
+.sym 12200 count[26]
+.sym 12201 count_SB_DFFE_Q_D_SB_LUT4_O_I3[26]
+.sym 12232 count_SB_DFFE_Q_E$2
+.sym 12233 clk_in$2$2
+.sym 12234 $false
+.sym 12309 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O
+.sym 12335 SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
+.sym 12336 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 12338 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 12339 SPI.C1.clk_count[7]
+.sym 12340 SPI.C1.clk_count[6]
+.sym 12372 $true
+.sym 12409 SPI.C1.clk_count[0]$2
+.sym 12410 $false
+.sym 12411 SPI.C1.clk_count[0]
+.sym 12412 $false
+.sym 12413 $false
+.sym 12415 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[2]
+.sym 12417 $false
+.sym 12418 SPI.C1.clk_count[1]
+.sym 12421 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[3]
+.sym 12422 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12423 $false
+.sym 12424 SPI.C1.clk_count[2]
+.sym 12425 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[2]
+.sym 12427 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[4]
+.sym 12428 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12429 $false
+.sym 12430 SPI.C1.clk_count[3]
+.sym 12431 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[3]
+.sym 12433 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[5]
+.sym 12434 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12435 $false
+.sym 12436 SPI.C1.clk_count[4]
+.sym 12437 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[4]
+.sym 12439 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[6]
+.sym 12440 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12441 $false
+.sym 12442 SPI.C1.clk_count[5]
+.sym 12443 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[5]
+.sym 12445 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[7]
+.sym 12446 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12447 $false
+.sym 12448 SPI.C1.clk_count[6]
+.sym 12449 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[6]
+.sym 12452 $false
+.sym 12453 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12454 SPI.C1.clk_count[7]
+.sym 12455 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3[7]
+.sym 12573 SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2_SB_LUT4_O_I0
+.sym 12574 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I1_SB_LUT4_I2_O
+.sym 12575 SPI.C1.done
+.sym 12576 SPI.C1.clk_count[1]
+.sym 12579 SPI.C1.clk_count[3]
+.sym 12580 SPI.C1.clk_count[2]
+.sym 12581 SPI.C1.clk_count[1]
+.sym 12582 SPI.C1.clk_count[0]
+.sym 12585 $false
+.sym 12586 $false
+.sym 12587 SPI.C1.clk_count[1]
+.sym 12588 SPI.C1.clk_count[0]
+.sym 12591 $false
+.sym 12592 $false
+.sym 12593 SPI.C1.clk_count[2]
+.sym 12594 SPI.C1.done
+.sym 12597 $false
+.sym 12598 $false
+.sym 12599 SPI.C1.clk_count[4]
+.sym 12600 SPI.C1.done
+.sym 12603 $false
+.sym 12604 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 12605 SPI.C1.clk_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I2
+.sym 12606 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 12609 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 12610 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 12611 SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I2
+.sym 12612 SPI.C1.clk_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I3
+.sym 12615 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 12616 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 12617 SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.sym 12618 SPI.C1.clk_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 12619 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 12620 SPI.C0.clk$2
+.sym 12621 genStart.RST$2
+.sym 12714 $false
+.sym 12715 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 12716 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2
+.sym 12717 SPI.C1.clk_edge_buffer
+.sym 12742 SPI.C1.clk_edge_buffer_SB_DFFE_Q_E
+.sym 12743 SPI.C0.clk$2
+.sym 12744 $false
+.sym 12825 $false
+.sym 12826 $false
+.sym 12827 count[19]
+.sym 12828 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.sym 12868 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 12869 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1
+.sym 12870 SPI.C0.STATE_SB_DFF_Q_3_D_SB_LUT4_O_I3
+.sym 12871 SPI.C0.CONFIGUREsel[0]
+.sym 12872 SPI.C0.CONFIGUREsel[1]
+.sym 12874 SPI.C0.CONFIGUREsel[2]
+.sym 12875 SPI.C0.STATE[0]
+.sym 12942 $false
+.sym 12943 $false
+.sym 12944 SPI.C0.STATE[0]
+.sym 12945 SPI.C0.done_configure
+.sym 12948 $false
+.sym 12949 SPI.C0.done_configure
+.sym 12950 SPI.C0.STATE[5]
+.sym 12951 SPI.C0.sample_done
+.sym 12954 $false
+.sym 12955 SPI.C0.STATE[4]
+.sym 12956 SPI.C0.CONFIGUREsel[1]
+.sym 12957 SPI.C0.CONFIGUREsel[2]
+.sym 12960 SPI.C0.STATE[0]
+.sym 12961 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 12962 SPI.C0.STATE[5]
+.sym 12963 SPI.C0.sample_done
+.sym 12966 $false
+.sym 12967 SPI.C0.CONFIGUREsel[0]
+.sym 12968 SPI.C0.CONFIGUREsel[1]
+.sym 12969 SPI.C0.CONFIGUREsel[2]
+.sym 12972 $false
+.sym 12973 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 12974 count[19]
+.sym 12975 SPI.C0.CONFIGUREsel[0]
+.sym 12978 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 12979 SPI.C0.STATE[4]
+.sym 12980 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3
+.sym 12981 SPI.C0.transmit
+.sym 12984 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0
+.sym 12985 count[19]
+.sym 12986 SPI.C0.done_configure
+.sym 12987 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I3
+.sym 12988 $true
+.sym 12989 SPI.C0.clk$2
+.sym 12990 $false
+.sym 12991 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 12992 SPI.C0.finish_SB_LUT4_I3_O
+.sym 12993 SPI.C0.sample_done_SB_DFFESR_Q_E
+.sym 12994 SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 12995 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I1
+.sym 12996 SPI.C0.finish_SB_LUT4_I0_I3
+.sym 12997 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.sym 12998 SPI.C0.sample_done
+.sym 13065 SPI.C0.STATE[0]
+.sym 13066 SPI.C0.STATE[5]
+.sym 13067 SPI.C0.STATE[6]
+.sym 13068 SPI.C0.STATE[4]
+.sym 13071 SPI.C0.txdata[13]
+.sym 13072 SPI.C0.STATE[4]
+.sym 13073 SPI.C0.CONFIGUREsel[1]
+.sym 13074 SPI.C0.CONFIGUREsel[2]
+.sym 13077 count[19]
+.sym 13078 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 13079 SPI.C0.STATE[4]
+.sym 13080 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I3
+.sym 13083 $false
+.sym 13084 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 13085 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 13086 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 13089 SPI.C0.STATE[0]
+.sym 13090 SPI.C0.done_configure
+.sym 13091 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 13092 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 13095 $false
+.sym 13096 $false
+.sym 13097 SPI.C0.STATE[0]
+.sym 13098 SPI.C0.done_configure
+.sym 13101 $false
+.sym 13102 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 13103 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 13104 SPI.C0.STATE[5]
+.sym 13107 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 13108 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 13109 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2
+.sym 13110 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I3
+.sym 13111 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 13112 SPI.C0.clk$2
+.sym 13113 genStart.RST$2
+.sym 13114 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 13115 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 13116 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.sym 13117 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 13118 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 13119 SPI.C0.finish_SB_DFFESR_Q_E
+.sym 13120 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 13121 SPI.C0.finish
+.sym 13188 SPI.C0.txdata[15]
+.sym 13189 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 13190 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 13191 SPI.C0.STATE[5]
+.sym 13194 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 13195 SPI.C0.txdata[12]
+.sym 13196 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 13197 SPI.C0.STATE[5]
+.sym 13200 $false
+.sym 13201 SPI.C0.STATE[6]
+.sym 13202 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 13203 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 13206 SPI.C0.txdata[9]
+.sym 13207 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 13208 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.sym 13209 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 13212 SPI.C0.txdata[9]
+.sym 13213 SPI.C0.STATE[5]
+.sym 13214 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 13215 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 13218 $false
+.sym 13219 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 13220 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I2
+.sym 13221 SPI.C0.txdata_SB_DFFESR_Q_3_D_SB_LUT4_O_I3
+.sym 13224 $false
+.sym 13225 $false
+.sym 13226 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 13227 SPI.C0.txdata_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 13230 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 13231 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1
+.sym 13232 SPI.C0.txdata[9]
+.sym 13233 SPI.C1.done
+.sym 13234 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 13235 SPI.C0.clk$2
+.sym 13236 genStart.RST$2
+.sym 13237 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 13238 SPI.C0.x_axis_data_SB_DFFESR_Q_4_E
+.sym 13239 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.sym 13240 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1
+.sym 13241 SPI.C0.z_axis_data_SB_DFFESR_Q_4_E
+.sym 13242 SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2
+.sym 13243 SPI.C0.txdata[8]
+.sym 13244 SPI.C0.txdata[3]
+.sym 13323 $false
+.sym 13324 $false
+.sym 13325 $false
+.sym 13326 $false
+.sym 13347 $false
+.sym 13348 $false
+.sym 13349 SPI.C0.txdata[14]
+.sym 13350 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 13357 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 13358 SPI.C0.clk$2
+.sym 13359 genStart.RST$2
+.sym 13361 SPI.C0.z_axis_data[5]
+.sym 13362 SPI.C0.z_axis_data[7]
+.sym 13367 SPI.C0.z_axis_data[6]
+.sym 13434 SPI.C1.rx_shift_register[6]
+.sym 13435 $false
+.sym 13436 $false
+.sym 13437 $false
+.sym 13446 SPI.C1.rx_shift_register[5]
+.sym 13447 $false
+.sym 13448 $false
+.sym 13449 $false
+.sym 13452 SPI.C1.rx_shift_register[7]
+.sym 13453 $false
+.sym 13454 $false
+.sym 13455 $false
+.sym 13480 SPI.C0.x_axis_data_SB_DFFESR_Q_4_E
+.sym 13481 SPI.C0.clk$2
+.sym 13482 genStart.RST$2
+.sym 13483 SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 13484 SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 13485 SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.sym 13486 SPI.C1.tx_shift_register[8]
+.sym 13487 SPI.C1.tx_shift_register[7]
+.sym 13488 SPI.C1.tx_shift_register[9]
+.sym 13557 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 13558 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 13559 SPI.C1.tx_shift_register[13]
+.sym 13560 SPI.C1.tx_shift_register[14]
+.sym 13563 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 13564 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 13565 SPI.C1.tx_shift_register[11]
+.sym 13566 SPI.C1.tx_shift_register[12]
+.sym 13569 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 13570 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 13571 SPI.C1.tx_shift_register[12]
+.sym 13572 SPI.C1.tx_shift_register[13]
+.sym 13575 SPI.C1.tx_shift_register_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.sym 13576 SPI.C0.txdata[12]
+.sym 13577 SPI.C1.TxSTATE[0]
+.sym 13578 SPI.C1.TxSTATE[1]
+.sym 13581 SPI.C1.tx_shift_register_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.sym 13582 SPI.C0.txdata[14]
+.sym 13583 SPI.C1.TxSTATE[0]
+.sym 13584 SPI.C1.TxSTATE[1]
+.sym 13587 SPI.C1.tx_shift_register_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 13588 SPI.C0.txdata[13]
+.sym 13589 SPI.C1.TxSTATE[0]
+.sym 13590 SPI.C1.TxSTATE[1]
+.sym 13603 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 13604 SPI.C0.clk$2
+.sym 13605 genStart.RST$2
+.sym 13606 SPI.C1.tx_shift_register_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.sym 13608 SPI.C0.txdata[7]
+.sym 13609 SPI.C0.txdata[5]
+.sym 13612 SPI.C0.txdata[0]
+.sym 13698 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 13699 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 13700 SPI.C1.tx_shift_register[4]
+.sym 13701 SPI.C1.tx_shift_register[5]
+.sym 13704 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 13705 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 13706 SPI.C1.tx_shift_register[5]
+.sym 13707 SPI.C1.tx_shift_register[6]
+.sym 13716 SPI.C1.tx_shift_register_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.sym 13717 SPI.C0.txdata[6]
+.sym 13718 SPI.C1.TxSTATE[0]
+.sym 13719 SPI.C1.TxSTATE[1]
+.sym 13722 SPI.C1.tx_shift_register_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.sym 13723 SPI.C0.txdata[5]
+.sym 13724 SPI.C1.TxSTATE[0]
+.sym 13725 SPI.C1.TxSTATE[1]
+.sym 13726 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 13727 SPI.C0.clk$2
+.sym 13728 genStart.RST$2
+.sym 13803 $false
+.sym 13804 $false
+.sym 13805 $false
+.sym 13806 count[0]
+.sym 13809 $false
+.sym 13810 $false
+.sym 13811 $false
+.sym 13812 count[5]
+.sym 13815 $false
+.sym 13816 $false
+.sym 13817 $false
+.sym 13818 count[3]
+.sym 13821 $false
+.sym 13822 $false
+.sym 13823 $false
+.sym 13824 count[1]
+.sym 13827 $false
+.sym 13828 $false
+.sym 13829 $false
+.sym 13830 count[4]
+.sym 13833 count_SB_DFFE_Q_D[0]
+.sym 13834 $false
+.sym 13835 $false
+.sym 13836 $false
+.sym 13849 count_SB_DFFE_Q_E$2
+.sym 13850 clk_in$2$2
+.sym 13851 $false
+.sym 13926 $false
+.sym 13927 $false
+.sym 13928 $false
+.sym 13929 count[2]
+.sym 13932 $false
+.sym 13933 $false
+.sym 13934 $false
+.sym 13935 count[11]
+.sym 13938 $false
+.sym 13939 $false
+.sym 13940 $false
+.sym 13941 count[7]
+.sym 13944 $false
+.sym 13945 $false
+.sym 13946 $false
+.sym 13947 count[6]
+.sym 13950 count[19]
+.sym 13951 count[2]
+.sym 13952 count[1]
+.sym 13953 count[0]
+.sym 13956 $false
+.sym 13957 $false
+.sym 13958 $false
+.sym 13959 count[8]
+.sym 13962 $false
+.sym 13963 $false
+.sym 13964 $false
+.sym 13965 count[12]
+.sym 13968 count[7]
+.sym 13969 count[6]
+.sym 13970 count[5]
+.sym 13971 count[3]
+.sym 14049 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 14050 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 14051 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 14052 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 14055 $false
+.sym 14056 $false
+.sym 14057 $false
+.sym 14058 count[14]
+.sym 14061 $false
+.sym 14062 $false
+.sym 14063 $false
+.sym 14064 count[20]
+.sym 14067 count[15]
+.sym 14068 count[14]
+.sym 14069 count[13]
+.sym 14070 count[12]
+.sym 14073 $false
+.sym 14074 $false
+.sym 14075 $false
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+.sym 14079 $false
+.sym 14080 $false
+.sym 14081 $false
+.sym 14082 count[9]
+.sym 14085 count[11]
+.sym 14086 count[10]
+.sym 14087 count[8]
+.sym 14088 count[9]
+.sym 14091 $false
+.sym 14092 $false
+.sym 14093 $false
+.sym 14094 count[13]
+.sym 14101 count_SB_DFFE_Q_E_SB_LUT4_O_I2
+.sym 14102 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_15_I1
+.sym 14103 count_SB_DFFE_Q_E
+.sym 14104 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_11_I1
+.sym 14105 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_10_I1
+.sym 14172 count[22]
+.sym 14173 count[4]
+.sym 14174 count[26]
+.sym 14175 count[21]
+.sym 14178 $false
+.sym 14179 $false
+.sym 14180 $false
+.sym 14181 count[26]
+.sym 14184 $false
+.sym 14185 count[25]
+.sym 14186 count[24]
+.sym 14187 count[23]
+.sym 14190 $false
+.sym 14191 $false
+.sym 14192 $false
+.sym 14193 count[16]
+.sym 14196 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 14197 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 14198 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 14199 count_SB_DFFE_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 14202 $false
+.sym 14203 $false
+.sym 14204 $false
+.sym 14205 count[17]
+.sym 14208 $false
+.sym 14209 $false
+.sym 14210 $false
+.sym 14211 count[25]
+.sym 14214 count[20]
+.sym 14215 count[16]
+.sym 14216 count[17]
+.sym 14217 count[18]
+.sym 14418 SPI.C0.clk
+.sym 14519 $false
+.sym 14520 $false
+.sym 14521 SPI.C1.clk_count[6]
+.sym 14522 SPI.C1.done
+.sym 14525 SPI.C1.clk_count[7]
+.sym 14526 SPI.C1.clk_count[6]
+.sym 14527 SPI.C1.clk_count[5]
+.sym 14528 SPI.C1.clk_count[4]
+.sym 14537 $false
+.sym 14538 $false
+.sym 14539 SPI.C1.clk_count[7]
+.sym 14540 SPI.C1.done
+.sym 14543 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 14544 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 14545 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 14546 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 14549 SPI.C1.clk_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 14550 SPI.C1.clk_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 14551 SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I2
+.sym 14552 SPI.C1.clk_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I3
+.sym 14565 SPI.C1.SCLKSTATE_SB_DFFESR_Q_E
+.sym 14566 SPI.C0.clk$2
+.sym 14567 genStart.RST$2
+.sym 14731 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 14732 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 14733 SPI.C0.prevstart[3]
+.sym 14734 SPI.C0.prevstart[2]
+.sym 14737 SPI.C0.prevstart[1]
+.sym 14738 SPI.C0.prevstart[0]
+.sym 14857 SS_SB_LUT4_O_I3_SB_DFFE_Q_E
+.sym 14860 SS_SB_LUT4_O_I3
+.sym 14977 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1
+.sym 14979 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2
+.sym 14982 SPI.C0.STATE[2]
+.sym 14984 SPI.C0.STATE[3]
+.sym 15051 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I0
+.sym 15052 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 15053 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 15054 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2
+.sym 15057 count[19]
+.sym 15058 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I1
+.sym 15059 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 15060 SPI.C0.STATE[5]
+.sym 15063 $false
+.sym 15064 SPI.C0.sample_done
+.sym 15065 SPI.C0.STATE[5]
+.sym 15066 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 15069 $false
+.sym 15070 count[19]
+.sym 15071 SPI.C0.CONFIGUREsel[0]
+.sym 15072 SPI.C0.STATE[4]
+.sym 15075 count[19]
+.sym 15076 SPI.C0.CONFIGUREsel[1]
+.sym 15077 SPI.C0.CONFIGUREsel[2]
+.sym 15078 SPI.C0.STATE[4]
+.sym 15087 count[19]
+.sym 15088 SPI.C0.STATE[4]
+.sym 15089 SPI.C0.CONFIGUREsel[0]
+.sym 15090 SPI.C0.CONFIGUREsel[2]
+.sym 15093 $false
+.sym 15094 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I1
+.sym 15095 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2
+.sym 15096 genStart.CLKOUT
+.sym 15097 $true
+.sym 15098 SPI.C0.clk$2
+.sym 15099 $false
+.sym 15100 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0
+.sym 15101 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 15102 SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 15103 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 15104 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I0
+.sym 15105 SPI.C0.DATA[2]
+.sym 15106 SPI.C0.DATA[1]
+.sym 15107 SPI.C0.DATA[0]
+.sym 15174 SPI.C0.transmit
+.sym 15175 SPI.C0.STATE[0]
+.sym 15176 SPI.C0.STATE[5]
+.sym 15177 SPI.C0.transmit_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 15180 $false
+.sym 15181 genStart.CLKOUT
+.sym 15182 SPI.C0.sample_done
+.sym 15183 SPI.C0.finish
+.sym 15186 $false
+.sym 15187 SPI.C0.STATE[0]
+.sym 15188 SPI.C0.STATE[6]
+.sym 15189 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 15192 $false
+.sym 15193 SPI.C0.STATE[6]
+.sym 15194 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 15195 SPI.C0.finish_SB_LUT4_I0_I3
+.sym 15198 $false
+.sym 15199 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 15200 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 15201 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 15204 $false
+.sym 15205 SPI.C0.STATE[0]
+.sym 15206 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 15207 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 15210 SPI.C0.STATE_SB_DFF_Q_2_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 15211 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 15212 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 15213 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 15216 SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 15217 SPI.C0.sample_done
+.sym 15218 SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 15219 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2
+.sym 15220 SPI.C0.sample_done_SB_DFFESR_Q_E
+.sym 15221 SPI.C0.clk$2
+.sym 15222 genStart.RST$2
+.sym 15223 SPI.C0.hold_count_SB_DFFESR_Q_E
+.sym 15224 SPI.C0.z_axis_data_SB_DFFESR_Q_E
+.sym 15225 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 15226 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I2
+.sym 15227 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1
+.sym 15228 SPI.C0.x_axis_data_SB_DFFESR_Q_E
+.sym 15229 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 15230 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 15297 $false
+.sym 15298 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 15299 SPI.C0.STATE[4]
+.sym 15300 SPI.C0.CONFIGUREsel[2]
+.sym 15303 $false
+.sym 15304 SPI.C0.STATE[6]
+.sym 15305 SPI.C1.done
+.sym 15306 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 15309 $false
+.sym 15310 SPI.C0.finish_SB_LUT4_I0_I3
+.sym 15311 SPI.C0.STATE[4]
+.sym 15312 SPI.C0.CONFIGUREsel[1]
+.sym 15315 $false
+.sym 15316 $false
+.sym 15317 SPI.C0.CONFIGUREsel[1]
+.sym 15318 SPI.C0.STATE[4]
+.sym 15321 SPI.C0.finish
+.sym 15322 SPI.C0.STATE[4]
+.sym 15323 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 15324 SPI.C0.finish_SB_LUT4_I0_I3
+.sym 15327 $false
+.sym 15328 count[19]
+.sym 15329 SPI.C0.STATE[0]
+.sym 15330 SPI.C0.STATE[4]
+.sym 15333 SPI.C0.finish_SB_LUT4_I0_I2
+.sym 15334 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 15335 SPI.C0.STATE_SB_DFF_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 15336 SPI.C0.register_select
+.sym 15339 $false
+.sym 15340 $false
+.sym 15341 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 15342 SPI.C0.finish_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 15343 SPI.C0.finish_SB_DFFESR_Q_E
+.sym 15344 SPI.C0.clk$2
+.sym 15345 genStart.RST$2
+.sym 15346 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.sym 15348 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 15349 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 15350 SPI.C0.txdata[10]
+.sym 15352 SPI.C0.txdata[11]
+.sym 15420 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.sym 15421 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1
+.sym 15422 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 15423 SPI.C0.STATE[5]
+.sym 15426 count[19]
+.sym 15427 SPI.C0.STATE[6]
+.sym 15428 SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2
+.sym 15429 SPI.C0.DATA[0]
+.sym 15432 $false
+.sym 15433 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1
+.sym 15434 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_O
+.sym 15435 SPI.C0.STATE[5]
+.sym 15438 $false
+.sym 15439 SPI.C0.STATE[6]
+.sym 15440 SPI.C0.STATE_SB_DFF_Q_D_SB_LUT4_O_I0
+.sym 15441 SPI.C1.done
+.sym 15444 count[19]
+.sym 15445 SPI.C0.STATE[6]
+.sym 15446 SPI.C0.z_axis_data_SB_DFFESR_Q_4_E_SB_LUT4_O_I2
+.sym 15447 SPI.C0.DATA[1]
+.sym 15450 $false
+.sym 15451 $false
+.sym 15452 SPI.C1.done
+.sym 15453 SPI.C0.register_select
+.sym 15456 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 15457 SPI.C0.txdata[8]
+.sym 15458 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.sym 15459 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3
+.sym 15462 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 15463 SPI.C0.txdata[3]
+.sym 15464 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.sym 15465 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.sym 15466 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 15467 SPI.C0.clk$2
+.sym 15468 genStart.RST$2
+.sym 15472 genStart.RST
+.sym 15549 SPI.C1.rx_shift_register[5]
+.sym 15550 $false
+.sym 15551 $false
+.sym 15552 $false
+.sym 15555 SPI.C1.rx_shift_register[7]
+.sym 15556 $false
+.sym 15557 $false
+.sym 15558 $false
+.sym 15585 SPI.C1.rx_shift_register[6]
+.sym 15586 $false
+.sym 15587 $false
+.sym 15588 $false
+.sym 15589 SPI.C0.z_axis_data_SB_DFFESR_Q_4_E
+.sym 15590 SPI.C0.clk$2
+.sym 15591 genStart.RST$2
+.sym 15592 SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 15594 SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 15597 SPI.C1.tx_shift_register[11]
+.sym 15598 SPI.C1.tx_shift_register[10]
+.sym 15666 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 15667 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 15668 SPI.C1.tx_shift_register[8]
+.sym 15669 SPI.C1.tx_shift_register[9]
+.sym 15672 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 15673 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 15674 SPI.C1.tx_shift_register[7]
+.sym 15675 SPI.C1.tx_shift_register[8]
+.sym 15678 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 15679 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 15680 SPI.C1.tx_shift_register[6]
+.sym 15681 SPI.C1.tx_shift_register[7]
+.sym 15684 SPI.C1.tx_shift_register_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 15685 SPI.C0.txdata[8]
+.sym 15686 SPI.C1.TxSTATE[0]
+.sym 15687 SPI.C1.TxSTATE[1]
+.sym 15690 SPI.C1.tx_shift_register_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.sym 15691 SPI.C0.txdata[7]
+.sym 15692 SPI.C1.TxSTATE[0]
+.sym 15693 SPI.C1.TxSTATE[1]
+.sym 15696 SPI.C1.tx_shift_register_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 15697 SPI.C0.txdata[9]
+.sym 15698 SPI.C1.TxSTATE[0]
+.sym 15699 SPI.C1.TxSTATE[1]
+.sym 15712 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 15713 SPI.C0.clk$2
+.sym 15714 genStart.RST$2
+.sym 15717 SPI.C1.TxSTATE[1]
+.sym 15789 $false
+.sym 15790 SPI.C0.txdata[0]
+.sym 15791 SPI.C1.TxSTATE[0]
+.sym 15792 SPI.C1.TxSTATE[1]
+.sym 15801 $false
+.sym 15802 $false
+.sym 15803 SPI.C0.txdata[7]
+.sym 15804 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 15807 $false
+.sym 15808 $false
+.sym 15809 SPI.C0.txdata[5]
+.sym 15810 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 15825 $false
+.sym 15826 $false
+.sym 15827 SPI.C0.txdata[0]
+.sym 15828 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_O
+.sym 15835 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 15836 SPI.C0.clk$2
+.sym 15837 genStart.RST$2
+.sym 15844 count[1]
+.sym 15874 $true
+.sym 15911 count_SB_DFFE_Q_D[0]$2
+.sym 15912 $false
+.sym 15913 count_SB_DFFE_Q_D[0]
+.sym 15914 $false
+.sym 15915 $false
+.sym 15917 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[2]
+.sym 15919 $false
+.sym 15920 count_SB_DFFE_Q_D_SB_CARRY_CI_I1
+.sym 15923 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[3]
+.sym 15925 $false
+.sym 15926 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_7_I1
+.sym 15929 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[4]
+.sym 15931 $false
+.sym 15932 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_6_I1
+.sym 15935 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[5]
+.sym 15937 $false
+.sym 15938 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_5_I1
+.sym 15941 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[6]
+.sym 15943 $false
+.sym 15944 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_4_I1
+.sym 15947 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[7]
+.sym 15949 $false
+.sym 15950 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_3_I1
+.sym 15953 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[8]
+.sym 15955 $true$2
+.sym 15956 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_2_I1
+.sym 15997 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[8]
+.sym 16034 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[9]
+.sym 16036 $true$2
+.sym 16037 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_1_I1
+.sym 16040 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[10]
+.sym 16042 $false
+.sym 16043 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_I1
+.sym 16046 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[11]
+.sym 16048 $true$2
+.sym 16049 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_23_I1
+.sym 16052 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[12]
+.sym 16054 $true$2
+.sym 16055 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_22_I1
+.sym 16058 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[13]
+.sym 16060 $false
+.sym 16061 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_21_I1
+.sym 16064 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[14]
+.sym 16066 $false
+.sym 16067 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_20_I1
+.sym 16070 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[15]
+.sym 16072 $false
+.sym 16073 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_19_I1
+.sym 16076 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[16]
+.sym 16078 $true$2
+.sym 16079 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_18_I1
+.sym 16120 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[16]
+.sym 16157 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[17]
+.sym 16159 $true$2
+.sym 16160 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_17_I1
+.sym 16163 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[18]
+.sym 16165 $true$2
+.sym 16166 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_16_I1
+.sym 16169 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[19]
+.sym 16171 $false
+.sym 16172 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_15_I1
+.sym 16175 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[20]
+.sym 16177 $true$2
+.sym 16178 genStart.RST$2
+.sym 16181 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[21]
+.sym 16183 $true$2
+.sym 16184 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_13_I1
+.sym 16187 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[22]
+.sym 16189 $false
+.sym 16190 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_12_I1
+.sym 16193 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[23]
+.sym 16195 $true$2
+.sym 16196 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_11_I1
+.sym 16199 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[24]
+.sym 16201 $false
+.sym 16202 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_10_I1
+.sym 16243 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[24]
+.sym 16280 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[25]
+.sym 16282 $false
+.sym 16283 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_9_I1
+.sym 16286 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI[26]
+.sym 16288 $false
+.sym 16289 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_8_I1
+.sym 16292 count_SB_DFFE_Q_E_SB_LUT4_O_I2$2
+.sym 16294 $false
+.sym 16295 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_I1
+.sym 16302 count_SB_DFFE_Q_E_SB_LUT4_O_I2$2
+.sym 16305 $false
+.sym 16306 $false
+.sym 16307 $false
+.sym 16308 count[18]
+.sym 16311 $false
+.sym 16312 $false
+.sym 16313 count_SB_DFFE_Q_E_SB_LUT4_O_I2
+.sym 16314 count_SB_DFFE_Q_E_SB_LUT4_O_I3
+.sym 16317 $false
+.sym 16318 $false
+.sym 16319 $false
+.sym 16320 count[22]
+.sym 16323 $false
+.sym 16324 $false
+.sym 16325 $false
+.sym 16326 count[23]
+.sym 16497 count_SB_DFFE_Q_E
+.sym 16847 SS$2
+.sym 16914 $false
+.sym 16915 SPI.C0.prevstart[1]
+.sym 16916 SPI.C0.prevstart[0]
+.sym 16917 genStart.CLKOUT
+.sym 16920 $false
+.sym 16921 $false
+.sym 16922 SPI.C0.prevstart[3]
+.sym 16923 SPI.C0.prevstart[2]
+.sym 16926 SPI.C0.prevstart[2]
+.sym 16927 $false
+.sym 16928 $false
+.sym 16929 $false
+.sym 16932 SPI.C0.prevstart[1]
+.sym 16933 $false
+.sym 16934 $false
+.sym 16935 $false
+.sym 16950 SPI.C0.prevstart[0]
+.sym 16951 $false
+.sym 16952 $false
+.sym 16953 $false
+.sym 16956 genStart.CLKOUT
+.sym 16957 $false
+.sym 16958 $false
+.sym 16959 $false
+.sym 16960 $true
+.sym 16961 SPI.C0.clk$2
+.sym 16962 $false
+.sym 16963 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 16965 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 16966 SPI.C0.hold_count_SB_DFFESR_Q_19_D_SB_LUT4_O_I0
+.sym 16969 SPI.C0.hold_count[0]
+.sym 16970 SPI.C0.hold_count[4]
+.sym 17055 $false
+.sym 17056 count[19]
+.sym 17057 SPI.C0.transmit
+.sym 17058 SPI.C1.done
+.sym 17073 $false
+.sym 17074 $false
+.sym 17075 SPI.C0.transmit
+.sym 17076 count[19]
+.sym 17083 SS_SB_LUT4_O_I3_SB_DFFE_Q_E
+.sym 17084 SPI.C0.clk$2
+.sym 17085 $false
+.sym 17160 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0
+.sym 17161 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 17162 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 17163 SPI.C0.STATE[3]
+.sym 17172 $false
+.sym 17173 SPI.C0.STATE[3]
+.sym 17174 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 17175 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 17190 count[19]
+.sym 17191 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1
+.sym 17192 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I2
+.sym 17193 SPI.C0.finish_SB_LUT4_I3_O_SB_LUT4_I3_1_O
+.sym 17202 genStart.CLKOUT
+.sym 17203 count[19]
+.sym 17204 SPI.C0.STATE_SB_DFF_Q_6_D_SB_LUT4_O_I2
+.sym 17205 SPI.C0.STATE_SB_DFF_Q_3_D_SB_LUT4_O_I3
+.sym 17206 $true
+.sym 17207 SPI.C0.clk$2
+.sym 17208 $false
+.sym 17213 SCLK$2
+.sym 17216 SPI.C0.hold_count[17]
+.sym 17283 SPI.C0.STATE_SB_DFF_Q_4_D_SB_LUT4_O_I1_SB_LUT4_O_I0_SB_LUT4_O_I0
+.sym 17284 SPI.C0.done_configure_SB_LUT4_I3_1_O
+.sym 17285 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I3
+.sym 17286 SPI.C0.finish_SB_LUT4_I0_I3_SB_LUT4_O_I2
+.sym 17289 $false
+.sym 17290 SPI.C0.DATA[2]
+.sym 17291 SPI.C0.DATA[1]
+.sym 17292 SPI.C0.DATA[0]
+.sym 17295 $false
+.sym 17296 $false
+.sym 17297 SPI.C0.DATA[1]
+.sym 17298 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 17301 SPI.C0.STATE[6]
+.sym 17302 SPI.C0.DATA[2]
+.sym 17303 SPI.C0.DATA[1]
+.sym 17304 SPI.C0.DATA[0]
+.sym 17307 SPI.C0.STATE[2]
+.sym 17308 SPI.C0.DATA[2]
+.sym 17309 SPI.C0.DATA[1]
+.sym 17310 SPI.C0.DATA[0]
+.sym 17313 count[19]
+.sym 17314 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 17315 SPI.C0.DATA[0]
+.sym 17316 SPI.C0.DATA[2]
+.sym 17319 count[19]
+.sym 17320 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 17321 SPI.C0.DATA[2]
+.sym 17322 SPI.C0.DATA[1]
+.sym 17325 count[19]
+.sym 17326 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 17327 SPI.C0.DATA[1]
+.sym 17328 SPI.C0.DATA[0]
+.sym 17329 $true
+.sym 17330 SPI.C0.clk$2
+.sym 17331 $false
+.sym 17337 LED_MINUS[0]$2
+.sym 17338 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.sym 17339 SPI.C0.z_axis_data[9]
+.sym 17406 $false
+.sym 17407 $false
+.sym 17408 count[19]
+.sym 17409 SPI.C0.STATE[3]
+.sym 17412 $false
+.sym 17413 $false
+.sym 17414 count[19]
+.sym 17415 SPI.C0.sample_done_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 17418 $false
+.sym 17419 $false
+.sym 17420 SPI.C0.register_select
+.sym 17421 SPI.C1.done
+.sym 17424 SPI.C0.DATA[1]
+.sym 17425 SPI.C0.txdata[9]
+.sym 17426 SPI.C0.DATA[2]
+.sym 17427 SPI.C0.DATA[0]
+.sym 17430 $false
+.sym 17431 SPI.C0.STATE[6]
+.sym 17432 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I2
+.sym 17433 SPI.C0.txdata_SB_DFFESR_Q_6_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 17436 $false
+.sym 17437 count[19]
+.sym 17438 SPI.C0.DATA[0]
+.sym 17439 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1
+.sym 17442 SPI.C1.done
+.sym 17443 SPI.C0.register_select
+.sym 17444 SPI.C0.DATA[0]
+.sym 17445 SPI.C0.DATA[2]
+.sym 17448 $false
+.sym 17449 $false
+.sym 17450 SPI.C0.STATE[6]
+.sym 17451 SPI.C0.DATA_SB_DFF_Q_D_SB_LUT4_O_I1_SB_LUT4_O_I3
+.sym 17457 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.sym 17458 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.sym 17459 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1
+.sym 17460 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 17461 SPI.C0.x_axis_data[9]
+.sym 17462 SPI.C0.x_axis_data[8]
+.sym 17529 SPI.C1.done
+.sym 17530 SPI.C0.register_select
+.sym 17531 SPI.C0.DATA[1]
+.sym 17532 SPI.C0.DATA[0]
+.sym 17541 $false
+.sym 17542 SPI.C0.STATE[6]
+.sym 17543 SPI.C0.txdata[10]
+.sym 17544 SPI.C1.done
+.sym 17547 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 17548 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I1
+.sym 17549 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0_SB_LUT4_O_I2
+.sym 17550 SPI.C0.DATA[2]
+.sym 17553 SPI.C0.txdata_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 17554 SPI.C0.txdata[10]
+.sym 17555 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.sym 17556 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.sym 17565 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 17566 SPI.C0.txdata[11]
+.sym 17567 SPI.C0.txdata_SB_DFFESR_Q_7_D_SB_LUT4_O_I3_SB_LUT4_I0_I1_SB_LUT4_I1_O
+.sym 17568 SPI.C0.txdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3
+.sym 17575 SPI.C0.txdata_SB_DFFESR_Q_2_D_SB_LUT4_O_I2_SB_LUT4_I3_O$2
+.sym 17576 SPI.C0.clk$2
+.sym 17577 genStart.RST$2
+.sym 17578 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.sym 17579 LED_PLUS_SB_LUT4_O_1_I3
+.sym 17580 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 17582 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 17584 LED_PLUS[0]$2
+.sym 17585 SPI.C0.z_axis_data[8]
+.sym 17670 $false
+.sym 17671 $false
+.sym 17672 $false
+.sym 17673 count[19]
+.sym 17702 LED_PLUS_SB_LUT4_O_I3
+.sym 17706 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 17708 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.sym 17775 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 17776 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 17777 SPI.C1.tx_shift_register[9]
+.sym 17778 SPI.C1.tx_shift_register[10]
+.sym 17787 SPI.C1.tx_count_SB_DFFESR_Q_E_SB_LUT4_O_I1
+.sym 17788 SPI.C1.tx_count_SB_DFFESR_Q_D_SB_LUT4_O_I1_SB_LUT4_I3_O
+.sym 17789 SPI.C1.tx_shift_register[10]
+.sym 17790 SPI.C1.tx_shift_register[11]
+.sym 17805 SPI.C1.tx_shift_register_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 17806 SPI.C0.txdata[11]
+.sym 17807 SPI.C1.TxSTATE[0]
+.sym 17808 SPI.C1.TxSTATE[1]
+.sym 17811 SPI.C1.tx_shift_register_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 17812 SPI.C0.txdata[10]
+.sym 17813 SPI.C1.TxSTATE[0]
+.sym 17814 SPI.C1.TxSTATE[1]
+.sym 17821 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 17822 SPI.C0.clk$2
+.sym 17823 genStart.RST$2
+.sym 17910 $false
+.sym 17911 $false
+.sym 17912 $false
+.sym 17913 $false
+.sym 17944 SPI.C1.sdo_SB_DFFESS_Q_E$2
+.sym 17945 SPI.C0.clk$2
+.sym 17946 genStart.RST$2
+.sym 18057 $false
+.sym 18058 $false
+.sym 18059 count[1]
+.sym 18060 count[0]
+.sym 18067 count_SB_DFFE_Q_E$2
+.sym 18068 clk_in$2$2
+.sym 18069 $false
+.sym 18075 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3
+.sym 19064 $false
+.sym 19065 $false
+.sym 19066 $false
+.sym 19067 SS_SB_LUT4_O_I3
+.sym 19145 SPI.C0.hold_count[5]
+.sym 19146 SPI.C0.hold_count[4]
+.sym 19147 SPI.C0.hold_count[3]
+.sym 19148 SPI.C0.hold_count[2]
+.sym 19157 $false
+.sym 19158 SPI.C0.hold_count[1]
+.sym 19159 SPI.C0.hold_count[0]
+.sym 19160 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 19163 $false
+.sym 19164 $false
+.sym 19165 SPI.C0.hold_count[1]
+.sym 19166 SPI.C0.hold_count[0]
+.sym 19181 $false
+.sym 19182 $false
+.sym 19183 genStart.CLKOUT
+.sym 19184 SPI.C0.hold_count[0]
+.sym 19187 SPI.C0.hold_count_SB_DFFESR_Q_16_D_SB_LUT4_O_I0
+.sym 19188 genStart.CLKOUT
+.sym 19189 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 19190 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 19191 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 19192 SPI.C0.clk$2
+.sym 19193 genStart.RST$2
+.sym 19415 $false
+.sym 19416 $false
+.sym 19417 $false
+.sym 19418 SPI.C1.clk_edge_buffer_SB_DFFE_Q_D_SB_LUT4_O_I2_SB_LUT4_I2_O_SB_LUT4_I1_O_SB_DFFE_D_Q
+.sym 19433 SPI.C0.hold_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.sym 19434 genStart.CLKOUT
+.sym 19435 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 19436 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 19437 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 19438 SPI.C0.clk$2
+.sym 19439 genStart.RST$2
+.sym 19476 $true
+.sym 19513 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI$2
+.sym 19514 $false
+.sym 19515 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 19516 $false
+.sym 19517 $false
+.sym 19519 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2]
+.sym 19521 $false
+.sym 19522 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.sym 19525 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3]
+.sym 19527 $false
+.sym 19528 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.sym 19531 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4]
+.sym 19533 $false
+.sym 19534 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.sym 19537 LED_MINUS_SB_LUT4_O_1_I3
+.sym 19539 $false
+.sym 19540 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1
+.sym 19544 $false
+.sym 19545 $false
+.sym 19546 SPI.C0.x_axis_data[9]
+.sym 19547 LED_MINUS_SB_LUT4_O_1_I3
+.sym 19550 $false
+.sym 19551 $false
+.sym 19552 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 19553 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 19556 SPI.C1.rx_shift_register[1]
+.sym 19557 $false
+.sym 19558 $false
+.sym 19559 $false
+.sym 19560 SPI.C0.z_axis_data_SB_DFFESR_Q_E
+.sym 19561 SPI.C0.clk$2
+.sym 19562 genStart.RST$2
+.sym 19599 $true
+.sym 19636 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI$3
+.sym 19637 $false
+.sym 19638 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 19639 $false
+.sym 19640 $false
+.sym 19642 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2]
+.sym 19644 $false
+.sym 19645 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 19648 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3]
+.sym 19649 $false
+.sym 19650 $false
+.sym 19651 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.sym 19652 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2]
+.sym 19654 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3
+.sym 19655 $false
+.sym 19656 $false
+.sym 19657 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 19658 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3]
+.sym 19661 $false
+.sym 19662 $false
+.sym 19663 $false
+.sym 19664 LED_MINUS_SB_LUT4_O_1_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3
+.sym 19667 $false
+.sym 19668 $false
+.sym 19669 $false
+.sym 19670 SPI.C0.x_axis_data[8]
+.sym 19673 SPI.C1.rx_shift_register[1]
+.sym 19674 $false
+.sym 19675 $false
+.sym 19676 $false
+.sym 19679 SPI.C1.rx_shift_register[0]
+.sym 19680 $false
+.sym 19681 $false
+.sym 19682 $false
+.sym 19683 SPI.C0.x_axis_data_SB_DFFESR_Q_E
+.sym 19684 SPI.C0.clk$2
+.sym 19685 genStart.RST$2
+.sym 19760 $false
+.sym 19761 $false
+.sym 19762 $false
+.sym 19763 SPI.C0.x_axis_data[7]
+.sym 19766 SPI.C0.x_axis_data[5]
+.sym 19767 SPI.C0.x_axis_data[8]
+.sym 19768 SPI.C0.x_axis_data[7]
+.sym 19769 SPI.C0.x_axis_data[6]
+.sym 19772 $false
+.sym 19773 $false
+.sym 19774 $false
+.sym 19775 SPI.C0.x_axis_data[5]
+.sym 19784 $false
+.sym 19785 $false
+.sym 19786 $false
+.sym 19787 SPI.C0.x_axis_data[6]
+.sym 19796 $false
+.sym 19797 $false
+.sym 19798 SPI.C0.x_axis_data[9]
+.sym 19799 LED_PLUS_SB_LUT4_O_1_I3
+.sym 19802 SPI.C1.rx_shift_register[0]
+.sym 19803 $false
+.sym 19804 $false
+.sym 19805 $false
+.sym 19806 SPI.C0.z_axis_data_SB_DFFESR_Q_E
+.sym 19807 SPI.C0.clk$2
+.sym 19808 genStart.RST$2
+.sym 19889 SPI.C0.z_axis_data[8]
+.sym 19890 SPI.C0.z_axis_data[7]
+.sym 19891 SPI.C0.z_axis_data[6]
+.sym 19892 SPI.C0.z_axis_data[5]
+.sym 19913 $false
+.sym 19914 $false
+.sym 19915 $false
+.sym 19916 SPI.C0.z_axis_data[8]
+.sym 19925 $false
+.sym 19926 $false
+.sym 19927 $false
+.sym 19928 SPI.C0.z_axis_data[7]
+.sym 20282 $false
+.sym 20283 $false
+.sym 20284 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 20285 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 21088 SPI.C0.hold_count_SB_DFFESR_Q_18_D_SB_LUT4_O_I0
+.sym 21089 SPI.C0.hold_count_SB_DFFESR_Q_17_D_SB_LUT4_O_I0
+.sym 21090 SPI.C0.hold_count_SB_DFFESR_Q_16_D_SB_LUT4_O_I0
+.sym 21091 SPI.C0.hold_count_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.sym 21092 SPI.C0.hold_count_SB_DFFESR_Q_14_D_SB_LUT4_O_I0
+.sym 21093 SPI.C0.hold_count_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.sym 21188 SPI.C0.hold_count_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.sym 21189 SPI.C0.hold_count_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.sym 21190 SPI.C0.hold_count_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.sym 21191 SPI.C0.hold_count_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.sym 21192 SPI.C0.hold_count_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.sym 21193 SPI.C0.hold_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 21194 SPI.C0.hold_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 21195 SPI.C0.hold_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 21290 SPI.C0.hold_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 21291 SPI.C0.hold_count_SB_DFFESR_Q_3_D_SB_LUT4_O_I0
+.sym 21292 SPI.C0.hold_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 21293 SPI.C0.hold_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.sym 21294 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 21295 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 21296 SPI.C0.hold_count[16]
+.sym 21297 SPI.C0.hold_count[15]
+.sym 21497 genStart.CLKOUT
+.sym 21700 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.sym 21701 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.sym 21702 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 21703 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.sym 21704 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 21705 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 22004 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 22005 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 22006 count_SB_DFFE_Q_E_SB_LUT4_O_I2_SB_CARRY_CO_CI_SB_CARRY_CO_23_I1
+.sym 22008 genStart.CLKOUT_SB_DFFER_Q_E
+.sym 22009 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 22010 genStart.clkCount[0]
+.sym 22011 genStart.clkCount[1]
+.sym 22108 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 22109 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2
+.sym 22110 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I0
+.sym 22213 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 22214 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 22952 SPI.C0.hold_count[5]
+.sym 22954 SPI.C0.hold_count[7]
+.sym 22955 SPI.C0.hold_count[3]
+.sym 22956 SPI.C0.hold_count[1]
+.sym 22957 SPI.C0.hold_count[2]
+.sym 22958 SPI.C0.hold_count[6]
+.sym 22988 $true
+.sym 23025 SPI.C0.hold_count[0]$2
+.sym 23026 $false
+.sym 23027 SPI.C0.hold_count[0]
+.sym 23028 $false
+.sym 23029 $false
+.sym 23031 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 23033 $false
+.sym 23034 SPI.C0.hold_count[1]
+.sym 23037 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 23038 $false
+.sym 23039 $false
+.sym 23040 SPI.C0.hold_count[2]
+.sym 23041 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[2]
+.sym 23043 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[4]
+.sym 23044 $false
+.sym 23045 $false
+.sym 23046 SPI.C0.hold_count[3]
+.sym 23047 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[3]
+.sym 23049 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[5]
+.sym 23050 $false
+.sym 23051 $false
+.sym 23052 SPI.C0.hold_count[4]
+.sym 23053 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[4]
+.sym 23055 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[6]
+.sym 23056 $false
+.sym 23057 $false
+.sym 23058 SPI.C0.hold_count[5]
+.sym 23059 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[5]
+.sym 23061 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[7]
+.sym 23062 $false
+.sym 23063 $false
+.sym 23064 SPI.C0.hold_count[6]
+.sym 23065 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[6]
+.sym 23067 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8]
+.sym 23068 $false
+.sym 23069 $false
+.sym 23070 SPI.C0.hold_count[7]
+.sym 23071 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[7]
+.sym 23075 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 23076 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 23077 SPI.C0.hold_count[11]
+.sym 23078 SPI.C0.hold_count[8]
+.sym 23079 SPI.C0.hold_count[13]
+.sym 23080 SPI.C0.hold_count[9]
+.sym 23081 SPI.C0.hold_count[10]
+.sym 23082 SPI.C0.hold_count[12]
+.sym 23111 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8]
+.sym 23148 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[9]
+.sym 23149 $false
+.sym 23150 $false
+.sym 23151 SPI.C0.hold_count[8]
+.sym 23152 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[8]
+.sym 23154 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[10]
+.sym 23155 $false
+.sym 23156 $false
+.sym 23157 SPI.C0.hold_count[9]
+.sym 23158 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[9]
+.sym 23160 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[11]
+.sym 23161 $false
+.sym 23162 $false
+.sym 23163 SPI.C0.hold_count[10]
+.sym 23164 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[10]
+.sym 23166 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[12]
+.sym 23167 $false
+.sym 23168 $false
+.sym 23169 SPI.C0.hold_count[11]
+.sym 23170 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[11]
+.sym 23172 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[13]
+.sym 23173 $false
+.sym 23174 $false
+.sym 23175 SPI.C0.hold_count[12]
+.sym 23176 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[12]
+.sym 23178 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[14]
+.sym 23179 $false
+.sym 23180 $false
+.sym 23181 SPI.C0.hold_count[13]
+.sym 23182 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[13]
+.sym 23184 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[15]
+.sym 23185 $false
+.sym 23186 $false
+.sym 23187 SPI.C0.hold_count[14]
+.sym 23188 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[14]
+.sym 23190 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16]
+.sym 23191 $false
+.sym 23192 $false
+.sym 23193 SPI.C0.hold_count[15]
+.sym 23194 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[15]
+.sym 23199 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 23200 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 23201 SPI.C0.hold_count[18]
+.sym 23202 SPI.C0.hold_count[19]
+.sym 23203 SPI.C0.hold_count[14]
+.sym 23204 SPI.C0.hold_count[20]
+.sym 23234 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16]
+.sym 23271 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[17]
+.sym 23272 $false
+.sym 23273 $false
+.sym 23274 SPI.C0.hold_count[16]
+.sym 23275 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[16]
+.sym 23277 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[18]
+.sym 23278 $false
+.sym 23279 $false
+.sym 23280 SPI.C0.hold_count[17]
+.sym 23281 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[17]
+.sym 23283 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[19]
+.sym 23284 $false
+.sym 23285 $false
+.sym 23286 SPI.C0.hold_count[18]
+.sym 23287 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[18]
+.sym 23289 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[20]
+.sym 23290 $false
+.sym 23291 $false
+.sym 23292 SPI.C0.hold_count[19]
+.sym 23293 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[19]
+.sym 23296 $false
+.sym 23297 $false
+.sym 23298 SPI.C0.hold_count[20]
+.sym 23299 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0_SB_LUT4_O_I3[20]
+.sym 23302 SPI.C0.hold_count[17]
+.sym 23303 SPI.C0.hold_count[16]
+.sym 23304 SPI.C0.hold_count[15]
+.sym 23305 SPI.C0.hold_count[14]
+.sym 23308 SPI.C0.hold_count_SB_DFFESR_Q_4_D_SB_LUT4_O_I0
+.sym 23309 genStart.CLKOUT
+.sym 23310 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 23311 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 23314 SPI.C0.hold_count_SB_DFFESR_Q_5_D_SB_LUT4_O_I0
+.sym 23315 genStart.CLKOUT
+.sym 23316 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 23317 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 23318 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 23319 SPI.C0.clk$2
+.sym 23320 genStart.RST$2
+.sym 23536 $false
+.sym 23537 $false
+.sym 23538 $false
+.sym 23539 genStart.CLKOUT
+.sym 23564 genStart.CLKOUT_SB_DFFER_Q_E
+.sym 23565 SPI.C0.clk$2
+.sym 23566 genStart.RST$2
+.sym 23695 LED_MINUS[1]$2
+.sym 23696 LED$2
+.sym 23697 LED_PLUS[1]$2
+.sym 23726 $true
+.sym 23763 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI$3
+.sym 23764 $false
+.sym 23765 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 23766 $false
+.sym 23767 $false
+.sym 23769 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2]
+.sym 23771 $false
+.sym 23772 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 23775 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3]
+.sym 23776 $false
+.sym 23777 $false
+.sym 23778 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1_SB_LUT4_O_I2
+.sym 23779 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[2]
+.sym 23781 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3
+.sym 23782 $false
+.sym 23783 $false
+.sym 23784 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 23785 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_CI[3]
+.sym 23788 $false
+.sym 23789 $false
+.sym 23790 $false
+.sym 23791 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3
+.sym 23794 $false
+.sym 23795 $false
+.sym 23796 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1_SB_LUT4_O_I2
+.sym 23797 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 23800 $false
+.sym 23801 $false
+.sym 23802 $false
+.sym 23803 SPI.C0.z_axis_data[6]
+.sym 23806 $false
+.sym 23807 $false
+.sym 23808 $false
+.sym 23809 SPI.C0.z_axis_data[5]
+.sym 24061 genStart.clkCount[2]
+.sym 24062 genStart.clkCount[3]
+.sym 24063 genStart.clkCount[4]
+.sym 24064 genStart.clkCount[5]
+.sym 24065 genStart.clkCount[6]
+.sym 24066 genStart.clkCount[7]
+.sym 24133 $false
+.sym 24134 $false
+.sym 24135 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2
+.sym 24136 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3
+.sym 24139 genStart.clkCount[8]
+.sym 24140 genStart.clkCount[6]
+.sym 24141 genStart.clkCount[5]
+.sym 24142 genStart.clkCount[4]
+.sym 24145 $false
+.sym 24146 $false
+.sym 24147 $false
+.sym 24148 count[10]
+.sym 24157 $false
+.sym 24158 $false
+.sym 24159 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2
+.sym 24160 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I3
+.sym 24163 genStart.clkCount[3]
+.sym 24164 genStart.clkCount[2]
+.sym 24165 genStart.clkCount[1]
+.sym 24166 genStart.clkCount[0]
+.sym 24169 $false
+.sym 24170 $false
+.sym 24171 genStart.clkCount[0]
+.sym 24172 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 24175 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 24176 $false
+.sym 24177 genStart.clkCount[1]
+.sym 24178 genStart.clkCount[0]
+.sym 24179 $true
+.sym 24180 SPI.C0.clk$2
+.sym 24181 genStart.RST$2
+.sym 24182 genStart.clkCount[8]
+.sym 24183 genStart.clkCount[9]
+.sym 24184 genStart.clkCount[10]
+.sym 24185 genStart.clkCount[11]
+.sym 24186 genStart.clkCount[12]
+.sym 24187 genStart.clkCount[13]
+.sym 24188 genStart.clkCount[14]
+.sym 24189 genStart.clkCount[15]
+.sym 24268 genStart.clkCount[16]
+.sym 24269 genStart.clkCount[14]
+.sym 24270 genStart.clkCount[13]
+.sym 24271 genStart.clkCount[11]
+.sym 24274 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I0
+.sym 24275 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I1
+.sym 24276 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I2
+.sym 24277 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_O_I3
+.sym 24280 genStart.clkCount[12]
+.sym 24281 genStart.clkCount[10]
+.sym 24282 genStart.clkCount[9]
+.sym 24283 genStart.clkCount[7]
+.sym 24305 genStart.clkCount[16]
+.sym 24306 genStart.clkCount[17]
+.sym 24307 genStart.clkCount[18]
+.sym 24308 genStart.clkCount[19]
+.sym 24309 genStart.clkCount[20]
+.sym 24310 genStart.clkCount[21]
+.sym 24311 genStart.clkCount[22]
+.sym 24312 genStart.clkCount[23]
+.sym 24409 genStart.clkCount[23]
+.sym 24410 genStart.clkCount[20]
+.sym 24411 genStart.clkCount[19]
+.sym 24412 genStart.clkCount[15]
+.sym 24415 genStart.clkCount[22]
+.sym 24416 genStart.clkCount[21]
+.sym 24417 genStart.clkCount[18]
+.sym 24418 genStart.clkCount[17]
+.sym 25091 SDI$2
+.sym 25195 SPI.C0.hold_count_SB_DFFESR_Q_15_D_SB_LUT4_O_I0
+.sym 25196 genStart.CLKOUT
+.sym 25197 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25198 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25207 SPI.C0.hold_count_SB_DFFESR_Q_13_D_SB_LUT4_O_I0
+.sym 25208 genStart.CLKOUT
+.sym 25209 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25210 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25213 SPI.C0.hold_count_SB_DFFESR_Q_17_D_SB_LUT4_O_I0
+.sym 25214 genStart.CLKOUT
+.sym 25215 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25216 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25219 SPI.C0.hold_count_SB_DFFESR_Q_19_D_SB_LUT4_O_I0
+.sym 25220 genStart.CLKOUT
+.sym 25221 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25222 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25225 SPI.C0.hold_count_SB_DFFESR_Q_18_D_SB_LUT4_O_I0
+.sym 25226 genStart.CLKOUT
+.sym 25227 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25228 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25231 SPI.C0.hold_count_SB_DFFESR_Q_14_D_SB_LUT4_O_I0
+.sym 25232 genStart.CLKOUT
+.sym 25233 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25234 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25241 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 25242 SPI.C0.clk$2
+.sym 25243 genStart.RST$2
+.sym 25350 SPI.C0.hold_count[13]
+.sym 25351 SPI.C0.hold_count[12]
+.sym 25352 SPI.C0.hold_count[11]
+.sym 25353 SPI.C0.hold_count[10]
+.sym 25356 SPI.C0.hold_count[9]
+.sym 25357 SPI.C0.hold_count[8]
+.sym 25358 SPI.C0.hold_count[7]
+.sym 25359 SPI.C0.hold_count[6]
+.sym 25362 SPI.C0.hold_count_SB_DFFESR_Q_9_D_SB_LUT4_O_I0
+.sym 25363 genStart.CLKOUT
+.sym 25364 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25365 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25368 SPI.C0.hold_count_SB_DFFESR_Q_12_D_SB_LUT4_O_I0
+.sym 25369 genStart.CLKOUT
+.sym 25370 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25371 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25374 SPI.C0.hold_count_SB_DFFESR_Q_7_D_SB_LUT4_O_I0
+.sym 25375 genStart.CLKOUT
+.sym 25376 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25377 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25380 SPI.C0.hold_count_SB_DFFESR_Q_11_D_SB_LUT4_O_I0
+.sym 25381 genStart.CLKOUT
+.sym 25382 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25383 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25386 SPI.C0.hold_count_SB_DFFESR_Q_10_D_SB_LUT4_O_I0
+.sym 25387 genStart.CLKOUT
+.sym 25388 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25389 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25392 SPI.C0.hold_count_SB_DFFESR_Q_8_D_SB_LUT4_O_I0
+.sym 25393 genStart.CLKOUT
+.sym 25394 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25395 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25396 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 25397 SPI.C0.clk$2
+.sym 25398 genStart.RST$2
+.sym 25511 $false
+.sym 25512 SPI.C0.hold_count[20]
+.sym 25513 SPI.C0.hold_count[19]
+.sym 25514 SPI.C0.hold_count[18]
+.sym 25517 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I0
+.sym 25518 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I1
+.sym 25519 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I2
+.sym 25520 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3_SB_LUT4_O_I3
+.sym 25523 SPI.C0.hold_count_SB_DFFESR_Q_2_D_SB_LUT4_O_I0
+.sym 25524 genStart.CLKOUT
+.sym 25525 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25526 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25529 SPI.C0.hold_count_SB_DFFESR_Q_1_D_SB_LUT4_O_I0
+.sym 25530 genStart.CLKOUT
+.sym 25531 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25532 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25535 SPI.C0.hold_count_SB_DFFESR_Q_6_D_SB_LUT4_O_I0
+.sym 25536 genStart.CLKOUT
+.sym 25537 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25538 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25541 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I0
+.sym 25542 genStart.CLKOUT
+.sym 25543 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I2
+.sym 25544 SPI.C0.hold_count_SB_DFFESR_Q_D_SB_LUT4_O_I3
+.sym 25551 SPI.C0.hold_count_SB_DFFESR_Q_E$2
+.sym 25552 SPI.C0.clk$2
+.sym 25553 genStart.RST$2
+.sym 26087 $true
+.sym 26124 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI$2
+.sym 26125 $false
+.sym 26126 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_CI
+.sym 26127 $false
+.sym 26128 $false
+.sym 26130 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[2]
+.sym 26132 $false
+.sym 26133 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_1_I1
+.sym 26136 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[3]
+.sym 26138 $false
+.sym 26139 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO_SB_CARRY_CO_I1
+.sym 26142 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O_SB_CARRY_I1_CO[4]
+.sym 26144 $false
+.sym 26145 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O
+.sym 26148 LED_MINUS_SB_LUT4_O_I3
+.sym 26150 $false
+.sym 26151 LED_MINUS_SB_LUT4_O_I3_SB_CARRY_CO_I1
+.sym 26155 $false
+.sym 26156 $false
+.sym 26157 SPI.C0.z_axis_data[9]
+.sym 26158 LED_MINUS_SB_LUT4_O_I3
+.sym 26161 LED_MINUS[1]$2
+.sym 26162 LED_MINUS[0]$2
+.sym 26163 LED_PLUS[1]$2
+.sym 26164 LED_PLUS[0]$2
+.sym 26167 $false
+.sym 26168 $false
+.sym 26169 SPI.C0.z_axis_data[9]
+.sym 26170 LED_PLUS_SB_LUT4_O_I3
+.sym 26552 $true
+.sym 26589 genStart.clkCount[0]$2
+.sym 26590 $false
+.sym 26591 genStart.clkCount[0]
+.sym 26592 $false
+.sym 26593 $false
+.sym 26595 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
+.sym 26597 $false
+.sym 26598 genStart.clkCount[1]
+.sym 26601 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[3]
+.sym 26602 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26603 $false
+.sym 26604 genStart.clkCount[2]
+.sym 26605 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[2]
+.sym 26607 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[4]
+.sym 26608 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26609 $false
+.sym 26610 genStart.clkCount[3]
+.sym 26611 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[3]
+.sym 26613 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[5]
+.sym 26614 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26615 $false
+.sym 26616 genStart.clkCount[4]
+.sym 26617 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[4]
+.sym 26619 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[6]
+.sym 26620 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26621 $false
+.sym 26622 genStart.clkCount[5]
+.sym 26623 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[5]
+.sym 26625 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[7]
+.sym 26626 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26627 $false
+.sym 26628 genStart.clkCount[6]
+.sym 26629 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[6]
+.sym 26631 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8]
+.sym 26632 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26633 $false
+.sym 26634 genStart.clkCount[7]
+.sym 26635 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[7]
+.sym 26636 $true
+.sym 26637 SPI.C0.clk$2
+.sym 26638 genStart.RST$2
+.sym 26707 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8]
+.sym 26744 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[9]
+.sym 26745 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26746 $false
+.sym 26747 genStart.clkCount[8]
+.sym 26748 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[8]
+.sym 26750 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[10]
+.sym 26751 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26752 $false
+.sym 26753 genStart.clkCount[9]
+.sym 26754 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[9]
+.sym 26756 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[11]
+.sym 26757 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26758 $false
+.sym 26759 genStart.clkCount[10]
+.sym 26760 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[10]
+.sym 26762 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[12]
+.sym 26763 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26764 $false
+.sym 26765 genStart.clkCount[11]
+.sym 26766 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[11]
+.sym 26768 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[13]
+.sym 26769 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26770 $false
+.sym 26771 genStart.clkCount[12]
+.sym 26772 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[12]
+.sym 26774 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[14]
+.sym 26775 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26776 $false
+.sym 26777 genStart.clkCount[13]
+.sym 26778 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[13]
+.sym 26780 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[15]
+.sym 26781 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26782 $false
+.sym 26783 genStart.clkCount[14]
+.sym 26784 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[14]
+.sym 26786 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16]
+.sym 26787 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26788 $false
+.sym 26789 genStart.clkCount[15]
+.sym 26790 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[15]
+.sym 26791 $true
+.sym 26792 SPI.C0.clk$2
+.sym 26793 genStart.RST$2
+.sym 26862 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16]
+.sym 26899 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[17]
+.sym 26900 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26901 $false
+.sym 26902 genStart.clkCount[16]
+.sym 26903 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[16]
+.sym 26905 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[18]
+.sym 26906 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26907 $false
+.sym 26908 genStart.clkCount[17]
+.sym 26909 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[17]
+.sym 26911 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[19]
+.sym 26912 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26913 $false
+.sym 26914 genStart.clkCount[18]
+.sym 26915 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[18]
+.sym 26917 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[20]
+.sym 26918 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26919 $false
+.sym 26920 genStart.clkCount[19]
+.sym 26921 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[19]
+.sym 26923 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[21]
+.sym 26924 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26925 $false
+.sym 26926 genStart.clkCount[20]
+.sym 26927 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[20]
+.sym 26929 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[22]
+.sym 26930 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26931 $false
+.sym 26932 genStart.clkCount[21]
+.sym 26933 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[21]
+.sym 26935 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[23]
+.sym 26936 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26937 $false
+.sym 26938 genStart.clkCount[22]
+.sym 26939 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[22]
+.sym 26942 $false
+.sym 26943 genStart.CLKOUT_SB_DFFER_Q_E_SB_LUT4_O_I2_SB_LUT4_I2_O
+.sym 26944 genStart.clkCount[23]
+.sym 26945 genStart.clkCount_SB_DFFR_Q_D_SB_LUT4_O_I3[23]
+.sym 26946 $true
+.sym 26947 SPI.C0.clk$2
+.sym 26948 genStart.RST$2
+.sym 27283 SS$2
+.sym 27310 SPI.C1.sdo
+.sym 27370 SCLK$2
+.sym 27429 SPI.C0.hold_count_SB_DFFESR_Q_E
+.sym 27459 genStart.RST
+.sym 27463 LED$2
+.sym 27519 LED_PLUS[1]$2
+.sym 27522 LED_PLUS[0]$2
+.sym 27549 LED_MINUS[1]$2
+.sym 27552 LED_MINUS[0]$2
diff --git a/IceStick_Accelerometer/src/pmodacl_demo.v b/IceStick_Accelerometer/src/pmodacl_demo.v
new file mode 100644
index 0000000..8d7d90c
--- /dev/null
+++ b/IceStick_Accelerometer/src/pmodacl_demo.v
@@ -0,0 +1,143 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    PmodACL_Demo
+
+// ====================================================================================
+//    Define Module
+// ====================================================================================
+module PmodACL_Demo(
+    clk_in,
+    SDI,
+    SDO,
+    SCLK,
+    SS,
+    test1,
+    test2,
+    LED_PLUS,
+    LED_MINUS,
+    LED
+);
+
+// ====================================================================================
+//    Port Declarations
+// ====================================================================================
+   input        clk_in ;
+   output       test1  ;
+   output       test2  ;
+   input        SDI    ;
+   output       SDO    ;
+   output       SCLK   ;
+   output       SS     ;
+   
+   output [1:0]   LED_PLUS ;
+   output [1:0]   LED_MINUS;
+   output         LED;
+   
+// ====================================================================================
+//    Parameters, Register, and Wires
+// ====================================================================================
+
+// parameters (constants)
+   parameter clk_freq = 27'd12000000;  // in Hz for 12MHz clock
+   reg [26:0]   count   ;
+   wire         RST     ;
+   wire [9:0]   xAxis   ;  // x-axis data from PmodACL
+   wire [9:0]   yAxis   ;  // y-axis data from PmodACL
+   wire [9:0]   zAxis   ;  // z-axis data from PmodACL
+   wire [9:0]   selData ;  // Data selected to display
+   wire         START   ;  // Data Transfer Request Signal
+   wire         CLK     ;
+   
+   wire plus_0, plus_1, plus_2, plus_3 ;
+   wire minus_0, minus_1, minus_2, minus_3 ;
+   
+//  ===================================================================================
+//    Implementation
+//  ===================================================================================
+
+//// Internal Oscillator
+//// defparam OSCH_inst.NOM_FREQ = "2.08";// This is the default frequency
+//defparam OSCH_inst.NOM_FREQ = "88.67";
+//OSCH OSCH_inst( .STDBY(1'b0), // 0=Enabled, 1=Disabled
+//// also Disabled with Bandgap=OFF
+//.OSC(osc_clk),
+//.SEDSTDBY()); // this signal is not required if not using SED
+
+// PLL instantiation
+ice_pll ice_pll_inst(
+     .REFERENCECLK ( clk_in        ),    // input 12MHz
+     .PLLOUTCORE   ( osc_clk       ),    // output 88MHz
+     .PLLOUTGLOBAL ( PLLOUTGLOBAL  ),
+     .RESET        ( 1'b1          )
+     );
+
+assign CLK = osc_clk ;
+
+// internal reset generation
+always @ (posedge clk_in)
+    begin
+        if (count >= (clk_freq/2)) begin
+        end else                       
+            count <= count + 1;
+    end
+
+assign RST = ~count[19] ;
+
+//-----------------------------------------------
+//    Interfaces PmodACL
+//-----------------------------------------------
+SPIcomponent SPI(
+    .CLK   (CLK   ),
+    .RST   (RST   ),
+    .START (START ),
+    .SDI   (SDI   ),
+    .SDO   (SDO   ),
+    .SCLK  (SCLK  ),
+    .SS    (SS    ),
+    .xAxis (xAxis ),
+    .yAxis (yAxis ),
+    .zAxis (zAxis )
+);
+
+//-----------------------------------------------
+//    Generates a 5Hz Data Transfer Request Signal
+//-----------------------------------------------
+ClkDiv_5Hz genStart(
+    .CLK    (CLK   ),
+    .RST    (RST   ),
+    .CLKOUT (START )
+);
+
+  wire plus_0, plus_1, plus_2, plus_3 ;
+  wire minus_0, minus_1, minus_2, minus_3 ;
+  
+  assign plus_0 = xAxis[8:5] > 0 ;
+  assign plus_1 = xAxis[8:5] > 1 ;
+  
+  assign minus_0 = (16 - xAxis[8:5]) > 0 ;
+  assign minus_1 = (16 - xAxis[8:5]) > 1 ;
+
+// Z direction
+  wire z_plus_0, z_minus_0 ;
+  assign z_plus_0  = zAxis[8:5] > 0 ;
+  assign z_minus_0 = (16 - zAxis[8:5]) > 0 ;
+  assign z_plus_1  = zAxis[8:5] > 1 ;
+  assign z_minus_1 = (16 - zAxis[8:5]) > 1 ;
+ 
+  assign  LED_PLUS[0]  = (xAxis[9]==0) ? ~plus_0 : 1'b1 ;
+  assign  LED_MINUS[0] = (xAxis[9]==1) ? ~minus_0 : 1'b1 ;
+  assign  LED_PLUS[1]  = (xAxis[9]==0) ? ~plus_1 : 1'b1 ;
+  assign  LED_MINUS[1] = (xAxis[9]==1) ? ~minus_1 : 1'b1 ;  
+
+  assign  LED_PLUS[1]  = (zAxis[9]==0) ? ~z_plus_0 : 1'b1 ;  
+  assign  LED_MINUS[1] = (zAxis[9]==1) ? ~z_minus_0 : 1'b1 ;
+  
+  // middle led if flat
+  assign LED = LED_PLUS[0] & LED_MINUS[0] & LED_PLUS[1] & LED_MINUS[1] ;
+  
+// debug
+  assign test1 = osc_clk ;
+  assign test2 = RST ;
+
+endmodule
diff --git a/IceStick_Accelerometer/src/slaveselect.v b/IceStick_Accelerometer/src/slaveselect.v
new file mode 100644
index 0000000..21ac9d4
--- /dev/null
+++ b/IceStick_Accelerometer/src/slaveselect.v
@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    slaveSelect
+
+//  ===================================================================================
+//  								Define Module, Inputs and Outputs
+//  ===================================================================================
+module slaveSelect(
+		rst,
+		clk,
+		transmit,
+		done,
+		ss
+);
+
+// ====================================================================================
+// 										Port Declarations
+// ====================================================================================
+   input   rst;
+   input   clk;
+   input   transmit;
+   input   done;
+   output  ss;
+   reg     ss = 1'b1;
+   
+   
+//  ===================================================================================
+// 							  				Implementation
+//  ===================================================================================
+   
+   
+		//-----------------------------------------------
+		//			  Generates Slave Select Signal
+		//-----------------------------------------------
+		always @(posedge clk)
+		begin: ssprocess
+			
+			begin
+				//reset state, ss goes high ( disabled )
+				if (rst == 1'b1)
+					ss <= 1'b1;
+				//if transmitting, then ss goes low ( enabled )
+				else if (transmit == 1'b1)
+					ss <= 1'b0;
+				//if done, then ss goes high ( disabled )
+				else if (done == 1'b1)
+					ss <= 1'b1;
+			end
+		end
+   
+endmodule
+
+
diff --git a/IceStick_Accelerometer/src/spicomponent.v b/IceStick_Accelerometer/src/spicomponent.v
new file mode 100644
index 0000000..8318c96
--- /dev/null
+++ b/IceStick_Accelerometer/src/spicomponent.v
@@ -0,0 +1,95 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    SPIcomponent
+
+//  ===================================================================================
+//  								  Define Module, Inputs and Outputs
+//  ===================================================================================
+module SPIcomponent(
+		CLK,
+		RST,
+		START,
+		SDI,
+		SDO,
+		SCLK,
+		SS,
+		xAxis,
+		yAxis,
+		zAxis
+);
+
+// ====================================================================================
+// 										Port Declarations
+// ====================================================================================
+   input        CLK;
+   input        RST;
+   input        START;
+   input        SDI;
+   output       SDO;
+   output       SCLK;
+   output       SS;
+   output [9:0] xAxis;
+   output [9:0] yAxis;
+   output [9:0] zAxis;
+   
+// ====================================================================================
+// 								Parameters, Register, and Wires
+// ====================================================================================
+	wire [9:0] 	 xAxis;
+	wire [9:0] 	 yAxis;
+	wire [9:0] 	 zAxis;
+
+   wire [15:0]  TxBuffer;
+   wire [7:0]   RxBuffer;
+   wire         doneConfigure;
+   wire         done;
+   wire         transmit;
+   
+//  ===================================================================================
+// 							  				Implementation
+//  ===================================================================================
+   
+		//-------------------------------------------------------------------------
+		//	Controls SPI Interface, Stores Received Data, and Controls Data to Send
+		//-------------------------------------------------------------------------
+		SPImaster C0(
+					.rst(RST),
+					.start(START),
+					.clk(CLK),
+					.transmit(transmit),
+					.txdata(TxBuffer),
+					.rxdata(RxBuffer),
+					.done(done),
+					.x_axis_data(xAxis),
+					.y_axis_data(yAxis),
+					.z_axis_data(zAxis)
+		);
+		
+		//-------------------------------------------------------------------------
+		//		 Produces Timing Signal, Reads ACL Data, and Writes Data to ACL
+		//-------------------------------------------------------------------------
+		SPIinterface C1(
+					.sdi(SDI),
+					.sdo(SDO),
+					.rst(RST),
+					.clk(CLK),
+					.sclk(SCLK),
+					.txbuffer(TxBuffer),
+					.rxbuffer(RxBuffer),
+					.done_out(done),
+					.transmit(transmit)
+		);
+		
+		//-------------------------------------------------------------------------
+		//		 			 	Enables/Disables PmodACL Communication
+		//-------------------------------------------------------------------------
+		slaveSelect C2(
+					.clk(CLK),
+					.ss(SS),
+					.done(done),
+					.transmit(transmit),
+					.rst(RST)
+		);
+   
+endmodule
diff --git a/IceStick_Accelerometer/src/spiinterface.v b/IceStick_Accelerometer/src/spiinterface.v
new file mode 100644
index 0000000..40df693
--- /dev/null
+++ b/IceStick_Accelerometer/src/spiinterface.v
@@ -0,0 +1,236 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    SPIinterface
+
+//  ===================================================================================
+//  								Define Module, Inputs and Outputs
+//  ===================================================================================
+module SPIinterface(
+		txbuffer,
+		rxbuffer,
+		transmit,
+		done_out,
+		sdi, sdo,
+		rst, clk,
+		sclk
+);
+   
+// ====================================================================================
+// 										Port Declarations
+// ====================================================================================
+   input            clk;
+   input            rst;
+   input            transmit;
+   input            sdi;
+	input [15:0]     txbuffer;
+   output [7:0]     rxbuffer;
+   output           done_out;
+   output           sdo;
+   output           sclk;
+   
+   
+// ====================================================================================
+// 							  Parameters, Registers, and Wires
+// ====================================================================================
+	wire             sclk;
+	wire             done_out;
+   reg              sdo;
+	wire [7:0]		  rxbuffer;
+   
+   parameter [7:0]  CLKDIVIDER = 8'hFF;		//leads to sclk of about 98kHz
+
+   parameter [1:0]  TxType_idle = 0,
+                    TxType_transmitting = 1;
+
+   parameter [1:0]  RxType_idle = 0,
+                    RxType_recieving = 1;
+
+   parameter [1:0]  SCLKType_idle = 0,
+                    SCLKType_running = 1;
+						  
+   reg [7:0]        clk_count = 7'd0;
+   reg              clk_edge_buffer = 1'd0;
+   
+   reg              sck_previous = 1'b1;
+   reg              sck_buffer = 1'b1;
+   
+   reg [15:0]       tx_shift_register = 16'h0000;
+   reg [3:0]        tx_count = 4'h0;
+   reg [7:0]        rx_shift_register = 8'h00;
+   reg [3:0]        rx_count = 4'h0;
+
+   reg              done = 1'b0;
+   reg [1:0]        TxSTATE = TxType_idle;
+   reg [1:0]        RxSTATE = RxType_idle;
+   reg [1:0]        SCLKSTATE = SCLKType_idle;
+   
+//  ===================================================================================
+// 							  				Implementation
+//  ===================================================================================
+   
+		//-------------------------------------------------------------------------
+		//		 			 			 Transmission Controller
+		//-------------------------------------------------------------------------
+		always @(posedge clk)
+		begin: TxProcess
+			//Reset state
+			
+			begin
+				if (rst == 1'b1)
+				begin
+					tx_shift_register <= 16'd0;
+					tx_count <= 4'd0;
+					sdo <= 1'b1;
+					TxSTATE <= TxType_idle;
+				end
+				else
+					case (TxSTATE)
+						//when idle, if transmit goes high, then the state goes into 
+						//transmitting. during idle state, sdo is held high
+						TxType_idle :
+							begin
+								tx_shift_register <= txbuffer;
+								//sdo<='1';
+								if (transmit == 1'b1)
+									TxSTATE <= TxType_transmitting;
+								else if (done == 1'b1)
+									sdo <= 1'b1;
+							end
+						TxType_transmitting :
+							if (sck_previous == 1'b1 & sck_buffer == 1'b0)
+							begin
+								//when count is 15, then cycles out to idle state again. 
+								//otherwise, the TxData is shifted out on the falling edge
+								//of the serial clock
+								if (tx_count == 4'b1111) begin
+									TxSTATE <= TxType_idle;
+									tx_count <= 4'd0;
+									sdo <= tx_shift_register[15];
+								end
+								else begin
+									tx_count <= tx_count + 4'b0001;
+									sdo <= tx_shift_register[15];
+									tx_shift_register <= {tx_shift_register[14:0], 1'b0};
+								end
+							end
+					endcase
+			end
+		end
+		
+		//-------------------------------------------------------------------------
+		//		 			 			  Reception Controller
+		//-------------------------------------------------------------------------
+		always @(posedge clk)
+		begin: RxProcess
+			//Reset state
+			
+			begin
+				if (rst == 1'b1)
+				begin
+					rx_shift_register <= 8'h00;
+					rx_count <= 4'h0;
+					done <= 1'b0;
+					RxSTATE <= RxType_idle;
+				end
+				else
+					case (RxSTATE)
+						RxType_idle :
+							//when transmit goes high from the SPImaster, the state
+							//goes to recieving and rx_shift_register is zeroed
+							if (transmit == 1'b1)
+							begin
+								RxSTATE <= RxType_recieving;
+								rx_shift_register <= 8'h00;
+							end
+							else if (SCLKSTATE == RxType_idle)
+								done <= 1'b0;
+						RxType_recieving :
+							if (sck_previous == 1'b0 & sck_buffer == 1'b1)
+							begin
+								//sdi is sampled on the rising edge and after the 16 rising edge, 
+								//the state goes back to idle and done is asserted
+								if (rx_count == 4'b1111)
+								begin
+									RxSTATE <= RxType_idle;
+									rx_count <= 4'd0;
+									rx_shift_register <= {rx_shift_register[6:0], sdi};
+									done <= 1'b1;
+								end
+								else
+								begin
+									rx_count <= rx_count + 4'd1;
+									rx_shift_register <= {rx_shift_register[6:0], sdi};
+								end
+							end
+					endcase
+			end
+		end
+		
+		//-------------------------------------------------------------------------
+		//		 			 					Serial Clock
+		//-------------------------------------------------------------------------
+		always @(posedge clk)
+		begin: SCLKgen
+			//Reset State with SCK held high      
+			begin
+				if (rst == 1'b1)
+				begin
+					clk_count <= 8'h00;
+					SCLKSTATE <= SCLKType_idle;
+					sck_previous <= 1'b1;
+					sck_buffer <= 1'b1;
+				end
+				else
+					case (SCLKSTATE)
+						SCLKType_idle :
+							begin
+								sck_previous <= 1'b1;
+								sck_buffer <= 1'b1;
+								clk_count <= 8'h00;
+								clk_edge_buffer <= 1'b0;
+								
+								//when transmit is high, the state goes to running
+								if (transmit == 1'b1)
+								begin
+									SCLKSTATE <= SCLKType_running;
+								end
+							end
+						SCLKType_running :
+							//when done is high, the state goes back to idle
+							if (done == 1'b1) begin
+								SCLKSTATE <= SCLKType_idle;
+							end
+							//if done is nto asserted, the clock continues to be 
+							//generated
+							else if (clk_count == CLKDIVIDER) begin
+								if (clk_edge_buffer == 1'b0) begin
+									sck_buffer <= 1'b1;
+									clk_edge_buffer <= 1'b1;
+								end
+								else begin
+									sck_buffer <= (~sck_buffer);
+									clk_count <= 8'h00;
+								end
+							end
+							else begin
+								sck_previous <= sck_buffer;
+								clk_count <= clk_count + 1'b1;
+							end
+					endcase
+			end
+		end
+		
+		//-------------------------------------------------------------------------
+		//		 			 					Assign Outputs
+		//-------------------------------------------------------------------------
+		//The rxbuffer is tied to the rx_shift_register and is ouput to the SPImaster
+		assign rxbuffer = rx_shift_register;
+		//the signal SCK is tied to the output sclk
+		assign sclk = sck_buffer;
+		//done_out, to the SPImaster, is tied to the signal done produced in the recieving state machine
+		assign done_out = done;
+   
+endmodule
+
+
diff --git a/IceStick_Accelerometer/src/spimaster.v b/IceStick_Accelerometer/src/spimaster.v
new file mode 100644
index 0000000..26ed21c
--- /dev/null
+++ b/IceStick_Accelerometer/src/spimaster.v
@@ -0,0 +1,380 @@
+`timescale 1ns / 1ps
+// Created By: Tritai Nguyen
+// Create Date:    03/07/2020
+// Module Name:    SPImaster
+
+//  ===================================================================================
+//  								Define Module, Inputs and Outputs
+//  ===================================================================================
+module SPImaster(
+		rst,
+		clk,
+		start,
+		rxdata,
+		done,
+		transmit,
+		txdata,
+		x_axis_data,
+		y_axis_data,
+		z_axis_data
+);
+
+// ====================================================================================
+// 										Port Declarations
+// ====================================================================================
+	input            rst;
+   input            clk;
+   input            start;
+   input [7:0]      rxdata;
+   input            done;
+   output           transmit;
+   output [15:0]    txdata;
+   output [9:0]     x_axis_data;
+   output [9:0]     y_axis_data;
+   output [9:0]     z_axis_data;
+   
+// ====================================================================================
+// 								Parameters, Register, and Wires
+// ====================================================================================
+   
+   reg [15:0]       txdata;
+   reg [9:0]        x_axis_data;
+   reg [9:0]        y_axis_data;
+   reg [9:0]        z_axis_data;
+   reg              transmit;
+
+   // Define FSM states
+   parameter [2:0]  state_type_idle = 3'd0,
+                    state_type_configure = 3'd1,
+                    state_type_transmitting = 3'd2,
+                    state_type_recieving = 3'd3,
+                    state_type_finished = 3'd4,
+                    state_type_break = 3'd5,
+                    state_type_holding = 3'd6;
+   // STATE reg
+   reg [2:0]        STATE;
+   
+   parameter [1:0]  data_type_x_axis = 2'd0,
+                    data_type_y_axis = 2'd1,
+                    data_type_z_axis = 2'd2;
+   reg [1:0]        DATA;
+   
+   parameter [1:0]  configure_type_powerCtl = 0,
+                    configure_type_bwRate = 1,
+                    configure_type_dataFormat = 2;
+   reg [1:0]        CONFIGUREsel;
+   
+   //Setting up Configuration Registers
+   //POWER_CTL Bits 0x2D
+   parameter [15:0] POWER_CTL = 16'h2D08;
+   //BW_RATE Bits 0x2C
+   parameter [15:0] BW_RATE = 16'h2C08;
+   //CONFIG Bits 0x31
+   parameter [15:0] DATA_FORMAT = 16'h3100;
+   
+   //Axis registers set to only read and do it in single byte increments
+   parameter [15:0] xAxis0 = 16'hB200;		//10110010;
+   parameter [15:0] xAxis1 = 16'hB300;		//10110011;
+   parameter [15:0] yAxis0 = 16'hB400;		//10110100;
+   parameter [15:0] yAxis1 = 16'hB500;		//10110101;
+   parameter [15:0] zAxis0 = 16'hB600;		//10110110;
+   parameter [15:0] zAxis1 = 16'hB700;		//10110111;
+   
+   reg [11:0]       break_count;
+   reg [20:0]       hold_count;
+   reg              end_configure;
+   reg              done_configure;
+   reg              register_select;
+   reg              finish;
+   reg              sample_done;
+   reg [3:0]        prevstart;
+   
+//  ===================================================================================
+// 							  				Implementation
+//  ===================================================================================
+   
+   
+		//-----------------------------------------------
+		//						Master Controller
+		//-----------------------------------------------
+		always @(posedge clk)
+		begin: spi_masterProcess
+			begin
+				// Debounce Start Button
+				prevstart <= {prevstart[2:0], start};
+				//Reset Condition
+				if (rst == 1'b1) begin
+					transmit <= 1'b0;
+					STATE <= state_type_idle;
+					DATA <= data_type_x_axis;
+					break_count <= 12'h000;
+					hold_count <= 21'b000000000000000000000;
+					done_configure <= 1'b0;
+					CONFIGUREsel <= configure_type_powerCtl;
+					txdata <= 16'h0000;
+					register_select <= 1'b0;
+					sample_done <= 1'b0;
+					finish <= 1'b0;
+					x_axis_data <= 10'b0000000000;
+					y_axis_data <= 10'b0000000000;
+					z_axis_data <= 10'b0000000000;
+					end_configure <= 1'b0;
+				end
+				else
+					//Main State, selects what the overall system is doing
+					case (STATE)
+						state_type_idle :
+							//If the system has not been configured, enter the configure state
+							if (done_configure == 1'b0) begin
+								STATE <= state_type_configure;
+								txdata <= POWER_CTL;
+								transmit <= 1'b1;
+							end
+							//If the system has been configured, enter the transmission state when start is asserted
+							else if (prevstart == 4'b0011 & start == 1'b1 & done_configure == 1'b1) begin
+								STATE <= state_type_transmitting;
+								finish <= 1'b0;
+								txdata <= xAxis0;
+								sample_done <= 1'b0;
+							end
+						state_type_configure :
+							//Substate of configure selects what configuration is output
+							case (CONFIGUREsel)
+								//Send power control address with desired configuration bits
+								configure_type_powerCtl : begin
+										STATE <= state_type_finished;
+										CONFIGUREsel <= configure_type_bwRate;
+										transmit <= 1'b1;
+									end
+								//Send band width rate address with desired configuration bits
+								configure_type_bwRate : begin
+										txdata <= BW_RATE;
+										STATE <= state_type_finished;
+										CONFIGUREsel <= configure_type_dataFormat;
+										transmit <= 1'b1;
+									end
+								//Send data format address with desired configuration bits
+								configure_type_dataFormat : begin
+										txdata <= DATA_FORMAT;
+										STATE <= state_type_finished;
+										transmit <= 1'b1;
+										finish <= 1'b1;
+										end_configure <= 1'b1;
+									end
+								default :
+									;
+							endcase
+						
+						//transmitting leads to the transmission of addresses of data to sample them
+						state_type_transmitting :
+							//Substate of transmitting selects which data register will be sampled
+							case (DATA)
+								//Selects the x_axis data
+								data_type_x_axis :
+									//register_select chooses which of the two registers for each axis 
+									//will be sampled
+									case (register_select)
+										1'b0 :
+											begin
+												//in each case for data and register_select the state goes to 
+												//recieving to accept data from SPIinterface and transmit goes
+												//high to begin the transmission of data to the ACL
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+										default :
+											begin
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+									endcase
+								data_type_y_axis :
+									case (register_select)
+										1'b0 :
+											begin
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+										default :
+											begin
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+									endcase
+								data_type_z_axis :
+									case (register_select)
+										1'b0 :
+											begin
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+										default :
+											begin
+												STATE <= state_type_recieving;
+												transmit <= 1'b1;
+											end
+									endcase
+								default :
+									;
+							endcase
+						
+						//recieving controls the flow of data into the spi_master
+						state_type_recieving :
+							//Substate of Recieving, DATA controls where data will be stored
+							case (DATA)
+								//Substate of DATA same as in transmitting
+								data_type_x_axis :
+									//register_select controls which half of the output register the 
+									//collected data goes to
+									case (register_select)
+										1'b0 :
+											begin
+												//transmit de-asserted as transmission has already be begun
+												transmit <= 1'b0;
+												//when done is asserted, the register to be sampled next
+												//changes with txdata, data is assigned to the desired output,
+												//the overall state goes to finish, and register select is 
+												//inverted to go to the other half. this same purpose is used
+												//throughout DATA in recieving
+												if (done == 1'b1)
+												begin
+													txdata <= xAxis1;
+													x_axis_data[7:0] <= rxdata[7:0];
+													STATE <= state_type_finished;
+													register_select <= 1'b1;
+												end
+											end
+										default :
+											begin
+												transmit <= 1'b0;
+												if (done == 1'b1)
+												begin
+													txdata <= yAxis0;
+													x_axis_data[9:8] <= rxdata[1:0];
+													register_select <= 1'b0;
+													DATA <= data_type_y_axis;
+													STATE <= state_type_finished;
+												end
+											end
+									endcase
+								data_type_y_axis :
+									case (register_select)
+										1'b0 :
+											begin
+												transmit <= 1'b0;
+												if (done == 1'b1)
+												begin
+													txdata <= yAxis1;
+													y_axis_data[7:0] <= rxdata[7:0];
+													register_select <= 1'b1;
+													STATE <= state_type_finished;
+												end
+											end
+										default :
+											begin
+												transmit <= 1'b0;
+												if (done == 1'b1)
+												begin
+													txdata <= zAxis0;
+													y_axis_data[9:8] <= rxdata[1:0];
+													register_select <= 1'b0;
+													DATA <= data_type_z_axis;
+													STATE <= state_type_finished;
+												end
+											end
+									endcase
+								data_type_z_axis :
+									case (register_select)
+										1'b0 :
+											begin
+												transmit <= 1'b0;
+												if (done == 1'b1)
+												begin
+													txdata <= zAxis1;
+													z_axis_data[7:0] <= rxdata[7:0];
+													register_select <= 1'b1;
+													STATE <= state_type_finished;
+												end
+											end
+										default :
+											begin
+												transmit <= 1'b0;
+												if (done == 1'b1)
+												begin
+													txdata <= xAxis0;
+													z_axis_data[9:8] <= rxdata[1:0];
+													register_select <= 1'b0;
+													DATA <= data_type_x_axis;
+													STATE <= state_type_finished;
+													sample_done <= 1'b1;
+												end
+											end
+									endcase
+								default :
+									;
+							endcase
+						
+						//finished leads to the break state when transmission completed
+						state_type_finished :
+							begin
+								transmit <= 1'b0;
+								if (done == 1'b1)
+								begin
+									STATE <= state_type_break;
+									if (end_configure == 1'b1)
+										done_configure <= 1'b1;
+								end
+							end
+						
+						//the break state keeps an idle state long enough between transmissions 
+						//to satisfy timing requirements. break can be decreased if desired
+						state_type_break :
+							if (break_count == 12'hFFF)
+							begin
+								break_count <= 12'h000;
+								//only exit to idle if start has been de-asserted ( to keep from 
+								//looping transmitting and recieving undesirably ) and finish and 
+								//sample_done are high showing that the desired action has been 
+								//completed
+								if ((finish == 1'b1 | sample_done == 1'b1) & start == 1'b0)
+								begin
+									STATE <= state_type_idle;
+									txdata <= xAxis0;
+								end
+								//if done configure is high, and sample done is low, the reception
+								//has not been completed so the state goes back to transmitting
+								else if (sample_done == 1'b1 & start == 1'b1)
+									STATE <= state_type_holding;
+								else if (done_configure == 1'b1 & sample_done == 1'b0)
+								begin
+									STATE <= state_type_transmitting;
+									transmit <= 1'b1;
+								end
+								//if the system has not finished configuration, then the state loops
+								//back to configure
+								else if (done_configure == 1'b0)
+									STATE <= state_type_configure;
+							end
+							else
+								break_count <= break_count + 1'b1;
+						state_type_holding :
+							if (hold_count == 24'h1FFFFF)
+							begin
+								hold_count <= 21'd0;
+								STATE <= state_type_transmitting;
+								sample_done <= 1'b0;
+							end
+							else if (start <= 1'b0)
+							begin
+								STATE <= state_type_idle;
+								hold_count <= 21'd0;
+							end
+							else begin
+								hold_count <= hold_count + 1'b1;
+							end
+					endcase
+			end
+		end
+   
+endmodule
+
diff --git a/Upduino_Camera/Microcontroller/ESP_Image_Upload.ino b/Upduino_Camera/Microcontroller/ESP_Image_Upload.ino
new file mode 100644
index 0000000..13b89ef
--- /dev/null
+++ b/Upduino_Camera/Microcontroller/ESP_Image_Upload.ino
@@ -0,0 +1,174 @@
+
+#include "SPIFFS.h"
+#include <SPI.h>
+
+#define CSPIN  5  // A1 for IU board
+//
+//SPI pins
+//SSN  = ESP pin 10  = UPDuino pin 46
+//SCK  = ESP pin 13 = UPDuino pin 47
+//MOSI = ESP pin 11 = UPDuino pin 48
+//MISO = ESP pin 12 = UPDuino pin 45
+
+int i = 0;
+int j = 0;
+byte pixdata;
+int address;
+  
+void setup(void)
+{
+  pinMode(CSPIN, OUTPUT);
+  SPI.begin(); 
+  digitalWrite(CSPIN, HIGH);
+  Serial.begin(115200);
+  if(!SPIFFS.begin(true)){
+       Serial.println("An Error has occurred while mounting SPIFFS");
+       return;
+  }
+  delay(4000);
+  File file = SPIFFS.open("/data.txt", FILE_WRITE);
+  if(!file){
+      Serial.println("There was an error opening the file for writing");
+      return;
+  }
+  file.println("424D36DC05000000000036000000280000004001000090010000010018000000000000DC050000000000000000000000000000000000");
+  //adds bitmap header
+  //Serial.println("424D36DC05000000000036000000280000004001000090010000010018000000000000DC050000000000000000000000000000000000");   
+  digitalWrite(CSPIN, LOW);
+  
+  //wait at least 1/30fps = 33.333ms for last frame to finish writing in FPGA
+  delay(100);
+  
+  while(j<400)
+  {
+    while(i<320) 
+    {
+    
+      address = j*320+i;
+      if(j==0 && i==0)
+        pixdata = readRegister(0x0, 1);
+      else
+        pixdata = readRegisterDataOnly(1);
+      
+      if(pixdata<16)
+      { 
+//        Serial.print("0"); //hex print prints "0" instead of "00", so this fixes it
+//        Serial.print(pixdata, HEX);
+//        Serial.print("0"); //hex print prints "0" instead of "00", so this fixes it
+//        Serial.print(pixdata, HEX);
+//        Serial.print("0"); //hex print prints "0" instead of "00", so this fixes it
+//        Serial.print(pixdata, HEX);
+        file.print("0"); //hex print prints "0" instead of "00", so this fixes it
+        file.print(pixdata, HEX);
+        file.print("0"); //hex print prints "0" instead of "00", so this fixes it
+        file.print(pixdata, HEX);
+        file.print("0"); //hex print prints "0" instead of "00", so this fixes it
+        file.print(pixdata, HEX);    
+      }
+      else
+      {      
+//        Serial.print(pixdata, HEX); //the address is only used the first time CSPIN is set low.  After that the address is automatically incremented in the fpga design.
+//        Serial.print(pixdata, HEX); //print 3 times to make the 8-bit monochrome value 24 bit RGB
+//        Serial.print(pixdata, HEX);      
+        file.print(pixdata, HEX); //the address is only used the first time CSPIN is set low.  After that the address is automatically incremented in the fpga design.
+        file.print(pixdata, HEX); //print 3 times to make the 8-bit monochrome value 24 bit RGB
+        file.print(pixdata, HEX);    
+      }      
+      
+      i++;
+    }
+    
+    i = 0;
+    j++;
+    file.print("\n");
+  //  Serial.print("\n");
+
+  }
+  file.close();  
+  
+  digitalWrite(CSPIN, HIGH);   
+  
+  File file2 = SPIFFS.open("/data.txt");
+      if(!file2){
+        Serial.println("Failed to open file for reading");
+        return;
+    }
+  delay(50);
+   while(file2.available()) {
+    Serial.print(file2.read());
+   }
+   file2.close();
+
+}
+
+void loop(void)
+{
+}
+
+//Read data from FPGA over SPI
+unsigned int readRegisterDataOnly(int bytesToRead) {
+  byte inByte = 0;           // incoming byte from the SPI
+  unsigned int result = 0;   // result to return
+  
+  // send a value of 0 to read the first byte returned:
+  result = SPI.transfer(0x00);
+  
+  // decrement the number of bytes left to read:
+  bytesToRead--;
+  
+  // if you still have another byte to read:
+  if (bytesToRead > 0) {
+    // shift the first byte left, then get the second byte:
+    result = result << 8;
+    inByte = SPI.transfer(0x00);
+    
+    // combine the byte you just got with the previous one:
+    result = inByte;
+    // decrement the number of bytes left to read:
+    bytesToRead--;
+  }
+  
+  // take the chip select high to de-select:
+  //digitalWrite(CSPIN, HIGH);
+  
+  // return the result:
+  return (result);
+}
+
+//Initiate and read data from FPGA over SPI
+unsigned int readRegister(byte thisRegister, int bytesToRead) {
+  byte inByte = 0;           // incoming byte from the SPI
+  unsigned int result = 0;   // result to return
+  
+  // now combine the address and the command into one byte
+  byte dataToSend = thisRegister ;//& READ;
+  
+  // send the device the register you want to read:
+  SPI.transfer(dataToSend);
+  
+  // send a value of 0 to read the first byte returned:
+  result = SPI.transfer(0x00);
+  
+  // decrement the number of bytes left to read:
+  bytesToRead--;
+  
+  // if you still have another byte to read:
+  if (bytesToRead > 0) {
+  
+    // shift the first byte left, then get the second byte:
+    result = result << 8;
+    inByte = SPI.transfer(0x00);
+    
+    // combine the byte you just got with the previous one:
+    result = inByte;
+    
+    // decrement the number of bytes left to read:
+    bytesToRead--;
+  }
+  
+  // take the chip select high to de-select:
+  //digitalWrite(CSPIN, HIGH);
+  // return the result:
+  return (result);
+}
+
diff --git a/Upduino_Camera/README.md b/Upduino_Camera/README.md
new file mode 100644
index 0000000..36d71e9
--- /dev/null
+++ b/Upduino_Camera/README.md
@@ -0,0 +1,7 @@
+# FPGA-Camera
+Loads SPI controller onto Upduino board and sends image to ESP32, where file contents are stored and uploaded to serial monitor.
+
+Use open-source toolchain to load verilog files onto Upduino. Use Yosys to convert verilog to BLIF file, Arachne-pnr as place and route tool, and Icestorm 
+to flash Upduino. 
+
+Connect Upduino board and ESP32. Upload ino file to ESP32 and open serial monitor to recieve data stream. Copy data stream into HxD program and save as .bmp.
\ No newline at end of file
diff --git a/Upduino_Camera/Upduino/I2C_Interface.v b/Upduino_Camera/Upduino/I2C_Interface.v
new file mode 100644
index 0000000..f727ec2
--- /dev/null
+++ b/Upduino_Camera/Upduino/I2C_Interface.v
@@ -0,0 +1,162 @@
+// Created By: Tritai Nguyen
+// I2C_Interface.v
+// Date : 03/07/2020
+
+module I2C_Interface ( 
+    input clk,                                  // 50Mhz clock signal
+    inout siod,                                 // Data signal for SCCB
+    output sioc,                                // Clock signal for SCCB
+    output taken,                               // Flag to go to next address of LUT
+    input send,                                 // Flag to indicate if configuration is finshed
+    input [7:0] rega,                           // Resgister address
+    input [7:0] value);                         // Data to write into a regsiter address
+                            
+    
+    // Internal signals
+    reg [7:0] divider = 8'b00000001;
+    reg [31:0] busy_sr = {32{1'b0}};
+    reg [31:0] data_sr = {32{1'b1}};
+    reg sioc_temp;
+    reg taken_temp;
+    reg siod_temp;
+    
+    // ID of an OV7670 for SCCB protocol
+    localparam id = 8'h42;
+    
+    // Assign value for outputs
+    assign siod = siod_temp;
+    assign sioc = sioc_temp;
+    assign taken = taken_temp;
+    
+    always @ (busy_sr or data_sr[31]) begin
+        // when the bus is idle SIOD must be tri-state
+        if(busy_sr[11:10] == 2'b10 || busy_sr[20:19] == 2'b10 || busy_sr[29:28] == 2'b10) begin
+            siod_temp <= 1'bZ;
+        end
+        // else SIOD will be driven my master (FPGA board)
+        else begin
+            siod_temp <= data_sr[31];
+        end
+    end
+        
+    always @ (posedge clk) begin
+        taken_temp <= 1'b0;
+        
+        // If all 31 bits are transmitted 
+        if(busy_sr[31] == 0) begin
+            // Assert SIOC high for starting new transmission
+            sioc_temp <= 1;
+            
+            // If New data is arrived from LUT 
+            if(send == 1) begin
+                if(divider == 8'b00000000) begin
+                    // Create an data to send through the data signal of the SCCB
+                    // The data is created using 3-phase write transmission cycle of SCCB protocol
+                    //
+                    // Data:  
+                    // 3'b100 --> SIOD will go from 1 to 0 to indicate a start transmission
+                    //            the last bit is an don't care bit
+                    // id     --> the ID of a slave (8'h42). The last bit of the slave is 0 inidicate a write transaction
+                    // 1'b0   --> don't care bit to seperate phases
+                    // rega   --> register address that want to write into
+                    // 1'b0   --> don't care bit to seperate phases
+                    // value  --> data to write into the register address
+                    // 1'b0   --> don't care bit to seperate phases
+                    // 2'b01  --> SIOD will go from 0 to 1 to indicate a stop tranmission
+                    
+                    data_sr <= {3'b100, id, 1'b0, rega, 1'b0, value, 1'b0, 2'b01};
+                    busy_sr <= {3'b111, 9'b111111111, 9'b111111111, 9'b111111111, 2'b11};
+                    taken_temp <= 1'b1;
+                end
+                else begin
+                    divider <= divider + 1;
+                end
+            end
+            
+        end
+        
+        // Implement two-write data transmission of SCCB protocol
+        else begin
+            case ({busy_sr[31:29],busy_sr[2:0]})        // Checking for the start and stop condition
+                // For START condition
+                6'b111_111: begin                       // bit 31th of data_sr is transmitted, SIOC must be high
+                    case (divider[7:6])                 // --> SIOD goes from tri-state to high             
+                        2'b00: sioc_temp <= 1;          
+                        2'b01: sioc_temp <= 1;          
+                        2'b10: sioc_temp <= 1;          
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+                
+                6'b111_110: begin                       // bit 30th of data_sr is transmitted
+                    case (divider[7:6])                 // --> SIOD goes from high to low, SIOC must be high
+                        2'b00: sioc_temp <= 1;          // --> complete START condition
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b111_100: begin                       // bit 29th of data_sr is transmitted (don't care bit)
+                    case (divider[7:6])                 // --> SIOD goes from tri-state to high, then high to low 
+                        2'b00: sioc_temp <= 0;          //     after SIOC goes from high to low 
+                        2'b01: sioc_temp <= 0;          // --> Ready for first transmission from Master to Slave
+                        2'b10: sioc_temp <= 0;
+                        default: sioc_temp <= 0;
+                    endcase
+                end
+            
+                // For STOP condition
+                6'b110_000: begin                       // bit 2nd of data_sr is transmitted (don't care bit)
+                    case (divider[7:6])                 // SIOC waits for 1 clock cyle of 200Khz then go high    
+                        2'b00: sioc_temp <= 0;
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b100_000: begin                       // bit 1st of data_sr is transmitted
+                    case (divider[7:6])                 // SIOD is low
+                        2'b00: sioc_temp <= 1;          // SIOC must be high
+                        2'b01: sioc_temp <= 1;
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+            
+                6'b000_000: begin                       // bit 0th of data_sr is transmitted
+                    case (divider[7:6])                 // SIOD is high
+                        2'b00: sioc_temp <= 1;          // --> SIOD goes from low to high while SIOC is high
+                        2'b01: sioc_temp <= 1;          // --> complete STOP condition for SCCB protocol    
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 1;
+                    endcase
+                end
+                
+                // Between START and STOP condition
+                // SIOC is high on 2 cycles of 400Khz and low on 2 cycle of 400Khz
+                // --> SIOC is 200Khz
+                default: begin                          
+                    case (divider[7:6])
+                        2'b00: sioc_temp <= 0;          
+                        2'b01: sioc_temp <= 1;          
+                        2'b10: sioc_temp <= 1;
+                        default: sioc_temp <= 0;
+                    endcase
+                end
+            endcase
+        
+            // Create a frequency for SCCB with is 200KHz
+            if(divider == 8'b11111111) begin
+                busy_sr <= {busy_sr[30:0], 1'b0};        // Update number of bit that get transmitted
+                data_sr <= {data_sr[30:0], 1'b1};        // Update new bit 31th by bit 30th
+                divider <= {8{1'b0}};                   // Reset counter for clock divider
+            end
+            else begin
+                divider <= divider + 1;
+            end
+        
+        end
+    end
+endmodule
\ No newline at end of file
diff --git a/Upduino_Camera/Upduino/OV7670_Controller.v b/Upduino_Camera/Upduino/OV7670_Controller.v
new file mode 100644
index 0000000..016cc43
--- /dev/null
+++ b/Upduino_Camera/Upduino/OV7670_Controller.v
@@ -0,0 +1,53 @@
+// Created By: Tritai Nguyen
+// OV7670_Controller.v
+// Date : 03/07/2020
+
+module OV7670_Controller (
+    input clk,                              // 50Mhz clock signal
+    input resend,                           // Reset signal
+    output config_finished,                 // Flag to indicate that the configuration is finished
+    output sioc,                            // SCCB interface - clock signal
+    inout siod,                             // SCCB interface - data signal
+    output reset,                           // RESET signal for OV7670
+    output pwdn                             // PWDN signal for OV7670
+);
+
+    // Internal signals
+    wire [15:0] command;
+    wire finished;
+    wire taken;
+    reg send = 0;
+   
+    // Signal for testing
+    assign config_finished = finished;
+    
+    // Signals for RESET and PWDN OV7670
+    assign reset = 1;
+    assign pwdn = 0;
+    
+    // Signal to indicate that the configuration is finshied    
+    always @ (finished) begin
+        send = ~finished;
+    end
+    
+    // Create an instance of a LUT table 
+    OV7670_Registers LUT(
+        .clk(clk),                          // 50Mhz clock signal
+        .advance(taken),                    // Flag to advance to next register
+        .command(command),                  // register value and data for OV7670
+        .finished(finished),                // Flag to indicate the configuration is finshed
+        .resend(resend)                     // Re-configure flag for OV7670
+    );
+    
+    // Create an instance of a SCCB interface
+    I2C_Interface I2C(
+        .clk(clk),                          // 50Mhz clock signal
+        .taken(taken),                      // Flag to advance to next register
+        .siod(siod),                        // Clock signal for SCCB interface
+        .sioc(sioc),                        // Data signal for SCCB interface 
+        .send(send),                        // Continue to configure OV7670
+        .rega(command[15:8]),               // Register address
+        .value(command[7:0])                // Data to write into register
+    );
+    
+endmodule
diff --git a/Upduino_Camera/Upduino/OV7670_Registers.v b/Upduino_Camera/Upduino/OV7670_Registers.v
new file mode 100644
index 0000000..712243b
--- /dev/null
+++ b/Upduino_Camera/Upduino/OV7670_Registers.v
@@ -0,0 +1,108 @@
+// Created By: Tritai Nguyen
+// OV7670_Registers
+// Date : 03/07/2020
+
+module OV7670_Registers (
+    input clk, 
+    input resend, 
+    input advance, 
+    output [15:0] command, 
+    output finished
+);
+
+    // Internal signals
+    reg [15:0] sreg;
+    reg finished_temp;
+    reg [7:0] address = {8{1'b0}};
+    
+    // Assign values to outputs
+    assign command = sreg; 
+    assign finished = finished_temp;
+    
+    // When register and value is FFFF
+    // a flag is asserted indicating the configuration is finished
+    always @ (sreg) begin
+        if(sreg == 16'hFFFF) begin
+            finished_temp <= 1;
+        end
+        else begin
+            finished_temp <= 0;
+        end
+    end
+    
+    // Get value out of the LUT
+    always @ (posedge clk) begin
+        if(resend == 1) begin           // reset the configuration
+            address <= {8{1'b0}};
+        end
+        else if(advance == 1) begin     // Get the next value
+            address <= address+1;
+        end
+           
+        case (address) 
+            0 : sreg <= 16'h12_80;          // COM7     RESET
+            1 : sreg <= 16'h12_80;          // COM7     RESET
+            2 : sreg <= 16'h12_00;          // COM7     Size & YUV output
+            3 : sreg <= 16'h11_00;          // CLKRC    Use internal clock
+            4 : sreg <= 16'h0C_00;          // COM3     Default
+            5 : sreg <= 16'h3E_00;          // COM14    SDCW and scaling PCLK, manual scaling enable, PCLK divider          
+            6 : sreg <= 16'h8C_00;          // RGB444   Disable RGB 444 format
+            7 : sreg <= 16'h04_00;          // COM1     Disable CCIR 656
+            8 : sreg <= 16'h40_00;          // COM15    Disable RGB 565 (effective only after disable RGB 444 format)
+            9 : sreg <= 16'h3A_04;          // TSLB     Disable auto-reset window
+            10 : sreg <= 16'h14_6A;         // COM9     Set auto gain ceiling to x16 
+            11 : sreg <= 16'h4F_40;         // MTX1     matrix coefficient 1(default)
+            12 : sreg <= 16'h50_34;         // MTX2     matrix coefficient 2(default)
+            13 : sreg <= 16'h51_0C;         // MTX3     matrix coefficient 3(default)
+            14 : sreg <= 16'h52_17;         // MTX4     matrix coefficient 4(default)
+            15 : sreg <= 16'h53_29;         // MTX5     matrix coefficient 5(default)
+            16 : sreg <= 16'h54_40;         // MTX6     matrix coefficient 6(default)
+            17 : sreg <= 16'h58_1E;         // MTXS     default
+            18 : sreg <= 16'h3D_C0;         // COM13    Turn on GAMMA and auto UV adjust
+            19 : sreg <= 16'h11_00;         // CLKRC    Use internal clock 
+            20 : sreg <= 16'h17_16;         // HSTART   Horizontal Frame start (high 8 bits)
+            21 : sreg <= 16'h18_04;         // HSTOP    Horizontal Frame stop (high 8 bits)
+            22 : sreg <= 16'h32_A4;         // HREF     set Horizontal Frame control
+            23 : sreg <= 16'h19_02;         // VSTART   Vertical Frame start (high 8 bits)
+            24 : sreg <= 16'h1A_7A;         // VSTOP    Vertical Frame stop (high 8 bits)
+            25 : sreg <= 16'h03_0A;         // VREF     set Vertical Frame control
+            26 : sreg <= 16'h0E_61;         // COM5     reserve
+            27 : sreg <= 16'h0F_4B;         // COM6     Enable HREF at optical black
+            28 : sreg <= 16'h16_02;         // RSVD     reserve
+            29 : sreg <= 16'h1E_17;         // MVFP     detect mirror image and enable flip image
+            30 : sreg <= 16'h21_02;         // ADCCTR1  reserve
+            31 : sreg <= 16'h22_91;         // ADCCTR2  reserve
+            32 : sreg <= 16'h29_07;         // RSVD     reserve
+            33 : sreg <= 16'h33_0B;         // CHLF     reserve
+            34 : sreg <= 16'h35_0B;         // RSVD     reserve
+            35 : sreg <= 16'h37_1D;         // ADC      reserve
+            36 : sreg <= 16'h38_71;         // ACOM     reserve
+            37 : sreg <= 16'h39_2A;         // OFON     reserve
+            38 : sreg <= 16'h3C_78;         // COM12    Set to no HREF when VSYNC is low
+            39 : sreg <= 16'h4D_40;         // RSVD     reserve
+            40 : sreg <= 16'h4E_20;         // RSVD     reserve
+            41 : sreg <= 16'h69_00;         // GFIX     Fix gain control (default)
+            42 : sreg <= 16'h6B_4A;         // DBLV     set PLL control to 4x and bypass internal regulator
+            43 : sreg <= 16'h70_3A;          // SCALING_XSC
+            44 : sreg <= 16'h71_35;          // SCALING_YSC
+            45 : sreg <= 16'h72_11;          // SCALING_DCWCTR
+            46 : sreg <= 16'h73_F0;          // SCALING_PCLK_DIV
+            47 : sreg <= 16'h74_10;         // REG74    default
+            48 : sreg <= 16'h8D_4F;         // RSVD     reserve
+            49 : sreg <= 16'h8E_00;         // RSVD     reserve
+            50 : sreg <= 16'h8F_00;         // RSVD     reserve
+            51 : sreg <= 16'h90_00;         // RSVD     reserve
+            52 : sreg <= 16'h91_00;         // RSVD     reserve
+            53 : sreg <= 16'h96_00;         // RSVD     reserve
+            54 : sreg <= 16'h9A_00;         // RSVD     reserve
+            55 : sreg <= 16'hA2_02;          // SCALING_PCLK_DELAY
+            56 : sreg <= 16'hB0_84;         // RSVD     reserve
+            57 : sreg <= 16'hB1_0C;         // ABLC1    disable ABLC function
+            58 : sreg <= 16'hB2_0E;         // RSVD     reserve
+            59 : sreg <= 16'hB3_82;         // RSVD     reserve
+            60 : sreg <= 16'hB8_0A;         // RSVD     reserve
+            default : sreg <= 16'hFF_FF;    // End configuration
+        endcase  
+            
+    end
+endmodule
\ No newline at end of file
diff --git a/Upduino_Camera/Upduino/spi_slave.v b/Upduino_Camera/Upduino/spi_slave.v
new file mode 100644
index 0000000..bc54efd
--- /dev/null
+++ b/Upduino_Camera/Upduino/spi_slave.v
@@ -0,0 +1,143 @@
+// Created By: Tritai Nguyen
+// spi_slave.v
+// Date : 03/07/2020
+
+module spi_slave (
+  input           clk,
+  input           reset_n,
+  
+  input           sclk,
+  input           mosi,
+  input           ssel,
+  output          miso,
+  
+  output [16:0]   mem_addr,
+  input  [7:0]    mem_data  
+  );
+  
+  
+  reg    [1:0]    sclk_reg;
+  reg    [1:0]    mosi_reg;
+  reg    [2:0]    bit_cnt;
+  wire   [7:0]    data_to_send;
+  reg    [7:0]    data_to_send_buf;
+  reg    [7:0]    data_received;
+  reg             byte_received;
+  reg             addr_data_flag;
+  
+  reg    [16:0]   rd_addr_reg;
+  
+  wire            sclk_rising_edge = (sclk_reg == 2'b01);
+  wire            sclk_falling_edge = (sclk_reg == 2'b10);
+  wire            mosi_data = mosi_reg[1];
+  
+  assign          miso = data_to_send_buf[7];
+  assign          mem_addr = rd_addr_reg;
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        sclk_reg <= 2'b00;
+      else
+      if (ssel)
+        sclk_reg <= 2'b00;
+      else
+        sclk_reg <= {sclk_reg[0], sclk};      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        mosi_reg <= 2'b00;
+      else
+      if (ssel)
+        mosi_reg <= 2'b00;
+      else
+        mosi_reg <= {mosi_reg[0], mosi};      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        begin
+          bit_cnt <= 3'h0;
+          data_received <= 8'h00;
+        end
+      else
+      if (ssel)
+        begin
+          bit_cnt <= 3'h0;
+          data_received <= 8'h00;        
+        end
+      else
+      if (sclk_rising_edge)
+        begin
+          bit_cnt <= bit_cnt + 3'h1;
+          data_received <= {data_received[6:0], mosi_data};
+        end
+      else
+        begin
+          bit_cnt <= bit_cnt;
+          data_received <= data_received;
+        end        
+    end
+    
+  always @ (posedge clk or negedge reset_n)  
+    begin
+      if (!reset_n)
+        byte_received <= 1'b0;
+      else
+      if ((!ssel) && sclk_rising_edge && (bit_cnt == 3'h7)) 
+        byte_received <= 1'b1;
+      else
+        byte_received <= 1'b0;      
+    end
+    
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        data_to_send_buf <= 8'h00;
+      else
+      if (ssel)
+        data_to_send_buf <= 8'h00;
+      else
+      if ((bit_cnt == 3'h0) && sclk_falling_edge)
+        data_to_send_buf <= data_to_send;
+      else
+      if (sclk_falling_edge)
+        data_to_send_buf <= {data_to_send_buf[6:0], 1'b0};
+      else
+        data_to_send_buf <= data_to_send_buf;      
+    end    
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        addr_data_flag <= 1'b0;
+      else
+      if (ssel)
+        addr_data_flag <= 1'b0;
+      else
+      if ((!ssel) && byte_received)
+        addr_data_flag <= 1'b1;
+      else
+        addr_data_flag <= addr_data_flag;      
+    end
+  
+  always @ (posedge clk or negedge reset_n)
+    begin
+      if (!reset_n)
+        rd_addr_reg <= 17'h00000;
+      else
+      if ((!addr_data_flag) && byte_received)     
+        rd_addr_reg <= {9'h000, data_received};
+      else
+      if (addr_data_flag && byte_received)
+        rd_addr_reg <= rd_addr_reg + 17'h00001;
+      else
+        rd_addr_reg <= rd_addr_reg;      
+    end  
+
+  assign          data_to_send = mem_data;
+  
+endmodule  
\ No newline at end of file
diff --git a/Upduino_Camera/Upduino/top.v b/Upduino_Camera/Upduino/top.v
new file mode 100644
index 0000000..b825e6f
--- /dev/null
+++ b/Upduino_Camera/Upduino/top.v
@@ -0,0 +1,135 @@
+// Created By: Tritai Nguyen
+// top.v
+// Date : 03/07/2020
+
+module top (
+ 
+  output          xclk,
+  input           pclk,
+  input           vsync,
+  input           href,
+  input  [7:0]    pdata,
+  output          cam_reset_n,
+  output          cam_pwrdn,
+  
+  output          sioc,
+  inout           siod,
+  
+  input           sclk,
+  input           mosi,
+  output          miso,
+  input           ssel  
+
+  );
+  
+  wire            clk_24m /* synthesis syn_keep=1 */;
+  
+  reg    [17:0]   pixel_cnt;
+  reg             pixel_wr_disable;
+  wire            cam_config_done;
+  
+  wire   [16:0]   mem_rd_addr;
+  wire   [7:0]    mem_rd_data;
+  wire            reset_n = 1'b1;
+  reg             q_vsync, q_href;
+  //considering two bytes per pixel, taking only one byte out of two by having condition (pixel_cnt[0] == 1'b0)
+  wire            pixel_wr = q_href && (!pixel_wr_disable) && (pixel_cnt[0]==0);
+  wire            xclk_in;  
+  
+  reg    [7:0]    q_pdata;
+
+  reg    [15:0]   pix_per_line;
+  
+  always @(posedge pclk)
+    begin
+      q_pdata <= pdata;
+      q_vsync <= vsync;
+      q_href  <= href & (pix_per_line < (320*2));  
+    end
+
+  assign          xclk = clk_24m;
+
+  always @ (posedge pclk)
+    begin
+      pix_per_line <= href ? pix_per_line+1 : 0;
+    end
+
+  //Manage address for writing in DPRAM through pixel counter
+  always @ (posedge pclk)
+    begin
+      if (!reset_n)
+        begin
+          pixel_cnt    <= 18'h00000;
+        end
+      else
+      if (q_vsync)
+        begin
+          pixel_cnt    <= 18'h00000;
+        end
+      else
+      if (q_href) 
+        begin
+          pixel_cnt    <= (pixel_cnt<(320*400*2))    ?  pixel_cnt + 18'h00001 : pixel_cnt;
+        end
+      else
+        begin
+          pixel_cnt <= pixel_cnt;     
+        end  
+    end    
+    
+	
+  //Disable pixel data write from next frame if SPI transfer has been initiated
+  always @ (posedge pclk)
+    begin
+      if (q_vsync)
+        pixel_wr_disable <= !ssel;
+      else
+        pixel_wr_disable <= pixel_wr_disable;
+    end
+  
+  SB_HFOSC  u_SB_HFOSC (
+    .CLKHFPU  (1'b1), 
+    .CLKHFEN  (1'b1), 
+    .CLKHF    (xclk_in)
+  ); 
+  defparam u_SB_HFOSC.CLKHF_DIV = "0b01";  
+
+  assign clk_24m = xclk_in;
+
+  up_spram cam_buf (
+    .reset_n  (reset_n),
+    
+    .wr_clk   (pclk ),
+    .wr_addr  ({pixel_cnt[17:1]}),
+    .wr_data  (q_pdata ),  
+    .wr_en    (pixel_wr),
+    
+    .rd_clk   (pclk ),
+    .rd_addr  (mem_rd_addr),
+    .rd_data  (mem_rd_data)
+    );  
+  
+  OV7670_Controller u_OV7670_Controller(
+    .clk             (clk_24m),          // 24Mhz clock signal
+    .resend          (1'b0),             // Reset signal
+    .config_finished (cam_config_done),  // Flag to indicate that the configuration is finished
+    .sioc            (sioc),             // SCCB interface - clock signal
+    .siod            (siod),             // SCCB interface - data signal
+    .reset           (cam_reset_n),      // RESET signal for OV7670
+    .pwdn            (cam_pwrdn)         // PWDN signal for OV7670
+  );  
+  
+  spi_slave esp32_spi (
+    .clk      (pclk ),
+    .reset_n  (reset_n),
+
+    .sclk     (sclk),
+    .mosi     (mosi),
+    .ssel     (ssel),
+    .miso     (miso),
+
+    .mem_addr (mem_rd_addr),
+    .mem_data (mem_rd_data)  
+  );
+  
+endmodule  
\ No newline at end of file
diff --git a/Upduino_Camera/Upduino/top_pcf_sbt.pcf b/Upduino_Camera/Upduino/top_pcf_sbt.pcf
new file mode 100644
index 0000000..32ca70e
--- /dev/null
+++ b/Upduino_Camera/Upduino/top_pcf_sbt.pcf
@@ -0,0 +1,37 @@
+# ##############################################################################
+
+# iCEcube PCF
+
+# Version:            2017.01.27914
+
+# File Generated:     Feb 1 2018 09:18:04
+
+# Family & Device:    iCE40UP5K
+
+# Package:            SG48
+
+# ##############################################################################
+
+###IOSet List 21
+set_io pdata[2] 35
+set_io pdata[5] 9
+set_io ssel 46
+set_io href 25
+set_io pdata[0] 31
+set_io pdata[4] 32
+set_io siod 23 -pullup yes
+set_io mosi 48
+set_io pdata[3] 6
+set_io pdata[7] 11
+set_io sioc 13 -pullup yes
+set_io vsync 19
+set_io xclk_in 12
+set_io cam_pwrdn 37
+set_io cam_reset_n 4
+set_io pclk 18
+set_io pdata[6] 27
+set_io miso 45
+set_io pdata[1] 44
+set_io sclk 47
+set_io xclk 26
+
diff --git a/Upduino_Camera/Upduino/up_spram.v b/Upduino_Camera/Upduino/up_spram.v
new file mode 100644
index 0000000..e0da49c
--- /dev/null
+++ b/Upduino_Camera/Upduino/up_spram.v
@@ -0,0 +1,96 @@
+`timescale 1ns/1ns
+
+// Created By: Tritai Nguyen
+// up_spram.v
+// Date : 03/07/2020
+
+module up_spram (
+  input           reset_n,
+  
+  input           wr_clk,
+  input  [16:0]   wr_addr,
+  input  [7:0]    wr_data,  
+  input           wr_en,
+  
+  input           rd_clk,
+  input  [16:0]   rd_addr,
+  output [7:0]    rd_data
+  );
+
+  wire   [15:0]   ram_rdata;  
+  wire   [15:0]   ram_rdata0, ram_rdata1, ram_rdata2, ram_rdata3;  
+  wire   [16:0]   w_addr;
+  assign          w_addr = wr_en ? wr_addr : rd_addr;
+  wire   [3:0]    w_mask;
+  assign          w_mask = w_addr[16] ? 4'b1100 : 4'b0011;
+  wire   [3:0]    wr_ram;
+  assign          wr_ram[0] = ~w_addr[15] & ~w_addr[14] & wr_en;
+  assign          wr_ram[1] = ~w_addr[15] &  w_addr[14] & wr_en;
+  assign          wr_ram[2] =  w_addr[15] & ~w_addr[14] & wr_en;
+  assign          wr_ram[3] =  w_addr[15] &  w_addr[14] & wr_en;
+  
+  assign          ram_rdata = (w_addr[16:14]==3'd0) ? ram_rdata0[7:0] : 
+                              (w_addr[16:14]==3'd1) ? ram_rdata1[7:0] : 
+                              (w_addr[16:14]==3'd2) ? ram_rdata2[7:0] : 
+                              (w_addr[16:14]==3'd3) ? ram_rdata3[7:0] :
+                              (w_addr[16:14]==3'd4) ? ram_rdata0[15:8] : 
+                              (w_addr[16:14]==3'd5) ? ram_rdata1[15:8] : 
+                              (w_addr[16:14]==3'd6) ? ram_rdata2[15:8] : 
+                              (w_addr[16:14]==3'd7) ? ram_rdata3[15:8] : 0; 
+                                                  
+  assign          rd_data = ram_rdata[7:0];
+    
+  //RAM instantiations
+  SB_SPRAM256KA u_spram0 (
+    .ADDRESS      ( w_addr[13:0 ]       ),
+    .DATAIN       ( {wr_data,wr_data}   ),
+    .MASKWREN     ( w_mask              ),
+    .WREN         ( wr_ram[0]           ),
+    .CHIPSELECT   ( 1'b1                ),
+    .CLOCK        ( rd_clk              ),
+    .STANDBY      ( 1'b0                ),
+    .SLEEP        ( 1'b0                ),
+    .POWEROFF     ( 1'b1                ),
+    .DATAOUT      ( ram_rdata0          )
+    );
+    
+  SB_SPRAM256KA u_spram1 (
+    .ADDRESS      ( w_addr[13:0]        ),
+    .DATAIN       ( {wr_data,wr_data}   ),
+    .MASKWREN     ( w_mask              ),
+    .WREN         ( wr_ram[1]           ),
+    .CHIPSELECT   ( 1'b1                ),
+    .CLOCK        ( rd_clk              ),
+    .STANDBY      ( 1'b0                ),
+    .SLEEP        ( 1'b0                ),
+    .POWEROFF     ( 1'b1                ),
+    .DATAOUT      ( ram_rdata1          )
+    );
+
+  SB_SPRAM256KA u_spram2 (
+    .ADDRESS      ( w_addr[13:0]        ),
+    .DATAIN       ( {wr_data,wr_data}   ),
+    .MASKWREN     ( w_mask              ),
+    .WREN         ( wr_ram[2]           ),
+    .CHIPSELECT   ( 1'b1                ),
+    .CLOCK        ( rd_clk              ),
+    .STANDBY      ( 1'b0                ),
+    .SLEEP        ( 1'b0                ),
+    .POWEROFF     ( 1'b1                ),
+    .DATAOUT      ( ram_rdata2          )
+    );
+
+  SB_SPRAM256KA u_spram3 (
+    .ADDRESS      ( w_addr[13:0]        ),
+    .DATAIN       ( {wr_data,wr_data}   ),
+    .MASKWREN     ( w_mask              ),
+    .WREN         ( wr_ram[3]           ),
+    .CHIPSELECT   ( 1'b1                ),
+    .CLOCK        ( rd_clk              ),
+    .STANDBY      ( 1'b0                ),
+    .SLEEP        ( 1'b0                ),
+    .POWEROFF     ( 1'b1                ),
+    .DATAOUT      ( ram_rdata3          )
+    );  
+
+endmodule  
\ No newline at end of file