diff --git a/.gitmodules b/.gitmodules index 69aa470ea6a..fcfcdd66e58 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,63 +1,69 @@ [submodule "3rdparty/blobs"] path = 3rdparty/blobs - url = ../blobs.git + url = https://github.com/MrChromebox/blobs.git update = none ignore = dirty [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage - url = ../nvidia-cbootimage.git + url = https://review.coreboot.org/nvidia-cbootimage.git [submodule "vboot"] path = 3rdparty/vboot - url = ../vboot.git + url = https://review.coreboot.org/vboot.git branch = main [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware - url = ../arm-trusted-firmware.git + url = https://review.coreboot.org/arm-trusted-firmware.git [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec - url = ../chrome-ec.git + url = https://review.coreboot.org/chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase - url = ../libhwbase.git + url = https://review.coreboot.org/libhwbase.git [submodule "libgfxinit"] path = 3rdparty/libgfxinit - url = ../libgfxinit.git + url = https://review.coreboot.org/libgfxinit.git [submodule "3rdparty/fsp"] path = 3rdparty/fsp - url = ../fsp.git + url = https://review.coreboot.org/fsp.git update = none ignore = dirty [submodule "opensbi"] path = 3rdparty/opensbi - url = ../opensbi.git + url = https://review.coreboot.org/opensbi.git [submodule "intel-microcode"] path = 3rdparty/intel-microcode - url = ../intel-microcode.git + url = https://review.coreboot.org/intel-microcode.git update = none ignore = dirty branch = main [submodule "3rdparty/ffs"] path = 3rdparty/ffs - url = ../ffs.git + url = https://review.coreboot.org/ffs.git [submodule "3rdparty/amd_blobs"] path = 3rdparty/amd_blobs - url = ../amd_blobs + url = https://review.coreboot.org/amd_blobs update = none ignore = dirty [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka - url = ../cmocka.git + url = https://review.coreboot.org/cmocka.git update = none branch = stable-1.1 [submodule "3rdparty/qc_blobs"] path = 3rdparty/qc_blobs - url = ../qc_blobs.git + url = https://review.coreboot.org/qc_blobs.git update = none ignore = dirty [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools - url = ../9esec-security-tooling.git + url = https://review.coreboot.org/9esec-security-tooling.git [submodule "3rdparty/stm"] path = 3rdparty/stm - url = ../STM + url = https://review.coreboot.org/STM.git branch = stmpe +[submodule "3rdparty/purism-blobs"] + path = 3rdparty/purism-blobs + url = https://source.puri.sm/coreboot/purism-blobs.git +[submodule "3rdparty/dasharo-blobs"] + path = 3rdparty/dasharo-blobs + url = git@github.com:Dasharo/dasharo-blobs.git diff --git a/3rdparty/blobs b/3rdparty/blobs index d55c315b612..1f7232114e7 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit d55c315b6126fbcca6a3881b5be8dff1509fe7ef +Subproject commit 1f7232114e7e903f6d42916e551b119d525ce6d7 diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs new file mode 160000 index 00000000000..5b0453b6069 --- /dev/null +++ b/3rdparty/dasharo-blobs @@ -0,0 +1 @@ +Subproject commit 5b0453b6069bcc18d7094b5fde944269abe56ad4 diff --git a/3rdparty/purism-blobs b/3rdparty/purism-blobs new file mode 160000 index 00000000000..51227164fe6 --- /dev/null +++ b/3rdparty/purism-blobs @@ -0,0 +1 @@ +Subproject commit 51227164fe693042b66c7372f54057d8082dff08 diff --git a/Makefile.inc b/Makefile.inc index d2235e0c077..3379f14c781 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -407,9 +407,20 @@ ifeq ($(CONFIG_COMPRESS_PRERAM_STAGES),y) CBFS_PRERAM_COMPRESS_FLAG:=LZ4 endif +strip_version = $(strip $(subst v,,$(subst ., ,$(1)))) + ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_VERSION := $(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_MAJOR_VERSION := $(word 1,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_MINOR_VERSION := $(word 2,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_PATCH_VERSION := $(word 3,$(call strip_version,$(DASHARO_VERSION))) + COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION +COREBOOT_EXPORTS += DASHARO_VERSION +COREBOOT_EXPORTS += DASHARO_MAJOR_VERSION +COREBOOT_EXPORTS += DASHARO_MINOR_VERSION +COREBOOT_EXPORTS += DASHARO_PATCH_VERSION endif CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj) @@ -531,7 +542,9 @@ build_h := $(obj)/build.h # when we call it through the `$(shell)` function. This is fragile # but as variables newly added to `genbuild_h.sh` would just not # work, we'd notice that instantly at least. -build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION +build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION \ + DASHARO_VERSION DASHARO_MAJOR_VERSION DASHARO_MINOR_VERSION \ + DASHARO_PATCH_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ diff --git a/build-uefi.sh b/build-uefi.sh new file mode 100755 index 00000000000..70ea23c7e20 --- /dev/null +++ b/build-uefi.sh @@ -0,0 +1,41 @@ +#!/bin/bash +# + +set -e + +platforms=('snb_ivb' 'hsw' 'byt' 'bdw' 'bsw' 'skl' 'apl' 'kbl' 'whl' 'glk' \ + 'cml' 'jsl' 'tgl' 'str') +build_targets=() + +json_file=cbmodels.json +rom_path=https://www.mrchromebox.tech/files/firmware/full_rom/ +echo -e "{" > $json_file + +if [ -z "$1" ]; then + for subdir in "${platforms[@]}"; do + for cfg in configs/$subdir/config*.*; do + build_targets+=("$(basename $cfg | cut -f2 -d'.')") + done + done +else + build_targets=($@) +fi + +for device in "${build_targets[@]}"; do + filename="coreboot_tiano-${device}-mrchromebox_$(date +"%Y%m%d").rom" + rm -f ~/dev/firmware/${filename}* + rm -rf ./build + cfg_file=$(find ./configs -name "config.$device.uefi") + cp "$cfg_file" .config + make clean + make olddefconfig + make -j$(nproc) + cp ./build/coreboot.rom ./${filename} + sha1sum ${filename} > ${filename}.sha1 + echo -e "\t\"${device}\": {" >> $json_file + echo -e "\t\t\"url\": \"${rom_path}${filename}\"," >> $json_file + echo -e "\t\t\"sha1\": \"$(cat ${filename}.sha1 | awk 'NR==1{print $1}')\"" >> $json_file + echo -e "\t}," >> $json_file + mv ${filename}* ~/dev/firmware/ +done +echo -e "}" >> $json_file diff --git a/cbfs/bootorder.emmc b/cbfs/bootorder.emmc new file mode 100644 index 00000000000..280d61c2a4b --- /dev/null +++ b/cbfs/bootorder.emmc @@ -0,0 +1,7 @@ +/rom@etc/sdcard0 +/rom@etc/sdcard1 +/rom@etc/sdcard2 +/rom@etc/sdcard3 +/rom@etc/sdcard4 +/rom@etc/sdcard5 +/rom@etc/sdcard6 diff --git a/cbfs/bootorder.emmc.apl b/cbfs/bootorder.emmc.apl new file mode 100644 index 00000000000..da6673c3d22 --- /dev/null +++ b/cbfs/bootorder.emmc.apl @@ -0,0 +1 @@ +/pci@i0cf8/*@1c diff --git a/cbfs/bootorder.ssd b/cbfs/bootorder.ssd new file mode 100644 index 00000000000..095fb7237c7 --- /dev/null +++ b/cbfs/bootorder.ssd @@ -0,0 +1 @@ +/pci@i0cf8/*@1f,2/drive@0/disk@0 diff --git a/cbfs/bootorder.usb b/cbfs/bootorder.usb new file mode 100644 index 00000000000..c666c6876a3 --- /dev/null +++ b/cbfs/bootorder.usb @@ -0,0 +1,48 @@ +/pci@i0cf8/usb@14/usb-*@0 +/pci@i0cf8/usb@14/usb-*@1 +/pci@i0cf8/usb@14/usb-*@2 +/pci@i0cf8/usb@14/usb-*@3 +/pci@i0cf8/usb@14/usb-*@4 +/pci@i0cf8/usb@14/usb-*@5 +/pci@i0cf8/usb@14/usb-*@6 +/pci@i0cf8/usb@14/usb-*@7 +/pci@i0cf8/usb@14/usb-*@8 +/pci@i0cf8/usb@14/usb-*@9 +/pci@i0cf8/usb@14/usb-*@a +/pci@i0cf8/usb@14/usb-*@b +/pci@i0cf8/usb@14/usb-*@c +/pci@i0cf8/usb@14/usb-*@d +/pci@i0cf8/usb@14/usb-*@e +/pci@i0cf8/usb@14/usb-*@f +/pci@i0cf8/usb@14/hub@1/usb-*@0 +/pci@i0cf8/usb@14/hub@1/usb-*@1 +/pci@i0cf8/usb@14/hub@1/usb-*@2 +/pci@i0cf8/usb@14/hub@1/usb-*@3 +/pci@i0cf8/usb@14/hub@1/usb-*@4 +/pci@i0cf8/usb@14/hub@1/usb-*@5 +/pci@i0cf8/usb@14/hub@1/usb-*@6 +/pci@i0cf8/usb@14/hub@1/usb-*@7 +/pci@i0cf8/usb@14/hub@1/usb-*@8 +/pci@i0cf8/usb@14/hub@1/usb-*@9 +/pci@i0cf8/usb@14/hub@1/usb-*@a +/pci@i0cf8/usb@14/hub@1/usb-*@b +/pci@i0cf8/usb@14/hub@1/usb-*@c +/pci@i0cf8/usb@14/hub@1/usb-*@d +/pci@i0cf8/usb@14/hub@1/usb-*@e +/pci@i0cf8/usb@14/hub@1/usb-*@f +/pci@i0cf8/usb@1d/hub@1/*@0 +/pci@i0cf8/usb@1d/hub@1/*@1 +/pci@i0cf8/usb@1d/hub@1/*@2 +/pci@i0cf8/usb@1d/hub@1/*@3 +/pci@i0cf8/usb@1d/hub@1/*@4 +/pci@i0cf8/usb@1d/hub@1/*@5 +/pci@i0cf8/usb@1d/hub@1/*@6 +/pci@i0cf8/usb@1d/hub@1/*@7 +/pci@i0cf8/usb@1d/hub@1/usb-*@0 +/pci@i0cf8/usb@1d/hub@1/usb-*@1 +/pci@i0cf8/usb@1d/hub@1/usb-*@2 +/pci@i0cf8/usb@1d/hub@1/usb-*@3 +/pci@i0cf8/usb@1d/hub@1/usb-*@4 +/pci@i0cf8/usb@1d/hub@1/usb-*@5 +/pci@i0cf8/usb@1d/hub@1/usb-*@6 +/pci@i0cf8/usb@1d/hub@1/usb-*@7 diff --git a/cbfs/links.apl b/cbfs/links.apl new file mode 100644 index 00000000000..804f02f14bb --- /dev/null +++ b/cbfs/links.apl @@ -0,0 +1,2 @@ +pci8086,5a84.rom seavgabios.rom +pci8086,5a85.rom seavgabios.rom diff --git a/cbfs/links.bsw b/cbfs/links.bsw new file mode 100644 index 00000000000..234cef3f194 --- /dev/null +++ b/cbfs/links.bsw @@ -0,0 +1,2 @@ +pci8086,22b0.rom pci8086,22b0.rom +pci8086,22b1.rom pci8086,22b0.rom diff --git a/cbfs/links.hswbdw b/cbfs/links.hswbdw new file mode 100644 index 00000000000..4242209ee61 --- /dev/null +++ b/cbfs/links.hswbdw @@ -0,0 +1,6 @@ +pci8086,0a06.rom pci8086,0406.rom # HSW U GT1 +pci8086,0a16.rom pci8086,0406.rom # HSW U GT2 +pci8086,0a26.rom pci8086,0406.rom # HSW U GT3 +pci8086,1606.rom pci8086,0406.rom # BDW U GT1 +pci8086,1616.rom pci8086,0406.rom # BDW U GT2 +pci8086,1626.rom pci8086,0406.rom # BDW U GT3 diff --git a/cbfs/links.kbl b/cbfs/links.kbl new file mode 100644 index 00000000000..0ba983308e3 --- /dev/null +++ b/cbfs/links.kbl @@ -0,0 +1,5 @@ +pci8086,5906.rom seavgabios.rom # Kabylake GT1 SULTM +pci8086,591e.rom seavgabios.rom # Kabylake GT2 SULXM +pci8086,5916.rom seavgabios.rom # Kabylake GT2 SULTM +pci8086,5917.rom seavgabios.rom # Kabylake GT2 SULTMR +pci8086,591b.rom seavgabios.rom # Kabylake GT2 SHALM diff --git a/cbfs/links.sbib b/cbfs/links.sbib new file mode 100644 index 00000000000..66a59191c60 --- /dev/null +++ b/cbfs/links.sbib @@ -0,0 +1,10 @@ +pci8086,0106.rom pci8086,0106.rom +pci8086,0116.rom pci8086,0106.rom +pci8086,0126.rom pci8086,0106.rom +pci8086,0136.rom pci8086,0106.rom +pci8086,0146.rom pci8086,0106.rom +pci8086,0156.rom pci8086,0106.rom +pci8086,0166.rom pci8086,0106.rom +pci8086,0176.rom pci8086,0106.rom +pci8086,0186.rom pci8086,0106.rom +pci8086,0196.rom pci8086,0106.rom diff --git a/cbfs/links.skl b/cbfs/links.skl new file mode 100644 index 00000000000..2f903d66bac --- /dev/null +++ b/cbfs/links.skl @@ -0,0 +1,3 @@ +pci8086,1906.rom pci8086,0406.rom # SKL GT1 ULT +pci8086,1916.rom pci8086,0406.rom # SKL GT2 ULT +pci8086,191e.rom pci8086,0406.rom # SKL GT2 ULX diff --git a/configs/apl/config.astronaut.uefi b/configs/apl/config.astronaut.uefi new file mode 100644 index 00000000000..38886e537eb --- /dev/null +++ b/configs/apl/config.astronaut.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Astronaut" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.babymega.uefi b/configs/apl/config.babymega.uefi new file mode 100644 index 00000000000..8f08b40bd00 --- /dev/null +++ b/configs/apl/config.babymega.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Babymega" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.babytiger.uefi b/configs/apl/config.babytiger.uefi new file mode 100644 index 00000000000..b09218ecefb --- /dev/null +++ b/configs/apl/config.babytiger.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Babytiger" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.blacktip.uefi b/configs/apl/config.blacktip.uefi new file mode 100644 index 00000000000..74ebc18ab3f --- /dev/null +++ b/configs/apl/config.blacktip.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blacktip" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.blue.uefi b/configs/apl/config.blue.uefi new file mode 100644 index 00000000000..bb9a00fdeef --- /dev/null +++ b/configs/apl/config.blue.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blue" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.bruce.uefi b/configs/apl/config.bruce.uefi new file mode 100644 index 00000000000..708de61e573 --- /dev/null +++ b/configs/apl/config.bruce.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bruce" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.coral.uefi b/configs/apl/config.coral.uefi new file mode 100644 index 00000000000..b1b156ecd9c --- /dev/null +++ b/configs/apl/config.coral.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.electro.uefi b/configs/apl/config.electro.uefi new file mode 100644 index 00000000000..83bb05c3c29 --- /dev/null +++ b/configs/apl/config.electro.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Electro" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/reef/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/reef/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.epaulette.uefi b/configs/apl/config.epaulette.uefi new file mode 100644 index 00000000000..65066fbec26 --- /dev/null +++ b/configs/apl/config.epaulette.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Epaulette" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.lava.uefi b/configs/apl/config.lava.uefi new file mode 100644 index 00000000000..d03d0964b07 --- /dev/null +++ b/configs/apl/config.lava.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Lava" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.nasher.uefi b/configs/apl/config.nasher.uefi new file mode 100644 index 00000000000..f62ce96ac3e --- /dev/null +++ b/configs/apl/config.nasher.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nasher" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.nasher360.uefi b/configs/apl/config.nasher360.uefi new file mode 100644 index 00000000000..cf77795bc4c --- /dev/null +++ b/configs/apl/config.nasher360.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nasher360" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.pyro.uefi b/configs/apl/config.pyro.uefi new file mode 100644 index 00000000000..4b0806b37e0 --- /dev/null +++ b/configs/apl/config.pyro.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PYRO=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/pyro/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/pyro/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.rabbid.uefi b/configs/apl/config.rabbid.uefi new file mode 100644 index 00000000000..125d82e14bb --- /dev/null +++ b/configs/apl/config.rabbid.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Rabbid" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.reef.uefi b/configs/apl/config.reef.uefi new file mode 100644 index 00000000000..ef4f60b8a5b --- /dev/null +++ b/configs/apl/config.reef.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_REEF=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/reef/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/reef/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_REVISION_ID="origin/upp_202111" diff --git a/configs/apl/config.robo.uefi b/configs/apl/config.robo.uefi new file mode 100644 index 00000000000..4dcdc3267c9 --- /dev/null +++ b/configs/apl/config.robo.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Robo" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.robo360.uefi b/configs/apl/config.robo360.uefi new file mode 100644 index 00000000000..ab4f5ac81b7 --- /dev/null +++ b/configs/apl/config.robo360.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Robo360" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.sand.uefi b/configs/apl/config.sand.uefi new file mode 100644 index 00000000000..84dcce400a8 --- /dev/null +++ b/configs/apl/config.sand.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_SAND=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/sand/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/sand/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.santa.uefi b/configs/apl/config.santa.uefi new file mode 100644 index 00000000000..db465821696 --- /dev/null +++ b/configs/apl/config.santa.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Santa" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.snappy.uefi b/configs/apl/config.snappy.uefi new file mode 100644 index 00000000000..08dd5195a59 --- /dev/null +++ b/configs/apl/config.snappy.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_SNAPPY=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/snappy/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/snappy/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/apl/config.whitetip.uefi b/configs/apl/config.whitetip.uefi new file mode 100644 index 00000000000..667943dcac3 --- /dev/null +++ b/configs/apl/config.whitetip.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/reef/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CORAL=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_NEED_IFWI=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Whitetip" +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/reef/coral/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/apl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/reef/coral/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/bdw/config.auron_paine.uefi b/configs/bdw/config.auron_paine.uefi new file mode 100644 index 00000000000..a92885790c5 --- /dev/null +++ b/configs/bdw/config.auron_paine.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_AURON_PAINE=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/paine/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.auron_yuna.uefi b/configs/bdw/config.auron_yuna.uefi new file mode 100644 index 00000000000..2d2090f966c --- /dev/null +++ b/configs/bdw/config.auron_yuna.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_AURON_YUNA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/yuna/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.buddy.uefi b/configs/bdw/config.buddy.uefi new file mode 100644 index 00000000000..bbaa2dfdc0a --- /dev/null +++ b/configs/bdw/config.buddy.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/auron/buddy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_BUDDY=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/buddy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.gandof.uefi b/configs/bdw/config.gandof.uefi new file mode 100644 index 00000000000..184665673e5 --- /dev/null +++ b/configs/bdw/config.gandof.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_GANDOF=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/gandof/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.guado.uefi b/configs/bdw/config.guado.uefi new file mode 100644 index 00000000000..db44e314d2f --- /dev/null +++ b/configs/bdw/config.guado.uefi @@ -0,0 +1,21 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_GUADO=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.librem_13v1.uefi b/configs/bdw/config.librem_13v1.uefi new file mode 100644 index 00000000000..142cf6e7b44 --- /dev/null +++ b/configs/bdw/config.librem_13v1.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x5C0000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/me.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/bdw/config.librem_15v2.uefi b/configs/bdw/config.librem_15v2.uefi new file mode 100644 index 00000000000..b0930a90f17 --- /dev/null +++ b/configs/bdw/config.librem_15v2.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_CBFS_SIZE=0x5C0000 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_bdw/me.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_BOARD_PURISM_LIBREM15_V2=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/purism-blobs/mainboard/purism/librem_bdw/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/bdw/config.lulu.uefi b/configs/bdw/config.lulu.uefi new file mode 100644 index 00000000000..c14cc719464 --- /dev/null +++ b/configs/bdw/config.lulu.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/book/me.bin" +CONFIG_BOARD_GOOGLE_LULU=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/lulu/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.rikku.uefi b/configs/bdw/config.rikku.uefi new file mode 100644 index 00000000000..316ade39d0a --- /dev/null +++ b/configs/bdw/config.rikku.uefi @@ -0,0 +1,21 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_RIKKU=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bdw/config.samus.uefi b/configs/bdw/config.samus.uefi new file mode 100644 index 00000000000..2454345295d --- /dev/null +++ b/configs/bdw/config.samus.uefi @@ -0,0 +1,22 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1275 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/auron/samus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/auron/samus/me.bin" +CONFIG_BOARD_GOOGLE_SAMUS=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/book/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/book/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/auron/samus/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/bdw/config.tidus.uefi b/configs/bdw/config.tidus.uefi new file mode 100644 index 00000000000..7b4bdc73cb5 --- /dev/null +++ b/configs/bdw/config.tidus.uefi @@ -0,0 +1,21 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bdw/box/me.bin" +CONFIG_BOARD_GOOGLE_TIDUS=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/bdw/box/mrc.bin" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/bdw/box/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bdw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.banon.uefi b/configs/bsw/config.banon.uefi new file mode 100644 index 00000000000..525b64ff1ed --- /dev/null +++ b/configs/bsw/config.banon.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/banon/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_BANON=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/banon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/banon/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.celes.uefi b/configs/bsw/config.celes.uefi new file mode 100644 index 00000000000..7cf1c06b18f --- /dev/null +++ b/configs/bsw/config.celes.uefi @@ -0,0 +1,29 @@ +CONFIG_LOCALVERSION="v0.1.0" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/celes/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_CELES=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/celes/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/celes/fsp.bin" +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_GOP_DRIVER=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_UEFIPAYLOAD=y +CONFIG_EDK2_TAG_OR_REV="b647b3e963b8f9ffcfb4bd88912d3a0a5a371992" +CONFIG_EDK2_RELEASE=y +CONFIG_EDK2_BOOTSPLASH_IMAGE=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/evaluation_logo.bmp" +CONFIG_EDK2_SECURE_BOOT=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C diff --git a/configs/bsw/config.cyan.uefi b/configs/bsw/config.cyan.uefi new file mode 100644 index 00000000000..d90381c4a34 --- /dev/null +++ b/configs/bsw/config.cyan.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/cyan/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_CYAN=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/cyan/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/cyan/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.edgar.uefi b/configs/bsw/config.edgar.uefi new file mode 100644 index 00000000000..74bbdc25f08 --- /dev/null +++ b/configs/bsw/config.edgar.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/edgar/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_EDGAR=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/edgar/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/edgar/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.kefka.uefi b/configs/bsw/config.kefka.uefi new file mode 100644 index 00000000000..1189d8c51fc --- /dev/null +++ b/configs/bsw/config.kefka.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/kefka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_KEFKA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/kefka/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/kefka/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.reks.uefi b/configs/bsw/config.reks.uefi new file mode 100644 index 00000000000..b1be71cecee --- /dev/null +++ b/configs/bsw/config.reks.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/reks/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_REKS=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/reks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/reks/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.relm.uefi b/configs/bsw/config.relm.uefi new file mode 100644 index 00000000000..0a809256b35 --- /dev/null +++ b/configs/bsw/config.relm.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/relm/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_RELM=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/relm/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/relm/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.setzer.uefi b/configs/bsw/config.setzer.uefi new file mode 100644 index 00000000000..ab12b6fde5d --- /dev/null +++ b/configs/bsw/config.setzer.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/setzer/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_SETZER=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/setzer/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/setzer/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.terra.uefi b/configs/bsw/config.terra.uefi new file mode 100644 index 00000000000..d3781305686 --- /dev/null +++ b/configs/bsw/config.terra.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/terra/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_TERRA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/terra/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/terra/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.ultima.uefi b/configs/bsw/config.ultima.uefi new file mode 100644 index 00000000000..cc1acbc6e92 --- /dev/null +++ b/configs/bsw/config.ultima.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/ultima/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_ULTIMA=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/ultima/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/ultima/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/bsw/config.wizpig.uefi b/configs/bsw/config.wizpig.uefi new file mode 100644 index 00000000000..4b2ee4f1100 --- /dev/null +++ b/configs/bsw/config.wizpig.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/cyan/wizpig/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/bsw/me.bin" +CONFIG_BOARD_GOOGLE_WIZPIG=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/bsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/cyan/wizpig/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_HAVE_FSP_BIN=y +CONFIG_FSP_FILE="3rdparty/blobs/mainboard/google/cyan/wizpig/fsp.bin" +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.banjo.uefi b/configs/byt/config.banjo.uefi new file mode 100644 index 00000000000..f6b34e5d32f --- /dev/null +++ b/configs/byt/config.banjo.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_BANJO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/banjo/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.candy.uefi b/configs/byt/config.candy.uefi new file mode 100644 index 00000000000..e96d538d94b --- /dev/null +++ b/configs/byt/config.candy.uefi @@ -0,0 +1,25 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_VGA_BIOS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_CANDY=y +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/google/rambi/candy/vgabios.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/candy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_INTEL_GMA_ADD_VBT is not set +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/byt/config.clapper.uefi b/configs/byt/config.clapper.uefi new file mode 100644 index 00000000000..acb435740ef --- /dev/null +++ b/configs/byt/config.clapper.uefi @@ -0,0 +1,25 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_VGA_BIOS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_CLAPPER=y +CONFIG_VGA_BIOS_FILE="3rdparty/blobs/mainboard/google/rambi/clapper/vgabios.bin" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/clapper/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_INTEL_GMA_ADD_VBT is not set +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/byt/config.enguarde.uefi b/configs/byt/config.enguarde.uefi new file mode 100644 index 00000000000..57019ee554e --- /dev/null +++ b/configs/byt/config.enguarde.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_ENGUARDE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/enguarde/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.glimmer.uefi b/configs/byt/config.glimmer.uefi new file mode 100644 index 00000000000..f1fae24cf0e --- /dev/null +++ b/configs/byt/config.glimmer.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_GLIMMER=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/glimmer/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.gnawty.uefi b/configs/byt/config.gnawty.uefi new file mode 100644 index 00000000000..a57b8b6f640 --- /dev/null +++ b/configs/byt/config.gnawty.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_GNAWTY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/gnawty/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.heli.uefi b/configs/byt/config.heli.uefi new file mode 100644 index 00000000000..930dd0f3015 --- /dev/null +++ b/configs/byt/config.heli.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_HELI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/heli/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.kip.uefi b/configs/byt/config.kip.uefi new file mode 100644 index 00000000000..eb1c89fe831 --- /dev/null +++ b/configs/byt/config.kip.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_KIP=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/kip/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.ninja.uefi b/configs/byt/config.ninja.uefi new file mode 100644 index 00000000000..f4a76b8a059 --- /dev/null +++ b/configs/byt/config.ninja.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_NINJA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/ninja/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.orco.uefi b/configs/byt/config.orco.uefi new file mode 100644 index 00000000000..0d26ddabda2 --- /dev/null +++ b/configs/byt/config.orco.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_ORCO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/orco/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.quawks.uefi b/configs/byt/config.quawks.uefi new file mode 100644 index 00000000000..1c73a028b93 --- /dev/null +++ b/configs/byt/config.quawks.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_QUAWKS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/quawks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.squawks.uefi b/configs/byt/config.squawks.uefi new file mode 100644 index 00000000000..291a49e44ff --- /dev/null +++ b/configs/byt/config.squawks.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SQUAWKS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/squawks/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.sumo.uefi b/configs/byt/config.sumo.uefi new file mode 100644 index 00000000000..84b171689cf --- /dev/null +++ b/configs/byt/config.sumo.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SUMO=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/sumo/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.swanky.uefi b/configs/byt/config.swanky.uefi new file mode 100644 index 00000000000..11bdf895b91 --- /dev/null +++ b/configs/byt/config.swanky.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_SWANKY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/swanky/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/byt/config.winky.uefi b/configs/byt/config.winky.uefi new file mode 100644 index 00000000000..4979ecc5b9a --- /dev/null +++ b/configs/byt/config.winky.uefi @@ -0,0 +1,23 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/byt/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/byt/me.bin" +CONFIG_BOARD_GOOGLE_WINKY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/byt/mrc.elf" +CONFIG_HAVE_REFCODE_BLOB=y +CONFIG_REFCODE_BLOB_FILE="3rdparty/blobs/soc/intel/byt/refcode.elf" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/byt/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/rambi/winky/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.akemi.uefi b/configs/cml/config.akemi.uefi new file mode 100644 index 00000000000..7a2bd2203ae --- /dev/null +++ b/configs/cml/config.akemi.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/akemi/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/akemi/me.bin" +CONFIG_BOARD_GOOGLE_AKEMI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/akemi/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/cml/config.dooly.uefi b/configs/cml/config.dooly.uefi new file mode 100644 index 00000000000..8880f322749 --- /dev/null +++ b/configs/cml/config.dooly.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dooly/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff_legacy/me.bin" +CONFIG_BOARD_GOOGLE_DOOLY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.dragonair.uefi b/configs/cml/config.dragonair.uefi new file mode 100644 index 00000000000..cedc04cd9ad --- /dev/null +++ b/configs/cml/config.dragonair.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/me.bin" +CONFIG_BOARD_GOOGLE_DRATINI=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Dragonair" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/dratini/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.drallion.uefi b/configs/cml/config.drallion.uefi new file mode 100644 index 00000000000..1a93d11db6d --- /dev/null +++ b/configs/cml/config.drallion.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/drallion/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/me.bin" +CONFIG_BOARD_GOOGLE_DRALLION=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/drallion/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_EC_BIN=y +CONFIG_EC_BIN_PATH="3rdparty/blobs/mainboard/google/drallion/ec.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1028 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/cml/config.dratini.uefi b/configs/cml/config.dratini.uefi new file mode 100644 index 00000000000..cd456d50122 --- /dev/null +++ b/configs/cml/config.dratini.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/dratini/me.bin" +CONFIG_BOARD_GOOGLE_DRATINI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/dratini/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.duffy.uefi b/configs/cml/config.duffy.uefi new file mode 100644 index 00000000000..e604b428489 --- /dev/null +++ b/configs/cml/config.duffy.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_DUFFY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.faffy.uefi b/configs/cml/config.faffy.uefi new file mode 100644 index 00000000000..73ee8ed50ff --- /dev/null +++ b/configs/cml/config.faffy.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_FAFFY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.helios.uefi b/configs/cml/config.helios.uefi new file mode 100644 index 00000000000..5a5c9a80a46 --- /dev/null +++ b/configs/cml/config.helios.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/helios/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/helios/me.bin" +CONFIG_BOARD_GOOGLE_HELIOS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/helios/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.jinlon.uefi b/configs/cml/config.jinlon.uefi new file mode 100644 index 00000000000..822a9ead936 --- /dev/null +++ b/configs/cml/config.jinlon.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/jinlon/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/jinlon/me.bin" +CONFIG_BOARD_GOOGLE_JINLON=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/jinlon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.kaisa.uefi b/configs/cml/config.kaisa.uefi new file mode 100644 index 00000000000..4e60bfd46df --- /dev/null +++ b/configs/cml/config.kaisa.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_KAISA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.kindred.uefi b/configs/cml/config.kindred.uefi new file mode 100644 index 00000000000..e6e15dbddeb --- /dev/null +++ b/configs/cml/config.kindred.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/me.bin" +CONFIG_BOARD_GOOGLE_KINDRED=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kindred/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.kled.uefi b/configs/cml/config.kled.uefi new file mode 100644 index 00000000000..fb055ec759b --- /dev/null +++ b/configs/cml/config.kled.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kindred/me.bin" +CONFIG_BOARD_GOOGLE_KINDRED=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Kled" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kindred/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.kohaku.uefi b/configs/cml/config.kohaku.uefi new file mode 100644 index 00000000000..a09679f9184 --- /dev/null +++ b/configs/cml/config.kohaku.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kohaku/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/kohaku/me.bin" +CONFIG_BOARD_GOOGLE_KOHAKU=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/kohaku/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.librem_14.uefi b/configs/cml/config.librem_14.uefi new file mode 100644 index 00000000000..28a46cebaa0 --- /dev/null +++ b/configs/cml/config.librem_14.uefi @@ -0,0 +1,12 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/librem_14/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_14=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.librem_mini_v2.uefi b/configs/cml/config.librem_mini_v2.uefi new file mode 100644 index 00000000000..6edbe87d32b --- /dev/null +++ b/configs/cml/config.librem_mini_v2.uefi @@ -0,0 +1,12 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini_v2/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini_v2/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_MINI_V2=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.nightfury.uefi b/configs/cml/config.nightfury.uefi new file mode 100644 index 00000000000..7aa70578547 --- /dev/null +++ b/configs/cml/config.nightfury.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/nightfury/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/nightfury/me.bin" +CONFIG_BOARD_GOOGLE_NIGHTFURY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/nightfury/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/cml/config.noibat.uefi b/configs/cml/config.noibat.uefi new file mode 100644 index 00000000000..84d80ddb783 --- /dev/null +++ b/configs/cml/config.noibat.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/noibat/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_NOIBAT=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/cml/config.wyvern.uefi b/configs/cml/config.wyvern.uefi new file mode 100644 index 00000000000..2686c046ea5 --- /dev/null +++ b/configs/cml/config.wyvern.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/wyvern/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/hatch/puff/me.bin" +CONFIG_BOARD_GOOGLE_WYVERN=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/cml/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/hatch/puff/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/glk/config.ampton.uefi b/configs/glk/config.ampton.uefi new file mode 100644 index 00000000000..8b2c219cb9a --- /dev/null +++ b/configs/glk/config.ampton.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.apel.uefi b/configs/glk/config.apel.uefi new file mode 100644 index 00000000000..ff1a157bd4a --- /dev/null +++ b/configs/glk/config.apel.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Apel" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.bloog.uefi b/configs/glk/config.bloog.uefi new file mode 100644 index 00000000000..a7133bcb57a --- /dev/null +++ b/configs/glk/config.bloog.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.blooglet.uefi b/configs/glk/config.blooglet.uefi new file mode 100644 index 00000000000..147380d5d77 --- /dev/null +++ b/configs/glk/config.blooglet.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blooglet" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.blooguard.uefi b/configs/glk/config.blooguard.uefi new file mode 100644 index 00000000000..877676d2af3 --- /dev/null +++ b/configs/glk/config.blooguard.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bloog/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BLOOG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blooguard" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bloog/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bloog/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bloog/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.blorb.uefi b/configs/glk/config.blorb.uefi new file mode 100644 index 00000000000..cb75f316f51 --- /dev/null +++ b/configs/glk/config.blorb.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Blorb" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.bluebird.uefi b/configs/glk/config.bluebird.uefi new file mode 100644 index 00000000000..1565195c624 --- /dev/null +++ b/configs/glk/config.bluebird.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/casta/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CASTA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bluebird" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/casta/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/casta/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/casta/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/casta/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/casta/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.bobba.uefi b/configs/glk/config.bobba.uefi new file mode 100644 index 00000000000..299b89c7d1e --- /dev/null +++ b/configs/glk/config.bobba.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.bobba360.uefi b/configs/glk/config.bobba360.uefi new file mode 100644 index 00000000000..146d0a2735e --- /dev/null +++ b/configs/glk/config.bobba360.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Bobba360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.casta.uefi b/configs/glk/config.casta.uefi new file mode 100644 index 00000000000..ca80861cbba --- /dev/null +++ b/configs/glk/config.casta.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/casta/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_CASTA=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/casta/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/casta/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/casta/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/casta/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/casta/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.dood.uefi b/configs/glk/config.dood.uefi new file mode 100644 index 00000000000..9c4afc6b764 --- /dev/null +++ b/configs/glk/config.dood.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/dood/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_DOOD=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/dood/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/dood/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/dood/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/dood/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/dood/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.dorp.uefi b/configs/glk/config.dorp.uefi new file mode 100644 index 00000000000..481b8203ae0 --- /dev/null +++ b/configs/glk/config.dorp.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Dorp" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.droid.uefi b/configs/glk/config.droid.uefi new file mode 100644 index 00000000000..9752dc63665 --- /dev/null +++ b/configs/glk/config.droid.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Droid" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.fleex.uefi b/configs/glk/config.fleex.uefi new file mode 100644 index 00000000000..19ebc75a060 --- /dev/null +++ b/configs/glk/config.fleex.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.foob.uefi b/configs/glk/config.foob.uefi new file mode 100644 index 00000000000..9d2925a9723 --- /dev/null +++ b/configs/glk/config.foob.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/foob/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FOOB=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/foob/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/foob/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/foob/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/foob/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/foob/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.foob360.uefi b/configs/glk/config.foob360.uefi new file mode 100644 index 00000000000..a2f5983f6ca --- /dev/null +++ b/configs/glk/config.foob360.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/foob/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FOOB=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Foob360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/foob/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/foob/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/foob/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/foob/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/foob/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.garfour.uefi b/configs/glk/config.garfour.uefi new file mode 100644 index 00000000000..008344a6eaf --- /dev/null +++ b/configs/glk/config.garfour.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Garfour" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.garg.uefi b/configs/glk/config.garg.uefi new file mode 100644 index 00000000000..f3b1f170610 --- /dev/null +++ b/configs/glk/config.garg.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.garg360.uefi b/configs/glk/config.garg360.uefi new file mode 100644 index 00000000000..f04c8c72373 --- /dev/null +++ b/configs/glk/config.garg360.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/garg/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_GARG=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Garg360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/garg/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/garg/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/garg/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/garg/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.grabbiter.uefi b/configs/glk/config.grabbiter.uefi new file mode 100644 index 00000000000..f3485f6276f --- /dev/null +++ b/configs/glk/config.grabbiter.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Grabbiter" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.laser.uefi b/configs/glk/config.laser.uefi new file mode 100644 index 00000000000..52d23ca4a7b --- /dev/null +++ b/configs/glk/config.laser.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Laser" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.laser14.uefi b/configs/glk/config.laser14.uefi new file mode 100644 index 00000000000..46aec5b86d2 --- /dev/null +++ b/configs/glk/config.laser14.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Laser14" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.lick.uefi b/configs/glk/config.lick.uefi new file mode 100644 index 00000000000..6eb1ccf7024 --- /dev/null +++ b/configs/glk/config.lick.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/lick/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_LICK=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/lick/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/lick/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/lick/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/lick/cpu_microcode_blob.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.meep.uefi b/configs/glk/config.meep.uefi new file mode 100644 index 00000000000..eb60fbe19ed --- /dev/null +++ b/configs/glk/config.meep.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.mimrock.uefi b/configs/glk/config.mimrock.uefi new file mode 100644 index 00000000000..e9eadee1bf7 --- /dev/null +++ b/configs/glk/config.mimrock.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/mimrock/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Mimrock" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/mimrock/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/mimrock/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/mimrock/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/mimrock/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.nospike.uefi b/configs/glk/config.nospike.uefi new file mode 100644 index 00000000000..c12190d281e --- /dev/null +++ b/configs/glk/config.nospike.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/ampton/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_AMPTON=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Nospike" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/ampton/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/ampton/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/ampton/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.orbatrix.uefi b/configs/glk/config.orbatrix.uefi new file mode 100644 index 00000000000..47642538795 --- /dev/null +++ b/configs/glk/config.orbatrix.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/fleex/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_FLEEX=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Orbatrix" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/fleex/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/fleex/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/fleex/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.phaser.uefi b/configs/glk/config.phaser.uefi new file mode 100644 index 00000000000..9abf33e2bdb --- /dev/null +++ b/configs/glk/config.phaser.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.phaser360.uefi b/configs/glk/config.phaser360.uefi new file mode 100644 index 00000000000..ad9e845ce57 --- /dev/null +++ b/configs/glk/config.phaser360.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Phaser360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.phaser360s.uefi b/configs/glk/config.phaser360s.uefi new file mode 100644 index 00000000000..a5309111efd --- /dev/null +++ b/configs/glk/config.phaser360s.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/phaser/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_PHASER=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Phaser360s" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/phaser/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/phaser/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/phaser/cpu_microcode_blob.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.sparky.uefi b/configs/glk/config.sparky.uefi new file mode 100644 index 00000000000..ed36a15a413 --- /dev/null +++ b/configs/glk/config.sparky.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Sparky" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.sparky360.uefi b/configs/glk/config.sparky360.uefi new file mode 100644 index 00000000000..d8003a6dd18 --- /dev/null +++ b/configs/glk/config.sparky360.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/bobba/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_BOBBA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Sparky360" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/bobba/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/bobba/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/bobba/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.vorticon.uefi b/configs/glk/config.vorticon.uefi new file mode 100644 index 00000000000..b286bc5503f --- /dev/null +++ b/configs/glk/config.vorticon.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Vorticon" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/glk/config.vortininja.uefi b/configs/glk/config.vortininja.uefi new file mode 100644 index 00000000000..86f7c9c92ca --- /dev/null +++ b/configs/glk/config.vortininja.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/octopus/meep/flashdescriptor.bin" +CONFIG_BOARD_GOOGLE_MEEP=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Vortininja" +CONFIG_NEED_IFWI=y +CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/google/octopus/meep/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/octopus/meep/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/octopus/meep/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/octopus/meep/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/hsw/config.falco.uefi b/configs/hsw/config.falco.uefi new file mode 100644 index 00000000000..c685e48444b --- /dev/null +++ b/configs/hsw/config.falco.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_FALCO=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/falco/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.leon.uefi b/configs/hsw/config.leon.uefi new file mode 100644 index 00000000000..b1d21edb749 --- /dev/null +++ b/configs/hsw/config.leon.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_LEON=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/leon/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.mccloud.uefi b/configs/hsw/config.mccloud.uefi new file mode 100644 index 00000000000..5edadf5ac5b --- /dev/null +++ b/configs/hsw/config.mccloud.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_MCCLOUD=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.monroe.uefi b/configs/hsw/config.monroe.uefi new file mode 100644 index 00000000000..aeefbe579fa --- /dev/null +++ b/configs/hsw/config.monroe.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_MONROE=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.panther.uefi b/configs/hsw/config.panther.uefi new file mode 100644 index 00000000000..06ffbac6682 --- /dev/null +++ b/configs/hsw/config.panther.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/soc/intel/hsw/box/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_PANTHER=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.peppy.uefi b/configs/hsw/config.peppy.uefi new file mode 100644 index 00000000000..f063dfb3c39 --- /dev/null +++ b/configs/hsw/config.peppy.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_PEPPY=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/peppy/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.tricky.uefi b/configs/hsw/config.tricky.uefi new file mode 100644 index 00000000000..8b63468b1ff --- /dev/null +++ b/configs/hsw/config.tricky.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_TRICKY=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.wolf.uefi b/configs/hsw/config.wolf.uefi new file mode 100644 index 00000000000..56353a8facc --- /dev/null +++ b/configs/hsw/config.wolf.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/book/me.bin" +CONFIG_BOARD_GOOGLE_WOLF=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/book/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/slippy/wolf/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/hsw/config.zako.uefi b/configs/hsw/config.zako.uefi new file mode 100644 index 00000000000..aa5468102a3 --- /dev/null +++ b/configs/hsw/config.zako.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/soc/intel/hsw/box/me.bin" +CONFIG_BOARD_GOOGLE_ZAKO=y +CONFIG_HAVE_IFD_BIN=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_HAVE_MRC=y +CONFIG_MRC_FILE="3rdparty/blobs/soc/intel/hsw/box/mrc.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/hsw/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/jsl/config.drawcia.uefi b/configs/jsl/config.drawcia.uefi new file mode 100644 index 00000000000..f35ed7a734d --- /dev/null +++ b/configs/jsl/config.drawcia.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/jsl/config.drawlat.uefi b/configs/jsl/config.drawlat.uefi new file mode 100644 index 00000000000..ee9bb6e7913 --- /dev/null +++ b/configs/jsl/config.drawlat.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Drawlat" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/jsl/config.drawman.uefi b/configs/jsl/config.drawman.uefi new file mode 100644 index 00000000000..601b575c202 --- /dev/null +++ b/configs/jsl/config.drawman.uefi @@ -0,0 +1,20 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/drawcia/me.bin" +CONFIG_BOARD_GOOGLE_DRAWCIA=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Drawman" +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/drawcia/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/drawcia/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/jsl/config.lantis.uefi b/configs/jsl/config.lantis.uefi new file mode 100644 index 00000000000..2a566a14e2c --- /dev/null +++ b/configs/jsl/config.lantis.uefi @@ -0,0 +1,21 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_FMDFILE="" +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/lantis/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/dedede/lantis/me.bin" +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/vbt.bin" +CONFIG_BOARD_GOOGLE_LANTIS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_FSP_M_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/fspm.bin" +CONFIG_FSP_S_FILE="3rdparty/blobs/mainboard/google/dedede/lantis/fsps.bin" +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/dedede/lantis/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +# CONFIG_SET_GOP_DRIVER_VERSION is not set +CONFIG_ADD_FSP_BINARIES=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_RUN_FSP_GOP=y diff --git a/configs/kbl/config.atlas.uefi b/configs/kbl/config.atlas.uefi new file mode 100644 index 00000000000..2f0d967c882 --- /dev/null +++ b/configs/kbl/config.atlas.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/atlas/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/atlas/me.bin" +CONFIG_BOARD_GOOGLE_ATLAS=y +CONFIG_INCLUDE_NHLT_BLOBS_ATLAS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.eve.uefi b/configs/kbl/config.eve.uefi new file mode 100644 index 00000000000..b2ebb25bc68 --- /dev/null +++ b/configs/kbl/config.eve.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/eve/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/eve/me.bin" +CONFIG_BOARD_GOOGLE_EVE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/eve/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.fizz.uefi b/configs/kbl/config.fizz.uefi new file mode 100644 index 00000000000..34f88a9bb25 --- /dev/null +++ b/configs/kbl/config.fizz.uefi @@ -0,0 +1,19 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/me.bin" +CONFIG_BOARD_GOOGLE_FIZZ=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/fizz/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/kbl/config.karma.uefi b/configs/kbl/config.karma.uefi new file mode 100644 index 00000000000..149717d23cd --- /dev/null +++ b/configs/kbl/config.karma.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/karma/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/fizz/karma/me.bin" +CONFIG_BOARD_GOOGLE_KARMA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/kbl/config.leona.uefi b/configs/kbl/config.leona.uefi new file mode 100644 index 00000000000..a312999fae4 --- /dev/null +++ b/configs/kbl/config.leona.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/me.bin" +CONFIG_BOARD_GOOGLE_RAMMUS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Leona" +CONFIG_INCLUDE_NHLT_BLOBS_RAMMUS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.librem_13v4.uefi b/configs/kbl/config.librem_13v4.uefi new file mode 100644 index 00000000000..5776027cf3e --- /dev/null +++ b/configs/kbl/config.librem_13v4.uefi @@ -0,0 +1,10 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM13_V4=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.librem_15v4.uefi b/configs/kbl/config.librem_15v4.uefi new file mode 100644 index 00000000000..3aba8520be4 --- /dev/null +++ b/configs/kbl/config.librem_15v4.uefi @@ -0,0 +1,12 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_kbl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM15_V4=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.nami.uefi b/configs/kbl/config.nami.uefi new file mode 100644 index 00000000000..0328b121e13 --- /dev/null +++ b/configs/kbl/config.nami.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nami/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nami/me.bin" +CONFIG_BOARD_GOOGLE_NAMI=y +CONFIG_OEM_BIN_FILE="3rdparty/blobs/mainboard/google/poppy/nami/oem.bin" +CONFIG_INCLUDE_NHLT_BLOBS_NAMI=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.nautilus.uefi b/configs/kbl/config.nautilus.uefi new file mode 100644 index 00000000000..18cfd8b5b0a --- /dev/null +++ b/configs/kbl/config.nautilus.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nautilus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nautilus/me.bin" +CONFIG_BOARD_GOOGLE_NAUTILUS=y +CONFIG_INCLUDE_NHLT_BLOBS_NAUTILUS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.nocturne.uefi b/configs/kbl/config.nocturne.uefi new file mode 100644 index 00000000000..0c1a43a6d59 --- /dev/null +++ b/configs/kbl/config.nocturne.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nocturne/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/nocturne/me.bin" +CONFIG_BOARD_GOOGLE_NOCTURNE=y +CONFIG_INCLUDE_NHLT_BLOBS_NOCTURNE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.shyvana.uefi b/configs/kbl/config.shyvana.uefi new file mode 100644 index 00000000000..a228b8fa982 --- /dev/null +++ b/configs/kbl/config.shyvana.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/rammus/me.bin" +CONFIG_BOARD_GOOGLE_RAMMUS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Shyvana" +CONFIG_INCLUDE_NHLT_BLOBS_RAMMUS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/kbl/config.soraka.uefi b/configs/kbl/config.soraka.uefi new file mode 100644 index 00000000000..067bcf2e766 --- /dev/null +++ b/configs/kbl/config.soraka.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/soraka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/poppy/soraka/me.bin" +CONFIG_BOARD_GOOGLE_SORAKA=y +CONFIG_OEM_BIN_FILE="3rdparty/blobs/mainboard/google/poppy/soraka/oem.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/kbl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.asuka.uefi b/configs/skl/config.asuka.uefi new file mode 100644 index 00000000000..ab301beb5da --- /dev/null +++ b/configs/skl/config.asuka.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/asuka/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/asuka/me.bin" +CONFIG_BOARD_GOOGLE_ASUKA=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/asuka/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.caroline.uefi b/configs/skl/config.caroline.uefi new file mode 100644 index 00000000000..df8f55d97fa --- /dev/null +++ b/configs/skl/config.caroline.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1200 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1800 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/caroline/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/caroline/me.bin" +CONFIG_BOARD_GOOGLE_CAROLINE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/caroline/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.cave.uefi b/configs/skl/config.cave.uefi new file mode 100644 index 00000000000..225d794806d --- /dev/null +++ b/configs/skl/config.cave.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/cave/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/cave/me.bin" +CONFIG_BOARD_GOOGLE_CAVE=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/cave/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.chell.uefi b/configs/skl/config.chell.uefi new file mode 100644 index 00000000000..5776ca947a6 --- /dev/null +++ b/configs/skl/config.chell.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1080 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/chell/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/chell/me.bin" +CONFIG_BOARD_GOOGLE_CHELL=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/chell/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.lars.uefi b/configs/skl/config.lars.uefi new file mode 100644 index 00000000000..24095c9ed38 --- /dev/null +++ b/configs/skl/config.lars.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/lars/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/lars/me.bin" +CONFIG_BOARD_GOOGLE_LARS=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/lars/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.librem_13v2.uefi b/configs/skl/config.librem_13v2.uefi new file mode 100644 index 00000000000..74018248946 --- /dev/null +++ b/configs/skl/config.librem_13v2.uefi @@ -0,0 +1,10 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM13_V2=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_skl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.librem_15v3.uefi b/configs/skl/config.librem_15v3.uefi new file mode 100644 index 00000000000..b9ed15341ad --- /dev/null +++ b/configs/skl/config.librem_15v3.uefi @@ -0,0 +1,10 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_skl/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM15_V3=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_skl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/skl/config.sentry.uefi b/configs/skl/config.sentry.uefi new file mode 100644 index 00000000000..1eb8ef459cc --- /dev/null +++ b/configs/skl/config.sentry.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +CONFIG_INCLUDE_NHLT_BLOBS=y +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/glados/sentry/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/glados/sentry/me.bin" +CONFIG_BOARD_GOOGLE_SENTRY=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/skl/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/glados/sentry/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.butterfly.uefi b/configs/snb_ivb/config.butterfly.uefi new file mode 100644 index 00000000000..a21d41fdd61 --- /dev/null +++ b/configs/snb_ivb/config.butterfly.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_MAINBOARD_VENDOR="Google" +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/butterfly/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/butterfly/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/butterfly/me.bin" +CONFIG_BOARD_GOOGLE_BUTTERFLY=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.link.uefi b/configs/snb_ivb/config.link.uefi new file mode 100644 index 00000000000..d4cf069b716 --- /dev/null +++ b/configs/snb_ivb/config.link.uefi @@ -0,0 +1,21 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1275 +CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=1920 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/link/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/link/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/link/me.bin" +CONFIG_BOARD_GOOGLE_LINK=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/link/ec.RW.flat" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_GOP_DRIVER_VERSION="3.0.1030" +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.lumpy.uefi b/configs/snb_ivb/config.lumpy.uefi new file mode 100644 index 00000000000..7ea0caac043 --- /dev/null +++ b/configs/snb_ivb/config.lumpy.uefi @@ -0,0 +1,15 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_SAMSUNG=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/samsung/lumpy/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/samsung/lumpy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/samsung/lumpy/me.bin" +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.parrot.uefi b/configs/snb_ivb/config.parrot.uefi new file mode 100644 index 00000000000..e9566570906 --- /dev/null +++ b/configs/snb_ivb/config.parrot.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/parrot/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/parrot/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/parrot/me.bin" +CONFIG_BOARD_GOOGLE_PARROT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.stout.uefi b/configs/snb_ivb/config.stout.uefi new file mode 100644 index 00000000000..76f5f496e5c --- /dev/null +++ b/configs/snb_ivb/config.stout.uefi @@ -0,0 +1,16 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/stout/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/stout/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/stout/me.bin" +CONFIG_BOARD_GOOGLE_STOUT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/ivb/cpu_microcode_blob.bin" +# CONFIG_USE_NATIVE_RAMINIT is not set +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/snb_ivb/config.stumpy.uefi b/configs/snb_ivb/config.stumpy.uefi new file mode 100644 index 00000000000..d90d2e3a24a --- /dev/null +++ b/configs/snb_ivb/config.stumpy.uefi @@ -0,0 +1,17 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_SAMSUNG=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x250000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GOOGLE" +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/samsung/stumpy/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/samsung/stumpy/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/samsung/stumpy/me.bin" +CONFIG_PCIEXP_L1_SUB_STATE=y +# CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_BOARD_SAMSUNG_STUMPY=y +CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/soc/intel/snb/cpu_microcode_blob.bin" +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.aleena.uefi b/configs/str/config.aleena.uefi new file mode 100644 index 00000000000..c41148a32c4 --- /dev/null +++ b/configs/str/config.aleena.uefi @@ -0,0 +1,13 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_ALEENA=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/aleena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.barla.uefi b/configs/str/config.barla.uefi new file mode 100644 index 00000000000..69037ff3b76 --- /dev/null +++ b/configs/str/config.barla.uefi @@ -0,0 +1,14 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_CAREENA=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Barla" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/careena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.careena.uefi b/configs/str/config.careena.uefi new file mode 100644 index 00000000000..61825a905ef --- /dev/null +++ b/configs/str/config.careena.uefi @@ -0,0 +1,13 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_CAREENA=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/careena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.kasumi.uefi b/configs/str/config.kasumi.uefi new file mode 100644 index 00000000000..b4426700719 --- /dev/null +++ b/configs/str/config.kasumi.uefi @@ -0,0 +1,14 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_GRUNT=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Kasumi" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/aleena/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.liara.uefi b/configs/str/config.liara.uefi new file mode 100644 index 00000000000..fcb95bc3d86 --- /dev/null +++ b/configs/str/config.liara.uefi @@ -0,0 +1,13 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_LIARA=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/liara/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/str/config.treeya.uefi b/configs/str/config.treeya.uefi new file mode 100644 index 00000000000..663b53b6a5c --- /dev/null +++ b/configs/str/config.treeya.uefi @@ -0,0 +1,14 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VGA_BIOS=y +CONFIG_BOARD_GOOGLE_TREEYA=y +CONFIG_USE_PSPSECUREOS=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/kahlee/treeya/ec.RW.flat" +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1D4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/tgl/config.drobit.uefi b/configs/tgl/config.drobit.uefi new file mode 100644 index 00000000000..ebba45b37cf --- /dev/null +++ b/configs/tgl/config.drobit.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/drobit/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/drobit/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/drobit/me.bin" +CONFIG_BOARD_GOOGLE_DROBIT=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/drobit/cpu_microcode_blob.bin" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="3rdparty/blobs/mainboard/google/volteer/drobit/ec.RW.flat" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_RUN_FSP_GOP=y +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/configs/tgl/config.voxel.uefi b/configs/tgl/config.voxel.uefi new file mode 100644 index 00000000000..0fb0e868704 --- /dev/null +++ b/configs/tgl/config.voxel.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +CONFIG_CBFS_SIZE=0x450000 +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/volteer/voxel/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/volteer/voxel/me.bin" +CONFIG_BOARD_GOOGLE_VOXEL=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/volteer/voxel/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y +CONFIG_NO_GFX_INIT=y +CONFIG_INTEL_GMA_ADD_VBT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/whl/config.librem_mini.uefi b/configs/whl/config.librem_mini.uefi new file mode 100644 index 00000000000..22cbd28c959 --- /dev/null +++ b/configs/whl/config.librem_mini.uefi @@ -0,0 +1,12 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_PURISM=y +CONFIG_IFD_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/purism-blobs/mainboard/purism/librem_cnl/mini/me.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PURISM_LIBREM_MINI=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/purism-blobs/mainboard/purism/librem_cnl/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/whl/config.sarien.uefi b/configs/whl/config.sarien.uefi new file mode 100644 index 00000000000..ae863be6390 --- /dev/null +++ b/configs/whl/config.sarien.uefi @@ -0,0 +1,18 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_VENDOR_GOOGLE=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_INTEL_GMA_VBT_FILE="3rdparty/blobs/mainboard/google/sarien/vbt.bin" +CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/flashdescriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/gbe.bin" +CONFIG_BOARD_GOOGLE_SARIEN=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="3rdparty/blobs/mainboard/google/sarien/cpu_microcode_blob.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_HAVE_EC_BIN=y +CONFIG_EC_BIN_PATH="3rdparty/blobs/mainboard/google/sarien/ec.bin" +CONFIG_NO_GFX_INIT=y +CONFIG_PAYLOAD_TIANOCORE=y +CONFIG_TIANOCORE_GOP_DRIVER=y diff --git a/configs/zen2/config.morphius.uefi b/configs/zen2/config.morphius.uefi new file mode 100644 index 00000000000..eeef146b4eb --- /dev/null +++ b/configs/zen2/config.morphius.uefi @@ -0,0 +1,11 @@ +CONFIG_LOCALVERSION="MrChromebox-4.17.2" +CONFIG_USE_AMD_BLOBS=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_NO_POST=y +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_BOARD_GOOGLE_MORPHIUS=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_USER=y +CONFIG_FRAMEBUFFER_VESA_MODE=0x1d4 +CONFIG_PAYLOAD_TIANOCORE=y diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 8b167ed784a..0b23614380b 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -169,18 +169,29 @@ $(obj)/UEFIPAYLOAD.fd edk2: $(DOTCONFIG) CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \ CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \ CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \ + CONFIG_EDK2_BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) \ CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \ CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \ CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \ CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \ CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \ + CONFIG_EDK2_IPXE=$(CONFIG_EDK2_ENABLE_IPXE) \ + CONFIG_EDK2_OPAL_PASSWORD=$(CONFIG_EDK2_OPAL_PASSWORD) \ CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \ CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \ + CONFIG_EDK2_SATA_PASSWORD=$(CONFIG_EDK2_SATA_PASSWORD) \ CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \ + CONFIG_EDK2_SECURE_BOOT=$(CONFIG_EDK2_SECURE_BOOT) \ + CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE=$(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE) \ + CONFIG_EDK2_SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) \ CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \ + CONFIG_EDK2_TPM_ENABLE=$(CONFIG_TPM1)$(CONFIG_TPM2) \ CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \ CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \ CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \ + CONFIG_EDK2_GOP_DRIVER=$(CONFIG_EDK2_GOP_DRIVER) \ + CONFIG_EDK2_GOP_FILE=$(CONFIG_EDK2_GOP_FILE) \ + CONFIG_EDK2_VBT_FILE=$(CONFIG_INTEL_GMA_VBT_FILE) \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ @@ -316,6 +327,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT) CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \ CONFIG_PXE_NO_PROMPT=$(CONFIG_PXE_NO_PROMPT) \ CONFIG_PXE_HAS_HTTPS=$(CONFIG_PXE_HAS_HTTPS) \ + CONFIG_PXE_CUSTOM_BUILD_ID=$(CONFIG_PXE_CUSTOM_BUILD_ID) \ MFLAGS= MAKEFLAGS= # LinuxBoot diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index ec6be897e3a..5ee670da74e 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -118,7 +118,7 @@ config EDK2_BOOTSPLASH_FILE config EDK2_BOOT_MANAGER_ESCAPE bool "Use Escape key for Boot Manager" - default n + default y help Use Escape as the hot-key to access the Boot Manager. This replaces the default key of F2. @@ -141,7 +141,7 @@ config EDK2_CBMEM_LOGGING config EDK2_FOLLOW_BGRT_SPEC bool "Center logo 38.2% from the top of screen" - default n + default y help Follow the BGRT Specification implemented by Microsoft and the Boot Logo 38.2% will be vertically centered 38.2% from @@ -180,6 +180,23 @@ config EDK2_SD_MMC_TIMEOUT The amount of time allowed to initialize the SD Card reader and/or eMMC drive. Most only require 10ms, but certain readers can take 1s. +config EDK2_GOP_DRIVER + bool "Add a GOP driver to the Tianocore build" + depends on INTEL_GMA_ADD_VBT + +config EDK2_GOP_FILE + string "GOP driver file" + depends on EDK2_GOP_DRIVER + default "3rdparty/blobs/soc/intel/bdw/IntelGopDriver.efi" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "3rdparty/blobs/soc/intel/byt/IntelGopDriver.efi" if SOC_INTEL_BAYTRAIL + default "3rdparty/blobs/soc/intel/bsw/IntelGopDriver.efi" if SOC_INTEL_BRASWELL + default "3rdparty/blobs/soc/intel/kbl/IntelGopDriver.efi" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE + default "3rdparty/blobs/soc/intel/glk/IntelGopDriver.efi" if SOC_INTEL_GEMINILAKE + default "3rdparty/blobs/soc/intel/apl/IntelGopDriver.efi" if SOC_INTEL_APOLLOLAKE + default "3rdparty/blobs/soc/intel/cml/IntelGopDriver.efi" if SOC_INTEL_COMETLAKE || SOC_INTEL_WHISKEYLAKE + default "3rdparty/blobs/soc/intel/tgl/IntelGopDriver.efi" if SOC_INTEL_TIGERLAKE + default "IntelGopDriver.efi" + config EDK2_SERIAL_SUPPORT bool "Support serial output" default y if EDK2_DEBUG @@ -188,6 +205,95 @@ config EDK2_SERIAL_SUPPORT Enable serial port output in edk2. Serial output limits the performance of edk2's FrontPage. +config EDK2_ENABLE_IPXE + bool "Include iPXE in edk2 payload" + default n + help + Includes a prebuilt iPXE for EFI to the EDK2 payload. + +config EDK2_SECURE_BOOT + bool "Enable UEFI Secure Boot" + depends on SMMSTORE_V2 + default n + help + Enables UEFI Secure Boot image verification in EDK2 Payload. + +config EDK2_SATA_PASSWORD + bool "Enable TianoCore SATA disk password" + default n + help + Enable SATA disk password suupport in the TianoCore payload. + +config EDK2_OPAL_PASSWORD + bool "Enable TianoCore TCG OPAL password" + default n + help + Enables TCG OPAL disk password in the TianoCore Payload. + +config EDK2_BOOT_MENU_KEY + hex "TianoCore boot menu key" + default 0x0016 + help + Select the TianoCore payload boot menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +config EDK2_SETUP_MENU_KEY + hex "TianoCore setup menu key" + default 0x0017 + help + Select the TianoCore payload setup menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +if EDK2_SECURE_BOOT + +config EDK2_SECURE_BOOT_DEFAULT_ENABLE + bool "Set Secure Boot state to enabled by default" + default y + help + Sets the UEFI Secure Boot state to enabled by default. + +endif + endif config EDK2_CUSTOM_BUILD_PARAMS @@ -200,4 +306,10 @@ config EDK2_CUSTOM_BUILD_PARAMS This option can support both macros `-D` and Pcds `--pcd`. +config EDK2_USE_8254_TIMER + bool "TianoCore 8254 Timer" + help + Use 8254 Timer for legacy support. + + endif diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index a03acbf406c..6cc63296964 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -32,19 +32,19 @@ endif ifeq ($(CONFIG_EDK2_RELEASE),y) BUILD_STR += -b RELEASE endif -# DISABLE_SERIAL_TERMINAL = FALSE -ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) -BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE +# SERIAL_TERMINAL = TRUE +ifeq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) +BUILD_STR += -D SERIAL_TERMINAL=TRUE endif # FOLLOW_BGRT_SPEC = FALSE ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y) BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE endif -# PCIE_BASE_ADDRESS = 0 +# PCIE_BASE_ADDRESS = 0 ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),) BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) endif -# PCIE_BASE_LENGTH = 0 +# PCIE_BASE_LENGTH = 0 ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),) BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH) endif @@ -76,6 +76,37 @@ endif ifneq ($(CONFIG_EDK2_SD_MMC_TIMEOUT),) BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_EDK2_SD_MMC_TIMEOUT) * 1000)) ) endif +# EDK2_GOP_DRIVER = FALSE +ifeq ($(CONFIG_EDK2_GOP_DRIVER), y) +BUILD_STR += -D USE_PLATFORM_GOP=TRUE +endif +# NETWORK_IPXE = FALSE +ifeq ($(CONFIG_EDK2_IPXE),y) +BUILD_STR += -D NETWORK_IPXE=TRUE +endif +# SECURE_BOOT_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_SECURE_BOOT),y) +BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE +endif +# SECURE_BOOT_DEFAULT_ENABLE = TRUE +ifneq ($(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE),y) +BUILD_STR += -D SECURE_BOOT_DEFAULT_ENABLE=FALSE +endif +# SATA_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_SATA_PASSWORD),y) +BUILD_STR += -D SATA_PASSWORD_ENABLE=TRUE +endif +# OPAL_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_OPAL_PASSWORD),y) +BUILD_STR += -D OPAL_PASSWORD_ENABLE=TRUE +endif +# TPM_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_TPM_ENABLE),y) +BUILD_STR += -D TPM_ENABLE=TRUE +endif + +BUILD_STR += -D BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) +BUILD_STR += -D SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) # # EDKII has the below PCDs that are relevant to coreboot: @@ -124,10 +155,10 @@ update: $(project_dir) logo: $(project_dir) case "$(CONFIG_EDK2_BOOTSPLASH_FILE)" in \ "") ;; \ - /*) convert -background None $(CONFIG_EDK2_BOOTSPLASH_FILE) \ - BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ - *) convert -background None $(top)/$(CONFIG_EDK2_BOOTSPLASH_FILE) \ - BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ + /*) cp $(CONFIG_EDK2_BOOTSPLASH_FILE) \ + $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ + *) cp $(top)/$(CONFIG_EDK2_BOOTSPLASH_FILE) \ + $(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \ esac \ checktools: @@ -141,15 +172,15 @@ checktools: echo -n "EDK2: Checking nasm:" type nasm > /dev/null 2>&1 && echo " Found!" || \ ( echo " Not found!"; echo "ERROR: Please install nasm."; exit 1 ) - echo -n "EDK2: Checking imagemagick:" - -convert -size 1x1 xc: test.png &> /dev/null; - if [ -f test.png ]; then \ - rm test.png && echo " Found!"; \ - else \ - echo " Not found!"; \ - echo "ERROR: Please install imagemagick"; \ - exit 1; \ - fi +# echo -n "EDK2: Checking imagemagick:" +# -convert -size 1x1 xc: test.png &> /dev/null; +# if [ -f test.png ]; then \ +# rm test.png && echo " Found!"; \ +# else \ +# echo " Not found!"; \ +# echo "ERROR: Please install imagemagick"; \ +# exit 1; \ +# fi print: echo " ##### $(project_name) Build Summary #####" @@ -168,6 +199,11 @@ print: build: update print logo checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1 + if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \ + echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(project_dir)/UefiPayloadPkg/IntelGopDriver.efi; \ + cp $(top)/$(CONFIG_EDK2_VBT_FILE) $(project_dir)/UefiPayloadPkg/vbt.bin; \ + fi; \ cd $(project_dir); \ export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \ export WORKSPACE=$(project_dir); \ diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 645d41b55b6..0fdb5521f21 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -110,5 +110,12 @@ config PXE_HAS_HTTPS Enable HTTPS protocol, which allows you to encrypt all communication with a web server and to verify the server's identity +config PXE_CUSTOM_BUILD_ID + string "iPXE custom build_id variable" + default "" + help + This option allows user to customize build_id for reproducible builds. + It is 32-bit hexadecimal number without "0x" prefix. + endmenu endif diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index b6aa1b63efd..41b5199cca8 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -11,6 +11,17 @@ project_name=iPXE project_dir=ipxe project_git_repo=https://git.ipxe.org/ipxe.git +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +ifneq ($(CONFIG_PXE_CUSTOM_BUILD_ID),) +PXE_MAKE_OPTS := BUILD_ID_CMD="echo 0x$(CONFIG_PXE_CUSTOM_BUILD_ID)" +endif + all: build $(project_dir): @@ -60,10 +71,10 @@ endif build: config $(CONFIG_SCRIPT) ifeq ($(CONFIG_HAS_SCRIPT),y) echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) $(PXE_MAKE_OPTS) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom $(PXE_MAKE_OPTS) endif cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) diff --git a/shrinkconfigs.sh b/shrinkconfigs.sh new file mode 100644 index 00000000000..82af5b14e25 --- /dev/null +++ b/shrinkconfigs.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +for filename in configs/.config.*; do + [ -e "$filename" ] || continue + cp "$filename" .config + make savedefconfig + cp defconfig "$filename" +done diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 78d5f07045e..06b3086c20d 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -440,6 +440,9 @@ static void acpi_ssdt_write_cbtable(void) acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", 0); acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index fd41ff23f14..240b52d0c88 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -277,59 +277,15 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, return smbios_full_table_len(&t->header, t->eos); } -#define VERSION_VPD "firmware_version" -static const char *vpd_get_bios_version(void) +static const char *get_bios_framework_string(void) { - int size; - const char *s; - char *version; - - s = vpd_find(VERSION_VPD, &size, VPD_RO); - if (!s) { - printk(BIOS_ERR, "Find version from VPD %s failed\n", VERSION_VPD); - return NULL; - } - - version = malloc(size + 1); - if (!version) { - printk(BIOS_ERR, "Failed to malloc %d bytes for VPD version\n", size + 1); - return NULL; - } - memcpy(version, s, size); - version[size] = '\0'; - printk(BIOS_DEBUG, "Firmware version %s from VPD %s\n", version, VERSION_VPD); - return version; -} + if (CONFIG(PAYLOAD_SEABIOS)) + return "coreboot+SeaBIOS"; -static const char *get_bios_version(void) -{ - const char *s; - -#define SPACES \ - " " + if (CONFIG(PAYLOAD_EDK2)) + return "coreboot+UEFI"; - if (CONFIG(CHROMEOS)) - return SPACES; - - if (CONFIG(VPD_SMBIOS_VERSION)) { - s = vpd_get_bios_version(); - if (s != NULL) - return s; - } - - s = smbios_mainboard_bios_version(); - if (s != NULL) - return s; - - if (strlen(CONFIG_LOCALVERSION) != 0) { - printk(BIOS_DEBUG, "BIOS version set to CONFIG_LOCALVERSION: '%s'\n", - CONFIG_LOCALVERSION); - return CONFIG_LOCALVERSION; - } - - printk(BIOS_DEBUG, "SMBIOS firmware version is set to coreboot_version: '%s'\n", - coreboot_version); - return coreboot_version; + return "coreboot"; } static int smbios_write_type0(unsigned long *current, int handle) @@ -337,16 +293,22 @@ static int smbios_write_type0(unsigned long *current, int handle) struct smbios_type0 *t = smbios_carve_table(*current, SMBIOS_BIOS_INFORMATION, sizeof(*t), handle); - t->vendor = smbios_add_string(t->eos, "coreboot"); + char bversion[100]; + + t->vendor = smbios_add_string(t->eos, "3mdeb"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); + snprintf(bversion, sizeof(bversion), "Dasharo (%s) %s", + get_bios_framework_string(), dasharo_version); + t->bios_version = smbios_add_string(t->eos, bversion); + if (CONFIG(CHROMEOS_NVS)) { uintptr_t version_address = (uintptr_t)t->eos; /* SMBIOS offsets start at 1 rather than 0 */ version_address += (u32)smbios_string_table_len(t->eos) - 1; smbios_type0_bios_version(version_address); } - t->bios_version = smbios_add_string(t->eos, get_bios_version()); + uint32_t rom_size = CONFIG_ROM_SIZE; rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB); t->bios_rom_size = (rom_size / 65535) - 1; @@ -357,8 +319,8 @@ static int smbios_write_type0(unsigned long *current, int handle) t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); } - t->system_bios_major_release = coreboot_major_revision; - t->system_bios_minor_release = coreboot_minor_revision; + t->system_bios_major_release = dasharo_major_revision; + t->system_bios_minor_release = dasharo_minor_revision; smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release); diff --git a/src/device/Kconfig b/src/device/Kconfig index 6f4a24ef1aa..b6b53a05b0e 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -897,6 +897,28 @@ config INTEL_GMA_VBT_FILE help The path and filename of the VBT binary. +config SET_GOP_DRIVER_VERSION + bool "Set the GOP Driver version" + depends on INTEL_GMA_ADD_VBT + default y if INTEL_GMA_ADD_VBT + help + Inject the GOP driver version into the OpRegion ACPI table. + +config GOP_DRIVER_VERSION + string "GOP Driver version" + depends on SET_GOP_DRIVER_VERSION + default "2.0.1024" if NORTHBRIDGE_INTEL_SANDYBRIDGE + default "5.5.1034" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL + default "7.2.1013" if SOC_INTEL_BAYTRAIL + default "8.0.1041" if SOC_INTEL_BRASWELL + default "9.0.1080" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE + default "9.0.1107" if SOC_INTEL_COMETLAKE || SOC_INTEL_WHISKEYLAKE + default "13.0.1018" if SOC_INTEL_GEMINILAKE + default "10.0.1037" if SOC_INTEL_APOLLOLAKE + default "17.0.1064" if SOC_INTEL_TIGERLAKE + help + Must be in the format X.Y.ZZZZ + config SOFTWARE_I2C bool "Enable I2C controller emulation in software" default n diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index a99b09536e1..cbb4081ec0e 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -11,6 +11,7 @@ struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ + const char *sub; /* ACPI _SUB */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned int uid; /* ACPI _UID */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 872891b64b2..43176f37889 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -83,6 +83,12 @@ void i2c_generic_fill_ssdt(const struct device *dev, acpigen_write_name_string("_HID", config->hid); if (config->cid) acpigen_write_name_string("_CID", config->cid); + if (config->sub) + acpigen_write_name_string("_SUB", config->sub); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + else + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); if (config->desc) acpigen_write_name_string("_DDN", config->desc); diff --git a/src/drivers/i2c/max98373/max98373.c b/src/drivers/i2c/max98373/max98373.c index eb5590d3e22..6178fe1b8a2 100644 --- a/src/drivers/i2c/max98373/max98373.c +++ b/src/drivers/i2c/max98373/max98373.c @@ -32,6 +32,9 @@ static void max98373_fill_ssdt(const struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", MAX98373_ACPI_HID); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); if (config->desc) acpigen_write_name_string("_DDN", config->desc); diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c index e80f569f1d2..51404c620ae 100644 --- a/src/drivers/i2c/max98927/max98927.c +++ b/src/drivers/i2c/max98927/max98927.c @@ -30,6 +30,9 @@ static void max98927_fill_ssdt(const struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", MAX98927_ACPI_HID); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); if (config->desc) acpigen_write_name_string("_DDN", config->desc); diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 49b107cb1c0..58fbd668c91 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -8,6 +8,7 @@ #include struct drivers_i2c_rt5663_config { + const char *sub; /* I2C Bus Frequency in Hertz (default 400kHz) */ unsigned int bus_speed; /* Identifier for multiple chips */ diff --git a/src/drivers/i2c/rt5663/rt5663.c b/src/drivers/i2c/rt5663/rt5663.c index 9949566c048..ee77082ceb7 100644 --- a/src/drivers/i2c/rt5663/rt5663.c +++ b/src/drivers/i2c/rt5663/rt5663.c @@ -33,6 +33,12 @@ static void rt5663_fill_ssdt(const struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", RT5663_ACPI_HID); + if (config->sub) + acpigen_write_name_string("_SUB", config->sub); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + else + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); diff --git a/src/drivers/i2c/tpm/chip.c b/src/drivers/i2c/tpm/chip.c index 07052f6f0dc..5697054cd2f 100644 --- a/src/drivers/i2c/tpm/chip.c +++ b/src/drivers/i2c/tpm/chip.c @@ -33,6 +33,12 @@ static void i2c_tpm_fill_ssdt(const struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); + if (config->sub) + acpigen_write_name_string("_SUB", config->sub); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + else + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); diff --git a/src/drivers/i2c/tpm/chip.h b/src/drivers/i2c/tpm/chip.h index 4eac7e16f47..2247a7b69f6 100644 --- a/src/drivers/i2c/tpm/chip.h +++ b/src/drivers/i2c/tpm/chip.h @@ -11,6 +11,7 @@ enum tpm_power_managed_mode { struct drivers_i2c_tpm_config { const char *hid; /* ACPI _HID (required) */ + const char *sub; /* ACPI _SUB */ const char *desc; /* Device Description */ unsigned int uid; /* ACPI _UID */ enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ diff --git a/src/drivers/intel/gma/acpi.c b/src/drivers/intel/gma/acpi.c index b2086864555..ba81cfec7f4 100644 --- a/src/drivers/intel/gma/acpi.c +++ b/src/drivers/intel/gma/acpi.c @@ -67,7 +67,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring("^^XBCL"); acpigen_pop_len(); - +#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) /* Method (_BCM, 1, NotSerialized) { @@ -78,7 +78,7 @@ drivers_intel_gma_displays_ssdt_generate(const struct i915_gpu_controller_info * acpigen_emit_namestring("^^XBCM"); acpigen_emit_byte(ARG0_OP); acpigen_pop_len(); - +#endif /* Method (_BQC, 0, NotSerialized) { diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index fe333fa6742..ed7bea6f5ca 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -350,6 +350,12 @@ enum cb_err intel_gma_init_igd_opregion(void) /* Get the opregion version information */ opregion->header.opver = opregion_get_version(); +#if CONFIG(SET_GOP_DRIVER_VERSION) + /* Inject GOP driver version */ + memcpy(opregion->header.dver, STR16(CONFIG_GOP_DRIVER_VERSION), + 2 * strlen(CONFIG_GOP_DRIVER_VERSION)); + +#endif /* Extended VBT support */ if (is_ext_vbt_required(opregion, vbt)) { /* Place extended VBT just after opregion */ @@ -371,7 +377,10 @@ enum cb_err intel_gma_init_igd_opregion(void) // TODO Initialize Mailbox 1 opregion->mailbox1.clid = 1; - // TODO Initialize Mailbox 3 + //From Intel OpRegion reference doc + opregion->header.pcon = 279; + + // Initialize Mailbox 3 opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index 1dd177c2db6..69c31a69292 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -41,8 +41,7 @@ typedef struct { #define IGD_MBOX4 (1 << 3) #define IGD_MBOX5 (1 << 4) -#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ - IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_MOBILE (IGD_MBOX1| IGD_MBOX3 | IGD_MBOX4 | IGD_MBOX5) #define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) #define SBIOS_VERSION_SIZE 32 diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 32e02759c14..2efaeb7cddc 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -379,6 +379,7 @@ static void r8168_net_fill_ssdt(const struct device *dev) if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* Power Resource */ if (CONFIG(RT8168_GEN_ACPI_POWER_RESOURCE) && config->has_power_resource) { diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index abebd880953..d3723717991 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -97,6 +97,12 @@ static void spi_acpi_fill_ssdt_generator(const struct device *dev) acpigen_write_name_string("_HID", config->hid); if (config->cid) acpigen_write_name_string("_CID", config->cid); + if (config->sub) + acpigen_write_name_string("_SUB", config->sub); +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + else + acpigen_write_name_string("_SUB", CONFIG_ACPI_SUBSYSTEM_ID); +#endif acpigen_write_name_integer("_UID", config->uid); if (config->desc) acpigen_write_name_string("_DDN", config->desc); diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h index 9849f177f87..1378027e7ca 100644 --- a/src/drivers/spi/acpi/chip.h +++ b/src/drivers/spi/acpi/chip.h @@ -8,6 +8,7 @@ struct drivers_spi_acpi_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ + const char *sub; /* ACPI _SUB */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned int uid; /* ACPI _UID */ diff --git a/src/drivers/vpd/Kconfig b/src/drivers/vpd/Kconfig index 7d45eb6a850..1b4f7ca9943 100644 --- a/src/drivers/vpd/Kconfig +++ b/src/drivers/vpd/Kconfig @@ -2,7 +2,7 @@ config VPD bool "Support for Vital Product Data tables" - default n + default y if !DRIVERS_GENERIC_CBFS_SERIAL help Enable support for flash based vital product data. @@ -23,4 +23,4 @@ config VPD_FMAP_SIZE config SMBIOS_SERIAL_FROM_VPD bool "Load device serial from VPD" depends on VPD && GENERATE_SMBIOS_TABLES - default n + default y diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index 53390b09765..e30f51b4127 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -6,8 +6,24 @@ Device (SIO) { Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) -// Keyboard or AUX port (a.k.a Mouse) +// PS2 Keyboard #ifdef SIO_EC_ENABLE_PS2K - #include + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, Package() { EISAID("PNP030B"), "GGL0303" } ) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xF) + } + } #endif } diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index f6c53d3880f..7fdc148e187 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -21,7 +21,7 @@ endif bootblock-y += ec.c bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c -ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c +ramstage-y += ec.c crosec_proto.c vstore.c usbc_mux.c utility.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c @@ -62,7 +62,6 @@ cbfs-files-y += ecrw ecrw-file := $(obj)/mainboard/$(MAINBOARDDIR)/ecrw ecrw-name := ecrw ecrw-type := raw -ecrw-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += ecrw.hash ecrw.hash-file := $(obj)/mainboard/$(MAINBOARDDIR)/ecrw.hash ecrw.hash-name := ecrw.hash diff --git a/src/ec/google/chromeec/acpi/ac.asl b/src/ec/google/chromeec/acpi/ac.asl index ccab7ce0058..abf3c2c5741 100644 --- a/src/ec/google/chromeec/acpi/ac.asl +++ b/src/ec/google/chromeec/acpi/ac.asl @@ -5,6 +5,9 @@ Device (AC) { Name (_HID, "ACPI0003") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_PCL, Package () { \_SB }) Method (_PSR) diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 702fbb1112a..7fa90f51277 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -229,6 +229,9 @@ Method (BBST, 4, Serialized) Device (BAT0) { Name (_HID, EISAID ("PNP0C0A")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_PCL, Package () { \_SB }) @@ -279,8 +282,8 @@ Device (BAT0) }) Name (BSTP, Zero) - // Workaround for full battery status, disabled by default - Name (BFWK, Zero) + // Workaround for full battery status, enabled by default + Name (BFWK, One) // Method to enable full battery workaround Method (BFWE) @@ -369,8 +372,8 @@ Device (BAT1) }) Name (BSTP, Zero) - // Workaround for full battery status, disabled by default - Name (BFWK, Zero) + // Workaround for full battery status, enabled by default + Name (BFWK, One) // Method to enable full battery workaround Method (BFWE) diff --git a/src/ec/google/chromeec/acpi/cros_ec.asl b/src/ec/google/chromeec/acpi/cros_ec.asl index 5a9541349b5..23dead10d8d 100644 --- a/src/ec/google/chromeec/acpi/cros_ec.asl +++ b/src/ec/google/chromeec/acpi/cros_ec.asl @@ -3,37 +3,22 @@ Device (CREC) { Name (_HID, "GOOG0004") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_DDN, "EC Command Device") #ifdef EC_ENABLE_WAKE_PIN Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) #endif -#ifdef EC_ENABLE_SYNC_IRQ - Name (_CRS, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive) - { - EC_SYNC_IRQ - } - }) -#endif - -#ifdef EC_ENABLE_SYNC_IRQ_GPIO - Name (_CRS, ResourceTemplate () - { - GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, - "\\_SB.GPIO", 0x00, ResourceConsumer, ,) - { - EC_SYNC_IRQ - } - }) -#endif - #ifdef EC_ENABLE_MKBP_DEVICE Device (CKSC) { Name (_HID, "GOOG0007") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_DDN, "EC MKBP Device") } @@ -53,7 +38,7 @@ Device (CREC) #endif Method(_STA, 0) { - Return (0xB) + Return (0xF) } #if CONFIG(DRIVERS_ACPI_THERMAL_ZONE) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index c0c1abb9ad1..4d9f2fffee3 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -18,6 +18,9 @@ External(\_SB.DPTC, MethodObj) Device (EC0) { Name (_HID, EISAID ("PNP0C09")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_GPE, EC_SCI_GPI) Name (TOFS, EC_TEMP_SENSOR_OFFSET) @@ -101,6 +104,9 @@ Device (EC0) Device (LID0) { Name (_HID, EisaId ("PNP0C0D")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Method (_LID, 0) { Return (^^LIDS) @@ -385,7 +391,15 @@ Device (EC0) \_SB.DPTF.TPET() #endif #ifdef EC_ENABLE_TBMC_DEVICE - Notify (TBMC, 0x80) + If (LEqual(_OSI("Linux"), 1)) { + Notify (TBMC, 0x80) + } else { + If (LEqual ((^TBMD), One)) { + Notify (VBTN, 0xCC) + } Else { + Notify (VBTN, 0xCD) + } + } #endif #ifdef EC_ENABLE_AMD_DPTC_SUPPORT If (CondRefOf (\_SB.DPTC)) { @@ -574,5 +588,6 @@ Device (EC0) #ifdef EC_ENABLE_TBMC_DEVICE #include "tbmc.asl" + #include "vbtn.asl" #endif } diff --git a/src/ec/google/chromeec/acpi/keyboard_backlight.asl b/src/ec/google/chromeec/acpi/keyboard_backlight.asl index 4c306d50c3b..d12a4fe5499 100644 --- a/src/ec/google/chromeec/acpi/keyboard_backlight.asl +++ b/src/ec/google/chromeec/acpi/keyboard_backlight.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Scope (\_SB) +/* Scope modified for coolstar's Windows driver */ +Scope (\_SB.PCI0.LPCB.EC0.CREC) { /* * Chrome EC Keyboard Backlight interface @@ -8,30 +9,34 @@ Scope (\_SB) Device (KBLT) { Name (_HID, "GOOG0002") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + } +} + +Scope (\_SB) +{ + /* + * Stub for linux driver which hardcodes location + */ + Device (KBLT) + { + Name (_HID, "GOOG0002") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) - /* Ask EC if we even have a backlight - * Return 0xf (present, enabled, show in UI, functioning) or 0 - * - * With older EC codebases that don't support the Device - * Features bitfield, this reports the keyboard backlight as - * enabled since reads to undefined addresses in EC address - * space return 0xff and so KBLE will be 1. - */ Method (_STA, 0, NotSerialized) { - /* If query is unsupported, but this code is compiled - * in, assume the backlight exists physically. - */ - If (\_SB.PCI0.LPCB.EC0.DFUD == 1) { - Return (0xf) - } - /* If EC reports that backlight exists, trust it */ - If (\_SB.PCI0.LPCB.EC0.KBLE == 1) { - Return (0xf) - } - /* Otherwise: no device -> disable */ - Return (0) + Return (0x0) } /* Read current backlight value */ diff --git a/src/ec/google/chromeec/acpi/pd.asl b/src/ec/google/chromeec/acpi/pd.asl index 5b45ab1b2b9..89a5ab2cad9 100644 --- a/src/ec/google/chromeec/acpi/pd.asl +++ b/src/ec/google/chromeec/acpi/pd.asl @@ -3,6 +3,9 @@ Device (ECPD) { Name (_HID, "GOOG0003") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_DDN, "EC PD Device") Method(_STA, 0) diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 84afa17ed1e..2222f2d8647 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -26,6 +26,9 @@ Device (SIO) { #ifdef SIO_EC_MEMMAP_ENABLE Device (ECMM) { Name (_HID, EISAID ("PNP0C02")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 4) Method (_STA, 0, NotSerialized) { @@ -43,6 +46,9 @@ Device (SIO) { #ifdef SIO_EC_HOST_ENABLE Device (ECUI) { Name (_HID, EISAID ("PNP0C02")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 3) Method (_STA, 0, NotSerialized) { @@ -70,6 +76,9 @@ Device (SIO) { #ifdef SIO_EC_ENABLE_COM1 Device (COM1) { Name (_HID, EISAID ("PNP0501")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Method (_STA, 0, NotSerialized) { @@ -93,6 +102,9 @@ Scope (\_SB.PCI0) Name (_UID, 0) Name (_HID, "GOOG000A") Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Method (_STA, 0, NotSerialized) { Return (0x0F) diff --git a/src/ec/google/chromeec/acpi/vbtn.asl b/src/ec/google/chromeec/acpi/vbtn.asl new file mode 100644 index 00000000000..9a9347e35b5 --- /dev/null +++ b/src/ec/google/chromeec/acpi/vbtn.asl @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* VGBS reports 0x40 when NOT in tablet mode. */ +/* Sent event 0xCC for tablet mode, 0xCD for laptop */ +/* Linux driver expects SMBIOS_ENCLOSURE_TYPE=SMBIOS_ENCLOSURE_CONVERTIBLE */ + +Device (VBTN) +{ + Name (_HID, "INT33D6") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif + Name (_DDN, "Tablet Virtual Buttons") + + Method (VBDL, 0) + { + } + + Method (VGBS) + { + If (LEqual (^^RCTM, One)) { + Return (0x0) + } Else { + Return (0x40) + } + } + Method(_STA, 0) + { + Return (0xF) + } +} + +Device (VBTO) +{ + Name (_HID, "INT33D3") + // _SUB intentionally excluded due to driver issue + Name (_CID, "PNP0C60") + Method (_STA, 0) + { + Return (0xF) + } +} diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 6604abd49e0..ebd4329ecf0 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -2,18 +2,25 @@ #include #include +#include #include +#include +#include #include #include #include #include #include +#include +#include #include #include #include #include #include "ec.h" +#include "ec_commands.h" +#include "utility.h" #define INVALID_HCMD 0xFF @@ -1341,42 +1348,78 @@ static void google_chromeec_log_uptimeinfo(void) printk(BIOS_DEBUG, "\n"); } -/* Cache and retrieve the EC image type (ro or rw) */ -enum ec_image google_chromeec_get_current_image(void) +static enum ec_current_image google_chromeec_get_version(void) { - static enum ec_image ec_image_type = EC_IMAGE_UNKNOWN; + struct chromeec_command cec_cmd; + struct ec_response_get_version cec_resp; + cec_cmd.cmd_code = EC_CMD_GET_VERSION; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = 0; + cec_cmd.cmd_data_out = &cec_resp; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(cec_resp); + cec_cmd.cmd_dev_index = 0; + google_chromeec_command(&cec_cmd); - if (ec_image_type != EC_IMAGE_UNKNOWN) - return ec_image_type; - - struct ec_response_get_version resp = {}; - struct chromeec_command cmd = { - .cmd_code = EC_CMD_GET_VERSION, - .cmd_version = 0, - .cmd_data_out = &resp, - .cmd_size_in = 0, - .cmd_size_out = sizeof(resp), - .cmd_dev_index = 0, - }; - - google_chromeec_command(&cmd); - - if (cmd.cmd_code) { + if (cec_cmd.cmd_code) { printk(BIOS_DEBUG, "Google Chrome EC: version command failed!\n"); + return EC_IMAGE_UNKNOWN; } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", resp.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", resp.version_string_rw); + printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", - resp.current_image); - ec_image_type = resp.current_image; + cec_resp.current_image); + return cec_resp.current_image; } +} + +/* Cached EC image type (ro or rw). */ +enum ec_current_image google_chromeec_get_current_image(void) +{ + static enum ec_current_image ec_image_type = EC_IMAGE_UNKNOWN; + + if (ec_image_type == EC_IMAGE_UNKNOWN) + ec_image_type = google_chromeec_get_version(); - /* Will still be UNKNOWN if command failed */ return ec_image_type; } +void google_chromeec_init(void) +{ + printk(BIOS_DEBUG, "Google Chrome EC: Initializing\n"); + + google_chromeec_log_uptimeinfo(); + + /* Check which EC image is active */ + google_chromeec_get_current_image(); + + /* Check/update EC RW image if needed */ + if (google_chromeec_swsync() != 0) { + printk(BIOS_ERR, "ChromeEC: EC SW SYNC FAILED\n"); + } else if (google_chromeec_get_current_image() != EC_IMAGE_RW) { + /* EC RW image is up to date, switch to it if not already*/ + google_chromeec_reboot(0, EC_REBOOT_JUMP_RW, 0); + mdelay(100); + /* Use Hello cmd to "reset" EC now in RW mode */ + google_chromeec_hello(); + /* re-run version command & print */ + google_chromeec_get_version(); + } + + /* Enable auto fan control if applicable */ + struct chromeec_command cec_cmd; + cec_cmd.cmd_code = EC_CMD_THERMAL_AUTO_FAN_CTRL; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = NULL; + cec_cmd.cmd_data_out = NULL; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = 0; + cec_cmd.cmd_dev_index = 0; + google_chromeec_command(&cec_cmd); +} + int google_chromeec_get_num_pd_ports(unsigned int *num_ports) { struct ec_response_charge_port_count resp = {}; @@ -1428,14 +1471,405 @@ int google_chromeec_get_pd_port_caps(int port, return 0; } -void google_chromeec_init(void) +int google_ec_running_ro(void) { - google_chromeec_log_uptimeinfo(); + return (google_chromeec_get_current_image() == EC_IMAGE_RO); } -int google_ec_running_ro(void) +void google_chromeec_reboot_ro(void) { - return (google_chromeec_get_current_image() == EC_IMAGE_RO); + /* Reboot the EC and make it come back in RO mode */ + printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n"); + post_code(0); /* clear current post code */ + google_chromeec_reboot(0, EC_REBOOT_COLD, 0); + udelay(1000); + board_reset(); + halt(); +} + +/* Timeout waiting for EC hash calculation completion */ +static const int CROS_EC_HASH_TIMEOUT_MS = 2000; + +/* Time to delay between polling status of EC hash calculation */ +static const int CROS_EC_HASH_CHECK_DELAY_MS = 10; + +int google_chromeec_swsync(void) +{ + static struct ec_response_vboot_hash resp; + uint8_t *ec_hash; + int ec_hash_size; + uint8_t *ecrw_hash, *ecrw; + int need_update = 0, i; + size_t ecrw_size; + + /* skip if on S3 resume path */ + if (acpi_is_wakeup_s3()) + return 0; + + /* Get EC_RW hash from CBFS */ + ecrw_hash = cbfs_map("ecrw.hash", NULL); + + if (!ecrw_hash) { + /* Assume no EC update file for this board */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: no EC_RW update available\n"); + return 0; + } + + /* Got an expected hash */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: Expected hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ecrw_hash[i]); + printk(BIOS_DEBUG, "\n"); + + /* Get hash of current EC-RW */ + if (google_chromeec_read_hash(&resp)) { + printk(BIOS_ERR, "Failed to read current EC_RW hash.\n"); + return -1; + } + ec_hash = resp.hash_digest; + ec_hash_size = resp.digest_size; + /* Check hash size */ + if (ec_hash_size != SHA256_DIGEST_SIZE) { + printk(BIOS_ERR, "ChromeEC SW Sync: - " + "read_hash says size %d, not %d\n", + ec_hash_size, SHA256_DIGEST_SIZE); + return -1; + } + + /* We got a proper hash */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: current EC_RW hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ec_hash[i]); + printk(BIOS_DEBUG, "\n"); + + /* compare hashes */ + need_update = SafeMemcmp(ec_hash, ecrw_hash, SHA256_DIGEST_SIZE); + + /* If in RW and need to update, return/reboot to RO */ + if (need_update && google_chromeec_get_current_image() == EC_IMAGE_RW + && !CONFIG(SOC_INTEL_CSE_LITE_SKU) && !CONFIG(BOARD_GOOGLE_BASEBOARD_FIZZ)) { + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW needs update but in RW; rebooting to RO\n"); + google_chromeec_reboot_ro(); + return -1; + } + + /* Update EC if necessary */ + if (need_update) { + printk(BIOS_DEBUG, "ChromeEC SW Sync: updating EC_RW...\n"); + + /* Get ecrw image from CBFS */ + ecrw = cbfs_map("ecrw", &ecrw_size); + if (!ecrw) { + printk(BIOS_ERR, "ChromeEC SW Sync: no ecrw image found in CBFS; cannot update\n"); + return -1; + } + + if (google_chromeec_flash_update_rw(ecrw, ecrw_size)) { + printk(BIOS_ERR, "ChromeEC SW Sync: Failed to update EC_RW.\n"); + return -1; + } + + /* Boards which jump to EC-RW early need a full reset here */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + google_chromeec_reboot_ro(); + } + + /* Have EC recompute hash for new EC_RW block */ + if (google_chromeec_read_hash(&resp) ) { + printk(BIOS_ERR, "ChromeEC SW Sync: Failed to read new EC_RW hash.\n"); + return -1; + } + + /* Compare new EC_RW hash to value from CBFS */ + ec_hash = resp.hash_digest; + if(SafeMemcmp(ec_hash, ecrw_hash, SHA256_DIGEST_SIZE)) { + /* hash mismatch! */ + printk(BIOS_DEBUG, "ChromeEC SW Sync: Expected hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ecrw_hash[i]); + printk(BIOS_DEBUG, "\n"); + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC hash: "); + for (i = 0; i < SHA256_DIGEST_SIZE; i++) + printk(BIOS_DEBUG, "%02x", ec_hash[i]); + printk(BIOS_DEBUG, "\n"); + return -1; + } + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW hashes match\n"); + printk(BIOS_DEBUG, "ChromeEC SW Sync: done\n"); + } else { + printk(BIOS_DEBUG, "ChromeEC SW Sync: EC_RW is up to date\n"); + } + + return 0; +} + +int google_chromeec_read_hash(struct ec_response_vboot_hash *hash) +{ + struct chromeec_command cec_cmd; + struct ec_params_vboot_hash p; + int recalc_requested = 0; + uint64_t start = timer_us(0); + + do { + /* Get hash if available. */ + p.cmd = EC_VBOOT_HASH_GET; + cec_cmd.cmd_code = EC_CMD_VBOOT_HASH; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = hash; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(*hash); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "ChromeEC: Getting hash:\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + + switch (hash->status) { + case EC_VBOOT_HASH_STATUS_NONE: + /* We have no valid hash - let's request a recalc + * if we haven't done so yet. */ + if (recalc_requested != 0) { + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + } + printk(BIOS_DEBUG, "ChromeEC: No valid hash (status=%d size=%d). " + "Compute one...\n", hash->status, hash->size); + p.cmd = EC_VBOOT_HASH_RECALC; + p.hash_type = EC_VBOOT_HASH_TYPE_SHA256; + p.nonce_size = 0; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + p.offset = EC_VBOOT_HASH_OFFSET_UPDATE; + } else { + p.offset = EC_VBOOT_HASH_OFFSET_RW; + } + p.size = 0; + cec_cmd.cmd_code = EC_CMD_VBOOT_HASH; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = hash; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(*hash); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "ChromeEC: Starting EC hash:\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + recalc_requested = 1; + /* Command will wait to return until hash is done/ready */ + break; + case EC_VBOOT_HASH_STATUS_BUSY: + /* Hash is still calculating. */ + mdelay(CROS_EC_HASH_CHECK_DELAY_MS); + break; + case EC_VBOOT_HASH_STATUS_DONE: + default: + /* We have a valid hash. */ + break; + } + } while (hash->status != EC_VBOOT_HASH_STATUS_DONE && + timer_us(start) < CROS_EC_HASH_TIMEOUT_MS * 1000); + if (hash->status != EC_VBOOT_HASH_STATUS_DONE) { + printk(BIOS_DEBUG, "ChromeEC: Hash status not done: %d\n", hash->status); + return -1; + } + return 0; +} + +int google_chromeec_flash_update_rw(const uint8_t *image, int image_size) +{ + uint32_t rw_offset, rw_size; + int ret; + enum ec_flash_region region; + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) { + region = EC_FLASH_REGION_UPDATE; + } else { + region = EC_FLASH_REGION_RW; + } + + /* get max size that can be written, offset to write */ + if (google_chromeec_flash_offset(region, &rw_offset, &rw_size)) + return -1; + if (image_size > rw_size) { + printk(BIOS_ERR, "Image size (%d) greater than flash region size (%d)\n", + image_size, rw_size); + return -1; + } + + /* + * Erase the entire RW section, so that the EC doesn't see any garbage + * past the new image if it's smaller than the current image. + * + */ + ret = google_chromeec_flash_erase(rw_offset, rw_size); + if (ret) + return ret; + /* Write the image */ + return(google_chromeec_flash_write(image, rw_offset, image_size)); +} + +int google_chromeec_flash_offset(enum ec_flash_region region, + uint32_t *offset, uint32_t *size) +{ + struct chromeec_command cec_cmd; + struct ec_params_flash_region_info p; + struct ec_response_flash_region_info r; + p.region = region; + + /* Get offset and size */ + cec_cmd.cmd_code = EC_CMD_FLASH_REGION_INFO; + cec_cmd.cmd_version = EC_VER_FLASH_REGION_INFO; + cec_cmd.cmd_data_in = &p; + cec_cmd.cmd_data_out = &r; + cec_cmd.cmd_size_in = sizeof(p); + cec_cmd.cmd_size_out = sizeof(r); + cec_cmd.cmd_dev_index = 0; + printk(BIOS_DEBUG, "Getting EC region info\n"); + if (google_chromeec_command(&cec_cmd)) + return -1; + + if (offset) + *offset = r.offset; + if (size) + *size = r.size; + return 0; +} + +static uint32_t burst = 0; + +int google_chromeec_flash_write(const uint8_t *data, uint32_t offset, uint32_t size) +{ + //printk(BIOS_DEBUG, "google_chromeec_flash_write(): 0x%x bytes at 0x%x\n", size, offset); + burst = google_chromeec_flash_write_burst_size(); + uint32_t end, off; + int ret; + if (!burst) + return -1; + end = offset + size; + printk(BIOS_DEBUG, "Writing EC RW region\n"); + for (off = offset; off < end; off += burst, data += burst) { + uint32_t todo = MIN(end - off, burst); + if (todo < burst) { + uint8_t *buf = malloc(burst); + memcpy(buf, data, todo); + // Pad the buffer with a decent guess for erased data + // value. + memset(buf + todo, 0xff, burst - todo); + ret = google_chromeec_flash_write_block_old(buf, + off, burst); + free(buf); + } else { + ret = google_chromeec_flash_write_block_old(data, + off, burst); + } + if (ret) + return ret; + } + return 0; +} + +/** + * Return optimal flash write burst size + */ +int google_chromeec_flash_write_burst_size(void) +{ + struct chromeec_command cec_cmd; + struct ec_response_flash_info info; + uint32_t pdata_max_size = EC_LPC_HOST_PACKET_SIZE - sizeof(struct ec_host_request) - + sizeof(struct ec_params_flash_write); + + /* + * Determine whether we can use version 1 of the command with more + * data, or only version 0. + */ + if (!google_chromeec_cmd_version_supported(EC_CMD_FLASH_WRITE, EC_VER_FLASH_WRITE)) + return EC_FLASH_WRITE_VER0_SIZE; + + /* + * Determine step size. This must be a multiple of the write block + * size, and must also fit into the host parameter buffer. + */ + cec_cmd.cmd_code = EC_CMD_FLASH_INFO; + cec_cmd.cmd_version = 0; + cec_cmd.cmd_data_in = NULL; + cec_cmd.cmd_data_out = &info; + cec_cmd.cmd_size_in = 0; + cec_cmd.cmd_size_out = sizeof(info); + cec_cmd.cmd_dev_index = 0; + if (google_chromeec_command(&cec_cmd)) + return -1; + + return (pdata_max_size / info.write_block_size) * + info.write_block_size; +} + +static uint8_t *buf = NULL; +static uint32_t bufsize = 0; + +/** + * Write a single block to the flash + * + * Write a block of data to the EC flash. The size must not exceed the flash + * write block size which you can obtain from cros_ec_flash_write_burst_size(). + * + * The offset starts at 0. You can obtain the region information from + * cros_ec_flash_offset() to find out where to write for a particular region. + * + * Attempting to write to the region where the EC is currently running from + * will result in an error. + * + * @param data Pointer to data buffer to write + * @param offset Offset within flash to write to. + * @param size Number of bytes to write + * @return 0 if ok, -1 on error + */ +int google_chromeec_flash_write_block_old(const uint8_t *data, + uint32_t offset, uint32_t size) +{ + struct chromeec_command cec_cmd; + struct ec_params_flash_write *p; + + assert(data); + /* Make sure request fits in the allowed packet size */ + if (bufsize == 0) { + bufsize = sizeof(*p) + size; + buf = malloc(bufsize); + } else if (bufsize != sizeof(*p) + size) { + free(buf); + bufsize = sizeof(*p) + size; + buf = malloc(bufsize); + } + if (bufsize > EC_LPC_HOST_PACKET_SIZE) + return -1; + + p = (struct ec_params_flash_write *)buf; + p->offset = offset; + p->size = size; + memcpy(p + 1, data, size); + + cec_cmd.cmd_code = EC_CMD_FLASH_WRITE; + cec_cmd.cmd_version = burst == EC_FLASH_WRITE_VER0_SIZE ? 0 : EC_VER_FLASH_WRITE; + cec_cmd.cmd_data_in = buf; + cec_cmd.cmd_data_out = NULL; + cec_cmd.cmd_size_in = bufsize; + cec_cmd.cmd_size_out = 0; + cec_cmd.cmd_dev_index = 0; + + return google_chromeec_command(&cec_cmd); +} + +/** + * Return non-zero if the EC supports the command and version + * + * @param cmd Command to check + * @param ver Version to check + * @return non-zero if command version supported; 0 if not. + */ +int google_chromeec_cmd_version_supported(int cmd, int ver) +{ + uint32_t mask = 0; + if (google_chromeec_get_cmd_versions(cmd, &mask)) + return 0; + return (mask & EC_VER_MASK(ver)) ? 1 : 0; } /* Returns data role and type of device connected */ diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 821eaa3b34b..64fc670ac05 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -353,6 +353,21 @@ struct usb_pd_port_caps { */ int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps); +#define SHA256_DIGEST_SIZE 32 + +void google_chromeec_reboot_ro(void); +void google_chromeec_reboot_rw(void); + +int google_chromeec_swsync(void); +int google_chromeec_read_hash(struct ec_response_vboot_hash *hash); +int google_chromeec_flash_update_rw(const uint8_t *image, int image_size); +int google_chromeec_flash_offset(enum ec_flash_region region, + uint32_t *offset, uint32_t *size); +int google_chromeec_flash_write(const uint8_t *data, uint32_t offset, uint32_t size); +int google_chromeec_flash_write_burst_size(void); +int google_chromeec_flash_write_block_old(const uint8_t *data, + uint32_t offset, uint32_t size); +int google_chromeec_cmd_version_supported(int cmd, int ver); /** * Get the keyboard configuration / layout information from EC diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index a82ea5d9abf..246018840af 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -94,8 +94,8 @@ static inline u8 write_byte(u8 val, u16 port) static int google_chromeec_status_check(u16 port, u8 mask, u8 cond) { struct stopwatch timeout_sw; - /* One second is more than plenty for any EC operation to complete */ - const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC; + /* Two seconds is more than plenty for any EC operation to complete */ + const uint64_t ec_status_timeout_us = 2 * USECS_PER_SEC; /* Wait 1 usec between read attempts */ const uint64_t ec_status_read_period_us = 1; diff --git a/src/ec/google/chromeec/utility.c b/src/ec/google/chromeec/utility.c new file mode 100644 index 00000000000..3448265d993 --- /dev/null +++ b/src/ec/google/chromeec/utility.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "utility.h" + +int SafeMemcmp(const void *s1, const void *s2, size_t n) +{ + const unsigned char *us1 = s1; + const unsigned char *us2 = s2; + int result = 0; + + if (0 == n) + return 0; + + /* + * Code snippet without data-dependent branch due to Nate Lawson + * (nate@root.org) of Root Labs. + */ + while (n--) + result |= *us1++ ^ *us2++; + + return result != 0; +} + +long timer_us(long startTime) +{ + struct mono_time now; + timer_monotonic_get(&now); + return (now.microseconds - startTime); +} diff --git a/src/ec/google/chromeec/utility.h b/src/ec/google/chromeec/utility.h new file mode 100644 index 00000000000..d832b6a1c40 --- /dev/null +++ b/src/ec/google/chromeec/utility.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * Compare [n] bytes starting at [s1] with [s2] and return 0 if they + * match, 1 if they don't. Returns 0 if n=0, since no bytes mismatched. + * + * Time taken to perform the comparison is only dependent on [n] and + * not on the relationship of the match between [s1] and [s2]. + * + * Note that unlike Memcmp(), this only indicates inequality, not + * whether s1 is less than or greater than s2. + */ +int SafeMemcmp(const void *s1, const void *s2, size_t n); + +long timer_us(long startTime); diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl index 5c88d669bc2..9ac3cfcaf1e 100644 --- a/src/ec/google/wilco/acpi/ec_dev.asl +++ b/src/ec/google/wilco/acpi/ec_dev.asl @@ -11,7 +11,7 @@ Device (WLCO) Method (_STA) { - Return (0xf) + Return (0xb) } Name (_CRS, ResourceTemplate () diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl index a779147abb3..b2737c321f9 100644 --- a/src/ec/google/wilco/acpi/superio.asl +++ b/src/ec/google/wilco/acpi/superio.asl @@ -36,7 +36,10 @@ Device (SIO) EndDependentFn () }) } +} +Scope (\_SB.PCI0) +{ Device (PS2K) { Name (_HID, EisaId ("PNP0303")) diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl index c76239a63bb..1cf6394f533 100644 --- a/src/ec/google/wilco/acpi/ucsi.asl +++ b/src/ec/google/wilco/acpi/ucsi.asl @@ -6,7 +6,7 @@ Device (UCSI) Name (_CID, EisaId ("PNP0CA0")) Name (_DDN, "Wilco EC UCSI") Name (_UID, One) - Name (_STA, 0xf) + Name (_STA, 0xb) /* Value written to EC control register to start UCSI command */ Name (UCMD, 0xE0) diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl index 008f573f759..c7f04d24392 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/superio.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl @@ -3,16 +3,15 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { + Name (_HID, EisaId("PNP0A05")) Name (_UID, 0) - Name (_ADR, 0) - #ifdef SIO_EC_ENABLE_PS2K Device (PS2K) // Keyboard { Name (_UID, 0) Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) + Name (_CID, Package() { EISAID("PNP030B"), "GGL0303" } ) Method (_STA, 0, NotSerialized) { Return (0x0F) diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl index 9cdf26581af..1d40598e4f9 100644 --- a/src/ec/quanta/it8518/acpi/superio.asl +++ b/src/ec/quanta/it8518/acpi/superio.asl @@ -12,7 +12,7 @@ Device (SIO) { Name (_UID, 0) Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) + Name (_CID, Package() { EISAID("PNP030B"), "GGL0303" } ) Method (_STA, 0, NotSerialized) { @@ -42,7 +42,8 @@ Device (SIO) #ifdef SIO_ENABLE_PS2M Device (PS2M) // Mouse { - Name (_HID, EISAID("PNP0F13")) + Name (_HID, EISAID("LEN2011")) + Name (_CID, EISAID("PNP0F13")) Method (_STA, 0, NotSerialized) { diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b6d778b4c96..177195e902b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -23,6 +23,7 @@ #define APM_CNT_ROUTE_ALL_XHCI 0xca #define APM_CNT_FINALIZE 0xcb #define APM_CNT_LEGACY 0xcc +#define APM_CNT_END_OF_DXE 0xcd #define APM_CNT_MBI_UPDATE 0xeb #define APM_CNT_SMMINFO 0xec #define APM_CNT_SMMSTORE 0xed diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 167be520dcd..5d7564bd763 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -299,6 +299,17 @@ struct nhlt_tdm_config { enum { NHLT_TDM_BASIC, NHLT_TDM_MIC_ARRAY, + NHLT_TDM_RENDER_WITH_LOOPBACK, + NHLT_TDM_RENDER_FEEDBACK, + NHLT_TDM_MULTI_MODE, + NHLT_TDM_MULTI_MODE_MIC_ARRAY = NHLT_TDM_MULTI_MODE | NHLT_TDM_MIC_ARRAY +}; + +struct nhlt_feedback_config { + struct nhlt_tdm_config tdm_config; + uint8_t feedback_virtual_slot; + uint16_t feedback_channels; + uint16_t feedback_valid_bits_per_sample; }; struct nhlt_dmic_array_config { diff --git a/src/include/string.h b/src/include/string.h index f595c7ed2e0..cc6208503b1 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -7,6 +7,10 @@ #include #include +/* Convert 8-bit char to 16-bit */ +#define STR16_(str) (u ## str) +#define STR16(str) STR16_(str) + void *memcpy(void *dest, const void *src, size_t n); void *memmove(void *dest, const void *src, size_t n); void *memset(void *s, int c, size_t n); diff --git a/src/include/version.h b/src/include/version.h index 84bb34a7b51..a0c7878cfe0 100644 --- a/src/include/version.h +++ b/src/include/version.h @@ -7,6 +7,12 @@ extern const char mainboard_vendor[]; extern const char mainboard_part_number[]; +/* Dasharo version */ +extern const char dasharo_version[]; +extern const unsigned int dasharo_major_revision; +extern const unsigned int dasharo_minor_revision; +extern const unsigned int dasharo_patch_revision; + /* coreboot Version */ extern const char coreboot_version[]; extern const char coreboot_extra_version[]; diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index a061b828646..b6fe9a652dc 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -181,14 +181,6 @@ int nhlt_endpoint_add_formats(struct nhlt_endpoint *endp, return 0; } -void nhlt_next_instance(struct nhlt *nhlt, int link_type) -{ - if (link_type < NHLT_LINK_HDA || link_type >= NHLT_MAX_LINK_TYPES) - return; - - nhlt->current_instance_id[link_type]++; -} - static size_t calc_specific_config_size(struct nhlt_specific_config *cfg) { return sizeof(cfg->size) + cfg->size; @@ -255,7 +247,7 @@ static size_t calc_size(struct nhlt *nhlt) size_t nhlt_current_size(struct nhlt *nhlt) { - return calc_size(nhlt) + sizeof(acpi_header_t); + return calc_size(nhlt) + sizeof(acpi_header_t) + sizeof(uint32_t); } static void nhlt_free_resources(struct nhlt *nhlt) @@ -360,12 +352,13 @@ static void serialize_endpoint(struct nhlt_endpoint *endp, struct cursor *cur) static void nhlt_serialize_endpoints(struct nhlt *nhlt, struct cursor *cur) { - int i; + int i, capabilities_size = 0; ser8(cur, nhlt->num_endpoints); for (i = 0; i < nhlt->num_endpoints; i++) serialize_endpoint(&nhlt->endpoints[i], cur); + ser32(cur, capabilities_size); } uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) @@ -468,12 +461,5 @@ int nhlt_add_endpoints(struct nhlt *nhlt, int nhlt_add_ssp_endpoints(struct nhlt *nhlt, int virtual_bus_id, const struct nhlt_endp_descriptor *epds, size_t num_epds) { - int ret; - - ret = _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds); - - if (!ret) - nhlt_next_instance(nhlt, NHLT_LINK_SSP); - - return ret; + return _nhlt_add_endpoints(nhlt, virtual_bus_id, epds, num_epds); } diff --git a/src/lib/version.c b/src/lib/version.c index 84718328f0f..d36626da6a7 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -25,6 +25,22 @@ #define COREBOOT_EXTRA_VERSION "" #endif +#ifndef DASHARO_VERSION +#define DASHARO_VERSION "*INVALID*" +#endif + +#ifndef DASHARO_MAJOR_VERSION +#define DASHARO_MAJOR_VERSION 0 +#endif + +#ifndef DASHARO_MINOR_VERSION +#define DASHARO_MINOR_VERSION 0 +#endif + +#ifndef DASHARO_PATCH_VERSION +#define DASHARO_PATCH_VERSION 0 +#endif + const char mainboard_vendor[] = CONFIG_MAINBOARD_VENDOR; const char mainboard_part_number[] = CONFIG_MAINBOARD_PART_NUMBER; @@ -35,6 +51,11 @@ const unsigned int coreboot_version_timestamp = COREBOOT_VERSION_TIMESTAMP; const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION; const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION; +const char dasharo_version[] = DASHARO_VERSION; +const unsigned int dasharo_major_revision = DASHARO_MAJOR_VERSION; +const unsigned int dasharo_minor_revision = DASHARO_MINOR_VERSION; +const unsigned int dasharo_patch_revision = DASHARO_PATCH_VERSION; + const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; const char coreboot_dmi_date[] = COREBOOT_DMI_DATE; diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index f503d465e8b..7edb9579e5e 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -76,4 +76,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif diff --git a/src/mainboard/google/auron/acpi/superio.asl b/src/mainboard/google/auron/acpi/superio.asl index e3a31bc657b..42eaba1825c 100644 --- a/src/mainboard/google/auron/acpi/superio.asl +++ b/src/mainboard/google/auron/acpi/superio.asl @@ -6,7 +6,6 @@ #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 /* ACPI code for EC SuperIO functions */ #include diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 6fa95e8dff3..cc10d97a007 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -77,6 +77,7 @@ void mainboard_smi_sleep(u8 slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) { google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index a2c435b2440..d04cd76ea28 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -74,4 +74,8 @@ config EDK2_BOOT_TIMEOUT int default 5 +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index c6b686ee6c5..614ac9b23d0 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -141,11 +141,7 @@ Scope (\_TZ) } Method (_AC4) { - If (\FLVL <= 4) { - Return (CTOK (FAN4_THRESHOLD_OFF)) - } Else { - Return (CTOK (FAN4_THRESHOLD_ON)) - } + Return (CTOK (0)) } Name (_AL0, Package () { FAN0 }) diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 33f4b6bf3d5..0df98bff955 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -19,8 +19,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) /* TPM Present */ gnvs->tpmp = 1; - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; gnvs->f3of = FAN3_THRESHOLD_OFF; diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8eada253260..7a2b9cac06f 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -87,6 +87,7 @@ chip northbridge/intel/haswell register "peci_tmpin" = "3" # Enable FAN2 register "fan2_enable" = "1" + register "fan2_speed" = "0x47" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h index f4c04743291..3bf0f6aa348 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/mccloud/include/variant/thermal.h @@ -3,29 +3,27 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 35 -#define FAN3_THRESHOLD_ON 40 -#define FAN3_PWM 0x88 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x68 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 44 -#define FAN2_THRESHOLD_ON 48 -#define FAN2_PWM 0x94 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x84 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 53 -#define FAN1_THRESHOLD_ON 58 -#define FAN1_PWM 0xb5 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa5 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 65 -#define FAN0_THRESHOLD_ON 70 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 #define FAN0_PWM 0xc4 /* Temperature which OS will shutdown at */ diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h index c2a2ef09b87..edde804e3b0 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/monroe/include/variant/thermal.h @@ -3,30 +3,28 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 45 -#define FAN3_THRESHOLD_ON 58 -#define FAN3_PWM 0x40 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x68 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x84 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 59 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb3 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa3 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 79 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xc4 /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 98 diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h index 27c6c337568..e953fd62ffc 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/panther/include/variant/thermal.h @@ -3,10 +3,8 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 40 @@ -14,19 +12,19 @@ #define FAN3_PWM 0x6b /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 75 -#define FAN2_THRESHOLD_ON 83 -#define FAN2_PWM 0xcc +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 86 -#define FAN1_THRESHOLD_ON 90 -#define FAN1_PWM 0xe5 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 93 -#define FAN0_THRESHOLD_ON 96 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h index 68db6b89e6e..1ca26b0df38 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/tricky/include/variant/thermal.h @@ -3,29 +3,27 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 50 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x76 +#define FAN3_THRESHOLD_ON 60 +#define FAN3_PWM 0x62 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 59 -#define FAN2_THRESHOLD_ON 65 -#define FAN2_PWM 0x98 +#define FAN2_THRESHOLD_OFF 65 +#define FAN2_THRESHOLD_ON 77 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 68 -#define FAN1_THRESHOLD_ON 75 -#define FAN1_PWM 0xbf +#define FAN1_THRESHOLD_OFF 77 +#define FAN1_THRESHOLD_ON 85 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 80 -#define FAN0_THRESHOLD_ON 86 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 #define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h index 5006b649832..1d9f021ff14 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h +++ b/src/mainboard/google/beltino/variants/zako/include/variant/thermal.h @@ -3,30 +3,28 @@ #ifndef THERMAL_H #define THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x4c +/* Fan is at default speed */ +#define FAN4_PWM 0x47 /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 52 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 #define FAN3_PWM 0x6d /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 50 -#define FAN2_THRESHOLD_ON 55 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 #define FAN2_PWM 0x7c /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 52 -#define FAN1_THRESHOLD_ON 58 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 #define FAN1_PWM 0xa3 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 55 -#define FAN0_THRESHOLD_ON 60 -#define FAN0_PWM 0xba +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 98 diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 49ac7d2ae11..4dc070f4aef 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -39,4 +39,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BUTTERFLY diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl index 3552e29ad85..bcf79334527 100644 --- a/src/mainboard/google/butterfly/acpi/mainboard.asl +++ b/src/mainboard/google/butterfly/acpi/mainboard.asl @@ -15,11 +15,9 @@ Scope (\_SB) { Device (TPAD) { - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_REV, 2) // Trackpad Wake is GPIO11, wake from S3 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) @@ -27,7 +25,7 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQG -> GSI22 - Interrupt (ResourceConsumer, EDGE, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) { BOARD_TRACKPAD_IRQ } diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index ac679c765fa..8a505a34380 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -115,4 +115,8 @@ config CONSOLE_SERIAL config ENABLE_BUILTIN_COM1 default y if CONSOLE_SERIAL +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl index e85e93775ca..414db27df0a 100644 --- a/src/mainboard/google/cyan/acpi/codec_maxim.asl +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -9,6 +9,7 @@ Scope (\_SB.PCI0.I2C2) Name (_CID, AUDIO_CODEC_CID) Name (_DDN, AUDIO_CODEC_DDN) Name (_UID, 1) + Name (_HRV, 0x02) /* Add DT style bindings with _DSD */ Name (_DSD, Package () { @@ -31,8 +32,16 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) + /* For Linux driver */ GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + + /* For coolstar's Windows driver */ + GpioIo (Exclusive, PullNone, 0x0000, 0x0000, IoRestrictionInputOnly, + "\\_SB.GPSE", 0x00, ResourceConsumer, ,) + { + BOARD_JACK_MAXIM_GPIO_INDEX + } } ) Return (SBUF) } @@ -74,7 +83,7 @@ Scope (\_SB.PCI0.I2C2) "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ ) - GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullDefault,, + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } } ) diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl index 3a5d04e6c9e..1394c8f88ec 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -36,8 +36,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl index e972056510d..15ffe6f6dd6 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -35,8 +35,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl index a944db6113d..56200848ac9 100644 --- a/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl +++ b/src/mainboard/google/cyan/acpi/touchscreen_synaptics.asl @@ -78,8 +78,6 @@ Scope (\_SB.PCI0.I2C1) } } - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl index 91678de8b8b..cf430dd2e56 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_atmel.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_atmel.asl @@ -8,7 +8,6 @@ Scope (\_SB.PCI0.I2C6) Name (_DDN, "Atmel Touchpad") Name (_UID, 2) Name (ISTP, 1) /* Touchpad */ - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) Name (_CRS, ResourceTemplate() { diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl index aa268b1b5d6..8aa3d1d0926 100644 --- a/src/mainboard/google/cyan/acpi/trackpad_elan.asl +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -31,8 +31,6 @@ Scope (\_SB.PCI0.I2C6) } } - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - /* Allow device to power off in S0 */ Name (_S0W, 4) } diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c968dfc0b76..f53a65e9cc7 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -99,7 +99,7 @@ chip soc/intel/braswell device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display device pci 03.0 off end # 8086 22b8 - Camera and Image Processor - device pci 0b.0 on end # 8086 22dc - Signal Processing Controller + device pci 0b.0 off end # 8086 22dc - Signal Processing Controller device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port device pci 12.0 on end # 8086 0F16 - SD Port @@ -124,7 +124,7 @@ chip soc/intel/braswell device pci 1e.0 on end # 8086 2286 - SIO - DMA device pci 1e.1 off end # 8086 0F08 - PWM 1 device pci 1e.2 off end # 8086 0F09 - PWM 2 - device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.3 off end # 8086 228a - HSUART 1 device pci 1e.4 off end # 8086 228c - HSUART 2 device pci 1e.5 on end # 8086 228e - SPI 1 device pci 1e.6 off end # 8086 2290 - SPI 2 diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 9083a8773b6..194810df394 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -98,6 +98,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index dca36a6e9be..cbc35bfb89a 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -19,6 +19,7 @@ config BOARD_GOOGLE_DRAWCIA select DRIVERS_GENERIC_MAX98357A select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR select DRIVERS_INTEL_MIPI_CAMERA + select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU help The Drawcia board supports the following devices: diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 7a403b536c4..49e1a10b890 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -165,9 +165,9 @@ static const struct pad_config gpio_table[] = { /* D4 : TOUCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_D4, NONE, PLTRST, LEVEL, INVERT), /* D5 : TOUCH_RESET_L */ - PAD_CFG_GPO(GPP_D5, 0, DEEP), + PAD_CFG_GPO(GPP_D5, 1, DEEP), /* D6 : EN_PP3300_TOUCH_S0 */ - PAD_CFG_GPO(GPP_D6, 0, DEEP), + PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D7 : EMR_INT_ODL */ PAD_NC(GPP_D7, NONE), /* D8 : GPP_D8/GSPI2_CS0B/UART0A_RXD */ @@ -434,6 +434,11 @@ static const struct pad_config early_gpio_table[] = { /* D1 : WLAN_PERST_L */ PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* D5 : TOUCH_RESET_L */ + PAD_CFG_GPO(GPP_D5, 0, DEEP), + /* D6 : EN_PP3300_TOUCH_S0 */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 0, DEEP), diff --git a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc index c517214e468..9e9af40e769 100644 --- a/src/mainboard/google/dedede/variants/drawcia/Makefile.inc +++ b/src/mainboard/google/dedede/variants/drawcia/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_FW_CONFIG) += variant.c smm-y += variant.c + +$(call add_vbt_to_cbfs, vbt_drawman.bin, drawman-data.vbt) diff --git a/src/mainboard/google/dedede/variants/drawcia/data.vbt b/src/mainboard/google/dedede/variants/drawcia/data.vbt new file mode 100644 index 00000000000..7a45a860ec1 Binary files /dev/null and b/src/mainboard/google/dedede/variants/drawcia/data.vbt differ diff --git a/src/mainboard/google/dedede/variants/drawcia/drawman-data.vbt b/src/mainboard/google/dedede/variants/drawcia/drawman-data.vbt new file mode 100644 index 00000000000..b29655cf6c8 Binary files /dev/null and b/src/mainboard/google/dedede/variants/drawcia/drawman-data.vbt differ diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 3ba85bd3b12..a72a1b8c8d8 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -165,7 +165,7 @@ chip soc/intel/jasperlake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_03" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end #I2C 0 @@ -175,7 +175,7 @@ chip soc/intel/jasperlake register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "probed" = "1" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" @@ -205,7 +205,7 @@ chip soc/intel/jasperlake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" @@ -219,7 +219,7 @@ chip soc/intel/jasperlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "2" diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 916a235de0e..0d31362ac09 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -89,4 +89,7 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + endif # BOARD_GOOGLE_BASEBOARD_DRALLION diff --git a/src/mainboard/google/drallion/default.fmd b/src/mainboard/google/drallion/default.fmd new file mode 100644 index 00000000000..4f2bedf9c24 --- /dev/null +++ b/src/mainboard/google/drallion/default.fmd @@ -0,0 +1,11 @@ +FLASH@0xfe000000 0x2000000 { + SI_BIOS@0x400000 { + MEMORY_MAPPED@0xc00000 { /* 16MiB total */ + RW_MRC_CACHE 0x10000 + SMMSTORE 0x40000 + RO_VPD 0x4000 + FMAP 0x300 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index fd1153c30ef..3bfe6f3dbab 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -336,7 +336,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" @@ -358,7 +358,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" @@ -378,8 +378,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "10" register "reset_off_delay_ms" = "5" @@ -397,15 +397,15 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "detect" = "1" device i2c 2c on end end chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "detect" = "1" device i2c 15 on end end end # I2C #1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 6220bf28b7b..2d0d8eb543f 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -65,7 +65,7 @@ static const struct pad_config gpio_table[] = { /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, @@ -132,7 +132,7 @@ static const struct pad_config gpio_table[] = { /* SATA_DEVSLP0 */ PAD_NC(GPP_E4, NONE), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */ /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */ -/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, PLTRST), /* TOUCH_SCREEN_PD# */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, PLTRST), /* TOUCH_SCREEN_PD# */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */ @@ -215,6 +215,9 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */ +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, PLTRST), /* TOUCH_SCREEN_PD# */ /* UART2_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ /* UART2_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* SDA_PCH_H1 */ diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h index 98615d91c7e..89c5175d9cf 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -176,6 +176,15 @@ const u32 cim_verb_data[] = { 0x02040000, 0x0205000F, 0x02040000, + + 0x8086280b, /* Codec Vendor/Device ID: Intel CometPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 0579c0dfe1d..68ed68d2aad 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -72,4 +72,9 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n + +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 1e9ffd9255e..02111921a34 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -232,6 +232,7 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on + subsystemid 0x1AE0 0x006B inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem diff --git a/src/mainboard/google/eve/ec.c b/src/mainboard/google/eve/ec.c index 499f56484bf..eb4e0978fb0 100644 --- a/src/mainboard/google/eve/ec.c +++ b/src/mainboard/google/eve/ec.c @@ -15,4 +15,10 @@ void mainboard_ec_init(void) }; google_chromeec_events_init(&info, acpi_is_wakeup_s3()); + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + /* Turn off keyboard backlight after turning on in romstage */ + if (!acpi_is_wakeup_s3()) + google_chromeec_kbbacklight(0); +#endif } diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index f3c0f1140b4..9aa4d453409 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -2,10 +2,12 @@ #include #include +#include #include #include #include #include "spd/spd.h" +#include "ec.h" void mainboard_memory_init_params(FSPM_UPD *mupd) { @@ -41,4 +43,11 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) printk(BIOS_WARNING, "Limiting memory to 1600MHz\n"); mem_cfg->DdrFreqLimit = 1600; } + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + /* Turn on keyboard backlight to indicate we are booting */ + const FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; + if (arch_upd->BootMode != FSP_BOOT_ON_S3_RESUME) + google_chromeec_kbbacklight(50); +#endif } diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 8b7811c1a6d..9930cfe3085 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -98,10 +98,14 @@ config UART_FOR_CONSOLE default 2 config USE_PM_ACPI_TIMER - default n + default y config EDK2_BOOT_TIMEOUT int default 5 +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 13bc9b70cae..e01c9fa8aef 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -20,6 +20,8 @@ #include +#define SUBSYSTEM_ID 0x1AE0006C + #define FIZZ_SKU_ID_I7_U42 0x4 #define FIZZ_SKU_ID_I5_U42 0x5 #define FIZZ_SKU_ID_I3_U42 0x6 @@ -137,6 +139,13 @@ static void mainboard_set_power_limits(struct soc_power_limits_config *conf) conf->tdp_pl4 = SET_PSYSPL2(psyspl2); } + + /* Override PL1/PL2 for i7 KBL-R SKU */ + if (sku & FIZZ_SKU_ID_I7_U42) { + conf->tdp_pl1_override = 20; + pl2 = 40; + } + conf->tdp_pl2_override = pl2; /* set psyspl2 to 90% of max adapter power */ conf->tdp_psyspl2 = SET_PSYSPL2(psyspl2); @@ -180,6 +189,24 @@ const char *smbios_system_sku(void) return sku_str; } +const char *smbios_mainboard_product_name(void) +{ + static char product[12]; + + switch (board_oem_id()) + { + case 0: snprintf(product, sizeof(product), "Kench"); break; + case 1: snprintf(product, sizeof(product), "Teemo"); break; + case 2: snprintf(product, sizeof(product), "Sion"); break; + case 3: + case 4: + case 5: snprintf(product, sizeof(product), "Wukong"); break; + case 6: snprintf(product, sizeof(product), "Teemo"); break; + default: snprintf(product, sizeof(product), "UNK Fizz"); break; + } + return product; +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -201,6 +228,8 @@ static unsigned long mainboard_write_acpi_tables( if (!nhlt) return start_addr; + nhlt->subsystem_id = SUBSYSTEM_ID; + variant_nhlt_init(nhlt); variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision); diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 5ecc77bc779..5285d4ed23a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -309,6 +309,7 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on + subsystemid 0x1AE0 0x006C inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index ff6b1ea8624..3667f371f1c 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -126,4 +126,8 @@ config CONSOLE_SERIAL config USE_PM_ACPI_TIMER default n +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 2d8ee15766e..ca41f01243a 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -1,4 +1,4 @@ -config BOARD_GOOGLE_HATCH_COMMON +config BOARD_GOOGLE_BASEBOARD_HATCH def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS @@ -17,6 +17,7 @@ config BOARD_GOOGLE_HATCH_COMMON select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 @@ -24,57 +25,17 @@ config BOARD_GOOGLE_HATCH_COMMON select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_DTT select SPI_TPM - select TPM_GOOGLE_CR50 - -config BOARD_GOOGLE_BASEBOARD_HATCH - def_bool n - select BOARD_GOOGLE_HATCH_COMMON select SYSTEM_TYPE_LAPTOP - -config BOARD_GOOGLE_BASEBOARD_PUFF - def_bool n - select BOARD_GOOGLE_HATCH_COMMON - select DRIVERS_INTEL_DPTF - select ROMSTAGE_SPD_SMBUS - select RT8168_GEN_ACPI_POWER_RESOURCE - select RT8168_GET_MAC_FROM_VPD - select RT8168_SET_LED_MODE - select SOC_INTEL_CSE_LITE_SKU - select SPD_READ_BY_WORD - select FW_CONFIG - select FW_CONFIG_SOURCE_CHROMEEC_CBI + select TPM_GOOGLE_CR50 config BOARD_GOOGLE_AKEMI select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_AMBASSADOR - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_DOOLY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_DRATINI select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_DUFFY_LEGACY - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_DUFFY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_FAFFY - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_GENESIS - select BOARD_GOOGLE_BASEBOARD_PUFF - config BOARD_GOOGLE_HATCH select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_32768 @@ -97,15 +58,6 @@ config BOARD_GOOGLE_JINLON select DRIVERS_GFX_GENERIC select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_KAISA_LEGACY - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_KAISA - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_KINDRED select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT @@ -115,12 +67,8 @@ config BOARD_GOOGLE_KOHAKU select BOARD_GOOGLE_BASEBOARD_HATCH select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_MOONBUGGY - select BOARD_GOOGLE_BASEBOARD_PUFF - config BOARD_GOOGLE_MUSHU select BOARD_GOOGLE_BASEBOARD_HATCH - select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_NIGHTFURY select BOARD_GOOGLE_BASEBOARD_HATCH @@ -128,34 +76,18 @@ config BOARD_GOOGLE_NIGHTFURY select DRIVERS_I2C_MAX98390 select INTEL_GMA_HAVE_VBT -config BOARD_GOOGLE_NOIBAT - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - config BOARD_GOOGLE_PALKIA select BOARD_GOOGLE_BASEBOARD_HATCH select CHROMEOS_DSM_CALIB if CHROMEOS select DRIVERS_I2C_RT1011 -config BOARD_GOOGLE_PUFF - select BOARD_GOOGLE_BASEBOARD_PUFF - select BOARD_ROMSIZE_KB_32768 - select INTEL_GMA_HAVE_VBT - -config BOARD_GOOGLE_SCOUT - select BOARD_GOOGLE_BASEBOARD_PUFF - -config BOARD_GOOGLE_WYVERN - select BOARD_GOOGLE_BASEBOARD_PUFF - select INTEL_GMA_HAVE_VBT - -if BOARD_GOOGLE_HATCH_COMMON +if BOARD_GOOGLE_BASEBOARD_HATCH config DISABLE_HECI1_AT_PRE_BOOT - default y if BOARD_GOOGLE_BASEBOARD_HATCH + default y config CHROMEOS - select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if !ROMSTAGE_SPD_SMBUS + select CHROMEOS_DRAM_PART_NUMBER_IN_CBI select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_DEV_BOOT_USB @@ -163,7 +95,6 @@ config CHROMEOS select GBB_FLAG_FORCE_MANUAL_RECOVERY select HAS_RECOVERY_MRC_CACHE select VBOOT_LID_SWITCH - select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU config CHROMEOS_WIFI_SAR bool "Enable SAR options for ChromeOS build" @@ -179,37 +110,15 @@ config DEVICETREE config DIMM_MAX default 2 -config ROMSTAGE_SPD_CBFS - bool - default y if !ROMSTAGE_SPD_SMBUS - select HAVE_SPD_IN_CBFS - -config ROMSTAGE_SPD_SMBUS - bool - default n - select SPD_CACHE_IN_FMAP - config DRIVER_TPM_SPI_BUS default 0x1 config UART_FOR_CONSOLE default 0 -if BOARD_GOOGLE_BASEBOARD_HATCH -config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-hatch-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS -endif - -if BOARD_GOOGLE_BASEBOARD_PUFF config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-puff-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-puff-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS - -config POWER_OFF_ON_CR50_UPDATE - bool - default n -endif + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS config MAINBOARD_DIR default "google/hatch" @@ -221,28 +130,15 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Akemi" if BOARD_GOOGLE_AKEMI default "Dratini" if BOARD_GOOGLE_DRATINI - default "Duffy" if BOARD_GOOGLE_DUFFY - default "Duffy" if BOARD_GOOGLE_DUFFY_LEGACY - default "Faffy" if BOARD_GOOGLE_FAFFY default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP default "Jinlon" if BOARD_GOOGLE_JINLON - default "Kaisa" if BOARD_GOOGLE_KAISA - default "Kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU - default "Noibat" if BOARD_GOOGLE_NOIBAT - default "Palkia" if BOARD_GOOGLE_PALKIA default "Nightfury" if BOARD_GOOGLE_NIGHTFURY - default "Puff" if BOARD_GOOGLE_PUFF - default "Wyvern" if BOARD_GOOGLE_WYVERN - default "Dooly" if BOARD_GOOGLE_DOOLY - default "Ambassador" if BOARD_GOOGLE_AMBASSADOR - default "Genesis" if BOARD_GOOGLE_GENESIS - default "Scout" if BOARD_GOOGLE_SCOUT - default "Moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "Palkia" if BOARD_GOOGLE_PALKIA config OVERRIDE_DEVICETREE default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP @@ -255,28 +151,15 @@ config TPM_TIS_ACPI_INTERRUPT config VARIANT_DIR default "akemi" if BOARD_GOOGLE_AKEMI default "dratini" if BOARD_GOOGLE_DRATINI - default "duffy" if BOARD_GOOGLE_DUFFY - default "duffy" if BOARD_GOOGLE_DUFFY_LEGACY - default "faffy" if BOARD_GOOGLE_FAFFY default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP default "jinlon" if BOARD_GOOGLE_JINLON - default "kaisa" if BOARD_GOOGLE_KAISA - default "kaisa" if BOARD_GOOGLE_KAISA_LEGACY default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU - default "noibat" if BOARD_GOOGLE_NOIBAT - default "palkia" if BOARD_GOOGLE_PALKIA default "nightfury" if BOARD_GOOGLE_NIGHTFURY - default "puff" if BOARD_GOOGLE_PUFF - default "wyvern" if BOARD_GOOGLE_WYVERN - default "dooly" if BOARD_GOOGLE_DOOLY - default "ambassador" if BOARD_GOOGLE_AMBASSADOR - default "genesis" if BOARD_GOOGLE_GENESIS - default "scout" if BOARD_GOOGLE_SCOUT - default "moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "palkia" if BOARD_GOOGLE_PALKIA config VBOOT select HAS_RECOVERY_MRC_CACHE @@ -289,4 +172,8 @@ config EDK2_BOOT_TIMEOUT int default 5 if BOARD_GOOGLE_BASEBOARD_PUFF -endif # BOARD_GOOGLE_HATCH_COMMON +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + +endif # BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 1307314e9ad..0564476468d 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -3,27 +3,9 @@ comment "Hatch" config BOARD_GOOGLE_AKEMI bool "-> Akemi (IdeaPad Flex 5/5i Chromebook)" -config BOARD_GOOGLE_AMBASSADOR - bool "-> Ambassador" - -config BOARD_GOOGLE_DOOLY - bool "-> Dooly" - config BOARD_GOOGLE_DRATINI bool "-> Dratini (HP Pro c640 Chromebook)" -config BOARD_GOOGLE_DUFFY_LEGACY - bool "-> Duffy Legacy (32MB)" - -config BOARD_GOOGLE_DUFFY - bool "-> Duffy (ASUS Chromebox 4)" - -config BOARD_GOOGLE_FAFFY - bool "-> Faffy (ASUS Fanless Chromebox)" - -config BOARD_GOOGLE_GENESIS - bool "-> Genesis" - config BOARD_GOOGLE_HATCH bool "-> Hatch" @@ -36,38 +18,17 @@ config BOARD_GOOGLE_HELIOS_DISKSWAP config BOARD_GOOGLE_JINLON bool "-> Jinlon (HP Elite c1030 Chromebook)" -config BOARD_GOOGLE_KAISA_LEGACY - bool "-> Kaisa Legacy (32MB)" - -config BOARD_GOOGLE_KAISA - bool "-> Kaisa (Acer Chromebox CXI4)" - config BOARD_GOOGLE_KINDRED bool "-> Kindred (Acer Chromebook 712)" config BOARD_GOOGLE_KOHAKU bool "-> Kohaku (Samsung Galaxy Chromebook)" -config BOARD_GOOGLE_MOONBUGGY - bool "-> Moonbuggy" - config BOARD_GOOGLE_MUSHU bool "-> Mushu" config BOARD_GOOGLE_NIGHTFURY bool "-> Nightfury (Samsung Galaxy Chromebook 2)" -config BOARD_GOOGLE_NOIBAT - bool "-> Noibat (HP Chromebox G3)" - config BOARD_GOOGLE_PALKIA bool "-> Palkia" - -config BOARD_GOOGLE_PUFF - bool "-> Puff" - -config BOARD_GOOGLE_SCOUT - bool "-> Scout" - -config BOARD_GOOGLE_WYVERN - bool "-> Wyvern (CTL Chromebox CBx2)" diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc index debe94295f3..b4c3a1bd62e 100644 --- a/src/mainboard/google/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/Makefile.inc @@ -7,8 +7,7 @@ ramstage-y += ramstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c -romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c -romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += romstage_spd_smbus.c +romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c @@ -20,4 +19,4 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include -subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd +subdirs-y += spd diff --git a/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd rename to src/mainboard/google/hatch/chromeos-16MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd b/src/mainboard/google/hatch/chromeos-32MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-hatch-32MiB.fmd rename to src/mainboard/google/hatch/chromeos-32MiB.fmd diff --git a/src/mainboard/google/hatch/romstage_spd_cbfs.c b/src/mainboard/google/hatch/romstage.c similarity index 100% rename from src/mainboard/google/hatch/romstage_spd_cbfs.c rename to src/mainboard/google/hatch/romstage.c diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index fb1e99c7f4d..7608ad9b907 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -165,6 +165,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/akemi/overridetree.cb b/src/mainboard/google/hatch/variants/akemi/overridetree.cb index 97a6eaf8834..5cb4d35d998 100644 --- a/src/mainboard/google/hatch/variants/akemi/overridetree.cb +++ b/src/mainboard/google/hatch/variants/akemi/overridetree.cb @@ -167,9 +167,9 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -177,7 +177,7 @@ chip soc/intel/cannonlake register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -186,8 +186,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" @@ -200,7 +200,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "150" diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index eab831aabf7..f3dc3f7ced4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -166,7 +166,7 @@ static const struct pad_config gpio_table[] = { /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* D10 : GPP_D10 ==> NC */ PAD_NC(GPP_D10, NONE), /* D11 : GPP_D11 ==> NC */ @@ -178,7 +178,7 @@ static const struct pad_config gpio_table[] = { /* D14 : ISH_UART_TX */ PAD_NC(GPP_D14, NONE), /* D15 : TOUCHSCREEN_RST_L */ - PAD_CFG_GPO(GPP_D15, 0, DEEP), + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* D16 : USI_INT */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE), /* D17 : PCH_HP_SDW_CLK */ diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index c78ad5b154b..77dbdefb89c 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -36,119 +35,6 @@ static void wait_for_hpd(gpio_t gpio, long timeout) stopwatch_duration_msecs(&sw)); } -/* - * For type-C chargers, set PL2 to 97% of max power to account for - * cable loss and FET Rdson loss in the path from the source. - */ -#define SET_PSYSPL2(w) (97 * (w) / 100) -#define PUFF_U22_PL2 (35) -#define PUFF_U62_U42_PL2 (51) -#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) -#define PUFF_CORE_CPU_PSYSPL2 (90) -#define PUFF_MAX_TIME_WINDOW 6 -#define PUFF_MIN_DUTYCYCLE 4 - -/* - * mainboard_set_power_limits - * - * Set Pl2 and SysPl2 values based on detected charger. - * Values are defined below but we use U22 value for all SKUs for now. - * definitions: - * x = no value entered. Use default value in parenthesis. - * will set 0 to anything that shouldn't be set. - * n = max value of power adapter. - * +-------------+-----+---------+-----------+-------+ - * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+---------+-----------+-------+ - * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | - * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | - * +-------------+-----+---------+-----------+-------+ - * For USB C charger: - * +-------------+-----------------+---------+---------+-------+ - * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | - * +-------------+-----+-----------+---------+---------+-------+ - * | n | min(0.97n, PL2) | 0.97n | 0.97n | 0.97n | - * +-------------+-----+-----------+---------+---------+-------+ - */ - -/* - * Psys_pmax considerations - * - * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. - * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A - * instead of real system power. The equation is shown below: - * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) - * Hence, Iinput (Amps) = 9.6A - * Since there is no voltage information from PSYS, different voltage input - * would map to different Psys_pmax settings: - * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W - * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W - * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W - */ -#define PSYS_IMAX 9600 -#define BJ_VOLTS_MV 19000 - -static void mainboard_set_power_limits(struct soc_power_limits_config *conf) -{ - enum usb_chg_type type; - u32 watts; - u16 volts_mv, current_ma; - u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value - u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 - int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); - - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); - u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - dev = pcidev_path_on_root(SA_DEVFN_IGD); - u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; - - /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ - conf->tdp_psyspl3 = 0; - conf->tdp_pl4 = 0; - - if (rv == 0 && type == USB_CHG_TYPE_PD) { - /* Detected USB-PD. Base on max value of adapter */ - watts = ((u32)current_ma * volts_mv) / 1000000; - /* set psyspl2 to 90% of adapter rating */ - psyspl2 = SET_PSYSPL2(watts); - - /* Limit PL2 if the adapter is with lower capability */ - if (mch_id == PCI_DID_INTEL_CML_ULT || - mch_id == PCI_DID_INTEL_CML_ULT_6_2) - pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; - else - pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; - - conf->tdp_psyspl3 = psyspl2; - /* set max possible time window */ - conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; - /* set minimum duty cycle */ - conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; - /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ - conf->tdp_pl4 = psyspl2; - } else { - /* - * Input type is barrel jack, from the SKU matrix: - * 1. i3/i5/i7 SKUs use 90W BJ - * 2. Celeron and Pentium use 65W BJ (default) - */ - volts_mv = BJ_VOLTS_MV; - /* Use IGD ID to check if CPU is Core SKUs */ - if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 && - igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) { - psyspl2 = PUFF_CORE_CPU_PSYSPL2; - if (mch_id == PCI_DID_INTEL_CML_ULT || - mch_id == PCI_DID_INTEL_CML_ULT_6_2) - pl2 = PUFF_U62_U42_PL2; - } - } - /* voltage unit is milliVolts and current is in milliAmps */ - conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); - - conf->tdp_pl2_override = pl2; - conf->tdp_psyspl2 = psyspl2; -} - void variant_ramstage_init(void) { static const long display_timeout_ms = 3000; @@ -165,7 +51,4 @@ void variant_ramstage_init(void) if (google_chromeec_wait_for_displayport(display_timeout_ms)) wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); } - /* Psys_pmax needs to be setup before FSP-S */ - soc_config = &conf->power_limits_config; - mainboard_set_power_limits(soc_config); } diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c index 02555a03690..6949b726fcf 100644 --- a/src/mainboard/google/hatch/variants/dratini/gpio.c +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -90,6 +90,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index 6176fc6252c..a2fd9b76672 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -76,9 +76,9 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # I2C #0 @@ -87,7 +87,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" @@ -100,8 +100,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" @@ -115,7 +115,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" @@ -131,7 +131,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 80279b45134..9f7cd3e2846 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -63,6 +63,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index bf21bf1762d..f0026934694 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -75,7 +75,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -84,8 +84,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" @@ -98,7 +98,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index c93562059aa..e93110576e4 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -93,7 +93,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -104,8 +104,8 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = - "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb index 129bb269f56..eb3af70157d 100644 --- a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb @@ -109,7 +109,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -120,8 +120,8 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = - "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "500" diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 1020dd6ecfd..83b93c2037a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -94,6 +94,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index 88c9a54c7ee..0d1cccd5d13 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -98,9 +98,9 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # I2C #0 @@ -109,7 +109,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" @@ -122,8 +122,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" @@ -137,7 +137,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" @@ -153,7 +153,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN2513"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" diff --git a/src/mainboard/google/hatch/variants/kindred/gpio.c b/src/mainboard/google/hatch/variants/kindred/gpio.c index 26740b9e9c3..f2ad219cd26 100644 --- a/src/mainboard/google/hatch/variants/kindred/gpio.c +++ b/src/mainboard/google/hatch/variants/kindred/gpio.c @@ -223,6 +223,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index f27423f537c..381c06d1939 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -112,9 +112,9 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -122,7 +122,7 @@ chip soc/intel/cannonlake register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "generic.wake" = "GPE0_DW0_21" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -131,8 +131,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" register "reset_off_delay_ms" = "5" @@ -145,8 +145,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "1" register "reset_off_delay_ms" = "2" @@ -160,7 +160,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN9004"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" register "generic.reset_off_delay_ms" = "2" diff --git a/src/mainboard/google/hatch/variants/kohaku/gpio.c b/src/mainboard/google/hatch/variants/kohaku/gpio.c index aa869324263..3bed2aff6ac 100644 --- a/src/mainboard/google/hatch/variants/kohaku/gpio.c +++ b/src/mainboard/google/hatch/variants/kohaku/gpio.c @@ -31,13 +31,15 @@ static const struct pad_config gpio_table[] = { /* C7 : PEN_IRQ_OD_L */ PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), /* C12 : EN_PP3300_TSP_DX */ - PAD_CFG_GPO(GPP_C12, 0, DEEP), + PAD_CFG_GPO(GPP_C12, 1, DEEP), /* C13 : EC_PCH_INT_L - needs to wake the system */ PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C15 : EN_PP3300_DIG_DX */ PAD_CFG_GPO(GPP_C15, 0, DEEP), /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), + /* D15 : EN_PP3300_TSP_RST */ + PAD_CFG_GPO(GPP_C12, 1, DEEP), /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* E23 : GPP_E23 ==> NC */ @@ -100,6 +102,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* C9 : UART_PCH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C12 : EN_PP3300_TSP_DX */ + PAD_CFG_GPO(GPP_C12, 1, DEEP), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 266346b3b56..67fd583a77d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -155,10 +155,11 @@ chip soc/intel/cannonlake device pci 15.0 on chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.wake" = "GPE0_DW0_21" register "hid_desc_reg_offset" = "0x20" device i2c 0x20 on end @@ -177,15 +178,15 @@ chip soc/intel/cannonlake register "enable_delay_ms" = "1" # 90 ns register "has_power_resource" = "1" register "disable_gpio_export_in_crs" = "1" - register "probed" = "1" + register "detect" = "1" device i2c 4b on end end chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "detect" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" register "enable_delay_ms" = "10" register "enable_off_delay_ms" = "100" diff --git a/src/mainboard/google/hatch/variants/nightfury/gpio.c b/src/mainboard/google/hatch/variants/nightfury/gpio.c index a813dfa5772..170ecf53045 100644 --- a/src/mainboard/google/hatch/variants/nightfury/gpio.c +++ b/src/mainboard/google/hatch/variants/nightfury/gpio.c @@ -28,13 +28,15 @@ static const struct pad_config gpio_table[] = { /* C1 : NC */ PAD_NC(GPP_C1, NONE), - /* C12 : EN_PP3300_TSP_DX */ - PAD_CFG_GPO(GPP_C12, 0, DEEP), + /* C12 : EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C12, 1, DEEP), /* C13 : EC_PCH_INT_L - needs to wake the system */ PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT), /* C23 : UART2_CTS# ==> NC */ PAD_NC(GPP_C23, NONE), + /* D15 : TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* D16 : TOUCHSCREEN_INT_L */ PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* D19 : DMIC_CLK_0_SNDW4_CLK */ @@ -114,6 +116,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* C9 : UART_PCH_TX_DEBUG_RX */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C12 : EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C12, 1, DEEP), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), /* PCH_WP_OD */ diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 8805a324af3..c2b672a7789 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -197,8 +197,8 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" + register "detect" = "1" register "wake" = "GPE0_DW0_21" device i2c 0x15 on end end @@ -209,7 +209,7 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN902C"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "20" diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c index c6e43689735..c779bbf0a30 100644 --- a/src/mainboard/google/hatch/variants/palkia/gpio.c +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -129,6 +129,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 1, DEEP), /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP1 */ diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb index b7f6ff2ca5c..0bfa06f2f13 100644 --- a/src/mainboard/google/hatch/variants/palkia/overridetree.cb +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -104,7 +104,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -115,8 +115,8 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN9008"" register "generic.desc" = ""ELAN Touchscreen USI"" register "generic.irq" = - "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" + "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.enable_delay_ms" = "12" @@ -136,8 +136,8 @@ chip soc/intel/cannonlake register "generic.hid" = ""ELAN9009"" register "generic.desc" = ""ELAN Touchscreen USI"" register "generic.irq" = - "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" + "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D10)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 4cbad81d097..44414445f3c 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -61,4 +61,8 @@ config EDK2_BOOT_TIMEOUT int default 5 +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 1adc5d5438c..1b0e5108bee 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -47,6 +47,7 @@ void mainboard_smi_sleep(u8 slp_typ) set_gpio(GPIO_USB_CTL_1, 0); } break; + case ACPI_S4: case ACPI_S5: set_power_led(LED_OFF); break; diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h index 7dc48369824..7a988946637 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/guado/include/variant/thermal.h @@ -11,22 +11,22 @@ /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 40 #define FAN3_THRESHOLD_ON 50 -#define FAN3_PWM 0x55 +#define FAN3_PWM 0x62 /* Fan is at MEDIUM speed */ #define FAN2_THRESHOLD_OFF 55 #define FAN2_THRESHOLD_ON 67 -#define FAN2_PWM 0xa6 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 65 -#define FAN1_THRESHOLD_ON 70 -#define FAN1_PWM 0xc0 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 90 -#define FAN0_THRESHOLD_ON 100 -#define FAN0_PWM 0xff +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 104 diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h index 58ca2f6d98d..bc46ae39b30 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/thermal.h @@ -9,24 +9,24 @@ #define FAN4_PWM 0x4d /* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 42 -#define FAN3_THRESHOLD_ON 47 -#define FAN3_PWM 0xa5 +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x62 /* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 54 -#define FAN2_THRESHOLD_ON 59 -#define FAN2_PWM 0xb2 +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0x86 /* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 66 -#define FAN1_THRESHOLD_ON 71 -#define FAN1_PWM 0xc9 +#define FAN1_THRESHOLD_OFF 67 +#define FAN1_THRESHOLD_ON 75 +#define FAN1_PWM 0xa8 /* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 78 -#define FAN0_THRESHOLD_ON 83 -#define FAN0_PWM 0xd8 +#define FAN0_THRESHOLD_OFF 85 +#define FAN0_THRESHOLD_ON 90 +#define FAN0_PWM 0xdc /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index 10524fe5e9f..e0c416eebac 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -146,4 +146,8 @@ endif config USE_PSPSECUREOS def_bool n +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index e6e4b0bff12..93f1672a9ea 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -35,4 +35,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_LINK diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 2f42b7da181..3ed68b6e2e8 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -54,6 +54,7 @@ void mainboard_smi_sleep(u8 slp_typ) google_chromeec_set_usb_charge_mode( 1, USB_CHARGE_MODE_DISABLED); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 88e37badf62..6e09e6eb573 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -191,4 +191,8 @@ config DRAM_PART_IN_CBI_BOARD_ID_MIN config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index 4a65b2ce2f1..0f72809a301 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -131,7 +131,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ @@ -191,14 +191,14 @@ static const struct pad_config gpio_table[] = { DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ // Also we may be able to use eSPI WAKE# Virtual Wire instead PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_NC(GPIO_142, UP_20K),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL(unused) */ PAD_NC(GPIO_143, UP_20K), /* GPIO_143 - NC */ PAD_NC(GPIO_144, UP_20K), /* GPIO_144 - PEN_EJECT */ PAD_NC(GPIO_145, UP_20K), /* GPIO_145 - PEN_EJECT */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ /* * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for @@ -293,6 +293,8 @@ static const struct pad_config early_gpio_table[] = { /* GSPI0_MOSI */ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ + /* Enable power to wifi early in bootblock and de-assert PERST#. */ PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN_L */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ diff --git a/src/mainboard/google/octopus/variants/ampton/overridetree.cb b/src/mainboard/google/octopus/variants/ampton/overridetree.cb index cfc5e8ac788..19a3ca44231 100644 --- a/src/mainboard/google/octopus/variants/ampton/overridetree.cb +++ b/src/mainboard/google/octopus/variants/ampton/overridetree.cb @@ -79,6 +79,7 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end @@ -89,7 +90,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -104,7 +105,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 6 @@ -112,8 +113,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -125,7 +126,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "70" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index abf53b47c53..ea2164a9e6e 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -115,7 +115,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Gaussian Mixture Model (GMM) + device pci 03.0 off end # - Gaussian Mixture Model (GMM) device pci 0c.0 on chip drivers/wifi/generic register "wake" = "GPE0A_CNVI_PME_STS" @@ -238,7 +238,7 @@ chip soc/intel/apollolake end end end # - XHCI - device pci 15.1 on end # - XDCI + device pci 15.1 off end # - XDCI device pci 16.0 on end # - I2C 0 device pci 16.1 off end # - I2C 1 device pci 16.2 off end # - I2C 2 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 76f74a560ba..e32804171f1 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -346,6 +346,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */ + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt b/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt index 1d93571b5fc..446210021de 100644 Binary files a/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt and b/src/mainboard/google/octopus/variants/bloog/blooguard-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/bloog/data.vbt b/src/mainboard/google/octopus/variants/bloog/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/bloog/data.vbt and b/src/mainboard/google/octopus/variants/bloog/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/bloog/gpio.c b/src/mainboard/google/octopus/variants/bloog/gpio.c index cea0451849d..5e728777f97 100644 --- a/src/mainboard/google/octopus/variants/bloog/gpio.c +++ b/src/mainboard/google/octopus/variants/bloog/gpio.c @@ -30,8 +30,10 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; diff --git a/src/mainboard/google/octopus/variants/bloog/overridetree.cb b/src/mainboard/google/octopus/variants/bloog/overridetree.cb index b585c853e34..9ca2d26a322 100644 --- a/src/mainboard/google/octopus/variants/bloog/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bloog/overridetree.cb @@ -105,7 +105,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -120,7 +120,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 6 @@ -128,8 +128,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -141,7 +141,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "3" @@ -155,7 +155,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/bobba/data.vbt b/src/mainboard/google/octopus/variants/bobba/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/bobba/data.vbt and b/src/mainboard/google/octopus/variants/bobba/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/bobba/gpio.c b/src/mainboard/google/octopus/variants/bobba/gpio.c index f5ba83a9335..4a9cf2f43d6 100644 --- a/src/mainboard/google/octopus/variants/bobba/gpio.c +++ b/src/mainboard/google/octopus/variants/bobba/gpio.c @@ -20,9 +20,10 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), }; @@ -35,9 +36,10 @@ static const struct pad_config lte_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), @@ -79,6 +81,10 @@ static const struct pad_config lte_early_override_table[] = { /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ PAD_CFG_GPO(GPIO_161, 0, DEEP), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), }; const struct pad_config *variant_early_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index c43153ac331..314aa937633 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -100,6 +100,7 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end @@ -155,7 +156,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -170,15 +171,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -187,8 +189,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -199,8 +201,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -212,7 +214,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "70" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/casta/data.vbt b/src/mainboard/google/octopus/variants/casta/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/casta/data.vbt and b/src/mainboard/google/octopus/variants/casta/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index a09bcbb9e1e..3dc2f092ab5 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -134,7 +134,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -142,7 +142,7 @@ chip soc/intel/apollolake register "generic.desc" = ""Zinitix Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0xE" device i2c 40 on end end diff --git a/src/mainboard/google/octopus/variants/dood/gpio.c b/src/mainboard/google/octopus/variants/dood/gpio.c index 639e9ca54d7..911a6e07837 100644 --- a/src/mainboard/google/octopus/variants/dood/gpio.c +++ b/src/mainboard/google/octopus/variants/dood/gpio.c @@ -16,8 +16,10 @@ enum { static const struct pad_config default_override_table[] = { PAD_NC(GPIO_104, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), @@ -27,8 +29,10 @@ static const struct pad_config lte_override_table[] = { /* Default override table. */ PAD_NC(GPIO_104, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), @@ -69,6 +73,10 @@ static const struct pad_config lte_early_override_table[] = { /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ PAD_CFG_GPO(GPIO_161, 0, DEEP), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), }; const struct pad_config *variant_early_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/dood/overridetree.cb b/src/mainboard/google/octopus/variants/dood/overridetree.cb index 465078f8c32..b331a5cf508 100644 --- a/src/mainboard/google/octopus/variants/dood/overridetree.cb +++ b/src/mainboard/google/octopus/variants/dood/overridetree.cb @@ -106,15 +106,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -123,8 +124,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -135,8 +136,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -148,7 +149,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/fleex/data.vbt b/src/mainboard/google/octopus/variants/fleex/data.vbt index 2848abe0335..0fabf7f1315 100644 Binary files a/src/mainboard/google/octopus/variants/fleex/data.vbt and b/src/mainboard/google/octopus/variants/fleex/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/fleex/gpio.c b/src/mainboard/google/octopus/variants/fleex/gpio.c index 732fe6861c5..d9088ccbe72 100644 --- a/src/mainboard/google/octopus/variants/fleex/gpio.c +++ b/src/mainboard/google/octopus/variants/fleex/gpio.c @@ -22,8 +22,10 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPO(GPIO_144, 1, PWROK), PAD_NC(GPIO_145, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ PAD_CFG_GPO(GPIO_161, 1, DEEP), @@ -48,6 +50,9 @@ static const struct pad_config lte_early_override_table[] = { /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ PAD_CFG_GPO(GPIO_161, 0, DEEP), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; const struct pad_config *variant_early_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/fleex/overridetree.cb b/src/mainboard/google/octopus/variants/fleex/overridetree.cb index 50077190023..41e87ea6dbd 100644 --- a/src/mainboard/google/octopus/variants/fleex/overridetree.cb +++ b/src/mainboard/google/octopus/variants/fleex/overridetree.cb @@ -98,7 +98,7 @@ chip soc/intel/apollolake "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end @@ -127,7 +127,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -158,7 +158,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -166,7 +166,7 @@ chip soc/intel/apollolake register "generic.desc" = ""Goodix Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end @@ -175,8 +175,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -188,7 +188,7 @@ chip soc/intel/apollolake register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -202,7 +202,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/foob/gpio.c b/src/mainboard/google/octopus/variants/foob/gpio.c index 1cc044e45ee..5918162c368 100644 --- a/src/mainboard/google/octopus/variants/foob/gpio.c +++ b/src/mainboard/google/octopus/variants/foob/gpio.c @@ -13,9 +13,10 @@ static const struct pad_config default_override_table[] = { PAD_NC(GPIO_117, UP_20K), PAD_NC(GPIO_143, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_161, DN_20K), diff --git a/src/mainboard/google/octopus/variants/foob/overridetree.cb b/src/mainboard/google/octopus/variants/foob/overridetree.cb index 4161090aa63..a868f427a6b 100644 --- a/src/mainboard/google/octopus/variants/foob/overridetree.cb +++ b/src/mainboard/google/octopus/variants/foob/overridetree.cb @@ -120,15 +120,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -138,7 +139,7 @@ chip soc/intel/apollolake register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "generic.reset_delay_ms" = "20" @@ -151,7 +152,7 @@ chip soc/intel/apollolake register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "generic.reset_delay_ms" = "45" diff --git a/src/mainboard/google/octopus/variants/garg/data.vbt b/src/mainboard/google/octopus/variants/garg/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/garg/data.vbt and b/src/mainboard/google/octopus/variants/garg/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/garg/garfour-data.vbt b/src/mainboard/google/octopus/variants/garg/garfour-data.vbt index 1d93571b5fc..446210021de 100644 Binary files a/src/mainboard/google/octopus/variants/garg/garfour-data.vbt and b/src/mainboard/google/octopus/variants/garg/garfour-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt b/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt index abf1d8848e2..9b969a96314 100644 Binary files a/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt and b/src/mainboard/google/octopus/variants/garg/garfour-hdmi-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt b/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt index 2073536009b..f04d2f4ba25 100644 Binary files a/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt and b/src/mainboard/google/octopus/variants/garg/garg-hdmi-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index dad442bc45d..7ca59a009cc 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -14,9 +14,10 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), }; @@ -35,9 +36,10 @@ static const struct pad_config hdmi_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), @@ -51,9 +53,10 @@ static const struct pad_config lte_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), PAD_NC(GPIO_213, DN_20K), @@ -100,6 +103,9 @@ static const struct pad_config lte_early_override_table[] = { /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ PAD_CFG_GPO(GPIO_161, 0, DEEP), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; const struct pad_config *variant_early_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/garg/overridetree.cb b/src/mainboard/google/octopus/variants/garg/overridetree.cb index c2a6997479b..f8c6685083e 100644 --- a/src/mainboard/google/octopus/variants/garg/overridetree.cb +++ b/src/mainboard/google/octopus/variants/garg/overridetree.cb @@ -133,7 +133,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -148,15 +148,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -165,8 +166,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -177,8 +178,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -190,7 +191,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/lick/data.vbt b/src/mainboard/google/octopus/variants/lick/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/lick/data.vbt and b/src/mainboard/google/octopus/variants/lick/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index e2b35cb5982..13602e798b8 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -98,15 +98,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end diff --git a/src/mainboard/google/octopus/variants/meep/data.vbt b/src/mainboard/google/octopus/variants/meep/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/meep/data.vbt and b/src/mainboard/google/octopus/variants/meep/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt b/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt index ac58bd4e0cc..548c5119193 100644 Binary files a/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt and b/src/mainboard/google/octopus/variants/meep/dorp-hdmi-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 3aa8d9dac2f..8a9c7fc2c44 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -14,9 +14,12 @@ static const struct pad_config default_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + /* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), }; static const struct pad_config hdmi_sku_override_table[] = { @@ -33,9 +36,12 @@ static const struct pad_config hdmi_sku_override_table[] = { PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + /* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/meep/overridetree.cb b/src/mainboard/google/octopus/variants/meep/overridetree.cb index 87521413d10..82bda654b08 100644 --- a/src/mainboard/google/octopus/variants/meep/overridetree.cb +++ b/src/mainboard/google/octopus/variants/meep/overridetree.cb @@ -147,7 +147,7 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end @@ -158,7 +158,7 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0xa on end end @@ -186,7 +186,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -201,7 +201,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 6 @@ -209,8 +209,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -222,7 +222,7 @@ chip soc/intel/apollolake register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "130" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -236,7 +236,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt b/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt index 1d93571b5fc..446210021de 100644 Binary files a/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt and b/src/mainboard/google/octopus/variants/meep/vortininja-data.vbt differ diff --git a/src/mainboard/google/octopus/variants/phaser/data.vbt b/src/mainboard/google/octopus/variants/phaser/data.vbt index fbcf46e8494..57a18505121 100644 Binary files a/src/mainboard/google/octopus/variants/phaser/data.vbt and b/src/mainboard/google/octopus/variants/phaser/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/phaser/gpio.c b/src/mainboard/google/octopus/variants/phaser/gpio.c index f227b019a94..7a8bf37ec9b 100644 --- a/src/mainboard/google/octopus/variants/phaser/gpio.c +++ b/src/mainboard/google/octopus/variants/phaser/gpio.c @@ -18,9 +18,12 @@ static const struct pad_config default_override_table[] = { DISPUPD), PAD_NC(GPIO_143, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + /* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_161, DN_20K), @@ -41,9 +44,12 @@ static const struct pad_config sku1_default_override_table[] = { DISPUPD), PAD_NC(GPIO_143, UP_20K), + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, - DISPUPD), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), + /* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), PAD_NC(GPIO_161, DN_20K), diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index ae52c3dc57c..ec563ee9240 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -91,6 +91,7 @@ chip soc/intel/apollolake register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end @@ -118,7 +119,7 @@ chip soc/intel/apollolake register "name" = ""RT58"" register "desc" = ""Realtek RT5682"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_137_IRQ)" - register "probed" = "1" + register "detect" = "1" register "property_count" = "1" # Set the jd_src to RT5668_JD1 for jack detection register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" @@ -133,15 +134,16 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" register "generic.wake" = "GPE0_DW3_27" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -151,7 +153,7 @@ chip soc/intel/apollolake register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -163,7 +165,7 @@ chip soc/intel/apollolake register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" register "generic.reset_delay_ms" = "45" @@ -175,8 +177,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" @@ -188,7 +190,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7502"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "generic.enable_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" diff --git a/src/mainboard/google/octopus/variants/yorp/data.vbt b/src/mainboard/google/octopus/variants/yorp/data.vbt index 764ee940ed3..0d92b64b089 100644 Binary files a/src/mainboard/google/octopus/variants/yorp/data.vbt and b/src/mainboard/google/octopus/variants/yorp/data.vbt differ diff --git a/src/mainboard/google/octopus/variants/yorp/gpio.c b/src/mainboard/google/octopus/variants/yorp/gpio.c index 63763b34aaa..20362d9b0f7 100644 --- a/src/mainboard/google/octopus/variants/yorp/gpio.c +++ b/src/mainboard/google/octopus/variants/yorp/gpio.c @@ -31,6 +31,11 @@ static const struct pad_config early_gpio_table[] = { */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, ENPU), /* ESPI_IO1 */ + + /* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD), + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/octopus/variants/yorp/overridetree.cb b/src/mainboard/google/octopus/variants/yorp/overridetree.cb index a7fec750666..7b254abad29 100644 --- a/src/mainboard/google/octopus/variants/yorp/overridetree.cb +++ b/src/mainboard/google/octopus/variants/yorp/overridetree.cb @@ -79,7 +79,7 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchpad"" register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPIO_135_IRQ)" register "wake" = "GPE0_DW3_27" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 6 @@ -87,8 +87,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_212_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)" diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index dd6df3ea134..69f2f62fb08 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -36,4 +36,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_PARROT diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 6d5e9070fe8..4bd1ed7c1de 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -29,11 +29,10 @@ Scope (\_SB) { Device (TPAD) { - Name (_UID, 1) - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_REV, 2) // Trackpad Wake is GPIO12, wake from S3 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 3007bcbc9aa..046dad1fe23 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -47,6 +47,7 @@ config BOARD_GOOGLE_NAMI select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select SPI_TPM select SYSTEM_TYPE_LAPTOP @@ -57,6 +58,7 @@ config BOARD_GOOGLE_NAUTILUS select DRIVERS_I2C_DA7219 select I2C_TPM select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select SYSTEM_TYPE_CONVERTIBLE select VARIANT_HAS_CAMERA_ACPI @@ -66,6 +68,7 @@ config BOARD_GOOGLE_NOCTURNE select DRIVERS_I2C_DA7219 select DRIVERS_I2C_MAX98373 select DRIVERS_I2C_SX9310 + select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EXCLUDE_NATIVE_SD_INTERFACE @@ -74,7 +77,6 @@ config BOARD_GOOGLE_NOCTURNE select NO_FADT_8042 select SPI_TPM select SYSTEM_TYPE_DETACHABLE - select VARIANT_HAS_CAMERA_ACPI config BOARD_GOOGLE_RAMMUS select BOARD_GOOGLE_BASEBOARD_POPPY @@ -93,6 +95,7 @@ config BOARD_GOOGLE_SORAKA select DRIVERS_I2C_MAX98927 select I2C_TPM select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT select NO_FADT_8042 select SYSTEM_TYPE_DETACHABLE select VARIANT_HAS_CAMERA_ACPI @@ -222,4 +225,8 @@ config UART_FOR_CONSOLE config USE_PM_ACPI_TIMER default n +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_POPPY diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 0e6c7b98c60..07acad7809d 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -9,6 +9,8 @@ #include +#define SUBSYSTEM_ID 0x1AE0006C + static void mainboard_init(struct device *dev) { mainboard_ec_init(); @@ -31,6 +33,8 @@ static unsigned long mainboard_write_acpi_tables(const struct device *device, if (nhlt == NULL) return start_addr; + nhlt->subsystem_id = SUBSYSTEM_ID; + variant_nhlt_init(nhlt); variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision); diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index d26f6bd28a4..92ac8322754 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -231,6 +231,7 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on + subsystemid 0x1AE0 0x006C inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index ffea6949100..6db66641722 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -141,7 +141,7 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -213,7 +213,7 @@ static const struct pad_config gpio_table[] = { /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ - PAD_CFG_GPO(GPP_E11, 0, DEEP), + PAD_CFG_GPO(GPP_E11, 1, DEEP), /* E12 : USB2_OC3# ==> NC */ PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ @@ -354,6 +354,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index db4aeebb9f1..7fd1e3b4e7e 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -265,8 +265,8 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" @@ -278,7 +278,7 @@ chip soc/intel/skylake register "hid" = ""ATML0001"" register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "probed" = "1" + register "detect" = "1" register "has_power_resource" = "1" register "disable_gpio_export_in_crs" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" @@ -345,7 +345,7 @@ chip soc/intel/skylake register "name" = ""RT53"" register "desc" = ""Realtek RT5663"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" - register "probed" = "1" + register "detect" = "1" device i2c 13 on end end end # I2C #5 diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index c7abe77be5e..cf2a7905007 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -144,7 +144,7 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = { /* E2 : SATAXPCIE2 ==> NC */ PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ - PAD_CFG_GPO(GPP_E3, 0, DEEP), + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ @@ -355,6 +355,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 7609e004cc2..ab312d9142d 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "1" @@ -280,8 +289,8 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "reset_delay_ms" = "20" register "reset_off_delay_ms" = "2" @@ -296,8 +305,8 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "reset_delay_ms" = "1" register "reset_off_delay_ms" = "2" @@ -308,13 +317,14 @@ chip soc/intel/skylake register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" register "stop_delay_ms" = "20" register "stop_off_delay_ms" = "2" + register "disable_gpio_export_in_crs" = "1" device i2c 39 on end end chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" register "generic.enable_delay_ms" = "45" register "generic.has_power_resource" = "1" @@ -326,7 +336,7 @@ chip soc/intel/skylake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" @@ -341,16 +351,18 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" register "wake" = "GPE0_DW2_16" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" register "generic.wake" = "GPE0_DW2_16" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -360,7 +372,7 @@ chip soc/intel/skylake register "generic.hid" = ""WCOM005C"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D1_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" register "generic.reset_delay_ms" = "20" register "generic.has_power_resource" = "1" diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index b5ec95405e4..9762a69fd9c 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -57,9 +57,9 @@ static const struct pad_config gpio_table[] = { /* B2 : VRALERT# ==> NC */ PAD_NC(GPP_B2, NONE), /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ - PAD_CFG_GPO(GPP_B3, 0, DEEP), + PAD_CFG_GPO(GPP_B3, 1, DEEP), /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_B4, 0, DEEP), + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* B5 : SRCCLKREQ0# ==> NC */ PAD_NC(GPP_B5, NONE), /* B6 : SRCCLKREQ1# ==> CLKREQ_PCIE#1 */ @@ -337,6 +337,8 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : CPU_GP3 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */ @@ -381,14 +383,14 @@ static const struct pad_config nami_default_sku_gpio_table[] = { /* D17 : DMIC_CLK1 ==> SOC_DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), + PAD_CFG_GPO(GPP_C3, 1, DEEP), }; static const struct pad_config no_dmic1_sku_gpio_table[] = { /* D17 : DMIC_CLK1 ==> NC */ PAD_NC(GPP_D17, NONE), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), + PAD_CFG_GPO(GPP_C3, 1, DEEP), }; static const struct pad_config pantheon_gpio_table[] = { @@ -414,7 +416,7 @@ static const struct pad_config fpmcu_gpio_table[] = { /* B22 : GSPI1_MOSI ==> PCH_SPI_FP_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), /* C3 : SML0CLK ==> TOUCHSCREEN_DIS# */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), + PAD_CFG_GPO(GPP_C3, 1, DEEP), /* C9 : UART0_TXD ==> FP_RST_ODL */ PAD_CFG_GPO(GPP_C9, 1, DEEP), /* D5 : ISH_I2C0_SDA ==> FPMCU_BOOT0 */ @@ -478,3 +480,15 @@ const struct pad_config *variant_sku_gpio_table(size_t *num) } return board_gpio_tables; } + + +static const struct pad_config romstage_gpio_table[] = { + /* B3 : CPU_GP2 ==> TOUCHSCREEN_RST# */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), +}; + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 629469d48e2..48a556e1e51 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -174,6 +174,56 @@ const char *smbios_mainboard_manufacturer(void) return manuf; } +const char *smbios_mainboard_product_name(void) +{ + uint32_t sku_id = variant_board_sku(); + static char product[12]; + + switch (sku_id) { + case SKU_0_PANTHEON: + case SKU_1_PANTHEON: + case SKU_2_PANTHEON: + case SKU_3_PANTHEON: + case SKU_4_PANTHEON: + snprintf(product, sizeof(product), "Pantheon"); break; + case SKU_0_VAYNE: + case SKU_1_VAYNE: + case SKU_2_VAYNE: + snprintf(product, sizeof(product), "Vayne"); break; + case SKU_0_AKALI: + case SKU_1_AKALI: + snprintf(product, sizeof(product), "Akali"); break; + case SKU_0_AKALI360: + case SKU_1_AKALI360: + snprintf(product, sizeof(product), "Akali 360"); break; + case SKU_0_BARD: + case SKU_1_BARD: + case SKU_2_BARD: + case SKU_3_BARD: + snprintf(product, sizeof(product), "Bard"); break; + case SKU_0_EKKO: + case SKU_1_EKKO: + case SKU_2_EKKO: + case SKU_3_EKKO: + snprintf(product, sizeof(product), "Ekko"); break; + case SKU_0_SONA: + case SKU_1_SONA: + snprintf(product, sizeof(product), "Sona"); break; + case SKU_0_SYNDRA: + case SKU_1_SYNDRA: + case SKU_2_SYNDRA: + case SKU_3_SYNDRA: + case SKU_4_SYNDRA: + case SKU_5_SYNDRA: + case SKU_6_SYNDRA: + case SKU_7_SYNDRA: + snprintf(product, sizeof(product), "Syndra"); break; + default: + snprintf(product, sizeof(product), "Nami"); break; + } + return product; +} + const char *mainboard_vbt_filename(void) { uint32_t sku_id = variant_board_sku(); diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b8a18127519..6249345c90b 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" @@ -288,7 +297,7 @@ chip soc/intel/skylake register "generic.hid" = ""SYTS7813"" register "generic.desc" = ""Synaptics Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "45" register "generic.has_power_resource" = "1" @@ -374,7 +383,7 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15 on end end diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index e06355a3b7b..f99fb2b879e 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -116,7 +116,7 @@ static const struct pad_config gpio_table[] = { /* C8 : UART0_RXD ==> CHP3_P3.3V_DX_WFCAM_EN */ PAD_CFG_GPO(GPP_C8, 0, DEEP), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ - PAD_CFG_GPO(GPP_C9, 0, DEEP), + PAD_CFG_GPO(GPP_C9, 1, DEEP), /* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_UFCAM_EN */ @@ -141,8 +141,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> CHP3_TX_SERVO_RX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), @@ -334,6 +334,9 @@ static const struct pad_config early_gpio_table[] = { /* C6 : SM1CLK ==> EC_IN_RW_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, UP_20K, DEEP), + /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ + PAD_CFG_GPO(GPP_C9, 1, DEEP), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ @@ -345,6 +348,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 03336f2e473..f3a4005f5bc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -248,10 +248,16 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on + subsystemid 0x1AE0 0x006C inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem - device pci 05.0 on end # SA IMGU + device pci 05.0 on + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_IMGU" + device generic 0 on end + end + end # SA IMGU - MIPI Camera device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -283,14 +289,24 @@ chip soc/intel/skylake end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 14.3 on end # Camera + device pci 14.3 on + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + register "cio2_num_ports" = "2" + register "cio2_lanes_used[0]" = "4" + register "cio2_lane_endpoint[0]" = ""\\_SB.PCI0.I2C3.CAM0"" + register "cio2_lanes_used[1]" = "4" + register "cio2_lane_endpoint[1]" = ""\\_SB.PCI0.I2C5.CAM1"" + device generic 0 on end + end + end # Camera device pci 15.0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST_PLUS" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" register "generic.reset_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" @@ -320,7 +336,55 @@ chip soc/intel/skylake end end # I2C #1 device pci 15.2 off end # I2C #2 - device pci 15.3 on end # I2C #3 - Camera + device pci 15.3 on + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "acpi_hid" = ""SONY319A"" + register "chip_name" = ""Sony IMX319 Camera"" + register "pr0" = ""FCPR"" + register "rom_address" = "0x50" + register "ssdb.sensor_card_sku" = "0x20" + register "ssdb.rom_type" = "9" # m24c64 + register "use_pld" = "1" + register "num_freq_entries" = "1" + register "link_freq[0]" = "482400000" + register "remote_name" = ""CIO2"" + register "has_power_resource" = "1" + register "low_power_probe" = "1" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_1" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" # GPIO_PCH_FCAM_CLK_EN + register "gpio_panel.gpio[1].gpio_num" = "GPP_B4" # GPIO_FCAM_PWR_EN + register "gpio_panel.gpio[2].gpio_num" = "GPP_D15" # GPIO_FCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 0)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(0, 3)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 12)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + + device i2c 0x10 on end + end + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "chip_name" = ""M24C64S"" + register "pr0" = ""FCPR"" + register "nvm_size" = "8192" + register "nvm_width" = "16" + device i2c 0x50 on end + end + end # I2C #3 - Camera device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -345,6 +409,69 @@ chip soc/intel/skylake register "startup_sensor" = "0" register "proxraw_strength" = "0" end + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + register "acpi_hid" = ""SONY355A"" + register "chip_name" = ""Sony IMX355A Camera"" + register "sensor_name" = ""50-704GVGEA8"" + register "pr0" = ""RCPR"" + register "vcm_address" = "0x0c" + register "rom_address" = "0x51" + register "ssdb.sensor_card_sku" = "0x20" + register "ssdb.link_used" = "1" + register "ssdb.rom_type" = "9" + register "ssdb.vcm_type" = "9" + register "use_pld" = "1" + register "pld.panel" = "PLD_PANEL_BACK" + register "pld.horizontal_position" = "PLD_HORIZONTAL_POSITION_RIGHT" + register "num_freq_entries" = "1" + register "link_freq[0]" = "360000000" + register "remote_name" = ""CIO2"" + register "has_power_resource" = "1" + register "low_power_probe" = "1" + + #Controls + register "clk_panel.clks[0].clknum" = "IMGCLKOUT_1" + register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ" + register "gpio_panel.gpio[0].gpio_num" = "GPP_D14" # GPIO_PCH_RCAM_CLK_EN + register "gpio_panel.gpio[1].gpio_num" = "GPP_D7" # GPIO_RCAM_PWR_EN + register "gpio_panel.gpio[2].gpio_num" = "GPP_D16" # GPIO_RCAM_RST_L + + #_ON + register "on_seq.ops_cnt" = "5" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 0)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(0, 3)" + register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 12)" + + #_OFF + register "off_seq.ops_cnt" = "4" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(2, 0)" + register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + + device i2c 0x1a on end + end + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_NVM" + register "acpi_uid" = "1" + register "chip_name" = ""M24C64S"" + register "pr0" = ""RCPR"" + register "nvm_size" = "8192" + register "nvm_width" = "16" + device i2c 0x51 on end + end + chip drivers/intel/mipi_camera + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + register "acpi_uid" = "3" + register "acpi_name" = ""VCM1"" + register "chip_name" = ""AKM AF DAC"" + register "pr0" = ""RCPR"" + register "vcm_compat" = ""asahi-kasei,ak7375"" + device i2c 0xc on end + end end # I2C #5 device pci 19.2 on chip drivers/i2c/max98373 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 6324d8fa479..e4b2e11b76d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -144,7 +144,7 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -220,7 +220,7 @@ static const struct pad_config gpio_table[] = { /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */ - PAD_CFG_TERM_GPO(GPP_E11, 0, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP), /* E12 : USB2_OC3# ==> NC */ PAD_NC(GPP_E12, NONE), /* E13 : DDPB_HPD0 ==> USB_C1_DP_HPD */ @@ -361,6 +361,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl deleted file mode 100644 index c3449a7f662..00000000000 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C3) -{ - PowerResource (FCPR, 0, 0) - { - Name (STA, 0) - Method (_ON, 0, Serialized) { - If (STA == 0) { - CTXS (GPIO_FCAM_RST_L) - STXS (GPIO_FCAM_PWR_EN) - STXS (GPIO_PCH_FCAM_CLK_EN) - Sleep (3) - STXS (GPIO_FCAM_RST_L) - - /* - * A delay of T7 (minimum of 5 ms) + T8 - * (max 5 ms + delay of coarse integration - * time value + 14 H, time for 14 horizontal - * lines) is needed to have the sensor ready - * for streaming, as soon as the power on - * sequence completes - */ - Sleep (11) - STA = 1 - } - } - Method (_OFF, 0, Serialized) { - If (STA == 1) { - CTXS (GPIO_PCH_FCAM_CLK_EN) - CTXS (GPIO_FCAM_RST_L) - CTXS (GPIO_FCAM_PWR_EN) - STA = 0 - } - } - Method (_STA, 0, NotSerialized) { - Return (STA) - } - } - - Device (CAM0) - { - Name (_HID, "SONY319A") /* _HID: Hardware ID */ - Name (_UID, Zero) /* _UID: Unique ID */ - Name (_DDN, "Sony IMX319 Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () - { - I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package () { FCPR }) - Name (_PR3, Package () { FCPR }) - - /* Port0 of CAM0 is connected to port0 of CIO2 device */ - Name (_DSD, Package () { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "port0", "PRT0" }, - }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "clock-frequency", 19200000 }, - } - }) - - Name (PRT0, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "port", 0 }, - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "endpoint0", "EP00" }, - } - }) - - Name (EP00, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "endpoint", 0 }, - Package () { "clock-lanes", 0 }, - Package () { "data-lanes", - Package () { 1, 2, 3, 4 } - }, - Package () { "link-frequencies", - Package() { 482400000 } - }, - Package () { "remote-endpoint", - Package() { \_SB.PCI0.CIO2, 0, 0 } - }, - } - }) - } - - Device (NVM0) - { - Name (_HID, "INT3499") /* _HID: Hardware ID */ - Name (_UID, Zero) /* _UID: Unique ID */ - Name (_DDN, "M24C64S") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () - { - I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C3", - 0x00, ResourceConsumer, ,) - }) - Name (_DEP, Package () { CAM0 }) - - Name (_PR0, Package () { FCPR }) - Name (_PR3, Package () { FCPR }) - - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "size", 8192 }, - Package () { "pagesize", 1 }, - Package () { "read-only", 1 }, - Package () { "address-width", 16 }, - } - }) - } -} diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl deleted file mode 100644 index 0e31eee538f..00000000000 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.I2C5) -{ - PowerResource (RCPR, 0, 0) - { - Name (STA, 0) - Method (_ON, 0, Serialized) { - If (STA == 0) { - CTXS (GPIO_RCAM_RST_L) - STXS (GPIO_RCAM_PWR_EN) - STXS (GPIO_PCH_RCAM_CLK_EN) - Sleep (3) - STXS (GPIO_RCAM_RST_L) - - /* - * A delay of T7 (minimum of 10 ms) + T8 - * (max 1.4 ms + delay of coarse integration - * time value) is needed to have the sensor - * ready for streaming, as soon as the power - * on sequence completes - */ - Sleep (12) - STA = 1 - } - } - Method (_OFF, 0, Serialized) { - If (STA == 1) { - CTXS (GPIO_PCH_RCAM_CLK_EN) - CTXS (GPIO_RCAM_RST_L) - CTXS (GPIO_RCAM_PWR_EN) - STA = 0 - } - } - Method (_STA, 0, NotSerialized) { - Return (STA) - } - } - - Device (CAM1) - { - Name (_HID, "SONY355A") /* _HID: Hardware ID */ - Name (_UID, Zero) /* _UID: Unique ID */ - Name (_DDN, "SONY IMX355A Camera") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () - { - I2cSerialBus (0x001A, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - - Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) - - /* Port0 of CAM1 is connected to port1 of CIO2 device */ - Name (_DSD, Package () { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "port0", "PRT0" }, - }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "clock-frequency", 19200000 }, - Package () { "lens-focus", - Package () { \_SB.PCI0.I2C5.VCM1 } - } - } - }) - - Name (PRT0, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "port", 0 }, - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "endpoint0", "EP00" }, - } - }) - - Name (EP00, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "endpoint", 0 }, - Package () { "clock-lanes", 0 }, - Package () { "data-lanes", - Package () { 1, 2, 3, 4 } - }, - Package () { "link-frequencies", - Package() { 360000000 } - }, - Package () { "remote-endpoint", - Package() { \_SB.PCI0.CIO2, 1, 0 } - }, - } - }) - } - - Device (VCM1) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - Name (_UID, 3) /* _UID: Unique ID */ - Name (_DDN, "AKM AF DAC") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () - { - I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - - Name (_DEP, Package() { CAM1 }) - - Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) - - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "compatible", "asahi-kasei,ak7375" }, - } - }) - } - - Device (NVM1) - { - Name (_HID, "INT3499") /* _HID: Hardware ID */ - Name (_UID, 1) /* _UID: Unique ID */ - Name (_DDN, "M24C64S") /* _DDN: DOS Device Name */ - - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - - Name (_CRS, ResourceTemplate () - { - I2cSerialBus (0x0051, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, ,) - }) - Name (_DEP, Package () { CAM1 }) - - Name (_PR0, Package () { RCPR }) - Name (_PR3, Package () { RCPR }) - - Name (_DSD, Package () - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "size", 8192 }, - Package () { "pagesize", 1 }, - Package () { "read-only", 1 }, - Package () { "address-width", 16 }, - } - }) - } -} diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl deleted file mode 100644 index 51b4ebc0460..00000000000 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/camera.asl +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "ipu_mainboard.asl" -#include "ipu_endpoints.asl" -#include "cam0.asl" -#include "cam1.asl" diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl deleted file mode 100644 index 06fef897b93..00000000000 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_endpoints.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.CIO2) -{ - Name (EP00, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "endpoint", 0 }, - Package () { "clock-lanes", 0 }, - Package () { "data-lanes", Package () { 1, 2, 3, 4 } }, - Package () { "remote-endpoint", - Package() { \_SB.PCI0.I2C3.CAM0, 0, 0 } - }, - } - }) - - Name (EP10, Package() { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "endpoint", 0 }, - Package () { "clock-lanes", 0 }, - Package () { "data-lanes", Package () { 1, 2, 3, 4 } }, - Package () { "remote-endpoint", - Package() { \_SB.PCI0.I2C5.CAM1, 0, 0 } - }, - } - }) -} diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl b/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl deleted file mode 100644 index 024dfed7522..00000000000 --- a/src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/ipu_mainboard.asl +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.CIO2) -{ - /* Define two ports for CIO2 device where endpoint of port0 - is connected to CAM0 and endpoint of port1 is connected to CAM1 */ - - Name (_DSD, Package () { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "port0", "PRT0" }, - Package () { "port1", "PRT1" }, - } - }) - - Name (PRT0, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "port", 0 }, /* csi 0 */ - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "endpoint0", "EP00" }, - } - }) - - Name (PRT1, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { "port", 1 }, /* csi 1 */ - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package () { - Package () { "endpoint0", "EP10" }, - } - }) - -} diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index c6c2d3df60b..011c236ffe4 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -234,6 +234,7 @@ chip soc/intel/skylake device lapic 0 on end end device domain 0 on + subsystemid 0x1AE0 0x006C inherit device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA thermal subsystem @@ -280,7 +281,7 @@ chip soc/intel/skylake register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""SISC Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" register "generic.enable_delay_ms" = "105" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" @@ -295,8 +296,9 @@ chip soc/intel/skylake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" # GPP_B5 + register "detect" = "1" device i2c 15 on end end end # I2C #1 diff --git a/src/mainboard/google/poppy/variants/rammus/gpio.c b/src/mainboard/google/poppy/variants/rammus/gpio.c index c67c560c708..1f7b4b3bf4c 100644 --- a/src/mainboard/google/poppy/variants/rammus/gpio.c +++ b/src/mainboard/google/poppy/variants/rammus/gpio.c @@ -143,7 +143,7 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -203,7 +203,7 @@ static const struct pad_config gpio_table[] = { /* E2 : SATAXPCIE2 ==> NC */ PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN I2C OPERATION ENABLE/DISABLE. */ - PAD_CFG_GPO(GPP_E3, 0, DEEP), + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ @@ -358,6 +358,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 5c347924df7..1e5bd22c207 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -3,6 +3,15 @@ chip soc/intel/skylake # IGD Displays register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "panel_cfg" = "{ + .up_delay_ms = 100, + .down_delay_ms = 500, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 1000, + }" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" @@ -267,7 +276,7 @@ chip soc/intel/skylake register "generic.hid" = ""WCOMCOHO"" register "generic.desc" = ""WCOM Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" @@ -319,7 +328,7 @@ chip soc/intel/skylake register "name" = ""RT53"" register "desc" = ""Realtek RT5663"" register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" - register "probed" = "1" + register "detect" = "1" device i2c 13 on end end end # I2C #5 diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 808ab3b504e..2614bbd9083 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -143,7 +143,7 @@ static const struct pad_config gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -203,7 +203,7 @@ static const struct pad_config gpio_table[] = { /* E2 : SATAXPCIE2 ==> NC */ PAD_NC(GPP_E2, NONE), /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ - PAD_CFG_GPO(GPP_E3, 0, DEEP), + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* E4 : SATA_DEVSLP0 ==> NC */ PAD_NC(GPP_E4, NONE), /* E5 : SATA_DEVSLP1 ==> NC */ @@ -219,7 +219,7 @@ static const struct pad_config gpio_table[] = { /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */ - PAD_CFG_GPO(GPP_E11, 0, DEEP), + PAD_CFG_GPO(GPP_E11, 1, DEEP), /* E12 : USB2_OC3# ==> USB2_OC3_L */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */ @@ -357,6 +357,9 @@ static const struct pad_config early_gpio_table[] = { /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_C22, 1, DEEP), + /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, UP_20K, DEEP), @@ -375,3 +378,14 @@ const struct pad_config *variant_early_gpio_table(size_t *num) *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + +static const struct pad_config romstage_gpio_table[] = { + /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), +}; + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig new file mode 100644 index 00000000000..74333ac0001 --- /dev/null +++ b/src/mainboard/google/puff/Kconfig @@ -0,0 +1,187 @@ +config BOARD_GOOGLE_BASEBOARD_PUFF + def_bool n + select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_I2C_SX9310 + select DRIVERS_INTEL_DPTF + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL + select EC_GOOGLE_CHROMEEC_SKUID + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_TPM2 + select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_DTT + select SOC_INTEL_CSE_LITE_SKU + select SPD_CACHE_IN_FMAP + select SPD_READ_BY_WORD + select SPI_TPM + select TPM_GOOGLE_CR50 + +config BOARD_GOOGLE_AMBASSADOR + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_DOOLY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_DUFFY_LEGACY + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_DUFFY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_FAFFY + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_GENESIS + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_KAISA_LEGACY + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_KAISA + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_MOONBUGGY + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_NOIBAT + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_PUFF + select BOARD_GOOGLE_BASEBOARD_PUFF + select BOARD_ROMSIZE_KB_32768 + select INTEL_GMA_HAVE_VBT + +config BOARD_GOOGLE_SCOUT + select BOARD_GOOGLE_BASEBOARD_PUFF + +config BOARD_GOOGLE_WYVERN + select BOARD_GOOGLE_BASEBOARD_PUFF + select INTEL_GMA_HAVE_VBT + +if BOARD_GOOGLE_BASEBOARD_PUFF + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config CHROMEOS + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_ALTFW + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + select VBOOT_LID_SWITCH + select CHROMEOS_CSE_BOARD_RESET_OVERRIDE + +config CHROMEOS_WIFI_SAR + bool "Enable SAR options for Chrome OS build" + depends on CHROMEOS + select DSAR_ENABLE + select GEO_SAR_ENABLE + select SAR_ENABLE + select USE_SAR + +config DEVICETREE + default "variants/baseboard/devicetree.cb" + +config DIMM_MAX + default 2 + +config DRIVER_TPM_SPI_BUS + default 0x1 + +config UART_FOR_CONSOLE + default 0 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 && CHROMEOS + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 && CHROMEOS + +config POWER_OFF_ON_CR50_UPDATE + bool + default n + +config MAINBOARD_DIR + default "google/puff" + +config MAINBOARD_FAMILY + string + default "Google_Puff" + +config MAINBOARD_PART_NUMBER + default "Ambassador" if BOARD_GOOGLE_AMBASSADOR + default "Dooly" if BOARD_GOOGLE_DOOLY + default "Duffy" if BOARD_GOOGLE_DUFFY + default "Duffy" if BOARD_GOOGLE_DUFFY_LEGACY + default "Faffy" if BOARD_GOOGLE_FAFFY + default "Genesis" if BOARD_GOOGLE_GENESIS + default "Kaisa" if BOARD_GOOGLE_KAISA + default "Kaisa" if BOARD_GOOGLE_KAISA_LEGACY + default "Moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "Noibat" if BOARD_GOOGLE_NOIBAT + default "Puff" if BOARD_GOOGLE_PUFF + default "Scout" if BOARD_GOOGLE_SCOUT + default "Wyvern" if BOARD_GOOGLE_WYVERN + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config TPM_TIS_ACPI_INTERRUPT + int + default 53 # GPE0_DW1_21 (GPP_C21) + +config VARIANT_DIR + default "ambassador" if BOARD_GOOGLE_AMBASSADOR + default "dooly" if BOARD_GOOGLE_DOOLY + default "duffy" if BOARD_GOOGLE_DUFFY + default "duffy" if BOARD_GOOGLE_DUFFY_LEGACY + default "faffy" if BOARD_GOOGLE_FAFFY + default "genesis" if BOARD_GOOGLE_GENESIS + default "kaisa" if BOARD_GOOGLE_KAISA + default "kaisa" if BOARD_GOOGLE_KAISA_LEGACY + default "moonbuggy" if BOARD_GOOGLE_MOONBUGGY + default "noibat" if BOARD_GOOGLE_NOIBAT + default "puff" if BOARD_GOOGLE_PUFF + default "scout" if BOARD_GOOGLE_SCOUT + default "wyvern" if BOARD_GOOGLE_WYVERN + +config VBOOT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_EARLY_EC_SYNC + +config USE_PM_ACPI_TIMER + default n + +config TIANOCORE_BOOT_TIMEOUT + int + default 5 + +endif # BOARD_GOOGLE_BASEBOARD_PUFF diff --git a/src/mainboard/google/puff/Kconfig.name b/src/mainboard/google/puff/Kconfig.name new file mode 100644 index 00000000000..5e2a365d398 --- /dev/null +++ b/src/mainboard/google/puff/Kconfig.name @@ -0,0 +1,40 @@ +comment "Puff" + +config BOARD_GOOGLE_AMBASSADOR + bool "-> Ambassador" + +config BOARD_GOOGLE_DOOLY + bool "-> Dooly" + +config BOARD_GOOGLE_DUFFY_LEGACY + bool "-> Duffy Legacy (32MB)" + +config BOARD_GOOGLE_DUFFY + bool "-> Duffy (ASUS Chromebox 4)" + +config BOARD_GOOGLE_FAFFY + bool "-> Faffy (ASUS Fanless Chromebox)" + +config BOARD_GOOGLE_GENESIS + bool "-> Genesis" + +config BOARD_GOOGLE_KAISA_LEGACY + bool "-> Kaisa Legacy (32MB)" + +config BOARD_GOOGLE_KAISA + bool "-> Kaisa (Acer Chromebox CXI4)" + +config BOARD_GOOGLE_MOONBUGGY + bool "-> Moonbuggy" + +config BOARD_GOOGLE_NOIBAT + bool "-> Noibat (HP Chromebox G3)" + +config BOARD_GOOGLE_PUFF + bool "-> Puff" + +config BOARD_GOOGLE_SCOUT + bool "-> Scout" + +config BOARD_GOOGLE_WYVERN + bool "-> Wyvern (CTL Chromebox CBx2)" diff --git a/src/mainboard/google/puff/Makefile.inc b/src/mainboard/google/puff/Makefile.inc new file mode 100644 index 00000000000..12d43743058 --- /dev/null +++ b/src/mainboard/google/puff/Makefile.inc @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += ramstage.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c + +romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/puff/board_info.txt b/src/mainboard/google/puff/board_info.txt new file mode 100644 index 00000000000..1168548e9e4 --- /dev/null +++ b/src/mainboard/google/puff/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Puff +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/puff/bootblock.c b/src/mainboard/google/puff/bootblock.c new file mode 100644 index 00000000000..6e2f34d10ed --- /dev/null +++ b/src/mainboard/google/puff/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + const struct pad_config *variant_early_table; + size_t variant_gpios; + + variant_early_table = variant_early_gpio_table(&variant_gpios); + gpio_configure_pads(variant_early_table, variant_gpios); +} diff --git a/src/mainboard/google/hatch/chromeos-puff-16MiB.fmd b/src/mainboard/google/puff/chromeos-16MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-puff-16MiB.fmd rename to src/mainboard/google/puff/chromeos-16MiB.fmd diff --git a/src/mainboard/google/hatch/chromeos-puff-32MiB.fmd b/src/mainboard/google/puff/chromeos-32MiB.fmd similarity index 100% rename from src/mainboard/google/hatch/chromeos-puff-32MiB.fmd rename to src/mainboard/google/puff/chromeos-32MiB.fmd diff --git a/src/mainboard/google/puff/chromeos.c b/src/mainboard/google/puff/chromeos.c new file mode 100644 index 00000000000..bbca895340a --- /dev/null +++ b/src/mainboard/google/puff/chromeos.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *cros_gpios; + size_t num_gpios = 0; + + cros_gpios = variant_cros_gpios(&num_gpios); + + chromeos_acpi_gpio_generate(cros_gpios, num_gpios); +} + +int get_ec_is_trusted(void) +{ + /* EC is trusted if not in RW. */ + return !gpio_get(GPIO_EC_IN_RW); +} diff --git a/src/mainboard/google/puff/dsdt.asl b/src/mainboard/google/puff/dsdt.asl new file mode 100644 index 00000000000..a0f1a537d89 --- /dev/null +++ b/src/mainboard/google/puff/dsdt.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include + #include + + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } +} diff --git a/src/mainboard/google/puff/ec.c b/src/mainboard/google/puff/ec.c new file mode 100644 index 00000000000..e25abb4ede3 --- /dev/null +++ b/src/mainboard/google/puff/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/puff/ramstage.c b/src/mainboard/google/puff/ramstage.c new file mode 100644 index 00000000000..ff466a34a81 --- /dev/null +++ b/src/mainboard/google/puff/ramstage.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void mainboard_silicon_init_params(FSPS_UPD *supd) +{ + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +void __weak variant_ramstage_init(void) +{ + /* Default weak implementation */ +} + +void __weak variant_mainboard_enable(struct device *dev) +{ + /* Override mainboard settings per board */ +} + +static void mainboard_init(struct device *dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + variant_mainboard_enable(dev); +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *base_table; + const struct pad_config *override_table; + size_t base_gpios; + size_t override_gpios; + + base_table = base_gpio_table(&base_gpios); + override_table = override_gpio_table(&override_gpios); + + gpio_configure_pads_with_override(base_table, + base_gpios, + override_table, + override_gpios); + + variant_ramstage_init(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/puff/romstage.c similarity index 100% rename from src/mainboard/google/hatch/romstage_spd_smbus.c rename to src/mainboard/google/puff/romstage.c diff --git a/src/mainboard/google/puff/smihandler.c b/src/mainboard/google/puff/smihandler.c new file mode 100644 index 00000000000..ceab9fa2acc --- /dev/null +++ b/src/mainboard/google/puff/smihandler.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_sleep_gpio_table(slp_typ, &num); + gpio_configure_pads(pads, num); + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S0IX_WAKE_EVENTS); +} diff --git a/src/mainboard/google/hatch/variants/ambassador/Makefile.inc b/src/mainboard/google/puff/variants/ambassador/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/ambassador/Makefile.inc rename to src/mainboard/google/puff/variants/ambassador/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/ambassador/gpio.c b/src/mainboard/google/puff/variants/ambassador/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/ambassador/gpio.c rename to src/mainboard/google/puff/variants/ambassador/gpio.c diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h b/src/mainboard/google/puff/variants/ambassador/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/ambassador/include/variant/ec.h rename to src/mainboard/google/puff/variants/ambassador/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h b/src/mainboard/google/puff/variants/ambassador/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/ambassador/include/variant/gpio.h rename to src/mainboard/google/puff/variants/ambassador/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/ambassador/overridetree.cb b/src/mainboard/google/puff/variants/ambassador/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/ambassador/overridetree.cb rename to src/mainboard/google/puff/variants/ambassador/overridetree.cb diff --git a/src/mainboard/google/puff/variants/baseboard/Makefile.inc b/src/mainboard/google/puff/variants/baseboard/Makefile.inc new file mode 100644 index 00000000000..69f9322fb53 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/Makefile.inc @@ -0,0 +1,13 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-$(CONFIG_BOARD_GOOGLE_BASEBOARD_PUFF) += mainboard.c + +verstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/puff/variants/baseboard/devicetree.cb b/src/mainboard/google/puff/variants/baseboard/devicetree.cb new file mode 100644 index 00000000000..976d82970c8 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/devicetree.cb @@ -0,0 +1,355 @@ +chip soc/intel/cannonlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # DW1 is used by: + # - GPP_C1 - PCIE_14_WLAN_WAKE_ODL + # - GPP_C21 - H1_PCH_INT_ODL + register "gpe0_dw0" = "PMC_GPP_A" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_D" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # FSP configuration + register "SkipExtGfxScan" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Configure devslp pad reset to PLT_RST + register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" + register "satapwroptimize" = "1" + # Enable System Agent dynamic frequency + register "SaGv" = "SaGv_Enabled" + # Enable S0ix + register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 64, + }" + register "Device4Enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "tcc_offset" = "10" # TCC of 90C + # Unlock GPIO pads + register "PchUnlockGpioPads" = "1" + # SD card WP pin configuration + register "ScsSdCardWpPinEnabled" = "0" + + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "77" + + # Select CPU PL2/PL4 config + register "cpu_pl2_4_cfg" = "baseline" + + # VR Settings Configuration for 4 Domains + #+----------------+-------+-------+-------+-------+ + #| Domain/Setting | SA | IA | GTUS | GTS | + #+----------------+-------+-------+-------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 6A | 70A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | + #+----------------+-------+-------+-------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 180, + .dc_loadline = 180, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = 0, + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "1" # 500ms + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + + # Enable Audio DSP oscillator qualification for S0ix + register "cppmvric2_adsposcdis" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN + + # Enable Root port 9(x4) for NVMe. + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "8" + # ClkReq-to-ClkSrc mapping for CLK SRC 1 + register "PcieClkSrcClkReq[1]" = "1" + + # PCIe port 14 for M.2 E-key WLAN + register "PcieRpEnable[13]" = "1" + register "PcieRpLtrEnable[13]" = "1" + # RP 14 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcClkReq[3]" = "3" + + #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkSsp0" = "1" + register "PchHdaAudioLinkSsp1" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "0" + + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + # Disable dynamic clock gating; with bits 0-5 set in these registers, + # some short interrupt pulses were missed (esp. cr50 irq) + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # SA IPU + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi wifi + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 (USB) + device pci 1c.1 off end # PCI Express Port 2 (USB) + device pci 1c.2 off end # PCI Express Port 3 (USB) + device pci 1c.3 off end # PCI Express Port 4 (USB) + device pci 1c.4 off end # PCI Express Port 5 (USB) + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (X4 NVME) + register "PcieRpSlotImplemented[8]" = "1" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express port 13 + device pci 1d.5 on + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_01" + device pci 00.0 on end + end + register "PcieRpSlotImplemented[13]" = "1" + end # PCI Express Port 14 (x4) + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/google/puff/variants/baseboard/gpio.c b/src/mainboard/google/puff/variants/baseboard/gpio.c new file mode 100644 index 00000000000..f9ffcd96eca --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/gpio.c @@ -0,0 +1,439 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* A0 : GPP_A0 ==> NC */ + PAD_NC(GPP_A0, NONE), + /* A1 : ESPI_IO0 */ + /* A2 : ESPI_IO1 */ + /* A3 : ESPI_IO2 */ + /* A4 : ESPI_IO3 */ + /* A5 : ESPI_CS# */ + /* A6 : GPP_A6 ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : PP3300_SOC_A */ + PAD_NC(GPP_A7, NONE), + /* A8 : GPP_A8 ==> NC */ + PAD_NC(GPP_A8, NONE), + /* A9 : ESPI_CLK */ + /* A10 : GPP_A10 ==> NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : GPP_A11 ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : GPP_A12 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A13 : SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + /* A14 : ESPI_RST_L */ + /* A15 : SUSACK_L */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : SD_1P8_SEL => NC */ + PAD_NC(GPP_A16, NONE), + /* A17 : EN_PP3300_SD_DX */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* A18 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ + PAD_CFG_GPO(GPP_A19, 1, DEEP), + /* A20 : WLAN_INT_L */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT), + /* A21 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT), + /* A22 : FPMCU_PCH_BOOT0 */ + PAD_CFG_GPO(GPP_A22, 0, DEEP), + /* A23 : FPMCU_PCH_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : GPP_B2 ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : GPP_B3 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B4 : GPP_B4 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : SRCCLKREQ1 */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : GPP_B7 ==> NC */ + PAD_NC(GPP_B7, NONE), + /* B8 : PCIE_14_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : GPP_B9 ==> NC */ + PAD_NC(GPP_B9, NONE), + /* B10 : GPP_B10 ==> NC */ + PAD_NC(GPP_B10, NONE), + /* B11 : EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : PCH_SPI_FPMCU_CLK_R */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : PCH_SPI_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : PCH_SPI_FPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : GPP_B23_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : GPP_C0 => NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : PCIE_14_WLAN_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE), + /* C2 : GPP_C2 => NC */ + PAD_NC(GPP_C2, NONE), + /* C3 : WLAN_OFF_L */ + PAD_CFG_GPO(GPP_C3, 1, DEEP), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C5 : GPP_C5 => NC */ + PAD_NC(GPP_C5, NONE), + /* C6 : PEN_PDCT_OD_L */ + PAD_NC(GPP_C6, NONE), + /* C7 : PEN_IRQ_OD_L */ + PAD_NC(GPP_C7, NONE), + /* C8 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : GPP_10 ==> GPP_C10_TP */ + PAD_NC(GPP_C10, NONE), + /* C11 : GPP_11 ==> EN_FP_RAILS */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), + /* C12 : GPP_C12 ==> NC */ + PAD_NC(GPP_C12, NONE), + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 1, DEEP), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* C16 : PCH_I2C_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : PCH_I2C_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : PCH_I2C_TOUCHSCREEN_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : PCH_I2C_TOUCHSCREEN_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_C22, NONE, DEEP), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : TP31 */ + PAD_NC(GPP_D0, NONE), + /* D1 : TP16 */ + PAD_NC(GPP_D1, NONE), + /* D2 : TP26 */ + PAD_NC(GPP_D2, NONE), + /* D3 : TP27 */ + PAD_NC(GPP_D3, NONE), + /* D4 : TP40 */ + PAD_NC(GPP_D4, NONE), + /* D5 : WWAN_CONFIG_0 */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_CONFIG_1 */ + PAD_NC(GPP_D6, NONE), + /* D7 : WWAN_CONFIG_2 */ + PAD_NC(GPP_D7, NONE), + /* D8 : WWAN_CONFIG_3 */ + PAD_NC(GPP_D8, NONE), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), + /* D10 : GPP_D10 ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D11 : GPP_D11 ==> NC */ + PAD_NC(GPP_D11, NONE), + /* D12 : GPP_D12 */ + PAD_NC(GPP_D12, NONE), + /* D13 : ISH_UART_RX */ + PAD_NC(GPP_D13, NONE), + /* D14 : ISH_UART_TX */ + PAD_NC(GPP_D14, NONE), + /* D15 : TOUCHSCREEN_RST_L */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* D16 : USI_INT */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE), + /* D17 : PCH_HP_SDW_CLK */ + PAD_NC(GPP_D17, NONE), + /* D18 : PCH_HP_SDW_DAT */ + PAD_NC(GPP_D18, NONE), + /* D19 : DMIC_CLK_0_SNDW4_CLK */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20 : DMIC_DATA_0_SNDW4_DATA */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21 : GPP_D21 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* D22 : GPP_D22 ==> NC */ + PAD_NC(GPP_D22, NONE), + /* D23 : SPP_MCLK */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* E0 : GPP_E0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E2 : GPP_E2 ==> NC */ + PAD_NC(GPP_E2, NONE), + /* E3 : GPP_E3 ==> NC */ + PAD_NC(GPP_E3, NONE), + /* E4 : M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* E6 : M2_SSD_RST_L */ + PAD_NC(GPP_E6, NONE), + /* E7 : GPP_E7 ==> NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> NC */ + PAD_NC(GPP_E8, NONE), + /* E9 : GPP_E9 ==> NC */ + PAD_NC(GPP_E9, NONE), + /* E10 : GPP_E10 ==> NC */ + PAD_NC(GPP_E10, NONE), + /* E11 : USB_C_OC_OD USB_OC2 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : USB_A_OC_OD USB_OC3 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14 : DDI2_HPD_ODL */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : DDPD_HPD2 => NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : DDPE_HPD2 => NC */ + PAD_NC(GPP_E16, NONE), + /* E17 : EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18 : DDPB_CTRLCLK => NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_CFG_GPI(GPP_E19, NONE, DEEP), + /* E20 : DDPC_CTRLCLK => NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_CFG_GPI(GPP_E21, NONE, DEEP), + /* E22 : DDPD_CTRLCLK => NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : GPP_E23_STRAP */ + PAD_NC(GPP_E23, NONE), + + /* F0 : GPIO_WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : WWAN_RESET_1V8_ODL */ + PAD_CFG_GPO(GPP_F1, 1, DEEP), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F3 : GPP_F3 ==> NC */ + PAD_NC(GPP_F3, NONE), + /* F4 : CNV_BRI_DT */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + /* F6 : CNV_RGI_DT */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* F8 : UART_WWANTX_WLANRX_COEX1 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* F9 : UART_WWANRX_WLANTX_COEX2 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* F10 : GPP_F10 ==> NC */ + PAD_NC(GPP_F10, NONE), + /* F11 : PCH_MEM_STRAP2 */ + PAD_CFG_GPI(GPP_F11, NONE, PLTRST), + /* F12 : GPP_F12 ==> NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : GPP_F13 ==> NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : GPP_F14 ==> NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : GPP_F15 ==> NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : GPP_F16 ==> NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : GPP_F17 ==> NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : GPP_F18 ==> NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : GPP_F19 ==> NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : PCH_MEM_STRAP0 */ + PAD_CFG_GPI(GPP_F20, NONE, PLTRST), + /* F21 : PCH_MEM_STRAP1 */ + PAD_CFG_GPI(GPP_F21, NONE, PLTRST), + /* F22 : PCH_MEM_STRAP3 */ + PAD_CFG_GPI(GPP_F22, NONE, PLTRST), + /* F23 : GPP_F23 ==> NC */ + PAD_NC(GPP_F23, NONE), + + /* G0 : SD_CMD */ + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), + /* G1 : SD_DATA0 */ + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), + /* G2 : SD_DATA1 */ + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), + /* G3 : SD_DATA2 */ + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), + /* G4 : SD_DATA3 */ + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), + /* G5 : SD_CD# */ + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), + /* G6 : SD_CLK */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), + /* G7 : SD_WP + * As per schematics SD host controller SD_WP pin is not connected to + * uSD card connector. In order to overcome gpio default state, ensures + * to configure gpio pin as NF1 with internal 20K pull down. + */ + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), + /* + * H0 : HP_INT_L + */ + PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH), + /* H1 : CNV_RF_RESET_L */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), + /* H2 : CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* H3 : GPP_H3 ==> NC */ + PAD_NC(GPP_H3, NONE), + /* H4 : PCH_I2C_PEN_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5 : PCH_I2C_PEN_SCL */ + PAD_NC(GPP_H5, NONE), + /* H6 : PCH_I2C_SAR0_MST_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_SAR0_MST_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : PCH_I2C_M2_AUDIO_SAR1_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* H9 : PCH_I2C_M2_AUDIO_SAR1_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : PCH_I2C_TRACKPAD_SDA */ + PAD_NC(GPP_H10, NONE), + /* H11 : PCH_I2C_TRACKPAD_SCL */ + PAD_NC(GPP_H11, NONE), + /* H12 : GPP_H12 ==> NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : GPP_H13 ==> NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : GPP_H14 ==> NC */ + PAD_NC(GPP_H14, NONE), + /* H15 : GPP_H15 ==> NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : GPP_H16 ==> NC */ + PAD_NC(GPP_H16, NONE), + /* H17 : TP1 */ + PAD_NC(GPP_H17, NONE), + /* H18 : CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : GPP_H19 ==> NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : TP41 */ + PAD_NC(GPP_H20, NONE), + /* H21 : XTAL_FREQ_SEL */ + PAD_NC(GPP_H21, NONE), + /* H22 : GPP_H22 ==> NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : GPP_H23_STRAP */ + PAD_NC(GPP_H23, NONE), + + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* SD card detect VGPIO */ + PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP), + + /* CNV_WCEN : Disable Wireless Charging */ + PAD_CFG_GPO(CNV_WCEN, 0, DEEP), +}; + +const struct pad_config *base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, + * turn off EN_PP3300_WWAN and FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */ +}; + +const struct pad_config *__weak variant_sleep_gpio_table( + u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} + +/* Weak implementation of overrides */ +const struct pad_config *__weak override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +/* Weak implementation of early gpio */ +const struct pad_config *__weak variant_early_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl new file mode 100644 index 00000000000..ef9b5694fa8 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 39 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 00000000000..4760adc3161 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 00000000000..6c549789960 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include + +#define GPIO_EC_IN_RW GPP_C22 + +#define GPIO_PCH_WP GPP_C20 + +/* EC wake pin is routed to GPD2/LAN_WAKE# on PCH */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC sync irq is GPP_C13_IRQ */ +#define EC_SYNC_IRQ GPP_C13_IRQ + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 00000000000..2f06a55e6fd --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef BASEBOARD_VARIANTS_H +#define BASEBOARD_VARIANTS_H + +#include +#include +#include +#include + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. The "base" GPIOs live in the "baseboard" variant, and + * the overrides live with the specific board (kohaku, kled, etc.). +*/ +const struct pad_config *base_gpio_table(size_t *num); +const struct pad_config *override_gpio_table(size_t *num); + +/* Return board specific memory configuration */ +void variant_memory_params(struct cnl_mb_cfg *bcfg); + +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + +/* Return variant specific gpio pads to be configured during sleep */ +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num); + +/* Return GPIO pads that need to be configured before ramstage */ +const struct pad_config *variant_early_gpio_table(size_t *num); + +/* Return ChromeOS gpio table and fill in number of entries. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); + +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); + +/* Perform variant specific initialization early on in ramstage. */ +void variant_ramstage_init(void); + +/* Perform variant specific mainboard initialization */ +void variant_mainboard_enable(struct device *dev); + +#endif /* BASEBOARD_VARIANTS_H */ diff --git a/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h b/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h new file mode 100644 index 00000000000..986cf61c05f --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/include/puff/ec.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + +#define MAINBOARD_EC_SMI_EVENTS 0 + +/* EC can wake from S5 with power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with power button */ +#define MAINBOARD_EC_S3_WAKE_EVENTS (MAINBOARD_EC_S5_WAKE_EVENTS) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable cros_ec_keyb device */ +#define EC_ENABLE_MKBP_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* + * Defines EC wake pin route. + * Note that GPE_EC_WAKE is defined, confusingly, as GPE_LAN_WAK which is GPD2/LAN_WAKE# + * on the PCH or as the line EC_PCH_WAKE_ODL on the schematic. + */ +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/google/puff/variants/baseboard/mainboard.c b/src/mainboard/google/puff/variants/baseboard/mainboard.c new file mode 100644 index 00000000000..c78ad5b154b --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/mainboard.c @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +/* + * For type-C chargers, set PL2 to 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ +#define SET_PSYSPL2(w) (97 * (w) / 100) +#define PUFF_U22_PL2 (35) +#define PUFF_U62_U42_PL2 (51) +#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) +#define PUFF_CORE_CPU_PSYSPL2 (90) +#define PUFF_MAX_TIME_WINDOW 6 +#define PUFF_MIN_DUTYCYCLE 4 + +/* + * mainboard_set_power_limits + * + * Set Pl2 and SysPl2 values based on detected charger. + * Values are defined below but we use U22 value for all SKUs for now. + * definitions: + * x = no value entered. Use default value in parenthesis. + * will set 0 to anything that shouldn't be set. + * n = max value of power adapter. + * +-------------+-----+---------+-----------+-------+ + * | sku_id | PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+---------+-----------+-------+ + * | i7 U42 | 51 | 90 | x(.85PL4) | x(82) | + * | i3 U22 | 35 | 65 | x(.85PL4) | x(51) | + * +-------------+-----+---------+-----------+-------+ + * For USB C charger: + * +-------------+-----------------+---------+---------+-------+ + * | Max Power(W)| PL2 | PsysPL2 | PsysPL3 | PL4 | + * +-------------+-----+-----------+---------+---------+-------+ + * | n | min(0.97n, PL2) | 0.97n | 0.97n | 0.97n | + * +-------------+-----+-----------+---------+---------+-------+ + */ + +/* + * Psys_pmax considerations + * + * Given the hardware design in puff, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 0.8v maps to system current 9.6A + * instead of real system power. The equation is shown below: + * PSYS = 0.8v = (0.01ohm x Iinput) x 50 (INA213, gain 50V/V) x 15k/(15k + 75k) + * Hence, Iinput (Amps) = 9.6A + * Since there is no voltage information from PSYS, different voltage input + * would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax sholud be 15v x 9.6A = 144W + * For Type-C 20V, the Psys_pmax should be 20v x 9.6A = 192W + * For a barral jack, the Psys_pmax should be 19v x 9.6A = 182.4W + */ +#define PSYS_IMAX 9600 +#define BJ_VOLTS_MV 19000 + +static void mainboard_set_power_limits(struct soc_power_limits_config *conf) +{ + enum usb_chg_type type; + u32 watts; + u16 volts_mv, current_ma; + u32 psyspl2 = PUFF_CELERON_PENTIUM_PSYSPL2; // default BJ value + u32 pl2 = PUFF_U22_PL2; // default PL2 for U22 + int rv = google_chromeec_get_usb_pd_power_info(&type, ¤t_ma, &volts_mv); + + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + u16 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + dev = pcidev_path_on_root(SA_DEVFN_IGD); + u16 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; + + /* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/ + conf->tdp_psyspl3 = 0; + conf->tdp_pl4 = 0; + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + /* set psyspl2 to 90% of adapter rating */ + psyspl2 = SET_PSYSPL2(watts); + + /* Limit PL2 if the adapter is with lower capability */ + if (mch_id == PCI_DID_INTEL_CML_ULT || + mch_id == PCI_DID_INTEL_CML_ULT_6_2) + pl2 = (psyspl2 > PUFF_U62_U42_PL2) ? PUFF_U62_U42_PL2 : psyspl2; + else + pl2 = (psyspl2 > PUFF_U22_PL2) ? PUFF_U22_PL2 : psyspl2; + + conf->tdp_psyspl3 = psyspl2; + /* set max possible time window */ + conf->tdp_psyspl3_time = PUFF_MAX_TIME_WINDOW; + /* set minimum duty cycle */ + conf->tdp_psyspl3_dutycycle = PUFF_MIN_DUTYCYCLE; + /* No data about an arbitrary Type-C adapter, set pl4 conservatively. */ + conf->tdp_pl4 = psyspl2; + } else { + /* + * Input type is barrel jack, from the SKU matrix: + * 1. i3/i5/i7 SKUs use 90W BJ + * 2. Celeron and Pentium use 65W BJ (default) + */ + volts_mv = BJ_VOLTS_MV; + /* Use IGD ID to check if CPU is Core SKUs */ + if (igd_id != PCI_DID_INTEL_CML_GT1_ULT_1 && + igd_id != PCI_DID_INTEL_CML_GT2_ULT_5) { + psyspl2 = PUFF_CORE_CPU_PSYSPL2; + if (mch_id == PCI_DID_INTEL_CML_ULT || + mch_id == PCI_DID_INTEL_CML_ULT_6_2) + pl2 = PUFF_U62_U42_PL2; + } + } + /* voltage unit is milliVolts and current is in milliAmps */ + conf->psys_pmax = (u16)(((u32)PSYS_IMAX * volts_mv) / 1000000); + + conf->tdp_pl2_override = pl2; + conf->tdp_psyspl2 = psyspl2; +} + +void variant_ramstage_init(void) +{ + static const long display_timeout_ms = 3000; + struct soc_power_limits_config *soc_config; + config_t *conf = config_of_soc(); + + /* This is reconfigured back to whatever FSP-S expects by gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } + /* Psys_pmax needs to be setup before FSP-S */ + soc_config = &conf->power_limits_config; + mainboard_set_power_limits(soc_config); +} diff --git a/src/mainboard/google/puff/variants/baseboard/memory.c b/src/mainboard/google/puff/variants/baseboard/memory.c new file mode 100644 index 00000000000..5df73333a69 --- /dev/null +++ b/src/mainboard/google/puff/variants/baseboard/memory.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* Baseboard uses 121, 81 and 100 rcomp resistors */ + .rcomp_resistor = {121, 81, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {100, 40, 20, 20, 26}, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} diff --git a/src/mainboard/google/hatch/variants/dooly/Makefile.inc b/src/mainboard/google/puff/variants/dooly/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/Makefile.inc rename to src/mainboard/google/puff/variants/dooly/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/dooly/data.vbt b/src/mainboard/google/puff/variants/dooly/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/data.vbt rename to src/mainboard/google/puff/variants/dooly/data.vbt diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/puff/variants/dooly/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/gpio.c rename to src/mainboard/google/puff/variants/dooly/gpio.c diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/ec.h b/src/mainboard/google/puff/variants/dooly/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/include/variant/ec.h rename to src/mainboard/google/puff/variants/dooly/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h b/src/mainboard/google/puff/variants/dooly/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/include/variant/gpio.h rename to src/mainboard/google/puff/variants/dooly/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/puff/variants/dooly/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/dooly/overridetree.cb rename to src/mainboard/google/puff/variants/dooly/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/duffy/Makefile.inc b/src/mainboard/google/puff/variants/duffy/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/Makefile.inc rename to src/mainboard/google/puff/variants/duffy/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/duffy/data.vbt b/src/mainboard/google/puff/variants/duffy/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/data.vbt rename to src/mainboard/google/puff/variants/duffy/data.vbt diff --git a/src/mainboard/google/hatch/variants/duffy/gpio.c b/src/mainboard/google/puff/variants/duffy/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/gpio.c rename to src/mainboard/google/puff/variants/duffy/gpio.c diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/ec.h b/src/mainboard/google/puff/variants/duffy/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/include/variant/ec.h rename to src/mainboard/google/puff/variants/duffy/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h b/src/mainboard/google/puff/variants/duffy/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/include/variant/gpio.h rename to src/mainboard/google/puff/variants/duffy/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/puff/variants/duffy/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/duffy/overridetree.cb rename to src/mainboard/google/puff/variants/duffy/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/faffy/Makefile.inc b/src/mainboard/google/puff/variants/faffy/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/Makefile.inc rename to src/mainboard/google/puff/variants/faffy/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/faffy/data.vbt b/src/mainboard/google/puff/variants/faffy/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/data.vbt rename to src/mainboard/google/puff/variants/faffy/data.vbt diff --git a/src/mainboard/google/hatch/variants/faffy/gpio.c b/src/mainboard/google/puff/variants/faffy/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/gpio.c rename to src/mainboard/google/puff/variants/faffy/gpio.c diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/ec.h b/src/mainboard/google/puff/variants/faffy/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/include/variant/ec.h rename to src/mainboard/google/puff/variants/faffy/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/faffy/include/variant/gpio.h b/src/mainboard/google/puff/variants/faffy/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/include/variant/gpio.h rename to src/mainboard/google/puff/variants/faffy/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/faffy/overridetree.cb b/src/mainboard/google/puff/variants/faffy/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/faffy/overridetree.cb rename to src/mainboard/google/puff/variants/faffy/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/genesis/Makefile.inc b/src/mainboard/google/puff/variants/genesis/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/genesis/Makefile.inc rename to src/mainboard/google/puff/variants/genesis/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/puff/variants/genesis/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/genesis/gpio.c rename to src/mainboard/google/puff/variants/genesis/gpio.c diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/ec.h b/src/mainboard/google/puff/variants/genesis/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/genesis/include/variant/ec.h rename to src/mainboard/google/puff/variants/genesis/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h b/src/mainboard/google/puff/variants/genesis/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/genesis/include/variant/gpio.h rename to src/mainboard/google/puff/variants/genesis/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/puff/variants/genesis/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/genesis/overridetree.cb rename to src/mainboard/google/puff/variants/genesis/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/kaisa/Makefile.inc b/src/mainboard/google/puff/variants/kaisa/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/Makefile.inc rename to src/mainboard/google/puff/variants/kaisa/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/kaisa/data.vbt b/src/mainboard/google/puff/variants/kaisa/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/data.vbt rename to src/mainboard/google/puff/variants/kaisa/data.vbt diff --git a/src/mainboard/google/hatch/variants/kaisa/gpio.c b/src/mainboard/google/puff/variants/kaisa/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/gpio.c rename to src/mainboard/google/puff/variants/kaisa/gpio.c diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h b/src/mainboard/google/puff/variants/kaisa/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/include/variant/ec.h rename to src/mainboard/google/puff/variants/kaisa/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h b/src/mainboard/google/puff/variants/kaisa/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/include/variant/gpio.h rename to src/mainboard/google/puff/variants/kaisa/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/puff/variants/kaisa/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/kaisa/overridetree.cb rename to src/mainboard/google/puff/variants/kaisa/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/moonbuggy/Makefile.inc b/src/mainboard/google/puff/variants/moonbuggy/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/moonbuggy/Makefile.inc rename to src/mainboard/google/puff/variants/moonbuggy/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/puff/variants/moonbuggy/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/moonbuggy/gpio.c rename to src/mainboard/google/puff/variants/moonbuggy/gpio.c diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/ec.h b/src/mainboard/google/puff/variants/moonbuggy/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/moonbuggy/include/variant/ec.h rename to src/mainboard/google/puff/variants/moonbuggy/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h b/src/mainboard/google/puff/variants/moonbuggy/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h rename to src/mainboard/google/puff/variants/moonbuggy/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/puff/variants/moonbuggy/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb rename to src/mainboard/google/puff/variants/moonbuggy/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/puff/variants/mushu/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/Makefile.inc rename to src/mainboard/google/puff/variants/mushu/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/mushu/data.vbt b/src/mainboard/google/puff/variants/mushu/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/data.vbt rename to src/mainboard/google/puff/variants/mushu/data.vbt diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/puff/variants/mushu/gpio.c similarity index 97% rename from src/mainboard/google/hatch/variants/mushu/gpio.c rename to src/mainboard/google/puff/variants/mushu/gpio.c index fd56f33f89f..e9fd20590d9 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/puff/variants/mushu/gpio.c @@ -39,7 +39,7 @@ const struct pad_config *override_gpio_table(size_t *num) /* * GPIOs configured before ramstage - * Note: the Hatch platform's romstage will configure + * Note: the Puff platform's romstage will configure * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins * as inputs before it reads them, so they are not * needed in this table. diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/puff/variants/mushu/include/variant/acpi/dptf.asl similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl rename to src/mainboard/google/puff/variants/mushu/include/variant/acpi/dptf.asl diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/puff/variants/mushu/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/include/variant/ec.h rename to src/mainboard/google/puff/variants/mushu/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/puff/variants/mushu/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h rename to src/mainboard/google/puff/variants/mushu/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/puff/variants/mushu/overridetree.cb similarity index 98% rename from src/mainboard/google/hatch/variants/mushu/overridetree.cb rename to src/mainboard/google/puff/variants/mushu/overridetree.cb index 0edea304419..427121f6864 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/puff/variants/mushu/overridetree.cb @@ -95,7 +95,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)" register "wake" = "GPE0_DW0_21" device i2c 15 on end end @@ -104,7 +104,7 @@ chip soc/intel/cannonlake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "100" diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/puff/variants/mushu/ramstage.c similarity index 100% rename from src/mainboard/google/hatch/variants/mushu/ramstage.c rename to src/mainboard/google/puff/variants/mushu/ramstage.c diff --git a/src/mainboard/google/hatch/variants/noibat/Makefile.inc b/src/mainboard/google/puff/variants/noibat/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/Makefile.inc rename to src/mainboard/google/puff/variants/noibat/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/noibat/data.vbt b/src/mainboard/google/puff/variants/noibat/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/data.vbt rename to src/mainboard/google/puff/variants/noibat/data.vbt diff --git a/src/mainboard/google/hatch/variants/noibat/gpio.c b/src/mainboard/google/puff/variants/noibat/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/gpio.c rename to src/mainboard/google/puff/variants/noibat/gpio.c diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/ec.h b/src/mainboard/google/puff/variants/noibat/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/include/variant/ec.h rename to src/mainboard/google/puff/variants/noibat/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h b/src/mainboard/google/puff/variants/noibat/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/include/variant/gpio.h rename to src/mainboard/google/puff/variants/noibat/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/noibat/overridetree.cb b/src/mainboard/google/puff/variants/noibat/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/noibat/overridetree.cb rename to src/mainboard/google/puff/variants/noibat/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/puff/Makefile.inc b/src/mainboard/google/puff/variants/puff/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/puff/Makefile.inc rename to src/mainboard/google/puff/variants/puff/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/puff/data.vbt b/src/mainboard/google/puff/variants/puff/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/puff/data.vbt rename to src/mainboard/google/puff/variants/puff/data.vbt diff --git a/src/mainboard/google/hatch/variants/puff/gpio.c b/src/mainboard/google/puff/variants/puff/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/puff/gpio.c rename to src/mainboard/google/puff/variants/puff/gpio.c diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/ec.h b/src/mainboard/google/puff/variants/puff/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/puff/include/variant/ec.h rename to src/mainboard/google/puff/variants/puff/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/puff/include/variant/gpio.h b/src/mainboard/google/puff/variants/puff/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/puff/include/variant/gpio.h rename to src/mainboard/google/puff/variants/puff/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/puff/variants/puff/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/puff/overridetree.cb rename to src/mainboard/google/puff/variants/puff/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/scout/Makefile.inc b/src/mainboard/google/puff/variants/scout/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/scout/Makefile.inc rename to src/mainboard/google/puff/variants/scout/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/puff/variants/scout/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/scout/gpio.c rename to src/mainboard/google/puff/variants/scout/gpio.c diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/ec.h b/src/mainboard/google/puff/variants/scout/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/scout/include/variant/ec.h rename to src/mainboard/google/puff/variants/scout/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/scout/include/variant/gpio.h b/src/mainboard/google/puff/variants/scout/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/scout/include/variant/gpio.h rename to src/mainboard/google/puff/variants/scout/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/puff/variants/scout/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/scout/overridetree.cb rename to src/mainboard/google/puff/variants/scout/overridetree.cb diff --git a/src/mainboard/google/hatch/variants/wyvern/Makefile.inc b/src/mainboard/google/puff/variants/wyvern/Makefile.inc similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/Makefile.inc rename to src/mainboard/google/puff/variants/wyvern/Makefile.inc diff --git a/src/mainboard/google/hatch/variants/wyvern/data.vbt b/src/mainboard/google/puff/variants/wyvern/data.vbt similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/data.vbt rename to src/mainboard/google/puff/variants/wyvern/data.vbt diff --git a/src/mainboard/google/hatch/variants/wyvern/gpio.c b/src/mainboard/google/puff/variants/wyvern/gpio.c similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/gpio.c rename to src/mainboard/google/puff/variants/wyvern/gpio.c diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/ec.h b/src/mainboard/google/puff/variants/wyvern/include/variant/ec.h similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/include/variant/ec.h rename to src/mainboard/google/puff/variants/wyvern/include/variant/ec.h diff --git a/src/mainboard/google/hatch/variants/wyvern/include/variant/gpio.h b/src/mainboard/google/puff/variants/wyvern/include/variant/gpio.h similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/include/variant/gpio.h rename to src/mainboard/google/puff/variants/wyvern/include/variant/gpio.h diff --git a/src/mainboard/google/hatch/variants/wyvern/overridetree.cb b/src/mainboard/google/puff/variants/wyvern/overridetree.cb similarity index 100% rename from src/mainboard/google/hatch/variants/wyvern/overridetree.cb rename to src/mainboard/google/puff/variants/wyvern/overridetree.cb diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index f8af00f6b15..87a783b85f4 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -155,4 +155,8 @@ config SEABIOS_HARDWARE_IRQ bool default n +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_RAMBI diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 1d0c71eeabe..a6bbb1be018 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -89,6 +89,11 @@ Scope (\_SB.PCI0.I2C2) { BOARD_CODEC_IRQ } + + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000E } + + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000F } + }) Method (_STA) @@ -106,14 +111,24 @@ Scope (\_SB.PCI0.LPEA) { Name (GBUF, ResourceTemplate () { + /* Jack Detect (index 0) */ - GpioInt (Level, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 14 } + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000E } /* Mic Detect (index 1) */ - GpioInt (Level, ActiveHigh, Exclusive, PullNone,, - "\\_SB.GPSC") { 15 } + GpioIo (Exclusive, PullNone, 0, 0, , "\\_SB.GPSC", 0, ResourceConsumer, ,){ 0x000F } + + /* SST Wants This */ + GpioInt (Edge, ActiveHigh, Exclusive, PullNone, 0x0000, + "\\_SB.GPSS", 0x00, ResourceConsumer, ,) + { + 0x001C // Pin list + } }) + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } } #include diff --git a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl index 018905c9cfa..590fb8071e1 100644 --- a/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl +++ b/src/mainboard/google/rambi/acpi/touchscreen_atmel.asl @@ -7,7 +7,6 @@ Scope (\_SB.PCI0.I2C6) Device (ATSA) { Name (_HID, "ATML0001") - Name (_CID, EisaId ("PNP0C0E")) Name (_DDN, "Atmel Touchscreen") Name (_UID, 5) Name (ISTP, 0) /* TouchScreen */ diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 63a1fc7885e..9cf8c045d3b 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -27,9 +27,6 @@ DefinitionBlock( #include #include } - - /* Dynamic Platform Thermal Framework */ - #include "acpi/dptf.asl" } #include diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 358a92f9679..5d73df939a0 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -66,6 +66,7 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake pin in GPE block. */ enable_gpe(WAKE_GPIO_EN); break; + case ACPI_S4: case ACPI_S5: if (gnvs->s5u0 == 0) google_chromeec_set_usb_charge_mode( diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 47d111431dd..7bb20753ef2 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -104,4 +104,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 9aadc9ed528..acb11dadd8e 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -128,7 +128,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -188,8 +188,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -202,9 +202,9 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 4 @@ -213,6 +213,7 @@ chip soc/intel/apollolake register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0x9 on end end diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index aeb8edf9992..b0fc2d3286f 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -370,6 +370,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ }; const struct pad_config * __weak diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index e8f8cc334ae..ff146702085 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -128,7 +128,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -188,8 +188,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -200,8 +200,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -214,9 +214,9 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid @@ -224,7 +224,7 @@ chip soc/intel/apollolake register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "generic.wake" = "GPE0_DW1_15" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end @@ -241,8 +241,8 @@ chip soc/intel/apollolake device pci 17.2 off end # - I2C 6 device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 - device pci 18.1 on end # - UART 1 - device pci 18.2 on end # - UART 2 + device pci 18.1 off end # - UART 1 + device pci 18.2 off end # - UART 2 device pci 18.3 off end # - UART 3 device pci 19.0 on end # - SPI 0 device pci 19.1 off end # - SPI 1 diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index 1a814aa7a38..d54a6dec9d2 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -371,6 +371,9 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */ PAD_CFG_GPI(GPIO_41, NONE, DEEP), /* LPSS_UART0_CTS - EC_IN_RW */ + + /* Touch enable */ + PAD_CFG_GPO(GPIO_152, 1, DEEP), /* ISH_GPIO_6 */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index af459bebefc..47a1499e672 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -137,7 +137,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -198,7 +198,7 @@ chip soc/intel/apollolake register "generic.hid" = ""WCOMNTN2"" register "generic.desc" = ""WCOM Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "20" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -211,8 +211,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -225,9 +225,9 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 4 diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 91555ad6c8d..ffa1835bd8d 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -124,7 +124,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -184,8 +184,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -198,9 +198,9 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 4 diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index d4e9705fc31..2f12a4786cc 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -133,7 +133,7 @@ chip soc/intel/apollolake device pci 02.0 on # - Gen register "gfx" = "GMA_DEFAULT_PANEL(0)" end - device pci 03.0 on end # - Iunit + device pci 03.0 off end # - Iunit device pci 0d.0 on end # - P2SB device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI @@ -193,8 +193,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -205,8 +205,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""MLFS0000"" register "desc" = ""Melfas Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" # Melfas TS IC doesn't have reset pin design, current FW also not # declare "ce-gpios" in ACPI _DSD to let Melfas TS driver to know # "enable gpio#152 (VTSP) but because of kernel bug & Melfas TS driver @@ -226,8 +226,8 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" + register "detect" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "reset_delay_ms" = "1" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -239,7 +239,7 @@ chip soc/intel/apollolake register "generic.hid" = ""WDHT0002"" register "generic.desc" = ""WDT Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "130" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -253,7 +253,7 @@ chip soc/intel/apollolake register "generic.hid" = ""GTCH7503"" register "generic.desc" = ""G2TOUCH Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" - register "generic.probed" = "1" + register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" register "generic.reset_delay_ms" = "50" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" @@ -268,9 +268,9 @@ chip soc/intel/apollolake chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" register "wake" = "GPE0_DW1_15" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end end # - I2C 4 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 37c72ad663d..cdf6da7a486 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -101,4 +101,7 @@ config VBOOT config INTEL_GMA_VBT_FILE default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" if !CHROMEOS + endif # BOARD_GOOGLE_BASEBOARD_SARIEN diff --git a/src/mainboard/google/sarien/default.fmd b/src/mainboard/google/sarien/default.fmd new file mode 100644 index 00000000000..4f2bedf9c24 --- /dev/null +++ b/src/mainboard/google/sarien/default.fmd @@ -0,0 +1,11 @@ +FLASH@0xfe000000 0x2000000 { + SI_BIOS@0x400000 { + MEMORY_MAPPED@0xc00000 { /* 16MiB total */ + RW_MRC_CACHE 0x10000 + SMMSTORE 0x40000 + RO_VPD 0x4000 + FMAP 0x300 + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 437797ce03c..7440185e0d0 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -72,4 +72,8 @@ config MAINBOARD_SMBIOS_MANUFACTURER config ENABLE_DDR_2X_REFRESH default y if BOARD_GOOGLE_FALCO +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_SLIPPY diff --git a/src/mainboard/google/slippy/acpi/superio.asl b/src/mainboard/google/slippy/acpi/superio.asl index 587bb8bf0ff..4a1456bb0ed 100644 --- a/src/mainboard/google/slippy/acpi/superio.asl +++ b/src/mainboard/google/slippy/acpi/superio.asl @@ -6,7 +6,6 @@ #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 /* ACPI code for EC SuperIO functions */ #include diff --git a/src/mainboard/google/slippy/variants/peppy/gpio.c b/src/mainboard/google/slippy/variants/peppy/gpio.c index 2ed92cdb81c..e50e6cd56ad 100644 --- a/src/mainboard/google/slippy/variants/peppy/gpio.c +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -22,7 +22,7 @@ const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { LP_GPIO_UNUSED, /* 16: UNUSED */ LP_GPIO_UNUSED, /* 17: UNUSED */ LP_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - LP_GPIO_UNUSED, /* 19: UNUSED */ + LP_GPIO_NATIVE, /* 19: PCIE_CLKREQ_LTE# */ LP_GPIO_UNUSED, /* 20: UNUSED */ LP_GPIO_UNUSED, /* 21: UNUSED */ LP_GPIO_UNUSED, /* 22: UNUSED */ diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index e79309059ba..69f027db053 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -60,7 +60,7 @@ Scope (\_SB.PCI0.I2C0) AddressingMode7Bit, // AddressingMode "\\_SB.PCI0.I2C0" // ResourceSource ) - Interrupt (ResourceConsumer, Edge, ActiveLow, Shared) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared) { BOARD_TRACKPAD_IRQ } @@ -142,4 +142,33 @@ Scope (\_SB.PCI0.I2C1) } } } + + Device (ALSI) + { + Name (_HID, "ISL29018") + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 6) + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_LIGHTSENSOR_IRQ + } + }) + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } } diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl index 768a690e94d..80cb5c8d7c6 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl @@ -85,6 +85,23 @@ Scope (\_SB.PCI0.XHCI.HUB7.PRT5) Return (GPLD (One)) } } +Scope (\_SB.PCI0.XHCI.HUB7.PRT6) +{ + // SIM USB 2.0 Slot + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} Scope (\_SB.PCI0.XHCI.HUB7.PRT7) { // SD Card diff --git a/src/mainboard/google/slippy/variants/peppy/overridetree.cb b/src/mainboard/google/slippy/variants/peppy/overridetree.cb index bb30f763f3a..75a70ee5cdb 100644 --- a/src/mainboard/google/slippy/variants/peppy/overridetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/overridetree.cb @@ -23,6 +23,8 @@ chip northbridge/intel/haswell # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" end + + device pci 1c.1 on end # PCIe Port #2 end end end diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 32fdd97e947..2347690baba 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -43,8 +43,8 @@ const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { USB_PORT_MINI_PCIE }, { 0x0040, 1, 2, /* P4: Port B, CN6 */ USB_PORT_BACK_PANEL }, - { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */ - USB_PORT_SKIP }, + { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: SIM */ + USB_PORT_INTERNAL }, { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ USB_PORT_FLEX }, { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 926a0ca4b16..068c220ffea 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -55,6 +55,7 @@ config BOARD_GOOGLE_LINDAR select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_I2C_RT1011 select INTEL_CAR_NEM + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_MALEFOR select BOARD_GOOGLE_BASEBOARD_VOLTEER @@ -221,4 +222,8 @@ config VARIANT_HAS_MIPI_CAMERA bool default n +config ACPI_SUBSYSTEM_ID + string + default "1AE0006C" + endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index 4193d3d1e7f..eeaf61379fe 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -28,6 +28,7 @@ DefinitionBlock( #include #include #include + #include #if CONFIG(VARIANT_HAS_MIPI_CAMERA) #include #endif diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 9f3987e6721..67e6712ac9f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -357,7 +357,9 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable" = "1" device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end device ref dptf on # Default DPTF Policy for all Volteer boards if not overridden chip drivers/intel/dptf diff --git a/src/mainboard/google/volteer/variants/lindar/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/Makefile.inc index 22bcbd7727b..82518a503e6 100644 --- a/src/mainboard/google/volteer/variants/lindar/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/Makefile.inc @@ -7,3 +7,5 @@ romstage-y += memory.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c + +$(call add_vbt_to_cbfs, vbt-oled.bin, data-oled.vbt) diff --git a/src/mainboard/google/volteer/variants/lindar/data-oled.vbt b/src/mainboard/google/volteer/variants/lindar/data-oled.vbt new file mode 100644 index 00000000000..dfeea359f9c Binary files /dev/null and b/src/mainboard/google/volteer/variants/lindar/data-oled.vbt differ diff --git a/src/mainboard/google/volteer/variants/lindar/data.vbt b/src/mainboard/google/volteer/variants/lindar/data.vbt new file mode 100644 index 00000000000..2b48ae09786 Binary files /dev/null and b/src/mainboard/google/volteer/variants/lindar/data.vbt differ diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 68eb6ea5887..382c6b7c16f 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -249,7 +249,7 @@ chip soc/amd/picasso device ref iommu on end device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic - register "wake" = "GEVENT_8" + #register "wake" = "GEVENT_8" device pci 00.0 on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 4bb42dea1c9..e2834aaab2e 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -247,7 +247,7 @@ chip soc/amd/picasso device ref iommu on end device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic - register "wake" = "GEVENT_8" + #register "wake" = "GEVENT_8" device pci 00.0 on end end end diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h index d2ec79bef9f..5a7e99e35b2 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/ec.h @@ -52,7 +52,6 @@ /* Enable LID switch */ #define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index c2f0baf24b0..6a099d8e30a 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -47,7 +47,7 @@ chip soc/amd/picasso register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" # 32ms: Rise time of the reset line # 20ms: Firmware ready time @@ -60,7 +60,7 @@ chip soc/amd/picasso register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" register "reset_delay_ms" = "20" register "has_power_resource" = "1" @@ -97,15 +97,16 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "wake" = "GEVENT_22" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index c5507e90e3e..5e97e6e9f6c 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -104,15 +104,16 @@ chip soc/amd/picasso register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "wake" = "GEVENT_22" - register "probed" = "1" + register "detect" = "1" device i2c 15 on end end chip drivers/i2c/hid - register "generic.hid" = ""PNP0C50"" + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0000"" register "generic.desc" = ""Synaptics Touchpad"" register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" register "generic.wake" = "GEVENT_22" - register "generic.probed" = "1" + register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c index 1256c1721b0..ff6e53f862f 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c @@ -5,7 +5,7 @@ const u32 cim_verb_data[] = { 0x10ec0256, /* Codec Vendor/Device ID: Realtek ALC256 */ 0x10ec0256, /* Subsystem ID */ - 16, /* Number of entries */ + 18, /* Number of entries */ AZALIA_RESET(0x1), @@ -14,12 +14,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x411111f0), /* NC */ AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Internal speakers */ AZALIA_PIN_CFG(0, 0x18, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x19, 0x04a11130), /* Jack analog mic */ + AZALIA_PIN_CFG(0, 0x19, 0x04a11120), /* Jack analog mic */ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */ AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x21, 0x04211120), /* Jack analog out */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), /* Jack analog out */ /* Hidden SW reset */ 0x0205001a, @@ -45,6 +45,18 @@ const u32 cim_verb_data[] = { 0x02050007, 0x02040200, + /* CTIA jack type */ + 0x02050045, + 0x0204d489, + 0x0205001b, + 0x02040e6b, + + /* Jack reset, autodetect */ + 0x0205004a, + 0x02048000, + 0x0205004a, + 0x0204000e, + 0x8086280b, /* Codec Vendor/Device ID: Intel CometPoint HDMI */ 0x80860101, /* Subsystem ID */ 4, /* Number of entries */ diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index d9c9d614a73..fcbd148fc87 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -23,9 +23,9 @@ Scope (\_SB) { Device (TPAD) { - // Report as a Sleep Button device so - // Linux will automatically enable for wake - Name(_HID, EisaId("PNP0C0E")) + Name(_HID, "CYSM0000") + Name(_UID, 1) + Name(_REV, 2) // Trackpad Wake is GPIO11 Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 }) @@ -33,7 +33,7 @@ Scope (\_SB) { Name(_CRS, ResourceTemplate() { // PIRQF -> GSI21 - Interrupt (ResourceConsumer, Edge, ActiveLow) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, ) { BOARD_TRACKPAD_IRQ } diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index cf44aba7677..030137b5f4a 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -102,11 +102,7 @@ Scope (\_TZ) } Method (_AC4) { - If (\FLVL <= 4) { - Return (CTOK (\F4OF)) - } Else { - Return (CTOK (\F4ON)) - } + Return (CTOK (0)) } Name (_AL0, Package () { FAN0 }) diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 6912ca1a76e..bf297d7cf3b 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -19,8 +19,6 @@ void mainboard_fill_gnvs(struct global_nvs *gnvs) gnvs->s5u0 = 1; gnvs->s5u1 = 1; - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; gnvs->f4pw = FAN4_PWM; gnvs->f3of = FAN3_THRESHOLD_OFF; diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index 90ed429ec8c..b8887ff6861 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -79,6 +79,9 @@ chip northbridge/intel/sandybridge register "peci_tmpin" = "3" # Enable FAN3 register "fan3_enable" = "1" + register "fan2_enable" = "1" + # Default FAN3 speed + register "fan3_speed" = "0x90" device pnp 2e.0 off end # FDC device pnp 2e.1 on # Serial Port 1 diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h index fa8a08ed75d..41327e19bcf 100644 --- a/src/mainboard/samsung/stumpy/thermal.h +++ b/src/mainboard/samsung/stumpy/thermal.h @@ -3,25 +3,23 @@ #ifndef STUMPY_THERMAL_H #define STUMPY_THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 +/* Fan is at default speed */ +#define FAN4_PWM 0x90 /* Fan is at LOW speed */ #define FAN3_THRESHOLD_OFF 48 #define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 +#define FAN3_PWM 0xA0 /* Fan is at MEDIUM speed */ #define FAN2_THRESHOLD_OFF 52 #define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 +#define FAN2_PWM 0xB0 /* Fan is at HIGH speed */ #define FAN1_THRESHOLD_OFF 60 #define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 +#define FAN1_PWM 0xC0 /* Fan is at FULL speed */ #define FAN0_THRESHOLD_OFF 66 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index e1b8b730971..48a75ba15c2 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -400,20 +400,6 @@ static void gma_pm_init_post_vbios(struct device *dev) gtt_write(0x0a188, 0x00000001); } -/* Enable SCI to ACPI _GPE._L06 */ -static void gma_enable_swsci(void) -{ - u16 reg16; - - /* Clear DMISCI status */ - reg16 = inw(get_pmbase() + TCO1_STS); - reg16 &= DMISCI_STS; - outw(get_pmbase() + TCO1_STS, reg16); - - /* Clear and enable ACPI TCO SCI */ - enable_tco_sci(); -} - static void gma_func0_init(struct device *dev) { int lightup_ok = 0; @@ -450,8 +436,6 @@ static void gma_func0_init(struct device *dev) printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); gma_pm_init_post_vbios(dev); - - gma_enable_swsci(); } static void gma_generate_ssdt(const struct device *dev) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index cf1d61ce9fe..980a31babf4 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -49,3 +49,12 @@ Device (PDRC) /* Integrated graphics 0:2.0 */ #include + +Device (DPTF) +{ + Name (_ADR, 0x00040000) // _ADR: Address + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } +} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 7acc5af845b..7f30a35c51e 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -87,7 +87,7 @@ static void sandybridge_setup_graphics(void) printk(BIOS_DEBUG, "Initializing Graphics...\n"); /* Fall back to 32 MiB for IGD memory by setting GGC[7:3] = 1 */ - gfxsize = get_uint_option("gfx_uma_size", 0); + gfxsize = get_uint_option("gfx_uma_size", 2); reg16 = pci_read_config16(HOST_BRIDGE, GGC); reg16 &= ~0x00f8; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index d1b92639803..94be6985311 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -562,25 +562,6 @@ static void gma_pm_init_post_vbios(struct device *dev) } } -/* Enable SCI to ACPI _GPE._L06 */ -static void gma_enable_swsci(void) -{ - u16 reg16; - - /* Clear DMISCI status */ - reg16 = inw(DEFAULT_PMBASE + TCO1_STS); - reg16 &= DMISCI_STS; - outw(DEFAULT_PMBASE + TCO1_STS, reg16); - - /* Clear ACPI TCO status */ - outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); - - /* Enable ACPI TCO SCIs */ - reg16 = inw(DEFAULT_PMBASE + GPE0_EN); - reg16 |= TCOSCI_EN; - outw(DEFAULT_PMBASE + GPE0_EN, reg16); -} - static void gma_func0_init(struct device *dev) { intel_gma_init_igd_opregion(); @@ -615,8 +596,6 @@ static void gma_func0_init(struct device *dev) gfx_set_init_done(1); } } - - gma_enable_swsci(); } static void gma_generate_ssdt(const struct device *device) diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e4b78e5e836..a9f0de03ea1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -194,7 +194,7 @@ OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), -- OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -ifeq ($(CONFIG_VBOOT),) +ifneq ($(CONFIG_VBOOT_SLOTS_RW_A),y) OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) endif diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl index f7cf04f3133..eb800c3c0f2 100644 --- a/src/soc/intel/apollolake/acpi/pcie.asl +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -7,7 +7,7 @@ Device (RP01) Name (_ADR, 0x00140000) Name (_DDN, "PCIe-B 0") - #include "pcie_port.asl" +// #include "pcie_port.asl" } Device (RP03) @@ -15,5 +15,5 @@ Device (RP03) Name (_ADR, 0x00130000) Name (_DDN, "PCIe-A 0") - #include "pcie_port.asl" +// #include "pcie_port.asl" } diff --git a/src/soc/intel/baytrail/acpi/gpio.asl b/src/soc/intel/baytrail/acpi/gpio.asl index 4e48cc6d975..78997d050ae 100644 --- a/src/soc/intel/baytrail/acpi/gpio.asl +++ b/src/soc/intel/baytrail/acpi/gpio.asl @@ -26,7 +26,12 @@ Device (GPSC) Return (^RBUF) } - Method (_STA) + Method (_HRV) + { + Return (0x06) + } + + Method (_STA) { Return (0xF) } @@ -55,6 +60,11 @@ Device (GPNC) Return (^RBUF) } + Method (_HRV) + { + Return (0x06) + } + Method (_STA) { Return (0xF) @@ -84,6 +94,11 @@ Device (GPSS) Return (^RBUF) } + Method (_HRV) + { + Return (0x06) + } + Method (_STA) { Return (0xF) diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl index 6ba615d438f..b7a4766a13a 100644 --- a/src/soc/intel/baytrail/acpi/lpss.asl +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -94,6 +94,8 @@ Device (I2C1) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S1EN, 1)) { @@ -153,6 +155,8 @@ Device (I2C2) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S2EN, 1)) { @@ -205,6 +209,8 @@ Device (I2C3) FixedDMA (0x15, 0x5, Width32Bit, ) }) + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_CRS) { CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) @@ -271,6 +277,8 @@ Device (I2C4) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S4EN, 1)) { @@ -330,6 +338,8 @@ Device (I2C5) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S5EN, 1)) { @@ -389,6 +399,8 @@ Device (I2C6) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S6EN, 1)) { @@ -448,6 +460,8 @@ Device (I2C7) Return (^RBUF) } + Method (_HRV, 0, NotSerialized) { Return (0x06) } + Method (_STA) { If (LEqual (\S7EN, 1)) { diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index c994fdabbeb..37c0e30b62d 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -250,6 +250,15 @@ Device (IOSF) Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS) Return (^RBUF) } + + Method (_STA) + { +#if CONFIG(CHROMEOS) + Return (0xF) +#else + Return (0x0) +#endif + } } /* LPC Bridge 0:1f.0 */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 8892b531f98..9da82aafd6b 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -70,15 +70,6 @@ void baytrail_init_scc(void) void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR16(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, - SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; struct device_nvs *dev_nvs = acpi_get_device_nvs(); @@ -93,7 +84,4 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) /* Device is enabled in ACPI mode */ dev_nvs->scc_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 20e15902b10..3f9b57424ea 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -113,10 +113,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); @@ -222,14 +222,6 @@ static void soc_legacy(void) struct device_nvs *dev_nvs = acpi_get_device_nvs(); u32 reg32; - /* LPE Device */ - if (dev_nvs->lpe_en) { - reg32 = iosf_port58_read(LPE_PCICFGCTR1); - reg32 &= - ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); - iosf_port58_write(LPE_PCICFGCTR1, reg32); - } - /* SCC Devices */ #define SCC_ACPI_MODE_DISABLE(name_) \ do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ @@ -241,29 +233,30 @@ static void soc_legacy(void) SCC_ACPI_MODE_DISABLE(MMC); SCC_ACPI_MODE_DISABLE(SD); SCC_ACPI_MODE_DISABLE(SDIO); +} - /* LPSS Devices */ -#define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \ - reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ - reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ - iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ +/* + * soc_end_of_dxe: A payload (Tianocore) has indicated that the + * UEFI payload is being loaded. Switch SCC devices that are + * in PCI mode to ACPI mode so that Windows will work. + * + */ +static void soc_end_of_dxe(void) +{ + struct device_nvs *dev_nvs = acpi_get_device_nvs(); + u32 reg32; + + /* SCC Devices */ +#define SCC_ACPI_MODE_ENABLE(name_) \ + do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \ + reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ + reg32 |= (SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ + iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ } } while (0) - LPSS_ACPI_MODE_DISABLE(SIO_DMA1); - LPSS_ACPI_MODE_DISABLE(I2C1); - LPSS_ACPI_MODE_DISABLE(I2C2); - LPSS_ACPI_MODE_DISABLE(I2C3); - LPSS_ACPI_MODE_DISABLE(I2C4); - LPSS_ACPI_MODE_DISABLE(I2C5); - LPSS_ACPI_MODE_DISABLE(I2C6); - LPSS_ACPI_MODE_DISABLE(I2C7); - LPSS_ACPI_MODE_DISABLE(SIO_DMA2); - LPSS_ACPI_MODE_DISABLE(PWM1); - LPSS_ACPI_MODE_DISABLE(PWM2); - LPSS_ACPI_MODE_DISABLE(HSUART1); - LPSS_ACPI_MODE_DISABLE(HSUART2); - LPSS_ACPI_MODE_DISABLE(SPI); + SCC_ACPI_MODE_ENABLE(MMC); + SCC_ACPI_MODE_ENABLE(SD); + SCC_ACPI_MODE_ENABLE(SDIO); } static void southbridge_smi_store(void) @@ -308,6 +301,10 @@ static void southbridge_smi_apmc(void) if (CONFIG(SMMSTORE)) southbridge_smi_store(); break; + case APM_CNT_END_OF_DXE: + soc_end_of_dxe(); + break; + } mainboard_smi_apmc(reg8); diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 8e765de4ff0..f235252f9f9 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -249,6 +249,15 @@ Device (IOSF) Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS) Return (^RBUF) } + + Method (_STA) + { +#if CONFIG(CHROMEOS) + Return (0xF) +#else + Return (0x0) +#endif + } } /* LPC Bridge 0:1f.0 */ diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 138dc339df0..11aec2be97d 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -137,10 +137,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 4650a224eb3..cfe19babc66 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -593,25 +593,6 @@ static int mkhi_hmrfpo_lock_noack(void) return 0; } -static void intel_me_finalize(struct device *dev) -{ - u16 reg16; - - /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) - return; - - /* Make sure IO is disabled */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(dev, PCI_COMMAND, reg16); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); - RCBA32(FD2); -} - static int me_icc_set_clock_enables(u32 mask) { struct icc_clock_enables_msg clk = { @@ -1020,22 +1001,11 @@ static void intel_me_init(struct device *dev) } } -static void intel_me_enable(struct device *dev) -{ - /* Avoid talking to the device in S3 path */ - if (acpi_is_wakeup_s3()) { - dev->enabled = 0; - pch_disable_devfn(dev); - } -} - static struct device_operations device_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .enable = &intel_me_enable, .init = &intel_me_init, - .final = &intel_me_finalize, .ops_pci = &pci_dev_ops_pci, }; diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index a8e206783d1..beca651b053 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -184,10 +184,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Turn off backlight if needed */ backlight_off(); diff --git a/src/soc/intel/common/block/acpi/acpi/lpc.asl b/src/soc/intel/common/block/acpi/acpi/lpc.asl index c4a7dd3aaf8..e06ab63bdee 100644 --- a/src/soc/intel/common/block/acpi/acpi/lpc.asl +++ b/src/soc/intel/common/block/acpi/acpi/lpc.asl @@ -13,6 +13,9 @@ Device (LPCB) Device (DMAC) { Name (_HID, EISAID("PNP0200")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_CRS, ResourceTemplate() { IO (Decode16, 0x00, 0x00, 0x01, 0x20) @@ -27,6 +30,9 @@ Device (LPCB) Device (FWH) { Name (_HID, EISAID ("INT0800")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_DDN, "Firmware Hub") Name (_CRS, ResourceTemplate () { @@ -39,6 +45,9 @@ Device (LPCB) { Name (_HID, EISAID ("PNP0103")) Name (_CID, 0x010CD041) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_DDN, "High Precision Event Timer") Name (_CRS, ResourceTemplate () { @@ -54,6 +63,9 @@ Device (LPCB) Device(MATH) { Name (_HID, EISAID("PNP0C04")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_CRS, ResourceTemplate() { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) @@ -65,6 +77,9 @@ Device (LPCB) Device (PIC) { Name (_HID, EISAID ("PNP0000")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_DDN, "8259 Interrupt Controller") Name (_CRS, ResourceTemplate() { @@ -93,6 +108,9 @@ Device (LPCB) Device (LDRC) { Name (_HID, EISAID ("PNP0C02")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 2) Name (_DDN, "Legacy Device Resources") Name (_CRS, ResourceTemplate () @@ -115,6 +133,9 @@ Device (LPCB) Device (RTC) { Name (_HID, EISAID ("PNP0B00")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_DDN, "Real Time Clock") Name (_CRS, ResourceTemplate () { @@ -126,6 +147,9 @@ Device (LPCB) Device (TIMR) { Name (_HID, EISAID ("PNP0100")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_DDN, "8254 Timer") Name (_CRS, ResourceTemplate () { diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index 42613a8f84f..7bd499ee055 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -5,8 +5,7 @@ config SOC_INTEL_COMMON_BLOCK_TIMER config USE_LEGACY_8254_TIMER bool "Use Legacy 8254 Timer" - default y if PAYLOAD_SEABIOS || VGA_ROM_RUN - default n + default y help Setting this makes the Legacy 8254 Timer available by disabling clock gating. This needs to be enabled in order to boot a legacy diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl index 97c83553c04..c68a20dfcac 100644 --- a/src/soc/intel/skylake/acpi/dptf/charger.asl +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -3,6 +3,9 @@ Device (TCHG) { Name (_HID, "INT3403") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 0) Name (PTYP, 0x0B) Name (_STR, Unicode("Battery Charger")) diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index e72437a520d..d8971c976a9 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -3,6 +3,9 @@ Device (DPTF) { Name (_HID, EISAID ("INT3400")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 0) Name (IDSP, Package() diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl index eb75ba94ab8..dbc3de6f65a 100644 --- a/src/soc/intel/skylake/acpi/dptf/fan.asl +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -3,6 +3,9 @@ Device (TFN1) { Name (_HID, "INT3404") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 0) Name (_STR, Unicode("Fan Control")) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 95912a47fa8..9b0faa40642 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -98,6 +98,9 @@ Method (DTRP, 2, Serialized) Device (TSR0) { Name (_HID, EISAID ("INT3403")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR0_SENSOR_ID) @@ -207,6 +210,9 @@ Device (TSR0) Device (TSR1) { Name (_HID, EISAID ("INT3403")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 2) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR1_SENSOR_ID) @@ -304,6 +310,9 @@ Device (TSR1) Device (TSR2) { Name (_HID, EISAID ("INT3403")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 3) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR2_SENSOR_ID) @@ -368,6 +377,9 @@ Device (TSR2) Device (TSR3) { Name (_HID, EISAID ("INT3403")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 4) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR3_SENSOR_ID) diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index f863fc70219..519e7d0ab45 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -5,6 +5,9 @@ Device (GPIO) { Name (_HID, "INT344B") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_DDN, "GPIO Controller") diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index 63d450c5f98..2b9a2bbb8cb 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -30,6 +30,9 @@ Name (IREM, 0x0f) /* Interrupt Routing Mask */ Device (LNKA) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Name (_PRS, ResourceTemplate () @@ -79,6 +82,9 @@ Device (LNKA) Device (LNKB) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 2) Name (_PRS, ResourceTemplate () @@ -128,6 +134,9 @@ Device (LNKB) Device (LNKC) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 3) Name (_PRS, ResourceTemplate () @@ -177,6 +186,9 @@ Device (LNKC) Device (LNKD) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 4) Name (_PRS, ResourceTemplate () @@ -226,6 +238,9 @@ Device (LNKD) Device (LNKE) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 5) Name (_PRS, ResourceTemplate () @@ -275,6 +290,9 @@ Device (LNKE) Device (LNKF) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 6) Name (_PRS, ResourceTemplate () @@ -324,6 +342,9 @@ Device (LNKF) Device (LNKG) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 7) Name (_PRS, ResourceTemplate () @@ -373,6 +394,9 @@ Device (LNKG) Device (LNKH) { Name (_HID, EISAID ("PNP0C0F")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 8) Name (_PRS, ResourceTemplate () diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index f9b8f2d7c3c..ea8443920e3 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -7,6 +7,9 @@ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_UID, Zero) // _UID: Unique ID +#ifdef CONFIG_ACPI_SUBSYSTEM_ID +Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Device (MCHC) { @@ -266,6 +269,9 @@ Method (GDMB, 0, Serialized) Device (PDRC) { Name (_HID, EISAID ("PNP0C02")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_UID, 1) Method (_CRS, 0, Serialized) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 12a6ae9762a..d5aa74d5cde 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -299,6 +299,11 @@ struct soc_intel_skylake_config { */ u8 LockDownConfigRtcLock; + /* Subsystem Vendor ID of the SA devices*/ + u16 DefaultSvid; + /* Subsystem ID of the SA devices*/ + u16 DefaultSid; + /* * Determine if WLAN wake from Sx, corresponds to the * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. diff --git a/src/soc/intel/skylake/nhlt/max98373.c b/src/soc/intel/skylake/nhlt/max98373.c index 306ff5cc1ec..a82afcf9fc1 100644 --- a/src/soc/intel/skylake/nhlt/max98373.c +++ b/src/soc/intel/skylake/nhlt/max98373.c @@ -3,15 +3,6 @@ #include static const struct nhlt_format_config max98373_render_formats[] = { - /* 48 KHz 24-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 32, - .valid_bits_per_sample = 24, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98373-render-2ch-48khz-24b.bin", - }, /* 48 KHz 16-bits per sample. */ { .num_channels = 2, @@ -44,6 +35,26 @@ static const struct nhlt_format_config max98373_capture_formats[] = { }, }; +static struct nhlt_feedback_config render_config = { + .tdm_config = { + .virtual_slot = 0x0, + .config_type = NHLT_TDM_RENDER_FEEDBACK, + }, + .feedback_virtual_slot = 2, + .feedback_channels = 4, + .feedback_valid_bits_per_sample = 16, +}; + +static struct nhlt_feedback_config capture_config = { + .tdm_config = { + .virtual_slot = 0x2, + .config_type = NHLT_TDM_RENDER_FEEDBACK, + }, + .feedback_virtual_slot = 0, + .feedback_channels = 2, + .feedback_valid_bits_per_sample = 16, +}; + static const struct nhlt_endp_descriptor max98373_descriptors[] = { { .link = NHLT_LINK_SSP, @@ -51,6 +62,8 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = { .direction = NHLT_DIR_RENDER, .vid = NHLT_VID, .did = NHLT_DID_SSP, + .cfg = &render_config, + .cfg_size = sizeof(render_config), .formats = max98373_render_formats, .num_formats = ARRAY_SIZE(max98373_render_formats), }, @@ -60,6 +73,8 @@ static const struct nhlt_endp_descriptor max98373_descriptors[] = { .direction = NHLT_DIR_CAPTURE, .vid = NHLT_VID, .did = NHLT_DID_SSP, + .cfg = &capture_config, + .cfg_size = sizeof(capture_config), .formats = max98373_capture_formats, .num_formats = ARRAY_SIZE(max98373_capture_formats), }, diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c index ec352281849..3fce21cb4f6 100644 --- a/src/soc/intel/skylake/nhlt/max98927.c +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -3,15 +3,6 @@ #include static const struct nhlt_format_config max98927_render_formats[] = { - /* 48 KHz 24-bits per sample. */ - { - .num_channels = 2, - .sample_freq_khz = 48, - .container_bits_per_sample = 32, - .valid_bits_per_sample = 24, - .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, - .settings_file = "max98927-render-2ch-48khz-24b.bin", - }, /* 48 KHz 16-bits per sample. */ { .num_channels = 2, @@ -35,6 +26,28 @@ static const struct nhlt_format_config max98927_capture_formats[] = { .settings_file = "max98927-render-2ch-48khz-16b.bin", }, }; + +static struct nhlt_feedback_config render_config = { + .tdm_config = { + .virtual_slot = 0x0, + .config_type = NHLT_TDM_RENDER_FEEDBACK, + }, + .feedback_virtual_slot = 2, + .feedback_channels = 4, + .feedback_valid_bits_per_sample = 16, +}; + +static struct nhlt_feedback_config capture_config = { + .tdm_config = { + .virtual_slot = 0x2, + .config_type = NHLT_TDM_RENDER_FEEDBACK, + }, + .feedback_virtual_slot = 0, + .feedback_channels = 2, + .feedback_valid_bits_per_sample = 16, +}; + + static const struct nhlt_endp_descriptor max98927_descriptors[] = { { .link = NHLT_LINK_SSP, @@ -42,6 +55,8 @@ static const struct nhlt_endp_descriptor max98927_descriptors[] = { .direction = NHLT_DIR_RENDER, .vid = NHLT_VID, .did = NHLT_DID_SSP, + .cfg = &render_config, + .cfg_size = sizeof(render_config), .formats = max98927_render_formats, .num_formats = ARRAY_SIZE(max98927_render_formats), }, @@ -51,6 +66,8 @@ static const struct nhlt_endp_descriptor max98927_descriptors[] = { .direction = NHLT_DIR_CAPTURE, .vid = NHLT_VID, .did = NHLT_DID_SSP, + .cfg = &capture_config, + .cfg_size = sizeof(capture_config), .formats = max98927_capture_formats, .num_formats = ARRAY_SIZE(max98927_capture_formats), }, diff --git a/src/soc/intel/skylake/nhlt/rt5514.c b/src/soc/intel/skylake/nhlt/rt5514.c index bc886e1c56c..aef53e9b94a 100644 --- a/src/soc/intel/skylake/nhlt/rt5514.c +++ b/src/soc/intel/skylake/nhlt/rt5514.c @@ -17,6 +17,7 @@ static const struct nhlt_format_config rt5514_4ch_formats[] = { static const struct nhlt_dmic_array_config rt5514_4ch_mic_config = { .tdm_config = { + .virtual_slot = 0x1, .config_type = NHLT_TDM_MIC_ARRAY, }, .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 66c7dd2997b..caf485412a7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -192,7 +192,6 @@ static void intel_me_init(struct device *dev) #if CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: #endif - intel_me_hide(dev); break; case ME_NORMAL_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2a6caa67db4..15510ff65d4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -191,7 +191,6 @@ static void intel_me_init(struct device *dev) #if CONFIG(HIDE_MEI_ON_ERROR) case ME_ERROR_BIOS_PATH: #endif - intel_me_hide(dev); break; case ME_NORMAL_BIOS_PATH: diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 3c190757d66..4f560f45757 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -24,6 +24,17 @@ static void pch_smbus_init(struct device *dev) smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } +static void smbus_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) +{ + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((0x04B4 & 0xffff) << 16) | (0x18D1 & 0xffff)); +} + +static struct pci_operations smbus_pci_ops = { + .set_subsystem = smbus_set_subsystem, +}; + static const char *smbus_acpi_name(const struct device *dev) { return "SBUS"; @@ -36,7 +47,7 @@ static struct device_operations smbus_ops = { .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &pci_dev_ops_pci, + .ops_pci = &smbus_pci_ops, .acpi_name = smbus_acpi_name, }; diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 40626c2362e..76372bc7fcb 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -543,12 +543,6 @@ void intel_me_finalize(struct device *dev) /* Try to send EOP command so ME stops accepting other commands */ mkhi_end_of_post(); - /* Make sure IO is disabled */ - pci_and_config16(dev, PCI_COMMAND, - ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - - /* Hide the PCI device */ - RCBA32_OR(FD2, PCH_DISABLE_MEI1); } static int me_icc_set_clock_enables(u32 mask) @@ -900,20 +894,10 @@ static void intel_me_init(struct device *dev) */ } -static void intel_me_enable(struct device *dev) -{ - /* Avoid talking to the device in S3 path */ - if (acpi_is_wakeup_s3()) { - dev->enabled = 0; - pch_disable_devfn(dev); - } -} - static struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .enable = intel_me_enable, .init = intel_me_init, .final = intel_me_finalize, .ops_pci = &pci_dev_ops_pci, diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 769cacb792f..789f13850f7 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -136,10 +136,10 @@ static void southbridge_smi_sleep(void) wbinvd(); break; case ACPI_S4: - printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); - break; case ACPI_S5: - printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, (slp_typ == ACPI_S4) ? + "SMI#: Entering S4 (Suspend-To-Disk)\n" : + "SMI#: Entering S5 (Soft Power off)\n"); /* Disable all GPE */ disable_all_gpe(); diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 1219bccf8c7..9a8935a479e 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -273,56 +273,21 @@ static void usb_xhci_clock_gating(struct device *dev) static void usb_xhci_init(struct device *dev) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; - u8 *mem_base = usb_xhci_mem_base(dev); struct southbridge_intel_lynxpoint_config *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ pci_update_config16(dev, XHCI_PWR_CTL_STS, ~PWR_CTL_SET_MASK, PWR_CTL_SET_D0); + /* Disable Compliance Mode Entry */ + reg32 = read32(res2mmio(res, 0x80ec, 0)); + reg32 |= (1 << 0); + write32(res2mmio(res, 0x80ec, 0), reg32); + /* Enable clock gating first */ usb_xhci_clock_gating(dev); - reg32 = read32(mem_base + 0x8144); - if (pch_is_lp()) { - /* XHCIBAR + 8144h[8,7,6] = 111b */ - reg32 |= (1 << 8) | (1 << 7) | (1 << 6); - } else { - /* XHCIBAR + 8144h[8,7,6] = 100b */ - reg32 &= ~((1 << 7) | (1 << 6)); - reg32 |= (1 << 8); - } - write32(mem_base + 0x8144, reg32); - - if (pch_is_lp()) { - /* XHCIBAR + 816Ch[19:0] = 000e0038h */ - reg32 = read32(mem_base + 0x816c); - reg32 &= ~0x000fffff; - reg32 |= 0x000e0038; - write32(mem_base + 0x816c, reg32); - - /* D20:F0:B0h[17,14,13] = 100b */ - pci_update_config32(dev, 0xb0, ~((1 << 14) | (1 << 13)), 1 << 17); - } - - reg32 = pci_read_config32(dev, 0x50); - if (pch_is_lp()) { - /* D20:F0:50h[28:0] = 0FCE2E5Fh */ - reg32 &= ~0x1fffffff; - reg32 |= 0x0fce2e5f; - } else { - /* D20:F0:50h[26:0] = 07886E9Fh */ - reg32 &= ~0x07ffffff; - reg32 |= 0x07886e9f; - } - pci_write_config32(dev, 0x50, reg32); - - /* D20:F0:44h[31] = 1 (Access Control Bit) */ - pci_or_config32(dev, 0x44, 1 << 31); - - /* D20:F0:40h[31,23] = 10b (OC Configuration Done) */ - pci_update_config32(dev, 0x40, ~(1 << 23), 1 << 31); /* unsupported request */ - if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or * polling before returning to the OS. */ diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index 117de961db9..fc3c92938a5 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -3,7 +3,8 @@ // Scope is \_SB.PCI0.LPCB Device (SIO) { - Name (_ADR, 0x2E) + Name (_HID, EisaId ("PNP0A05")) + OperationRegion (SIOA, SystemIO, 0x2E, 0x02) Field (SIOA, ByteAcc, NoLock, Preserve) { @@ -157,7 +158,7 @@ Device (SIO) { Device (SKBC) // Keyboard { Name (_HID, EISAID("PNP0303")) - Name (_CID, EISAID("PNP030B")) + Name (_CID, Package() { EISAID("PNP030B"), "GGL0303" } ) Method (_STA, 0, NotSerialized) { Return (ISEN (LKBC)) diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index b9f807fada9..13daa15a46a 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -9,6 +9,9 @@ Device (CRHW) { Name(_HID, "GOOG0016") Name(_CID, EISAID("GGL0001")) +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Method(_STA, 0, Serialized) { diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl index fdce750bb05..060bb87795f 100644 --- a/src/vendorcode/google/chromeos/acpi/ramoops.asl +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -5,6 +5,9 @@ Scope (\_SB) Device(RMOP) { Name (_HID, "GOOG9999") +#ifdef CONFIG_ACPI_SUBSYSTEM_ID + Name (_SUB, CONFIG_ACPI_SUBSYSTEM_ID) +#endif Name (_CID, "GOOG9999") Name (_UID, 1) diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index 8c72ddfb4a6..10f8c4bc8fb 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -66,6 +66,12 @@ printf "#define COREBOOT_VERSION %s\n" "\"$KERNELVERSION\"" #See if the build is running in a git repo and the git command is available printf "/* timesource: $TIMESOURCE */\n" + +printf "#define DASHARO_VERSION \"%s\"\n" "$DASHARO_VERSION" +printf "#define DASHARO_MAJOR_VERSION %d\\n" "$DASHARO_MAJOR_VERSION" +printf "#define DASHARO_MINOR_VERSION %d\\n" "$DASHARO_MINOR_VERSION" +printf "#define DASHARO_PATCH_VERSION %d\\n" "$DASHARO_PATCH_VERSION" + printf "#define COREBOOT_VERSION_TIMESTAMP $DATE\n" printf "#define COREBOOT_ORIGIN_GIT_REVISION \"$GITREV\"\n"