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cpu.c
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/* gameplaySP
*
* Copyright (C) 2006 Exophase <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Important todo:
// - stm reglist writeback when base is in the list needs adjustment
// - block memory needs psr swapping and user mode reg swapping
#include "common.h"
u32 memory_region_access_read_u8[16];
u32 memory_region_access_read_s8[16];
u32 memory_region_access_read_u16[16];
u32 memory_region_access_read_s16[16];
u32 memory_region_access_read_u32[16];
u32 memory_region_access_write_u8[16];
u32 memory_region_access_write_u16[16];
u32 memory_region_access_write_u32[16];
u32 memory_reads_u8;
u32 memory_reads_s8;
u32 memory_reads_u16;
u32 memory_reads_s16;
u32 memory_reads_u32;
u32 memory_writes_u8;
u32 memory_writes_u16;
u32 memory_writes_u32;
const u8 bit_count[256] =
{
0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3,
4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4,
4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2,
3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5,
4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4,
5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3,
3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2,
3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6,
4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5,
6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5,
5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6,
7, 7, 8
};
#ifdef REGISTER_USAGE_ANALYZE
u64 instructions_total = 0;
u64 arm_reg_freq[16];
u64 arm_reg_access_total = 0;
u64 arm_instructions_total = 0;
u64 thumb_reg_freq[16];
u64 thumb_reg_access_total = 0;
u64 thumb_instructions_total = 0;
// mla/long mla's addition operand are not counted yet.
#define using_register(instruction_set, register, type) \
instruction_set##_reg_freq[register]++; \
instruction_set##_reg_access_total++ \
#define using_register_list(instruction_set, rlist, count) \
{ \
u32 i; \
for(i = 0; i < count; i++) \
{ \
if((reg_list >> i) & 0x01) \
{ \
using_register(instruction_set, i, memory_target); \
} \
} \
} \
#define using_instruction(instruction_set) \
instruction_set##_instructions_total++; \
instructions_total++ \
int sort_tagged_element(const void *_a, const void *_b)
{
const u64 *a = _a;
const u64 *b = _b;
return (int)(b[1] - a[1]);
}
void print_register_usage(void)
{
u32 i;
u64 arm_reg_freq_tagged[32];
u64 thumb_reg_freq_tagged[32];
double percent;
double percent_total = 0.0;
for(i = 0; i < 16; i++)
{
arm_reg_freq_tagged[i * 2] = i;
arm_reg_freq_tagged[(i * 2) + 1] = arm_reg_freq[i];
thumb_reg_freq_tagged[i * 2] = i;
thumb_reg_freq_tagged[(i * 2) + 1] = thumb_reg_freq[i];
}
qsort(arm_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element);
qsort(thumb_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element);
printf("ARM register usage (%lf%% ARM instructions):\n",
(arm_instructions_total * 100.0) / instructions_total);
for(i = 0; i < 16; i++)
{
percent = (arm_reg_freq_tagged[(i * 2) + 1] * 100.0) /
arm_reg_access_total;
percent_total += percent;
printf("r%02d: %lf%% (-- %lf%%)\n",
(u32)arm_reg_freq_tagged[(i * 2)], percent, percent_total);
}
percent_total = 0.0;
printf("\nThumb register usage (%lf%% Thumb instructions):\n",
(thumb_instructions_total * 100.0) / instructions_total);
for(i = 0; i < 16; i++)
{
percent = (thumb_reg_freq_tagged[(i * 2) + 1] * 100.0) /
thumb_reg_access_total;
percent_total += percent;
printf("r%02d: %lf%% (-- %lf%%)\n",
(u32)thumb_reg_freq_tagged[(i * 2)], percent, percent_total);
}
memset(arm_reg_freq, 0, sizeof(u64) * 16);
memset(thumb_reg_freq, 0, sizeof(u64) * 16);
arm_reg_access_total = 0;
thumb_reg_access_total = 0;
}
#else
#define using_register(instruction_set, register, type) \
#define using_register_list(instruction_set, rlist, count) \
#define using_instruction(instruction_set) \
#endif
#define arm_decode_data_proc_reg(opcode) \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F; \
(void)rd; \
(void)rn; \
using_register(arm, rd, op_dest); \
using_register(arm, rn, op_src); \
using_register(arm, rm, op_src) \
#define arm_decode_data_proc_imm(opcode) \
u32 imm; \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
(void)rd; \
(void)rn; \
ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \
using_register(arm, rd, op_dest); \
using_register(arm, rn, op_src) \
#define arm_decode_psr_reg(opcode) \
u32 psr_field = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F; \
(void)rd; \
(void)rm; \
(void)psr_field; \
using_register(arm, rd, op_dest); \
using_register(arm, rm, op_src) \
#define arm_decode_psr_imm(opcode) \
u32 imm; \
u32 psr_field = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
(void)rd; \
ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \
using_register(arm, rd, op_dest) \
#define arm_decode_branchx(opcode) \
u32 rn = opcode & 0x0F; \
using_register(arm, rn, branch_target) \
#define arm_decode_multiply() \
u32 rd = (opcode >> 16) & 0x0F; \
u32 rn = (opcode >> 12) & 0x0F; \
u32 rs = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F; \
(void)rn; \
using_register(arm, rd, op_dest); \
using_register(arm, rn, op_src); \
using_register(arm, rm, op_src) \
#define arm_decode_multiply_long() \
u32 rdhi = (opcode >> 16) & 0x0F; \
u32 rdlo = (opcode >> 12) & 0x0F; \
u32 rn = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F; \
using_register(arm, rdhi, op_dest); \
using_register(arm, rdlo, op_dest); \
using_register(arm, rn, op_src); \
using_register(arm, rm, op_src) \
#define arm_decode_swap() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F; \
using_register(arm, rd, memory_target); \
using_register(arm, rn, memory_base); \
using_register(arm, rm, memory_target) \
#define arm_decode_half_trans_r() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F; \
using_register(arm, rd, memory_target); \
using_register(arm, rn, memory_base); \
using_register(arm, rm, memory_offset) \
#define arm_decode_half_trans_of() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F); \
using_register(arm, rd, memory_target); \
using_register(arm, rn, memory_base) \
#define arm_decode_data_trans_imm() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = opcode & 0x0FFF; \
using_register(arm, rd, memory_target); \
using_register(arm, rn, memory_base) \
#define arm_decode_data_trans_reg() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F; \
using_register(arm, rd, memory_target); \
using_register(arm, rn, memory_base); \
using_register(arm, rm, memory_offset) \
#define arm_decode_block_trans() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 reg_list = opcode & 0xFFFF; \
using_register(arm, rn, memory_base); \
using_register_list(arm, reg_list, 16) \
#define arm_decode_branch() \
s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \
#define thumb_decode_shift() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, op_dest); \
using_register(thumb, rs, op_shift) \
#define thumb_decode_add_sub() \
u32 rn = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, op_dest); \
using_register(thumb, rn, op_src); \
using_register(thumb, rn, op_src) \
#define thumb_decode_add_sub_imm() \
u32 imm = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, op_src_dest); \
using_register(thumb, rs, op_src) \
#define thumb_decode_imm() \
u32 imm = opcode & 0xFF; \
using_register(thumb, ((opcode >> 8) & 0x07), op_dest) \
#define thumb_decode_alu_op() \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, op_src_dest); \
using_register(thumb, rs, op_src) \
#define thumb_decode_hireg_op() \
u32 rs = (opcode >> 3) & 0x0F; \
u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07); \
(void)rd; \
using_register(thumb, rd, op_src_dest); \
using_register(thumb, rs, op_src) \
#define thumb_decode_mem_reg() \
u32 ro = (opcode >> 6) & 0x07; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, memory_target); \
using_register(thumb, rb, memory_base); \
using_register(thumb, ro, memory_offset) \
#define thumb_decode_mem_imm() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07; \
using_register(thumb, rd, memory_target); \
using_register(thumb, rb, memory_base) \
#define thumb_decode_add_sp() \
u32 imm = opcode & 0x7F; \
using_register(thumb, REG_SP, op_dest) \
#define thumb_decode_rlist() \
u32 reg_list = opcode & 0xFF; \
using_register_list(thumb, rlist, 8) \
#define thumb_decode_branch_cond() \
s32 offset = (s8)(opcode & 0xFF) \
#define thumb_decode_swi() \
u32 comment = opcode & 0xFF \
#define thumb_decode_branch() \
u32 offset = opcode & 0x07FF \
#define get_shift_register(dest) \
u32 shift = reg[(opcode >> 8) & 0x0F]; \
using_register(arm, ((opcode >> 8) & 0x0F), op_shift); \
dest = reg[rm]; \
if(rm == 15) \
dest += 4 \
#define calculate_z_flag(dest) \
z_flag = (dest == 0) \
#define calculate_n_flag(dest) \
n_flag = ((signed)dest < 0) \
#define calculate_c_flag_sub(dest, src_a, src_b) \
c_flag = ((unsigned)src_b <= (unsigned)src_a) \
#define calculate_v_flag_sub(dest, src_a, src_b) \
v_flag = ((signed)src_b > (signed)src_a) != ((signed)dest < 0) \
#define calculate_c_flag_add(dest, src_a, src_b) \
c_flag = ((unsigned)dest < (unsigned)src_a) \
#define calculate_v_flag_add(dest, src_a, src_b) \
v_flag = ((signed)dest < (signed)src_a) != ((signed)src_b < 0) \
#define calculate_reg_sh() \
u32 reg_sh = 0; \
switch((opcode >> 4) & 0x07) \
{ \
/* LSL imm */ \
case 0x0: \
{ \
reg_sh = reg[rm] << ((opcode >> 7) & 0x1F); \
break; \
} \
\
/* LSL reg */ \
case 0x1: \
{ \
get_shift_register(reg_sh); \
if(shift <= 31) \
reg_sh = reg_sh << shift; \
else \
reg_sh = 0; \
break; \
} \
\
/* LSR imm */ \
case 0x2: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
if(imm == 0) \
reg_sh = 0; \
else \
reg_sh = reg[rm] >> imm; \
break; \
} \
\
/* LSR reg */ \
case 0x3: \
{ \
get_shift_register(reg_sh); \
if(shift <= 31) \
reg_sh = reg_sh >> shift; \
else \
reg_sh = 0; \
break; \
} \
\
/* ASR imm */ \
case 0x4: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
reg_sh = reg[rm]; \
\
if(imm == 0) \
reg_sh = (s32)reg_sh >> 31; \
else \
reg_sh = (s32)reg_sh >> imm; \
break; \
} \
\
/* ASR reg */ \
case 0x5: \
{ \
get_shift_register(reg_sh); \
if(shift <= 31) \
reg_sh = (s32)reg_sh >> shift; \
else \
reg_sh = (s32)reg_sh >> 31; \
break; \
} \
\
/* ROR imm */ \
case 0x6: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
\
if(imm == 0) \
reg_sh = (reg[rm] >> 1) | (c_flag << 31); \
else \
ror(reg_sh, reg[rm], imm); \
break; \
} \
\
/* ROR reg */ \
case 0x7: \
{ \
get_shift_register(reg_sh); \
ror(reg_sh, reg_sh, shift); \
break; \
} \
} \
#define calculate_reg_sh_flags() \
u32 reg_sh = 0; \
switch((opcode >> 4) & 0x07) \
{ \
/* LSL imm */ \
case 0x0: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
reg_sh = reg[rm]; \
\
if(imm != 0) \
{ \
c_flag = (reg_sh >> (32 - imm)) & 0x01; \
reg_sh <<= imm; \
} \
\
break; \
} \
\
/* LSL reg */ \
case 0x1: \
{ \
get_shift_register(reg_sh); \
if(shift != 0) \
{ \
if(shift > 31) \
{ \
if(shift == 32) \
c_flag = reg_sh & 0x01; \
else \
c_flag = 0; \
reg_sh = 0; \
} \
else \
{ \
c_flag = (reg_sh >> (32 - shift)) & 0x01; \
reg_sh <<= shift; \
} \
} \
break; \
} \
\
/* LSR imm */ \
case 0x2: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
reg_sh = reg[rm]; \
if(imm == 0) \
{ \
c_flag = reg_sh >> 31; \
reg_sh = 0; \
} \
else \
{ \
c_flag = (reg_sh >> (imm - 1)) & 0x01; \
reg_sh >>= imm; \
} \
break; \
} \
\
/* LSR reg */ \
case 0x3: \
{ \
get_shift_register(reg_sh); \
if(shift != 0) \
{ \
if(shift > 31) \
{ \
if(shift == 32) \
c_flag = (reg_sh >> 31) & 0x01; \
else \
c_flag = 0; \
reg_sh = 0; \
} \
else \
{ \
c_flag = (reg_sh >> (shift - 1)) & 0x01; \
reg_sh >>= shift; \
} \
} \
break; \
} \
\
/* ASR imm */ \
case 0x4: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
reg_sh = reg[rm]; \
if(imm == 0) \
{ \
reg_sh = (s32)reg_sh >> 31; \
c_flag = reg_sh & 0x01; \
} \
else \
{ \
c_flag = (reg_sh >> (imm - 1)) & 0x01; \
reg_sh = (s32)reg_sh >> imm; \
} \
break; \
} \
\
/* ASR reg */ \
case 0x5: \
{ \
get_shift_register(reg_sh); \
if(shift != 0) \
{ \
if(shift > 31) \
{ \
reg_sh = (s32)reg_sh >> 31; \
c_flag = reg_sh & 0x01; \
} \
else \
{ \
c_flag = (reg_sh >> (shift - 1)) & 0x01; \
reg_sh = (s32)reg_sh >> shift; \
} \
} \
break; \
} \
\
/* ROR imm */ \
case 0x6: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
reg_sh = reg[rm]; \
if(imm == 0) \
{ \
u32 old_c_flag = c_flag; \
c_flag = reg_sh & 0x01; \
reg_sh = (reg_sh >> 1) | (old_c_flag << 31); \
} \
else \
{ \
c_flag = (reg_sh >> (imm - 1)) & 0x01; \
ror(reg_sh, reg_sh, imm); \
} \
break; \
} \
\
/* ROR reg */ \
case 0x7: \
{ \
get_shift_register(reg_sh); \
if(shift != 0) \
{ \
c_flag = (reg_sh >> (shift - 1)) & 0x01; \
ror(reg_sh, reg_sh, shift); \
} \
break; \
} \
} \
#define calculate_reg_offset() \
u32 reg_offset = 0; \
switch((opcode >> 5) & 0x03) \
{ \
/* LSL imm */ \
case 0x0: \
{ \
reg_offset = reg[rm] << ((opcode >> 7) & 0x1F); \
break; \
} \
\
/* LSR imm */ \
case 0x1: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
if(imm == 0) \
reg_offset = 0; \
else \
reg_offset = reg[rm] >> imm; \
break; \
} \
\
/* ASR imm */ \
case 0x2: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
if(imm == 0) \
reg_offset = (s32)reg[rm] >> 31; \
else \
reg_offset = (s32)reg[rm] >> imm; \
break; \
} \
\
/* ROR imm */ \
case 0x3: \
{ \
u32 imm = (opcode >> 7) & 0x1F; \
if(imm == 0) \
reg_offset = (reg[rm] >> 1) | (c_flag << 31); \
else \
ror(reg_offset, reg[rm], imm); \
break; \
} \
} \
#define calculate_flags_add(dest, src_a, src_b) \
calculate_z_flag(dest); \
calculate_n_flag(dest); \
calculate_c_flag_add(dest, src_a, src_b); \
calculate_v_flag_add(dest, src_a, src_b) \
#define calculate_flags_sub(dest, src_a, src_b) \
calculate_z_flag(dest); \
calculate_n_flag(dest); \
calculate_c_flag_sub(dest, src_a, src_b); \
calculate_v_flag_sub(dest, src_a, src_b) \
#define calculate_flags_logic(dest) \
calculate_z_flag(dest); \
calculate_n_flag(dest) \
#define extract_flags() \
n_flag = reg[REG_CPSR] >> 31; \
z_flag = (reg[REG_CPSR] >> 30) & 0x01; \
c_flag = (reg[REG_CPSR] >> 29) & 0x01; \
v_flag = (reg[REG_CPSR] >> 28) & 0x01; \
#define collapse_flags() \
reg[REG_CPSR] = (n_flag << 31) | (z_flag << 30) | (c_flag << 29) | \
(v_flag << 28) | (reg[REG_CPSR] & 0xFF) \
#define memory_region(r_dest, l_dest, address) \
r_dest = memory_regions[address >> 24]; \
l_dest = memory_limits[address >> 24] \
#define pc_region() \
memory_region(pc_region, pc_limit, pc) \
#define check_pc_region() \
new_pc_region = (pc >> 15); \
if(new_pc_region != pc_region) \
{ \
pc_region = new_pc_region; \
pc_address_block = memory_map_read[new_pc_region]; \
\
if(!pc_address_block) \
pc_address_block = load_gamepak_page(pc_region & 0x3FF); \
} \
u32 branch_targets = 0;
u32 high_frequency_branch_targets = 0;
#define BRANCH_ACTIVITY_THRESHOLD 50
#define arm_update_pc() \
pc = reg[REG_PC] \
#define arm_pc_offset(val) \
pc += val; \
reg[REG_PC] = pc \
#define arm_pc_offset_update(val) \
pc += val; \
reg[REG_PC] = pc \
#define arm_pc_offset_update_direct(val) \
pc = val; \
reg[REG_PC] = pc \
// It should be okay to still generate result flags, spsr will overwrite them.
// This is pretty infrequent (returning from interrupt handlers, et al) so
// probably not worth optimizing for.
#define check_for_interrupts() \
if((io_registers[REG_IE] & io_registers[REG_IF]) && \
io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \
{ \
reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4; \
spsr[MODE_IRQ] = reg[REG_CPSR]; \
reg[REG_CPSR] = 0xD2; \
reg[REG_PC] = 0x00000018; \
arm_update_pc(); \
set_cpu_mode(MODE_IRQ); \
goto arm_loop; \
} \
#define arm_spsr_restore() \
if(rd == 15) \
{ \
if(reg[CPU_MODE] != MODE_USER) \
{ \
reg[REG_CPSR] = spsr[reg[CPU_MODE]]; \
extract_flags(); \
set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \
check_for_interrupts(); \
} \
arm_update_pc(); \
\
if(reg[REG_CPSR] & 0x20) \
goto thumb_loop; \
} \
#define arm_data_proc_flags_reg() \
arm_decode_data_proc_reg(opcode); \
calculate_reg_sh_flags() \
#define arm_data_proc_reg() \
arm_decode_data_proc_reg(opcode); \
calculate_reg_sh() \
#define arm_data_proc_flags_imm() \
arm_decode_data_proc_imm(opcode) \
#define arm_data_proc_imm() \
arm_decode_data_proc_imm(opcode) \
#define arm_data_proc(expr, type) \
{ \
u32 dest; \
arm_pc_offset(8); \
arm_data_proc_##type(); \
dest = expr; \
arm_pc_offset(-4); \
reg[rd] = dest; \
\
if(rd == 15) \
{ \
arm_update_pc(); \
} \
} \
#define flags_vars(src_a, src_b) \
u32 dest; \
const u32 _sa = src_a; \
const u32 _sb = src_b \
#define arm_data_proc_logic_flags(expr, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_flags_##type(); \
u32 dest = expr; \
calculate_flags_logic(dest); \
arm_pc_offset(-4); \
reg[rd] = dest; \
arm_spsr_restore(); \
} \
#define arm_data_proc_add_flags(src_a, src_b, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_##type(); \
flags_vars(src_a, src_b); \
dest = _sa + _sb; \
calculate_flags_add(dest, _sa, _sb); \
arm_pc_offset(-4); \
reg[rd] = dest; \
arm_spsr_restore(); \
}
#define arm_data_proc_sub_flags(src_a, src_b, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_##type(); \
flags_vars(src_a, src_b); \
dest = _sa - _sb; \
calculate_flags_sub(dest, _sa, _sb); \
arm_pc_offset(-4); \
reg[rd] = dest; \
arm_spsr_restore(); \
} \
#define arm_data_proc_test_logic(expr, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_flags_##type(); \
u32 dest = expr; \
calculate_flags_logic(dest); \
arm_pc_offset(-4); \
} \
#define arm_data_proc_test_add(src_a, src_b, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_##type(); \
flags_vars(src_a, src_b); \
dest = _sa + _sb; \
calculate_flags_add(dest, _sa, _sb); \
arm_pc_offset(-4); \
} \
#define arm_data_proc_test_sub(src_a, src_b, type) \
{ \
arm_pc_offset(8); \
arm_data_proc_##type(); \
flags_vars(src_a, src_b); \
dest = _sa - _sb; \
calculate_flags_sub(dest, _sa, _sb); \
arm_pc_offset(-4); \
} \
#define arm_multiply_flags_yes(_dest) \
calculate_z_flag(_dest); \
calculate_n_flag(_dest); \
#define arm_multiply_flags_no(_dest) \
#define arm_multiply_long_flags_yes(_dest_lo, _dest_hi) \
z_flag = (_dest_lo == 0) & (_dest_hi == 0); \
calculate_n_flag(_dest_hi) \
#define arm_multiply_long_flags_no(_dest_lo, _dest_hi) \
#define arm_multiply(add_op, flags) \
{ \
u32 dest; \
arm_decode_multiply(); \
dest = (reg[rm] * reg[rs]) add_op; \
arm_multiply_flags_##flags(dest); \
reg[rd] = dest; \
arm_pc_offset(4); \
} \
#define arm_multiply_long_addop(type) \
+ ((type##64)((((type##64)reg[rdhi]) << 32) | reg[rdlo])); \
#define arm_multiply_long(add_op, flags, type) \
{ \
type##64 dest; \
u32 dest_lo; \
u32 dest_hi; \
arm_decode_multiply_long(); \
dest = ((type##64)((type##32)reg[rm]) * \
(type##64)((type##32)reg[rn])) add_op; \
dest_lo = (u32)dest; \
dest_hi = (u32)(dest >> 32); \
arm_multiply_long_flags_##flags(dest_lo, dest_hi); \
reg[rdlo] = dest_lo; \
reg[rdhi] = dest_hi; \
arm_pc_offset(4); \
} \
const u32 psr_masks[16] =
{
0x00000000, 0x000000FF, 0x0000FF00, 0x0000FFFF, 0x00FF0000,
0x00FF00FF, 0x00FFFF00, 0x00FFFFFF, 0xFF000000, 0xFF0000FF,
0xFF00FF00, 0xFF00FFFF, 0xFFFF0000, 0xFFFF00FF, 0xFFFFFF00,
0xFFFFFFFF
};
#define arm_psr_read(dummy, psr_reg) \
collapse_flags(); \
reg[rd] = psr_reg \
#define arm_psr_store_cpsr(source) \
reg[REG_CPSR] = (source & store_mask) | (reg[REG_CPSR] & (~store_mask)); \
extract_flags(); \
if(store_mask & 0xFF) \
{ \
set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \
check_for_interrupts(); \
} \
#define arm_psr_store_spsr(source) \
u32 _psr = spsr[reg[CPU_MODE]]; \
spsr[reg[CPU_MODE]] = (source & store_mask) | (_psr & (~store_mask)) \
#define arm_psr_store(source, psr_reg) \
const u32 store_mask = psr_masks[psr_field]; \
arm_psr_store_##psr_reg(source) \
#define arm_psr_src_reg reg[rm]
#define arm_psr_src_imm imm
#define arm_psr(op_type, transfer_type, psr_reg) \
{ \
arm_decode_psr_##op_type(opcode); \
arm_pc_offset(4); \
arm_psr_##transfer_type(arm_psr_src_##op_type, psr_reg); \
} \
#define arm_data_trans_reg() \
arm_decode_data_trans_reg(); \
calculate_reg_offset() \
#define arm_data_trans_imm() \
arm_decode_data_trans_imm() \
#define arm_data_trans_half_reg() \
arm_decode_half_trans_r() \
#define arm_data_trans_half_imm() \
arm_decode_half_trans_of() \
#define aligned_address_mask8 0xF0000000
#define aligned_address_mask16 0xF0000001
#define aligned_address_mask32 0xF0000003
#define fast_read_memory(size, type, address, dest) \
{ \
u8 *map; \
u32 _address = address; \
\
if(_address < 0x10000000) \
{ \
memory_region_access_read_##type[_address >> 24]++; \
memory_reads_##type++; \
} \
if(((_address >> 24) == 0) && (pc >= 0x4000)) \
{ \
dest = *((type *)((u8 *)&bios_read_protect + (_address & 0x03))); \
} \
else \
\
if(((_address & aligned_address_mask##size) == 0) && \
(map = memory_map_read[_address >> 15])) \
{ \
dest = *((type *)((u8 *)map + (_address & 0x7FFF))); \
} \
else \
{ \
dest = (type)read_memory##size(_address); \
} \
} \
#define fast_read_memory_s16(address, dest) \
{ \
u8 *map; \
u32 _address = address; \
if(_address < 0x10000000) \
{ \
memory_region_access_read_s16[_address >> 24]++; \
memory_reads_s16++; \
} \
if(((_address & aligned_address_mask16) == 0) && \
(map = memory_map_read[_address >> 15])) \
{ \
dest = *((s16 *)((u8 *)map + (_address & 0x7FFF))); \
} \
else \
{ \
dest = (s16)read_memory16_signed(_address); \
} \