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signextension.vcd
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$date
Fri Mar 13 15:53:28 2020
$end
$version
GHDL v0
$end
$timescale
1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module t_signextension $end
$var reg 8 ! input_t[7:0] $end
$var reg 16 " output_t[15:0] $end
$var reg 1 # reset_t $end
$scope module extension $end
$var reg 8 $ input[7:0] $end
$var reg 16 % output[15:0] $end
$var reg 1 & reset $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
bUUUUUUUU !
b0000000000000000 "
1#
bUUUUUUUU $
b0000000000000000 %
1&
#1000000000000
bUUUUUUUUUUUUUUUU "
0#
bUUUUUUUUUUUUUUUU %
0&
#2000000000000
b00000001 !
b0000000000000001 "
b00000001 $
b0000000000000001 %
#3000000000000
#4000000000000
b01111111 !
b0000000001111111 "
b01111111 $
b0000000001111111 %
#5000000000000
#6000000000000
b10000000 !
b1111111110000000 "
b10000000 $
b1111111110000000 %
#7000000000000
#8000000000000
b11111111 !
b1111111111111111 "
b11111111 $
b1111111111111111 %
#9000000000000
#10000000000000
b0000000000000000 "
1#
b0000000000000000 %
1&