Can't Solve Fill Cell/Density DRC Error

[shafinhossain]

I initially ran the DRC without using any fill cells and I encountered multiple density errors.

Then I ran the scripts for active, metal and top metal fillers and even ran the density report.
After that I executed the DRC again and encountered the exact density DRC errors before using the filler cells. Could anyone kindly walk me through this issue?

Note: I did not draw any PR boundaries, could that be a factor? and if I had to draw one how would I approach?

[PhillipRambo]

Hi @shafinhossain could you please provide the testcases so i can reproduce the issues. Are you working on the latest commit?

Kindes Regards Phillip

[shafinhossain]

Hello @PhillipRambo
Here you can find the testcase, file name is 'test_case_cell.gds':
https://drive.google.com/drive/folders/1FOBsojHR_wbLBcXiUR6d9uIEcFulxXRO?usp=sharing

[Ikram-rs22]

@PhillipRambo any update on this issue?? Facing the same problem.

[akrinke]

I think this problem is caused by the chip being too small. Since the area at the border is not filled, the overall density becomes too low. Maybe you can increase the fill density in the scripts?

[Ikram-rs22]

Do I reduce it? I've already reduced reduced the spacing of active filler to 0.42 which I assume to be the drc limit.

Does the other filler layers (gatpoly, metal, top metal) have the same drc limit of 0.42?

[akrinke]

I used a value of 0.5 and it removed most of the DRC errors regarding active density. The remaining 3 errors are due to the 800x800 µm² window that is used for density calculation. I think they can be ignored.

[PhillipRambo]

Hi, i just had the time to run the testcase, and i agree with @akrinke. In my case i simply ran the filler script without any exlusion layers, and i reduced the DRC errors from 33 to around 26 where most of them where related to the chip being to small. i.e the min size of 800x800mu. Could you confirm same behaviour on your side @shafinhossain, with the latest dev commit.

Regards Phillip

[Ikram-rs22]

Yes I can confirm that after resizing the seal ring to 750x750 and using spacing for both active & gate poly filler to 0.42, the drc reduced from 33 to 21

[PhillipRambo]

And what are the remaning issues related to then? Are you using the testcase provided by @shafinhossain?

[Ikram-rs22]

No I'm using a separate testcase. I don't know about @shafinhossain testcase

[shafinhossain]

@PhillipRambo I ran the DRC using 750x750 um seal ring, with 0.5 filler script spacing.

I got 21 errors in the first run, in the second run oddly I got 17.

[shafinhossain]

@PhillipRambo did you follow up on this issue? it would be really helpful for me.
TIA.

[PhillipRambo]

@shafinhossain Hi. There is a lot of tasks at the moment so response time is varying a bit. I hope you understand

Looking at your answer i increase the size of the sealring in the testcase you provided and at this point i get 15 DRC errors, realted to coverage ratio for specific sized chip area. However this doesnt allign with your case, and from the pictures its not clear what DRC you are facing. I will need some more information about which errors you face and not just the number of errors. Which branch and commit are you on? And i guess you also are filling every layer and not excluding any? If your setup changes and differs from my own its very hard for me to reproduce the errors. Can you clarify these points :)

From the issues im facing it looks like the DRC is not experiencing the fillers from different layers properly but again im not to big an expert on this, what is your take @akrinke , i guess this is the same as what you saw?

Regards Phillip

[sergeiandreyev]

Hi @shafinhossain, could you please make a screenshot with the DRC violations expanded (to make the exact rule names and numbers visible) or send us the .rdb file

[shafinhossain]

Hello @PhillipRambo @sergeiandreyev @akrinke
I am using the latest commit and dev branch, I am filling all the layers and I do not know how to exclude any.

I filled activ/gatpoly, metal and topmetal and then ran a density report.

Here's the snap of the stretched error box.

I am also dropping the .rdb file link here.
https://drive.google.com/file/d/1oSMQ-p9HM8hUVaG0fkZtmimucAjOG7Pv/view?usp=sharing

If you need anything else please do let me know. Really grateful for you responses.

[shafinhossain]

any update on the matter @PhillipRambo @sergeiandreyev ?
TIA. :D

[PhillipRambo]

Hi @shafinhossain,

After reviewing the testcase, we’ve identified that the filler script needs optimization to address the density errors and related issues.

If your goal is to submit the design for an OS tapeout, a possible workaround would be to send the final design to us, and we’ll take care of adding the necessary fillers for you.

@dnltz, could you please take a look at the testcase? It serves as a good example of how the filler script could be improved for small designs like this.

Best regards,
Phillip

[shafinhossain]

Thanks a lot @PhillipRambo. I do want to submit my design for the March Tapeout. If I clean the rest of the drcs (ones except the density and filler cells), could you be kind enough to take care the rest of it as you mentioned?

Regards,
Shafin Hossain

[dnltz]

Hi @shafinhossain,

After reviewing the testcase, we’ve identified that the filler script needs optimization to address the density errors and related issues.

If your goal is to submit the design for an OS tapeout, a possible workaround would be to send the final design to us, and we’ll take care of adding the necessary fillers for you.

@dnltz, could you please take a look at the testcase? It serves as a good example of how the filler script could be improved for small designs like this.

Best regards, Phillip

The current implementation is too stupid to various different chip layouts because the gaps and filler cell size are hard-coded. Ideally we fill each tile independently and check the whether they meet the requirements. If they don't meet them, the script should fill with less or more material.

I started to do that but I don't have much time right now to continue: #229

The alternative would be to use commercial tools for fill.

[PhillipRambo]

@dnltz Hi Daniel. Thanks for the update, we tried playing around with some different spacing settings and i can then meet the filler rules for the design given in this example, but you are right a more sofisticated approach to filling is needed. Thanks for the help!