-
Notifications
You must be signed in to change notification settings - Fork 2
/
Copy pathcapsense_pkg.vhdl
76 lines (72 loc) · 4.5 KB
/
capsense_pkg.vhdl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
------------------------------------------------------------------------------
---- ----
---- Capsense controller package ----
---- ----
---- This file is part FPGA Libre project http://fpgalibre.sf.net/ ----
---- ----
---- Description: ----
---- Declarations for the CapSense library. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador en inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2016-2017 Salvador E. Tropea <salvador en inti.gob.ar> ----
---- Copyright (c) 2016-2017 Instituto Nacional de Tecnología Industrial ----
---- ----
---- This file can be distributed under the terms of the GPL 2.0 license ----
---- or newer. ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: Devices (Package) ----
---- File name: capsense_pkg.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: None ----
---- Dependencies: IEEE.std_logic_1164 ----
---- Target FPGA: iCE40HX4K-TQ144 ----
---- Language: VHDL ----
---- Wishbone: None ----
---- Synthesis tools: iCEcube2 2016.02 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package Devices is
component CapSense is
generic(
N : integer range 2 to 8);
port(
clk_i : in std_logic; -- System clock
rst_i : in std_logic; -- System reset
ena_i : in std_logic; -- Frequency used to sample the buttons
start_i : in std_logic; -- Start a sampling sequence
buttons_i : in std_logic_vector(N-1 downto 0); -- Input pins
but_oe_o : out std_logic; -- Cap. discharge
sampled_o : out std_logic_vector(N-1 downto 0); -- Last sample result
debug_o : out std_logic_vector(N-1 downto 0) -- Used to measure the button timing
);
end component CapSense;
component CapSense_Sys is
generic(
DIRECT : std_logic:='1';
FREQUENCY : integer:=24;
N : integer range 2 to 8:=4);
port(
clk_i : in std_logic; -- System clock
rst_i : in std_logic; -- System reset
capsense_i : in std_logic_vector(N-1 downto 0); -- Input pins
capsense_o : out std_logic; -- Cap. discharge
buttons_o : out std_logic_vector(N-1 downto 0); -- Last sample result
debug_o : out std_logic_vector(N-1 downto 0) -- Used to measure the button timing
);
end component CapSense_Sys;
end package Devices;