diff --git a/Data_Base/STM32_Prog_DB_0x413.xml b/Data_Base/STM32_Prog_DB_0x413.xml index cd2add6..7c4de78 100644 --- a/Data_Base/STM32_Prog_DB_0x413.xml +++ b/Data_Base/STM32_Prog_DB_0x413.xml @@ -10,7 +10,17 @@ ARM 32-bit Cortex-M4 based device - + + + + + + + + + + + @@ -42,9 +52,43 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE - + + + + + Single + 0x4 + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + diff --git a/Data_Base/STM32_Prog_DB_0x451.xml b/Data_Base/STM32_Prog_DB_0x451.xml index 7611df8..d7e75da 100644 --- a/Data_Base/STM32_Prog_DB_0x451.xml +++ b/Data_Base/STM32_Prog_DB_0x451.xml @@ -11,40 +11,40 @@ - + - + - + - + - + - + - + - + @@ -62,13 +62,23 @@ - + - + - + + + + + + + + + + + @@ -105,7 +115,7 @@ - + Single @@ -123,7 +133,7 @@ - + Dual @@ -152,7 +162,7 @@ - + Single @@ -170,7 +180,7 @@ - + Dual @@ -207,7 +217,7 @@ 0xFF RWE - + Single @@ -225,7 +235,7 @@ - + Dual diff --git a/Data_Base/STM32_Prog_DB_0x456.xml b/Data_Base/STM32_Prog_DB_0x456.xml index 9ba008f..30def70 100644 --- a/Data_Base/STM32_Prog_DB_0x456.xml +++ b/Data_Base/STM32_Prog_DB_0x456.xml @@ -5,7 +5,7 @@ STMicroelectronics MCU Cortex-M0+ - STM32G051/STM32G061 + STM32G05x/STM32G06x STM32G0 ARM 32-bit Cortex-M0+ based device diff --git a/Data_Base/STM32_Prog_DB_0x459.xml b/Data_Base/STM32_Prog_DB_0x459.xml new file mode 100644 index 0000000..0276d6e --- /dev/null +++ b/Data_Base/STM32_Prog_DB_0x459.xml @@ -0,0 +1,702 @@ + + + + 0x459 + STMicroelectronics + MCU + + Cortex-M0+ + STM32U0xx + STM32U0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + This bitfield contains the VDD supply level threshold that activates/releases the reset + 0x8 + 0x3 + RW + + BOR level 0, reset level threshold around 1.7 V + BOR level 1, reset level threshold around 2.0 V + BOR level 2, reset level threshold around 2.2 V + BOR level 3, reset level threshold around 2.5 V + BOR level 4, reset level threshold around 2.8 V + + + + + + + User Configuration + + + + + nRST_STOP + + 0xD + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + + + nRST_STDBY + + 0xE + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + + + nRST_SHDW + + 0xF + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + RAM_PARITY_CHECK + + 0x16 + 0x1 + RW + + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + BKPSRAM_HW_ERASE_DISABLE + + 0x17 + 0x1 + RW + + Backup SRAM is erased on system reset + Backup SRAM content is kept when a system reset occurs + + + + NBOOT_SEL + + 0x18 + 0x1 + RW + + BOOT0 pin (legacy mode) + NBOOT0 option bit + + + + nBOOT1 + + 0x19 + 0x1 + RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 1, otherwise system memory + + + + nBOOT0 + + 0x1A + 0x1 + RW + + nBOOT0=0 + nBOOT0=1 + + + + NRST_MODE + + 0x1B + 0x2 + RW + + Reserved + Reset input only + Standard GPIO:only internal RESET is possible + Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode + + + + BDRST + + 0x15 + 0x1 + RW + + Backup domain not reset on shutdown exit + Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit + + + + IRHEN + + 0x1D + 0x1 + RW + + Internal resets are propagated as simple pulse on NRST pin + Internal resets drives NRST pin low until it is seen as low level + + + + + + + Write Protection + + + + + WRP1A_STRT + Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1A_END + End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 + 0x7 + RW + + + + + + + + + WRP1B_STRT + Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1B_END + End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect + 0x10 + 0x7 + RW + + + + + + + + FLASH security + + + + + HDP1_PEND + Securable memory area size + 0x0 + 0x7 + RW + + + + BOOT_lOCK + Used to force boot from user area + 0x10 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from Main Flash memory + + + + HDP1EN + Hide protection area enable + 0x18 + 0x8 + RW + + no HDP area + or any value other than 0xB4 HDP area enabled + + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + This bitfield contains the VDD supply level threshold that activates/releases the reset + 0x8 + 0x3 + RW + + BOR level 0, reset level threshold around 1.7 V + BOR level 1, reset level threshold around 2.0 V + BOR level 2, reset level threshold around 2.2 V + BOR level 3, reset level threshold around 2.5 V + BOR level 4, reset level threshold around 2.8 V + + + + + + + User Configuration + + + + + nRST_STOP + + 0xD + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + + + nRST_STDBY + + 0xE + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + + + nRST_SHDW + + 0xF + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + RAM_PARITY_CHECK + + 0x16 + 0x1 + RW + + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + BKPSRAM_HW_ERASE_DISABLE + + 0x17 + 0x1 + RW + + Backup SRAM is erased on system reset + Backup SRAM content is kept when a system reset occurs + + + + NBOOT_SEL + + 0x18 + 0x1 + RW + + BOOT0 pin (legacy mode) + NBOOT0 option bit + + + + nBOOT1 + + 0x19 + 0x1 + RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 1, otherwise system memory + + + + nBOOT0 + + 0x1A + 0x1 + RW + + nBOOT0=0 + nBOOT0=1 + + + + NRST_MODE + + 0x1B + 0x2 + RW + + Reserved + Reset input only + Standard GPIO:only internal RESET is possible + Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode + + + + BDRST + + 0x15 + 0x1 + RW + + Backup domain not reset on shutdown exit + Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit + + + + IRHEN + + 0x1D + 0x1 + RW + + Internal resets are propagated as simple pulse on NRST pin + Internal resets drives NRST pin low until it is seen as low level + + + + + + + Write Protection + + + + + WRP1A_STRT + Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1A_END + End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 + 0x7 + RW + + + + + + + + + WRP1B_STRT + Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1B_END + End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect + 0x10 + 0x7 + RW + + + + + + + + FLASH security + + + + + HDP1_PEND + Securable memory area size + 0x0 + 0x7 + RW + + + + BOOT_lOCK + Used to force boot from user area + 0x10 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from Main Flash memory + + + + HDP1EN + Hide protection area enable + 0x18 + 0x8 + RW + + no HDP area + or any value other than 0xB4 HDP area enabled + + + + + + + + + + + \ No newline at end of file diff --git a/Data_Base/STM32_Prog_DB_0x461.xml b/Data_Base/STM32_Prog_DB_0x461.xml index 163f9f8..22040b7 100644 --- a/Data_Base/STM32_Prog_DB_0x461.xml +++ b/Data_Base/STM32_Prog_DB_0x461.xml @@ -10,9 +10,67 @@ ARM 32-bit Cortex-M4 based device - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + + + + + + + + @@ -47,8 +105,8 @@ - - + + Dual 0x8 @@ -63,6 +121,64 @@ + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + @@ -186,15 +302,15 @@ No reset generated when entering Standby mode - - nRST_SHDW + + DualBank - 0xE + 0x15 0x1 RW - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode + 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 + 256 KB/512 KB Dual-bank Flash @@ -593,6 +709,17 @@ No reset generated + + DualBank + + 0x15 + 0x1 + RW + + 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 + 256 KB/512 KB Dual-bank Flash + + nRST_SHDW diff --git a/Data_Base/STM32_Prog_DB_0x466.xml b/Data_Base/STM32_Prog_DB_0x466.xml index d0bfaad..b542af2 100644 --- a/Data_Base/STM32_Prog_DB_0x466.xml +++ b/Data_Base/STM32_Prog_DB_0x466.xml @@ -42,6 +42,11 @@ + + + + + @@ -99,7 +104,7 @@ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE - + @@ -137,6 +142,18 @@ + + + + + Single + 0x8 + + + + + + diff --git a/Data_Base/STM32_Prog_DB_0x467.xml b/Data_Base/STM32_Prog_DB_0x467.xml index 063f370..908ce38 100644 --- a/Data_Base/STM32_Prog_DB_0x467.xml +++ b/Data_Base/STM32_Prog_DB_0x467.xml @@ -731,6 +731,7 @@ 0x0 0x8 RW + SEC_SIZE2 @@ -1216,6 +1217,7 @@ 0x0 0x8 RW + SEC_SIZE2 diff --git a/Data_Base/STM32_Prog_DB_0x468.xml b/Data_Base/STM32_Prog_DB_0x468.xml index a8b7dcd..e4b7833 100644 --- a/Data_Base/STM32_Prog_DB_0x468.xml +++ b/Data_Base/STM32_Prog_DB_0x468.xml @@ -415,8 +415,8 @@ 0x1 RW - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level @@ -740,8 +740,8 @@ 0x1 RW - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level diff --git a/Data_Base/STM32_Prog_DB_0x469.xml b/Data_Base/STM32_Prog_DB_0x469.xml index c3f9324..b8e13ce 100644 --- a/Data_Base/STM32_Prog_DB_0x469.xml +++ b/Data_Base/STM32_Prog_DB_0x469.xml @@ -47,28 +47,28 @@ - + - + - + - + - + - + @@ -762,8 +762,8 @@ 0x1 RW - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level @@ -1152,33 +1152,10 @@ - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - + PCROP Protection (Bank 2) @@ -1301,8 +1278,40 @@ + + + + + Secure Protection (Bank 1) + + + + + SEC_SIZE1 + sets the number of pages used in the bank 1 securable area + 0x0 + 0x8 + RW + + + BOOT_LOCK + Unique boot entry point + 0x10 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level + + + + + + + + - Secure Protection + Secure Protection (Bank 2) diff --git a/Data_Base/STM32_Prog_DB_0x472.xml b/Data_Base/STM32_Prog_DB_0x472.xml index 44d7773..7ea6127 100644 --- a/Data_Base/STM32_Prog_DB_0x472.xml +++ b/Data_Base/STM32_Prog_DB_0x472.xml @@ -677,38 +677,7 @@ - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - + @@ -1018,6 +987,38 @@ + + + + + HDP2EN + Hide protection second area enable + 0x1F + 0x1 + RW + + No HDP area 2 + HDP second area is enabled + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x7 + RW + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x7 + RW + + + + @@ -1782,7 +1783,7 @@ - + Read Out Protection @@ -2848,38 +2849,6 @@ - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - @@ -2959,6 +2928,38 @@ + + + + + HDP2EN + Hide protection second area enable + 0x1F + 0x1 + RW + + No HDP area 2 + HDP second area is enabled + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x7 + RW + + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x7 + RW + + + + Write Protection 1 diff --git a/Data_Base/STM32_Prog_DB_0x474.xml b/Data_Base/STM32_Prog_DB_0x474.xml index ebc2c3f..a2dd92e 100644 --- a/Data_Base/STM32_Prog_DB_0x474.xml +++ b/Data_Base/STM32_Prog_DB_0x474.xml @@ -218,7 +218,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -232,7 +232,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -252,9 +252,8 @@ R BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -270,9 +269,8 @@ W BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -962,7 +960,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -976,7 +974,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -995,10 +993,9 @@ 0x2 R - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -1013,10 +1010,9 @@ 0x2 W - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -1705,7 +1701,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -1719,7 +1715,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -1738,10 +1734,9 @@ 0x2 R - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -1756,10 +1751,9 @@ 0x2 W - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) diff --git a/Data_Base/STM32_Prog_DB_0x478.xml b/Data_Base/STM32_Prog_DB_0x478.xml new file mode 100644 index 0000000..9a6a8c4 --- /dev/null +++ b/Data_Base/STM32_Prog_DB_0x478.xml @@ -0,0 +1,3488 @@ + + + + 0x478 + STMicroelectronics + MCU + Cortex-M33 + STM32H533/523 + STM32H5 + ARM 32-bit Cortex-M33 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + Single + + + + + + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0xFF + RWE + + + + Single + 0x10 + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + W + disabled + enabled + + + + + + User Configuration + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in standby Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + R + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + R + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + W + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + W + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + + + + Boot Configuration + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + R + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + R + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + W + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + W + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress + 0x8 + 0x18 + R + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress. + 0x8 + 0x18 + W + + + + + + + + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + R + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + W + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data bank 1 sectors + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data bank 2 sectors + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + R + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + R + + + + + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + W + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + W + disabled + enabled + + + + + + User Configuration + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in standby Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + R + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + R + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + W + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + W + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + + + + Boot Configuration + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + R + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + R + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + W + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + W + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress + 0x8 + 0x18 + R + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress. + 0x8 + 0x18 + W + + + + + + + + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + R + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + W + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + + + + Flash data bank 1 sectors + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + + + + Flash data bank 2 sectors + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + R + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + R + + + + + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + W + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + W + + + + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + + Product state + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + R + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + + + PRODUCT_STATE + Life state code. + 0x8 + 0x8 + W + + Open + Provisioning, Debug partially opened (only non-secure) + iRoT-provisioned, Debug partially opened (only non-secure) + TZ-Closed, Debug partially opened (only non-secure) + Closed, Debug disabled, regression is possible + Locked + + + + + + + BOR Level + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + R + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + Brownout level option status bit. + 0x0 + 0x2 + W + + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + R + disabled + enabled + + + + + + + + BORH_EN + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off + 0x2 + 0x1 + W + disabled + enabled + + + + + + User Configuration + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDD_HSLV + VDD I/O high-speed at low-voltage status bit. + 0x10 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + R + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IO_VDDIO2_HSLV + High-speed IO at low VDDIO2 voltage configuration bit + 0x11 + 0x1 + W + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + R + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STOP + Stop mode freeze option status bit. + 0x14 + 0x1 + W + Independent watchdog frozen in system Stop mode + Independent watchdog keep running in system Stop mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + R + Independent watchdog frozen in system standby mode + Independent watchdog keep running in system standby mode. + + + + + + + + IWDG_STDBY + Standby mode freeze option status bit. + 0x15 + 0x1 + W + Independent watchdog frozen in system standby mode + Independent watchdog keep running in standby Stop mode. + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + R + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + BOOT_UBE + Unique boot entry control, selects either ST or OEM iRoT for secure boot. + 0x16 + 0x8 + W + + OEM-iRoT (user flash) selected + ST-iRoT (system flash) selected + + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + R + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + SWAP_BANK + Bank swapping option status bit. + 0x1F + 0x1 + W + bank 1 and bank 2 not swapped + bank 1 and bank 2 swapped + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + R + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + IWDG_SW + IWDG control mode option status bit. + 0x3 + 0x1 + W + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + R + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STOP + Core domain Stop entry reset option status bit. + 0x6 + 0x1 + W + a reset is generated when entering Stop or Stop2 mode on core domain + no reset generated when entering Stop or Stop2 mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + R + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + + + NRST_STDBY + Core domain Standby entry reset option status bit. + 0x7 + 0x1 + W + a reset is generated when entering Standby mode on core domain + no reset generated when entering Standby mode on core domain + + + + + + User Configuration 2 + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + R + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + R + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + R + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + R + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + R + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + R + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + + + TZEN + Trust Zone Enable configuration bits + 0x18 + 0x8 + W + + Trust zone disabled + Trust zone enabled + + + + SRAM2_ECC + ECC in SRAM2 region configuration bit + 0x6 + 0x1 + W + + SRAM2 ECC check enabled + SRAM2 ECC check disabled + + + + SRAM3_ECC + ECC in SRAM3 region configuration bit + 0x5 + 0x1 + W + + SRAM3 ECC check enabled + SRAM3 ECC check disabled + + + + BKPRAM_ECC + ECC in BKPRAM region configuration bit + 0x4 + 0x1 + W + + BKPRAM ECC check enabled + BKPRAM ECC check disabled + + + + SRAM2_RST + SRAM2 Erase when system reset + 0x3 + 0x1 + W + + SRAM2 erase when system reset + SRAM2 not erased when a system reset occurs + + + + SRAM1_3_RST + SRAM1 and SRAM3 erase upon system reset + 0x2 + 0x1 + W + + SRAM1 and SRAM3 erased when a system reset occurs + SRAM1 and SRAM3 not erased when a system reset occurs + + + + + + + Boot Configuration + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + R + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + R + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + NSBOOTADD + Non secure unique boot entry address + 0x8 + 0x18 + W + + + + NSBOOT_LOCK + A field locking the values of SWAP_BANK, and NSBOOTADD settings + 0x0 + 0x8 + W + + The SWAP_BANK and NSBOOTADD can still be modified following their individual rules. + The NSBOOTADD is frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + R + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress + 0x8 + 0x18 + R + + + + + + + + + SECBOOT_LOCK + A field locking the values of UBE, SWAP_BANK, and SECBOOTADD settings. + 0x0 + 0x8 + W + + The BOOT_UBE, SWAP_BANK and SECBOOTADD can still be modified following their individual rules. + The BOOT_UBE and SECBOOTADD are frozen. SWAP_BANK can only be modified with TZEN set to 0xC3 (disabled). + + + + SECBOOTADD + Unique Boot Entry Secure Adress. + 0x8 + 0x18 + W + + + + + + + Bank1 - Flash watermark area definition + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + R + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM1_STRT + Bank 1 security WM area 1 start sector + 0x0 + 0x5 + W + + + + SECWM1_END + Bank 1 security WM area 1 end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 1 + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn1 + Bank 1 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + OTP write protection + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + R + + + + + + + + + LOCKBL + OTP Block Lock + 0x0 + 0x20 + W + + + + + + + Flash data bank 1 sectors + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + R + + + + + + + + + EDATA1_EN + Bank1 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA1_STRT + EDATA1_STRT contains the start sectors of the Flash high-cycle data area in Bank1. + 0x0 + 0x3 + W + + + + + + + Flash HDP bank 1 + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + R + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + R + + + + + + + + + HDP1_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x5 + W + + + + HDP1_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x5 + W + + + + + + + + + + Bank2 - Flash watermark area definition + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + R + + + + + + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x5 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x5 + W + + + + + + + Write sector group protection 2 + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + R + + + + + + + + + WRPSGn2 + Bank 2 sector group protection option status byte + 0x0 + 0x8 + W + + + + + + + Flash data bank 2 sectors + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + R + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + R + + + + + + + + + EDATA2_EN + Bank2 Flash high-cycle data enable + 0xF + 0x1 + W + + No Flash high-cycle data area + Flash high-cycle data is used + + + + EDATA2_STRT + EDATA2_STRT contains the start sectors of the Flash high-cycle data area in Bank2. + 0x0 + 0x3 + W + + + + + + + Flash HDP bank 2 + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + R + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + R + + + + + + + + + HDP2_STRT + HDP barrier start set in number of 8kb sectors + 0x0 + 0x7 + W + + + + HDP2_END + HDP barrier end set in number of 8kb sectors + 0x10 + 0x7 + W + + + + + + + + + + \ No newline at end of file diff --git a/Data_Base/STM32_Prog_DB_0x479.xml b/Data_Base/STM32_Prog_DB_0x479.xml index 3372db0..f62156e 100644 --- a/Data_Base/STM32_Prog_DB_0x479.xml +++ b/Data_Base/STM32_Prog_DB_0x479.xml @@ -483,8 +483,8 @@ 0x1 RW - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level @@ -858,8 +858,8 @@ 0x1 RW - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level + Boot based on the pad/option bit configuration + Boot will be done from user flash only, whatever the RDP level diff --git a/Data_Base/STM32_Prog_DB_0x481.xml b/Data_Base/STM32_Prog_DB_0x481.xml index ba741a6..6e4d1bb 100644 --- a/Data_Base/STM32_Prog_DB_0x481.xml +++ b/Data_Base/STM32_Prog_DB_0x481.xml @@ -112,7 +112,23 @@ - + + + + Single + 0x10 + + + + + + + + + + + + Single diff --git a/Data_Base/STM32_Prog_DB_0x482.xml b/Data_Base/STM32_Prog_DB_0x482.xml index 276129c..cd017b5 100644 --- a/Data_Base/STM32_Prog_DB_0x482.xml +++ b/Data_Base/STM32_Prog_DB_0x482.xml @@ -57,40 +57,22 @@ - - - - - + - - - - - - + - - - - - - + - - - - - + @@ -98,39 +80,32 @@ - + - + - + - + - - - - + - + - - - - - + @@ -145,7 +120,7 @@ 0xFF RWE - + Single @@ -155,7 +130,7 @@ - + Single @@ -177,17 +152,6 @@ - - - - Single - 0x10 - - - - - - @@ -195,7 +159,7 @@ 0x10 - + @@ -231,17 +195,6 @@ - - - - Single - 0x10 - - - - - - @@ -249,7 +202,7 @@ 0x10 - + @@ -293,7 +246,34 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - + + + + Single + 0x4 + + + + + + + + + + Dual + 0x4 + + + + + + + + + + + + Single @@ -304,7 +284,7 @@ - + Single @@ -364,7 +344,7 @@ Configuration RW - + @@ -671,15 +651,7 @@ - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 @@ -687,15 +659,7 @@ RW - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - + WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 @@ -719,33 +683,17 @@ - - WRP1B_PSTRT - Bank 1 WPR second area "B" start page - 0x0 - 0x7 - RW - - - + WRP1B_PSTRT - Bank 1 WPR second area "B" start page + Bank 1 WPR first area "B" start page 0x0 0x7 RW - - WRP1B_PEND - Bank 1 WPR second area "B" end page - 0x10 - 0x7 - RW - - - + WRP1B_PEND - Bank 1 WPR second area "B" end page + Bank 1 WPR first area "B" end page 0x10 0x7 RW @@ -753,7 +701,7 @@ UNLOCK_1B - Bank 1 WPR second area B unlock + Bank 1 WPR first area B unlock 0x1F 0x1 RW @@ -773,15 +721,7 @@ - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 @@ -789,15 +729,15 @@ RW - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 + + WRP2A_PSTRT + Bank 2 WPR first area "A" start page + 0x0 0x7 RW - + - + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 @@ -805,7 +745,15 @@ RW - + + WRP2A_PEND + Bank 2 WPR first area "A" end page + 0x10 + 0x7 + RW + + + UNLOCK_2A Bank 2 WPR first area A unlock 0x1F @@ -821,41 +769,41 @@ - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - + - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - + - + WRP2B_PEND - Bank 2 WPR second area "B" end page - 0x10 - 0x7 - RW - + Bank 2 WPR first area "B" end page + 0x10 + 0x7 + RW + - + WRP2B_PEND - Bank 2 WPR second area "B" end page + Bank 2 WPR first area "B" end page 0x10 0x7 RW - + - + UNLOCK_2B - Bank 2 WPR second area B unlock + Bank 2 WPR first area B unlock 0x1F 0x1 RW @@ -869,7 +817,7 @@ - + @@ -1037,8 +985,8 @@ 0x1 RW - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data + Single bank Flash with contiguous address in bank 1 + Dual-bank Flash with contiguous addresses @@ -1206,15 +1154,7 @@ - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - + SECWM1_PSTRT Start page of first secure area 0x0 @@ -1222,15 +1162,7 @@ RW - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - + SECWM1_PEND End page of first secure area 0x10 @@ -1243,15 +1175,7 @@ - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - + HDP1_PEND End page of first hide protection area 0x10 @@ -1278,15 +1202,7 @@ - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 @@ -1294,15 +1210,7 @@ RW - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - + WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 @@ -1326,33 +1234,17 @@ - + WRP1B_PSTRT - Bank 1 WPR second area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR second area "B" start page + Bank 1 WPR first area "B" start page 0x0 0x7 RW - - WRP1B_PEND - Bank 1 WPR second area "B" end page - 0x10 - 0x7 - RW - - - + WRP1B_PEND - Bank 1 WPR second area "B" end page + Bank 1 WPR first area "B" end page 0x10 0x7 RW @@ -1360,7 +1252,7 @@ UNLOCK_1B - Bank 1 WPR second area B unlock + Bank 1 WPR first area B unlock 0x1F 0x1 RW @@ -1380,15 +1272,7 @@ - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - + SECWM2_PSTRT Start page of second secure area 0x0 @@ -1396,35 +1280,35 @@ RW - + SECWM2_PEND End page of second secure area 0x10 0x7 RW - + - + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x7 + RW + + + SECWM2_PEND End page of second secure area 0x10 0x7 RW - + - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - HDP2_PEND End page of second hide protection area @@ -1433,7 +1317,7 @@ RW - + HDP2EN Hide protection second area enable 0x1F @@ -1444,7 +1328,7 @@ HDP second area is enabled - + @@ -1455,15 +1339,7 @@ - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 @@ -1471,23 +1347,31 @@ RW - + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW - + - + + WRP2A_PSTRT + Bank 2 WPR first area "A" start page + 0x0 + 0x7 + RW + + + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW - + - + UNLOCK_2A Bank 2 WPR first area A unlock 0x1F @@ -1503,41 +1387,41 @@ - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - + - - WRP2B_PSTRT - Bank 2 WPR second area "B" start page - 0x0 + + WRP2B_PEND + Bank 2 WPR first area "B" end page + 0x10 0x7 RW - - WRP2B_PEND - Bank 2 WPR second area "B" end page - 0x10 + + WRP2B_PSTRT + Bank 2 WPR first area "B" start page + 0x0 0x7 RW - + - + WRP2B_PEND - Bank 2 WPR second area "B" end page + Bank 2 WPR first area "B" end page 0x10 0x7 RW - + - + UNLOCK_2B - Bank 2 WPR second area B unlock + Bank 2 WPR first area B unlock 0x1F 0x1 RW @@ -1551,7 +1435,7 @@ - + @@ -1719,8 +1603,8 @@ 0x1 RW - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data + Single bank Flash with contiguous address in bank 1 + Dual-bank Flash with contiguous addresses @@ -1921,15 +1805,7 @@ - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - + SECWM1_PSTRT Start page of first secure area 0x0 @@ -1937,15 +1813,7 @@ RW - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - + SECWM1_PEND End page of first secure area 0x10 @@ -1958,15 +1826,7 @@ - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - + HDP1_PEND End page of first hide protection area 0x10 @@ -1993,15 +1853,7 @@ - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 @@ -2009,15 +1861,7 @@ RW - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - + WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 @@ -2041,33 +1885,17 @@ - + WRP1B_PSTRT - Bank 1 WPR second area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR second area "B" start page + Bank 1 WPR first area "B" start page 0x0 0x7 RW - - WRP1B_PEND - Bank 1 WPR second area "B" end page - 0x10 - 0x7 - RW - - - + WRP1B_PEND - Bank 1 WPR second area "B" end page + Bank 1 WPR first area "B" end page 0x10 0x7 RW @@ -2075,7 +1903,7 @@ UNLOCK_1B - Bank 1 WPR second area B unlock + Bank 1 WPR first area B unlock 0x1F 0x1 RW @@ -2095,51 +1923,43 @@ - + SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW - + - + SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW - + - + SECWM2_PEND End page of second secure area 0x10 0x7 RW - + - + SECWM2_PEND End page of second secure area 0x10 0x7 RW - + - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - HDP2_PEND End page of second hide protection area @@ -2148,7 +1968,7 @@ RW - + HDP2EN Hide protection second area enable 0x1F @@ -2170,39 +1990,39 @@ - + WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW - + - + WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW - + - + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW - + - + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW - + - + UNLOCK_2A Bank 2 WPR first area A unlock 0x1F @@ -2218,41 +2038,41 @@ - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - + - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - + - + WRP2B_PEND - Bank 2 WPR second area "B" end page + Bank 2 WPR first area "B" end page 0x10 0x7 RW - + - + WRP2B_PEND - Bank 2 WPR second area "B" end page + Bank 2 WPR first area "B" end page 0x10 0x7 RW - + - + UNLOCK_2B - Bank 2 WPR second area B unlock + Bank 2 WPR first area B unlock 0x1F 0x1 RW @@ -2433,8 +2253,8 @@ 0x1 RW - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data + Single bank Flash with contiguous address in bank 1 + Dual-bank Flash with contiguous addresses @@ -2548,7 +2368,7 @@ - + SECBOOTADD0 Secure boot base address 0 0x7 @@ -2561,7 +2381,7 @@ - + BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 @@ -2580,15 +2400,7 @@ - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - + SECWM1_PSTRT Start page of first secure area 0x0 @@ -2596,15 +2408,7 @@ RW - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - + SECWM1_PEND End page of first secure area 0x10 @@ -2617,15 +2421,7 @@ - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - + HDP1_PEND End page of first hide protection area 0x10 @@ -2633,7 +2429,7 @@ RW - + HDP1EN Hide protection first area enable 0x1F @@ -2652,15 +2448,7 @@ - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 @@ -2668,15 +2456,7 @@ RW - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - + WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 @@ -2700,33 +2480,17 @@ - - WRP1B_PSTRT - Bank 1 WPR second area "B" start page - 0x0 - 0x7 - RW - - - + WRP1B_PSTRT - Bank 1 WPR second area "B" start page + Bank 1 WPR first area "B" start page 0x0 0x7 RW - + WRP1B_PEND - Bank 1 WPR second area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR second area "B" end page + Bank 1 WPR first area "B" end page 0x10 0x7 RW @@ -2751,60 +2515,52 @@ - + SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW - + - + SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW - + - + SECWM2_PEND - End page of second secure area + End page of second secure area 0x10 0x7 RW - + - + SECWM2_PEND End page of second secure area 0x10 0x7 RW - + - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - + HDP2_PEND End page of second hide protection area 0x10 0x7 RW - + - + HDP2EN Hide protection second area enable 0x1F @@ -2823,15 +2579,7 @@ - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - + WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 @@ -2839,23 +2587,31 @@ RW - + + WRP2A_PSTRT + Bank 2 WPR first area "A" start page + 0x0 + 0x7 + RW + + + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 - 0x7 + 0x7 RW - + - + WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW - + - + UNLOCK_2A Bank 2 WPR first area A unlock 0x1F @@ -2871,39 +2627,39 @@ - - WRP2B_PSTRT - Bank 2 WPR second area "B" start page - 0x0 - 0x7 - RW - - - + WRP2B_PSTRT - Bank 2 WPR second area "B" start page + Bank 2 WPR first area "B" start page 0x0 0x7 RW - - WRP2B_PEND - Bank 2 WPR second area "B" end page - 0x10 - 0x7 - RW - + + WRP2B_PSTRT + Bank 2 WPR first area "B" start page + 0x0 + 0x7 + RW + - + WRP2B_PEND - Bank 2 WPR second area "B" end page + Bank 2 WPR first area "B" end page 0x10 0x7 RW - + + WRP2B_PEND + Bank 2 WPR first area "B" end page + 0x10 + 0x7 + RW + + + UNLOCK_2B Bank 2 WPR second area B unlock 0x1F diff --git a/Data_Base/STM32_Prog_DB_0x484.xml b/Data_Base/STM32_Prog_DB_0x484.xml index c50d7d5..4a36ca2 100644 --- a/Data_Base/STM32_Prog_DB_0x484.xml +++ b/Data_Base/STM32_Prog_DB_0x484.xml @@ -5,60 +5,123 @@ STMicroelectronics MCU Cortex-M33 - STM32H5xx + STM32H56x/573 STM32H5 ARM 32-bit Cortex-M33 based device - - + + - - + + - + + - + + - + + + + + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + - - + + + - - + + @@ -71,24 +134,23 @@ 0xFF RWE - - - + + Single - + - + Single - + @@ -106,7 +168,7 @@ - + Dual @@ -122,7 +184,7 @@ - + Dual @@ -138,7 +200,7 @@ - + Dual @@ -154,7 +216,57 @@ + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + Data EEPROM @@ -162,8 +274,7 @@ The Data EEPROM memory block. It contains user data. 0xFF RWE - - + Single @@ -179,7 +290,7 @@ - + Single @@ -195,6 +306,39 @@ + + + + + Single + 0x10 + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + + @@ -222,7 +366,7 @@ Configuration RW - + @@ -281,9 +425,8 @@ R BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -299,9 +442,8 @@ W BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -311,7 +453,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -325,7 +467,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -929,7 +1071,7 @@ - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -937,7 +1079,7 @@ R - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -945,12 +1087,28 @@ R + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + R + + - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -958,7 +1116,7 @@ W - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -966,6 +1124,22 @@ W + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + W + + @@ -1236,7 +1410,7 @@ - + @@ -1295,9 +1469,8 @@ R BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -1313,9 +1486,8 @@ W BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -1325,7 +1497,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -1339,7 +1511,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -1943,7 +2115,7 @@ - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -1951,7 +2123,7 @@ R - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -1959,12 +2131,28 @@ R + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + R + + - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -1972,7 +2160,7 @@ W - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -1980,6 +2168,22 @@ W + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + W + + @@ -2307,10 +2511,9 @@ 0x2 R - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -2325,10 +2528,9 @@ 0x2 W - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) @@ -2338,7 +2540,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 R @@ -2352,7 +2554,7 @@ BORH_EN - Brownout high enable configuration bit + Brownout high enable configuration bit. Checked : BOR Level taken from BOR_LEV. Unchecked : BOR off 0x2 0x1 W @@ -3072,7 +3274,7 @@ - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -3080,7 +3282,7 @@ R - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -3088,12 +3290,28 @@ R + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + R + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + R + + - + SECWM2_STRT Bank 2 security WM area start sector 0x0 @@ -3101,7 +3319,7 @@ W - + SECWM2_END Bank 2 security WM area end sector 0x10 @@ -3109,6 +3327,22 @@ W + + SECWM2_STRT + Bank 2 security WM area start sector + 0x0 + 0x7 + W + + + + SECWM2_END + Bank 2 security WM area end sector + 0x10 + 0x7 + W + + diff --git a/Data_Base/STM32_Prog_DB_0x485.xml b/Data_Base/STM32_Prog_DB_0x485.xml new file mode 100644 index 0000000..77c3bd1 --- /dev/null +++ b/Data_Base/STM32_Prog_DB_0x485.xml @@ -0,0 +1,1204 @@ + + + + 0x485 + STMicroelectronics + MCU + Cortex-M7 + STM32H7RSxx + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x2 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Product State + + + + + PRODUCT_STATE + Virtual Product State + 0x0 + 0x8 + RW + + Open + Provisioning + Closed + Locked + + + + + + + + + + + + FLASH ROT programming + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + R + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + W + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + OTP write protection + + + + + OTPL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + OTPL + OTP Lock + 0x0 + 0x10 + W + + + + + + + Write Protection + + + + + WRPS + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + WRPS + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + + + + + Flash HDP bank + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + R + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + R + + + + + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + W + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + W + + + + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration1 + + + + + IWDG_HW + + 0x4 + 0x1 + R + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + R + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + R + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + R + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + R + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + R + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + IWDG_HW + + 0x4 + 0x1 + W + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + W + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + W + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + W + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + W + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + W + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + User Configuration 2 + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is selected + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is selected + + + + + + + + + + Product State + + + + + PRODUCT_STATE + Virtual Product State + 0x0 + 0x8 + RW + + Open + Provisioning + Closed + Locked + + + + + + + + + + + FLASH ROT programming + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + R + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + W + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + OTP write protection + + + + + OTPL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + OTPL + OTP Lock + 0x0 + 0x10 + W + + + + + + + Write Protection + + + + + WRPS + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + WRPS + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + Flash HDP bank + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + R + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + R + + + + + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + W + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + W + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration1 + + + + + IWDG_HW + + 0x4 + 0x1 + R + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + R + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + R + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + R + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + R + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + R + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + IWDG_HW + + 0x4 + 0x1 + W + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + W + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + W + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + W + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + W + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + W + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + User Configuration 2 + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is selected + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is selected + + + + + + + + + + \ No newline at end of file diff --git a/Data_Base/STM32_Prog_DB_0x485_swv.xml b/Data_Base/STM32_Prog_DB_0x485_swv.xml new file mode 100644 index 0000000..e96e3fb --- /dev/null +++ b/Data_Base/STM32_Prog_DB_0x485_swv.xml @@ -0,0 +1,1154 @@ + + + + 0x485 + STMicroelectronics + MCU + Cortex-M7 + STM32H7RSxx + STM32H7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + + + + + + + + + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x2 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + FLASH ROT programming + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + R + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + W + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + OTP write protection + + + + + OTPL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + OTPL + OTP Lock + 0x0 + 0x10 + W + + + + + + + Write Protection + + + + + WRPS + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + WRPS + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + + + + + Flash HDP bank + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + R + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + R + + + + + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + W + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + W + + + + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration1 + + + + + IWDG_HW + + 0x4 + 0x1 + R + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + R + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + R + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + R + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + R + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + R + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + IWDG_HW + + 0x4 + 0x1 + W + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + W + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + W + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + W + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + W + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + W + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + User Configuration 2 + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is selected + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is selected + + + + + + + + + + FLASH ROT programming + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + R + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + + + IROT_SELECT + iRoT selection + 0x18 + 0x8 + W + + OEM iRoT is selected at boot + ST iRoT is selected at boot + + + + + + + OTP write protection + + + + + OTPL + OTP Lock + 0x0 + 0x10 + R + + + + + + + + + OTPL + OTP Lock + 0x0 + 0x10 + W + + + + + + + Write Protection + + + + + WRPS + + 0x0 + 0x8 + R + + Write protection active + Write protection not active + + + + + + + + + WRPS + + 0x0 + 0x8 + W + + Write protection active + Write protection not active + + + + + + + Flash HDP bank + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + R + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + R + + + + + + + + + HDP_AREA_START + This option sets the start address that contains the last 256-byte block of the hide protection (HDP) area in user Flash area. + 0x0 + 0x9 + W + + + + HDP_AREA_END + This option sets the end address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. + 0x10 + 0x9 + W + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + R + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. + 0x2 + 0x2 + W + + BOR OFF, POR/PDR reset threshold level is applied + BOR Level 1, the threshold level is low (around 2.1 V) + BOR Level 2, the threshold level is medium (around 2.4 V) + BOR Level 3, the threshold level is high (around 2.7 V) + + + + + + + User Configuration1 + + + + + IWDG_HW + + 0x4 + 0x1 + R + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + R + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + R + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + R + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + R + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + R + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + R + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + R + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + + + IWDG_HW + + 0x4 + 0x1 + W + + IWDG watchdog is controlled by hardware + IWDG watchdog is controlled by software + + + + NRST_STOP + + 0x6 + 0x1 + W + + Independent WDG generates a reset if STOP mode is requested + Independent WDG does not generate a reset if STOP mode is requested + + + + NRST_STBY + + 0x7 + 0x1 + W + + Independent WDG generates a reset if STANDBY mode is requested + Independent WDG does not generate a reset if STANDBY mode is requested + + + + XSPI1_HSLV + + 0x8 + 0x1 + W + + I/O XSPIM_P1 High-Speed option disabled + I/O XSPIM_P1 High-Speed option enabled + + + + XSPI2_HSLV + + 0x9 + 0x1 + W + + I/O XSPIM_P2 High-Speed option disabled + I/O XSPIM_P2 High-Speed option enabled + + + + IWDG_FZ_STOP + + 0x11 + 0x1 + W + + Independent watchdog frozen in Stop mode + Independent watchdog keep running in Stop mode + + + + IWDG_FZ_SDBY + + 0x12 + 0x1 + W + + Independent watchdog frozen in Standby mode + Independent watchdog keep running in Standby mode + + + + VDDIO_HSLV + + 0x1D + 0x1 + W + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + + + + + + ITCM RAM Protection + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + R + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + + + ITCM_AXI_SHARE + + 0x0 + 0x3 + W + + ITCM 64 Kbytes + ITCM 128 Kbytes + ITCM 192 Kbytes + ITCM 64 Kbytes + + + + + + + DTCM RAM Protection + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + R + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + + + DTCM_AXI_SHARE + + 0x4 + 0x3 + W + + DTCM 64 Kbytes + DTCM 128 Kbytes + DTCM 192 Kbytes + DTCM 64 Kbytes + + + + + + + User Configuration 2 + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + R + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + ECC_ON_SRAM + + 0x8 + 0x1 + W + + ECC_ON_SRAM disabled + ECC_ON_SRAM enabled + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + R + + I3C is selected + I2C is selected + + + + + + + + + I2C_NI3C + + 0x9 + 0x1 + W + + I3C is selected + I2C is selected + + + + + + + + + + \ No newline at end of file diff --git a/Data_Base/STM32_Prog_DB_0x489.xml b/Data_Base/STM32_Prog_DB_0x489.xml new file mode 100644 index 0000000..29c1c59 --- /dev/null +++ b/Data_Base/STM32_Prog_DB_0x489.xml @@ -0,0 +1,706 @@ + + + + 0x489 + STMicroelectronics + MCU + + Cortex-M0+ + STM32U0xx + STM32U0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + This bitfield contains the VDD supply level threshold that activates/releases the reset + 0x8 + 0x3 + RW + + BOR level 0, reset level threshold around 1.7 V + BOR level 1, reset level threshold around 2.0 V + BOR level 2, reset level threshold around 2.2 V + BOR level 3, reset level threshold around 2.5 V + BOR level 4, reset level threshold around 2.8 V + + + + + + + User Configuration + + + + + nRST_STOP + + 0xD + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + + + nRST_STDBY + + 0xE + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + + + nRST_SHDW + + 0xF + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + RAM_PARITY_CHECK + + 0x16 + 0x1 + RW + + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + BKPSRAM_HW_ERASE_DISABLE + + 0x17 + 0x1 + RW + + Backup SRAM is erased on system reset + Backup SRAM content is kept when a system reset occurs + + + + NBOOT_SEL + + 0x18 + 0x1 + RW + + BOOT0 pin (legacy mode) + NBOOT0 option bit + + + + nBOOT1 + + 0x19 + 0x1 + RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 1, otherwise system memory + + + + nBOOT0 + + 0x1A + 0x1 + RW + + nBOOT0=0 + nBOOT0=1 + + + + NRST_MODE + + 0x1B + 0x2 + RW + + Reserved + Reset input only + Standard GPIO:only internal RESET is possible + Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode + + + + BDRST + + 0x15 + 0x1 + RW + + Backup domain not reset on shutdown exit + Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit + + + + IRHEN + + 0x1D + 0x1 + RW + + Internal resets are propagated as simple pulse on NRST pin + Internal resets drives NRST pin low until it is seen as low level + + + + + + + Write Protection + + + + + WRP1A_STRT + Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1A_END + End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 + 0x7 + RW + + + + + + + + + WRP1B_STRT + Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1B_END + End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect + 0x10 + 0x7 + RW + + + + + + + + FLASH security + + + + + HDP1_PEND + Securable memory area size + 0x0 + 0x7 + RW + + + + BOOT_lOCK + Used to force boot from user area + 0x10 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from Main Flash memory + + + + HDP1EN + Hide protection area enable + 0x18 + 0x8 + RW + + no HDP area + or any value other than 0xB4 HDP area enabled + + + + + + + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + + + + + + BOR Level + + + + + BOR_LEV + This bitfield contains the VDD supply level threshold that activates/releases the reset + 0x8 + 0x3 + RW + + BOR level 0, reset level threshold around 1.7 V + BOR level 1, reset level threshold around 2.0 V + BOR level 2, reset level threshold around 2.2 V + BOR level 3, reset level threshold around 2.5 V + BOR level 4, reset level threshold around 2.8 V + + + + + + + User Configuration + + + + + nRST_STOP + + 0xD + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + + + nRST_STDBY + + 0xE + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + + + nRST_SHDW + + 0xF + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independant watchdog + Software independant watchdog + + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + + + RAM_PARITY_CHECK + + 0x16 + 0x1 + RW + + RAM_PARITY_CHECK enable + RAM_PARITY_CHECK disable + + + + BKPSRAM_HW_ERASE_DISABLE + + 0x17 + 0x1 + RW + + Backup SRAM is erased on system reset + Backup SRAM content is kept when a system reset occurs + + + + NBOOT_SEL + + 0x18 + 0x1 + RW + + BOOT0 pin (legacy mode) + NBOOT0 option bit + + + + nBOOT1 + + 0x19 + 0x1 + RW + + Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 1, otherwise system memory + + + + nBOOT0 + + 0x1A + 0x1 + RW + + nBOOT0=0 + nBOOT0=1 + + + + NRST_MODE + + 0x1B + 0x2 + RW + + Reserved + Reset input only + Standard GPIO:only internal RESET is possible + Bidirectional reset:The NRST pin is configured in reset input/output (legacy) mode + + + + BDRST + + 0x15 + 0x1 + RW + + Backup domain not reset on shutdown exit + Reset of backup domaine(RTC registers and backup registers)forsed on shutdown exit + + + + IRHEN + + 0x1D + 0x1 + RW + + Internal resets are propagated as simple pulse on NRST pin + Internal resets drives NRST pin low until it is seen as low level + + + + + + + Write Protection + + + + + WRP1A_STRT + Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1A_END + End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect. + 0x10 + 0x7 + RW + + + + + + + + + WRP1B_STRT + Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect + 0x0 + 0x7 + RW + + + + WRP1B_END + End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect + 0x10 + 0x7 + RW + + + + + + + + FLASH security + + + + + HDP1_PEND + Securable memory area size + 0x0 + 0x7 + RW + + + + BOOT_lOCK + Used to force boot from user area + 0x10 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from Main Flash memory + + + + HDP1EN + Hide protection area enable + 0x18 + 0x8 + RW + + no HDP area + or any value other than 0xB4 HDP area enabled + + + + + + + + + + + \ No newline at end of file diff --git a/Data_Base/STM32_Prog_DB_0x492.xml b/Data_Base/STM32_Prog_DB_0x492.xml index 5d79b7b..8fa858f 100644 --- a/Data_Base/STM32_Prog_DB_0x492.xml +++ b/Data_Base/STM32_Prog_DB_0x492.xml @@ -93,7 +93,7 @@ 0xFF RWE - + Single diff --git a/Programmer/ExternalLoader/MX25UW25645G_NUCLEO-H7S3L8.stldr b/Programmer/ExternalLoader/MX25UW25645G_NUCLEO-H7S3L8.stldr new file mode 100644 index 0000000..007e151 Binary files /dev/null and b/Programmer/ExternalLoader/MX25UW25645G_NUCLEO-H7S3L8.stldr differ diff --git a/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK-SFIx.stldr b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK-SFIx.stldr new file mode 100644 index 0000000..314804d Binary files /dev/null and b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK-SFIx.stldr differ diff --git a/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1-SFIx.stldr b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1-SFIx.stldr new file mode 100644 index 0000000..d990861 Binary files /dev/null and b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1-SFIx.stldr differ diff --git a/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1.stldr b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1.stldr new file mode 100644 index 0000000..b87039c Binary files /dev/null and b/Programmer/ExternalLoader/MX66UW1G45G_STM32H7S78-DK_XSPIM1.stldr differ diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x413.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x413.xml new file mode 100644 index 0000000..3d3fe38 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x413.xml @@ -0,0 +1,241 @@ + + + + 0x413 + STMicroelectronics + MCU + Cortex-M4 + STM32F405xx/F407xx/F415xx/F417xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x0 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0xC + RW + + Write protection active + Write protection not active + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x415.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x415.xml new file mode 100644 index 0000000..90aac95 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x415.xml @@ -0,0 +1,576 @@ + + + + 0x415 + STMicroelectronics + MCU + Cortex-M4 + STM32L4x1/STM32L475xx/STM32L476xx/STM32L486xx + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + BFB2 + + 0x14 + 0x1 + RW + + Dual-bank boot disable + Dual-bank boot enable + + 0x0 + + + DualBank + + 0x15 + 0x1 + RW + + 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 + 256 KB/512 KB Dual-bank Flash + + 0x1 + + + nBOOT1 + + 0x17 + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + SRAM2_PE + + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + + 0x1B + 0x1 + RW + + nBOOT0 = 0 + nBOOT0 = 1 + + 0x1 + + + + + + PCROP Protection (Bank 1) + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Write Protection (Bank 1) + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the first page of the Bank 1 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + PCROP Protection (Bank 2) + + + + + PCROP2_STRT + Flash Bank 2 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP2_END + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + + + + Write Protection (Bank 2) + + + + + WRP2A_STRT + The address of first page of the Bank 2 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP2A_END + The address of last page of the Bank 2 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP2B_STRT + The address of first page of the Bank 2 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP2B_END + The address of last page of the Bank 2 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x417.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x417.xml new file mode 100644 index 0000000..5ca939c --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x417.xml @@ -0,0 +1,264 @@ + + + + 0x417 + STMicroelectronics + MCU + Cortex-M0+ + STM32L05x/L06x/L010 + STM32L0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0x00 + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0x00 + RWE + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + WPRMOD + Sector protection mode selection option byte. + 0x8 + 0x1 + RW + + WRPx bit defines sector write protection + WRPx bit defines sector read/write (PCROP) protection + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x0 + 0x4 + RW + + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level 1, reset level threshold for 1.69 V-1.8 V + BOR Level 2, reset level threshold for 1.94 V-2.1 V + BOR Level 3, reset level threshold for 2.3 V-2.49 V + BOR Level 4, reset level threshold for 2.54 V-2.74 V + BOR Level 5, reset level threshold for 2.77 V-3.0 V + + 0x0 + + + + + + User Configuration + + + + + IWDG_SW + + 0x4 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x5 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x6 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + nBOOT1 + + 0x0F + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + + + + Write Protection + + + + + WRPOT1 + + 0x0 + 0x10 + RW + + Write protection not active + Write protection active + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x419.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x419.xml new file mode 100644 index 0000000..07ecf61 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x419.xml @@ -0,0 +1,510 @@ + + + + 0x419 + STMicroelectronics + MCU + Cortex-M4 + STM32F42xxx/F43xxx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + 0x0 + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + 0x0 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP1 + + 0x11 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP2 + + 0x12 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP3 + + 0x13 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP4 + + 0x14 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP5 + + 0x15 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP6 + + 0x16 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP7 + + 0x17 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP8 + + 0x18 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP9 + + 0x19 + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP10 + + 0x1A + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + nWRP11 + + 0x1B + 0x1 + RW + + Write protection active on selected sector + Write protection inactive on selected sector + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x421.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x421.xml new file mode 100644 index 0000000..d180085 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x421.xml @@ -0,0 +1,244 @@ + + + + 0x421 + STMicroelectronics + MCU + Cortex-M4 + STM32F446xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x8 + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x423.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x423.xml new file mode 100644 index 0000000..5c00ef1 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x423.xml @@ -0,0 +1,244 @@ + + + + 0x423 + STMicroelectronics + MCU + Cortex-M4 + STM32F401xB/C + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x6 + RW + + Write protection active + Write protection not active + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x425.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x425.xml new file mode 100644 index 0000000..833167e --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x425.xml @@ -0,0 +1,244 @@ + + + + 0x425 + STMicroelectronics + MCU + Cortex-M0+ + STM32L03x/L04x/L010 + STM32L0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0x00 + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0x00 + RWE + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + WPRMOD + Sector protection mode selection option byte. + 0x8 + 0x1 + RW + + WRPx bit defines sector write protection + WRPx bit defines sector read/write (PCROP) protection + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x0 + 0x4 + RW + + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level 1, reset level threshold for 1.69 V-1.8 V + BOR Level 2, reset level threshold for 1.94 V-2.1 V + BOR Level 3, reset level threshold for 2.3 V-2.49 V + BOR Level 4, reset level threshold for 2.54 V-2.74 V + BOR Level 5, reset level threshold for 2.77 V-3.0 V + + 0x0 + + + + + + User Configuration + + + + + IWDG_SW + + 0x4 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x5 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x6 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + nBOOT1 + + 0x0F + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + + + + Write Protection + + + + + WRPOT0 + + 0x0 + 0x8 + RW + + Write protection not active + Write protection active + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x431.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x431.xml new file mode 100644 index 0000000..448663e --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x431.xml @@ -0,0 +1,244 @@ + + + + 0x431 + STMicroelectronics + MCU + Cortex-M4 + STM32F411xC/E + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + + 0x0 + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x8 + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x432.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x432.xml new file mode 100644 index 0000000..906b840 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x432.xml @@ -0,0 +1,268 @@ + + + + 0x432 + STMicroelectronics + MCU + Cortex-M4 + STM32F37xx + STM32F3 + ARM 32-bit Cortex-M4 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x8 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + nBOOT1 + Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system flash when BOOT0=1 + + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + + + SDADC12_VDD + + 0x17 + 0x1 + RW + + SDADC12_VDD power supply supervisor disabled. + SDADC12_VDD power supply supervisor enabled + + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP8 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + + + + + + nWRP16 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP24 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x433.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x433.xml new file mode 100644 index 0000000..f1dd8d3 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x433.xml @@ -0,0 +1,244 @@ + + + + 0x433 + STMicroelectronics + MCU + Cortex-M4 + STM32F401xD/E + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x8 + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x434.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x434.xml new file mode 100644 index 0000000..ea3d4b7 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x434.xml @@ -0,0 +1,340 @@ + + + + 0x434 + STMicroelectronics + MCU + Cortex-M4 + STM32F469xx/F467xx + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + + + + + + + Dual + 0x4 + + + + + + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + BFB2 + + 0x4 + 0x1 + RW + + Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) + Dual-bank boot enabled. Boot is always performed from system memory. + + 0x0 + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + DB1M + Dual-bank on 1 Mbyte Flash memory devices + 0x1E + 0x1 + RW + + 1 Mbyte single bank Flash memory (contiguous addresses in bank1) + 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each + + 0x0 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0xC + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + nWRP12 + + 0x10 + 0xC + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x435.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x435.xml new file mode 100644 index 0000000..14b644a --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x435.xml @@ -0,0 +1,398 @@ + + + + 0x435 + STMicroelectronics + MCU + Cortex-M4 + STM32L43xxx/STM32L44xxx + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. + 0x17 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + + + SRAM2_PE + + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x1B + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory + + 0x1 + + + + + + PCROP Protection + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Write Protection + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the first page of the Bank 1 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x440.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x440.xml new file mode 100644 index 0000000..0fb6cbc --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x440.xml @@ -0,0 +1,225 @@ + + + + 0x440 + STMicroelectronics + MCU + Cortex-M0 + STM32F05x/F030x8 + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + 0x1 + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + 0x1 + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + 0x1 + + + + + + Write Protection + + + + + WRP bit0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x441.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x441.xml new file mode 100644 index 0000000..0b936c5 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x441.xml @@ -0,0 +1,244 @@ + + + + 0x441 + STMicroelectronics + MCU + Cortex-M4 + STM32F412 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xFF + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0xC + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x442.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x442.xml new file mode 100644 index 0000000..eb5085c --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x442.xml @@ -0,0 +1,656 @@ + + + + 0x442 + STMicroelectronics + MCU + Cortex-M0 + STM32F09x/F030xC + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + 0x1 + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x13 + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from main flash memory + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + 0x1 + + + BOOT_SEL + + 0x17 + 0x1 + RW + + BOOT0 signal is defined by nBOOT0 option bit + BOOT0 signal is defined by BOOT0 pin value + + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + 0x1 + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP1 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP2 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP3 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP4 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP5 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP6 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP7 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP8 + + 0x10 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP9 + + 0x11 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP10 + + 0x12 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP11 + + 0x13 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP12 + + 0x14 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP13 + + 0x15 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP14 + + 0x16 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP15 + + 0x17 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + + + + + + nWRP16 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP17 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP18 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP19 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP20 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP21 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP22 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP23 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP24 + + 0x10 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP25 + + 0x11 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP26 + + 0x12 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP27 + + 0x13 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP28 + + 0x14 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP29 + + 0x15 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP30 + + 0x16 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP31 + + 0x17 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x444.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x444.xml new file mode 100644 index 0000000..e8a92d5 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x444.xml @@ -0,0 +1,316 @@ + + + + 0x444 + STMicroelectronics + MCU + Cortex-M0 + STM32F03x + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + 0x1 + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + 0x1 + + + nBOOT1 + Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system flash when BOOT0=1 + + 0x1 + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + 0x1 + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP1 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP2 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP3 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP4 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP5 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP6 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP7 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x445.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x445.xml new file mode 100644 index 0000000..2ed871e --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x445.xml @@ -0,0 +1,340 @@ + + + + 0x445 + STMicroelectronics + MCU + Cortex-M0 + STM32F04x/F070x6 + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + 0x1 + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x13 + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from main flash memory + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + 0x1 + + + BOOT_SEL + + 0x17 + 0x1 + RW + + BOOT0 signal is defined by nBOOT0 option bit + BOOT0 signal is defined by BOOT0 pin value + + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + 0x1 + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + 0x1 + + + + + + Write Protection WRP0 + + + + + WRP0 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP1 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP2 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP3 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP4 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP5 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP6 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + WRP7 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x447.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x447.xml new file mode 100644 index 0000000..908c945 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x447.xml @@ -0,0 +1,876 @@ + + + + 0x447 + STMicroelectronics + MCU + Cortex-M0+ + STM32L07x/L08x/L010 + STM32L0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0x00 + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0x00 + RWE + + + + + Single + 0x4 + + + + + + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + WPRMOD + Sector protection mode selection option byte. + 0x8 + 0x1 + RW + + WRPx bit defines sector write protection + WRPx bit defines sector read/write (PCROP) protection + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x0 + 0x4 + RW + + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level 1, reset level threshold for 1.69 V-1.8 V + BOR Level 2, reset level threshold for 1.94 V-2.1 V + BOR Level 3, reset level threshold for 2.3 V-2.49 V + BOR Level 4, reset level threshold for 2.54 V-2.74 V + BOR Level 5, reset level threshold for 2.77 V-3.0 V + + 0x0 + + + + + + User Configuration + + + + + IWDG_SW + + 0x4 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x5 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x6 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + BFB2 + + 0x7 + 0x1 + RW + + Boot from flash bank 1 + boot from flash bank 2 + + 0x0 + + + nBOOT1 + + 0x0F + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + + + + Write Protection + + + + + WRPOT0 + + 0x0 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT1 + + 0x1 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT2 + + 0x2 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT3 + + 0x3 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT4 + + 0x4 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT5 + + 0x5 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT6 + + 0x6 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT7 + + 0x7 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT8 + + 0x8 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT9 + + 9 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT10 + + 0xA + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT11 + + 0xB + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT12 + + 0xC + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT13 + + 0xD + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT14 + + 0xE + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT15 + + 0xF + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT16 + + 0x10 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT17 + + 0x11 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT18 + + 0x12 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT19 + + 0x13 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT20 + + 0x14 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT21 + + 0x15 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT22 + + 0x16 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT23 + + 0x17 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT24 + + 0x18 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT25 + + 0x19 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT26 + + 0x1A + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT27 + + 0x1B + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT28 + + 0x1C + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT29 + + 0x1D + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT30 + + 0x1E + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT31 + + 0x1F + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + + + + + + WRPOT32 + + 0x0 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT33 + + 0x1 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT34 + + 0x2 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT35 + + 0x3 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT36 + + 0x4 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT38 + + 0x5 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT39 + + 0x6 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT40 + + 0x7 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT41 + + 0x8 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT42 + + 9 + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT43 + + 0xA + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT44 + + 0xB + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT45 + + 0xC + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT46 + + 0xD + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT47 + + 0xE + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + WRPOT48 + + 0xF + 0x1 + RW + + Read / Write protection not active + Read / Write protection active + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x448.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x448.xml new file mode 100644 index 0000000..b7d4a61 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x448.xml @@ -0,0 +1,635 @@ + + + + 0x448 + STMicroelectronics + MCU + Cortex-M0 + STM32F07x + STM32F0 + ARM 32-bit Cortex-M0 based device + + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + 0x1 + + + + + + User Configuration + + + + + WDG_SW + + 0x10 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + 0x1 + + + nRST_STOP + + 0x11 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + 0x1 + + + nRST_STDBY + + 0x12 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + 0x1 + + + nBOOT1 + Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. + 0x14 + 0x1 + RW + + Boot from embedded SRAM when BOOT0=1 + Boot from system flash when BOOT0=1 + + 0x1 + 0x1 + + + VDDA_MONITOR + + 0x15 + 0x1 + RW + + VDDA power supply supervisor disabled + VDDA power supply supervisor enabled + + 0x1 + 0x1 + + + RAM_PARITY + + 0x16 + 0x1 + RW + + RAM parity check enabled + RAM parity check disabled + + 0x1 + 0x1 + + + + + + User Data + + + + + Data0 + User data 0 (8-bit) + 0x0 + 0x8 + RW + 0xFF + 0x1 + + + Data1 + User data 1 (8-bit) + 0x10 + 0x8 + RW + 0xFF + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP1 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP2 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP3 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP4 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP5 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP6 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP7 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP8 + + 0x10 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP9 + + 0x11 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP10 + + 0x12 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP11 + + 0x13 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP12 + + 0x14 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP13 + + 0x15 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP14 + + 0x16 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP15 + + 0x17 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + + + + + + nWRP16 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP17 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP18 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP19 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP20 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP21 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP22 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP23 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP24 + + 0x10 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP25 + + 0x11 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP26 + + 0x12 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP27 + + 0x13 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP28 + + 0x14 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP29 + + 0x15 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP30 + + 0x16 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + nWRP31 + + 0x17 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x449.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x449.xml new file mode 100644 index 0000000..6df2a54 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x449.xml @@ -0,0 +1,420 @@ + + + + 0x449 + STMicroelectronics + MCU + Cortex-M7 + STM32F74x/STM32F75x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x10 + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + 0x3 + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + 0x0080 + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + 0x0040 + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP1 + + 0x1 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP2 + + 0x2 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP3 + + 0x3 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP4 + + 0x4 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP5 + + 0x5 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP6 + + 0x6 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + nWRP7 + + 0x7 + 0x1 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x450.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x450.xml new file mode 100644 index 0000000..671ea83 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x450.xml @@ -0,0 +1,621 @@ + + + + 0x450 + STMicroelectronics + MCU + Cortex-M7 + STM32H7xx + STM32H7 + ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Dual + 0x20 + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Dual + 0x20 + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + RSS + + + + + + + + + + + + + + + BOR Level + + + + + BOR_LEV + These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. + 0x2 + 0x2 + RW + + reset level is set to VBOR0 + reset level is set to VBOR1 + reset level is set to VBOR2 + reset level is set to VBOR3 + + 0x0 + + + + + + User Configuration + + + + + IWDG1_SW + + 0x4 + 0x1 + RW + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + 0x1 + + + IWDG2_SW + + 0x5 + 0x1 + RW + + Independent watchdog is controlled by hardware + Independent watchdog is controlled by software + + 0x1 + + + NRST_STOP_D1 + + 0x6 + 0x1 + RW + + STOP mode on Domain 1 is entering with reset + STOP mode on Domain 1 is entering without reset + + 0x1 + + + NRST_STBY_D1 + + 0x7 + 0x1 + RW + + STANDBY mode on Domain 1 is entering with reset + STANDBY mode on Domain 1 is entering without reset + + 0x1 + + + FZ_IWDG_STOP + + 0x11 + 0x1 + RW + + Independent watchdog is freezed in STOP mode + Independent watchdog is running in STOP mode + + 0x1 + + + FZ_IWDG_SDBY + + 0x12 + 0x1 + RW + + Independent watchdog is freezed in STANDBY mode + Independent watchdog is running in STANDBY mode + + 0x1 + + + SECURITY + + 0x15 + 0x1 + RW + + Security feature disabled + Security feature enabled + + 0x0 + + + BCM4 + + 0x16 + 0x1 + RW + + CM4 boot disabled + CM4 boot enabled + + 0x1 + + + BCM7 + + 0x17 + 0x1 + RW + + CM7 boot disabled + CM7 boot enabled + + 0x1 + + + NRST_STOP_D2 + + 0x18 + 0x1 + RW + + STOP mode on Domain 2 is entering with reset + STOP mode on Domain 2 is entering without reset + + 0x1 + + + NRST_STBY_D2 + + 0x19 + 0x1 + RW + + STANDBY mode on Domain 2 is entering with reset + STANDBY mode on Domain 2 is entering without reset + + 0x1 + + + SWAP_BANK + + 0x1F + 0x1 + RW + + after boot loading, no swap for user sectors + after boot loading, user sectors swapped + + 0x0 + + + IO_HSLV + I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V + 0x1D + 0x1 + RW + + Product working in the full voltage range, I/O speed optimization at low-voltage disabled + Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed + + 0x0 + + + + + + Boot address Option Bytes + + + + + BOOT_CM7_ADD0 + Define the boot address for Cortex-M7 when BOOT0=0 + 0x0 + 0x10 + RW + + 0x0800 + + + BOOT_CM7_ADD1 + Define the boot address for Cortex-M7 when BOOT0=1 + 0x10 + 0x10 + RW + + 0x1FF0 + + + + + + + + BOOT_CM4_ADD0 + Define the boot address for Cortex-M4 when BOOT0=0 + 0x0 + 0x10 + RW + + 0x0800 + + + BOOT_CM4_ADD1 + Define the boot address for Cortex-M4 when BOOT0=1 + 0x10 + 0x10 + RW + + 0x1FF0 + + + + + + PCROP Protection + + + + + PROT_AREA_START1 + Flash Bank 1 PCROP start address + 0x0 + 0xC + RW + + 0xFF + + + PROT_AREA_END1 + Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. + 0x10 + 0xC + RW + + 0x0 + + + DMEP1 + + 0x1F + 0x1 + RW + + Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + 0x0 + + + + + + + + PROT_AREA_START2 + Flash Bank 2 PCROP start address + 0x0 + 0xC + RW + + 0xFF + + + PROT_AREA_END2 + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address + 0x10 + 0xC + RW + + 0x0 + + + DMEP2 + + 0x1F + 0x1 + RW + + Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs + + 0x0 + + + + + + Secure Protection + + + + + SEC_AREA_START1 + Flash Bank 1 secure area start address + 0x0 + 0xC + RW + + 0xFF + + + SEC_AREA_END1 + Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. + 0x10 + 0xC + RW + + 0x0 + + + DMES1 + + 0x1F + 0x1 + RW + + Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + 0x0 + + + + + + + + SEC_AREA_START2 + Flash Bank 2 secure area start address + 0x0 + 0xC + RW + + 0xFF + + + SEC_AREA_END2 + Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. + 0x10 + 0xC + RW + + 0x0 + + + DMES2 + + 0x1F + 0x1 + RW + + Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs + Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs + + 0x0 + + + + + + DTCM RAM Protection + + + + + ST_RAM_SIZE + + 0x13 + 0x2 + RW + + 2 KB + 4 KB + 8 KB + 16 KB + + 0x3 + + + + + + Write Protection + + + + + nWRP0 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + + + + + + + + nWRP8 + + 0x0 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x451.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x451.xml new file mode 100644 index 0000000..4e7155b --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x451.xml @@ -0,0 +1,573 @@ + + + + 0x451 + STMicroelectronics + MCU + Cortex-M7 + STM32F76x/STM32F77x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x20 + + + + + + + + + + + + + + + + + Dual + 0x10 + + + + + + + + + + + + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + 0x3 + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + nDBANK + + 0x1D + 0x1 + RW + + Flash in dual bank with 128 bits read access + Flash in single bank with 256 bits read access + + 0x1 + + + nDBOOT + + 0x1C + 0x1 + RW + + Dual Boot enabled + Dual Boot disabled + + 0x1 + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + 0x0080 + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + 0x0040 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP1 + + 0x11 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP2 + + 0x12 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP3 + + 0x13 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP4 + + 0x14 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP5 + + 0x15 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP6 + + 0x16 + 0x1 + RW + + Write protection active on bank2 sector 2i and 2i+1 + Write protection not active on bank2 sector 2i, 2i+1 + + 0x1 + + + nWRP7 + + 0x17 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP8 + + 0x18 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP9 + + 0x19 + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP10 + + 0x1A + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + nWRP11 + + 0x1B + 0x1 + RW + + Write protection active on this sector / Write protection active on bank1 sector 2i and 2i+1 + Write protection not active on this sector / Write protection not active on bank1 sector 2i, 2i+1 + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x452.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x452.xml new file mode 100644 index 0000000..9cfbe5b --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x452.xml @@ -0,0 +1,373 @@ + + + + 0x452 + STMicroelectronics + MCU + Cortex-M7 + STM32F72x/STM32F73x + STM32F7 + ARM 32-bit Cortex-M7 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x10 + + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + ITCM Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + Single + 0x10 + + + + + + + + + + + + + + + + + Single + 0x10 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 (VBOR3), brownout threshold level 3 + BOR Level 2 (VBOR2), brownout threshold level 2 + BOR Level 1 (VBOR1), brownout threshold level 1 + BOR off, POR/PDR reset threshold level is applied + + 0x3 + + + + + + User Configuration + + + + + IWDG_STOP + + 0x1F + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x1E + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x4 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + IWDG_SW + + 0x5 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Boot address Option Bytes + + + + + BOOT_ADD0 + Define the boot address when BOOT0=0 + 0x0 + 0x10 + RW + + 0x0080 + + + BOOT_ADD1 + Define the boot address when BOOT0=1 + 0x10 + 0x10 + RW + + 0x0040 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x8 + RW + + Write protection active on this sector + Write protection not active on this sector + + 0x1 + + + + + + Read/Write Protection + + + + + PCROP0 + + 0x0 + 0x8 + RW + + PCROP protection not active on this sector + PCROP protection active on this sector + + 0x1 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml index 8b91525..114da5d 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml @@ -125,6 +125,7 @@ Level 2, chip protection 0xAA + 0x1 @@ -194,6 +195,7 @@ No reset generated when entering Stop mode 0x1 + 0x1 nRST_STDBY @@ -206,6 +208,7 @@ No reset generated when entering Standby mode 0x1 + 0x1 nRST_SHDW @@ -230,6 +233,7 @@ Software independent watchdog 0x1 + 0x1 IWDG_STOP @@ -242,6 +246,7 @@ IWDG counter active in stop mode 0x1 + 0x1 IWDG_STDBY @@ -254,6 +259,7 @@ IWDG counter active in standby mode 0x1 + 0x1 WWDG_SW @@ -266,6 +272,7 @@ Software window watchdog 0x1 + 0x1 RAM_PARITY_CHECK @@ -278,6 +285,7 @@ SRAM parity check disable 0x1 + 0x1 nBOOT_SEL @@ -290,6 +298,7 @@ BOOT0 signal is defined by nBOOT0 option bit 0x1 + 0x1 nBOOT1 @@ -302,6 +311,7 @@ Boot from Flash if BOOT0 = 0, otherwise system memory 0x1 + 0x1 nBOOT0 @@ -314,6 +324,7 @@ nBOOT0=1 0x1 + 0x1 NRST_MODE @@ -428,6 +439,7 @@ RW 0xFF + 0x1 WRP1A_END @@ -437,6 +449,7 @@ RW 0x0 + 0x1 @@ -451,6 +464,7 @@ RW 0xFF + 0x1 WRP1B_END @@ -460,6 +474,7 @@ RW 0x0 + 0x1 diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x457.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x457.xml new file mode 100644 index 0000000..6dda43b --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x457.xml @@ -0,0 +1,268 @@ + + + + 0x457 + STMicroelectronics + MCU + Cortex-M0+ + STM32L01x/L02x + STM32L0 + ARM 32-bit Cortex-M0+ based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0x00 + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0x00 + RWE + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + PCROP Protection + + + + + WPRMOD + Sector protection mode selection option byte. + 0x8 + 0x1 + RW + + WRPx bit defines sector write protection + WRPx bit defines sector read/write (PCROP) protection + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x0 + 0x4 + RW + + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold the 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level OFF, reset level threshold for 1.45 V-1.55 V + BOR Level 1, reset level threshold for 1.69 V-1.8 V + BOR Level 2, reset level threshold for 1.94 V-2.1 V + BOR Level 3, reset level threshold for 2.3 V-2.49 V + BOR Level 4, reset level threshold for 2.54 V-2.74 V + BOR Level 5, reset level threshold for 2.77 V-3.0 V + + 0x0 + + + + + + User Configuration + + + + + IWDG_SW + + 0x4 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + nRST_STOP + + 0x5 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x6 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + nBOOT_SEL + + 0xD + 0x1 + RW + + BOOT0 signal is defined by BOOT0 pin value (default mode) + BOOT0 signal is defined by nBOOT0 option bit + + 0x0 + + + nBOOT0 + When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode + 0xE + 0x1 + RW + + Main Flash memory is selected as boot area + nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area + + 0x0 + + + nBOOT1 + + 0x0F + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + + + + Write Protection + + + + + WRPOT0 + + 0x0 + 0x4 + RW + + Write protection not active + Write protection active + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x458.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x458.xml new file mode 100644 index 0000000..0872850 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x458.xml @@ -0,0 +1,241 @@ + + + + 0x458 + STMicroelectronics + MCU + Cortex-M4 + STM32F410 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + 0xFF + + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + WRP0 + + 0x10 + 0x5 + RW + + Write protection active / PCROP protection not active on sector i + Write protection not active / PCROP protection active on sector i + + 0x1F + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml index 0b29770..ee7fa16 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml @@ -130,6 +130,7 @@ Level 2, chip protection 0xAA + 0x1 @@ -198,6 +199,7 @@ No reset generated when entering Stop mode 0x1 + 0x1 nRST_STDBY @@ -210,6 +212,7 @@ No reset generated when entering Standby mode 0x1 + 0x1 nRST_SHDW @@ -234,6 +237,7 @@ Software independent watchdog 0x1 + 0x1 IWDG_STOP @@ -246,6 +250,7 @@ IWDG counter active in stop mode 0x1 + 0x1 IWDG_STDBY @@ -258,6 +263,7 @@ IWDG counter active in standby mode 0x1 + 0x1 WWDG_SW @@ -270,6 +276,7 @@ Software window watchdog 0x1 + 0x1 RAM_PARITY_CHECK @@ -282,6 +289,7 @@ SRAM parity check disable 0x1 + 0x1 nBOOT_SEL @@ -294,6 +302,7 @@ BOOT0 signal is defined by nBOOT0 option bit 0x1 + 0x1 nBOOT1 @@ -306,6 +315,7 @@ Boot from Flash if BOOT0 = 0, otherwise system memory 0x1 + 0x1 nBOOT0 @@ -318,6 +328,7 @@ nBOOT0=1 0x1 + 0x1 NRST_MODE @@ -432,6 +443,7 @@ RW 0x7F + 0x1 WRP1A_END @@ -441,6 +453,7 @@ RW 0x0 + 0x1 @@ -455,6 +468,7 @@ RW 0x7F + 0x1 WRP1B_END @@ -464,6 +478,7 @@ RW 0x0 + 0x1 diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x461.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x461.xml new file mode 100644 index 0000000..cdd3cb7 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x461.xml @@ -0,0 +1,510 @@ + + + + 0x461 + STMicroelectronics + MCU + Cortex-M4 + STM32L496xx/STM32L4A6xx + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + BFB2 + + 0x14 + 0x1 + RW + + Dual-bank boot disable + Dual-bank boot enable + + 0x0 + + + DUALBANK + + 0x15 + 0x1 + RW + + 256 KB/512 KB Single-bank Flash + 256 KB/512 KB Dual-bank Flash + + 0x1 + + + nBOOT1 + + 0x17 + 0x1 + RW + + Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 + Boot from Flash if BOOT0 = 0, otherwise system memory + + 0x1 + + + SRAM2_PE + + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + + + + PCROP Protection (Bank 1) + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Write Protection (Bank 1) + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the first page of the Bank 1 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + PCROP Protection (Bank 2) + + + + + PCROP2_STRT + Flash Bank 2 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP2_END + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + + + + Write Protection (Bank 2) + + + + + WRP2A_STRT + The address of first page of the Bank 2 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP2A_END + The address of last page of the Bank 2 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP2B_STRT + The address of first page of the Bank 2 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP2B_END + The address of last page of the Bank 2 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x463.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x463.xml new file mode 100644 index 0000000..7ba464a --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x463.xml @@ -0,0 +1,412 @@ + + + + 0x463 + STMicroelectronics + MCU + Cortex-M4 + STM32F413/F423 + STM32F4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x4 + + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x8 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xFF + + + + + + PCROP Protection + + + + + SPRMOD + Selection of protection mode for nWPRi bits. + 0x1F + 0x1 + RW + + PCROP disabled. nWPRi bits used for Write protection on sector i + PCROP enabled. nWPRi bits used for PCROP protection on sector i + + 0x0 + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x2 + 0x2 + RW + + BOR Level 3 reset threshold level from 2.70 to 3.60 V + BOR Level 2 reset threshold level from 2.40 to 2.70 V + BOR Level 1 reset threshold level from 2.10 to 2.40 V + BOR OFF reset threshold level from 1.80 to 2.10 V + + 0x3 + + + + + + User Configuration + + + + + WDG_SW + + 0x5 + 0x1 + RW + + Hardware watchdog + Software watchdog + + 0x1 + + + nRST_STOP + + 0x6 + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated + + 0x1 + + + nRST_STDBY + + 0x7 + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated + + 0x1 + + + + + + Write Protection + + + + + nWRP0 + + 0x10 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 0 + Write protection not active / PCROP protection active on sector 0 + + 0x1 + + + nWRP1 + + 0x11 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 1 + Write protection not active / PCROP protection active on sector 1 + + 0x1 + + + nWRP2 + + 0x12 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 2 + Write protection not active / PCROP protection active on sector 2 + + 0x1 + + + nWRP3 + + 0x13 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 3 + Write protection not active / PCROP protection active on sector 3 + + 0x1 + + + nWRP4 + + 0x14 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 4 + Write protection not active / PCROP protection active on sector 4 + + 0x1 + + + nWRP5 + + 0x15 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 5 + Write protection not active / PCROP protection active on sector 5 + + 0x1 + + + nWRP6 + + 0x16 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 6 + Write protection not active / PCROP protection active on sector 6 + + 0x1 + + + nWRP7 + + 0x17 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 7 + Write protection not active / PCROP protection active on sector 7 + + 0x1 + + + nWRP8 + + 0x18 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 8 + Write protection not active / PCROP protection active on sector 8 + + 0x1 + + + nWRP9 + + 0x19 + 0x1 + RW + + Write protection active / PCROP protection not active on sector 9 + Write protection not active / PCROP protection active on sector 9 + + 0x1 + + + nWRP10 + + 0x1A + 0x1 + RW + + Write protection active / PCROP protection not active on sector 10 + Write protection not active / PCROP protection active on sector 10 + + 0x1 + + + nWRP11 + + 0x1B + 0x1 + RW + + Write protection active / PCROP protection not active on sector 11 + Write protection not active / PCROP protection active on sector 11 + + 0x1 + + + nWRP12 + + 0x1C + 0x1 + RW + + Write protection active / PCROP protection not active on sector 12 + Write protection not active / PCROP protection active on sector 12 + + 0x1 + + + nWRP13 + + 0x1D + 0x1 + RW + + Write protection active / PCROP protection not active on sector 13 + Write protection not active / PCROP protection active on sector 13 + + 0x1 + + + nWRP15_14 + + 0x1E + 0x1 + RW + + Write protection active / PCROP protection not active on sectors 14 and 15 + Write protection not active / PCROP protection active on sectors 14 and 15 + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x464.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x464.xml new file mode 100644 index 0000000..2b0babb --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x464.xml @@ -0,0 +1,400 @@ + + + + 0x464 + STMicroelectronics + MCU + Cortex-M4 + STM32L41x + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. + 0x17 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + + + SRAM2_PE + + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x1B + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory + + 0x1 + + + + + + PCROP Protection + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Write Protection + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x6 + RW + + 0x3F + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x6 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the first page of the Bank 1 WRP second area + 0x0 + 0x6 + RW + + 0x3F + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x6 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml index ff7f157..2c494b4 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml @@ -150,6 +150,7 @@ Level 2, chip protection 0xAA + 0x1 @@ -218,6 +219,7 @@ No reset generated when entering Stop mode 0x1 + 0x1 nRST_STDBY @@ -230,6 +232,7 @@ No reset generated when entering Standby mode 0x1 + 0x1 nRST_SHDW @@ -253,6 +256,7 @@ Software independent watchdog 0x1 + 0x1 IWDG_STOP @@ -265,6 +269,7 @@ IWDG counter active in stop mode 0x1 + 0x1 IWDG_STDBY @@ -277,6 +282,7 @@ IWDG counter active in standby mode 0x1 + 0x1 WWDG_SW @@ -289,6 +295,7 @@ Software window watchdog 0x1 + 0x1 RAM_PARITY_CHECK @@ -301,6 +308,7 @@ SRAM parity check disable 0x1 + 0x1 nBOOT_SEL @@ -313,6 +321,7 @@ BOOT0 signal is defined by nBOOT0 option bit 0x1 + 0x1 nBOOT1 @@ -325,6 +334,7 @@ Boot from Flash if BOOT0 = 1, otherwise system memory 0x1 + 0x1 nBOOT0 @@ -337,6 +347,7 @@ nBOOT0=1 0x1 + 0x1 NRST_MODE @@ -408,34 +419,6 @@ - - - - - PCROP2A_STRT - Flash Area A in Bank 2 PCROP start address - 0x0 - 0x8 - RW - - 0xFF - - - - - - - - PCROP2A_END - Flash Area A in Bank 2 PCROP end address - 0x0 - 0x8 - RW - - 0x0 - - - @@ -464,34 +447,6 @@ - - - - - PCROP2B_STRT - Flash Area B in Bank 2 PCROP start address - 0x0 - 0x8 - RW - - 0xFF - - - - - - - - PCROP2B_END - Flash Area B in Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - 0x0 - - - Write Protection @@ -506,6 +461,7 @@ RW 0xFF + 0x1 WRP1A_END @@ -515,6 +471,7 @@ RW 0x0 + 0x1 @@ -529,6 +486,7 @@ RW 0xFF + 0x1 WRP1B_END @@ -538,52 +496,7 @@ RW 0x0 - - - - - - - - WRP2A_STRT - The address of the first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - 0xFF - - - WRP2A_END - The address of the last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - 0x0 - - - - - - - - WRP2B_STRT - The address of the first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - 0xFF - - - WRP2B_END - The address of the last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - 0x0 + 0x1 @@ -617,15 +530,6 @@ 0x0 - - SEC_SIZE2 - Securable memory area size, Bank 2 - 0x0 - 0x7 - RW - - 0x0 - diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml index 6fb4d62..73d82b6 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml @@ -186,6 +186,7 @@ Level 2, chip protection 0xAA + 0x1 @@ -254,6 +255,7 @@ No reset generated when entering Stop mode 0x1 + 0x1 nRST_STDBY @@ -266,6 +268,7 @@ No reset generated when entering Standby mode 0x1 + 0x1 nRST_SHDW @@ -290,6 +293,7 @@ Software independent watchdog 0x1 + 0x1 IWDG_STOP @@ -302,6 +306,7 @@ IWDG counter active in stop mode 0x1 + 0x1 IWDG_STDBY @@ -314,6 +319,7 @@ IWDG counter active in standby mode 0x1 + 0x1 WWDG_SW @@ -326,6 +332,7 @@ Software window watchdog 0x1 + 0x1 nSWAP_BANK @@ -338,6 +345,7 @@ Bank 2 0x1 + 0x1 DUAL_BANK @@ -350,6 +358,7 @@ 256 Kbytes/512 Kbytes dual-bank Flash memory 0x1 + 0x1 RAM_PARITY_CHECK @@ -362,6 +371,7 @@ SRAM parity check disable 0x1 + 0x1 nBOOT_SEL @@ -374,6 +384,7 @@ BOOT0 signal is defined by nBOOT0 option bit 0x1 + 0x1 nBOOT1 @@ -386,6 +397,7 @@ Boot from Flash if BOOT0 = 0, otherwise system memory 0x1 + 0x1 nBOOT0 @@ -398,6 +410,7 @@ nBOOT0=1 0x1 + 0x1 NRST_MODE @@ -568,6 +581,7 @@ RW 0x7F + 0x1 WRP1A_END @@ -577,6 +591,7 @@ RW 0x0 + 0x1 @@ -591,6 +606,7 @@ RW 0x7F + 0x1 WRP1B_END @@ -600,10 +616,10 @@ RW 0x0 + 0x1 - @@ -615,6 +631,7 @@ RW 0x7F + 0x1 WRP2A_END @@ -624,6 +641,7 @@ RW 0x0 + 0x1 @@ -638,6 +656,7 @@ RW 0x7F + 0x1 WRP2B_END @@ -647,6 +666,7 @@ RW 0x0 + 0x1 diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml index a5f3f57..d535329 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml @@ -531,7 +531,7 @@ - + PCROP2_STRT Flash Bank 2 PCROP start address 0x0 @@ -581,7 +581,7 @@ - + WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 @@ -589,7 +589,7 @@ RW 0x7F - + WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x470.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x470.xml new file mode 100644 index 0000000..dba33c8 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x470.xml @@ -0,0 +1,606 @@ + + + + 0x470 + STMicroelectronics + MCU + Cortex-M4 + STM32L4Rxxx/STM32L4Sxxx + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + BFB2 + + 0x14 + 0x1 + RW + + Dual-bank boot disable + Dual-bank boot enable + + 0x0 + + + DB1M + Dual-Bank on 1 MB Flash or 512 KB Flash memory devices + 0x15 + 0x1 + RW + + 1 MB or 512 Kb single Flash: contiguous address in bank1 + 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. + + 0x1 + + + DBANK + This bit can only be written when PCROPA/B is disabled + 0x16 + 0x1 + RW + + Single bank mode with 128 bits data read width + Dual bank mode with 64 bits data + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. + 0x17 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + + + SRAM2_PE + SRAM2 parity check enable + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + SRAM2 Erase when system reset + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + Software BOOT0 + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x1B + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory + + 0x1 + + + + + + PCROP Protection (Bank 1) + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x11 + RW + + 0x1FFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x11 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + Write Protection (FLASH_WRP1AR) + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + Write Protection (FLASH_WRP2AR) + + + + + WRP2A_STRT + The address of first page of the Bank 2 WRP first area + 0x0 + 0x8 + RW + + 0xFFFF + + + WRP2A_END + The address of last page of the Bank 2 WRP first area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + PCROP Protection (Bank 2) + + + + + PCROP2_STRT + Flash Bank 2 PCROP start address + 0x0 + 0x11 + RW + + 0x1FFFF + + + + + + + + PCROP2_END + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x11 + RW + + 0x0 + + + + + + Write Protection (FLASH_WRP1BR) + + + + + WRP1B_STRT + The address of the last page of the Bank 1 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + Write Protection (FLASH_WRP2BR) + + + + + WRP2B_STRT + The address of first page of the Bank 2 WRP second area + 0x0 + 0x8 + RW + + 0xFF + + + WRP2B_END + The address of last page of the Bank 2 WRP second area + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x471.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x471.xml new file mode 100644 index 0000000..0073ec1 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x471.xml @@ -0,0 +1,600 @@ + + + + 0x471 + STMicroelectronics + MCU + Cortex-M4 + STM32L4Pxxx/STM32L4Qxxx + STM32L4 + ARM 32-bit Cortex-M4 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Dual + 0x4 + + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + BFB2 + + 0x14 + 0x1 + RW + + Dual-bank boot disable + Dual-bank boot enable + + 0x0 + + + DB1M + Dual-Bank on 1 MB Flash or 512 KB Flash memory devices + 0x15 + 0x1 + RW + + 1 MB or 512 Kb single Flash: contiguous address in bank1 + 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. + + 0x1 + + + DBANK + This bit can only be written when PCROPA/B is disabled + 0x16 + 0x1 + RW + + Single bank mode with 128 bits data read width + Dual bank mode with 64 bits data + + 0x1 + + + nBOOT1 + This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. + 0x17 + 0x1 + RW + + Boot from embedded SRAM1 when BOOT0=1 + Boot from system memory when BOOT0=1 + + 0x1 + + + SRAM2_PE + SRAM2 parity check enable + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + SRAM2 Erase when system reset + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + Software BOOT0 + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + This option bit sets the BOOT0 value only when nSWBOOT0=0 + 0x1B + 0x1 + RW + + BOOT0 = 1, boot memory depends on nBOOT1 value + BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory + + 0x1 + + + + + + PCROP Protection (Bank 1) + + + + + PCROP1_STRT + Flash Bank 1 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP1_END + Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x0 + + + + + + Write Protection (Bank 1) + + + + + WRP1A_STRT + The address of the first page of the Bank 1 WRP first area + 0x0 + 0x7 + RW + + 0x7F + + + WRP1A_END + The address of the last page of the Bank 1 WRP first area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the last page of the Bank 1 WRP second area + 0x0 + 0x7 + RW + + 0x7F + + + WRP1B_END + The address of the last page of the Bank 1 WRP second area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + + PCROP Protection (Bank 2) + + + + + PCROP2_STRT + Flash Bank 2 PCROP start address + 0x0 + 0x10 + RW + + 0xFFFF + + + + + + + + PCROP2_END + Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 + 0x0 + 0x10 + RW + + 0x0 + + + + + + Write Protection (Bank 2) + + + + + WRP2A_STRT + The address of first page of the Bank 2 WRP first area + 0x0 + 0x7 + RW + + 0x7F + + + WRP2A_END + The address of last page of the Bank 2 WRP first area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + WRP2B_STRT + The address of first page of the Bank 2 WRP second area + 0x0 + 0x7 + RW + + 0x7F + + + WRP2B_END + The address of last page of the Bank 2 WRP second area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x472.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x472.xml new file mode 100644 index 0000000..c8bc6ee --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x472.xml @@ -0,0 +1,974 @@ + + + + 0x472 + STMicroelectronics + MCU + Cortex-M33 + STM32L5xx + STM32L5 + ARM 32-bit Cortex-M33 based device + + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Single + + + + + + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + Single + 0x8 + + + + + + + + + + Single + 0x8 + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + Single + 0x8 + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + Dual + 0x8 + + + + + + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0xFF + RWE + + + + Single + 0x8 + + + + + + + + + + Single + 0x8 + + + + + + + + + + Single + 0x8 + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + + + + + + Single + 0x8 + + + + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + + + + + Option Bytes + Configuration + + RW + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) + Level 1, read protection of memories + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + nRST_SHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + SWAP_BANK + + 0x14 + 0x1 + RW + + Bank 1 and bank 2 address are not swapped + Bank 1 and bank 2 address are swapped + + 0x0 + + + DB256 + Dual-Bank on 256 Kb Flash memory devices + 0x15 + 0x1 + RW + + 256Kb single Flash: contiguous address in bank1 + 256Kb dual-bank Flash with contiguous addresses + + 0x1 + + + DBANK + This bit can only be written when all protection (secure, PCROP, HDP) are disabled + 0x16 + 0x1 + RW + + Single bank mode with 128 bits data read width + Dual bank mode with 64 bits data + + 0x1 + + + SRAM2_PE + SRAM2 parity check enable + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + SRAM2 Erase when system reset + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + Software BOOT0 + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + nBOOT0 option bit + 0x1B + 0x1 + RW + + nBOOT0 = 0 + nBOOT0 = 1 + + 0x1 + + + PA15_PUPEN + PA15 pull-up enable + 0x1C + 0x1 + RW + + USB power delivery dead-battery enabled/ TDI pull-up deactivated + USB power delivery dead-battery disabled/ TDI pull-up activated + + 0x1 + + + TZEN + Global TrustZone security enable + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + 0x0 + + + + + + + + HDP1EN + Hide protection first area enable + 0x1F + 0x1 + RW + + No HDP area 1 + HDP first area is enabled + + 0x0 + + + HDP1_PEND + End page of first hide protection area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + HDP2EN + Hide protection second area enable + 0x1F + 0x1 + RW + + No HDP area 2 + HDP second area is enabled + + 0x0 + + + HDP2_PEND + End page of second hide protection area + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + NSBOOTADD0 + Non-secure Boot base address 0 + 0x7 + 0x19 + RW + + 0x0100000 + + + + + + + + NSBOOTADD1 + Non-secure Boot base address 1 + 0x7 + 0x19 + RW + + 0x017F200 + + + + + + + + SECBOOTADD0 + Secure boot base address 0 + 0x7 + 0x19 + RW + + 0x0180000 + + + + + + + + BOOT_LOCK + The boot is always forced to base address value programmed in SECBOOTADD0 + 0x0 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from base address memory + + 0x0 + + + + + + Secure Area 1 + + + + + SECWM1_PSTRT + Start page of first secure area + 0x0 + 0x7 + RW + + 0x0 + + + SECWM1_PEND + End page of first secure area + 0x10 + 0x7 + RW + + 0x7F + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Write Protection 1 + + + + + WRP1A_PSTRT + Bank 1 WPR first area "A" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRP1A_PEND + Bank 1 WPR first area "A" end page + 0x10 + 0x7 + RW + : + 0x0s + + + + + + + + WRP1B_PSTRT + Bank 1 WPR first area "B" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRP1B_PEND + Bank 1 WPR first area "B" end page + 0x10 + 0x7 + RW + + 0x0 + + + + + + Secure Area 2 + + + + + SECWM2_PSTRT + Start page of second secure area + 0x0 + 0x7 + RW + + 0x0 + + + SECWM2_PEND + End page of second secure area + 0x10 + 0x7 + RW + + 0x7F + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Write Protection 2 + + + + + WRP2A_PSTRT + Bank 2 WPR first area "A" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRP2A_PEND + Bank 2 WPR first area "A" end page + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + WRP2B_PSTRT + Bank 2 WPR first area "B" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRP2B_PEND + Bank 2 WPR first area "B" end page + 0x10 + 0x7 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml index 08a4483..c5ec9f0 100644 --- a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml @@ -193,8 +193,8 @@ Hardware window watchdog Software window watchdog + 0x1 - 0x1 IWDG_SW @@ -243,18 +243,6 @@ 0x1 - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - 0x0 - nBOOT1 diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x492.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x492.xml new file mode 100644 index 0000000..edcd804 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x492.xml @@ -0,0 +1,566 @@ + + + + 0x492 + STMicroelectronics + MCU + Cortex-M33 + STM32WBA52/54/55 + STM32WBA + ARM 32-bit Cortex-M33 based device + + + + + + + + + + Embedded SRAM + Storage + + 0xFF + RWE + + + + + Single + + + + + + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0xFF + RWE + + + + + + + Single + 0x10 + + + + + + + + + + Data EEPROM + Storage + The Data EEPROM memory block. It contains user data. + 0xFF + RWE + + + + + Single + 0x4 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) + Level 1, read protection of memories + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the VDD supply level threshold that activates/releases the reset. + 0x8 + 0x3 + RW + + BOR Level 0, reset level threshold is around 1.7 V + BOR Level 1, reset level threshold is around 2.0 V + BOR Level 2, reset level threshold is around 2.2 V + BOR Level 3, reset level threshold is around 2.5 V + BOR Level 4, reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering Stop mode + No reset generated when entering Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering Standby mode + No reset generated when entering Standby mode + + 0x1 + + + SRAM1_RST + SRAM1 erase upon system reset + 0xF + 0x1 + RW + + SRAM1 erased when a system reset occurs + SRAM1 not erased when a system reset occurs + + 0x1 + + + IWDG_SW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + IWDG_STOP + + 0x11 + 0x1 + RW + + Freeze IWDG counter in stop mode + IWDG counter active in stop mode + + 0x1 + + + IWDG_STDBY + + 0x12 + 0x1 + RW + + Freeze IWDG counter in standby mode + IWDG counter active in standby mode + + 0x1 + + + WWDG_SW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + SRAM2_PE + SRAM2 parity check enable + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + SRAM2_RST + SRAM2 Erase when system reset + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x1 + + + nSWBOOT0 + Software BOOT0 + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + nBOOT0 + nBOOT0 option bit + 0x1B + 0x1 + RW + + nBOOT0 = 0 + nBOOT0 = 1 + + 0x1 + + + TZEN + Global TrustZone security enable + 0x1F + 0x1 + RW + + Global TrustZone security disabled + Global TrustZone security enabled + + 0x0 + + + + + + Boot Configuration + + + + + NSBOOTADD0 + Non-secure Boot base address 0 + 0x7 + 0x19 + RW + + 0x100000 + + + + + + + + NSBOOTADD1 + Non-secure Boot base address 1 + 0x7 + 0x19 + RW + + 0x17F200 + + + + + + + + SECBOOTADD0 + Secure boot base address 0 + 0x7 + 0x19 + RW + + 0x180000 + + + + + + + + BOOT_LOCK + The boot is always forced to base address value programmed in SECBOOTADD0 + 0x0 + 0x1 + RW + + Boot based on the pad/option bit configuration + Boot forced from base address memory + + 0x0 + + + + + + Secure Area + + + + + SECWM_PSTRT + Start page of secure area + 0x0 + 0x7 + RW + + 0x0 + + + SECWM_PEND + End page of first secure area + 0x10 + 0x7 + RW + + 0x7F + + + + + + + + HDP_PEND + End page of secure hide protection area + 0x10 + 0x7 + RW + + 0x0 + + + HDPEN + Secure Hide protection first area enable + 0x1F + 0x1 + RW + + No secHDP area + HDP first area is enabled + + 0x0 + + + + + + Write Protection 1 + + + + + WRPA_PSTRT + WPR first area "A" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRPA_PEND + WPR first area "A" end page + 0x10 + 0x7 + RW + + 0x0 + + + UNLOCK_A + WPR first area A unlock + 0x1F + 0x1 + RW + + WRPA start and end pages locked + WRPA start and end pages unlocked + + 0x1 + + + + + + + + WRPB_PSTRT + WPR second area "B" start page + 0x0 + 0x7 + RW + + 0x7F + + + WRPB_PEND + WPR second area "B" end page + 0x10 + 0x7 + RW + + 0x0 + + + UNLOCK_B + WPR second area B unlock + 0x1F + 0x1 + RW + + WRPB start and end pages locked + WRPB start and end pages unlocked + + 0x1 + + + + + + OEM Keys + + + + + OEM1KEY[31:0] + OEM1 least significant bytes key + 0x0 + 0x20 + RW + + 0x0 + + + + + + + + OEM1KEY[63:32] + OEM1 most significant bytes key + 0x0 + 0x20 + RW + + 0x0 + + + + + + + + OEM2KEY[31:0] + OEM2 least significant bytes key + 0x0 + 0x20 + RW + + 0x0 + + + + + + + + OEM2KEY[63:32] + OEM2 most significant bytes key + 0x0 + 0x20 + RW + + 0x0 + + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x494.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x494.xml new file mode 100644 index 0000000..fab5bc1 --- /dev/null +++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x494.xml @@ -0,0 +1,615 @@ + + + + 0x494 + STMicroelectronics + MCU + Cortex-M0+/M4 + STM32WB1xxx + STM32WB + ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device + + + + + + + + + Embedded SRAM + Storage + + 0x00 + RWE + + + + + Single + + + + + + + + + + Embedded Flash + Storage + The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms + 0x00 + RWE + + + + + + + Single + 0x8 + + + + + + + + + + OTP + Storage + The Data OTP memory block. It contains the one time programmable bits. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + MirrorOptionBytes + Storage + Mirror Option Bytes contains the extra area. + 0xFF + RW + + + + + Single + 0x4 + + + + + + + + + + Option Bytes + Configuration + + RW + + + + + Read Out Protection + + + + + RDP + Read protection option byte. The read protection is used to protect the software code stored in Flash memory. + 0x0 + 0x8 + RW + + Level 0, no protection + or any value other than 0xAA and 0xCC: Level 1, read protection + Level 2, chip protection + + 0xAA + + + + + + BOR Level + + + + + BOR_LEV + These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory + 0x9 + 0x3 + RW + + BOR Level 0 reset level threshold is around 1.7 V + BOR Level 1 reset level threshold is around 2.0 V + BOR Level 2 reset level threshold is around 2.2 V + BOR Level 3 reset level threshold is around 2.5 V + BOR Level 4 reset level threshold is around 2.8 V + + 0x0 + + + + + + User Configuration + + + + + nBOOT0 + + 0x1B + 0x1 + RW + + nBOOT0=0 + nBOOT0=1 + + 0x1 + + + nBOOT1 + + 0x17 + 0x1 + RW + + Boot from code area if BOOT0=0 otherwise embedded SRAM1 + Boot from code area if BOOT0=0 otherwise system Flash + + 0x1 + + + nSWBOOT0 + + 0x1A + 0x1 + RW + + BOOT0 taken from the option bit nBOOT0 + BOOT0 taken from PH3/BOOT0 pin + + 0x1 + + + SRAM2RST + + 0x19 + 0x1 + RW + + SRAM2 erased when a system reset occurs + SRAM2 is not erased when a system reset occurs + + 0x0 + + + SRAM2PE + + 0x18 + 0x1 + RW + + SRAM2 parity check enable + SRAM2 parity check disable + + 0x1 + + + nRST_STOP + + 0xC + 0x1 + RW + + Reset generated when entering the Stop mode + No reset generated when entering the Stop mode + + 0x1 + + + nRST_STDBY + + 0xD + 0x1 + RW + + Reset generated when entering the Standby mode + No reset generated when entering the Standby mode + + 0x1 + + + nRSTSHDW + + 0xE + 0x1 + RW + + Reset generated when entering the Shutdown mode + No reset generated when entering the Shutdown mode + + 0x1 + + + WWDGSW + + 0x13 + 0x1 + RW + + Hardware window watchdog + Software window watchdog + + 0x1 + + + IWDGSTDBY + + 0x12 + 0x1 + RW + + Independent watchdog counter frozen in Standby mode + Independent watchdog counter running in Standby mode + + 0x1 + + + IWDGSTOP + + 0x11 + 0x1 + RW + + Independent watchdog counter frozen in Stop mode + Independent watchdog counter running in Stop mode + + 0x1 + + + IWDGSW + + 0x10 + 0x1 + RW + + Hardware independent watchdog + Software independent watchdog + + 0x1 + + + GPIO_MODE_PB11 + PB11 GPIO mode + 0x1C + 0x1 + RW + + If RESET_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode, GPIO functionality is not available on PB11. If RESET_MODE_PB11 = 1: Reset Input only, a low level on the NRST pin generates system reset, internal RESET. + If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11. + + 0x1 + + + RESET_MODE_PB11 + PB11 reset mode + 0x16 + 0x1 + RW + + If GPIO_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode. If GPIO_MODE_PB11 = 1: Standard GPIO pad functionality, only internal RESET possible. + If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode). + + 0x1 + + + IRH + Internal reset holder enable bit + 0xF + 0x1 + RW + + Internal resets are propagated as simple pulse on NRST pin. + Internal resets drives NRST pin low until it is seen as low level. + + 0x1 + + + + + + ESE + + + + + ESE + System Security Enabled flag + 0x8 + 0x1 + RW + + Security disabled + Security enabled + + 0x1 + + + + + + PCROP Protection + + + + + PCROP1A_STRT + Flash Area 1 PCROP start address + 0x0 + 0x9 + RW + + 0x1FF + + + + + + + + PCROP1A_END + Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. + 0x0 + 0x9 + RW + + 0x0 + + + PCROP_RDP + + 0x1F + 0x1 + RW + + PCROP zone is kept when RDP is decreased + PCROP zone is erased when RDP is decreased + + 0x1 + + + + + + + + PCROP1B_STRT + Flash Area 2 PCROP start address + 0x0 + 0x9 + RW + + 0x1FF + + + + + + + + PCROP1B_END + Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. + 0x0 + 0x9 + RW + + 0x0 + + + + + + Write Protection + + + + + WRP1A_STRT + The address of the first page of the WRP first area. + 0x0 + 0x8 + RW + + 0xFF + + + WRP1A_END + The address of the last page of the WRP first area. + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + WRP1B_STRT + The address of the first page of WRP second area. + 0x0 + 0x8 + RW + + 0xFF + + + WRP1B_END + The address of the last page of WRP second area. + 0x10 + 0x8 + RW + + 0x0 + + + + + + + + + IPCCDBA-AA + + + + + IPCCDBA + IPCC mailbox data buffer base address + 0x0 + 0xE + RW + + 0x0 + + + + + + + + + Security Configuration Option bytes + + + + + SFSA + Secure Flash Start Address + 0x0 + 0x8 + RW + + 0x0 + + + FSD + Flash Security Disable + 0x8 + 0x1 + RW + + System and Flash secure + System and Flash non-secure + + 0x0 + + + DDS + Disable CPU2 Debug access + 0xC + 0x1 + RW + + CPU2 debug access enabled + CPU2 debug access disabled + + 0x1 + + + + + + + + C2OPT + CPU2 boot reset vector memory selection + 0x1F + 0x1 + RW + + SBRV will address SRAM1 or SRAM2 + SBRV will address Flash + + 0x0 + + + BRSD_B + Backup SRAM2b security disable + 0x1E + 0x1 + RW + + SRAM2b is secure + SRAM2b is non-secure + + 0x0 + + + SBRSA_B + SBRSA_B[1:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. + 0x19 + 0x2 + RW + + 0x0 + + + BRSD_A + Backup SRAM2a security disable + 0x17 + 0x1 + RW + + SRAM2a is secure + SRAM2a is non-secure + + 0x0 + + + SBRSA_A + SBRSA_A[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. + 0x12 + 0x5 + RW + + 0x0 + + + SBRV + Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. + 0x0 + 0x11 + RW + + 0x0 + + + + + + + + + \ No newline at end of file diff --git a/Programmer/FlashLoader/0x459.stldr b/Programmer/FlashLoader/0x459.stldr new file mode 100644 index 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b/Programmer/x86/libwinpthread-1.dll index 73ef1ab..61a76da 100644 Binary files a/Programmer/x86/libwinpthread-1.dll and b/Programmer/x86/libwinpthread-1.dll differ diff --git a/Programmer/x86/zlib1.dll b/Programmer/x86/zlib1.dll new file mode 100644 index 0000000..26e8999 Binary files /dev/null and b/Programmer/x86/zlib1.dll differ diff --git a/README.md b/README.md index 7ae8057..750f249 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ # KSociety.SharpCubeProgrammer -KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.15.0. +KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.16.0. First unofficial and open source C# wrapper. @@ -23,13 +23,13 @@ It makes use of several 3rd party tools: ## Introduction -This is a C# wrapper for STM32 CubeProgrammer_API v2.15.0 (not fully tested). +This is a C# wrapper for STM32 CubeProgrammer_API v2.16.0 (not fully tested). This package does not contain any C/C++ runtimes (MSVC), and is meant to run on Windows operating systems only (for now). Please make sure you have updated the firmware of your ST-LINK V2 / V3, you can do this using STM32CubeProgrammer. The STM32 CubeProgrammer_API is a C-library, created by ST for ST-Link access to micro-controllers for the purpose of flash downloads or general memory access. The ST-Link drivers is required, and can be downloaded from st.com and installed [(STSW-LINK009)](https://www.st.com/en/development-tools/stsw-link009.html). -This has been tested on Windows 10, you don't need to install STM32CubeProgrammer. +This has been tested on Windows 10 and Windows 11, you don't need to install STM32CubeProgrammer. ### KSociety.SharpCubeProgrammer STM32CubeProgrammer_API C# wrapper, the first wrapper for C#. Any suggestions are welcome. @@ -260,5 +260,4 @@ The project is under Microsoft Reciprocal License [(MS-RL)](http://www.opensourc List of technologies, frameworks and libraries used for implementation: -- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces) for .NET Standard 2.0 only. - [Microsoft.Extensions.Logging.Abstractions](https://www.nuget.org/packages/Microsoft.Extensions.Logging.Abstractions) \ No newline at end of file diff --git a/docs/KSociety.SharpCubeProgrammer/README.md b/docs/KSociety.SharpCubeProgrammer/README.md index 91f6d28..fc3d4ed 100644 --- a/docs/KSociety.SharpCubeProgrammer/README.md +++ b/docs/KSociety.SharpCubeProgrammer/README.md @@ -6,7 +6,7 @@ # KSociety.SharpCubeProgrammer -KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.15.0. +KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.16.0. First unofficial and open source C# wrapper. @@ -19,13 +19,13 @@ It makes use of several 3rd party tools: ## Introduction -This is a C# wrapper for STM32 CubeProgrammer_API v2.15.0 (not fully tested). +This is a C# wrapper for STM32 CubeProgrammer_API v2.16.0 (not fully tested). This package does not contain any C/C++ runtimes (MSVC), and is meant to run on Windows operating systems only (for now). Please make sure you have updated the firmware of your ST-LINK V2 / V3, you can do this using STM32CubeProgrammer. The STM32 CubeProgrammer_API is a C-library, created by ST for ST-Link access to micro-controllers for the purpose of flash downloads or general memory access. The ST-Link drivers is required, and can be downloaded from st.com and installed [(STSW-LINK009)](https://www.st.com/en/development-tools/stsw-link009.html). -This has been tested on Windows 10, you don't need to install STM32CubeProgrammer. +This has been tested on Windows 10 and Windows 11, you don't need to install STM32CubeProgrammer. ### KSociety.SharpCubeProgrammer STM32CubeProgrammer_API C# wrapper, the first wrapper for C#. Any suggestions are welcome. @@ -255,5 +255,4 @@ The project is under Microsoft Reciprocal License [(MS-RL)](http://www.opensourc List of technologies, frameworks and libraries used for implementation: -- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces) for .NET Standard 2.0 only. - [Microsoft.Extensions.Logging.Abstractions](https://www.nuget.org/packages/Microsoft.Extensions.Logging.Abstractions) \ No newline at end of file diff --git a/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs b/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs index ab89664..9a3c874 100644 --- a/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs +++ b/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs @@ -4,18 +4,20 @@ namespace SharpCubeProgrammer { using System; using System.Collections.Generic; + using System.Diagnostics.CodeAnalysis; using System.Globalization; using System.IO; using System.Runtime.InteropServices; + using System.Threading; + using System.Threading.Tasks; using DeviceDataStructure; using Enum; using Interface; using Microsoft.Extensions.Logging; using Microsoft.Extensions.Logging.Abstractions; using Struct; - using Util; - public class CubeProgrammerApi : Disposable, ICubeProgrammerApi + public class CubeProgrammerApi : ICubeProgrammerApi { /// /// Synchronization object to protect loading the native library and its functions. This field is read-only. @@ -25,6 +27,9 @@ public class CubeProgrammerApi : Disposable, ICubeProgrammerApi private Native.SafeLibraryHandle _handle; private readonly ILogger _logger; + private const int DisposedFlag = 1; + private int _isDisposed; + #region [Constructor] public CubeProgrammerApi(ILogger logger = default) @@ -1517,8 +1522,27 @@ private CubeProgrammerError CheckResult(int result) #region [Dispose] - /// - protected override void Dispose(bool disposing) + /// + /// Performs application-defined tasks associated with freeing, releasing, or resetting unmanaged resources. + /// + [SuppressMessage("Microsoft.Design", "CA1063:ImplementIDisposableCorrectly", Justification = "Dispose is implemented correctly, FxCop just doesn't see it.")] + public void Dispose() + { + var wasDisposed = Interlocked.Exchange(ref this._isDisposed, DisposedFlag); + if (wasDisposed == DisposedFlag) + { + return; + } + + this.Dispose(true); + GC.SuppressFinalize(this); + } + + /// + /// Releases unmanaged and - optionally - managed resources. + /// + /// true to release both managed and unmanaged resources; false to release only unmanaged resources. + protected void Dispose(bool disposing) { if (disposing) { @@ -1528,8 +1552,51 @@ protected override void Dispose(bool disposing) // Free any unmanaged objects here. this._handle?.Dispose(); this._handle = null; + } + + /// + /// Gets a value indicating whether the current instance has been disposed. + /// + protected bool IsDisposed + { + get + { + Interlocked.MemoryBarrier(); + return this._isDisposed == DisposedFlag; + } + } + + /// + [SuppressMessage( + "Usage", + "CA1816:Dispose methods should call SuppressFinalize", + Justification = "DisposeAsync should also call SuppressFinalize (see various .NET internal implementations).")] + public ValueTask DisposeAsync() + { + // Still need to check if we've already disposed; can't do both. + var wasDisposed = Interlocked.Exchange(ref this._isDisposed, DisposedFlag); + if (wasDisposed != DisposedFlag) + { + GC.SuppressFinalize(this); + + // Always true, but means we get the similar syntax as Dispose, + // and separates the two overloads. + return this.DisposeAsync(true); + } + + return default; + } + + /// + /// Releases unmanaged and - optionally - managed resources, asynchronously. + /// + /// true to release both managed and unmanaged resources; false to release only unmanaged resources. + protected ValueTask DisposeAsync(bool disposing) + { + // Default implementation does a synchronous dispose. + this.Dispose(disposing); - base.Dispose(disposing); + return default; } #endregion diff --git a/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj b/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj index 9dadaf9..b178017 100644 --- a/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj +++ b/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj @@ -59,8 +59,7 @@ - - + all runtime; build; native; contentfiles; analyzers; buildtransitive diff --git a/src/01/KSociety.SharpCubeProgrammer/Util/Disposable.cs b/src/01/KSociety.SharpCubeProgrammer/Util/Disposable.cs deleted file mode 100644 index ce3d351..0000000 --- a/src/01/KSociety.SharpCubeProgrammer/Util/Disposable.cs +++ /dev/null @@ -1,87 +0,0 @@ -// Copyright © K-Society and contributors. All rights reserved. Licensed under the K-Society License. See LICENSE.TXT file in the project root for full license information. - -namespace SharpCubeProgrammer.Util -{ - using System; - using System.Diagnostics.CodeAnalysis; - using System.Threading; - using System.Threading.Tasks; - - /// - /// Base class for disposable objects. - /// - public class Disposable : IDisposable, IAsyncDisposable - { - private const int DisposedFlag = 1; - private int _isDisposed; - - /// - /// Performs application-defined tasks associated with freeing, releasing, or resetting unmanaged resources. - /// - [SuppressMessage("Microsoft.Design", "CA1063:ImplementIDisposableCorrectly", Justification = "Dispose is implemented correctly, FxCop just doesn't see it.")] - public void Dispose() - { - var wasDisposed = Interlocked.Exchange(ref this._isDisposed, DisposedFlag); - if (wasDisposed == DisposedFlag) - { - return; - } - - this.Dispose(true); - GC.SuppressFinalize(this); - } - - /// - /// Releases unmanaged and - optionally - managed resources. - /// - /// true to release both managed and unmanaged resources; false to release only unmanaged resources. - protected virtual void Dispose(bool disposing) - { - } - - /// - /// Gets a value indicating whether the current instance has been disposed. - /// - protected bool IsDisposed - { - get - { - Interlocked.MemoryBarrier(); - return this._isDisposed == DisposedFlag; - } - } - - /// - [SuppressMessage( - "Usage", - "CA1816:Dispose methods should call SuppressFinalize", - Justification = "DisposeAsync should also call SuppressFinalize (see various .NET internal implementations).")] - public ValueTask DisposeAsync() - { - // Still need to check if we've already disposed; can't do both. - var wasDisposed = Interlocked.Exchange(ref this._isDisposed, DisposedFlag); - if (wasDisposed != DisposedFlag) - { - GC.SuppressFinalize(this); - - // Always true, but means we get the similar syntax as Dispose, - // and separates the two overloads. - return this.DisposeAsync(true); - } - - return default; - } - - /// - /// Releases unmanaged and - optionally - managed resources, asynchronously. - /// - /// true to release both managed and unmanaged resources; false to release only unmanaged resources. - protected virtual ValueTask DisposeAsync(bool disposing) - { - // Default implementation does a synchronous dispose. - this.Dispose(disposing); - - return default; - } - } -} diff --git a/src/01/KSociety.Test/KSociety.Test.csproj b/src/01/KSociety.Test/KSociety.Test.csproj index 7cdb0fb..ad9b9c9 100644 --- a/src/01/KSociety.Test/KSociety.Test.csproj +++ b/src/01/KSociety.Test/KSociety.Test.csproj @@ -18,7 +18,7 @@ runtime; build; native; contentfiles; analyzers; buildtransitive all - + runtime; build; native; contentfiles; analyzers; buildtransitive all diff --git a/src/Directory.csproj.props b/src/Directory.csproj.props index f10a434..36a6c74 100644 --- a/src/Directory.csproj.props +++ b/src/Directory.csproj.props @@ -3,7 +3,7 @@ - netstandard2.0;netstandard2.1 + netstandard2.1;netstandard2.0 $([System.IO.Path]::GetFullPath($(MSBuildThisFileDirectory)ksociety.snk)) true diff --git a/version.json b/version.json index 55a8e79..f09c3d5 100644 --- a/version.json +++ b/version.json @@ -1,7 +1,7 @@ { "$schema": "https://raw.githubusercontent.com/dotnet/Nerdbank.GitVersioning/master/src/NerdBank.GitVersioning/version.schema.json", - "version": "0.2", - "assemblyVersion": "0.2", + "version": "0.3", + "assemblyVersion": "0.3", "nugetPackageVersion": { "semVer": 2 },