diff --git a/.gitignore b/.gitignore
index d615cce..89f3131 100644
--- a/.gitignore
+++ b/.gitignore
@@ -371,4 +371,6 @@ Visual Studio 2022/
Visual Studio 2022Templates/
Test/
src/01/Samples/Dojo/
-KSociety.Dojo.sln
\ No newline at end of file
+src/01/KSociety.ProgrammerTerminal
+KSociety.Dojo.sln
+KSociety.ProgrammerTerminal.sln
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x443.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x443.xml
new file mode 100644
index 0000000..9a27e50
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x443.xml
@@ -0,0 +1,504 @@
+
+
+
+ 0x443
+ STMicroelectronics
+ MCU
+
+ Cortex-M0+
+ STM32C01x
+ STM32C0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x1
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.1 V
+ BOR falling level 2 with threshold around 2.3 V
+ BOR falling level 3 with threshold around 2.6 V
+ BOR falling level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.0 V
+ BOR rising level 2 with threshold around 2.2 V
+ BOR rising level 3 with threshold around 2.5 V
+ BOR rising level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ HSE_NOT_REMAPPED
+
+ 0x15
+ 0x1
+ RW
+
+ HSE_NOT_REMAPPED enable
+ HSE_NOT_REMAPPED disable
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ RAM_PARITY_CHECK enable
+ RAM_PARITY_CHECK disable
+
+ 0x1
+
+
+ SECURE_MUXING_EN
+
+ 0x17
+ 0x1
+ RW
+
+ SECURE_MUXING_EN disable
+ SECURE_MUXING_EN enable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 pin (legacy mode)
+ nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 1, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Start offset of first PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+
+
+
+
+
+ PCROP1A_END
+ End offset of first PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased; Partial Mass Erase done
+ PCROP zone is erased when RDP is decreased Full Mass Erase done
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Start offset of second PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+
+
+
+
+
+ PCROP1B_END
+ End offset of second PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect
+ 0x0
+ 0x4
+ RW
+
+ 0xF
+
+
+ WRP1A_END
+ End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.
+ 0x10
+ 0x4
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect
+ 0x0
+ 0x4
+ RW
+
+ 0xF
+
+
+ WRP1B_END
+ End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect
+ 0x10
+ 0x4
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ FLASH security
+
+
+
+
+ SEC_SIZE
+ Securable memory area size
+ 0x0
+ 0x5
+ RW
+
+ 0x0
+
+
+ BOOT_LOCK
+ Used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x453.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x453.xml
new file mode 100644
index 0000000..4d3c7f2
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x453.xml
@@ -0,0 +1,504 @@
+
+
+
+ 0x453
+ STMicroelectronics
+ MCU
+
+ Cortex-M0+
+ STM32C03x
+ STM32C0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x1
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.1 V
+ BOR falling level 2 with threshold around 2.3 V
+ BOR falling level 3 with threshold around 2.6 V
+ BOR falling level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.0 V
+ BOR rising level 2 with threshold around 2.2 V
+ BOR rising level 3 with threshold around 2.5 V
+ BOR rising level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ HSE_NOT_REMAPPED
+
+ 0x15
+ 0x1
+ RW
+
+ HSE_NOT_REMAPPED enable
+ HSE_NOT_REMAPPED disable
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ RAM_PARITY_CHECK enable
+ RAM_PARITY_CHECK disable
+
+ 0x1
+
+
+ SECURE_MUXING_EN
+
+ 0x17
+ 0x1
+ RW
+
+ SECURE_MUXING_EN disable
+ SECURE_MUXING_EN enable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 pin (legacy mode)
+ nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 1, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Start offset of first PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+
+
+
+
+
+ PCROP1A_END
+ End offset of first PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased; Partial Mass Erase done
+ PCROP zone is erased when RDP is decreased Full Mass Erase done
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Start offset of second PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+
+
+
+
+
+ PCROP1B_END
+ End offset of second PCROP zone in bank 1
+ 0x0
+ 0x6
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect
+ 0x0
+ 0x4
+ RW
+
+ 0xF
+
+
+ WRP1A_END
+ End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.
+ 0x10
+ 0x4
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect
+ 0x0
+ 0x4
+ RW
+
+ 0xF
+
+
+ WRP1B_END
+ End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect
+ 0x10
+ 0x4
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ FLASH security
+
+
+
+
+ SEC_SIZE
+ Securable memory area size
+ 0x0
+ 0x5
+ RW
+
+ 0x0
+
+
+ BOOT_LOCK
+ Used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x455.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x455.xml
new file mode 100644
index 0000000..a291239
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x455.xml
@@ -0,0 +1,693 @@
+
+
+
+ 0x455
+ STMicroelectronics
+ MCU
+ Cortex-M33
+ STM32U535/STM32U545
+ STM32U5
+ ARM 32-bit Cortex-M33 based device
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)
+ Level 1, read protection of memories
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the VDD supply level threshold that activates/releases the reset.
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ TZEN
+ Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously
+ 0x1F
+ 0x1
+ RW
+
+ Global TrustZone security disabled
+ Global TrustZone security enabled
+
+ 0x0
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ SRAM134_RST
+ SRAM1, SRAM3 and SRAM4 erase upon system reset
+ 0xF
+ 0x1
+ RW
+
+ SRAM1, SRAM3 and SRAM4 erased when a system reset occurs
+ SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independant watchdog
+ Software independant watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ SWAP_BANK
+
+ 0x14
+ 0x1
+ RW
+
+ Bank 1 and bank 2 address are not swapped
+ Bank 1 and bank 2 address are swapped
+
+ 0x0
+
+
+ DUALBANK
+
+ 0x15
+ 0x1
+ RW
+
+ Single-bank flash memory with contiguous address in bank 1
+ Dual-bank flash memory with contiguous addresses
+
+ 0x1
+
+
+ BKPRAM_ECC
+ SRAM2 parity check enable
+ 0x16
+ 0x1
+ RW
+
+ Backup RAM ECC check enabled
+ Backup RAM ECC check disabled
+
+ 0x1
+
+
+ SRAM2_ECC
+ SRAM2 ECC detection and correction enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 ECC check enabled
+ SRAM2 ECC check disabled
+
+ 0x1
+
+
+ SRAM2_RST
+ SRAM2 Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ SRAM2 erased when a system reset occurs
+ SRAM2 is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ nBOOT0 option bit
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ PA15_PUPEN
+ PA15 pull-up enable
+ 0x1C
+ 0x1
+ RW
+
+ USB power delivery dead-battery enabled/ TDI pull-up deactivated
+ USB power delivery dead-battery disabled/ TDI pull-up activated
+
+ 0x1
+
+
+ IO_VDD_HSLV
+ High-speed IO at low VDD voltage configuration bit
+ 0x1D
+ 0x1
+ RW
+
+ High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)
+ High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)
+
+ 0x0
+
+
+ IO_VDDIO2_HSLV
+ High-speed IO at low VDDIO2 voltage configuration bit
+ 0x1E
+ 0x1
+ RW
+
+ High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)
+ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)
+
+ 0x0
+
+
+
+
+
+ Boot Configuration
+
+
+
+
+ NSBOOTADD0
+ Non-secure Boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x100000
+
+
+
+
+
+
+
+ NSBOOTADD1
+ Non-secure Boot base address 1
+ 0x7
+ 0x19
+ RW
+
+ 0x17F200
+
+
+
+
+
+
+
+ SECBOOTADD0
+ Secure boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x180000
+
+
+
+
+
+
+
+ BOOT_LOCK
+ The boot is always forced to base address value programmed in SECBOOTADD0
+ 0x0
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from base address memory
+
+ 0x0
+
+
+
+
+
+
+
+
+ SECWM1_PSTRT
+ Start page of first secure area
+ 0x0
+ 0x5
+ RW
+
+ 0x0
+
+
+ SECWM1_PEND
+ End page of first secure area
+ 0x10
+ 0x5
+ RW
+
+ 0x1F
+
+
+
+
+
+
+
+ HDP1_PEND
+ End page of first hide protection area
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ HDP1EN
+ Hide protection first area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 1
+ HDP first area is enabled
+
+ 0x0
+
+
+
+
+
+
+ Write Protection 1
+
+
+
+
+ WRP1A_PSTRT
+ Bank 1 WPR first area "A" start page
+ 0x0
+ 0x5
+ RW
+
+ 0x1F
+
+
+
+ WRP1A_PEND
+ Bank 1 WPR first area "A" end page
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ UNLOCK_1A
+ Bank 1 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1A start and end pages locked
+ WRP1A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+
+ WRP1B_PSTRT
+ Bank 1 WPR first area "B" start page
+ 0x0
+ 0x5
+ RW
+
+ 0x1F
+
+
+ WRP1B_PEND
+ Bank 1 WPR first area "B" end page
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ UNLOCK_1B
+ Bank 1 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1B start and end pages locked
+ WRP1B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+ Secure Area 2
+
+
+
+
+ SECWM2_PSTRT
+ Start page of second secure area
+ 0x0
+ 0x5
+ RW
+
+ 0x1F
+
+
+ SECWM2_PEND
+ End page of second secure area
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ HDP2_PEND
+ End page of second hide protection area
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ HDP2EN
+ Hide protection second area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 2
+ HDP second area is enabled
+
+ 0x0
+
+
+
+
+
+
+
+
+
+ Write Protection 2
+
+
+
+
+ WRP2A_PSTRT
+ Bank 2 WPR first area "A" start page
+ 0x0
+ 0x5
+ RW
+
+ 0x1F
+
+
+ WRP2A_PEND
+ Bank 2 WPR first area "A" end page
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ UNLOCK_2A
+ Bank 2 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2A start and end pages locked
+ WRP2A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+
+ WRP2B_PSTRT
+ Bank 2 WPR first area "B" start page
+ 0x0
+ 0x5
+ RW
+
+ 0x1F
+
+
+ WRP2B_PEND
+ Bank 2 WPR first area "B" end page
+ 0x10
+ 0x5
+ RW
+
+ 0x0
+
+
+ UNLOCK_2B
+ Bank 2 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2B start and end pages locked
+ WRP2B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+ OEM Keys
+
+
+
+
+ OEM1KEY [0:31]
+ OEM1 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM1KEY [63:32]
+ OEM1 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [0:31]
+ OEM2 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [63:32]
+ OEM2 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml
new file mode 100644
index 0000000..8b91525
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x456.xml
@@ -0,0 +1,502 @@
+
+
+
+ 0x456
+ STMicroelectronics
+ MCU
+ Cortex-M0+
+ STM32G051/STM32G061
+ STM32G0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Dual
+ 0x4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x0
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.1 V
+ BOR rising level 2 with threshold around 2.3 V
+ BOR rising level 3 with threshold around 2.6 V
+ BOR rising level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.0 V
+ BOR falling level 2 with threshold around 2.2 V
+ BOR falling level 3 with threshold around 2.5 V
+ BOR falling level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ SRAM parity check enable
+ SRAM parity check disable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 signal is defined by BOOT0 pin value (legacy mode)
+ BOOT0 signal is defined by nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Flash Area A PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1A_END
+ Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Flash Area B PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1B_END
+ Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ FLASH security
+
+
+
+
+ BOOT_LOCK
+ used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+ SEC_SIZE
+ Securable memory area size
+ 0x0
+ 0x6
+ RW
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml
new file mode 100644
index 0000000..0b29770
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x460.xml
@@ -0,0 +1,504 @@
+
+
+
+ 0x460
+ STMicroelectronics
+ MCU
+ Cortex-M0+
+ STM32G07x/STM32G08x
+ STM32G0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Dual
+ 0x4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x0
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.1 V
+ BOR rising level 2 with threshold around 2.3 V
+ BOR rising level 3 with threshold around 2.6 V
+ BOR rising level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.0 V
+ BOR falling level 2 with threshold around 2.2 V
+ BOR falling level 3 with threshold around 2.5 V
+ BOR falling level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ SRAM parity check enable
+ SRAM parity check disable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 signal is defined by BOOT0 pin value (legacy mode)
+ BOOT0 signal is defined by nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Flash Area A PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1A_END
+ Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Flash Area B PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1B_END
+ Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+ FLASH security
+
+
+
+
+ BOOT_LOCK
+ used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+ SEC_SIZE
+ Securable memory area size
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x462.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x462.xml
new file mode 100644
index 0000000..4fc3793
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x462.xml
@@ -0,0 +1,401 @@
+
+
+
+ 0x462
+ STMicroelectronics
+ MCU
+ Cortex-M4
+ STM32L45x/L46x
+ STM32L4
+ ARM 32-bit Cortex-M4 based device
+
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independant watchdog
+ Software independant watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ nBOOT1
+ This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory.
+ 0x17
+ 0x1
+ RW
+
+ Boot from embedded SRAM1 when BOOT0=1
+ Boot from system memory when BOOT0=1
+
+ 0x1
+
+
+ SRAM2_PE
+
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 parity check enable
+ SRAM2 parity check disable
+
+ 0x1
+
+
+ SRAM2_RST
+
+ 0x19
+ 0x1
+ RW
+
+ SRAM2 erased when a system reset occurs
+ SRAM2 is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ This option bit sets the BOOT0 value only when nSWBOOT0=0
+ 0x1B
+ 0x1
+ RW
+
+ BOOT0 = 1, boot memory depends on nBOOT1 value
+ BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1_STRT
+ Flash Bank 1 PCROP start address
+ 0x0
+ 0x10
+ RW
+
+ 0xFFFF
+
+
+
+
+
+
+
+ PCROP1_END
+ Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x10
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x1
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml
new file mode 100644
index 0000000..ff7f157
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x466.xml
@@ -0,0 +1,636 @@
+
+
+
+ 0x466
+ STMicroelectronics
+ MCU
+ Cortex-M0+
+ STM32G03x/STM32G04x
+ STM32G0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Dual
+ 0x4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x0
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.0 V
+ BOR falling level 2 with threshold around 2.2 V
+ BOR falling level 3 with threshold around 2.5 V
+ BOR falling level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.1 V
+ BOR rising level 2 with threshold around 2.3 V
+ BOR rising level 3 with threshold around 2.6 V
+ BOR rising level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ SRAM parity check enable
+ SRAM parity check disable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 signal is defined by BOOT0 pin value (legacy mode)
+ BOOT0 signal is defined by nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 1, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Flash Area A in Bank1 PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1A_END
+ Flash Area A in Bank1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP2A_STRT
+ Flash Area A in Bank 2 PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP2A_END
+ Flash Area A in Bank 2 PCROP end address
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Flash Area B in Bank1 PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1B_END
+ Flash Area B in Bank1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP2B_STRT
+ Flash Area B in Bank 2 PCROP start address
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP2B_END
+ Flash Area B in Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP2A_STRT
+ The address of the first page of the Bank 2 WRP first area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP2A_END
+ The address of the last page of the Bank 2 WRP first area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP2B_STRT
+ The address of the first page of the Bank 2 WRP second area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP2B_END
+ The address of the last page of the Bank 2 WRP second area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ FLASH security
+
+
+
+
+ BOOT_LOCK
+ used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+ SEC_SIZE
+ Securable memory area size, Bank 1
+ 0x0
+ 0x7
+ RW
+
+ 0x0
+
+
+ SEC_SIZE2
+ Securable memory area size, Bank 2
+ 0x0
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml
new file mode 100644
index 0000000..6fb4d62
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x467.xml
@@ -0,0 +1,697 @@
+
+
+
+ 0x467
+ STMicroelectronics
+ MCU
+
+ Cortex-M0+
+ STM32G0B0xx/B1xx/C1xx
+ STM32G0
+ ARM 32-bit Cortex-M0+ based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Dual
+ 0x4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_EN
+
+ 0x8
+ 0x1
+ RW
+
+ Configurable brown out reset disabled, power-on reset defined by POR/PDR levels
+ Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account
+
+ 0x0
+
+
+ BORF_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x2
+ RW
+
+ BOR falling level 1 with threshold around 2.0 V
+ BOR falling level 2 with threshold around 2.2 V
+ BOR falling level 3 with threshold around 2.5 V
+ BOR falling level 4 with threshold around 2.8 V
+
+ 0x3
+
+
+ BORR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0xB
+ 0x2
+ RW
+
+ BOR rising level 1 with threshold around 2.1 V
+ BOR rising level 2 with threshold around 2.3 V
+ BOR rising level 3 with threshold around 2.6 V
+ BOR rising level 4 with threshold around 2.9 V
+
+ 0x3
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xF
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ nSWAP_BANK
+
+ 0x14
+ 0x1
+ RW
+
+ Bank 1
+ Bank 2
+
+ 0x1
+
+
+ DUAL_BANK
+
+ 0x15
+ 0x1
+ RW
+
+ 256 Kbytes/512 Kbytes single-bank Flash memory(contiguous addresses in Bank 1)
+ 256 Kbytes/512 Kbytes dual-bank Flash memory
+
+ 0x1
+
+
+ RAM_PARITY_CHECK
+
+ 0x16
+ 0x1
+ RW
+
+ SRAM parity check enable
+ SRAM parity check disable
+
+ 0x1
+
+
+ nBOOT_SEL
+
+ 0x18
+ 0x1
+ RW
+
+ BOOT0 signal is defined by BOOT0 pin value (legacy mode)
+ BOOT0 signal is defined by nBOOT0 option bit
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x19
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ nBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1B
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1D
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Flash Area A PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1A_END
+ Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Flash Area B PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1B_END
+ Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP2A_STRT
+ Flash Area A PCROP2 start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP2A_END
+ Flash Area A PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP2B_STRT
+ Flash Area B PCROP2 start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP2B_END
+ Flash Area B PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ WRP2A_STRT
+ The address of the first page of the Bank 2 WRP first area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP2A_END
+ The address of the last page of the Bank 2 WRP first area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP2B_STRT
+ The address of the first page of the Bank 2 WRP second area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP2B_END
+ The address of the last page of the Bank 2 WRP second area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ FLASH security
+
+
+
+
+ BOOT_LOCK
+ used to force boot from user area
+ 0x10
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from Main Flash memory
+
+ 0x0
+
+
+ SEC_SIZE
+ Securable memory for Bank 1
+ 0x0
+ 0x8
+ RW
+ 0x0
+
+
+ SEC_SIZE2
+ Securable memory for Bank 2 On Dual Bank device,otherwise reserved
+ 0x14
+ 0x8
+ RW
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x468.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x468.xml
new file mode 100644
index 0000000..7936cc2
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x468.xml
@@ -0,0 +1,454 @@
+
+
+
+ 0x468
+ STMicroelectronics
+ MCU
+ Cortex-M4
+ STM32G43x/G44x
+ STM32G4
+ ARM 32-bit Cortex-M4 based device
+
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, no debug
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x17
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ SRAM_PE
+ SRAM1 and CCM SRAM parity check enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM1 and CCM SRAM parity check enable
+ SRAM1 and CCM SRAM parity check disable
+
+ 0x1
+
+
+ CCMSRAM_RST
+ CCM SRAM Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ CCM SRAM erased when a system reset occurs
+ CCM SRAM is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PB8/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ This option bit sets the BOOT0 value only when nSWBOOT0=0
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1C
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1E
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1_STRT
+ Flash Bank 1 PCROP start address
+ 0x0
+ 0xE
+ RW
+
+ 0x3FFF
+
+
+
+
+
+
+
+ PCROP1_END
+ Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0xE
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x6
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x6
+ RW
+
+ 0x3F
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x6
+ RW
+
+ 0x0
+
+
+
+
+
+ Secure Protection
+
+
+
+
+ SEC_SIZE1
+ sets the number of pages used in the bank 1 securable area
+ 0x0
+ 0x8
+ RW
+ 0x0
+
+
+ BOOT_LOCK
+ Unique boot entry point
+ 0x10
+ 0x1
+ RW
+
+ This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.
+ the boot will be done from user flash only, whatever the RDP level
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml
new file mode 100644
index 0000000..a5f3f57
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x469.xml
@@ -0,0 +1,654 @@
+
+
+
+ 0x469
+ STMicroelectronics
+ MCU
+ Cortex-M4
+ STM32G47x/G48x
+ STM32G4
+ Category 3 devices, ARM 32-bit Cortex-M4 based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, no debug
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ BFB2
+
+ 0x14
+ 0x1
+ RW
+
+ Dual-bank boot disable
+ Dual-bank boot enable
+
+ 0x0
+
+
+ DBANK
+
+ 0x16
+ 0x1
+ RW
+
+ Single bank mode with 128 bits data read width
+ Dual bank mode with 64 bits data
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x17
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ SRAM_PE
+ SRAM1 and CCM SRAM parity check enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM1 and CCM SRAM parity check enable
+ SRAM1 and CCM SRAM parity check disable
+
+ 0x1
+
+
+ CCMSRAM_RST
+ CCM SRAM Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ CCM SRAM erased when a system reset occurs
+ CCM SRAM is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PB8/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ This option bit sets the BOOT0 value only when nSWBOOT0=0
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1C
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1E
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+
+
+
+ PCROP Protection (Bank 1)
+
+
+
+
+ PCROP1_STRT
+ Flash Bank 1 PCROP start address
+ 0x0
+ 0xF
+ RW
+ 0x7FFF
+
+
+
+
+
+
+
+ PCROP1_END
+ Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0xF
+ RW
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+ Write Protection (Bank 1)
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x7
+ RW
+ 0x7F
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x7
+ RW
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x7
+ RW
+ 0x7F
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x7
+ RW
+ 0x0
+
+
+
+
+
+
+
+
+ PCROP Protection (Bank 2)
+
+
+
+
+ PCROP2_STRT
+ Flash Bank 2 PCROP start address
+ 0x0
+ 0xF
+ RW
+ 0x7FFF
+
+
+
+
+
+
+
+ PCROP2_END
+ Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0xF
+ RW
+ 0x0
+
+
+
+
+
+ Write Protection (Bank 2)
+
+
+
+
+ WRP2A_STRT
+ The address of first page of the Bank 2 WRP first area
+ 0x0
+ 0x7
+ RW
+ 0x7F
+
+
+ WRP2A_END
+ The address of last page of the Bank 2 WRP first area
+ 0x10
+ 0x7
+ RW
+ 0x0
+
+
+
+
+
+
+
+ WRP2B_STRT
+ The address of first page of the Bank 2 WRP second area
+ 0x0
+ 0x7
+ RW
+ 0x7F
+
+
+ WRP2B_END
+ The address of last page of the Bank 2 WRP second area
+ 0x10
+ 0x7
+ RW
+ 0x0
+
+
+
+
+
+
+
+
+ Secure Protection (Bank 1)
+
+
+
+
+ SEC_SIZE1
+ sets the number of pages used in the bank 1 securable area
+ 0x0
+ 0x8
+ RW
+ 0x0
+
+
+ BOOT_LOCK
+ Unique boot entry point
+ 0x10
+ 0x1
+ RW
+
+ This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.
+ the boot will be done from user flash only, whatever the RDP level
+
+ 0x0
+
+
+
+
+
+ Secure Protection (Bank 2)
+
+
+
+
+ SEC_SIZE2
+ sets the number of pages used in the bank 2 securable area
+ 0x0
+ 0x8
+ RW
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml
new file mode 100644
index 0000000..08a4483
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x479.xml
@@ -0,0 +1,479 @@
+
+
+
+ 0x479
+ STMicroelectronics
+ MCU
+ Cortex-M4
+ STM32G491xC/E
+ STM32G4
+ Category 3 devices, ARM 32-bit Cortex-M4 based device
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0xFF
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x10
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, no debug
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+
+ 0x1
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ BFB2
+
+ 0x14
+ 0x1
+ RW
+
+ Dual-bank boot disable
+ Dual-bank boot enable
+
+ 0x0
+
+
+ nBOOT1
+
+ 0x17
+ 0x1
+ RW
+
+ Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1
+ Boot from Flash if BOOT0 = 0, otherwise system memory
+
+ 0x1
+
+
+ SRAM_PE
+ SRAM1 and CCM SRAM parity check enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM1 and CCM SRAM parity check enable
+ SRAM1 and CCM SRAM parity check disable
+
+ 0x1
+
+
+ CCMSRAM_RST
+ CCM SRAM Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ CCM SRAM erased when a system reset occurs
+ CCM SRAM is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PB8/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ This option bit sets the BOOT0 value only when nSWBOOT0=0
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ NRST_MODE
+
+ 0x1C
+ 0x2
+ RW
+
+ Reserved
+ Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
+ GPIO: standard GPIO pad functionality, only internal RESET possible
+ Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
+
+ 0x3
+
+
+ IRHEN
+ Internal reset holder enable bit
+ 0x1E
+ 0x1
+ RW
+
+ Internal resets are propagated as simple pulse on NRST pin
+ Internal resets drives NRST pin low until it is seen as low level
+
+ 0x1
+
+
+ PB4_PUEN
+
+ 0x16
+ 0x1
+ RW
+
+ USB power delivery dead-battery enabled/ TDI pull-up deactivated
+ USB power delivery dead-battery disabled/ TDI pull-up activated
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1_STRT
+ Flash PCROP start address
+ 0x0
+ 0x10
+ RW
+
+ 0xFFFF
+
+
+
+
+
+
+
+ PCROP1_END
+ Flash PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0
+ 0x0
+ 0x10
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of WRP first area
+ 0x0
+ 0x8
+ RW
+ 0x7F
+
+
+ WRP1A_END
+ The address of the last page of WRP first area
+ 0x10
+ 0x8
+ RW
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of WRP second area
+ 0x0
+ 0x8
+ RW
+ 0x7F
+
+
+ WRP1B_END
+ The address of the last page of WRP second area
+ 0x10
+ 0x8
+ RW
+ 0x0
+
+
+
+
+
+ Secure Protection
+
+
+
+
+ SEC_SIZE1
+ sets the number of pages used in the bank 1 securable area
+ 0x0
+ 0x9
+ RW
+ 0x0
+
+
+ BOOT_LOCK
+ Unique boot entry point
+ 0x10
+ 0x1
+ RW
+
+ This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.
+ the boot will be done from user flash only, whatever the RDP level
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x480.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x480.xml
new file mode 100644
index 0000000..169f8b9
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x480.xml
@@ -0,0 +1,1250 @@
+
+
+
+ 0x480
+ STMicroelectronics
+ MCU
+ Cortex-M7
+ STM32H7A/B
+ STM32H7
+ ARM 32-bit Cortex-M7 based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Dual
+ 0x20
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dual
+ 0x20
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x20
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x8
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x2
+ 0x2
+ RW
+
+ reset level OFF
+ reset level is set to 2.1 V
+ reset level is set to 2.4 V
+ reset level is set to 2.7 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ IWDG1_SW
+
+ 0x4
+ 0x1
+ RW
+
+ Independent watchdog is controlled by hardware
+ Independent watchdog is controlled by software
+
+ 0x1
+
+
+ NRST_STOP
+
+ 0x6
+ 0x1
+ RW
+
+ STOP mode on Domain 1 is entering with reset
+ STOP mode on Domain 1 is entering without reset
+
+ 0x1
+
+
+ NRST_STBY
+
+ 0x7
+ 0x1
+ RW
+
+ STANDBY mode on Domain 1 is entering with reset
+ STANDBY mode on Domain 1 is entering without reset
+
+ 0x1
+
+
+ VDDMMC_HSLV
+
+ 0x10
+ 0x1
+ RW
+
+ I/O speed optimization at low-voltage disabled
+ VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed
+
+ 0x0
+
+
+ IWDG_FZ_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Independent watchdog is freezed in STOP mode
+ Independent watchdog is running in STOP mode
+
+ 0x1
+
+
+ IWDG_FZ_SDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Independent watchdog is freezed in STANDBY mode
+ Independent watchdog is running in STANDBY mode
+
+ 0x1
+
+
+ SECURITY
+
+ 0x15
+ 0x1
+ RW
+
+ Security feature disabled
+ Security feature enabled
+
+ 0x0
+
+
+ VDDIO_HSLV
+
+ 0x1D
+ 0x1
+ RW
+
+ Product working in the full voltage range,I/O speed optimization at low-voltage disabled
+ VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed
+
+ 0x0
+
+
+ SWAP_BANK_OPT
+
+ 0x1F
+ 0x1
+ RW
+
+ after boot loading, no swap for user sectors
+ after boot loading, user sectors swapped
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PROT_AREA_START1
+ Flash Bank 1 PCROP start address
+ 0x0
+ 0xC
+ RW
+
+ 0xFF
+
+
+ PROT_AREA_END1
+ Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMEP1
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x0
+
+
+
+
+
+
+
+ PROT_AREA_START2
+ Flash Bank 2 PCROP start address
+ 0x0
+ 0xC
+ RW
+
+ 0xFF
+
+
+ PROT_AREA_END2
+ Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMEP2
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x0
+
+
+
+
+
+ Secure Protection
+
+
+
+
+ SEC_AREA_START1
+ Flash Bank 1 secure area start address
+ 0x0
+ 0xC
+ RW
+
+ 0xFF
+
+
+ SEC_AREA_END1
+ Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMES1
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x0
+
+
+
+
+
+
+
+ SEC_AREA_START2
+ Flash Bank 2 secure area start address
+ 0x0
+ 0xC
+ RW
+
+ 0xFF
+
+
+ SEC_AREA_END2
+ Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMES2
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x0
+
+
+
+
+
+ DTCM RAM Protection
+
+
+
+
+ ST_RAM_SIZE
+
+ 0x13
+ 0x2
+ RW
+
+ 2 KB
+ 4 KB
+ 8 KB
+ 16 KB
+
+ 0x3
+
+
+
+
+
+ Write Protection
+
+
+
+
+ nWRP0
+
+ 0x0
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP1
+
+ 0x1
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP2
+
+ 0x2
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP3
+
+ 0x3
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP4
+
+ 0x4
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP5
+
+ 0x5
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP6
+
+ 0x6
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP7
+
+ 0x7
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP8
+
+ 0x8
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP9
+
+ 0x9
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP10
+
+ 0xA
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP11
+
+ 0xB
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP12
+
+ 0xC
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP13
+
+ 0xD
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP14
+
+ 0xE
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP15
+
+ 0xF
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP16
+
+ 0x10
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP17
+
+ 0x11
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP18
+
+ 0x12
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP19
+
+ 0x13
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP20
+
+ 0x14
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP21
+
+ 0x15
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP22
+
+ 0x16
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP23
+
+ 0x17
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP24
+
+ 0x18
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP25
+
+ 0x19
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP26
+
+ 0x1A
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP27
+
+ 0x1B
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP28
+
+ 0x1C
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP29
+
+ 0x1D
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP30
+
+ 0x1E
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP31
+
+ 0x1F
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+
+
+
+
+
+ nWRP32
+
+ 0x0
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP33
+
+ 0x1
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP34
+
+ 0x2
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP35
+
+ 0x3
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP36
+
+ 0x4
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP37
+
+ 0x5
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP38
+
+ 0x6
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP39
+
+ 0x7
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP40
+
+ 0x8
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP41
+
+ 0x9
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP42
+
+ 0xA
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP43
+
+ 0xB
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP44
+
+ 0xC
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP45
+
+ 0xD
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP46
+
+ 0xE
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP47
+
+ 0xF
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP48
+
+ 0x10
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP49
+
+ 0x11
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP50
+
+ 0x12
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP51
+
+ 0x13
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP52
+
+ 0x14
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP53
+
+ 0x15
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP54
+
+ 0x16
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP55
+
+ 0x17
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP56
+
+ 0x18
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP57
+
+ 0x19
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP58
+
+ 0x1A
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP59
+
+ 0x1B
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP60
+
+ 0x1C
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP61
+
+ 0x1D
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP62
+
+ 0x1E
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP63
+
+ 0x1F
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+
+
+
+ Boot address Option Bytes
+
+
+
+
+ BOOT_ADD0
+
+ 0x0
+ 0x10
+ RW
+
+ 0x0800
+
+
+ BOOT_ADD1
+
+ 0x10
+ 0x10
+ RW
+
+ 0x1FF0
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x481.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x481.xml
new file mode 100644
index 0000000..22bd22e
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x481.xml
@@ -0,0 +1,700 @@
+
+
+
+ 0x481
+ STMicroelectronics
+ MCU
+ Cortex-M33
+ STM32U59x
+ STM32U5
+ ARM 32-bit Cortex-M33 based device
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)
+ Level 1, read protection of memories
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the VDD supply level threshold that activates/releases the reset.
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ TZEN
+ Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously
+ 0x1F
+ 0x1
+ RW
+
+ Global TrustZone security disabled
+ Global TrustZone security enabled
+
+ 0x0
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ SRAM_RST
+ SRAM1, SRAM3 and SRAM4 and SRAM5 erase upon system reset
+ 0xF
+ 0x1
+ RW
+
+ SRAM1, SRAM3 and SRAM4 and SRAM5 erased when a system reset occurs
+ SRAM1, SRAM3 and SRAM4 and SRAM5 not erased when a system reset occurs
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independant watchdog
+ Software independant watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ SWAP_BANK
+
+ 0x14
+ 0x1
+ RW
+
+ Bank 1 and bank 2 address are not swapped
+ Bank 1 and bank 2 address are swapped
+
+ 0x0
+
+
+ DBANK
+ Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices
+ 0x15
+ 0x1
+ RW
+
+ Single bank Flash with contiguous address in bank 1
+ Dual-bank Flash with contiguous addresses
+
+ 0x1
+
+
+ BKPRAM_ECC
+ SRAM2 parity check enable
+ 0x16
+ 0x1
+ RW
+
+ Backup RAM ECC check enabled
+ Backup RAM ECC check disabled
+
+ 0x1
+
+
+ SRAM3_ECC
+ SRAM3 ECC detection and correction enable
+ 0x17
+ 0x1
+ RW
+
+ SRAM3 ECC check enabled
+ SRAM3 ECC check disabled
+
+ 0x1
+
+
+ SRAM2_ECC
+ SRAM2 ECC detection and correction enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 ECC check enabled
+ SRAM2 ECC check disabled
+
+ 0x1
+
+
+ SRAM2_RST
+ SRAM2 Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ SRAM2 erased when a system reset occurs
+ SRAM2 is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ nBOOT0 option bit
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ PA15_PUPEN
+ PA15 pull-up enable
+ 0x1C
+ 0x1
+ RW
+
+ USB power delivery dead-battery enabled/ TDI pull-up deactivated
+ USB power delivery dead-battery disabled/ TDI pull-up activated
+
+ 0x1
+
+
+ IO_VDD_HSLV
+ High-speed IO at low VDD voltage configuration bit
+ 0x1D
+ 0x1
+ RW
+
+ High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)
+ High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)
+
+ 0x0
+
+
+ IO_VDDIO2_HSLV
+ High-speed IO at low VDDIO2 voltage configuration bit
+ 0x1E
+ 0x1
+ RW
+
+ High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)
+ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)
+
+ 0x0
+
+
+
+
+
+ Boot Configuration
+
+
+
+
+ NSBOOTADD0
+ Non-secure Boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x100000
+
+
+
+
+
+
+
+ NSBOOTADD1
+ Non-secure Boot base address 1
+ 0x7
+ 0x19
+ RW
+
+ 0x17F200
+
+
+
+
+
+
+
+ SECBOOTADD0
+ Secure boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x180000
+
+
+
+
+
+
+
+ BOOT_LOCK
+ The boot is always forced to base address value programmed in SECBOOTADD0
+ 0x0
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from base address memory
+
+ 0x0
+
+
+
+
+
+
+
+ SECWM1_PSTRT
+ Start page of first secure area
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ SECWM1_PEND
+ End page of first secure area
+ 0x10
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ HDP1_PEND
+ End page of first hide protection area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ HDP1EN
+ Hide protection first area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 1
+ HDP first area is enabled
+
+ 0x0
+
+
+
+
+
+ Write Protection 1
+
+
+
+
+ WRP1A_PSTRT
+ Bank 1 WPR first area "A" start page
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1A_PEND
+ Bank 1 WPR first area "A" end page
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ UNLOCK_1A
+ Bank 1 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1A start and end pages locked
+ WRP1A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+ WRP1B_PSTRT
+ Bank 1 WPR first area "B" start page
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1B_PEND
+ Bank 1 WPR first area "B" end page
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ UNLOCK_1B
+ Bank 1 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1B start and end pages locked
+ WRP1B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+ Secure Area 2
+
+
+
+
+ SECWM2_PSTRT
+ Start page of second secure area
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ SECWM2_PEND
+ End page of second secure area
+ 0x10
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ HDP2_PEND
+ End page of second hide protection area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ HDP2EN
+ Hide protection second area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 2
+ HDP second area is enabled
+
+ 0x0
+
+
+
+
+
+
+
+
+ Write Protection 2
+
+
+
+
+ WRP2A_PSTRT
+ Bank 2 WPR first area "A" start page
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP2A_PEND
+ Bank 2 WPR first area "A" end page
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ UNLOCK_2A
+ Bank 2 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2A start and end pages locked
+ WRP2A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+ WRP2B_PSTRT
+ Bank 2 WPR first area "B" start page
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP2B_PEND
+ Bank 2 WPR first area "B" end page
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+ UNLOCK_2B
+ Bank 2 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2B start and end pages locked
+ WRP2B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+ OEM Keys
+
+
+
+
+ OEM1KEY [0:31]
+ OEM1 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM1KEY [63:32]
+ OEM1 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [0:31]
+ OEM2 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [63:32]
+ OEM2 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x482.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x482.xml
new file mode 100644
index 0000000..7ba2acd
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x482.xml
@@ -0,0 +1,712 @@
+
+
+
+ 0x482
+ STMicroelectronics
+ MCU
+ Cortex-M33
+ STM32U575/STM32U585
+ STM32U5
+ ARM 32-bit Cortex-M33 based device
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)
+ Level 1, read protection of memories
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the VDD supply level threshold that activates/releases the reset.
+ 0x8
+ 0x3
+ RW
+
+ BOR Level 0, reset level threshold is around 1.7 V
+ BOR Level 1, reset level threshold is around 2.0 V
+ BOR Level 2, reset level threshold is around 2.2 V
+ BOR Level 3, reset level threshold is around 2.5 V
+ BOR Level 4, reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ TZEN
+ Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously
+ 0x1F
+ 0x1
+ RW
+
+ Global TrustZone security disabled
+ Global TrustZone security enabled
+
+ 0x0
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering Stop mode
+ No reset generated when entering Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering Standby mode
+ No reset generated when entering Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ SRAM134_RST
+ SRAM1, SRAM3 and SRAM4 erase upon system reset
+ 0xF
+ 0x1
+ RW
+
+ SRAM1, SRAM3 and SRAM4 erased when a system reset occurs
+ SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independant watchdog
+ Software independant watchdog
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Freeze IWDG counter in stop mode
+ IWDG counter active in stop mode
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Freeze IWDG counter in standby mode
+ IWDG counter active in standby mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ SWAP_BANK
+
+ 0x14
+ 0x1
+ RW
+
+ Bank 1 and bank 2 address are not swapped
+ Bank 1 and bank 2 address are swapped
+
+ 0x0
+
+
+ DBANK
+ Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices
+ 0x15
+ 0x1
+ RW
+
+ Single bank Flash with contiguous address in bank 1
+ Dual-bank Flash with contiguous addresses
+
+ 0x1
+
+
+ BKPRAM_ECC
+ SRAM2 parity check enable
+ 0x16
+ 0x1
+ RW
+
+ Backup RAM ECC check enabled
+ Backup RAM ECC check disabled
+
+ 0x1
+
+
+ SRAM3_ECC
+ SRAM3 ECC detection and correction enable
+ 0x17
+ 0x1
+ RW
+
+ SRAM3 ECC check enabled
+ SRAM3 ECC check disabled
+
+ 0x1
+
+
+ SRAM2_ECC
+ SRAM2 ECC detection and correction enable
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 ECC check enabled
+ SRAM2 ECC check disabled
+
+ 0x1
+
+
+ SRAM2_RST
+ SRAM2 Erase when system reset
+ 0x19
+ 0x1
+ RW
+
+ SRAM2 erased when a system reset occurs
+ SRAM2 is not erased when a system reset occurs
+
+ 0x1
+
+
+ nSWBOOT0
+ Software BOOT0
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ nBOOT0
+ nBOOT0 option bit
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0 = 0
+ nBOOT0 = 1
+
+ 0x1
+
+
+ PA15_PUPEN
+ PA15 pull-up enable
+ 0x1C
+ 0x1
+ RW
+
+ USB power delivery dead-battery enabled/ TDI pull-up deactivated
+ USB power delivery dead-battery disabled/ TDI pull-up activated
+
+ 0x1
+
+
+ IO_VDD_HSLV
+ High-speed IO at low VDD voltage configuration bit
+ 0x1D
+ 0x1
+ RW
+
+ High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)
+ High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)
+
+ 0x0
+
+
+ IO_VDDIO2_HSLV
+ High-speed IO at low VDDIO2 voltage configuration bit
+ 0x1E
+ 0x1
+ RW
+
+ High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)
+ High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)
+
+ 0x0
+
+
+
+
+
+ Boot Configuration
+
+
+
+
+ NSBOOTADD0
+ Non-secure Boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x100000
+
+
+
+
+
+
+
+ NSBOOTADD1
+ Non-secure Boot base address 1
+ 0x7
+ 0x19
+ RW
+
+ 0x17F200
+
+
+
+
+
+
+
+ SECBOOTADD0
+ Secure boot base address 0
+ 0x7
+ 0x19
+ RW
+
+ 0x180000
+
+
+
+
+
+
+
+ BOOT_LOCK
+ The boot is always forced to base address value programmed in SECBOOTADD0
+ 0x0
+ 0x1
+ RW
+
+ Boot based on the pad/option bit configuration
+ Boot forced from base address memory
+
+ 0x0
+
+
+
+
+
+
+
+ SECWM1_PSTRT
+ Start page of first secure area
+ 0x0
+ 0x7
+ RW
+
+ 0x0
+
+
+ SECWM1_PEND
+ End page of first secure area
+ 0x10
+ 0x7
+ RW
+
+ 0x7F
+
+
+
+
+
+
+
+ HDP1_PEND
+ End page of first hide protection area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ HDP1EN
+ Hide protection first area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 1
+ HDP first area is enabled
+
+ 0x0
+
+
+
+
+
+ Write Protection 1
+
+
+
+
+ WRP1A_PSTRT
+ Bank 1 WPR first area "A" start page
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1A_PEND
+ Bank 1 WPR first area "A" end page
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ UNLOCK_1A
+ Bank 1 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1A start and end pages locked
+ WRP1A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+ WRP1B_PSTRT
+ Bank 1 WPR first area "B" start page
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1B_PEND
+ Bank 1 WPR first area "B" end page
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ UNLOCK_1B
+ Bank 1 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP1B start and end pages locked
+ WRP1B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+ Secure Area 2
+
+
+
+
+ SECWM2_PSTRT
+ Start page of second secure area
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ SECWM2_PEND
+ End page of second secure area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ HDP2_PEND
+ End page of second hide protection area
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ HDP2EN
+ Hide protection second area enable
+ 0x1F
+ 0x1
+ RW
+
+ No HDP area 2
+ HDP second area is enabled
+
+ 0x0
+
+
+
+
+
+
+
+
+ Write Protection 2
+
+
+
+
+ WRP2A_PSTRT
+ Bank 2 WPR first area "A" start page
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP2A_PEND
+ Bank 2 WPR first area "A" end page
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ UNLOCK_2A
+ Bank 2 WPR first area A unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2A start and end pages locked
+ WRP2A start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+
+
+ WRP2B_PSTRT
+ Bank 2 WPR first area "B" start page
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP2B_PEND
+ Bank 2 WPR first area "B" end page
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+ UNLOCK_2B
+ Bank 2 WPR first area B unlock
+ 0x1F
+ 0x1
+ RW
+
+ WRP2B start and end pages locked
+ WRP2B start and end pages unlocked
+
+ 0x1
+
+
+
+
+
+ OEM Keys
+
+
+
+
+ KEYSDIVERS
+ 0x0
+ 0x20
+ RW
+ 0x0
+
+
+
+
+
+
+
+ OEM1KEY [0:31]
+ OEM1 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM1KEY [63:32]
+ OEM1 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [0:31]
+ OEM2 least significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ OEM2KEY [63:32]
+ OEM2 most significant bytes key
+ 0x0
+ 0x20
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x483.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x483.xml
new file mode 100644
index 0000000..607c8ff
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x483.xml
@@ -0,0 +1,459 @@
+
+
+
+ 0x483
+ STMicroelectronics
+ MCU
+ Cortex-M7
+ STM32H72x/STM32H73x
+ STM32H7
+ ARM 32-bit Cortex-M7 based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x20
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x8
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x2
+ 0x2
+ RW
+
+ reset level is set to 0.0 V
+ reset level is set to 2.1 V
+ reset level is set to 2.4 V
+ reset level is set to 2.7 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ IWDG1_SW
+
+ 0x4
+ 0x1
+ RW
+
+ Independent watchdog is controlled by hardware
+ Independent watchdog is controlled by software
+
+ 0x1
+
+
+ NRST_STOP_D1
+
+ 0x6
+ 0x1
+ RW
+
+ STOP mode on Domain 1 is entering with reset
+ STOP mode on Domain 1 is entering without reset
+
+ 0x1
+
+
+ NRST_STBY_D1
+
+ 0x7
+ 0x1
+ RW
+
+ STANDBY mode on Domain 1 is entering with reset
+ STANDBY mode on Domain 1 is entering without reset
+
+ 0x1
+
+
+ IO_HSLV
+
+ 0x1D
+ 0x1
+ RW
+
+ Product working in the full voltage range, I/O speed optimization at low-voltage disabled
+ Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed
+
+ 0x0
+
+
+ IWDG_FZ_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Independent watchdog is freezed in STOP mode
+ Independent watchdog is running in STOP mode
+
+ 0x1
+
+
+
+ IWDG_FZ_SDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Independent watchdog is freezed in STANDBY mode
+ Independent watchdog is running in STANDBY mode
+
+ 0x1
+
+
+ ST_RAM_SIZE
+
+ 0x13
+ 0x2
+ RW
+
+ 2 KB reserved to ST code
+ 4 KB reserved to ST code
+ 8 KB reserved to ST code
+ 16 KB reserved to ST code
+
+ 0x3
+
+
+ SECURITY
+
+ 0x15
+ 0x1
+ RW
+
+ Security feature disabled
+ Security feature enabled
+
+ 0x0
+
+
+
+
+
+
+
+ TCM_AXI_SHARED
+ This bitfield configures the ITCM memory size and the AXI system RAM
+ 0x0
+ 0x2
+ RW
+
+ 64-Kbyte ITCM / 320 Kbyte system AXI
+ 128-Kbyte ITCM / 256-Kbyte system AXI
+ 192-Kbyte ITCM / 192-Kbyte system AXI
+ 256-Kbyte ITCM / 128-Kbyte system AXI
+
+ 0x0
+
+
+ CPUFREQ_BOOST
+ This bit configures whether the CPU frequency can be boosted or not. When it is set, the ECC on ITCM and DTCM are no more used
+ 0x2
+ 0x1
+ RW
+
+
+
+
+
+ 0x0
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PROT_AREA_START
+ Flash Bank PCROP start address
+ 0x0
+ 0xC
+ RW
+
+ 0x0FF
+
+
+ PROT_AREA_END
+ Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMEP
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x0
+
+
+
+
+
+ Secure Protection
+
+
+
+
+ SEC_AREA_START
+ Flash secure area start address
+ 0x0
+ 0xC
+ RW
+
+ 0xFF
+
+
+ SEC_AREA_END
+ Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory.
+ 0x10
+ 0xC
+ RW
+
+ 0x0
+
+
+ DMES
+
+ 0x1F
+ 0x1
+ RW
+
+ Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs
+ Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs
+
+ 0x1
+
+
+
+
+
+ Write Protection
+
+
+
+
+ nWRP0
+
+ 0x0
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP1
+
+ 0x1
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP2
+
+ 0x2
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP3
+
+ 0x3
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP4
+
+ 0x4
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP5
+
+ 0x5
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP6
+
+ 0x6
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+ nWRP7
+
+ 0x7
+ 0x1
+ RW
+
+ Write protection active
+ Write protection not active
+
+ 0x1
+
+
+
+
+
+ TCM_AXI Shared Configuration
+
+
+
+
+ BOOT_CM_ADD0
+
+ 0x0
+ 0x10
+ RW
+
+ 0x0800
+
+
+ BOOT_CM_ADD1
+
+ 0x10
+ 0x10
+ RW
+
+ 0x1FF0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x495.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x495.xml
new file mode 100644
index 0000000..665d7c0
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x495.xml
@@ -0,0 +1,573 @@
+
+
+
+ 0x495
+ STMicroelectronics
+ MCU
+ Cortex-M0+/M4
+ STM32WB5x/35xx
+ STM32WB
+ ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0xFF
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x3
+ RW
+
+ BOR Level 0 reset level threshold is around 1.7 V
+ BOR Level 1 reset level threshold is around 2.0 V
+ BOR Level 2 reset level threshold is around 2.2 V
+ BOR Level 3 reset level threshold is around 2.5 V
+ BOR Level 4 reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nBOOT0
+
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0=0 Boot selected based on nBOOT1
+ nBOOT0=1 Boot from main Flash
+
+ 0x1
+
+
+ nBOOT1
+
+ 0x17
+ 0x1
+ RW
+
+ Boot from code area if BOOT0=0 otherwise embedded SRAM
+ Boot from code area if BOOT0=0 otherwise system Flash
+
+ 0x1
+
+
+ nSWBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ SRAM2_RST
+
+ 0x19
+ 0x1
+ RW
+
+ SRAM2 erased when a system reset occurs
+ SRAM2 is not erased when a system reset occurs
+
+ 0x0
+
+
+ SRAM2_PE
+
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 parity check enable
+ SRAM2 parity check disable
+
+ 0x1
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering the Stop mode
+ No reset generated when entering the Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering the Standby mode
+ No reset generated when entering the Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ IWDG_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Independent watchdog counter frozen in Standby mode
+ Independent watchdog counter running in Standby mode
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Independent watchdog counter frozen in Stop mode
+ Independent watchdog counter running in Stop mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+
+
+
+
+
+ IPCCDBA
+ IPCC mailbox data buffer base address
+ 0x0
+ 0xE
+ RW
+ 0x0
+
+
+
+
+
+ Security Configuration Option bytes - 1
+
+
+
+
+ ESE
+
+ 0x8
+ 0x1
+ R
+
+ Security disabled
+ Security enabled
+
+ 0x1
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ Flash Area 1 PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1A_END
+ Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x1
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ Flash Area 2 PCROP start address
+ 0x0
+ 0x9
+ RW
+
+ 0x1FF
+
+
+
+
+
+
+
+ PCROP1B_END
+ Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.
+ 0x0
+ 0x9
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ WRP1A_STRT
+ The address of the first page of the Bank 1 WRP first area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1A_END
+ The address of the last page of the Bank 1 WRP first area
+ 0x10
+ 0x8
+ RW
+
+ 0x00
+
+
+
+
+
+
+
+ WRP1B_STRT
+ The address of the first page of the Bank 1 WRP second area
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+ WRP1B_END
+ The address of the last page of the Bank 1 WRP second area
+ 0x10
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+ Security Configuration Option bytes - 2
+
+
+
+
+ SFSA
+ Secure Flash start address
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ FSD
+
+ 0x8
+ 0x1
+ RW
+
+ System and Flash secure
+ System and Flash non-secure
+
+ 0x0
+
+
+ DDS
+
+ 0xC
+ 0x1
+ RW
+
+ CPU2 debug access enabled
+ CPU2 debug access disabled
+
+ 0x1
+
+
+
+
+
+
+
+ C2OPT
+
+ 0x1F
+ 0x1
+ RW
+
+ SBRV will address SRAM2
+ SBRV will address Flash
+
+ 0x0
+
+
+ NBRSD
+ If FSD=1 : SRAM2b is non-secure. If FSD=0 :
+ 0x1E
+ 0x1
+ RW
+
+ SRAM2b is secure
+ SRAM2b is non-secure
+
+ 0x0
+
+
+ SNBRSA
+ SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.
+ 0x19
+ 0x5
+ RW
+
+ 0x0
+
+
+ BRSD
+ If FSD=1 : SRAM2a is non-secure. If FSD=0 :
+ 0x17
+ 0x1
+ RW
+
+ SRAM2a is secure
+ SRAM2a is non-secure
+
+ 0x0
+
+
+ SBRSA
+ SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.
+ 0x12
+ 0x5
+ RW
+
+ 0x0
+
+
+ SBRV
+ Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.
+ 0x0
+ 0x12
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x497.xml b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x497.xml
new file mode 100644
index 0000000..c1e116f
--- /dev/null
+++ b/Programmer/FastROM_Data_Base/STM32_Prog_DB_0x497.xml
@@ -0,0 +1,621 @@
+
+
+
+ 0x497
+ STMicroelectronics
+ MCU
+ Cortex-M0+/M4
+ STM32WLxx
+ STM32WL
+ ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device
+
+
+
+
+
+
+
+
+
+ Embedded SRAM
+ Storage
+
+ 0x00
+ RWE
+
+
+
+
+ Single
+
+
+
+
+
+
+
+
+
+ Embedded Flash
+ Storage
+ The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms
+ 0xFF
+ RWE
+
+
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ OTP
+ Storage
+ The Data OTP memory block. It contains the one time programmable bits.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x8
+
+
+
+
+
+
+
+
+
+ MirrorOptionBytes
+ Storage
+ Mirror Option Bytes contains the extra area.
+ 0xFF
+ RW
+
+
+
+
+ Single
+ 0x4
+
+
+
+
+
+
+
+
+
+ Option Bytes
+ Configuration
+
+ RW
+
+
+
+ Read Out Protection
+
+
+
+
+ RDP
+ Read protection option byte. The read protection is used to protect the software code stored in Flash memory.
+ 0x0
+ 0x8
+ RW
+
+ Level 0, no protection
+ or any value other than 0xAA and 0xCC: Level 1, read protection
+ Level 2, chip protection
+
+ 0xAA
+
+
+
+
+
+ BOR Level
+
+
+
+
+ BOR_LEV
+ These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory
+ 0x9
+ 0x3
+ RW
+
+ BOR Level 0 reset level threshold is around 1.7 V
+ BOR Level 1 reset level threshold is around 2.0 V
+ BOR Level 2 reset level threshold is around 2.2 V
+ BOR Level 3 reset level threshold is around 2.5 V
+ BOR Level 4 reset level threshold is around 2.8 V
+
+ 0x0
+
+
+
+
+
+ User Configuration
+
+
+
+
+ nBOOT0
+
+ 0x1B
+ 0x1
+ RW
+
+ nBOOT0=0
+ nBOOT0=1
+
+ 0x1
+
+
+ nBOOT1
+ Together with the BOOT0 pin or option bit nBOOT0, this bit selects boot mode from the user Flash memory, SRAM1 or system Flash memory . Refer to Reference Manual: Boot configuration Section.
+ 0x17
+ 0x1
+ RW
+
+
+
+
+ 0x1
+
+
+ nSWBOOT0
+
+ 0x1A
+ 0x1
+ RW
+
+ BOOT0 taken from the option bit nBOOT0
+ BOOT0 taken from PH3/BOOT0 pin
+
+ 0x1
+
+
+ SRAM_RST
+
+ 0x19
+ 0x1
+ RW
+
+ SRAM1 and SRAM2 are erased when a system reset occurs
+ SRAM1 and SRAM2 are not erased when a system reset occurs
+
+ 0x1
+
+
+ SRAM2_PE
+
+ 0x18
+ 0x1
+ RW
+
+ SRAM2 parity check enable
+ SRAM2 parity check disable
+
+ 0x1
+
+
+ nRST_STOP
+
+ 0xC
+ 0x1
+ RW
+
+ Reset generated when entering the Stop mode
+ No reset generated when entering the Stop mode
+
+ 0x1
+
+
+ nRST_STDBY
+
+ 0xD
+ 0x1
+ RW
+
+ Reset generated when entering the Standby mode
+ No reset generated when entering the Standby mode
+
+ 0x1
+
+
+ nRST_SHDW
+
+ 0xE
+ 0x1
+ RW
+
+ Reset generated when entering the Shutdown mode
+ No reset generated when entering the Shutdown mode
+
+ 0x1
+
+
+ WWDG_SW
+
+ 0x13
+ 0x1
+ RW
+
+ Hardware window watchdog
+ Software window watchdog
+
+ 0x1
+
+
+ IWGD_STDBY
+
+ 0x12
+ 0x1
+ RW
+
+ Independent watchdog counter frozen in Standby mode
+ Independent watchdog counter running in Standby mode
+
+ 0x1
+
+
+ IWDG_STOP
+
+ 0x11
+ 0x1
+ RW
+
+ Independent watchdog counter frozen in Stop mode
+ Independent watchdog counter running in Stop mode
+
+ 0x1
+
+
+ IWDG_SW
+
+ 0x10
+ 0x1
+ RW
+
+ Hardware independent watchdog
+ Software independent watchdog
+
+ 0x1
+
+
+ BOOT_LOCK
+
+ 0x1E
+ 0x1
+ RW
+
+ CPU1 CM4 Boot lock disabled
+ CPU1 CM4 Boot lock enabled
+
+ 0x0
+
+
+ C2BOOT_LOCK
+
+ 0x1F
+ 0x1
+ RW
+
+ CPU2 CM0+ Boot lock disabled
+ CPU2 CM0+ Boot lock enabled
+
+ 0x0
+
+
+
+
+
+ Security Configuration Option bytes ESE
+
+
+
+
+ ESE
+
+ 0x8
+ 0x1
+ RW
+
+ Security disabled
+ Security enabled
+
+ 0x0
+
+
+
+
+
+ PCROP Protection
+
+
+
+
+ PCROP1A_STRT
+ PCROP1A_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone A
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1A_END
+ PCROP1A_END[7:0] contain the last included 1kB page readout protected of the Flash area zone A
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+ PCROP_RDP
+
+ 0x1F
+ 0x1
+ RW
+
+ PCROP zone is kept when RDP is decreased
+ PCROP zone is erased when RDP is decreased
+
+ 0x1
+
+
+
+
+
+
+
+
+ WRP1A_STRT
+ WRP1A_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone A.
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1A_END
+ WRP1A_END[6:0] contain the last included 2kB page write protected of the Flash area zone A.
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ WRP1B_STRT
+ WRP1B_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone B.
+ 0x0
+ 0x7
+ RW
+
+ 0x7F
+
+
+ WRP1B_END
+ WRP1B_END[6:0] contain the last included 2kB page write protected of the Flash area zone B.
+ 0x10
+ 0x7
+ RW
+
+ 0x0
+
+
+
+
+
+
+
+ PCROP1B_STRT
+ PCROP1B_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone B
+ 0x0
+ 0x8
+ RW
+
+ 0xFF
+
+
+
+
+
+
+
+ PCROP1B_END
+ PCROP1B_END[7:0] contain the last included 1kB page readout protected of the Flash area zone B
+ 0x0
+ 0x8
+ RW
+
+ 0x0
+
+
+
+
+
+ Write Protection
+
+
+
+
+ IPCCDBA
+ IPCC mailbox data buffer base address
+ 0x0
+ 0xE
+ RW
+ 0x3FFF
+
+
+
+
+
+
+
+ SFSA
+ This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area.
+ 0x0
+ 0x7
+ RW
+ 0x7F
+
+
+ FSD
+
+ 0x7
+ 0x1
+ RW
+
+ System and Flash secure. This bit can only be accessed when HDPADIS = 0
+ System and Flash non-secure. This bit can only be accessed when HDPADIS = 0
+
+ 0x1
+
+
+ DDS
+
+ 0xC
+ 0x1
+ RW
+
+ CPU2 debug access enabled (when also enabled by C2SWDBGEN)
+ CPU2 debug access disabled (when also enabled by C2SWDBGEN)
+
+ 0x0
+
+
+ HDPSA
+ HDPSA[6:0] contain the start address of the first 2 kB page of the User Flash hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash hide protection area enabled.
+ 0x10
+ 0x7
+ RW
+ 0x7F
+
+
+ HDPAD
+ User Flash hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0
+ 0x17
+ 0x1
+ RW
+
+ User Flash hide protection area access enabled.
+ User Flash hide protection area access disabled.
+
+ 0x1
+
+
+
+ SUBGHSPISD
+ SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled
+ 0x1F
+ 0x1
+ RW
+
+ FSD=0 and SUBGHSPISD=0: SPI3 security enabled
+ FSD=0 and SUBGHSPISD=1: SPI3 security disabled
+
+ 0x1
+
+
+
+
+
+
+
+
+ C2OPT
+
+ 0x1F
+ 0x1
+ RW
+
+ SBRV will address SRAM1 or SRAM2, from start address 0x2000 0000 + SBRV.
+ SBRV will address Flash memory, from start address 0x0800 0000 + SBRV.
+
+ 0x1
+
+
+ NBRSD
+
+ 0x1E
+ 0x1
+ RW
+
+ SRAM1 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0
+ SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0
+
+ 0x1
+
+
+ SNBRSA
+ SNBRSA[4:0] contain the start address of the first 1 kB page of the secure "non-backup" SRAM1 area. To keep the tool working you have to set a value greater or equal to 0xC
+ 0x19
+ 0x5
+ RW
+ 0x1F
+
+
+ BRSD
+
+ 0x17
+ 0x1
+ RW
+
+ SRAM2 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0
+ SRAM2 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0
+
+ 0x1
+
+
+ SBRSA
+ SBRSA[4:0] contain the start address of the first 1 kB page of the secure backup SRAM2 area. To keep the tool working you have to set a value less than 0x15
+ 0x12
+ 0x5
+ RW
+ 0x1F
+
+
+ SBRV
+ SBRV[15:0] contain the word (4B) aligned CPU2 boot reset start address offset within the selected memory area by C2OPT.
+ 0x0
+ 0x10
+ RW
+ 0x8000
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/README.md b/README.md
index dec3e83..7ae8057 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,21 @@
[](https://github.com/K-Society)
+
[](https://github.com/K-Society/KSociety.SharpCubeProgrammer/actions/workflows/build.yml?query=branch%3Adevelop)
[](https://www.nuget.org/packages/KSociety.SharpCubeProgrammer)
[](https://www.nuget.org/stats/packages/KSociety.SharpCubeProgrammer?groupby=Version)
+
+
[KSociety.SharpCubeProgrammer Home](https://github.com/K-Society/KSociety.SharpCubeProgrammer)
# KSociety.SharpCubeProgrammer
KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.15.0.
+
+First unofficial and open source C# wrapper.
+
+
It makes use of several 3rd party tools:
- STM32 Cube Programmer
@@ -30,6 +37,7 @@ STM32CubeProgrammer_API C# wrapper, the first wrapper for C#. Any suggestions ar
## Get Packages
You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](https://www.nuget.org/packages/KSociety.SharpCubeProgrammer/).
+You need to use _PackageReference_, otherwise some contents will not be copied to the output folder and consequently it will not work.
## Currently supported features
@@ -40,8 +48,15 @@ You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](
- Reset
## Bootloader functions
+- GetUsartList
+- ConnectUsartBootloader
+- SendByteUart
- GetDfuDeviceList
- ConnectDfuBootloader
+- ConnectDfuBootloader2
+- ConnectSpiBootloader
+- ConnectCanBootloader
+- ConnectI2CBootloader
## General purposes functions
- SetDisplayCallbacks
@@ -120,7 +135,7 @@ You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](
## Get Started
-Examples include the QuickStart project, is a very basic example.
+Examples include the [QuickStart](https://github.com/K-Society/KSociety.SharpCubeProgrammer/tree/master/src/01/Samples/QuickStart) project, is a very basic example.
- Creates a new instance of the CharpCubeProgrammer class:
@@ -245,5 +260,5 @@ The project is under Microsoft Reciprocal License [(MS-RL)](http://www.opensourc
List of technologies, frameworks and libraries used for implementation:
-- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces)
+- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces) for .NET Standard 2.0 only.
- [Microsoft.Extensions.Logging.Abstractions](https://www.nuget.org/packages/Microsoft.Extensions.Logging.Abstractions)
\ No newline at end of file
diff --git a/docs/KSociety.SharpCubeProgrammer/README.md b/docs/KSociety.SharpCubeProgrammer/README.md
index e806e2e..91f6d28 100644
--- a/docs/KSociety.SharpCubeProgrammer/README.md
+++ b/docs/KSociety.SharpCubeProgrammer/README.md
@@ -8,6 +8,10 @@
KSociety.SharpCubeProgrammer is a wrapper for CubeProgrammer_API v2.15.0.
+
+First unofficial and open source C# wrapper.
+
+
It makes use of several 3rd party tools:
- STM32 Cube Programmer
@@ -29,6 +33,7 @@ STM32CubeProgrammer_API C# wrapper, the first wrapper for C#. Any suggestions ar
## Get Packages
You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](https://www.nuget.org/packages/KSociety.SharpCubeProgrammer/).
+You need to use _PackageReference_, otherwise some contents will not be copied to the output folder and consequently it will not work.
## Currently supported features
@@ -39,8 +44,15 @@ You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](
- Reset
## Bootloader functions
+- GetUsartList
+- ConnectUsartBootloader
+- SendByteUart
- GetDfuDeviceList
- ConnectDfuBootloader
+- ConnectDfuBootloader2
+- ConnectSpiBootloader
+- ConnectCanBootloader
+- ConnectI2CBootloader
## General purposes functions
- SetDisplayCallbacks
@@ -118,7 +130,7 @@ You can get KSociety.SharpCubeProgrammer by [grabbing the latest NuGet package](
| MSVC v143 - VS 2022 C++ x64/x86 |
## Get Started
-Examples include the QuickStart project, is a very basic example.
+Examples include the [QuickStart](https://github.com/K-Society/KSociety.SharpCubeProgrammer/tree/master/src/01/Samples/QuickStart) project, is a very basic example.
- Creates a new instance of the CharpCubeProgrammer class:
@@ -243,5 +255,5 @@ The project is under Microsoft Reciprocal License [(MS-RL)](http://www.opensourc
List of technologies, frameworks and libraries used for implementation:
-- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces)
+- [Microsoft.Bcl.AsyncInterfaces](https://www.nuget.org/packages/Microsoft.Bcl.AsyncInterfaces) for .NET Standard 2.0 only.
- [Microsoft.Extensions.Logging.Abstractions](https://www.nuget.org/packages/Microsoft.Extensions.Logging.Abstractions)
\ No newline at end of file
diff --git a/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs b/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs
index a41bf3e..ab89664 100644
--- a/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs
+++ b/src/01/KSociety.SharpCubeProgrammer/CubeProgrammerApi.cs
@@ -187,21 +187,69 @@ public CubeProgrammerError Reset(DebugResetMode rstMode)
//Bootloader module is a way to group Serial interfaces USB/UART/SPI/I2C/CAN function together.
///
- public void GetUsartList()
+ public IEnumerable GetUsartList()
{
- throw new NotImplementedException();
+ var listPtr = new IntPtr();
+ var parametersList = new List();
+ try
+ {
+ var size = Marshal.SizeOf();
+ var numberOfItems = Native.ProgrammerApi.GetUsartList(ref listPtr);
+ if (listPtr != IntPtr.Zero)
+ {
+ for (var i = 0; i < numberOfItems; i++)
+ {
+ var currentItem = Marshal.PtrToStructure(listPtr + (i * size));
+ parametersList.Add(currentItem);
+ Marshal.DestroyStructure(listPtr + (i * size));
+ }
+ }
+ else
+ {
+ this._logger?.LogWarning("GetUsartList IntPtr: {0}!", "Zero");
+ }
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "GetUsartList: ");
+ }
+ return parametersList;
}
///
- public void ConnectUsartBootloader()
+ public CubeProgrammerError ConnectUsartBootloader(UsartConnectParameters usartConnectParameters)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+
+ try
+ {
+ var connectUsartResult = Native.ProgrammerApi.ConnectUsartBootloader(usartConnectParameters);
+
+ output = this.CheckResult(connectUsartResult);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "ConnectUsartBootloader: ");
+ }
+
+ return output;
}
///
- public void SendByteUart()
+ public CubeProgrammerError SendByteUart(int bytes)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+ try
+ {
+ var connectUsartResult = Native.ProgrammerApi.SendByteUart(bytes);
+
+ output = this.CheckResult(connectUsartResult);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "SendByteUart: ");
+ }
+ return output;
}
///
@@ -259,27 +307,87 @@ public CubeProgrammerError ConnectDfuBootloader(string usbIndex)
}
///
- public void ConnectDfuBootloader2()
+ public CubeProgrammerError ConnectDfuBootloader2(DfuConnectParameters dfuParameters)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+ try
+ {
+ var connectDfuBootloader2Result = Native.ProgrammerApi.ConnectDfuBootloader2(dfuParameters);
+ if (connectDfuBootloader2Result != 0)
+ {
+ this.Disconnect();
+ }
+
+ output = this.CheckResult(connectDfuBootloader2Result);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "ConnectDfuBootloader2: ");
+ }
+ return output;
}
///
- public void ConnectSpiBootloader()
+ public CubeProgrammerError ConnectSpiBootloader(SpiConnectParameters spiParameters)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+ try
+ {
+ var connectSpiBootloaderResult = Native.ProgrammerApi.ConnectSpiBootloader(spiParameters);
+ if (connectSpiBootloaderResult != 0)
+ {
+ this.Disconnect();
+ }
+
+ output = this.CheckResult(connectSpiBootloaderResult);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "ConnectSpiBootloader: ");
+ }
+ return output;
}
///
- public void ConnectCanBootloader()
+ public CubeProgrammerError ConnectCanBootloader(CanConnectParameters canParameters)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+ try
+ {
+ var connectCanBootloaderResult = Native.ProgrammerApi.ConnectCanBootloader(canParameters);
+ if (connectCanBootloaderResult != 0)
+ {
+ this.Disconnect();
+ }
+
+ output = this.CheckResult(connectCanBootloaderResult);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "ConnectCanBootloader: ");
+ }
+ return output;
}
///
- public void ConnectI2cBootloader()
+ public CubeProgrammerError ConnectI2CBootloader(I2CConnectParameters i2CParameters)
{
- throw new NotImplementedException();
+ var output = CubeProgrammerError.CubeprogrammerErrorOther;
+ try
+ {
+ var connectI2CBootloaderResult = Native.ProgrammerApi.ConnectI2cBootloader(i2CParameters);
+ if (connectI2CBootloaderResult != 0)
+ {
+ this.Disconnect();
+ }
+
+ output = this.CheckResult(connectI2CBootloaderResult);
+ }
+ catch (Exception ex)
+ {
+ this._logger?.LogError(ex, "ConnectI2CBootloader: ");
+ }
+ return output;
}
#endregion
@@ -1414,13 +1522,25 @@ protected override void Dispose(bool disposing)
{
if (disposing)
{
- this._handle?.Dispose();
- this._handle = null;
+ // Free any other managed objects here.
}
+ // Free any unmanaged objects here.
+ this._handle?.Dispose();
+ this._handle = null;
+
base.Dispose(disposing);
}
#endregion
+
+ #region [Destructor]
+
+ ~CubeProgrammerApi()
+ {
+ this.Dispose(false);
+ }
+
+ #endregion
} // CubeProgrammerApi.
}
diff --git a/src/01/KSociety.SharpCubeProgrammer/Interface/ICubeProgrammerApi.cs b/src/01/KSociety.SharpCubeProgrammer/Interface/ICubeProgrammerApi.cs
index 3dc291e..769a9f3 100644
--- a/src/01/KSociety.SharpCubeProgrammer/Interface/ICubeProgrammerApi.cs
+++ b/src/01/KSociety.SharpCubeProgrammer/Interface/ICubeProgrammerApi.cs
@@ -51,17 +51,17 @@ public interface ICubeProgrammerApi : IDisposable, IAsyncDisposable
///
/// This routine allows to get connected serial ports.
///
- void GetUsartList();
+ IEnumerable GetUsartList();
///
/// This routine allows to start connection to device through USART interface.
///
- void ConnectUsartBootloader();
+ CubeProgrammerError ConnectUsartBootloader(UsartConnectParameters usartConnectParameters);
///
/// This routine allows to send a single byte through the USART interface.
///
- void SendByteUart();
+ CubeProgrammerError SendByteUart(int bytes);
///
/// This routine allows to get connected DFU devices.
@@ -76,22 +76,22 @@ public interface ICubeProgrammerApi : IDisposable, IAsyncDisposable
///
/// This routine allows to start connection to device through USB DFU interface.
///
- void ConnectDfuBootloader2();
+ CubeProgrammerError ConnectDfuBootloader2(DfuConnectParameters dfuParameters);
///
/// This routine allows to start connection to device through SPI interface.
///
- void ConnectSpiBootloader();
+ CubeProgrammerError ConnectSpiBootloader(SpiConnectParameters spiParameters);
///
/// This routine allows to start connection to device through CAN interface.
///
- void ConnectCanBootloader();
+ CubeProgrammerError ConnectCanBootloader(CanConnectParameters canParameters);
///
/// This routine allows to start connection to device through I2C interface.
///
- void ConnectI2cBootloader();
+ CubeProgrammerError ConnectI2CBootloader(I2CConnectParameters i2CParameters);
#endregion
diff --git a/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj b/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj
index cfb9d79..9dadaf9 100644
--- a/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj
+++ b/src/01/KSociety.SharpCubeProgrammer/KSociety.SharpCubeProgrammer.csproj
@@ -53,6 +53,9 @@
true
+
+ true
+
diff --git a/src/01/KSociety.Test/KSociety.Test.csproj b/src/01/KSociety.Test/KSociety.Test.csproj
index 7508892..7cdb0fb 100644
--- a/src/01/KSociety.Test/KSociety.Test.csproj
+++ b/src/01/KSociety.Test/KSociety.Test.csproj
@@ -9,16 +9,16 @@
-
+
-
-
+
+
runtime; build; native; contentfiles; analyzers; buildtransitive
all
-
+
runtime; build; native; contentfiles; analyzers; buildtransitive
all