From 554ba525182b41876cd8d9b73704eef176332f48 Mon Sep 17 00:00:00 2001 From: rgantonio Date: Mon, 30 Sep 2024 15:08:09 +0200 Subject: [PATCH] hw: add pipe regs for cluster_base_addr_i --- hw/snitch/src/snitch.sv | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/snitch/src/snitch.sv b/hw/snitch/src/snitch.sv index a04ed6d61..ca73a09c0 100644 --- a/hw/snitch/src/snitch.sv +++ b/hw/snitch/src/snitch.sv @@ -358,6 +358,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( assign core_events_o = '0; `endif + // Pipe-lining some input signals + addr_t cluster_base_addr_reg; + `FFAR(cluster_base_addr_reg, cluster_base_addr_i, '0, clk_i, rst_i) + logic [AddrWidth-32-1:0] mseg_q, mseg_d; `FFAR(mseg_q, mseg_d, cluster_base_addr_i[AddrWidth - 1 : 32], clk_i, rst_i) @@ -423,7 +427,7 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( // If trans_active is high (under VM mode), the virtual memory is replaced by translated hardware address; otherwise, the address is prepended by the chiplet base address. assign inst_addr_o[PPNSize+PageShift-1:PageShift] = ({(PPNSize){trans_active}} & itlb_pa) - | (~{(PPNSize){trans_active}} & {cluster_base_addr_i[AddrWidth-1:32], pc_q[31:PageShift]}); + | (~{(PPNSize){trans_active}} & {cluster_base_addr_reg[AddrWidth-1:32], pc_q[31:PageShift]}); assign inst_addr_o[PageShift-1:0] = pc_q[PageShift-1:0]; assign inst_cacheable_o = snitch_pma_pkg::is_inside_cacheable_regions(SnitchPMACfg, inst_addr_o); assign inst_valid_o = ~wfi_q && ~csr_stall_q; @@ -2463,10 +2467,10 @@ module snitch import snitch_pkg::*; import riscv_instr::*; #( if (!exception) mseg_d = alu_result[$bits(mseg_q)-1:0]; end CsrBaseAddrL: begin - csr_rvalue = cluster_base_addr_i[31:0]; + csr_rvalue = cluster_base_addr_reg[31:0]; end CsrBaseAddrH: begin - csr_rvalue = {{(64 - AddrWidth){1'b0}}, cluster_base_addr_i[AddrWidth - 1:32]}; + csr_rvalue = {{(64 - AddrWidth){1'b0}}, cluster_base_addr_reg[AddrWidth - 1:32]}; end CsrClusterCoreId: begin csr_rvalue = cluster_core_id_i;