diff --git a/README.md b/README.md
index 447c784..bbf0840 100644
--- a/README.md
+++ b/README.md
@@ -31,14 +31,14 @@ The processor has 64 general registers of 64 bits, and 64 registers of 128 bits
The processor only has SIMD instructions for the FPU.
-It has 160 instructions distributed like this:
-ALU : 42
-LSU : 32
+It has 151 instructions distributed like this:
+ALU : 36
+LSU : 28
CMP : 8
Other : 2
BRU : 20
VFPU : 32
-EFU : 9
+EFU : 12
FPU-D : 8
DMA : 5
@@ -84,5 +84,8 @@ GPU todo list : https://docs.google.com/spreadsheets/d/1eRX1vLHEJdrAsx2u1OiycSSz
## Pipeline
+## Architecture
+
+
## APU Die (420 MT) 30 mm² , 28 nm FD-SOI
diff --git a/VM/altairx/VM_AltairX.depend b/VM/altairx/VM_AltairX.depend
index 3994c8e..c3fd8ec 100644
--- a/VM/altairx/VM_AltairX.depend
+++ b/VM/altairx/VM_AltairX.depend
@@ -165,7 +165,7 @@
"src/vm.h"
-1645468691 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/main.c
+1646662284 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/main.c
@@ -173,7 +173,7 @@
"src/vm.h"
-1645725743 /home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/vm.h
+1646329498 /home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/vm.h
1645696326 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/debug.c
@@ -184,7 +184,7 @@
"vm.h"
-1645710334 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/decode.c
+1645731672 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/decode.c
@@ -193,7 +193,7 @@
"vm.h"
-1645711112 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/execute.c
+1645773388 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/execute.c
@@ -202,7 +202,7 @@
"vm.h"
-1645695346 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/syscall.c
+1645739893 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/syscall.c
@@ -210,7 +210,7 @@
"vm.h"
-1645711544 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/vm.c
+1646329498 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/vm.c
@@ -218,7 +218,7 @@
"vm.h"
-1645727202 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/cycle.c
+1646662301 source:/home/Kannagi/Documents/Projet/AltairX/Git_AX/VM/altairx/src/cycle.c
diff --git a/VM/altairx/bin/vasmAltairK1_mot b/VM/altairx/bin/vasmAltairK1_mot
index e205419..6c388d2 100755
Binary files a/VM/altairx/bin/vasmAltairK1_mot and b/VM/altairx/bin/vasmAltairK1_mot differ
diff --git a/VM/altairx/bin/vm_altairx b/VM/altairx/bin/vm_altairx
index fdb1740..e006914 100755
Binary files a/VM/altairx/bin/vm_altairx and b/VM/altairx/bin/vm_altairx differ
diff --git a/VM/altairx/bin/vm_altairx.exe b/VM/altairx/bin/vm_altairx.exe
index 281ea73..aef6c0e 100755
Binary files a/VM/altairx/bin/vm_altairx.exe and b/VM/altairx/bin/vm_altairx.exe differ
diff --git a/VM/altairx/main.c b/VM/altairx/main.c
index 186e1c9..9e22885 100644
--- a/VM/altairx/main.c
+++ b/VM/altairx/main.c
@@ -6,8 +6,6 @@
#include "src/vm.h"
-
-
int main(int argc, char** argv)
{
int i,arg = 0;
diff --git a/VM/altairx/obj/main.o b/VM/altairx/obj/main.o
index 33c7f5e..386d6b6 100644
Binary files a/VM/altairx/obj/main.o and b/VM/altairx/obj/main.o differ
diff --git a/VM/altairx/obj/src/cycle.o b/VM/altairx/obj/src/cycle.o
index 1d356ab..3ae1788 100644
Binary files a/VM/altairx/obj/src/cycle.o and b/VM/altairx/obj/src/cycle.o differ
diff --git a/VM/altairx/obj/src/debug.o b/VM/altairx/obj/src/debug.o
index 93603bc..bf70c5f 100644
Binary files a/VM/altairx/obj/src/debug.o and b/VM/altairx/obj/src/debug.o differ
diff --git a/VM/altairx/obj/src/decode.o b/VM/altairx/obj/src/decode.o
index 67a9bf9..19b31f6 100644
Binary files a/VM/altairx/obj/src/decode.o and b/VM/altairx/obj/src/decode.o differ
diff --git a/VM/altairx/obj/src/execute.o b/VM/altairx/obj/src/execute.o
index c8659d7..b4a3a09 100644
Binary files a/VM/altairx/obj/src/execute.o and b/VM/altairx/obj/src/execute.o differ
diff --git a/VM/altairx/obj/src/syscall.o b/VM/altairx/obj/src/syscall.o
index 1dfc2e3..ad5831f 100644
Binary files a/VM/altairx/obj/src/syscall.o and b/VM/altairx/obj/src/syscall.o differ
diff --git a/VM/altairx/obj/src/vm.o b/VM/altairx/obj/src/vm.o
index 2efd788..ead5a6b 100644
Binary files a/VM/altairx/obj/src/vm.o and b/VM/altairx/obj/src/vm.o differ
diff --git a/VM/altairx/src/cycle.c b/VM/altairx/src/cycle.c
index 945f59c..b3b7835 100644
--- a/VM/altairx/src/cycle.c
+++ b/VM/altairx/src/cycle.c
@@ -11,60 +11,444 @@
void AX_Cache_miss(Core *core)
{
//I-Cache
- uint32_t index = (core->pc>>7);
+ uint32_t index = (core->pc>>10);
index = (index&0x3F);
if(core->icache[index] != core->pc)
{
core->icache[index] = core->pc;
- core->cycle += 24 + (5*16); //5cycle /64 B
+ core->cycle += 14 + (5*16); //5cycle /64 B
+ core->bandwidth += 1024;
+ core->icachemiss++;
+ core->icachemiss_cycle += 14 + (5*16);
}
- uint32_t unit1 = core->operations[0].unit1;
- uint32_t unit2 = core->operations[0].unit2;
- if(unit1 == AX_EXE_LSU)
+ //D-Cache
+ for(int i = 0;i < core->swt+1;i++)
+ {
+ uint32_t unit1 = core->operations[i].unit1;
+ uint32_t unit2 = core->operations[i].unit2;
+ uint64_t opB = core->operations[i].opB;
+ uint64_t opC = core->operations[i].opC;
+ uint64_t offset;
+
+ if(unit1 == AX_EXE_LSU)
+ {
+ switch(unit2)
+ {
+
+ case AX_OPCODE_LD:
+ case AX_OPCODE_ST:
+ case AX_OPCODE_LDV:
+ case AX_OPCODE_STV:
+ offset = opB + opC;
+ index = (offset>>7);
+ index = (index&0x3FF);
+
+ if(core->dcache[index] != offset)
+ {
+ core->dcache[index] = offset;
+ core->cycle += (14 + 5 )*2; //5cycle /64 B
+
+ core->bandwidth += 128;
+ core->dcachemiss++;
+ core->dcachemiss_cycle += (14 + 5)*2;
+ }
+ break;
+
+ case AX_OPCODE_FLUSH:
+ case AX_OPCODE_PREFETCH:
+ case AX_OPCODE_IFLUSH:
+ case AX_OPCODE_IPREFETCH:
+
+ break;
+ }
+ }
+ else
+ if(unit1 == AX_EXE_DMA)
+ {
+ if(unit2 != AX_OPCODE_WAIT)
+ {
+ core->cycle += (14 + (5*opC) );
+ core->bandwidth += 64*opC;
+ }
+
+ }
+ }
+}
+
+#define AX_ALU_CYCLE 3
+#define AX_FPU_CYCLE 4
+#define AX_FPUD_CYCLE 4
+/*
+void AX_Pipeline_stall(Core *core)
+{
+ for(i = 0;i < AX_core_IREG_COUNT;i++)
+ {
+ if(core->busy_reg[i] > 0)
+ core->busy_reg[i]--;
+ }
+
+ for(i = 0;i < AX_core_VREG_COUNT;i++)
+ {
+ if(core->busy_vreg[i] > 0)
+ core->busy_vreg[i]--;
+ }
+
+
+ for(int i = 0;i < core->swt+1;i++)
+ {
+
+
+
+ }
+
+
+ //Decode
+ switch(compute_unit)
{
- switch(unit2)
- {
- case AX_OPCODE_LD:
+ //ALU-A
+ case 0:
- break;
+ switch(unit1)
+ {
+ case 1:
+ case 2:
+ case 6:
+ case 7:
+ regB = 1;
+ break;
- case AX_OPCODE_ST:
+ case 4:
+ case 5:
+ regB = 1;
+ regC = 1;
+ break;
- break;
- case AX_OPCODE_LDV:
+ }
- break;
+ if(i == 0)
+ {
+ if( (opcode&0x400) && (unit1 > 9) )
+ unit1
+ }
- case AX_OPCODE_STV:
+ core->busy_reg[regA] = AX_ALU_CYCLE;
- break;
- case AX_OPCODE_FLUSH:
+ if(unit == 3) //SMOVE
+ {
+ core->operations[id].opB = ( (imm>>2)&0xFFFF );
+ }
+ else if(unit == 6) //SLTS
+ {
+ core->operations[id].opC = extendSign( (imm>>2)&0x3FF,9);
+ output->unit2 = AX_OPCODE_SLTS;
+ }
+ else if(unit ==7) //SLTU
+ {
+ core->operations[id].opC = ( (imm>>2)&0x3FF );
+ output->unit2 = AX_OPCODE_SLTU;
+ }
+ else if(unit == 8) //MOVEI
+ {
+ core->operations[id].opB = extendSign( imm&0x3FFFF,17 );
+ output->unit2 = AX_OPCODE_MOVE;
+ }
+ else if(unit == 9) //MOVEIU
+ {
+ core->operations[id].opB = imm&0x3FFFF;
+ output->unit2 = AX_OPCODE_MOVE;
+ }
+ else if(unit > 9)
+ {
+ if(id == 0) //MUL/DIV/REM
+ {
+ output->unit2 = unit;
+ if(opcode&0x400)
+ {
+ if(unit == 0)
+ core->operations[id].opC = extendSign( (imm>>3)&0x1FF,8);
+ else
+ core->operations[id].opC = ( (imm>>3)&0x1FF );
+ }
- break;
+ }
+ else
+ {
- case AX_OPCODE_PREFETCH:
+ }
- break;
+ }
- case AX_OPCODE_IFLUSH:
- break;
- case AX_OPCODE_IPREFETCH:
+ break;
- break;
+ //ALU-B
+ case 1:
+ output->unit1 = AX_EXE_ALU;
+ output->unit2 = unit&0x07;
- }
- }
-}
+ if(unit&0x08)
+ {
+ if(unit == 2) //XOR
+ core->operations[id].opC = extendSign( (imm>>2)&0x3FF,9);
+ else
+ core->operations[id].opC = ( (imm>>2)&0x3FF );
+ }
-void AX_Pipeline_stall(Core *core,uint32_t index)
-{
- //core->register_busy
+ break;
-}
+ //LSU-A
+ case 2:
+ output->unit1 = AX_EXE_LSU;
+ output->unit2 = unit&0x03;
+
+ core->operations[id].opC = ( (imm>>2)&0xFFFF );
+
+ tmp = unit>>2;
+ core->operations[id].opB = core->ireg[tmp];
+ break;
+
+ //LSU-B/DMA
+ case 3:
+ output->unit1 = AX_EXE_LSU;
+ output->unit2 = unit&0x03;
+
+ tmp = unit>>2;
+
+ if(tmp == 0)
+ {
+ //----
+ }
+ else if(tmp == 1)
+ {
+ core->operations[id].opC = extendSign( (imm>>2)&0x3FF,9);
+ }
+ else
+ {
+ if(id == 0) //DMA
+ {
+ output->unit1 = AX_EXE_DMA;
+ output->unit2 = unit&1;
+
+ if(unit&0x2)
+ {
+ output->opC = ( (imm>>2)&0xFFFF );
+ }
+ }
+ else //PREFETCH
+ {
+ if(unit == 0xC)
+ {
+ output->unit2 = AX_OPCODE_PREFETCH;
+ core->operations[id].opB = ( (imm>>2)&0xFFFF);
+ }
+ else if(unit == 0xD)
+ {
+ output->unit2 = AX_OPCODE_FLUSH;
+ core->operations[id].opB = ( (imm>>2)&0xFFFF);
+ }
+ else if(unit == 0xE)
+ {
+ output->unit2 = AX_OPCODE_PREFETCH;
+ }
+ else if(unit == 0xF)
+ {
+ output->unit2 = AX_OPCODE_FLUSH;
+ }
+ }
+
+ }
+
+
+ break;
+
+ //CMP/OTHER
+ case 4:
+
+ if(unit&0x8)
+ {
+
+ if(unit == 8)
+ {
+ output->unit1 = AX_EXE_OTHER;
+ output->unit2 = AX_OPCODE_ENDP;
+ }
+ else if(unit == 9)
+ {
+ output->unit1 = AX_EXE_OTHER;
+ output->unit2 = AX_OPCODE_EXE;
+ }
+ else if(unit == 10)
+ {
+ output->unit1 = AX_EXE_DMA;
+ output->unit2 = AX_OPCODE_WAIT;
+ }
+ else if(unit == 12)
+ {
+ output->unit1 = AX_EXE_BRU;
+ core->delayop = output->unit2 = AX_OPCODE_RET;
+ core->delay = 0;
+ }
+ else if(unit == 13)
+ {
+ output->unit1 = AX_EXE_BRU;
+ core->delayop = output->unit2 = AX_OPCODE_RETI;
+ core->delay = 0;
+ }
+ else if(unit == 14)
+ {
+ output->unit1 = AX_EXE_BRU;
+ core->delayop = output->unit2 = AX_OPCODE_SYSCALL;
+ core->delay = 0;
+ }
+ else if(unit == 15)
+ {
+ output->unit1 = AX_EXE_BRU;
+ core->delayop = output->unit2 = AX_OPCODE_INT;
+ core->delay = 0;
+ }
+ else
+ {
+ return 1;
+ }
+ }
+ else
+ {
+ output->unit1 = AX_EXE_CMP;
+ output->unit2 = unit;
+
+ if(unit == 2)
+ {
+ output->opB = extendSign(imm&0x3FFFF,17);
+ output->unit2 = AX_OPCODE_CMP;
+ }
+ else if(unit == 3)
+ {
+ output->opB = (imm&0x3FFFF);
+ output->unit2 = AX_OPCODE_CMP;
+ }
+ else if(unit == 6)
+ {
+ output->id = (output->size+1)&0x3;
+ output->fopB[output->id] = convertImmFloat(imm>>2);
+ output->unit2 = AX_OPCODE_FCMP;
+ }
+ else if(unit == 7)
+ {
+ output->dopB = convertImmDouble(imm>>2);
+ output->unit2 = AX_OPCODE_DCMP;
+ }
+ else
+ {
+
+ }
+ }
+
+
+ break;
+
+
+ //BRU
+ case 5:
+ output->unit1 = AX_EXE_BRU;
+ core->delayop = output->unit2 = unit;
+ core->delay = 0;
+ tmp = readbits(opcode, 8, 24);
+
+ if((unit&0xC) == 0xC)
+ {
+ core->imm = tmp;
+ }
+ else
+ {
+ core->imm = extendSign( (tmp>>2),21);
+ }
+
+ break;
+
+ //VFPU-A - FPU-Double
+ case 6:
+ output->unit1 = AX_EXE_VFPU;
+
+ if(id == 0) //VFPU-A
+ {
+ output->unit2 = unit;
+
+ for(int i = 0;i < 4;i++)
+ {
+ output->fopB[i] = core->vreg[(regB*4)+i];
+ output->fopC[i] = core->vreg[(regC*4)+i];
+ }
+
+ if(unit == 0x0F)
+ {
+ output->opC = (imm>>2)&0x3FF;
+ }
+ }
+ else if(id == 1) //FPU-Double
+ {
+ output->unit2 = unit+0x30;
+
+ output->dopB = core->dreg[(regB*2)];
+ output->dopC = core->dreg[(regC*2)];
+
+ if(unit == 0)
+ {
+ output->dopB = convertImmDouble(imm>>2);
+ }
+ }
+
+ break;
+
+ //VFPU-B - EFU
+ case 7:
+ output->unit1 = AX_EXE_VFPU;
+
+ for(int i = 0;i < 4;i++)
+ {
+ output->fopB[i] = core->vreg[(regB*4)+i];
+ output->fopC[i] = core->vreg[(regC*4)+i];
+ }
+
+ output->dopB = core->dreg[(regB*2)];
+
+
+ if(id == 0) //VFPU-B
+ {
+ output->unit2 = unit+0x10;
+
+ if(unit == 2)
+ {
+ output->id = (output->size+1)&0x3;
+ output->fopB[output->id] = convertImmFloat(imm>>2);
+ output->unit2 = AX_OPCODE_FMOVE+0x10;
+ }
+ else if(unit == 3)
+ {
+ float tmp = convertImmFloat(imm>>2);
+ for(uint32_t i = 0;i < output->size;i++)
+ output->fopB[i] = tmp;
+ output->unit2 = AX_OPCODE_VFMOVE+0x10;
+ }
+ }
+ else if(id == 1) //EFU
+ {
+ output->unit2 = unit+0x20;
+ }
+
+ break;
+
+
+ default :
+ return AX_ERROR_OPCODE;
+ break;
+
+ }
+
+ return 0;
+}*/
diff --git a/VM/altairx/src/decode.c b/VM/altairx/src/decode.c
index 7db2c0c..0ccf54f 100644
--- a/VM/altairx/src/decode.c
+++ b/VM/altairx/src/decode.c
@@ -84,6 +84,7 @@ static double convertImmDouble(uint32_t imm)
static int decode(Core *core,uint32_t id)
{
+
uint32_t tmp;
const uint32_t opcode = core->opcodes[id];
diff --git a/VM/altairx/src/execute.c b/VM/altairx/src/execute.c
index b62f714..99597fa 100644
--- a/VM/altairx/src/execute.c
+++ b/VM/altairx/src/execute.c
@@ -188,11 +188,8 @@ static void executeDelayedInstruction(Core *core, uint32_t imm)
}
core->delay = 0;
-
}
-
-
static void executeLS(Core *core,void *reg,uint64_t offset,uint32_t size,uint32_t store)
{
void *address = NULL;
@@ -217,39 +214,35 @@ static void executeLS(Core *core,void *reg,uint64_t offset,uint32_t size,uint32_
else if(offset&MEMORY_MAP_SPM2_BEGIN)
{
address = core->mmap.spm2;
- max = (core->mmap.nspm2-1); //Max 64 Mio
+ max = (core->mmap.nspm2-1); //Max 256 Mio
}
- else
+ else if(offset&MEMORY_MAP_SPMT_BEGIN)
{
- uint64_t tmp = (offset>>25)&3;
- if(tmp == 0) // SPM L1
- {
- address = core->spm;
- max = 0x7FFF; //Max 32 Kio
- }else
- if(tmp == 1) // ROM
- {
- address = core->mmap.rom;
- max = (core->mmap.nrom-1); //Max 32 Mio
- }else
- if(tmp == 2) // I/O
- {
- address = core->mmap.io;
- max = 0xFFFFF; //Max 1 Mio (max 32 Mio)
- }else
- if(tmp == 3) // SPM Thread
- {
- address = core->mmap.spmt;
- max = (core->mmap.nspmt-1); //Max 32 Mio
- }
-
+ address = core->mmap.spmt;
+ max = (core->mmap.nspmt-1); //Max 128 Mio
+ }
+ else if(offset&MEMORY_MAP_ROM_BEGIN)
+ {
+ address = core->mmap.rom;
+ max = (core->mmap.nrom-1); //Max 64 Mio
+ }
+ else if(offset&MEMORY_MAP_IO_BEGIN)
+ {
+ address = core->mmap.io;
+ max = 0x7FFFFF; //Max 8 Mio (miroir 32 Mio)
+ }
+ else //SPM
+ {
+ address = core->spm;
+ max = 0x7FFF; //Max 32 Kio
}
offset &= max;
+ /*
if( (offset+size) > max)
{
exit(-1);
- }
+ }*/
if(store)
{
diff --git a/VM/altairx/src/syscall.c b/VM/altairx/src/syscall.c
index 3c0ee0d..2d3f134 100644
--- a/VM/altairx/src/syscall.c
+++ b/VM/altairx/src/syscall.c
@@ -38,7 +38,7 @@ int AX_syscall_emul(Core *core)
break;
case 1:
- adr = AX_Memory_Map(core,reg1,1000);
+ adr = AX_Memory_Map(core,reg1);
printf(adr);
break;
@@ -67,8 +67,8 @@ int AX_syscall_emul(Core *core)
break;
case 8: //FOPEN
- adr = AX_Memory_Map(core,reg2,1000);
- adr2 = AX_Memory_Map(core,reg3,1000);
+ adr = AX_Memory_Map(core,reg2);
+ adr2 = AX_Memory_Map(core,reg3);
file = fopen(adr,adr2);
core->ireg[4] = (uint64_t)file;
break;
diff --git a/VM/altairx/src/vm.c b/VM/altairx/src/vm.c
index 55e87bd..eae90ba 100644
--- a/VM/altairx/src/vm.c
+++ b/VM/altairx/src/vm.c
@@ -6,7 +6,7 @@
#include
#include "vm.h"
-void *AX_Memory_Map(Core *core,uint64_t offset,uint32_t size)
+void *AX_Memory_Map(Core *core,uint64_t offset)
{
void *address = NULL;
uint64_t max = 0;
@@ -15,7 +15,7 @@ void *AX_Memory_Map(Core *core,uint64_t offset,uint32_t size)
{
address = core->mmap.wram;
max = core->mmap.nwram-1; //Max 2 Gio
- }
+ }
else if(offset&MEMORY_MAP_VRAM_BEGIN)
{
address = core->mmap.vram;
@@ -29,39 +29,30 @@ void *AX_Memory_Map(Core *core,uint64_t offset,uint32_t size)
else if(offset&MEMORY_MAP_SPM2_BEGIN)
{
address = core->mmap.spm2;
- max = (core->mmap.nspm2-1); //Max 64 Mio
+ max = (core->mmap.nspm2-1); //Max 256 Mio
}
- else
+ else if(offset&MEMORY_MAP_SPMT_BEGIN)
{
- uint64_t tmp = (offset>>25)&3;
- if(tmp == 0) // SPM L1
- {
- address = core->spm;
- max = 0x7FFF; //Max 32 Kio
- }else
- if(tmp == 1) // ROM
- {
- address = core->mmap.rom;
- max = (core->mmap.nrom-1); //Max 32 Mio
- }else
- if(tmp == 2) // I/O
- {
- address = core->mmap.io;
- max = 0xFFFFF; //Max 1 Mio (max 32 Mio)
- }else
- if(tmp == 3) // SPM Thread
- {
- address = core->mmap.spmt;
- max = (core->mmap.nspmt-1); //Max 32 Mio
- }
-
+ address = core->mmap.spmt;
+ max = (core->mmap.nspmt-1); //Max 128 Mio
+ }
+ else if(offset&MEMORY_MAP_ROM_BEGIN)
+ {
+ address = core->mmap.rom;
+ max = (core->mmap.nrom-1); //Max 64 Mio
+ }
+ else if(offset&MEMORY_MAP_IO_BEGIN)
+ {
+ address = core->mmap.io;
+ max = 0x7FFFFF; //Max 8 Mio (miroir 32 Mio)
+ }
+ else //SPM
+ {
+ address = core->spm;
+ max = 0x7FFF; //Max 32 Kio
}
offset &= max;
- if( (offset+size) > max)
- {
- //exit(-1);
- }
return address+offset;
@@ -130,7 +121,7 @@ int AX_init_proc_mem(Processor *processor)
processor->mmap.spmt = malloc(processor->mmap.nspmt);
processor->mmap.spm2 = malloc(processor->mmap.nspm2);
- processor->mmap.io = malloc(0x10000); // 1 Mio
+ processor->mmap.io = malloc(0x80000); // 8 Mio
return 0;
}
@@ -150,6 +141,26 @@ int AX_add_core(Processor *processor)
core->pc = 0x100/4;
core->wram = (uint32_t*)processor->mmap.wram;
+
+ int i;
+ for(i = 0;i < AR_core_DCACHE_SIZE*2;i++)
+ core->dcache[i] = 0;
+
+ for(i = 0;i < AR_core_ICACHE_SIZE;i++)
+ core->icache[i] = 0;
+
+ for(i = 0;i < AX_core_IREG_COUNT;i++)
+ core->busy_reg[i] = 0;
+
+ for(i = 0;i < AX_core_VREG_COUNT;i++)
+ core->busy_vreg[i] = 0;
+
+ core->icachemiss = 0;
+ core->dcachemiss = 0;
+ core->icachemiss_cycle = 0;
+ core->dcachemiss_cycle = 0;
+ core->bandwidth = 0;
+
processor->core[processor->icore] = core;
processor->icore++;
@@ -195,6 +206,11 @@ int AX_exe_core(Core *core)
//printf("%d\n",core->pc);
}
+ printf("%ld instructions\n",core->instruction);
+ printf("%ld cycle\n",core->cycle);
+
+ printf("IPC : %f\n",(float)core->instruction/(float)core->cycle);
+
return error;
}
diff --git a/VM/altairx/src/vm.h b/VM/altairx/src/vm.h
index 8e6bd82..51e4209 100644
--- a/VM/altairx/src/vm.h
+++ b/VM/altairx/src/vm.h
@@ -2,11 +2,8 @@
#define MEMORY_MAP_SPM1_BEGIN (0x00000000)
#define MEMORY_MAP_ROM_BEGIN (0x02000000)
#define MEMORY_MAP_IO_BEGIN (0x04000000)
-#define MEMORY_MAP_SPMT_BEGIN (0x06000000)
-
-
-#define MEMORY_MAP_SPM2_BEGIN (0x08000000)
-
+#define MEMORY_MAP_SPMT_BEGIN (0x08000000)
+#define MEMORY_MAP_SPM2_BEGIN (0x10000000)
//32 BITS
#define MEMORY_MAP_SRAM_BEGIN (0x20000000)
#define MEMORY_MAP_VRAM_BEGIN (0x40000000)
@@ -83,6 +80,7 @@ typedef struct core
uint64_t instruction;
uint64_t cycle;
+ uint64_t bandwidth;
uint32_t opcodes[AX_core_MAX_OPERATIONS];
@@ -93,6 +91,12 @@ typedef struct core
uint32_t imm;
+ uint32_t icachemiss,dcachemiss;
+ uint32_t icachemiss_cycle,dcachemiss_cycle;
+
+
+
+
/// \brief CPU Flags register
///
@@ -103,8 +107,12 @@ typedef struct core
uint16_t flags;
uint8_t delay,delayop,swt,syscall;
+ uint8_t busy_reg[AX_core_IREG_COUNT];
+ uint8_t busy_vreg[AX_core_VREG_COUNT];
+
uint8_t spm[AX_core_SPM_SIZE];
uint32_t icache[AR_core_ICACHE_SIZE];
+ uint32_t dcache[AR_core_DCACHE_SIZE*2];
uint32_t dcacher[AR_core_DCACHE_SIZE];
uint32_t dcacherw[AR_core_DCACHE_SIZE];
@@ -323,4 +331,4 @@ int AX_init_proc(Processor *processor);
int AX_init_proc_mem(Processor *processor);
void AX_init_mem(Processor *processor,int nwram,int nvram,int nsram,int nspmt,int nspm2);
int AX_load_prog(char *name,MMAP *mmap);
-void *AX_Memory_Map(Core *core,uint64_t offset,uint32_t size);
+void *AX_Memory_Map(Core *core,uint64_t offset);
diff --git a/graph/Architecture.png b/graph/Architecture.png
new file mode 100644
index 0000000..af6d351
Binary files /dev/null and b/graph/Architecture.png differ
diff --git a/vasm/cpus/AltairK1/cpu.c b/vasm/cpus/AltairK1/cpu.c
index 45c1ce6..0f8f19c 100755
--- a/vasm/cpus/AltairK1/cpu.c
+++ b/vasm/cpus/AltairK1/cpu.c
@@ -232,18 +232,6 @@ int parse_operand(char *p,int len,operand *op,int requires)
return 1;
}
- //Register BR
- if(requires == OP_RBR )
- {
- if(len != 2) return 0;
- if( !(p[0] == 'b' || p[0] == 'B') )
- return 0;
-
- if( !(p[1] == 'r' || p[1] == 'R') )
- return 0;
-
- return 1;
- }
//Register FR
if(requires == OP_RFR )
@@ -488,6 +476,16 @@ dblock *eval_instruction(instruction *p,section *sec,taddr pc)
opcode |= (operand1.type&0x3)<<26;
}
+ if(operand1.type == OP_RGQ)
+ {
+ opcode |= (0x3F<<26);
+ }
+
+ if(operand1.type == OP_RGP)
+ {
+ opcode |= (0x3E<<26);
+ }
+
//------------- OPERAND 2 -------------
if( (operand2.type == OP_REG) || (operand2.type == OP_VRG) )
{
diff --git a/vasm/cpus/AltairK1/opcodes.h b/vasm/cpus/AltairK1/opcodes.h
index 4709f33..46d58c1 100755
--- a/vasm/cpus/AltairK1/opcodes.h
+++ b/vasm/cpus/AltairK1/opcodes.h
@@ -1,51 +1,3 @@
- //LSU-A Unit 2 (010)
- "ldl", {OP_REG,OP_IMM, }, {K1,(0b00000100)},
- "stl", {OP_REG,OP_IMM, }, {K1,(0b00010100)},
- "ldvl", {OP_VRG,OP_IMM, }, {K1,(0b00100100)},
- "stvl", {OP_VRG,OP_IMM, }, {K1,(0b00110100)},
-
- "ldl2", {OP_REG,OP_IMM, }, {K1,(0b01000100)},
- "stl2", {OP_REG,OP_IMM, }, {K1,(0b01010100)},
- "ldvl2", {OP_VRG,OP_IMM, }, {K1,(0b01100100)},
- "stvl2", {OP_VRG,OP_IMM, }, {K1,(0b01110100)},
-
- "ldl3", {OP_REG,OP_IMM, }, {K1,(0b10000100)},
- "stl3", {OP_REG,OP_IMM, }, {K1,(0b10010100)},
- "ldvl3", {OP_VRG,OP_IMM, }, {K1,(0b10100100)},
- "stvl3", {OP_VRG,OP_IMM, }, {K1,(0b10110100)},
-
- "ldl4", {OP_REG,OP_IMM, }, {K1,(0b11000100)},
- "stl4", {OP_REG,OP_IMM, }, {K1,(0b11010100)},
- "ldvl4", {OP_VRG,OP_IMM, }, {K1,(0b11100100)},
- "stvl4", {OP_VRG,OP_IMM, }, {K1,(0b11110100)},
-
- //LSU-B Unit 3 (011)
- "ld", {OP_REG,OP_RRG, }, {K1,(0b00000110)},
- "st", {OP_REG,OP_RRG, }, {K1,(0b00010110)},
- "ldv", {OP_VRG,OP_RRG, }, {K1,(0b00100110)},
- "stv", {OP_VRG,OP_RRG, }, {K1,(0b00110110)},
-
- "ldi", {OP_REG,OP_IMR, }, {K1,(0b01000110)},
- "sti", {OP_REG,OP_IMR, }, {K1,(0b01010110)},
- "ldvi", {OP_VRG,OP_IMR, }, {K1,(0b01100110)},
- "stvi", {OP_VRG,OP_IMR, }, {K1,(0b01110110)},
-
- "iprefetch",{OP_IMR, }, {K1,(0b10000110)},
- "iflush", {OP_IMR, }, {K1,(0b10010110)},
- "iprefetch",{OP_RRG, }, {K1,(0b10100110)},
- "iflush", {OP_RRG, }, {K1,(0b10110110)},
-
- "prefetch", {OP_IMR, }, {K1,(0b11000110)},
- "flush", {OP_IMR, }, {K1,(0b11010110)},
- "prefetch", {OP_RRG, }, {K1,(0b11100110)},
- "flush", {OP_RRG, }, {K1,(0b11110110)},
-
- //---------
- "lddma", {OP_REG,OP_REG,OP_REG}, {K1,(0b10000110)},
- "stdma", {OP_REG,OP_REG,OP_REG}, {K1,(0b10010110)},
- "lddmai", {OP_REG,OP_REG,OP_IMM}, {K1,(0b10100110)},
- "stdmai", {OP_REG,OP_REG,OP_IMM}, {K1,(0b10110110)},
-
//ALU-A Unit 0 (000)
"nop", { }, {K1,(0b00000000)},
"sext", {OP_REG,OP_REG, }, {K1,(0b00010000)},
@@ -87,7 +39,7 @@
"move", {OP_RFR,OP_REG, }, {K1,(0b11110000)},
"move", {OP_RBR,OP_REG, }, {K1,(0b11110000)},
"move", {OP_RLR,OP_REG, }, {K1,(0b11110000)},
- "move", {OP_RIR,OP_REG, }, {K1,(0b11110000)},
+ "move", {OP_RIR,OP_REG, }, {K1,(0b11110000)},
//ALU-B Unit 1 (001)
"move", {OP_REG,OP_REG, }, {K1,(0b10110010)}, //ori
@@ -110,30 +62,54 @@
"asri", {OP_REG,OP_REG,OP_IMM}, {K1,(0b11100010)},
"lsri", {OP_REG,OP_REG,OP_IMM}, {K1,(0b11110010)},
- //BRU Unit 5 (101)
- "bne", {OP_IMB, }, {K1,(0b00001010)},
- "beq", {OP_IMB, }, {K1,(0b00011010)},
+ //LSU-A Unit 2 (010)
+ "ldl", {OP_REG,OP_IMM, }, {K1,(0b00000100)},
+ "stl", {OP_REG,OP_IMM, }, {K1,(0b00010100)},
+ "ldvl", {OP_VRG,OP_IMM, }, {K1,(0b00100100)},
+ "stvl", {OP_VRG,OP_IMM, }, {K1,(0b00110100)},
- "bl", {OP_IMB, }, {K1,(0b00101010)},
- "ble", {OP_IMB, }, {K1,(0b00111010)},
+ "ldl2", {OP_REG,OP_IMM, }, {K1,(0b01000100)},
+ "stl2", {OP_REG,OP_IMM, }, {K1,(0b01010100)},
+ "ldvl2", {OP_VRG,OP_IMM, }, {K1,(0b01100100)},
+ "stvl2", {OP_VRG,OP_IMM, }, {K1,(0b01110100)},
- "bg", {OP_IMB, }, {K1,(0b01001010)},
- "bge", {OP_IMB, }, {K1,(0b01011010)},
+ "ldl3", {OP_REG,OP_IMM, }, {K1,(0b10000100)},
+ "stl3", {OP_REG,OP_IMM, }, {K1,(0b10010100)},
+ "ldvl3", {OP_VRG,OP_IMM, }, {K1,(0b10100100)},
+ "stvl3", {OP_VRG,OP_IMM, }, {K1,(0b10110100)},
- "bls", {OP_IMB, }, {K1,(0b01101010)},
- "bles", {OP_IMB, }, {K1,(0b01111010)},
+ "ldl4", {OP_REG,OP_IMM, }, {K1,(0b11000100)},
+ "stl4", {OP_REG,OP_IMM, }, {K1,(0b11010100)},
+ "ldvl4", {OP_VRG,OP_IMM, }, {K1,(0b11100100)},
+ "stvl4", {OP_VRG,OP_IMM, }, {K1,(0b11110100)},
- "bgs", {OP_IMB, }, {K1,(0b10001010)},
- "bges", {OP_IMB, }, {K1,(0b10011010)},
+ //LSU-B Unit 3 (011)
+ "ld", {OP_REG,OP_RRG, }, {K1,(0b00000110)},
+ "st", {OP_REG,OP_RRG, }, {K1,(0b00010110)},
+ "ldv", {OP_VRG,OP_RRG, }, {K1,(0b00100110)},
+ "stv", {OP_VRG,OP_RRG, }, {K1,(0b00110110)},
- "bra", {OP_IMB, }, {K1,(0b10101010)},
- "loop", {OP_IMB, }, {K1,(0b10111010)},
+ "ldi", {OP_REG,OP_IMR, }, {K1,(0b01000110)},
+ "sti", {OP_REG,OP_IMR, }, {K1,(0b01010110)},
+ "ldvi", {OP_VRG,OP_IMR, }, {K1,(0b01100110)},
+ "stvi", {OP_VRG,OP_IMR, }, {K1,(0b01110110)},
+
+ "iprefetch",{OP_ILB, }, {K1,(0b10000110)},
+ "iflush", {OP_ILB, }, {K1,(0b10010110)},
+ "iprefetch",{OP_IMR, }, {K1,(0b10100110)},
+ "iflush", {OP_IMR, }, {K1,(0b10110110)},
+
+ "prefetch", {OP_IMR, }, {K1,(0b11000110)},
+ "flush", {OP_IMR, }, {K1,(0b11010110)},
+ "prefetch", {OP_RRG, }, {K1,(0b11100110)},
+ "flush", {OP_RRG, }, {K1,(0b11110110)},
+
+ //---------
+ "lddma", {OP_REG,OP_REG,OP_REG}, {K1,(0b10000110)},
+ "stdma", {OP_REG,OP_REG,OP_REG}, {K1,(0b10010110)},
+ "lddmai", {OP_REG,OP_REG,OP_IMM}, {K1,(0b10100110)},
+ "stdmai", {OP_REG,OP_REG,OP_IMM}, {K1,(0b10110110)},
- "jmp", {OP_ILB, }, {K1,(0b11001010)},
- "jmpbr", {OP_ILB, }, {K1,(0b11011010)},
- "call", {OP_ILB, }, {K1,(0b11101010)},
- "callbr", {OP_ILB, }, {K1,(0b11111010)},
-
//CMP Unit 4 (100)
"cmp", {OP_REG,OP_REG, }, {K1,(0b00001000)},
"cmp", {OP_RFR,OP_IMM, }, {K1,(0b00011000)},
@@ -146,15 +122,39 @@
"dcmpi", {OP_VRG,OP_IMF, }, {K1,(0b01111000)},
"endp", { }, {K1,(0b10001000)},
- "wait", { }, {K1,(0b10011000)},
- "exe", {OP_REG, }, {K1,(0b10101000)},
- //"___", {OP_REG, }, {K1,(0b10111000)},
+ "exe", {OP_REG, }, {K1,(0b10011000)},
+ "wait", { }, {K1,(0b10101000)},
+ //"_", {OP_REG, }, {K1,(0b10111000)},
"ret", { }, {K1,(0b11001000)},
"reti", { }, {K1,(0b11011000)},
"syscall", { }, {K1,(0b11101000)},
"int", { }, {K1,(0b11111000)},
+ //BRU Unit 5 (101)
+ "bne", {OP_IMB, }, {K1,(0b00001010)},
+ "beq", {OP_IMB, }, {K1,(0b00011010)},
+
+ "bl", {OP_IMB, }, {K1,(0b00101010)},
+ "ble", {OP_IMB, }, {K1,(0b00111010)},
+
+ "bg", {OP_IMB, }, {K1,(0b01001010)},
+ "bge", {OP_IMB, }, {K1,(0b01011010)},
+
+ "bls", {OP_IMB, }, {K1,(0b01101010)},
+ "bles", {OP_IMB, }, {K1,(0b01111010)},
+
+ "bgs", {OP_IMB, }, {K1,(0b10001010)},
+ "bges", {OP_IMB, }, {K1,(0b10011010)},
+
+ "bra", {OP_IMB, }, {K1,(0b10101010)},
+ "loop", {OP_IMB, }, {K1,(0b10111010)},
+
+ "jmp", {OP_ILB, }, {K1,(0b11001010)},
+ "jmpbr", {OP_ILB, }, {K1,(0b11011010)},
+ "call", {OP_ILB, }, {K1,(0b11101010)},
+ "callbr", {OP_ILB, }, {K1,(0b11111010)},
+
//VFPU-A Unit 6 (110)
"fadd", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b00001100)},
"fsub", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b00011100)},
@@ -200,18 +200,18 @@
//EFU Unit 6 (110)
"fdiv", {OP_RGQ,OP_VRG,OP_VRG}, {K1,(0b00001100)},
"fsqrt", {OP_RGQ,OP_VRG, }, {K1,(0b00011100)},
- //"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b00101100)},
- //"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b00111100)},
+ "ddiv", {OP_RGQ,OP_VRG,OP_VRG}, {K1,(0b00101100)},
+ "dsqrt", {OP_RGQ,OP_VRG, }, {K1,(0b00111100)},
"fatan", {OP_RGQ,OP_VRG, }, {K1,(0b01001100)},
"fatan2", {OP_RGQ,OP_VRG,OP_VRG}, {K1,(0b01011100)},
"fexp", {OP_RGQ,OP_VRG, }, {K1,(0b01101100)},
- //"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b01111100)},
+ //"___", {OP_RGQ,OP_VRG, }, {K1,(0b01111100)},
"fsum", {OP_RGP,OP_VRG,OP_VRG}, {K1,(0b10001100)},
"fipr", {OP_RGP,OP_VRG,OP_VRG}, {K1,(0b10011100)},
"fsin", {OP_RGP,OP_VRG, }, {K1,(0b10101100)},
- //"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b10111100)},
+ "dsin", {OP_RGP,OP_VRG, }, {K1,(0b10111100)},
//"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b11001100)},
//"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b11011100)},
@@ -229,9 +229,9 @@
"dmin", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b01101110)},
"dmax", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b01111110)},
- "ddiv", {OP_RGQ,OP_VRG,OP_VRG}, {K1,(0b10001110)},
- "dsqrt", {OP_RGQ,OP_VRG, }, {K1,(0b10011110)},
- "dsin", {OP_RGP,OP_VRG, }, {K1,(0b10101110)},
+ //"ddiv", {OP_RGQ,OP_VRG,OP_VRG}, {K1,(0b10001110)},
+ //"dsqrt", {OP_RGQ,OP_VRG, }, {K1,(0b10011110)},
+ //"dsin", {OP_RGP,OP_VRG, }, {K1,(0b10101110)},
//"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b10111110)},
//"____", {OP_VRG,OP_VRG,OP_VRG}, {K1,(0b11001110)},
diff --git a/vasm/obj/AltairK1_mot_cpu.o b/vasm/obj/AltairK1_mot_cpu.o
index 96c428b..0165db7 100644
Binary files a/vasm/obj/AltairK1_mot_cpu.o and b/vasm/obj/AltairK1_mot_cpu.o differ
diff --git a/vasm/vasmAltairK1_mot b/vasm/vasmAltairK1_mot
index e205419..6c388d2 100755
Binary files a/vasm/vasmAltairK1_mot and b/vasm/vasmAltairK1_mot differ