The objectives of this project is to design, implement and simulate an fpga virtual composant in differents languages and platorms to compare performance of each.
Simulate with GHDL or/and NVC.
Simulate with icarus or/and Verilator.
Simulate with same tools than for verilog.
Simulate in scala Chisel and/or Verilator
Simulate in Haskell clash language.
Simulate in Python Based HDL.
i.MX6 + CycloneV board from Armadeus System.
Ice40 little dev kit (usb key)
A lowcost ECP5 kit.