diff --git a/difftest b/difftest
index eebf5547..0a3afff8 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit eebf5547a66fa58be9d38ee731b4efecfc6e36e9
+Subproject commit 0a3afff8985117840656c4461c2a7c931e99a80b
diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala
index 2fdd7d80..9f10463d 100644
--- a/src/main/scala/sim/NutShellSim.scala
+++ b/src/main/scala/sim/NutShellSim.scala
@@ -30,12 +30,6 @@ import utils.GTimer
 import difftest._
 
 class SimTop extends Module {
-  val io = IO(new Bundle{
-    val logCtrl = new LogCtrlIO
-    val perfInfo = new PerfInfoIO
-    val uart = new UARTIO
-  })
-
   lazy val config = NutCoreConfig(FPGAPlatform = false)
   val soc = Module(new NutShell()(config))
   val mem = Module(new AXI4RAM(memByte = 128 * 1024 * 1024, useBlackBox = true))
@@ -53,10 +47,12 @@ class SimTop extends Module {
 
   soc.io.meip := mmio.io.meip
 
+  val difftest = DifftestModule.finish("nutshell")
+
   val log_begin, log_end, log_level = WireInit(0.U(64.W))
-  log_begin := io.logCtrl.log_begin
-  log_end := io.logCtrl.log_end
-  log_level := io.logCtrl.log_level
+  log_begin := difftest.logCtrl.begin
+  log_end := difftest.logCtrl.end
+  log_level := difftest.logCtrl.level
 
   assert(log_begin <= log_end)
   BoringUtils.addSource(WireInit((GTimer() >= log_begin) && (GTimer() < log_end)), "DISPLAY_ENABLE")
@@ -65,7 +61,5 @@ class SimTop extends Module {
   val dummyWire = WireInit(false.B)
   BoringUtils.addSink(dummyWire, "DISPLAY_ENABLE")
 
-  io.uart <> mmio.io.uart
-
-  DifftestModule.finish("nutshell")
+  difftest.uart <> mmio.io.uart
 }