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FPGA - SDRAM Communication
If you haven't done it already, I would recommend working on the Simple Hardware Adder project first before attempting this one. That project covers a lot of introductory concepts such Platform Designer, Avalon Slaves, memory addressing etc. which we'll build upon in this project.
In this project, we'll up the game quite a bit and introduce several new concepts and techniques. These include:
- Avalon MM Burst transactions
- Custom Avalon Memory Mapped (MM) Master Component
- HPS hardware register modifications
And perhaps more. I'll try to be as detailed as possible, but as always, if I've missed anything please raise an issue and I'll try to address it.
In the previous project, we used the HPS to FPGA bridge to share data from the HPS to the FPGA. While this works fine for many data transfers, it's not fast enough when dealing with video data. For that reading and writing to SDRAM will be much faster. The Cyclone V FPGA supports this and we'll be taking advantage of it.
By the end of the project we will read a value from SDRAM and show it on the LEDs of the de10-nano. Note that it is very unlikely that you would use the SDRAM in this way, but this allows us to keep the project simple so that the concepts make sense. This is a lot more complicated than appears at first glance.
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