diff --git a/bsp/bouffalo_lab/bl808/m0/board/wlan_port/drv_wifi.c b/bsp/bouffalo_lab/bl808/m0/board/wlan_port/drv_wifi.c
index faa52f50f2b4..01795a05b1be 100644
--- a/bsp/bouffalo_lab/bl808/m0/board/wlan_port/drv_wifi.c
+++ b/bsp/bouffalo_lab/bl808/m0/board/wlan_port/drv_wifi.c
@@ -303,7 +303,7 @@ static rt_err_t drv_wlan_softap(struct rt_wlan_device *wlan, struct rt_ap_info *
     }
 
     if (ret < 0)
-        return RT_ERROR;
+        return -RT_ERROR;
 
     return RT_EOK;
 }
diff --git a/bsp/microblaze/board.c b/bsp/microblaze/board.c
index f46f431492aa..74af2076be19 100755
--- a/bsp/microblaze/board.c
+++ b/bsp/microblaze/board.c
@@ -33,83 +33,83 @@
 #include "drivers/dev_serial.h"
 #endif
 
-#define  TIMER_CNTR_0		0
-#define  PIV  				(XPAR_PROC_BUS_0_FREQ_HZ / RT_TICK_PER_SECOND)
-#define  LEDS_DEVICE_ID    	XPAR_LEDS_4BITS_DEVICE_ID
-#define  RS232_DEVICE_ID   	XPAR_USB_UART_DEVICE_ID
+#define  TIMER_CNTR_0       0
+#define  PIV                (XPAR_PROC_BUS_0_FREQ_HZ / RT_TICK_PER_SECOND)
+#define  LEDS_DEVICE_ID     XPAR_LEDS_4BITS_DEVICE_ID
+#define  RS232_DEVICE_ID    XPAR_USB_UART_DEVICE_ID
 
 #ifdef   RT_USING_UART1
-#define  USB_UART_BASE		((struct uartport *)XPAR_USB_UART_BASEADDR)
+#define  USB_UART_BASE      ((struct uartport *)XPAR_USB_UART_BASEADDR)
 #endif
 
 /* Global Variables: */
-XTmrCtr 	timer; 			/* The instance of the timer */
-XGpio 		gpio_output; 	/* The driver instance for GPIO Device configured as O/P */
-XUartLite 	uart_lite; 		/* Instance of the UartLite device */
-XIntc 		int_ctl; 		/* The instance of the Interrupt Controller */
-static		rt_uint32_t led_data;
+XTmrCtr     timer;          /* The instance of the timer */
+XGpio       gpio_output;    /* The driver instance for GPIO Device configured as O/P */
+XUartLite   uart_lite;      /* Instance of the UartLite device */
+XIntc       int_ctl;        /* The instance of the Interrupt Controller */
+static      rt_uint32_t led_data;
 static int cnt;
 
 
 
 static void rt_hw_board_led_init(void);
 
-/** 
+/**
  * This function will init led on the board
  */
 static void rt_hw_board_led_init()
 {
-	rt_uint32_t status;
-	led_data = 0;
-	cnt = 0;
-	status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
-	if (status != XST_SUCCESS)
-	{
-		return;
-	}
-
-	/*
-	 * Set the direction for all signals to be outputs
-	 */
-	XGpio_SetDataDirection(&gpio_output, 1, 0x0);
-	/*
-	 * Set the GPIO outputs to high
-	 */
-	XGpio_DiscreteWrite(&gpio_output, 1, 3);
+    rt_uint32_t status;
+    led_data = 0;
+    cnt = 0;
+    status = XGpio_Initialize(&gpio_output, LEDS_DEVICE_ID);
+    if (status != XST_SUCCESS)
+    {
+        return;
+    }
+
+    /*
+     * Set the direction for all signals to be outputs
+     */
+    XGpio_SetDataDirection(&gpio_output, 1, 0x0);
+    /*
+     * Set the GPIO outputs to high
+     */
+    XGpio_DiscreteWrite(&gpio_output, 1, 3);
 }
 
-/** 
+/**
  * This function will take the led on board on.
  *
  * @param n the number nth led
  */
 void rt_hw_board_led_on(rt_uint32_t led)
 {
-	led_data |= led;
-	XGpio_DiscreteWrite(&gpio_output, 1, led_data);
+    led_data |= led;
+    XGpio_DiscreteWrite(&gpio_output, 1, led_data);
 }
 
-/** 
+/**
  * This function will take the led on board off.
  *
  * @param n the number nth led
  */
 void rt_hw_board_led_off(rt_uint32_t led)
 {
-	led_data &= ~led;
-	XGpio_DiscreteWrite(&gpio_output, 1, led_data);
+    led_data &= ~led;
+    XGpio_DiscreteWrite(&gpio_output, 1, led_data);
 }
 
 
 void rt_hw_led_flash(void)
 {
-	volatile rt_uint32_t i;
+    volatile rt_uint32_t i;
 
-	rt_hw_board_led_off(1);
-	for (i = 0; i < 20000; i ++);
+    rt_hw_board_led_off(1);
+    for (i = 0; i < 20000; i ++);
 
-	rt_hw_board_led_on(1);
-	for (i = 0; i < 20000; i ++);
+    rt_hw_board_led_on(1);
+    for (i = 0; i < 20000; i ++);
 }
 
 
@@ -126,30 +126,30 @@ void rt_hw_led_flash(void)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
+    while (*str)
+    {
 
-		/* Transmit Character */
+        /* Transmit Character */
 
-		XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
-		if (*str == '\n')
-			XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
-		str++;
-	}
+        XUartLite_SendByte(STDOUT_BASEADDRESS, *str);
+        if (*str == '\n')
+            XUartLite_SendByte(STDOUT_BASEADDRESS, '\r');
+        str++;
+    }
 }
 
 static void rt_hw_console_init()
 {
-	rt_uint32_t status;
+    rt_uint32_t status;
 
-	/*
-	* Initialize the UartLite driver so that it is ready to use.
-	*/
-	status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
-	if (status != XST_SUCCESS)
-	{
-		return;
-	}
+    /*
+    * Initialize the UartLite driver so that it is ready to use.
+    */
+    status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID);
+    if (status != XST_SUCCESS)
+    {
+        return;
+    }
 
 }
 #endif
@@ -157,16 +157,16 @@ static void rt_hw_console_init()
 
 void rt_hw_timer_handler(void)
 {
-	rt_uint32_t csr;
-	csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET);
-	/*
-	 * Check if timer expired and interrupt occured
-	 */
-	if (csr & XTC_CSR_INT_OCCURED_MASK)
-	{
-		rt_tick_increase();
-		XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
-	}
+    rt_uint32_t csr;
+    csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET);
+    /*
+     * Check if timer expired and interrupt occured
+     */
+    if (csr & XTC_CSR_INT_OCCURED_MASK)
+    {
+        rt_tick_increase();
+        XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK);
+    }
 
 }
 
@@ -192,24 +192,24 @@ void  rt_intc_init (void)
 
     status = XIntc_Initialize(&int_ctl, XPAR_INTC_0_DEVICE_ID);
 
-	/* install interrupt handler */
+    /* install interrupt handler */
     rt_hw_interrupt_install(XPAR_INTC_0_TMRCTR_0_VEC_ID, (rt_isr_handler_t)rt_hw_timer_handler, RT_NULL);
-	rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
+    rt_hw_interrupt_umask(XPAR_INTC_0_TMRCTR_0_VEC_ID);
 
-	XIntc_Start(&int_ctl, XIN_REAL_MODE);
+    XIntc_Start(&int_ctl, XIN_REAL_MODE);
 
 }
 
 
 void  rt_tmr_init (void)
 {
-	rt_uint32_t ctl;
-    XStatus  	status;
+    rt_uint32_t ctl;
+    XStatus     status;
 
     status = XTmrCtr_Initialize(&timer,XPAR_AXI_TIMER_0_DEVICE_ID);
-	XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
+    XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV);
     ctl = XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK;
-	XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
+    XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl);
 }
 
 
@@ -219,15 +219,15 @@ void  rt_tmr_init (void)
  */
 void rt_hw_board_init()
 {
-	microblaze_disable_icache();
-	microblaze_disable_dcache();
-	/* init hardware console */
-	rt_hw_console_init();
+    microblaze_disable_icache();
+    microblaze_disable_dcache();
+    /* init hardware console */
+    rt_hw_console_init();
 
-	/* init led */
-	rt_hw_board_led_init();
+    /* init led */
+    rt_hw_board_led_init();
 
-	/* init intc */
+    /* init intc */
     rt_intc_init();
 
     /* timer init */
diff --git a/bsp/mini2440/drivers/s3cmci.c b/bsp/mini2440/drivers/s3cmci.c
index e85d4bc6ceff..a646707ceacd 100644
--- a/bsp/mini2440/drivers/s3cmci.c
+++ b/bsp/mini2440/drivers/s3cmci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,7 +13,7 @@
 #include <drivers/dev_mmcsd_core.h>
 #include <s3c24x0.h>
 
-#define S3C_PCLK	50000000
+#define S3C_PCLK    50000000
 
 
 static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock)
@@ -21,10 +21,10 @@ static void s3c_mmc_set_clk(struct rt_mmcsd_host *host, rt_uint32_t clock)
     rt_uint32_t prescale;
     rt_uint32_t realClk;
 
-    for(prescale = 0; prescale < 256; ++prescale) 
+    for(prescale = 0; prescale < 256; ++prescale)
     {
         realClk = S3C_PCLK / (1 + prescale);
-        if(realClk <= clock) 
+        if(realClk <= clock)
         {
             break;
         }
@@ -47,29 +47,29 @@ static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_
 
     if(cmd->flags & 0xF)
     {
-        // Need response
+        /* Need response*/
         ccon |= (1 << 9);
     }
 
     if((cmd->flags & 0xF) == RESP_R2)
     {
-        // R2 need 136bit response
+        /* R2 need 136bit response*/
         ccon |= (1 << 10);
     }
 
     SDICCON = ccon; /* start cmd */
 
-    if(cmd->flags & 0xF) 
+    if(cmd->flags & 0xF)
     {
         cmdSta = SDICSTA;
-        while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400) 
+        while((cmdSta & 0x200) != 0x200 && (cmdSta & 0x400) != 0x400)
         {
             cmdSta = SDICSTA;
         }
 
-        if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4) 
+        if((cmdSta & 0x1000) == 0x1000 && (cmd->flags & 0xF) != RESP_R3 && (cmd->flags & 0xF) != RESP_R4)
         {
-            // crc error, but R3 R4 ignore it
+            /* crc error, but R3 R4 ignore it*/
             SDICSTA = cmdSta;
             return -RT_ERROR;
         }
@@ -81,7 +81,7 @@ static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_
         }
 
         cmd->resp[0] = SDIRSP0;
-        if((cmd->flags & 0xF) == RESP_R2) 
+        if((cmd->flags & 0xF) == RESP_R2)
         {
             cmd->resp[1] = SDIRSP1;
             cmd->resp[2] = SDIRSP2;
@@ -94,10 +94,10 @@ static rt_uint32_t s3c_mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_
         while((cmdSta & 0x800) != 0x800)
         {
             cmdSta = SDICSTA;
-        } 
+        }
     }
 
-    SDICSTA = cmdSta; // clear current status
+    SDICSTA = cmdSta; /* clear current status*/
 
     return RT_EOK;
 
@@ -126,7 +126,7 @@ static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
             if ((SDIDSTA & 0x20) == 0x20)
             {
                 SDIDSTA = (0x1 << 0x5);
-                break; 
+                break;
             }
 
             status = SDIFSTA;
@@ -137,7 +137,7 @@ static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
             }
         }
     }
-    else 
+    else
     {
         while(handled_size < xfer_size)
         {
@@ -150,7 +150,7 @@ static rt_uint32_t s3c_mmc_xfer_data(struct rt_mmcsd_data *data)
         }
     }
 
-    // wait for end
+    /* wait for end*/
     status = SDIDSTA;
     while((status & 0x30) == 0)
     {
@@ -184,9 +184,9 @@ static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
     cmd = req->cmd;
 
     /* prepare for data transfer*/
-    if(req->data != RT_NULL) 
+    if(req->data != RT_NULL)
     {
-        SDIFSTA = SDIFSTA | (1<<16); // reset fifo 
+        SDIFSTA = SDIFSTA | (1<<16); /* reset fifo*/
 
         while(SDIDSTA & 0x03)
         {
@@ -204,23 +204,23 @@ static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
             goto out;
         }
 
-        val = (2 << 22)  //word transfer
-                  | (1 << 20) // transmet after response
-                  | (1 << 19) // reciveve after command sent
-                  | (1 << 17) // block data transfer
-                  | (1 << 14); // data start
+        val = (2 << 22)  /*word transfer*/
+                  | (1 << 20) /* transmet after response*/
+                  | (1 << 19) /* reciveve after command sent*/
+                  | (1 << 17) /* block data transfer*/
+                  | (1 << 14); /* data start*/
 
         if(host->io_cfg.bus_width == MMCSD_BUS_WIDTH_4)
         {
-            val |= (1 << 16); // wide bus mode(4bit data)
+            val |= (1 << 16); /* wide bus mode(4bit data)*/
         }
 
-        if(data->flags & DATA_DIR_READ) 
+        if(data->flags & DATA_DIR_READ)
         {
-            // for data read 
+            /* for data read*/
             val |= (2 << 12);
         }
-        else 
+        else
         {
             val |= (3 << 12);
         }
@@ -234,7 +234,8 @@ static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
     }
 
     ret = s3c_mmc_send_cmd(host,req->cmd);
-    if(ret != RT_EOK) {
+    if(ret != RT_EOK)
+    {
         cmd->err = ret;
         goto out;
     }
@@ -255,12 +256,13 @@ static void mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
 }
 static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
 {
-    switch (io_cfg->power_mode) {
+    switch (io_cfg->power_mode)
+    {
     case MMCSD_POWER_ON:
     case MMCSD_POWER_UP:
         /* Enable PCLK into SDI Block */
         CLKCON |= 1 << 9;
-        
+
         /* Setup GPIO as SD and SDCMD, SDDAT[3:0] Pull up En */
         GPEUP  = GPEUP  & (~(0x3f << 5))   | (0x01 << 5);
         GPECON = GPECON & (~(0xfff << 10)) | (0xaaa << 10);
@@ -268,7 +270,7 @@ static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io
 
     case MMCSD_POWER_OFF:
     default:
-        break;                 
+        break;
     }
 
     s3c_mmc_set_clk(host, io_cfg->clock);
@@ -284,7 +286,7 @@ static void mmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
 {
 }
 
-static const struct rt_mmcsd_host_ops ops = 
+static const struct rt_mmcsd_host_ops ops =
 {
     mmc_request,
     mmc_set_iocfg,
diff --git a/bsp/samd21/applications/application.c b/bsp/samd21/applications/application.c
index 54d755bb132f..3247e0a4bb96 100644
--- a/bsp/samd21/applications/application.c
+++ b/bsp/samd21/applications/application.c
@@ -35,35 +35,35 @@ void extint_detection_callback(void);
 
 void configure_extint_channel(void)
 {
-//! [setup_1]
+/*! [setup_1]*/
     struct extint_chan_conf config_extint_chan;
-//! [setup_1]
-//! [setup_2]
+/*! [setup_1]*/
+/*! [setup_2]*/
     extint_chan_get_config_defaults(&config_extint_chan);
-//! [setup_2]
+/*! [setup_2]*/
 
-//! [setup_3]
+/*! [setup_3]*/
     config_extint_chan.gpio_pin           = PIN_PA15A_EIC_EXTINT15;
     config_extint_chan.gpio_pin_mux       = MUX_PA15A_EIC_EXTINT15;
     config_extint_chan.gpio_pin_pull      = EXTINT_PULL_UP;
     config_extint_chan.detection_criteria = EXTINT_DETECT_BOTH;
-//! [setup_3]
-//! [setup_4]
+/*! [setup_3]*/
+/*! [setup_4]*/
     extint_chan_set_config(15, &config_extint_chan);
-//! [setup_4]
+/*! [setup_4]*/
 }
 
 void configure_extint_callbacks(void)
 {
-//! [setup_5]
+/*! [setup_5]*/
     extint_register_callback(extint_detection_callback, 15, EXTINT_CALLBACK_TYPE_DETECT);
-//! [setup_5]
-//! [setup_6]
+/*! [setup_5]*/
+/*! [setup_6]*/
     extint_chan_enable_callback(15, EXTINT_CALLBACK_TYPE_DETECT);
-//! [setup_6]
+/*! [setup_6]*/
 }
 
-//! [setup_7]
+/*! [setup_7]*/
 void extint_detection_callback(void)
 {
     bool pin_state = port_pin_get_input_level(PIN_PA15);
@@ -97,7 +97,7 @@ void rt_init_thread_entry(void* parameter)
     configure_extint_callbacks();
 
     sleep_timer_init();
-    // sleep_timer_start(1500);
+    /* sleep_timer_start(1500);*/
 
     while (1)
     {
diff --git a/bsp/samd21/board/board.c b/bsp/samd21/board/board.c
index 282a179281d6..6ec74dcf2c62 100644
--- a/bsp/samd21/board/board.c
+++ b/bsp/samd21/board/board.c
@@ -10,91 +10,91 @@
 void SysTick_Handler(void)
 {
     /* enter interrupt */
-	rt_interrupt_enter();
+    rt_interrupt_enter();
 
-	rt_tick_increase();
+    rt_tick_increase();
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 }
 
 void configure_extosc32k(void);
 void configure_dfll_open_loop(void);
 
-//! [setup]
-//! [config_extosc32k]
+/*! [setup]*/
+/*! [config_extosc32k]*/
 void configure_extosc32k(void)
 {
-//! [config_extosc32k_config]
-	struct system_clock_source_xosc32k_config config_ext32k;
-//! [config_extosc32k_config]
-//! [config_extosc32k_get_defaults]
-	system_clock_source_xosc32k_get_config_defaults(&config_ext32k);
-//! [config_extosc32k_get_defaults]
-
-//! [config_extosc32k_change_defaults]
-	config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;
+/*! [config_extosc32k_config]*/
+    struct system_clock_source_xosc32k_config config_ext32k;
+/*! [config_extosc32k_config]*/
+/*! [config_extosc32k_get_defaults]*/
+    system_clock_source_xosc32k_get_config_defaults(&config_ext32k);
+/*! [config_extosc32k_get_defaults]*/
+
+/*! [config_extosc32k_change_defaults]*/
+    config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;
     config_ext32k.on_demand = false;
-//! [config_extosc32k_change_defaults]
+/*! [config_extosc32k_change_defaults]*/
 
-//! [config_extosc32k_set_config]
-	system_clock_source_xosc32k_set_config(&config_ext32k);
-//! [config_extosc32k_set_config]
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+/*! [config_extosc32k_set_config]*/
+    system_clock_source_xosc32k_set_config(&config_ext32k);
+/*! [config_extosc32k_set_config]*/
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
 }
-//! [config_extosc32k]
+/*! [config_extosc32k]*/
 
 #if (!SAMC21)
-//! [config_dfll]
+/*! [config_dfll]*/
 void configure_dfll_open_loop(void)
 {
-//! [config_dfll_config]
-	struct system_clock_source_dfll_config config_dfll;
-//! [config_dfll_config]
-//! [config_dfll_get_defaults]
-	system_clock_source_dfll_get_config_defaults(&config_dfll);
-//! [config_dfll_get_defaults]
-	config_dfll.coarse_value    = (*((uint8_t*)(0x806020 + 7))) >> 2;// 0x1f / 4; /* Midpoint */
-	config_dfll.fine_value      = (*((uint32_t*)(0x806020 + 8))) & 0x3FF;//0xff / 4; /* Midpoint */
-//! [config_dfll_set_config]
-	system_clock_source_dfll_set_config(&config_dfll);
-//! [config_dfll_set_config]
-
-//! [enable_dfll_main]
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
-	// while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
-
-//! [enable_dfll_main]
-	/* Configure flash wait states before switching to high frequency clock */
-//! [set_sys_wait_states]
-	system_flash_set_waitstates(2);
-//! [set_sys_wait_states]
-
-	/* Change system clock to DFLL */
-//! [set_sys_clk_src]
-	struct system_gclk_gen_config config_gclock_gen;
-	system_gclk_gen_get_config_defaults(&config_gclock_gen);
-	config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
-	config_gclock_gen.division_factor = 1;
-	system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
-//! [set_sys_clk_src]
+/*! [config_dfll_config]*/
+    struct system_clock_source_dfll_config config_dfll;
+/*! [config_dfll_config]*/
+/*! [config_dfll_get_defaults]*/
+    system_clock_source_dfll_get_config_defaults(&config_dfll);
+/*! [config_dfll_get_defaults]*/
+    config_dfll.coarse_value    = (*((uint8_t*)(0x806020 + 7))) >> 2;/* 0x1f / 4; /* Midpoint */
+    config_dfll.fine_value      = (*((uint32_t*)(0x806020 + 8))) & 0x3FF;/*0xff / 4; /* Midpoint */
+/*! [config_dfll_set_config]*/
+    system_clock_source_dfll_set_config(&config_dfll);
+/*! [config_dfll_set_config]*/
+
+/*! [enable_dfll_main]*/
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+    /* while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));*/
+
+/*! [enable_dfll_main]*/
+    /* Configure flash wait states before switching to high frequency clock */
+/*! [set_sys_wait_states]*/
+    system_flash_set_waitstates(2);
+/*! [set_sys_wait_states]*/
+
+    /* Change system clock to DFLL */
+/*! [set_sys_clk_src]*/
+    struct system_gclk_gen_config config_gclock_gen;
+    system_gclk_gen_get_config_defaults(&config_gclock_gen);
+    config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
+    config_gclock_gen.division_factor = 1;
+    system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
+/*! [set_sys_clk_src]*/
 }
-//! [config_dfll]
+/*! [config_dfll]*/
 #endif
 
 void rt_board_init(void)
 {
     extern void uart_init(void);
 
-    // configure_extosc32k();
+    /* configure_extosc32k();*/
 
-    // configure_dfll_open_loop();
-	system_init();
+    /* configure_dfll_open_loop();*/
+    system_init();
 
-	/* initialize systick */
-	SystemCoreClock = system_gclk_gen_get_hz(0);
-	SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    /* initialize systick */
+    SystemCoreClock = system_gclk_gen_get_hz(0);
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
 
     uart_init();
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
diff --git a/bsp/samd21/board/sleep_timer.c b/bsp/samd21/board/sleep_timer.c
index a676d5bc859e..c2374f5004ae 100644
--- a/bsp/samd21/board/sleep_timer.c
+++ b/bsp/samd21/board/sleep_timer.c
@@ -1,7 +1,7 @@
-// From module: RTC - Real Time Counter in Count Mode (Polled APIs)
+/* From module: RTC - Real Time Counter in Count Mode (Polled APIs)*/
 #include <rtc_count.h>
 #include <rtc_count_interrupt.h>
-// #include <rtc_tamper.h>
+/* #include <rtc_tamper.h>*/
 #include <power.h>
 #include <port.h>
 
@@ -12,115 +12,115 @@ static struct rtc_module rtc_instance;
 
 static void _rtc_timer_int_cb(void)
 {
-	port_pin_toggle_output_level(PIN_PB30);
+    port_pin_toggle_output_level(PIN_PB30);
 }
 
 /* Init RTC as ADC sample timer */
 static void _rtc_timer_init(void)
 {
-	struct rtc_count_config conf;
+    struct rtc_count_config conf;
 
-	rtc_count_get_config_defaults(&conf);
+    rtc_count_get_config_defaults(&conf);
 
-	conf.prescaler         = RTC_COUNT_PRESCALER_DIV_1;
-	conf.mode              = RTC_COUNT_MODE_32BIT;
-	conf.clear_on_match    = false;
-	conf.compare_values[0] = 0;
+    conf.prescaler         = RTC_COUNT_PRESCALER_DIV_1;
+    conf.mode              = RTC_COUNT_MODE_32BIT;
+    conf.clear_on_match    = false;
+    conf.compare_values[0] = 0;
 
-	// struct rtc_count_events evconfig;
-	// evconfig.generate_event_on_compare[0] = true;
+    /* struct rtc_count_events evconfig;*/
+    /* evconfig.generate_event_on_compare[0] = true;*/
 
-	rtc_count_init(&rtc_instance, RTC, &conf);
-	// rtc_count_enable_events(&rtc_instance, &evconfig);
-    // rtc_count_enable(&rtc_instance);
-	rtc_count_set_count(&rtc_instance, 0);
-	rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
-	// rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+    rtc_count_init(&rtc_instance, RTC, &conf);
+    /* rtc_count_enable_events(&rtc_instance, &evconfig);*/
+    /* rtc_count_enable(&rtc_instance);*/
+    rtc_count_set_count(&rtc_instance, 0);
+    rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
+    /* rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);*/
 }
 
 static void _rtc_timer_start(uint32_t ms)
 {
-	uint32_t compare = 0;
+    uint32_t compare = 0;
 
-	compare = (uint32_t)(32.768 * ms);
+    compare = (uint32_t)(32.768 * ms);
 
-	// rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
-	rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+    /* rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);*/
+    rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
 
-	rtc_count_set_count(&rtc_instance, 0);
-	rtc_count_set_compare(&rtc_instance, compare, RTC_COUNT_COMPARE_0);
-	rtc_count_enable(&rtc_instance);
+    rtc_count_set_count(&rtc_instance, 0);
+    rtc_count_set_compare(&rtc_instance, compare, RTC_COUNT_COMPARE_0);
+    rtc_count_enable(&rtc_instance);
 }
 
 static void sleep_tick_adjust(uint32_t ms)
 {
-	uint32_t diff;
+    uint32_t diff;
 
-	diff = rt_tick_from_millisecond(ms);
+    diff = rt_tick_from_millisecond(ms);
 
-	rt_tick_set(rt_tick_get() + diff);
-	{
-		struct rt_thread *thread;
+    rt_tick_set(rt_tick_get() + diff);
+    {
+        struct rt_thread *thread;
 
-		/* check time slice */
-		thread = rt_thread_self();
+        /* check time slice */
+        thread = rt_thread_self();
 
-		if (thread->remaining_tick <= diff)
-		{
-			/* change to initialized tick */
-			thread->remaining_tick = thread->init_tick;
+        if (thread->remaining_tick <= diff)
+        {
+            /* change to initialized tick */
+            thread->remaining_tick = thread->init_tick;
 
-			/* yield */
-			rt_thread_yield();
-		}
-		else
-		{
-			thread->remaining_tick -= diff;
-		}
+            /* yield */
+            rt_thread_yield();
+        }
+        else
+        {
+            thread->remaining_tick -= diff;
+        }
 
-		/* check timer */
-		rt_timer_check();
-	}
+        /* check timer */
+        rt_timer_check();
+    }
 }
 
 static void _sleep_entry(void)
 {
-	rt_tick_t timeout;
-	rt_uint32_t ms;
-	rt_uint32_t count;
+    rt_tick_t timeout;
+    rt_uint32_t ms;
+    rt_uint32_t count;
 
-	system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
-	timeout = rt_timer_next_timeout_tick() - rt_tick_get();
+    system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
+    timeout = rt_timer_next_timeout_tick() - rt_tick_get();
 
-	ms = timeout * (1000 / RT_TICK_PER_SECOND);
-	rt_kprintf("os tick:%u entry sleep:%u tick\r\n", rt_tick_get(), timeout);
+    ms = timeout * (1000 / RT_TICK_PER_SECOND);
+    rt_kprintf("os tick:%u entry sleep:%u tick\r\n", rt_tick_get(), timeout);
 
-	_rtc_timer_start(ms);
+    _rtc_timer_start(ms);
 
-	system_sleep();
+    system_sleep();
 
-	rt_enter_critical();
-	count = rtc_count_get_count(&rtc_instance);
-	ms = (count + 32) / 32.768;
-	rtc_count_disable(&rtc_instance);
-	sleep_tick_adjust(ms);
-	timeout = rt_tick_get();
-	rt_exit_critical();
-	rt_kprintf("sleep exited, os tick:%u\n", timeout);
+    rt_enter_critical();
+    count = rtc_count_get_count(&rtc_instance);
+    ms = (count + 32) / 32.768;
+    rtc_count_disable(&rtc_instance);
+    sleep_tick_adjust(ms);
+    timeout = rt_tick_get();
+    rt_exit_critical();
+    rt_kprintf("sleep exited, os tick:%u\n", timeout);
 }
 
 void sleep_timer_init(void)
 {
-	_rtc_timer_init();
-	rt_thread_idle_sethook(_sleep_entry);
+    _rtc_timer_init();
+    rt_thread_idle_sethook(_sleep_entry);
 }
 
 void sleep_timer_start(uint32_t ms)
 {
-	_rtc_timer_start(ms);
+    _rtc_timer_start(ms);
 }
 
 void sleep_timer_stop(void)
 {
-	rtc_count_disable(&rtc_instance);
+    rtc_count_disable(&rtc_instance);
 }
diff --git a/bsp/samd21/board/uart.c b/bsp/samd21/board/uart.c
index 666ebefc6416..2a61f2b0c00f 100644
--- a/bsp/samd21/board/uart.c
+++ b/bsp/samd21/board/uart.c
@@ -1,11 +1,11 @@
-// From module: SERCOM Callback API
+/* From module: SERCOM Callback API*/
 #include <samd21.h>
 #include <sercom.h>
-// #include <sercom_interrupt.h>
+/* #include <sercom_interrupt.h>*/
 
-// From module: SERCOM USART - Serial Communications (Callback APIs)
+/* From module: SERCOM USART - Serial Communications (Callback APIs)*/
 #include <usart.h>
-// #include <usart_interrupt.h>
+/* #include <usart_interrupt.h>*/
 
 #include <rtdevice.h>
 
@@ -36,9 +36,9 @@ static SAMD2x_UART_T _uart3 = {
     SYSTEM_INTERRUPT_MODULE_SERCOM3
 };
 
-// static struct rt_serial_device _serial2;
-// static struct rt_serial_device _serial3;
-// static struct rt_serial_device _serial4;
+/* static struct rt_serial_device _serial2;*/
+/* static struct rt_serial_device _serial3;*/
+/* static struct rt_serial_device _serial4;*/
 
 static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
@@ -48,12 +48,12 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
     RT_ASSERT(cfg != RT_NULL);
 
     uart = (SAMD2x_UART_T *)serial->parent.user_data;
-    //! [setup_config]
-	struct usart_config config_usart;
-    //! [setup_config]
-    //! [setup_config_defaults]
+    /*! [setup_config]*/
+    struct usart_config config_usart;
+    /*! [setup_config]*/
+    /*! [setup_config_defaults]*/
     usart_get_config_defaults(&config_usart);
-    //! [setup_config_defaults]
+    /*! [setup_config_defaults]*/
     config_usart.baudrate = cfg->baud_rate;
 
     switch (cfg->data_bits )
@@ -122,7 +122,8 @@ static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configu
     config_usart.receiver_enable = false;
     config_usart.transmitter_enable = true;
 
-    while (usart_init(uart->instance, uart->com, &config_usart) != STATUS_OK) {
+    while (usart_init(uart->instance, uart->com, &config_usart) != STATUS_OK)
+    {
     }
 
     usart_enable(uart->instance);
@@ -148,7 +149,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
         usart_disable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
         system_interrupt_disable(uart->vector);
         /* Wait for the synchronization to complete */
-	    _usart_wait_for_sync(uart->instance);
+        _usart_wait_for_sync(uart->instance);
         break;
         /* enable interrupt */
     case RT_DEVICE_CTRL_SET_INT:
@@ -158,7 +159,7 @@ static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
         usart_enable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
         system_interrupt_enable(uart->vector);
         /* Wait for the synchronization to complete */
-	    _usart_wait_for_sync(uart->instance);
+        _usart_wait_for_sync(uart->instance);
         break;
 
     default:
@@ -174,16 +175,18 @@ static int _uart_putc(struct rt_serial_device *serial, char c)
 
     RT_ASSERT(serial != RT_NULL);
 
-    // while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
-    // }
+    /* while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE))*/
+    {
+    /* }*/
 
     uart = (SAMD2x_UART_T *)(serial->parent.user_data);
 
-	/* Write data to USART module */
-	uart->com->USART.DATA.reg = c;
+    /* Write data to USART module */
+    uart->com->USART.DATA.reg = c;
 
-	while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
-		/* Wait until data is sent */
+    while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC))
+    {
+        /* Wait until data is sent */
     }
 
     return 1;
@@ -199,9 +202,10 @@ static int _uart_getc(struct rt_serial_device *serial)
     uart = (SAMD2x_UART_T *)(serial->parent.user_data);
 
     /* Check if USART has new data */
-	if (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
-		/* Return error code */
-		return -1;
+    if (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC))
+    {
+        /* Return error code */
+        return -1;
     }
 
     ch = uart->com->USART.DATA.reg & 0x1FF;
@@ -219,54 +223,63 @@ static struct rt_uart_ops _uart_ops = {
 static void uart_int_cb(SAMD2x_UART_T *uart_handle)
 {
     /* Temporary variables */
-	uint16_t interrupt_status;
-	uint8_t error_code;
+    uint16_t interrupt_status;
+    uint8_t error_code;
     struct usart_module *module = uart_handle->instance;
-	/* Pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	/* Read and mask interrupt flag register */
-	interrupt_status = usart_hw->INTFLAG.reg;
-	interrupt_status &= usart_hw->INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    interrupt_status = usart_hw->INTFLAG.reg;
+    interrupt_status &= usart_hw->INTENSET.reg;
 
-	/* Check if the Receive Complete interrupt has occurred, and that
-	 * there's more data to receive */
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+    /* Check if the Receive Complete interrupt has occurred, and that
+     * there's more data to receive */
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXC)
+    {
         /* Read out the status code and mask away all but the 4 LSBs*/
         error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
 #if !SAMD20
         /* CTS status should not be considered as an error */
-        if(error_code & SERCOM_USART_STATUS_CTS) {
+        if(error_code & SERCOM_USART_STATUS_CTS)
+        {
             error_code &= ~SERCOM_USART_STATUS_CTS;
         }
 #endif
 #ifdef FEATURE_USART_LIN_MASTER
         /* TXE status should not be considered as an error */
-        if(error_code & SERCOM_USART_STATUS_TXE) {
+        if(error_code & SERCOM_USART_STATUS_TXE)
+        {
             error_code &= ~SERCOM_USART_STATUS_TXE;
         }
 #endif
         /* Check if an error has occurred during the receiving */
-        if (error_code) {
+        if (error_code)
+        {
             /* Check which error occurred */
-            if (error_code & SERCOM_USART_STATUS_FERR) {
+            if (error_code & SERCOM_USART_STATUS_FERR)
+            {
                 /* clear flag by writing 1 to it */
                 usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-            } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+            } else if (error_code & SERCOM_USART_STATUS_BUFOVF)
+            {
                 /* clear flag by writing 1 to it */
                 usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-            } else if (error_code & SERCOM_USART_STATUS_PERR) {
+            } else if (error_code & SERCOM_USART_STATUS_PERR)
+            {
                 /* clear flag by writing 1 to it */
                 usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
             }
 #ifdef FEATURE_USART_LIN_SLAVE
-            else if (error_code & SERCOM_USART_STATUS_ISF) {
+            else if (error_code & SERCOM_USART_STATUS_ISF)
+            {
                 /* clear flag by writing 1 to it */
                 usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
             }
 #endif
 #ifdef FEATURE_USART_COLLISION_DECTION
-            else if (error_code & SERCOM_USART_STATUS_COLL) {
+            else if (error_code & SERCOM_USART_STATUS_COLL)
+            {
                 /* clear flag by writing 1 to it */
                 usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
             }
@@ -274,33 +287,36 @@ static void uart_int_cb(SAMD2x_UART_T *uart_handle)
         } else {
             rt_hw_serial_isr(uart_handle->serial, RT_SERIAL_EVENT_RX_IND);
         }
-	}
+    }
 
 #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+    }
 #endif
 
 #ifdef FEATURE_USART_LIN_SLAVE
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+    }
 #endif
 
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXS)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+    }
 #endif
 }
 
diff --git a/bsp/samd21/rtconfig.h b/bsp/samd21/rtconfig.h
index 50852b6dac0a..0e869c067d59 100644
--- a/bsp/samd21/rtconfig.h
+++ b/bsp/samd21/rtconfig.h
@@ -3,34 +3,34 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	   6
+#define RT_NAME_MAX    6
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	8
+#define RT_ALIGN_SIZE   8
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	8
+#define RT_THREAD_PRIORITY_MAX  8
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	200
+#define RT_TICK_PER_SECOND  200
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
-//#define RT_DEBUG_INIT 1
+/*#define RT_DEBUG_INIT 1*/
 #define RT_USING_OVERFLOW_CHECK
 
 /* Using Hook */
 #define RT_USING_HOOK
 
-#define IDLE_THREAD_STACK_SIZE	512
+#define IDLE_THREAD_STACK_SIZE  512
 
 /* Using Software Timer */
 /* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO		4
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	100
+#define RT_TIMER_THREAD_PRIO        4
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    100
 
 /* SECTION: IPC */
 /* Using Semaphore*/
@@ -59,38 +59,38 @@
 #define RT_USING_SMALL_MEM
 #define RT_USING_TINY_SIZE
 
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-//#define RT_USING_COMPONENTS_INIT
+/* <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />*/
+/*#define RT_USING_COMPONENTS_INIT*/
 
 /* SECTION: Device System */
 /* Using Device System */
 #define RT_USING_DEVICE
-// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+/* <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />*/
 #define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+/* <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />*/
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
 
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
-#define RT_CONSOLE_DEVICE_NAME	    "uart3"
+#define RT_CONSOLEBUF_SIZE  128
+/* <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />*/
+#define RT_CONSOLE_DEVICE_NAME      "uart3"
 
-// #define RT_USING_SPI
+/* #define RT_USING_SPI*/
 
 /* SECTION: finsh, a C-Express shell */
-// #define RT_USING_FINSH
+/* #define RT_USING_FINSH*/
 /* configure finsh parameters */
 #define FINSH_THREAD_PRIORITY 6
-#define FINSH_THREAD_STACK_SIZE	512
-#define FINSH_HISTORY_LINES	1
+#define FINSH_THREAD_STACK_SIZE 512
+#define FINSH_HISTORY_LINES 1
 /* Using symbol table */
-// #define FINSH_USING_SYMTAB
-// #define FINSH_USING_DESCRIPTION
+/* #define FINSH_USING_SYMTAB*/
+/* #define FINSH_USING_DESCRIPTION*/
 
-// #define FINSH_USING_MSH
-// #define FINSH_USING_MSH_ONLY
+/* #define FINSH_USING_MSH*/
+/* #define FINSH_USING_MSH_ONLY*/
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h
index 76aadca49019..e5bb4a679915 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h
@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        31. July 2014
-* $Revision: 	V1.4.4
+* $Revision:    V1.4.4
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_common_tables.h
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
 *
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
 *
 * Target Processor: Cortex-M4/Cortex-M3
 *
@@ -46,8 +46,8 @@
 extern const uint16_t armBitRevTable[1024];
 extern const q15_t armRecipTableQ15[64];
 extern const q31_t armRecipTableQ31[64];
-//extern const q31_t realCoefAQ31[1024];
-//extern const q31_t realCoefBQ31[1024];
+/*extern const q31_t realCoefAQ31[1024];*/
+/*extern const q31_t realCoefBQ31[1024];*/
 extern const float32_t twiddleCoef_16[32];
 extern const float32_t twiddleCoef_32[64];
 extern const float32_t twiddleCoef_64[128];
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h
index 217f1d50e260..ac4b8618ca0d 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h
@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        31. July 2014
-* $Revision: 	V1.4.4
+* $Revision:    V1.4.4
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_const_structs.h
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
 *
-* Description:	This file has constant structs that are initialized for
+* Description:  This file has constant structs that are initialized for
 *              user convenience.  For example, some can be given as
 *              arguments to the arm_cfft_f32() function.
 *
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h
index f06a0713eb80..a93897d4dd85 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_math.h
@@ -2,12 +2,12 @@
 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
 *
 * $Date:        12. March 2014
-* $Revision: 	V1.4.4
+* $Revision:    V1.4.4
 *
-* Project: 	    CMSIS DSP Library
-* Title:	    arm_math.h
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
 *
-* Description:	Public header file for CMSIS DSP Library
+* Description:  Public header file for CMSIS DSP Library
 *
 * Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
 *
@@ -134,7 +134,7 @@
    * <hr>
    * CMSIS-DSP in ARM::CMSIS Pack
    * -----------------------------
-   * 
+   *
    * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
    * |File/Folder                   |Content                                                                 |
    * |------------------------------|------------------------------------------------------------------------|
@@ -142,7 +142,7 @@
    * |\b CMSIS\\DSP_Lib             | Software license agreement (license.txt)                               |
    * |\b CMSIS\\DSP_Lib\\Examples   | Example projects demonstrating the usage of the library functions      |
    * |\b CMSIS\\DSP_Lib\\Source     | Source files for rebuilding the library                                |
-   * 
+   *
    * <hr>
    * Revision History of CMSIS-DSP
    * ------------
@@ -302,7 +302,7 @@
 #undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
 #include "string.h"
 #include "math.h"
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 extern "C"
 {
 #endif
@@ -312,11 +312,11 @@ extern "C"
    * @brief Macros required for reciprocal calculation in Normalized LMS
    */
 
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
+#define DELTA_Q31           (0x100)
+#define DELTA_Q15           0x5
+#define INDEX_MASK          0x0000003F
 #ifndef PI
-#define PI					3.14159265358979f
+#define PI                  3.14159265358979f
 #endif
 
   /**
@@ -328,15 +328,15 @@ extern "C"
 #define FAST_MATH_Q15_SHIFT   (16 - 10)
 #define CONTROLLER_Q31_SHIFT  (32 - 9)
 #define TABLE_SIZE  256
-#define TABLE_SPACING_Q31	   0x400000
-#define TABLE_SPACING_Q15	   0x80
+#define TABLE_SPACING_Q31      0x400000
+#define TABLE_SPACING_Q15      0x80
 
   /**
    * @brief Macros required for SINE and COSINE Controller functions
    */
   /* 1.31(q31) Fixed value of 2/360 */
   /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
+#define INPUT_SPACING           0xB60B61
 
   /**
    * @brief Macro for Unaligned Support
@@ -349,7 +349,7 @@ extern "C"
   #else
     #define ALIGN4 __align(4)
   #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+#endif  /*  #ifndef UNALIGNED_SUPPORT_DISABLE   */
 
   /**
    * @brief Error status returned by some functions in the library.
@@ -408,7 +408,7 @@ extern "C"
 #elif defined __GNUC__
 #define __SIMD32_TYPE int32_t
 #define CMSIS_UNUSED __attribute__((unused))
-#elif defined __CSMC__			/* Cosmic */
+#elif defined __CSMC__          /* Cosmic */
 #define CMSIS_UNUSED
 #define __SIMD32_TYPE int32_t
 #else
@@ -439,16 +439,16 @@ extern "C"
    */
 #ifndef ARM_MATH_BIG_ENDIAN
 
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
 #else
 
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \
+                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
 
 #endif
 
@@ -574,7 +574,7 @@ extern "C"
       tempVal = (q31_t) (((q63_t) in * out) >> 31u);
       tempVal = 0x7FFFFFFF - tempVal;
       /*      1.31 with exp 1 */
-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      /*out = (q31_t) (((q63_t) out * tempVal) >> 30u);*/
       out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
     }
 
@@ -1214,11 +1214,11 @@ extern "C"
   /**
    * @brief  Initialization function for the Q31 FIR filter.
    * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
    */
   void arm_fir_init_q31(
   arm_fir_instance_q31 * S,
@@ -1244,11 +1244,11 @@ extern "C"
   /**
    * @brief  Initialization function for the floating-point FIR filter.
    * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
+   * @param[in]     numTaps  Number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs points to the filter coefficients.
+   * @param[in]     *pState points to the state buffer.
+   * @param[in]     blockSize number of samples that are processed at a time.
+   * @return        none.
    */
   void arm_fir_init_f32(
   arm_fir_instance_f32 * S,
@@ -1563,7 +1563,7 @@ extern "C"
    * @brief Floating-point matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
 
@@ -1576,7 +1576,7 @@ extern "C"
    * @brief Q15 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
 
@@ -1588,7 +1588,7 @@ extern "C"
    * @brief Q31 matrix transpose.
    * @param[in]  *pSrc points to the input matrix
    * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
    * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
 
@@ -1616,7 +1616,7 @@ extern "C"
    * @param[in]       *pSrcA points to the first input matrix structure
    * @param[in]       *pSrcB points to the second input matrix structure
    * @param[out]      *pDst points to output matrix structure
-   * @param[in]		 *pState points to the array for storing intermediate results
+   * @param[in]      *pState points to the array for storing intermediate results
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
@@ -1632,7 +1632,7 @@ extern "C"
    * @param[in]       *pSrcA  points to the first input matrix structure
    * @param[in]       *pSrcB  points to the second input matrix structure
    * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results
+   * @param[in]       *pState points to the array for storing intermediate results
    * @return     The function returns either
    * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
    */
@@ -1766,7 +1766,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -1781,7 +1781,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -1796,7 +1796,7 @@ extern "C"
    * @param[in,out] *S             points to an instance of the floating-point matrix structure.
    * @param[in]     nRows          number of rows in the matrix.
    * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
+   * @param[in]     *pData         points to the matrix data array.
    * @return        none
    */
 
@@ -2214,11 +2214,11 @@ extern "C"
     uint16_t bitRevLength;             /**< bit reversal table length. */
   } arm_cfft_instance_q15;
 
-void arm_cfft_q15( 
-    const arm_cfft_instance_q15 * S, 
+void arm_cfft_q15(
+    const arm_cfft_instance_q15 * S,
     q15_t * p1,
     uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
+    uint8_t bitReverseFlag);
 
   /**
    * @brief Instance structure for the fixed-point CFFT/CIFFT function.
@@ -2232,12 +2232,12 @@ void arm_cfft_q15(
     uint16_t bitRevLength;             /**< bit reversal table length. */
   } arm_cfft_instance_q31;
 
-void arm_cfft_q31( 
-    const arm_cfft_instance_q31 * S, 
+void arm_cfft_q31(
+    const arm_cfft_instance_q31 * S,
     q31_t * p1,
     uint8_t ifftFlag,
-    uint8_t bitReverseFlag);  
-  
+    uint8_t bitReverseFlag);
+
   /**
    * @brief Instance structure for the floating-point CFFT/CIFFT function.
    */
@@ -2344,12 +2344,12 @@ typedef struct
   {
     arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
     uint16_t fftLenRFFT;                        /**< length of the real sequence */
-	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+    float32_t * pTwiddleRFFT;                   /**< Twiddle factors real stage  */
   } arm_rfft_fast_instance_f32 ;
 
 arm_status arm_rfft_fast_init_f32 (
-	arm_rfft_fast_instance_f32 * S,
-	uint16_t fftLen);
+    arm_rfft_fast_instance_f32 * S,
+    uint16_t fftLen);
 
 void arm_rfft_fast_f32(
   arm_rfft_fast_instance_f32 * S,
@@ -2379,7 +2379,7 @@ void arm_rfft_fast_f32(
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
    */
 
   arm_status arm_dct4_init_f32(
@@ -2426,7 +2426,7 @@ void arm_rfft_fast_f32(
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
    */
 
   arm_status arm_dct4_init_q31(
@@ -2473,7 +2473,7 @@ void arm_rfft_fast_f32(
    * @param[in]     N          length of the DCT4.
    * @param[in]     Nby2       half of the length of the DCT4.
    * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
    */
 
   arm_status arm_dct4_init_q15(
@@ -3115,11 +3115,11 @@ void arm_rfft_fast_f32(
    */
 
   void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
+              q15_t * pSrcA,
+             uint32_t srcALen,
+              q15_t * pSrcB,
+             uint32_t srcBLen,
+             q15_t * pDst);
 
   /**
    * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
@@ -3301,13 +3301,13 @@ void arm_rfft_fast_f32(
    */
 
   arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
+                        q15_t * pSrcA,
+                       uint32_t srcALen,
+                        q15_t * pSrcB,
+                       uint32_t srcBLen,
+                       q15_t * pDst,
+                       uint32_t firstIndex,
+                       uint32_t numPoints);
 
 
   /**
@@ -4587,11 +4587,11 @@ void arm_rfft_fast_f32(
    */
 
   void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
+                   q15_t * pSrcA,
+                  uint32_t srcALen,
+                   q15_t * pSrcB,
+                  uint32_t srcBLen,
+                  q15_t * pDst);
 
 
 
@@ -5498,8 +5498,8 @@ void arm_rfft_fast_f32(
    * @brief Floating-point Park transform
    * @param[in]       Ialpha input two-phase vector coordinate alpha
    * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[out]      *pId   points to output   rotor reference frame d
+   * @param[out]      *pIq   points to output   rotor reference frame q
    * @param[in]       sinVal sine value of rotation angle theta
    * @param[in]       cosVal cosine value of rotation angle theta
    * @return none.
@@ -5645,7 +5645,7 @@ void arm_rfft_fast_f32(
 
 
   /**
-   * @brief  Inverse Park transform for	Q31 version
+   * @brief  Inverse Park transform for Q31 version
    * @param[in]       Id        input coordinate of rotor reference frame d
    * @param[in]       Iq        input coordinate of rotor reference frame q
    * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
@@ -6093,7 +6093,7 @@ void arm_rfft_fast_f32(
     if(in > 0)
     {
 
-//      #if __FPU_USED
+/*      #if __FPU_USED*/
 #if (__FPU_USED == 1) && defined ( __CC_ARM   )
       *pOut = __sqrtf(in);
 #else
@@ -7429,80 +7429,80 @@ void arm_rfft_fast_f32(
   /**
    * @} end of BilinearInterpolate group
    */
-   
 
-//SMMLAR
+
+/*SMMLAR*/
 #define multAcc_32x32_keep32_R(a, x, y) \
     a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
 
-//SMMLSR
+/*SMMLSR*/
 #define multSub_32x32_keep32_R(a, x, y) \
     a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
 
-//SMMULR
+/*SMMULR*/
 #define mult_32x32_keep32_R(a, x, y) \
     a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
 
-//SMMLA
+/*SMMLA*/
 #define multAcc_32x32_keep32(a, x, y) \
     a += (q31_t) (((q63_t) x * y) >> 32)
 
-//SMMLS
+/*SMMLS*/
 #define multSub_32x32_keep32(a, x, y) \
     a -= (q31_t) (((q63_t) x * y) >> 32)
 
-//SMMUL
+/*SMMUL*/
 #define mult_32x32_keep32(a, x, y) \
     a = (q31_t) (((q63_t) x * y ) >> 32)
 
 
-#if defined ( __CC_ARM ) //Keil
+#if defined ( __CC_ARM ) /*Keil*/
 
-//Enter low optimization region - place directly above function definition
+/*Enter low optimization region - place directly above function definition*/
     #ifdef ARM_MATH_CM4
       #define LOW_OPTIMIZATION_ENTER \
          _Pragma ("push")         \
          _Pragma ("O1")
     #else
-      #define LOW_OPTIMIZATION_ENTER 
+      #define LOW_OPTIMIZATION_ENTER
     #endif
 
-//Exit low optimization region - place directly after end of function definition
+/*Exit low optimization region - place directly after end of function definition*/
     #ifdef ARM_MATH_CM4
       #define LOW_OPTIMIZATION_EXIT \
          _Pragma ("pop")
     #else
-      #define LOW_OPTIMIZATION_EXIT  
+      #define LOW_OPTIMIZATION_EXIT
     #endif
 
-//Enter low optimization region - place directly above function definition
+/*Enter low optimization region - place directly above function definition*/
   #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
 
-//Exit low optimization region - place directly after end of function definition
+/*Exit low optimization region - place directly after end of function definition*/
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 
-#elif defined(__ICCARM__) //IAR
+#elif defined(__ICCARM__) /*IAR*/
 
-//Enter low optimization region - place directly above function definition
+/*Enter low optimization region - place directly above function definition*/
     #ifdef ARM_MATH_CM4
       #define LOW_OPTIMIZATION_ENTER \
          _Pragma ("optimize=low")
     #else
-      #define LOW_OPTIMIZATION_ENTER   
+      #define LOW_OPTIMIZATION_ENTER
     #endif
 
-//Exit low optimization region - place directly after end of function definition
+/*Exit low optimization region - place directly after end of function definition*/
   #define LOW_OPTIMIZATION_EXIT
 
-//Enter low optimization region - place directly above function definition
+/*Enter low optimization region - place directly above function definition*/
     #ifdef ARM_MATH_CM4
       #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
          _Pragma ("optimize=low")
     #else
-      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER   
+      #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
     #endif
 
-//Exit low optimization region - place directly after end of function definition
+/*Exit low optimization region - place directly after end of function definition*/
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 
 #elif defined(__GNUC__)
@@ -7515,7 +7515,7 @@ void arm_rfft_fast_f32(
 
   #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
 
-#elif defined(__CSMC__)		// Cosmic
+#elif defined(__CSMC__)     /* Cosmic*/
 
 #define LOW_OPTIMIZATION_ENTER
 #define LOW_OPTIMIZATION_EXIT
@@ -7525,7 +7525,7 @@ void arm_rfft_fast_f32(
 #endif
 
 
-#ifdef	__cplusplus
+#ifdef  __cplusplus
 }
 #endif
 
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h
index 5186cb483882..57f469e64fa7 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0.h
@@ -138,8 +138,8 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
@@ -610,7 +610,8 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
@@ -633,7 +634,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h
index 17e43984fcf9..cd239afd9e37 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm0plus.h
@@ -138,8 +138,8 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
@@ -721,7 +721,8 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
@@ -744,7 +745,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h
index e1357c6735b0..9184ffc89dcd 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm3.h
@@ -138,8 +138,8 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
@@ -1424,7 +1424,8 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
@@ -1445,7 +1446,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
@@ -1608,10 +1610,12 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
     \return             Received character.
     \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1627,9 +1631,11 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
     \return          0  No character available.
     \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h
index bb6be1305d27..50dd8421b15a 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm4.h
@@ -171,8 +171,8 @@
     #define __FPU_USED         0
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
@@ -1576,7 +1576,8 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
@@ -1597,7 +1598,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
@@ -1760,10 +1762,12 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
     \return             Received character.
     \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1779,9 +1783,11 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
     \return          0  No character available.
     \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h
index e21e9e29fc4e..69a829a5dff2 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cm7.h
@@ -171,8 +171,8 @@
     #define __FPU_USED         0
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #if (__FPU_PRESENT == 1)
       #define __FPU_USED       1
     #else
@@ -1763,7 +1763,8 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)]            = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts  */
@@ -1784,7 +1785,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]            >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
@@ -1885,8 +1887,8 @@ __STATIC_INLINE void SCB_EnableICache(void)
   #if (__ICACHE_PRESENT == 1)
     __DSB();
     __ISB();
-    SCB->ICIALLU = 0;                       // invalidate I-Cache
-    SCB->CCR |=  SCB_CCR_IC_Msk;            // enable I-Cache
+    SCB->ICIALLU = 0;                       /* invalidate I-Cache*/
+    SCB->CCR |=  SCB_CCR_IC_Msk;            /* enable I-Cache*/
     __DSB();
     __ISB();
   #endif
@@ -1902,8 +1904,8 @@ __STATIC_INLINE void SCB_DisableICache(void)
   #if (__ICACHE_PRESENT == 1)
     __DSB();
     __ISB();
-    SCB->CCR &= ~SCB_CCR_IC_Msk;            // disable I-Cache
-    SCB->ICIALLU = 0;                       // invalidate I-Cache
+    SCB->CCR &= ~SCB_CCR_IC_Msk;            /* disable I-Cache*/
+    SCB->ICIALLU = 0;                       /* invalidate I-Cache*/
     __DSB();
     __ISB();
   #endif
@@ -1944,7 +1946,7 @@ __STATIC_INLINE void SCB_EnableDCache(void)
 
     __DSB();
 
-    do {                                    // invalidate D-Cache
+    do {                                    /* invalidate D-Cache*/
          int32_t tmpways = ways;
          do {
               sw = ((tmpways << wshift) | (sets << sshift));
@@ -1953,7 +1955,7 @@ __STATIC_INLINE void SCB_EnableDCache(void)
         } while(sets--);
     __DSB();
 
-    SCB->CCR |=  SCB_CCR_DC_Msk;            // enable D-Cache
+    SCB->CCR |=  SCB_CCR_DC_Msk;            /* enable D-Cache*/
 
     __DSB();
     __ISB();
@@ -1979,9 +1981,9 @@ __STATIC_INLINE void SCB_DisableDCache(void)
 
     __DSB();
 
-    SCB->CCR &= ~SCB_CCR_DC_Msk;            // disable D-Cache
+    SCB->CCR &= ~SCB_CCR_DC_Msk;            /* disable D-Cache*/
 
-    do {                                    // clean & invalidate D-Cache
+    do {                                    /* clean & invalidate D-Cache*/
          int32_t tmpways = ways;
          do {
               sw = ((tmpways << wshift) | (sets << sshift));
@@ -2014,7 +2016,7 @@ __STATIC_INLINE void SCB_InvalidateDCache(void)
 
     __DSB();
 
-    do {                                    // invalidate D-Cache
+    do {                                    /* invalidate D-Cache*/
          int32_t tmpways = ways;
          do {
               sw = ((tmpways << wshift) | (sets << sshift));
@@ -2046,7 +2048,7 @@ __STATIC_INLINE void SCB_CleanDCache(void)
 
     __DSB();
 
-    do {                                    // clean D-Cache
+    do {                                    /* clean D-Cache*/
          int32_t tmpways = ways;
          do {
               sw = ((tmpways << wshift) | (sets << sshift));
@@ -2078,7 +2080,7 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void)
 
     __DSB();
 
-    do {                                    // clean & invalidate D-Cache
+    do {                                    /* clean & invalidate D-Cache*/
          int32_t tmpways = ways;
          do {
               sw = ((tmpways << wshift) | (sets << sshift));
@@ -2179,10 +2181,12 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
     \return             Received character.
     \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -2198,9 +2202,11 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
     \return          0  No character available.
     \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h
index 2e3bb0eabb93..28e8e23a4ecf 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmInstr.h
@@ -523,7 +523,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
  */
 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
 {
-  return (op1 >> op2) | (op1 << (32 - op2)); 
+  return (op1 >> op2) | (op1 << (32 - op2));
 }
 
 
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h
index ee58eee56dd7..e8a0d301c971 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmSimd.h
@@ -524,9 +524,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t o
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian*/
   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian*/
   __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -541,9 +541,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian*/
   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian*/
   __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -590,9 +590,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t o
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian*/
   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian*/
   __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
@@ -607,9 +607,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t
   } llr;
   llr.w64 = acc;
 
-#ifndef __ARMEB__   // Little endian
+#ifndef __ARMEB__   /* Little endian*/
   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               // Big endian
+#else               /* Big endian*/
   __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
 #endif
 
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h
index 5d0219c89f4b..883926a31174 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc000.h
@@ -138,8 +138,8 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
@@ -741,7 +741,8 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
         (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
   else {
@@ -764,7 +765,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
   else {
     return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
diff --git a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h
index b6f6e8b5f2d8..77826c0b2014 100644
--- a/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h
+++ b/bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_sc300.h
@@ -138,8 +138,8 @@
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
+#elif defined ( __CSMC__ )      /* Cosmic */
+  #if ( __CSMC__ & 0x400)       /* FPU present for parser*/
     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #endif
@@ -1404,7 +1404,8 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
  */
 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
@@ -1425,7 +1426,8 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {
 
-  if(IRQn < 0) {
+  if(IRQn < 0)
+  {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
@@ -1588,10 +1590,12 @@ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
     \return             Received character.
     \return         -1  No character pending.
  */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
   int32_t ch = -1;                           /* no character available */
 
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
@@ -1607,9 +1611,11 @@ __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
     \return          0  No character available.
     \return          1  Character available.
  */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
 
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/board.h b/bsp/samd21/sam_d2x_asflib/common/boards/board.h
index 0dc09cd1b683..2c649abdfa6d 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/board.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/board.h
@@ -68,121 +68,121 @@ extern "C" {
 
 /*! \name Base Boards
  */
-//! @{
-#define EVK1100                     1  //!< AT32UC3A EVK1100 board.
-#define EVK1101                     2  //!< AT32UC3B EVK1101 board.
-#define UC3C_EK                     3  //!< AT32UC3C UC3C-EK board.
-#define EVK1104                     4  //!< AT32UC3A3 EVK1104 board.
-#define EVK1105                     5  //!< AT32UC3A EVK1105 board.
-#define STK600_RCUC3L0              6  //!< STK600 RCUC3L0 board.
-#define UC3L_EK                     7  //!< AT32UC3L-EK board.
-#define XPLAIN                      8  //!< ATxmega128A1 Xplain board.
-#define STK600_RC064X              10  //!< ATxmega256A3 STK600 board.
-#define STK600_RC100X              11  //!< ATxmega128A1 STK600 board.
-#define UC3_A3_XPLAINED            13  //!< ATUC3A3 UC3-A3 Xplained board.
-#define UC3_L0_XPLAINED            15  //!< ATUC3L0 UC3-L0 Xplained board.
-#define STK600_RCUC3D              16  //!< STK600 RCUC3D board.
-#define STK600_RCUC3C0             17  //!< STK600 RCUC3C board.
-#define XMEGA_B1_XPLAINED          18  //!< ATxmega128B1 Xplained board.
-#define XMEGA_A1_XPLAINED          19  //!< ATxmega128A1 Xplain-A1 board.
-#define XMEGA_A1U_XPLAINED_PRO     20  //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
-#define STK600_RCUC3L4             21  //!< ATUCL4 STK600 board.
-#define UC3_L0_XPLAINED_BC         22  //!< ATUC3L0 UC3-L0 Xplained board controller board.
-#define MEGA1284P_XPLAINED_BC      23  //!< ATmega1284P-Xplained board controller board.
-#define STK600_RC044X              24  //!< STK600 with RC044X routing card board.
-#define STK600_RCUC3B0             25  //!< STK600 RCUC3B0 board.
-#define UC3_L0_QT600               26  //!< QT600 UC3L0 MCU board.
-#define XMEGA_A3BU_XPLAINED        27  //!< ATxmega256A3BU Xplained board.
-#define STK600_RC064X_LCDX         28  //!< XMEGAB3 STK600 RC064X LCDX board.
-#define STK600_RC100X_LCDX         29  //!< XMEGAB1 STK600 RC100X LCDX board.
-#define UC3B_BOARD_CONTROLLER      30  //!< AT32UC3B1 board controller for Atmel boards.
-#define RZ600                      31  //!< AT32UC3A RZ600 MCU board.
-#define SAM3S_EK                   32  //!< SAM3S-EK board.
-#define SAM3U_EK                   33  //!< SAM3U-EK board.
-#define SAM3X_EK                   34  //!< SAM3X-EK board.
-#define SAM3N_EK                   35  //!< SAM3N-EK board.
-#define SAM3S_EK2                  36  //!< SAM3S-EK2 board.
-#define SAM4S_EK                   37  //!< SAM4S-EK board.
-#define STK600_RCUC3A0             38  //!< STK600 RCUC3A0 board.
-#define STK600_MEGA                39  //!< STK600 MEGA board.
-#define MEGA_1284P_XPLAINED        40  //!< ATmega1284P Xplained board.
-#define SAM4S_XPLAINED             41  //!< SAM4S Xplained board.
-#define ATXMEGA128A1_QT600         42  //!< QT600 ATXMEGA128A1 MCU board.
-#define ARDUINO_DUE_X              43  //!< Arduino Due/X board.
-#define STK600_RCUC3L3             44  //!< ATUCL3 STK600 board.
-#define SAM4L_EK                   45  //!< SAM4L-EK board.
-#define STK600_MEGA_RF             46  //!< STK600 MEGA RF EVK board.
-#define XMEGA_C3_XPLAINED          47  //!< ATxmega384C3 Xplained board.
-#define STK600_RC032X              48  //!< STK600 with RC032X routing card board.
-#define SAM4S_EK2                  49  //!< SAM4S-EK2 board.
-#define XMEGA_E5_XPLAINED          50  //!< ATxmega32E5 Xplained board.
-#define SAM4E_EK                   51  //!< SAM4E-EK board.
-#define ATMEGA256RFR2_XPLAINED_PRO 52  //!< ATmega256RFR2 Xplained Pro board.
-#define SAM4S_XPLAINED_PRO         53  //!< SAM4S Xplained Pro board.
-#define SAM4L_XPLAINED_PRO         54  //!< SAM4L Xplained Pro board.
-#define ATMEGA256RFR2_ZIGBIT       55  //!< ATmega256RFR2 zigbit.
-#define XMEGA_RF233_ZIGBIT         56  //!< ATxmega256A3U with AT86RF233 Zigbit.
-#define XMEGA_RF212B_ZIGBIT        57  //!< ATxmega256A3U with AT86RF212B Zigbit.
-#define SAM4S_WPIR_RD              58  //!< SAM4S-WPIR-RD board.
-#define SAMD20_XPLAINED_PRO        59  //!< SAM D20 Xplained Pro board.
-#define SAM4L8_XPLAINED_PRO        60  //!< SAM4L8 Xplained Pro board.
-#define SAM4N_XPLAINED_PRO         61  //!< SAM4N Xplained Pro board.
-#define XMEGA_A3_REB_CBB           62  //!< XMEGA REB Controller Base board.
-#define ATMEGARFX_RCB              63  //!< RFR2 & RFA1 RCB.
-#define SAM4C_EK                   64  //!< SAM4C-EK board.
-#define RCB256RFR2_XPRO            65  //!< RFR2 RCB Xplained Pro board.
-#define SAMG53_XPLAINED_PRO        66  //!< SAMG53 Xplained Pro board.
-#define SAM4CP16BMB                67  //!< SAM4CP16BMB board.
-#define SAM4E_XPLAINED_PRO         68  //!< SAM4E Xplained Pro board.
-#define SAMD21_XPLAINED_PRO        69  //!< SAM D21 Xplained Pro board.
-#define SAMR21_XPLAINED_PRO        70  //!< SAM R21 Xplained Pro board.
-#define SAM4CMP_DB                 71  //!< SAM4CMP demo board.
-#define SAM4CMS_DB                 72  //!< SAM4CMS demo board.
-#define ATPL230AMB                 73  //!< ATPL230AMB board.
-#define SAMD11_XPLAINED_PRO        74  //!< SAM D11 Xplained Pro board.
-#define SAMG55_XPLAINED_PRO        75  //!< SAMG55 Xplained Pro board.
-#define SAML21_XPLAINED_PRO        76  //!< SAM L21 Xplained Pro board.
-#define SAMD10_XPLAINED_MINI       77  //!< SAM D10 Xplained Mini board.
-#define SAMDA1_XPLAINED_PRO        78  //!< SAM DA1 Xplained Pro board.
-#define SAMW25_XPLAINED_PRO        79  //!< SAMW25 Xplained Pro board.
-#define SAMC21_XPLAINED_PRO        80  //!< SAM C21 Xplained Pro board.
-#define SAMV71_XPLAINED_ULTRA      81  //!< SAMV71 Xplained Ultra board.
-#define ATMEGA328P_XPLAINED_MINI   82  //!< ATMEGA328P Xplained MINI board.
-#define ATMEGA328PB_XPLAINED_MINI  83  //!< ATMEGA328PB Xplained MINI board.
-#define SAMB11_XPLAINED_PRO        84  //!< SAM B11 Xplained Pro board.
-#define SAME70_XPLAINED            85  //!< SAME70 Xplained board.
-#define SAML22_XPLAINED_PRO        86  //!< SAM L22 Xplained Pro board.
-#define SAML22_XPLAINED_PRO_B      87  //!< SAM L22 Xplained Pro board.
-#define SAMR21ZLL_EK               88  //!< SAMR21ZLL-EK board.
-#define ATMEGA168PB_XPLAINED_MINI  89  //!< ATMEGA168PB Xplained MINI board.
-#define ATMEGA324PB_XPLAINED_PRO   90  //!< ATMEGA324PB Xplained Pro board.
-#define SAMB11CSP_XPLAINED_PRO     91  //!< SAM B11 CSP Xplained Pro board.
-#define SAMB11ZR_XPLAINED_PRO      92  //!< SAM B11 ZR Xplained Pro board.
-#define SAMR30_XPLAINED_PRO        93  //!< SAM R30 Xplained Pro board.
-#define SAMHA1G16A_XPLAINED_PRO    94  //!< SAM HA1G16A Xplained Pro board.
-#define SIMULATOR_XMEGA_A1         97  //!< Simulator for XMEGA A1 devices.
-#define AVR_SIMULATOR_UC3          98  //!< Simulator for the AVR UC3 device family.
-#define USER_BOARD                 99  //!< User-reserved board (if any).
-#define DUMMY_BOARD               100  //!< Dummy board to support board-independent applications (e.g. bootloader).
-//! @}
+/*! @{*/
+#define EVK1100                     1  /*!< AT32UC3A EVK1100 board.*/
+#define EVK1101                     2  /*!< AT32UC3B EVK1101 board.*/
+#define UC3C_EK                     3  /*!< AT32UC3C UC3C-EK board.*/
+#define EVK1104                     4  /*!< AT32UC3A3 EVK1104 board.*/
+#define EVK1105                     5  /*!< AT32UC3A EVK1105 board.*/
+#define STK600_RCUC3L0              6  /*!< STK600 RCUC3L0 board.*/
+#define UC3L_EK                     7  /*!< AT32UC3L-EK board.*/
+#define XPLAIN                      8  /*!< ATxmega128A1 Xplain board.*/
+#define STK600_RC064X              10  /*!< ATxmega256A3 STK600 board.*/
+#define STK600_RC100X              11  /*!< ATxmega128A1 STK600 board.*/
+#define UC3_A3_XPLAINED            13  /*!< ATUC3A3 UC3-A3 Xplained board.*/
+#define UC3_L0_XPLAINED            15  /*!< ATUC3L0 UC3-L0 Xplained board.*/
+#define STK600_RCUC3D              16  /*!< STK600 RCUC3D board.*/
+#define STK600_RCUC3C0             17  /*!< STK600 RCUC3C board.*/
+#define XMEGA_B1_XPLAINED          18  /*!< ATxmega128B1 Xplained board.*/
+#define XMEGA_A1_XPLAINED          19  /*!< ATxmega128A1 Xplain-A1 board.*/
+#define XMEGA_A1U_XPLAINED_PRO     20  /*!< ATxmega128A1U XMEGA-A1U Xplained Pro board.*/
+#define STK600_RCUC3L4             21  /*!< ATUCL4 STK600 board.*/
+#define UC3_L0_XPLAINED_BC         22  /*!< ATUC3L0 UC3-L0 Xplained board controller board.*/
+#define MEGA1284P_XPLAINED_BC      23  /*!< ATmega1284P-Xplained board controller board.*/
+#define STK600_RC044X              24  /*!< STK600 with RC044X routing card board.*/
+#define STK600_RCUC3B0             25  /*!< STK600 RCUC3B0 board.*/
+#define UC3_L0_QT600               26  /*!< QT600 UC3L0 MCU board.*/
+#define XMEGA_A3BU_XPLAINED        27  /*!< ATxmega256A3BU Xplained board.*/
+#define STK600_RC064X_LCDX         28  /*!< XMEGAB3 STK600 RC064X LCDX board.*/
+#define STK600_RC100X_LCDX         29  /*!< XMEGAB1 STK600 RC100X LCDX board.*/
+#define UC3B_BOARD_CONTROLLER      30  /*!< AT32UC3B1 board controller for Atmel boards.*/
+#define RZ600                      31  /*!< AT32UC3A RZ600 MCU board.*/
+#define SAM3S_EK                   32  /*!< SAM3S-EK board.*/
+#define SAM3U_EK                   33  /*!< SAM3U-EK board.*/
+#define SAM3X_EK                   34  /*!< SAM3X-EK board.*/
+#define SAM3N_EK                   35  /*!< SAM3N-EK board.*/
+#define SAM3S_EK2                  36  /*!< SAM3S-EK2 board.*/
+#define SAM4S_EK                   37  /*!< SAM4S-EK board.*/
+#define STK600_RCUC3A0             38  /*!< STK600 RCUC3A0 board.*/
+#define STK600_MEGA                39  /*!< STK600 MEGA board.*/
+#define MEGA_1284P_XPLAINED        40  /*!< ATmega1284P Xplained board.*/
+#define SAM4S_XPLAINED             41  /*!< SAM4S Xplained board.*/
+#define ATXMEGA128A1_QT600         42  /*!< QT600 ATXMEGA128A1 MCU board.*/
+#define ARDUINO_DUE_X              43  /*!< Arduino Due/X board.*/
+#define STK600_RCUC3L3             44  /*!< ATUCL3 STK600 board.*/
+#define SAM4L_EK                   45  /*!< SAM4L-EK board.*/
+#define STK600_MEGA_RF             46  /*!< STK600 MEGA RF EVK board.*/
+#define XMEGA_C3_XPLAINED          47  /*!< ATxmega384C3 Xplained board.*/
+#define STK600_RC032X              48  /*!< STK600 with RC032X routing card board.*/
+#define SAM4S_EK2                  49  /*!< SAM4S-EK2 board.*/
+#define XMEGA_E5_XPLAINED          50  /*!< ATxmega32E5 Xplained board.*/
+#define SAM4E_EK                   51  /*!< SAM4E-EK board.*/
+#define ATMEGA256RFR2_XPLAINED_PRO 52  /*!< ATmega256RFR2 Xplained Pro board.*/
+#define SAM4S_XPLAINED_PRO         53  /*!< SAM4S Xplained Pro board.*/
+#define SAM4L_XPLAINED_PRO         54  /*!< SAM4L Xplained Pro board.*/
+#define ATMEGA256RFR2_ZIGBIT       55  /*!< ATmega256RFR2 zigbit.*/
+#define XMEGA_RF233_ZIGBIT         56  /*!< ATxmega256A3U with AT86RF233 Zigbit.*/
+#define XMEGA_RF212B_ZIGBIT        57  /*!< ATxmega256A3U with AT86RF212B Zigbit.*/
+#define SAM4S_WPIR_RD              58  /*!< SAM4S-WPIR-RD board.*/
+#define SAMD20_XPLAINED_PRO        59  /*!< SAM D20 Xplained Pro board.*/
+#define SAM4L8_XPLAINED_PRO        60  /*!< SAM4L8 Xplained Pro board.*/
+#define SAM4N_XPLAINED_PRO         61  /*!< SAM4N Xplained Pro board.*/
+#define XMEGA_A3_REB_CBB           62  /*!< XMEGA REB Controller Base board.*/
+#define ATMEGARFX_RCB              63  /*!< RFR2 & RFA1 RCB.*/
+#define SAM4C_EK                   64  /*!< SAM4C-EK board.*/
+#define RCB256RFR2_XPRO            65  /*!< RFR2 RCB Xplained Pro board.*/
+#define SAMG53_XPLAINED_PRO        66  /*!< SAMG53 Xplained Pro board.*/
+#define SAM4CP16BMB                67  /*!< SAM4CP16BMB board.*/
+#define SAM4E_XPLAINED_PRO         68  /*!< SAM4E Xplained Pro board.*/
+#define SAMD21_XPLAINED_PRO        69  /*!< SAM D21 Xplained Pro board.*/
+#define SAMR21_XPLAINED_PRO        70  /*!< SAM R21 Xplained Pro board.*/
+#define SAM4CMP_DB                 71  /*!< SAM4CMP demo board.*/
+#define SAM4CMS_DB                 72  /*!< SAM4CMS demo board.*/
+#define ATPL230AMB                 73  /*!< ATPL230AMB board.*/
+#define SAMD11_XPLAINED_PRO        74  /*!< SAM D11 Xplained Pro board.*/
+#define SAMG55_XPLAINED_PRO        75  /*!< SAMG55 Xplained Pro board.*/
+#define SAML21_XPLAINED_PRO        76  /*!< SAM L21 Xplained Pro board.*/
+#define SAMD10_XPLAINED_MINI       77  /*!< SAM D10 Xplained Mini board.*/
+#define SAMDA1_XPLAINED_PRO        78  /*!< SAM DA1 Xplained Pro board.*/
+#define SAMW25_XPLAINED_PRO        79  /*!< SAMW25 Xplained Pro board.*/
+#define SAMC21_XPLAINED_PRO        80  /*!< SAM C21 Xplained Pro board.*/
+#define SAMV71_XPLAINED_ULTRA      81  /*!< SAMV71 Xplained Ultra board.*/
+#define ATMEGA328P_XPLAINED_MINI   82  /*!< ATMEGA328P Xplained MINI board.*/
+#define ATMEGA328PB_XPLAINED_MINI  83  /*!< ATMEGA328PB Xplained MINI board.*/
+#define SAMB11_XPLAINED_PRO        84  /*!< SAM B11 Xplained Pro board.*/
+#define SAME70_XPLAINED            85  /*!< SAME70 Xplained board.*/
+#define SAML22_XPLAINED_PRO        86  /*!< SAM L22 Xplained Pro board.*/
+#define SAML22_XPLAINED_PRO_B      87  /*!< SAM L22 Xplained Pro board.*/
+#define SAMR21ZLL_EK               88  /*!< SAMR21ZLL-EK board.*/
+#define ATMEGA168PB_XPLAINED_MINI  89  /*!< ATMEGA168PB Xplained MINI board.*/
+#define ATMEGA324PB_XPLAINED_PRO   90  /*!< ATMEGA324PB Xplained Pro board.*/
+#define SAMB11CSP_XPLAINED_PRO     91  /*!< SAM B11 CSP Xplained Pro board.*/
+#define SAMB11ZR_XPLAINED_PRO      92  /*!< SAM B11 ZR Xplained Pro board.*/
+#define SAMR30_XPLAINED_PRO        93  /*!< SAM R30 Xplained Pro board.*/
+#define SAMHA1G16A_XPLAINED_PRO    94  /*!< SAM HA1G16A Xplained Pro board.*/
+#define SIMULATOR_XMEGA_A1         97  /*!< Simulator for XMEGA A1 devices.*/
+#define AVR_SIMULATOR_UC3          98  /*!< Simulator for the AVR UC3 device family.*/
+#define USER_BOARD                 99  /*!< User-reserved board (if any).*/
+#define DUMMY_BOARD               100  /*!< Dummy board to support board-independent applications (e.g. bootloader).*/
+/*! @}*/
 
 /*! \name Extension Boards
  */
-//! @{
-#define EXT1102                      1  //!< AT32UC3B EXT1102 board
-#define MC300                        2  //!< AT32UC3 MC300 board
-#define SENSORS_XPLAINED_INERTIAL_1  3  //!< Xplained inertial sensor board 1
-#define SENSORS_XPLAINED_INERTIAL_2  4  //!< Xplained inertial sensor board 2
-#define SENSORS_XPLAINED_PRESSURE_1  5  //!< Xplained pressure sensor board
-#define SENSORS_XPLAINED_LIGHTPROX_1 6  //!< Xplained light & proximity sensor board
-#define SENSORS_XPLAINED_INERTIAL_A1 7  //!< Xplained inertial sensor board "A"
-#define RZ600_AT86RF231              8  //!< AT86RF231 RF board in RZ600
-#define RZ600_AT86RF230B             9  //!< AT86RF230B RF board in RZ600
-#define RZ600_AT86RF212             10  //!< AT86RF212 RF board in RZ600
-#define SENSORS_XPLAINED_BREADBOARD 11  //!< Xplained sensor development breadboard
-#define SECURITY_XPLAINED           12  //!< Xplained ATSHA204 board
-#define USER_EXT_BOARD              99  //!< User-reserved extension board (if any).
-//! @}
+/*! @{*/
+#define EXT1102                      1  /*!< AT32UC3B EXT1102 board*/
+#define MC300                        2  /*!< AT32UC3 MC300 board*/
+#define SENSORS_XPLAINED_INERTIAL_1  3  /*!< Xplained inertial sensor board 1*/
+#define SENSORS_XPLAINED_INERTIAL_2  4  /*!< Xplained inertial sensor board 2*/
+#define SENSORS_XPLAINED_PRESSURE_1  5  /*!< Xplained pressure sensor board*/
+#define SENSORS_XPLAINED_LIGHTPROX_1 6  /*!< Xplained light & proximity sensor board*/
+#define SENSORS_XPLAINED_INERTIAL_A1 7  /*!< Xplained inertial sensor board "A"*/
+#define RZ600_AT86RF231              8  /*!< AT86RF231 RF board in RZ600*/
+#define RZ600_AT86RF230B             9  /*!< AT86RF230B RF board in RZ600*/
+#define RZ600_AT86RF212             10  /*!< AT86RF212 RF board in RZ600*/
+#define SENSORS_XPLAINED_BREADBOARD 11  /*!< Xplained sensor development breadboard*/
+#define SECURITY_XPLAINED           12  /*!< Xplained ATSHA204 board*/
+#define USER_EXT_BOARD              99  /*!< User-reserved extension board (if any).*/
+/*! @}*/
 
 #if BOARD == EVK1100
 #  include "evk1100/evk1100.h"
@@ -383,7 +383,7 @@ extern "C" {
 #elif BOARD == AVR_SIMULATOR_UC3
 #  include "avr_simulator_uc3/avr_simulator_uc3.h"
 #elif BOARD == USER_BOARD
-  // User-reserved area: #include the header file of your board here (if any).
+  /* User-reserved area: #include the header file of your board here (if any).*/
 #  include "user_board.h"
 #elif BOARD == DUMMY_BOARD
 #  include "dummy/dummy_board.h"
@@ -410,14 +410,14 @@ extern "C" {
 #  elif EXT_BOARD == SECURITY_XPLAINED
 #    include "security_xplained.h"
 #  elif EXT_BOARD == USER_EXT_BOARD
-    // User-reserved area: #include the header file of your extension board here
-    // (if any).
+    /* User-reserved area: #include the header file of your extension board here*/
+    /* (if any).*/
 #  endif
 #endif
 
 
 #if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
-#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+#ifdef __AVR32_ABI_COMPILER__ /* Automatically defined when compiling for AVR32, not when assembling.*/
 
 /*! \brief This function initializes the board target resources
  *
@@ -426,7 +426,7 @@ extern "C" {
  */
 extern void board_init(void);
 
-#endif  // #ifdef __AVR32_ABI_COMPILER__
+#endif  /* #ifdef __AVR32_ABI_COMPILER__*/
 #else
 /*! \brief This function initializes the board target resources
  *
@@ -445,4 +445,4 @@ extern void board_init(void);
  * \}
  */
 
-#endif  // _BOARD_H_
+#endif  /* _BOARD_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c
index db2b5a69813e..e1e2f2e80af1 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c
@@ -51,7 +51,7 @@
 #include "conf_atsha204.h"
 
 
-//! TWI address used at SHA204 library startup
+/*! TWI address used at SHA204 library startup*/
 #define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
 
 
@@ -60,7 +60,7 @@
  */
 void security_board_init(void)
 {
-	sha204p_init();
+    sha204p_init();
 }
 
 
@@ -70,7 +70,7 @@ void security_board_init(void)
  */
 uint8_t sha204_i2c_address(uint8_t index)
 {
-	static uint8_t i2c_addresses[SHA204_DEVICE_COUNT] = {SHA204_I2C_DEFAULT_ADDRESS, 0xCC, 0xCE, 0xF8};
-	return i2c_addresses[index % SHA204_DEVICE_COUNT];
+    static uint8_t i2c_addresses[SHA204_DEVICE_COUNT] = {SHA204_I2C_DEFAULT_ADDRESS, 0xCC, 0xCE, 0xF8};
+    return i2c_addresses[index % SHA204_DEVICE_COUNT];
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h
index 3ba88a1fecb8..261e997cc07d 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h
@@ -54,7 +54,7 @@
 
 #include <compiler.h>
 
-//! number of ATSHA204 I2C devices on Security Xplained extension board
+/*! number of ATSHA204 I2C devices on Security Xplained extension board*/
 #define SHA204_DEVICE_COUNT          (4)
 
 void security_board_init(void);
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c
index 08a69693a62c..a031902cc915 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.c
@@ -115,19 +115,22 @@ static volatile void *sensor_pin5_arg;
  */
 ISR(gpio_irq_handler, AVR32_GPIO_IRQ_GROUP, GPIO_INT_LVL)
 {
-	if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN3)) {
-		sensor_pin3_handler(sensor_pin3_arg);
-
-		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN3);
-	} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN4)) {
-		sensor_pin4_handler(sensor_pin4_arg);
-
-		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN4);
-	} else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN5)) {
-		sensor_pin5_handler(sensor_pin5_arg);
-
-		gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN5);
-	}
+    if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN3))
+    {
+        sensor_pin3_handler(sensor_pin3_arg);
+
+        gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN3);
+    } else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN4))
+    {
+        sensor_pin4_handler(sensor_pin4_arg);
+
+        gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN4);
+    } else if (gpio_get_pin_interrupt_flag(SENSOR_BOARD_PIN5))
+    {
+        sensor_pin5_handler(sensor_pin5_arg);
+
+        gpio_clear_pin_interrupt_flag(SENSOR_BOARD_PIN5);
+    }
 }
 
 #elif XMEGA
@@ -142,22 +145,25 @@ ISR(gpio_irq_handler, AVR32_GPIO_IRQ_GROUP, GPIO_INT_LVL)
  */
 ISR(SENSOR_BOARD_PORT_vect)
 {
-	PORT_t *const port = &(SENSOR_BOARD_PORT);
-
-	/* Call the interrupt handler (if any). */
-	if (sensor_pin3_handler && (port->IN & PIN2_bm)) {
-		/* Note: header pin 3 = io port pin 2 */
-		sensor_pin3_handler(sensor_pin3_arg);
-	} else if (sensor_pin4_handler && (port->IN & PIN3_bm)) {
-		/* Note: header pin 4 = io port pin 3 */
-		sensor_pin4_handler(sensor_pin4_arg);
-	} else if (sensor_pin5_handler && (port->IN & PIN4_bm)) {
-		/* Note: header pin 5 = io port pin 4 */
-		sensor_pin5_handler(sensor_pin5_arg);
-	}
-
-	/* Clear the port interrupt flag */
-	port->INTFLAGS = PORT_INT0IF_bm;
+    PORT_t *const port = &(SENSOR_BOARD_PORT);
+
+    /* Call the interrupt handler (if any). */
+    if (sensor_pin3_handler && (port->IN & PIN2_bm))
+    {
+        /* Note: header pin 3 = io port pin 2 */
+        sensor_pin3_handler(sensor_pin3_arg);
+    } else if (sensor_pin4_handler && (port->IN & PIN3_bm))
+    {
+        /* Note: header pin 4 = io port pin 3 */
+        sensor_pin4_handler(sensor_pin4_arg);
+    } else if (sensor_pin5_handler && (port->IN & PIN4_bm))
+    {
+        /* Note: header pin 5 = io port pin 4 */
+        sensor_pin5_handler(sensor_pin5_arg);
+    }
+
+    /* Clear the port interrupt flag */
+    port->INTFLAGS = PORT_INT0IF_bm;
 }
 #endif
 
@@ -172,9 +178,9 @@ ISR(SENSOR_BOARD_PORT_vect)
  */
 ISR(eic_pin3_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
 {
-	sensor_pin3_handler(sensor_pin3_arg);     /* call handler in driver */
+    sensor_pin3_handler(sensor_pin3_arg);     /* call handler in driver */
 
-	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN3_EIC_LINE);
+    eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN3_EIC_LINE);
 }
 #endif
 
@@ -189,9 +195,9 @@ ISR(eic_pin3_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
  */
 ISR(eic_pin4_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
 {
-	sensor_pin4_handler(sensor_pin4_arg);     /* call handler in driver */
+    sensor_pin4_handler(sensor_pin4_arg);     /* call handler in driver */
 
-	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN4_EIC_LINE);
+    eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN4_EIC_LINE);
 }
 #endif
 
@@ -206,9 +212,9 @@ ISR(eic_pin4_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
  */
 ISR(eic_pin5_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
 {
-	sensor_pin5_handler(sensor_pin5_arg);     /* call handler in driver */
+    sensor_pin5_handler(sensor_pin5_arg);     /* call handler in driver */
 
-	eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN5_EIC_LINE);
+    eic_clear_interrupt_line(&AVR32_EIC, SENSOR_PIN5_EIC_LINE);
 }
 #endif
 
@@ -223,8 +229,8 @@ ISR(eic_pin5_handler, AVR32_EIC_IRQ_GROUP, EIC_INT_LVL)
  */
 static void gpio_irq_connect(uint32_t gpio_pin, uint32_t gpio_irq)
 {
-	irq_register_handler(gpio_irq_handler, gpio_irq, GPIO_INT_LVL);
-	gpio_enable_pin_interrupt(gpio_pin, GPIO_RISING_EDGE);
+    irq_register_handler(gpio_irq_handler, gpio_irq, GPIO_INT_LVL);
+    gpio_enable_pin_interrupt(gpio_pin, GPIO_RISING_EDGE);
 }
 
 #endif
@@ -242,25 +248,25 @@ static void gpio_irq_connect(uint32_t gpio_pin, uint32_t gpio_irq)
  * \param eic_handler   Interrupt handler to register
  */
 static void eic_irq_connect(uint32_t eic_line, uint32_t eic_pin,
-		uint32_t eic_func, uint32_t eic_irq, __int_handler eic_handler)
+        uint32_t eic_func, uint32_t eic_irq, __int_handler eic_handler)
 {
-	eic_options_t const eic_options = {
-		.eic_line   = eic_line,
-		.eic_mode   = EIC_MODE_EDGE_TRIGGERED,
-		.eic_edge   = EIC_EDGE_RISING_EDGE,
-		.eic_level  = EIC_LEVEL_HIGH_LEVEL,
-		.eic_filter = EIC_FILTER_ENABLED,
-		.eic_async  = EIC_ASYNCH_MODE
-	};
-
-	sysclk_enable_pba_module(SYSCLK_EIC);
-
-	gpio_enable_module_pin(eic_pin, eic_func);
-	irq_register_handler(eic_handler, eic_irq, 0);
-
-	eic_init(&AVR32_EIC, &eic_options, 1);
-	eic_enable_line(&AVR32_EIC, eic_line);
-	eic_enable_interrupt_line(&AVR32_EIC, eic_line);
+    eic_options_t const eic_options = {
+        .eic_line   = eic_line,
+        .eic_mode   = EIC_MODE_EDGE_TRIGGERED,
+        .eic_edge   = EIC_EDGE_RISING_EDGE,
+        .eic_level  = EIC_LEVEL_HIGH_LEVEL,
+        .eic_filter = EIC_FILTER_ENABLED,
+        .eic_async  = EIC_ASYNCH_MODE
+    };
+
+    sysclk_enable_pba_module(SYSCLK_EIC);
+
+    gpio_enable_module_pin(eic_pin, eic_func);
+    irq_register_handler(eic_handler, eic_irq, 0);
+
+    eic_init(&AVR32_EIC, &eic_options, 1);
+    eic_enable_line(&AVR32_EIC, eic_line);
+    eic_enable_interrupt_line(&AVR32_EIC, eic_line);
 }
 
 #endif
@@ -287,104 +293,108 @@ static void eic_irq_connect(uint32_t eic_line, uint32_t eic_pin,
  * \return  bool        true if the call succeeds, else false.
  */
 bool sensor_board_irq_connect(uint32_t gpio_pin,
-		SENSOR_IRQ_HANDLER handler, void *arg)
+        SENSOR_IRQ_HANDLER handler, void *arg)
 {
-	bool status = false;
+    bool status = false;
 
 #if XMEGA
-	PORT_t *sensor_port;
+    PORT_t *sensor_port;
 #endif
 
-	/* Ensure that the caller has specified a function address. */
+    /* Ensure that the caller has specified a function address. */
 
-	if (handler == NULL) {
-		return status;
-	}
+    if (handler == NULL)
+    {
+        return status;
+    }
 
-	/* Save the interrupt flag state and disable MCU interrupts. */
+    /* Save the interrupt flag state and disable MCU interrupts. */
 
-	irqflags_t const irq_flags = cpu_irq_save();
+    irqflags_t const irq_flags = cpu_irq_save();
 
-	cpu_irq_disable();
+    cpu_irq_disable();
 
-	/* Initialize an interrupt for a specified I/O pin. */
+    /* Initialize an interrupt for a specified I/O pin. */
 
-	if (SENSOR_BOARD_PIN3 == gpio_pin) {
-		sensor_pin3_handler = handler;
-		sensor_pin3_arg     = arg;
+    if (SENSOR_BOARD_PIN3 == gpio_pin)
+    {
+        sensor_pin3_handler = handler;
+        sensor_pin3_arg     = arg;
 
 #if UC3
 #  if defined(SENSOR_PIN3_EIC_LINE)
-		eic_irq_connect(SENSOR_PIN3_EIC_LINE, SENSOR_PIN3_EIC_PIN,
-				SENSOR_PIN3_EIC_FUNC, SENSOR_PIN3_EIC_IRQ,
-				eic_pin3_handler);
+        eic_irq_connect(SENSOR_PIN3_EIC_LINE, SENSOR_PIN3_EIC_PIN,
+                SENSOR_PIN3_EIC_FUNC, SENSOR_PIN3_EIC_IRQ,
+                eic_pin3_handler);
 #  else
-		gpio_irq_connect(gpio_pin, SENSOR_PIN3_IRQ);
+        gpio_irq_connect(gpio_pin, SENSOR_PIN3_IRQ);
 #  endif
 #elif XMEGA
-		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN3);
-		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
-		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN3);
-		/* Some Xplained kits have limited asynchronous sensing on most
-		 * pins, which requires them to be sensing on both edges.
-		 */
-		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN3,
-				IOPORT_SENSE_BOTHEDGES);
+        sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN3);
+        sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+        sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN3);
+        /* Some Xplained kits have limited asynchronous sensing on most
+         * pins, which requires them to be sensing on both edges.
+         */
+        ioport_set_pin_sense_mode(SENSOR_BOARD_PIN3,
+                IOPORT_SENSE_BOTHEDGES);
 #endif
-		status = true;
-	} else if (SENSOR_BOARD_PIN4 == gpio_pin) {
-		sensor_pin4_handler = handler;
-		sensor_pin4_arg     = arg;
+        status = true;
+    } else if (SENSOR_BOARD_PIN4 == gpio_pin)
+    {
+        sensor_pin4_handler = handler;
+        sensor_pin4_arg     = arg;
 
 #if UC3
 #  if defined(SENSOR_PIN4_EIC_LINE)
-		eic_irq_connect(SENSOR_PIN4_EIC_LINE, SENSOR_PIN4_EIC_PIN,
-				SENSOR_PIN4_EIC_FUNC, SENSOR_PIN4_EIC_IRQ,
-				eic_pin4_handler);
+        eic_irq_connect(SENSOR_PIN4_EIC_LINE, SENSOR_PIN4_EIC_PIN,
+                SENSOR_PIN4_EIC_FUNC, SENSOR_PIN4_EIC_IRQ,
+                eic_pin4_handler);
 #  else
-		gpio_irq_connect(gpio_pin, SENSOR_PIN4_IRQ);
+        gpio_irq_connect(gpio_pin, SENSOR_PIN4_IRQ);
 #  endif
 #elif XMEGA
-		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN4);
-		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
-		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN4);
-		/* Some Xplained kits have limited asynchronous sensing on most
-		 * pins, which requires them to be sensing on both edges.
-		 */
-		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN4,
-				IOPORT_SENSE_BOTHEDGES);
+        sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN4);
+        sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+        sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN4);
+        /* Some Xplained kits have limited asynchronous sensing on most
+         * pins, which requires them to be sensing on both edges.
+         */
+        ioport_set_pin_sense_mode(SENSOR_BOARD_PIN4,
+                IOPORT_SENSE_BOTHEDGES);
 #endif
-		status = true;
-	} else if (SENSOR_BOARD_PIN5 == gpio_pin) {
-		sensor_pin5_handler = handler;
-		sensor_pin5_arg     = arg;
+        status = true;
+    } else if (SENSOR_BOARD_PIN5 == gpio_pin)
+    {
+        sensor_pin5_handler = handler;
+        sensor_pin5_arg     = arg;
 
 #if UC3
 #  if defined(SENSOR_PIN5_EIC_LINE)
-		eic_irq_connect(SENSOR_PIN5_EIC_LINE, SENSOR_PIN5_EIC_PIN,
-				SENSOR_PIN5_EIC_FUNC, SENSOR_PIN5_EIC_IRQ,
-				eic_pin5_handler);
+        eic_irq_connect(SENSOR_PIN5_EIC_LINE, SENSOR_PIN5_EIC_PIN,
+                SENSOR_PIN5_EIC_FUNC, SENSOR_PIN5_EIC_IRQ,
+                eic_pin5_handler);
 #  else
-		gpio_irq_connect(gpio_pin, SENSOR_PIN5_IRQ);
+        gpio_irq_connect(gpio_pin, SENSOR_PIN5_IRQ);
 #  endif
 #elif XMEGA
-		sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN5);
-		sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
-		sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN5);
-		/* Some Xplained kits have limited asynchronous sensing on most
-		 * pins, which requires them to be sensing on both edges.
-		 */
-		ioport_set_pin_sense_mode(SENSOR_BOARD_PIN5,
-				IOPORT_SENSE_BOTHEDGES);
+        sensor_port = ioport_pin_to_port(SENSOR_BOARD_PIN5);
+        sensor_port->INTCTRL   = PORT_INT0LVL_LO_gc;
+        sensor_port->INT0MASK |= ioport_pin_to_mask(SENSOR_BOARD_PIN5);
+        /* Some Xplained kits have limited asynchronous sensing on most
+         * pins, which requires them to be sensing on both edges.
+         */
+        ioport_set_pin_sense_mode(SENSOR_BOARD_PIN5,
+                IOPORT_SENSE_BOTHEDGES);
 #endif
-		status = true;
-	}
+        status = true;
+    }
 
-	/* Restore the MCU interrupt flag state. */
+    /* Restore the MCU interrupt flag state. */
 
-	cpu_irq_restore(irq_flags);
+    cpu_irq_restore(irq_flags);
 
-	return status;
+    return status;
 }
 
 #endif /* defined(SENSORS_XPLAINED_BOARD) && defined(COMMON_SENSOR_PLATFORM) */
@@ -398,38 +408,38 @@ bool sensor_board_irq_connect(uint32_t gpio_pin,
  */
 void sensor_board_init(void)
 {
-	/* Configure all defined Xplained Sensor board I/O pins.
-	 *
-	 * \todo
-	 * Determine whether the interrupt event flag (rising edge, falling
-	 * edge, toggle, etc.) should be a statically configurable parameter
-	 * for devices requiring more flexibility in how events are detected.
-	 */
+    /* Configure all defined Xplained Sensor board I/O pins.
+     *
+     * \todo
+     * Determine whether the interrupt event flag (rising edge, falling
+     * edge, toggle, etc.) should be a statically configurable parameter
+     * for devices requiring more flexibility in how events are detected.
+     */
 #if (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
-	(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
-	(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
+    (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
+    (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1)
 
-	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
-	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
-	gpio_configure_pin(SENSOR_BOARD_PIN5, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN5, PIN_INPUT_FLAGS);
 
 #elif (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1)
-	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_OUTPUT_FLAGS);
-	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_OUTPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
 
 #elif (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1)
-	gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN3, PIN_INPUT_FLAGS);
 
 #elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
-	gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
+    gpio_configure_pin(SENSOR_BOARD_PIN4, PIN_INPUT_FLAGS);
 #endif
 
-	/* Global Interrupt Disable */
-	cpu_irq_disable();
+    /* Global Interrupt Disable */
+    cpu_irq_disable();
 
-	/* Initialize interrupt vector table support. */
-	irq_initialize_vectors();
+    /* Initialize interrupt vector table support. */
+    irq_initialize_vectors();
 
-	/* Global Interrupt Enable */
-	cpu_irq_enable();
+    /* Global Interrupt Enable */
+    cpu_irq_enable();
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h
index 59f4908d6db0..1e6d5251af3f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/sensors_xplained.h
@@ -193,7 +193,7 @@ extern "C" {
 #   undef SENSORS_XPLAINED_BOARD
 #   warning "The EXT_BOARD constant does not define a Sensors Xplained board."
 #endif
-// @}
+/* @}*/
 
 
 /*! \name Xplained Board J1 Connector Pin Mapping
@@ -205,16 +205,16 @@ extern "C" {
  *
  * \code
 
-	      10-pin Header           Function
-	  -------------------------------------------
-	      Pin 1                   SDA
-	      Pin 2                   SCL
-	      Pin 3                   RXD
-	      Pin 4                   TXD
-	      Pin 5                   SS
-	      Pin 6                   MOSI
-	      Pin 7                   MISO
-	      Pin 8                   SCK
+          10-pin Header           Function
+      -------------------------------------------
+          Pin 1                   SDA
+          Pin 2                   SCL
+          Pin 3                   RXD
+          Pin 4                   TXD
+          Pin 5                   SS
+          Pin 6                   MOSI
+          Pin 7                   MISO
+          Pin 8                   SCK
 
 \endcode
  * @{
@@ -232,7 +232,7 @@ extern "C" {
 #   define SENSOR_BOARD_PORT        XPLD_HEADER_J1_PORT
 #   define SENSOR_BOARD_PORT_vect   XPLD_HEADER_J1_INT0_vect
 #endif
-// @}
+/* @}*/
 
 
 /*! \name Sensor Device Interrupt Routing
@@ -324,7 +324,7 @@ extern "C" {
 #    define SENSOR_PIN8_EIC_PIN     XPLD_HEADER_J1_PIN8_EIC_PIN
 #    define SENSOR_PIN8_EIC_FUNC    XPLD_HEADER_J1_PIN8_EIC_FUNC
 #endif
-// @}
+/* @}*/
 
 
 /*! \name Sensor Device I/O Pins
@@ -373,7 +373,7 @@ extern "C" {
 #   define bma222_sigint            (SENSOR_BOARD_PIN4)
 #   define bma222_sigout            (INVALID_PIN_NUMBER)
 #endif
-// @}
+/* @}*/
 
 
 /*! \name Sensor Physical Orientation
@@ -413,12 +413,12 @@ extern "C" {
 #elif (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
 #   define bma222_orientation       {AXIS_X_POS, AXIS_Y_POS, AXIS_Z_POS}
 #endif
-// @}
+/* @}*/
 
-/** @} */ // atavrsb_config group
+/** @} */ /* atavrsb_config group*/
 
 
-//! \brief Sensor Pin Interrupt Handler Callback Type
+/*! \brief Sensor Pin Interrupt Handler Callback Type*/
 
 typedef void (*SENSOR_IRQ_HANDLER)(volatile void *);
 
@@ -454,7 +454,7 @@ extern void sensor_board_init(void);
  * \return  bool        true if the call succeeds, else false.
  */
 extern bool sensor_board_irq_connect
-	(uint32_t gpio_pin, SENSOR_IRQ_HANDLER handler, void *arg);
+    (uint32_t gpio_pin, SENSOR_IRQ_HANDLER handler, void *arg);
 
 
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h
index 8e16645d7041..12db21bd11a2 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/sensors_xplained/xplained_headers.h
@@ -72,8 +72,8 @@ extern "C" {
 #define INVALID_PIN_NUMBER              ((unsigned int) -1)
 
 
-//! \name Xplained I/O Expansion Header Pin Mapping
-// @{
+/*! \name Xplained I/O Expansion Header Pin Mapping*/
+/* @{*/
 #if (BOARD == UC3_A3_XPLAINED)
 #   define XPLD_HEADER_J1_PIN1          (AVR32_PIN_PA25)
 #   define XPLD_HEADER_J1_PIN2          (AVR32_PIN_PA26)
@@ -297,11 +297,11 @@ extern "C" {
 #   define XPLD_HEADER_J4_PIN7          INVALID_PIN_NUMBER
 #   define XPLD_HEADER_J4_PIN8          INVALID_PIN_NUMBER
 #endif
-// @}
+/* @}*/
 
 
-//! \name Xplained Expansion Header External Interrupt Controller Pin Mapping
-// @{
+/*! \name Xplained Expansion Header External Interrupt Controller Pin Mapping*/
+/* @{*/
 #if (BOARD == UC3_A3_XPLAINED)
 #   define XPLD_HEADER_J2_PIN1_EIC_LINE (AVR32_EIC_INT0)
 #   define XPLD_HEADER_J2_PIN1_EIC_IRQ  (AVR32_EIC_IRQ_0)
@@ -323,8 +323,8 @@ extern "C" {
 #   define XPLD_HEADER_J2_PIN4_EIC_PIN  (AVR32_EIC_EXTINT_3_PIN)
 #   define XPLD_HEADER_J2_PIN4_EIC_FUNC (AVR32_EIC_EXTINT_3_FUNCTION)
 
-#   define XPLD_HEADER_J2_PIN5_EIC_LINE (8) // NMI
-#   define XPLD_HEADER_J2_PIN5_EIC_IRQ  (0) // NMI - special handler required
+#   define XPLD_HEADER_J2_PIN5_EIC_LINE (8) /* NMI*/
+#   define XPLD_HEADER_J2_PIN5_EIC_IRQ  (0) /* NMI - special handler required*/
 #   define XPLD_HEADER_J2_PIN5_EIC_PIN  (AVR32_EIC_EXTINT_8_PIN)
 #   define XPLD_HEADER_J2_PIN5_EIC_FUNC (AVR32_EIC_EXTINT_8_FUNCTION)
 
@@ -429,7 +429,7 @@ extern "C" {
 #   define XPLD_HEADER_J1_INT1_vect     (PORTC_INT1_vect)
 
 #endif
-// @}
+/* @}*/
 
 
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h
index 7b88c97fc205..0bd0ed6a4517 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h
@@ -11,4 +11,4 @@
 #ifndef CONF_BOARD_H
 #define CONF_BOARD_H
 
-#endif // CONF_BOARD_H
+#endif /* CONF_BOARD_H*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c
index 32fba3695e75..a1d7cf6541aa 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c
@@ -14,8 +14,8 @@
 
 void board_init(void)
 {
-	/* This function is meant to contain board-specific initialization code
-	 * for, e.g., the I/O pins. The initialization can rely on application-
-	 * specific board configuration, found in conf_board.h.
-	 */
+    /* This function is meant to contain board-specific initialization code
+     * for, e.g., the I/O pins. The initialization can rely on application-
+     * specific board configuration, found in conf_board.h.
+     */
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h
index 39980a7d2e46..6167a8215a30 100644
--- a/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h
+++ b/bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h
@@ -19,22 +19,22 @@
 
 #include <conf_board.h>
 
-// External oscillator settings.
-// Uncomment and set correct values if external oscillator is used.
+/* External oscillator settings.*/
+/* Uncomment and set correct values if external oscillator is used.*/
 
-// External oscillator frequency
-//#define BOARD_XOSC_HZ          8000000
+/* External oscillator frequency*/
+/*#define BOARD_XOSC_HZ          8000000*/
 
-// External oscillator type.
-//!< External clock signal
-//#define BOARD_XOSC_TYPE        XOSC_TYPE_EXTERNAL
-//!< 32.768 kHz resonator on TOSC
-//#define BOARD_XOSC_TYPE        XOSC_TYPE_32KHZ
-//!< 0.4 to 16 MHz resonator on XTALS
-//#define BOARD_XOSC_TYPE        XOSC_TYPE_XTAL
+/* External oscillator type.*/
+/*!< External clock signal*/
+/*#define BOARD_XOSC_TYPE        XOSC_TYPE_EXTERNAL*/
+/*!< 32.768 kHz resonator on TOSC*/
+/*#define BOARD_XOSC_TYPE        XOSC_TYPE_32KHZ*/
+/*!< 0.4 to 16 MHz resonator on XTALS*/
+/*#define BOARD_XOSC_TYPE        XOSC_TYPE_XTAL*/
 
-// External oscillator startup time
-//#define BOARD_XOSC_STARTUP_US  500000
+/* External oscillator startup time*/
+/*#define BOARD_XOSC_STARTUP_US  500000*/
 
 
-#endif // USER_BOARD_H
+#endif /* USER_BOARD_H*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h
index f1adbce38e19..67579ac2ea6a 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h
@@ -50,19 +50,19 @@
 #include <board.h>
 
 #if BOARD == XMEGA_A1_XPLAINED
-// Interface configuration for XMEGA-A1 Xplained
+/* Interface configuration for XMEGA-A1 Xplained*/
 #  define ATSHA204_TWI_PORT         (&TWIC)
 
 #else
-// Interface configuration for other boards
+/* Interface configuration for other boards*/
 #  warning ATSHA204 TWI port is not set for your board. Please see conf_atsha204.h.
 #  define ATSHA204_TWI_PORT         (&TWIC)
-#endif // BOARD
+#endif /* BOARD*/
 
-// Xplain board independent configuration
-#define ATSHA204_TWI_SPEED      	(400000)
+/* Xplain board independent configuration*/
+#define ATSHA204_TWI_SPEED          (400000)
 
-//! TWI address used at SHA204 library startup
+/*! TWI address used at SHA204 library startup*/
 #define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
 
 #endif /* CONF_ATSHA204_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c
index 24c484b1e77c..2697c418a980 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.c
@@ -45,9 +45,9 @@
  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  */
 
-#include "sha204_comm.h"                //!< definitions and declarations for the Communication module
-#include "sha204_timer.h"               //!< definitions for timer functions
-#include "sha204_lib_return_codes.h"    //!< declarations of function return codes
+#include "sha204_comm.h"                /*!< definitions and declarations for the Communication module*/
+#include "sha204_timer.h"               /*!< definitions for timer functions*/
+#include "sha204_lib_return_codes.h"    /*!< declarations of function return codes*/
 
 uint8_t sha204c_check_crc(uint8_t *response);
 uint8_t sha204c_resync(uint8_t size, uint8_t *response);
@@ -58,27 +58,30 @@ uint8_t sha204c_resync(uint8_t size, uint8_t *response);
  * \param[in] data pointer to data for which CRC should be calculated
  * \param[out] crc pointer to 16-bit CRC
  */
-void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc) {
-	uint8_t counter;
-	uint16_t crc_register = 0;
-	uint16_t polynom = 0x8005;
-	uint8_t shift_register;
-	uint8_t data_bit, crc_bit;
-
-	for (counter = 0; counter < length; counter++) {
-	  for (shift_register = 0x01; shift_register > 0x00; shift_register <<= 1) {
-		 data_bit = (data[counter] & shift_register) ? 1 : 0;
-		 crc_bit = crc_register >> 15;
-
-		 // Shift CRC to the left by 1.
-		 crc_register <<= 1;
-
-		 if ((data_bit ^ crc_bit) != 0)
-			crc_register ^= polynom;
-	  }
-	}
-	crc[0] = (uint8_t) (crc_register & 0x00FF);
-	crc[1] = (uint8_t) (crc_register >> 8);
+void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc)
+{
+    uint8_t counter;
+    uint16_t crc_register = 0;
+    uint16_t polynom = 0x8005;
+    uint8_t shift_register;
+    uint8_t data_bit, crc_bit;
+
+    for (counter = 0; counter < length; counter++)
+    {
+      for (shift_register = 0x01; shift_register > 0x00; shift_register <<= 1)
+      {
+         data_bit = (data[counter] & shift_register) ? 1 : 0;
+         crc_bit = crc_register >> 15;
+
+         /* Shift CRC to the left by 1.*/
+         crc_register <<= 1;
+
+         if ((data_bit ^ crc_bit) != 0)
+            crc_register ^= polynom;
+      }
+    }
+    crc[0] = (uint8_t) (crc_register & 0x00FF);
+    crc[1] = (uint8_t) (crc_register >> 8);
 }
 
 
@@ -88,14 +91,14 @@ void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc) {
  */
 uint8_t sha204c_check_crc(uint8_t *response)
 {
-	uint8_t crc[SHA204_CRC_SIZE];
-	uint8_t count = response[SHA204_BUFFER_POS_COUNT];
+    uint8_t crc[SHA204_CRC_SIZE];
+    uint8_t count = response[SHA204_BUFFER_POS_COUNT];
 
-	count -= SHA204_CRC_SIZE;
-	sha204c_calculate_crc(count, response, crc);
+    count -= SHA204_CRC_SIZE;
+    sha204c_calculate_crc(count, response, crc);
 
-	return (crc[0] == response[count] && crc[1] == response[count + 1])
-		? SHA204_SUCCESS : SHA204_BAD_CRC;
+    return (crc[0] == response[count] && crc[1] == response[count + 1])
+        ? SHA204_SUCCESS : SHA204_BAD_CRC;
 }
 
 
@@ -106,28 +109,28 @@ uint8_t sha204c_check_crc(uint8_t *response)
  */
 uint8_t sha204c_wakeup(uint8_t *response)
 {
-	uint8_t ret_code = sha204p_wakeup();
-	if (ret_code != SHA204_SUCCESS)
-		return ret_code;
-
-	ret_code = sha204p_receive_response(SHA204_RSP_SIZE_MIN, response);
-	if (ret_code != SHA204_SUCCESS)
-		return ret_code;
-
-	// Verify status response.
-	if (response[SHA204_BUFFER_POS_COUNT] != SHA204_RSP_SIZE_MIN)
-		ret_code = SHA204_INVALID_SIZE;
-	else if (response[SHA204_BUFFER_POS_STATUS] != SHA204_STATUS_BYTE_WAKEUP)
-		ret_code = SHA204_COMM_FAIL;
-	else {
-		if ((response[SHA204_RSP_SIZE_MIN - SHA204_CRC_SIZE] != 0x33)
-					|| (response[SHA204_RSP_SIZE_MIN + 1 - SHA204_CRC_SIZE] != 0x43))
-			ret_code = SHA204_BAD_CRC;
-	}
-	if (ret_code != SHA204_SUCCESS)
-		sha204h_delay_ms(SHA204_COMMAND_EXEC_MAX);
-
-	return ret_code;
+    uint8_t ret_code = sha204p_wakeup();
+    if (ret_code != SHA204_SUCCESS)
+        return ret_code;
+
+    ret_code = sha204p_receive_response(SHA204_RSP_SIZE_MIN, response);
+    if (ret_code != SHA204_SUCCESS)
+        return ret_code;
+
+    /* Verify status response.*/
+    if (response[SHA204_BUFFER_POS_COUNT] != SHA204_RSP_SIZE_MIN)
+        ret_code = SHA204_INVALID_SIZE;
+    else if (response[SHA204_BUFFER_POS_STATUS] != SHA204_STATUS_BYTE_WAKEUP)
+        ret_code = SHA204_COMM_FAIL;
+    else {
+        if ((response[SHA204_RSP_SIZE_MIN - SHA204_CRC_SIZE] != 0x33)
+                    || (response[SHA204_RSP_SIZE_MIN + 1 - SHA204_CRC_SIZE] != 0x43))
+            ret_code = SHA204_BAD_CRC;
+    }
+    if (ret_code != SHA204_SUCCESS)
+        sha204h_delay_ms(SHA204_COMMAND_EXEC_MAX);
+
+    return ret_code;
 }
 
 
@@ -157,22 +160,22 @@ uint8_t sha204c_wakeup(uint8_t *response)
  */
 uint8_t sha204c_resync(uint8_t size, uint8_t *response)
 {
-	// Try to re-synchronize without sending a Wake token
-	// (step 1 of the re-synchronization process).
-	uint8_t ret_code = sha204p_resync(size, response);
-	if (ret_code == SHA204_SUCCESS)
-		return ret_code;
-
-	// We lost communication. Send a Wake pulse and try
-	// to receive a response (steps 2 and 3 of the
-	// re-synchronization process).
-	(void) sha204p_sleep();
-	ret_code = sha204c_wakeup(response);
-
-	// Translate a return value of success into one
-	// that indicates that the device had to be woken up
-	// and might have lost its TempKey.
-	return (ret_code == SHA204_SUCCESS ? SHA204_RESYNC_WITH_WAKEUP : ret_code);
+    /* Try to re-synchronize without sending a Wake token*/
+    /* (step 1 of the re-synchronization process).*/
+    uint8_t ret_code = sha204p_resync(size, response);
+    if (ret_code == SHA204_SUCCESS)
+        return ret_code;
+
+    /* We lost communication. Send a Wake pulse and try*/
+    /* to receive a response (steps 2 and 3 of the*/
+    /* re-synchronization process).*/
+    (void) sha204p_sleep();
+    ret_code = sha204c_wakeup(response);
+
+    /* Translate a return value of success into one*/
+    /* that indicates that the device had to be woken up*/
+    /* and might have lost its TempKey.*/
+    return (ret_code == SHA204_SUCCESS ? SHA204_RESYNC_WITH_WAKEUP : ret_code);
 }
 
 
@@ -189,124 +192,131 @@ uint8_t sha204c_resync(uint8_t size, uint8_t *response)
  */
 uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args)
 {
-	uint8_t ret_code = SHA204_FUNC_FAIL;
-	uint8_t ret_code_resync;
-	uint8_t n_retries_send;
-	uint8_t n_retries_receive;
-	uint8_t i;
-	uint8_t status_byte;
-	uint8_t count = args->tx_buffer[SHA204_BUFFER_POS_COUNT];
-	uint8_t count_minus_crc = count - SHA204_CRC_SIZE;
-
-	// Append CRC.
-	sha204c_calculate_crc(count_minus_crc, args->tx_buffer, args->tx_buffer + count_minus_crc);
-
-	// Retry loop for sending a command and receiving a response.
-	n_retries_send = SHA204_RETRY_COUNT + 1;
-
-	while ((n_retries_send-- > 0) && (ret_code != SHA204_SUCCESS)) {
-
-		// Send command.
-		ret_code = sha204p_send_command(count, args->tx_buffer);
-		if (ret_code != SHA204_SUCCESS) {
-			if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
-				// The device seems to be dead in the water.
-				return ret_code;
-			else
-				continue;
-		}
-
-		// Wait typical command execution time and then start polling for a response.
-		sha204h_delay_ms(args->poll_delay);
-
-		// Retry loop for receiving a response.
-		n_retries_receive = SHA204_RETRY_COUNT + 1;
-		while (n_retries_receive-- > 0) {
-
-			// Reset response buffer.
-			for (i = 0; i < args->rx_size; i++)
-				args->rx_buffer[i] = 0;
-
-			sha204h_start_timeout_timer_ms(args->poll_timeout);
-			do {
-				ret_code = sha204p_receive_response(args->rx_size, args->rx_buffer);
-			} while (!sha204_timer_expired && (ret_code == SHA204_RX_NO_RESPONSE));
-
-			if (ret_code == SHA204_RX_NO_RESPONSE) {
-				// We did not receive a response. Re-synchronize and send command again.
-				if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
-					// The device seems to be dead in the water.
-					return ret_code;
-				else
-					break;
-			}
-
-			// Check whether we received a valid response.
-			if (ret_code == SHA204_INVALID_SIZE) {
-				// We see 0xFF for the count when communication got out of sync.
-				ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
-				if (ret_code_resync == SHA204_SUCCESS)
-					// We did not have to wake up the device. Try receiving response again.
-					continue;
-				if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
-					// We could re-synchronize, but only after waking up the device.
-					// Re-send command.
-					break;
-				else
-					// We failed to re-synchronize.
-					return ret_code;
-			}
-
-			// We received a response of valid size.
-			// Check the consistency of the response.
-			ret_code = sha204c_check_crc(args->rx_buffer);
-			if (ret_code == SHA204_SUCCESS) {
-				// Received valid response.
-				if (args->rx_buffer[SHA204_BUFFER_POS_COUNT] > SHA204_RSP_SIZE_MIN)
-					// Received non-status response. We are done.
-					return ret_code;
-
-				// Received status response.
-				status_byte = args->rx_buffer[SHA204_BUFFER_POS_STATUS];
-
-				// Translate the three possible device status error codes
-				// into library return codes.
-				if (status_byte == SHA204_STATUS_BYTE_PARSE)
-					return SHA204_PARSE_ERROR;
-				if (status_byte == SHA204_STATUS_BYTE_EXEC)
-					return SHA204_CMD_FAIL;
-				if (status_byte == SHA204_STATUS_BYTE_COMM) {
-					// In case of the device status byte indicating a communication
-					// error this function exits the retry loop for receiving a response
-					// and enters the overall retry loop
-					// (send command / receive response).
-					ret_code = SHA204_STATUS_CRC;
-					break;
-				}
-
-				// Received status response from CheckMAC, DeriveKey, GenDig,
-				// Lock, Nonce, Pause, UpdateExtra, or Write command.
-				return ret_code;
-			}
-
-			else {
-				// Received response with incorrect CRC.
-				ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
-				if (ret_code_resync == SHA204_SUCCESS)
-					// We did not have to wake up the device. Try receiving response again.
-					continue;
-				if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
-					// We could re-synchronize, but only after waking up the device.
-					// Re-send command.
-					break;
-				else
-					// We failed to re-synchronize.
-					return ret_code;
-			} // block end of check response consistency
-
-		} // block end of receive retry loop
-
-	} // block end of send and receive retry loop
-
-	return ret_code;
+    uint8_t ret_code = SHA204_FUNC_FAIL;
+    uint8_t ret_code_resync;
+    uint8_t n_retries_send;
+    uint8_t n_retries_receive;
+    uint8_t i;
+    uint8_t status_byte;
+    uint8_t count = args->tx_buffer[SHA204_BUFFER_POS_COUNT];
+    uint8_t count_minus_crc = count - SHA204_CRC_SIZE;
+
+    /* Append CRC.*/
+    sha204c_calculate_crc(count_minus_crc, args->tx_buffer, args->tx_buffer + count_minus_crc);
+
+    /* Retry loop for sending a command and receiving a response.*/
+    n_retries_send = SHA204_RETRY_COUNT + 1;
+
+    while ((n_retries_send-- > 0) && (ret_code != SHA204_SUCCESS))
+    {
+
+        /* Send command.*/
+        ret_code = sha204p_send_command(count, args->tx_buffer);
+        if (ret_code != SHA204_SUCCESS)
+        {
+            if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
+                /* The device seems to be dead in the water.*/
+                return ret_code;
+            else
+                continue;
+        }
+
+        /* Wait typical command execution time and then start polling for a response.*/
+        sha204h_delay_ms(args->poll_delay);
+
+        /* Retry loop for receiving a response.*/
+        n_retries_receive = SHA204_RETRY_COUNT + 1;
+        while (n_retries_receive-- > 0)
+        {
+
+            /* Reset response buffer.*/
+            for (i = 0; i < args->rx_size; i++)
+                args->rx_buffer[i] = 0;
+
+            sha204h_start_timeout_timer_ms(args->poll_timeout);
+            do {
+                ret_code = sha204p_receive_response(args->rx_size, args->rx_buffer);
+            } while (!sha204_timer_expired && (ret_code == SHA204_RX_NO_RESPONSE));
+
+            if (ret_code == SHA204_RX_NO_RESPONSE)
+            {
+                /* We did not receive a response. Re-synchronize and send command again.*/
+                if (sha204c_resync(args->rx_size, args->rx_buffer) == SHA204_RX_NO_RESPONSE)
+                    /* The device seems to be dead in the water.*/
+                    return ret_code;
+                else
+                    break;
+            }
+
+            /* Check whether we received a valid response.*/
+            if (ret_code == SHA204_INVALID_SIZE)
+            {
+                /* We see 0xFF for the count when communication got out of sync.*/
+                ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
+                if (ret_code_resync == SHA204_SUCCESS)
+                    /* We did not have to wake up the device. Try receiving response again.*/
+                    continue;
+                if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
+                    /* We could re-synchronize, but only after waking up the device.*/
+                    /* Re-send command.*/
+                    break;
+                else
+                    /* We failed to re-synchronize.*/
+                    return ret_code;
+            }
+
+            /* We received a response of valid size.*/
+            /* Check the consistency of the response.*/
+            ret_code = sha204c_check_crc(args->rx_buffer);
+            if (ret_code == SHA204_SUCCESS)
+            {
+                /* Received valid response.*/
+                if (args->rx_buffer[SHA204_BUFFER_POS_COUNT] > SHA204_RSP_SIZE_MIN)
+                    /* Received non-status response. We are done.*/
+                    return ret_code;
+
+                /* Received status response.*/
+                status_byte = args->rx_buffer[SHA204_BUFFER_POS_STATUS];
+
+                /* Translate the three possible device status error codes*/
+                /* into library return codes.*/
+                if (status_byte == SHA204_STATUS_BYTE_PARSE)
+                    return SHA204_PARSE_ERROR;
+                if (status_byte == SHA204_STATUS_BYTE_EXEC)
+                    return SHA204_CMD_FAIL;
+                if (status_byte == SHA204_STATUS_BYTE_COMM)
+                {
+                    /* In case of the device status byte indicating a communication*/
+                    /* error this function exits the retry loop for receiving a response*/
+                    /* and enters the overall retry loop*/
+                    /* (send command / receive response).*/
+                    ret_code = SHA204_STATUS_CRC;
+                    break;
+                }
+
+                /* Received status response from CheckMAC, DeriveKey, GenDig,*/
+                /* Lock, Nonce, Pause, UpdateExtra, or Write command.*/
+                return ret_code;
+            }
+
+            else {
+                /* Received response with incorrect CRC.*/
+                ret_code_resync = sha204c_resync(args->rx_size, args->rx_buffer);
+                if (ret_code_resync == SHA204_SUCCESS)
+                    /* We did not have to wake up the device. Try receiving response again.*/
+                    continue;
+                if (ret_code_resync == SHA204_RESYNC_WITH_WAKEUP)
+                    /* We could re-synchronize, but only after waking up the device.*/
+                    /* Re-send command.*/
+                    break;
+                else
+                    /* We failed to re-synchronize.*/
+                    return ret_code;
+            } /* block end of check response consistency*/
+
+        } /* block end of receive retry loop*/
+
+    } /* block end of send and receive retry loop*/
+
+    return ret_code;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h
index c1c41f5800da..f36a579e7476 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_comm.h
@@ -48,49 +48,49 @@
 #ifndef SHA204_COMM_H
 #   define SHA204_COMM_H
 
-#include <compiler.h>               //!< compiler dependent definitions
+#include <compiler.h>               /*!< compiler dependent definitions*/
 
-#include "sha204_physical.h"        //!< declarations that are common to all interface implementations
+#include "sha204_physical.h"        /*!< declarations that are common to all interface implementations*/
 
-//! maximum command delay
+/*! maximum command delay*/
 #define SHA204_COMMAND_EXEC_MAX      (69)
 
-//! minimum number of bytes in command (from count byte to second CRC byte)
+/*! minimum number of bytes in command (from count byte to second CRC byte)*/
 #define SHA204_CMD_SIZE_MIN          ((uint8_t)  7)
 
-//! maximum size of command packet (CheckMac)
+/*! maximum size of command packet (CheckMac)*/
 #define SHA204_CMD_SIZE_MAX          ((uint8_t) 84)
 
-//! number of CRC bytes
+/*! number of CRC bytes*/
 #define SHA204_CRC_SIZE              ((uint8_t)  2)
 
-//! buffer index of status byte in status response
+/*! buffer index of status byte in status response*/
 #define SHA204_BUFFER_POS_STATUS     (1)
 
-//! buffer index of first data byte in data response
+/*! buffer index of first data byte in data response*/
 #define SHA204_BUFFER_POS_DATA       (1)
 
-//! status byte after wake-up
+/*! status byte after wake-up*/
 #define SHA204_STATUS_BYTE_WAKEUP    ((uint8_t) 0x11)
 
-//! command parse error
+/*! command parse error*/
 #define SHA204_STATUS_BYTE_PARSE     ((uint8_t) 0x03)
 
-//! command execution error
+/*! command execution error*/
 #define SHA204_STATUS_BYTE_EXEC      ((uint8_t) 0x0F)
 
-//! communication error
+/*! communication error*/
 #define SHA204_STATUS_BYTE_COMM      ((uint8_t) 0xFF)
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204c_send_and_receive function.
  */
 struct sha204_send_and_receive_parameters {
-	uint8_t *tx_buffer;         //!< pointer to send buffer
-	uint8_t rx_size;            //!< size of receive buffer
-	uint8_t *rx_buffer;         //!< pointer to receive buffer
-	uint8_t poll_delay;         //!< how long to wait before polling for response-ready
-	uint8_t poll_timeout;       //!< how long to poll before timing out
+    uint8_t *tx_buffer;         /*!< pointer to send buffer*/
+    uint8_t rx_size;            /*!< size of receive buffer*/
+    uint8_t *rx_buffer;         /*!< pointer to receive buffer*/
+    uint8_t poll_delay;         /*!< how long to wait before polling for response-ready*/
+    uint8_t poll_timeout;       /*!< how long to poll before timing out*/
 };
 
 /**
@@ -100,6 +100,6 @@ struct sha204_send_and_receive_parameters {
 void sha204c_calculate_crc(uint8_t length, uint8_t *data, uint8_t *crc);
 uint8_t sha204c_wakeup(uint8_t *response);
 uint8_t sha204c_send_and_receive(struct sha204_send_and_receive_parameters *args);
-//! @}
+/*! @}*/
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c
index e2137bcd4f88..f46c516d5406 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.c
@@ -45,10 +45,10 @@
  * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
  */
 
-#include <string.h>                    // needed for memcpy()
+#include <string.h>                    /* needed for memcpy()*/
 
-#include "sha204_lib_return_codes.h"   // declarations of function return codes
-#include "sha204_command_marshaling.h"    // definitions and declarations for the Command module
+#include "sha204_lib_return_codes.h"   /* declarations of function return codes*/
+#include "sha204_command_marshaling.h"    /* definitions and declarations for the Command module*/
 
 /** \brief This function checks the parameters for sha204m_execute().
  *
@@ -59,99 +59,100 @@ static uint8_t sha204m_check_parameters(struct sha204_command_parameters *args)
 {
 #ifdef SHA204_CHECK_PARAMETERS
 
-	uint8_t len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
-	if (!args->tx_buffer || args->tx_size < len || args->rx_size < SHA204_RSP_SIZE_MIN || !args->rx_buffer)
-		return SHA204_BAD_PARAM;
-
-	if ((args->data_len_1 > 0 && !args->data_1) || (args->data_len_2 > 0 && !args->data_2) || (args->data_len_3 > 0 && !args->data_3))
-		return SHA204_BAD_PARAM;
-
-	// Check parameters depending on op-code.
-	switch (args->op_code) {
-	case SHA204_CHECKMAC:
-		if (
-				// no null pointers allowed
-				!args->data_1 || !args->data_2
-				// No reserved bits should be set.
-				|| (args->param_1 | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
-				// key_id > 15 not allowed
-				|| args->param_2 > SHA204_KEY_ID_MAX
-			)
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_DERIVE_KEY:
-		if (((args->param_1 & ~DERIVE_KEY_RANDOM_FLAG) != 0)
-					 || (args->param_2 > SHA204_KEY_ID_MAX))
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_DEVREV:
-		break;
-
-	case SHA204_GENDIG:
-		if ((args->param_1 != GENDIG_ZONE_OTP) && (args->param_1 != GENDIG_ZONE_DATA))
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_HMAC:
-		if ((args->param_1 & ~HMAC_MODE_MASK) != 0)
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_LOCK:
-		if (((args->param_1 & ~LOCK_ZONE_MASK) != 0)
-					|| ((args->param_1 & LOCK_ZONE_NO_CRC) && (args->param_2 != 0)))
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_MAC:
-		if (((args->param_1 & ~MAC_MODE_MASK) != 0)
-					|| (((args->param_1 & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->data_1))
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_NONCE:
-		if (!args->data_1
-				|| (args->param_1 > NONCE_MODE_PASSTHROUGH)
-				|| (args->param_1 == NONCE_MODE_INVALID)
-			)
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_PAUSE:
-		break;
-
-	case SHA204_RANDOM:
-		if (args->param_1 > RANDOM_NO_SEED_UPDATE)
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_READ:
-		if (((args->param_1 & ~READ_ZONE_MASK) != 0)
-					|| ((args->param_1 & READ_ZONE_MODE_32_BYTES) && (args->param_1 == SHA204_ZONE_OTP)))
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_UPDATE_EXTRA:
-		if (args->param_1 > UPDATE_CONFIG_BYTE_86)
-			return SHA204_BAD_PARAM;
-		break;
-
-	case SHA204_WRITE:
-		if (!args->data_1 || ((args->param_1 & ~WRITE_ZONE_MASK) != 0))
-			return SHA204_BAD_PARAM;
-		break;
-
-	default:
-		// unknown op-code
-		return SHA204_BAD_PARAM;
-	}
-
-	return SHA204_SUCCESS;
+    uint8_t len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
+    if (!args->tx_buffer || args->tx_size < len || args->rx_size < SHA204_RSP_SIZE_MIN || !args->rx_buffer)
+        return SHA204_BAD_PARAM;
+
+    if ((args->data_len_1 > 0 && !args->data_1) || (args->data_len_2 > 0 && !args->data_2) || (args->data_len_3 > 0 && !args->data_3))
+        return SHA204_BAD_PARAM;
+
+    /* Check parameters depending on op-code.*/
+    switch (args->op_code)
+    {
+    case SHA204_CHECKMAC:
+        if (
+                /* no null pointers allowed*/
+                !args->data_1 || !args->data_2
+                /* No reserved bits should be set.*/
+                || (args->param_1 | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
+                /* key_id > 15 not allowed*/
+                || args->param_2 > SHA204_KEY_ID_MAX
+            )
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_DERIVE_KEY:
+        if (((args->param_1 & ~DERIVE_KEY_RANDOM_FLAG) != 0)
+                     || (args->param_2 > SHA204_KEY_ID_MAX))
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_DEVREV:
+        break;
+
+    case SHA204_GENDIG:
+        if ((args->param_1 != GENDIG_ZONE_OTP) && (args->param_1 != GENDIG_ZONE_DATA))
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_HMAC:
+        if ((args->param_1 & ~HMAC_MODE_MASK) != 0)
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_LOCK:
+        if (((args->param_1 & ~LOCK_ZONE_MASK) != 0)
+                    || ((args->param_1 & LOCK_ZONE_NO_CRC) && (args->param_2 != 0)))
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_MAC:
+        if (((args->param_1 & ~MAC_MODE_MASK) != 0)
+                    || (((args->param_1 & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->data_1))
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_NONCE:
+        if (!args->data_1
+                || (args->param_1 > NONCE_MODE_PASSTHROUGH)
+                || (args->param_1 == NONCE_MODE_INVALID)
+            )
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_PAUSE:
+        break;
+
+    case SHA204_RANDOM:
+        if (args->param_1 > RANDOM_NO_SEED_UPDATE)
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_READ:
+        if (((args->param_1 & ~READ_ZONE_MASK) != 0)
+                    || ((args->param_1 & READ_ZONE_MODE_32_BYTES) && (args->param_1 == SHA204_ZONE_OTP)))
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_UPDATE_EXTRA:
+        if (args->param_1 > UPDATE_CONFIG_BYTE_86)
+            return SHA204_BAD_PARAM;
+        break;
+
+    case SHA204_WRITE:
+        if (!args->data_1 || ((args->param_1 & ~WRITE_ZONE_MASK) != 0))
+            return SHA204_BAD_PARAM;
+        break;
+
+    default:
+        /* unknown op-code*/
+        return SHA204_BAD_PARAM;
+    }
+
+    return SHA204_SUCCESS;
 
 #else
-	return SHA204_SUCCESS;
+    return SHA204_SUCCESS;
 #endif
 }
 
@@ -162,131 +163,135 @@ static uint8_t sha204m_check_parameters(struct sha204_command_parameters *args)
  */
 uint8_t sha204m_execute(struct sha204_command_parameters *args)
 {
-	uint8_t *p_buffer;
-	uint8_t len;
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer
-	};
-
-	uint8_t ret_code = sha204m_check_parameters(args);
-	if (ret_code != SHA204_SUCCESS)
-		return ret_code;
-
-	// Supply delays and response size.
-	switch (args->op_code) {
-	case SHA204_CHECKMAC:
-		comm_parameters.poll_delay = CHECKMAC_DELAY;
-		comm_parameters.poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY;
-		comm_parameters.rx_size = CHECKMAC_RSP_SIZE;
-		break;
-
-	case SHA204_DERIVE_KEY:
-		comm_parameters.poll_delay = DERIVE_KEY_DELAY;
-		comm_parameters.poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY;
-		comm_parameters.rx_size = DERIVE_KEY_RSP_SIZE;
-		break;
-
-	case SHA204_DEVREV:
-		comm_parameters.poll_delay = DEVREV_DELAY;
-		comm_parameters.poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY;
-		comm_parameters.rx_size = DEVREV_RSP_SIZE;
-		break;
-
-	case SHA204_GENDIG:
-		comm_parameters.poll_delay = GENDIG_DELAY;
-		comm_parameters.poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY;
-		comm_parameters.rx_size = GENDIG_RSP_SIZE;
-		break;
-
-	case SHA204_HMAC:
-		comm_parameters.poll_delay = HMAC_DELAY;
-		comm_parameters.poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY;
-		comm_parameters.rx_size = HMAC_RSP_SIZE;
-		break;
-
-	case SHA204_LOCK:
-		comm_parameters.poll_delay = LOCK_DELAY;
-		comm_parameters.poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY;
-		comm_parameters.rx_size = LOCK_RSP_SIZE;
-		break;
-
-	case SHA204_MAC:
-		comm_parameters.poll_delay = MAC_DELAY;
-		comm_parameters.poll_timeout = MAC_EXEC_MAX - MAC_DELAY;
-		comm_parameters.rx_size = MAC_RSP_SIZE;
-		break;
-
-	case SHA204_NONCE:
-		comm_parameters.poll_delay = NONCE_DELAY;
-		comm_parameters.poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY;
-		comm_parameters.rx_size = args->param_1 == NONCE_MODE_PASSTHROUGH
-							? NONCE_RSP_SIZE_SHORT : NONCE_RSP_SIZE_LONG;
-		break;
-
-	case SHA204_PAUSE:
-		comm_parameters.poll_delay = PAUSE_DELAY;
-		comm_parameters.poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY;
-		comm_parameters.rx_size = PAUSE_RSP_SIZE;
-		break;
-
-	case SHA204_RANDOM:
-		comm_parameters.poll_delay = RANDOM_DELAY;
-		comm_parameters.poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY;
-		comm_parameters.rx_size = RANDOM_RSP_SIZE;
-		break;
-
-	case SHA204_READ:
-		comm_parameters.poll_delay = READ_DELAY;
-		comm_parameters.poll_timeout = READ_EXEC_MAX - READ_DELAY;
-		comm_parameters.rx_size = (args->param_1 & SHA204_ZONE_COUNT_FLAG)
-							? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
-		break;
-
-	case SHA204_UPDATE_EXTRA:
-		comm_parameters.poll_delay = UPDATE_DELAY;
-		comm_parameters.poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY;
-		comm_parameters.rx_size = UPDATE_RSP_SIZE;
-		break;
-
-	case SHA204_WRITE:
-		comm_parameters.poll_delay = WRITE_DELAY;
-		comm_parameters.poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY;
-		comm_parameters.rx_size = WRITE_RSP_SIZE;
-		break;
-
-	default:
-		comm_parameters.poll_delay = 0;
-		comm_parameters.poll_timeout = SHA204_COMMAND_EXEC_MAX;
-		comm_parameters.rx_size = args->rx_size;
-	}
-
-	// Assemble command.
-	len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
-	p_buffer = args->tx_buffer;
-	*p_buffer++ = len;
-	*p_buffer++ = args->op_code;
-	*p_buffer++ = args->param_1;
-	*p_buffer++ = args->param_2 & 0xFF;
-	*p_buffer++ = args->param_2 >> 8;
-
-	if (args->data_len_1 > 0) {
-		memcpy(p_buffer, args->data_1, args->data_len_1);
-		p_buffer += args->data_len_1;
-	}
-	if (args->data_len_2 > 0) {
-		memcpy(p_buffer, args->data_2, args->data_len_2);
-		p_buffer += args->data_len_2;
-	}
-	if (args->data_len_3 > 0) {
-		memcpy(p_buffer, args->data_3, args->data_len_3);
-		p_buffer += args->data_len_3;
-	}
-
-	sha204c_calculate_crc(len - SHA204_CRC_SIZE, args->tx_buffer, p_buffer);
-
-	// Send command and receive response.
-	return sha204c_send_and_receive(&comm_parameters);
+    uint8_t *p_buffer;
+    uint8_t len;
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer
+    };
+
+    uint8_t ret_code = sha204m_check_parameters(args);
+    if (ret_code != SHA204_SUCCESS)
+        return ret_code;
+
+    /* Supply delays and response size.*/
+    switch (args->op_code)
+    {
+    case SHA204_CHECKMAC:
+        comm_parameters.poll_delay = CHECKMAC_DELAY;
+        comm_parameters.poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY;
+        comm_parameters.rx_size = CHECKMAC_RSP_SIZE;
+        break;
+
+    case SHA204_DERIVE_KEY:
+        comm_parameters.poll_delay = DERIVE_KEY_DELAY;
+        comm_parameters.poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY;
+        comm_parameters.rx_size = DERIVE_KEY_RSP_SIZE;
+        break;
+
+    case SHA204_DEVREV:
+        comm_parameters.poll_delay = DEVREV_DELAY;
+        comm_parameters.poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY;
+        comm_parameters.rx_size = DEVREV_RSP_SIZE;
+        break;
+
+    case SHA204_GENDIG:
+        comm_parameters.poll_delay = GENDIG_DELAY;
+        comm_parameters.poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY;
+        comm_parameters.rx_size = GENDIG_RSP_SIZE;
+        break;
+
+    case SHA204_HMAC:
+        comm_parameters.poll_delay = HMAC_DELAY;
+        comm_parameters.poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY;
+        comm_parameters.rx_size = HMAC_RSP_SIZE;
+        break;
+
+    case SHA204_LOCK:
+        comm_parameters.poll_delay = LOCK_DELAY;
+        comm_parameters.poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY;
+        comm_parameters.rx_size = LOCK_RSP_SIZE;
+        break;
+
+    case SHA204_MAC:
+        comm_parameters.poll_delay = MAC_DELAY;
+        comm_parameters.poll_timeout = MAC_EXEC_MAX - MAC_DELAY;
+        comm_parameters.rx_size = MAC_RSP_SIZE;
+        break;
+
+    case SHA204_NONCE:
+        comm_parameters.poll_delay = NONCE_DELAY;
+        comm_parameters.poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY;
+        comm_parameters.rx_size = args->param_1 == NONCE_MODE_PASSTHROUGH
+                            ? NONCE_RSP_SIZE_SHORT : NONCE_RSP_SIZE_LONG;
+        break;
+
+    case SHA204_PAUSE:
+        comm_parameters.poll_delay = PAUSE_DELAY;
+        comm_parameters.poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY;
+        comm_parameters.rx_size = PAUSE_RSP_SIZE;
+        break;
+
+    case SHA204_RANDOM:
+        comm_parameters.poll_delay = RANDOM_DELAY;
+        comm_parameters.poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY;
+        comm_parameters.rx_size = RANDOM_RSP_SIZE;
+        break;
+
+    case SHA204_READ:
+        comm_parameters.poll_delay = READ_DELAY;
+        comm_parameters.poll_timeout = READ_EXEC_MAX - READ_DELAY;
+        comm_parameters.rx_size = (args->param_1 & SHA204_ZONE_COUNT_FLAG)
+                            ? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
+        break;
+
+    case SHA204_UPDATE_EXTRA:
+        comm_parameters.poll_delay = UPDATE_DELAY;
+        comm_parameters.poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY;
+        comm_parameters.rx_size = UPDATE_RSP_SIZE;
+        break;
+
+    case SHA204_WRITE:
+        comm_parameters.poll_delay = WRITE_DELAY;
+        comm_parameters.poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY;
+        comm_parameters.rx_size = WRITE_RSP_SIZE;
+        break;
+
+    default:
+        comm_parameters.poll_delay = 0;
+        comm_parameters.poll_timeout = SHA204_COMMAND_EXEC_MAX;
+        comm_parameters.rx_size = args->rx_size;
+    }
+
+    /* Assemble command.*/
+    len = args->data_len_1 + args->data_len_2 + args->data_len_3 + SHA204_CMD_SIZE_MIN;
+    p_buffer = args->tx_buffer;
+    *p_buffer++ = len;
+    *p_buffer++ = args->op_code;
+    *p_buffer++ = args->param_1;
+    *p_buffer++ = args->param_2 & 0xFF;
+    *p_buffer++ = args->param_2 >> 8;
+
+    if (args->data_len_1 > 0)
+    {
+        memcpy(p_buffer, args->data_1, args->data_len_1);
+        p_buffer += args->data_len_1;
+    }
+    if (args->data_len_2 > 0)
+    {
+        memcpy(p_buffer, args->data_2, args->data_len_2);
+        p_buffer += args->data_len_2;
+    }
+    if (args->data_len_3 > 0)
+    {
+        memcpy(p_buffer, args->data_3, args->data_len_3);
+        p_buffer += args->data_len_3;
+    }
+
+    sha204c_calculate_crc(len - SHA204_CRC_SIZE, args->tx_buffer, p_buffer);
+
+    /* Send command and receive response.*/
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -296,35 +301,35 @@ uint8_t sha204m_execute(struct sha204_command_parameters *args)
  */
 uint8_t sha204m_check_mac(struct sha204_check_mac_parameters *args)
 {
-	if (		// no null pointers allowed
-				!args->tx_buffer || !args->rx_buffer || !args->client_response || !args->other_data
-				// No reserved bits should be set.
-				|| (args->mode | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
-				// key_id > 15 not allowed
-				|| args->key_id > SHA204_KEY_ID_MAX)
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = CHECKMAC_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_CHECKMAC;
-	args->tx_buffer[CHECKMAC_MODE_IDX] = args->mode & CHECKMAC_MODE_MASK;
-	args->tx_buffer[CHECKMAC_KEYID_IDX]= args->key_id;
-	args->tx_buffer[CHECKMAC_KEYID_IDX + 1] = 0;
-	if (args->client_challenge == NULL)
-		memset(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], 0, CHECKMAC_CLIENT_CHALLENGE_SIZE);
-	else
-		memcpy(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], args->client_challenge, CHECKMAC_CLIENT_CHALLENGE_SIZE);
-
-	memcpy(&args->tx_buffer[CHECKMAC_CLIENT_RESPONSE_IDX], args->client_response, CHECKMAC_CLIENT_RESPONSE_SIZE);
-	memcpy(&args->tx_buffer[CHECKMAC_DATA_IDX], args->other_data, CHECKMAC_OTHER_DATA_SIZE);
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = CHECKMAC_RSP_SIZE,
-		.poll_delay = CHECKMAC_DELAY,
-		.poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (        /* no null pointers allowed*/
+                !args->tx_buffer || !args->rx_buffer || !args->client_response || !args->other_data
+                /* No reserved bits should be set.*/
+                || (args->mode | CHECKMAC_MODE_MASK) != CHECKMAC_MODE_MASK
+                /* key_id > 15 not allowed*/
+                || args->key_id > SHA204_KEY_ID_MAX)
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = CHECKMAC_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_CHECKMAC;
+    args->tx_buffer[CHECKMAC_MODE_IDX] = args->mode & CHECKMAC_MODE_MASK;
+    args->tx_buffer[CHECKMAC_KEYID_IDX]= args->key_id;
+    args->tx_buffer[CHECKMAC_KEYID_IDX + 1] = 0;
+    if (args->client_challenge == NULL)
+        memset(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], 0, CHECKMAC_CLIENT_CHALLENGE_SIZE);
+    else
+        memcpy(&args->tx_buffer[CHECKMAC_CLIENT_CHALLENGE_IDX], args->client_challenge, CHECKMAC_CLIENT_CHALLENGE_SIZE);
+
+    memcpy(&args->tx_buffer[CHECKMAC_CLIENT_RESPONSE_IDX], args->client_response, CHECKMAC_CLIENT_RESPONSE_SIZE);
+    memcpy(&args->tx_buffer[CHECKMAC_DATA_IDX], args->other_data, CHECKMAC_OTHER_DATA_SIZE);
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = CHECKMAC_RSP_SIZE,
+        .poll_delay = CHECKMAC_DELAY,
+        .poll_timeout = CHECKMAC_EXEC_MAX - CHECKMAC_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -334,30 +339,30 @@ uint8_t sha204m_check_mac(struct sha204_check_mac_parameters *args)
  */
 uint8_t sha204m_derive_key(struct sha204_derive_key_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || ((args->use_random & ~DERIVE_KEY_RANDOM_FLAG) != 0)
-				 || (args->target_key > SHA204_KEY_ID_MAX))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DERIVE_KEY;
-	args->tx_buffer[DERIVE_KEY_RANDOM_IDX] = args->use_random;
-	args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX] = args->target_key;
-	args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX + 1] = 0;
-	if (args->mac != NULL)
-	{
-		memcpy(&args->tx_buffer[DERIVE_KEY_MAC_IDX], args->mac, DERIVE_KEY_MAC_SIZE);
-		args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_LARGE;
-	}
-	else
-		args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_SMALL;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = DERIVE_KEY_RSP_SIZE,
-		.poll_delay = DERIVE_KEY_DELAY,
-		.poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || ((args->use_random & ~DERIVE_KEY_RANDOM_FLAG) != 0)
+                 || (args->target_key > SHA204_KEY_ID_MAX))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DERIVE_KEY;
+    args->tx_buffer[DERIVE_KEY_RANDOM_IDX] = args->use_random;
+    args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX] = args->target_key;
+    args->tx_buffer[DERIVE_KEY_TARGETKEY_IDX + 1] = 0;
+    if (args->mac != NULL)
+    {
+        memcpy(&args->tx_buffer[DERIVE_KEY_MAC_IDX], args->mac, DERIVE_KEY_MAC_SIZE);
+        args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_LARGE;
+    }
+    else
+        args->tx_buffer[SHA204_COUNT_IDX] = DERIVE_KEY_COUNT_SMALL;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = DERIVE_KEY_RSP_SIZE,
+        .poll_delay = DERIVE_KEY_DELAY,
+        .poll_timeout = DERIVE_KEY_EXEC_MAX - DERIVE_KEY_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -367,25 +372,25 @@ uint8_t sha204m_derive_key(struct sha204_derive_key_parameters *args)
  */
 uint8_t sha204m_dev_rev(struct sha204_dev_rev_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer)
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = DEVREV_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DEVREV;
-
-	// Parameters are 0.
-	args->tx_buffer[DEVREV_PARAM1_IDX] =
-	args->tx_buffer[DEVREV_PARAM2_IDX] =
-	args->tx_buffer[DEVREV_PARAM2_IDX + 1] = 0;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = DEVREV_RSP_SIZE,
-		.poll_delay = DEVREV_DELAY,
-		.poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer)
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = DEVREV_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_DEVREV;
+
+    /* Parameters are 0.*/
+    args->tx_buffer[DEVREV_PARAM1_IDX] =
+    args->tx_buffer[DEVREV_PARAM2_IDX] =
+    args->tx_buffer[DEVREV_PARAM2_IDX + 1] = 0;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = DEVREV_RSP_SIZE,
+        .poll_delay = DEVREV_DELAY,
+        .poll_timeout = DEVREV_EXEC_MAX - DEVREV_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -395,34 +400,34 @@ uint8_t sha204m_dev_rev(struct sha204_dev_rev_parameters *args)
  */
 uint8_t sha204m_gen_dig(struct sha204_gen_dig_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer
-				|| ((args->zone != GENDIG_ZONE_OTP) && (args->zone != GENDIG_ZONE_DATA)))
-		return SHA204_BAD_PARAM;
-
-	if (((args->zone == GENDIG_ZONE_OTP) && (args->key_id > SHA204_OTP_BLOCK_MAX))
-				|| ((args->zone == GENDIG_ZONE_DATA) && (args->key_id > SHA204_KEY_ID_MAX)))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_GENDIG;
-	args->tx_buffer[GENDIG_ZONE_IDX] = args->zone;
-	args->tx_buffer[GENDIG_KEYID_IDX] = args->key_id;
-	args->tx_buffer[GENDIG_KEYID_IDX + 1] = 0;
-	if (args->other_data != NULL)
-	{
-		memcpy(&args->tx_buffer[GENDIG_DATA_IDX], args->other_data, GENDIG_OTHER_DATA_SIZE);
-		args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT_DATA;
-	}
-	else
-		args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = GENDIG_RSP_SIZE,
-		.poll_delay = GENDIG_DELAY,
-		.poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer
+                || ((args->zone != GENDIG_ZONE_OTP) && (args->zone != GENDIG_ZONE_DATA)))
+        return SHA204_BAD_PARAM;
+
+    if (((args->zone == GENDIG_ZONE_OTP) && (args->key_id > SHA204_OTP_BLOCK_MAX))
+                || ((args->zone == GENDIG_ZONE_DATA) && (args->key_id > SHA204_KEY_ID_MAX)))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_GENDIG;
+    args->tx_buffer[GENDIG_ZONE_IDX] = args->zone;
+    args->tx_buffer[GENDIG_KEYID_IDX] = args->key_id;
+    args->tx_buffer[GENDIG_KEYID_IDX + 1] = 0;
+    if (args->other_data != NULL)
+    {
+        memcpy(&args->tx_buffer[GENDIG_DATA_IDX], args->other_data, GENDIG_OTHER_DATA_SIZE);
+        args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT_DATA;
+    }
+    else
+        args->tx_buffer[SHA204_COUNT_IDX] = GENDIG_COUNT;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = GENDIG_RSP_SIZE,
+        .poll_delay = GENDIG_DELAY,
+        .poll_timeout = GENDIG_EXEC_MAX - GENDIG_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -432,26 +437,26 @@ uint8_t sha204m_gen_dig(struct sha204_gen_dig_parameters *args)
  */
 uint8_t sha204m_hmac(struct sha204_hmac_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~HMAC_MODE_MASK) != 0))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = HMAC_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_HMAC;
-	args->tx_buffer[HMAC_MODE_IDX] = args->mode;
-
-	// Although valid key identifiers are only
-	// from 0 to 15, all 16 bits are used in the HMAC message.
-	args->tx_buffer[HMAC_KEYID_IDX] = args->key_id & 0xFF;
-	args->tx_buffer[HMAC_KEYID_IDX + 1] = args->key_id >> 8;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = HMAC_RSP_SIZE,
-		.poll_delay = HMAC_DELAY,
-		.poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~HMAC_MODE_MASK) != 0))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = HMAC_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_HMAC;
+    args->tx_buffer[HMAC_MODE_IDX] = args->mode;
+
+    /* Although valid key identifiers are only*/
+    /* from 0 to 15, all 16 bits are used in the HMAC message.*/
+    args->tx_buffer[HMAC_KEYID_IDX] = args->key_id & 0xFF;
+    args->tx_buffer[HMAC_KEYID_IDX + 1] = args->key_id >> 8;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = HMAC_RSP_SIZE,
+        .poll_delay = HMAC_DELAY,
+        .poll_timeout = HMAC_EXEC_MAX - HMAC_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -461,24 +466,24 @@ uint8_t sha204m_hmac(struct sha204_hmac_parameters *args)
  */
 uint8_t sha204m_lock(struct sha204_lock_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~LOCK_ZONE_MASK) != 0)
-				|| ((args->zone & LOCK_ZONE_NO_CRC) && (args->summary != 0)))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = LOCK_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_LOCK;
-	args->tx_buffer[LOCK_ZONE_IDX] = args->zone & LOCK_ZONE_MASK;
-	args->tx_buffer[LOCK_SUMMARY_IDX]= args->summary & 0xFF;
-	args->tx_buffer[LOCK_SUMMARY_IDX + 1]= args->summary >> 8;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = LOCK_RSP_SIZE,
-		.poll_delay = LOCK_DELAY,
-		.poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~LOCK_ZONE_MASK) != 0)
+                || ((args->zone & LOCK_ZONE_NO_CRC) && (args->summary != 0)))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = LOCK_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_LOCK;
+    args->tx_buffer[LOCK_ZONE_IDX] = args->zone & LOCK_ZONE_MASK;
+    args->tx_buffer[LOCK_SUMMARY_IDX]= args->summary & 0xFF;
+    args->tx_buffer[LOCK_SUMMARY_IDX + 1]= args->summary >> 8;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = LOCK_RSP_SIZE,
+        .poll_delay = LOCK_DELAY,
+        .poll_timeout = LOCK_EXEC_MAX - LOCK_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -488,29 +493,29 @@ uint8_t sha204m_lock(struct sha204_lock_parameters *args)
  */
 uint8_t sha204m_mac(struct sha204_mac_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~MAC_MODE_MASK) != 0)
-				|| (((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->challenge))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_SHORT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_MAC;
-	args->tx_buffer[MAC_MODE_IDX] = args->mode;
-	args->tx_buffer[MAC_KEYID_IDX] = args->key_id & 0xFF;
-	args->tx_buffer[MAC_KEYID_IDX + 1] = args->key_id >> 8;
-	if ((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0)
-	{
-		memcpy(&args->tx_buffer[MAC_CHALLENGE_IDX], args->challenge, MAC_CHALLENGE_SIZE);
-		args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_LONG;
-	}
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = MAC_RSP_SIZE,
-		.poll_delay = MAC_DELAY,
-		.poll_timeout = MAC_EXEC_MAX - MAC_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || ((args->mode & ~MAC_MODE_MASK) != 0)
+                || (((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0) && !args->challenge))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_SHORT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_MAC;
+    args->tx_buffer[MAC_MODE_IDX] = args->mode;
+    args->tx_buffer[MAC_KEYID_IDX] = args->key_id & 0xFF;
+    args->tx_buffer[MAC_KEYID_IDX + 1] = args->key_id >> 8;
+    if ((args->mode & MAC_MODE_BLOCK2_TEMPKEY) == 0)
+    {
+        memcpy(&args->tx_buffer[MAC_CHALLENGE_IDX], args->challenge, MAC_CHALLENGE_SIZE);
+        args->tx_buffer[SHA204_COUNT_IDX] = MAC_COUNT_LONG;
+    }
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = MAC_RSP_SIZE,
+        .poll_delay = MAC_DELAY,
+        .poll_timeout = MAC_EXEC_MAX - MAC_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -520,40 +525,40 @@ uint8_t sha204m_mac(struct sha204_mac_parameters *args)
  */
 uint8_t sha204m_nonce(struct sha204_nonce_parameters *args)
 {
-	uint8_t rx_size;
-
-	if (!args->tx_buffer || !args->rx_buffer || !args->num_in
-				|| (args->mode > NONCE_MODE_PASSTHROUGH) || (args->mode == NONCE_MODE_INVALID))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_NONCE;
-	args->tx_buffer[NONCE_MODE_IDX] = args->mode;
-
-	// 2. parameter is 0.
-	args->tx_buffer[NONCE_PARAM2_IDX] =
-	args->tx_buffer[NONCE_PARAM2_IDX + 1] = 0;
-
-	if (args->mode != NONCE_MODE_PASSTHROUGH)
-	{
-		memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE);
-		args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_SHORT;
-		rx_size = NONCE_RSP_SIZE_LONG;
-	}
-	else
-	{
-		memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE_PASSTHROUGH);
-		args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_LONG;
-		rx_size = NONCE_RSP_SIZE_SHORT;
-	}
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = rx_size,
-		.poll_delay = NONCE_DELAY,
-		.poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    uint8_t rx_size;
+
+    if (!args->tx_buffer || !args->rx_buffer || !args->num_in
+                || (args->mode > NONCE_MODE_PASSTHROUGH) || (args->mode == NONCE_MODE_INVALID))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_NONCE;
+    args->tx_buffer[NONCE_MODE_IDX] = args->mode;
+
+    /* 2. parameter is 0.*/
+    args->tx_buffer[NONCE_PARAM2_IDX] =
+    args->tx_buffer[NONCE_PARAM2_IDX + 1] = 0;
+
+    if (args->mode != NONCE_MODE_PASSTHROUGH)
+    {
+        memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE);
+        args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_SHORT;
+        rx_size = NONCE_RSP_SIZE_LONG;
+    }
+    else
+    {
+        memcpy(&args->tx_buffer[NONCE_INPUT_IDX], args->num_in, NONCE_NUMIN_SIZE_PASSTHROUGH);
+        args->tx_buffer[SHA204_COUNT_IDX] = NONCE_COUNT_LONG;
+        rx_size = NONCE_RSP_SIZE_SHORT;
+    }
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = rx_size,
+        .poll_delay = NONCE_DELAY,
+        .poll_timeout = NONCE_EXEC_MAX - NONCE_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -564,25 +569,25 @@ uint8_t sha204m_nonce(struct sha204_nonce_parameters *args)
  */
 uint8_t sha204m_pause(struct sha204_pause_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer)
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = PAUSE_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_PAUSE;
-	args->tx_buffer[PAUSE_SELECT_IDX] = args->selector;
-
-	// 2. parameter is 0.
-	args->tx_buffer[PAUSE_PARAM2_IDX] =
-	args->tx_buffer[PAUSE_PARAM2_IDX + 1] = 0;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = PAUSE_RSP_SIZE,
-		.poll_delay = PAUSE_DELAY,
-		.poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer)
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = PAUSE_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_PAUSE;
+    args->tx_buffer[PAUSE_SELECT_IDX] = args->selector;
+
+    /* 2. parameter is 0.*/
+    args->tx_buffer[PAUSE_PARAM2_IDX] =
+    args->tx_buffer[PAUSE_PARAM2_IDX + 1] = 0;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = PAUSE_RSP_SIZE,
+        .poll_delay = PAUSE_DELAY,
+        .poll_timeout = PAUSE_EXEC_MAX - PAUSE_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -592,25 +597,25 @@ uint8_t sha204m_pause(struct sha204_pause_parameters *args)
  */
 uint8_t sha204m_random(struct sha204_random_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || (args->mode > RANDOM_NO_SEED_UPDATE))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = RANDOM_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_RANDOM;
-	args->tx_buffer[RANDOM_MODE_IDX] = args->mode & RANDOM_SEED_UPDATE;
-
-	// 2. parameter is 0.
-	args->tx_buffer[RANDOM_PARAM2_IDX] =
-	args->tx_buffer[RANDOM_PARAM2_IDX + 1] = 0;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = RANDOM_RSP_SIZE,
-		.poll_delay = RANDOM_DELAY,
-		.poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || (args->mode > RANDOM_NO_SEED_UPDATE))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = RANDOM_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_RANDOM;
+    args->tx_buffer[RANDOM_MODE_IDX] = args->mode & RANDOM_SEED_UPDATE;
+
+    /* 2. parameter is 0.*/
+    args->tx_buffer[RANDOM_PARAM2_IDX] =
+    args->tx_buffer[RANDOM_PARAM2_IDX + 1] = 0;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = RANDOM_RSP_SIZE,
+        .poll_delay = RANDOM_DELAY,
+        .poll_timeout = RANDOM_EXEC_MAX - RANDOM_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -620,49 +625,52 @@ uint8_t sha204m_random(struct sha204_random_parameters *args)
  */
 uint8_t sha204m_read(struct sha204_read_parameters *args)
 {
-	uint8_t rx_size;
-	uint16_t address;
-
-	if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~READ_ZONE_MASK) != 0)
-				|| ((args->zone & READ_ZONE_MODE_32_BYTES) && (args->zone == SHA204_ZONE_OTP)))
-		return SHA204_BAD_PARAM;
-
-	// If we would just mask address bits, we would
-	// read from an address that was not intended.
-	address = args->address >> 2;
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG) {
-		if (address > SHA204_ADDRESS_MASK_CONFIG)
-			return SHA204_BAD_PARAM;
-	}		
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP) {
-		if (address > SHA204_ADDRESS_MASK_OTP)
-			// If we would just mask this bit, we would
-			// read from an address that was not intended.
-			return SHA204_BAD_PARAM;
-	}		
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA) {
-		if (address > SHA204_ADDRESS_MASK)
-			// If we would just mask this bit, we would
-			// read from an address that was not intended.
-			return SHA204_BAD_PARAM;
-	}
-
-	args->tx_buffer[SHA204_COUNT_IDX] = READ_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_READ;
-	args->tx_buffer[READ_ZONE_IDX] = args->zone;
-	args->tx_buffer[READ_ADDR_IDX] = (uint8_t) address;
-	args->tx_buffer[READ_ADDR_IDX + 1] = 0;
-
-	rx_size = (args->zone & SHA204_ZONE_COUNT_FLAG) ? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = rx_size,
-		.poll_delay = READ_DELAY,
-		.poll_timeout = READ_EXEC_MAX - READ_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    uint8_t rx_size;
+    uint16_t address;
+
+    if (!args->tx_buffer || !args->rx_buffer || ((args->zone & ~READ_ZONE_MASK) != 0)
+                || ((args->zone & READ_ZONE_MODE_32_BYTES) && (args->zone == SHA204_ZONE_OTP)))
+        return SHA204_BAD_PARAM;
+
+    /* If we would just mask address bits, we would*/
+    /* read from an address that was not intended.*/
+    address = args->address >> 2;
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG)
+    {
+        if (address > SHA204_ADDRESS_MASK_CONFIG)
+            return SHA204_BAD_PARAM;
+    }
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP)
+    {
+        if (address > SHA204_ADDRESS_MASK_OTP)
+            /* If we would just mask this bit, we would*/
+            /* read from an address that was not intended.*/
+            return SHA204_BAD_PARAM;
+    }
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA)
+    {
+        if (address > SHA204_ADDRESS_MASK)
+            /* If we would just mask this bit, we would*/
+            /* read from an address that was not intended.*/
+            return SHA204_BAD_PARAM;
+    }
+
+    args->tx_buffer[SHA204_COUNT_IDX] = READ_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_READ;
+    args->tx_buffer[READ_ZONE_IDX] = args->zone;
+    args->tx_buffer[READ_ADDR_IDX] = (uint8_t) address;
+    args->tx_buffer[READ_ADDR_IDX + 1] = 0;
+
+    rx_size = (args->zone & SHA204_ZONE_COUNT_FLAG) ? READ_32_RSP_SIZE : READ_4_RSP_SIZE;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = rx_size,
+        .poll_delay = READ_DELAY,
+        .poll_timeout = READ_EXEC_MAX - READ_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -672,23 +680,23 @@ uint8_t sha204m_read(struct sha204_read_parameters *args)
  */
 uint8_t sha204m_update_extra(struct sha204_update_extra_parameters *args)
 {
-	if (!args->tx_buffer || !args->rx_buffer || (args->mode > UPDATE_CONFIG_BYTE_86))
-		return SHA204_BAD_PARAM;
-
-	args->tx_buffer[SHA204_COUNT_IDX] = UPDATE_COUNT;
-	args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_UPDATE_EXTRA;
-	args->tx_buffer[UPDATE_MODE_IDX] = args->mode;
-	args->tx_buffer[UPDATE_VALUE_IDX] = args->new_value;
-	args->tx_buffer[UPDATE_VALUE_IDX + 1] = 0;
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = UPDATE_RSP_SIZE,
-		.poll_delay = UPDATE_DELAY,
-		.poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    if (!args->tx_buffer || !args->rx_buffer || (args->mode > UPDATE_CONFIG_BYTE_86))
+        return SHA204_BAD_PARAM;
+
+    args->tx_buffer[SHA204_COUNT_IDX] = UPDATE_COUNT;
+    args->tx_buffer[SHA204_OPCODE_IDX] = SHA204_UPDATE_EXTRA;
+    args->tx_buffer[UPDATE_MODE_IDX] = args->mode;
+    args->tx_buffer[UPDATE_VALUE_IDX] = args->new_value;
+    args->tx_buffer[UPDATE_VALUE_IDX + 1] = 0;
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = UPDATE_RSP_SIZE,
+        .poll_delay = UPDATE_DELAY,
+        .poll_timeout = UPDATE_EXEC_MAX - UPDATE_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
 
 
@@ -698,58 +706,61 @@ uint8_t sha204m_update_extra(struct sha204_update_extra_parameters *args)
  */
 uint8_t sha204m_write(struct sha204_write_parameters *args)
 {
-	uint8_t *p_command;
-	uint8_t count;
-	uint16_t address;
-
-	if (!args->tx_buffer || !args->rx_buffer || !args->new_value || ((args->zone & ~WRITE_ZONE_MASK) != 0))
-		return SHA204_BAD_PARAM;
-
-	// If we would just mask address bits, we would
-	// read from an address that was not intended.
-	address = args->address >> 2;
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG) {
-		if (address > SHA204_ADDRESS_MASK_CONFIG)
-			return SHA204_BAD_PARAM;
-	}		
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP) {
-		if (address > SHA204_ADDRESS_MASK_OTP)
-			// If we would just mask this bit, we would
-			// read from an address that was not intended.
-			return SHA204_BAD_PARAM;
-	}		
-	if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA) {
-		if (address > SHA204_ADDRESS_MASK)
-			// If we would just mask this bit, we would
-			// read from an address that was not intended.
-			return SHA204_BAD_PARAM;
-	}
-
-	p_command = &args->tx_buffer[SHA204_OPCODE_IDX];
-	*p_command++ = SHA204_WRITE;
-	*p_command++ = args->zone;
-	*p_command++ = (uint8_t) address;
-	*p_command++ = 0;
-
-	count = (args->zone & SHA204_ZONE_COUNT_FLAG) ? SHA204_ZONE_ACCESS_32 : SHA204_ZONE_ACCESS_4;
-	memcpy(p_command, args->new_value, count);
-	p_command += count;
-
-	if (args->mac != NULL)
-	{
-		memcpy(p_command, args->mac, WRITE_MAC_SIZE);
-		p_command += WRITE_MAC_SIZE;
-	}
-
-	// Supply count.
-	args->tx_buffer[SHA204_COUNT_IDX] = (uint8_t) (p_command - &args->tx_buffer[0] + SHA204_CRC_SIZE);
-
-	struct sha204_send_and_receive_parameters comm_parameters = {
-		.tx_buffer = args->tx_buffer,
-		.rx_buffer = args->rx_buffer,
-		.rx_size = WRITE_RSP_SIZE,
-		.poll_delay = WRITE_DELAY,
-		.poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY
-	};
-	return sha204c_send_and_receive(&comm_parameters);
+    uint8_t *p_command;
+    uint8_t count;
+    uint16_t address;
+
+    if (!args->tx_buffer || !args->rx_buffer || !args->new_value || ((args->zone & ~WRITE_ZONE_MASK) != 0))
+        return SHA204_BAD_PARAM;
+
+    /* If we would just mask address bits, we would*/
+    /* read from an address that was not intended.*/
+    address = args->address >> 2;
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_CONFIG)
+    {
+        if (address > SHA204_ADDRESS_MASK_CONFIG)
+            return SHA204_BAD_PARAM;
+    }
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_OTP)
+    {
+        if (address > SHA204_ADDRESS_MASK_OTP)
+            /* If we would just mask this bit, we would*/
+            /* read from an address that was not intended.*/
+            return SHA204_BAD_PARAM;
+    }
+    if ((args->zone & SHA204_ZONE_MASK) == SHA204_ZONE_DATA)
+    {
+        if (address > SHA204_ADDRESS_MASK)
+            /* If we would just mask this bit, we would*/
+            /* read from an address that was not intended.*/
+            return SHA204_BAD_PARAM;
+    }
+
+    p_command = &args->tx_buffer[SHA204_OPCODE_IDX];
+    *p_command++ = SHA204_WRITE;
+    *p_command++ = args->zone;
+    *p_command++ = (uint8_t) address;
+    *p_command++ = 0;
+
+    count = (args->zone & SHA204_ZONE_COUNT_FLAG) ? SHA204_ZONE_ACCESS_32 : SHA204_ZONE_ACCESS_4;
+    memcpy(p_command, args->new_value, count);
+    p_command += count;
+
+    if (args->mac != NULL)
+    {
+        memcpy(p_command, args->mac, WRITE_MAC_SIZE);
+        p_command += WRITE_MAC_SIZE;
+    }
+
+    /* Supply count.*/
+    args->tx_buffer[SHA204_COUNT_IDX] = (uint8_t) (p_command - &args->tx_buffer[0] + SHA204_CRC_SIZE);
+
+    struct sha204_send_and_receive_parameters comm_parameters = {
+        .tx_buffer = args->tx_buffer,
+        .rx_buffer = args->rx_buffer,
+        .rx_size = WRITE_RSP_SIZE,
+        .poll_delay = WRITE_DELAY,
+        .poll_timeout = WRITE_EXEC_MAX - WRITE_DELAY
+    };
+    return sha204c_send_and_receive(&comm_parameters);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h
index ed5bcc631b25..db809785a1ac 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_command_marshaling.h
@@ -79,442 +79,442 @@
 
 /** \todo Create doxygen groups. */
 
-//////////////////////////////////////////////////////////////////////
-// command op-code definitions
-#define SHA204_CHECKMAC                 ((uint8_t) 0x28)       //!< CheckMac command op-code
-#define SHA204_DERIVE_KEY               ((uint8_t) 0x1C)       //!< DeriveKey command op-code
-#define SHA204_DEVREV                   ((uint8_t) 0x30)       //!< DevRev command op-code
-#define SHA204_GENDIG                   ((uint8_t) 0x15)       //!< GenDig command op-code
-#define SHA204_HMAC                     ((uint8_t) 0x11)       //!< HMAC command op-code
-#define SHA204_LOCK                     ((uint8_t) 0x17)       //!< Lock command op-code
-#define SHA204_MAC                      ((uint8_t) 0x08)       //!< MAC command op-code
-#define SHA204_NONCE                    ((uint8_t) 0x16)       //!< Nonce command op-code
-#define SHA204_PAUSE                    ((uint8_t) 0x01)       //!< Pause command op-code
-#define SHA204_RANDOM                   ((uint8_t) 0x1B)       //!< Random command op-code
-#define SHA204_READ                     ((uint8_t) 0x02)       //!< Read command op-code
-#define SHA204_UPDATE_EXTRA             ((uint8_t) 0x20)       //!< UpdateExtra command op-code
-#define SHA204_WRITE                    ((uint8_t) 0x12)       //!< Write command op-code
-
-
-//////////////////////////////////////////////////////////////////////
-// packet size definitions
-#define SHA204_RSP_SIZE_VAL             ((uint8_t)  7)         //!< size of response packet containing four bytes of data
-
-//////////////////////////////////////////////////////////////////////
-// parameter range definitions
-#define SHA204_KEY_ID_MAX               ((uint8_t) 15)         //!< maximum value for key id
-#define SHA204_OTP_BLOCK_MAX            ((uint8_t)  1)         //!< maximum value for OTP block
-
-//////////////////////////////////////////////////////////////////////
-// definitions for command packet indexes common to all commands
-#define SHA204_COUNT_IDX                ( 0)                   //!< command packet index for count
-#define SHA204_OPCODE_IDX               ( 1)                   //!< command packet index for op-code
-#define SHA204_PARAM1_IDX               ( 2)                   //!< command packet index for first parameter
-#define SHA204_PARAM2_IDX               ( 3)                   //!< command packet index for second parameter
-#define SHA204_DATA_IDX                 ( 5)                   //!< command packet index for second parameter
-
-//////////////////////////////////////////////////////////////////////
-// zone definitions
-#define SHA204_ZONE_CONFIG              ((uint8_t)  0x00)      //!< Configuration zone
-#define SHA204_ZONE_OTP                 ((uint8_t)  0x01)      //!< OTP (One Time Programming) zone
-#define SHA204_ZONE_DATA                ((uint8_t)  0x02)      //!< Data zone
-#define SHA204_ZONE_MASK                ((uint8_t)  0x03)      //!< Zone mask
-#define SHA204_ZONE_COUNT_FLAG          ((uint8_t)  0x80)      //!< Zone bit 7 set: Access 32 bytes, otherwise 4 bytes.
-#define SHA204_ZONE_ACCESS_4            ((uint8_t)     4)      //!< Read or write 4 bytes.
-#define SHA204_ZONE_ACCESS_32           ((uint8_t)    32)      //!< Read or write 32 bytes.
-#define SHA204_ADDRESS_MASK_CONFIG      (         0x001F)      //!< Address bits 5 to 7 are 0 for Configuration zone.
-#define SHA204_ADDRESS_MASK_OTP         (         0x000F)      //!< Address bits 4 to 7 are 0 for OTP zone.
-#define SHA204_ADDRESS_MASK             (         0x007F)    //!< Address bit 7 to 15 are always 0.
-
-//////////////////////////////////////////////////////////////////////
-// CheckMAC command definitions
-#define CHECKMAC_MODE_IDX               SHA204_PARAM1_IDX      //!< CheckMAC command index for mode
-#define CHECKMAC_KEYID_IDX              SHA204_PARAM2_IDX      //!< CheckMAC command index for key identifier
-#define CHECKMAC_CLIENT_CHALLENGE_IDX   SHA204_DATA_IDX        //!< CheckMAC command index for client challenge
-#define CHECKMAC_CLIENT_RESPONSE_IDX    (37)                   //!< CheckMAC command index for client response
-#define CHECKMAC_DATA_IDX               (69)                   //!< CheckMAC command index for other data
-#define CHECKMAC_COUNT                  (84)                   //!< CheckMAC command packet size
-#define CHECKMAC_MODE_MASK              ((uint8_t) 0x27)       //!< CheckMAC mode bits 3, 4, 6, and 7 are 0.
-#define CHECKMAC_CLIENT_CHALLENGE_SIZE  (32)                   //!< CheckMAC size of client challenge
-#define CHECKMAC_CLIENT_RESPONSE_SIZE   (32)                   //!< CheckMAC size of client response
-#define CHECKMAC_OTHER_DATA_SIZE        (13)                   //!< CheckMAC size of "other data"
-#define CHECKMAC_CLIENT_COMMAND_SIZE    ( 4)                   //!< CheckMAC size of client command header size inside "other data"
-
-//////////////////////////////////////////////////////////////////////
-// DeriveKey command definitions
-#define DERIVE_KEY_RANDOM_IDX           SHA204_PARAM1_IDX      //!< DeriveKey command index for random bit
-#define DERIVE_KEY_TARGETKEY_IDX        SHA204_PARAM2_IDX      //!< DeriveKey command index for target slot
-#define DERIVE_KEY_MAC_IDX              SHA204_DATA_IDX        //!< DeriveKey command index for optional MAC
-#define DERIVE_KEY_COUNT_SMALL          SHA204_CMD_SIZE_MIN    //!< DeriveKey command packet size without MAC
-#define DERIVE_KEY_COUNT_LARGE          (39)                   //!< DeriveKey command packet size with MAC
-#define DERIVE_KEY_RANDOM_FLAG          ((uint8_t) 4)          //!< DeriveKey 1. parameter
-#define DERIVE_KEY_MAC_SIZE             (32)                   //!< DeriveKey MAC size
-
-//////////////////////////////////////////////////////////////////////
-// DevRev command definitions
-#define DEVREV_PARAM1_IDX               SHA204_PARAM1_IDX      //!< DevRev command index for 1. parameter (ignored)
-#define DEVREV_PARAM2_IDX               SHA204_PARAM2_IDX      //!< DevRev command index for 2. parameter (ignored)
-#define DEVREV_COUNT                    SHA204_CMD_SIZE_MIN    //!< DevRev command packet size
-
-//////////////////////////////////////////////////////////////////////
-// GenDig command definitions
-#define GENDIG_ZONE_IDX                 SHA204_PARAM1_IDX      //!< GenDig command index for zone
-#define GENDIG_KEYID_IDX                SHA204_PARAM2_IDX      //!< GenDig command index for key id
-#define GENDIG_DATA_IDX                 SHA204_DATA_IDX        //!< GenDig command index for optional data
-#define GENDIG_COUNT                    SHA204_CMD_SIZE_MIN    //!< GenDig command packet size without "other data"
-#define GENDIG_COUNT_DATA               (11)                   //!< GenDig command packet size with "other data"
-#define GENDIG_OTHER_DATA_SIZE          (4)                    //!< GenDig size of "other data"
-#define GENDIG_ZONE_OTP                 ((uint8_t) 1)          //!< GenDig zone id OTP
-#define GENDIG_ZONE_DATA                ((uint8_t) 2)          //!< GenDig zone id data
-
-//////////////////////////////////////////////////////////////////////
-// HMAC command definitions
-#define HMAC_MODE_IDX                   SHA204_PARAM1_IDX      //!< HMAC command index for mode
-#define HMAC_KEYID_IDX                  SHA204_PARAM2_IDX      //!< HMAC command index for key id
-#define HMAC_COUNT                      SHA204_CMD_SIZE_MIN    //!< HMAC command packet size
-#define HMAC_MODE_MASK                  ((uint8_t) 0x74)       //!< HMAC mode bits 0, 1, 3, and 7 are 0.
-
-//////////////////////////////////////////////////////////////////////
-// Lock command definitions
-#define LOCK_ZONE_IDX                   SHA204_PARAM1_IDX      //!< Lock command index for zone
-#define LOCK_SUMMARY_IDX                SHA204_PARAM2_IDX      //!< Lock command index for summary
-#define LOCK_COUNT                      SHA204_CMD_SIZE_MIN    //!< Lock command packet size
-#define LOCK_ZONE_NO_CONFIG             ((uint8_t) 0x01)       //!< Lock zone is OTP or Data
-#define LOCK_ZONE_NO_CRC                ((uint8_t) 0x80)       //!< Lock command: Ignore summary.
-#define LOCK_ZONE_MASK                  (0x81)                 //!< Lock parameter 1 bits 2 to 6 are 0.
-
-//////////////////////////////////////////////////////////////////////
-// Mac command definitions
-#define MAC_MODE_IDX                    SHA204_PARAM1_IDX      //!< MAC command index for mode
-#define MAC_KEYID_IDX                   SHA204_PARAM2_IDX      //!< MAC command index for key id
-#define MAC_CHALLENGE_IDX               SHA204_DATA_IDX        //!< MAC command index for optional challenge
-#define MAC_COUNT_SHORT                 SHA204_CMD_SIZE_MIN    //!< MAC command packet size without challenge
-#define MAC_COUNT_LONG                  (39)                   //!< MAC command packet size with challenge
-#define MAC_MODE_BLOCK2_TEMPKEY         ((uint8_t) 0x01)       //!< MAC mode bit   0: second SHA block from TempKey
-#define MAC_MODE_BLOCK1_TEMPKEY         ((uint8_t) 0x02)       //!< MAC mode bit   1: first SHA block from TempKey
-#define MAC_MODE_SOURCE_FLAG_MATCH      ((uint8_t) 0x04)       //!< MAC mode bit   2: match TempKey.SourceFlag
-#define MAC_MODE_PASSTHROUGH            ((uint8_t) 0x07)       //!< MAC mode bit 0-2: pass-through mode
-#define MAC_MODE_INCLUDE_OTP_88         ((uint8_t) 0x10)       //!< MAC mode bit   4: include first 88 OTP bits
-#define MAC_MODE_INCLUDE_OTP_64         ((uint8_t) 0x20)       //!< MAC mode bit   5: include first 64 OTP bits
-#define MAC_MODE_INCLUDE_SN             ((uint8_t) 0x50)       //!< MAC mode bit   6: include serial number
-#define MAC_CHALLENGE_SIZE              (32)                   //!< MAC size of challenge
-#define MAC_MODE_MASK                   ((uint8_t) 0x77)       //!< MAC mode bits 3 and 7 are 0.
-
-
-//////////////////////////////////////////////////////////////////////
-// Nonce command definitions
-#define NONCE_MODE_IDX                  SHA204_PARAM1_IDX      //!< Nonce command index for mode
-#define NONCE_PARAM2_IDX                SHA204_PARAM2_IDX      //!< Nonce command index for 2. parameter
-#define NONCE_INPUT_IDX                 SHA204_DATA_IDX        //!< Nonce command index for input data
-#define NONCE_COUNT_SHORT               (27)                   //!< Nonce command packet size for 20 bytes of data
-#define NONCE_COUNT_LONG                (39)                   //!< Nonce command packet size for 32 bytes of data
-#define NONCE_MODE_MASK                 ((uint8_t) 3)          //!< Nonce mode bits 2 to 7 are 0.
-#define NONCE_MODE_SEED_UPDATE          ((uint8_t) 0x00)       //!< Nonce mode: update seed
-#define NONCE_MODE_NO_SEED_UPDATE       ((uint8_t) 0x01)       //!< Nonce mode: do not update seed
-#define NONCE_MODE_INVALID              ((uint8_t) 0x02)       //!< Nonce mode 2 is invalid.
-#define NONCE_MODE_PASSTHROUGH          ((uint8_t) 0x03)       //!< Nonce mode: pass-through
-#define NONCE_NUMIN_SIZE                (20)                   //!< Nonce data length
-#define NONCE_NUMIN_SIZE_PASSTHROUGH    (32)                   //!< Nonce data length in pass-through mode (mode = 3)
-
-//////////////////////////////////////////////////////////////////////
-// Pause command definitions
-#define PAUSE_SELECT_IDX                SHA204_PARAM1_IDX      //!< Pause command index for Selector
-#define PAUSE_PARAM2_IDX                SHA204_PARAM2_IDX      //!< Pause command index for 2. parameter
-#define PAUSE_COUNT                     SHA204_CMD_SIZE_MIN    //!< Pause command packet size
-
-//////////////////////////////////////////////////////////////////////
-// Random command definitions
-#define RANDOM_MODE_IDX                 SHA204_PARAM1_IDX      //!< Random command index for mode
-#define RANDOM_PARAM2_IDX               SHA204_PARAM2_IDX      //!< Random command index for 2. parameter
-#define RANDOM_COUNT                    SHA204_CMD_SIZE_MIN    //!< Random command packet size
-#define RANDOM_SEED_UPDATE              ((uint8_t) 0x00)       //!< Random mode for automatic seed update
-#define RANDOM_NO_SEED_UPDATE           ((uint8_t) 0x01)       //!< Random mode for no seed update
-
-//////////////////////////////////////////////////////////////////////
-// Read command definitions
-#define READ_ZONE_IDX                   SHA204_PARAM1_IDX      //!< Read command index for zone
-#define READ_ADDR_IDX                   SHA204_PARAM2_IDX      //!< Read command index for address
-#define READ_COUNT                      SHA204_CMD_SIZE_MIN    //!< Read command packet size
-#define READ_ZONE_MASK                  ((uint8_t) 0x83)       //!< Read zone bits 2 to 6 are 0.
-#define READ_ZONE_MODE_32_BYTES         ((uint8_t) 0x80)       //!< Read mode: 32 bytes
-
-//////////////////////////////////////////////////////////////////////
-// UpdateExtra command definitions
-#define UPDATE_MODE_IDX                  SHA204_PARAM1_IDX     //!< UpdateExtra command index for mode
-#define UPDATE_VALUE_IDX                 SHA204_PARAM2_IDX     //!< UpdateExtra command index for new value
-#define UPDATE_COUNT                     SHA204_CMD_SIZE_MIN   //!< UpdateExtra command packet size
-#define UPDATE_CONFIG_BYTE_86            ((uint8_t) 0x01)      //!< UpdateExtra mode: update Config byte 86
-
-//////////////////////////////////////////////////////////////////////
-// Write command definitions
-#define WRITE_ZONE_IDX                  SHA204_PARAM1_IDX      //!< Write command index for zone
-#define WRITE_ADDR_IDX                  SHA204_PARAM2_IDX      //!< Write command index for address
-#define WRITE_VALUE_IDX                 SHA204_DATA_IDX        //!< Write command index for data
-#define WRITE_MAC_VS_IDX                ( 9)                   //!< Write command index for MAC following short data
-#define WRITE_MAC_VL_IDX                (37)                   //!< Write command index for MAC following long data
-#define WRITE_COUNT_SHORT               (11)                   //!< Write command packet size with short data and no MAC
-#define WRITE_COUNT_LONG                (39)                   //!< Write command packet size with long data and no MAC
-#define WRITE_COUNT_SHORT_MAC           (43)                   //!< Write command packet size with short data and MAC
-#define WRITE_COUNT_LONG_MAC            (71)                   //!< Write command packet size with long data and MAC
-#define WRITE_MAC_SIZE                  (32)                   //!< Write MAC size
-#define WRITE_ZONE_MASK                 ((uint8_t) 0xC1)       //!< Write zone bits 2 to 5 are 0.
-#define WRITE_ZONE_WITH_MAC             ((uint8_t) 0x40)       //!< Write zone bit 6: write encrypted with MAC
-
-//////////////////////////////////////////////////////////////////////
-// Response size definitions
-#define CHECKMAC_RSP_SIZE               SHA204_RSP_SIZE_MIN    //!< response size of DeriveKey command
-#define DERIVE_KEY_RSP_SIZE             SHA204_RSP_SIZE_MIN    //!< response size of DeriveKey command
-#define DEVREV_RSP_SIZE                 SHA204_RSP_SIZE_VAL    //!< response size of DevRev command returns 4 bytes
-#define GENDIG_RSP_SIZE                 SHA204_RSP_SIZE_MIN    //!< response size of GenDig command
-#define HMAC_RSP_SIZE                   SHA204_RSP_SIZE_MAX    //!< response size of HMAC command
-#define LOCK_RSP_SIZE                   SHA204_RSP_SIZE_MIN    //!< response size of Lock command
-#define MAC_RSP_SIZE                    SHA204_RSP_SIZE_MAX    //!< response size of MAC command
-#define NONCE_RSP_SIZE_SHORT            SHA204_RSP_SIZE_MIN    //!< response size of Nonce command with mode[0:1] = 3
-#define NONCE_RSP_SIZE_LONG             SHA204_RSP_SIZE_MAX    //!< response size of Nonce command
-#define PAUSE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    //!< response size of Pause command
-#define RANDOM_RSP_SIZE                 SHA204_RSP_SIZE_MAX    //!< response size of Random command
-#define READ_4_RSP_SIZE                 SHA204_RSP_SIZE_VAL    //!< response size of Read command when reading 4 bytes
-#define READ_32_RSP_SIZE                SHA204_RSP_SIZE_MAX    //!< response size of Read command when reading 32 bytes
-#define UPDATE_RSP_SIZE                 SHA204_RSP_SIZE_MIN    //!< response size of UpdateExtra command
-#define WRITE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    //!< response size of Write command
-
-//////////////////////////////////////////////////////////////////////
-// command timing definitions for typical execution times (ms)
-//! CheckMAC typical command delay
+*/
+/* command op-code definitions*/
+#define SHA204_CHECKMAC                 ((uint8_t) 0x28)       /*!< CheckMac command op-code*/
+#define SHA204_DERIVE_KEY               ((uint8_t) 0x1C)       /*!< DeriveKey command op-code*/
+#define SHA204_DEVREV                   ((uint8_t) 0x30)       /*!< DevRev command op-code*/
+#define SHA204_GENDIG                   ((uint8_t) 0x15)       /*!< GenDig command op-code*/
+#define SHA204_HMAC                     ((uint8_t) 0x11)       /*!< HMAC command op-code*/
+#define SHA204_LOCK                     ((uint8_t) 0x17)       /*!< Lock command op-code*/
+#define SHA204_MAC                      ((uint8_t) 0x08)       /*!< MAC command op-code*/
+#define SHA204_NONCE                    ((uint8_t) 0x16)       /*!< Nonce command op-code*/
+#define SHA204_PAUSE                    ((uint8_t) 0x01)       /*!< Pause command op-code*/
+#define SHA204_RANDOM                   ((uint8_t) 0x1B)       /*!< Random command op-code*/
+#define SHA204_READ                     ((uint8_t) 0x02)       /*!< Read command op-code*/
+#define SHA204_UPDATE_EXTRA             ((uint8_t) 0x20)       /*!< UpdateExtra command op-code*/
+#define SHA204_WRITE                    ((uint8_t) 0x12)       /*!< Write command op-code*/
+
+
+*/
+/* packet size definitions*/
+#define SHA204_RSP_SIZE_VAL             ((uint8_t)  7)         /*!< size of response packet containing four bytes of data*/
+
+*/
+/* parameter range definitions*/
+#define SHA204_KEY_ID_MAX               ((uint8_t) 15)         /*!< maximum value for key id*/
+#define SHA204_OTP_BLOCK_MAX            ((uint8_t)  1)         /*!< maximum value for OTP block*/
+
+*/
+/* definitions for command packet indexes common to all commands*/
+#define SHA204_COUNT_IDX                ( 0)                   /*!< command packet index for count*/
+#define SHA204_OPCODE_IDX               ( 1)                   /*!< command packet index for op-code*/
+#define SHA204_PARAM1_IDX               ( 2)                   /*!< command packet index for first parameter*/
+#define SHA204_PARAM2_IDX               ( 3)                   /*!< command packet index for second parameter*/
+#define SHA204_DATA_IDX                 ( 5)                   /*!< command packet index for second parameter*/
+
+*/
+/* zone definitions*/
+#define SHA204_ZONE_CONFIG              ((uint8_t)  0x00)      /*!< Configuration zone*/
+#define SHA204_ZONE_OTP                 ((uint8_t)  0x01)      /*!< OTP (One Time Programming) zone*/
+#define SHA204_ZONE_DATA                ((uint8_t)  0x02)      /*!< Data zone*/
+#define SHA204_ZONE_MASK                ((uint8_t)  0x03)      /*!< Zone mask*/
+#define SHA204_ZONE_COUNT_FLAG          ((uint8_t)  0x80)      /*!< Zone bit 7 set: Access 32 bytes, otherwise 4 bytes.*/
+#define SHA204_ZONE_ACCESS_4            ((uint8_t)     4)      /*!< Read or write 4 bytes.*/
+#define SHA204_ZONE_ACCESS_32           ((uint8_t)    32)      /*!< Read or write 32 bytes.*/
+#define SHA204_ADDRESS_MASK_CONFIG      (         0x001F)      /*!< Address bits 5 to 7 are 0 for Configuration zone.*/
+#define SHA204_ADDRESS_MASK_OTP         (         0x000F)      /*!< Address bits 4 to 7 are 0 for OTP zone.*/
+#define SHA204_ADDRESS_MASK             (         0x007F)    /*!< Address bit 7 to 15 are always 0.*/
+
+*/
+/* CheckMAC command definitions*/
+#define CHECKMAC_MODE_IDX               SHA204_PARAM1_IDX      /*!< CheckMAC command index for mode*/
+#define CHECKMAC_KEYID_IDX              SHA204_PARAM2_IDX      /*!< CheckMAC command index for key identifier*/
+#define CHECKMAC_CLIENT_CHALLENGE_IDX   SHA204_DATA_IDX        /*!< CheckMAC command index for client challenge*/
+#define CHECKMAC_CLIENT_RESPONSE_IDX    (37)                   /*!< CheckMAC command index for client response*/
+#define CHECKMAC_DATA_IDX               (69)                   /*!< CheckMAC command index for other data*/
+#define CHECKMAC_COUNT                  (84)                   /*!< CheckMAC command packet size*/
+#define CHECKMAC_MODE_MASK              ((uint8_t) 0x27)       /*!< CheckMAC mode bits 3, 4, 6, and 7 are 0.*/
+#define CHECKMAC_CLIENT_CHALLENGE_SIZE  (32)                   /*!< CheckMAC size of client challenge*/
+#define CHECKMAC_CLIENT_RESPONSE_SIZE   (32)                   /*!< CheckMAC size of client response*/
+#define CHECKMAC_OTHER_DATA_SIZE        (13)                   /*!< CheckMAC size of "other data"*/
+#define CHECKMAC_CLIENT_COMMAND_SIZE    ( 4)                   /*!< CheckMAC size of client command header size inside "other data"*/
+
+*/
+/* DeriveKey command definitions*/
+#define DERIVE_KEY_RANDOM_IDX           SHA204_PARAM1_IDX      /*!< DeriveKey command index for random bit*/
+#define DERIVE_KEY_TARGETKEY_IDX        SHA204_PARAM2_IDX      /*!< DeriveKey command index for target slot*/
+#define DERIVE_KEY_MAC_IDX              SHA204_DATA_IDX        /*!< DeriveKey command index for optional MAC*/
+#define DERIVE_KEY_COUNT_SMALL          SHA204_CMD_SIZE_MIN    /*!< DeriveKey command packet size without MAC*/
+#define DERIVE_KEY_COUNT_LARGE          (39)                   /*!< DeriveKey command packet size with MAC*/
+#define DERIVE_KEY_RANDOM_FLAG          ((uint8_t) 4)          /*!< DeriveKey 1. parameter*/
+#define DERIVE_KEY_MAC_SIZE             (32)                   /*!< DeriveKey MAC size*/
+
+*/
+/* DevRev command definitions*/
+#define DEVREV_PARAM1_IDX               SHA204_PARAM1_IDX      /*!< DevRev command index for 1. parameter (ignored)*/
+#define DEVREV_PARAM2_IDX               SHA204_PARAM2_IDX      /*!< DevRev command index for 2. parameter (ignored)*/
+#define DEVREV_COUNT                    SHA204_CMD_SIZE_MIN    /*!< DevRev command packet size*/
+
+*/
+/* GenDig command definitions*/
+#define GENDIG_ZONE_IDX                 SHA204_PARAM1_IDX      /*!< GenDig command index for zone*/
+#define GENDIG_KEYID_IDX                SHA204_PARAM2_IDX      /*!< GenDig command index for key id*/
+#define GENDIG_DATA_IDX                 SHA204_DATA_IDX        /*!< GenDig command index for optional data*/
+#define GENDIG_COUNT                    SHA204_CMD_SIZE_MIN    /*!< GenDig command packet size without "other data"*/
+#define GENDIG_COUNT_DATA               (11)                   /*!< GenDig command packet size with "other data"*/
+#define GENDIG_OTHER_DATA_SIZE          (4)                    /*!< GenDig size of "other data"*/
+#define GENDIG_ZONE_OTP                 ((uint8_t) 1)          /*!< GenDig zone id OTP*/
+#define GENDIG_ZONE_DATA                ((uint8_t) 2)          /*!< GenDig zone id data*/
+
+*/
+/* HMAC command definitions*/
+#define HMAC_MODE_IDX                   SHA204_PARAM1_IDX      /*!< HMAC command index for mode*/
+#define HMAC_KEYID_IDX                  SHA204_PARAM2_IDX      /*!< HMAC command index for key id*/
+#define HMAC_COUNT                      SHA204_CMD_SIZE_MIN    /*!< HMAC command packet size*/
+#define HMAC_MODE_MASK                  ((uint8_t) 0x74)       /*!< HMAC mode bits 0, 1, 3, and 7 are 0.*/
+
+*/
+/* Lock command definitions*/
+#define LOCK_ZONE_IDX                   SHA204_PARAM1_IDX      /*!< Lock command index for zone*/
+#define LOCK_SUMMARY_IDX                SHA204_PARAM2_IDX      /*!< Lock command index for summary*/
+#define LOCK_COUNT                      SHA204_CMD_SIZE_MIN    /*!< Lock command packet size*/
+#define LOCK_ZONE_NO_CONFIG             ((uint8_t) 0x01)       /*!< Lock zone is OTP or Data*/
+#define LOCK_ZONE_NO_CRC                ((uint8_t) 0x80)       /*!< Lock command: Ignore summary.*/
+#define LOCK_ZONE_MASK                  (0x81)                 /*!< Lock parameter 1 bits 2 to 6 are 0.*/
+
+*/
+/* Mac command definitions*/
+#define MAC_MODE_IDX                    SHA204_PARAM1_IDX      /*!< MAC command index for mode*/
+#define MAC_KEYID_IDX                   SHA204_PARAM2_IDX      /*!< MAC command index for key id*/
+#define MAC_CHALLENGE_IDX               SHA204_DATA_IDX        /*!< MAC command index for optional challenge*/
+#define MAC_COUNT_SHORT                 SHA204_CMD_SIZE_MIN    /*!< MAC command packet size without challenge*/
+#define MAC_COUNT_LONG                  (39)                   /*!< MAC command packet size with challenge*/
+#define MAC_MODE_BLOCK2_TEMPKEY         ((uint8_t) 0x01)       /*!< MAC mode bit   0: second SHA block from TempKey*/
+#define MAC_MODE_BLOCK1_TEMPKEY         ((uint8_t) 0x02)       /*!< MAC mode bit   1: first SHA block from TempKey*/
+#define MAC_MODE_SOURCE_FLAG_MATCH      ((uint8_t) 0x04)       /*!< MAC mode bit   2: match TempKey.SourceFlag*/
+#define MAC_MODE_PASSTHROUGH            ((uint8_t) 0x07)       /*!< MAC mode bit 0-2: pass-through mode*/
+#define MAC_MODE_INCLUDE_OTP_88         ((uint8_t) 0x10)       /*!< MAC mode bit   4: include first 88 OTP bits*/
+#define MAC_MODE_INCLUDE_OTP_64         ((uint8_t) 0x20)       /*!< MAC mode bit   5: include first 64 OTP bits*/
+#define MAC_MODE_INCLUDE_SN             ((uint8_t) 0x50)       /*!< MAC mode bit   6: include serial number*/
+#define MAC_CHALLENGE_SIZE              (32)                   /*!< MAC size of challenge*/
+#define MAC_MODE_MASK                   ((uint8_t) 0x77)       /*!< MAC mode bits 3 and 7 are 0.*/
+
+
+*/
+/* Nonce command definitions*/
+#define NONCE_MODE_IDX                  SHA204_PARAM1_IDX      /*!< Nonce command index for mode*/
+#define NONCE_PARAM2_IDX                SHA204_PARAM2_IDX      /*!< Nonce command index for 2. parameter*/
+#define NONCE_INPUT_IDX                 SHA204_DATA_IDX        /*!< Nonce command index for input data*/
+#define NONCE_COUNT_SHORT               (27)                   /*!< Nonce command packet size for 20 bytes of data*/
+#define NONCE_COUNT_LONG                (39)                   /*!< Nonce command packet size for 32 bytes of data*/
+#define NONCE_MODE_MASK                 ((uint8_t) 3)          /*!< Nonce mode bits 2 to 7 are 0.*/
+#define NONCE_MODE_SEED_UPDATE          ((uint8_t) 0x00)       /*!< Nonce mode: update seed*/
+#define NONCE_MODE_NO_SEED_UPDATE       ((uint8_t) 0x01)       /*!< Nonce mode: do not update seed*/
+#define NONCE_MODE_INVALID              ((uint8_t) 0x02)       /*!< Nonce mode 2 is invalid.*/
+#define NONCE_MODE_PASSTHROUGH          ((uint8_t) 0x03)       /*!< Nonce mode: pass-through*/
+#define NONCE_NUMIN_SIZE                (20)                   /*!< Nonce data length*/
+#define NONCE_NUMIN_SIZE_PASSTHROUGH    (32)                   /*!< Nonce data length in pass-through mode (mode = 3)*/
+
+*/
+/* Pause command definitions*/
+#define PAUSE_SELECT_IDX                SHA204_PARAM1_IDX      /*!< Pause command index for Selector*/
+#define PAUSE_PARAM2_IDX                SHA204_PARAM2_IDX      /*!< Pause command index for 2. parameter*/
+#define PAUSE_COUNT                     SHA204_CMD_SIZE_MIN    /*!< Pause command packet size*/
+
+*/
+/* Random command definitions*/
+#define RANDOM_MODE_IDX                 SHA204_PARAM1_IDX      /*!< Random command index for mode*/
+#define RANDOM_PARAM2_IDX               SHA204_PARAM2_IDX      /*!< Random command index for 2. parameter*/
+#define RANDOM_COUNT                    SHA204_CMD_SIZE_MIN    /*!< Random command packet size*/
+#define RANDOM_SEED_UPDATE              ((uint8_t) 0x00)       /*!< Random mode for automatic seed update*/
+#define RANDOM_NO_SEED_UPDATE           ((uint8_t) 0x01)       /*!< Random mode for no seed update*/
+
+*/
+/* Read command definitions*/
+#define READ_ZONE_IDX                   SHA204_PARAM1_IDX      /*!< Read command index for zone*/
+#define READ_ADDR_IDX                   SHA204_PARAM2_IDX      /*!< Read command index for address*/
+#define READ_COUNT                      SHA204_CMD_SIZE_MIN    /*!< Read command packet size*/
+#define READ_ZONE_MASK                  ((uint8_t) 0x83)       /*!< Read zone bits 2 to 6 are 0.*/
+#define READ_ZONE_MODE_32_BYTES         ((uint8_t) 0x80)       /*!< Read mode: 32 bytes*/
+
+*/
+/* UpdateExtra command definitions*/
+#define UPDATE_MODE_IDX                  SHA204_PARAM1_IDX     /*!< UpdateExtra command index for mode*/
+#define UPDATE_VALUE_IDX                 SHA204_PARAM2_IDX     /*!< UpdateExtra command index for new value*/
+#define UPDATE_COUNT                     SHA204_CMD_SIZE_MIN   /*!< UpdateExtra command packet size*/
+#define UPDATE_CONFIG_BYTE_86            ((uint8_t) 0x01)      /*!< UpdateExtra mode: update Config byte 86*/
+
+*/
+/* Write command definitions*/
+#define WRITE_ZONE_IDX                  SHA204_PARAM1_IDX      /*!< Write command index for zone*/
+#define WRITE_ADDR_IDX                  SHA204_PARAM2_IDX      /*!< Write command index for address*/
+#define WRITE_VALUE_IDX                 SHA204_DATA_IDX        /*!< Write command index for data*/
+#define WRITE_MAC_VS_IDX                ( 9)                   /*!< Write command index for MAC following short data*/
+#define WRITE_MAC_VL_IDX                (37)                   /*!< Write command index for MAC following long data*/
+#define WRITE_COUNT_SHORT               (11)                   /*!< Write command packet size with short data and no MAC*/
+#define WRITE_COUNT_LONG                (39)                   /*!< Write command packet size with long data and no MAC*/
+#define WRITE_COUNT_SHORT_MAC           (43)                   /*!< Write command packet size with short data and MAC*/
+#define WRITE_COUNT_LONG_MAC            (71)                   /*!< Write command packet size with long data and MAC*/
+#define WRITE_MAC_SIZE                  (32)                   /*!< Write MAC size*/
+#define WRITE_ZONE_MASK                 ((uint8_t) 0xC1)       /*!< Write zone bits 2 to 5 are 0.*/
+#define WRITE_ZONE_WITH_MAC             ((uint8_t) 0x40)       /*!< Write zone bit 6: write encrypted with MAC*/
+
+*/
+/* Response size definitions*/
+#define CHECKMAC_RSP_SIZE               SHA204_RSP_SIZE_MIN    /*!< response size of DeriveKey command*/
+#define DERIVE_KEY_RSP_SIZE             SHA204_RSP_SIZE_MIN    /*!< response size of DeriveKey command*/
+#define DEVREV_RSP_SIZE                 SHA204_RSP_SIZE_VAL    /*!< response size of DevRev command returns 4 bytes*/
+#define GENDIG_RSP_SIZE                 SHA204_RSP_SIZE_MIN    /*!< response size of GenDig command*/
+#define HMAC_RSP_SIZE                   SHA204_RSP_SIZE_MAX    /*!< response size of HMAC command*/
+#define LOCK_RSP_SIZE                   SHA204_RSP_SIZE_MIN    /*!< response size of Lock command*/
+#define MAC_RSP_SIZE                    SHA204_RSP_SIZE_MAX    /*!< response size of MAC command*/
+#define NONCE_RSP_SIZE_SHORT            SHA204_RSP_SIZE_MIN    /*!< response size of Nonce command with mode[0:1] = 3*/
+#define NONCE_RSP_SIZE_LONG             SHA204_RSP_SIZE_MAX    /*!< response size of Nonce command*/
+#define PAUSE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    /*!< response size of Pause command*/
+#define RANDOM_RSP_SIZE                 SHA204_RSP_SIZE_MAX    /*!< response size of Random command*/
+#define READ_4_RSP_SIZE                 SHA204_RSP_SIZE_VAL    /*!< response size of Read command when reading 4 bytes*/
+#define READ_32_RSP_SIZE                SHA204_RSP_SIZE_MAX    /*!< response size of Read command when reading 32 bytes*/
+#define UPDATE_RSP_SIZE                 SHA204_RSP_SIZE_MIN    /*!< response size of UpdateExtra command*/
+#define WRITE_RSP_SIZE                  SHA204_RSP_SIZE_MIN    /*!< response size of Write command*/
+
+*/
+/* command timing definitions for typical execution times (ms)*/
+/*! CheckMAC typical command delay*/
 #define CHECKMAC_DELAY                  (12)
 
-//! DeriveKey typical command delay
+/*! DeriveKey typical command delay*/
 #define DERIVE_KEY_DELAY                (14)
 
-//! DevRev typical command delay
-#define DEVREV_DELAY                    ( 1)  // 0.4 rounded up
+/*! DevRev typical command delay*/
+#define DEVREV_DELAY                    ( 1)  /* 0.4 rounded up*/
 
-//! GenDig typical command delay
+/*! GenDig typical command delay*/
 #define GENDIG_DELAY                    (11)
 
-//! HMAC typical command delay
+/*! HMAC typical command delay*/
 #define HMAC_DELAY                      (27)
 
-//! Lock typical command delay
+/*! Lock typical command delay*/
 #define LOCK_DELAY                      ( 5)
 
-//! MAC typical command delay
+/*! MAC typical command delay*/
 #define MAC_DELAY                       (12)
 
-//! Nonce typical command delay
+/*! Nonce typical command delay*/
 #define NONCE_DELAY                     (22)
 
-//! Pause typical command delay
-#define PAUSE_DELAY                     ( 1)  // 0.4 rounded up
+/*! Pause typical command delay*/
+#define PAUSE_DELAY                     ( 1)  /* 0.4 rounded up*/
 
-//! Random typical command delay
+/*! Random typical command delay*/
 #define RANDOM_DELAY                    (11)
 
-//! Read typical command delay
-#define READ_DELAY                      ( 1)  // 0.4 rounded up
+/*! Read typical command delay*/
+#define READ_DELAY                      ( 1)  /* 0.4 rounded up*/
 
-//! UpdateExtra typical command delay
+/*! UpdateExtra typical command delay*/
 #define UPDATE_DELAY                    ( 8)
 
-//! Write typical command delay
+/*! Write typical command delay*/
 #define WRITE_DELAY                     ( 4)
 
-//////////////////////////////////////////////////////////////////////
-// command timing definitions for maximum execution times (ms)
-//! CheckMAC maximum execution time
+*/
+/* command timing definitions for maximum execution times (ms)*/
+/*! CheckMAC maximum execution time*/
 #define CHECKMAC_EXEC_MAX                (38)
 
-//! DeriveKey maximum execution time
+/*! DeriveKey maximum execution time*/
 #define DERIVE_KEY_EXEC_MAX              (62)
 
-//! DevRev maximum execution time
+/*! DevRev maximum execution time*/
 #define DEVREV_EXEC_MAX                  ( 2)
 
-//! GenDig maximum execution time
+/*! GenDig maximum execution time*/
 #define GENDIG_EXEC_MAX                  (43)
 
-//! HMAC maximum execution time
+/*! HMAC maximum execution time*/
 #define HMAC_EXEC_MAX                    (69)
 
-//! Lock maximum execution time
+/*! Lock maximum execution time*/
 #define LOCK_EXEC_MAX                    (24)
 
-//! MAC maximum execution time
+/*! MAC maximum execution time*/
 #define MAC_EXEC_MAX                     (35)
 
-//! Nonce maximum execution time
+/*! Nonce maximum execution time*/
 #define NONCE_EXEC_MAX                   (60)
 
-//! Pause maximum execution time
+/*! Pause maximum execution time*/
 #define PAUSE_EXEC_MAX                   ( 2)
 
-//! Random maximum execution time
+/*! Random maximum execution time*/
 #define RANDOM_EXEC_MAX                  (50)
 
-//! Read maximum execution time
+/*! Read maximum execution time*/
 #define READ_EXEC_MAX                    ( 4)
 
-//! UpdateExtra maximum execution time
+/*! UpdateExtra maximum execution time*/
 #define UPDATE_EXEC_MAX                  (12)
 
-//! Write maximum execution time
+/*! Write maximum execution time*/
 #define WRITE_EXEC_MAX                   (42)
 
-//////////////////////////////////////////////////////////////////////
+*/
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_check_mac function.
  */
 struct sha204_check_mac_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< what to include in the MAC calculation
-   uint8_t key_id;            //!< what key to use for the MAC calculation
-   uint8_t *client_challenge; //!< pointer to challenge that host had sent to client
-   uint8_t *client_response;  //!< pointer to challenge response received from client 
-   uint8_t *other_data;       //!< pointer to 13 bytes of data that were used by client to calculate MAC
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< what to include in the MAC calculation*/
+   uint8_t key_id;            /*!< what key to use for the MAC calculation*/
+   uint8_t *client_challenge; /*!< pointer to challenge that host had sent to client*/
+   uint8_t *client_response;  /*!< pointer to challenge response received from client*/
+   uint8_t *other_data;       /*!< pointer to 13 bytes of data that were used by client to calculate MAC*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_derive_key function.
  */
 struct sha204_derive_key_parameters {
-   uint8_t *tx_buffer;   	//!< pointer to send buffer
-   uint8_t *rx_buffer;   	//!< pointer to receive buffer
-   uint8_t use_random;   	//!< true if source for TempKey was random number
-   uint8_t target_key;   	//!< slot where derived key should be stored
-   uint8_t *mac;	     	   //!< pointer to MAC for this command
+   uint8_t *tx_buffer;      /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;      /*!< pointer to receive buffer*/
+   uint8_t use_random;      /*!< true if source for TempKey was random number*/
+   uint8_t target_key;      /*!< slot where derived key should be stored*/
+   uint8_t *mac;               /*!< pointer to MAC for this command*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_dev_rev function.
  */
 struct sha204_dev_rev_parameters {
-   uint8_t *tx_buffer;   	//!< pointer to send buffer
-   uint8_t *rx_buffer;		//!< pointer to receive buffer
+   uint8_t *tx_buffer;      /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;      /*!< pointer to receive buffer*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_gen_dig function.
  */
 struct sha204_gen_dig_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t zone;              //!< what zone (config, OTP, or data) to use in the digest calculation
-   uint8_t key_id;            //!< what key or OTP block to use for the digest calculation
-   uint8_t *other_data;       //!< pointer to four bytes of data to use for the digest calculation, only needed when key is CheckMac only key 
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t zone;              /*!< what zone (config, OTP, or data) to use in the digest calculation*/
+   uint8_t key_id;            /*!< what key or OTP block to use for the digest calculation*/
+   uint8_t *other_data;       /*!< pointer to four bytes of data to use for the digest calculation, only needed when key is CheckMac only key*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_hmac function.
  */
 struct sha204_hmac_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< what to include in the HMAC calculation
-   uint16_t key_id;           //!< what key to use for the HMAC calculation
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< what to include in the HMAC calculation*/
+   uint16_t key_id;           /*!< what key to use for the HMAC calculation*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_lock function.
  */
 struct sha204_lock_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t zone;              //!< what zone (config, OTP, or data) to lock
-   uint16_t summary;          //!< CRC over the zone to be locked
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t zone;              /*!< what zone (config, OTP, or data) to lock*/
+   uint16_t summary;          /*!< CRC over the zone to be locked*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_mac function.
  */
 struct sha204_mac_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< what to include in the MAC calculation
-   uint16_t key_id;           //!< what key to use for the MAC calculation
-   uint8_t *challenge;        //!< pointer to 32 bytes of challenge data to be sent to client
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< what to include in the MAC calculation*/
+   uint16_t key_id;           /*!< what key to use for the MAC calculation*/
+   uint8_t *challenge;        /*!< pointer to 32 bytes of challenge data to be sent to client*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_nonce function.
  */
 struct sha204_nonce_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< what TempKey should be loaded with
-   uint8_t *num_in;           //!< pointer to 20 bytes of input or 32 bytes of pass-through data
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< what TempKey should be loaded with*/
+   uint8_t *num_in;           /*!< pointer to 20 bytes of input or 32 bytes of pass-through data*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_pause function.
  */
 struct sha204_pause_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t selector;          //!< which device not to set into Idle mode (single-wire interface only)
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t selector;          /*!< which device not to set into Idle mode (single-wire interface only)*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_random function.
  */
 struct sha204_random_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< true if existing EEPROM seed should be used
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< true if existing EEPROM seed should be used*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_read function.
  */
 struct sha204_read_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t zone;              //!< what zone (config, OTP, or data) to read from and how many bytes (4 or 32)
-   uint16_t address;          //!< what address to read from
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t zone;              /*!< what zone (config, OTP, or data) to read from and how many bytes (4 or 32)*/
+   uint16_t address;          /*!< what address to read from*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_update_extra function.
  */
 struct sha204_update_extra_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t mode;              //!< config byte address = 84 + mode (0 or 1)
-   uint8_t new_value;         //!< value to write
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t mode;              /*!< config byte address = 84 + mode (0 or 1)*/
+   uint8_t new_value;         /*!< value to write*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_write function.
  */
 struct sha204_write_parameters {
-   uint8_t *tx_buffer;        //!< pointer to send buffer
-   uint8_t *rx_buffer;        //!< pointer to receive buffer
-   uint8_t zone;              //!< what zone (config, OTP, or data) to write to, how many bytes (4 or 32), and whether data are encrypted
-   uint16_t address;          //!< what address to write to
-   uint8_t *new_value;        //!< pointer to 4 or 32 bytes of data to be written
-   uint8_t *mac;              //!< pointer to MAC of this command (null if zone is unlocked) 
+   uint8_t *tx_buffer;        /*!< pointer to send buffer*/
+   uint8_t *rx_buffer;        /*!< pointer to receive buffer*/
+   uint8_t zone;              /*!< what zone (config, OTP, or data) to write to, how many bytes (4 or 32), and whether data are encrypted*/
+   uint16_t address;          /*!< what address to write to*/
+   uint8_t *new_value;        /*!< pointer to 4 or 32 bytes of data to be written*/
+   uint8_t *mac;              /*!< pointer to MAC of this command (null if zone is unlocked)*/
 };
 
-/** 
+/**
  * \brief This structure contains the parameters for the \ref sha204m_execute function.
  */
 struct sha204_command_parameters {
-	uint8_t op_code;      //!< command code
-	uint8_t param_1;      //!< parameter 1
-	uint16_t param_2;     //!< parameter 2
-	uint8_t data_len_1;   //!< length of data field 1
-	uint8_t data_len_2;   //!< length of data field 2
-	uint8_t data_len_3;   //!< length of data field 3
-	uint8_t *data_1;      //!< pointer to data field 1
-	uint8_t *data_2;      //!< pointer to data field 2
-	uint8_t *data_3;      //!< pointer to data field 3
-	uint8_t *tx_buffer;   //!< pointer to send buffer
-	uint8_t *rx_buffer;   //!< pointer to receive buffer
-	uint8_t tx_size;      //!< size of supplied send buffer
-	uint8_t rx_size;      //!< size of supplied receive buffer
+    uint8_t op_code;      /*!< command code*/
+    uint8_t param_1;      /*!< parameter 1*/
+    uint16_t param_2;     /*!< parameter 2*/
+    uint8_t data_len_1;   /*!< length of data field 1*/
+    uint8_t data_len_2;   /*!< length of data field 2*/
+    uint8_t data_len_3;   /*!< length of data field 3*/
+    uint8_t *data_1;      /*!< pointer to data field 1*/
+    uint8_t *data_2;      /*!< pointer to data field 2*/
+    uint8_t *data_3;      /*!< pointer to data field 3*/
+    uint8_t *tx_buffer;   /*!< pointer to send buffer*/
+    uint8_t *rx_buffer;   /*!< pointer to receive buffer*/
+    uint8_t tx_size;      /*!< size of supplied send buffer*/
+    uint8_t rx_size;      /*!< size of supplied receive buffer*/
 };
-	
+
 /**
  * \defgroup sha204_command_marshaling_group SHA204 Service - command marshaling functions
  *
@@ -534,6 +534,6 @@ uint8_t sha204m_read(struct sha204_read_parameters *args);
 uint8_t sha204m_update_extra(struct sha204_update_extra_parameters *args);
 uint8_t sha204m_write(struct sha204_write_parameters *args);
 uint8_t sha204m_execute(struct sha204_command_parameters *args);
-//! @}
+/*! @}*/
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c
index 10057ef8a6da..c5ccb4870fef 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_i2c.c
@@ -48,11 +48,11 @@
 #include "conf_twim.h"
 #include "conf_atsha204.h"
 #include "twi_master.h"
-#include "sha204_physical.h"            // declarations that are common to all interface implementations
-#include "sha204_lib_return_codes.h"    // declarations of function return codes
-#include "sha204_timer.h"               // definitions for delay functions
+#include "sha204_physical.h"            /* declarations that are common to all interface implementations*/
+#include "sha204_lib_return_codes.h"    /* declarations of function return codes*/
+#include "sha204_timer.h"               /* definitions for delay functions*/
 
-/** 
+/**
  * \brief This enumeration lists all packet types sent to a SHA204 device.
  *
  * The following byte stream is sent to a SHA204 TWI device:
@@ -60,14 +60,14 @@
  * Data are only sent after a word address of value #SHA204_I2C_PACKET_FUNCTION_NORMAL.
  */
 enum i2c_word_address {
-	SHA204_I2C_PACKET_FUNCTION_RESET,  //!< Reset device.
-	SHA204_I2C_PACKET_FUNCTION_SLEEP,  //!< Put device into Sleep mode.
-	SHA204_I2C_PACKET_FUNCTION_IDLE,   //!< Put device into Idle mode.
-	SHA204_I2C_PACKET_FUNCTION_NORMAL  //!< Write / evaluate data that follow this word address byte.
+    SHA204_I2C_PACKET_FUNCTION_RESET,  /*!< Reset device.*/
+    SHA204_I2C_PACKET_FUNCTION_SLEEP,  /*!< Put device into Sleep mode.*/
+    SHA204_I2C_PACKET_FUNCTION_IDLE,   /*!< Put device into Idle mode.*/
+    SHA204_I2C_PACKET_FUNCTION_NORMAL  /*!< Write / evaluate data that follow this word address byte.*/
 };
 
 
-//! I2C address can be changed by calling #sha204p_set_device_id.
+/*! I2C address can be changed by calling #sha204p_set_device_id.*/
 static uint8_t device_address = SHA204_I2C_DEFAULT_ADDRESS >> 1;
 
 
@@ -75,18 +75,18 @@ static uint8_t device_address = SHA204_I2C_DEFAULT_ADDRESS >> 1;
  */
 void sha204p_init(void)
 {
-	// Initialize timer.
-	sha204h_timer_init();
+    /* Initialize timer.*/
+    sha204h_timer_init();
 
-	// Initialize interrupt vectors.
-	irq_initialize_vectors();
+    /* Initialize interrupt vectors.*/
+    irq_initialize_vectors();
 
-	// Enable interrupts.
-	cpu_irq_enable();
+    /* Enable interrupts.*/
+    cpu_irq_enable();
 }
 
 
-/** 
+/**
  * \brief This I2C function sets the I2C address.
  *         Communication functions will use this address.
  *
@@ -94,45 +94,45 @@ void sha204p_init(void)
  */
 void sha204p_set_device_id(uint8_t id)
 {
-	device_address = id >> 1;
+    device_address = id >> 1;
 }
 
 
-/** 
+/**
  * \brief This I2C function generates a Wake-up pulse and delays.
  * \return status of the operation
  */
 uint8_t sha204p_wakeup(void)
 {
-	twi_package_t twi_package;
-	twi_options_t twi_options = {.speed = 133333};
-   
-	// Set SDA low for 60 us. Speed is therefore: f = 1 / 0.00006 / 8 = 133,333.
-	// Generating the Stop condition adds 20 us for this particular implementation / target,
-	// but a longer wake pulse is okay.
-	twi_master_disable(ATSHA204_TWI_PORT);
-	int twi_master_setup_status = twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
-	if (twi_master_setup_status != STATUS_OK)
-		return SHA204_COMM_FAIL;
-
-	twi_package.chip = 0;
-	twi_package.addr_length = 0;
-	twi_package.length = 0;
-	twi_package.buffer = NULL;
-
-	// This call will return a nack error.
-	(void) twi_master_write(ATSHA204_TWI_PORT, &twi_package);
-
-	sha204h_delay_ms(SHA204_WAKEUP_DELAY);
-	
-	// Set I2C speed back to communication speed.
-	twi_master_enable(ATSHA204_TWI_PORT);
-	twi_options.speed = ATSHA204_TWI_SPEED;
-	return (uint8_t) twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
+    twi_package_t twi_package;
+    twi_options_t twi_options = {.speed = 133333};
+
+    /* Set SDA low for 60 us. Speed is therefore: f = 1 / 0.00006 / 8 = 133,333.*/
+    /* Generating the Stop condition adds 20 us for this particular implementation / target,*/
+    /* but a longer wake pulse is okay.*/
+    twi_master_disable(ATSHA204_TWI_PORT);
+    int twi_master_setup_status = twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
+    if (twi_master_setup_status != STATUS_OK)
+        return SHA204_COMM_FAIL;
+
+    twi_package.chip = 0;
+    twi_package.addr_length = 0;
+    twi_package.length = 0;
+    twi_package.buffer = NULL;
+
+    /* This call will return a nack error.*/
+    (void) twi_master_write(ATSHA204_TWI_PORT, &twi_package);
+
+    sha204h_delay_ms(SHA204_WAKEUP_DELAY);
+
+    /* Set I2C speed back to communication speed.*/
+    twi_master_enable(ATSHA204_TWI_PORT);
+    twi_options.speed = ATSHA204_TWI_SPEED;
+    return (uint8_t) twi_master_setup(ATSHA204_TWI_PORT, &twi_options);
 }
 
 
-/** 
+/**
  * \brief This function sends a I2C packet enclosed by a I2C start and stop to a SHA204 device.
  *
  *         This function combines a I2C packet send sequence that is common to all packet types.
@@ -145,18 +145,18 @@ uint8_t sha204p_wakeup(void)
  */
 static uint8_t sha204p_send(uint8_t word_address, uint8_t count, uint8_t *buffer)
 {
-	twi_package_t twi_package = {
-		.chip = device_address,
-		.addr_length = 1,
-		.length = count,
-		.buffer = (void *) buffer,
-		.addr[0] = word_address
-	};
-	return (twi_master_write(ATSHA204_TWI_PORT, &twi_package) ? SHA204_COMM_FAIL : SHA204_SUCCESS);
+    twi_package_t twi_package = {
+        .chip = device_address,
+        .addr_length = 1,
+        .length = count,
+        .buffer = (void *) buffer,
+        .addr[0] = word_address
+    };
+    return (twi_master_write(ATSHA204_TWI_PORT, &twi_package) ? SHA204_COMM_FAIL : SHA204_SUCCESS);
 }
 
 
-/** 
+/**
  * \brief This I2C function sends a command to the device.
  * \param[in] count number of bytes to send
  * \param[in] command pointer to command buffer
@@ -164,41 +164,41 @@ static uint8_t sha204p_send(uint8_t word_address, uint8_t count, uint8_t *buffer
  */
 uint8_t sha204p_send_command(uint8_t count, uint8_t *command)
 {
-	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_NORMAL, count, command);
+    return sha204p_send(SHA204_I2C_PACKET_FUNCTION_NORMAL, count, command);
 }
 
 
-/** 
+/**
  * \brief This I2C function puts the SHA204 device into idle state.
  * \return status of the operation
  */
 uint8_t sha204p_idle(void)
 {
-	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_IDLE, 0, NULL);
+    return sha204p_send(SHA204_I2C_PACKET_FUNCTION_IDLE, 0, NULL);
 }
 
 
-/** 
+/**
  * \brief This I2C function puts the SHA204 device into low-power state.
  * \return status of the operation
  */
 uint8_t sha204p_sleep(void)
 {
-	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_SLEEP, 0, NULL);
+    return sha204p_send(SHA204_I2C_PACKET_FUNCTION_SLEEP, 0, NULL);
 }
 
 
-/** 
+/**
  * \brief This I2C function resets the I/O buffer of the SHA204 device.
  * \return status of the operation
  */
 uint8_t sha204p_reset_io(void)
 {
-	return sha204p_send(SHA204_I2C_PACKET_FUNCTION_RESET, 0, NULL);
+    return sha204p_send(SHA204_I2C_PACKET_FUNCTION_RESET, 0, NULL);
 }
 
 
-/** 
+/**
  * \brief This I2C function receives a response from the SHA204 device.
  *
  * \param[in] size size of receive buffer
@@ -207,22 +207,22 @@ uint8_t sha204p_reset_io(void)
  */
 uint8_t sha204p_receive_response(uint8_t size, uint8_t *response)
 {
-    // Read count.
-	twi_package_t twi_package = {
-		.chip = device_address,
-		.addr_length = 0,
-		.length = 1,
-		.buffer = (void *) response
-	};
-	status_code_t i2c_status = twi_master_read(ATSHA204_TWI_PORT, &twi_package);
-	if (i2c_status != STATUS_OK)
-	    return (i2c_status == ERR_TIMEOUT ? SHA204_TIMEOUT : SHA204_RX_NO_RESPONSE);
-
-	uint8_t count = response[SHA204_BUFFER_POS_COUNT];
-	if ((count < SHA204_RSP_SIZE_MIN) || (count > SHA204_RSP_SIZE_MAX))
-		return SHA204_INVALID_SIZE;
-	   
-	// Read packet remainder.
+    /* Read count.*/
+    twi_package_t twi_package = {
+        .chip = device_address,
+        .addr_length = 0,
+        .length = 1,
+        .buffer = (void *) response
+    };
+    status_code_t i2c_status = twi_master_read(ATSHA204_TWI_PORT, &twi_package);
+    if (i2c_status != STATUS_OK)
+        return (i2c_status == ERR_TIMEOUT ? SHA204_TIMEOUT : SHA204_RX_NO_RESPONSE);
+
+    uint8_t count = response[SHA204_BUFFER_POS_COUNT];
+    if ((count < SHA204_RSP_SIZE_MIN) || (count > SHA204_RSP_SIZE_MAX))
+        return SHA204_INVALID_SIZE;
+
+    /* Read packet remainder.*/
     twi_package.length = (count > size) ? size : count;
     twi_package.length--;
     twi_package.buffer = response + 1;
@@ -230,7 +230,7 @@ uint8_t sha204p_receive_response(uint8_t size, uint8_t *response)
 }
 
 
-/** 
+/**
  * \brief This I2C function resynchronizes communication.
  *
  * Parameters are not used for I2C.\n
@@ -282,19 +282,19 @@ uint8_t sha204p_receive_response(uint8_t size, uint8_t *response)
  */
 uint8_t sha204p_resync(uint8_t size, uint8_t *response)
 {
-	// Generate Start, nine clocks, Stop.
-	// (Adding a Repeat Start before the Stop would additionally
-	// prevent erroneously writing a byte, but a Stop right after a
-	// Start is not "legal" for I2C and the SHA204 will not write
-	// anything without a successful CRC check.)
-	twi_package_t twi_package = {
-		.chip = (uint8_t) 0xFF,
-		.addr_length = 1,
-		.length = 0,
-		.buffer = (void *) response,
-		.addr[0] = 0
-	};
-	(void) twi_master_read(ATSHA204_TWI_PORT, &twi_package);
-
-	return sha204p_reset_io();
+    /* Generate Start, nine clocks, Stop.*/
+    /* (Adding a Repeat Start before the Stop would additionally*/
+    /* prevent erroneously writing a byte, but a Stop right after a*/
+    /* Start is not "legal" for I2C and the SHA204 will not write*/
+    /* anything without a successful CRC check.)*/
+    twi_package_t twi_package = {
+        .chip = (uint8_t) 0xFF,
+        .addr_length = 1,
+        .length = 0,
+        .buffer = (void *) response,
+        .addr[0] = 0
+    };
+    (void) twi_master_read(ATSHA204_TWI_PORT, &twi_package);
+
+    return sha204p_reset_io();
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h
index aba98e672818..26a37f9b2974 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_lib_return_codes.h
@@ -48,21 +48,21 @@
 #ifndef SHA204_LIB_RETURN_CODES_H
 #   define SHA204_LIB_RETURN_CODES_H
 
-#include <compiler.h>               //!< compiler dependent definitions
+#include <compiler.h>               /*!< compiler dependent definitions*/
 
-#define SHA204_SUCCESS              ((uint8_t)  0x00) //!< Function succeeded.
-#define SHA204_PARSE_ERROR          ((uint8_t)  0xD2) //!< response status byte indicates parsing error
-#define SHA204_CMD_FAIL             ((uint8_t)  0xD3) //!< response status byte indicates command execution error
-#define SHA204_STATUS_CRC           ((uint8_t)  0xD4) //!< response status byte indicates CRC error
-#define SHA204_FUNC_FAIL            ((uint8_t)  0xE0) //!< Function could not execute due to incorrect condition / state.
-#define SHA204_BAD_PARAM            ((uint8_t)  0xE2) //!< bad argument (out of range, null pointer, etc.)
-#define SHA204_INVALID_SIZE         ((uint8_t)  0xE4) //!< Count value is out of range or greater than buffer size.
-#define SHA204_BAD_CRC              ((uint8_t)  0xE5) //!< incorrect CRC received
-#define SHA204_RX_FAIL              ((uint8_t)  0xE6) //!< Timed out while waiting for response. Number of bytes received is > 0.
-#define SHA204_RX_NO_RESPONSE       ((uint8_t)  0xE7) //!< Not an error while the Command layer is polling for a command response.
-#define SHA204_RESYNC_WITH_WAKEUP   ((uint8_t)  0xE8) //!< re-synchronization succeeded, but only after generating a Wake-up
+#define SHA204_SUCCESS              ((uint8_t)  0x00) /*!< Function succeeded.*/
+#define SHA204_PARSE_ERROR          ((uint8_t)  0xD2) /*!< response status byte indicates parsing error*/
+#define SHA204_CMD_FAIL             ((uint8_t)  0xD3) /*!< response status byte indicates command execution error*/
+#define SHA204_STATUS_CRC           ((uint8_t)  0xD4) /*!< response status byte indicates CRC error*/
+#define SHA204_FUNC_FAIL            ((uint8_t)  0xE0) /*!< Function could not execute due to incorrect condition / state.*/
+#define SHA204_BAD_PARAM            ((uint8_t)  0xE2) /*!< bad argument (out of range, null pointer, etc.)*/
+#define SHA204_INVALID_SIZE         ((uint8_t)  0xE4) /*!< Count value is out of range or greater than buffer size.*/
+#define SHA204_BAD_CRC              ((uint8_t)  0xE5) /*!< incorrect CRC received*/
+#define SHA204_RX_FAIL              ((uint8_t)  0xE6) /*!< Timed out while waiting for response. Number of bytes received is > 0.*/
+#define SHA204_RX_NO_RESPONSE       ((uint8_t)  0xE7) /*!< Not an error while the Command layer is polling for a command response.*/
+#define SHA204_RESYNC_WITH_WAKEUP   ((uint8_t)  0xE8) /*!< re-synchronization succeeded, but only after generating a Wake-up*/
 
-#define SHA204_COMM_FAIL            ((uint8_t)  0xF0) //!< Communication with device failed. Same as in hardware dependent modules.
-#define SHA204_TIMEOUT              ((uint8_t)  0xF1) //!< Timed out while waiting for response. Number of bytes received is 0.
+#define SHA204_COMM_FAIL            ((uint8_t)  0xF0) /*!< Communication with device failed. Same as in hardware dependent modules.*/
+#define SHA204_TIMEOUT              ((uint8_t)  0xF1) /*!< Timed out while waiting for response. Number of bytes received is 0.*/
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h
index 660ffdf8adb0..c34a5f743130 100644
--- a/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h
+++ b/bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/sha204_physical.h
@@ -48,15 +48,15 @@
 #ifndef SHA204_PHYSICAL_H
 #   define SHA204_PHYSICAL_H
 
-#include "sha204_config.h"                           //!< configuration values
+#include "sha204_config.h"                           /*!< configuration values*/
 
-#define SHA204_RSP_SIZE_MIN          ((uint8_t)  4)  //!< minimum number of bytes in response
-#define SHA204_RSP_SIZE_MAX          ((uint8_t) 35)  //!< maximum size of response packet
+#define SHA204_RSP_SIZE_MIN          ((uint8_t)  4)  /*!< minimum number of bytes in response*/
+#define SHA204_RSP_SIZE_MAX          ((uint8_t) 35)  /*!< maximum size of response packet*/
 
-#define SHA204_BUFFER_POS_COUNT      (0)             //!< buffer index of count byte in command or response
-#define SHA204_BUFFER_POS_DATA       (1)             //!< buffer index of data in response
+#define SHA204_BUFFER_POS_COUNT      (0)             /*!< buffer index of count byte in command or response*/
+#define SHA204_BUFFER_POS_DATA       (1)             /*!< buffer index of data in response*/
 
-//! delay between Wakeup pulse and communication in ms
+/*! delay between Wakeup pulse and communication in ms*/
 #define SHA204_WAKEUP_DELAY          (3)
 /**
  * \defgroup sha204_communication_physical_group SHA204 Service - hardware dependent communication functions
@@ -72,6 +72,6 @@ uint8_t sha204p_idle(void);
 uint8_t sha204p_sleep(void);
 uint8_t sha204p_reset_io(void);
 uint8_t sha204p_resync(uint8_t size, uint8_t *response);
-//! @}
+/*! @}*/
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h
index b5007a87f206..22c5de279ab1 100644
--- a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h
+++ b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/common_nvm.h
@@ -63,18 +63,18 @@ extern "C" {
 /* ! \name Non volatile memory types */
 /* ! @{ */
 typedef enum {
-	INT_FLASH     /* !< Internal Flash */
+    INT_FLASH     /* !< Internal Flash */
 
 #if (XMEGA || UC3 || SAM4S)
-	, INT_USERPAGE  /* !< Userpage/User signature */
+    , INT_USERPAGE  /* !< Userpage/User signature */
 #endif
 
 #if XMEGA
-	, INT_EEPROM    /* !< Internal EEPROM */
+    , INT_EEPROM    /* !< Internal EEPROM */
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	, AT45DBX        /* !< External AT45DBX dataflash */
+    , AT45DBX        /* !< External AT45DBX dataflash */
 #endif
 } mem_type_t;
 /* ! @} */
@@ -139,7 +139,7 @@ status_code_t nvm_write_char(mem_type_t mem, uint32_t address, uint8_t data);
  * \param len Number of bytes to read
  */
 status_code_t nvm_read(mem_type_t mem, uint32_t address, void *buffer,
-		uint32_t len);
+        uint32_t len);
 
 /**
  * \brief Write \a len number of bytes at address \a address in non volatile
@@ -154,7 +154,7 @@ status_code_t nvm_read(mem_type_t mem, uint32_t address, void *buffer,
  * \param len Number of bytes to write
  */
 status_code_t nvm_write(mem_type_t mem, uint32_t address, void *buffer,
-		uint32_t len);
+        uint32_t len);
 
 /**
  * \brief Erase a page in the non volatile memory.
@@ -192,7 +192,7 @@ status_code_t nvm_get_page_size(mem_type_t mem, uint32_t *size);
  * \param num Pointer to where to store the page number
  */
 status_code_t nvm_get_pagenumber(mem_type_t mem, uint32_t address,
-		uint32_t *num);
+        uint32_t *num);
 
 /**
  * \brief Enable security bit which blocks external read and write access
@@ -220,8 +220,8 @@ status_code_t nvm_set_security_bit(void);
  * \subsection nvm_basic_use_case_setup_code Example code
  * Add to you application C-file:
  * \code
-	if(nvm_init(INT_FLASH) == STATUS_OK)
-	  do_something();
+    if(nvm_init(INT_FLASH) == STATUS_OK)
+      do_something();
 \endcode
  *
  * \subsection nvm_basic_use_case_setup_flow Workflow
@@ -238,39 +238,40 @@ status_code_t nvm_set_security_bit(void);
  * non volatile memory
  * Use in the application C-file:
  * \code
-	   uint8_t buffer[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE};
+       uint8_t buffer[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE};
 
-	   if(nvm_write(INT_FLASH, test_address, (void *)buffer, sizeof(buffer)) ==
-	 STATUS_OK)
-	     do_something();
+       if(nvm_write(INT_FLASH, test_address, (void *)buffer, sizeof(buffer)) ==
+     STATUS_OK)
+         do_something();
 \endcode
  *
  * \subsection nvm_basic_use_case_usage_flow Workflow
  * -# Prepare the data you want to send to the non volatile memory
  *   \code uint8_t buffer[] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE}; \endcode
  * -# Call nvm_write \code nvm_write(INT_FLASH, test_address, (void *)buffer,
-	 sizeof(buffer)) \endcode
+     sizeof(buffer)) \endcode
  * and optionally check its return value for STATUS_OK.
  *
  * \subsection nvm_basic_use_case_usage_code_reading Example code: Reading from
  * non volatile memory
  * Use in application C-file:
  * \code
-	   uint8_t data_read[8];
+       uint8_t data_read[8];
 
-	   if(nvm_read(INT_FLASH, test_address, (void *)data_read, sizeof(data_read))
-	 == STATUS_OK) {
-	     //Check read content
-	     if(data_read[0] == 0xAA)
-	       do_something();
-	   }
+       if(nvm_read(INT_FLASH, test_address, (void *)data_read, sizeof(data_read))
+     == STATUS_OK)
+     {
+         //Check read content
+         if(data_read[0] == 0xAA)
+           do_something();
+       }
 \endcode
  *
  * \subsection nvm_basic_use_case_usage_flow Workflow
  * -# Prepare a data buffer that will read data from non volatile memory
  *   \code uint8_t data_read[8]; \endcode
  * -# Call nvm_read \code nvm_read(INT_FLASH, test_address, (void *)data_read,
-	 sizeof(data_read)); \endcode
+     sizeof(data_read)); \endcode
  * and optionally check its return value for STATUS_OK.
  * The data read from the non volatile memory are in data_read.
  *
@@ -278,8 +279,8 @@ status_code_t nvm_set_security_bit(void);
  * page of non volatile memory
  * Use in the application C-file:
  * \code
-	if(nvm_page_erase(INT_FLASH, test_page) == STATUS_OK)
-	  do_something();
+    if(nvm_page_erase(INT_FLASH, test_page) == STATUS_OK)
+      do_something();
 \endcode
  *
  * \subsection nvm_basic_use_case_usage_flow Workflow
@@ -290,11 +291,11 @@ status_code_t nvm_set_security_bit(void);
  *configuration of non volatile memory
  * Use in application C-file:
  * \code
-	   uint8_t mem_size, page_size, page_num;
+       uint8_t mem_size, page_size, page_num;
 
-	   nvm_get_size(INT_FLASH, &mem_size);
-	   nvm_get_page_size(INT_FLASH, &page_size);
-	   nvm_get_pagenumber(INT_FLASH, test_address, &page_num);
+       nvm_get_size(INT_FLASH, &mem_size);
+       nvm_get_page_size(INT_FLASH, &page_size);
+       nvm_get_pagenumber(INT_FLASH, test_address, &page_num);
 \endcode
  *
  * \subsection nvm_basic_use_case_usage_flow Workflow
@@ -308,7 +309,7 @@ status_code_t nvm_set_security_bit(void);
  * and optionally check its return value for STATUS_OK.
  * The page size of the non volatile memory is in page_size.
  * -# Call nvm_get_pagenumber \code nvm_get_page_number(INT_FLASH, test_address,
-	 &page_num); \endcode
+     &page_num); \endcode
  * and optionally check its return value for STATUS_OK.
  * The page number of given address in the non volatile memory is in page_num.
  *
@@ -316,8 +317,8 @@ status_code_t nvm_set_security_bit(void);
  * security bit
  * Use in the application C-file:
  * \code
-	if(nvm_set_security_bit() == STATUS_OK)
-	  do_something();
+    if(nvm_set_security_bit() == STATUS_OK)
+      do_something();
 \endcode
  *
  * \subsection nvm_basic_use_case_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c
index cf23c7fee780..5d07d41172f7 100644
--- a/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c
+++ b/bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/sam_nvm.c
@@ -50,345 +50,378 @@
 
 status_code_t nvm_init(mem_type_t mem)
 {
-	switch (mem) {
-	case INT_FLASH:
+    switch (mem)
+    {
+    case INT_FLASH:
 #if SAM4S
-	case INT_USERPAGE:
+    case INT_USERPAGE:
 #endif
-		break;
+        break;
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-		/* Initialize dataflash */
-		at45dbx_init();
-		/* Perform memory check */
-		if (!at45dbx_mem_check()) {
-			return ERR_NO_MEMORY;
-		}
-		break;
+    case AT45DBX:
+        /* Initialize dataflash */
+        at45dbx_init();
+        /* Perform memory check */
+        if (!at45dbx_mem_check())
+        {
+            return ERR_NO_MEMORY;
+        }
+        break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_read_char(mem_type_t mem, uint32_t address, uint8_t *data)
 {
-	switch (mem) {
-	case INT_FLASH:
-		*data = *((uint8_t *)(address));
-		break;
+    switch (mem)
+    {
+    case INT_FLASH:
+        *data = *((uint8_t *)(address));
+        break;
 
 #if SAM4S
-	case INT_USERPAGE:
-	{
-		/*! This function creates a buffer of IFLASH_PAGE_SIZE to
-		 * read the data from starting of user signature */
-		uint32_t buffer[IFLASH_PAGE_SIZE];
-		uint32_t offset = address - IFLASH_ADDR;
-		if (offset < 0) {
-			return ERR_INVALID_ARG;
-		}
-
-		flash_read_user_signature(buffer, offset);
-		*data = buffer[offset];
-		break;
-	}
+    case INT_USERPAGE:
+    {
+        /*! This function creates a buffer of IFLASH_PAGE_SIZE to
+         * read the data from starting of user signature */
+        uint32_t buffer[IFLASH_PAGE_SIZE];
+        uint32_t offset = address - IFLASH_ADDR;
+        if (offset < 0)
+        {
+            return ERR_INVALID_ARG;
+        }
+
+        flash_read_user_signature(buffer, offset);
+        *data = buffer[offset];
+        break;
+    }
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-		if (!at45dbx_read_byte_open(address)) {
-			return ERR_BAD_ADDRESS;
-		}
-
-		*data = at45dbx_read_byte();
-		at45dbx_read_close();
-		break;
+    case AT45DBX:
+        if (!at45dbx_read_byte_open(address))
+        {
+            return ERR_BAD_ADDRESS;
+        }
+
+        *data = at45dbx_read_byte();
+        at45dbx_read_close();
+        break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_write_char(mem_type_t mem, uint32_t address, uint8_t data)
 {
-	switch (mem) {
-	case INT_FLASH:
+    switch (mem)
+    {
+    case INT_FLASH:
 #if SAM4S
 
-		if (flash_write(address, (const void *)&data, 1,
-				false)) {
-			return ERR_INVALID_ARG;
-		}
+        if (flash_write(address, (const void *)&data, 1,
+                false))
+                {
+            return ERR_INVALID_ARG;
+        }
 
 #else
-		if (flash_write(address, (const void *)&data, 1, true)) {
-			return ERR_INVALID_ARG;
-		}
+        if (flash_write(address, (const void *)&data, 1, true))
+        {
+            return ERR_INVALID_ARG;
+        }
 
 #endif
-		break;
+        break;
 
 #if SAM4S
-	case INT_USERPAGE:
-		if (flash_write_user_signature((const void *)&data,	1)) {
-			return ERR_INVALID_ARG;
-		}
-		break;
+    case INT_USERPAGE:
+        if (flash_write_user_signature((const void *)&data, 1))
+        {
+            return ERR_INVALID_ARG;
+        }
+        break;
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-		if (!at45dbx_write_byte_open(address)) {
-			return ERR_BAD_ADDRESS;
-		}
-
-		at45dbx_write_byte(data);
-		at45dbx_write_close();
-		break;
+    case AT45DBX:
+        if (!at45dbx_write_byte_open(address))
+        {
+            return ERR_BAD_ADDRESS;
+        }
+
+        at45dbx_write_byte(data);
+        at45dbx_write_close();
+        break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_read(mem_type_t mem, uint32_t address, void *buffer,
-		uint32_t len)
+        uint32_t len)
 {
-	switch (mem) {
-	case INT_FLASH:
-		memcpy(buffer, (const void *)address, len);
-		break;
+    switch (mem)
+    {
+    case INT_FLASH:
+        memcpy(buffer, (const void *)address, len);
+        break;
 
 #if SAM4S
-	case INT_USERPAGE:
-	{
-		/*! This function creates a buffer of IFLASH_PAGE_SIZE to
-		 * read the data from starting of user signature */
-		uint32_t temp_buff[IFLASH_PAGE_SIZE], *buff = buffer;
-
-		/* Read from the starting of user signature */
-		if (flash_read_user_signature(temp_buff, len)) {
-			return ERR_INVALID_ARG;
-		}
-
-		/* Calculate offset and copy required number of bytes */
-		for (uint16_t i = 0; i < len; i++) {
-			*buff = temp_buff[address - IFLASH_ADDR + i];
-			buff++;
-		}
-		break;
-	}
+    case INT_USERPAGE:
+    {
+        /*! This function creates a buffer of IFLASH_PAGE_SIZE to
+         * read the data from starting of user signature */
+        uint32_t temp_buff[IFLASH_PAGE_SIZE], *buff = buffer;
+
+        /* Read from the starting of user signature */
+        if (flash_read_user_signature(temp_buff, len))
+        {
+            return ERR_INVALID_ARG;
+        }
+
+        /* Calculate offset and copy required number of bytes */
+        for (uint16_t i = 0; i < len; i++)
+        {
+            *buff = temp_buff[address - IFLASH_ADDR + i];
+            buff++;
+        }
+        break;
+    }
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-	{
-		if (len == AT45DBX_SECTOR_SIZE) {
-			uint32_t sector = address / AT45DBX_SECTOR_SIZE;
-			if (!at45dbx_read_sector_open(sector)) {
-				return ERR_BAD_ADDRESS;
-			}
-
-			at45dbx_read_sector_to_ram(buffer);
-			at45dbx_read_close();
-		} else {
-			if (!at45dbx_read_byte_open(address)) {
-				return ERR_BAD_ADDRESS;
-			}
-			uint8_t *buf = (uint8_t *)buffer;
-			while (len--) {
-				*buf++ = at45dbx_read_byte();
-			}
-			at45dbx_read_close();
-		}
-		
-	}
-	break;
+    case AT45DBX:
+    {
+        if (len == AT45DBX_SECTOR_SIZE)
+        {
+            uint32_t sector = address / AT45DBX_SECTOR_SIZE;
+            if (!at45dbx_read_sector_open(sector))
+            {
+                return ERR_BAD_ADDRESS;
+            }
+
+            at45dbx_read_sector_to_ram(buffer);
+            at45dbx_read_close();
+        } else {
+            if (!at45dbx_read_byte_open(address))
+            {
+                return ERR_BAD_ADDRESS;
+            }
+            uint8_t *buf = (uint8_t *)buffer;
+            while (len--)
+            {
+                *buf++ = at45dbx_read_byte();
+            }
+            at45dbx_read_close();
+        }
+
+    }
+    break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_write(mem_type_t mem, uint32_t address, void *buffer,
-		uint32_t len)
+        uint32_t len)
 {
-	switch (mem) {
-	case INT_FLASH:
+    switch (mem)
+    {
+    case INT_FLASH:
 #if SAM4S
 
-		if (flash_write(address, (const void *)buffer, len, false)) {
-			return ERR_INVALID_ARG;
-		}
+        if (flash_write(address, (const void *)buffer, len, false))
+        {
+            return ERR_INVALID_ARG;
+        }
 
 #else
-		if (flash_write(address, (const void *)buffer, len, true)) {
-			return ERR_INVALID_ARG;
-		}
+        if (flash_write(address, (const void *)buffer, len, true))
+        {
+            return ERR_INVALID_ARG;
+        }
 
 #endif
-		break;
+        break;
 
 #if SAM4S
-	case INT_USERPAGE:
-		if (flash_write_user_signature((const void *)buffer, len)) {
-			return ERR_INVALID_ARG;
-		}
-		break;
+    case INT_USERPAGE:
+        if (flash_write_user_signature((const void *)buffer, len))
+        {
+            return ERR_INVALID_ARG;
+        }
+        break;
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-	{
-		if (len == AT45DBX_SECTOR_SIZE) {
-			uint32_t sector = address / AT45DBX_SECTOR_SIZE;
-			if (!at45dbx_write_sector_open(sector)) {
-				return ERR_BAD_ADDRESS;
-			}
-
-			at45dbx_write_sector_from_ram((const void *)buffer);
-			at45dbx_write_close();
-		} else {
-			if (!at45dbx_write_byte_open(address)) {
-				return ERR_BAD_ADDRESS;
-			}
-			uint8_t *buf = (uint8_t *)buffer;
-			while (len--) {
-				at45dbx_write_byte(*buf++);
-			}
-			at45dbx_write_close();
-		}	
-	}
-	break;
+    case AT45DBX:
+    {
+        if (len == AT45DBX_SECTOR_SIZE)
+        {
+            uint32_t sector = address / AT45DBX_SECTOR_SIZE;
+            if (!at45dbx_write_sector_open(sector))
+            {
+                return ERR_BAD_ADDRESS;
+            }
+
+            at45dbx_write_sector_from_ram((const void *)buffer);
+            at45dbx_write_close();
+        } else {
+            if (!at45dbx_write_byte_open(address))
+            {
+                return ERR_BAD_ADDRESS;
+            }
+            uint8_t *buf = (uint8_t *)buffer;
+            while (len--)
+            {
+                at45dbx_write_byte(*buf++);
+            }
+            at45dbx_write_close();
+        }
+    }
+    break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_page_erase(mem_type_t mem, uint32_t page_number)
 {
-	switch (mem) {
-	case INT_FLASH:
-	{
+    switch (mem)
+    {
+    case INT_FLASH:
+    {
 #if SAM4S
-		/*! Page erase function erases minimum 8 pages in Flash */
-		if (flash_erase_page((uint32_t)(page_number * IFLASH_PAGE_SIZE),
-				IFLASH_ERASE_PAGES_8)) {
-			return ERR_INVALID_ARG;
-		}
+        /*! Page erase function erases minimum 8 pages in Flash */
+        if (flash_erase_page((uint32_t)(page_number * IFLASH_PAGE_SIZE),
+                IFLASH_ERASE_PAGES_8))
+                {
+            return ERR_INVALID_ARG;
+        }
 
 #else
-		uint32_t buffer[IFLASH_PAGE_SIZE], byte_address;
-		for (uint16_t i = 0; i < IFLASH_PAGE_SIZE; i++) {
-			buffer[i] = 0xFFFFFFFF;
-		}
-		byte_address = page_number * IFLASH_PAGE_SIZE;
-
-		/* Erase and write FFs to a page as there is no function for
-		 * erase */
-		if (!flash_write(byte_address, (const void *)buffer,
-				IFLASH_PAGE_SIZE, true)) {
-			return ERR_INVALID_ARG;
-		}
+        uint32_t buffer[IFLASH_PAGE_SIZE], byte_address;
+        for (uint16_t i = 0; i < IFLASH_PAGE_SIZE; i++)
+        {
+            buffer[i] = 0xFFFFFFFF;
+        }
+        byte_address = page_number * IFLASH_PAGE_SIZE;
+
+        /* Erase and write FFs to a page as there is no function for
+         * erase */
+        if (!flash_write(byte_address, (const void *)buffer,
+                IFLASH_PAGE_SIZE, true))
+                {
+            return ERR_INVALID_ARG;
+        }
 
 #endif
-		break;
-	}
+        break;
+    }
 
 #if SAM4S
-	case INT_USERPAGE:
-		flash_erase_user_signature();
-		break;
+    case INT_USERPAGE:
+        flash_erase_user_signature();
+        break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_get_size(mem_type_t mem, uint32_t *size)
 {
-	switch (mem) {
-	case INT_FLASH:
-		*size = (uint32_t)IFLASH_SIZE;
-		break;
+    switch (mem)
+    {
+    case INT_FLASH:
+        *size = (uint32_t)IFLASH_SIZE;
+        break;
 
 #if SAM4S
-	case INT_USERPAGE:
-		*size = (uint32_t)IFLASH_PAGE_SIZE;
-		break;
+    case INT_USERPAGE:
+        *size = (uint32_t)IFLASH_PAGE_SIZE;
+        break;
 #endif
 
 #if defined(USE_EXTMEM) && defined(CONF_BOARD_AT45DBX)
-	case AT45DBX:
-		*size = (uint32_t)AT45DBX_MEM_SIZE;
-		break;
+    case AT45DBX:
+        *size = (uint32_t)AT45DBX_MEM_SIZE;
+        break;
 #endif
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_get_page_size(mem_type_t mem, uint32_t *size)
 {
-	switch (mem) {
-	case INT_FLASH:
+    switch (mem)
+    {
+    case INT_FLASH:
 #if SAM4S
-	case INT_USERPAGE:
+    case INT_USERPAGE:
 #endif
-		*size = (uint32_t)IFLASH_PAGE_SIZE;
-		break;
+        *size = (uint32_t)IFLASH_PAGE_SIZE;
+        break;
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_get_pagenumber(mem_type_t mem, uint32_t address,
-		uint32_t *num)
+        uint32_t *num)
 {
-	switch (mem) {
-	case INT_FLASH:
-		*num = (uint32_t)(address / IFLASH_PAGE_SIZE);
-		break;
+    switch (mem)
+    {
+    case INT_FLASH:
+        *num = (uint32_t)(address / IFLASH_PAGE_SIZE);
+        break;
 
-	default:
-		return ERR_INVALID_ARG;
-	}
+    default:
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 status_code_t nvm_set_security_bit(void)
 {
-	if (!flash_enable_security_bit()) {
-		return ERR_INVALID_ARG;
-	}
+    if (!flash_enable_security_bit())
+    {
+        return ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c
index 5b41fc76ed9e..9e494dfe8058 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.c
@@ -66,16 +66,18 @@ static enum rx_state_e rx_state;
 
 uint16_t adp_add_send_byte(uint8_t* buffer, uint8_t index, uint8_t* data, uint16_t length)
 {
-	for(uint16_t i = 0; i < length; i++) {
-		if (*(data + i) == ADP_TOKEN){
-			*(buffer + index) = ADP_TOKEN;
-			index++;
-		}
-		*(buffer + index) = *(data + i);
-		index++;
-	}
-
-	return index;
+    for(uint16_t i = 0; i < length; i++)
+    {
+        if (*(data + i) == ADP_TOKEN)
+        {
+            *(buffer + index) = ADP_TOKEN;
+            index++;
+        }
+        *(buffer + index) = *(data + i);
+        index++;
+    }
+
+    return index;
 }
 
 /**
@@ -89,154 +91,173 @@ uint16_t adp_add_send_byte(uint8_t* buffer, uint8_t index, uint8_t* data, uint16
 */
 static bool adp_add_receive_byte(uint8_t data)
 {
-	static uint8_t message_id;
-
-	if ((rx_state == RX_STATE_GOT_SYMBOL) && (data != ADP_TOKEN)) {
-		/* Abort packet reception, new packet incoming */
-		rx_state = RX_STATE_WAIT_LENGTH_LSB;
-	}
-
-	switch (rx_state) {
-		case RX_STATE_IDLE:
-			packet_received = false;
-			last_received_message_id = 0xFF;
-			/* We are waiting for a new packet. */
-			if (data != ADP_TOKEN) {
-				return false;
-			}
-			/* Got start symbol, wait for message ID */
-			rx_state = RX_STATE_WAIT_MSG_ID;
-			return false;
-
-		case RX_STATE_WAIT_MSG_ID:
-			if (data == ADP_TOKEN) {
-				/* Restart. Don't change state. Wait for new message ID */
-				return false;
-			}
-			message_id = data;
-			rx_state = RX_STATE_WAIT_LENGTH_LSB;
-			return false;
-
-		case RX_STATE_WAIT_LENGTH_LSB:
-			if (data == ADP_TOKEN) {
-				if (prev_data != ADP_TOKEN) {
-					prev_data = ADP_TOKEN;
-					return false;
-				}
-			}
-			length_received = data;
-			rx_state = RX_STATE_WAIT_LENGTH_MSB;
-			prev_data = 0;
-			return false;
-
-		case RX_STATE_WAIT_LENGTH_MSB:
-			if (data == ADP_TOKEN) {
-				if (prev_data != ADP_TOKEN) {
-					prev_data = ADP_TOKEN;
-					return false;
-				}
-			}
-			length_received += (uint16_t)data << 8;
-			prev_data = 0;
-			/* Got valid length, do we expect data? */
-			if (length_received == 0) {
-				/* No data here, wait for next packet */
-				rx_state = RX_STATE_IDLE;
-				packet_received = true;
-				last_received_message_id = message_id;
-				return false;
-			}
-
-			/* Wait for packet data */
-			bytes_received = 0;
-			rx_state = RX_STATE_GET_DATA;
-			return false;
-
-		case RX_STATE_GET_DATA:
-		case RX_STATE_GOT_SYMBOL:
-			if ((data == ADP_TOKEN) && (rx_state == RX_STATE_GET_DATA)) {
-				rx_state = RX_STATE_GOT_SYMBOL;
-				return false;
-			}
-			/* Add new data to rx buffer */
-			bytes_received++;
-			/* Are we done yet? */
-			if (length_received == bytes_received) {
-				/* Yes we are! */
-				packet_received = true;
-				rx_state = RX_STATE_IDLE;
-				last_received_message_id = message_id;
-				return true;
-			}
-			/* Not done yet.. keep on receiving */
-			rx_state = RX_STATE_GET_DATA;
-			return true;
-	}
-	return false;
+    static uint8_t message_id;
+
+    if ((rx_state == RX_STATE_GOT_SYMBOL) && (data != ADP_TOKEN))
+    {
+        /* Abort packet reception, new packet incoming */
+        rx_state = RX_STATE_WAIT_LENGTH_LSB;
+    }
+
+    switch (rx_state)
+    {
+        case RX_STATE_IDLE:
+            packet_received = false;
+            last_received_message_id = 0xFF;
+            /* We are waiting for a new packet. */
+            if (data != ADP_TOKEN)
+            {
+                return false;
+            }
+            /* Got start symbol, wait for message ID */
+            rx_state = RX_STATE_WAIT_MSG_ID;
+            return false;
+
+        case RX_STATE_WAIT_MSG_ID:
+            if (data == ADP_TOKEN)
+            {
+                /* Restart. Don't change state. Wait for new message ID */
+                return false;
+            }
+            message_id = data;
+            rx_state = RX_STATE_WAIT_LENGTH_LSB;
+            return false;
+
+        case RX_STATE_WAIT_LENGTH_LSB:
+            if (data == ADP_TOKEN)
+            {
+                if (prev_data != ADP_TOKEN)
+                {
+                    prev_data = ADP_TOKEN;
+                    return false;
+                }
+            }
+            length_received = data;
+            rx_state = RX_STATE_WAIT_LENGTH_MSB;
+            prev_data = 0;
+            return false;
+
+        case RX_STATE_WAIT_LENGTH_MSB:
+            if (data == ADP_TOKEN)
+            {
+                if (prev_data != ADP_TOKEN)
+                {
+                    prev_data = ADP_TOKEN;
+                    return false;
+                }
+            }
+            length_received += (uint16_t)data << 8;
+            prev_data = 0;
+            /* Got valid length, do we expect data? */
+            if (length_received == 0)
+            {
+                /* No data here, wait for next packet */
+                rx_state = RX_STATE_IDLE;
+                packet_received = true;
+                last_received_message_id = message_id;
+                return false;
+            }
+
+            /* Wait for packet data */
+            bytes_received = 0;
+            rx_state = RX_STATE_GET_DATA;
+            return false;
+
+        case RX_STATE_GET_DATA:
+        case RX_STATE_GOT_SYMBOL:
+            if ((data == ADP_TOKEN) && (rx_state == RX_STATE_GET_DATA))
+            {
+                rx_state = RX_STATE_GOT_SYMBOL;
+                return false;
+            }
+            /* Add new data to rx buffer */
+            bytes_received++;
+            /* Are we done yet? */
+            if (length_received == bytes_received)
+            {
+                /* Yes we are! */
+                packet_received = true;
+                rx_state = RX_STATE_IDLE;
+                last_received_message_id = message_id;
+                return true;
+            }
+            /* Not done yet.. keep on receiving */
+            rx_state = RX_STATE_GET_DATA;
+            return true;
+    }
+    return false;
 }
 
 static bool adp_is_received(void)
 {
-	if (bytes_received == 0) {
-		return false;
-	}
-	return packet_received;
+    if (bytes_received == 0)
+    {
+        return false;
+    }
+    return packet_received;
 }
 
 static uint8_t adp_packet_received_get_id(void)
 {
-	return last_received_message_id;
+    return last_received_message_id;
 }
 
 static bool adp_protocol_add_byte(uint8_t rx_id, uint8_t* rx_buf, uint8_t length, uint8_t* protocol_buf)
 {
-	uint8_t i;
-
-	for (i = 0; i < length; i++)
-	{
-		if (adp_add_receive_byte(*(rx_buf + i)) == true) {
-			/* This is a data byte */
-			protocol_buf[bytes_received - 1] = *(rx_buf + i);
-		}
-		if (adp_is_received() & (adp_packet_received_get_id() == rx_id)) {
-			return true;
-		}
-	}
-	return false;
+    uint8_t i;
+
+    for (i = 0; i < length; i++)
+    {
+        if (adp_add_receive_byte(*(rx_buf + i)) == true)
+        {
+            /* This is a data byte */
+            protocol_buf[bytes_received - 1] = *(rx_buf + i);
+        }
+        if (adp_is_received() & (adp_packet_received_get_id() == rx_id))
+        {
+            return true;
+        }
+    }
+    return false;
 }
 
 static bool adp_check_for_response(uint8_t rx_id, uint8_t* protocol_buf, uint8_t length)
 {
-	uint8_t retry;
-	bool status = false;
-	uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
-
-	retry = 50;
-	length = length + ADP_LENGTH_PACKET_HEADER;
-	packet_received = false;
-	while((adp_is_received() == false) & (retry-- > 0)) {	
-		if(adp_interface_read_response(rx_buf, length) == STATUS_OK) {
-			status = adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
-			if(status == true) {
-				break;
-			}
-		}
-	}
-	
-	return status;
+    uint8_t retry;
+    bool status = false;
+    uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
+
+    retry = 50;
+    length = length + ADP_LENGTH_PACKET_HEADER;
+    packet_received = false;
+    while((adp_is_received() == false) & (retry-- > 0))
+    {
+        if(adp_interface_read_response(rx_buf, length) == STATUS_OK)
+        {
+            status = adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
+            if(status == true)
+            {
+                break;
+            }
+        }
+    }
+
+    return status;
 }
 
 static void adp_wait_for_response(uint8_t rx_id, uint8_t* protocol_buf, uint8_t length)
 {
-	uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
-
-	packet_received = false;
-	length = length + ADP_LENGTH_PACKET_HEADER;
-	while((adp_is_received() == false)) {
-		if(adp_interface_read_response(rx_buf, length) == STATUS_OK) {
-			adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
-		}
-	}
+    uint8_t rx_buf[ADP_MAX_PACKET_DATA_SIZE] = {0,};
+
+    packet_received = false;
+    length = length + ADP_LENGTH_PACKET_HEADER;
+    while((adp_is_received() == false))
+    {
+        if(adp_interface_read_response(rx_buf, length) == STATUS_OK)
+        {
+            adp_protocol_add_byte(rx_id, rx_buf, length, protocol_buf);
+        }
+    }
 }
 
 /**
@@ -246,7 +267,7 @@ static void adp_wait_for_response(uint8_t rx_id, uint8_t* protocol_buf, uint8_t
 */
 void adp_init(void)
 {
-	adp_interface_init();
+    adp_interface_init();
 }
 
 /**
@@ -261,25 +282,25 @@ void adp_init(void)
 */
 static bool adp_request_handshake(uint8_t protocol_version, uint8_t options, uint8_t* protocol_buf)
 {
-	uint16_t data_length = MSQ_REQ_HANDSHAKE_LEN + ADP_LENGTH_PACKET_HEADER;
-	uint8_t key[8] = ADP_HANDSHAKE_KEY;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	struct adp_msg_request_handshake msg_request_handshake;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_REQ_HANDSHAKE;
-	msg_format.data_length = MSQ_REQ_HANDSHAKE_LEN;
-	
-	msg_request_handshake.protocol_version = protocol_version;
-	msg_request_handshake.options = options;
-	memcpy(&msg_request_handshake.key, key, 8);
-	memcpy((uint8_t*)&msg_format.data, &msg_request_handshake, sizeof(msg_request_handshake));
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	return adp_check_for_response(MSG_RES_HANDSHAKE, protocol_buf, 1);
+    uint16_t data_length = MSQ_REQ_HANDSHAKE_LEN + ADP_LENGTH_PACKET_HEADER;
+    uint8_t key[8] = ADP_HANDSHAKE_KEY;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+    struct adp_msg_request_handshake msg_request_handshake;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_REQ_HANDSHAKE;
+    msg_format.data_length = MSQ_REQ_HANDSHAKE_LEN;
+
+    msg_request_handshake.protocol_version = protocol_version;
+    msg_request_handshake.options = options;
+    memcpy(&msg_request_handshake.key, key, 8);
+    memcpy((uint8_t*)&msg_format.data, &msg_request_handshake, sizeof(msg_request_handshake));
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    return adp_check_for_response(MSG_RES_HANDSHAKE, protocol_buf, 1);
 }
 
 
@@ -292,14 +313,15 @@ static bool adp_request_handshake(uint8_t protocol_version, uint8_t options, uin
 */
 enum adp_handshake_status adp_wait_for_handshake(void)
 {
-	uint8_t handshake_status;
+    uint8_t handshake_status;
 
-	/* Keep sending handshake until we get something back */
-	while (adp_request_handshake(ADP_VERSION, ADP_HANDSHAKE_OPTIONS_GPIO, &handshake_status) == false) {
-	}
+    /* Keep sending handshake until we get something back */
+    while (adp_request_handshake(ADP_VERSION, ADP_HANDSHAKE_OPTIONS_GPIO, &handshake_status) == false)
+    {
+    }
 
-	/* Return status */
-	return ((enum adp_handshake_status)handshake_status);
+    /* Return status */
+    return ((enum adp_handshake_status)handshake_status);
 }
 
 
@@ -312,21 +334,21 @@ enum adp_handshake_status adp_wait_for_handshake(void)
 */
 enum adp_status_code adp_request_status(void)
 {
-	uint16_t data_length = MSG_REQ_STATUS_LEN + ADP_LENGTH_PACKET_HEADER;
-	uint16_t status;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_REQ_STATUS;
-	msg_format.data_length = MSG_REQ_STATUS_LEN;
-
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	/* Wait for response from PC */
-	adp_wait_for_response(MSG_RES_STATUS, (uint8_t*)&status, 2);
-	return ((enum adp_status_code)status);
+    uint16_t data_length = MSG_REQ_STATUS_LEN + ADP_LENGTH_PACKET_HEADER;
+    uint16_t status;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_REQ_STATUS;
+    msg_format.data_length = MSG_REQ_STATUS_LEN;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+    /* Wait for response from PC */
+    adp_wait_for_response(MSG_RES_STATUS, (uint8_t*)&status, 2);
+    return ((enum adp_status_code)status);
 }
 
 
@@ -342,36 +364,36 @@ enum adp_status_code adp_request_status(void)
 */
 bool adp_configure_info(const char* title, const char* description)
 {
-	uint16_t title_len;
-	uint16_t description_len;
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	
-	struct adp_msg_format msg_format;
-
-	/* Add null-termination to length */
-	title_len = strlen(title) + 1;
-	description_len = strlen(description) + 1;
-	/* Make sure the strings are not too long */
-	Assert(title_len + description_len <= ADP_MAX_PACKET_DATA_SIZE);	
-	
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_INFO;
-	msg_format.data_length = title_len + description_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)description, description_len);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-
-	return (ack == ADP_ACK_OK);
+    uint16_t title_len;
+    uint16_t description_len;
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+
+    struct adp_msg_format msg_format;
+
+    /* Add null-termination to length */
+    title_len = strlen(title) + 1;
+    description_len = strlen(description) + 1;
+    /* Make sure the strings are not too long */
+    Assert(title_len + description_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_INFO;
+    msg_format.data_length = title_len + description_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)description, description_len);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -385,35 +407,35 @@ bool adp_configure_info(const char* title, const char* description)
 */
 bool adp_configure_stream(struct adp_msg_configure_stream *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t label_len;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-
-	/* Add null-termination to length */
-	label_len = strlen(label) + 1;
-	/* Make sure the strings are not too long */
-	Assert(label_len <= ADP_MAX_PACKET_DATA_SIZE);
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_STREAM;
-	msg_format.data_length = MSG_CONF_STREAM_LEN + label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->type, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t label_len;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    /* Add null-termination to length */
+    label_len = strlen(label) + 1;
+    /* Make sure the strings are not too long */
+    Assert(label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_STREAM;
+    msg_format.data_length = MSG_CONF_STREAM_LEN + label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->type, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -429,26 +451,26 @@ bool adp_configure_stream(struct adp_msg_configure_stream *const config, const c
 */
 bool adp_toggle_stream(struct adp_msg_toggle_stream *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_TOGGLE_STREAM;
-	msg_format.data_length = MSG_CONF_TOGGLE_STREAM_LEN;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_TOGGLE_STREAM;
+    msg_format.data_length = MSG_CONF_TOGGLE_STREAM_LEN;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->state, 1);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -462,41 +484,41 @@ bool adp_toggle_stream(struct adp_msg_toggle_stream *const config)
 * \retval false  Message received but not accepted
 */
 bool adp_configure_graph(struct adp_msg_configure_graph *const config, \
-						const char* graph_label, const char* x_label)
+                        const char* graph_label, const char* x_label)
 {
-	uint8_t ack;
-	uint16_t graph_label_len, x_label_len;
-
-	/* Add 0-termination to label string length */
-	graph_label_len = strlen(graph_label) + 1;
-	x_label_len = strlen(x_label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_GRAPH;
-	msg_format.data_length = MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)graph_label, graph_label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)x_label, x_label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, MSG_CONF_GRAPH_LEN - 10);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t graph_label_len, x_label_len;
+
+    /* Add 0-termination to label string length */
+    graph_label_len = strlen(graph_label) + 1;
+    x_label_len = strlen(x_label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_GRAPH;
+    msg_format.data_length = MSG_CONF_GRAPH_LEN + graph_label_len + x_label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)graph_label, graph_label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)x_label, x_label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, MSG_CONF_GRAPH_LEN - 10);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -511,35 +533,35 @@ bool adp_configure_graph(struct adp_msg_configure_graph *const config, \
 */
 bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t label_len;
-
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_TERMINAL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_TERMINAL;
-	msg_format.data_length = MSG_CONF_TERMINAL_LEN + label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->width, MSG_CONF_TERMINAL_LEN - 1);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t label_len;
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_TERMINAL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_TERMINAL;
+    msg_format.data_length = MSG_CONF_TERMINAL_LEN + label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->width, MSG_CONF_TERMINAL_LEN - 1);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -553,37 +575,37 @@ bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const ch
 */
 bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const config, const char* tag_text)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t tag_text_len;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	/* Add 0-termination to label string length */
-	tag_text_len = strlen(tag_text) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len <= ADP_MAX_PACKET_DATA_SIZE);
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_ADD_TO_TERMINAL;
-	msg_format.data_length = MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->text_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_text, tag_text_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->tag_text_color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t tag_text_len;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    /* Add 0-termination to label string length */
+    tag_text_len = strlen(tag_text) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_ADD_TO_TERMINAL;
+    msg_format.data_length = MSG_CONF_ADD_TO_TERMINAL_LEN + tag_text_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->terminal_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->text_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_text, tag_text_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->tag_text_color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -598,40 +620,40 @@ bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const con
 */
 bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint16_t label_len;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_AXIS_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_AXIS;
-	msg_format.data_length = MSG_CONF_AXIS_LEN + label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_denominator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint16_t label_len;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_AXIS_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_AXIS;
+    msg_format.data_length = MSG_CONF_AXIS_LEN + label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_numerator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_scale_denominator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -646,36 +668,36 @@ bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* l
 */
 bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_AXIS;
-	msg_format.data_length = MSG_CONF_ADD_STREAM_TO_AXIS_LEN;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_numerator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_denominator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_numerator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_denominator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_offset, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_AXIS;
+    msg_format.data_length = MSG_CONF_ADD_STREAM_TO_AXIS_LEN;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_numerator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->sample_rate_denominator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_numerator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_scale_denominator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_offset, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 
@@ -690,44 +712,44 @@ bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config)
 */
 bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint16_t label_len;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_CURSOR_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_CURSOR_TO_GRAPH;
-	msg_format.data_length = MSG_CONF_CURSOR_TO_GRAPH_LEN;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->thickness, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_numerator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_denominator, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_offset, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint16_t label_len;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_CURSOR_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_CURSOR_TO_GRAPH;
+    msg_format.data_length = MSG_CONF_CURSOR_TO_GRAPH_LEN;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->axis_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->thickness, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_numerator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_denominator, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->scale_offset, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -742,46 +764,46 @@ bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, c
 * \retval false  Message received but not accepted
 */
 bool adp_add_gpio_to_graph(struct adp_msg_conf_gpio_to_graph *const config, \
-					const char* tag_high_state, const char* tag_low_state)
+                    const char* tag_high_state, const char* tag_low_state)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint16_t label_len, tag_high_state_len, tag_low_state_len;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	/* Add 0-termination to label string length */
-	tag_high_state_len = strlen(tag_high_state) + 1;
-	tag_low_state_len = strlen(tag_low_state) + 1;
-	label_len = tag_high_state_len + tag_low_state_len;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_GPIO_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_GPIO_TO_GRAPH;
-	msg_format.data_length = MSG_CONF_GPIO_TO_GRAPH_LEN + label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->gpio_number, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_high_state, tag_high_state_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_low_state, tag_low_state_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_high_state, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_low_state, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint16_t label_len, tag_high_state_len, tag_low_state_len;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    /* Add 0-termination to label string length */
+    tag_high_state_len = strlen(tag_high_state) + 1;
+    tag_low_state_len = strlen(tag_low_state) + 1;
+    label_len = tag_high_state_len + tag_low_state_len;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_GPIO_TO_GRAPH_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_GPIO_TO_GRAPH;
+    msg_format.data_length = MSG_CONF_GPIO_TO_GRAPH_LEN + label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->gpio_number, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_id, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_high_state, tag_high_state_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)tag_low_state, tag_low_state_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_thickness, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_high_state, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_color_low_state, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->line_style, 1);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -796,51 +818,51 @@ bool adp_add_gpio_to_graph(struct adp_msg_conf_gpio_to_graph *const config, \
 */
 bool adp_add_dashboard(struct adp_msg_conf_dashboard *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t label_len;
-
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(MSG_CONF_DASHBOARD_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD;
-	msg_format.data_length = MSG_CONF_DASHBOARD_LEN + label_len;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index,(uint8_t*)&config->dashboard_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->height, 2);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t label_len;
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(MSG_CONF_DASHBOARD_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD;
+    msg_format.data_length = MSG_CONF_DASHBOARD_LEN + label_len;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index,(uint8_t*)&config->dashboard_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->height, 2);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 static uint16_t adp_add_dashboard_element_common_send_byte(uint8_t* add_buf, uint16_t index, \
-									struct adp_msg_conf_dashboard_element_common *const config)
+                                    struct adp_msg_conf_dashboard_element_common *const config)
 {
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->dashboard_id, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_id, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->z_index, 1);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->x, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->y, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->width, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->height, 2);
-	index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_type, 1);
-	
-	return index;
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->dashboard_id, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_id, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->z_index, 1);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->x, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->y, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->width, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->height, 2);
+    index = adp_add_send_byte(add_buf, index, (uint8_t *)&config->element_type, 1);
+
+    return index;
 }
 
 /**
@@ -854,43 +876,43 @@ static uint16_t adp_add_dashboard_element_common_send_byte(uint8_t* add_buf, uin
 */
 bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t label_len;
-
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(ADP_ELEMENT_TYPE_LABEL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_LABEL_LEN + label_len;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->attribute, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->horisontal_alignment, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->vertical_alignment, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t label_len;
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(ADP_ELEMENT_TYPE_LABEL_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_LABEL_LEN + label_len;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->attribute, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->horisontal_alignment, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->vertical_alignment, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->foreground_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -904,36 +926,36 @@ bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *con
 */
 bool adp_add_button_to_dashboard(struct adp_msg_conf_dashboard_element_button *const config, const char* label)
 {
-	uint8_t ack;
-	uint16_t label_len;
-
-	/* Add 0-termination to label string length */
-	label_len = strlen(label) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(ADP_ELEMENT_TYPE_BUTTON_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_BUTTON_LEN + label_len;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-										(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t label_len;
+
+    /* Add 0-termination to label string length */
+    label_len = strlen(label) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(ADP_ELEMENT_TYPE_BUTTON_LEN + label_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_BUTTON_LEN + label_len;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                        (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)label, label_len);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -946,30 +968,30 @@ bool adp_add_button_to_dashboard(struct adp_msg_conf_dashboard_element_button *c
 * \retval false  Message received but not accepted
 */
 bool adp_add_slider_to_dashboard(struct adp_msg_conf_dashboard_element_slider *const config)
-{	
-		uint8_t ack;
-		uint16_t data_length;
-		uint16_t index = 0;
-		uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-		
-		struct adp_msg_format msg_format;
-		
-		msg_format.protocol_token = ADP_TOKEN;
-		msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-		msg_format.data_length = ADP_ELEMENT_TYPE_SLIDER_LEN;
-		index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-												(struct adp_msg_conf_dashboard_element_common *)config);
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
-		data_length = ADP_LENGTH_PACKET_HEADER + index;
-		
-		/* Send the protocol packet data */
-		adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-		
-		/* Wait for response and return status */
-		adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-		return (ack == ADP_ACK_OK);
+{
+        uint8_t ack;
+        uint16_t data_length;
+        uint16_t index = 0;
+        uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+        struct adp_msg_format msg_format;
+
+        msg_format.protocol_token = ADP_TOKEN;
+        msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+        msg_format.data_length = ADP_ELEMENT_TYPE_SLIDER_LEN;
+        index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                                (struct adp_msg_conf_dashboard_element_common *)config);
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+        data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+        /* Send the protocol packet data */
+        adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+        /* Wait for response and return status */
+        adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+        return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -983,30 +1005,30 @@ bool adp_add_slider_to_dashboard(struct adp_msg_conf_dashboard_element_slider *c
 */
 bool adp_add_progress_to_dashboard(struct adp_msg_conf_dashboard_element_progress *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_PROGRESS_LEN;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_PROGRESS_LEN;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->initial_value, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1020,30 +1042,30 @@ bool adp_add_progress_to_dashboard(struct adp_msg_conf_dashboard_element_progres
 */
 bool adp_add_signal_to_dashboard(struct adp_msg_conf_dashboard_element_signal *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_SIGNAL_LEN;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_SIGNAL_LEN;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->on_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->off_color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1057,30 +1079,30 @@ bool adp_add_signal_to_dashboard(struct adp_msg_conf_dashboard_element_signal *c
 */
 bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_SEGMENT_LEN;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->segment_count, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->base, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_SEGMENT_LEN;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->segment_count, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->base, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->transparency, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->color, 3);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1094,45 +1116,45 @@ bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment
 */
 bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *const config, const char* title)
 {
-	uint8_t ack;
-	uint16_t title_len;
-
-	/* Add 0-termination to label string length */
-	title_len = strlen(title) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(ADP_ELEMENT_TYPE_GRAPH_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_GRAPH_LEN + title_len;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-										(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_background_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->plot_count, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
-	
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t title_len;
+
+    /* Add 0-termination to label string length */
+    title_len = strlen(title) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(ADP_ELEMENT_TYPE_GRAPH_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_GRAPH_LEN + title_len;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                        (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->graph_background_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->plot_count, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_min, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->x_max, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_min, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->y_max, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->mode, 1);
+
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1146,29 +1168,29 @@ bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *con
 */
 bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_TEXT_LEN;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum, 4);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->value, 4);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_TEXT_LEN;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->minimum, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->maximum, 4);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->value, 4);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1182,38 +1204,38 @@ bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const
 */
 bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *const config, const char* text)
 {
-	uint8_t ack;
-	uint16_t text_len;
-
-	/* Add 0-termination to label string length */
-	text_len = strlen(text) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(ADP_ELEMENT_TYPE_RADIO_LEN + text_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_RADIO_LEN + text_len;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_items, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->orientation, 1);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)text, text_len);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t text_len;
+
+    /* Add 0-termination to label string length */
+    text_len = strlen(text) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(ADP_ELEMENT_TYPE_RADIO_LEN + text_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_RADIO_LEN + text_len;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->font_size, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_items, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->orientation, 1);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)text, text_len);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1227,38 +1249,38 @@ bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *con
 */
 bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const config, const char* title)
 {
-	uint8_t ack;
-	uint16_t title_len;
-
-	/* Add 0-termination to label string length */
-	title_len = strlen(title) + 1;
-
-	/* Make sure label isn't too big */
-	Assert(ADP_ELEMENT_TYPE_PIE_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
-
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
-	msg_format.data_length = ADP_ELEMENT_TYPE_PIE_LEN + title_len;
-	index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
-											(struct adp_msg_conf_dashboard_element_common *)config);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_slices, 1);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t title_len;
+
+    /* Add 0-termination to label string length */
+    title_len = strlen(title) + 1;
+
+    /* Make sure label isn't too big */
+    Assert(ADP_ELEMENT_TYPE_PIE_LEN + title_len <= ADP_MAX_PACKET_DATA_SIZE);
+
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_DASHBOARD_ELEMENT;
+    msg_format.data_length = ADP_ELEMENT_TYPE_PIE_LEN + title_len;
+    index = adp_add_dashboard_element_common_send_byte((uint8_t*)&msg_format.data, index, \
+                                            (struct adp_msg_conf_dashboard_element_common *)config);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->background_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->title_color, 3);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)title, title_len);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->number_slices, 1);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 /**
@@ -1272,59 +1294,60 @@ bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const c
 */
 bool adp_add_stream_to_element(struct adp_conf_add_stream_to_element *const config)
 {
-	uint8_t ack;
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_ELEMENT;
-	msg_format.data_length = MSG_CONF_ADD_STREAM_TO_ELEMENT_LEN;
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->dashboard_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->element_id, 2);
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-
-	/* Wait for response and return status */
-	adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
-	return (ack == ADP_ACK_OK);
+    uint8_t ack;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_CONF_ADD_STREAM_TO_ELEMENT;
+    msg_format.data_length = MSG_CONF_ADD_STREAM_TO_ELEMENT_LEN;
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->dashboard_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->element_id, 2);
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&config->stream_id, 2);
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    /* Wait for response and return status */
+    adp_wait_for_response(MSG_CONF_ACK, &ack, 1);
+    return (ack == ADP_ACK_OK);
 }
 
 bool adp_transceive_stream(struct adp_msg_data_stream *const stream_data, uint8_t *protocol_buf)
 {
-	uint8_t stream_num;	
-	uint16_t data_length;
-	uint16_t index = 0;
-	uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
-	
-	struct adp_msg_format msg_format;
-	
-	index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&stream_data->number_of_streams, 1);
-	/* find packet size */
-	for (stream_num = 0; stream_num < stream_data->number_of_streams; stream_num++) {
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
-						(uint8_t*)&stream_data->stream[stream_num].stream_id, 2);
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
-						(uint8_t*)&stream_data->stream[stream_num].data_size, 1);
-		index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
-						stream_data->stream[stream_num].data, \
-						stream_data->stream[stream_num].data_size);
-	}
-	
-	msg_format.protocol_token = ADP_TOKEN;
-	msg_format.protocol_msg_id = MSG_DATA_STREAM;
-	msg_format.data_length = index;
-	data_length = ADP_LENGTH_PACKET_HEADER + index;
-	
-	/* Send the protocol packet data */
-	adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
-	
-	return adp_protocol_add_byte(MSG_RES_DATA, rx_buf, data_length, protocol_buf);
+    uint8_t stream_num;
+    uint16_t data_length;
+    uint16_t index = 0;
+    uint8_t rx_buf[ADP_MAX_PACKET_LENGTH] = {0,};
+
+    struct adp_msg_format msg_format;
+
+    index = adp_add_send_byte((uint8_t*)&msg_format.data, index, (uint8_t*)&stream_data->number_of_streams, 1);
+    /* find packet size */
+    for (stream_num = 0; stream_num < stream_data->number_of_streams; stream_num++)
+    {
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+                        (uint8_t*)&stream_data->stream[stream_num].stream_id, 2);
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+                        (uint8_t*)&stream_data->stream[stream_num].data_size, 1);
+        index = adp_add_send_byte((uint8_t*)&msg_format.data, index, \
+                        stream_data->stream[stream_num].data, \
+                        stream_data->stream[stream_num].data_size);
+    }
+
+    msg_format.protocol_token = ADP_TOKEN;
+    msg_format.protocol_msg_id = MSG_DATA_STREAM;
+    msg_format.data_length = index;
+    data_length = ADP_LENGTH_PACKET_HEADER + index;
+
+    /* Send the protocol packet data */
+    adp_interface_transceive_procotol((uint8_t*)&msg_format, data_length, rx_buf);
+
+    return adp_protocol_add_byte(MSG_RES_DATA, rx_buf, data_length, protocol_buf);
 }
 
 
@@ -1339,15 +1362,15 @@ bool adp_transceive_stream(struct adp_msg_data_stream *const stream_data, uint8_
 */
 bool adp_transceive_single_stream(uint16_t stream_id, uint8_t* data, uint8_t data_size, uint8_t* protocol_buf)
 {
-	struct adp_msg_data_stream data_stream;
-	volatile uint8_t status;
-
-	data_stream.number_of_streams = 1;
-	data_stream.stream[0].stream_id = stream_id;
-	data_stream.stream[0].data_size = data_size;
-	data_stream.stream[0].data = data;
-	status = adp_transceive_stream(&data_stream, protocol_buf);
-	
-	return status;
+    struct adp_msg_data_stream data_stream;
+    volatile uint8_t status;
+
+    data_stream.number_of_streams = 1;
+    data_stream.stream[0].stream_id = stream_id;
+    data_stream.stream[0].data_size = data_size;
+    data_stream.stream[0].data = data;
+    status = adp_transceive_stream(&data_stream, protocol_buf);
+
+    return status;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h
index 4e8656ca6d46..ef13f8400022 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/adp.h
@@ -96,18 +96,18 @@
 
 /** States in receive state machine */
 enum rx_state_e {
-	/** We are idle, waiting for a new packet */
-	RX_STATE_IDLE,
-	/** Start symbol received, waiting for Message ID */
-	RX_STATE_WAIT_MSG_ID,
-	/** Message ID received, waiting for data length */
-	RX_STATE_WAIT_LENGTH_LSB,
-	/** Message ID received, waiting for data length */
-	RX_STATE_WAIT_LENGTH_MSB,
-	/** Length received; we are receiving packet data */
-	RX_STATE_GET_DATA,
-	/** Start symbol received */
-	RX_STATE_GOT_SYMBOL,
+    /** We are idle, waiting for a new packet */
+    RX_STATE_IDLE,
+    /** Start symbol received, waiting for Message ID */
+    RX_STATE_WAIT_MSG_ID,
+    /** Message ID received, waiting for data length */
+    RX_STATE_WAIT_LENGTH_LSB,
+    /** Message ID received, waiting for data length */
+    RX_STATE_WAIT_LENGTH_MSB,
+    /** Length received; we are receiving packet data */
+    RX_STATE_GET_DATA,
+    /** Start symbol received */
+    RX_STATE_GOT_SYMBOL,
 };
 
 /** Max length of labels */
@@ -115,27 +115,27 @@ enum rx_state_e {
 
 static inline void adp_set_color(uint8_t* struct_member, uint8_t c_red, uint8_t c_green, uint8_t c_blue)
 {
-	struct_member[0] = c_red;
-	struct_member[1] = c_green;
-	struct_member[2] = c_blue;
+    struct_member[0] = c_red;
+    struct_member[1] = c_green;
+    struct_member[2] = c_blue;
 }
 
 
 #define adp_set_string(struct_member, string)                  \
-		Assert(sizeof(struct_member));                         \
-		strncpy(struct_member, string, sizeof(struct_member)); \
-		struct_member[sizeof(struct_member)-1] = '\0';
+        Assert(sizeof(struct_member));                         \
+        strncpy(struct_member, string, sizeof(struct_member)); \
+        struct_member[sizeof(struct_member)-1] = '\0';
 
 /* MESSAGE FORMAT */
 SHORTENUM struct adp_msg_format {
-	/* Start token for ADP data */
-	uint8_t protocol_token;
-	/* Describes what data is sent */
-	uint8_t protocol_msg_id;
-	/* Length of data packet */
-	uint16_t data_length;
-	/* Data packet for the message */
-	uint8_t data[ADP_MAX_PACKET_DATA_SIZE];
+    /* Start token for ADP data */
+    uint8_t protocol_token;
+    /* Describes what data is sent */
+    uint8_t protocol_msg_id;
+    /* Length of data packet */
+    uint16_t data_length;
+    /* Data packet for the message */
+    uint8_t data[ADP_MAX_PACKET_DATA_SIZE];
 };
 
 
@@ -143,34 +143,34 @@ SHORTENUM struct adp_msg_format {
 #define MSG_REQ_HANDSHAKE 0x00
 #define MSQ_REQ_HANDSHAKE_LEN 10
 enum adp_handshake_options {
-	/* Use GPIO */
-	ADP_HANDSHAKE_OPTIONS_GPIO,
-	/* Lock configuration */
-	ADP_HANDSHAKE_OPTIONS_LOCK,
+    /* Use GPIO */
+    ADP_HANDSHAKE_OPTIONS_GPIO,
+    /* Lock configuration */
+    ADP_HANDSHAKE_OPTIONS_LOCK,
 };
 SHORTENUM struct adp_msg_request_handshake {
-	/* Version of protocol on target */
-	uint8_t protocol_version;
-	/* Is GPIO in use in this app?
-	 * Can user change configuration on PC side? 
-	 */
-	uint8_t options;
-	/* Token used to verify ADP protocol */
-	uint8_t key[8];
+    /* Version of protocol on target */
+    uint8_t protocol_version;
+    /* Is GPIO in use in this app?
+     * Can user change configuration on PC side?
+     */
+    uint8_t options;
+    /* Token used to verify ADP protocol */
+    uint8_t key[8];
 };
 
 /* MSG_RES_HANDSHAKE */
 #define MSG_RES_HANDSHAKE 0x10
 enum adp_handshake_status {
-	/* Handshake accepted */
-	ADP_HANDSHAKE_ACCEPTED,
-	/* Handshake rejected. Invalid protocol version */
-	ADP_HANDSHAKE_REJECTED_PROTOCOL,
-	/* Handshake rejected. Other reason */
-	ADP_HANDSHAKE_REJECTED_OTHER,
+    /* Handshake accepted */
+    ADP_HANDSHAKE_ACCEPTED,
+    /* Handshake rejected. Invalid protocol version */
+    ADP_HANDSHAKE_REJECTED_PROTOCOL,
+    /* Handshake rejected. Other reason */
+    ADP_HANDSHAKE_REJECTED_OTHER,
 };
 SHORTENUM struct adp_msg_response_handshake {
-	enum adp_handshake_status status;
+    enum adp_handshake_status status;
 };
 
 enum adp_handshake_status adp_wait_for_handshake(void);
@@ -183,21 +183,21 @@ enum adp_handshake_status adp_wait_for_handshake(void);
 /* MSG_RES_STATUS */
 #define MSG_RES_STATUS 0x12
 enum adp_status_code {
-	/* Invalid packet received */
-	ADP_STATUS_INVALID_PACKET,
-	/* Invalid configuration data received */
-	ADP_STATUS_INVALID_CONFIGURATION,
-	/* Data ready to be transmitted to target */
-	ADP_STATUS_DATA_READY,
-	/* Invalid stream request (req_data) */
-	ADP_STATUS_INVALID_REQUEST,
-	/* No data available on stream (req_data) */
-	ADP_STATUS_NO_DATA,
-	/* Request target software reset */
-	ADP_STATUS_RESET,
+    /* Invalid packet received */
+    ADP_STATUS_INVALID_PACKET,
+    /* Invalid configuration data received */
+    ADP_STATUS_INVALID_CONFIGURATION,
+    /* Data ready to be transmitted to target */
+    ADP_STATUS_DATA_READY,
+    /* Invalid stream request (req_data) */
+    ADP_STATUS_INVALID_REQUEST,
+    /* No data available on stream (req_data) */
+    ADP_STATUS_NO_DATA,
+    /* Request target software reset */
+    ADP_STATUS_RESET,
 };
 SHORTENUM struct adp_msg_response_status {
-	enum adp_status_code status;
+    enum adp_status_code status;
 };
 
 enum adp_status_code adp_request_status(void);
@@ -206,57 +206,57 @@ enum adp_status_code adp_request_status(void);
 #define MSG_RES_DATA 0x14
 #define MSG_RES_DATA_MAX_LEN (ADP_MAX_BYTE_REQUEST + 4)
 SHORTENUM struct adp_msg_response_data {
-	/* ID of stream */
-	uint8_t stream_id;
-	/* Number of bytes in packet. 
-	 * If the target has requested data from an unknown stream, or if stream 
-	 * has no data to send, this field should be set to 0 and the appropriate 
-	 * status flag should be set.
-	 */
-	uint8_t bytes_sent;
-	/* The data */		
-	uint8_t data[ADP_MAX_BYTE_REQUEST];
+    /* ID of stream */
+    uint8_t stream_id;
+    /* Number of bytes in packet.
+     * If the target has requested data from an unknown stream, or if stream
+     * has no data to send, this field should be set to 0 and the appropriate
+     * status flag should be set.
+     */
+    uint8_t bytes_sent;
+    /* The data */
+    uint8_t data[ADP_MAX_BYTE_REQUEST];
 };
 
 void adp_request_data(uint8_t stream_id, uint8_t bytes_to_send, struct adp_msg_response_data *response);
 
 #define MSG_RES_PACKET_DATA_MAX_LEN (ADP_MAX_BYTE_REQUEST + 2)
 SHORTENUM struct adp_msg_packet_data {
-	uint16_t stream_id;
-	uint8_t bytes_sent;
-	uint8_t data[ADP_MAX_BYTE_REQUEST];
+    uint16_t stream_id;
+    uint8_t bytes_sent;
+    uint8_t data[ADP_MAX_BYTE_REQUEST];
 };
 bool adp_receive_packet_data(uint8_t *receive_buf);
 
 /* MSG_CONF_STREAM */
 enum adp_stream_type {
-	ADP_STREAM_EVENT,
-	ADP_STREAM_STRING,
-	ADP_STREAM_UINT_8,
-	ADP_STREAM_INT_8,
-	ADP_STREAM_UINT_16,
-	ADP_STREAM_INT_16,
-	ADP_STREAM_UINT_32,
-	ADP_STREAM_INT_32,
-	ADP_STREAM_XY_8,
-	ADP_STREAM_XY_16,
-	ADP_STREAM_XY_32,
-	ADP_STREAM_BOOL,
-	ADP_STREAM_FLOAT,
+    ADP_STREAM_EVENT,
+    ADP_STREAM_STRING,
+    ADP_STREAM_UINT_8,
+    ADP_STREAM_INT_8,
+    ADP_STREAM_UINT_16,
+    ADP_STREAM_INT_16,
+    ADP_STREAM_UINT_32,
+    ADP_STREAM_INT_32,
+    ADP_STREAM_XY_8,
+    ADP_STREAM_XY_16,
+    ADP_STREAM_XY_32,
+    ADP_STREAM_BOOL,
+    ADP_STREAM_FLOAT,
 };
 
 enum adp_stream_state {
-	ADP_STREAM_OFF,
-	ADP_STREAM_ON,
+    ADP_STREAM_OFF,
+    ADP_STREAM_ON,
 };
 
 enum adp_stream_mode {
-	/* Incoming (normal) */
-	ADP_STREAM_IN,
-	/* Incoming (single value) */
-	ADP_STREAM_IN_SINGLE,
-	/* Outgoing */
-	ADP_STREAM_OUT,
+    /* Incoming (normal) */
+    ADP_STREAM_IN,
+    /* Incoming (single value) */
+    ADP_STREAM_IN_SINGLE,
+    /* Outgoing */
+    ADP_STREAM_OUT,
 };
 
 #define MSG_CONF_ACK       0x30
@@ -270,23 +270,23 @@ bool adp_configure_info(const char* title, const char* description);
 #define MSG_CONF_STREAM     0x20
 #define MSG_CONF_STREAM_LEN 5
 SHORTENUM struct adp_msg_configure_stream {
-	/* ID of stream */
-	uint16_t stream_id;
-	/* Stream type */
-	enum adp_stream_type type;
-	/* Stream mode/direction */
-	enum adp_stream_mode mode;
-	/* Stream state */
-	enum adp_stream_state state;
+    /* ID of stream */
+    uint16_t stream_id;
+    /* Stream type */
+    enum adp_stream_type type;
+    /* Stream mode/direction */
+    enum adp_stream_mode mode;
+    /* Stream state */
+    enum adp_stream_state state;
 };
 
 static inline void adp_configure_stream_get_defaults(struct adp_msg_configure_stream *const config)
 {
-	Assert(config);
-	config->stream_id = 0;
-	config->type = ADP_STREAM_UINT_8;
-	config->mode = ADP_STREAM_OUT;
-	config->state = ADP_STREAM_ON;
+    Assert(config);
+    config->stream_id = 0;
+    config->type = ADP_STREAM_UINT_8;
+    config->mode = ADP_STREAM_OUT;
+    config->state = ADP_STREAM_ON;
 }
 
 bool adp_configure_stream(struct adp_msg_configure_stream *const config, const char* label);
@@ -295,8 +295,8 @@ bool adp_configure_stream(struct adp_msg_configure_stream *const config, const c
 #define MSG_CONF_TOGGLE_STREAM   0x21
 #define MSG_CONF_TOGGLE_STREAM_LEN 3
 SHORTENUM struct adp_msg_toggle_stream {
-	uint16_t               stream_id;
-	enum adp_stream_state  state;
+    uint16_t               stream_id;
+    enum adp_stream_state  state;
 };
 bool adp_toggle_stream(struct adp_msg_toggle_stream *const config);
 
@@ -305,89 +305,89 @@ bool adp_toggle_stream(struct adp_msg_toggle_stream *const config);
 #define MSG_CONF_GRAPH_LEN       23
 
 enum adp_graph_scale_mode {
-	ADP_GRAPH_SCALE_OFF,
-	ADP_GRAPH_SCALE_AUTO
+    ADP_GRAPH_SCALE_OFF,
+    ADP_GRAPH_SCALE_AUTO
 };
 
 enum adp_graph_scroll_mode {
-	/* No scrolling */
-	ADP_GRAPH_SCROLL_OFF,
-	/* Stepping */
-	ADP_GRAPH_SCROLL_STEP,
-	/* Scroll */
-	ADP_GRAPH_SCROLL_SCROLL,
-	/* Circular/sweep */
-	ADP_GRAPH_SCROLL_CIRCULAR
+    /* No scrolling */
+    ADP_GRAPH_SCROLL_OFF,
+    /* Stepping */
+    ADP_GRAPH_SCROLL_STEP,
+    /* Scroll */
+    ADP_GRAPH_SCROLL_SCROLL,
+    /* Circular/sweep */
+    ADP_GRAPH_SCROLL_CIRCULAR
 };
 
 SHORTENUM struct adp_msg_configure_graph {
-	/* ID of new graph */
-	uint8_t graph_id;
-	/* Range Xmin value */
-	uint32_t x_min;
-	/* Range Xmax value */
-	uint32_t x_max;
-	/* Xscale numerator */
-	uint32_t x_scale_numerator;
-	/* X range scale value. Set to 0 to enable auto range */
-	uint32_t x_scale_denominator;
-	/* Vertical scaling */
-	enum adp_graph_scale_mode scale_mode;
-	/* RGB background color */
-	uint8_t background_color[3];
-	/* Horizontal scrolling */
-	enum adp_graph_scroll_mode scroll_mode;
+    /* ID of new graph */
+    uint8_t graph_id;
+    /* Range Xmin value */
+    uint32_t x_min;
+    /* Range Xmax value */
+    uint32_t x_max;
+    /* Xscale numerator */
+    uint32_t x_scale_numerator;
+    /* X range scale value. Set to 0 to enable auto range */
+    uint32_t x_scale_denominator;
+    /* Vertical scaling */
+    enum adp_graph_scale_mode scale_mode;
+    /* RGB background color */
+    uint8_t background_color[3];
+    /* Horizontal scrolling */
+    enum adp_graph_scroll_mode scroll_mode;
 };
 
 static inline void adp_configure_graph_get_defaults(struct adp_msg_configure_graph *const config)
 {
-	Assert(config);
-	config->graph_id = 0;
-	config->x_min = 0;
-	config->x_max = 0;
-	config->x_scale_numerator = 0;
-	config->x_scale_denominator = 0;
-	config->scale_mode = ADP_GRAPH_SCALE_OFF;
-	adp_set_color(config->background_color, ADP_COLOR_WHITE);
-	config->scroll_mode = ADP_GRAPH_SCROLL_SCROLL;
+    Assert(config);
+    config->graph_id = 0;
+    config->x_min = 0;
+    config->x_max = 0;
+    config->x_scale_numerator = 0;
+    config->x_scale_denominator = 0;
+    config->scale_mode = ADP_GRAPH_SCALE_OFF;
+    adp_set_color(config->background_color, ADP_COLOR_WHITE);
+    config->scroll_mode = ADP_GRAPH_SCROLL_SCROLL;
 }
 
 bool adp_configure_graph(struct adp_msg_configure_graph *const config, \
-						const char* graph_label, const char* x_label);
+                        const char* graph_label, const char* x_label);
 
 /* MSG_CONF_AXIS */
 #define MSG_CONF_AXIS       0x29
 #define MSG_CONF_AXIS_LEN   24
 SHORTENUM struct adp_msg_conf_axis {
-	/* ID of new axis */
-	uint16_t axis_id;
-	/* ID of graph */
-	uint16_t graph_id;
-	/* Range Ymin value */
-	int32_t y_min;
-	/* Range Ymax value */
-	int32_t y_max;
-	/* X range scale value.	Set to 0 to enable auto range */
-	uint32_t x_scale_numerator;
-	/* X range scale value.	Set to 0 to enable auto range */
-	uint32_t x_scale_denominator;
-	/* Mode */
-	uint8_t mode;                                         // TODO
-	/* RGB color */
-	uint8_t color[3];
+    /* ID of new axis */
+    uint16_t axis_id;
+    /* ID of graph */
+    uint16_t graph_id;
+    /* Range Ymin value */
+    int32_t y_min;
+    /* Range Ymax value */
+    int32_t y_max;
+    /* X range scale value. Set to 0 to enable auto range */
+    uint32_t x_scale_numerator;
+    /* X range scale value. Set to 0 to enable auto range */
+    uint32_t x_scale_denominator;
+    /* Mode */
+    uint8_t mode;                                         /* TODO*/
+    /* RGB color */
+    uint8_t color[3];
 };
 
 static inline void adp_add_axis_to_graph_get_defaults(struct adp_msg_conf_axis *const config)
 {
-	Assert(config);
-	config->axis_id = 0;
-	config->graph_id = 0;
-	config->y_min = 0;
-	config->y_max = 0;
-	config->x_scale_numerator = 0;
-	config->x_scale_denominator = 0;
-	config->mode = 0;
-	adp_set_color(config->color, ADP_COLOR_BLACK);
+    Assert(config);
+    config->axis_id = 0;
+    config->graph_id = 0;
+    config->y_min = 0;
+    config->y_max = 0;
+    config->x_scale_numerator = 0;
+    config->x_scale_denominator = 0;
+    config->mode = 0;
+    adp_set_color(config->color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* label);
@@ -400,51 +400,51 @@ bool adp_add_axis_to_graph(struct adp_msg_conf_axis *const config, const char* l
 #define ADP_AXIS_POINTS_bm  0x02
 
 SHORTENUM struct adp_msg_add_stream_to_axis {
-	/* ID of graph */
-	uint16_t graph_id;
-	/* ID of new axis */
-	uint16_t axis_id;
-	/* ID of stream */
-	uint16_t stream_id;
-	/* Sample rate of stream, set to 0 if NA */
-	uint32_t sample_rate_numerator;
-	/* Sample rate of stream, set to 0 if NA */
-	uint32_t sample_rate_denominator;
-	/* Range Ymin value */
-	uint32_t y_scale_numerator;
-	/* Range Ymax value */
-	uint32_t y_scale_denominator;
-	/* Offset of values */
-	uint32_t y_offset;
-	/* Adjust the transparency */
-	uint8_t transparency;
-	/* For graphs:  bit 0 = line on/off
-	 *              bit 1 = points on/off
-	 * For text:    bit 0 = flag
-	 *              bit 1 = text
-	 */
-	uint8_t mode;                           // TODO
-	/* Thickness of line */
-	uint8_t line_thickness;
-	/* RGB color of line */
-	uint8_t line_color[3];
+    /* ID of graph */
+    uint16_t graph_id;
+    /* ID of new axis */
+    uint16_t axis_id;
+    /* ID of stream */
+    uint16_t stream_id;
+    /* Sample rate of stream, set to 0 if NA */
+    uint32_t sample_rate_numerator;
+    /* Sample rate of stream, set to 0 if NA */
+    uint32_t sample_rate_denominator;
+    /* Range Ymin value */
+    uint32_t y_scale_numerator;
+    /* Range Ymax value */
+    uint32_t y_scale_denominator;
+    /* Offset of values */
+    uint32_t y_offset;
+    /* Adjust the transparency */
+    uint8_t transparency;
+    /* For graphs:  bit 0 = line on/off
+     *              bit 1 = points on/off
+     * For text:    bit 0 = flag
+     *              bit 1 = text
+     */
+    uint8_t mode;                           /* TODO*/
+    /* Thickness of line */
+    uint8_t line_thickness;
+    /* RGB color of line */
+    uint8_t line_color[3];
 };
 
 static inline void adp_add_stream_to_axis_get_defaults(struct adp_msg_add_stream_to_axis *const config)
 {
-	Assert(config);
-	config->graph_id = 0;
-	config->axis_id = 0;
-	config->stream_id = 0;
-	config->sample_rate_numerator = 0;
-	config->sample_rate_denominator = 0;
-	config->y_scale_numerator = 0;
-	config->y_scale_denominator = 0;
-	config->y_offset = 0;
-	config->transparency = 0;
-	config->mode = ADP_AXIS_LINE_bm;
-	config->line_thickness = 1;
-	adp_set_color(config->line_color, ADP_COLOR_BLACK);
+    Assert(config);
+    config->graph_id = 0;
+    config->axis_id = 0;
+    config->stream_id = 0;
+    config->sample_rate_numerator = 0;
+    config->sample_rate_denominator = 0;
+    config->y_scale_numerator = 0;
+    config->y_scale_denominator = 0;
+    config->y_offset = 0;
+    config->transparency = 0;
+    config->mode = ADP_AXIS_LINE_bm;
+    config->line_thickness = 1;
+    adp_set_color(config->line_color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config);
@@ -453,47 +453,47 @@ bool adp_add_stream_to_axis(struct adp_msg_add_stream_to_axis *const config);
 #define MSG_CONF_CURSOR_TO_GRAPH     0x24
 #define MSG_CONF_CURSOR_TO_GRAPH_LEN 35
 SHORTENUM struct adp_msg_add_cursor_to_graph {
-	/* ID of streama */
-	uint16_t stream_id;
-	/* ID of graph */
-	uint16_t graph_id;
-	/* ID of axis */
-	uint16_t axis_id;
-	/* Thickness of line */
-	uint8_t thickness;
-	/* RGB color of cursor */
-	uint8_t color[3];
-	/* Starting point of cursor */
-	uint32_t initial_value;
-	/* Minimum allowed value */
-	uint32_t minimum_value;
-	/* Maximum */
-	uint32_t maximum_value;
-	/* Numerator of scaling value */
-	uint32_t scale_numerator;
-	/* Denominator of scaling value */
-	uint32_t scale_denominator;
-	/* Offset of value */
-	uint32_t scale_offset;
-	/* The style of line: Solid, dashed, dotted.. */
-	uint8_t line_style;          // TODO
+    /* ID of streama */
+    uint16_t stream_id;
+    /* ID of graph */
+    uint16_t graph_id;
+    /* ID of axis */
+    uint16_t axis_id;
+    /* Thickness of line */
+    uint8_t thickness;
+    /* RGB color of cursor */
+    uint8_t color[3];
+    /* Starting point of cursor */
+    uint32_t initial_value;
+    /* Minimum allowed value */
+    uint32_t minimum_value;
+    /* Maximum */
+    uint32_t maximum_value;
+    /* Numerator of scaling value */
+    uint32_t scale_numerator;
+    /* Denominator of scaling value */
+    uint32_t scale_denominator;
+    /* Offset of value */
+    uint32_t scale_offset;
+    /* The style of line: Solid, dashed, dotted.. */
+    uint8_t line_style;          /* TODO*/
 };
 
 static inline void adp_add_cursor_to_graph_get_defaults(struct adp_msg_add_cursor_to_graph *const config)
 {
-	Assert(config);
-	config->stream_id = 0;
-	config->graph_id = 0;
-	config->axis_id = 0;
-	config->thickness = 1;
-	adp_set_color(config->color, ADP_COLOR_WHITE);
-	config->initial_value = 0;
-	config->minimum_value = 0;
-	config->maximum_value = 0;
-	config->scale_numerator = 0;
-	config->scale_denominator = 0;
-	config->scale_offset = 0;
-	config->line_style = 0;
+    Assert(config);
+    config->stream_id = 0;
+    config->graph_id = 0;
+    config->axis_id = 0;
+    config->thickness = 1;
+    adp_set_color(config->color, ADP_COLOR_WHITE);
+    config->initial_value = 0;
+    config->minimum_value = 0;
+    config->maximum_value = 0;
+    config->scale_numerator = 0;
+    config->scale_denominator = 0;
+    config->scale_offset = 0;
+    config->line_style = 0;
 }
 
 bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, const char* label);
@@ -502,67 +502,67 @@ bool adp_add_cursor_to_graph(struct adp_msg_add_cursor_to_graph *const config, c
 #define MSG_CONF_GPIO_TO_GRAPH       0x25
 #define MSG_CONF_GPIO_TO_GRAPH_LEN   15
 SHORTENUM struct adp_msg_conf_gpio_to_graph {
-	/* ID of graph */
-	uint16_t graph_id;
-	/* GPIO number to add to graph. Bit 0: GPIO0. bit 1: GPIO1 etc. */
-	uint8_t gpio_number;
-	/* Used to group graphs and cursors to the same scale */
-	uint8_t group_id;
-	/* Adjust the transparency */
-	uint8_t transparency;
-	/* Mode */
-	uint16_t mode;                                    // TODO
-	/* Thickness of line */
-	uint8_t line_thickness;
-	/* RGB color of line when GPIO pin is high */
-	uint8_t line_color_high_state[3];
-	/* RGB color of line when GPIO pin is low */
-	uint8_t line_color_low_state[3];
-	/* The style of line */
-	uint8_t line_style;
+    /* ID of graph */
+    uint16_t graph_id;
+    /* GPIO number to add to graph. Bit 0: GPIO0. bit 1: GPIO1 etc. */
+    uint8_t gpio_number;
+    /* Used to group graphs and cursors to the same scale */
+    uint8_t group_id;
+    /* Adjust the transparency */
+    uint8_t transparency;
+    /* Mode */
+    uint16_t mode;                                    /* TODO*/
+    /* Thickness of line */
+    uint8_t line_thickness;
+    /* RGB color of line when GPIO pin is high */
+    uint8_t line_color_high_state[3];
+    /* RGB color of line when GPIO pin is low */
+    uint8_t line_color_low_state[3];
+    /* The style of line */
+    uint8_t line_style;
 };
 
 static inline void adp_gpio_to_graph_get_defaults(struct adp_msg_conf_gpio_to_graph *const config)
 {
-	Assert(config);
-	config->graph_id = 0;
-	config->gpio_number = 0;
-	config->group_id = 0;
-	config->transparency = 0;
-	config->mode = 0;
-	config->line_thickness = 1;
-	adp_set_color(config->line_color_high_state, ADP_COLOR_WHITE);
-	adp_set_color(config->line_color_low_state, ADP_COLOR_WHITE);
-	config->line_style = 0;
+    Assert(config);
+    config->graph_id = 0;
+    config->gpio_number = 0;
+    config->group_id = 0;
+    config->transparency = 0;
+    config->mode = 0;
+    config->line_thickness = 1;
+    adp_set_color(config->line_color_high_state, ADP_COLOR_WHITE);
+    adp_set_color(config->line_color_low_state, ADP_COLOR_WHITE);
+    config->line_style = 0;
 }
 
 bool adp_add_gpio_to_graph(struct adp_msg_conf_gpio_to_graph *const config, \
-						const char* tag_high_state, const char* tag_low_state);
+                        const char* tag_high_state, const char* tag_low_state);
 
 /* MSG_CONF_TERMINAL */
 #define MSG_CONF_TERMINAL        0x26
 #define MSG_CONF_TERMINAL_LEN    10
 SHORTENUM struct adp_msg_conf_terminal {
-	/* ID of terminal */
-	uint16_t terminal_id;
-	/* Number of characters wide */
-	uint8_t width;
-	/* Number of characters high */
-	uint8_t height;
-	/* RGB background color */
-	uint8_t background_color[3];
-	/* RGB background color */
-	uint8_t foreground_color[3];
+    /* ID of terminal */
+    uint16_t terminal_id;
+    /* Number of characters wide */
+    uint8_t width;
+    /* Number of characters high */
+    uint8_t height;
+    /* RGB background color */
+    uint8_t background_color[3];
+    /* RGB background color */
+    uint8_t foreground_color[3];
 };
 
 static inline void adp_configure_terminal_get_defaults(struct adp_msg_conf_terminal *const config)
 {
-	Assert(config);
-	config->terminal_id = 0;
-	config->width = 80;
-	config->height = 25;
-	adp_set_color(config->background_color, ADP_COLOR_WHITE);
-	adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
+    Assert(config);
+    config->terminal_id = 0;
+    config->width = 80;
+    config->height = 25;
+    adp_set_color(config->background_color, ADP_COLOR_WHITE);
+    adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
 }
 
 bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const char* label);
@@ -571,31 +571,31 @@ bool adp_configure_terminal(struct adp_msg_conf_terminal *const config, const ch
 #define MSG_CONF_ADD_TO_TERMINAL       0x27
 #define MSG_CONF_ADD_TO_TERMINAL_LEN   11
 SHORTENUM struct adp_msg_add_stream_to_terminal {
-	/* ID of Terminal */
-	uint16_t terminal_id;
-	/* ID of stream */
-	uint16_t stream_id;
-	/* 0bx x x N T S F F
-	 * N = implicit newline in incoming text
-	 * T = enable tag
-	 * S = timestamped
-	 * F = format (Hex, decimal, binary, ascii)
-	 */
-	uint8_t mode;                                    // TODO
-	/* RGB color of the text stream received */
-	uint8_t text_color[3];
-	/* RGB color of the tag text */
-	uint8_t tag_text_color[3];
+    /* ID of Terminal */
+    uint16_t terminal_id;
+    /* ID of stream */
+    uint16_t stream_id;
+    /* 0bx x x N T S F F
+     * N = implicit newline in incoming text
+     * T = enable tag
+     * S = timestamped
+     * F = format (Hex, decimal, binary, ascii)
+     */
+    uint8_t mode;                                    /* TODO*/
+    /* RGB color of the text stream received */
+    uint8_t text_color[3];
+    /* RGB color of the tag text */
+    uint8_t tag_text_color[3];
 };
 
 static inline void adp_add_stream_to_terminal_get_defaults(struct adp_msg_add_stream_to_terminal *const config)
 {
-	Assert(config);
-	config->terminal_id = 0;
-	config->stream_id = 0;
-	config->mode = 0;
-	adp_set_color(config->text_color, ADP_COLOR_BLACK);
-	adp_set_color(config->tag_text_color, ADP_COLOR_BLACK);
+    Assert(config);
+    config->terminal_id = 0;
+    config->stream_id = 0;
+    config->mode = 0;
+    adp_set_color(config->text_color, ADP_COLOR_BLACK);
+    adp_set_color(config->tag_text_color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const config, const char* tag_text);
@@ -604,17 +604,17 @@ bool adp_add_stream_to_terminal(struct adp_msg_add_stream_to_terminal *const con
 #define MSG_CONF_DASHBOARD       0x2A
 #define MSG_CONF_DASHBOARD_LEN   7
 SHORTENUM struct adp_msg_conf_dashboard {
-	uint16_t dashboard_id;
-	uint8_t color[3];
-	uint16_t height;
+    uint16_t dashboard_id;
+    uint8_t color[3];
+    uint16_t height;
 };
 
 static inline void adp_conf_dashboard_get_defaults(struct adp_msg_conf_dashboard *const config)
 {
-	Assert(config);
-	config->dashboard_id = 0;
-	adp_set_color(config->color, ADP_COLOR_BLACK);
-	config->height = 100;
+    Assert(config);
+    config->dashboard_id = 0;
+    adp_set_color(config->color, ADP_COLOR_BLACK);
+    config->height = 100;
 }
 
 bool adp_add_dashboard(struct adp_msg_conf_dashboard *const config, const char* label);
@@ -623,104 +623,104 @@ bool adp_add_dashboard(struct adp_msg_conf_dashboard *const config, const char*
 #define MSG_CONF_DASHBOARD_ELEMENT 0x2B
 
 enum adp_dashboard_element_type {
-	ADP_ELEMENT_TYPE_LABEL,
-	ADP_ELEMENT_TYPE_BUTTON,
-	ADP_ELEMENT_TYPE_SLIDER,
-	ADP_ELEMENT_TYPE_PROGRESS,
-	ADP_ELEMENT_TYPE_SIGNAL,
-	ADP_ELEMENT_TYPE_SEGMENT,
-	ADP_ELEMENT_TYPE_GRAPH,
-	ADP_ELEMENT_TYPE_TEXT,
-	ADP_ELEMENT_TYPE_RADIO,
-	ADP_ELEMENT_TYPE_PIE,
+    ADP_ELEMENT_TYPE_LABEL,
+    ADP_ELEMENT_TYPE_BUTTON,
+    ADP_ELEMENT_TYPE_SLIDER,
+    ADP_ELEMENT_TYPE_PROGRESS,
+    ADP_ELEMENT_TYPE_SIGNAL,
+    ADP_ELEMENT_TYPE_SEGMENT,
+    ADP_ELEMENT_TYPE_GRAPH,
+    ADP_ELEMENT_TYPE_TEXT,
+    ADP_ELEMENT_TYPE_RADIO,
+    ADP_ELEMENT_TYPE_PIE,
 };
 
 #define MSG_CONF_DASHBOARD_COMMON_LEN    14
 #define ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS \
-	uint16_t  dashboard_id; \
-	uint16_t  element_id;   \
-	uint8_t   z_index;      \
-	uint16_t  x;            \
-	uint16_t  y;            \
-	uint16_t  width;        \
-	uint16_t  height;       \
-	enum adp_dashboard_element_type element_type 
+    uint16_t  dashboard_id; \
+    uint16_t  element_id;   \
+    uint8_t   z_index;      \
+    uint16_t  x;            \
+    uint16_t  y;            \
+    uint16_t  width;        \
+    uint16_t  height;       \
+    enum adp_dashboard_element_type element_type
 
 SHORTENUM struct adp_msg_conf_dashboard_element_common {
-	/* Dashboard ID */
-	uint16_t  dashboard_id;
-	/* Unique ID of element */
-	uint16_t  element_id;
-	/* Order index */
-	uint8_t   z_index;
-	/* X-coordinate of element location. 0 is leftmost position on dashboard */
-	uint16_t  x;
-	/* Y-coordinate of element location. 0 is topmost position on dashboard */
-	uint16_t  y;
-	/* Width of element */
-	uint16_t  width;
-	/* Height of element */
-	uint16_t  height;
-	/* See each element type below */
-	enum adp_dashboard_element_type element_type;
+    /* Dashboard ID */
+    uint16_t  dashboard_id;
+    /* Unique ID of element */
+    uint16_t  element_id;
+    /* Order index */
+    uint8_t   z_index;
+    /* X-coordinate of element location. 0 is leftmost position on dashboard */
+    uint16_t  x;
+    /* Y-coordinate of element location. 0 is topmost position on dashboard */
+    uint16_t  y;
+    /* Width of element */
+    uint16_t  width;
+    /* Height of element */
+    uint16_t  height;
+    /* See each element type below */
+    enum adp_dashboard_element_type element_type;
 };
 
 static inline void adp_conf_dashboard_element_get_defaults(struct adp_msg_conf_dashboard_element_common *const config)
 {
-	Assert(config);
-	config->dashboard_id = 0;
-	config->element_id = 0;
-	config->z_index = 0;
-	config->x = 0;
-	config->y = 0;
-	config->width = 0;
-	config->height = 0;
+    Assert(config);
+    config->dashboard_id = 0;
+    config->element_id = 0;
+    config->z_index = 0;
+    config->x = 0;
+    config->y = 0;
+    config->width = 0;
+    config->height = 0;
 }
 
 enum adp_label_attribute_alignment {
-	BOLD_OFF_ITALIC_OFF,
-	BOLD_ON_ITALIC_OFF,
-	BOLD_OFF_ITALIC_ON,
-	BOLD_ON_ITALIC_ON,
+    BOLD_OFF_ITALIC_OFF,
+    BOLD_ON_ITALIC_OFF,
+    BOLD_OFF_ITALIC_ON,
+    BOLD_ON_ITALIC_ON,
 };
 
 enum adp_label_horisontal_alignment {
-	HORISONTAL_ALIGNMENT_LEFT,
-	HORISONTAL_ALIGNMENT_CENTER,
-	HORISONTAL_ALIGNMENT_RIGHT,
+    HORISONTAL_ALIGNMENT_LEFT,
+    HORISONTAL_ALIGNMENT_CENTER,
+    HORISONTAL_ALIGNMENT_RIGHT,
 };
 
 enum adp_label_vertical_alignment {
-	VERTICAL_ALIGNMENT_TOP,
-	VERTICAL_ALIGNMENT_CENTER,
-	VERTICAL_ALIGNMENT_BOTTOM,
+    VERTICAL_ALIGNMENT_TOP,
+    VERTICAL_ALIGNMENT_CENTER,
+    VERTICAL_ALIGNMENT_BOTTOM,
 };
 
 #define ADP_ELEMENT_TYPE_LABEL_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
 SHORTENUM struct adp_msg_conf_dashboard_element_label {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t                             font_size;
-	uint8_t                             attribute;                               // TODO
-	enum adp_label_horisontal_alignment horisontal_alignment;
-	enum adp_label_vertical_alignment   vertical_alignment;
-	uint8_t                             background_transparency;
-	uint8_t                             background_color[3];
-	uint8_t                             foreground_transparency;
-	uint8_t                             foreground_color[3];
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t                             font_size;
+    uint8_t                             attribute;                               /* TODO*/
+    enum adp_label_horisontal_alignment horisontal_alignment;
+    enum adp_label_vertical_alignment   vertical_alignment;
+    uint8_t                             background_transparency;
+    uint8_t                             background_color[3];
+    uint8_t                             foreground_transparency;
+    uint8_t                             foreground_color[3];
 };
 
 static inline void adp_conf_dashboard_label_get_defaults(struct adp_msg_conf_dashboard_element_label *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_LABEL;
-	config->font_size = 10;
-	config->attribute = 0;
-	config->horisontal_alignment = HORISONTAL_ALIGNMENT_LEFT;
-	config->vertical_alignment = VERTICAL_ALIGNMENT_CENTER;
-	config->background_transparency = 0;
-	adp_set_color(config->background_color, ADP_COLOR_BLACK);
-	config->foreground_transparency = 0;
-	adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_LABEL;
+    config->font_size = 10;
+    config->attribute = 0;
+    config->horisontal_alignment = HORISONTAL_ALIGNMENT_LEFT;
+    config->vertical_alignment = VERTICAL_ALIGNMENT_CENTER;
+    config->background_transparency = 0;
+    adp_set_color(config->background_color, ADP_COLOR_BLACK);
+    config->foreground_transparency = 0;
+    adp_set_color(config->foreground_color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *const config, const char* label);
@@ -728,99 +728,99 @@ bool adp_add_label_to_dashboard(struct adp_msg_conf_dashboard_element_label *con
 #define ADP_ELEMENT_TYPE_BUTTON_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 1)
 
 SHORTENUM struct adp_msg_conf_dashboard_element_button {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t font_size;
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t font_size;
 };
 
 static inline void adp_conf_dashboard_button_get_defaults(struct adp_msg_conf_dashboard_element_button *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_BUTTON;
-	config->font_size = 10;
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_BUTTON;
+    config->font_size = 10;
 }
 
 bool adp_add_button_to_dashboard(struct adp_msg_conf_dashboard_element_button *const config, const char* label);
 
 #define ADP_ELEMENT_TYPE_SLIDER_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
 SHORTENUM struct adp_msg_conf_dashboard_element_slider {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint32_t minimum_value;
-	uint32_t maximum_value;
-	uint32_t initial_value;
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint32_t minimum_value;
+    uint32_t maximum_value;
+    uint32_t initial_value;
 };
 
 static inline void adp_conf_dashboard_slider_get_defaults(struct adp_msg_conf_dashboard_element_slider *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_SLIDER;
-	config->minimum_value = 0;
-	config->maximum_value = 100;
-	config->initial_value = 0;
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_SLIDER;
+    config->minimum_value = 0;
+    config->maximum_value = 100;
+    config->initial_value = 0;
 }
 
 bool adp_add_slider_to_dashboard(struct adp_msg_conf_dashboard_element_slider *const config);
 
 #define ADP_ELEMENT_TYPE_SIGNAL_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 8)
 SHORTENUM struct adp_msg_conf_dashboard_element_signal {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t on_transparency;
-	uint8_t on_color[3];
-	uint8_t off_transparency;
-	uint8_t off_color[3];
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t on_transparency;
+    uint8_t on_color[3];
+    uint8_t off_transparency;
+    uint8_t off_color[3];
 };
 
 static inline void adp_conf_dashboard_signal_get_defaults(struct adp_msg_conf_dashboard_element_signal *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_SIGNAL;
-	config->on_transparency = 0;
-	adp_set_color(config->on_color, ADP_COLOR_WHITE);
-	config->off_transparency = 0;
-	adp_set_color(config->off_color, ADP_COLOR_BLACK);
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_SIGNAL;
+    config->on_transparency = 0;
+    adp_set_color(config->on_color, ADP_COLOR_WHITE);
+    config->off_transparency = 0;
+    adp_set_color(config->off_color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_signal_to_dashboard(struct adp_msg_conf_dashboard_element_signal *const config);
 
 #define ADP_ELEMENT_TYPE_PROGRESS_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 15)
 SHORTENUM struct adp_msg_conf_dashboard_element_progress {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint32_t minimum_value;
-	uint32_t maximum_value;
-	uint32_t initial_value;
-	uint8_t color[3];
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint32_t minimum_value;
+    uint32_t maximum_value;
+    uint32_t initial_value;
+    uint8_t color[3];
 };
 
 static inline void adp_conf_dashboard_progress_get_defaults(struct adp_msg_conf_dashboard_element_progress *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_PROGRESS;
-	config->minimum_value = 0;
-	config->maximum_value = 100;
-	config->initial_value = 0;
-	adp_set_color(config->color, ADP_COLOR_BLACK);
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_PROGRESS;
+    config->minimum_value = 0;
+    config->maximum_value = 100;
+    config->initial_value = 0;
+    adp_set_color(config->color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_progress_to_dashboard(struct adp_msg_conf_dashboard_element_progress *const config);
 
 #define ADP_ELEMENT_TYPE_SEGMENT_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 6)
 SHORTENUM struct adp_msg_conf_dashboard_element_segment {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	/* Values: 1 ~ 20 */
-	uint8_t segment_count;
-	/* Values: 2 ~ 16*/
-	uint8_t base;
-	uint8_t transparency;
-	uint8_t color[3];
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    /* Values: 1 ~ 20 */
+    uint8_t segment_count;
+    /* Values: 2 ~ 16*/
+    uint8_t base;
+    uint8_t transparency;
+    uint8_t color[3];
 };
 
 static inline void adp_conf_dashboard_segment_get_defaults(struct adp_msg_conf_dashboard_element_segment *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_SEGMENT;
-	config->segment_count = 1;
-	config->base = 10;
-	config->transparency = 0;
-	adp_set_color(config->color, ADP_COLOR_BLACK);
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_SEGMENT;
+    config->segment_count = 1;
+    config->base = 10;
+    config->transparency = 0;
+    adp_set_color(config->color, ADP_COLOR_BLACK);
 }
 
 bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment *const config);
@@ -828,41 +828,41 @@ bool adp_add_segment_to_dashboard(struct adp_msg_conf_dashboard_element_segment
 /* MSG_CONF_ADD_GRAPH_TO_ELEMENT */
 #define  ADP_ELEMENT_TYPE_GRAPH_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 27)
 typedef union {
-	struct {
-		uint8_t mouse:1;
-		uint8_t fit_graph:1;
-		uint8_t :6;
-	} bit;
-	uint8_t reg;
+    struct {
+        uint8_t mouse:1;
+        uint8_t fit_graph:1;
+        uint8_t :6;
+    } bit;
+    uint8_t reg;
 } mode_type;
 
 SHORTENUM struct adp_msg_conf_dashboard_element_graph {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t title_color[3];
-	uint8_t background_color[3];
-	uint8_t graph_background_color[3];
-	uint8_t plot_count;
-	float x_min;
-	float x_max;
-	float y_min;
-	float y_max;
-	mode_type mode;
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t title_color[3];
+    uint8_t background_color[3];
+    uint8_t graph_background_color[3];
+    uint8_t plot_count;
+    float x_min;
+    float x_max;
+    float y_min;
+    float y_max;
+    mode_type mode;
 };
 
 static inline void adp_conf_dashboard_graph_get_defaults(struct adp_msg_conf_dashboard_element_graph *const config)
 {
-	adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
-	config->element_type = ADP_ELEMENT_TYPE_GRAPH;
-	adp_set_color(config->title_color, ADP_COLOR_WHITE);
-	adp_set_color(config->background_color, ADP_COLOR_BLACK);
-	adp_set_color(config->graph_background_color, ADP_COLOR_BLACK);
-	config->plot_count = 1;
-	config->x_min = 0;
-	config->x_max = 10;
-	config->y_min = 0;
-	config->y_max = 5;
-	config->mode.bit.fit_graph = 1;
-	config->mode.bit.mouse = 0;
+    adp_conf_dashboard_element_get_defaults((struct adp_msg_conf_dashboard_element_common*)config);
+    config->element_type = ADP_ELEMENT_TYPE_GRAPH;
+    adp_set_color(config->title_color, ADP_COLOR_WHITE);
+    adp_set_color(config->background_color, ADP_COLOR_BLACK);
+    adp_set_color(config->graph_background_color, ADP_COLOR_BLACK);
+    config->plot_count = 1;
+    config->x_min = 0;
+    config->x_max = 10;
+    config->y_min = 0;
+    config->y_max = 5;
+    config->mode.bit.fit_graph = 1;
+    config->mode.bit.mouse = 0;
 }
 
 bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *const config, const char* title);
@@ -871,10 +871,10 @@ bool adp_add_graph_to_dashboard(struct adp_msg_conf_dashboard_element_graph *con
 /* MSG_CONF_ADD_TEXT_TO_ELEMENT */
 #define  ADP_ELEMENT_TYPE_TEXT_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 12)
 SHORTENUM struct adp_msg_conf_dashboard_element_text {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t minimum[4];
-	uint8_t maximum[4];
-	uint8_t value[4];
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t minimum[4];
+    uint8_t maximum[4];
+    uint8_t value[4];
 };
 
 bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const config);
@@ -883,15 +883,15 @@ bool adp_add_text_to_dashboard(struct adp_msg_conf_dashboard_element_text *const
 #define  ADP_ELEMENT_TYPE_RADIO_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 3)
 
 enum adp_radio_orientation {
-	HORIZONTAL,
-	VERTICAL,
+    HORIZONTAL,
+    VERTICAL,
 };
 
 SHORTENUM struct adp_msg_conf_dashboard_element_radio {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t font_size;
-	uint8_t number_items;
-	enum adp_radio_orientation orientation;
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t font_size;
+    uint8_t number_items;
+    enum adp_radio_orientation orientation;
 };
 bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *const config, const char* text);
 
@@ -899,10 +899,10 @@ bool adp_add_radio_to_dashboard(struct adp_msg_conf_dashboard_element_radio *con
 #define  ADP_ELEMENT_TYPE_PIE_LEN (MSG_CONF_DASHBOARD_COMMON_LEN + 7)
 
 SHORTENUM struct adp_msg_conf_dashboard_element_pie {
-	ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
-	uint8_t background_color[3];
-	uint8_t title_color[3];
-	uint8_t number_slices;
+    ADP_DASHBOARD_ELEMENT_COMMON_MEMBERS;
+    uint8_t background_color[3];
+    uint8_t title_color[3];
+    uint8_t number_slices;
 };
 bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const config, const char* title);
 
@@ -911,9 +911,9 @@ bool adp_add_pie_to_dashboard(struct adp_msg_conf_dashboard_element_pie *const c
 #define MSG_CONF_ADD_STREAM_TO_ELEMENT_LEN   6
 
 SHORTENUM struct adp_conf_add_stream_to_element {
-	uint16_t dashboard_id;
-	uint16_t element_id;
-	uint16_t stream_id;
+    uint16_t dashboard_id;
+    uint16_t element_id;
+    uint16_t stream_id;
 };
 
 bool adp_add_stream_to_element(struct adp_conf_add_stream_to_element *const config);
@@ -921,14 +921,14 @@ bool adp_add_stream_to_element(struct adp_conf_add_stream_to_element *const conf
 /* MSG_DATA_STREAM */
 #define MSG_DATA_STREAM 0x40
 SHORTENUM struct adp_msg_data_stream_data {
-	uint16_t stream_id;
-	uint8_t data_size;
-	uint8_t *data;
+    uint16_t stream_id;
+    uint8_t data_size;
+    uint8_t *data;
 };
 
 SHORTENUM struct adp_msg_data_stream {
-	uint8_t number_of_streams;
-	struct adp_msg_data_stream_data stream[ADP_MAX_OUTGOING_STREAMS];
+    uint8_t number_of_streams;
+    struct adp_msg_data_stream_data stream[ADP_MAX_OUTGOING_STREAMS];
 };
 
 bool adp_send_stream(struct adp_msg_data_stream *const stream_data, uint8_t* receive_buf);
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c
index 1eaab719abb5..bba46139d557 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_spi.c
@@ -48,10 +48,10 @@
 #include <asf.h>
 #include "adp_interface.h"
 
-//! \name Embedded debugger SPI interface definitions
-//@{
+/*! \name Embedded debugger SPI interface definitions*/
+/*@{*/
 #define EDBG_SPI_MODULE           SPI
-//@}
+/*@}*/
 
 #define SPI_CHIP_SEL  SPI_NPCS3_PA5_GPIO
 
@@ -59,8 +59,8 @@
 #define SPI_BAUDRATE          1500000
 
 struct spi_device SPI_DEVICE = {
-	/** Board specific select id */
-	.id = SPI_DEVICE_ID
+    /** Board specific select id */
+    .id = SPI_DEVICE_ID
 };
 
 /**
@@ -69,7 +69,7 @@ struct spi_device SPI_DEVICE = {
 */
 static void adp_interface_send_start(void)
 {
-	spi_select_device(EDBG_SPI_MODULE, &SPI_DEVICE);
+    spi_select_device(EDBG_SPI_MODULE, &SPI_DEVICE);
 }
 
 /**
@@ -78,7 +78,7 @@ static void adp_interface_send_start(void)
 */
 static void adp_interface_send_stop(void)
 {
-	spi_deselect_device(EDBG_SPI_MODULE, &SPI_DEVICE);
+    spi_deselect_device(EDBG_SPI_MODULE, &SPI_DEVICE);
 }
 
 /**
@@ -90,7 +90,7 @@ static void adp_interface_send_stop(void)
 */
 static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_t length)
 {
-	spi_transceive_packet(EDBG_SPI_MODULE, tx_data, rx_data, length);
+    spi_transceive_packet(EDBG_SPI_MODULE, tx_data, rx_data, length);
 }
 
 /**
@@ -99,15 +99,15 @@ static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_
 */
 enum status_code adp_interface_init(void)
 {
-	sysclk_init();
+    sysclk_init();
 
-	/* Configure the SPI interface */
-	spi_master_init(EDBG_SPI_MODULE);
-	spi_master_setup_device(EDBG_SPI_MODULE, &SPI_DEVICE, SPI_MODE_0,
-			SPI_BAUDRATE, 0);
-	spi_enable(EDBG_SPI_MODULE);
+    /* Configure the SPI interface */
+    spi_master_init(EDBG_SPI_MODULE);
+    spi_master_setup_device(EDBG_SPI_MODULE, &SPI_DEVICE, SPI_MODE_0,
+            SPI_BAUDRATE, 0);
+    spi_enable(EDBG_SPI_MODULE);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -119,13 +119,13 @@ enum status_code adp_interface_init(void)
 */
 void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
 {
-	/* Send SPI start condition */
-	adp_interface_send_start();
+    /* Send SPI start condition */
+    adp_interface_send_start();
 
-	adp_interface_transceive(tx_buf, rx_buf, length);
-	
-	/* Send SPI end condition */
-	adp_interface_send_stop();
+    adp_interface_transceive(tx_buf, rx_buf, length);
+
+    /* Send SPI end condition */
+    adp_interface_send_stop();
 }
 
 /**
@@ -138,13 +138,13 @@ void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t
 */
 enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
 {
-	enum status_code status;
+    enum status_code status;
 
-	/* Send SPI start condition */
-	adp_interface_send_start();	
-	status = spi_read_packet(EDBG_SPI_MODULE, rx_buf, length);
-	/* Send SPI end condition */
-	adp_interface_send_stop();
+    /* Send SPI start condition */
+    adp_interface_send_start();
+    status = spi_read_packet(EDBG_SPI_MODULE, rx_buf, length);
+    /* Send SPI end condition */
+    adp_interface_send_stop();
 
-	return status;
+    return status;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c
index f29b01821519..192965008fd5 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam/adp_interface_twi.c
@@ -45,10 +45,10 @@
 #include <asf.h>
 #include "adp_interface.h"
 
-//! \name Embedded debugger TWI interface definitions
-//@{
+/*! \name Embedded debugger TWI interface definitions*/
+/*@{*/
 #define EDBG_TWI_MODULE           TWI0
-//@}
+/*@}*/
 
 #define TWI_EDBG_SLAVE_ADDR 0x28
 #define TIMEOUT 1000
@@ -59,14 +59,14 @@
 */
 enum status_code adp_interface_init(void)
 {
-	sysclk_init();
+    sysclk_init();
 
-	/* Configure the TWI interface */
-	twi_master_options_t opt = {
-		.speed = 100000,
-		.chip  = TWI_EDBG_SLAVE_ADDR
-	};
-	return twi_master_setup(EDBG_TWI_MODULE, &opt);
+    /* Configure the TWI interface */
+    twi_master_options_t opt = {
+        .speed = 100000,
+        .chip  = TWI_EDBG_SLAVE_ADDR
+    };
+    return twi_master_setup(EDBG_TWI_MODULE, &opt);
 }
 
 /**
@@ -77,12 +77,12 @@ enum status_code adp_interface_init(void)
 */
 static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
 {
-	twi_package_t packet_write = {
-		.chip         = TWI_EDBG_SLAVE_ADDR, /* TWI slave bus address */
-		.buffer       = tx_buf,        /* transfer data source buffer */
-		.length       = length               /* transfer data size (bytes) */
-	};
-	return twi_master_write(EDBG_TWI_MODULE, &packet_write);
+    twi_package_t packet_write = {
+        .chip         = TWI_EDBG_SLAVE_ADDR, /* TWI slave bus address */
+        .buffer       = tx_buf,        /* transfer data source buffer */
+        .length       = length               /* transfer data size (bytes) */
+    };
+    return twi_master_write(EDBG_TWI_MODULE, &packet_write);
 }
 
 /**
@@ -91,25 +91,26 @@ static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
 * \param[out] data   Pointer to place received data
 * \param[in]  length Number of bytes to receive
 */
-enum status_code adp_interface_read_response(uint8_t *data,	uint16_t length)
+enum status_code adp_interface_read_response(uint8_t *data, uint16_t length)
 {
-	enum status_code status = ERR_IO_ERROR;
-	uint8_t data_len = 0;
-	
-	twi_package_t packet_read = {
-		.chip         = TWI_EDBG_SLAVE_ADDR, // TWI slave bus address
-		.buffer       = &data_len,                // transfer data destination buffer
-		.length       = 1               // transfer data size (bytes)
-	};
-	twi_master_read(EDBG_TWI_MODULE, &packet_read);
-	
-	if(data_len != 0){
-		packet_read.length = data_len;
-		packet_read.buffer = data;
-		status = twi_master_read(EDBG_TWI_MODULE, &packet_read);	
-	}
+    enum status_code status = ERR_IO_ERROR;
+    uint8_t data_len = 0;
 
-	return status;
+    twi_package_t packet_read = {
+        .chip         = TWI_EDBG_SLAVE_ADDR, /* TWI slave bus address*/
+        .buffer       = &data_len,                /* transfer data destination buffer*/
+        .length       = 1               /* transfer data size (bytes)*/
+    };
+    twi_master_read(EDBG_TWI_MODULE, &packet_read);
+
+    if(data_len != 0)
+    {
+        packet_read.length = data_len;
+        packet_read.buffer = data;
+        status = twi_master_read(EDBG_TWI_MODULE, &packet_read);
+    }
+
+    return status;
 }
 
 /**
@@ -121,7 +122,7 @@ enum status_code adp_interface_read_response(uint8_t *data,	uint16_t length)
 */
 void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
 {
-	adp_interface_send(tx_buf, length);
-	adp_interface_read_response(rx_buf, length);
+    adp_interface_send(tx_buf, length);
+    adp_interface_read_response(rx_buf, length);
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c
index f23ab1074203..fedb595990a3 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_spi.c
@@ -59,7 +59,7 @@ struct spi_slave_inst slave;
 */
 static void adp_interface_send_start(void)
 {
-	spi_select_slave(&edbg_spi, &slave, true);
+    spi_select_slave(&edbg_spi, &slave, true);
 }
 
 /**
@@ -68,7 +68,7 @@ static void adp_interface_send_start(void)
 */
 static void adp_interface_send_stop(void)
 {
-	spi_select_slave(&edbg_spi, &slave, false);
+    spi_select_slave(&edbg_spi, &slave, false);
 }
 
 /**
@@ -80,7 +80,7 @@ static void adp_interface_send_stop(void)
 */
 static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_t length)
 {
-	spi_transceive_buffer_wait(&edbg_spi, tx_data, rx_data, length);
+    spi_transceive_buffer_wait(&edbg_spi, tx_data, rx_data, length);
 }
 
 /**
@@ -89,31 +89,31 @@ static void adp_interface_transceive(uint8_t *tx_data, uint8_t *rx_data, uint16_
 */
 enum status_code adp_interface_init(void)
 {
-	enum status_code return_value;
+    enum status_code return_value;
 
-	system_init();
+    system_init();
 
-	struct spi_slave_inst_config slave_dev_config;
+    struct spi_slave_inst_config slave_dev_config;
 
-	struct spi_config config;
+    struct spi_config config;
 
-	spi_slave_inst_get_config_defaults(&slave_dev_config);
-	slave_dev_config.ss_pin = (EDBG_SPI_SERCOM_PINMUX_PAD1 >> 16) & 0xFF;
-	spi_attach_slave(&slave, &slave_dev_config);
+    spi_slave_inst_get_config_defaults(&slave_dev_config);
+    slave_dev_config.ss_pin = (EDBG_SPI_SERCOM_PINMUX_PAD1 >> 16) & 0xFF;
+    spi_attach_slave(&slave, &slave_dev_config);
 
-	spi_get_config_defaults(&config);
-	config.mode_specific.master.baudrate = 1000000;
-	config.mux_setting = EDBG_SPI_SERCOM_MUX_SETTING;
-	config.pinmux_pad0 = EDBG_SPI_SERCOM_PINMUX_PAD0;
-	config.pinmux_pad1 = PINMUX_UNUSED;
-	config.pinmux_pad2 = EDBG_SPI_SERCOM_PINMUX_PAD2;
-	config.pinmux_pad3 = EDBG_SPI_SERCOM_PINMUX_PAD3;
+    spi_get_config_defaults(&config);
+    config.mode_specific.master.baudrate = 1000000;
+    config.mux_setting = EDBG_SPI_SERCOM_MUX_SETTING;
+    config.pinmux_pad0 = EDBG_SPI_SERCOM_PINMUX_PAD0;
+    config.pinmux_pad1 = PINMUX_UNUSED;
+    config.pinmux_pad2 = EDBG_SPI_SERCOM_PINMUX_PAD2;
+    config.pinmux_pad3 = EDBG_SPI_SERCOM_PINMUX_PAD3;
 
-	return_value = spi_init(&edbg_spi, EDBG_SPI_MODULE, &config);
+    return_value = spi_init(&edbg_spi, EDBG_SPI_MODULE, &config);
 
-	spi_enable(&edbg_spi);
+    spi_enable(&edbg_spi);
 
-	return return_value;
+    return return_value;
 }
 
 /**
@@ -125,13 +125,13 @@ enum status_code adp_interface_init(void)
 */
 void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
 {
-	/* Send SPI start condition */
-	adp_interface_send_start();
+    /* Send SPI start condition */
+    adp_interface_send_start();
 
-	adp_interface_transceive(tx_buf, rx_buf, length);
-	
-	/* Send SPI end condition */
-	adp_interface_send_stop();
+    adp_interface_transceive(tx_buf, rx_buf, length);
+
+    /* Send SPI end condition */
+    adp_interface_send_stop();
 }
 
 /**
@@ -144,13 +144,13 @@ void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t
 */
 enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
 {
-	bool status;
+    bool status;
 
-	/* Send SPI start condition */
-	adp_interface_send_start();	
-	status = spi_read_buffer_wait(&edbg_spi, rx_buf, length, 0xFF);
-	/* Send SPI end condition */
-	adp_interface_send_stop();
+    /* Send SPI start condition */
+    adp_interface_send_start();
+    status = spi_read_buffer_wait(&edbg_spi, rx_buf, length, 0xFF);
+    /* Send SPI end condition */
+    adp_interface_send_stop();
 
-	return status;
-}
\ No newline at end of file
+    return status;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c
index 18d5202cdf90..a01f1808fd56 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/adp/sam0/adp_interface_twi.c
@@ -62,31 +62,31 @@ struct i2c_master_module i2c_master_instance;
 */
 enum status_code adp_interface_init(void)
 {
-	enum status_code return_value;
+    enum status_code return_value;
 
-	system_init();
+    system_init();
 
-	struct i2c_master_config config_i2c_master;
-	i2c_master_get_config_defaults(&config_i2c_master);
-	config_i2c_master.buffer_timeout = 10000;
-	return_value = i2c_master_init(&i2c_master_instance, EDBG_TWI, &config_i2c_master);
-	i2c_master_enable(&i2c_master_instance);
-	return return_value;
+    struct i2c_master_config config_i2c_master;
+    i2c_master_get_config_defaults(&config_i2c_master);
+    config_i2c_master.buffer_timeout = 10000;
+    return_value = i2c_master_init(&i2c_master_instance, EDBG_TWI, &config_i2c_master);
+    i2c_master_enable(&i2c_master_instance);
+    return return_value;
 }
 
 static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
 {
-	enum status_code status;
-	
-	struct i2c_master_packet packet = {
-		.address = TWI_EDBG_SLAVE_ADDR,
-		.data_length = length,
-		.data = tx_buf,
-	};
-	/* Send data to PC */
-	status = i2c_master_write_packet_wait(&i2c_master_instance, &packet);
-	
-	return status;
+    enum status_code status;
+
+    struct i2c_master_packet packet = {
+        .address = TWI_EDBG_SLAVE_ADDR,
+        .data_length = length,
+        .data = tx_buf,
+    };
+    /* Send data to PC */
+    status = i2c_master_write_packet_wait(&i2c_master_instance, &packet);
+
+    return status;
 }
 
 /**
@@ -99,24 +99,24 @@ static enum status_code adp_interface_send(uint8_t* tx_buf, uint16_t length)
 */
 enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
 {
-	enum status_code status = STATUS_ERR_IO;
-	uint8_t data_len = 0;
+    enum status_code status = STATUS_ERR_IO;
+    uint8_t data_len = 0;
+
+    struct i2c_master_packet packet = {
+        .address = TWI_EDBG_SLAVE_ADDR,
+        .data_length = 1,
+        .data = &data_len,
+    };
+    i2c_master_read_packet_wait(&i2c_master_instance, &packet);
 
-	struct i2c_master_packet packet = {
-		.address = TWI_EDBG_SLAVE_ADDR,
-		.data_length = 1,
-		.data = &data_len,
-	};
-	i2c_master_read_packet_wait(&i2c_master_instance, &packet);
-	
-	if (data_len != 0)
-	{
-		packet.data_length = data_len;
-		packet.data = rx_buf;
-		status = i2c_master_read_packet_wait(&i2c_master_instance, &packet);
-	}
-	
-	return status;
+    if (data_len != 0)
+    {
+        packet.data_length = data_len;
+        packet.data = rx_buf;
+        status = i2c_master_read_packet_wait(&i2c_master_instance, &packet);
+    }
+
+    return status;
 }
 
 /**
@@ -127,7 +127,7 @@ enum status_code adp_interface_read_response(uint8_t* rx_buf, uint16_t length)
 * \param[out] rx_buf  Pointer to store the received I2C character
 */
 void adp_interface_transceive_procotol(uint8_t* tx_buf, uint16_t length, uint8_t* rx_buf)
-{	
-	adp_interface_send(tx_buf, length);
-	adp_interface_read_response(rx_buf, length);
+{
+    adp_interface_send(tx_buf, length);
+    adp_interface_read_response(rx_buf, length);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c
index 9d06e0d86ea1..c952fa8d4ebe 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.c
@@ -47,22 +47,22 @@
 #include "calendar.h"
 #include <stdio.h>
 
-//! Unix epoch year
+/*! Unix epoch year*/
 #define EPOCH_YEAR 1970
 
-//! Number of seconds in a day
+/*! Number of seconds in a day*/
 #define SECS_PER_DAY 86400UL
 
-//! Number of seconds in an hour
+/*! Number of seconds in an hour*/
 #define SECS_PER_HOUR 3600UL
 
-//! Number of seconds in a minute
+/*! Number of seconds in a minute*/
 #define SECS_PER_MINUTE 60UL
 
-//! Number of days in a specified month. Index 1 for leap year, else 0.
+/*! Number of days in a specified month. Index 1 for leap year, else 0.*/
 const uint8_t month[2][12] = {
-	{ 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },
-	{ 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }
+    { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 },
+    { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }
 };
 
 /**
@@ -78,11 +78,12 @@ const uint8_t month[2][12] = {
  */
 static bool calendar_leapyear(uint16_t year)
 {
-	if(!((year) % 4) && (((year) % 100) || !((year) % 400))) {
-		return true;
-	} else {
-		return false;
-	}
+    if(!((year) % 4) && (((year) % 100) || !((year) % 400)))
+    {
+        return true;
+    } else {
+        return false;
+    }
 }
 
 /**
@@ -99,11 +100,12 @@ static bool calendar_leapyear(uint16_t year)
  */
 static uint16_t calendar_yearsize(uint16_t year)
 {
-	if (calendar_leapyear(year)) {
-		return 366;
-	} else {
-		return 365;
-	}
+    if (calendar_leapyear(year))
+    {
+        return 366;
+    } else {
+        return 365;
+    }
 }
 
 /**
@@ -117,9 +119,10 @@ static uint16_t calendar_yearsize(uint16_t year)
  */
 static void calendar_add_year_to_date(struct calendar_date *date)
 {
-	if (date->year < 2105) {
-		date->year++;
-	}
+    if (date->year < 2105)
+    {
+        date->year++;
+    }
 }
 
 /**
@@ -133,13 +136,14 @@ static void calendar_add_year_to_date(struct calendar_date *date)
  */
 static void calendar_add_month_to_date(struct calendar_date *date)
 {
-	uint8_t months = date->month;
-	months++;
-	if (months == 12){
-		months = 0;
-		calendar_add_year_to_date(date);
-	}
-	date->month = months;
+    uint8_t months = date->month;
+    months++;
+    if (months == 12)
+    {
+        months = 0;
+        calendar_add_year_to_date(date);
+    }
+    date->month = months;
 }
 
 /**
@@ -154,20 +158,22 @@ static void calendar_add_month_to_date(struct calendar_date *date)
  */
 static void calendar_add_day_to_date(struct calendar_date *date)
 {
-	uint8_t dates = date->date;
-	uint8_t months = date->month;
-	uint8_t year = date->year;
-
-	dates++;
-	if (dates == month[calendar_leapyear(year)][months]) {
-		dates = 0;
-		calendar_add_month_to_date(date);
-	}
-	date->dayofweek++;
-	if (date->dayofweek == 7) {
-		date->dayofweek = 0;
-	}
-	date->date = dates;
+    uint8_t dates = date->date;
+    uint8_t months = date->month;
+    uint8_t year = date->year;
+
+    dates++;
+    if (dates == month[calendar_leapyear(year)][months])
+    {
+        dates = 0;
+        calendar_add_month_to_date(date);
+    }
+    date->dayofweek++;
+    if (date->dayofweek == 7)
+    {
+        date->dayofweek = 0;
+    }
+    date->date = dates;
 }
 
 /**
@@ -181,13 +187,14 @@ static void calendar_add_day_to_date(struct calendar_date *date)
  */
 static void calendar_add_hour_to_date(struct calendar_date *date)
 {
-	int8_t hour = date->hour;
-	hour++;
-	if (hour == 24){
-		hour = 0;
-		calendar_add_day_to_date(date);
-	}
-	date->hour = hour;
+    int8_t hour = date->hour;
+    hour++;
+    if (hour == 24)
+    {
+        hour = 0;
+        calendar_add_day_to_date(date);
+    }
+    date->hour = hour;
 }
 
 /**
@@ -201,13 +208,14 @@ static void calendar_add_hour_to_date(struct calendar_date *date)
  */
 static void calendar_add_minute_to_date(struct calendar_date *date)
 {
-	uint8_t minute = date->minute;
-	minute++;
-	if (minute == 60){
-		minute = 0;
-		calendar_add_hour_to_date(date);
-	}
-	date->minute = minute;
+    uint8_t minute = date->minute;
+    minute++;
+    if (minute == 60)
+    {
+        minute = 0;
+        calendar_add_hour_to_date(date);
+    }
+    date->minute = minute;
 }
 
 /**
@@ -223,27 +231,31 @@ static void calendar_add_minute_to_date(struct calendar_date *date)
  */
 bool calendar_is_date_valid(struct calendar_date *date)
 {
-	// Make sure time is valid
-	if ((date->second >= 60) || (date->minute >= 60) || (date->hour >= 24)) {
-		return false;
-	}
-
-	// Make sure month and date is valid
-	if ((date->month >= 12) || (date->date >=31)) {
-		return false;
-	}
-
-	// Make sure days in month are not more than it should be
-	if (date->date >= month[calendar_leapyear(date->year)][date->month]) {
-		return false;
-	}
-
-	// Make sure year is not earlier than 1970 and before 2106
-	if ((date->year < EPOCH_YEAR) || (date->year >= 2106)) {
-		return false;
-	} else {
-		return true;
-	}
+    /* Make sure time is valid*/
+    if ((date->second >= 60) || (date->minute >= 60) || (date->hour >= 24))
+    {
+        return false;
+    }
+
+    /* Make sure month and date is valid*/
+    if ((date->month >= 12) || (date->date >=31))
+    {
+        return false;
+    }
+
+    /* Make sure days in month are not more than it should be*/
+    if (date->date >= month[calendar_leapyear(date->year)][date->month])
+    {
+        return false;
+    }
+
+    /* Make sure year is not earlier than 1970 and before 2106*/
+    if ((date->year < EPOCH_YEAR) || (date->year >= 2106))
+    {
+        return false;
+    } else {
+        return true;
+    }
 }
 
 /**
@@ -256,33 +268,35 @@ bool calendar_is_date_valid(struct calendar_date *date)
  *
  */
 void calendar_timestamp_to_date(uint32_t timestamp,
-		struct calendar_date *date_out)
+        struct calendar_date *date_out)
 {
-	uint32_t day_number;
-	uint32_t day_clock;
-
-	date_out->year = EPOCH_YEAR;
-	date_out->month = 0;
-
-	day_clock = timestamp % SECS_PER_DAY;
-	day_number = timestamp / SECS_PER_DAY;
-
-	date_out->second = day_clock % SECS_PER_MINUTE;
-	date_out->minute = (day_clock % SECS_PER_HOUR) / SECS_PER_MINUTE;
-	date_out->hour = day_clock / SECS_PER_HOUR;
-	date_out->dayofweek = (day_number + 4) % 7;
-
-	while (day_number >= calendar_yearsize(date_out->year)) {
-		day_number -= calendar_yearsize(date_out->year);
-		date_out->year++;
-	}
-
-	while (day_number >=
-			month[calendar_leapyear(date_out->year)][date_out->month]) {
-		day_number -= month[calendar_leapyear(date_out->year)][date_out->month];
-		date_out->month++;
-	}
-	date_out->date = day_number;
+    uint32_t day_number;
+    uint32_t day_clock;
+
+    date_out->year = EPOCH_YEAR;
+    date_out->month = 0;
+
+    day_clock = timestamp % SECS_PER_DAY;
+    day_number = timestamp / SECS_PER_DAY;
+
+    date_out->second = day_clock % SECS_PER_MINUTE;
+    date_out->minute = (day_clock % SECS_PER_HOUR) / SECS_PER_MINUTE;
+    date_out->hour = day_clock / SECS_PER_HOUR;
+    date_out->dayofweek = (day_number + 4) % 7;
+
+    while (day_number >= calendar_yearsize(date_out->year))
+    {
+        day_number -= calendar_yearsize(date_out->year);
+        date_out->year++;
+    }
+
+    while (day_number >=
+            month[calendar_leapyear(date_out->year)][date_out->month])
+            {
+        day_number -= month[calendar_leapyear(date_out->year)][date_out->month];
+        date_out->month++;
+    }
+    date_out->date = day_number;
 }
 
 /**
@@ -298,16 +312,17 @@ void calendar_timestamp_to_date(uint32_t timestamp,
  *
  */
 void calendar_timestamp_to_date_tz(uint32_t timestamp, int8_t hour,
-		uint8_t min, struct calendar_date *date_out)
+        uint8_t min, struct calendar_date *date_out)
 {
-	// Multiply timezone offset by seconds, and add to timestamp
-	if (hour >= 0) {
-		calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) +
-				(SECS_PER_MINUTE * min)), date_out);
-	} else {
-		calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) -
-				(SECS_PER_MINUTE * min)), date_out);
-	}
+    /* Multiply timezone offset by seconds, and add to timestamp*/
+    if (hour >= 0)
+    {
+        calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) +
+                (SECS_PER_MINUTE * min)), date_out);
+    } else {
+        calendar_timestamp_to_date((timestamp + (SECS_PER_HOUR * hour) -
+                (SECS_PER_MINUTE * min)), date_out);
+    }
 }
 
 /**
@@ -324,34 +339,36 @@ void calendar_timestamp_to_date_tz(uint32_t timestamp, int8_t hour,
 uint32_t calendar_date_to_timestamp(struct calendar_date *date)
 {
 
-	// Make sure date is valid
-	if (!calendar_is_date_valid(date))
-		return 0;
-
-	uint32_t timestamp = 0;
-	uint8_t date_month;
-	uint16_t date_year;
-
-	date_month = date->month;
-	date_year = date->year;
-
-	// Add number of seconds elapsed in current month
-	timestamp += (date->date * SECS_PER_DAY) + (date->hour * SECS_PER_HOUR) +
-			(date->minute * SECS_PER_MINUTE) + date->second;
-
-	while (date_month != 0) {
-		date_month--;
-		// Add number of seconds in months of current year
-		timestamp += month[calendar_leapyear(date_year)][date_month]
-				* SECS_PER_DAY;
-	}
-	while (date_year > EPOCH_YEAR) {
-		date_year--;
-		// Add number of seconds in all years since epoch year
-		timestamp += calendar_yearsize(date_year) * SECS_PER_DAY;
-	}
-
-	return timestamp;
+    /* Make sure date is valid*/
+    if (!calendar_is_date_valid(date))
+        return 0;
+
+    uint32_t timestamp = 0;
+    uint8_t date_month;
+    uint16_t date_year;
+
+    date_month = date->month;
+    date_year = date->year;
+
+    /* Add number of seconds elapsed in current month*/
+    timestamp += (date->date * SECS_PER_DAY) + (date->hour * SECS_PER_HOUR) +
+            (date->minute * SECS_PER_MINUTE) + date->second;
+
+    while (date_month != 0)
+    {
+        date_month--;
+        /* Add number of seconds in months of current year*/
+        timestamp += month[calendar_leapyear(date_year)][date_month]
+                * SECS_PER_DAY;
+    }
+    while (date_year > EPOCH_YEAR)
+    {
+        date_year--;
+        /* Add number of seconds in all years since epoch year*/
+        timestamp += calendar_yearsize(date_year) * SECS_PER_DAY;
+    }
+
+    return timestamp;
 }
 
 /**
@@ -368,21 +385,23 @@ uint32_t calendar_date_to_timestamp(struct calendar_date *date)
  * \retval 0 if date is not valid
  */
 uint32_t calendar_date_to_timestamp_tz(struct calendar_date *date, int8_t hour,
-		uint8_t min)
+        uint8_t min)
 {
-	uint32_t timestamp = calendar_date_to_timestamp(date);
-	if (timestamp == 0) {
-		return 0;
-	} else {
-		// Subtract the seconds of offset in time zone offset from timestamp
-		if (hour >= 0) {
-			return (timestamp - (SECS_PER_HOUR * hour + SECS_PER_MINUTE *
-					min));
-		} else {
-			return (timestamp - (SECS_PER_HOUR * hour - SECS_PER_MINUTE *
-					min));
-		}
-	}
+    uint32_t timestamp = calendar_date_to_timestamp(date);
+    if (timestamp == 0)
+    {
+        return 0;
+    } else {
+        /* Subtract the seconds of offset in time zone offset from timestamp*/
+        if (hour >= 0)
+        {
+            return (timestamp - (SECS_PER_HOUR * hour + SECS_PER_MINUTE *
+                    min));
+        } else {
+            return (timestamp - (SECS_PER_HOUR * hour - SECS_PER_MINUTE *
+                    min));
+        }
+    }
 }
 
 /**
@@ -398,76 +417,87 @@ uint32_t calendar_date_to_timestamp_tz(struct calendar_date *date, int8_t hour,
  *
  */
 void calendar_time_between_dates(struct calendar_date *date_end,
-		struct calendar_date *date_start, struct calendar_date *date_out)
+        struct calendar_date *date_start, struct calendar_date *date_out)
 {
-	uint32_t timestamp_start;
-	uint32_t timestamp_end;
-	struct calendar_date *temp;
-
-	timestamp_start = calendar_date_to_timestamp(date_start);
-	timestamp_end = calendar_date_to_timestamp(date_end);
-
-	// Switch dates if date_end is before date_start
-	if (timestamp_end < timestamp_start) {
-		temp = date_end;
-		date_end = date_start;
-		date_start = temp;
-	}
-
-	// Calculate number of years
-	date_out->year = date_end->year - date_start->year;
-
-	// Check if months wrap around new year
-	if (date_end->month - date_start->month < 0 ) {
-		date_end->month += 12;
-		if (date_out->year != 0) {
-			date_out->year--;
-		}
-	}
-	// Calculate number of months
-	date_out->month = date_end->month - date_start->month;
-
-	// Check if dates wrap around month
-	if(date_end->date - date_start->date < 0) {
-		// Add number of days in last month to get number of days correct
-		date_end->date +=
-			month[calendar_leapyear(date_end->year)][date_end->month-1];
-		if (date_out->month != 0) {
-			date_out->month--;
-		}
-	}
-	// Calculate number of days
-	date_out->date = date_end->date - date_start->date;
-
-	// Check if hours wrap around midnight
-	if (date_end->hour - date_start->hour < 0) {
-		date_end->hour += 24;
-		if (date_out->date != 0) {
-			date_out->date--;
-		}
-	}
-	// Calculate number of hours
-	date_out->hour = date_end->hour - date_start->hour;
-
-	// Check if minutes wrap around hour
-	if (date_end->minute - date_start->minute < 0) {
-		date_end->minute += 60;
-		if (date_out->hour != 0) {
-			date_out->hour--;
-		}
-	}
-	// Calculate number of minutes
-	date_out->minute = date_end->minute - date_start->minute;
-
-	// Check if seconds wrap around minute
-	if (date_end->second - date_start->second < 0) {
-		date_end->second += 60;
-		if (date_out->minute != 0) {
-			date_out->minute--;
-		}
-	}
-	// Calculate number of seconds
-	date_out->second = date_end->second - date_start->second;
+    uint32_t timestamp_start;
+    uint32_t timestamp_end;
+    struct calendar_date *temp;
+
+    timestamp_start = calendar_date_to_timestamp(date_start);
+    timestamp_end = calendar_date_to_timestamp(date_end);
+
+    /* Switch dates if date_end is before date_start*/
+    if (timestamp_end < timestamp_start)
+    {
+        temp = date_end;
+        date_end = date_start;
+        date_start = temp;
+    }
+
+    /* Calculate number of years*/
+    date_out->year = date_end->year - date_start->year;
+
+    /* Check if months wrap around new year*/
+    if (date_end->month - date_start->month < 0 )
+    {
+        date_end->month += 12;
+        if (date_out->year != 0)
+        {
+            date_out->year--;
+        }
+    }
+    /* Calculate number of months*/
+    date_out->month = date_end->month - date_start->month;
+
+    /* Check if dates wrap around month*/
+    if(date_end->date - date_start->date < 0)
+    {
+        /* Add number of days in last month to get number of days correct*/
+        date_end->date +=
+            month[calendar_leapyear(date_end->year)][date_end->month-1];
+        if (date_out->month != 0)
+        {
+            date_out->month--;
+        }
+    }
+    /* Calculate number of days*/
+    date_out->date = date_end->date - date_start->date;
+
+    /* Check if hours wrap around midnight*/
+    if (date_end->hour - date_start->hour < 0)
+    {
+        date_end->hour += 24;
+        if (date_out->date != 0)
+        {
+            date_out->date--;
+        }
+    }
+    /* Calculate number of hours*/
+    date_out->hour = date_end->hour - date_start->hour;
+
+    /* Check if minutes wrap around hour*/
+    if (date_end->minute - date_start->minute < 0)
+    {
+        date_end->minute += 60;
+        if (date_out->hour != 0)
+        {
+            date_out->hour--;
+        }
+    }
+    /* Calculate number of minutes*/
+    date_out->minute = date_end->minute - date_start->minute;
+
+    /* Check if seconds wrap around minute*/
+    if (date_end->second - date_start->second < 0)
+    {
+        date_end->second += 60;
+        if (date_out->minute != 0)
+        {
+            date_out->minute--;
+        }
+    }
+    /* Calculate number of seconds*/
+    date_out->second = date_end->second - date_start->second;
 
 }
 
@@ -482,11 +512,12 @@ void calendar_time_between_dates(struct calendar_date *date_end,
  */
 void calendar_add_second_to_date(struct calendar_date *date)
 {
-	// Check if input date is valid
-	Assert(calendar_is_date_valid(date));
-
-	if (++date->second == 60) {
-		date->second = 0;
-		calendar_add_minute_to_date(date);
-	}
+    /* Check if input date is valid*/
+    Assert(calendar_is_date_valid(date));
+
+    if (++date->second == 60)
+    {
+        date->second = 0;
+        calendar_add_minute_to_date(date);
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h
index d825434fd98e..8656cd7b87d8 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/calendar/calendar.h
@@ -69,32 +69,32 @@ extern "C" {
  * @{
  */
 
-//! Calendar structure to hold a date
+/*! Calendar structure to hold a date*/
 struct calendar_date {
-	uint8_t second;        //!< 0-59
-	uint8_t minute;        //!< 0-59
-	uint8_t hour;          //!< 0-23
-	uint8_t date;          //!< 0-30 \note First day of month is 0, not 1.
-	uint8_t month;         //!< 0 January - 11 December
-	uint16_t year;         //!< 1970-2105
-	uint8_t dayofweek;     //!< 0 Sunday  - 6 Saturday
+    uint8_t second;        /*!< 0-59*/
+    uint8_t minute;        /*!< 0-59*/
+    uint8_t hour;          /*!< 0-23*/
+    uint8_t date;          /*!< 0-30 \note First day of month is 0, not 1.*/
+    uint8_t month;         /*!< 0 January - 11 December*/
+    uint16_t year;         /*!< 1970-2105*/
+    uint8_t dayofweek;     /*!< 0 Sunday  - 6 Saturday*/
 };
 
 bool calendar_is_date_valid(struct calendar_date *date);
 
 void calendar_timestamp_to_date(uint32_t timestamp, struct calendar_date
-		*date_out);
+        *date_out);
 
 void calendar_timestamp_to_date_tz(uint32_t timestamp, int8_t hour,
-		uint8_t min, struct calendar_date *date_out);
+        uint8_t min, struct calendar_date *date_out);
 
 uint32_t calendar_date_to_timestamp(struct calendar_date *date);
 
 uint32_t calendar_date_to_timestamp_tz(struct calendar_date *date, int8_t hour,
-		uint8_t min);
+        uint8_t min);
 
 void calendar_time_between_dates(struct calendar_date *date_end,
-		struct calendar_date *date_start, struct calendar_date *date_out);
+        struct calendar_date *date_start, struct calendar_date *date_out);
 
 void calendar_add_second_to_date(struct calendar_date *date);
 
@@ -132,14 +132,14 @@ void calendar_add_second_to_date(struct calendar_date *date);
  * be added to the project:
  * -# A date struct with a date:
  * \code
-	struct calendar_date date = {
-	    .second = 12,
-	    .minute = 1,
-	    .hour = 22,
-	    .date = 8,
-	    .month = 2,
-	    .year = 1985
-	};
+    struct calendar_date date = {
+        .second = 12,
+        .minute = 1,
+        .hour = 22,
+        .date = 8,
+        .month = 2,
+        .year = 1985
+    };
 \endcode
  *
  * \subsection calendar_basic_use_case_setup_code Example code
@@ -169,14 +169,14 @@ void calendar_add_second_to_date(struct calendar_date *date);
  * be added to the project:
  * -# Three date structs:
  * \code
-	struct calendar_date result;
-	struct calendar_date end_date;
-	struct calendar_date start_date;
+    struct calendar_date result;
+    struct calendar_date end_date;
+    struct calendar_date start_date;
 \endcode
  * -# Two timestamps:
  * \code
-	uint32_t end_timestamp = 1309174659;
-	uint32_t start_timestamp = 123456789;
+    uint32_t end_timestamp = 1309174659;
+    uint32_t start_timestamp = 123456789;
 \endcode
  *
  * \subsection calendar_use_case_1_setup_code Example code
@@ -187,9 +187,9 @@ void calendar_add_second_to_date(struct calendar_date *date);
  * \subsection calendar_use_case_1_usage_code Example code
  * Add to, e.g. the main loop in the application C-file:
  * \code
-	calendar_timestamp_to_date(end_timestamp, &end_date);
-	calendar_timestamp_to_date(start_timestamp, &start_date);
-	calendar_time_between_dates(&end_date, &start_date, &result);
+    calendar_timestamp_to_date(end_timestamp, &end_date);
+    calendar_timestamp_to_date(start_timestamp, &start_date);
+    calendar_time_between_dates(&end_date, &start_date, &result);
 \endcode
  *
  * \subsection calendar_use_case_1_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h
index ca5bb97adecd..54ee2495124f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/dfll.h
@@ -76,19 +76,19 @@
  * closed-loop mode using the default parameters specified through
  * configuration symbols.
  * \code
-	dfll_enable_config_defaults(0); \endcode
+    dfll_enable_config_defaults(0); \endcode
  *
  * To configure and enable DFLL0 in closed-loop mode using the default
  * parameters and to enable specific feature like dithering for better accuracy,
  * you can use this initialization process.
  * \code
-	struct dfll_config dfllcfg;
+    struct dfll_config dfllcfg;
 
-	dfll_enable_source(CONFIG_DFLL0_SOURCE);
-	dfll_config_defaults(&dfllcfg, 0);
-	dfll_config_enable_dithering(&dfllcfg);
-	dfll_enable(&dfllcfg, 0);
-	dfll_wait_for_accurate_lock(0); \endcode
+    dfll_enable_source(CONFIG_DFLL0_SOURCE);
+    dfll_config_defaults(&dfllcfg, 0);
+    dfll_config_enable_dithering(&dfllcfg);
+    dfll_enable(&dfllcfg, 0);
+    dfll_wait_for_accurate_lock(0); \endcode
  *
  * When the last function call returns, DFLL0 is running at a frequency
  * which matches the default configuration as accurately as possible.
@@ -100,8 +100,8 @@
  * @{
  */
 
-//! \name Chip-specific DFLL characteristics
-//@{
+/*! \name Chip-specific DFLL characteristics*/
+/*@{*/
 /**
  * \def NR_DFLLS
  * \brief Number of on-chip DFLLs.
@@ -114,15 +114,15 @@
  * \def DFLL_MAX_HZ
  * \brief Maximum frequency that the DFLL can generate.
  */
-//@}
+/*@}*/
 
 /**
  * \typedef dfll_refclk_t
  * \brief Type used for identifying a reference clock source for the DFLL.
  */
 
-//! \name DFLL Configuration
-//@{
+/*! \name DFLL Configuration*/
+/*@{*/
 
 /**
  * \struct dfll_config
@@ -248,10 +248,10 @@
  *
  * \param cfg The DFLL configuration to be modified.
  */
-//@}
+/*@}*/
 
-//! \name Interaction with the DFLL hardware
-//@{
+/*! \name Interaction with the DFLL hardware*/
+/*@{*/
 /**
  * \fn void dfll_enable_open_loop(const struct dfll_config *cfg,
  *              unsigned int dfll_id)
@@ -350,12 +350,13 @@
  */
 static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
 {
-	/* TODO: Add timeout mechanism */
-	while (!dfll_is_coarse_locked(dfll_id)) {
-		/* Do nothing */
-	}
+    /* TODO: Add timeout mechanism */
+    while (!dfll_is_coarse_locked(dfll_id))
+    {
+        /* Do nothing */
+    }
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -369,12 +370,13 @@ static inline int dfll_wait_for_coarse_lock(unsigned int dfll_id)
  */
 static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
 {
-	/* TODO: Add timeout mechanism */
-	while (!dfll_is_fine_locked(dfll_id)) {
-		/* Do nothing */
-	}
+    /* TODO: Add timeout mechanism */
+    while (!dfll_is_fine_locked(dfll_id))
+    {
+        /* Do nothing */
+    }
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -388,15 +390,16 @@ static inline int dfll_wait_for_fine_lock(unsigned int dfll_id)
  */
 static inline int dfll_wait_for_accurate_lock(unsigned int dfll_id)
 {
-	/* TODO: Add timeout mechanism */
-	while (!dfll_is_accurate_locked(dfll_id)) {
-		/* Do nothing */
-	}
+    /* TODO: Add timeout mechanism */
+    while (!dfll_is_accurate_locked(dfll_id))
+    {
+        /* Do nothing */
+    }
 
-	return 0;
+    return 0;
 }
 
-//@}
-//! @}
+/*@}*/
+/*! @}*/
 
 #endif /* CLK_DFLL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h
index 503a50a2f99f..4ececa6252b8 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/genclk.h
@@ -123,8 +123,8 @@
  * These are the available alternatives provided by the chip.
  */
 
-//! \name Generic clock configuration
-//@{
+/*! \name Generic clock configuration*/
+/*@{*/
 /**
  * \struct genclk_config
  * \brief Hardware representation of a set of generic clock parameters
@@ -160,10 +160,10 @@
  * \fn void genclk_enable_source(enum genclk_source src)
  * \brief Enable the source clock \a src used by a generic clock.
  */
- //@}
+ /*@}*/
 
-//! \name Enabling and disabling Generic Clocks
-//@{
+/*! \name Enabling and disabling Generic Clocks*/
+/*@{*/
 /**
  * \fn void genclk_enable(const struct genclk_config *cfg, unsigned int id)
  * \brief Activate the configuration \a cfg on the clock identified by
@@ -173,7 +173,7 @@
  * \fn void genclk_disable(unsigned int id)
  * \brief Disable the generic clock identified by \a id.
  */
-//@}
+/*@}*/
 
 /**
  * \brief Enable the configuration defined by \a src and \a divider
@@ -185,15 +185,15 @@
  */
 static inline void genclk_enable_config(unsigned int id, enum genclk_source src, unsigned int divider)
 {
-	struct genclk_config gcfg;
+    struct genclk_config gcfg;
 
-	genclk_config_defaults(&gcfg, id);
-	genclk_enable_source(src);
-	genclk_config_set_source(&gcfg, src);
-	genclk_config_set_divider(&gcfg, divider);
-	genclk_enable(&gcfg, id);
+    genclk_config_defaults(&gcfg, id);
+    genclk_enable_source(src);
+    genclk_config_set_source(&gcfg, src);
+    genclk_config_set_divider(&gcfg, divider);
+    genclk_enable(&gcfg, id);
 }
 
-//! @}
+/*! @}*/
 
 #endif /* CLK_GENCLK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h
index e67f01f50293..6d01ee72b6b2 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/osc.h
@@ -118,8 +118,8 @@
  * procedure is used on all platforms, the parameter to osc_enable()
  * will be different from device to device.
  * \code
-	osc_enable(OSC_ID_XOSC);
-	osc_wait_ready(OSC_ID_XOSC); \endcode
+    osc_enable(OSC_ID_XOSC);
+    osc_wait_ready(OSC_ID_XOSC); \endcode
  *
  * \section osc_group_board Board-specific Definitions
  * If external oscillators are used, the board code must provide the
@@ -134,8 +134,8 @@
  * @{
  */
 
-//! \name Oscillator Management
-//@{
+/*! \name Oscillator Management*/
+/*@{*/
 /**
  * \fn void osc_enable(uint8_t id)
  * \brief Enable oscillator \a id
@@ -171,15 +171,16 @@
  */
 static inline void osc_wait_ready(uint8_t id)
 {
-	while (!osc_is_ready(id)) {
-		/* Do nothing */
-	}
+    while (!osc_is_ready(id))
+    {
+        /* Do nothing */
+    }
 }
 
 #endif /* __ASSEMBLY__ */
 
-//@}
+/*@}*/
 
-//! @}
+/*! @}*/
 
 #endif /* OSC_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h
index 23e930c00a53..8fa1b3148a3c 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/pll.h
@@ -120,21 +120,22 @@
  * the default parameters specified using the configuration symbols
  * listed above.
  * \code
-	pll_enable_config_defaults(0); \endcode
+    pll_enable_config_defaults(0); \endcode
  *
  * To configure, enable PLL0 using the default parameters and to disable
  * a specific feature like Wide Bandwidth Mode (a UC3A3-specific
  * PLL option.), you can use this initialization process.
  * \code
-	struct pll_config pllcfg;
-	if (pll_is_locked(pll_id)) {
-		return; // Pll already running
-	}
-	pll_enable_source(CONFIG_PLL0_SOURCE);
-	pll_config_defaults(&pllcfg, 0);
-	pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
-	pll_enable(&pllcfg, 0);
-	pll_wait_for_lock(0); \endcode
+    struct pll_config pllcfg;
+    if (pll_is_locked(pll_id))
+    {
+        return; // Pll already running
+    }
+    pll_enable_source(CONFIG_PLL0_SOURCE);
+    pll_config_defaults(&pllcfg, 0);
+    pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
+    pll_enable(&pllcfg, 0);
+    pll_wait_for_lock(0); \endcode
  *
  * When the last function call returns, PLL0 is ready to be used as the
  * main system clock source.
@@ -156,8 +157,8 @@
  * @{
  */
 
-//! \name Chip-specific PLL characteristics
-//@{
+/*! \name Chip-specific PLL characteristics*/
+/*@{*/
 /**
  * \def PLL_MAX_STARTUP_CYCLES
  * \brief Maximum PLL startup time in number of slow clock cycles
@@ -179,15 +180,15 @@
  * \def PLL_NR_OPTIONS
  * \brief Number of PLL option bits
  */
-//@}
+/*@}*/
 
 /**
  * \enum pll_source
  * \brief PLL clock source
  */
 
-//! \name PLL configuration
-//@{
+/*! \name PLL configuration*/
+/*@{*/
 
 /**
  * \struct pll_config
@@ -266,10 +267,10 @@
  * \param pll_id The ID of the PLL to be updated.
  */
 
-//@}
+/*@}*/
 
-//! \name Interaction with the PLL hardware
-//@{
+/*! \name Interaction with the PLL hardware*/
+/*@{*/
 /**
  * \fn void pll_enable(const struct pll_config *cfg,
  *              unsigned int pll_id)
@@ -326,16 +327,17 @@
  */
 static inline int pll_wait_for_lock(unsigned int pll_id)
 {
-	Assert(pll_id < NR_PLLS);
+    Assert(pll_id < NR_PLLS);
 
-	while (!pll_is_locked(pll_id)) {
-		/* Do nothing */
-	}
+    while (!pll_is_locked(pll_id))
+    {
+        /* Do nothing */
+    }
 
-	return 0;
+    return 0;
 }
 
-//@}
-//! @}
+/*@}*/
+/*! @}*/
 
 #endif /* CLK_PLL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h b/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h
index 86e4bf7a247a..3da473ae25f1 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/clock/sysclk.h
@@ -164,8 +164,8 @@
  * @{
  */
 
-//! \name System Clock Initialization
-//@{
+/*! \name System Clock Initialization*/
+/*@{*/
 /**
  * \fn void sysclk_init(void)
  * \brief Initialize the synchronous clock system.
@@ -187,8 +187,8 @@
  * is the responsibility of the peripheral driver to re-enable any
  * clocks that are needed for normal operation.
  */
-//@}
+/*@}*/
 
-//! @}
+/*! @}*/
 
 #endif /* SYSCLK_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h b/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h
index 9d91bfb621c6..dd99d68fb1a2 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/cpu/reset_cause.h
@@ -101,43 +101,43 @@
 # define CHIP_RESET_CAUSE_BOD_IO        0
 #endif
 #ifndef CHIP_RESET_CAUSE_CPU_ERROR
-//! CPU error reset cause not available on this chip.
+/*! CPU error reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_CPU_ERROR     0
 #endif
 #ifndef CHIP_RESET_CAUSE_EXTRST
-//! External reset cause not available on this chip.
+/*! External reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_EXTRST        0
 #endif
 #ifndef CHIP_RESET_CAUSE_JTAG
-//! JTAG reset cause not available on this chip.
+/*! JTAG reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_JTAG          0
 #endif
 #ifndef CHIP_RESET_CAUSE_OCD
-//! On-chip debug system reset cause not available on this chip.
+/*! On-chip debug system reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_OCD           0
 #endif
 #ifndef CHIP_RESET_CAUSE_POR
-//! Power-on-reset reset cause not available on this chip.
+/*! Power-on-reset reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_POR           0
 #endif
 #ifndef CHIP_RESET_CAUSE_POR_IO
-//! Power-on-reset on I/O power domain reset cause not available on this chip.
+/*! Power-on-reset on I/O power domain reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_POR_IO           0
 #endif
 #ifndef CHIP_RESET_CAUSE_SLEEP
-//! Wake from Shutdown sleep mode reset cause not available on this chip.
+/*! Wake from Shutdown sleep mode reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_SLEEP         0
 #endif
 #ifndef CHIP_RESET_CAUSE_SOFT
-//! Software reset reset cause not available on this chip.
+/*! Software reset reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_SOFT          0
 #endif
 #ifndef CHIP_RESET_CAUSE_SPIKE
-//! Spike detected reset cause not available on this chip.
+/*! Spike detected reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_SPIKE         0
 #endif
 #ifndef CHIP_RESET_CAUSE_WDT
-//! Watchdog timeout reset cause not available on this chip.
+/*! Watchdog timeout reset cause not available on this chip.*/
 # define CHIP_RESET_CAUSE_WDT           0
 #endif
 
@@ -145,34 +145,34 @@
  * \brief List of reset causes in bit-mask format
  */
 enum reset_cause {
-	/** \brief Brown-out detected on CPU power domain reset cause */
-	RESET_CAUSE_BOD_CPU     = CHIP_RESET_CAUSE_BOD_CPU,
-	/** \brief Brown-out detected on I/O power domain reset cause */
-	RESET_CAUSE_BOD_IO      = CHIP_RESET_CAUSE_BOD_IO,
-	/** \brief CPU error reset cause */
-	RESET_CAUSE_CPU_ERROR   = CHIP_RESET_CAUSE_CPU_ERROR,
-	/** \brief External reset cause */
-	RESET_CAUSE_EXTRST      = CHIP_RESET_CAUSE_EXTRST,
-	/** \brief JTAG reset cause */
-	RESET_CAUSE_JTAG        = CHIP_RESET_CAUSE_JTAG,
-	/** \brief On-chip debug system reset cause */
-	RESET_CAUSE_OCD         = CHIP_RESET_CAUSE_OCD,
-	/** \brief Power-on-reset reset cause */
-	RESET_CAUSE_POR         = CHIP_RESET_CAUSE_POR,
-	/** \brief Power-on-reset reset cause */
-	RESET_CAUSE_POR_IO         = CHIP_RESET_CAUSE_POR_IO,
-	/** \brief Wake from Shutdown sleep mode reset cause */
-	RESET_CAUSE_SLEEP       = CHIP_RESET_CAUSE_SLEEP,
-	/** \brief Software reset reset cause */
-	RESET_CAUSE_SOFT        = CHIP_RESET_CAUSE_SOFT,
-	/** \brief Spike detected reset cause */
-	RESET_CAUSE_SPIKE       = CHIP_RESET_CAUSE_SPIKE,
-	/** \brief Watchdog timeout reset cause */
-	RESET_CAUSE_WDT         = CHIP_RESET_CAUSE_WDT,
+    /** \brief Brown-out detected on CPU power domain reset cause */
+    RESET_CAUSE_BOD_CPU     = CHIP_RESET_CAUSE_BOD_CPU,
+    /** \brief Brown-out detected on I/O power domain reset cause */
+    RESET_CAUSE_BOD_IO      = CHIP_RESET_CAUSE_BOD_IO,
+    /** \brief CPU error reset cause */
+    RESET_CAUSE_CPU_ERROR   = CHIP_RESET_CAUSE_CPU_ERROR,
+    /** \brief External reset cause */
+    RESET_CAUSE_EXTRST      = CHIP_RESET_CAUSE_EXTRST,
+    /** \brief JTAG reset cause */
+    RESET_CAUSE_JTAG        = CHIP_RESET_CAUSE_JTAG,
+    /** \brief On-chip debug system reset cause */
+    RESET_CAUSE_OCD         = CHIP_RESET_CAUSE_OCD,
+    /** \brief Power-on-reset reset cause */
+    RESET_CAUSE_POR         = CHIP_RESET_CAUSE_POR,
+    /** \brief Power-on-reset reset cause */
+    RESET_CAUSE_POR_IO         = CHIP_RESET_CAUSE_POR_IO,
+    /** \brief Wake from Shutdown sleep mode reset cause */
+    RESET_CAUSE_SLEEP       = CHIP_RESET_CAUSE_SLEEP,
+    /** \brief Software reset reset cause */
+    RESET_CAUSE_SOFT        = CHIP_RESET_CAUSE_SOFT,
+    /** \brief Spike detected reset cause */
+    RESET_CAUSE_SPIKE       = CHIP_RESET_CAUSE_SPIKE,
+    /** \brief Watchdog timeout reset cause */
+    RESET_CAUSE_WDT         = CHIP_RESET_CAUSE_WDT,
 };
 
-//! \name Management
-//@{
+/*! \name Management*/
+/*@{*/
 
 /**
  * \fn void reset_do_soft_reset(void)
@@ -201,10 +201,10 @@ enum reset_cause {
  * \param causes bit-mask of reset causes to clear
  */
 
-//@}
+/*@}*/
 
-//! \name Specific reset cause helper functions
-//@{
+/*! \name Specific reset cause helper functions*/
+/*@{*/
 
 /**
  * \brief Check if chip reset was caused by a CPU power brown-out detection
@@ -213,7 +213,7 @@ enum reset_cause {
  */
 static inline bool reset_cause_is_cpu_brown_out_detected(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_BOD_CPU);
+    return (reset_cause_get_causes() & RESET_CAUSE_BOD_CPU);
 }
 
 /**
@@ -223,7 +223,7 @@ static inline bool reset_cause_is_cpu_brown_out_detected(void)
  */
 static inline bool reset_cause_is_io_brown_out_detected(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_BOD_IO);
+    return (reset_cause_get_causes() & RESET_CAUSE_BOD_IO);
 }
 
 /**
@@ -234,8 +234,8 @@ static inline bool reset_cause_is_io_brown_out_detected(void)
  */
 static inline bool reset_cause_is_brown_out_detected(void)
 {
-	return (reset_cause_is_cpu_brown_out_detected() ||
-			reset_cause_is_io_brown_out_detected());
+    return (reset_cause_is_cpu_brown_out_detected() ||
+            reset_cause_is_io_brown_out_detected());
 }
 
 /**
@@ -245,7 +245,7 @@ static inline bool reset_cause_is_brown_out_detected(void)
  */
 static inline bool reset_cause_is_cpu_error(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_CPU_ERROR);
+    return (reset_cause_get_causes() & RESET_CAUSE_CPU_ERROR);
 }
 
 /**
@@ -255,7 +255,7 @@ static inline bool reset_cause_is_cpu_error(void)
  */
 static inline bool reset_cause_is_external_reset(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_EXTRST);
+    return (reset_cause_get_causes() & RESET_CAUSE_EXTRST);
 }
 
 /**
@@ -265,7 +265,7 @@ static inline bool reset_cause_is_external_reset(void)
  */
 static inline bool reset_cause_is_jtag(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_JTAG);
+    return (reset_cause_get_causes() & RESET_CAUSE_JTAG);
 }
 
 /**
@@ -275,7 +275,7 @@ static inline bool reset_cause_is_jtag(void)
  */
 static inline bool reset_cause_is_ocd(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_OCD);
+    return (reset_cause_get_causes() & RESET_CAUSE_OCD);
 }
 
 /**
@@ -285,7 +285,7 @@ static inline bool reset_cause_is_ocd(void)
  */
 static inline bool reset_cause_is_power_on_reset(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_POR);
+    return (reset_cause_get_causes() & RESET_CAUSE_POR);
 }
 
 /**
@@ -295,7 +295,7 @@ static inline bool reset_cause_is_power_on_reset(void)
  */
 static inline bool reset_cause_is_io_power_on_reset(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_POR_IO);
+    return (reset_cause_get_causes() & RESET_CAUSE_POR_IO);
 }
 
 /**
@@ -305,7 +305,7 @@ static inline bool reset_cause_is_io_power_on_reset(void)
  */
 static inline bool reset_cause_is_wake_from_shutdown_sleep(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_SLEEP);
+    return (reset_cause_get_causes() & RESET_CAUSE_SLEEP);
 }
 
 /**
@@ -315,7 +315,7 @@ static inline bool reset_cause_is_wake_from_shutdown_sleep(void)
  */
 static inline bool reset_cause_is_software_reset(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_SOFT);
+    return (reset_cause_get_causes() & RESET_CAUSE_SOFT);
 }
 
 /**
@@ -325,7 +325,7 @@ static inline bool reset_cause_is_software_reset(void)
  */
 static inline bool reset_cause_is_spike_detected(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_SPIKE);
+    return (reset_cause_get_causes() & RESET_CAUSE_SPIKE);
 }
 
 /**
@@ -335,12 +335,12 @@ static inline bool reset_cause_is_spike_detected(void)
  */
 static inline bool reset_cause_is_watchdog(void)
 {
-	return (reset_cause_get_causes() & RESET_CAUSE_WDT);
+    return (reset_cause_get_causes() & RESET_CAUSE_WDT);
 }
 
-//@}
+/*@}*/
 
-//! @}
+/*! @}*/
 
 /**
  * \page reset_cause_quickstart Quick start guide for reset cause service
@@ -362,15 +362,17 @@ static inline bool reset_cause_is_watchdog(void)
  * \subsection reset_cause_basic_use_case_setup_code Example code
  * Add to application C-file:
  * \code
-	 if (reset_cause_is_watchdog()) {
-		// Do action due to last reset being a watchdog reset
-		reset_cause_clear_causes(RESET_CAUSE_WDT);
-	 }
+     if (reset_cause_is_watchdog())
+     {
+        // Do action due to last reset being a watchdog reset
+        reset_cause_clear_causes(RESET_CAUSE_WDT);
+     }
 \endcode
  *
  * \subsection reset_cause_basic_use_case_setup_flow Workflow
  * -# Check for watchdog reset flag:
- *   - \code if (reset_cause_is_watchdog()) { \endcode
+ *   - \code if (reset_cause_is_watchdog())
+ { \endcode
  *   - \attention Please consult the specific device datasheet on which reset
  *   causes that are supported.
  * -# Insert your own code taking action here. E.g.: Increase a watchdog reset
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c
index e962c06d93fe..6b4d900cc2a5 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.c
@@ -82,21 +82,23 @@ typedef unsigned int word_t;
  * \attention This implementation assumes a little-endian architecture.
  */
 static inline crc32_t _crc32_recalculate_bytes_helper(word_t data,
-		crc32_t crc, uint_fast8_t bytes)
+        crc32_t crc, uint_fast8_t bytes)
 {
-	uint_fast8_t bit;
+    uint_fast8_t bit;
 
-	crc ^= data;
+    crc ^= data;
 
-	for (bit = 8 * bytes; bit > 0; bit--) {
-		if (crc & 1) {
-			crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
-		} else {
-			crc >>= 1;
-		}
-	}
+    for (bit = 8 * bytes; bit > 0; bit--)
+    {
+        if (crc & 1)
+        {
+            crc = (crc >> 1) ^ CRC32_POLYNOMIAL;
+        } else {
+            crc >>= 1;
+        }
+    }
 
-	return crc;
+    return crc;
 }
 
 /**
@@ -124,48 +126,53 @@ static inline crc32_t _crc32_recalculate_bytes_helper(word_t data,
  */
 enum status_code crc32_recalculate(const void *data, size_t length, crc32_t *crc)
 {
-	const word_t *word_ptr =
-			(word_t *)((uintptr_t)data & WORD_ALIGNMENT_MASK);
-	size_t temp_length;
-	crc32_t temp_crc = COMPLEMENT_CRC(*crc);
-	word_t word;
-
-	// Calculate for initial bytes to get word-aligned
-	if (length < WORD_SIZE) {
-		temp_length = length;
-	} else {
-		temp_length = ~WORD_ALIGNMENT_MASK & (WORD_SIZE - (uintptr_t)data);
-	}
-
-	if (temp_length) {
-		length -= temp_length;
-
-		word = *(word_ptr++);
-		word >>= 8 * (WORD_SIZE - temp_length);
-		temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, temp_length);
-	}
-
-	// Calculate for whole words, if any
-	temp_length = length & WORD_ALIGNMENT_MASK;
-
-	if (temp_length) {
-		length -= temp_length;
-		temp_length /= WORD_SIZE;
-
-		while (temp_length--) {
-			word = *(word_ptr++);
-			temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, WORD_SIZE);
-		}
-	}
-
-	// Calculate for tailing bytes
-	if (length) {
-		word = *word_ptr;
-		word &= 0xffffffffUL >> (8 * (WORD_SIZE - length));
-		temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, length);
-	}
-
-	*crc = COMPLEMENT_CRC(temp_crc);
-
-	return STATUS_OK;
-}
\ No newline at end of file
+    const word_t *word_ptr =
+            (word_t *)((uintptr_t)data & WORD_ALIGNMENT_MASK);
+    size_t temp_length;
+    crc32_t temp_crc = COMPLEMENT_CRC(*crc);
+    word_t word;
+
+    /* Calculate for initial bytes to get word-aligned*/
+    if (length < WORD_SIZE)
+    {
+        temp_length = length;
+    } else {
+        temp_length = ~WORD_ALIGNMENT_MASK & (WORD_SIZE - (uintptr_t)data);
+    }
+
+    if (temp_length)
+    {
+        length -= temp_length;
+
+        word = *(word_ptr++);
+        word >>= 8 * (WORD_SIZE - temp_length);
+        temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, temp_length);
+    }
+
+    /* Calculate for whole words, if any*/
+    temp_length = length & WORD_ALIGNMENT_MASK;
+
+    if (temp_length)
+    {
+        length -= temp_length;
+        temp_length /= WORD_SIZE;
+
+        while (temp_length--)
+        {
+            word = *(word_ptr++);
+            temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, WORD_SIZE);
+        }
+    }
+
+    /* Calculate for tailing bytes*/
+    if (length)
+    {
+        word = *word_ptr;
+        word &= 0xffffffffUL >> (8 * (WORD_SIZE - length));
+        temp_crc = _crc32_recalculate_bytes_helper(word, temp_crc, length);
+    }
+
+    *crc = COMPLEMENT_CRC(temp_crc);
+
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h
index e0994c3cf215..76ce4c9a8f80 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/crc32/crc32.h
@@ -64,7 +64,7 @@
  */
 
 
-//! Type to contain 32-bit CRC.
+/*! Type to contain 32-bit CRC.*/
 typedef uint32_t crc32_t;
 
 
@@ -100,11 +100,11 @@ enum status_code crc32_recalculate(const void *data, size_t length, crc32_t *crc
  * \ref crc32_recalculate() for the following blocks.
  */
 static inline enum status_code crc32_calculate(const void *data, size_t length,
-		crc32_t *crc)
+        crc32_t *crc)
 {
-	*crc = 0;
+    *crc = 0;
 
-	return crc32_recalculate(data, length, crc);
+    return crc32_recalculate(data, length, crc);
 }
 
 /** @} */
@@ -124,15 +124,15 @@ static inline enum status_code crc32_calculate(const void *data, size_t length,
  * \section common_services_crc32_quickstart_code Example Code
  *
 \code
-	uint8_t block1[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
-	uint8_t block2[6] = {0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
+    uint8_t block1[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
+    uint8_t block2[6] = {0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
 
-	crc32_t my_crc;
+    crc32_t my_crc;
 
-	crc32_calculate(block1, sizeof(block1), &my_crc);
-	crc32_recalculate(block2, sizeof(block2), &my_crc);
+    crc32_calculate(block1, sizeof(block1), &my_crc);
+    crc32_recalculate(block2, sizeof(block2), &my_crc);
 \endcode
  *
  */
 
-#endif // CRC32_H
\ No newline at end of file
+#endif /* CRC32_H*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c
index 96669ef6b870..f33ca7dd3875 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.c
@@ -46,16 +46,16 @@
 
 #include "cycle_counter.h"
 
-// Delay loop is put to SRAM so that FWS will not affect delay time
+/* Delay loop is put to SRAM so that FWS will not affect delay time*/
 OPTIMIZE_HIGH
 RAMFUNC
 void portable_delay_cycles(unsigned long n)
 {
-	UNUSED(n);
+    UNUSED(n);
 
-	__asm (
-		"loop: DMB	\n"
-		"SUBS R0, R0, #1  \n"
-		"BNE.N loop         "
-	);
+    __asm (
+        "loop: DMB  \n"
+        "SUBS R0, R0, #1  \n"
+        "BNE.N loop         "
+    );
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h
index 4ac1c6b58337..bc0efd92bd02 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/delay/sam/cycle_counter.h
@@ -99,16 +99,16 @@ void portable_delay_cycles(unsigned long n);
 #ifdef __CM7_REV
 
 #  define cpu_ms_2_cy(ms, f_cpu)  \
-	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
+    (((uint64_t)(ms) * (f_cpu) + (uint64_t)(5.932e3 - 1ul)) / (uint64_t)5.932e3)
 #  define cpu_us_2_cy(us, f_cpu)  \
-	(((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
+    (((uint64_t)(us) * (f_cpu) + (uint64_t)(5.932e6 - 1ul)) / (uint64_t)5.932e6)
 
 #else
 
 #  define cpu_ms_2_cy(ms, f_cpu)  \
-	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
+    (((uint64_t)(ms) * (f_cpu) + (uint64_t)(14e3 - 1ul)) / (uint64_t)14e3)
 #  define cpu_us_2_cy(us, f_cpu)  \
-	(((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
+    (((uint64_t)(us) * (f_cpu) + (uint64_t)(14e6 - 1ul)) / (uint64_t)14e6)
 
 #endif
 
@@ -116,7 +116,7 @@ void portable_delay_cycles(unsigned long n);
 
 #define cpu_delay_ms(delay, f_cpu) delay_cycles(cpu_ms_2_cy(delay, f_cpu))
 #define cpu_delay_us(delay, f_cpu) delay_cycles(cpu_us_2_cy(delay, f_cpu))
-//! @}
+/*! @}*/
 
 
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c
index 1b251bf4c20b..45878b71bb54 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.c
@@ -55,28 +55,28 @@
 
 int fifo_init(fifo_desc_t *fifo_desc, void *buffer, uint8_t size)
 {
-	// Check the size parameter. It must be not null...
-	Assert (size);
+    /* Check the size parameter. It must be not null...*/
+    Assert (size);
 
-	// ... must be a 2-power ...
-	Assert (!(size & (size - 1)));
+    /* ... must be a 2-power ...*/
+    Assert (!(size & (size - 1)));
 
-	// ... and must fit in a uint8_t. Since the read and write indexes are using a
-	// double-index range implementation, the max FIFO size is thus 128 items.
-	Assert (size <= 128);
+    /* ... and must fit in a uint8_t. Since the read and write indexes are using a*/
+    /* double-index range implementation, the max FIFO size is thus 128 items.*/
+    Assert (size <= 128);
 
-	// Fifo starts empty.
-	fifo_desc->read_index  = 0;
-	fifo_desc->write_index = 0;
+    /* Fifo starts empty.*/
+    fifo_desc->read_index  = 0;
+    fifo_desc->write_index = 0;
 
-	// Save the size parameter.
-	fifo_desc->size = size;
+    /* Save the size parameter.*/
+    fifo_desc->size = size;
 
-	// Create a mask to speed up the FIFO management (index swapping).
-	fifo_desc->mask = (2 * (uint16_t)size) - 1;
+    /* Create a mask to speed up the FIFO management (index swapping).*/
+    fifo_desc->mask = (2 * (uint16_t)size) - 1;
 
-	// Save the buffer pointer.
-	fifo_desc->buffer.u8ptr = buffer;
+    /* Save the buffer pointer.*/
+    fifo_desc->buffer.u8ptr = buffer;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h
index 7d57ad129768..b4e4685abba2 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/fifo/fifo.h
@@ -72,26 +72,26 @@
  * @{
  */
 
-//! Error codes used by FIFO driver.
+/*! Error codes used by FIFO driver.*/
 enum {
-	FIFO_OK = 0,          //!< Normal operation.
-	FIFO_ERROR_OVERFLOW,  //!< Attempt to push something in a FIFO that is full.
-	FIFO_ERROR_UNDERFLOW, //!< Attempt to pull something from a FIFO that is empty
-	FIFO_ERROR,           //!< Error condition during FIFO initialization
+    FIFO_OK = 0,          /*!< Normal operation.*/
+    FIFO_ERROR_OVERFLOW,  /*!< Attempt to push something in a FIFO that is full.*/
+    FIFO_ERROR_UNDERFLOW, /*!< Attempt to pull something from a FIFO that is empty*/
+    FIFO_ERROR,           /*!< Error condition during FIFO initialization*/
 };
 
-//! FIFO descriptor used by FIFO driver.
+/*! FIFO descriptor used by FIFO driver.*/
 struct fifo_desc {
-	union
-	{
-		uint32_t *u32ptr; //!< Pointer to unsigned-32 bits location
-		uint16_t *u16ptr; //!< Pointer to unsigned-16 bits location
-		uint8_t  *u8ptr;  //!< Pointer to unsigned-8 bits location
-	}  buffer;
-	volatile uint8_t read_index;  //!< Read index
-	volatile uint8_t write_index; //!< Write index
-	uint8_t size;                 //!< Size of the FIFO (unit is in number of 'element')
-	uint8_t mask;                 //!< Mask used to speed up FIFO operation (wrapping)
+    union
+    {
+        uint32_t *u32ptr; /*!< Pointer to unsigned-32 bits location*/
+        uint16_t *u16ptr; /*!< Pointer to unsigned-16 bits location*/
+        uint8_t  *u8ptr;  /*!< Pointer to unsigned-8 bits location*/
+    }  buffer;
+    volatile uint8_t read_index;  /*!< Read index*/
+    volatile uint8_t write_index; /*!< Write index*/
+    uint8_t size;                 /*!< Size of the FIFO (unit is in number of 'element')*/
+    uint8_t mask;                 /*!< Mask used to speed up FIFO operation (wrapping)*/
 };
 
 typedef struct fifo_desc fifo_desc_t;
@@ -121,7 +121,7 @@ int fifo_init(fifo_desc_t *fifo_desc, void *buffer, uint8_t size);
  */
 static inline uint8_t fifo_get_used_size(fifo_desc_t *fifo_desc)
 {
-	return ((fifo_desc->write_index - fifo_desc->read_index) & fifo_desc->mask);
+    return ((fifo_desc->write_index - fifo_desc->read_index) & fifo_desc->mask);
 }
 
 /**
@@ -133,7 +133,7 @@ static inline uint8_t fifo_get_used_size(fifo_desc_t *fifo_desc)
  */
 static inline uint8_t fifo_get_free_size(fifo_desc_t *fifo_desc)
 {
-	return fifo_desc->size - fifo_get_used_size(fifo_desc);
+    return fifo_desc->size - fifo_get_used_size(fifo_desc);
 }
 
 /**
@@ -147,7 +147,7 @@ static inline uint8_t fifo_get_free_size(fifo_desc_t *fifo_desc)
  */
 static inline bool fifo_is_empty(fifo_desc_t *fifo_desc)
 {
-	return (fifo_desc->write_index == fifo_desc->read_index);
+    return (fifo_desc->write_index == fifo_desc->read_index);
 }
 
 /**
@@ -161,7 +161,7 @@ static inline bool fifo_is_empty(fifo_desc_t *fifo_desc)
  */
 static inline bool fifo_is_full(fifo_desc_t *fifo_desc)
 {
-	return (fifo_get_used_size(fifo_desc) == fifo_desc->size);
+    return (fifo_get_used_size(fifo_desc) == fifo_desc->size);
 }
 
 /**
@@ -172,15 +172,15 @@ static inline bool fifo_is_full(fifo_desc_t *fifo_desc)
  */
 static inline void fifo_push_uint8_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 }
 
 /**
@@ -196,21 +196,22 @@ static inline void fifo_push_uint8_nocheck(fifo_desc_t *fifo_desc, uint32_t item
  */
 static inline int fifo_push_uint8(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	if (fifo_is_full(fifo_desc)) {
-		return FIFO_ERROR_OVERFLOW;
-	}
+    if (fifo_is_full(fifo_desc))
+    {
+        return FIFO_ERROR_OVERFLOW;
+    }
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u8ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -221,15 +222,15 @@ static inline int fifo_push_uint8(fifo_desc_t *fifo_desc, uint32_t item)
  */
 static inline void fifo_push_uint16_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 }
 
 /**
@@ -245,21 +246,22 @@ static inline void fifo_push_uint16_nocheck(fifo_desc_t *fifo_desc, uint32_t ite
  */
 static inline int fifo_push_uint16(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	if (fifo_is_full(fifo_desc)) {
-		return FIFO_ERROR_OVERFLOW;
-	}
+    if (fifo_is_full(fifo_desc))
+    {
+        return FIFO_ERROR_OVERFLOW;
+    }
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u16ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -270,15 +272,15 @@ static inline int fifo_push_uint16(fifo_desc_t *fifo_desc, uint32_t item)
  */
 static inline void fifo_push_uint32_nocheck(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 }
 
 /**
@@ -294,21 +296,22 @@ static inline void fifo_push_uint32_nocheck(fifo_desc_t *fifo_desc, uint32_t ite
  */
 static inline int fifo_push_uint32(fifo_desc_t *fifo_desc, uint32_t item)
 {
-	uint8_t write_index;
+    uint8_t write_index;
 
-	if (fifo_is_full(fifo_desc)) {
-		return FIFO_ERROR_OVERFLOW;
-	}
+    if (fifo_is_full(fifo_desc))
+    {
+        return FIFO_ERROR_OVERFLOW;
+    }
 
-	write_index = fifo_desc->write_index;
-	fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
-	write_index = (write_index + 1) & fifo_desc->mask;
+    write_index = fifo_desc->write_index;
+    fifo_desc->buffer.u32ptr[write_index & (fifo_desc->mask >> 1)] = item;
+    write_index = (write_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->write_index = write_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->write_index = write_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -320,18 +323,18 @@ static inline int fifo_push_uint32(fifo_desc_t *fifo_desc, uint32_t item)
  */
 static inline uint8_t fifo_pull_uint8_nocheck(fifo_desc_t *fifo_desc)
 {
-	uint8_t read_index;
-	uint8_t item;
+    uint8_t read_index;
+    uint8_t item;
 
-	read_index = fifo_desc->read_index;
-	item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return item;
+    return item;
 }
 
 /**
@@ -347,21 +350,22 @@ static inline uint8_t fifo_pull_uint8_nocheck(fifo_desc_t *fifo_desc)
  */
 static inline int fifo_pull_uint8(fifo_desc_t *fifo_desc, uint8_t *item)
 {
-	uint8_t read_index;
+    uint8_t read_index;
 
-	if (fifo_is_empty(fifo_desc)) {
-		return FIFO_ERROR_UNDERFLOW;
-	}
+    if (fifo_is_empty(fifo_desc))
+    {
+        return FIFO_ERROR_UNDERFLOW;
+    }
 
-	read_index = fifo_desc->read_index;
-	*item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    *item = fifo_desc->buffer.u8ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -373,18 +377,18 @@ static inline int fifo_pull_uint8(fifo_desc_t *fifo_desc, uint8_t *item)
  */
 static inline uint16_t fifo_pull_uint16_nocheck(fifo_desc_t *fifo_desc)
 {
-	uint8_t read_index;
-	uint16_t item;
+    uint8_t read_index;
+    uint16_t item;
 
-	read_index = fifo_desc->read_index;
-	item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return item;
+    return item;
 }
 
 /**
@@ -400,21 +404,22 @@ static inline uint16_t fifo_pull_uint16_nocheck(fifo_desc_t *fifo_desc)
  */
 static inline int fifo_pull_uint16(fifo_desc_t *fifo_desc, uint16_t *item)
 {
-	uint8_t read_index;
+    uint8_t read_index;
 
-	if (fifo_is_empty(fifo_desc)) {
-		return FIFO_ERROR_UNDERFLOW;
-	}
+    if (fifo_is_empty(fifo_desc))
+    {
+        return FIFO_ERROR_UNDERFLOW;
+    }
 
-	read_index = fifo_desc->read_index;
-	*item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    *item = fifo_desc->buffer.u16ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -426,18 +431,18 @@ static inline int fifo_pull_uint16(fifo_desc_t *fifo_desc, uint16_t *item)
  */
 static inline uint32_t fifo_pull_uint32_nocheck(fifo_desc_t *fifo_desc)
 {
-	uint8_t read_index;
-	uint32_t item;
+    uint8_t read_index;
+    uint32_t item;
 
-	read_index = fifo_desc->read_index;
-	item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return item;
+    return item;
 }
 
 /**
@@ -453,21 +458,22 @@ static inline uint32_t fifo_pull_uint32_nocheck(fifo_desc_t *fifo_desc)
  */
 static inline int fifo_pull_uint32(fifo_desc_t *fifo_desc, uint32_t *item)
 {
-	uint8_t read_index;
+    uint8_t read_index;
 
-	if (fifo_is_empty(fifo_desc)) {
-		return FIFO_ERROR_UNDERFLOW;
-	}
+    if (fifo_is_empty(fifo_desc))
+    {
+        return FIFO_ERROR_UNDERFLOW;
+    }
 
-	read_index = fifo_desc->read_index;
-	*item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
-	read_index = (read_index + 1) & fifo_desc->mask;
+    read_index = fifo_desc->read_index;
+    *item = fifo_desc->buffer.u32ptr[read_index & (fifo_desc->mask >> 1)];
+    read_index = (read_index + 1) & fifo_desc->mask;
 
-	// Must be the last thing to do.
-	barrier();
-	fifo_desc->read_index = read_index;
+    /* Must be the last thing to do.*/
+    barrier();
+    fifo_desc->read_index = read_index;
 
-	return FIFO_OK;
+    return FIFO_OK;
 }
 
 /**
@@ -480,7 +486,7 @@ static inline int fifo_pull_uint32(fifo_desc_t *fifo_desc, uint32_t *item)
  */
 static inline uint32_t fifo_peek_uint32(fifo_desc_t *fifo_desc)
 {
-	return fifo_desc->buffer.u32ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+    return fifo_desc->buffer.u32ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
 }
 
 /**
@@ -493,7 +499,7 @@ static inline uint32_t fifo_peek_uint32(fifo_desc_t *fifo_desc)
  */
 static inline uint16_t fifo_peek_uint16(fifo_desc_t *fifo_desc)
 {
-	return fifo_desc->buffer.u16ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+    return fifo_desc->buffer.u16ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
 }
 
 /**
@@ -506,7 +512,7 @@ static inline uint16_t fifo_peek_uint16(fifo_desc_t *fifo_desc)
  */
 static inline uint8_t fifo_peek_uint8(fifo_desc_t *fifo_desc)
 {
-	return fifo_desc->buffer.u8ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
+    return fifo_desc->buffer.u8ptr[fifo_desc->read_index & (fifo_desc->mask >> 1)];
 }
 
 /**
@@ -516,8 +522,8 @@ static inline uint8_t fifo_peek_uint8(fifo_desc_t *fifo_desc)
  */
 static inline void fifo_flush(fifo_desc_t *fifo_desc)
 {
-	// Fifo starts empty.
-	fifo_desc->read_index = fifo_desc->write_index = 0;
+    /* Fifo starts empty.*/
+    fifo_desc->read_index = fifo_desc->write_index = 0;
 }
 
 /**
@@ -548,20 +554,20 @@ static inline void fifo_flush(fifo_desc_t *fifo_desc)
  * \subsection fifo_basic_use_case_setup_code Example code
  * The following must be added to the project:
  * \code
-	#define FIFO_BUFFER_LENGTH  4
-	#define PUSH_VALUE          0x12345678
-	union buffer_element {
-	   uint8_t  byte;
-	   uint16_t halfword;
-	   uint32_t word;
-	};
+    #define FIFO_BUFFER_LENGTH  4
+    #define PUSH_VALUE          0x12345678
+    union buffer_element {
+       uint8_t  byte;
+       uint16_t halfword;
+       uint32_t word;
+    };
 \endcode
  *
  * Add to application initialization:
  * \code
-	union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
-	fifo_desc_t fifo_desc;
-	fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); 
+    union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
+    fifo_desc_t fifo_desc;
+    fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH);
 \endcode
  *
  * \subsection fifo_basic_use_case_setup_flow Workflow
@@ -580,10 +586,10 @@ static inline void fifo_flush(fifo_desc_t *fifo_desc)
  * \subsection fifo_basic_use_case_usage_code Example code
  * Add to application C-file:
  * \code
-	uint8_t status;
-	uint8_t pull_value;
-	status = fifo_push_uint8(&fifo_desc, PUSH_VALUE & 0xff);
-	status = fifo_pull_uint8(&fifo_desc, &pull_value);
+    uint8_t status;
+    uint8_t pull_value;
+    status = fifo_push_uint8(&fifo_desc, PUSH_VALUE & 0xff);
+    status = fifo_pull_uint8(&fifo_desc, &pull_value);
 \endcode
  *
  * \subsection fifo_basic_use_case_usage_flow Workflow
@@ -610,20 +616,20 @@ static inline void fifo_flush(fifo_desc_t *fifo_desc)
  * \subsection fifo_use_case_1_setup_code Example code
  * The following must be added to the project:
  * \code
-	#define FIFO_BUFFER_LENGTH  4
-	#define PUSH_VALUE          0x12345678
-	union buffer_element {
-	   uint8_t  byte;
-	   uint16_t halfword;
-	   uint32_t word;
-	};
+    #define FIFO_BUFFER_LENGTH  4
+    #define PUSH_VALUE          0x12345678
+    union buffer_element {
+       uint8_t  byte;
+       uint16_t halfword;
+       uint32_t word;
+    };
 \endcode
  *
  * Add to application initialization:
  * \code
-	union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
-	fifo_desc_t fifo_desc;
-	fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH); 
+    union buffer_element fifo_buffer[FIFO_BUFFER_LENGTH];
+    fifo_desc_t fifo_desc;
+    fifo_init(&fifo_desc, fifo_buffer, FIFO_BUFFER_LENGTH);
 \endcode
  *
  * \subsection fifo_use_case_1_setup_flow Workflow
@@ -641,12 +647,12 @@ static inline void fifo_flush(fifo_desc_t *fifo_desc)
  * \subsection fifo_use_case_1_usage_code Example code
  * Add to application C-file:
  * \code
-	uint8_t status;
-	bool fifo_empty;
-	status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
-	status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
-	fifo_flush(&fifo_desc);
-	fifo_empty = fifo_is_empty(&fifo_desc);
+    uint8_t status;
+    bool fifo_empty;
+    status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
+    status = fifo_push_uint16(&fifo_desc, PUSH_VALUE & 0xffff);
+    fifo_flush(&fifo_desc);
+    fifo_empty = fifo_is_empty(&fifo_desc);
 \endcode
  *
  * \subsection fifo_use_case_1_usage_flow Workflow
@@ -665,4 +671,4 @@ static inline void fifo_flush(fifo_desc_t *fifo_desc)
  * \note The fifo_empty variable will be true if the FIFO is empty.
  */
 
-#endif  // _FIFO_H_
+#endif  /* _FIFO_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h b/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h
index cb5e974f6359..d4c8107815d3 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/gpio/sam_gpio/sam_gpio.h
@@ -51,33 +51,33 @@
 #include "pio.h"
 
 #define gpio_pin_is_low(io_id) \
-	(pio_get_pin_value(io_id) ? 0 : 1)
+    (pio_get_pin_value(io_id) ? 0 : 1)
 
 #define gpio_pin_is_high(io_id) \
-	(pio_get_pin_value(io_id) ? 1 : 0)
+    (pio_get_pin_value(io_id) ? 1 : 0)
 
 #define gpio_set_pin_high(io_id) \
-	pio_set_pin_high(io_id)
+    pio_set_pin_high(io_id)
 
 #define gpio_set_pin_low(io_id) \
-	pio_set_pin_low(io_id)
+    pio_set_pin_low(io_id)
 
 #define gpio_toggle_pin(io_id) \
-	pio_toggle_pin(io_id)
+    pio_toggle_pin(io_id)
 
 #define gpio_configure_pin(io_id,io_flags) \
-	pio_configure_pin(io_id,io_flags)
+    pio_configure_pin(io_id,io_flags)
 
 #define gpio_configure_group(port_id,port_mask,io_flags) \
-	pio_configure_pin_group(port_id,port_mask,io_flags)
+    pio_configure_pin_group(port_id,port_mask,io_flags)
 
 #define gpio_set_pin_group_high(port_id,mask) \
-	pio_set_pin_group_high(port_id,mask)
+    pio_set_pin_group_high(port_id,mask)
 
 #define gpio_set_pin_group_low(port_id,mask) \
-	pio_set_pin_group_low(port_id,mask)
+    pio_set_pin_group_low(port_id,mask)
 
 #define gpio_toggle_pin_group(port_id,mask) \
-	pio_toggle_pin_group(port_id,mask)
+    pio_toggle_pin_group(port_id,mask)
 
 #endif /* SAM_GPIO_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h
index d7aa125a95e5..4b9d4485fd5f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/generic/hugemem.h
@@ -69,47 +69,47 @@ typedef void * hugemem_ptr_t;
 
 static inline uint8_t hugemem_read8(const hugemem_ptr_t from)
 {
-	return *(uint8_t *)from;
+    return *(uint8_t *)from;
 }
 
 static inline uint16_t hugemem_read16(const hugemem_ptr_t from)
 {
-	return *(uint16_t *)from;
+    return *(uint16_t *)from;
 }
 
 static inline uint32_t hugemem_read32(const hugemem_ptr_t from)
 {
-	return *(uint32_t *)from;
+    return *(uint32_t *)from;
 }
 
 static inline void hugemem_read_block(void *to, const hugemem_ptr_t from,
-		size_t size)
+        size_t size)
 {
-	memcpy(to, from, size);
+    memcpy(to, from, size);
 }
 
 static inline void hugemem_write8(hugemem_ptr_t to, uint8_t val)
 {
-	*(uint8_t *)to = val;
+    *(uint8_t *)to = val;
 }
 
 static inline void hugemem_write16(hugemem_ptr_t to, uint16_t val)
 {
-	*(uint16_t *)to = val;
+    *(uint16_t *)to = val;
 }
 
 
 static inline void hugemem_write32(hugemem_ptr_t to, uint32_t val)
 {
-	*(uint32_t *)to = val;
+    *(uint32_t *)to = val;
 }
 
 static inline void hugemem_write_block(hugemem_ptr_t to, const void *from,
-		size_t size)
+        size_t size)
 {
-	memcpy(to, from, size);
+    memcpy(to, from, size);
 }
 
-//@}
+/*@}*/
 
 #endif /* GENERIC_HUGEMEM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h
index f8395022f90a..68b7eefbb6c7 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/hugemem/hugemem.h
@@ -138,6 +138,6 @@
  * address \a to.
  */
 
-//@}
+/*@}*/
 
 #endif /* HUGEMEM_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h
index ed8db27cccce..a26ffeb950e4 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/ioport.h
@@ -84,45 +84,45 @@ extern "C" {
 
 /** \brief IOPORT pin directions */
 enum ioport_direction {
-	IOPORT_DIR_INPUT,  /*!< IOPORT input direction */
-	IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */
+    IOPORT_DIR_INPUT,  /*!< IOPORT input direction */
+    IOPORT_DIR_OUTPUT, /*!< IOPORT output direction */
 };
 
 /** \brief IOPORT levels */
 enum ioport_value {
-	IOPORT_PIN_LEVEL_LOW,  /*!< IOPORT pin value low */
-	IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */
+    IOPORT_PIN_LEVEL_LOW,  /*!< IOPORT pin value low */
+    IOPORT_PIN_LEVEL_HIGH, /*!< IOPORT pin value high */
 };
 
 #if MEGA_RF
 /** \brief IOPORT edge sense modes */
 enum ioport_sense {
-	IOPORT_SENSE_LEVEL,     /*!< IOPORT sense low level  */
-	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
-	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
-	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+    IOPORT_SENSE_LEVEL,     /*!< IOPORT sense low level  */
+    IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+    IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+    IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
 };
 #elif SAM && !SAM4L
 /** \brief IOPORT edge sense modes */
 enum ioport_sense {
-	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
-	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
-	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
-	IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level  */
-	IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level  */
+    IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+    IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+    IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+    IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level  */
+    IOPORT_SENSE_LEVEL_HIGH,/*!< IOPORT sense High level  */
 };
 #elif XMEGA
 enum ioport_sense {
-	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
-	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
-	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
-	IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */
+    IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+    IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+    IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+    IOPORT_SENSE_LEVEL_LOW, /*!< IOPORT sense low level */
 };
 #else
 enum ioport_sense {
-	IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
-	IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
-	IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
+    IOPORT_SENSE_BOTHEDGES, /*!< IOPORT sense both rising and falling edges */
+    IOPORT_SENSE_RISING,    /*!< IOPORT sense rising edges */
+    IOPORT_SENSE_FALLING,   /*!< IOPORT sense falling edges */
 };
 #endif
 
@@ -154,7 +154,7 @@ enum ioport_sense {
  */
 static inline void ioport_init(void)
 {
-	arch_ioport_init();
+    arch_ioport_init();
 }
 
 /**
@@ -165,7 +165,7 @@ static inline void ioport_init(void)
  */
 static inline void ioport_enable_pin(ioport_pin_t pin)
 {
-	arch_ioport_enable_pin(pin);
+    arch_ioport_enable_pin(pin);
 }
 
 /**
@@ -175,9 +175,9 @@ static inline void ioport_enable_pin(ioport_pin_t pin)
  * \param mask Mask of pins within the port to enable
  */
 static inline void ioport_enable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_enable_port(port, mask);
+    arch_ioport_enable_port(port, mask);
 }
 
 /**
@@ -188,7 +188,7 @@ static inline void ioport_enable_port(ioport_port_t port,
  */
 static inline void ioport_disable_pin(ioport_pin_t pin)
 {
-	arch_ioport_disable_pin(pin);
+    arch_ioport_disable_pin(pin);
 }
 
 /**
@@ -198,9 +198,9 @@ static inline void ioport_disable_pin(ioport_pin_t pin)
  * \param mask Pin mask of pins to disable
  */
 static inline void ioport_disable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_disable_port(port, mask);
+    arch_ioport_disable_port(port, mask);
 }
 
 /**
@@ -213,9 +213,9 @@ static inline void ioport_disable_port(ioport_port_t port,
  * ioport_modes)
  */
 static inline void ioport_set_port_mode(ioport_port_t port,
-		ioport_port_mask_t mask, ioport_mode_t mode)
+        ioport_port_mask_t mask, ioport_mode_t mode)
 {
-	arch_ioport_set_port_mode(port, mask, mode);
+    arch_ioport_set_port_mode(port, mask, mode);
 }
 
 /**
@@ -226,7 +226,7 @@ static inline void ioport_set_port_mode(ioport_port_t port,
  */
 static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)
 {
-	arch_ioport_set_pin_mode(pin, mode);
+    arch_ioport_set_pin_mode(pin, mode);
 }
 
 /**
@@ -236,9 +236,9 @@ static inline void ioport_set_pin_mode(ioport_pin_t pin, ioport_mode_t mode)
  * \param mask Mask of pins whose mode configuration is to be reset
  */
 static inline void ioport_reset_port_mode(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_set_port_mode(port, mask, 0);
+    arch_ioport_set_port_mode(port, mask, 0);
 }
 
 /**
@@ -248,7 +248,7 @@ static inline void ioport_reset_port_mode(ioport_port_t port,
  */
 static inline void ioport_reset_pin_mode(ioport_pin_t pin)
 {
-	arch_ioport_set_pin_mode(pin, 0);
+    arch_ioport_set_pin_mode(pin, 0);
 }
 
 /**
@@ -259,9 +259,9 @@ static inline void ioport_reset_pin_mode(ioport_pin_t pin)
  * \param dir Direction to set for the specified pins (\ref ioport_direction)
  */
 static inline void ioport_set_port_dir(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_direction dir)
+        ioport_port_mask_t mask, enum ioport_direction dir)
 {
-	arch_ioport_set_port_dir(port, mask, dir);
+    arch_ioport_set_port_dir(port, mask, dir);
 }
 
 /**
@@ -271,9 +271,9 @@ static inline void ioport_set_port_dir(ioport_port_t port,
  * \param dir Direction to set for the specified pin (\ref ioport_direction)
  */
 static inline void ioport_set_pin_dir(ioport_pin_t pin,
-		enum ioport_direction dir)
+        enum ioport_direction dir)
 {
-	arch_ioport_set_pin_dir(pin, dir);
+    arch_ioport_set_pin_dir(pin, dir);
 }
 
 /**
@@ -284,7 +284,7 @@ static inline void ioport_set_pin_dir(ioport_pin_t pin,
  */
 static inline void ioport_set_pin_level(ioport_pin_t pin, bool level)
 {
-	arch_ioport_set_pin_level(pin, level);
+    arch_ioport_set_pin_level(pin, level);
 }
 
 /**
@@ -296,9 +296,9 @@ static inline void ioport_set_pin_level(ioport_pin_t pin, bool level)
  * \param level Level of the pins to be modified
  */
 static inline void ioport_set_port_level(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_value level)
+        ioport_port_mask_t mask, enum ioport_value level)
 {
-	arch_ioport_set_port_level(port, mask, level);
+    arch_ioport_set_port_level(port, mask, level);
 }
 
 /**
@@ -310,7 +310,7 @@ static inline void ioport_set_port_level(ioport_port_t port,
  */
 static inline bool ioport_get_pin_level(ioport_pin_t pin)
 {
-	return arch_ioport_get_pin_level(pin);
+    return arch_ioport_get_pin_level(pin);
 }
 
 /**
@@ -323,9 +323,9 @@ static inline bool ioport_get_pin_level(ioport_pin_t pin)
  * a mask.
  */
 static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	return arch_ioport_get_port_level(port, mask);
+    return arch_ioport_get_port_level(port, mask);
 }
 
 /**
@@ -336,7 +336,7 @@ static inline ioport_port_mask_t ioport_get_port_level(ioport_pin_t port,
  */
 static inline void ioport_toggle_pin_level(ioport_pin_t pin)
 {
-	arch_ioport_toggle_pin_level(pin);
+    arch_ioport_toggle_pin_level(pin);
 }
 
 /**
@@ -346,9 +346,9 @@ static inline void ioport_toggle_pin_level(ioport_pin_t pin)
  * \param mask Pin mask of pins to toggle
  */
 static inline void ioport_toggle_port_level(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_toggle_port_level(port, mask);
+    arch_ioport_toggle_port_level(port, mask);
 }
 
 /**
@@ -358,9 +358,9 @@ static inline void ioport_toggle_port_level(ioport_port_t port,
  * \param pin_sense Edge to sense for the pin (\ref ioport_sense)
  */
 static inline void ioport_set_pin_sense_mode(ioport_pin_t pin,
-		enum ioport_sense pin_sense)
+        enum ioport_sense pin_sense)
 {
-	arch_ioport_set_pin_sense_mode(pin, pin_sense);
+    arch_ioport_set_pin_sense_mode(pin, pin_sense);
 }
 
 /**
@@ -371,10 +371,10 @@ static inline void ioport_set_pin_sense_mode(ioport_pin_t pin,
  * \param pin_sense Edge to sense for the pins (\ref ioport_sense)
  */
 static inline void ioport_set_port_sense_mode(ioport_port_t port,
-		ioport_port_mask_t mask,
-		enum ioport_sense pin_sense)
+        ioport_port_mask_t mask,
+        enum ioport_sense pin_sense)
 {
-	arch_ioport_set_port_sense_mode(port, mask, pin_sense);
+    arch_ioport_set_port_sense_mode(port, mask, pin_sense);
 }
 
 /**
@@ -385,7 +385,7 @@ static inline void ioport_set_port_sense_mode(ioport_port_t port,
  */
 static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin)
 {
-	return arch_ioport_pin_to_port_id(pin);
+    return arch_ioport_pin_to_port_id(pin);
 }
 
 /**
@@ -396,7 +396,7 @@ static inline ioport_port_t ioport_pin_to_port_id(ioport_pin_t pin)
  */
 static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
 {
-	return arch_ioport_pin_to_mask(pin);
+    return arch_ioport_pin_to_mask(pin);
 }
 
 /** @} */
@@ -420,14 +420,14 @@ static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
  *
  * \subsection ioport_quickstart_basic_setup_code Example code
  * \code
-	 #define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
-	 #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+     #define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
+     #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
 
-	 ioport_init();
+     ioport_init();
 
-	 ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);
-	 ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);
-	 ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);
+     ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);
+     ioport_set_pin_dir(MY_BUTTON, IOPORT_DIR_INPUT);
+     ioport_set_pin_mode(MY_BUTTON, IOPORT_MODE_PULLUP);
 \endcode
  *
  * \subsection ioport_quickstart_basic_setup_flow Workflow
@@ -435,8 +435,8 @@ static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
  *    the \ref IOPORT_CREATE_PIN macro. We define one for a LED and one for a
  *    button.
  *   - \code
-	#define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
-	#define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
+    #define MY_LED    IOPORT_CREATE_PIN(PORTA, 5)
+    #define MY_BUTTON IOPORT_CREATE_PIN(PORTA, 6)
 \endcode
  *   - \note The usefulness of the \ref IOPORT_CREATE_PIN macro and port names
  *           differ between architectures:
@@ -462,10 +462,10 @@ static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
  *
  * \subsection ioport_quickstart_basic_usage_code Example code
  * \code
-	 bool value;
+     bool value;
 
-	 value = ioport_get_pin_level(MY_BUTTON);
-	 ioport_set_pin_level(MY_LED, value);
+     value = ioport_get_pin_level(MY_BUTTON);
+     ioport_set_pin_level(MY_LED, value);
 \endcode
  *
  * \subsection ioport_quickstart_basic_usage_flow Workflow
@@ -490,21 +490,21 @@ static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
  *
  * \subsection ioport_quickstart_use_case_1_setup_code Example code
  * \code
-	 #define IN_PORT  IOPORT_PORTA
-	 #define OUT_PORT IOPORT_PORTB
-	 #define MASK     0x00000060
+     #define IN_PORT  IOPORT_PORTA
+     #define OUT_PORT IOPORT_PORTB
+     #define MASK     0x00000060
 
-	 ioport_init();
+     ioport_init();
 
-	 ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);
-	 ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);
+     ioport_set_port_dir(IN_PORT, MASK, IOPORT_DIR_INPUT);
+     ioport_set_port_dir(OUT_PORT, MASK, IOPORT_DIR_OUTPUT);
 \endcode
  *
  * \subsection ioport_quickstart_basic_setup_flow Workflow
  * -# It's useful to give the ports symbolic names:
  *   - \code
-	#define IN_PORT  IOPORT_PORTA
-	#define OUT_PORT IOPORT_PORTB
+    #define IN_PORT  IOPORT_PORTA
+    #define OUT_PORT IOPORT_PORTB
 \endcode
  *   - \note The port names differ between architectures:
  *     - MEGA_RF, MEGA and XMEGA: There are predefined names for ports: IOPORT_PORTA,
@@ -526,10 +526,10 @@ static inline ioport_port_mask_t ioport_pin_to_mask(ioport_pin_t pin)
  *
  * \subsection ioport_quickstart_basic_usage_code Example code
  * \code
-	 ioport_port_mask_t value;
+     ioport_port_mask_t value;
 
-	 value = ioport_get_port_level(IN_PORT, MASK);
-	 ioport_set_port_level(OUT_PORT, MASK, value);
+     value = ioport_get_port_level(IN_PORT, MASK);
+     ioport_set_port_level(OUT_PORT, MASK, value);
 \endcode
  *
  * \subsection ioport_quickstart_basic_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h
index 6f3cbd7f7b46..fa6cdc5e2e0f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_gpio.h
@@ -50,7 +50,7 @@
 
 #define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin))
 
-// Aliases
+/* Aliases*/
 #define IOPORT_GPIOA     0
 #define IOPORT_GPIOB     1
 #define IOPORT_GPIOC     2
@@ -98,210 +98,225 @@ typedef uint32_t ioport_port_mask_t;
 
 __always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
 {
-	return pin >> 5;
+    return pin >> 5;
 }
 
 __always_inline static volatile GpioPort *arch_ioport_port_to_base(
-		ioport_port_t port)
+        ioport_port_t port)
 {
-	return (volatile GpioPort *)(GPIO_ADDR
-		+ port * sizeof(GpioPort));
+    return (volatile GpioPort *)(GPIO_ADDR
+        + port * sizeof(GpioPort));
 }
 
 __always_inline static volatile GpioPort *arch_ioport_pin_to_base(ioport_pin_t pin)
 {
-	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+    return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
 }
 
 __always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
 {
-	return 1U << (pin & 0x1F);
+    return 1U << (pin & 0x1F);
 }
 
 __always_inline static void arch_ioport_init(void)
 {
-	sysclk_enable_peripheral_clock(GPIO);
+    sysclk_enable_peripheral_clock(GPIO);
 }
 
 __always_inline static void arch_ioport_enable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->GPIO_GPERS = mask;
+    arch_ioport_port_to_base(port)->GPIO_GPERS = mask;
 }
 
 __always_inline static void arch_ioport_disable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->GPIO_GPERC = mask;
+    arch_ioport_port_to_base(port)->GPIO_GPERC = mask;
 }
 
 __always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
 {
-	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 __always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
 {
-	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 __always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
-		ioport_port_mask_t mask, ioport_mode_t mode)
+        ioport_port_mask_t mask, ioport_mode_t mode)
 {
-	volatile GpioPort *base = arch_ioport_port_to_base(port);
+    volatile GpioPort *base = arch_ioport_port_to_base(port);
 
-	if (mode & IOPORT_MODE_PULLUP) {
-		base->GPIO_PUERS = mask;
-	} else {
-		base->GPIO_PUERC = mask;
-	}
+    if (mode & IOPORT_MODE_PULLUP)
+    {
+        base->GPIO_PUERS = mask;
+    } else {
+        base->GPIO_PUERC = mask;
+    }
 
 #ifdef IOPORT_MODE_PULLDOWN
-	if (mode & IOPORT_MODE_PULLDOWN) {
-		base->GPIO_PDERS = mask;
-	} else {
-		base->GPIO_PDERC = mask;
-	}
+    if (mode & IOPORT_MODE_PULLDOWN)
+    {
+        base->GPIO_PDERS = mask;
+    } else {
+        base->GPIO_PDERC = mask;
+    }
 #endif
 
-	if (mode & IOPORT_MODE_GLITCH_FILTER) {
-		base->GPIO_GFERS = mask;
-	} else {
-		base->GPIO_GFERC = mask;
-	}
+    if (mode & IOPORT_MODE_GLITCH_FILTER)
+    {
+        base->GPIO_GFERS = mask;
+    } else {
+        base->GPIO_GFERC = mask;
+    }
 
 #ifdef IOPORT_MODE_DRIVE_STRENGTH
-	if (mode & IOPORT_MODE_DRIVE_STRENGTH) {
-		base->GPIO_ODCR0S = mask;
-	} else {
-		base->GPIO_ODCR0C = mask;
-	}
+    if (mode & IOPORT_MODE_DRIVE_STRENGTH)
+    {
+        base->GPIO_ODCR0S = mask;
+    } else {
+        base->GPIO_ODCR0C = mask;
+    }
 #endif
 
-	if (mode & IOPORT_MODE_MUX_BIT0) {
-		base->GPIO_PMR0S = mask;
-	} else {
-		base->GPIO_PMR0C = mask;
-	}
+    if (mode & IOPORT_MODE_MUX_BIT0)
+    {
+        base->GPIO_PMR0S = mask;
+    } else {
+        base->GPIO_PMR0C = mask;
+    }
 
-	if (mode & IOPORT_MODE_MUX_BIT1) {
-		base->GPIO_PMR1S = mask;
-	} else {
-		base->GPIO_PMR1C = mask;
-	}
+    if (mode & IOPORT_MODE_MUX_BIT1)
+    {
+        base->GPIO_PMR1S = mask;
+    } else {
+        base->GPIO_PMR1C = mask;
+    }
 
 #ifdef IOPORT_MODE_MUX_BIT2
-	if (mode & IOPORT_MODE_MUX_BIT2) {
-		base->GPIO_PMR2S = mask;
-	} else {
-		base->GPIO_PMR2C = mask;
-	}
+    if (mode & IOPORT_MODE_MUX_BIT2)
+    {
+        base->GPIO_PMR2S = mask;
+    } else {
+        base->GPIO_PMR2C = mask;
+    }
 #endif
 }
 
 __always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
-		ioport_mode_t mode)
+        ioport_mode_t mode)
 {
-	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), mode);
+    arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), mode);
 }
 
 __always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
-		ioport_port_mask_t mask, unsigned char group_direction)
+        ioport_port_mask_t mask, unsigned char group_direction)
 {
-	if (group_direction == IOPORT_DIR_OUTPUT) {
-		arch_ioport_port_to_base(port)->GPIO_ODERS = mask;
-		// Always disable the Schmitt trigger for output pins.
-		arch_ioport_port_to_base(port)->GPIO_STERC = mask;
-	} else if (group_direction == IOPORT_DIR_INPUT) {
-		arch_ioport_port_to_base(port)->GPIO_ODERC = mask;
-		// Always enable the Schmitt trigger for input pins.
-		arch_ioport_port_to_base(port)->GPIO_STERS = mask;
-	}
+    if (group_direction == IOPORT_DIR_OUTPUT)
+    {
+        arch_ioport_port_to_base(port)->GPIO_ODERS = mask;
+        /* Always disable the Schmitt trigger for output pins.*/
+        arch_ioport_port_to_base(port)->GPIO_STERC = mask;
+    } else if (group_direction == IOPORT_DIR_INPUT)
+    {
+        arch_ioport_port_to_base(port)->GPIO_ODERC = mask;
+        /* Always enable the Schmitt trigger for input pins.*/
+        arch_ioport_port_to_base(port)->GPIO_STERS = mask;
+    }
 }
 
 __always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
-		enum ioport_direction dir)
+        enum ioport_direction dir)
 {
-	if (dir == IOPORT_DIR_OUTPUT) {
-		arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin);
-		// Always disable the Schmitt trigger for output pins.
-		arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin);
-	} else if (dir == IOPORT_DIR_INPUT) {
-		arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin);
-		// Always enable the Schmitt trigger for input pins.
-		arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin);
-	}
+    if (dir == IOPORT_DIR_OUTPUT)
+    {
+        arch_ioport_pin_to_base(pin)->GPIO_ODERS = arch_ioport_pin_to_mask(pin);
+        /* Always disable the Schmitt trigger for output pins.*/
+        arch_ioport_pin_to_base(pin)->GPIO_STERC = arch_ioport_pin_to_mask(pin);
+    } else if (dir == IOPORT_DIR_INPUT)
+    {
+        arch_ioport_pin_to_base(pin)->GPIO_ODERC = arch_ioport_pin_to_mask(pin);
+        /* Always enable the Schmitt trigger for input pins.*/
+        arch_ioport_pin_to_base(pin)->GPIO_STERS = arch_ioport_pin_to_mask(pin);
+    }
 }
 
 __always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
-		bool level)
+        bool level)
 {
-	if (level) {
-		arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin);
-	} else {
-		arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin);
-	}
+    if (level)
+    {
+        arch_ioport_pin_to_base(pin)->GPIO_OVRS = arch_ioport_pin_to_mask(pin);
+    } else {
+        arch_ioport_pin_to_base(pin)->GPIO_OVRC = arch_ioport_pin_to_mask(pin);
+    }
 }
 
 __always_inline static void arch_ioport_set_port_level(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_value level)
+        ioport_port_mask_t mask, enum ioport_value level)
 {
-	volatile GpioPort *base = arch_ioport_port_to_base(port);
-	if (level){
-		base->GPIO_OVRS = mask;
-	} else{
-		base->GPIO_OVRC = mask;
-	}
+    volatile GpioPort *base = arch_ioport_port_to_base(port);
+    if (level)
+    {
+        base->GPIO_OVRS = mask;
+    } else{
+        base->GPIO_OVRC = mask;
+    }
 }
 
 __always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
 {
-	return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin);
+    return arch_ioport_pin_to_base(pin)->GPIO_PVR & arch_ioport_pin_to_mask(pin);
 }
 
 __always_inline static ioport_port_mask_t arch_ioport_get_port_level(
-		ioport_port_t port, ioport_port_mask_t mask)
+        ioport_port_t port, ioport_port_mask_t mask)
 {
-	return arch_ioport_port_to_base(port)->GPIO_PVR & mask;
+    return arch_ioport_port_to_base(port)->GPIO_PVR & mask;
 }
 
 __always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
 {
-	arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin);
+    arch_ioport_pin_to_base(pin)->GPIO_OVRT = arch_ioport_pin_to_mask(pin);
 }
 
 __always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->GPIO_OVRT = mask;
+    arch_ioport_port_to_base(port)->GPIO_OVRT = mask;
 }
 
 __always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+        ioport_port_mask_t mask, enum ioport_sense pin_sense)
 {
-	volatile GpioPort *base = arch_ioport_port_to_base(port);
-
-	if (pin_sense & 0x01) {
-		base->GPIO_IMR0S = mask;
-	} else {
-		base->GPIO_IMR0C = mask;
-	}
-
-	if (pin_sense & 0x02) {
-		base->GPIO_IMR1S = mask;
-	} else {
-		base->GPIO_IMR1C = mask;
-	}
+    volatile GpioPort *base = arch_ioport_port_to_base(port);
+
+    if (pin_sense & 0x01)
+    {
+        base->GPIO_IMR0S = mask;
+    } else {
+        base->GPIO_IMR0C = mask;
+    }
+
+    if (pin_sense & 0x02)
+    {
+        base->GPIO_IMR1S = mask;
+    } else {
+        base->GPIO_IMR1C = mask;
+    }
 }
 
 __always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
-		enum ioport_sense pin_sense)
+        enum ioport_sense pin_sense)
 {
-	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), pin_sense);
+    arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), pin_sense);
 }
 
 #endif /* IOPORT_SAM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h
index f3005991df07..e6426dd9a633 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam/ioport_pio.h
@@ -106,278 +106,296 @@ typedef uint32_t ioport_port_mask_t;
 
 __always_inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
 {
-	return pin >> 5;
+    return pin >> 5;
 }
 
 __always_inline static Pio *arch_ioport_port_to_base(ioport_port_t port)
 {
 #if (SAM4C || SAM4CM || SAM4CP)
-	if (port == IOPORT_PIOC) {
-		return (Pio *)(uintptr_t)PIOC;
+    if (port == IOPORT_PIOC)
+    {
+        return (Pio *)(uintptr_t)PIOC;
 #  ifdef ID_PIOD
-	} else if (port == IOPORT_PIOD) {
-		return (Pio *)(uintptr_t)PIOD;
+    } else if (port == IOPORT_PIOD)
+    {
+        return (Pio *)(uintptr_t)PIOD;
 #  endif
-	} else {
-		return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
-		       (IOPORT_PIO_OFFSET * port));
-	}
+    } else {
+        return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+               (IOPORT_PIO_OFFSET * port));
+    }
 #else
-	return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
-	       (IOPORT_PIO_OFFSET * port));
+    return (Pio *)((uintptr_t)IOPORT_BASE_ADDRESS +
+           (IOPORT_PIO_OFFSET * port));
 #endif
 }
 
 __always_inline static Pio *arch_ioport_pin_to_base(ioport_pin_t pin)
 {
-	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+    return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
 }
 
 __always_inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
 {
-	return 1U << (pin & 0x1F);
+    return 1U << (pin & 0x1F);
 }
 
 __always_inline static void arch_ioport_init(void)
 {
 #ifdef ID_PIOA
-	sysclk_enable_peripheral_clock(ID_PIOA);
+    sysclk_enable_peripheral_clock(ID_PIOA);
 #endif
 #ifdef ID_PIOB
-	sysclk_enable_peripheral_clock(ID_PIOB);
+    sysclk_enable_peripheral_clock(ID_PIOB);
 #endif
 #ifdef ID_PIOC
-	sysclk_enable_peripheral_clock(ID_PIOC);
+    sysclk_enable_peripheral_clock(ID_PIOC);
 #endif
 #ifdef ID_PIOD
-	sysclk_enable_peripheral_clock(ID_PIOD);
+    sysclk_enable_peripheral_clock(ID_PIOD);
 #endif
 #ifdef ID_PIOE
-	sysclk_enable_peripheral_clock(ID_PIOE);
+    sysclk_enable_peripheral_clock(ID_PIOE);
 #endif
 #ifdef ID_PIOF
-	sysclk_enable_peripheral_clock(ID_PIOF);
+    sysclk_enable_peripheral_clock(ID_PIOF);
 #endif
 }
 
 __always_inline static void arch_ioport_enable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->PIO_PER = mask;
+    arch_ioport_port_to_base(port)->PIO_PER = mask;
 }
 
 __always_inline static void arch_ioport_disable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->PIO_PDR = mask;
+    arch_ioport_port_to_base(port)->PIO_PDR = mask;
 }
 
 __always_inline static void arch_ioport_enable_pin(ioport_pin_t pin)
 {
-	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 __always_inline static void arch_ioport_disable_pin(ioport_pin_t pin)
 {
-	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 __always_inline static void arch_ioport_set_port_mode(ioport_port_t port,
-		ioport_port_mask_t mask, ioport_mode_t mode)
+        ioport_port_mask_t mask, ioport_mode_t mode)
 {
-	Pio *base = arch_ioport_port_to_base(port);
+    Pio *base = arch_ioport_port_to_base(port);
 
-	if (mode & IOPORT_MODE_PULLUP) {
-		base->PIO_PUER = mask;
-	} else {
-		base->PIO_PUDR = mask;
-	}
+    if (mode & IOPORT_MODE_PULLUP)
+    {
+        base->PIO_PUER = mask;
+    } else {
+        base->PIO_PUDR = mask;
+    }
 
 #if defined(IOPORT_MODE_PULLDOWN)
-	if (mode & IOPORT_MODE_PULLDOWN) {
-		base->PIO_PPDER = mask;
-	} else {
-		base->PIO_PPDDR = mask;
-	}
+    if (mode & IOPORT_MODE_PULLDOWN)
+    {
+        base->PIO_PPDER = mask;
+    } else {
+        base->PIO_PPDDR = mask;
+    }
 #endif
 
-	if (mode & IOPORT_MODE_OPEN_DRAIN) {
-		base->PIO_MDER = mask;
-	} else {
-		base->PIO_MDDR = mask;
-	}
-
-	if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE)) {
-		base->PIO_IFER = mask;
-	} else {
-		base->PIO_IFDR = mask;
-	}
-
-	if (mode & IOPORT_MODE_DEBOUNCE) {
+    if (mode & IOPORT_MODE_OPEN_DRAIN)
+    {
+        base->PIO_MDER = mask;
+    } else {
+        base->PIO_MDDR = mask;
+    }
+
+    if (mode & (IOPORT_MODE_GLITCH_FILTER | IOPORT_MODE_DEBOUNCE))
+    {
+        base->PIO_IFER = mask;
+    } else {
+        base->PIO_IFDR = mask;
+    }
+
+    if (mode & IOPORT_MODE_DEBOUNCE)
+    {
 #if SAM3U || SAM3XA
-		base->PIO_DIFSR = mask;
+        base->PIO_DIFSR = mask;
 #else
-		base->PIO_IFSCER = mask;
+        base->PIO_IFSCER = mask;
 #endif
-	} else {
+    } else {
 #if SAM3U || SAM3XA
-		base->PIO_SCIFSR = mask;
+        base->PIO_SCIFSR = mask;
 #else
-		base->PIO_IFSCDR = mask;
+        base->PIO_IFSCDR = mask;
 #endif
-	}
+    }
 
 #if !defined(IOPORT_MODE_MUX_BIT1)
-	if (mode & IOPORT_MODE_MUX_BIT0) {
-		base->PIO_ABSR |= mask;
-	} else {
-		base->PIO_ABSR &= ~mask;
-	}
+    if (mode & IOPORT_MODE_MUX_BIT0)
+    {
+        base->PIO_ABSR |= mask;
+    } else {
+        base->PIO_ABSR &= ~mask;
+    }
 #else
-	if (mode & IOPORT_MODE_MUX_BIT0) {
-		base->PIO_ABCDSR[0] |= mask;
-	} else {
-		base->PIO_ABCDSR[0] &= ~mask;
-	}
-
-	if (mode & IOPORT_MODE_MUX_BIT1) {
-		base->PIO_ABCDSR[1] |= mask;
-	} else {
-		base->PIO_ABCDSR[1] &= ~mask;
-	}
+    if (mode & IOPORT_MODE_MUX_BIT0)
+    {
+        base->PIO_ABCDSR[0] |= mask;
+    } else {
+        base->PIO_ABCDSR[0] &= ~mask;
+    }
+
+    if (mode & IOPORT_MODE_MUX_BIT1)
+    {
+        base->PIO_ABCDSR[1] |= mask;
+    } else {
+        base->PIO_ABCDSR[1] &= ~mask;
+    }
 #endif
 }
 
 __always_inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
-		ioport_mode_t mode)
+        ioport_mode_t mode)
 {
-	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), mode);
+    arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), mode);
 }
 
 __always_inline static void arch_ioport_set_port_dir(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_direction group_direction)
+        ioport_port_mask_t mask, enum ioport_direction group_direction)
 {
-	Pio *base = arch_ioport_port_to_base(port);
+    Pio *base = arch_ioport_port_to_base(port);
 
-	if (group_direction == IOPORT_DIR_OUTPUT) {
-		base->PIO_OER = mask;
-	} else if (group_direction == IOPORT_DIR_INPUT) {
-		base->PIO_ODR = mask;
-	}
+    if (group_direction == IOPORT_DIR_OUTPUT)
+    {
+        base->PIO_OER = mask;
+    } else if (group_direction == IOPORT_DIR_INPUT)
+    {
+        base->PIO_ODR = mask;
+    }
 
-	base->PIO_OWER = mask;
+    base->PIO_OWER = mask;
 }
 
 __always_inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
-		enum ioport_direction dir)
+        enum ioport_direction dir)
 {
-	Pio *base = arch_ioport_pin_to_base(pin);
+    Pio *base = arch_ioport_pin_to_base(pin);
 
-	if (dir == IOPORT_DIR_OUTPUT) {
-		base->PIO_OER = arch_ioport_pin_to_mask(pin);
-	} else if (dir == IOPORT_DIR_INPUT) {
-		base->PIO_ODR = arch_ioport_pin_to_mask(pin);
-	}
+    if (dir == IOPORT_DIR_OUTPUT)
+    {
+        base->PIO_OER = arch_ioport_pin_to_mask(pin);
+    } else if (dir == IOPORT_DIR_INPUT)
+    {
+        base->PIO_ODR = arch_ioport_pin_to_mask(pin);
+    }
 
-	base->PIO_OWER = arch_ioport_pin_to_mask(pin);
+    base->PIO_OWER = arch_ioport_pin_to_mask(pin);
 }
 
 __always_inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
-		bool level)
+        bool level)
 {
-	Pio *base = arch_ioport_pin_to_base(pin);
-
-	if (level) {
-		base->PIO_SODR = arch_ioport_pin_to_mask(pin);
-	} else {
-		base->PIO_CODR = arch_ioport_pin_to_mask(pin);
-	}
+    Pio *base = arch_ioport_pin_to_base(pin);
+
+    if (level)
+    {
+        base->PIO_SODR = arch_ioport_pin_to_mask(pin);
+    } else {
+        base->PIO_CODR = arch_ioport_pin_to_mask(pin);
+    }
 }
 
 __always_inline static void arch_ioport_set_port_level(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_value level)
+        ioport_port_mask_t mask, enum ioport_value level)
 {
-	Pio *base = arch_ioport_port_to_base(port);
-
-	if (level){
-		base->PIO_SODR = mask;
-	} else {
-		base->PIO_CODR = mask;
-	}
+    Pio *base = arch_ioport_port_to_base(port);
+
+    if (level)
+    {
+        base->PIO_SODR = mask;
+    } else {
+        base->PIO_CODR = mask;
+    }
 }
 
 __always_inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
 {
-	return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin);
+    return arch_ioport_pin_to_base(pin)->PIO_PDSR & arch_ioport_pin_to_mask(pin);
 }
 
 __always_inline static ioport_port_mask_t arch_ioport_get_port_level(
-		ioport_port_t port, ioport_port_mask_t mask)
+        ioport_port_t port, ioport_port_mask_t mask)
 {
-	return arch_ioport_port_to_base(port)->PIO_PDSR & mask;
+    return arch_ioport_port_to_base(port)->PIO_PDSR & mask;
 }
 
 __always_inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
 {
-	Pio *port = arch_ioport_pin_to_base(pin);
-	ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin);
-
-	if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin)) {
-		port->PIO_CODR = mask;
-	} else {
-		port->PIO_SODR = mask;
-	}
+    Pio *port = arch_ioport_pin_to_base(pin);
+    ioport_port_mask_t mask = arch_ioport_pin_to_mask(pin);
+
+    if (port->PIO_PDSR & arch_ioport_pin_to_mask(pin))
+    {
+        port->PIO_CODR = mask;
+    } else {
+        port->PIO_SODR = mask;
+    }
 }
 
 __always_inline static void arch_ioport_toggle_port_level(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->PIO_ODSR ^= mask;
+    arch_ioport_port_to_base(port)->PIO_ODSR ^= mask;
 }
 
 __always_inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+        ioport_port_mask_t mask, enum ioport_sense pin_sense)
 {
-	Pio *base = arch_ioport_port_to_base(port);
-	/*   AIMMR    ELSR    FRLHSR
-	 *       0       X         X    IOPORT_SENSE_BOTHEDGES (Default)
-	 *       1       0         0    IOPORT_SENSE_FALLING
-	 *       1       0         1    IOPORT_SENSE_RISING
-	 *       1       1         0    IOPORT_SENSE_LEVEL_LOW
-	 *       1       1         1    IOPORT_SENSE_LEVEL_HIGH
-	 */
-	switch(pin_sense) {
-	case IOPORT_SENSE_LEVEL_LOW:
-		base->PIO_LSR = mask;
-		base->PIO_FELLSR = mask;
-		break;
-	case IOPORT_SENSE_LEVEL_HIGH:
-		base->PIO_LSR = mask;
-		base->PIO_REHLSR = mask;
-		break;
-	case IOPORT_SENSE_FALLING:
-		base->PIO_ESR = mask;
-		base->PIO_FELLSR = mask;
-		break;
-	case IOPORT_SENSE_RISING:
-		base->PIO_ESR = mask;
-		base->PIO_REHLSR = mask;
-		break;
-	default:
-		base->PIO_AIMDR = mask;
-		return;
-	}
-	base->PIO_AIMER = mask;
+    Pio *base = arch_ioport_port_to_base(port);
+    /*   AIMMR    ELSR    FRLHSR
+     *       0       X         X    IOPORT_SENSE_BOTHEDGES (Default)
+     *       1       0         0    IOPORT_SENSE_FALLING
+     *       1       0         1    IOPORT_SENSE_RISING
+     *       1       1         0    IOPORT_SENSE_LEVEL_LOW
+     *       1       1         1    IOPORT_SENSE_LEVEL_HIGH
+     */
+    switch(pin_sense)
+    {
+    case IOPORT_SENSE_LEVEL_LOW:
+        base->PIO_LSR = mask;
+        base->PIO_FELLSR = mask;
+        break;
+    case IOPORT_SENSE_LEVEL_HIGH:
+        base->PIO_LSR = mask;
+        base->PIO_REHLSR = mask;
+        break;
+    case IOPORT_SENSE_FALLING:
+        base->PIO_ESR = mask;
+        base->PIO_FELLSR = mask;
+        break;
+    case IOPORT_SENSE_RISING:
+        base->PIO_ESR = mask;
+        base->PIO_REHLSR = mask;
+        break;
+    default:
+        base->PIO_AIMDR = mask;
+        return;
+    }
+    base->PIO_AIMER = mask;
 }
 
 __always_inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
-		enum ioport_sense pin_sense)
+        enum ioport_sense pin_sense)
 {
-	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), pin_sense);
+    arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), pin_sense);
 }
 
 #endif /* IOPORT_SAM_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h
index 07d44ad7d460..6fe208837f07 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/ioport/sam0/ioport.h
@@ -50,7 +50,7 @@
 
 #define IOPORT_CREATE_PIN(port, pin) ((port) * 32 + (pin))
 
-// Aliases
+/* Aliases*/
 #if (PORT_GROUPS > 0)
 #  define IOPORT_PORTA     0
 #endif
@@ -104,202 +104,217 @@ typedef uint32_t ioport_port_mask_t;
 
 inline static ioport_port_t arch_ioport_pin_to_port_id(ioport_pin_t pin)
 {
-	return pin >> 5;
+    return pin >> 5;
 }
 
 inline static PortGroup *arch_ioport_port_to_base(
-		ioport_port_t port)
+        ioport_port_t port)
 {
-	return &PORT->Group[port];
+    return &PORT->Group[port];
 }
 
 inline static PortGroup *arch_ioport_pin_to_base(ioport_pin_t pin)
 {
-	return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
+    return arch_ioport_port_to_base(arch_ioport_pin_to_port_id(pin));
 }
 
 inline static ioport_port_mask_t arch_ioport_pin_to_mask(ioport_pin_t pin)
 {
-	return 1U << (pin & 0x1F);
+    return 1U << (pin & 0x1F);
 }
 
 inline static void arch_ioport_init(void)
 {
-	/* No implementation for SAM0 */
+    /* No implementation for SAM0 */
 }
 
 
 inline static void arch_ioport_enable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	volatile PortGroup *base = arch_ioport_port_to_base(port);
-
-	for (uint32_t i = 0; i < 32; i++) {
-		if (mask & (1 << i)) {
-			base->PINCFG[i].reg &= ~PORT_PINCFG_PMUXEN;
-		}
-	}
+    volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+    for (uint32_t i = 0; i < 32; i++)
+    {
+        if (mask & (1 << i))
+        {
+            base->PINCFG[i].reg &= ~PORT_PINCFG_PMUXEN;
+        }
+    }
 }
 
 inline static void arch_ioport_disable_port(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	volatile PortGroup *base = arch_ioport_port_to_base(port);
-
-	for (uint32_t i = 0; i < 32; i++) {
-		if (mask & (1 << i)) {
-			base->PINCFG[i].reg |= PORT_PINCFG_PMUXEN;
-		}
-	}
+    volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+    for (uint32_t i = 0; i < 32; i++)
+    {
+        if (mask & (1 << i))
+        {
+            base->PINCFG[i].reg |= PORT_PINCFG_PMUXEN;
+        }
+    }
 }
 
 inline static void arch_ioport_enable_pin(ioport_pin_t pin)
 {
-	arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_enable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 inline static void arch_ioport_disable_pin(ioport_pin_t pin)
 {
-	arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin));
+    arch_ioport_disable_port(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin));
 }
 
 inline static void arch_ioport_set_port_mode(ioport_port_t port,
-		ioport_port_mask_t mask, ioport_mode_t mode)
+        ioport_port_mask_t mask, ioport_mode_t mode)
 {
-	PortGroup *base = arch_ioport_port_to_base(port);
+    PortGroup *base = arch_ioport_port_to_base(port);
 
-	uint32_t config_mask = 0;
-	uint32_t config_mux  = 0;
+    uint32_t config_mask = 0;
+    uint32_t config_mux  = 0;
 
-	config_mask |= PORT_WRCONFIG_INEN;
+    config_mask |= PORT_WRCONFIG_INEN;
 
-	if ((mode & IOPORT_MODE_PULLDOWN) || (mode & IOPORT_MODE_PULLUP)) {
-		config_mask |= PORT_WRCONFIG_PULLEN;
-	}
+    if ((mode & IOPORT_MODE_PULLDOWN) || (mode & IOPORT_MODE_PULLUP))
+    {
+        config_mask |= PORT_WRCONFIG_PULLEN;
+    }
 
 #ifdef PORT_WRCONFIG_ODRAIN
-	if (mode & IOPORT_MODE_OPEN_DRAIN) {
-		config_mask |= PORT_WRCONFIG_ODRAIN;
-	}
+    if (mode & IOPORT_MODE_OPEN_DRAIN)
+    {
+        config_mask |= PORT_WRCONFIG_ODRAIN;
+    }
 #endif
 
-	if (mode & IOPORT_MODE_DRIVE_STRENGTH) {
-		config_mask |= PORT_WRCONFIG_DRVSTR;
-	}
-
-	config_mux = (mode & IOPORT_MODE_MUX_MASK) << PORT_WRCONFIG_PMUX_Pos;
-
-	uint32_t lower_pin_mask = (mask & 0xFFFF);
-	uint32_t upper_pin_mask = (mask >> 16);
-
-	base->WRCONFIG.reg =
-			(lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			config_mask | config_mux |
-			PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
-
-	base->WRCONFIG.reg =
-			(upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			config_mask | config_mux |
-			PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
-			PORT_WRCONFIG_HWSEL;
-
-	if (mode & IOPORT_MODE_PULLDOWN) {
-		base->OUTCLR.reg = mask;
-	}
-	else if (mode & IOPORT_MODE_PULLUP) {
-		base->OUTSET.reg = mask;
-	}
+    if (mode & IOPORT_MODE_DRIVE_STRENGTH)
+    {
+        config_mask |= PORT_WRCONFIG_DRVSTR;
+    }
+
+    config_mux = (mode & IOPORT_MODE_MUX_MASK) << PORT_WRCONFIG_PMUX_Pos;
+
+    uint32_t lower_pin_mask = (mask & 0xFFFF);
+    uint32_t upper_pin_mask = (mask >> 16);
+
+    base->WRCONFIG.reg =
+            (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+            config_mask | config_mux |
+            PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+
+    base->WRCONFIG.reg =
+            (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+            config_mask | config_mux |
+            PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+            PORT_WRCONFIG_HWSEL;
+
+    if (mode & IOPORT_MODE_PULLDOWN)
+    {
+        base->OUTCLR.reg = mask;
+    }
+    else if (mode & IOPORT_MODE_PULLUP)
+    {
+        base->OUTSET.reg = mask;
+    }
 }
 
 inline static void arch_ioport_set_pin_mode(ioport_pin_t pin,
-		ioport_mode_t mode)
+        ioport_mode_t mode)
 {
-	arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), mode);
+    arch_ioport_set_port_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), mode);
 }
 
 inline static void arch_ioport_set_port_dir(ioport_port_t port,
-		ioport_port_mask_t mask, unsigned char dir)
+        ioport_port_mask_t mask, unsigned char dir)
 {
-	if (dir == IOPORT_DIR_OUTPUT) {
-		arch_ioport_port_to_base(port)->DIRSET.reg = mask;
-	} else if (dir == IOPORT_DIR_INPUT) {
-		arch_ioport_port_to_base(port)->DIRCLR.reg = mask;
-	}
+    if (dir == IOPORT_DIR_OUTPUT)
+    {
+        arch_ioport_port_to_base(port)->DIRSET.reg = mask;
+    } else if (dir == IOPORT_DIR_INPUT)
+    {
+        arch_ioport_port_to_base(port)->DIRCLR.reg = mask;
+    }
 }
 
 inline static void arch_ioport_set_pin_dir(ioport_pin_t pin,
-		enum ioport_direction dir)
+        enum ioport_direction dir)
 {
-	PortGroup *base = arch_ioport_pin_to_base(pin);
+    PortGroup *base = arch_ioport_pin_to_base(pin);
 
-	if (dir == IOPORT_DIR_OUTPUT) {
-		base->DIRSET.reg = arch_ioport_pin_to_mask(pin);
-	} else if (dir == IOPORT_DIR_INPUT) {
-		base->DIRCLR.reg = arch_ioport_pin_to_mask(pin);
-	}
+    if (dir == IOPORT_DIR_OUTPUT)
+    {
+        base->DIRSET.reg = arch_ioport_pin_to_mask(pin);
+    } else if (dir == IOPORT_DIR_INPUT)
+    {
+        base->DIRCLR.reg = arch_ioport_pin_to_mask(pin);
+    }
 
-	base->PINCFG[pin].reg |= PORT_PINCFG_INEN;
+    base->PINCFG[pin].reg |= PORT_PINCFG_INEN;
 }
 
 inline static void arch_ioport_set_pin_level(ioport_pin_t pin,
-		bool level)
+        bool level)
 {
-	if (level) {
-		arch_ioport_pin_to_base(pin)->OUTSET.reg = arch_ioport_pin_to_mask(pin);
-	} else {
-		arch_ioport_pin_to_base(pin)->OUTCLR.reg = arch_ioport_pin_to_mask(pin);
-	}
+    if (level)
+    {
+        arch_ioport_pin_to_base(pin)->OUTSET.reg = arch_ioport_pin_to_mask(pin);
+    } else {
+        arch_ioport_pin_to_base(pin)->OUTCLR.reg = arch_ioport_pin_to_mask(pin);
+    }
 }
 
 inline static void arch_ioport_set_port_level(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_value level)
+        ioport_port_mask_t mask, enum ioport_value level)
 {
-	volatile PortGroup *base = arch_ioport_port_to_base(port);
-
-	if (level){
-		base->OUTSET.reg = mask;
-	} else {
-		base->OUTCLR.reg = mask;
-	}
+    volatile PortGroup *base = arch_ioport_port_to_base(port);
+
+    if (level)
+    {
+        base->OUTSET.reg = mask;
+    } else {
+        base->OUTCLR.reg = mask;
+    }
 }
 
 inline static bool arch_ioport_get_pin_level(ioport_pin_t pin)
 {
-	return arch_ioport_pin_to_base(pin)->IN.reg & arch_ioport_pin_to_mask(pin);
+    return arch_ioport_pin_to_base(pin)->IN.reg & arch_ioport_pin_to_mask(pin);
 }
 
 inline static ioport_port_mask_t arch_ioport_get_port_level(
-		ioport_port_t port, ioport_port_mask_t mask)
+        ioport_port_t port, ioport_port_mask_t mask)
 {
-	return arch_ioport_port_to_base(port)->IN.reg & mask;
+    return arch_ioport_port_to_base(port)->IN.reg & mask;
 }
 
 inline static void arch_ioport_toggle_pin_level(ioport_pin_t pin)
 {
-	arch_ioport_pin_to_base(pin)->OUTTGL.reg = arch_ioport_pin_to_mask(pin);
+    arch_ioport_pin_to_base(pin)->OUTTGL.reg = arch_ioport_pin_to_mask(pin);
 }
 
 inline static void arch_ioport_toggle_port_level(ioport_port_t port,
-		ioport_port_mask_t mask)
+        ioport_port_mask_t mask)
 {
-	arch_ioport_port_to_base(port)->OUTTGL.reg = mask;
+    arch_ioport_port_to_base(port)->OUTTGL.reg = mask;
 }
 
 inline static void arch_ioport_set_port_sense_mode(ioport_port_t port,
-		ioport_port_mask_t mask, enum ioport_sense pin_sense)
+        ioport_port_mask_t mask, enum ioport_sense pin_sense)
 {
-	// TODO
-	Assert(false);
+    /* TODO*/
+    Assert(false);
 }
 
 inline static void arch_ioport_set_pin_sense_mode(ioport_pin_t pin,
-		enum ioport_sense pin_sense)
+        enum ioport_sense pin_sense)
 {
-	arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
-			arch_ioport_pin_to_mask(pin), pin_sense);
+    arch_ioport_set_port_sense_mode(arch_ioport_pin_to_port_id(pin),
+            arch_ioport_pin_to_mask(pin), pin_sense);
 }
 
 #endif /* IOPORT_SAM0_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h
index 64a49b985d2a..d678250ef044 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/flip_protocol.h
@@ -61,12 +61,12 @@ extern "C" {
  * @{
  */
 
-//! \defgroup FLIP Protocol versions
-//@{
-#define  FLIP_PROTOCOL_VERSION_2     2 // Used by UC3 parts and Xmega parts
-#define  FLIP_PROTOCOL_VERSION_1     1 // Used by Mega
-#define  FLIP_PROTOCOL_VERSION_0     0 // Used by C51 parts
-//@}
+/*! \defgroup FLIP Protocol versions*/
+/*@{*/
+#define  FLIP_PROTOCOL_VERSION_2     2 /* Used by UC3 parts and Xmega parts*/
+#define  FLIP_PROTOCOL_VERSION_1     1 /* Used by Mega*/
+#define  FLIP_PROTOCOL_VERSION_0     0 /* Used by C51 parts*/
+/*@}*/
 
 
 /**
@@ -82,73 +82,73 @@ COMPILER_PACK_SET(1)
  * \brief FLIP message structure
  */
 typedef struct {
-	uint8_t cmd_id;
-	uint8_t arg[5];
+    uint8_t cmd_id;
+    uint8_t arg[5];
 } flip_msg_v1_t;
 COMPILER_PACK_RESET()
 
-//! Size of buffer used by FLIP to receive or send data
+/*! Size of buffer used by FLIP to receive or send data*/
 #define  FLIP_V1_BUF_TRANS_SIZE  1024
 
-//! \name FLIP commands
-//@{
+/*! \name FLIP commands*/
+/*@{*/
 #define  FLIP_V1_CMD_PROG_START            0x01
 #define  FLIP_V1_CMD_READ                  0x03
 #define  FLIP_V1_CMD_WRITE                 0x04
 #define  FLIP_V1_CMD_READ_ID               0x05
 #define  FLIP_V1_CMD_CHANGE_BASE_ADDR      0x06
 
-//! \name FLIP_V1_CMD_PROG_START first argument
-//@{
+/*! \name FLIP_V1_CMD_PROG_START first argument*/
+/*@{*/
 #define FLIP_V1_CMD_PROG_START_ARG_FLASH   0x00
 #define FLIP_V1_CMD_PROG_START_ARG_EEPROM  0x01
 #define FLIP_V1_CMD_PROG_START_ARG_CUSTOM  0x08
-//@}
+/*@}*/
 
-//! \name FLIP_V1_CMD_READ first argument
-//@{
+/*! \name FLIP_V1_CMD_READ first argument*/
+/*@{*/
 #define FLIP_V1_CMD_READ_ARG_FLASH      0x00
 #define FLIP_V1_CMD_READ_ARG_FLASHCHECK 0x01
 #define FLIP_V1_CMD_READ_ARG_EEPROM     0x02
 #define FLIP_V1_CMD_READ_ARG_CUSTOM     0x03
-//@}
+/*@}*/
 
-//! \name FLIP_V1_CMD_WRITE first argument
-//@{
+/*! \name FLIP_V1_CMD_WRITE first argument*/
+/*@{*/
 #define FLIP_V1_CMD_WRITE_ARG_ERASE     0x00
 #define FLIP_V1_CMD_WRITE_ARG_RST       0x03
-//! \name FLIP_V1_CMD_WRITE_ARG_ERASE following argument
-//@{
+/*! \name FLIP_V1_CMD_WRITE_ARG_ERASE following argument*/
+/*@{*/
 #define FLIP_V1_CMD_WRITE_ARG_ERASE_CHIP 0xFF
-//@}
-//! \name FLIP_V1_CMD_WRITE_ARG_RST following arguments
-//@{
+/*@}*/
+/*! \name FLIP_V1_CMD_WRITE_ARG_RST following arguments*/
+/*@{*/
 #define FLIP_V1_CMD_WRITE_ARG_RST_HW    0x00
 #define FLIP_V1_CMD_WRITE_ARG_RST_SF    0x01
-//@}
-//@}
+/*@}*/
+/*@}*/
 
-//! \name FLIP_V1_CMD_READ_ID first argument
-//@{
+/*! \name FLIP_V1_CMD_READ_ID first argument*/
+/*@{*/
 #define FLIP_V1_CMD_READ_ID_ARG_BOOTLOADER 0x00
 #define FLIP_V1_CMD_READ_ID_ARG_SIGNATURE  0x01
-//! \name FLIP_V1_CMD_READ_ID_ARG_SIGNATURE following arguments
-//@{
+/*! \name FLIP_V1_CMD_READ_ID_ARG_SIGNATURE following arguments*/
+/*@{*/
 #define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_MANUF              0x30
 #define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_FAMILY             0x31
 #define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_PRODUCT            0x60
 #define FLIP_V1_CMD_READ_ID_SIGNATURE_ARG_REVISION           0x61
-//@}
-//@}
+/*@}*/
+/*@}*/
 
-//! \name FLIP_V1_CMD_CHANGE_BASE_ADDR first argument
-//@{
+/*! \name FLIP_V1_CMD_CHANGE_BASE_ADDR first argument*/
+/*@{*/
 #define FLIP_V1_CMD_CHANGE_BASE_ADDR_ARG0   0x03
 #define FLIP_V1_CMD_CHANGE_BASE_ADDR_ARG1   0x00
-//@}
+/*@}*/
 
-//@}
-//@}
+/*@}*/
+/*@}*/
 
 
 /**
@@ -164,62 +164,62 @@ COMPILER_PACK_SET(1)
  * \brief FLIP message structure
  */
 typedef struct {
-	uint8_t group;
-	uint8_t cmd_id;
-	uint8_t arg[4];
+    uint8_t group;
+    uint8_t cmd_id;
+    uint8_t arg[4];
 } flip_msg_v2_t;
 COMPILER_PACK_RESET()
 
-//! Size of buffer used by FLIP to receive or send data
-//! Note:  Write uses 2K and Read uses 1KB
+/*! Size of buffer used by FLIP to receive or send data*/
+/*! Note:  Write uses 2K and Read uses 1KB*/
 #define  FLIP_V2_BUF_TRANS_SIZE  (2*1024)
 
-//! \name Command Groups
-//@{
+/*! \name Command Groups*/
+/*@{*/
 #define FLIP_V2_CMD_GRP_DNLOAD                0x01
 #define FLIP_V2_CMD_GRP_UPLOAD                0x03
 #define FLIP_V2_CMD_GRP_EXEC                  0x04
 #define FLIP_V2_CMD_GRP_SELECT                0x06
-//@}
+/*@}*/
 
-//! \name FLIP_V2_CMD_GRP_DNLOAD first argument
-//@{
+/*! \name FLIP_V2_CMD_GRP_DNLOAD first argument*/
+/*@{*/
 #define FLIP_V2_CMD_PROGRAM_START             0x00
-//@}
+/*@}*/
 
 
-//! \name FLIP_V2_CMD_GRP_UPLOAD first argument
-//@{
+/*! \name FLIP_V2_CMD_GRP_UPLOAD first argument*/
+/*@{*/
 #define FLIP_V2_CMD_READ_MEMORY               0x00
 #define FLIP_V2_CMD_BLANK_CHECK               0x01
-//@}
+/*@}*/
 
-//! \name FLIP_V2_CMD_GRP_EXEC first argument
-//@{
+/*! \name FLIP_V2_CMD_GRP_EXEC first argument*/
+/*@{*/
 #define FLIP_V2_CMD_ERASE                     0x00
 #define FLIP_V2_CMD_START_APPLI               0x03
-//! \name FLIP_V2_CMD_ERASE following argument
-//@{
+/*! \name FLIP_V2_CMD_ERASE following argument*/
+/*@{*/
 #define FLIP_V2_CMD_ERASE_ARG_CHIP            0xFF
-//@}
-//! \name FLIP_V2_CMD_START_APPLI following arguments
-//@{
+/*@}*/
+/*! \name FLIP_V2_CMD_START_APPLI following arguments*/
+/*@{*/
 #define FLIP_V2_CMD_START_APPLI_ARG_RESET     0x00
 #define FLIP_V2_CMD_START_APPLI_ARG_NO_RESET  0x01
-//@}
-//@}
+/*@}*/
+/*@}*/
 
-//! \name FLIP_V2_CMD_GRP_SELECT first argument
-//@{
+/*! \name FLIP_V2_CMD_GRP_SELECT first argument*/
+/*@{*/
 #define FLIP_V2_CMD_SELECT_MEMORY             0x03
-//! \name FLIP_V2_CMD_SELECT_MEMORY following arguments
-//@{
+/*! \name FLIP_V2_CMD_SELECT_MEMORY following arguments*/
+/*@{*/
 #define FLIP_V2_CMD_SELECT_MEMORY_ARG_UNIT    0x00
 #define FLIP_V2_CMD_SELECT_MEMORY_ARG_PAGE    0x01
-//@}
-//! \name FLIP_V2_CMD_SELECT_MEMORY_ARG_UNIT following arguments
-//! Memory units field
-//@{
+/*@}*/
+/*! \name FLIP_V2_CMD_SELECT_MEMORY_ARG_UNIT following arguments*/
+/*! Memory units field*/
+/*@{*/
 #define FLIP_V2_CMD_SELECT_MEM_FLASH          0x00
 #define FLIP_V2_CMD_SELECT_MEM_EEPROM         0x01
 #define FLIP_V2_CMD_SELECT_MEM_SECURITY       0x02
@@ -237,17 +237,17 @@ COMPILER_PACK_RESET()
 #define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS6    0x0E
 #define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_CS7    0x0F
 #define FLIP_V2_CMD_SELECT_MEM_EXT_MEM_DF     0x10
-#define FLIP_V2_CMD_SELECT_MEM_COUNT          0x11	// Number of memory units
-//@}
-//@}
+#define FLIP_V2_CMD_SELECT_MEM_COUNT          0x11  /* Number of memory units*/
+/*@}*/
+/*@}*/
 
-//@}
+/*@}*/
 
-//@}
+/*@}*/
 
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // _FLIP_PROTOCOL_H_
+#endif /* _FLIP_PROTOCOL_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h
index fe035029ea77..b82d3dd1e72c 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/isp.h
@@ -116,24 +116,24 @@ bool isp_erase_chip_split(void);
  * or a software reset to restart the CPU.
  */
 void isp_start_appli(void);
-//! @}
+/*! @}*/
 
 
-//! Data type for holding flash memory addresses
+/*! Data type for holding flash memory addresses*/
 #ifdef ISP_SMALL_MEMORY_SIZE
-	typedef uint16_t isp_addr_t;
+    typedef uint16_t isp_addr_t;
 #else
-	typedef uint32_t isp_addr_t;
+    typedef uint32_t isp_addr_t;
 #endif
 
-//! Memory API definition
+/*! Memory API definition*/
 typedef struct {
-	//! Size of the memory (unit Byte)
-	uint32_t size;
-	//! Function to read memory
-	void (*fnct_read) (void *dst, isp_addr_t src, uint16_t nbytes);
-	//! Function to write memory
-	void (*fnct_write) (isp_addr_t dst, const void *src, uint16_t nbytes);
+    /*! Size of the memory (unit Byte)*/
+    uint32_t size;
+    /*! Function to read memory*/
+    void (*fnct_read) (void *dst, isp_addr_t src, uint16_t nbytes);
+    /*! Function to write memory*/
+    void (*fnct_write) (isp_addr_t dst, const void *src, uint16_t nbytes);
 } isp_mem_t;
 
 /**
@@ -158,47 +158,47 @@ typedef struct {
 #define ISP_MEM_EXT_MEM_CS6                  0x0E
 #define ISP_MEM_EXT_MEM_CS7                  0x0F
 #define ISP_MEM_EXT_MEM_DF                   0x10
-#define ISP_MEM_COUNT                        0x11 // Number of memory units
-//! @}
+#define ISP_MEM_COUNT                        0x11 /* Number of memory units*/
+/*! @}*/
 
-//! Memories list structure
+/*! Memories list structure*/
 typedef union {
-	isp_mem_t const *mem[ISP_MEM_COUNT];
-	struct {
-		isp_mem_t const *flash;
-		isp_mem_t const *eeprom;
-		isp_mem_t const *security;
-		isp_mem_t const *conf;
-		isp_mem_t const *bootloader;
-		isp_mem_t const *signature;
-		isp_mem_t const *user;
-		isp_mem_t const *int_ram;
-		isp_mem_t const *ext_mem_cs0;
-		isp_mem_t const *ext_mem_cs1;
-		isp_mem_t const *ext_mem_cs2;
-		isp_mem_t const *ext_mem_cs3;
-		isp_mem_t const *ext_mem_cs4;
-		isp_mem_t const *ext_mem_cs5;
-		isp_mem_t const *ext_mem_cs6;
-		isp_mem_t const *ext_mem_cs7;
-		isp_mem_t const *ext_mem_df;
-	}list;
+    isp_mem_t const *mem[ISP_MEM_COUNT];
+    struct {
+        isp_mem_t const *flash;
+        isp_mem_t const *eeprom;
+        isp_mem_t const *security;
+        isp_mem_t const *conf;
+        isp_mem_t const *bootloader;
+        isp_mem_t const *signature;
+        isp_mem_t const *user;
+        isp_mem_t const *int_ram;
+        isp_mem_t const *ext_mem_cs0;
+        isp_mem_t const *ext_mem_cs1;
+        isp_mem_t const *ext_mem_cs2;
+        isp_mem_t const *ext_mem_cs3;
+        isp_mem_t const *ext_mem_cs4;
+        isp_mem_t const *ext_mem_cs5;
+        isp_mem_t const *ext_mem_cs6;
+        isp_mem_t const *ext_mem_cs7;
+        isp_mem_t const *ext_mem_df;
+    }list;
 } isp_mems_t;
 
-//! Memories list declaration
+/*! Memories list declaration*/
 extern const isp_mems_t isp_memories;
 
-COMPILER_PACK_SET(1) // alignment requested to simulate a memory
+COMPILER_PACK_SET(1) /* alignment requested to simulate a memory*/
 
-//! Memory signature structure to store JTAG ID
+/*! Memory signature structure to store JTAG ID*/
 typedef union {
-	uint8_t mem[4];
-	struct {
-		uint8_t manufacture;
-		uint8_t product_number_msb;
-		uint8_t product_number_lsb;
-		uint8_t product_revision;
-	};
+    uint8_t mem[4];
+    struct {
+        uint8_t manufacture;
+        uint8_t product_number_msb;
+        uint8_t product_number_lsb;
+        uint8_t product_revision;
+    };
 } isp_mem_signature_t;
 
 
@@ -213,17 +213,17 @@ typedef union {
  * - id1 & id2 are not used and must always be 0.
  */
 typedef struct {
-	uint8_t version;
-	uint8_t id1;
-	uint8_t id2;
+    uint8_t version;
+    uint8_t id1;
+    uint8_t id2;
 } isp_mem_bootloader_t;
 
 COMPILER_PACK_RESET()
 
-//! @}
+/*! @}*/
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // _ISP_H_
+#endif /* _ISP_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h
index cad66a3871f2..9fe02bc38099 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/isp/flip/module_config/conf_isp.h
@@ -47,27 +47,27 @@
 #ifndef _CONF_ISP_H_
 #define _CONF_ISP_H_
 
-// Bootloader Versions
-// Example: Version 0x00 gives 1.0.0 on batchisp log
-// Example: Version 0x03 gives 1.0.3 on batchisp log
-// Example: Version 0x25 gives 1.2.5 on batchisp log
-//
-// Note: a specific UC3 rule is defined:
-// - 1.0.X for USB bootloaders that follow the AVR32784 application note
-// specification
-// - 1.1.X for USB bootloaders that follow the AVR32806 application note
-// specification
-//
-#define BOOTLOADER_VERSION   0x00  // 1.0.0
+/* Bootloader Versions*/
+/* Example: Version 0x00 gives 1.0.0 on batchisp log*/
+/* Example: Version 0x03 gives 1.0.3 on batchisp log*/
+/* Example: Version 0x25 gives 1.2.5 on batchisp log*/
+*/
+/* Note: a specific UC3 rule is defined:*/
+/* - 1.0.X for USB bootloaders that follow the AVR32784 application note*/
+/* specification*/
+/* - 1.1.X for USB bootloaders that follow the AVR32806 application note*/
+/* specification*/
+*/
+#define BOOTLOADER_VERSION   0x00  /* 1.0.0*/
 
-// If all memories (flash,eeprom,...) do not exceed 64KB.
-// then the ISP interface can be optimized to save CODE.
+/* If all memories (flash,eeprom,...) do not exceed 64KB.*/
+/* then the ISP interface can be optimized to save CODE.*/
 #define ISP_SMALL_MEMORY_SIZE
 
-// Definition of hardware condition to enter in ISP mode on AVR Xmega devices
+/* Definition of hardware condition to enter in ISP mode on AVR Xmega devices*/
 #define ISP_PORT_DIR      PORTX_DIR
 #define ISP_PORT_PINCTRL  PORTX_PIN5CTRL
 #define ISP_PORT_IN       PORTX_IN
 #define ISP_PORT_PIN      0 to 7
 
-#endif // _CONF_ISP_H_
+#endif /* _CONF_ISP_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h
index acd235cf9607..7278587a3ca8 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam0_usart/usart_serial.h
@@ -58,7 +58,7 @@ extern "C" {
 
 typedef Sercom * usart_inst_t;
 
-//struct usart_module usart;
+/*struct usart_module usart;*/
 
 /*! \brief Initializes the Usart in serial mode.
  *
@@ -70,16 +70,17 @@ typedef Sercom * usart_inst_t;
  * \retval false if initialization failed (error in baud rate calculation)
  */
 static inline bool usart_serial_init(
-		struct usart_module *const module,
-		usart_inst_t const hw,
-		const struct usart_config *const config)
+        struct usart_module *const module,
+        usart_inst_t const hw,
+        const struct usart_config *const config)
 {
-	if (usart_init(module, hw, config) == STATUS_OK) {
-		return true;
-	}
-	else {
-		return false;
-	}
+    if (usart_init(module, hw, config) == STATUS_OK)
+    {
+        return true;
+    }
+    else {
+        return false;
+    }
 }
 
 /** \brief Sends a character with the USART.
@@ -90,12 +91,12 @@ static inline bool usart_serial_init(
  * \return Status code
  */
 static inline enum status_code usart_serial_putchar(
-		struct usart_module *const module,
-		uint8_t c)
+        struct usart_module *const module,
+        uint8_t c)
 {
-	while(STATUS_OK !=usart_write_wait(module, c));
+    while(STATUS_OK !=usart_write_wait(module, c));
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Waits until a character is received, and returns it.
@@ -104,14 +105,14 @@ static inline enum status_code usart_serial_putchar(
  * \param[out]    c       Destination for the read character.
  */
 static inline void usart_serial_getchar(
-		struct usart_module *const module,
-		uint8_t *c)
+        struct usart_module *const module,
+        uint8_t *c)
 {
-	uint16_t temp = 0;
+    uint16_t temp = 0;
 
-	while(STATUS_OK != usart_read_wait(module, &temp));
+    while(STATUS_OK != usart_read_wait(module, &temp));
 
-	*c = temp;
+    *c = temp;
 }
 
 /**
@@ -122,11 +123,11 @@ static inline void usart_serial_getchar(
  * \param[in]     length   Length of data to write.
  */
 static inline enum status_code usart_serial_write_packet(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        const uint8_t *tx_data,
+        uint16_t length)
 {
-	return usart_write_buffer_wait(module, tx_data, length);
+    return usart_write_buffer_wait(module, tx_data, length);
 }
 
 /**
@@ -137,15 +138,15 @@ static inline enum status_code usart_serial_write_packet(
  * \param[in]     length   Length of data to read.
  */
 static inline enum status_code usart_serial_read_packet(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	return usart_read_buffer_wait(module, rx_data, length);
+    return usart_read_buffer_wait(module, rx_data, length);
 }
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  // _USART_SERIAL_H_
+#endif  /* _USART_SERIAL_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h
index ce1dba582aec..eabc480307ba 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/module_config/conf_uart_serial.h
@@ -49,23 +49,23 @@
 
 /* A reference setting for UART */
 /** UART Interface */
-//#define CONF_UART            CONSOLE_UART
+/*#define CONF_UART            CONSOLE_UART*/
 /** Baudrate setting */
-//#define CONF_UART_BAUDRATE   115200
+/*#define CONF_UART_BAUDRATE   115200*/
 /** Parity setting */
-//#define CONF_UART_PARITY     UART_MR_PAR_NO
+/*#define CONF_UART_PARITY     UART_MR_PAR_NO*/
 
 
 /* A reference setting for USART */
 /** USART Interface */
-//#define CONF_UART              USART1
+/*#define CONF_UART              USART1*/
 /** Baudrate setting */
-//#define CONF_UART_BAUDRATE     115200
+/*#define CONF_UART_BAUDRATE     115200*/
 /** Character length setting */
-//#define CONF_UART_CHAR_LENGTH  US_MR_CHRL_8_BIT
+/*#define CONF_UART_CHAR_LENGTH  US_MR_CHRL_8_BIT*/
 /** Parity setting */
-//#define CONF_UART_PARITY       US_MR_PAR_NO
+/*#define CONF_UART_PARITY       US_MR_PAR_NO*/
 /** Stop bits setting */
-//#define CONF_UART_STOP_BITS    US_MR_NBSTOP_1_BIT
+/*#define CONF_UART_STOP_BITS    US_MR_NBSTOP_1_BIT*/
 
 #endif/* CONF_USART_SERIAL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h
index b6fece28ff66..e68d72c6ab98 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/sam_uart/uart_serial.h
@@ -56,30 +56,30 @@
 #endif
 #include "usart.h"
 
-/** 
+/**
  * \name Serial Management Configuration
  */
-//! @{
+/*! @{*/
 #include "conf_uart_serial.h"
 
-//! @}
+/*! @}*/
 
 /** Input parameters when initializing RS232 and similar modes. */
 typedef struct uart_rs232_options {
-	/** Set baud rate of the USART (unused in slave modes). */
-	uint32_t baudrate;
+    /** Set baud rate of the USART (unused in slave modes). */
+    uint32_t baudrate;
 
-	/** Number of bits to transmit as a character (5-bit to 9-bit). */
-	uint32_t charlength;
+    /** Number of bits to transmit as a character (5-bit to 9-bit). */
+    uint32_t charlength;
 
-	/**
-	 * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
-	 * USART_PMODE_ODD_gc.
-	 */
-	uint32_t paritytype;
+    /**
+     * Parity type: USART_PMODE_DISABLED_gc, USART_PMODE_EVEN_gc,
+     * USART_PMODE_ODD_gc.
+     */
+    uint32_t paritytype;
 
-	/** 1, 1.5 or 2 stop bits. */
-	uint32_t stopbits;
+    /** 1, 1.5 or 2 stop bits. */
+    uint32_t stopbits;
 
 } usart_rs232_options_t;
 
@@ -87,7 +87,7 @@ typedef usart_rs232_options_t usart_serial_options_t;
 
 typedef Usart *usart_if;
 
-/** 
+/**
  * \brief Initializes the Usart in master mode.
  *
  * \param p_usart  Base address of the USART instance.
@@ -95,277 +95,292 @@ typedef Usart *usart_if;
  * \ref usart_options_t).
  */
 static inline void usart_serial_init(usart_if p_usart,
-		usart_serial_options_t *opt)
+        usart_serial_options_t *opt)
 {
 #if ((!SAM4L) && (!SAMG55))
-	sam_uart_opt_t uart_settings;
-	uart_settings.ul_mck = sysclk_get_peripheral_hz();
-	uart_settings.ul_baudrate = opt->baudrate;
-	uart_settings.ul_mode = opt->paritytype;
+    sam_uart_opt_t uart_settings;
+    uart_settings.ul_mck = sysclk_get_peripheral_hz();
+    uart_settings.ul_baudrate = opt->baudrate;
+    uart_settings.ul_mode = opt->paritytype;
 #endif
 
-	sam_usart_opt_t usart_settings;
-	usart_settings.baudrate = opt->baudrate;
-	usart_settings.char_length = opt->charlength;
-	usart_settings.parity_type = opt->paritytype;
-	usart_settings.stop_bits= opt->stopbits;
-	usart_settings.channel_mode= US_MR_CHMODE_NORMAL;
-	
+    sam_usart_opt_t usart_settings;
+    usart_settings.baudrate = opt->baudrate;
+    usart_settings.char_length = opt->charlength;
+    usart_settings.parity_type = opt->paritytype;
+    usart_settings.stop_bits= opt->stopbits;
+    usart_settings.channel_mode= US_MR_CHMODE_NORMAL;
+
 #ifdef UART
-	if (UART == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 #else
 # ifdef UART0
-	if (UART0 == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART0);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART0 == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART0);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 # endif
 # ifdef UART1
-	if (UART1 == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART1);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART1 == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART1);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 # endif
 # ifdef UART2
-	if (UART2 == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART2);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART2 == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART2);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 # endif
 # ifdef UART3
-	if (UART3 == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART3);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART3 == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART3);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 # endif
 # ifdef UART4
-	if (UART4 == (Uart*)p_usart) {
-		sysclk_enable_peripheral_clock(ID_UART4);
-		/* Configure UART */
-		uart_init((Uart*)p_usart, &uart_settings);
-	}
+    if (UART4 == (Uart*)p_usart)
+    {
+        sysclk_enable_peripheral_clock(ID_UART4);
+        /* Configure UART */
+        uart_init((Uart*)p_usart, &uart_settings);
+    }
 # endif
 #endif /* ifdef UART */
 
 
 #ifdef USART
-	if (USART == p_usart) {
+    if (USART == p_usart)
+    {
 #if (!SAM4L)
-		sysclk_enable_peripheral_clock(ID_USART);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        sysclk_enable_peripheral_clock(ID_USART);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 #else
 # ifdef USART0
-	if (USART0 == p_usart) {
+    if (USART0 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM0);
-		flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM0);
+        flexcom_set_opmode(FLEXCOM0, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART0);
+        sysclk_enable_peripheral_clock(ID_USART0);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART1
-	if (USART1 == p_usart) {
+    if (USART1 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM1);
-		flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM1);
+        flexcom_set_opmode(FLEXCOM1, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART1);
+        sysclk_enable_peripheral_clock(ID_USART1);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART2
-	if (USART2 == p_usart) {
+    if (USART2 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM2);
-		flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM2);
+        flexcom_set_opmode(FLEXCOM2, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART2);
+        sysclk_enable_peripheral_clock(ID_USART2);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART3
-	if (USART3 == p_usart) {
+    if (USART3 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM3);
-		flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM3);
+        flexcom_set_opmode(FLEXCOM3, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART3);
+        sysclk_enable_peripheral_clock(ID_USART3);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART4
-	if (USART4 == p_usart) {
+    if (USART4 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM4);
-		flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM4);
+        flexcom_set_opmode(FLEXCOM4, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART4);
+        sysclk_enable_peripheral_clock(ID_USART4);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART5
-	if (USART5 == p_usart) {
+    if (USART5 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM5);
-		flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM5);
+        flexcom_set_opmode(FLEXCOM5, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART5);
+        sysclk_enable_peripheral_clock(ID_USART5);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART6
-	if (USART6 == p_usart) {
+    if (USART6 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM6);
-		flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM6);
+        flexcom_set_opmode(FLEXCOM6, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART6);
+        sysclk_enable_peripheral_clock(ID_USART6);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 # ifdef USART7
-	if (USART7 == p_usart) {
+    if (USART7 == p_usart)
+    {
 #if (!SAM4L)
 #if (SAMG55)
-		flexcom_enable(FLEXCOM7);
-		flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART);
+        flexcom_enable(FLEXCOM7);
+        flexcom_set_opmode(FLEXCOM7, FLEXCOM_USART);
 #else
-		sysclk_enable_peripheral_clock(ID_USART7);
+        sysclk_enable_peripheral_clock(ID_USART7);
 #endif
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_hz());
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_hz());
 #endif
 #if (SAM4L)
-		sysclk_enable_peripheral_clock(p_usart);
-		/* Configure USART */
-		usart_init_rs232(p_usart, &usart_settings,
-				sysclk_get_peripheral_bus_hz(p_usart));
+        sysclk_enable_peripheral_clock(p_usart);
+        /* Configure USART */
+        usart_init_rs232(p_usart, &usart_settings,
+                sysclk_get_peripheral_bus_hz(p_usart));
 #endif
-		/* Enable the receiver and transmitter. */
-		usart_enable_tx(p_usart);
-		usart_enable_rx(p_usart);
-	}
+        /* Enable the receiver and transmitter. */
+        usart_enable_tx(p_usart);
+        usart_enable_rx(p_usart);
+    }
 # endif
 
 #endif /* ifdef USART */
@@ -386,95 +401,109 @@ static inline void usart_serial_init(usart_if p_usart,
 static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c)
 {
 #ifdef UART
-	if (UART == (Uart*)p_usart) {
-		while (uart_write((Uart*)p_usart, c)!=0);
-		return 1;
-	}
+    if (UART == (Uart*)p_usart)
+    {
+        while (uart_write((Uart*)p_usart, c)!=0);
+        return 1;
+    }
 #else
 # ifdef UART0
-	if (UART0 == (Uart*)p_usart) {
-		while (uart_write((Uart*)p_usart, c)!=0);
-		return 1;
-	}
+    if (UART0 == (Uart*)p_usart)
+    {
+        while (uart_write((Uart*)p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef UART1
-	if (UART1 == (Uart*)p_usart) {
-		while (uart_write((Uart*)p_usart, c)!=0);
-		return 1;
-	}
+    if (UART1 == (Uart*)p_usart)
+    {
+        while (uart_write((Uart*)p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef UART2
-	if (UART2 == (Uart*)p_usart) {
-		while (uart_write((Uart*)p_usart, c)!=0);
-		return 1;
-	}
+    if (UART2 == (Uart*)p_usart)
+    {
+        while (uart_write((Uart*)p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef UART3
-	if (UART3 == (Uart*)p_usart) {
-		while (uart_write((Uart*)p_usart, c)!=0);
-		return 1;
-	}
+    if (UART3 == (Uart*)p_usart)
+    {
+        while (uart_write((Uart*)p_usart, c)!=0);
+        return 1;
+    }
 # endif
 #endif /* ifdef UART */
 
 
 #ifdef USART
-	if (USART == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 #else
 # ifdef USART0
-	if (USART0 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART0 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART1
-	if (USART1 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART1 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART2
-	if (USART2 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART2 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART3
-	if (USART3 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART3 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART4
-	if (USART4 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART4 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART5
-	if (USART5 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART5 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART6
-	if (USART6 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART6 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 # ifdef USART7
-	if (USART7 == p_usart) {
-		while (usart_write(p_usart, c)!=0);
-		return 1;
-	}
+    if (USART7 == p_usart)
+    {
+        while (usart_write(p_usart, c)!=0);
+        return 1;
+    }
 # endif
 #endif /* ifdef USART */
 
-	return 0;
+    return 0;
 }
 /**
  * \brief Waits until a character is received, and returns it.
@@ -485,92 +514,106 @@ static inline int usart_serial_putchar(usart_if p_usart, const uint8_t c)
  */
 static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data)
 {
-	uint32_t val = 0;
+    uint32_t val = 0;
 
-	/* Avoid Cppcheck Warning */
-	UNUSED(val);
+    /* Avoid Cppcheck Warning */
+    UNUSED(val);
 
 #ifdef UART
-	if (UART == (Uart*)p_usart) {
-		while (uart_read((Uart*)p_usart, data));
-	}
+    if (UART == (Uart*)p_usart)
+    {
+        while (uart_read((Uart*)p_usart, data));
+    }
 #else
 # ifdef UART0
-	if (UART0 == (Uart*)p_usart) {
-		while (uart_read((Uart*)p_usart, data));
-	}
+    if (UART0 == (Uart*)p_usart)
+    {
+        while (uart_read((Uart*)p_usart, data));
+    }
 # endif
 # ifdef UART1
-	if (UART1 == (Uart*)p_usart) {
-		while (uart_read((Uart*)p_usart, data));
-	}
+    if (UART1 == (Uart*)p_usart)
+    {
+        while (uart_read((Uart*)p_usart, data));
+    }
 # endif
 # ifdef UART2
-	if (UART2 == (Uart*)p_usart) {
-		while (uart_read((Uart*)p_usart, data));
-	}
+    if (UART2 == (Uart*)p_usart)
+    {
+        while (uart_read((Uart*)p_usart, data));
+    }
 # endif
 # ifdef UART3
-	if (UART3 == (Uart*)p_usart) {
-		while (uart_read((Uart*)p_usart, data));
-	}
+    if (UART3 == (Uart*)p_usart)
+    {
+        while (uart_read((Uart*)p_usart, data));
+    }
 # endif
 #endif /* ifdef UART */
 
 
 #ifdef USART
-	if (USART == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 #else
 # ifdef USART0
-	if (USART0 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART0 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART1
-	if (USART1 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART1 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART2
-	if (USART2 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART2 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART3
-	if (USART3 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART3 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART4
-	if (USART4 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART4 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART5
-	if (USART5 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART5 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART6
-	if (USART6 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART6 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 # ifdef USART7
-	if (USART7 == p_usart) {
-		while (usart_read(p_usart, &val));
-		*data = (uint8_t)(val & 0xFF);
-	}
+    if (USART7 == p_usart)
+    {
+        while (usart_read(p_usart, &val));
+        *data = (uint8_t)(val & 0xFF);
+    }
 # endif
 #endif /* ifdef USART */
 
@@ -587,81 +630,95 @@ static inline void usart_serial_getchar(usart_if p_usart, uint8_t *data)
 static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart)
 {
 #ifdef UART
-	if (UART == (Uart*)p_usart) {
-		return uart_is_rx_ready((Uart*)p_usart);
-	}
+    if (UART == (Uart*)p_usart)
+    {
+        return uart_is_rx_ready((Uart*)p_usart);
+    }
 #else
 # ifdef UART0
-	if (UART0 == (Uart*)p_usart) {
-		return uart_is_rx_ready((Uart*)p_usart);
-	}
+    if (UART0 == (Uart*)p_usart)
+    {
+        return uart_is_rx_ready((Uart*)p_usart);
+    }
 # endif
 # ifdef UART1
-	if (UART1 == (Uart*)p_usart) {
-		return uart_is_rx_ready((Uart*)p_usart);
-	}
+    if (UART1 == (Uart*)p_usart)
+    {
+        return uart_is_rx_ready((Uart*)p_usart);
+    }
 # endif
 # ifdef UART2
-	if (UART2 == (Uart*)p_usart) {
-		return uart_is_rx_ready((Uart*)p_usart);
-	}
+    if (UART2 == (Uart*)p_usart)
+    {
+        return uart_is_rx_ready((Uart*)p_usart);
+    }
 # endif
 # ifdef UART3
-	if (UART3 == (Uart*)p_usart) {
-		return uart_is_rx_ready((Uart*)p_usart);
-	}
+    if (UART3 == (Uart*)p_usart)
+    {
+        return uart_is_rx_ready((Uart*)p_usart);
+    }
 # endif
 #endif /* ifdef UART */
 
 
 #ifdef USART
-	if (USART == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 #else
 # ifdef USART0
-	if (USART0 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART0 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART1
-	if (USART1 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART1 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART2
-	if (USART2 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART2 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART3
-	if (USART3 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART3 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART4
-	if (USART4 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART4 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART5
-	if (USART5 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART5 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART6
-	if (USART6 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART6 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 # ifdef USART7
-	if (USART7 == p_usart) {
-		return usart_is_rx_ready(p_usart);
-	}
+    if (USART7 == p_usart)
+    {
+        return usart_is_rx_ready(p_usart);
+    }
 # endif
 #endif /* ifdef USART */
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -673,7 +730,7 @@ static inline uint32_t usart_serial_is_rx_ready(usart_if p_usart)
  *
  */
 status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
-		size_t len);
+        size_t len);
 
 /**
  * \brief Receive a sequence of bytes to a USART device
@@ -684,6 +741,6 @@ status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
  *
  */
 status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
-		size_t len);
+        size_t len);
 
 #endif  /* _UART_SERIAL_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h b/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h
index df0ae236b60e..6aa5bf3ca037 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/serial.h
@@ -103,8 +103,8 @@
  *
  * @{
  */
- 
-//! @}
+
+/*! @}*/
 
 /**
  * \page serial_quickstart Quick start guide for Serial Interface service
@@ -139,18 +139,18 @@
  * -# \ref sysclk_group "System Clock Management (sysclk)"
  *
  * \subsection serial_basic_use_case_setup_code Example code
- * The following configuration must be added to the project (typically to a 
+ * The following configuration must be added to the project (typically to a
  * conf_uart_serial.h file, but it can also be added to your main application file.)
  *
  * \note The following takes SAM3X configuration for example, other devices have similar
  * configuration, but their parameters may be different, refer to corresponding header files.
  *
  * \code
-	#define USART_SERIAL                     &USARTD0
-	#define USART_SERIAL_BAUDRATE            9600
-	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
-	#define USART_SERIAL_PARITY              US_MR_PAR_NO
-	#define USART_SERIAL_STOP_BIT            false
+    #define USART_SERIAL                     &USARTD0
+    #define USART_SERIAL_BAUDRATE            9600
+    #define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+    #define USART_SERIAL_PARITY              US_MR_PAR_NO
+    #define USART_SERIAL_STOP_BIT            false
 \endcode
  *
  * A variable for the received byte must be added:
@@ -158,16 +158,16 @@
  *
  * Add to application initialization:
  * \code
-	    sysclk_init();
+        sysclk_init();
 
-	    static usart_serial_options_t usart_options = {
-	       .baudrate = USART_SERIAL_BAUDRATE,
-	       .charlength = USART_SERIAL_CHAR_LENGTH,
-	       .paritytype = USART_SERIAL_PARITY,
-	       .stopbits = USART_SERIAL_STOP_BIT
-	    };
+        static usart_serial_options_t usart_options = {
+           .baudrate = USART_SERIAL_BAUDRATE,
+           .charlength = USART_SERIAL_CHAR_LENGTH,
+           .paritytype = USART_SERIAL_PARITY,
+           .stopbits = USART_SERIAL_STOP_BIT
+        };
 
-	    usart_serial_init(USART_SERIAL, &usart_options);
+        usart_serial_init(USART_SERIAL, &usart_options);
 \endcode
  *
  * \subsection serial_basic_use_case_setup_flow Workflow
@@ -175,12 +175,12 @@
  *   - \code sysclk_init(); \endcode
  * -# Create serial USART options struct:
  *   - \code
-	static usart_serial_options_t usart_options = {
-	   .baudrate = USART_SERIAL_BAUDRATE,
-	   .charlength = USART_SERIAL_CHAR_LENGTH,
-	   .paritytype = USART_SERIAL_PARITY,
-	   .stopbits = USART_SERIAL_STOP_BIT
-	};
+    static usart_serial_options_t usart_options = {
+       .baudrate = USART_SERIAL_BAUDRATE,
+       .charlength = USART_SERIAL_CHAR_LENGTH,
+       .paritytype = USART_SERIAL_PARITY,
+       .stopbits = USART_SERIAL_STOP_BIT
+    };
 \endcode
  * -# Initialize the serial service:
  *   - \code usart_serial_init(USART_SERIAL, &usart_options);\endcode
@@ -190,8 +190,8 @@
  * \subsection serial_basic_use_case_usage_code Example code
  * Add to application C-file:
  * \code
-	usart_serial_getchar(USART_SERIAL, &received_byte);
-	usart_serial_putchar(USART_SERIAL, received_byte);
+    usart_serial_getchar(USART_SERIAL, &received_byte);
+    usart_serial_putchar(USART_SERIAL, received_byte);
 \endcode
  *
  * \subsection serial_basic_use_case_usage_flow Workflow
@@ -220,32 +220,32 @@
  * -# \ref sysclk_group "System Clock Management (sysclk)"
  *
  * \subsection serial_use_case_1_setup_code Example code
- * The following configuration must be added to the project (typically to a 
+ * The following configuration must be added to the project (typically to a
  * conf_uart_serial.h file, but it can also be added to your main application file.):
  *
  * \note The following takes SAM3X configuration for example, other devices have similar
  * configuration, but their parameters may be different, refer to corresponding header files.
  *
  * \code
-	#define USART_SERIAL                     &USARTD0
-	#define USART_SERIAL_BAUDRATE            9600
-	#define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
-	#define USART_SERIAL_PARITY              US_MR_PAR_NO
-	#define USART_SERIAL_STOP_BIT            false
+    #define USART_SERIAL                     &USARTD0
+    #define USART_SERIAL_BAUDRATE            9600
+    #define USART_SERIAL_CHAR_LENGTH         US_MR_CHRL_8_BIT
+    #define USART_SERIAL_PARITY              US_MR_PAR_NO
+    #define USART_SERIAL_STOP_BIT            false
 \endcode
  *
  * Add to application initialization:
  * \code
-	    sysclk_init();
+        sysclk_init();
 
-	    static usart_serial_options_t usart_options = {
-	       .baudrate = USART_SERIAL_BAUDRATE,
-	       .charlength = USART_SERIAL_CHAR_LENGTH,
-	       .paritytype = USART_SERIAL_PARITY,
-	       .stopbits = USART_SERIAL_STOP_BIT
-	    };
+        static usart_serial_options_t usart_options = {
+           .baudrate = USART_SERIAL_BAUDRATE,
+           .charlength = USART_SERIAL_CHAR_LENGTH,
+           .paritytype = USART_SERIAL_PARITY,
+           .stopbits = USART_SERIAL_STOP_BIT
+        };
 
-	    usart_serial_init(USART_SERIAL, &usart_options);
+        usart_serial_init(USART_SERIAL, &usart_options);
 \endcode
  *
  * \subsection serial_use_case_1_setup_flow Workflow
@@ -253,12 +253,12 @@
  *   - \code sysclk_init(); \endcode
  * -# Create USART options struct:
  *   - \code
-	static usart_serial_options_t usart_options = {
-	   .baudrate = USART_SERIAL_BAUDRATE,
-	   .charlength = USART_SERIAL_CHAR_LENGTH,
-	   .paritytype = USART_SERIAL_PARITY,
-	   .stopbits = USART_SERIAL_STOP_BIT
-	};
+    static usart_serial_options_t usart_options = {
+       .baudrate = USART_SERIAL_BAUDRATE,
+       .charlength = USART_SERIAL_CHAR_LENGTH,
+       .paritytype = USART_SERIAL_PARITY,
+       .stopbits = USART_SERIAL_STOP_BIT
+    };
 \endcode
  * -# Initialize in RS232 mode:
  *   - \code usart_serial_init(USART_SERIAL_EXAMPLE, &usart_options); \endcode
@@ -268,7 +268,7 @@
  * \subsection serial_use_case_1_usage_code Example code
  * Add to, e.g., main loop in application C-file:
  * \code
-	usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
+    usart_serial_write_packet(USART_SERIAL, "Test String", strlen("Test String"));
 \endcode
  *
  * \subsection serial_use_case_1_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c b/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c
index c67c25632795..4cf17872c449 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/serial/usart_serial.c
@@ -56,14 +56,15 @@
  *
  */
 status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
-		size_t len)
+        size_t len)
 {
-	while (len) {
-		usart_serial_putchar(usart, *data);
-		len--;
-		data++;
-	}
-	return STATUS_OK;
+    while (len)
+    {
+        usart_serial_putchar(usart, *data);
+        len--;
+        data++;
+    }
+    return STATUS_OK;
 }
 
 
@@ -76,12 +77,13 @@ status_code_t usart_serial_write_packet(usart_if usart, const uint8_t *data,
  *
  */
 status_code_t usart_serial_read_packet(usart_if usart, uint8_t *data,
-		size_t len)
+        size_t len)
 {
-	while (len) {
-		usart_serial_getchar(usart, data);
-		len--;
-		data++;
-	}
-	return STATUS_OK;
+    while (len)
+    {
+        usart_serial_getchar(usart, data);
+        len--;
+        data++;
+    }
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h
index 0f6efbc456f0..bbc710f92c96 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h
@@ -46,7 +46,7 @@
 #ifndef CONF_SLEEPMGR_H
 #define CONF_SLEEPMGR_H
 
-// Sleep manager options
+/* Sleep manager options*/
 #define CONFIG_SLEEPMGR_ENABLE
 
 #endif /* CONF_SLEEPMGR_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h
index a39bfd32fbe4..adc4d0cd87a5 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sam/sleepmgr.h
@@ -61,28 +61,28 @@ extern "C" {
  * @{
  */
 enum sleepmgr_mode {
-	//! Active mode.
-	SLEEPMGR_ACTIVE = 0,
-	/*! WFE sleep mode.
-	 *  Potential Wake Up sources:
-	 *  fast startup events (USB, RTC, RTT, WKUPs),
-	 *  interrupt, and events. */
-	SLEEPMGR_SLEEP_WFE,
-	/*! WFI sleep mode.
-	 * Potential Wake Up sources: fast startup events and interrupt. */
-	SLEEPMGR_SLEEP_WFI,
-	/*! Wait mode, wakeup fast (in 3ms).
-	 *  XTAL is not disabled when sleep.
-	 *  Potential Wake Up sources: fast startup events */
-	SLEEPMGR_WAIT_FAST,
-	/*! Wait mode.
-	 *  Potential Wake Up sources: fast startup events */
-	SLEEPMGR_WAIT,
+    /*! Active mode.*/
+    SLEEPMGR_ACTIVE = 0,
+    /*! WFE sleep mode.
+     *  Potential Wake Up sources:
+     *  fast startup events (USB, RTC, RTT, WKUPs),
+     *  interrupt, and events. */
+    SLEEPMGR_SLEEP_WFE,
+    /*! WFI sleep mode.
+     * Potential Wake Up sources: fast startup events and interrupt. */
+    SLEEPMGR_SLEEP_WFI,
+    /*! Wait mode, wakeup fast (in 3ms).
+     *  XTAL is not disabled when sleep.
+     *  Potential Wake Up sources: fast startup events */
+    SLEEPMGR_WAIT_FAST,
+    /*! Wait mode.
+     *  Potential Wake Up sources: fast startup events */
+    SLEEPMGR_WAIT,
 #if (!(SAMG51 || SAMG53 || SAMG54))
-	//! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC.
-	SLEEPMGR_BACKUP,
+    /*! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC.*/
+    SLEEPMGR_BACKUP,
 #endif
-	SLEEPMGR_NR_OF_MODES,
+    SLEEPMGR_NR_OF_MODES,
 };
 
 /**
@@ -91,28 +91,28 @@ enum sleepmgr_mode {
  * @{
  */
 #if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
-//! Sleep mode lock counters
+/*! Sleep mode lock counters*/
 extern uint8_t sleepmgr_locks[];
 #endif /* CONFIG_SLEEPMGR_ENABLE */
-//! @}
+/*! @}*/
 
 
 static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
 {
-	Assert(sleep_mode != SLEEPMGR_ACTIVE);
+    Assert(sleep_mode != SLEEPMGR_ACTIVE);
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	cpu_irq_disable();
+    cpu_irq_disable();
 
-	// Atomically enable the global interrupts and enter the sleep mode.
-	pmc_sleep(sleep_mode);
+    /* Atomically enable the global interrupts and enter the sleep mode.*/
+    pmc_sleep(sleep_mode);
 #else
-	UNUSED(sleep_mode);
-	cpu_irq_enable();
+    UNUSED(sleep_mode);
+    cpu_irq_enable();
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 
 }
 
-//! @}
+/*! @}*/
 
 #ifdef __cplusplus
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h
index 2ccd8b3f7f67..27dc4856aadc 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h
@@ -46,7 +46,7 @@
 #ifndef CONF_SLEEPMGR_INCLUDED
 #define CONF_SLEEPMGR_INCLUDED
 
-// Sleep manager options
+/* Sleep manager options*/
 #define CONFIG_SLEEPMGR_ENABLE
 
 #endif /* CONF_SLEEPMGR_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h
index 8cb94ddb5b00..7cb448e78506 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/samd/sleepmgr.h
@@ -62,34 +62,34 @@ extern "C" {
  */
 
 enum sleepmgr_mode {
-	/** Active mode. */
-	SLEEPMGR_ACTIVE = 0,
-
-	/**
-	 *  Idle 0 mode.
-	 *  Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
-	 */
-	SLEEPMGR_IDLE_0,
-
-	/**
-	 *  Idle 1 mode.
-	 *  Potential Wake Up sources: Synchronous (APB), asynchronous
-	 */
-	SLEEPMGR_IDLE_1,
-
-	/**
-	 *  Idle 2 mode.
-	 *  Potential Wake Up sources: Asynchronous
-	 */
-	SLEEPMGR_IDLE_2,
-
-	/**
-	 * Standby mode.
-	 * Potential Wake Up sources: Asynchronous
-	 */
-	SLEEPMGR_STANDBY,
-
-	SLEEPMGR_NR_OF_MODES,
+    /** Active mode. */
+    SLEEPMGR_ACTIVE = 0,
+
+    /**
+     *  Idle 0 mode.
+     *  Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
+     */
+    SLEEPMGR_IDLE_0,
+
+    /**
+     *  Idle 1 mode.
+     *  Potential Wake Up sources: Synchronous (APB), asynchronous
+     */
+    SLEEPMGR_IDLE_1,
+
+    /**
+     *  Idle 2 mode.
+     *  Potential Wake Up sources: Asynchronous
+     */
+    SLEEPMGR_IDLE_2,
+
+    /**
+     * Standby mode.
+     * Potential Wake Up sources: Asynchronous
+     */
+    SLEEPMGR_STANDBY,
+
+    SLEEPMGR_NR_OF_MODES,
 };
 
 /**
@@ -105,17 +105,17 @@ extern uint8_t sleepmgr_locks[];
 
 static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
 {
-	Assert(sleep_mode != SLEEPMGR_ACTIVE);
+    Assert(sleep_mode != SLEEPMGR_ACTIVE);
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	cpu_irq_disable();
+    cpu_irq_disable();
 
-	/* Enter the sleep mode. */
-	system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
-	cpu_irq_enable();
-	system_sleep();
+    /* Enter the sleep mode. */
+    system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
+    cpu_irq_enable();
+    system_sleep();
 #else
-	UNUSED(sleep_mode);
-	cpu_irq_enable();
+    UNUSED(sleep_mode);
+    cpu_irq_enable();
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h
index ae38de13611b..f34c443caf03 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/sleepmgr/sleepmgr.h
@@ -127,12 +127,13 @@ extern "C" {
 static inline void sleepmgr_init(void)
 {
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	uint8_t i;
+    uint8_t i;
 
-	for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
-		sleepmgr_locks[i] = 0;
-	}
-	sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
+    for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++)
+    {
+        sleepmgr_locks[i] = 0;
+    }
+    sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 }
 
@@ -147,24 +148,26 @@ static inline void sleepmgr_init(void)
 static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
 {
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	irqflags_t flags;
+    irqflags_t flags;
 
-	if(sleepmgr_locks[mode] >= 0xff) {
-		while (true) {
-			// Warning: maximum value of sleepmgr_locks buffer is no more than 255.
-			// Check APP or change the data type to uint16_t.
-		}
-	}
+    if(sleepmgr_locks[mode] >= 0xff)
+    {
+        while (true)
+        {
+            /* Warning: maximum value of sleepmgr_locks buffer is no more than 255.*/
+            /* Check APP or change the data type to uint16_t.*/
+        }
+    }
 
-	// Enter a critical section
-	flags = cpu_irq_save();
+    /* Enter a critical section*/
+    flags = cpu_irq_save();
 
-	++sleepmgr_locks[mode];
+    ++sleepmgr_locks[mode];
 
-	// Leave the critical section
-	cpu_irq_restore(flags);
+    /* Leave the critical section*/
+    cpu_irq_restore(flags);
 #else
-	UNUSED(mode);
+    UNUSED(mode);
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 }
 
@@ -179,24 +182,26 @@ static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
 static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
 {
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	irqflags_t flags;
+    irqflags_t flags;
 
-	if(sleepmgr_locks[mode] == 0) {
-		while (true) {
-			// Warning: minimum value of sleepmgr_locks buffer is no less than 0.
-			// Check APP.
-		}
-	}
+    if(sleepmgr_locks[mode] == 0)
+    {
+        while (true)
+        {
+            /* Warning: minimum value of sleepmgr_locks buffer is no less than 0.*/
+            /* Check APP.*/
+        }
+    }
 
-	// Enter a critical section
-	flags = cpu_irq_save();
+    /* Enter a critical section*/
+    flags = cpu_irq_save();
 
-	--sleepmgr_locks[mode];
+    --sleepmgr_locks[mode];
 
-	// Leave the critical section
-	cpu_irq_restore(flags);
+    /* Leave the critical section*/
+    cpu_irq_restore(flags);
 #else
-	UNUSED(mode);
+    UNUSED(mode);
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 }
 
@@ -209,24 +214,25 @@ static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
  */
 static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
 {
-	enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
+    enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
 
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	uint8_t *lock_ptr = sleepmgr_locks;
+    uint8_t *lock_ptr = sleepmgr_locks;
 
-	// Find first non-zero lock count, starting with the shallowest modes.
-	while (!(*lock_ptr)) {
-		lock_ptr++;
-		sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
-	}
+    /* Find first non-zero lock count, starting with the shallowest modes.*/
+    while (!(*lock_ptr))
+    {
+        lock_ptr++;
+        sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
+    }
 
-	// Catch the case where one too many sleepmgr_unlock_mode() call has been
-	// performed on the deepest sleep mode.
-	Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
+    /* Catch the case where one too many sleepmgr_unlock_mode() call has been*/
+    /* performed on the deepest sleep mode.*/
+    Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
 
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 
-	return sleep_mode;
+    return sleep_mode;
 }
 
 /**
@@ -245,26 +251,27 @@ static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
 static inline void sleepmgr_enter_sleep(void)
 {
 #ifdef CONFIG_SLEEPMGR_ENABLE
-	enum sleepmgr_mode sleep_mode;
-
-	cpu_irq_disable();
-
-	// Find the deepest allowable sleep mode
-	sleep_mode = sleepmgr_get_sleep_mode();
-	// Return right away if first mode (ACTIVE) is locked.
-	if (sleep_mode==SLEEPMGR_ACTIVE) {
-		cpu_irq_enable();
-		return;
-	}
-	// Enter the deepest allowable sleep mode with interrupts enabled
-	sleepmgr_sleep(sleep_mode);
+    enum sleepmgr_mode sleep_mode;
+
+    cpu_irq_disable();
+
+    /* Find the deepest allowable sleep mode*/
+    sleep_mode = sleepmgr_get_sleep_mode();
+    /* Return right away if first mode (ACTIVE) is locked.*/
+    if (sleep_mode==SLEEPMGR_ACTIVE)
+    {
+        cpu_irq_enable();
+        return;
+    }
+    /* Enter the deepest allowable sleep mode with interrupts enabled*/
+    sleepmgr_sleep(sleep_mode);
 #else
-	cpu_irq_enable();
+    cpu_irq_enable();
 #endif /* CONFIG_SLEEPMGR_ENABLE */
 }
 
 
-//! @}
+/*! @}*/
 
 #ifdef __cplusplus
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h
index e98fe69f9cf5..d48e087f0694 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/module_config/conf_spi_master.h
@@ -49,19 +49,19 @@
 
 /* Possibility to change low-level configurations here */
 
-//! Default Config Spi Master Delay BCS
+/*! Default Config Spi Master Delay BCS*/
 #define CONFIG_SPI_MASTER_DELAY_BCS            0
 
-//! Default Config Spi Master Bits per Transfer Definition
+/*! Default Config Spi Master Bits per Transfer Definition*/
 #define CONFIG_SPI_MASTER_BITS_PER_TRANSFER    8
 
-//! Default Config Spi Master Delay BCT
+/*! Default Config Spi Master Delay BCT*/
 #define CONFIG_SPI_MASTER_DELAY_BCT            0
 
-//! Default Config Spi Master Delay BS
+/*! Default Config Spi Master Delay BS*/
 #define CONFIG_SPI_MASTER_DELAY_BS             0
 
-//! Default Config Spi Master Dummy Field
+/*! Default Config Spi Master Dummy Field*/
 #define CONFIG_SPI_MASTER_DUMMY                0xFF
 
 #endif /* CONF_SPI_MASTER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c
index 562a7dc7e7de..db08d198283d 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.c
@@ -78,19 +78,19 @@
 void spi_master_init(Spi *p_spi)
 {
 #if SAMG55
-	flexcom_enable(BOARD_FLEXCOM_SPI);
-	flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
+    flexcom_enable(BOARD_FLEXCOM_SPI);
+    flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
 #else
-	spi_enable_clock(p_spi);
+    spi_enable_clock(p_spi);
 #endif
-	spi_reset(p_spi);
-	spi_set_master_mode(p_spi);
-	spi_disable_mode_fault_detect(p_spi);
-	spi_disable_loopback(p_spi);
-	spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
-	spi_set_fixed_peripheral_select(p_spi);
-	spi_disable_peripheral_select_decode(p_spi);
-	spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
+    spi_reset(p_spi);
+    spi_set_master_mode(p_spi);
+    spi_disable_mode_fault_detect(p_spi);
+    spi_disable_loopback(p_spi);
+    spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
+    spi_set_fixed_peripheral_select(p_spi);
+    spi_disable_peripheral_select_decode(p_spi);
+    spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
 }
 
 /**
@@ -108,26 +108,27 @@ void spi_master_init(Spi *p_spi)
  * \param sel_id    Board specific select id.
  */
 void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
-		spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
+        spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
 {
 #if (SAM4L)
     int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_pba_hz());
 #else
-	int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_peripheral_hz());
+    int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_peripheral_hz());
 #endif
-	/* avoid Cppcheck Warning */
-	UNUSED(sel_id);
-	if (-1 == baud_div) {
-		Assert(0 == "Failed to find baudrate divider");
-	}
-	spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
-			CONFIG_SPI_MASTER_DELAY_BCT);
-	spi_set_bits_per_transfer(p_spi, device->id,
-			CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
-	spi_set_baudrate_div(p_spi, device->id, baud_div);
-	spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
-	spi_set_clock_polarity(p_spi, device->id, flags >> 1);
-	spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
+    /* avoid Cppcheck Warning */
+    UNUSED(sel_id);
+    if (-1 == baud_div)
+    {
+        Assert(0 == "Failed to find baudrate divider");
+    }
+    spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
+            CONFIG_SPI_MASTER_DELAY_BCT);
+    spi_set_bits_per_transfer(p_spi, device->id,
+            CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
+    spi_set_baudrate_div(p_spi, device->id, baud_div);
+    spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
+    spi_set_clock_polarity(p_spi, device->id, flags >> 1);
+    spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
 }
 
 /**
@@ -141,15 +142,18 @@ void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
  */
 void spi_select_device(Spi *p_spi, struct spi_device *device)
 {
-	if (spi_get_peripheral_select_decode_setting(p_spi)) {
-		if (device->id < MAX_NUM_WITH_DECODER) {
-			spi_set_peripheral_chip_select_value(p_spi, device->id);
-		}
-	} else {
-		if (device->id < MAX_NUM_WITHOUT_DECODER) {
-			spi_set_peripheral_chip_select_value(p_spi, (~(1 << device->id)));
-		}
-	}
+    if (spi_get_peripheral_select_decode_setting(p_spi))
+    {
+        if (device->id < MAX_NUM_WITH_DECODER)
+        {
+            spi_set_peripheral_chip_select_value(p_spi, device->id);
+        }
+    } else {
+        if (device->id < MAX_NUM_WITHOUT_DECODER)
+        {
+            spi_set_peripheral_chip_select_value(p_spi, (~(1 << device->id)));
+        }
+    }
 }
 
 /**
@@ -164,16 +168,17 @@ void spi_select_device(Spi *p_spi, struct spi_device *device)
  */
 void spi_deselect_device(Spi *p_spi, struct spi_device *device)
 {
-	/* avoid Cppcheck Warning */
-	UNUSED(device);
-	while (!spi_is_tx_empty(p_spi)) {
-	}
+    /* avoid Cppcheck Warning */
+    UNUSED(device);
+    while (!spi_is_tx_empty(p_spi))
+    {
+    }
 
-	// Assert all lines; no peripheral is selected.
-	spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
+    /* Assert all lines; no peripheral is selected.*/
+    spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
 
-	// Last transfer, so de-assert the current NPCS if CSAAT is set.
-	spi_set_lastxfer(p_spi);
+    /* Last transfer, so de-assert the current NPCS if CSAAT is set.*/
+    spi_set_lastxfer(p_spi);
 
 }
 
@@ -189,26 +194,29 @@ void spi_deselect_device(Spi *p_spi, struct spi_device *device)
  * \pre SPI device must be selected with spi_select_device() first.
  */
 status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data,
-		size_t len)
+        size_t len)
 {
-	uint32_t timeout = SPI_TIMEOUT;
-	uint32_t i = 0;
-	uint8_t val;
+    uint32_t timeout = SPI_TIMEOUT;
+    uint32_t i = 0;
+    uint8_t val;
 
-	while (len) {
-		timeout = SPI_TIMEOUT;
-		while (!spi_is_tx_ready(p_spi)) {
-			if (!timeout--) {
-				return ERR_TIMEOUT;
-			}
-		}
-		val = data[i];
-		spi_write_single(p_spi, val);
-		i++;
-		len--;
-	}
+    while (len)
+    {
+        timeout = SPI_TIMEOUT;
+        while (!spi_is_tx_ready(p_spi))
+        {
+            if (!timeout--)
+            {
+                return ERR_TIMEOUT;
+            }
+        }
+        val = data[i];
+        spi_write_single(p_spi, val);
+        i++;
+        len--;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -224,33 +232,38 @@ status_code_t spi_write_packet(Spi *p_spi, const uint8_t *data,
  */
 status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len)
 {
-	uint32_t timeout = SPI_TIMEOUT;
-	uint8_t val;
-	uint32_t i = 0;
+    uint32_t timeout = SPI_TIMEOUT;
+    uint8_t val;
+    uint32_t i = 0;
 
-	while (len) {
-		timeout = SPI_TIMEOUT;
-		while (!spi_is_tx_ready(p_spi)) {
-			if (!timeout--) {
-				return ERR_TIMEOUT;
-			}
-		}
-		spi_write_single(p_spi, CONFIG_SPI_MASTER_DUMMY);
+    while (len)
+    {
+        timeout = SPI_TIMEOUT;
+        while (!spi_is_tx_ready(p_spi))
+        {
+            if (!timeout--)
+            {
+                return ERR_TIMEOUT;
+            }
+        }
+        spi_write_single(p_spi, CONFIG_SPI_MASTER_DUMMY);
 
-		timeout = SPI_TIMEOUT;
-		while (!spi_is_rx_ready(p_spi)) {
-			if (!timeout--) {
-				return ERR_TIMEOUT;
-			}
-		}
-		spi_read_single(p_spi, &val);
+        timeout = SPI_TIMEOUT;
+        while (!spi_is_rx_ready(p_spi))
+        {
+            if (!timeout--)
+            {
+                return ERR_TIMEOUT;
+            }
+        }
+        spi_read_single(p_spi, &val);
 
-		data[i] = val;
-		i++;
-		len--;
-	}
+        data[i] = val;
+        i++;
+        len--;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -265,32 +278,37 @@ status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len)
  */
 status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len)
 {
-	uint32_t timeout = SPI_TIMEOUT;
-	uint8_t val;
-	uint32_t i = 0;
+    uint32_t timeout = SPI_TIMEOUT;
+    uint8_t val;
+    uint32_t i = 0;
 
-	while (len) {
-		timeout = SPI_TIMEOUT;
-		while (!spi_is_tx_ready(p_spi)) {
-			if (!timeout--) {
-				return ERR_TIMEOUT;
-			}
-		}
-		spi_write_single(p_spi, tx_data[i]);
+    while (len)
+    {
+        timeout = SPI_TIMEOUT;
+        while (!spi_is_tx_ready(p_spi))
+        {
+            if (!timeout--)
+            {
+                return ERR_TIMEOUT;
+            }
+        }
+        spi_write_single(p_spi, tx_data[i]);
 
-		timeout = SPI_TIMEOUT;
-		while (!spi_is_rx_ready(p_spi)) {
-			if (!timeout--) {
-				return ERR_TIMEOUT;
-			}
-		}
-		spi_read_single(p_spi, &val);
+        timeout = SPI_TIMEOUT;
+        while (!spi_is_rx_ready(p_spi))
+        {
+            if (!timeout--)
+            {
+                return ERR_TIMEOUT;
+            }
+        }
+        spi_read_single(p_spi, &val);
 
-		rx_data[i] = val;
-		i++;
-		len--;
-	}
+        rx_data[i] = val;
+        i++;
+        len--;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
-//! @}
+/*! @}*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h
index a5fd65576334..b01d1e754cf3 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_spi/spi_master.h
@@ -53,42 +53,42 @@
 #include "spi.h"
 
 /*! \name SPI Master Management Configuration */
-//! @{
+/*! @{*/
 #include "conf_spi_master.h"
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 extern "C" {
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
 
-//! Default Configuration of SPI Master Delay BCS
+/*! Default Configuration of SPI Master Delay BCS*/
 #ifndef CONFIG_SPI_MASTER_DELAY_BCS
 #define CONFIG_SPI_MASTER_DELAY_BCS          0
 #endif
 
-//! Default Configuration of SPI Master Bits per Transfer Definition
+/*! Default Configuration of SPI Master Bits per Transfer Definition*/
 #ifndef CONFIG_SPI_MASTER_BITS_PER_TRANSFER
 #define CONFIG_SPI_MASTER_BITS_PER_TRANSFER  SPI_CSR_BITS_8_BIT
 #endif
 
-//! Default Configuration of SPI Master Delay BCT
+/*! Default Configuration of SPI Master Delay BCT*/
 #ifndef CONFIG_SPI_MASTER_DELAY_BCT
 #define CONFIG_SPI_MASTER_DELAY_BCT          0
 #endif
 
-//! Default Configuration of SPI Master Delay BS
+/*! Default Configuration of SPI Master Delay BS*/
 #ifndef CONFIG_SPI_MASTER_DELAY_BS
 #define CONFIG_SPI_MASTER_DELAY_BS           0
 #endif
 
-//! Default Configuration of SPI Master Dummy Field
+/*! Default Configuration of SPI Master Dummy Field*/
 #ifndef CONFIG_SPI_MASTER_DUMMY
 #define CONFIG_SPI_MASTER_DUMMY              0xFF
 #endif
-//! @}
+/*! @}*/
 
 /**
  * \brief Clock phase.
@@ -119,17 +119,17 @@ extern "C" {
 
 #ifndef SPI_TYPE_DEFS
 #define SPI_TYPE_DEFS
-//! SPI Flags Definition
+/*! SPI Flags Definition*/
 typedef uint8_t spi_flags_t;
 
-//! Board SPI Select Id Definition
+/*! Board SPI Select Id Definition*/
 typedef uint32_t board_spi_select_id_t;
 #endif
 
-//! \brief Polled SPI device definition.
+/*! \brief Polled SPI device definition.*/
 struct spi_device {
-	//! Board specific select id
-	board_spi_select_id_t id;
+    /*! Board specific select id*/
+    board_spi_select_id_t id;
 };
 
 /** \brief Initialize the SPI in master mode.
@@ -154,7 +154,7 @@ extern void spi_master_init(Spi *p_spi);
  * \param sel_id    Board specific select id.
  */
 extern void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
-		spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id);
+        spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id);
 
 /**
  * \brief Select the given device on the SPI bus.
@@ -188,7 +188,7 @@ extern void spi_deselect_device(Spi *p_spi, struct spi_device *device);
  */
 static inline void spi_write_single(Spi *p_spi, uint8_t data)
 {
-	spi_put(p_spi, (uint16_t)data);
+    spi_put(p_spi, (uint16_t)data);
 }
 
 /**
@@ -203,7 +203,7 @@ static inline void spi_write_single(Spi *p_spi, uint8_t data)
  * \pre SPI device must be selected with spi_select_device() first.
  */
 extern status_code_t spi_write_packet(Spi *p_spi,
-		const uint8_t *data, size_t len);
+        const uint8_t *data, size_t len);
 
 /** \brief Receive one byte from an SPI device.
  *
@@ -213,7 +213,7 @@ extern status_code_t spi_write_packet(Spi *p_spi,
  */
 static inline void spi_read_single(Spi *p_spi, uint8_t *data)
 {
-	*data = (uint8_t)spi_get(p_spi);
+    *data = (uint8_t)spi_get(p_spi);
 }
 
 /**
@@ -241,12 +241,12 @@ extern status_code_t spi_read_packet(Spi *p_spi, uint8_t *data, size_t len);
  */
 extern status_code_t spi_transceive_packet(Spi *p_spi, uint8_t *tx_data, uint8_t *rx_data, size_t len);
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 }
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
 
-#endif // _SPI_MASTER_H_
+#endif /* _SPI_MASTER_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c
index 7dcaf7668989..81b8921377d8 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.c
@@ -51,13 +51,13 @@
 #include "conf_board.h"
 #endif
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 extern "C" {
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
 
 /*! \brief Enable the USART system clock in SPI master mode.
  *
@@ -68,41 +68,45 @@ void usart_spi_init(Usart *p_usart)
 {
 #if (!SAMG55)
 
-	uint8_t uc_id;
+    uint8_t uc_id;
 
 #ifdef USART0
-	if (p_usart == USART0) {
-		uc_id = ID_USART0;
-	}
+    if (p_usart == USART0)
+    {
+        uc_id = ID_USART0;
+    }
 #endif
 
 #ifdef USART1
-	else if(p_usart == USART1) {
-		uc_id = ID_USART1;
-	}
+    else if(p_usart == USART1)
+    {
+        uc_id = ID_USART1;
+    }
 #endif
 
 #ifdef USART2
-	else if(p_usart == USART2) {
-		uc_id = ID_USART2;
-	}
+    else if(p_usart == USART2)
+    {
+        uc_id = ID_USART2;
+    }
 #endif
 
 #ifdef USART3
-	else if(p_usart == USART3) {
-		uc_id = ID_USART3;
-	}
+    else if(p_usart == USART3)
+    {
+        uc_id = ID_USART3;
+    }
 #endif
 
 #endif
 
 #if SAM4L
-	sysclk_enable_peripheral_clock(p_usart);
+    sysclk_enable_peripheral_clock(p_usart);
 #elif SAMG55
-	flexcom_enable(BOARD_FLEXCOM_USART);
-	flexcom_set_opmode(BOARD_FLEXCOM_USART, FLEXCOM_USART);
+    flexcom_enable(BOARD_FLEXCOM_USART);
+    flexcom_set_opmode(BOARD_FLEXCOM_USART, FLEXCOM_USART);
 #else
-	sysclk_enable_peripheral_clock(uc_id);
+    sysclk_enable_peripheral_clock(uc_id);
 #endif
 }
 
@@ -120,42 +124,42 @@ void usart_spi_init(Usart *p_usart)
  * \param baud_rate Baud rate for communication with slave device in Hz.
  * \param sel_id    Board specific select id.
  */
-void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device, 
+void usart_spi_setup_device(Usart *p_usart, struct usart_spi_device *device,
      spi_flags_t flags, unsigned long baud_rate,
      board_spi_select_id_t sel_id)
 {
-	usart_spi_opt_t opt;
-
-	/* avoid Cppcheck Warning */
-	UNUSED(device);
-	UNUSED(sel_id);
-
-	/* Basic usart SPI configuration. */
-	opt.baudrate = baud_rate;
-	opt.char_length = US_MR_CHRL_8_BIT;
-	opt.spi_mode = flags;
-	opt.channel_mode = US_MR_CHMODE_NORMAL;
-	
-	/* Initialize the USART module as SPI master. */
+    usart_spi_opt_t opt;
+
+    /* avoid Cppcheck Warning */
+    UNUSED(device);
+    UNUSED(sel_id);
+
+    /* Basic usart SPI configuration. */
+    opt.baudrate = baud_rate;
+    opt.char_length = US_MR_CHRL_8_BIT;
+    opt.spi_mode = flags;
+    opt.channel_mode = US_MR_CHMODE_NORMAL;
+
+    /* Initialize the USART module as SPI master. */
 #if (SAM4L)
-	usart_init_spi_master(p_usart, &opt, sysclk_get_pba_hz());
+    usart_init_spi_master(p_usart, &opt, sysclk_get_pba_hz());
 #else
-	usart_init_spi_master(p_usart, &opt, sysclk_get_peripheral_hz());
+    usart_init_spi_master(p_usart, &opt, sysclk_get_peripheral_hz());
 #endif
 
-	usart_enable_rx(p_usart);
-	usart_enable_tx(p_usart);
+    usart_enable_rx(p_usart);
+    usart_enable_tx(p_usart);
 }
 
 /*! \brief Write one byte to an SPI device using USART in SPI mode.
  *
  * \param p_usart Base address of the USART instance.
- * \param data    The data to be sent out. 
+ * \param data    The data to be sent out.
  *
  */
 void usart_spi_write_single(Usart *p_usart, uint8_t data)
 {
-	usart_putchar(p_usart, data);
+    usart_putchar(p_usart, data);
 }
 
 /**
@@ -173,15 +177,16 @@ void usart_spi_write_single(Usart *p_usart, uint8_t data)
  */
 uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len)
 {
-	uint32_t dummy_data;
-	size_t i=0;
-	while(len) {
-		usart_putchar(p_usart, *(data+i));
-		usart_getchar(p_usart, &dummy_data);
-		len--;
-		i++;
-	}
-	return 0;
+    uint32_t dummy_data;
+    size_t i=0;
+    while(len)
+    {
+        usart_putchar(p_usart, *(data+i));
+        usart_getchar(p_usart, &dummy_data);
+        len--;
+        i++;
+    }
+    return 0;
 }
 
 /*! \brief Receive one byte from an SPI device using USART in SPI mode.
@@ -193,12 +198,12 @@ uint32_t usart_spi_write_packet(Usart *p_usart, const uint8_t *data, size_t len)
  */
 void usart_spi_read_single(Usart *p_usart, uint8_t *data)
 {
-	uint32_t temp_data = 0;
-	/* Dummy write one data to slave in order to read data. */
-	usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
+    uint32_t temp_data = 0;
+    /* Dummy write one data to slave in order to read data. */
+    usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
 
-	usart_getchar(p_usart, &temp_data);
-	*data = (uint8_t)temp_data;
+    usart_getchar(p_usart, &temp_data);
+    *data = (uint8_t)temp_data;
 }
 
 /**
@@ -216,20 +221,21 @@ void usart_spi_read_single(Usart *p_usart, uint8_t *data)
  */
 uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len)
 {
-	uint32_t val;
-	uint32_t i = 0;
-
-	while(len) {
-		/* Dummy write one data to slave in order to read data. */
-		usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
-		usart_getchar(p_usart, &val);
-
-		data[i] = (uint8_t)(val & 0xFF);
-		i++;
-		len--;
-	}
-	
-	return 0;
+    uint32_t val;
+    uint32_t i = 0;
+
+    while(len)
+    {
+        /* Dummy write one data to slave in order to read data. */
+        usart_putchar(p_usart, CONFIG_USART_SPI_DUMMY);
+        usart_getchar(p_usart, &val);
+
+        data[i] = (uint8_t)(val & 0xFF);
+        i++;
+        len--;
+    }
+
+    return 0;
 }
 
 /**
@@ -241,10 +247,10 @@ uint32_t usart_spi_read_packet(Usart *p_usart, uint8_t *data, size_t len)
  */
 void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device)
 {
-	/* avoid Cppcheck Warning */
-	UNUSED(device);
-	
-	usart_spi_force_chip_select(p_usart);
+    /* avoid Cppcheck Warning */
+    UNUSED(device);
+
+    usart_spi_force_chip_select(p_usart);
 }
 
 /**
@@ -255,10 +261,10 @@ void usart_spi_select_device(Usart *p_usart, struct usart_spi_device *device)
  */
 void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device)
 {
-	/* avoid Cppcheck Warning */
-	UNUSED(device);
-	
-	usart_spi_release_chip_select(p_usart);
+    /* avoid Cppcheck Warning */
+    UNUSED(device);
+
+    usart_spi_release_chip_select(p_usart);
 }
 
 /*! \brief Check whether there are data in Transmit Holding Register or
@@ -271,7 +277,7 @@ void usart_spi_deselect_device(Usart *p_usart, struct usart_spi_device *device)
  */
 uint32_t usart_spi_is_tx_empty(Usart *p_usart)
 {
-	return usart_is_tx_empty(p_usart);
+    return usart_is_tx_empty(p_usart);
 }
 
 /*! \brief Check whether the USART in SPI master mode contains a received character.
@@ -283,7 +289,7 @@ uint32_t usart_spi_is_tx_empty(Usart *p_usart)
  */
 uint32_t usart_spi_is_rx_ready(Usart *p_usart)
 {
-	return usart_is_rx_ready(p_usart);
+    return usart_is_rx_ready(p_usart);
 }
 
 /*! \brief Check if the USART Transmit Holding Register is empty or not in SPI mode.
@@ -295,7 +301,7 @@ uint32_t usart_spi_is_rx_ready(Usart *p_usart)
  */
 uint32_t usart_spi_is_tx_ready(Usart *p_usart)
 {
-	return usart_is_tx_ready(p_usart);
+    return usart_is_tx_ready(p_usart);
 }
 
 /*! \brief Check if both receive buffers are full.
@@ -308,7 +314,7 @@ uint32_t usart_spi_is_tx_ready(Usart *p_usart)
 uint32_t usart_spi_is_rx_full(Usart *p_usart)
 {
 #if (!SAMV71 && !SAMV70 && !SAME70 && !SAMS70)
-	return usart_is_rx_buf_full(p_usart);
+    return usart_is_rx_buf_full(p_usart);
 #endif
 }
 
@@ -318,8 +324,8 @@ uint32_t usart_spi_is_rx_full(Usart *p_usart)
  */
 void usart_spi_enable(Usart *p_usart)
 {
-	usart_enable_tx(p_usart);
-	usart_enable_rx(p_usart);
+    usart_enable_tx(p_usart);
+    usart_enable_rx(p_usart);
 }
 
 /*! \brief Disable the USART for the specified USART in SPI mode.
@@ -331,14 +337,14 @@ void usart_spi_enable(Usart *p_usart)
  */
 void usart_spi_disable(Usart *p_usart)
 {
-	usart_disable_tx(p_usart);
-	usart_disable_rx(p_usart);
+    usart_disable_tx(p_usart);
+    usart_disable_rx(p_usart);
 }
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 }
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h
index 026c4e302ae4..e0110ec85e56 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/sam_usart_spi/usart_spi.h
@@ -50,40 +50,40 @@
 #include "compiler.h"
 #include "usart.h"
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 extern "C" {
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
 
 /*! \name USART in SPI mode Management Configuration.
  */
-//! @{
+/*! @{*/
 #include "conf_usart_spi.h"
 
-//! Default Configuration of SPI Master Dummy Field
+/*! Default Configuration of SPI Master Dummy Field*/
 #ifndef CONFIG_USART_SPI_DUMMY
-	#define CONFIG_USART_SPI_DUMMY              0xFF
+    #define CONFIG_USART_SPI_DUMMY              0xFF
 #endif
-//! @}
+/*! @}*/
 
 #ifndef SPI_TYPE_DEFS
 #define SPI_TYPE_DEFS
-//! SPI Flags Definition
+/*! SPI Flags Definition*/
 typedef uint8_t spi_flags_t;
 
-//! Board SPI Select Id Definition
+/*! Board SPI Select Id Definition*/
 typedef uint32_t board_spi_select_id_t;
 #endif
 
-typedef uint8_t port_pin_t; 
+typedef uint8_t port_pin_t;
 
-//! \brief Polled SPI device definition.
+/*! \brief Polled SPI device definition.*/
 struct usart_spi_device {
-	/* Board specific select id. */
-	port_pin_t	id;
+    /* Board specific select id. */
+    port_pin_t  id;
 };
 
 void usart_spi_init(Usart *p_usart);
@@ -102,12 +102,12 @@ uint32_t usart_spi_is_rx_full(Usart *p_usart);
 void usart_spi_enable(Usart *p_usart);
 void usart_spi_disable(Usart *p_usart);
 
-/// @cond 0
+/*/ @cond 0*/
 /**INDENT-OFF**/
 #ifdef __cplusplus
 }
 #endif
 /**INDENT-ON**/
-/// @endcond
+/*/ @endcond*/
 
 #endif  /* _USART_SPI_H_ */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h
index e92f4ca5acb2..d8e22bbade63 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/spi_master.h
@@ -100,7 +100,7 @@
  * @{
  */
 
-//! @}
+/*! @}*/
 
 /**
  * \page common_spi_master_quickstart Quick Start Guide for the SPI Master Driver
@@ -134,26 +134,26 @@
  * \subsection spi_master_xmega_basic_setup_code Example code
  * Add to application C-file (e.g. main.c):
  * \code
-	   void spi_init_pins(void)
-	   {
-	       ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+       void spi_init_pins(void)
+       {
+           ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
 
-	       ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
-	       ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
-	       ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
-	       ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
-	   }
+           ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
+           ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+           ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
+           ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+       }
 
-	   void spi_init_module(void)
-	   {
-	      struct spi_device spi_device_conf = {
-	          .id = IOPORT_CREATE_PIN(PORTD, 1)
-	      };
+       void spi_init_module(void)
+       {
+          struct spi_device spi_device_conf = {
+              .id = IOPORT_CREATE_PIN(PORTD, 1)
+          };
 
-	      spi_master_init(&SPID);
-	      spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
-	      spi_enable(&SPID);
-	   }
+          spi_master_init(&SPID);
+          spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
+          spi_enable(&SPID);
+       }
 \endcode
  *
  * \subsection spi_master_xmega_basic_setup Workflow
@@ -164,58 +164,58 @@
  * the ATxmega32A4U device).
  *  -# Set the pin used for slave select as output high:
  *    \code
-	ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+    ioport_configure_port_pin(&PORTD, PIN1_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
 \endcode
  *  -# Enable pull-up on own chip select (SS):
  *    \code
-	ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
+    ioport_configure_port_pin(&PORTD, PIN4_bm, IOPORT_PULL_UP | IOPORT_DIR_INPUT);
 \endcode
  *    \attention If this pin is pulled low the SPI module will go into slave mode.
  *  -# Set MOSI and SCL as output high, and set MISO as input:
  *    \code
-	ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
-	ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
-	ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+    ioport_configure_port_pin(&PORTD, PIN5_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
+    ioport_configure_port_pin(&PORTD, PIN6_bm, IOPORT_DIR_INPUT);
+    ioport_configure_port_pin(&PORTD, PIN7_bm, IOPORT_INIT_HIGH | IOPORT_DIR_OUTPUT);
 \endcode
  * -# Define the SPI device configuration struct to describe which pin the
  * slave select (slave chip select) is connected to, in this case the slave
  * select pin has been connected to PORTD pin 1 (PD1):
  *  - \code
-	struct spi_device spi_device_conf = {
-	    .id = IOPORT_CREATE_PIN(PORTD, 1)
-	};
+    struct spi_device spi_device_conf = {
+        .id = IOPORT_CREATE_PIN(PORTD, 1)
+    };
 \endcode
  * -# Initialize the SPI module, in this case SPI on PORTD has been chosen:
  *  - \code
-	spi_master_init(&SPID);
+    spi_master_init(&SPID);
 \endcode
  * -# Setup the SPI master module for a specific device:
  *  - \code
-	spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
+    spi_master_setup_device(&SPID, &spi_device_conf, SPI_MODE_0, 1000000, 0);
 \endcode
  *  - \note The last argument, which is zero in this case, can be ignored and is
  *  only included for compatibility purposes.
  * -# Then enable the SPI:
  *  - \code
-	spi_enable(&SPID);
+    spi_enable(&SPID);
 \endcode
  *
  * \section spi_master_xmega_basic_usage Usage steps
  * \subsection spi_master_xmega_basic_usage_code Example code
  * Add to, e.g., the main loop in the application C-file:
  * \code
-	   uint8_t data_buffer[1] = {0xAA};
+       uint8_t data_buffer[1] = {0xAA};
 
-	   struct spi_device spi_device_conf = {
-	       .id = IOPORT_CREATE_PIN(PORTD, 1)
-	   };
+       struct spi_device spi_device_conf = {
+           .id = IOPORT_CREATE_PIN(PORTD, 1)
+       };
 
-	   spi_select_device(&SPID, &spi_device_conf);
+       spi_select_device(&SPID, &spi_device_conf);
 
-	   spi_write_packet(&SPID, data_buffer, 1);
-	   spi_read_packet(&SPID, data_buffer, 1);
+       spi_write_packet(&SPID, data_buffer, 1);
+       spi_read_packet(&SPID, data_buffer, 1);
 
-	   spi_deselect_device(&SPID, &spi_device_conf);
+       spi_deselect_device(&SPID, &spi_device_conf);
 \endcode
  *
  * \subsection spi_master_xmega_basic_usage_flow Workflow
@@ -223,15 +223,15 @@
  * a single byte buffer is used. The buffer can be of arbitrary size as long as
  * there is space left in SRAM:
  *  - \code
-	uint8_t data_buffer[1] = {0xAA};
+    uint8_t data_buffer[1] = {0xAA};
 \endcode
  * -# Define the SPI device configuration struct to describe which pin the
  * slave select (slave chip select) is connected to, in this case the slave
  * select pin has been connected to PORTD pin 1 (PD1):
  *  - \code
-	struct spi_device spi_device_conf = {
-	    .id = IOPORT_CREATE_PIN(PORTD, 1)
-	};
+    struct spi_device spi_device_conf = {
+        .id = IOPORT_CREATE_PIN(PORTD, 1)
+    };
 \endcode
  *  - \note As this struct is the same for both the initializing part and the usage
  * part it could be a good idea to make the struct global, and hence accessible
@@ -239,24 +239,24 @@
  * create the struct in the main function and pass the address of the struct to
  * the spi_init_module() function, e.g.:
  *  \code
-	   void spi_init_module(struct spi_device *spi_device_conf)
-	   {
-	       ...
+       void spi_init_module(struct spi_device *spi_device_conf)
+       {
+           ...
 
-	       spi_master_setup_device(&SPID, spi_device_conf, SPI_MODE_0, 1000000, 0);
+           spi_master_setup_device(&SPID, spi_device_conf, SPI_MODE_0, 1000000, 0);
 
-	       ...
-	   }
+           ...
+       }
 \endcode
  * -# Write data to the SPI slave device, in this case write one byte from the
  * data_buffer:
  *  - \code
-	spi_write_packet(&SPID, data_buffer, 1);
+    spi_write_packet(&SPID, data_buffer, 1);
 \endcode
  * -# Read data from the SPI slave device, in this case read one byte and put it
  * into the data_buffer:
  *  - \code
-	spi_read_packet(&SPID, data_buffer, 1);
+    spi_read_packet(&SPID, data_buffer, 1);
 \endcode
  *  - \attention As the SPI works as a shift register so that data is shifted in at
  * the same time as data is shifted out a read operation will mean that a dummy
@@ -265,7 +265,7 @@
  * file.
  * -# When read and write operations is done de-select the slave:
  *  - \code
-	spi_deselect_device(&SPID, &spi_device_conf);
+    spi_deselect_device(&SPID, &spi_device_conf);
 \endcode
  *
  */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h b/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h
index 92b407ff5c00..972fd6eff082 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/spi/usart_spi.h
@@ -99,6 +99,6 @@
  * @{
  */
 
-//! @}
+/*! @}*/
 
 #endif /* USART_SPI_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c
index 9b3b52b70357..d4ed7f92a3e1 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.c
@@ -57,7 +57,7 @@
  */
 
 
-//_____ I N C L U D E S ____________________________________________________
+/*_____ I N C L U D E S ____________________________________________________*/
 
 #include "compiler.h"
 #include "preprocessor.h"
@@ -68,13 +68,13 @@
 #include "ctrl_access.h"
 
 
-//_____ D E F I N I T I O N S ______________________________________________
+/*_____ D E F I N I T I O N S ______________________________________________*/
 
 #ifdef FREERTOS_USED
 
 /*! \name LUN Access Protection Macros
  */
-//! @{
+/*! @{*/
 
 /*! \brief Locks accesses to LUNs.
  *
@@ -86,16 +86,16 @@
  */
 #define Ctrl_access_unlock()  xSemaphoreGive(ctrl_access_semphr)
 
-//! @}
+/*! @}*/
 
-//! Handle to the semaphore protecting accesses to LUNs.
+/*! Handle to the semaphore protecting accesses to LUNs.*/
 static xSemaphoreHandle ctrl_access_semphr = NULL;
 
 #else
 
 /*! \name LUN Access Protection Macros
  */
-//! @{
+/*! @{*/
 
 /*! \brief Locks accesses to LUNs.
  *
@@ -107,9 +107,9 @@ static xSemaphoreHandle ctrl_access_semphr = NULL;
  */
 #define Ctrl_access_unlock()
 
-//! @}
+/*! @}*/
 
-#endif  // FREERTOS_USED
+#endif  /* FREERTOS_USED*/
 
 
 #if MAX_LUN
@@ -170,7 +170,7 @@ static xSemaphoreHandle ctrl_access_semphr = NULL;
   }
 #endif
 
-//! LUN descriptor table.
+/*! LUN descriptor table.*/
 static const struct
 {
   Ctrl_status (*test_unit_ready)(void);
@@ -249,20 +249,20 @@ bool g_wr_protect;
 
 /*! \name Control Interface
  */
-//! @{
+/*! @{*/
 
 
 #ifdef FREERTOS_USED
 
 bool ctrl_access_init(void)
 {
-  // If the handle to the protecting semaphore is not valid,
+  /* If the handle to the protecting semaphore is not valid,*/
   if (!ctrl_access_semphr)
   {
-    // try to create the semaphore.
+    /* try to create the semaphore.*/
     vSemaphoreCreateBinary(ctrl_access_semphr);
 
-    // If the semaphore could not be created, there is no backup solution.
+    /* If the semaphore could not be created, there is no backup solution.*/
     if (!ctrl_access_semphr) return false;
   }
 
@@ -276,16 +276,16 @@ bool ctrl_access_init(void)
  */
 static bool ctrl_access_lock(void)
 {
-  // If the semaphore could not be created, there is no backup solution.
+  /* If the semaphore could not be created, there is no backup solution.*/
   if (!ctrl_access_semphr) return false;
 
-  // Wait for the semaphore.
+  /* Wait for the semaphore.*/
   while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY));
 
   return true;
 }
 
-#endif  // FREERTOS_USED
+#endif  /* FREERTOS_USED*/
 
 
 U8 get_nb_lun(void)
@@ -475,14 +475,14 @@ const char *mem_name(U8 lun)
 }
 
 
-//! @}
+/*! @}*/
 
 
 #if ACCESS_USB == true
 
 /*! \name MEM <-> USB Interface
  */
-//! @{
+/*! @{*/
 
 
 Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector)
@@ -525,16 +525,16 @@ Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector)
 }
 
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_USB == true
+#endif  /* ACCESS_USB == true*/
 
 
 #if ACCESS_MEM_TO_RAM == true
 
 /*! \name MEM <-> RAM Interface
  */
-//! @{
+/*! @{*/
 
 
 Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram)
@@ -591,16 +591,16 @@ Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram)
 }
 
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_MEM_TO_RAM == true
+#endif  /* ACCESS_MEM_TO_RAM == true*/
 
 
 #if ACCESS_STREAM == true
 
 /*! \name Streaming MEM <-> MEM Interface
  */
-//! @{
+/*! @{*/
 
 
   #if ACCESS_MEM_TO_MEM == true
@@ -622,7 +622,7 @@ Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_ad
   return status;
 }
 
-  #endif  // ACCESS_MEM_TO_MEM == true
+  #endif  /* ACCESS_MEM_TO_MEM == true*/
 
 
 Ctrl_status stream_state(U8 id)
@@ -639,6 +639,6 @@ U16 stream_stop(U8 id)
 }
 
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_STREAM == true
+#endif  /* ACCESS_STREAM == true*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h
index af6c8ceb963e..9792efb53bf9 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/ctrl_access.h
@@ -80,19 +80,19 @@ extern "C" {
 #define SECTOR_SIZE  512
 #endif
 
-//! Status returned by CTRL_ACCESS interfaces.
+/*! Status returned by CTRL_ACCESS interfaces.*/
 typedef enum
 {
-  CTRL_GOOD       = PASS,     //!< Success, memory ready.
-  CTRL_FAIL       = FAIL,     //!< An error occurred.
-  CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged.
-  CTRL_BUSY       = FAIL + 2  //!< Memory not initialized or changed.
+  CTRL_GOOD       = PASS,     /*!< Success, memory ready.*/
+  CTRL_FAIL       = FAIL,     /*!< An error occurred.*/
+  CTRL_NO_PRESENT = FAIL + 1, /*!< Memory unplugged.*/
+  CTRL_BUSY       = FAIL + 2  /*!< Memory not initialized or changed.*/
 } Ctrl_status;
 
 
-// FYI: Each Logical Unit Number (LUN) corresponds to a memory.
+/* FYI: Each Logical Unit Number (LUN) corresponds to a memory.*/
 
-// Check LUN defines.
+/* Check LUN defines.*/
 #ifndef LUN_0
   #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h
 #endif
@@ -123,8 +123,8 @@ typedef enum
 
 /*! \name LUN IDs
  */
-//! @{
-#define LUN_ID_0        (0)                 //!< First static LUN.
+/*! @{*/
+#define LUN_ID_0        (0)                 /*!< First static LUN.*/
 #define LUN_ID_1        (LUN_ID_0 + LUN_0)
 #define LUN_ID_2        (LUN_ID_1 + LUN_1)
 #define LUN_ID_3        (LUN_ID_2 + LUN_2)
@@ -132,12 +132,12 @@ typedef enum
 #define LUN_ID_5        (LUN_ID_4 + LUN_4)
 #define LUN_ID_6        (LUN_ID_5 + LUN_5)
 #define LUN_ID_7        (LUN_ID_6 + LUN_6)
-#define MAX_LUN         (LUN_ID_7 + LUN_7)  //!< Number of static LUNs.
-#define LUN_ID_USB      (MAX_LUN)           //!< First dynamic LUN (USB host mass storage).
-//! @}
+#define MAX_LUN         (LUN_ID_7 + LUN_7)  /*!< Number of static LUNs.*/
+#define LUN_ID_USB      (MAX_LUN)           /*!< First dynamic LUN (USB host mass storage).*/
+/*! @}*/
 
 
-// Include LUN header files.
+/* Include LUN header files.*/
 #if LUN_0 == ENABLE
   #include LUN_0_INCLUDE
 #endif
@@ -167,7 +167,7 @@ typedef enum
 #endif
 
 
-// Check the configuration of write protection in conf_access.h.
+/* Check the configuration of write protection in conf_access.h.*/
 #ifndef GLOBAL_WR_PROTECT
   #error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h
 #endif
@@ -175,7 +175,7 @@ typedef enum
 
 #if GLOBAL_WR_PROTECT == true
 
-//! Write protect.
+/*! Write protect.*/
 extern bool g_wr_protect;
 
 #endif
@@ -183,7 +183,7 @@ extern bool g_wr_protect;
 
 /*! \name Control Interface
  */
-//! @{
+/*! @{*/
 
 #ifdef FREERTOS_USED
 
@@ -193,7 +193,7 @@ extern bool g_wr_protect;
  */
 extern bool ctrl_access_init(void);
 
-#endif  // FREERTOS_USED
+#endif  /* FREERTOS_USED*/
 
 /*! \brief Returns the number of LUNs.
  *
@@ -277,14 +277,14 @@ extern bool mem_removal(U8 lun);
  */
 extern const char *mem_name(U8 lun);
 
-//! @}
+/*! @}*/
 
 
 #if ACCESS_USB == true
 
 /*! \name MEM <-> USB Interface
  */
-//! @{
+/*! @{*/
 
 /*! \brief Transfers data from the memory to USB.
  *
@@ -306,16 +306,16 @@ extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector);
  */
 extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector);
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_USB == true
+#endif  /* ACCESS_USB == true*/
 
 
 #if ACCESS_MEM_TO_RAM == true
 
 /*! \name MEM <-> RAM Interface
  */
-//! @{
+/*! @{*/
 
 /*! \brief Copies 1 data sector from the memory to RAM.
  *
@@ -337,18 +337,18 @@ extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram);
  */
 extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram);
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_MEM_TO_RAM == true
+#endif  /* ACCESS_MEM_TO_RAM == true*/
 
 
 #if ACCESS_STREAM == true
 
 /*! \name Streaming MEM <-> MEM Interface
  */
-//! @{
+/*! @{*/
 
-//! Erroneous streaming data transfer ID.
+/*! Erroneous streaming data transfer ID.*/
 #define ID_STREAM_ERR         0xFF
 
   #if ACCESS_MEM_TO_MEM == true
@@ -365,7 +365,7 @@ extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram);
  */
 extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector);
 
-  #endif  // ACCESS_MEM_TO_MEM == true
+  #endif  /* ACCESS_MEM_TO_MEM == true*/
 
 /*! \brief Returns the state of a streaming data transfer.
  *
@@ -387,9 +387,9 @@ extern Ctrl_status stream_state(U8 id);
  */
 extern U16 stream_stop(U8 id);
 
-//! @}
+/*! @}*/
 
-#endif  // ACCESS_STREAM == true
+#endif  /* ACCESS_STREAM == true*/
 
 /**
  * \}
@@ -399,4 +399,4 @@ extern U16 stream_stop(U8 id);
 }
 #endif
 
-#endif  // _CTRL_ACCESS_H_
+#endif  /* _CTRL_ACCESS_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h
index 25e376c84a1c..3d04c1b2f3a1 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ctrl_access/module_config/conf_access.h
@@ -49,7 +49,7 @@
  */
 
 
- //! Configuration of ctrl_access which is an abstraction layer for memory interfaces (common/services/storage/ctrl_access)
+ /*! Configuration of ctrl_access which is an abstraction layer for memory interfaces (common/services/storage/ctrl_access)*/
 
 #ifndef _CONF_ACCESS_H_
 #define _CONF_ACCESS_H_
@@ -60,56 +60,56 @@
 
 /*! \name Activation of Logical Unit Numbers
  */
-//! @{
+/*! @{*/
 #ifdef VIRTUAL_MEMORY_ENABLE
-#define LUN_0                ENABLE   //!< Enable On-Chip Virtual Memory.
+#define LUN_0                ENABLE   /*!< Enable On-Chip Virtual Memory.*/
 #else
-#define LUN_0                DISABLE  //!< Disable On-Chip Virtual Memory.
+#define LUN_0                DISABLE  /*!< Disable On-Chip Virtual Memory.*/
 #endif
 
 #ifdef AT45DBX_ENABLE
-#define LUN_1                ENABLE   //!< Enable AT45DBX Data Flash.
+#define LUN_1                ENABLE   /*!< Enable AT45DBX Data Flash.*/
 #else
-#define LUN_1                DISABLE  //!< Disable AT45DBX Data Flash.
+#define LUN_1                DISABLE  /*!< Disable AT45DBX Data Flash.*/
 #endif
 
-//! New setting for SD/MMC stack in common folder
+/*! New setting for SD/MMC stack in common folder*/
 #ifdef SD_MMC_ENABLE
-#define LUN_2                ENABLE   //!< Enable common SD/MMC stack
+#define LUN_2                ENABLE   /*!< Enable common SD/MMC stack*/
 #define LUN_3                ENABLE
 #else
-#define LUN_2                DISABLE  //!< Disable common SD/MMC stack
+#define LUN_2                DISABLE  /*!< Disable common SD/MMC stack*/
 #define LUN_3                DISABLE
 #endif
 
-//! Old setting for SD/MMC stack in AVR folder
+/*! Old setting for SD/MMC stack in AVR folder*/
 #ifdef SD_MMC_SPI_ENABLE
-#define LUN_4                ENABLE   //!< Enable SD/MMC Card over SPI or SPI.
+#define LUN_4                ENABLE   /*!< Enable SD/MMC Card over SPI or SPI.*/
 #else
-#define LUN_4                DISABLE  //!< Disable SD/MMC Card over SPI or SPI.
+#define LUN_4                DISABLE  /*!< Disable SD/MMC Card over SPI or SPI.*/
 #endif
 
-//! Old setting for SD/MMC stack in AVR folder
+/*! Old setting for SD/MMC stack in AVR folder*/
 #ifdef SD_MMC_MCI_ENABLE
-#define LUN_5                ENABLE   //!< Enable SD/MMC Card over MCI or MCI.
+#define LUN_5                ENABLE   /*!< Enable SD/MMC Card over MCI or MCI.*/
 #else
-#define LUN_5                DISABLE  //!< Disable SD/MMC Card over MCI or MCI.
+#define LUN_5                DISABLE  /*!< Disable SD/MMC Card over MCI or MCI.*/
 #endif
 
 #define LUN_6                DISABLE
 #define LUN_7                DISABLE
 
 #ifdef USB_MASS_STORAGE_ENABLE
-#define LUN_USB              ENABLE   //!< Enable Host Mass-Storage Memory.
+#define LUN_USB              ENABLE   /*!< Enable Host Mass-Storage Memory.*/
 #else
-#define LUN_USB              DISABLE  //!< Disable Host Mass-Storage Memory.
+#define LUN_USB              DISABLE  /*!< Disable Host Mass-Storage Memory.*/
 #endif
 
-//! @}
+/*! @}*/
 
 /*! \name LUN 0 Definitions
  */
-//! @{
+/*! @{*/
 #define VIRTUAL_MEM                             LUN_0
 #define LUN_ID_VIRTUAL_MEM                      LUN_ID_0
 #define LUN_0_INCLUDE                           "virtual_mem.h"
@@ -123,11 +123,11 @@
 #define Lun_0_mem_2_ram                         virtual_mem_2_ram
 #define Lun_0_ram_2_mem                         virtual_ram_2_mem
 #define LUN_0_NAME                              "\"On-Chip Virtual Memory\""
-//! @}
+/*! @}*/
 
 /*! \name LUN 1 Definitions
  */
-//! @{
+/*! @{*/
 #define AT45DBX_MEM                             LUN_1
 #define LUN_ID_AT45DBX_MEM                      LUN_ID_1
 #define LUN_1_INCLUDE                           "at45dbx_mem.h"
@@ -141,11 +141,11 @@
 #define Lun_1_mem_2_ram                         at45dbx_df_2_ram
 #define Lun_1_ram_2_mem                         at45dbx_ram_2_df
 #define LUN_1_NAME                              "\"AT45DBX Data Flash\""
-//! @}
+/*! @}*/
 
 /*! \name LUN 2 Definitions
  */
-//! @{
+/*! @{*/
 #define SD_MMC_0_MEM                            LUN_2
 #define LUN_ID_SD_MMC_0_MEM                     LUN_ID_2
 #define LUN_2_INCLUDE                           "sd_mmc_mem.h"
@@ -159,11 +159,11 @@
 #define Lun_2_mem_2_ram                         sd_mmc_mem_2_ram_0
 #define Lun_2_ram_2_mem                         sd_mmc_ram_2_mem_0
 #define LUN_2_NAME                              "\"SD/MMC Card Slot 0\""
-//! @}
+/*! @}*/
 
 /*! \name LUN 3 Definitions
  */
-//! @{
+/*! @{*/
 #define SD_MMC_1_MEM                            LUN_3
 #define LUN_ID_SD_MMC_1_MEM                     LUN_ID_3
 #define LUN_3_INCLUDE                           "sd_mmc_mem.h"
@@ -177,11 +177,11 @@
 #define Lun_3_mem_2_ram                         sd_mmc_mem_2_ram_1
 #define Lun_3_ram_2_mem                         sd_mmc_ram_2_mem_1
 #define LUN_3_NAME                              "\"SD/MMC Card Slot 1\""
-//! @}
+/*! @}*/
 
 /*! \name LUN 4 Definitions
  */
-//! @{
+/*! @{*/
 #define SD_MMC_SPI_MEM                          LUN_4
 #define LUN_ID_SD_MMC_SPI_MEM                   LUN_ID_4
 #define LUN_4_INCLUDE                           "sd_mmc_spi_mem.h"
@@ -195,11 +195,11 @@
 #define Lun_4_mem_2_ram                         sd_mmc_spi_mem_2_ram
 #define Lun_4_ram_2_mem                         sd_mmc_spi_ram_2_mem
 #define LUN_4_NAME                              "\"SD/MMC Card over SPI\""
-//! @}
+/*! @}*/
 
 /*! \name LUN 5 Definitions
  */
-//! @{
+/*! @{*/
 #define SD_MMC_MCI_0_MEM                        LUN_5
 #define LUN_ID_SD_MMC_MCI_0_MEM                 LUN_ID_5
 #define LUN_5_INCLUDE                           "sd_mmc_mci_mem.h"
@@ -213,11 +213,11 @@
 #define Lun_5_mem_2_ram                         sd_mmc_mci_mem_2_ram_0
 #define Lun_5_ram_2_mem                         sd_mmc_mci_ram_2_mem_0
 #define LUN_5_NAME                              "\"SD/MMC Card over MCI Slot 0\""
-//! @}
+/*! @}*/
 
 /*! \name USB LUNs Definitions
  */
-//! @{
+/*! @{*/
 #define MEM_USB                                 LUN_USB
 #define LUN_ID_MEM_USB                          LUN_ID_USB
 #define LUN_USB_INCLUDE                         "uhi_msc_mem.h"
@@ -231,7 +231,7 @@
 #define Lun_usb_mem_2_ram(addr, ram)            uhi_msc_mem_read_10_ram(addr, ram)
 #define Lun_usb_ram_2_mem(addr, ram)            uhi_msc_mem_write_10_ram(addr, ram)
 #define LUN_USB_NAME                            "\"Host Mass-Storage Memory\""
-//! @}
+/*! @}*/
 
 /*! \name Actions Associated with Memory Accesses
  *
@@ -239,44 +239,44 @@
  *
  * \warning Be careful not to waste time in order not to disturb the functions.
  */
-//! @{
+/*! @{*/
 #define memory_start_read_action(nb_sectors)
 #define memory_stop_read_action()
 #define memory_start_write_action(nb_sectors)
 #define memory_stop_write_action()
-//! @}
+/*! @}*/
 
 /*! \name Activation of Interface Features
  */
-//! @{
+/*! @{*/
 #ifdef ACCESS_USB_ENABLED
-#define ACCESS_USB           true  //!< MEM <-> USB interface.
+#define ACCESS_USB           true  /*!< MEM <-> USB interface.*/
 #else
-#define ACCESS_USB           false //!< MEM <-> USB interface.
+#define ACCESS_USB           false /*!< MEM <-> USB interface.*/
 #endif
 
 #ifdef ACCESS_MEM_TO_RAM_ENABLED
-#define ACCESS_MEM_TO_RAM    true  //!< MEM <-> RAM interface.
+#define ACCESS_MEM_TO_RAM    true  /*!< MEM <-> RAM interface.*/
 #else
-#define ACCESS_MEM_TO_RAM    false //!< MEM <-> RAM interface.
+#define ACCESS_MEM_TO_RAM    false /*!< MEM <-> RAM interface.*/
 #endif
 
-#define ACCESS_STREAM        false //!< Streaming MEM <-> MEM interface.
-#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode.
-#define ACCESS_MEM_TO_MEM    false //!< MEM <-> MEM interface.
-#define ACCESS_CODEC         false //!< Codec interface.
-//! @}
+#define ACCESS_STREAM        false /*!< Streaming MEM <-> MEM interface.*/
+#define ACCESS_STREAM_RECORD false /*!< Streaming MEM <-> MEM interface in record mode.*/
+#define ACCESS_MEM_TO_MEM    false /*!< MEM <-> MEM interface.*/
+#define ACCESS_CODEC         false /*!< Codec interface.*/
+/*! @}*/
 
 /*! \name Specific Options for Access Control
  */
-//! @{
-#define GLOBAL_WR_PROTECT    false //!< Management of a global write protection.
-//! @}
+/*! @{*/
+#define GLOBAL_WR_PROTECT    false /*!< Management of a global write protection.*/
+/*! @}*/
 
 /*! \name Sector size option for different storage media.
  */
-//! @{
+/*! @{*/
 #define SECTOR_SIZE  512
-//! @}
+/*! @}*/
 
-#endif  // _CONF_ACCESS_H_
+#endif  /* _CONF_ACCESS_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c
index 680bf780b484..db13ec7d0097 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.c
@@ -55,16 +55,18 @@
  */
 static uint32_t count_bits_in_byte(uint8_t byte)
 {
-	uint32_t count = 0;
-
-	while (byte > 0) {
-		if (byte & 1) {
-			count++;
-		}
-		byte >>= 1;
-	}
-
-	return count;
+    uint32_t count = 0;
+
+    while (byte > 0)
+    {
+        if (byte & 1)
+        {
+            count++;
+        }
+        byte >>= 1;
+    }
+
+    return count;
 }
 
 /**
@@ -74,8 +76,8 @@ static uint32_t count_bits_in_byte(uint8_t byte)
  */
 static uint32_t count_bits_in_code256(uint8_t *code)
 {
-	return count_bits_in_byte(code[0]) + count_bits_in_byte(code[1]) +
-			count_bits_in_byte(code[2]);
+    return count_bits_in_byte(code[0]) + count_bits_in_byte(code[1]) +
+            count_bits_in_byte(code[2]);
 }
 
 /**
@@ -86,123 +88,134 @@ static uint32_t count_bits_in_code256(uint8_t *code)
  */
 static void compute256(const uint8_t *data, uint8_t *code)
 {
-	uint32_t i;
-	uint8_t column_sum = 0;
-	uint8_t even_line_code = 0;
-	uint8_t odd_line_code = 0;
-	uint8_t even_column_code = 0;
-	uint8_t odd_column_code = 0;
-
-	/* 
-	 * Xor all bytes together to get the column sum.
-	 * At the same time, calculate the even and odd line codes.
-	 */
-	for (i = 0; i < 256; i++) {
-		column_sum ^= data[i];
-
-		/* 
-		 * If the xor sum of the byte is 0, then this byte has no incidence on
-		 * the computed code. So check if the sum is 1.
-		 */
-		if ((count_bits_in_byte(data[i]) & 1) == 1) {
-			/*
-			 * Parity groups are formed by forcing a particular index bit to 0
-			 * (even) or 1 (odd).
-			 * Example on one byte:
-			 *
-			 * bits (dec)  7   6   5   4   3   2   1   0
-			 *      (bin) 111 110 101 100 011 010 001 000
-			 *                            '---'---'---'----------.
-			 *                                                   |
-			 * groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4     |
-			 *        P2' ooooooo eeeeeee ooooooo eeeeeee P2     |
-			 *        P1' ooo eee ooo eee ooo eee ooo eee P1     |
-			 *                                                   |
-			 * We can see that:                                  |
-			 *  - P4  -> bit 2 of index is 0 --------------------'
-			 *  - P4' -> bit 2 of index is 1.
-			 *  - P2  -> bit 1 of index if 0.
-			 *  - etc...
-			 * We deduce that a bit position has an impact on all even Px if
-			 * the log2(x)nth bit of its index is 0
-			 *     ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
-			 * and on all odd Px' if the log2(x)nth bit of its index is 1
-			 *     ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
-			 *
-			 * As such, we calculate all the possible Px and Px' values at the
-			 * same time in two variables, even_line_code and odd_line_code, such as
-			 *     even_line_code bits: P128  P64  P32  P16  P8  P4  P2  P1
-			 *     odd_line_code  bits: P128' P64' P32' P16' P8' P4' P2' P1'
-			 */
-			even_line_code ^= (255 - i);
-			odd_line_code ^= i;
-		}
-	}
-
-	/*
-	 * At this point, we have the line parities, and the column sum. First, We
-	 * must calculate the parity group values on the column sum.
-	 */
-	for (i = 0; i < 8; i++) {
-		if (column_sum & 1) {
-			even_column_code ^= (7 - i);
-			odd_column_code ^= i;
-		}
-		column_sum >>= 1;
-	}
-
-	/*
-	 * Now, we must interleave the parity values, to obtain the following layout:
-	 * Code[0] = Line1
-	 * Code[1] = Line2
-	 * Code[2] = Column
-	 * Line = Px' Px P(x-1)- P(x-1) ...
-	 * Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
-	 */
-	code[0] = 0;
-	code[1] = 0;
-	code[2] = 0;
-
-	for (i = 0; i < 4; i++) {
-		code[0] <<= 2;
-		code[1] <<= 2;
-		code[2] <<= 2;
-
-		/* Line 1 */
-		if ((odd_line_code & 0x80) != 0) {
-			code[0] |= 2;
-		}
-
-		if ((even_line_code & 0x80) != 0) {
-			code[0] |= 1;
-		}
-		/* Line 2 */
-		if ((odd_line_code & 0x08) != 0) {
-			code[1] |= 2;
-		}
-
-		if ((even_line_code & 0x08) != 0) {
-			code[1] |= 1;
-		}
-		/* Column */
-		if ((odd_column_code & 0x04) != 0) {
-			code[2] |= 2;
-		}
-
-		if ((even_column_code & 0x04) != 0) {
-			code[2] |= 1;
-		}
-
-		odd_line_code <<= 1;
-		even_line_code <<= 1;
-		odd_column_code <<= 1;
-		even_column_code <<= 1;
-	}
-
-	/* Invert codes (linux compatibility) */
-	code[0] = (~(uint32_t) code[0]);
-	code[1] = (~(uint32_t) code[1]);
-	code[2] = (~(uint32_t) code[2]);
+    uint32_t i;
+    uint8_t column_sum = 0;
+    uint8_t even_line_code = 0;
+    uint8_t odd_line_code = 0;
+    uint8_t even_column_code = 0;
+    uint8_t odd_column_code = 0;
+
+    /*
+     * Xor all bytes together to get the column sum.
+     * At the same time, calculate the even and odd line codes.
+     */
+    for (i = 0; i < 256; i++)
+    {
+        column_sum ^= data[i];
+
+        /*
+         * If the xor sum of the byte is 0, then this byte has no incidence on
+         * the computed code. So check if the sum is 1.
+         */
+        if ((count_bits_in_byte(data[i]) & 1) == 1)
+        {
+            /*
+             * Parity groups are formed by forcing a particular index bit to 0
+             * (even) or 1 (odd).
+             * Example on one byte:
+             *
+             * bits (dec)  7   6   5   4   3   2   1   0
+             *      (bin) 111 110 101 100 011 010 001 000
+             *                            '---'---'---'----------.
+             *                                                   |
+             * groups P4' ooooooooooooooo eeeeeeeeeeeeeee P4     |
+             *        P2' ooooooo eeeeeee ooooooo eeeeeee P2     |
+             *        P1' ooo eee ooo eee ooo eee ooo eee P1     |
+             *                                                   |
+             * We can see that:                                  |
+             *  - P4  -> bit 2 of index is 0 --------------------'
+             *  - P4' -> bit 2 of index is 1.
+             *  - P2  -> bit 1 of index if 0.
+             *  - etc...
+             * We deduce that a bit position has an impact on all even Px if
+             * the log2(x)nth bit of its index is 0
+             *     ex: log2(4) = 2, bit2 of the index must be 0 (-> 0 1 2 3)
+             * and on all odd Px' if the log2(x)nth bit of its index is 1
+             *     ex: log2(2) = 1, bit1 of the index must be 1 (-> 0 1 4 5)
+             *
+             * As such, we calculate all the possible Px and Px' values at the
+             * same time in two variables, even_line_code and odd_line_code, such as
+             *     even_line_code bits: P128  P64  P32  P16  P8  P4  P2  P1
+             *     odd_line_code  bits: P128' P64' P32' P16' P8' P4' P2' P1'
+             */
+            even_line_code ^= (255 - i);
+            odd_line_code ^= i;
+        }
+    }
+
+    /*
+     * At this point, we have the line parities, and the column sum. First, We
+     * must calculate the parity group values on the column sum.
+     */
+    for (i = 0; i < 8; i++)
+    {
+        if (column_sum & 1)
+        {
+            even_column_code ^= (7 - i);
+            odd_column_code ^= i;
+        }
+        column_sum >>= 1;
+    }
+
+    /*
+     * Now, we must interleave the parity values, to obtain the following layout:
+     * Code[0] = Line1
+     * Code[1] = Line2
+     * Code[2] = Column
+     * Line = Px' Px P(x-1)- P(x-1) ...
+     * Column = P4' P4 P2' P2 P1' P1 PadBit PadBit
+     */
+    code[0] = 0;
+    code[1] = 0;
+    code[2] = 0;
+
+    for (i = 0; i < 4; i++)
+    {
+        code[0] <<= 2;
+        code[1] <<= 2;
+        code[2] <<= 2;
+
+        /* Line 1 */
+        if ((odd_line_code & 0x80) != 0)
+        {
+            code[0] |= 2;
+        }
+
+        if ((even_line_code & 0x80) != 0)
+        {
+            code[0] |= 1;
+        }
+        /* Line 2 */
+        if ((odd_line_code & 0x08) != 0)
+        {
+            code[1] |= 2;
+        }
+
+        if ((even_line_code & 0x08) != 0)
+        {
+            code[1] |= 1;
+        }
+        /* Column */
+        if ((odd_column_code & 0x04) != 0)
+        {
+            code[2] |= 2;
+        }
+
+        if ((even_column_code & 0x04) != 0)
+        {
+            code[2] |= 1;
+        }
+
+        odd_line_code <<= 1;
+        even_line_code <<= 1;
+        odd_column_code <<= 1;
+        even_column_code <<= 1;
+    }
+
+    /* Invert codes (linux compatibility) */
+    code[0] = (~(uint32_t) code[0]);
+    code[1] = (~(uint32_t) code[1]);
+    code[2] = (~(uint32_t) code[2]);
 
 }
 
@@ -217,58 +230,61 @@ static void compute256(const uint8_t *data, uint8_t *code)
  */
 static uint32_t verify256(uint8_t *puc_data, const uint8_t *puc_original_code)
 {
-	/* Calculate new code */
-	uint8_t computed_code[3];
-	uint8_t correction_code[3];
-
-	compute256(puc_data, computed_code);
-
-	/* Xor both codes together */
-	correction_code[0] = computed_code[0] ^ puc_original_code[0];
-	correction_code[1] = computed_code[1] ^ puc_original_code[1];
-	correction_code[2] = computed_code[2] ^ puc_original_code[2];
-
-
-	/* If all bytes are 0, there is no error */
-	if ((correction_code[0] == 0) && (correction_code[1] == 0)
-			&& (correction_code[2] == 0)) {
-		return 0;
-	}
-
-	/* If there is a single bit error, there are 11 bits set to 1 */
-	if (count_bits_in_code256(correction_code) == 11) {
-		/* Get byte and bit indexes */
-		uint8_t byte;
-		uint8_t bit;
-
-		byte = correction_code[0] & 0x80;
-		byte |= ((correction_code[0] << 1) & 0x40);
-		byte |= ((correction_code[0] << 2) & 0x20);
-		byte |= ((correction_code[0] << 3) & 0x10);
-
-		byte |= ((correction_code[1] >> 4) & 0x08);
-		byte |= ((correction_code[1] >> 3) & 0x04);
-		byte |= ((correction_code[1] >> 2) & 0x02);
-		byte |= ((correction_code[1] >> 1) & 0x01);
-
-		bit = (correction_code[2] >> 5) & 0x04;
-		bit |= ((correction_code[2] >> 4) & 0x02);
-		bit |= ((correction_code[2] >> 3) & 0x01);
-
-		/* Correct bit */
-		puc_data[byte] ^= (1 << bit);
-
-		return HAMMING_ERROR_SINGLE_BIT;
-	}
-
-	/* Check if ECC has been corrupted */
-	if (count_bits_in_code256(correction_code) == 1) {
-		return HAMMING_ERROR_ECC;
-	}
-	/* Otherwise, this is a multi-bit error */
-	else {
-		return HAMMING_ERROR_MULTIPLE_BITS;
-	}
+    /* Calculate new code */
+    uint8_t computed_code[3];
+    uint8_t correction_code[3];
+
+    compute256(puc_data, computed_code);
+
+    /* Xor both codes together */
+    correction_code[0] = computed_code[0] ^ puc_original_code[0];
+    correction_code[1] = computed_code[1] ^ puc_original_code[1];
+    correction_code[2] = computed_code[2] ^ puc_original_code[2];
+
+
+    /* If all bytes are 0, there is no error */
+    if ((correction_code[0] == 0) && (correction_code[1] == 0)
+            && (correction_code[2] == 0))
+            {
+        return 0;
+    }
+
+    /* If there is a single bit error, there are 11 bits set to 1 */
+    if (count_bits_in_code256(correction_code) == 11)
+    {
+        /* Get byte and bit indexes */
+        uint8_t byte;
+        uint8_t bit;
+
+        byte = correction_code[0] & 0x80;
+        byte |= ((correction_code[0] << 1) & 0x40);
+        byte |= ((correction_code[0] << 2) & 0x20);
+        byte |= ((correction_code[0] << 3) & 0x10);
+
+        byte |= ((correction_code[1] >> 4) & 0x08);
+        byte |= ((correction_code[1] >> 3) & 0x04);
+        byte |= ((correction_code[1] >> 2) & 0x02);
+        byte |= ((correction_code[1] >> 1) & 0x01);
+
+        bit = (correction_code[2] >> 5) & 0x04;
+        bit |= ((correction_code[2] >> 4) & 0x02);
+        bit |= ((correction_code[2] >> 3) & 0x01);
+
+        /* Correct bit */
+        puc_data[byte] ^= (1 << bit);
+
+        return HAMMING_ERROR_SINGLE_BIT;
+    }
+
+    /* Check if ECC has been corrupted */
+    if (count_bits_in_code256(correction_code) == 1)
+    {
+        return HAMMING_ERROR_ECC;
+    }
+    /* Otherwise, this is a multi-bit error */
+    else {
+        return HAMMING_ERROR_MULTIPLE_BITS;
+    }
 }
 
 /**
@@ -280,15 +296,16 @@ static uint32_t verify256(uint8_t *puc_data, const uint8_t *puc_original_code)
  *  \param puc_code Pointer to codes buffer.
  */
 void hamming_compute_256x(const uint8_t *puc_data, uint32_t dw_size,
-		uint8_t *puc_code)
+        uint8_t *puc_code)
 {
-	while (dw_size > 0) {
-		compute256(puc_data, puc_code);
-
-		puc_data += 256;
-		puc_code += 3;
-		dw_size -= 256;
-	}
+    while (dw_size > 0)
+    {
+        compute256(puc_data, puc_code);
+
+        puc_data += 256;
+        puc_code += 3;
+        dw_size -= 256;
+    }
 }
 
 /**
@@ -304,26 +321,29 @@ void hamming_compute_256x(const uint8_t *puc_data, uint32_t dw_size,
  *  or HAMMING_ERROR_MULTIPLE_BITS.
  */
 uint32_t hamming_verify_256x(uint8_t *puc_data, uint32_t dw_size,
-		const uint8_t *puc_code)
+        const uint8_t *puc_code)
 {
-	uint32_t error;
-	uint32_t result = 0;
-
-	while (dw_size > 0) {
-		error = verify256(puc_data, puc_code);
-
-		if (error == HAMMING_ERROR_SINGLE_BIT) {
-			result = HAMMING_ERROR_SINGLE_BIT;
-		} else {
-			if (error) {
-				return error;
-			}
-		}
-
-		puc_data += 256;
-		puc_code += 3;
-		dw_size -= 256;
-	}
-
-	return result;
+    uint32_t error;
+    uint32_t result = 0;
+
+    while (dw_size > 0)
+    {
+        error = verify256(puc_data, puc_code);
+
+        if (error == HAMMING_ERROR_SINGLE_BIT)
+        {
+            result = HAMMING_ERROR_SINGLE_BIT;
+        } else {
+            if (error)
+            {
+                return error;
+            }
+        }
+
+        puc_data += 256;
+        puc_code += 3;
+        dw_size -= 256;
+    }
+
+    return result;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h
index fed7e947a53b..3d5ae0f8e50f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/storage/ecc_hamming/ecc-sw.h
@@ -72,8 +72,8 @@
 
 
 void hamming_compute_256x(const uint8_t *puc_data, uint32_t dw_size,
-		uint8_t *puc_code);
+        uint8_t *puc_code);
 uint32_t hamming_verify_256x(uint8_t *puc_data, uint32_t dw_size,
-		const uint8_t *puc_code);
+        const uint8_t *puc_code);
 
 #endif /* ECC_SW_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h
index c51d8009410b..e2bd7c7aea7a 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_master.h
@@ -55,53 +55,64 @@ typedef twi_options_t twi_master_options_t;
 typedef twi_packet_t twi_package_t;
 
 static inline uint32_t twi_master_setup(twi_master_t p_twi,
-		twi_master_options_t *p_opt)
+        twi_master_options_t *p_opt)
 {
-	p_opt->master_clk = sysclk_get_peripheral_hz();
-	p_opt->smbus      = 0;
+    p_opt->master_clk = sysclk_get_peripheral_hz();
+    p_opt->smbus      = 0;
 #if SAMG55
-	if (p_twi == TWI0) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM0);
-	} else if (p_twi == TWI1) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM1);
-	} else if (p_twi == TWI2) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM2);
-	} else if (p_twi == TWI3) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM3);
-	} else if (p_twi == TWI4) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM4);
-	} else if (p_twi == TWI5) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM5);
-	} else if (p_twi == TWI6) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+    if (p_twi == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+    } else if (p_twi == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+    } else if (p_twi == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+    } else if (p_twi == TWI3)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+    } else if (p_twi == TWI4)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+    } else if (p_twi == TWI5)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+    } else if (p_twi == TWI6)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM6);
 #ifdef _SAMG55_FLEXCOM7_INSTANCE_
-	} else if (p_twi == TWI7) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+    } else if (p_twi == TWI7)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM7);
 #endif /* _SAMG55_FLEXCOM7_INSTANCE_*/
-	} else {
-		// Do Nothing
-	}
+    } else {
+        /* Do Nothing*/
+    }
 #else
 #if (!(SAMG51 || SAMG53 || SAMG54))
-	if (p_twi == TWI0) {
-		sysclk_enable_peripheral_clock(ID_TWI0);
-	} else
+    if (p_twi == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI0);
+    } else
 #endif
-	if (p_twi == TWI1) {
-		sysclk_enable_peripheral_clock(ID_TWI1);
+    if (p_twi == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI1);
 #if (SAM4N || SAMG)
-	} else if (p_twi == TWI2) {
-		sysclk_enable_peripheral_clock(ID_TWI2);
+    } else if (p_twi == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI2);
 #endif
-	} else {
-		// Do Nothing
-	}
+    } else {
+        /* Do Nothing*/
+    }
 #endif
 
-	return (twi_master_init(p_twi, p_opt));
+    return (twi_master_init(p_twi, p_opt));
 }
 
 #define twi_master_enable(p_twi)   twi_enable_master_mode(p_twi)
 #define twi_master_disable(p_twi)  twi_disable_master_mode(p_twi)
 
-#endif // _TWI_MASTER_H_
+#endif /* _TWI_MASTER_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h
index fcd714ee454a..361514ca6260 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twi/twi_slave.h
@@ -55,49 +55,60 @@ typedef Twi *twi_slave_t;
 static inline void twi_slave_setup(twi_slave_t p_twi, uint32_t dw_device_addr)
 {
 #if SAMG55
-	if (p_twi == TWI0) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM0);
-	} else if (p_twi == TWI1) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM1);
-	} else if (p_twi == TWI2) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM2);
-	} else if (p_twi == TWI3) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM3);
-	} else if (p_twi == TWI4) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM4);
-	} else if (p_twi == TWI5) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM5);
-	} else if (p_twi == TWI6) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM6);
+    if (p_twi == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM0);
+    } else if (p_twi == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM1);
+    } else if (p_twi == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM2);
+    } else if (p_twi == TWI3)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM3);
+    } else if (p_twi == TWI4)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM4);
+    } else if (p_twi == TWI5)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM5);
+    } else if (p_twi == TWI6)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM6);
 #ifdef _SAMG55_FLEXCOM7_INSTANCE_
-	} else if (p_twi == TWI7) {
-		sysclk_enable_peripheral_clock(ID_FLEXCOM7);
+    } else if (p_twi == TWI7)
+    {
+        sysclk_enable_peripheral_clock(ID_FLEXCOM7);
 #endif /* _SAMG55_FLEXCOM7_INSTANCE_*/
-	} else {
-		// Do Nothing
-	}
+    } else {
+        /* Do Nothing*/
+    }
 #else
 #if (!(SAMG51 || SAMG53 || SAMG54))
-	if (p_twi == TWI0) {
-		sysclk_enable_peripheral_clock(ID_TWI0);
-	} else
+    if (p_twi == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI0);
+    } else
 #endif
-	if (p_twi == TWI1) {
-		sysclk_enable_peripheral_clock(ID_TWI1);
+    if (p_twi == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI1);
 #if (SAM4N || SAMG)
-	} else if (p_twi == TWI2) {
-		sysclk_enable_peripheral_clock(ID_TWI2);
+    } else if (p_twi == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI2);
 #endif
-	} else {
-		// Do Nothing
-	}
+    } else {
+        /* Do Nothing*/
+    }
 #endif
 
-	twi_slave_init(p_twi, dw_device_addr);
+    twi_slave_init(p_twi, dw_device_addr);
 }
 
 #define twi_slave_enable(p_twi)  twi_enable_slave_mode(p_twi)
 
 #define twi_slave_disable(p_twi)  twi_disable_slave_mode(p_twi)
 
-#endif // _TWI_SLAVE_H_
+#endif /* _TWI_SLAVE_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h
index 8af74cb4bfca..4891f9d84234 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_master.h
@@ -55,48 +55,59 @@ typedef twihs_options_t twihs_master_options_t;
 typedef twihs_packet_t twihs_package_t;
 
 static inline uint32_t twihs_master_setup(twihs_master_t p_twihs,
-		twihs_master_options_t *p_opt)
+        twihs_master_options_t *p_opt)
 {
-	p_opt->master_clk = sysclk_get_peripheral_hz();
-	p_opt->smbus      = 0;
+    p_opt->master_clk = sysclk_get_peripheral_hz();
+    p_opt->smbus      = 0;
 
 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
-	if (p_twihs == TWIHS0) {
-		sysclk_enable_peripheral_clock(ID_TWIHS0);
-	} else if (p_twihs == TWIHS1) {
-		sysclk_enable_peripheral_clock(ID_TWIHS1);
-	} else if (p_twihs == TWIHS2) {
-		sysclk_enable_peripheral_clock(ID_TWIHS2);
-	} else {
-		// Do Nothing
-	}
+    if (p_twihs == TWIHS0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS0);
+    } else if (p_twihs == TWIHS1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS1);
+    } else if (p_twihs == TWIHS2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS2);
+    } else {
+        /* Do Nothing*/
+    }
 #else
-	if (p_twihs == TWI0) {
-		sysclk_enable_peripheral_clock(ID_TWI0);
-#if SAMG55		
-	} else if (p_twihs == TWI1) {
-		sysclk_enable_peripheral_clock(ID_TWI1);
-	} else if (p_twihs == TWI2) {
-		sysclk_enable_peripheral_clock(ID_TWI2);
-	} else if (p_twihs == TWI3) {
-		sysclk_enable_peripheral_clock(ID_TWI3);
-	} else if (p_twihs == TWI4) {
-		sysclk_enable_peripheral_clock(ID_TWI4);
-	} else if (p_twihs == TWI5) {
-		sysclk_enable_peripheral_clock(ID_TWI5);
-	} else if (p_twihs == TWI6) {
-		sysclk_enable_peripheral_clock(ID_TWI6);
-	} else if (p_twihs == TWI7) {
-		sysclk_enable_peripheral_clock(ID_TWI7);
-#endif		
-	} else {
-		// Do Nothing
-	}
+    if (p_twihs == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI0);
+#if SAMG55
+    } else if (p_twihs == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI1);
+    } else if (p_twihs == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI2);
+    } else if (p_twihs == TWI3)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI3);
+    } else if (p_twihs == TWI4)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI4);
+    } else if (p_twihs == TWI5)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI5);
+    } else if (p_twihs == TWI6)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI6);
+    } else if (p_twihs == TWI7)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI7);
 #endif
-	return (twihs_master_init(p_twihs, p_opt));
+    } else {
+        /* Do Nothing*/
+    }
+#endif
+    return (twihs_master_init(p_twihs, p_opt));
 }
 
 #define twihs_master_enable(p_twihs)   twihs_enable_master_mode(p_twihs)
 #define twihs_master_disable(p_twihs)  twihs_disable_master_mode(p_twihs)
 
-#endif // _TWIHS_MASTER_H_
+#endif /* _TWIHS_MASTER_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h
index a39431a801e2..45aa38866156 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twihs/twihs_slave.h
@@ -55,39 +55,50 @@ typedef Twihs *twihs_slave_t;
 static inline void twihs_slave_setup(twihs_slave_t p_twihs, uint32_t dw_device_addr)
 {
 #if (SAMV70 || SAMV71 || SAME70 || SAMS70)
-	if (p_twihs == TWIHS0) {
-		sysclk_enable_peripheral_clock(ID_TWIHS0);
-	} else if (p_twihs == TWIHS1) {
-		sysclk_enable_peripheral_clock(ID_TWIHS1);
-	} else if (p_twihs == TWIHS2) {
-		sysclk_enable_peripheral_clock(ID_TWIHS2);
-	} else {
-		// Do Nothing
-	}
+    if (p_twihs == TWIHS0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS0);
+    } else if (p_twihs == TWIHS1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS1);
+    } else if (p_twihs == TWIHS2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWIHS2);
+    } else {
+        /* Do Nothing*/
+    }
 #else
-	if (p_twihs == TWI0) {
-		sysclk_enable_peripheral_clock(ID_TWI0);
-#if SAMG55		
-	} else if (p_twihs == TWI1) {
-		sysclk_enable_peripheral_clock(ID_TWI1);
-	} else if (p_twihs == TWI2) {
-		sysclk_enable_peripheral_clock(ID_TWI2);
-	} else if (p_twihs == TWI3) {
-		sysclk_enable_peripheral_clock(ID_TWI3);
-	} else if (p_twihs == TWI4) {
-		sysclk_enable_peripheral_clock(ID_TWI4);
-	} else if (p_twihs == TWI5) {
-		sysclk_enable_peripheral_clock(ID_TWI5);
-	} else if (p_twihs == TWI6) {
-		sysclk_enable_peripheral_clock(ID_TWI6);
-	} else if (p_twihs == TWI7) {
-		sysclk_enable_peripheral_clock(ID_TWI7);
-#endif		
-	} else {
-		// Do Nothing
-	}
+    if (p_twihs == TWI0)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI0);
+#if SAMG55
+    } else if (p_twihs == TWI1)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI1);
+    } else if (p_twihs == TWI2)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI2);
+    } else if (p_twihs == TWI3)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI3);
+    } else if (p_twihs == TWI4)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI4);
+    } else if (p_twihs == TWI5)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI5);
+    } else if (p_twihs == TWI6)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI6);
+    } else if (p_twihs == TWI7)
+    {
+        sysclk_enable_peripheral_clock(ID_TWI7);
 #endif
-	twihs_slave_init(p_twihs, dw_device_addr);
+    } else {
+        /* Do Nothing*/
+    }
+#endif
+    twihs_slave_init(p_twihs, dw_device_addr);
 }
 
 #define twihs_slave_enable(p_twihs)  twihs_enable_slave_mode(p_twihs)
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h
index a3570de6c262..480bbace1a99 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/sam_twim/twi_master.h
@@ -61,10 +61,10 @@ typedef twi_options_t twi_master_options_t;
 
 static inline uint32_t twi_master_setup(Twim *twi, twi_master_options_t *opt)
 {
-	opt->twim_clk = sysclk_get_pba_hz();
-	/* Initialize the TWIM Module */
-	twim_set_callback(twi, 0, twim_default_callback, 1);
-	return twi_master_init(twi, (twi_master_options_t *)opt);
+    opt->twim_clk = sysclk_get_pba_hz();
+    /* Initialize the TWIM Module */
+    twim_set_callback(twi, 0, twim_default_callback, 1);
+    return twi_master_init(twi, (twi_master_options_t *)opt);
 }
 
-#endif  // _TWI_MASTER_H_
+#endif  /* _TWI_MASTER_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h
index 183af4892331..df5e5a71a42e 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_master.h
@@ -108,7 +108,7 @@
  * architecture, ie. TWI_t* for XMEGA or avr32_twim_t* for UC3
  */
 
-//! @}
+/*! @}*/
 
 
 /**
@@ -133,15 +133,15 @@
  * \subsection twi_basic_use_case_setup_code Example code
  * Add to your application C-file:
  * \code
-	  void twi_init(void)
-	  {
-	    twi_master_options_t opt = {
-	        .speed = 50000,
-	        .chip  = 0x50
-	    };
+      void twi_init(void)
+      {
+        twi_master_options_t opt = {
+            .speed = 50000,
+            .chip  = 0x50
+        };
 
-	    twi_master_setup(&TWIM0, &opt);
-	  }
+        twi_master_setup(&TWIM0, &opt);
+      }
 \endcode
  *
  * \subsection twi_basic_use_case_setup_flow Workflow
@@ -152,10 +152,10 @@
  * -# Define and initialize config structs for TWI module in your TWI initialization
  * function:
  *   - \code
-	twi_master_options_t opt = {
-	  .speed = 50000,
-	  .chip  = 0x50
-	}; \endcode
+    twi_master_options_t opt = {
+      .speed = 50000,
+      .chip  = 0x50
+    }; \endcode
  *   - field \ref speed sets the baudrate of the TWI bus
  *   - field \ref chip sets the address of the slave device you want to communicate with
  * -# Call twi_master_setup and optionally check its return code
@@ -166,17 +166,17 @@
  * \subsection twi_basic_use_case_usage_code_writing Example code : Writing to a slave device
  * Use in application C-file:
  * \code
-	  const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
+      const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
 
-	  twi_package_t packet_write = {
-	    .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
-	    .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
-	    .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
-	    .buffer       = (void *)test_pattern, // transfer data source buffer
-	    .length       = sizeof(test_pattern)  // transfer data size (bytes)
-	  };
+      twi_package_t packet_write = {
+        .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
+        .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
+        .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
+        .buffer       = (void *)test_pattern, // transfer data source buffer
+        .length       = sizeof(test_pattern)  // transfer data size (bytes)
+      };
 
-	  while (twi_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
+      while (twi_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
 \endcode
  *
  * \subsection twi_basic_use_case_usage_flow Workflow
@@ -196,21 +196,22 @@
  * \subsection twi_basic_use_case_usage_code_reading Example code : Reading from a slave device
  * Use in application C-file:
  * \code
-	   uint8_t data_received[10];
+       uint8_t data_received[10];
 
-	   twi_package_t packet_read = {
-	     .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
-	     .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
-	     .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
-	     .buffer       = data_received,        // transfer data destination buffer
-	     .length       = 10                    // transfer data size (bytes)
-	   };
-	   // Perform a multi-byte read access then check the result.
-	   if(twi_master_read(&TWIM0, &packet_read) == TWI_SUCCESS){
-	     //Check read content
-	     if(data_received[0]==0x55)
-	       do_something();
-	   }
+       twi_package_t packet_read = {
+         .addr         = EEPROM_MEM_ADDR,      // TWI slave memory address data
+         .addr_length  = sizeof (uint16_t),    // TWI slave memory address data size
+         .chip         = EEPROM_BUS_ADDR,      // TWI slave bus address
+         .buffer       = data_received,        // transfer data destination buffer
+         .length       = 10                    // transfer data size (bytes)
+       };
+       // Perform a multi-byte read access then check the result.
+       if(twi_master_read(&TWIM0, &packet_read) == TWI_SUCCESS)
+       {
+         //Check read content
+         if(data_received[0]==0x55)
+           do_something();
+       }
 \endcode
  *
  * \subsection twi_basic_use_case_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h
index 497316b40a45..5f26d863c76a 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twi_slave.h
@@ -98,6 +98,6 @@
  * architecture, ie. TWI_t* for XMEGA or avr32_twi_t* for UC3
  */
 
-//! @}
+/*! @}*/
 
 #endif /* TWI_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h
index a620f3db20cd..12cb51d557f2 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_master.h
@@ -97,7 +97,7 @@
  * architecture.
  */
 
-//! @}
+/*! @}*/
 
 /**
  * \page twihs_quickstart Quickstart guide for Common service TWIHS
@@ -121,15 +121,15 @@
  * \subsection twihs_basic_use_case_setup_code Example code
  * Add to your application C-file, for example in SAM series chip:
  * \code
-	  void twihs_init(void)
-	  {
-	    twihs_master_options_t opt = {
-	        .speed = 400000,
-	        .chip  = 0x50
-	    };
+      void twihs_init(void)
+      {
+        twihs_master_options_t opt = {
+            .speed = 400000,
+            .chip  = 0x50
+        };
 
-	    twihs_master_setup(&TWIM0, &opt);
-	  }
+        twihs_master_setup(&TWIM0, &opt);
+      }
 \endcode
  *
  * \subsection twihs_basic_use_case_setup_flow Workflow
@@ -140,10 +140,10 @@
  * -# Define and initialize config structs for TWIHS module in your TWIHS initialization
  * function, for example in SAM series chip:
  *   - \code
-	twihs_master_options_t opt = {
-	  .speed = 400000,
-	  .chip  = 0x50
-	}; \endcode
+    twihs_master_options_t opt = {
+      .speed = 400000,
+      .chip  = 0x50
+    }; \endcode
  *   - field \ref speed sets the baudrate of the TWIHS bus
  *   - field \ref chip sets the address of the slave device you want to communicate with
  * -# Call twihs_master_setup and optionally check its return code
@@ -154,17 +154,17 @@
  * \subsection twihs_basic_use_case_usage_code_writing Example code : Writing to a slave device
  * Use in application C-file, for example in SAM series chip:
  * \code
-	  const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
+      const uint8_t test_pattern[] = {0x55,0xA5,0x5A,0x77,0x99};
 
-	  twihs_package_t packet_write = {
-	    .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
-	    .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
-	    .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
-	    .buffer       = (void *)test_pattern, // transfer data source buffer
-	    .length       = sizeof(test_pattern)  // transfer data size (bytes)
-	  };
+      twihs_package_t packet_write = {
+        .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
+        .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
+        .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
+        .buffer       = (void *)test_pattern, // transfer data source buffer
+        .length       = sizeof(test_pattern)  // transfer data size (bytes)
+      };
 
-	  while (twihs_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
+      while (twihs_master_write(&TWIM0, &packet_write) != TWI_SUCCESS);
 \endcode
  *
  * \subsection twihs_basic_use_case_usage_flow Workflow
@@ -184,21 +184,22 @@
  * \subsection twihs_basic_use_case_usage_code_reading Example code : Reading from a slave device
  * Use in application C-file, for example in SAM series chip:
  * \code
-	   uint8_t data_received[10];
+       uint8_t data_received[10];
 
-	   twihs_package_t packet_read = {
-	     .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
-	     .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
-	     .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
-	     .buffer       = data_received,        // transfer data destination buffer
-	     .length       = 10                    // transfer data size (bytes)
-	   };
-	   // Perform a multi-byte read access then check the result.
-	   if(twihs_master_read(&TWIM0, &packet_read) == TWI_SUCCESS){
-	     //Check read content
-	     if(data_received[0]==0x55)
-	       do_something();
-	   }
+       twihs_package_t packet_read = {
+         .addr         = EEPROM_MEM_ADDR,      // TWIHS slave memory address data
+         .addr_length  = sizeof (uint16_t),    // TWIHS slave memory address data size
+         .chip         = EEPROM_BUS_ADDR,      // TWIHS slave bus address
+         .buffer       = data_received,        // transfer data destination buffer
+         .length       = 10                    // transfer data size (bytes)
+       };
+       // Perform a multi-byte read access then check the result.
+       if(twihs_master_read(&TWIM0, &packet_read) == TWI_SUCCESS)
+       {
+         //Check read content
+         if(data_received[0]==0x55)
+           do_something();
+       }
 \endcode
  *
  * \subsection twihs_basic_use_case_usage_flow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h
index 4c768d03dc97..70574d0612ce 100644
--- a/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/common/services/twi/twihs_slave.h
@@ -89,6 +89,6 @@
  * architecture used.
  */
 
-//! @}
+/*! @}*/
 
 #endif /* TWIHS_SLAVE_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h
index a88c6f0c5990..e20925d02785 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt.h
@@ -78,8 +78,8 @@
 #  define CONFIG_INTERRUPT_FORCE_INTC
 #endif
 
-//! \name Global interrupt flags
-//@{
+/*! \name Global interrupt flags*/
+/*@{*/
 /**
  * \typedef irqflags_t
  * \brief Type used for holding state of interrupt flag
@@ -130,9 +130,9 @@
  *
  * \return True if interrupts are enabled.
  */
-//@}
+/*@}*/
 
-//! @}
+/*! @}*/
 
 /**
  * \ingroup interrupt_group
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h
index 66f2fa2c2fed..6c23dff145d9 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr32.h
@@ -55,7 +55,7 @@
  * @{
  */
 
-//! Pointer to interrupt handler.
+/*! Pointer to interrupt handler.*/
 #if (defined __GNUC__)
 typedef void (*__int_handler)(void);
 #elif (defined __ICCAVR32__)
@@ -86,11 +86,11 @@ typedef void (__interrupt *__int_handler)(void);
  *
  * Usage:
  * \code
-	ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n)
-	{
-	     // Function definition
-	     ...
-	}
+    ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n)
+    {
+         // Function definition
+         ...
+    }
 \endcode
  *
  * \param func Name for the function, needed by \ref irq_register_handler.
@@ -105,17 +105,17 @@ typedef void (__interrupt *__int_handler)(void);
  * device header files of both IAR and GCC.
  */
 #  define ISR(func, int_grp, int_lvl)    \
-	__attribute__((__interrupt__)) static void func (void)
+    __attribute__((__interrupt__)) static void func (void)
 
 #elif defined(__ICCAVR32__) && defined(CONFIG_INTERRUPT_FORCE_INTC)
 #  define ISR(func, int_grp, int_lvl) \
-		__interrupt static void func (void)
+        __interrupt static void func (void)
 
 #elif defined(__ICCAVR32__)
 #  define ISR0(...) _Pragma(#__VA_ARGS__)
 #  define ISR(func, int_grp, int_lvl)                                          \
-		ISR0(handler=int_grp, int_lvl)                                 \
-		__interrupt static void func (void)
+        ISR0(handler=int_grp, int_lvl)                                 \
+        __interrupt static void func (void)
 #endif
 
 #if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC)
@@ -154,8 +154,8 @@ typedef void (__interrupt *__int_handler)(void);
  *
  * Usage:
  * \code
-	irq_initialize_vectors();
-	irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n);
+    irq_initialize_vectors();
+    irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n);
 \endcode
  *
  * \note The function \a func must be defined with the \ref ISR macro.
@@ -163,39 +163,39 @@ typedef void (__interrupt *__int_handler)(void);
  * the GCC toolchain (avr32/\<part\>.h).
  */
 #  define irq_register_handler(func, int_num, int_lvl)                         \
-	INTC_register_interrupt(func, int_num,                                 \
-			TPASTE2(AVR32_INTC_INT, int_lvl))
+    INTC_register_interrupt(func, int_num,                                 \
+            TPASTE2(AVR32_INTC_INT, int_lvl))
 
 #elif defined(__ICCAVR32__)
 #  define irq_initialize_vectors()                        do{ } while(0)
 #  define irq_register_handler(func, int_num, int_lvl)    do{ } while(0)
 #endif
 
-//@}
+/*@}*/
 
 #if (defined __GNUC__)
 #  define cpu_irq_enable()                             \
-	do {                                           \
-		barrier();                             \
-		__builtin_csrf(AVR32_SR_GM_OFFSET);    \
-	} while (0)
+    do {                                           \
+        barrier();                             \
+        __builtin_csrf(AVR32_SR_GM_OFFSET);    \
+    } while (0)
 #  define cpu_irq_disable()                            \
-	do {                                           \
-		__builtin_ssrf(AVR32_SR_GM_OFFSET);    \
-		barrier();                             \
-	} while (0)
+    do {                                           \
+        __builtin_ssrf(AVR32_SR_GM_OFFSET);    \
+        barrier();                             \
+    } while (0)
 #elif (defined __ICCAVR32__)
 #  if (defined CONFIG_INTERRUPT_FORCE_INTC)
 #    define cpu_irq_enable()                                 \
-	do {                                                 \
-		barrier();                                   \
-		__clear_status_flag(AVR32_SR_GM_OFFSET);     \
-	} while(0)
+    do {                                                 \
+        barrier();                                   \
+        __clear_status_flag(AVR32_SR_GM_OFFSET);     \
+    } while(0)
 #    define cpu_irq_disable()                                \
-	do {                                                 \
-		__set_status_flag(AVR32_SR_GM_OFFSET);       \
-		barrier();                                   \
-	} while (0)
+    do {                                                 \
+        __set_status_flag(AVR32_SR_GM_OFFSET);       \
+        barrier();                                   \
+    } while (0)
 #  else
 #    define cpu_irq_enable()     __enable_interrupt()
 #    define cpu_irq_disable()    __disable_interrupt()
@@ -206,35 +206,36 @@ typedef uint32_t irqflags_t;
 
 static inline irqflags_t cpu_irq_save(void)
 {
-	volatile irqflags_t flags;
+    volatile irqflags_t flags;
 
-	flags = sysreg_read(AVR32_SR);
-	cpu_irq_disable();
+    flags = sysreg_read(AVR32_SR);
+    cpu_irq_disable();
 
-	return flags;
+    return flags;
 }
 
 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
 {
-	return !(flags & AVR32_SR_GM_MASK);
+    return !(flags & AVR32_SR_GM_MASK);
 }
 
 static inline void cpu_irq_restore(irqflags_t flags)
 {
-	barrier();
+    barrier();
 
    /* Restore the global IRQ mask status flag if it was previously set */
-   if ( cpu_irq_is_enabled_flags(flags) ) {
+   if ( cpu_irq_is_enabled_flags(flags) )
+   {
       cpu_irq_enable();
    }
 
-	barrier();
+    barrier();
 }
 
 #define cpu_irq_is_enabled()    cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR))
 
-//! \name Global interrupt levels
-//@{
+/*! \name Global interrupt levels*/
+/*@{*/
 
 /**
  * \brief Check if interrupt level is enabled in supplied flags
@@ -245,9 +246,9 @@ static inline void cpu_irq_restore(irqflags_t flags)
  * \return True if interrupt level is enabled.
  */
 static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
-		uint32_t level)
+        uint32_t level)
 {
-	return !(flags & (1 << level));
+    return !(flags & (1 << level));
 }
 
 /**
@@ -260,8 +261,8 @@ static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
  * \note The interrupt level must be known at compile time.
  */
 #define cpu_irq_level_is_enabled(level)                                  \
-	cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR),             \
-			TPASTE3(AVR32_SR_I, level, M_OFFSET))
+    cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR),             \
+            TPASTE3(AVR32_SR_I, level, M_OFFSET))
 
 #if defined(__GNUC__) || defined(__DOXYGEN__)
 /**
@@ -272,10 +273,10 @@ static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
  * \note The interrupt level must be known at compile time.
  */
 #  define cpu_irq_enable_level(level)                                    \
-	do {                                                             \
-		barrier();                                               \
-		__builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
-	} while (0)
+    do {                                                             \
+        barrier();                                               \
+        __builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
+    } while (0)
 
 /**
  * \brief Disable interrupt level
@@ -285,27 +286,27 @@ static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
  * \note The interrupt level must be known at compile time.
  */
 #  define cpu_irq_disable_level(level)                                   \
-	do {                                                             \
-		__builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
-		barrier();                                               \
-	} while (0)
+    do {                                                             \
+        __builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET));    \
+        barrier();                                               \
+    } while (0)
 
 #elif (defined __ICCAVR32__)
 #  define cpu_irq_enable_level(level)                                          \
-	do {                                                                   \
-		barrier();                                                     \
-		__clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));     \
-	} while(0)
+    do {                                                                   \
+        barrier();                                                     \
+        __clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));     \
+    } while(0)
 #  define cpu_irq_disable_level(level)                                         \
-	do {                                                                   \
-		__set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));       \
-		barrier();                                                     \
-	} while (0)
+    do {                                                                   \
+        __set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET));       \
+        barrier();                                                     \
+    } while (0)
 #endif
 
-//@}
+/*@}*/
 
-//@}
+/*@}*/
 
 /**
  * \weakgroup interrupt_deprecated_group
@@ -330,9 +331,9 @@ static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
  * \brief Start section with code protected against interrupts
  */
 #define AVR32_ENTER_CRITICAL_REGION()                                          \
-	{                                                                      \
-		bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
-		Disable_global_interrupt();
+    {                                                                      \
+        bool global_interrupt_enabled = Is_global_interrupt_enabled(); \
+        Disable_global_interrupt();
 
 /**
  * \brief End section with code protected against interrupts
@@ -341,11 +342,11 @@ static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags,
  * \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again.
  */
 #define AVR32_LEAVE_CRITICAL_REGION()                                          \
-		if (global_interrupt_enabled) Enable_global_interrupt();       \
-	}
+        if (global_interrupt_enabled) Enable_global_interrupt();       \
+    }
 
-//@}
+/*@}*/
 
-//@}
+/*@}*/
 
 #endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h
index 1e6928c285c8..cd8e94e4dc1f 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_avr8.h
@@ -65,10 +65,10 @@
  *
  * Usage:
  * \code
-	ISR(FOO_vect)
-	{
-	    ...
-	}
+    ISR(FOO_vect)
+    {
+        ...
+    }
 \endcode
  *
  * \param vect Interrupt vector name as found in the device header files.
@@ -81,7 +81,7 @@
 #  define __ISR(x) _Pragma(#x)
 #  define ISR(vect) __ISR(vector=vect) __interrupt void handler_##vect(void)
 #endif
-#endif // ISR_CUSTOM_H
+#endif /* ISR_CUSTOM_H*/
 
 #if XMEGA
 /**
@@ -90,7 +90,7 @@
  * and fixed priority scheduling.
  */
 #define irq_initialize_vectors() \
-	PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
+    PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm;
 #elif MEGA_RF
 #define irq_initialize_vectors()
 #endif
@@ -107,42 +107,42 @@ typedef uint8_t irqflags_t;
 
 static inline irqflags_t cpu_irq_save(void)
 {
-	volatile irqflags_t flags = SREG;
-	cpu_irq_disable();
-	return flags;
+    volatile irqflags_t flags = SREG;
+    cpu_irq_disable();
+    return flags;
 }
 
 static inline void cpu_irq_restore(irqflags_t flags)
 {
-	barrier();
-	SREG = flags;
+    barrier();
+    SREG = flags;
 }
 
 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
 {
 #if XMEGA
 #  ifdef __GNUC__
-	return flags & CPU_I_bm;
+    return flags & CPU_I_bm;
 #  else
-	return flags & I_bm;
+    return flags & I_bm;
 #  endif
 #elif MEGA || TINY
-	return flags & (1 << SREG_I);
+    return flags & (1 << SREG_I);
 #endif
 }
 
 #define cpu_irq_is_enabled()             cpu_irq_is_enabled_flags(SREG)
 
-//! @}
+/*! @}*/
 
 /**
  * \weakgroup interrupt_deprecated_group
  * @{
  */
-// Deprecated definitions.
+/* Deprecated definitions.*/
 #define Enable_global_interrupt()        cpu_irq_enable()
 #define Disable_global_interrupt()       cpu_irq_disable()
 #define Is_global_interrupt_enabled()    cpu_irq_is_enabled()
-//! @}
+/*! @}*/
 
 #endif /* UTILS_INTERRUPT_INTERRUPT_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c
index 26dcc91ef4dc..0d92c0b89af4 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.c
@@ -56,31 +56,34 @@ volatile bool g_interrupt_enabled = true;
 
 void cpu_irq_enter_critical(void)
 {
-	if (cpu_irq_critical_section_counter == 0) {
-		if (cpu_irq_is_enabled()) {
-			cpu_irq_disable();
-			cpu_irq_prev_interrupt_state = true;
-		} else {
-			/* Make sure the to save the prev state as false */
-			cpu_irq_prev_interrupt_state = false;
-		}
+    if (cpu_irq_critical_section_counter == 0)
+    {
+        if (cpu_irq_is_enabled())
+        {
+            cpu_irq_disable();
+            cpu_irq_prev_interrupt_state = true;
+        } else {
+            /* Make sure the to save the prev state as false */
+            cpu_irq_prev_interrupt_state = false;
+        }
 
-	}
+    }
 
-	cpu_irq_critical_section_counter++;
+    cpu_irq_critical_section_counter++;
 }
 
 void cpu_irq_leave_critical(void)
 {
-	/* Check if the user is trying to leave a critical section when not in a critical section */
-	Assert(cpu_irq_critical_section_counter > 0);
+    /* Check if the user is trying to leave a critical section when not in a critical section */
+    Assert(cpu_irq_critical_section_counter > 0);
 
-	cpu_irq_critical_section_counter--;
+    cpu_irq_critical_section_counter--;
 
-	/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
-	   was enabled when entering critical state */
-	if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
-		cpu_irq_enable();
-	}
+    /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
+       was enabled when entering critical state */
+    if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state))
+    {
+        cpu_irq_enable();
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h
index 419ad2046e8d..3959976e759c 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/interrupt/interrupt_sam_nvic.h
@@ -75,17 +75,17 @@ extern "C" {
  *
  * Usage:
  * \code
-	ISR(foo_irq_handler)
-	{
-	     // Function definition
-	     ...
-	}
+    ISR(foo_irq_handler)
+    {
+         // Function definition
+         ...
+    }
 \endcode
  *
  * \param func Name for the function.
  */
 #  define ISR(func)   \
-	void func (void)
+    void func (void)
 
 /**
  * \brief Initialize interrupt vectors
@@ -97,8 +97,8 @@ extern "C" {
  * This must be called prior to \ref irq_register_handler.
  */
 #  define irq_initialize_vectors()   \
-	do {                             \
-	} while(0)
+    do {                             \
+    } while(0)
 
 /**
  * \brief Register handler for interrupt
@@ -109,8 +109,8 @@ extern "C" {
  *
  * Usage:
  * \code
-	irq_initialize_vectors();
-	irq_register_handler(foo_irq_handler);
+    irq_initialize_vectors();
+    irq_register_handler(foo_irq_handler);
 \endcode
  *
  * \note The function \a func must be defined with the \ref ISR macro.
@@ -118,24 +118,24 @@ extern "C" {
  *       files (exceptions.h).
  */
 #  define irq_register_handler(int_num, int_prio)                      \
-	NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
-	NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
-	NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
+    NVIC_ClearPendingIRQ(    (IRQn_Type)int_num);                      \
+    NVIC_SetPriority(    (IRQn_Type)int_num, int_prio);                \
+    NVIC_EnableIRQ(      (IRQn_Type)int_num);                          \
 
-//@}
+/*@}*/
 
 #  define cpu_irq_enable()                     \
-	do {                                       \
-		g_interrupt_enabled = true;            \
-		__DMB();                               \
-		__enable_irq();                        \
-	} while (0)
+    do {                                       \
+        g_interrupt_enabled = true;            \
+        __DMB();                               \
+        __enable_irq();                        \
+    } while (0)
 #  define cpu_irq_disable()                    \
-	do {                                       \
-		__disable_irq();                       \
-		__DMB();                               \
-		g_interrupt_enabled = false;           \
-	} while (0)
+    do {                                       \
+        __disable_irq();                       \
+        __DMB();                               \
+        g_interrupt_enabled = false;           \
+    } while (0)
 
 typedef uint32_t irqflags_t;
 
@@ -150,20 +150,20 @@ static volatile bool     cpu_irq_prev_interrupt_state;
 
 static inline irqflags_t cpu_irq_save(void)
 {
-	volatile irqflags_t flags = cpu_irq_is_enabled();
-	cpu_irq_disable();
-	return flags;
+    volatile irqflags_t flags = cpu_irq_is_enabled();
+    cpu_irq_disable();
+    return flags;
 }
 
 static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
 {
-	return (flags);
+    return (flags);
 }
 
 static inline void cpu_irq_restore(irqflags_t flags)
 {
-	if (cpu_irq_is_enabled_flags(flags))
-		cpu_irq_enable();
+    if (cpu_irq_is_enabled_flags(flags))
+        cpu_irq_enable();
 }
 
 void cpu_irq_enter_critical(void);
@@ -178,9 +178,9 @@ void cpu_irq_leave_critical(void);
 #define Disable_global_interrupt()           cpu_irq_disable()
 #define Is_global_interrupt_enabled()        cpu_irq_is_enabled()
 
-//@}
+/*@}*/
 
-//@}
+/*@}*/
 
 #ifdef __cplusplus
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c
index c6a50c059f15..1bde99d044aa 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.c
@@ -65,18 +65,18 @@ static uint8_t membag_pool[CONF_MEMBAG_POOL_SIZE];
  * with maximum 32 blocks per membag.
  */
 struct membag {
-	/*! Number of bytes per block in this bag. */
-	size_t block_size;
-	/*! Total number of blocks. */
-	size_t num_blocks;
-	/*! Pointer to start of this bag. */
-	uintptr_t start;
-	/*! Pointer to end of this bag. */
-	uintptr_t end;
-	/*! 32-bit integer used to keep track of allocations. */
-	uint32_t allocated;
-	/*! Counter for number of free blocks. */
-	uint8_t blocks_free;
+    /*! Number of bytes per block in this bag. */
+    size_t block_size;
+    /*! Total number of blocks. */
+    size_t num_blocks;
+    /*! Pointer to start of this bag. */
+    uintptr_t start;
+    /*! Pointer to end of this bag. */
+    uintptr_t end;
+    /*! 32-bit integer used to keep track of allocations. */
+    uint32_t allocated;
+    /*! Counter for number of free blocks. */
+    uint8_t blocks_free;
 };
 
 /**
@@ -84,18 +84,18 @@ struct membag {
  * conf_membag.h header file. Example:
  *
  * \code
-	 #define CONF_MEMBAG_ARRAY \
-	     MEMBAG(32, 4),        \
-	     MEMBAG(16, 2),
+     #define CONF_MEMBAG_ARRAY \
+         MEMBAG(32, 4),        \
+         MEMBAG(16, 2),
 
-	 #define CONF_MEMBAG_POOL_SIZE \
-	     MEMBAG_SIZE(32, 4) +      \
-	     MEMBAG_SIZE(16, 2)
+     #define CONF_MEMBAG_POOL_SIZE \
+         MEMBAG_SIZE(32, 4) +      \
+         MEMBAG_SIZE(16, 2)
 \endcode
  *
  */
 static struct membag membag_list[] = {
-	CONF_MEMBAG_ARRAY
+    CONF_MEMBAG_ARRAY
 };
 
 /**
@@ -107,25 +107,26 @@ static struct membag membag_list[] = {
  */
 void membag_init(void)
 {
-	uint8_t i;
-	uintptr_t poolptr;
-
-	poolptr = (uintptr_t)membag_pool;
-
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		Assert(membag_list[i].block_size > 0);
-		Assert(membag_list[i].num_blocks > 0);
-		Assert(membag_list[i].num_blocks <= 32);
-	
-		membag_list[i].start = poolptr;
-		poolptr += (membag_list[i].block_size *
-				membag_list[i].num_blocks);
-		membag_list[i].end = poolptr;
-		membag_list[i].blocks_free = membag_list[i].num_blocks;
-
-		/* Mark all blocks as free. */
-		membag_list[i].allocated = 0;
-	}
+    uint8_t i;
+    uintptr_t poolptr;
+
+    poolptr = (uintptr_t)membag_pool;
+
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        Assert(membag_list[i].block_size > 0);
+        Assert(membag_list[i].num_blocks > 0);
+        Assert(membag_list[i].num_blocks <= 32);
+
+        membag_list[i].start = poolptr;
+        poolptr += (membag_list[i].block_size *
+                membag_list[i].num_blocks);
+        membag_list[i].end = poolptr;
+        membag_list[i].blocks_free = membag_list[i].num_blocks;
+
+        /* Mark all blocks as free. */
+        membag_list[i].allocated = 0;
+    }
 }
 
 /**
@@ -135,15 +136,16 @@ void membag_init(void)
  */
 size_t membag_get_total_free(void)
 {
-	uint8_t i;
-	size_t total_free = 0;
+    uint8_t i;
+    size_t total_free = 0;
 
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		total_free += membag_list[i].blocks_free *
-				membag_list[i].block_size;
-	}
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        total_free += membag_list[i].blocks_free *
+                membag_list[i].block_size;
+    }
 
-	return total_free;
+    return total_free;
 }
 
 /**
@@ -153,14 +155,15 @@ size_t membag_get_total_free(void)
  */
 size_t membag_get_total(void)
 {
-	uint8_t i;
-	size_t total = 0;
+    uint8_t i;
+    size_t total = 0;
 
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		total += membag_list[i].num_blocks * membag_list[i].block_size;
-	}
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        total += membag_list[i].num_blocks * membag_list[i].block_size;
+    }
 
-	return total;
+    return total;
 }
 
 /**
@@ -174,25 +177,29 @@ size_t membag_get_total(void)
  */
 size_t membag_get_smallest_free_block_size(void)
 {
-	uint8_t i;
-	struct membag *smallest_bag = NULL;
-
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		if (membag_list[i].blocks_free == 0) {
-			continue;
-		}
-
-		if (!smallest_bag ||
-				(smallest_bag->block_size > membag_list[i].block_size)) {
-			smallest_bag = &membag_list[i];
-		}
-	}
-
-	if (smallest_bag) {
-		return smallest_bag->block_size;
-	}
-
-	return 0;
+    uint8_t i;
+    struct membag *smallest_bag = NULL;
+
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        if (membag_list[i].blocks_free == 0)
+        {
+            continue;
+        }
+
+        if (!smallest_bag ||
+                (smallest_bag->block_size > membag_list[i].block_size))
+                {
+            smallest_bag = &membag_list[i];
+        }
+    }
+
+    if (smallest_bag)
+    {
+        return smallest_bag->block_size;
+    }
+
+    return 0;
 }
 
 /**
@@ -205,25 +212,29 @@ size_t membag_get_smallest_free_block_size(void)
  */
 size_t membag_get_largest_free_block_size(void)
 {
-	uint8_t i;
-	struct membag *largest_bag = NULL;
-
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		if (membag_list[i].blocks_free == 0) {
-			continue;
-		}
-
-		if (!largest_bag ||
-				(largest_bag->block_size < membag_list[i].block_size)) {
-			largest_bag = &membag_list[i];
-		}
-	}
-
-	if (largest_bag) {
-		return largest_bag->block_size;
-	}
-	
-	return 0;
+    uint8_t i;
+    struct membag *largest_bag = NULL;
+
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        if (membag_list[i].blocks_free == 0)
+        {
+            continue;
+        }
+
+        if (!largest_bag ||
+                (largest_bag->block_size < membag_list[i].block_size))
+                {
+            largest_bag = &membag_list[i];
+        }
+    }
+
+    if (largest_bag)
+    {
+        return largest_bag->block_size;
+    }
+
+    return 0;
 }
 
 /**
@@ -245,51 +256,58 @@ size_t membag_get_largest_free_block_size(void)
  */
 void *membag_alloc(const size_t size)
 {
-	uint8_t i;
-	struct membag *smallest_bag = NULL;
-	uintptr_t p;
-
-	/* Find the smallest available block size big enough for the requested
-	 * memory chunk size. */
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		if (membag_list[i].blocks_free == 0) {
-			continue;
-		}
-
-		if (membag_list[i].block_size >= size) {
-			if (!smallest_bag ||
-					(smallest_bag->block_size > membag_list[i].block_size)) {
-				smallest_bag = &membag_list[i];
-			}
-		}
-	}
-
-	/* We return the first available block in the bag that has one, and if
-	 * there is none, we return NULL.
-	 */
-	if (smallest_bag) {
-		/* We know that there is a free block within the membag's
-		 * memory, and we simply return the first one available.
-		 */
-		p = smallest_bag->start;
-
-		for (i = 0; i < smallest_bag->num_blocks; i++) {
-			/* Check the allocation byte to see whether the block is
-			 * in use. */
-			if (!(smallest_bag->allocated & ((uint32_t)1 << i))) {
-				/* It is free, set it to used. */
-				smallest_bag->allocated |= ((uint32_t)1 << i);
-				smallest_bag->blocks_free--;
-
-				return (void *)(p);
-			}
-
-			p += smallest_bag->block_size;
-		}
-	}
-
-	/* There is no available memory. Return NULL. */
-	return NULL;
+    uint8_t i;
+    struct membag *smallest_bag = NULL;
+    uintptr_t p;
+
+    /* Find the smallest available block size big enough for the requested
+     * memory chunk size. */
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        if (membag_list[i].blocks_free == 0)
+        {
+            continue;
+        }
+
+        if (membag_list[i].block_size >= size)
+        {
+            if (!smallest_bag ||
+                    (smallest_bag->block_size > membag_list[i].block_size))
+                    {
+                smallest_bag = &membag_list[i];
+            }
+        }
+    }
+
+    /* We return the first available block in the bag that has one, and if
+     * there is none, we return NULL.
+     */
+    if (smallest_bag)
+    {
+        /* We know that there is a free block within the membag's
+         * memory, and we simply return the first one available.
+         */
+        p = smallest_bag->start;
+
+        for (i = 0; i < smallest_bag->num_blocks; i++)
+        {
+            /* Check the allocation byte to see whether the block is
+             * in use. */
+            if (!(smallest_bag->allocated & ((uint32_t)1 << i)))
+            {
+                /* It is free, set it to used. */
+                smallest_bag->allocated |= ((uint32_t)1 << i);
+                smallest_bag->blocks_free--;
+
+                return (void *)(p);
+            }
+
+            p += smallest_bag->block_size;
+        }
+    }
+
+    /* There is no available memory. Return NULL. */
+    return NULL;
 }
 
 /**
@@ -307,19 +325,21 @@ void *membag_alloc(const size_t size)
  */
 void membag_free(const void *ptr)
 {
-	uint8_t i;
-	uintptr_t p = (uintptr_t)ptr;
-	uint8_t block_index;
-
-	for (i = 0; i < ARRAY_LEN(membag_list); i++) {
-		if (p >= membag_list[i].start && p < membag_list[i].end) {
-			block_index = (p - membag_list[i].start) / membag_list[i].block_size;
-			
-			/* Mark the memory as free. */
-			membag_list[i].allocated &= ~((uint32_t)1 << block_index);
-			membag_list[i].blocks_free++;
-
-			return;
-		}
-	}
+    uint8_t i;
+    uintptr_t p = (uintptr_t)ptr;
+    uint8_t block_index;
+
+    for (i = 0; i < ARRAY_LEN(membag_list); i++)
+    {
+        if (p >= membag_list[i].start && p < membag_list[i].end)
+        {
+            block_index = (p - membag_list[i].start) / membag_list[i].block_size;
+
+            /* Mark the memory as free. */
+            membag_list[i].allocated &= ~((uint32_t)1 << block_index);
+            membag_list[i].blocks_free++;
+
+            return;
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h
index 88495a53d337..5bcfd742b770 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/membag.h
@@ -93,7 +93,7 @@
  * \param nr_objs  Number of blocks in the bag, a value less than 32
  */
 #define MEMBAG(objsize, nr_objs)\
-	{ .block_size = objsize, .num_blocks = nr_objs }
+    { .block_size = objsize, .num_blocks = nr_objs }
 
 /**
  * Macro used to store the size of the membags in conf_membag.h
@@ -105,7 +105,7 @@
  * \param nr_objs  Number of blocks in the bag, a value less than 32
  */
 #define MEMBAG_SIZE(objsize, nr_objs)\
-	(objsize * nr_objs)
+    (objsize * nr_objs)
 
 void membag_init(void);
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h b/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h
index 3112435145fa..f03eab133c0a 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/membag/module_config/conf_membag.h
@@ -50,13 +50,13 @@
 #include <membag.h>
 
 #define CONF_MEMBAG_ARRAY\
-	MEMBAG(16, 5),\
-	MEMBAG(64, 2),\
-	MEMBAG(128, 10),
+    MEMBAG(16, 5),\
+    MEMBAG(64, 2),\
+    MEMBAG(128, 10),
 
 #define CONF_MEMBAG_POOL_SIZE\
-	MEMBAG_SIZE(16, 5) +\
-	MEMBAG_SIZE(64, 2) +\
-	MEMBAG_SIZE(128, 10)
+    MEMBAG_SIZE(16, 5) +\
+    MEMBAG_SIZE(64, 2) +\
+    MEMBAG_SIZE(128, 10)
 
 #endif /* CONF_MEMBAG_H */
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c
index e50748b4c06f..75f1ac56413e 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/osprintf/osprintf.c
@@ -51,53 +51,56 @@ xSemaphoreHandle trace_lock;
 
 void osprintf_init(void *usart, const void *opt)
 {
-	trace_lock = xSemaphoreCreateMutex();
-	stdio_serial_init(usart, opt);
+    trace_lock = xSemaphoreCreateMutex();
+    stdio_serial_init(usart, opt);
 }
 
 void osprintf(const char *fmt, ...)
 {
-	va_list args;
-	va_start(args, fmt);
-	xSemaphoreTake(trace_lock, portMAX_DELAY);
-	vprintf(fmt, args);
-	xSemaphoreGive(trace_lock);
-	va_end(args);
+    va_list args;
+    va_start(args, fmt);
+    xSemaphoreTake(trace_lock, portMAX_DELAY);
+    vprintf(fmt, args);
+    xSemaphoreGive(trace_lock);
+    va_end(args);
 }
 
 void osprint(const char *s)
 {
-	xSemaphoreTake(trace_lock, portMAX_DELAY);
-	puts(s);
-	xSemaphoreGive(trace_lock);		
+    xSemaphoreTake(trace_lock, portMAX_DELAY);
+    puts(s);
+    xSemaphoreGive(trace_lock);
 }
 
 void osprint_hex_array(uint8_t *p, int sz)
 {
-	xSemaphoreTake(trace_lock, portMAX_DELAY);
-	while (sz) {
-		if (sz < 8) {
-			while (sz--) {
-				printf("%02x ", *p);
-				p++;
-			}
-			break;
-		} 
-		printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",
-				p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
-		p += 8;
-		sz -= 8;
-	}
-	printf("\n");
-	xSemaphoreGive(trace_lock);
+    xSemaphoreTake(trace_lock, portMAX_DELAY);
+    while (sz)
+    {
+        if (sz < 8)
+        {
+            while (sz--)
+            {
+                printf("%02x ", *p);
+                p++;
+            }
+            break;
+        }
+        printf("%02x %02x %02x %02x %02x %02x %02x %02x\n",
+                p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+        p += 8;
+        sz -= 8;
+    }
+    printf("\n");
+    xSemaphoreGive(trace_lock);
 }
- 
+
 void osprint_sem_take(void)
 {
-	xSemaphoreTake(trace_lock, portMAX_DELAY);
+    xSemaphoreTake(trace_lock, portMAX_DELAY);
 }
 
 void osprint_sem_give(void)
 {
-	xSemaphoreGive(trace_lock);
+    xSemaphoreGive(trace_lock);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/parts.h b/bsp/samd21/sam_d2x_asflib/common/utils/parts.h
index 27cbe5fd2f39..fe7e8fadafdf 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/parts.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/parts.h
@@ -63,11 +63,11 @@
  */
 /* ! Check GCC and IAR part definition for 8-bit AVR */
 #define AVR8_PART_IS_DEFINED(part) \
-	(defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
+    (defined(__ ## part ## __) || defined(__AVR_ ## part ## __))
 
 /* ! Check GCC and IAR part definition for 32-bit AVR */
 #define AVR32_PART_IS_DEFINED(part) \
-	(defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
+    (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __))
 
 /* ! Check GCC and IAR part definition for SAM */
 #define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __))
@@ -82,126 +82,126 @@
  * \name AVR UC3 A series
  * @{
  */
-#define UC3A0 (	\
-		AVR32_PART_IS_DEFINED(UC3A0128) || \
-		AVR32_PART_IS_DEFINED(UC3A0256) || \
-		AVR32_PART_IS_DEFINED(UC3A0512)	\
-		)
-
-#define UC3A1 (	\
-		AVR32_PART_IS_DEFINED(UC3A1128) || \
-		AVR32_PART_IS_DEFINED(UC3A1256) || \
-		AVR32_PART_IS_DEFINED(UC3A1512)	\
-		)
-
-#define UC3A3 (	\
-		AVR32_PART_IS_DEFINED(UC3A364)   || \
-		AVR32_PART_IS_DEFINED(UC3A364S)  || \
-		AVR32_PART_IS_DEFINED(UC3A3128)  || \
-		AVR32_PART_IS_DEFINED(UC3A3128S) || \
-		AVR32_PART_IS_DEFINED(UC3A3256)  || \
-		AVR32_PART_IS_DEFINED(UC3A3256S) \
-		)
-
-#define UC3A4 (	\
-		AVR32_PART_IS_DEFINED(UC3A464)   || \
-		AVR32_PART_IS_DEFINED(UC3A464S)  || \
-		AVR32_PART_IS_DEFINED(UC3A4128)  || \
-		AVR32_PART_IS_DEFINED(UC3A4128S) || \
-		AVR32_PART_IS_DEFINED(UC3A4256)  || \
-		AVR32_PART_IS_DEFINED(UC3A4256S) \
-		)
+#define UC3A0 ( \
+        AVR32_PART_IS_DEFINED(UC3A0128) || \
+        AVR32_PART_IS_DEFINED(UC3A0256) || \
+        AVR32_PART_IS_DEFINED(UC3A0512) \
+        )
+
+#define UC3A1 ( \
+        AVR32_PART_IS_DEFINED(UC3A1128) || \
+        AVR32_PART_IS_DEFINED(UC3A1256) || \
+        AVR32_PART_IS_DEFINED(UC3A1512) \
+        )
+
+#define UC3A3 ( \
+        AVR32_PART_IS_DEFINED(UC3A364)   || \
+        AVR32_PART_IS_DEFINED(UC3A364S)  || \
+        AVR32_PART_IS_DEFINED(UC3A3128)  || \
+        AVR32_PART_IS_DEFINED(UC3A3128S) || \
+        AVR32_PART_IS_DEFINED(UC3A3256)  || \
+        AVR32_PART_IS_DEFINED(UC3A3256S) \
+        )
+
+#define UC3A4 ( \
+        AVR32_PART_IS_DEFINED(UC3A464)   || \
+        AVR32_PART_IS_DEFINED(UC3A464S)  || \
+        AVR32_PART_IS_DEFINED(UC3A4128)  || \
+        AVR32_PART_IS_DEFINED(UC3A4128S) || \
+        AVR32_PART_IS_DEFINED(UC3A4256)  || \
+        AVR32_PART_IS_DEFINED(UC3A4256S) \
+        )
 /** @} */
 
 /**
  * \name AVR UC3 B series
  * @{
  */
-#define UC3B0 (	\
-		AVR32_PART_IS_DEFINED(UC3B064)  || \
-		AVR32_PART_IS_DEFINED(UC3B0128) || \
-		AVR32_PART_IS_DEFINED(UC3B0256) || \
-		AVR32_PART_IS_DEFINED(UC3B0512)	\
-		)
-
-#define UC3B1 (	\
-		AVR32_PART_IS_DEFINED(UC3B164)  || \
-		AVR32_PART_IS_DEFINED(UC3B1128) || \
-		AVR32_PART_IS_DEFINED(UC3B1256) || \
-		AVR32_PART_IS_DEFINED(UC3B1512)	\
-		)
+#define UC3B0 ( \
+        AVR32_PART_IS_DEFINED(UC3B064)  || \
+        AVR32_PART_IS_DEFINED(UC3B0128) || \
+        AVR32_PART_IS_DEFINED(UC3B0256) || \
+        AVR32_PART_IS_DEFINED(UC3B0512) \
+        )
+
+#define UC3B1 ( \
+        AVR32_PART_IS_DEFINED(UC3B164)  || \
+        AVR32_PART_IS_DEFINED(UC3B1128) || \
+        AVR32_PART_IS_DEFINED(UC3B1256) || \
+        AVR32_PART_IS_DEFINED(UC3B1512) \
+        )
 /** @} */
 
 /**
  * \name AVR UC3 C series
  * @{
  */
-#define UC3C0 (	\
-		AVR32_PART_IS_DEFINED(UC3C064C)  || \
-		AVR32_PART_IS_DEFINED(UC3C0128C) || \
-		AVR32_PART_IS_DEFINED(UC3C0256C) || \
-		AVR32_PART_IS_DEFINED(UC3C0512C) \
-		)
-
-#define UC3C1 (	\
-		AVR32_PART_IS_DEFINED(UC3C164C)  || \
-		AVR32_PART_IS_DEFINED(UC3C1128C) || \
-		AVR32_PART_IS_DEFINED(UC3C1256C) || \
-		AVR32_PART_IS_DEFINED(UC3C1512C) \
-		)
-
-#define UC3C2 (	\
-		AVR32_PART_IS_DEFINED(UC3C264C)  || \
-		AVR32_PART_IS_DEFINED(UC3C2128C) || \
-		AVR32_PART_IS_DEFINED(UC3C2256C) || \
-		AVR32_PART_IS_DEFINED(UC3C2512C) \
-		)
+#define UC3C0 ( \
+        AVR32_PART_IS_DEFINED(UC3C064C)  || \
+        AVR32_PART_IS_DEFINED(UC3C0128C) || \
+        AVR32_PART_IS_DEFINED(UC3C0256C) || \
+        AVR32_PART_IS_DEFINED(UC3C0512C) \
+        )
+
+#define UC3C1 ( \
+        AVR32_PART_IS_DEFINED(UC3C164C)  || \
+        AVR32_PART_IS_DEFINED(UC3C1128C) || \
+        AVR32_PART_IS_DEFINED(UC3C1256C) || \
+        AVR32_PART_IS_DEFINED(UC3C1512C) \
+        )
+
+#define UC3C2 ( \
+        AVR32_PART_IS_DEFINED(UC3C264C)  || \
+        AVR32_PART_IS_DEFINED(UC3C2128C) || \
+        AVR32_PART_IS_DEFINED(UC3C2256C) || \
+        AVR32_PART_IS_DEFINED(UC3C2512C) \
+        )
 /** @} */
 
 /**
  * \name AVR UC3 D series
  * @{
  */
-#define UC3D3 (	\
-		AVR32_PART_IS_DEFINED(UC64D3)  || \
-		AVR32_PART_IS_DEFINED(UC128D3) \
-		)
-
-#define UC3D4 (	\
-		AVR32_PART_IS_DEFINED(UC64D4)  || \
-		AVR32_PART_IS_DEFINED(UC128D4) \
-		)
+#define UC3D3 ( \
+        AVR32_PART_IS_DEFINED(UC64D3)  || \
+        AVR32_PART_IS_DEFINED(UC128D3) \
+        )
+
+#define UC3D4 ( \
+        AVR32_PART_IS_DEFINED(UC64D4)  || \
+        AVR32_PART_IS_DEFINED(UC128D4) \
+        )
 /** @} */
 
 /**
  * \name AVR UC3 L series
  * @{
  */
-#define UC3L0 (	\
-		AVR32_PART_IS_DEFINED(UC3L016) || \
-		AVR32_PART_IS_DEFINED(UC3L032) || \
-		AVR32_PART_IS_DEFINED(UC3L064) \
-		)
+#define UC3L0 ( \
+        AVR32_PART_IS_DEFINED(UC3L016) || \
+        AVR32_PART_IS_DEFINED(UC3L032) || \
+        AVR32_PART_IS_DEFINED(UC3L064) \
+        )
 
 #define UC3L0128 ( \
-		AVR32_PART_IS_DEFINED(UC3L0128)	\
-		)
+        AVR32_PART_IS_DEFINED(UC3L0128) \
+        )
 
 #define UC3L0256 ( \
-		AVR32_PART_IS_DEFINED(UC3L0256)	\
-		)
+        AVR32_PART_IS_DEFINED(UC3L0256) \
+        )
 
-#define UC3L3 (	\
-		AVR32_PART_IS_DEFINED(UC64L3U)  || \
-		AVR32_PART_IS_DEFINED(UC128L3U) || \
-		AVR32_PART_IS_DEFINED(UC256L3U)	\
-		)
+#define UC3L3 ( \
+        AVR32_PART_IS_DEFINED(UC64L3U)  || \
+        AVR32_PART_IS_DEFINED(UC128L3U) || \
+        AVR32_PART_IS_DEFINED(UC256L3U) \
+        )
 
-#define UC3L4 (	\
-		AVR32_PART_IS_DEFINED(UC64L4U)  || \
-		AVR32_PART_IS_DEFINED(UC128L4U) || \
-		AVR32_PART_IS_DEFINED(UC256L4U)	\
-		)
+#define UC3L4 ( \
+        AVR32_PART_IS_DEFINED(UC64L4U)  || \
+        AVR32_PART_IS_DEFINED(UC128L4U) || \
+        AVR32_PART_IS_DEFINED(UC256L4U) \
+        )
 
 #define UC3L3_L4 (UC3L3 || UC3L4)
 /** @} */
@@ -241,25 +241,25 @@
  * @{
  */
 #define XMEGA_A1 ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A1)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A1) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64A1)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128A1) \
+        )
 
 #define XMEGA_A3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A3) || \
-		AVR8_PART_IS_DEFINED(ATxmega192A3) || \
-		AVR8_PART_IS_DEFINED(ATxmega256A3) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64A3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128A3) || \
+        AVR8_PART_IS_DEFINED(ATxmega192A3) || \
+        AVR8_PART_IS_DEFINED(ATxmega256A3) \
+        )
 
 #define XMEGA_A3B ( \
-		AVR8_PART_IS_DEFINED(ATxmega256A3B) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega256A3B) \
+        )
 
 #define XMEGA_A4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega16A4) || \
-		AVR8_PART_IS_DEFINED(ATxmega32A4) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega16A4) || \
+        AVR8_PART_IS_DEFINED(ATxmega32A4) \
+        )
 /** @} */
 
 /**
@@ -267,27 +267,27 @@
  * @{
  */
 #define XMEGA_A1U ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A1U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A1U) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64A1U)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128A1U) \
+        )
 
 #define XMEGA_A3U ( \
-		AVR8_PART_IS_DEFINED(ATxmega64A3U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
-		AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
-		AVR8_PART_IS_DEFINED(ATxmega256A3U) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64A3U)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128A3U) || \
+        AVR8_PART_IS_DEFINED(ATxmega192A3U) || \
+        AVR8_PART_IS_DEFINED(ATxmega256A3U) \
+        )
 
 #define XMEGA_A3BU ( \
-		AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega256A3BU) \
+        )
 
 #define XMEGA_A4U ( \
-		AVR8_PART_IS_DEFINED(ATxmega16A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64A4U)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128A4U) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega16A4U)  || \
+        AVR8_PART_IS_DEFINED(ATxmega32A4U)  || \
+        AVR8_PART_IS_DEFINED(ATxmega64A4U)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128A4U) \
+        )
 /** @} */
 
 /**
@@ -295,14 +295,14 @@
  * @{
  */
 #define XMEGA_B1  ( \
-		AVR8_PART_IS_DEFINED(ATxmega64B1)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128B1) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64B1)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128B1) \
+        )
 
 #define XMEGA_B3  ( \
-		AVR8_PART_IS_DEFINED(ATxmega64B3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128B3) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega64B3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128B3) \
+        )
 /** @} */
 
 /**
@@ -310,18 +310,18 @@
  * @{
  */
 #define XMEGA_C3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega384C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega256C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega192C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128C3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64C3)   || \
-		AVR8_PART_IS_DEFINED(ATxmega32C3) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega384C3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega256C3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega192C3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128C3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega64C3)   || \
+        AVR8_PART_IS_DEFINED(ATxmega32C3) \
+        )
 
 #define XMEGA_C4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega32C4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega16C4) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega32C4)  || \
+        AVR8_PART_IS_DEFINED(ATxmega16C4) \
+        )
 /** @} */
 
 /**
@@ -329,20 +329,20 @@
  * @{
  */
 #define XMEGA_D3 ( \
-		AVR8_PART_IS_DEFINED(ATxmega32D3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64D3)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega192D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega256D3) || \
-		AVR8_PART_IS_DEFINED(ATxmega384D3) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega32D3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega64D3)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128D3) || \
+        AVR8_PART_IS_DEFINED(ATxmega192D3) || \
+        AVR8_PART_IS_DEFINED(ATxmega256D3) || \
+        AVR8_PART_IS_DEFINED(ATxmega384D3) \
+        )
 
 #define XMEGA_D4 ( \
-		AVR8_PART_IS_DEFINED(ATxmega16D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega64D4)  || \
-		AVR8_PART_IS_DEFINED(ATxmega128D4) \
-		)
+        AVR8_PART_IS_DEFINED(ATxmega16D4)  || \
+        AVR8_PART_IS_DEFINED(ATxmega32D4)  || \
+        AVR8_PART_IS_DEFINED(ATxmega64D4)  || \
+        AVR8_PART_IS_DEFINED(ATxmega128D4) \
+        )
 /** @} */
 
 /**
@@ -350,10 +350,10 @@
  * @{
  */
 #define XMEGA_E5 ( \
-		AVR8_PART_IS_DEFINED(ATxmega8E5)   || \
-		AVR8_PART_IS_DEFINED(ATxmega16E5)  || \
-		AVR8_PART_IS_DEFINED(ATxmega32E5)     \
-	)
+        AVR8_PART_IS_DEFINED(ATxmega8E5)   || \
+        AVR8_PART_IS_DEFINED(ATxmega16E5)  || \
+        AVR8_PART_IS_DEFINED(ATxmega32E5)     \
+    )
 /** @} */
 
 
@@ -401,15 +401,15 @@
  * @{
  */
 #define MEGA_XX0 ( \
-		AVR8_PART_IS_DEFINED(ATmega640)  || \
-		AVR8_PART_IS_DEFINED(ATmega1280) || \
-		AVR8_PART_IS_DEFINED(ATmega2560) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega640)  || \
+        AVR8_PART_IS_DEFINED(ATmega1280) || \
+        AVR8_PART_IS_DEFINED(ATmega2560) \
+        )
 
 #define MEGA_XX1 ( \
-		AVR8_PART_IS_DEFINED(ATmega1281) || \
-		AVR8_PART_IS_DEFINED(ATmega2561) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega1281) || \
+        AVR8_PART_IS_DEFINED(ATmega2561) \
+        )
 /** @} */
 
 /**
@@ -421,92 +421,92 @@
 
 /** ATmegaxx4 group */
 #define MEGA_XX4 ( \
-		AVR8_PART_IS_DEFINED(ATmega164A)  || \
-		AVR8_PART_IS_DEFINED(ATmega164PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324A)  || \
-		AVR8_PART_IS_DEFINED(ATmega324PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324PB) || \
-		AVR8_PART_IS_DEFINED(ATmega644)   || \
-		AVR8_PART_IS_DEFINED(ATmega644A)  || \
-		AVR8_PART_IS_DEFINED(ATmega644PA) || \
-		AVR8_PART_IS_DEFINED(ATmega1284P)   || \
-		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega164A)  || \
+        AVR8_PART_IS_DEFINED(ATmega164PA) || \
+        AVR8_PART_IS_DEFINED(ATmega324A)  || \
+        AVR8_PART_IS_DEFINED(ATmega324PA) || \
+        AVR8_PART_IS_DEFINED(ATmega324PB) || \
+        AVR8_PART_IS_DEFINED(ATmega644)   || \
+        AVR8_PART_IS_DEFINED(ATmega644A)  || \
+        AVR8_PART_IS_DEFINED(ATmega644PA) || \
+        AVR8_PART_IS_DEFINED(ATmega1284P)   || \
+        AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+        )
 
 /** ATmegaxx4 group */
 #define MEGA_XX4_A ( \
-		AVR8_PART_IS_DEFINED(ATmega164A)  || \
-		AVR8_PART_IS_DEFINED(ATmega164PA) || \
-		AVR8_PART_IS_DEFINED(ATmega324A)  || \
-		AVR8_PART_IS_DEFINED(ATmega324PA) || \
-		AVR8_PART_IS_DEFINED(ATmega644A)  || \
-		AVR8_PART_IS_DEFINED(ATmega644PA) || \
-		AVR8_PART_IS_DEFINED(ATmega1284P) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega164A)  || \
+        AVR8_PART_IS_DEFINED(ATmega164PA) || \
+        AVR8_PART_IS_DEFINED(ATmega324A)  || \
+        AVR8_PART_IS_DEFINED(ATmega324PA) || \
+        AVR8_PART_IS_DEFINED(ATmega644A)  || \
+        AVR8_PART_IS_DEFINED(ATmega644PA) || \
+        AVR8_PART_IS_DEFINED(ATmega1284P) \
+        )
 
 /** ATmegaxx8 group */
 #define MEGA_XX8 ( \
-		AVR8_PART_IS_DEFINED(ATmega48)    || \
-		AVR8_PART_IS_DEFINED(ATmega48A)   || \
-		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega48PB)  || \
-		AVR8_PART_IS_DEFINED(ATmega88)    || \
-		AVR8_PART_IS_DEFINED(ATmega88A)   || \
-		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega88PB)  || \
-		AVR8_PART_IS_DEFINED(ATmega168)   || \
-		AVR8_PART_IS_DEFINED(ATmega168A)  || \
-		AVR8_PART_IS_DEFINED(ATmega168PA) || \
-		AVR8_PART_IS_DEFINED(ATmega168PB) || \
-		AVR8_PART_IS_DEFINED(ATmega328)   || \
-		AVR8_PART_IS_DEFINED(ATmega328P)  || \
-		AVR8_PART_IS_DEFINED(ATmega328PB) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega48)    || \
+        AVR8_PART_IS_DEFINED(ATmega48A)   || \
+        AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+        AVR8_PART_IS_DEFINED(ATmega48PB)  || \
+        AVR8_PART_IS_DEFINED(ATmega88)    || \
+        AVR8_PART_IS_DEFINED(ATmega88A)   || \
+        AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+        AVR8_PART_IS_DEFINED(ATmega88PB)  || \
+        AVR8_PART_IS_DEFINED(ATmega168)   || \
+        AVR8_PART_IS_DEFINED(ATmega168A)  || \
+        AVR8_PART_IS_DEFINED(ATmega168PA) || \
+        AVR8_PART_IS_DEFINED(ATmega168PB) || \
+        AVR8_PART_IS_DEFINED(ATmega328)   || \
+        AVR8_PART_IS_DEFINED(ATmega328P)  || \
+        AVR8_PART_IS_DEFINED(ATmega328PB) \
+        )
 
 /** ATmegaxx8A/P/PA group */
 #define MEGA_XX8_A ( \
-		AVR8_PART_IS_DEFINED(ATmega48A)   || \
-		AVR8_PART_IS_DEFINED(ATmega48PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega88A)   || \
-		AVR8_PART_IS_DEFINED(ATmega88PA)  || \
-		AVR8_PART_IS_DEFINED(ATmega168A)  || \
-		AVR8_PART_IS_DEFINED(ATmega168PA) || \
-		AVR8_PART_IS_DEFINED(ATmega328P) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega48A)   || \
+        AVR8_PART_IS_DEFINED(ATmega48PA)  || \
+        AVR8_PART_IS_DEFINED(ATmega88A)   || \
+        AVR8_PART_IS_DEFINED(ATmega88PA)  || \
+        AVR8_PART_IS_DEFINED(ATmega168A)  || \
+        AVR8_PART_IS_DEFINED(ATmega168PA) || \
+        AVR8_PART_IS_DEFINED(ATmega328P) \
+        )
 
 /** ATmegaxx group */
 #define MEGA_XX ( \
-		AVR8_PART_IS_DEFINED(ATmega16)   || \
-		AVR8_PART_IS_DEFINED(ATmega16A)  || \
-		AVR8_PART_IS_DEFINED(ATmega32)   || \
-		AVR8_PART_IS_DEFINED(ATmega32A)  || \
-		AVR8_PART_IS_DEFINED(ATmega64)   || \
-		AVR8_PART_IS_DEFINED(ATmega64A)  || \
-		AVR8_PART_IS_DEFINED(ATmega128)  || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega16)   || \
+        AVR8_PART_IS_DEFINED(ATmega16A)  || \
+        AVR8_PART_IS_DEFINED(ATmega32)   || \
+        AVR8_PART_IS_DEFINED(ATmega32A)  || \
+        AVR8_PART_IS_DEFINED(ATmega64)   || \
+        AVR8_PART_IS_DEFINED(ATmega64A)  || \
+        AVR8_PART_IS_DEFINED(ATmega128)  || \
+        AVR8_PART_IS_DEFINED(ATmega128A) \
+        )
 
 /** ATmegaxxA/P/PA group */
 #define MEGA_XX_A ( \
-		AVR8_PART_IS_DEFINED(ATmega16A)  || \
-		AVR8_PART_IS_DEFINED(ATmega32A)  || \
-		AVR8_PART_IS_DEFINED(ATmega64A)  || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega16A)  || \
+        AVR8_PART_IS_DEFINED(ATmega32A)  || \
+        AVR8_PART_IS_DEFINED(ATmega64A)  || \
+        AVR8_PART_IS_DEFINED(ATmega128A) \
+        )
 /** ATmegaxxRFA1 group */
 #define MEGA_RFA1 ( \
-		AVR8_PART_IS_DEFINED(ATmega128RFA1) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega128RFA1) \
+        )
 
 /** ATmegaxxRFR2 group */
 #define MEGA_RFR2 ( \
-		AVR8_PART_IS_DEFINED(ATmega64RFR2)   || \
-		AVR8_PART_IS_DEFINED(ATmega128RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega256RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega644RFR2)  || \
-		AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
-		AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega64RFR2)   || \
+        AVR8_PART_IS_DEFINED(ATmega128RFR2)  || \
+        AVR8_PART_IS_DEFINED(ATmega256RFR2)  || \
+        AVR8_PART_IS_DEFINED(ATmega644RFR2)  || \
+        AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \
+        AVR8_PART_IS_DEFINED(ATmega2564RFR2) \
+        )
 
 
 /** ATmegaxxRFxx group */
@@ -517,115 +517,115 @@
  * @{
  */
 #define MEGA_XX_UN0 ( \
-		AVR8_PART_IS_DEFINED(ATmega16)    || \
-		AVR8_PART_IS_DEFINED(ATmega16A)   || \
-		AVR8_PART_IS_DEFINED(ATmega32)    || \
-		AVR8_PART_IS_DEFINED(ATmega32A)	\
-		)
+        AVR8_PART_IS_DEFINED(ATmega16)    || \
+        AVR8_PART_IS_DEFINED(ATmega16A)   || \
+        AVR8_PART_IS_DEFINED(ATmega32)    || \
+        AVR8_PART_IS_DEFINED(ATmega32A) \
+        )
 
 /** ATmegaxx group without power reduction and
  *  And interrupt sense register.
  */
 #define MEGA_XX_UN1 ( \
-		AVR8_PART_IS_DEFINED(ATmega64)    || \
-		AVR8_PART_IS_DEFINED(ATmega64A)   || \
-		AVR8_PART_IS_DEFINED(ATmega128)   || \
-		AVR8_PART_IS_DEFINED(ATmega128A) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega64)    || \
+        AVR8_PART_IS_DEFINED(ATmega64A)   || \
+        AVR8_PART_IS_DEFINED(ATmega128)   || \
+        AVR8_PART_IS_DEFINED(ATmega128A) \
+        )
 
 /** ATmegaxx group without power reduction and
  *  And interrupt sense register.
  */
 #define MEGA_XX_UN2 ( \
-		AVR8_PART_IS_DEFINED(ATmega169P)  || \
-		AVR8_PART_IS_DEFINED(ATmega169PA) || \
-		AVR8_PART_IS_DEFINED(ATmega329P)  || \
-		AVR8_PART_IS_DEFINED(ATmega329PA) \
-		)
+        AVR8_PART_IS_DEFINED(ATmega169P)  || \
+        AVR8_PART_IS_DEFINED(ATmega169PA) || \
+        AVR8_PART_IS_DEFINED(ATmega329P)  || \
+        AVR8_PART_IS_DEFINED(ATmega329PA) \
+        )
 
 /** Devices added to complete megaAVR offering.
  *  Please do not use this group symbol as it is not intended
  *  to be permanent: the devices should be regrouped.
  */
 #define MEGA_UNCATEGORIZED ( \
-		AVR8_PART_IS_DEFINED(AT90CAN128)     || \
-		AVR8_PART_IS_DEFINED(AT90CAN32)      || \
-		AVR8_PART_IS_DEFINED(AT90CAN64)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM1)       || \
-		AVR8_PART_IS_DEFINED(AT90PWM216)     || \
-		AVR8_PART_IS_DEFINED(AT90PWM2B)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM316)     || \
-		AVR8_PART_IS_DEFINED(AT90PWM3B)      || \
-		AVR8_PART_IS_DEFINED(AT90PWM81)      || \
-		AVR8_PART_IS_DEFINED(AT90USB1286)    || \
-		AVR8_PART_IS_DEFINED(AT90USB1287)    || \
-		AVR8_PART_IS_DEFINED(AT90USB162)     || \
-		AVR8_PART_IS_DEFINED(AT90USB646)     || \
-		AVR8_PART_IS_DEFINED(AT90USB647)     || \
-		AVR8_PART_IS_DEFINED(AT90USB82)      || \
-		AVR8_PART_IS_DEFINED(ATmega1284)     || \
-		AVR8_PART_IS_DEFINED(ATmega162)      || \
-		AVR8_PART_IS_DEFINED(ATmega164P)     || \
-		AVR8_PART_IS_DEFINED(ATmega165A)     || \
-		AVR8_PART_IS_DEFINED(ATmega165P)     || \
-		AVR8_PART_IS_DEFINED(ATmega165PA)    || \
-		AVR8_PART_IS_DEFINED(ATmega168P)     || \
-		AVR8_PART_IS_DEFINED(ATmega169A)     || \
-		AVR8_PART_IS_DEFINED(ATmega16M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega16U2)     || \
-		AVR8_PART_IS_DEFINED(ATmega16U4)     || \
-		AVR8_PART_IS_DEFINED(ATmega256RFA2)  || \
-		AVR8_PART_IS_DEFINED(ATmega324P)     || \
-		AVR8_PART_IS_DEFINED(ATmega325)      || \
-		AVR8_PART_IS_DEFINED(ATmega3250)     || \
-		AVR8_PART_IS_DEFINED(ATmega3250A)    || \
-		AVR8_PART_IS_DEFINED(ATmega3250P)    || \
-		AVR8_PART_IS_DEFINED(ATmega3250PA)   || \
-		AVR8_PART_IS_DEFINED(ATmega325A)     || \
-		AVR8_PART_IS_DEFINED(ATmega325P)     || \
-		AVR8_PART_IS_DEFINED(ATmega325PA)    || \
-		AVR8_PART_IS_DEFINED(ATmega329)      || \
-		AVR8_PART_IS_DEFINED(ATmega3290)     || \
-		AVR8_PART_IS_DEFINED(ATmega3290A)    || \
-		AVR8_PART_IS_DEFINED(ATmega3290P)    || \
-		AVR8_PART_IS_DEFINED(ATmega3290PA)   || \
-		AVR8_PART_IS_DEFINED(ATmega329A)     || \
-		AVR8_PART_IS_DEFINED(ATmega32M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega32U2)     || \
-		AVR8_PART_IS_DEFINED(ATmega32U4)     || \
-		AVR8_PART_IS_DEFINED(ATmega48P)      || \
-		AVR8_PART_IS_DEFINED(ATmega644P)     || \
-		AVR8_PART_IS_DEFINED(ATmega645)      || \
-		AVR8_PART_IS_DEFINED(ATmega6450)     || \
-		AVR8_PART_IS_DEFINED(ATmega6450A)    || \
-		AVR8_PART_IS_DEFINED(ATmega6450P)    || \
-		AVR8_PART_IS_DEFINED(ATmega645A)     || \
-		AVR8_PART_IS_DEFINED(ATmega645P)     || \
-		AVR8_PART_IS_DEFINED(ATmega649)      || \
-		AVR8_PART_IS_DEFINED(ATmega6490)     || \
-		AVR8_PART_IS_DEFINED(ATmega6490A)    || \
-		AVR8_PART_IS_DEFINED(ATmega6490P)    || \
-		AVR8_PART_IS_DEFINED(ATmega649A)     || \
-		AVR8_PART_IS_DEFINED(ATmega649P)     || \
-		AVR8_PART_IS_DEFINED(ATmega64M1)     || \
-		AVR8_PART_IS_DEFINED(ATmega64RFA2)   || \
-		AVR8_PART_IS_DEFINED(ATmega8)        || \
-		AVR8_PART_IS_DEFINED(ATmega8515)     || \
-		AVR8_PART_IS_DEFINED(ATmega8535)     || \
-		AVR8_PART_IS_DEFINED(ATmega88P)      || \
-		AVR8_PART_IS_DEFINED(ATmega8A)       || \
-		AVR8_PART_IS_DEFINED(ATmega8U2)         \
-	)
+        AVR8_PART_IS_DEFINED(AT90CAN128)     || \
+        AVR8_PART_IS_DEFINED(AT90CAN32)      || \
+        AVR8_PART_IS_DEFINED(AT90CAN64)      || \
+        AVR8_PART_IS_DEFINED(AT90PWM1)       || \
+        AVR8_PART_IS_DEFINED(AT90PWM216)     || \
+        AVR8_PART_IS_DEFINED(AT90PWM2B)      || \
+        AVR8_PART_IS_DEFINED(AT90PWM316)     || \
+        AVR8_PART_IS_DEFINED(AT90PWM3B)      || \
+        AVR8_PART_IS_DEFINED(AT90PWM81)      || \
+        AVR8_PART_IS_DEFINED(AT90USB1286)    || \
+        AVR8_PART_IS_DEFINED(AT90USB1287)    || \
+        AVR8_PART_IS_DEFINED(AT90USB162)     || \
+        AVR8_PART_IS_DEFINED(AT90USB646)     || \
+        AVR8_PART_IS_DEFINED(AT90USB647)     || \
+        AVR8_PART_IS_DEFINED(AT90USB82)      || \
+        AVR8_PART_IS_DEFINED(ATmega1284)     || \
+        AVR8_PART_IS_DEFINED(ATmega162)      || \
+        AVR8_PART_IS_DEFINED(ATmega164P)     || \
+        AVR8_PART_IS_DEFINED(ATmega165A)     || \
+        AVR8_PART_IS_DEFINED(ATmega165P)     || \
+        AVR8_PART_IS_DEFINED(ATmega165PA)    || \
+        AVR8_PART_IS_DEFINED(ATmega168P)     || \
+        AVR8_PART_IS_DEFINED(ATmega169A)     || \
+        AVR8_PART_IS_DEFINED(ATmega16M1)     || \
+        AVR8_PART_IS_DEFINED(ATmega16U2)     || \
+        AVR8_PART_IS_DEFINED(ATmega16U4)     || \
+        AVR8_PART_IS_DEFINED(ATmega256RFA2)  || \
+        AVR8_PART_IS_DEFINED(ATmega324P)     || \
+        AVR8_PART_IS_DEFINED(ATmega325)      || \
+        AVR8_PART_IS_DEFINED(ATmega3250)     || \
+        AVR8_PART_IS_DEFINED(ATmega3250A)    || \
+        AVR8_PART_IS_DEFINED(ATmega3250P)    || \
+        AVR8_PART_IS_DEFINED(ATmega3250PA)   || \
+        AVR8_PART_IS_DEFINED(ATmega325A)     || \
+        AVR8_PART_IS_DEFINED(ATmega325P)     || \
+        AVR8_PART_IS_DEFINED(ATmega325PA)    || \
+        AVR8_PART_IS_DEFINED(ATmega329)      || \
+        AVR8_PART_IS_DEFINED(ATmega3290)     || \
+        AVR8_PART_IS_DEFINED(ATmega3290A)    || \
+        AVR8_PART_IS_DEFINED(ATmega3290P)    || \
+        AVR8_PART_IS_DEFINED(ATmega3290PA)   || \
+        AVR8_PART_IS_DEFINED(ATmega329A)     || \
+        AVR8_PART_IS_DEFINED(ATmega32M1)     || \
+        AVR8_PART_IS_DEFINED(ATmega32U2)     || \
+        AVR8_PART_IS_DEFINED(ATmega32U4)     || \
+        AVR8_PART_IS_DEFINED(ATmega48P)      || \
+        AVR8_PART_IS_DEFINED(ATmega644P)     || \
+        AVR8_PART_IS_DEFINED(ATmega645)      || \
+        AVR8_PART_IS_DEFINED(ATmega6450)     || \
+        AVR8_PART_IS_DEFINED(ATmega6450A)    || \
+        AVR8_PART_IS_DEFINED(ATmega6450P)    || \
+        AVR8_PART_IS_DEFINED(ATmega645A)     || \
+        AVR8_PART_IS_DEFINED(ATmega645P)     || \
+        AVR8_PART_IS_DEFINED(ATmega649)      || \
+        AVR8_PART_IS_DEFINED(ATmega6490)     || \
+        AVR8_PART_IS_DEFINED(ATmega6490A)    || \
+        AVR8_PART_IS_DEFINED(ATmega6490P)    || \
+        AVR8_PART_IS_DEFINED(ATmega649A)     || \
+        AVR8_PART_IS_DEFINED(ATmega649P)     || \
+        AVR8_PART_IS_DEFINED(ATmega64M1)     || \
+        AVR8_PART_IS_DEFINED(ATmega64RFA2)   || \
+        AVR8_PART_IS_DEFINED(ATmega8)        || \
+        AVR8_PART_IS_DEFINED(ATmega8515)     || \
+        AVR8_PART_IS_DEFINED(ATmega8535)     || \
+        AVR8_PART_IS_DEFINED(ATmega88P)      || \
+        AVR8_PART_IS_DEFINED(ATmega8A)       || \
+        AVR8_PART_IS_DEFINED(ATmega8U2)         \
+    )
 
 /** Unspecified group */
 #define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \
-	MEGA_UNCATEGORIZED)
+    MEGA_UNCATEGORIZED)
 
 /** @} */
 
 /** megaAVR product line */
 #define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \
-	MEGA_UNSPECIFIED)
+    MEGA_UNSPECIFIED)
 
 /** @} */
 
@@ -639,32 +639,32 @@
  * @{
  */
 #define SAM3S1 ( \
-		SAM_PART_IS_DEFINED(SAM3S1A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S1B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S1C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3S1A) || \
+        SAM_PART_IS_DEFINED(SAM3S1B) || \
+        SAM_PART_IS_DEFINED(SAM3S1C) \
+        )
 
 #define SAM3S2 ( \
-		SAM_PART_IS_DEFINED(SAM3S2A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S2B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S2C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3S2A) || \
+        SAM_PART_IS_DEFINED(SAM3S2B) || \
+        SAM_PART_IS_DEFINED(SAM3S2C) \
+        )
 
 #define SAM3S4 ( \
-		SAM_PART_IS_DEFINED(SAM3S4A) ||	\
-		SAM_PART_IS_DEFINED(SAM3S4B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S4C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3S4A) || \
+        SAM_PART_IS_DEFINED(SAM3S4B) || \
+        SAM_PART_IS_DEFINED(SAM3S4C) \
+        )
 
 #define SAM3S8 ( \
-		SAM_PART_IS_DEFINED(SAM3S8B) ||	\
-		SAM_PART_IS_DEFINED(SAM3S8C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3S8B) || \
+        SAM_PART_IS_DEFINED(SAM3S8C) \
+        )
 
 #define SAM3SD8 ( \
-		SAM_PART_IS_DEFINED(SAM3SD8B) || \
-		SAM_PART_IS_DEFINED(SAM3SD8C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3SD8B) || \
+        SAM_PART_IS_DEFINED(SAM3SD8C) \
+        )
 /** @} */
 
 /**
@@ -672,19 +672,19 @@
  * @{
  */
 #define SAM3U1 ( \
-		SAM_PART_IS_DEFINED(SAM3U1C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U1E) \
-		)
+        SAM_PART_IS_DEFINED(SAM3U1C) || \
+        SAM_PART_IS_DEFINED(SAM3U1E) \
+        )
 
 #define SAM3U2 ( \
-		SAM_PART_IS_DEFINED(SAM3U2C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U2E) \
-		)
+        SAM_PART_IS_DEFINED(SAM3U2C) || \
+        SAM_PART_IS_DEFINED(SAM3U2E) \
+        )
 
 #define SAM3U4 ( \
-		SAM_PART_IS_DEFINED(SAM3U4C) ||	\
-		SAM_PART_IS_DEFINED(SAM3U4E) \
-		)
+        SAM_PART_IS_DEFINED(SAM3U4C) || \
+        SAM_PART_IS_DEFINED(SAM3U4E) \
+        )
 /** @} */
 
 /**
@@ -692,33 +692,33 @@
  * @{
  */
 #define SAM3N00 ( \
-		SAM_PART_IS_DEFINED(SAM3N00A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N00B) \
-		)
+        SAM_PART_IS_DEFINED(SAM3N00A) ||    \
+        SAM_PART_IS_DEFINED(SAM3N00B) \
+        )
 
 #define SAM3N0 ( \
-		SAM_PART_IS_DEFINED(SAM3N0A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N0B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N0C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3N0A) || \
+        SAM_PART_IS_DEFINED(SAM3N0B) || \
+        SAM_PART_IS_DEFINED(SAM3N0C) \
+        )
 
 #define SAM3N1 ( \
-		SAM_PART_IS_DEFINED(SAM3N1A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N1B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N1C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3N1A) || \
+        SAM_PART_IS_DEFINED(SAM3N1B) || \
+        SAM_PART_IS_DEFINED(SAM3N1C) \
+        )
 
 #define SAM3N2 ( \
-		SAM_PART_IS_DEFINED(SAM3N2A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N2B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N2C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3N2A) || \
+        SAM_PART_IS_DEFINED(SAM3N2B) || \
+        SAM_PART_IS_DEFINED(SAM3N2C) \
+        )
 
 #define SAM3N4 ( \
-		SAM_PART_IS_DEFINED(SAM3N4A) ||	\
-		SAM_PART_IS_DEFINED(SAM3N4B) ||	\
-		SAM_PART_IS_DEFINED(SAM3N4C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3N4A) || \
+        SAM_PART_IS_DEFINED(SAM3N4B) || \
+        SAM_PART_IS_DEFINED(SAM3N4C) \
+        )
 /** @} */
 
 /**
@@ -726,15 +726,15 @@
  * @{
  */
 #define SAM3X4 ( \
-		SAM_PART_IS_DEFINED(SAM3X4C) ||	\
-		SAM_PART_IS_DEFINED(SAM3X4E) \
-		)
+        SAM_PART_IS_DEFINED(SAM3X4C) || \
+        SAM_PART_IS_DEFINED(SAM3X4E) \
+        )
 
 #define SAM3X8 ( \
-		SAM_PART_IS_DEFINED(SAM3X8C) ||	\
-		SAM_PART_IS_DEFINED(SAM3X8E) ||	\
-		SAM_PART_IS_DEFINED(SAM3X8H) \
-		)
+        SAM_PART_IS_DEFINED(SAM3X8C) || \
+        SAM_PART_IS_DEFINED(SAM3X8E) || \
+        SAM_PART_IS_DEFINED(SAM3X8H) \
+        )
 /** @} */
 
 /**
@@ -742,12 +742,12 @@
  * @{
  */
 #define SAM3A4 ( \
-		SAM_PART_IS_DEFINED(SAM3A4C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3A4C) \
+        )
 
 #define SAM3A8 ( \
-		SAM_PART_IS_DEFINED(SAM3A8C) \
-		)
+        SAM_PART_IS_DEFINED(SAM3A8C) \
+        )
 /** @} */
 
 /**
@@ -755,41 +755,41 @@
  * @{
  */
 #define SAM4S2 ( \
-		SAM_PART_IS_DEFINED(SAM4S2A) || \
- 		SAM_PART_IS_DEFINED(SAM4S2B) || \
- 		SAM_PART_IS_DEFINED(SAM4S2C) \
- 		)
+        SAM_PART_IS_DEFINED(SAM4S2A) || \
+        SAM_PART_IS_DEFINED(SAM4S2B) || \
+        SAM_PART_IS_DEFINED(SAM4S2C) \
+        )
 
 #define SAM4S4 ( \
-		SAM_PART_IS_DEFINED(SAM4S4A) || \
- 		SAM_PART_IS_DEFINED(SAM4S4B) || \
- 		SAM_PART_IS_DEFINED(SAM4S4C) \
- 		)
+        SAM_PART_IS_DEFINED(SAM4S4A) || \
+        SAM_PART_IS_DEFINED(SAM4S4B) || \
+        SAM_PART_IS_DEFINED(SAM4S4C) \
+        )
 
 #define SAM4S8 ( \
-		SAM_PART_IS_DEFINED(SAM4S8B) ||	\
-		SAM_PART_IS_DEFINED(SAM4S8C) \
-		)
+        SAM_PART_IS_DEFINED(SAM4S8B) || \
+        SAM_PART_IS_DEFINED(SAM4S8C) \
+        )
 
 #define SAM4S16 ( \
-		SAM_PART_IS_DEFINED(SAM4S16B) || \
-		SAM_PART_IS_DEFINED(SAM4S16C) \
-		)
+        SAM_PART_IS_DEFINED(SAM4S16B) || \
+        SAM_PART_IS_DEFINED(SAM4S16C) \
+        )
 
 #define SAM4SA16 ( \
-		SAM_PART_IS_DEFINED(SAM4SA16B) || \
-		SAM_PART_IS_DEFINED(SAM4SA16C)    \
-	)
+        SAM_PART_IS_DEFINED(SAM4SA16B) || \
+        SAM_PART_IS_DEFINED(SAM4SA16C)    \
+    )
 
 #define SAM4SD16 ( \
-		SAM_PART_IS_DEFINED(SAM4SD16B) || \
-		SAM_PART_IS_DEFINED(SAM4SD16C)    \
-	)
+        SAM_PART_IS_DEFINED(SAM4SD16B) || \
+        SAM_PART_IS_DEFINED(SAM4SD16C)    \
+    )
 
 #define SAM4SD32 ( \
-		SAM_PART_IS_DEFINED(SAM4SD32B) || \
-		SAM_PART_IS_DEFINED(SAM4SD32C)    \
-	)
+        SAM_PART_IS_DEFINED(SAM4SD32B) || \
+        SAM_PART_IS_DEFINED(SAM4SD32C)    \
+    )
 /** @} */
 
 /**
@@ -797,28 +797,28 @@
  * @{
  */
 #define SAM4LS ( \
-		SAM_PART_IS_DEFINED(SAM4LS2A) || \
-		SAM_PART_IS_DEFINED(SAM4LS2B) || \
-		SAM_PART_IS_DEFINED(SAM4LS2C) || \
-		SAM_PART_IS_DEFINED(SAM4LS4A) || \
-		SAM_PART_IS_DEFINED(SAM4LS4B) || \
-		SAM_PART_IS_DEFINED(SAM4LS4C) || \
-		SAM_PART_IS_DEFINED(SAM4LS8A) || \
-		SAM_PART_IS_DEFINED(SAM4LS8B) || \
-		SAM_PART_IS_DEFINED(SAM4LS8C)    \
-		)
+        SAM_PART_IS_DEFINED(SAM4LS2A) || \
+        SAM_PART_IS_DEFINED(SAM4LS2B) || \
+        SAM_PART_IS_DEFINED(SAM4LS2C) || \
+        SAM_PART_IS_DEFINED(SAM4LS4A) || \
+        SAM_PART_IS_DEFINED(SAM4LS4B) || \
+        SAM_PART_IS_DEFINED(SAM4LS4C) || \
+        SAM_PART_IS_DEFINED(SAM4LS8A) || \
+        SAM_PART_IS_DEFINED(SAM4LS8B) || \
+        SAM_PART_IS_DEFINED(SAM4LS8C)    \
+        )
 
 #define SAM4LC ( \
-		SAM_PART_IS_DEFINED(SAM4LC2A) || \
-		SAM_PART_IS_DEFINED(SAM4LC2B) || \
-		SAM_PART_IS_DEFINED(SAM4LC2C) || \
-		SAM_PART_IS_DEFINED(SAM4LC4A) || \
-		SAM_PART_IS_DEFINED(SAM4LC4B) || \
-		SAM_PART_IS_DEFINED(SAM4LC4C) || \
-		SAM_PART_IS_DEFINED(SAM4LC8A) || \
-		SAM_PART_IS_DEFINED(SAM4LC8B) || \
-		SAM_PART_IS_DEFINED(SAM4LC8C)    \
-		)
+        SAM_PART_IS_DEFINED(SAM4LC2A) || \
+        SAM_PART_IS_DEFINED(SAM4LC2B) || \
+        SAM_PART_IS_DEFINED(SAM4LC2C) || \
+        SAM_PART_IS_DEFINED(SAM4LC4A) || \
+        SAM_PART_IS_DEFINED(SAM4LC4B) || \
+        SAM_PART_IS_DEFINED(SAM4LC4C) || \
+        SAM_PART_IS_DEFINED(SAM4LC8A) || \
+        SAM_PART_IS_DEFINED(SAM4LC8B) || \
+        SAM_PART_IS_DEFINED(SAM4LC8C)    \
+        )
 /** @} */
 
 /**
@@ -826,30 +826,30 @@
  * @{
  */
 #define SAMD20J ( \
-		SAM_PART_IS_DEFINED(SAMD20J14) || \
-		SAM_PART_IS_DEFINED(SAMD20J15) || \
-		SAM_PART_IS_DEFINED(SAMD20J16) || \
-		SAM_PART_IS_DEFINED(SAMD20J17) || \
-		SAM_PART_IS_DEFINED(SAMD20J18) \
-	)
+        SAM_PART_IS_DEFINED(SAMD20J14) || \
+        SAM_PART_IS_DEFINED(SAMD20J15) || \
+        SAM_PART_IS_DEFINED(SAMD20J16) || \
+        SAM_PART_IS_DEFINED(SAMD20J17) || \
+        SAM_PART_IS_DEFINED(SAMD20J18) \
+    )
 
 #define SAMD20G ( \
-		SAM_PART_IS_DEFINED(SAMD20G14)  || \
-		SAM_PART_IS_DEFINED(SAMD20G15)  || \
-		SAM_PART_IS_DEFINED(SAMD20G16)  || \
-		SAM_PART_IS_DEFINED(SAMD20G17)  || \
-		SAM_PART_IS_DEFINED(SAMD20G17U) || \
-		SAM_PART_IS_DEFINED(SAMD20G18)  || \
-		SAM_PART_IS_DEFINED(SAMD20G18U) \
-	)
+        SAM_PART_IS_DEFINED(SAMD20G14)  || \
+        SAM_PART_IS_DEFINED(SAMD20G15)  || \
+        SAM_PART_IS_DEFINED(SAMD20G16)  || \
+        SAM_PART_IS_DEFINED(SAMD20G17)  || \
+        SAM_PART_IS_DEFINED(SAMD20G17U) || \
+        SAM_PART_IS_DEFINED(SAMD20G18)  || \
+        SAM_PART_IS_DEFINED(SAMD20G18U) \
+    )
 
 #define SAMD20E ( \
-		SAM_PART_IS_DEFINED(SAMD20E14) || \
-		SAM_PART_IS_DEFINED(SAMD20E15) || \
-		SAM_PART_IS_DEFINED(SAMD20E16) || \
-		SAM_PART_IS_DEFINED(SAMD20E17) || \
-		SAM_PART_IS_DEFINED(SAMD20E18) \
-	)
+        SAM_PART_IS_DEFINED(SAMD20E14) || \
+        SAM_PART_IS_DEFINED(SAMD20E15) || \
+        SAM_PART_IS_DEFINED(SAMD20E16) || \
+        SAM_PART_IS_DEFINED(SAMD20E17) || \
+        SAM_PART_IS_DEFINED(SAMD20E18) \
+    )
 /** @} */
 
 /**
@@ -857,49 +857,49 @@
  * @{
  */
 #define SAMD21J ( \
-		SAM_PART_IS_DEFINED(SAMD21J15A) || \
-		SAM_PART_IS_DEFINED(SAMD21J16A) || \
-		SAM_PART_IS_DEFINED(SAMD21J17A) || \
-		SAM_PART_IS_DEFINED(SAMD21J18A) || \
-		SAM_PART_IS_DEFINED(SAMD21J15B) || \
-		SAM_PART_IS_DEFINED(SAMD21J16B) \
-	)
+        SAM_PART_IS_DEFINED(SAMD21J15A) || \
+        SAM_PART_IS_DEFINED(SAMD21J16A) || \
+        SAM_PART_IS_DEFINED(SAMD21J17A) || \
+        SAM_PART_IS_DEFINED(SAMD21J18A) || \
+        SAM_PART_IS_DEFINED(SAMD21J15B) || \
+        SAM_PART_IS_DEFINED(SAMD21J16B) \
+    )
 
 #define SAMD21G ( \
-		SAM_PART_IS_DEFINED(SAMD21G15A) || \
-		SAM_PART_IS_DEFINED(SAMD21G16A) || \
-		SAM_PART_IS_DEFINED(SAMD21G17A) || \
-		SAM_PART_IS_DEFINED(SAMD21G17AU) || \
-		SAM_PART_IS_DEFINED(SAMD21G18A) || \
-		SAM_PART_IS_DEFINED(SAMD21G18AU) || \
-		SAM_PART_IS_DEFINED(SAMD21G15B) || \
-		SAM_PART_IS_DEFINED(SAMD21G16B) || \
-		SAM_PART_IS_DEFINED(SAMD21G15L) || \
-		SAM_PART_IS_DEFINED(SAMD21G16L) \
-	)
+        SAM_PART_IS_DEFINED(SAMD21G15A) || \
+        SAM_PART_IS_DEFINED(SAMD21G16A) || \
+        SAM_PART_IS_DEFINED(SAMD21G17A) || \
+        SAM_PART_IS_DEFINED(SAMD21G17AU) || \
+        SAM_PART_IS_DEFINED(SAMD21G18A) || \
+        SAM_PART_IS_DEFINED(SAMD21G18AU) || \
+        SAM_PART_IS_DEFINED(SAMD21G15B) || \
+        SAM_PART_IS_DEFINED(SAMD21G16B) || \
+        SAM_PART_IS_DEFINED(SAMD21G15L) || \
+        SAM_PART_IS_DEFINED(SAMD21G16L) \
+    )
 
 #define SAMD21GXXL ( \
-		SAM_PART_IS_DEFINED(SAMD21G15L) || \
-		SAM_PART_IS_DEFINED(SAMD21G16L) \
-		)
+        SAM_PART_IS_DEFINED(SAMD21G15L) || \
+        SAM_PART_IS_DEFINED(SAMD21G16L) \
+        )
 
 #define SAMD21E ( \
-		SAM_PART_IS_DEFINED(SAMD21E15A) || \
-		SAM_PART_IS_DEFINED(SAMD21E16A) || \
-		SAM_PART_IS_DEFINED(SAMD21E17A) || \
-		SAM_PART_IS_DEFINED(SAMD21E18A) || \
-		SAM_PART_IS_DEFINED(SAMD21E15B) || \
-		SAM_PART_IS_DEFINED(SAMD21E15BU) || \
-		SAM_PART_IS_DEFINED(SAMD21E16B) || \
-		SAM_PART_IS_DEFINED(SAMD21E16BU) || \
-		SAM_PART_IS_DEFINED(SAMD21E15L) || \
-		SAM_PART_IS_DEFINED(SAMD21E16L) \
-	)
+        SAM_PART_IS_DEFINED(SAMD21E15A) || \
+        SAM_PART_IS_DEFINED(SAMD21E16A) || \
+        SAM_PART_IS_DEFINED(SAMD21E17A) || \
+        SAM_PART_IS_DEFINED(SAMD21E18A) || \
+        SAM_PART_IS_DEFINED(SAMD21E15B) || \
+        SAM_PART_IS_DEFINED(SAMD21E15BU) || \
+        SAM_PART_IS_DEFINED(SAMD21E16B) || \
+        SAM_PART_IS_DEFINED(SAMD21E16BU) || \
+        SAM_PART_IS_DEFINED(SAMD21E15L) || \
+        SAM_PART_IS_DEFINED(SAMD21E16L) \
+    )
 
 #define SAMD21EXXL ( \
-		SAM_PART_IS_DEFINED(SAMD21E15L) || \
-		SAM_PART_IS_DEFINED(SAMD21E16L) \
-		)
+        SAM_PART_IS_DEFINED(SAMD21E15L) || \
+        SAM_PART_IS_DEFINED(SAMD21E16L) \
+        )
 
 /** @} */
 
@@ -908,17 +908,17 @@
  * @{
  */
 #define SAMR21G ( \
-		SAM_PART_IS_DEFINED(SAMR21G16A) || \
-		SAM_PART_IS_DEFINED(SAMR21G17A) || \
-		SAM_PART_IS_DEFINED(SAMR21G18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMR21G16A) || \
+        SAM_PART_IS_DEFINED(SAMR21G17A) || \
+        SAM_PART_IS_DEFINED(SAMR21G18A) \
+    )
 
 #define SAMR21E ( \
-		SAM_PART_IS_DEFINED(SAMR21E16A) || \
-		SAM_PART_IS_DEFINED(SAMR21E17A) || \
-		SAM_PART_IS_DEFINED(SAMR21E18A) || \
-		SAM_PART_IS_DEFINED(SAMR21E19A) \
-	)
+        SAM_PART_IS_DEFINED(SAMR21E16A) || \
+        SAM_PART_IS_DEFINED(SAMR21E17A) || \
+        SAM_PART_IS_DEFINED(SAMR21E18A) || \
+        SAM_PART_IS_DEFINED(SAMR21E19A) \
+    )
 /** @} */
 
 /**
@@ -926,12 +926,12 @@
  * @{
  */
 #define SAMR30G ( \
-		SAM_PART_IS_DEFINED(SAMR30G18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMR30G18A) \
+    )
 
 #define SAMR30E ( \
-		SAM_PART_IS_DEFINED(SAMR30E18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMR30E18A) \
+    )
 /** @} */
 
 /**
@@ -939,12 +939,12 @@
  * @{
  */
 #define SAMB11G ( \
-		SAM_PART_IS_DEFINED(SAMB11G18A) || \
-		SAM_PART_IS_DEFINED(SAMB11ZR) \
-	)
+        SAM_PART_IS_DEFINED(SAMB11G18A) || \
+        SAM_PART_IS_DEFINED(SAMB11ZR) \
+    )
 #define BTLC1000 ( \
-		SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
-	)
+        SAM_PART_IS_DEFINED(BTLC1000WLCSP) \
+    )
 
 /** @} */
 
@@ -953,12 +953,12 @@
  * @{
  */
 #define SAMD09C ( \
-		SAM_PART_IS_DEFINED(SAMD09C13A) \
-	)
+        SAM_PART_IS_DEFINED(SAMD09C13A) \
+    )
 
 #define SAMD09D ( \
-		SAM_PART_IS_DEFINED(SAMD09D14A) \
-	)
+        SAM_PART_IS_DEFINED(SAMD09D14A) \
+    )
 /** @} */
 
 /**
@@ -966,26 +966,26 @@
  * @{
  */
 #define SAMD10C ( \
-		SAM_PART_IS_DEFINED(SAMD10C12A) || \
-		SAM_PART_IS_DEFINED(SAMD10C13A) || \
-		SAM_PART_IS_DEFINED(SAMD10C14A) \
-	)
+        SAM_PART_IS_DEFINED(SAMD10C12A) || \
+        SAM_PART_IS_DEFINED(SAMD10C13A) || \
+        SAM_PART_IS_DEFINED(SAMD10C14A) \
+    )
 
 #define SAMD10DS ( \
-		SAM_PART_IS_DEFINED(SAMD10D12AS) || \
-		SAM_PART_IS_DEFINED(SAMD10D13AS) || \
-		SAM_PART_IS_DEFINED(SAMD10D14AS) \
-	)
+        SAM_PART_IS_DEFINED(SAMD10D12AS) || \
+        SAM_PART_IS_DEFINED(SAMD10D13AS) || \
+        SAM_PART_IS_DEFINED(SAMD10D14AS) \
+    )
 
 #define SAMD10DM ( \
-		SAM_PART_IS_DEFINED(SAMD10D12AM) || \
-		SAM_PART_IS_DEFINED(SAMD10D13AM) || \
-		SAM_PART_IS_DEFINED(SAMD10D14AM) \
-	)
+        SAM_PART_IS_DEFINED(SAMD10D12AM) || \
+        SAM_PART_IS_DEFINED(SAMD10D13AM) || \
+        SAM_PART_IS_DEFINED(SAMD10D14AM) \
+    )
 
 #define SAMD10DU ( \
-		SAM_PART_IS_DEFINED(SAMD10D14AU) \
-	)
+        SAM_PART_IS_DEFINED(SAMD10D14AU) \
+    )
 /** @} */
 
 /**
@@ -993,20 +993,20 @@
  * @{
  */
 #define SAMD11C ( \
-		SAM_PART_IS_DEFINED(SAMD11C14A) \
-	)
+        SAM_PART_IS_DEFINED(SAMD11C14A) \
+    )
 
 #define SAMD11DS ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AS) \
-	)
+        SAM_PART_IS_DEFINED(SAMD11D14AS) \
+    )
 
 #define SAMD11DM ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AM) \
-	)
+        SAM_PART_IS_DEFINED(SAMD11D14AM) \
+    )
 
 #define SAMD11DU ( \
-		SAM_PART_IS_DEFINED(SAMD11D14AU) \
-	)
+        SAM_PART_IS_DEFINED(SAMD11D14AU) \
+    )
 /** @} */
 
 /**
@@ -1014,47 +1014,47 @@
  * @{
  */
 #define SAML21E ( \
-		SAM_PART_IS_DEFINED(SAML21E18A) || \
-		SAM_PART_IS_DEFINED(SAML21E15B) || \
-		SAM_PART_IS_DEFINED(SAML21E16B) || \
-		SAM_PART_IS_DEFINED(SAML21E17B) || \
-		SAM_PART_IS_DEFINED(SAML21E18B) \
-	)
+        SAM_PART_IS_DEFINED(SAML21E18A) || \
+        SAM_PART_IS_DEFINED(SAML21E15B) || \
+        SAM_PART_IS_DEFINED(SAML21E16B) || \
+        SAM_PART_IS_DEFINED(SAML21E17B) || \
+        SAM_PART_IS_DEFINED(SAML21E18B) \
+    )
 
 #define SAML21G ( \
-		SAM_PART_IS_DEFINED(SAML21G18A) || \
-		SAM_PART_IS_DEFINED(SAML21G16B) || \
-		SAM_PART_IS_DEFINED(SAML21G17B) || \
-		SAM_PART_IS_DEFINED(SAML21G18B) \
-	)
+        SAM_PART_IS_DEFINED(SAML21G18A) || \
+        SAM_PART_IS_DEFINED(SAML21G16B) || \
+        SAM_PART_IS_DEFINED(SAML21G17B) || \
+        SAM_PART_IS_DEFINED(SAML21G18B) \
+    )
 
 #define SAML21J ( \
-		SAM_PART_IS_DEFINED(SAML21J18A) || \
-		SAM_PART_IS_DEFINED(SAML21J16B) || \
-		SAM_PART_IS_DEFINED(SAML21J17B) || \
-		SAM_PART_IS_DEFINED(SAML21J18B) \
-	)
+        SAM_PART_IS_DEFINED(SAML21J18A) || \
+        SAM_PART_IS_DEFINED(SAML21J16B) || \
+        SAM_PART_IS_DEFINED(SAML21J17B) || \
+        SAM_PART_IS_DEFINED(SAML21J18B) \
+    )
 
 /* Group for SAML21 A variant: SAML21[E/G/J][18]A */
 #define SAML21XXXA ( \
-		SAM_PART_IS_DEFINED(SAML21E18A) || \
-		SAM_PART_IS_DEFINED(SAML21G18A) || \
-		SAM_PART_IS_DEFINED(SAML21J18A) \
-	)
+        SAM_PART_IS_DEFINED(SAML21E18A) || \
+        SAM_PART_IS_DEFINED(SAML21G18A) || \
+        SAM_PART_IS_DEFINED(SAML21J18A) \
+    )
 
 /* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */
 #define SAML21XXXB ( \
-		SAM_PART_IS_DEFINED(SAML21E15B) || \
-		SAM_PART_IS_DEFINED(SAML21E16B) || \
-		SAM_PART_IS_DEFINED(SAML21E17B) || \
-		SAM_PART_IS_DEFINED(SAML21E18B) || \
-		SAM_PART_IS_DEFINED(SAML21G16B) || \
-		SAM_PART_IS_DEFINED(SAML21G17B) || \
-		SAM_PART_IS_DEFINED(SAML21G18B) || \
-		SAM_PART_IS_DEFINED(SAML21J16B) || \
-		SAM_PART_IS_DEFINED(SAML21J17B) || \
-		SAM_PART_IS_DEFINED(SAML21J18B) \
-	)
+        SAM_PART_IS_DEFINED(SAML21E15B) || \
+        SAM_PART_IS_DEFINED(SAML21E16B) || \
+        SAM_PART_IS_DEFINED(SAML21E17B) || \
+        SAM_PART_IS_DEFINED(SAML21E18B) || \
+        SAM_PART_IS_DEFINED(SAML21G16B) || \
+        SAM_PART_IS_DEFINED(SAML21G17B) || \
+        SAM_PART_IS_DEFINED(SAML21G18B) || \
+        SAM_PART_IS_DEFINED(SAML21J16B) || \
+        SAM_PART_IS_DEFINED(SAML21J17B) || \
+        SAM_PART_IS_DEFINED(SAML21J18B) \
+    )
 
 /** @} */
 
@@ -1063,22 +1063,22 @@
  * @{
  */
 #define SAML22N ( \
-		SAM_PART_IS_DEFINED(SAML22N16A) || \
-		SAM_PART_IS_DEFINED(SAML22N17A) || \
-		SAM_PART_IS_DEFINED(SAML22N18A) \
-	)
+        SAM_PART_IS_DEFINED(SAML22N16A) || \
+        SAM_PART_IS_DEFINED(SAML22N17A) || \
+        SAM_PART_IS_DEFINED(SAML22N18A) \
+    )
 
 #define SAML22G ( \
-		SAM_PART_IS_DEFINED(SAML22G16A) || \
-		SAM_PART_IS_DEFINED(SAML22G17A) || \
-		SAM_PART_IS_DEFINED(SAML22G18A) \
-	)
+        SAM_PART_IS_DEFINED(SAML22G16A) || \
+        SAM_PART_IS_DEFINED(SAML22G17A) || \
+        SAM_PART_IS_DEFINED(SAML22G18A) \
+    )
 
 #define SAML22J ( \
-		SAM_PART_IS_DEFINED(SAML22J16A) || \
-		SAM_PART_IS_DEFINED(SAML22J17A) || \
-		SAM_PART_IS_DEFINED(SAML22J18A) \
-	)
+        SAM_PART_IS_DEFINED(SAML22J16A) || \
+        SAM_PART_IS_DEFINED(SAML22J17A) || \
+        SAM_PART_IS_DEFINED(SAML22J18A) \
+    )
 /** @} */
 
 /**
@@ -1086,31 +1086,31 @@
  * @{
  */
 #define SAMDA1J ( \
-		SAM_PART_IS_DEFINED(SAMDA1J14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1J16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1J16B) \
-	)
+        SAM_PART_IS_DEFINED(SAMDA1J14A) || \
+        SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+        SAM_PART_IS_DEFINED(SAMDA1J15A) || \
+        SAM_PART_IS_DEFINED(SAMDA1J15B) || \
+        SAM_PART_IS_DEFINED(SAMDA1J16A) || \
+        SAM_PART_IS_DEFINED(SAMDA1J16B) \
+    )
 
 #define SAMDA1G ( \
-		SAM_PART_IS_DEFINED(SAMDA1G14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G14B) || \
-		SAM_PART_IS_DEFINED(SAMDA1G15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1G16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1G16B) \
-	)
+        SAM_PART_IS_DEFINED(SAMDA1G14A) || \
+        SAM_PART_IS_DEFINED(SAMDA1G14B) || \
+        SAM_PART_IS_DEFINED(SAMDA1G15A) || \
+        SAM_PART_IS_DEFINED(SAMDA1G15B) || \
+        SAM_PART_IS_DEFINED(SAMDA1G16A) || \
+        SAM_PART_IS_DEFINED(SAMDA1G16B) \
+    )
 
 #define SAMDA1E ( \
-		SAM_PART_IS_DEFINED(SAMDA1E14A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E14B) || \
-		SAM_PART_IS_DEFINED(SAMDA1E15A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E15B) || \
-		SAM_PART_IS_DEFINED(SAMDA1E16A) || \
-		SAM_PART_IS_DEFINED(SAMDA1E16B) \
-	)
+        SAM_PART_IS_DEFINED(SAMDA1E14A) || \
+        SAM_PART_IS_DEFINED(SAMDA1E14B) || \
+        SAM_PART_IS_DEFINED(SAMDA1E15A) || \
+        SAM_PART_IS_DEFINED(SAMDA1E15B) || \
+        SAM_PART_IS_DEFINED(SAMDA1E16A) || \
+        SAM_PART_IS_DEFINED(SAMDA1E16B) \
+    )
 /** @} */
 
 /**
@@ -1118,10 +1118,10 @@
  * @{
  */
 #define SAMHA1G ( \
-		SAM_PART_IS_DEFINED(SAMHA1G14A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G15A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G16A) \
-	)
+        SAM_PART_IS_DEFINED(SAMHA1G14A) || \
+        SAM_PART_IS_DEFINED(SAMHA1G15A) || \
+        SAM_PART_IS_DEFINED(SAMHA1G16A) \
+    )
 
 /** @} */
 
@@ -1130,25 +1130,25 @@
  * @{
  */
 #define SAMC20E ( \
-		SAM_PART_IS_DEFINED(SAMC20E15A) || \
-		SAM_PART_IS_DEFINED(SAMC20E16A) || \
-		SAM_PART_IS_DEFINED(SAMC20E17A) || \
-		SAM_PART_IS_DEFINED(SAMC20E18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC20E15A) || \
+        SAM_PART_IS_DEFINED(SAMC20E16A) || \
+        SAM_PART_IS_DEFINED(SAMC20E17A) || \
+        SAM_PART_IS_DEFINED(SAMC20E18A) \
+    )
 
 #define SAMC20G ( \
-		SAM_PART_IS_DEFINED(SAMC20G15A) || \
-		SAM_PART_IS_DEFINED(SAMC20G16A) || \
-		SAM_PART_IS_DEFINED(SAMC20G17A) || \
-		SAM_PART_IS_DEFINED(SAMC20G18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC20G15A) || \
+        SAM_PART_IS_DEFINED(SAMC20G16A) || \
+        SAM_PART_IS_DEFINED(SAMC20G17A) || \
+        SAM_PART_IS_DEFINED(SAMC20G18A) \
+    )
 
 #define SAMC20J ( \
-		SAM_PART_IS_DEFINED(SAMC20J15A) || \
-		SAM_PART_IS_DEFINED(SAMC20J16A) || \
-		SAM_PART_IS_DEFINED(SAMC20J17A) || \
-		SAM_PART_IS_DEFINED(SAMC20J18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC20J15A) || \
+        SAM_PART_IS_DEFINED(SAMC20J16A) || \
+        SAM_PART_IS_DEFINED(SAMC20J17A) || \
+        SAM_PART_IS_DEFINED(SAMC20J18A) \
+    )
 /** @} */
 
 /**
@@ -1156,25 +1156,25 @@
  * @{
  */
 #define SAMC21E ( \
-		SAM_PART_IS_DEFINED(SAMC21E15A) || \
-		SAM_PART_IS_DEFINED(SAMC21E16A) || \
-		SAM_PART_IS_DEFINED(SAMC21E17A) || \
-		SAM_PART_IS_DEFINED(SAMC21E18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC21E15A) || \
+        SAM_PART_IS_DEFINED(SAMC21E16A) || \
+        SAM_PART_IS_DEFINED(SAMC21E17A) || \
+        SAM_PART_IS_DEFINED(SAMC21E18A) \
+    )
 
 #define SAMC21G ( \
-		SAM_PART_IS_DEFINED(SAMC21G15A) || \
-		SAM_PART_IS_DEFINED(SAMC21G16A) || \
-		SAM_PART_IS_DEFINED(SAMC21G17A) || \
-		SAM_PART_IS_DEFINED(SAMC21G18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC21G15A) || \
+        SAM_PART_IS_DEFINED(SAMC21G16A) || \
+        SAM_PART_IS_DEFINED(SAMC21G17A) || \
+        SAM_PART_IS_DEFINED(SAMC21G18A) \
+    )
 
 #define SAMC21J ( \
-		SAM_PART_IS_DEFINED(SAMC21J15A) || \
-		SAM_PART_IS_DEFINED(SAMC21J16A) || \
-		SAM_PART_IS_DEFINED(SAMC21J17A) || \
-		SAM_PART_IS_DEFINED(SAMC21J18A) \
-	)
+        SAM_PART_IS_DEFINED(SAMC21J15A) || \
+        SAM_PART_IS_DEFINED(SAMC21J16A) || \
+        SAM_PART_IS_DEFINED(SAMC21J17A) || \
+        SAM_PART_IS_DEFINED(SAMC21J18A) \
+    )
 /** @} */
 
 /**
@@ -1182,16 +1182,16 @@
  * @{
  */
 #define SAM4E8 ( \
-		SAM_PART_IS_DEFINED(SAM4E8C) || \
-		SAM_PART_IS_DEFINED(SAM4E8CB) || \
-		SAM_PART_IS_DEFINED(SAM4E8E) \
-		)
+        SAM_PART_IS_DEFINED(SAM4E8C) || \
+        SAM_PART_IS_DEFINED(SAM4E8CB) || \
+        SAM_PART_IS_DEFINED(SAM4E8E) \
+        )
 
 #define SAM4E16 ( \
-		SAM_PART_IS_DEFINED(SAM4E16C) || \
-		SAM_PART_IS_DEFINED(SAM4E16CB) || \
-		SAM_PART_IS_DEFINED(SAM4E16E) \
-		)
+        SAM_PART_IS_DEFINED(SAM4E16C) || \
+        SAM_PART_IS_DEFINED(SAM4E16CB) || \
+        SAM_PART_IS_DEFINED(SAM4E16E) \
+        )
 /** @} */
 
 /**
@@ -1199,15 +1199,15 @@
  * @{
  */
 #define SAM4N8 ( \
-		SAM_PART_IS_DEFINED(SAM4N8A) || \
-		SAM_PART_IS_DEFINED(SAM4N8B) || \
-		SAM_PART_IS_DEFINED(SAM4N8C) \
-		)
+        SAM_PART_IS_DEFINED(SAM4N8A) || \
+        SAM_PART_IS_DEFINED(SAM4N8B) || \
+        SAM_PART_IS_DEFINED(SAM4N8C) \
+        )
 
 #define SAM4N16 ( \
-		SAM_PART_IS_DEFINED(SAM4N16B) || \
-		SAM_PART_IS_DEFINED(SAM4N16C) \
-		)
+        SAM_PART_IS_DEFINED(SAM4N16B) || \
+        SAM_PART_IS_DEFINED(SAM4N16C) \
+        )
 /** @} */
 
 /**
@@ -1215,44 +1215,44 @@
  * @{
  */
 #define SAM4C4_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C4C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C4C_0) \
+        )
 
 #define SAM4C4_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C4C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C4C_1) \
+        )
 
 #define SAM4C4 (SAM4C4_0 || SAM4C4_1)
 
 #define SAM4C8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C8C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C8C_0) \
+        )
 
 #define SAM4C8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C8C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C8C_1) \
+        )
 
 #define SAM4C8 (SAM4C8_0 || SAM4C8_1)
 
 #define SAM4C16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C16C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C16C_0) \
+        )
 
 #define SAM4C16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C16C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C16C_1) \
+        )
 
 #define SAM4C16 (SAM4C16_0 || SAM4C16_1)
 
 #define SAM4C32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
-		SAM_PART_IS_DEFINED(SAM4C32E_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C32C_0) ||\
+        SAM_PART_IS_DEFINED(SAM4C32E_0) \
+        )
 
 #define SAM4C32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
-		SAM_PART_IS_DEFINED(SAM4C32E_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4C32C_1) ||\
+        SAM_PART_IS_DEFINED(SAM4C32E_1) \
+        )
 
 
 #define SAM4C32 (SAM4C32_0 || SAM4C32_1)
@@ -1264,72 +1264,72 @@
  * @{
  */
 #define SAM4CMP8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP8C_0) \
+        )
 
 #define SAM4CMP8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP8C_1) \
+        )
 
 #define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1)
 
 #define SAM4CMP16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP16C_0) \
+        )
 
 #define SAM4CMP16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP16C_1) \
+        )
 
 #define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1)
 
 #define SAM4CMP32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP32C_0) \
+        )
 
 #define SAM4CMP32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMP32C_1) \
+        )
 
 #define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1)
 
 #define SAM4CMS4_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS4C_0) \
+        )
 
 #define SAM4CMS4_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS4C_1) \
+        )
 
 #define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1)
 
 #define SAM4CMS8_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS8C_0) \
+        )
 
 #define SAM4CMS8_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS8C_1) \
+        )
 
 #define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1)
 
 #define SAM4CMS16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS16C_0) \
+        )
 
 #define SAM4CMS16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS16C_1) \
+        )
 
 #define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1)
 
 #define SAM4CMS32_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS32C_0) \
+        )
 
 #define SAM4CMS32_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CMS32C_1) \
+        )
 
 #define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1)
 
@@ -1340,12 +1340,12 @@
  * @{
  */
 #define SAM4CP16_0 ( \
-		SAM_PART_IS_DEFINED(SAM4CP16B_0) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CP16B_0) \
+        )
 
 #define SAM4CP16_1 ( \
-		SAM_PART_IS_DEFINED(SAM4CP16B_1) \
-		)
+        SAM_PART_IS_DEFINED(SAM4CP16B_1) \
+        )
 
 #define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1)
 /** @} */
@@ -1355,27 +1355,27 @@
  * @{
  */
 #define SAMG51 ( \
-		SAM_PART_IS_DEFINED(SAMG51G18) \
-		)
+        SAM_PART_IS_DEFINED(SAMG51G18) \
+        )
 
 #define SAMG53 ( \
-		SAM_PART_IS_DEFINED(SAMG53G19) ||\
-		SAM_PART_IS_DEFINED(SAMG53N19) \
-		)
+        SAM_PART_IS_DEFINED(SAMG53G19) ||\
+        SAM_PART_IS_DEFINED(SAMG53N19) \
+        )
 
 #define SAMG54 ( \
-		SAM_PART_IS_DEFINED(SAMG54G19) ||\
-		SAM_PART_IS_DEFINED(SAMG54J19) ||\
-		SAM_PART_IS_DEFINED(SAMG54N19) \
-		)
+        SAM_PART_IS_DEFINED(SAMG54G19) ||\
+        SAM_PART_IS_DEFINED(SAMG54J19) ||\
+        SAM_PART_IS_DEFINED(SAMG54N19) \
+        )
 
 #define SAMG55 ( \
-		SAM_PART_IS_DEFINED(SAMG55G18) ||\
-		SAM_PART_IS_DEFINED(SAMG55G19) ||\
-		SAM_PART_IS_DEFINED(SAMG55J18) ||\
-		SAM_PART_IS_DEFINED(SAMG55J19) ||\
-		SAM_PART_IS_DEFINED(SAMG55N19) \
-		)
+        SAM_PART_IS_DEFINED(SAMG55G18) ||\
+        SAM_PART_IS_DEFINED(SAMG55G19) ||\
+        SAM_PART_IS_DEFINED(SAMG55J18) ||\
+        SAM_PART_IS_DEFINED(SAMG55J19) ||\
+        SAM_PART_IS_DEFINED(SAMG55N19) \
+        )
 /** @} */
 
 /**
@@ -1383,22 +1383,22 @@
  * @{
  */
 #define SAMV71J ( \
-		SAM_PART_IS_DEFINED(SAMV71J19) || \
-		SAM_PART_IS_DEFINED(SAMV71J20) || \
-		SAM_PART_IS_DEFINED(SAMV71J21) \
-	)
+        SAM_PART_IS_DEFINED(SAMV71J19) || \
+        SAM_PART_IS_DEFINED(SAMV71J20) || \
+        SAM_PART_IS_DEFINED(SAMV71J21) \
+    )
 
 #define SAMV71N ( \
-		SAM_PART_IS_DEFINED(SAMV71N19) || \
-		SAM_PART_IS_DEFINED(SAMV71N20) || \
-		SAM_PART_IS_DEFINED(SAMV71N21) \
-	)
+        SAM_PART_IS_DEFINED(SAMV71N19) || \
+        SAM_PART_IS_DEFINED(SAMV71N20) || \
+        SAM_PART_IS_DEFINED(SAMV71N21) \
+    )
 
 #define SAMV71Q ( \
-		SAM_PART_IS_DEFINED(SAMV71Q19) || \
-		SAM_PART_IS_DEFINED(SAMV71Q20) || \
-		SAM_PART_IS_DEFINED(SAMV71Q21) \
-	)
+        SAM_PART_IS_DEFINED(SAMV71Q19) || \
+        SAM_PART_IS_DEFINED(SAMV71Q20) || \
+        SAM_PART_IS_DEFINED(SAMV71Q21) \
+    )
 /** @} */
 
 /**
@@ -1406,19 +1406,19 @@
  * @{
  */
 #define SAMV70J ( \
-		SAM_PART_IS_DEFINED(SAMV70J19) || \
-		SAM_PART_IS_DEFINED(SAMV70J20) \
-	)
+        SAM_PART_IS_DEFINED(SAMV70J19) || \
+        SAM_PART_IS_DEFINED(SAMV70J20) \
+    )
 
 #define SAMV70N ( \
-		SAM_PART_IS_DEFINED(SAMV70N19) || \
-		SAM_PART_IS_DEFINED(SAMV70N20) \
-	)
+        SAM_PART_IS_DEFINED(SAMV70N19) || \
+        SAM_PART_IS_DEFINED(SAMV70N20) \
+    )
 
 #define SAMV70Q ( \
-		SAM_PART_IS_DEFINED(SAMV70Q19) || \
-		SAM_PART_IS_DEFINED(SAMV70Q20) \
-	)
+        SAM_PART_IS_DEFINED(SAMV70Q19) || \
+        SAM_PART_IS_DEFINED(SAMV70Q20) \
+    )
 /** @} */
 
 /**
@@ -1426,22 +1426,22 @@
  * @{
  */
 #define SAMS70J ( \
-		SAM_PART_IS_DEFINED(SAMS70J19) || \
-		SAM_PART_IS_DEFINED(SAMS70J20) || \
-		SAM_PART_IS_DEFINED(SAMS70J21) \
-	)
+        SAM_PART_IS_DEFINED(SAMS70J19) || \
+        SAM_PART_IS_DEFINED(SAMS70J20) || \
+        SAM_PART_IS_DEFINED(SAMS70J21) \
+    )
 
 #define SAMS70N ( \
-		SAM_PART_IS_DEFINED(SAMS70N19) || \
-		SAM_PART_IS_DEFINED(SAMS70N20) || \
-		SAM_PART_IS_DEFINED(SAMS70N21) \
-	)
+        SAM_PART_IS_DEFINED(SAMS70N19) || \
+        SAM_PART_IS_DEFINED(SAMS70N20) || \
+        SAM_PART_IS_DEFINED(SAMS70N21) \
+    )
 
 #define SAMS70Q ( \
-		SAM_PART_IS_DEFINED(SAMS70Q19) || \
-		SAM_PART_IS_DEFINED(SAMS70Q20) || \
-		SAM_PART_IS_DEFINED(SAMS70Q21) \
-	)
+        SAM_PART_IS_DEFINED(SAMS70Q19) || \
+        SAM_PART_IS_DEFINED(SAMS70Q20) || \
+        SAM_PART_IS_DEFINED(SAMS70Q21) \
+    )
 /** @} */
 
 /**
@@ -1449,22 +1449,22 @@
  * @{
  */
 #define SAME70J ( \
-		SAM_PART_IS_DEFINED(SAME70J19) || \
-		SAM_PART_IS_DEFINED(SAME70J20) || \
-		SAM_PART_IS_DEFINED(SAME70J21) \
-	)
+        SAM_PART_IS_DEFINED(SAME70J19) || \
+        SAM_PART_IS_DEFINED(SAME70J20) || \
+        SAM_PART_IS_DEFINED(SAME70J21) \
+    )
 
 #define SAME70N ( \
-		SAM_PART_IS_DEFINED(SAME70N19) || \
-		SAM_PART_IS_DEFINED(SAME70N20) || \
-		SAM_PART_IS_DEFINED(SAME70N21) \
-	)
+        SAM_PART_IS_DEFINED(SAME70N19) || \
+        SAM_PART_IS_DEFINED(SAME70N20) || \
+        SAM_PART_IS_DEFINED(SAME70N21) \
+    )
 
 #define SAME70Q ( \
-		SAM_PART_IS_DEFINED(SAME70Q19) || \
-		SAM_PART_IS_DEFINED(SAME70Q20) || \
-		SAM_PART_IS_DEFINED(SAME70Q21) \
-	)
+        SAM_PART_IS_DEFINED(SAME70Q19) || \
+        SAM_PART_IS_DEFINED(SAME70Q20) || \
+        SAM_PART_IS_DEFINED(SAME70Q21) \
+    )
 /** @} */
 
 /**
@@ -1546,11 +1546,11 @@
 
 /** SAM4CM Family */
 #define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \
-			SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
+            SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0)
 #define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \
-			SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
+            SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1)
 #define SAM4CM   (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \
-			SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
+            SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32)
 
 /** SAM4CP Family */
 #define SAM4CP_0 (SAM4CP16_0)
@@ -1577,13 +1577,13 @@
 
 /** SAM0 product line (cortex-m0+) */
 #define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\
-		SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1)
+        SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30 || SAMHA1)
 
 /** @} */
 
 /** SAM product line */
 #define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \
-		SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
+        SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70)
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c
index 1326308be558..5d220f2e603e 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/read.c
@@ -60,7 +60,7 @@ extern volatile void *volatile stdio_base;
 void (*ptr_get)(void volatile*, char*);
 
 
-// IAR common implementation
+/* IAR common implementation*/
 #if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) )
 
 #include <yfuns.h>
@@ -81,18 +81,20 @@ _STD_BEGIN
  */
 size_t __read(int handle, unsigned char *buffer, size_t size)
 {
-	int nChars = 0;
-	// This implementation only reads from stdin.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDIN) {
-		return _LLIO_ERROR;
-	}
-	for (; size > 0; --size) {
-		ptr_get(stdio_base, (char*)buffer);
-		buffer++;
-		nChars++;
-	}
-	return nChars;
+    int nChars = 0;
+    /* This implementation only reads from stdin.*/
+    /* For all other file handles, it returns failure.*/
+    if (handle != _LLIO_STDIN)
+    {
+        return _LLIO_ERROR;
+    }
+    for (; size > 0; --size)
+    {
+        ptr_get(stdio_base, (char*)buffer);
+        buffer++;
+        nChars++;
+    }
+    return nChars;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -100,8 +102,8 @@ size_t __read(int handle, unsigned char *buffer, size_t size)
  */
 int __close(int handle)
 {
-	UNUSED(handle);
-	return 0;
+    UNUSED(handle);
+    return 0;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -109,8 +111,8 @@ int __close(int handle)
  */
 int remove(const char* val)
 {
-	UNUSED(val);
-	return 0;
+    UNUSED(val);
+    return 0;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -118,46 +120,48 @@ int remove(const char* val)
  */
 long __lseek(int handle, long val, int val2)
 {
-	UNUSED(handle);
-	UNUSED(val2);
-	return val;
+    UNUSED(handle);
+    UNUSED(val2);
+    return val;
 }
 
 _STD_END
 
-// GCC AVR32 and SAM implementation
-#elif (defined(__GNUC__) && !XMEGA && !MEGA) 
+/* GCC AVR32 and SAM implementation*/
+#elif (defined(__GNUC__) && !XMEGA && !MEGA)
 
 int __attribute__((weak))
-_read (int file, char * ptr, int len); // Remove GCC compiler warning
+_read (int file, char * ptr, int len); /* Remove GCC compiler warning*/
 
 int __attribute__((weak))
 _read (int file, char * ptr, int len)
 {
-	int nChars = 0;
-
-	if (file != 0) {
-		return -1;
-	}
-
-	for (; len > 0; --len) {
-		ptr_get(stdio_base, ptr);
-		ptr++;
-		nChars++;
-	}
-	return nChars;
+    int nChars = 0;
+
+    if (file != 0)
+    {
+        return -1;
+    }
+
+    for (; len > 0; --len)
+    {
+        ptr_get(stdio_base, ptr);
+        ptr++;
+        nChars++;
+    }
+    return nChars;
 }
 
-// GCC AVR implementation
+/* GCC AVR implementation*/
 #elif (defined(__GNUC__) && (XMEGA || MEGA) )
 
-int _read (int *f); // Remove GCC compiler warning
+int _read (int *f); /* Remove GCC compiler warning*/
 
 int _read (int *f)
 {
-	char c;
-	ptr_get(stdio_base,&c);
-	return c;
+    char c;
+    ptr_get(stdio_base,&c);
+    return c;
 }
 #endif
 
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h
index b014bd89fbf7..3407b22fa884 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_serial/stdio_serial.h
@@ -70,17 +70,17 @@
 #include "drivers/dev_serial.h"
 
 #if (XMEGA || MEGA_RF) && defined(__GNUC__)
-	extern int _write (char c, int *f);
-	extern int _read (int *f);
+    extern int _write (char c, int *f);
+    extern int _read (int *f);
 #endif
 
 
-//! Pointer to the base of the USART module instance to use for stdio.
+/*! Pointer to the base of the USART module instance to use for stdio.*/
 extern volatile void *volatile stdio_base;
-//! Pointer to the external low level write function.
+/*! Pointer to the external low level write function.*/
 extern int (*ptr_put)(void volatile*, char);
 
-//! Pointer to the external low level read function.
+/*! Pointer to the external low level read function.*/
 extern void (*ptr_get)(void volatile*, char*);
 
 /*! \brief Initializes the stdio in Serial Mode.
@@ -91,33 +91,33 @@ extern void (*ptr_get)(void volatile*, char*);
  */
 static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt)
 {
-	stdio_base = (void *)usart;
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+    stdio_base = (void *)usart;
+    ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+    ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
 # if (XMEGA || MEGA_RF)
-	usart_serial_init((USART_t *)usart,opt);
+    usart_serial_init((USART_t *)usart,opt);
 # elif UC3
-	usart_serial_init(usart,(usart_serial_options_t *)opt);
+    usart_serial_init(usart,(usart_serial_options_t *)opt);
 # elif SAM
-	usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt);
+    usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt);
 # else
 #  error Unsupported chip type
 # endif
 
 # if defined(__GNUC__)
 #  if (XMEGA || MEGA_RF)
-	// For AVR GCC libc print redirection uses fdevopen.
-	fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
+    /* For AVR GCC libc print redirection uses fdevopen.*/
+    fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
 #  endif
 #  if UC3 || SAM
-	// For AVR32 and SAM GCC
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
+    /* For AVR32 and SAM GCC*/
+    /* Specify that stdout and stdin should not be buffered.*/
+    setbuf(stdout, NULL);
+    setbuf(stdin, NULL);
+    /* Note: Already the case in IAR's Normal DLIB default configuration*/
+    /* and AVR GCC library:*/
+    /* - printf() emits one character at a time.*/
+    /* - getchar() requests only 1 byte to exit.*/
 #  endif
 # endif
 }
@@ -126,4 +126,4 @@ static inline void stdio_serial_init(volatile void *usart, const usart_serial_op
  * \}
  */
 
-#endif  // _STDIO_SERIAL_H_
+#endif  /* _STDIO_SERIAL_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c
index 7eaa962f07fd..b5ac06040144 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.c
@@ -54,67 +54,69 @@ static bool stdio_usb_interface_enable = false;
 
 int stdio_usb_putchar (volatile void * unused, char data)
 {
-	/* A negative return value should be used to indicate that data
-	 * was not written, but this doesn't seem to work with GCC libc.
-	 */
-	if (!stdio_usb_interface_enable) {
-		return 0;  // -1
-	}
+    /* A negative return value should be used to indicate that data
+     * was not written, but this doesn't seem to work with GCC libc.
+     */
+    if (!stdio_usb_interface_enable)
+    {
+        return 0;  /* -1*/
+    }
 
-	return udi_cdc_putc(data) ? 0 : -1;
+    return udi_cdc_putc(data) ? 0 : -1;
 }
 
 void stdio_usb_getchar (void volatile * unused, char *data)
 {
-	/* A negative return value should be used to indicate that data
-	 * was not read, but this doesn't seem to work with GCC libc.
-	 */
-	if (!stdio_usb_interface_enable) {
-		*data = 0;  // -1
-		return;
-	}
+    /* A negative return value should be used to indicate that data
+     * was not read, but this doesn't seem to work with GCC libc.
+     */
+    if (!stdio_usb_interface_enable)
+    {
+        *data = 0;  /* -1*/
+        return;
+    }
 
-	*data = (char)udi_cdc_getc();
+    *data = (char)udi_cdc_getc();
 }
 
 bool stdio_usb_enable(void)
 {
-	stdio_usb_interface_enable = true;
-	return true;
+    stdio_usb_interface_enable = true;
+    return true;
 }
 
 void stdio_usb_disable(void)
 {
-	stdio_usb_interface_enable = false;
+    stdio_usb_interface_enable = false;
 }
 
 void stdio_usb_init(void)
 {
-	stdio_base = NULL;
-	ptr_put = stdio_usb_putchar;
-	ptr_get = stdio_usb_getchar;
+    stdio_base = NULL;
+    ptr_put = stdio_usb_putchar;
+    ptr_get = stdio_usb_getchar;
 
-	/*
-	 * Start and attach USB CDC device interface for devices with
-	 * integrated USB interfaces.  Assume the VBUS is present if
-	 * VBUS monitoring is not available.
-	 */
-	udc_start ();
+    /*
+     * Start and attach USB CDC device interface for devices with
+     * integrated USB interfaces.  Assume the VBUS is present if
+     * VBUS monitoring is not available.
+     */
+    udc_start ();
 
 #if defined(__GNUC__)
 # if XMEGA
-	// For AVR GCC libc print redirection uses fdevopen.
-	fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
+    /* For AVR GCC libc print redirection uses fdevopen.*/
+    fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read));
 # endif
 # if UC3 || SAM
-	// For AVR32 and SAM GCC
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
+    /* For AVR32 and SAM GCC*/
+    /* Specify that stdout and stdin should not be buffered.*/
+    setbuf(stdout, NULL);
+    setbuf(stdin, NULL);
+    /* Note: Already the case in IAR's Normal DLIB default configuration*/
+    /* and AVR GCC library:*/
+    /* - printf() emits one character at a time.*/
+    /* - getchar() requests only 1 byte to exit.*/
 # endif
 #endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h
index 4d0084f16782..48b7d50d17fc 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/stdio_usb/stdio_usb.h
@@ -71,11 +71,11 @@ extern int _write (char c, int *f);
 extern int _read (int *f);
 
 
-//! Pointer to the base of the USART module instance to use for stdio.
+/*! Pointer to the base of the USART module instance to use for stdio.*/
 extern volatile void *volatile stdio_base;
-//! Pointer to the external low level write function.
+/*! Pointer to the external low level write function.*/
 extern int (*ptr_put)(void volatile*, char);
-//! Pointer to the external low level read function.
+/*! Pointer to the external low level read function.*/
 extern void (*ptr_get)(void volatile*, char*);
 
 /*! \brief Sends a character with the USART.
@@ -120,4 +120,4 @@ void stdio_usb_init(void);
  * \}
  */
 
-#endif  // _stdio_usb_h_
+#endif  /* _stdio_usb_h_*/
diff --git a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c
index 1e8f45943774..d514cf118bdc 100644
--- a/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c
+++ b/bsp/samd21/sam_d2x_asflib/common/utils/stdio/write.c
@@ -80,26 +80,30 @@ _STD_BEGIN
  */
 size_t __write(int handle, const unsigned char *buffer, size_t size)
 {
-	size_t nChars = 0;
-
-	if (buffer == 0) {
-		// This means that we should flush internal buffers.
-		return 0;
-	}
-
-	// This implementation only writes to stdout and stderr.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
-		return _LLIO_ERROR;
-	}
-
-	for (; size != 0; --size) {
-		if (ptr_put(stdio_base, *buffer++) < 0) {
-			return _LLIO_ERROR;
-		}
-		++nChars;
-	}
-	return nChars;
+    size_t nChars = 0;
+
+    if (buffer == 0)
+    {
+        /* This means that we should flush internal buffers.*/
+        return 0;
+    }
+
+    /* This implementation only writes to stdout and stderr.*/
+    /* For all other file handles, it returns failure.*/
+    if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
+    {
+        return _LLIO_ERROR;
+    }
+
+    for (; size != 0; --size)
+    {
+        if (ptr_put(stdio_base, *buffer++) < 0)
+        {
+            return _LLIO_ERROR;
+        }
+        ++nChars;
+    }
+    return nChars;
 }
 
 _STD_END
@@ -113,19 +117,22 @@ _write (int file, const char *ptr, int len);
 int __attribute__((weak))
 _write (int file, const char *ptr, int len)
 {
-	int nChars = 0;
-
-	if ((file != 1) && (file != 2) && (file!=3)) {
-		return -1;
-	}
-
-	for (; len != 0; --len) {
-		if (ptr_put(stdio_base, *ptr++) < 0) {
-			return -1;
-		}
-		++nChars;
-	}
-	return nChars;
+    int nChars = 0;
+
+    if ((file != 1) && (file != 2) && (file!=3))
+    {
+        return -1;
+    }
+
+    for (; len != 0; --len)
+    {
+        if (ptr_put(stdio_base, *ptr++) < 0)
+        {
+            return -1;
+        }
+        ++nChars;
+    }
+    return nChars;
 }
 
 #elif (defined(__GNUC__) && (XMEGA || MEGA))
@@ -134,10 +141,11 @@ int _write (char c, int *f);
 
 int _write (char c, int *f)
 {
-	if (ptr_put(stdio_base, c) < 0) {
-		return -1;
-	}
-	return 1;
+    if (ptr_put(stdio_base, c) < 0)
+    {
+        return -1;
+    }
+    return 1;
 }
 #endif
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c
index c14090fe19a2..96c5dcae2430 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.c
@@ -55,21 +55,21 @@ void delay_init(void)
 {
 }
 
-// Delay loop is put to SRAM so that FWS will not affect delay time
+/* Delay loop is put to SRAM so that FWS will not affect delay time*/
 OPTIMIZE_HIGH
 RAMFUNC
 void portable_delay_cycles(unsigned long n)
 {
-	UNUSED(n);
+    UNUSED(n);
 
-	__asm (
-		"loop: DMB	\n"
+    __asm (
+        "loop: DMB  \n"
 #ifdef __ICCARM__
-		"SUBS r0, r0, #1 \n"
+        "SUBS r0, r0, #1 \n"
 #else
-		"SUB r0, r0, #1 \n"
+        "SUB r0, r0, #1 \n"
 #endif
-		"CMP r0, #0  \n"
-		"BNE loop         "
-	);
+        "CMP r0, #0  \n"
+        "BNE loop         "
+    );
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h
index 3a52bc574eaa..85700ec1a812 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/cycle_counter.h
@@ -104,16 +104,16 @@ extern "C" {
 void portable_delay_cycles(unsigned long n);
 
 #define cpu_ms_2_cy(ms, f_cpu)  \
-	(((uint64_t)(ms) * (f_cpu) + (uint64_t)(7e3-1ul)) / (uint64_t)7e3)
+    (((uint64_t)(ms) * (f_cpu) + (uint64_t)(7e3-1ul)) / (uint64_t)7e3)
 #define cpu_us_2_cy(us, f_cpu)  \
-	(((uint64_t)(us) * (f_cpu) + (uint64_t)(7e6-1ul)) / (uint64_t)7e6)
+    (((uint64_t)(us) * (f_cpu) + (uint64_t)(7e6-1ul)) / (uint64_t)7e6)
 
 #define delay_cycles               portable_delay_cycles
 
 #define cpu_delay_s(delay) delay_cycles(cpu_ms_2_cy(1000 * delay, F_CPU))
 #define cpu_delay_ms(delay) delay_cycles(cpu_ms_2_cy(delay, F_CPU))
 #define cpu_delay_us(delay) delay_cycles(cpu_us_2_cy(delay, F_CPU))
-//! @}
+/*! @}*/
 
 
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c
index 5a007cdba687..51391d1cafa3 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.c
@@ -60,11 +60,11 @@ static uint32_t cycles_per_us = 8000000UL / 1000000;
  */
 void delay_init(void)
 {
-	cycles_per_ms = system_gclk_gen_get_hz(0);
-	cycles_per_ms /= 1000;
-	cycles_per_us = cycles_per_ms / 1000;
+    cycles_per_ms = system_gclk_gen_get_hz(0);
+    cycles_per_ms /= 1000;
+    cycles_per_us = cycles_per_ms / 1000;
 
-	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
+    SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
 }
 
 /**
@@ -73,12 +73,13 @@ void delay_init(void)
  * \param n  Number of microseconds to wait
  */
 void delay_cycles_us(
-		uint32_t n)
+        uint32_t n)
 {
-	while (n--) {
-		/* Devide up to blocks of 10u */
-		delay_cycles(cycles_per_us);
-	}
+    while (n--)
+    {
+        /* Devide up to blocks of 10u */
+        delay_cycles(cycles_per_us);
+    }
 }
 
 /**
@@ -87,10 +88,11 @@ void delay_cycles_us(
  * \param n  Number of milliseconds to wait
  */
 void delay_cycles_ms(
-		uint32_t n)
+        uint32_t n)
 {
-	while (n--) {
-		/* Devide up to blocks of 1ms */
-		delay_cycles(cycles_per_ms);
-	}
+    while (n--)
+    {
+        /* Devide up to blocks of 1ms */
+        delay_cycles(cycles_per_ms);
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h
index 06885e63c693..8b668a485fef 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/delay/sam0/systick_counter.h
@@ -66,15 +66,17 @@ extern "C" {
  * \param n  Number of cycles to delay
  */
 static inline void delay_cycles(
-		const uint32_t n)
+        const uint32_t n)
 {
-	if (n > 0) {
-		SysTick->LOAD = n;
-		SysTick->VAL = 0;
+    if (n > 0)
+    {
+        SysTick->LOAD = n;
+        SysTick->VAL = 0;
 
-		while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) {
-		};
-	}
+        while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk))
+        {
+        };
+    }
 }
 
 void delay_cycles_us(uint32_t n);
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h
index 6b04da6e2d02..e2a1f581f8b7 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono.h
@@ -102,20 +102,20 @@ typedef uint8_t gfx_coord_t;
 
 /** Pixel operations */
 enum gfx_mono_color {
-	/** Pixel is cleared */
-	GFX_PIXEL_CLR = 0,
-	/** Pixel is set on screen (OR) */
-	GFX_PIXEL_SET = 1,
-	/** Pixel is XORed */
-	GFX_PIXEL_XOR = 2,
+    /** Pixel is cleared */
+    GFX_PIXEL_CLR = 0,
+    /** Pixel is set on screen (OR) */
+    GFX_PIXEL_SET = 1,
+    /** Pixel is XORed */
+    GFX_PIXEL_XOR = 2,
 };
 
 /** Bitmap types */
 enum gfx_mono_bitmap_type {
-	/** Bitmap stored in SRAM */
-	GFX_MONO_BITMAP_RAM,
-	/** Bitmap stored in progmem */
-	GFX_MONO_BITMAP_PROGMEM
+    /** Bitmap stored in SRAM */
+    GFX_MONO_BITMAP_RAM,
+    /** Bitmap stored in progmem */
+    GFX_MONO_BITMAP_PROGMEM
 };
 
 /* Cannot be moved to top, as they use the bitmap and color enums. */
@@ -294,9 +294,9 @@ enum gfx_mono_bitmap_type {
  * \subsection asfdoc_common2_gfx_mono_basic_usage_code Example code
  * Add to, e.g., the main function in the application C-file:
  * \code
-	system_init();
-	gfx_mono_init();
-	gfx_mono_draw_line(10, 10, 20, 20, GFX_PIXEL_SET);
+    system_init();
+    gfx_mono_init();
+    gfx_mono_draw_line(10, 10, 20, 20, GFX_PIXEL_SET);
 \endcode
  *
  * \subsection gfx_mono_basic_usage_workflow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c
index 296335726fde..f86a931d5c8c 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.c
@@ -62,28 +62,30 @@ static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
  */
 void gfx_mono_st7565r_init(void)
 {
-	uint8_t page;
-	uint8_t column;
+    uint8_t page;
+    uint8_t column;
 
 #ifdef CONFIG_ST7565R_FRAMEBUFFER
-	gfx_mono_set_framebuffer(framebuffer);
+    gfx_mono_set_framebuffer(framebuffer);
 #endif
 
-	/* Initialize the low-level display controller. */
-	st7565r_init();
-
-	/* Set display to output data from line 0 */
-	st7565r_set_display_start_line_address(0);
-
-	/* Clear the contents of the display.
-	 * If using a framebuffer (SPI interface) it will both clear the
-	 * controller memory and the framebuffer.
-	 */
-	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
-		for (column = 0; column < GFX_MONO_LCD_WIDTH; column++) {
-			gfx_mono_put_byte(page, column, 0x00);
-		}
-	}
+    /* Initialize the low-level display controller. */
+    st7565r_init();
+
+    /* Set display to output data from line 0 */
+    st7565r_set_display_start_line_address(0);
+
+    /* Clear the contents of the display.
+     * If using a framebuffer (SPI interface) it will both clear the
+     * controller memory and the framebuffer.
+     */
+    for (page = 0; page < GFX_MONO_LCD_PAGES; page++)
+    {
+        for (column = 0; column < GFX_MONO_LCD_WIDTH; column++)
+        {
+            gfx_mono_put_byte(page, column, 0x00);
+        }
+    }
 }
 
 /**
@@ -97,15 +99,16 @@ void gfx_mono_st7565r_init(void)
  */
 void gfx_mono_st7565r_put_framebuffer(void)
 {
-	uint8_t page;
-
-	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
-		st7565r_set_page_address(page);
-		st7565r_set_column_address(0);
-		gfx_mono_st7565r_put_page(framebuffer
-				+ (page * GFX_MONO_LCD_WIDTH), page, 0,
-				GFX_MONO_LCD_WIDTH);
-	}
+    uint8_t page;
+
+    for (page = 0; page < GFX_MONO_LCD_PAGES; page++)
+    {
+        st7565r_set_page_address(page);
+        st7565r_set_column_address(0);
+        gfx_mono_st7565r_put_page(framebuffer
+                + (page * GFX_MONO_LCD_WIDTH), page, 0,
+                GFX_MONO_LCD_WIDTH);
+    }
 }
 
 /**
@@ -117,57 +120,59 @@ void gfx_mono_st7565r_put_framebuffer(void)
  *
  * The following will set the pixel at x=10,y=10:
  * \code
-	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_SET);
+    gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_SET);
 \endcode
  * The following example will clear the pixel at x=10,y=10:
  * \code
-	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_CLR);
+    gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_CLR);
 \endcode
  * And the following will toggle the pixel at x=10,y=10:
  * \code
-	gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_XOR);
+    gfx_mono_st7565r_draw_pixel(10, 10, GFX_PIXEL_XOR);
 \endcode
  */
 void gfx_mono_st7565r_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t color)
+        gfx_coord_t color)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
-	uint8_t pixel_value;
-
-	/* Discard pixels drawn outside the screen */
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return;
-	}
-
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
-
-	/*
-	 * Read the page containing the pixel in interest, then perform the
-	 * requested action on this pixel before writing the page back to the
-	 * display.
-	 */
-	pixel_value = gfx_mono_get_byte(page, x);
-
-	switch (color) {
-	case GFX_PIXEL_SET:
-		pixel_value |= pixel_mask;
-		break;
-
-	case GFX_PIXEL_CLR:
-		pixel_value &= ~pixel_mask;
-		break;
-
-	case GFX_PIXEL_XOR:
-		pixel_value ^= pixel_mask;
-		break;
-
-	default:
-		break;
-	}
-
-	gfx_mono_put_byte(page, x, pixel_value);
+    uint8_t page;
+    uint8_t pixel_mask;
+    uint8_t pixel_value;
+
+    /* Discard pixels drawn outside the screen */
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return;
+    }
+
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
+
+    /*
+     * Read the page containing the pixel in interest, then perform the
+     * requested action on this pixel before writing the page back to the
+     * display.
+     */
+    pixel_value = gfx_mono_get_byte(page, x);
+
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        pixel_value |= pixel_mask;
+        break;
+
+    case GFX_PIXEL_CLR:
+        pixel_value &= ~pixel_mask;
+        break;
+
+    case GFX_PIXEL_XOR:
+        pixel_value ^= pixel_mask;
+        break;
+
+    default:
+        break;
+    }
+
+    gfx_mono_put_byte(page, x, pixel_value);
 }
 
 /**
@@ -179,22 +184,23 @@ void gfx_mono_st7565r_draw_pixel(gfx_coord_t x, gfx_coord_t y,
  *
  * The following example will read the pixel value from x=10,y=10:
  * \code
-	pixelval = gfx_mono_st7565r_get_pixel(10,10);
+    pixelval = gfx_mono_st7565r_get_pixel(10,10);
 \endcode
  */
 uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
+    uint8_t page;
+    uint8_t pixel_mask;
 
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return 0;
-	}
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return 0;
+    }
 
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
 
-	return gfx_mono_get_byte(page, x) & pixel_mask;
+    return gfx_mono_get_byte(page, x) & pixel_mask;
 }
 
 /**
@@ -202,7 +208,7 @@ uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y)
  *
  * If the controller is accessed by the SPI interface, we can not read
  * back data from the LCD controller RAM. Because of this all data that is
- * written to the LCD controller in this mode is also written to a framebuffer 
+ * written to the LCD controller in this mode is also written to a framebuffer
  * in MCU RAM.
  *
  * \param[in] data Pointer to data to be written
@@ -214,21 +220,21 @@ uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y)
  * column 10. This will place data_buf in the rectangle x1=10,y1=0,x2=42,y2=8
  * (10 pixels from the upper left corner of the screen):
  * \code
-	gfx_mono_st7565r_put_page(data_buf, 0, 10, 32);
+    gfx_mono_st7565r_put_page(data_buf, 0, 10, 32);
 \endcode
  */
 void gfx_mono_st7565r_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
 #ifdef CONFIG_ST7565R_FRAMEBUFFER
-	gfx_mono_framebuffer_put_page(data, page, column, width);
+    gfx_mono_framebuffer_put_page(data, page, column, width);
 #endif
-	st7565r_set_page_address(page);
-	st7565r_set_column_address(column);
+    st7565r_set_page_address(page);
+    st7565r_set_column_address(column);
 
-	do {
-		st7565r_write_data(*data++);
-	} while (--width);
+    do {
+        st7565r_write_data(*data++);
+    } while (--width);
 }
 
 /**
@@ -246,21 +252,21 @@ void gfx_mono_st7565r_put_page(gfx_mono_color_t *data, gfx_coord_t page,
  * The following example will read back the first 128 bytes (first page) from
  * the display memory:
  * \code
-	gfx_mono_st7565r_get_page(read_buffer, 0, 0, 128);
+    gfx_mono_st7565r_get_page(read_buffer, 0, 0, 128);
 \endcode
  */
 void gfx_mono_st7565r_get_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
 #ifdef CONFIG_ST7565R_FRAMEBUFFER
-	gfx_mono_framebuffer_get_page(data, page, column, width);
+    gfx_mono_framebuffer_get_page(data, page, column, width);
 #else
-	st7565r_set_page_address(page);
-	st7565r_set_column_address(column);
+    st7565r_set_page_address(page);
+    st7565r_set_column_address(column);
 
-	do {
-		*data++ = st7565r_read_data();
-	} while (--width);
+    do {
+        *data++ = st7565r_read_data();
+    } while (--width);
 #endif
 }
 
@@ -278,20 +284,20 @@ void gfx_mono_st7565r_get_page(gfx_mono_color_t *data, gfx_coord_t page,
  * setting a 8 pixel high column of pixels in the upper left corner of the
  * display.
  * \code
-	gfx_mono_st7565r_put_byte(0, 0, 0xFF);
+    gfx_mono_st7565r_put_byte(0, 0, 0xFF);
 \endcode
  */
 void gfx_mono_st7565r_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data)
+        uint8_t data)
 {
 #ifdef CONFIG_ST7565R_FRAMEBUFFER
-	gfx_mono_framebuffer_put_byte(page, column, data);
+    gfx_mono_framebuffer_put_byte(page, column, data);
 #endif
 
-	st7565r_set_page_address(page);
-	st7565r_set_column_address(column);
+    st7565r_set_page_address(page);
+    st7565r_set_column_address(column);
 
-	st7565r_write_data(data);
+    st7565r_write_data(data);
 }
 
 /**
@@ -308,19 +314,19 @@ void gfx_mono_st7565r_put_byte(gfx_coord_t page, gfx_coord_t column,
  * local framebuffer if direct read is not possible. The data represents the
  * pixels from x = 0 and y = 0 to y = 7.
  * \code
-	data = gfx_mono_st7565r_get_byte(0, 0);
+    data = gfx_mono_st7565r_get_byte(0, 0);
 \endcode
  */
 uint8_t gfx_mono_st7565r_get_byte(gfx_coord_t page, gfx_coord_t column)
 {
 #ifdef CONFIG_ST7565R_FRAMEBUFFER
-	return gfx_mono_framebuffer_get_byte(page, column);
+    return gfx_mono_framebuffer_get_byte(page, column);
 
 #else
-	st7565r_set_page_address(page);
-	st7565r_set_column_address(column);
+    st7565r_set_page_address(page);
+    st7565r_set_column_address(column);
 
-	return st7565r_read_data();
+    return st7565r_read_data();
 
 #endif
 }
@@ -340,30 +346,31 @@ uint8_t gfx_mono_st7565r_get_byte(gfx_coord_t page, gfx_coord_t column)
  *
  * A small example that will XOR the first byte of display memory with 0xAA
  * \code
-	gfx_mono_st7565r_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+    gfx_mono_st7565r_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
 \endcode
  */
 void gfx_mono_st7565r_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
 {
-	gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
+    gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
 
-	switch (color) {
-	case GFX_PIXEL_SET:
-		temp |= pixel_mask;
-		break;
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        temp |= pixel_mask;
+        break;
 
-	case GFX_PIXEL_CLR:
-		temp &= ~pixel_mask;
-		break;
+    case GFX_PIXEL_CLR:
+        temp &= ~pixel_mask;
+        break;
 
-	case GFX_PIXEL_XOR:
-		temp ^= pixel_mask;
-		break;
+    case GFX_PIXEL_XOR:
+        temp ^= pixel_mask;
+        break;
 
-	default:
-		break;
-	}
+    default:
+        break;
+    }
 
-	gfx_mono_put_byte(page, column, temp);
+    gfx_mono_put_byte(page, column, temp);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h
index 9aa99c02fe87..91049dfa5e83 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_c12832_a1z.h
@@ -74,90 +74,90 @@ extern "C" {
 
 #define GFX_MONO_LCD_WIDTH              128
 #ifndef GFX_MONO_LCD_HEIGHT
-#	define GFX_MONO_LCD_HEIGHT             32
+#   define GFX_MONO_LCD_HEIGHT             32
 #endif
 #define GFX_MONO_LCD_PIXELS_PER_BYTE    8
 #define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
-	GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_PIXELS_PER_BYTE)
 #define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
-	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
 
 #define gfx_mono_draw_horizontal_line(x, y, length, color) \
-	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+    gfx_mono_generic_draw_horizontal_line(x, y, length, color)
 
 #define gfx_mono_draw_vertical_line(x, y, length, color) \
-	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+    gfx_mono_generic_draw_vertical_line(x, y, length, color)
 
 #define gfx_mono_draw_line(x1, y1, x2, y2, color) \
-	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+    gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
 
 #define gfx_mono_draw_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_rect(x, y, width, height, color)
+    gfx_mono_generic_draw_rect(x, y, width, height, color)
 
 #define gfx_mono_draw_filled_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
-		color)
+    gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+        color)
 
 #define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
-	gfx_mono_generic_draw_circle(x, y, radius, color, \
-		octant_mask)
+    gfx_mono_generic_draw_circle(x, y, radius, color, \
+        octant_mask)
 
-#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
-	gfx_mono_generic_draw_filled_circle(x, y, radius, \
-		color, quadrant_mask)
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask) \
+    gfx_mono_generic_draw_filled_circle(x, y, radius, \
+        color, quadrant_mask)
 
 #define gfx_mono_put_bitmap(bitmap, x, y) \
-	gfx_mono_generic_put_bitmap(bitmap, x, y)
+    gfx_mono_generic_put_bitmap(bitmap, x, y)
 
 #define gfx_mono_draw_pixel(x, y, color) \
-	gfx_mono_st7565r_draw_pixel(x, y, color)
+    gfx_mono_st7565r_draw_pixel(x, y, color)
 
 #define gfx_mono_get_pixel(x, y) \
-	gfx_mono_st7565r_get_pixel(x, y)
+    gfx_mono_st7565r_get_pixel(x, y)
 
-#define gfx_mono_init()	\
-	gfx_mono_st7565r_init()
+#define gfx_mono_init() \
+    gfx_mono_st7565r_init()
 
 #define gfx_mono_put_page(data, page, column, width) \
-	gfx_mono_st7565r_put_page(data, page, column, width)
+    gfx_mono_st7565r_put_page(data, page, column, width)
 
 #define gfx_mono_get_page(data, page, column, width) \
-	gfx_mono_st7565r_get_page(data, page, column, width)
+    gfx_mono_st7565r_get_page(data, page, column, width)
 
 #define gfx_mono_put_byte(page, column, data) \
-	gfx_mono_st7565r_put_byte(page, column, data)
+    gfx_mono_st7565r_put_byte(page, column, data)
 
-#define gfx_mono_get_byte(page, column)	\
-	gfx_mono_st7565r_get_byte(page, column)
+#define gfx_mono_get_byte(page, column) \
+    gfx_mono_st7565r_get_byte(page, column)
 
 #define gfx_mono_mask_byte(page, column, pixel_mask, color) \
-	gfx_mono_st7565r_mask_byte(page, column, pixel_mask, color)
+    gfx_mono_st7565r_mask_byte(page, column, pixel_mask, color)
 
 #define gfx_mono_put_framebuffer() \
-	gfx_mono_st7565r_put_framebuffer()
+    gfx_mono_st7565r_put_framebuffer()
 
 void gfx_mono_st7565r_put_framebuffer(void);
 
 void gfx_mono_st7565r_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_st7565r_get_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_st7565r_init(void);
 
 void gfx_mono_st7565r_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_mono_color_t color);
+        gfx_mono_color_t color);
 
 uint8_t gfx_mono_st7565r_get_pixel(gfx_coord_t x, gfx_coord_t y);
 
 void gfx_mono_st7565r_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data);
+        uint8_t data);
 
 uint8_t gfx_mono_st7565r_get_byte(gfx_coord_t page, gfx_coord_t column);
 
 void gfx_mono_st7565r_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c
index 8e44bf8e519d..6c47cce68974 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.c
@@ -57,13 +57,13 @@ static uint8_t *fbpointer;
  *
  * A small example:
  * \code
-	uint8_t framebuffer[FRAMEBUFFER_SIZE];
-	gfx_mono_set_framebuffer(framebuffer);
+    uint8_t framebuffer[FRAMEBUFFER_SIZE];
+    gfx_mono_set_framebuffer(framebuffer);
 \endcode
  */
 void gfx_mono_set_framebuffer(uint8_t *framebuffer)
 {
-	fbpointer = framebuffer;
+    fbpointer = framebuffer;
 }
 
 /**
@@ -77,19 +77,19 @@ void gfx_mono_set_framebuffer(uint8_t *framebuffer)
  * The following example will write 32 bytes from data_buf to the page 0,
  * column 10 (byte 10 to 42 in the framebuffer).
  * \code
-	gfx_mono_framebuffer_put_page(data_buf, 0, 10, 32);
+    gfx_mono_framebuffer_put_page(data_buf, 0, 10, 32);
 \endcode
  */
 void gfx_mono_framebuffer_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
-	gfx_mono_color_t *data_pt = data;
-	gfx_coord_t *framebuffer_pt = fbpointer +
-			((page * GFX_MONO_LCD_WIDTH) + column);
+    gfx_mono_color_t *data_pt = data;
+    gfx_coord_t *framebuffer_pt = fbpointer +
+            ((page * GFX_MONO_LCD_WIDTH) + column);
 
-	do {
-		*framebuffer_pt++ = *data_pt++;
-	} while (--width > 0);
+    do {
+        *framebuffer_pt++ = *data_pt++;
+    } while (--width > 0);
 }
 
 /**
@@ -103,17 +103,17 @@ void gfx_mono_framebuffer_put_page(gfx_mono_color_t *data, gfx_coord_t page,
  * The following example will read back the first 128 bytes (first page) from
  * the framebuffer:
  * \code
-	gfx_mono_framebuffer_get_page(read_buffer, 0, 0, 128);
+    gfx_mono_framebuffer_get_page(read_buffer, 0, 0, 128);
 \endcode
  */
 void gfx_mono_framebuffer_get_page(gfx_mono_color_t *data, gfx_coord_t page, \
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
-	gfx_coord_t *framebuffer_pt = fbpointer +
-			((page * GFX_MONO_LCD_WIDTH) + column);
-	do {
-		*data++ = *framebuffer_pt++;
-	} while (--width > 0);
+    gfx_coord_t *framebuffer_pt = fbpointer +
+            ((page * GFX_MONO_LCD_WIDTH) + column);
+    do {
+        *data++ = *framebuffer_pt++;
+    } while (--width > 0);
 }
 
 /**
@@ -125,45 +125,47 @@ void gfx_mono_framebuffer_get_page(gfx_mono_color_t *data, gfx_coord_t page, \
  *
  */
 void gfx_mono_framebuffer_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_mono_color_t color)
+        gfx_mono_color_t color)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
-	uint8_t pixel_value;
+    uint8_t page;
+    uint8_t pixel_mask;
+    uint8_t pixel_value;
 
-	/* Discard pixels drawn outside the screen */
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return;
-	}
+    /* Discard pixels drawn outside the screen */
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return;
+    }
 
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
 
-	/*
-	 * Read the page containing the pixel in interest, then perform the
-	 * requested action on this pixel before writing the page back to the
-	 * display.
-	 */
-	pixel_value = gfx_mono_framebuffer_get_byte(page, x);
+    /*
+     * Read the page containing the pixel in interest, then perform the
+     * requested action on this pixel before writing the page back to the
+     * display.
+     */
+    pixel_value = gfx_mono_framebuffer_get_byte(page, x);
 
-	switch (color) {
-	case GFX_PIXEL_SET:
-		pixel_value |= pixel_mask;
-		break;
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        pixel_value |= pixel_mask;
+        break;
 
-	case GFX_PIXEL_CLR:
-		pixel_value &= ~pixel_mask;
-		break;
+    case GFX_PIXEL_CLR:
+        pixel_value &= ~pixel_mask;
+        break;
 
-	case GFX_PIXEL_XOR:
-		pixel_value ^= pixel_mask;
-		break;
+    case GFX_PIXEL_XOR:
+        pixel_value ^= pixel_mask;
+        break;
 
-	default:
-		break;
-	}
+    default:
+        break;
+    }
 
-	gfx_mono_framebuffer_put_byte(page, x, pixel_value);
+    gfx_mono_framebuffer_put_byte(page, x, pixel_value);
 }
 
 /**
@@ -176,17 +178,18 @@ void gfx_mono_framebuffer_draw_pixel(gfx_coord_t x, gfx_coord_t y,
  */
 uint8_t gfx_mono_framebuffer_get_pixel(gfx_coord_t x, gfx_coord_t y)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
+    uint8_t page;
+    uint8_t pixel_mask;
 
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return 0;
-	}
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return 0;
+    }
 
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
 
-	return gfx_mono_framebuffer_get_byte(page, x) & pixel_mask;
+    return gfx_mono_framebuffer_get_byte(page, x) & pixel_mask;
 }
 
 /**
@@ -198,13 +201,13 @@ uint8_t gfx_mono_framebuffer_get_pixel(gfx_coord_t x, gfx_coord_t y)
  *
  * This example will put the value 0xFF to the first byte in the framebuffer
  * \code
-	gfx_mono_framebuffer_put_byte(0, 0, 0xFF);
+    gfx_mono_framebuffer_put_byte(0, 0, 0xFF);
 \endcode
  */
 void gfx_mono_framebuffer_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data)
+        uint8_t data)
 {
-	*(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column) = data;
+    *(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column) = data;
 }
 
 /**
@@ -216,12 +219,12 @@ void gfx_mono_framebuffer_put_byte(gfx_coord_t page, gfx_coord_t column,
  *
  * The following code will read the first byte of the framebuffer
  * \code
-	data = gfx_mono_framebuffer_get_byte(0, 0);
+    data = gfx_mono_framebuffer_get_byte(0, 0);
 \endcode
  */
 uint8_t gfx_mono_framebuffer_get_byte(gfx_coord_t page, gfx_coord_t column)
 {
-	return *(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column);
+    return *(fbpointer + (page * GFX_MONO_LCD_WIDTH) + column);
 }
 
 /**
@@ -238,29 +241,30 @@ uint8_t gfx_mono_framebuffer_get_byte(gfx_coord_t page, gfx_coord_t column)
  *
  * A small example that will XOR the first byte of the framebuffer with 0xAA
  * \code
-	gfx_mono_framebuffer_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+    gfx_mono_framebuffer_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
 \endcode
  */
 void gfx_mono_framebuffer_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
 {
-	gfx_mono_color_t temp;
+    gfx_mono_color_t temp;
 
-	temp = gfx_mono_get_byte(page, column);
+    temp = gfx_mono_get_byte(page, column);
 
-	switch (color) {
-	case GFX_PIXEL_SET:
-		temp |= pixel_mask;
-		break;
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        temp |= pixel_mask;
+        break;
 
-	case GFX_PIXEL_CLR:
-		temp &= ~pixel_mask;
-		break;
+    case GFX_PIXEL_CLR:
+        temp &= ~pixel_mask;
+        break;
 
-	case GFX_PIXEL_XOR:
-		temp ^= pixel_mask;
-		break;
-	}
+    case GFX_PIXEL_XOR:
+        temp ^= pixel_mask;
+        break;
+    }
 
-	gfx_mono_put_byte(page, column, temp);
+    gfx_mono_put_byte(page, column, temp);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h
index a7b15436e180..60c0d03ddb28 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_framebuffer.h
@@ -69,23 +69,23 @@ extern "C" {
 void gfx_mono_set_framebuffer(uint8_t *framebuffer);
 
 void gfx_mono_framebuffer_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_framebuffer_get_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_framebuffer_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_mono_color_t color);
+        gfx_mono_color_t color);
 
 uint8_t gfx_mono_framebuffer_get_pixel(gfx_coord_t x, gfx_coord_t y);
 
 void gfx_mono_framebuffer_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data);
+        uint8_t data);
 
 uint8_t gfx_mono_framebuffer_get_byte(gfx_coord_t page, gfx_coord_t column);
 
 void gfx_mono_framebuffer_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c
index 42e18bae3c01..eda1ba2c509d 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.c
@@ -64,53 +64,59 @@
  * \param[in]  color      Pixel operation of the line.
  */
 void gfx_mono_generic_draw_horizontal_line(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t length, enum gfx_mono_color color)
+        gfx_coord_t length, enum gfx_mono_color color)
 {
-	uint8_t page;
-	uint8_t pixelmask;
-	uint8_t temp;
-
-	/* Clip line length if too long */
-	if (x + length > GFX_MONO_LCD_WIDTH) {
-		length = GFX_MONO_LCD_WIDTH - x;
-	}
-
-	page = y / 8;
-	pixelmask = (1 << (y - (page * 8)));
-
-	if (length == 0) {
-		/* Nothing to do. Move along. */
-		return;
-	}
-
-	switch (color) {
-	case GFX_PIXEL_SET:
-		while (length-- > 0) {
-			temp = gfx_mono_get_byte(page, x + length);
-			temp |= pixelmask;
-			gfx_mono_put_byte(page, x + length, temp);
-		}
-		break;
-
-	case GFX_PIXEL_CLR:
-		while (length-- > 0) {
-			temp = gfx_mono_get_byte(page, x + length);
-			temp &= ~pixelmask;
-			gfx_mono_put_byte(page, x + length, temp);
-		}
-		break;
-
-	case GFX_PIXEL_XOR:
-		while (length-- > 0) {
-			temp = gfx_mono_get_byte(page, x + length);
-			temp ^= pixelmask;
-			gfx_mono_put_byte(page, x + length, temp);
-		}
-		break;
-
-	default:
-		break;
-	}
+    uint8_t page;
+    uint8_t pixelmask;
+    uint8_t temp;
+
+    /* Clip line length if too long */
+    if (x + length > GFX_MONO_LCD_WIDTH)
+    {
+        length = GFX_MONO_LCD_WIDTH - x;
+    }
+
+    page = y / 8;
+    pixelmask = (1 << (y - (page * 8)));
+
+    if (length == 0)
+    {
+        /* Nothing to do. Move along. */
+        return;
+    }
+
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        while (length-- > 0)
+        {
+            temp = gfx_mono_get_byte(page, x + length);
+            temp |= pixelmask;
+            gfx_mono_put_byte(page, x + length, temp);
+        }
+        break;
+
+    case GFX_PIXEL_CLR:
+        while (length-- > 0)
+        {
+            temp = gfx_mono_get_byte(page, x + length);
+            temp &= ~pixelmask;
+            gfx_mono_put_byte(page, x + length, temp);
+        }
+        break;
+
+    case GFX_PIXEL_XOR:
+        while (length-- > 0)
+        {
+            temp = gfx_mono_get_byte(page, x + length);
+            temp ^= pixelmask;
+            gfx_mono_put_byte(page, x + length, temp);
+        }
+        break;
+
+    default:
+        break;
+    }
 }
 
 /**
@@ -127,45 +133,50 @@ void gfx_mono_generic_draw_horizontal_line(gfx_coord_t x, gfx_coord_t y,
  * \param[in]  color      Pixel operation of the line.
  */
 void gfx_mono_generic_draw_vertical_line(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t length, enum gfx_mono_color color)
+        gfx_coord_t length, enum gfx_mono_color color)
 {
-	if (length == 0) {
-		return;
-	}
-
-	gfx_coord_t y2 = y + length - 1;
-
-	if (y == y2) {
-		gfx_mono_draw_pixel(x, y, color);
-		return;
-	}
-
-	if (y2 >= GFX_MONO_LCD_HEIGHT - 1) {
-		y2 = GFX_MONO_LCD_HEIGHT - 1;
-	}
-
-	gfx_coord_t y1page = y / 8;
-	gfx_coord_t y2page = y2 / 8;
-
-	uint8_t y1bitpos = y & 0x07;
-	uint8_t y2bitpos = y2 & 0x07;
-
-	uint8_t y1pixelmask = 0xFF << y1bitpos;
-	uint8_t y2pixelmask = 0xFF >> (7 - y2bitpos);
-
-	/* The pixels are on the same page; combine masks */
-	if (y1page == y2page) {
-		uint8_t pixelmask = y1pixelmask & y2pixelmask;
-		gfx_mono_mask_byte(y1page, x, pixelmask, color);
-	} else {
-		gfx_mono_mask_byte(y1page, x, y1pixelmask, color);
-
-		while (++y1page < y2page) {
-			gfx_mono_mask_byte(y1page, x, 0xFF, color);
-		}
-
-		gfx_mono_mask_byte(y2page, x, y2pixelmask, color);
-	}
+    if (length == 0)
+    {
+        return;
+    }
+
+    gfx_coord_t y2 = y + length - 1;
+
+    if (y == y2)
+    {
+        gfx_mono_draw_pixel(x, y, color);
+        return;
+    }
+
+    if (y2 >= GFX_MONO_LCD_HEIGHT - 1)
+    {
+        y2 = GFX_MONO_LCD_HEIGHT - 1;
+    }
+
+    gfx_coord_t y1page = y / 8;
+    gfx_coord_t y2page = y2 / 8;
+
+    uint8_t y1bitpos = y & 0x07;
+    uint8_t y2bitpos = y2 & 0x07;
+
+    uint8_t y1pixelmask = 0xFF << y1bitpos;
+    uint8_t y2pixelmask = 0xFF >> (7 - y2bitpos);
+
+    /* The pixels are on the same page; combine masks */
+    if (y1page == y2page)
+    {
+        uint8_t pixelmask = y1pixelmask & y2pixelmask;
+        gfx_mono_mask_byte(y1page, x, pixelmask, color);
+    } else {
+        gfx_mono_mask_byte(y1page, x, y1pixelmask, color);
+
+        while (++y1page < y2page)
+        {
+            gfx_mono_mask_byte(y1page, x, 0xFF, color);
+        }
+
+        gfx_mono_mask_byte(y2page, x, y2pixelmask, color);
+    }
 }
 
 /**
@@ -178,73 +189,81 @@ void gfx_mono_generic_draw_vertical_line(gfx_coord_t x, gfx_coord_t y,
  * \param[in]  color       Pixel operation of the line.
  */
 void gfx_mono_generic_draw_line(gfx_coord_t x1, gfx_coord_t y1,
-		gfx_coord_t x2, gfx_coord_t y2,
-		enum gfx_mono_color color)
+        gfx_coord_t x2, gfx_coord_t y2,
+        enum gfx_mono_color color)
 {
-	uint8_t i;
-	uint8_t x;
-	uint8_t y;
-	int8_t xinc;
-	int8_t yinc;
-	int8_t dx;
-	int8_t dy;
-	int8_t e;
-
-	/* swap x1,y1  with x2,y2 */
-	if (x1 > x2) {
-		dx = x1;
-		x1 = x2;
-		x2 = dx;
-		dy = y1;
-		y1 = y2;
-		y2 = dy;
-	}
-
-	dx = x2 - x1;
-	dy = y2 - y1;
-
-	x = x1;
-	y = y1;
-
-	if (dx < 0) {
-		xinc = -1;
-		dx = -dx;
-	} else {
-		xinc = 1;
-	}
-
-	if (dy < 0) {
-		yinc = -1;
-		dy = -dy;
-	} else {
-		yinc = 1;
-	}
-
-	if (dx > dy) {
-		e = dy - dx;
-		for (i = 0; i <= dx; i++) {
-			gfx_mono_draw_pixel(x, y, color);
-			if (e >= 0) {
-				e -= dx;
-				y += yinc;
-			}
-
-			e += dy;
-			x += xinc;
-		}
-	} else {
-		e = dx - dy;
-		for (i = 0; i <= dy; i++) {
-			gfx_mono_draw_pixel(x, y, color);
-			if (e >= 0) {
-				e -= dy;
-				x += xinc;
-			}
-
-			e += dx;
-			y += yinc;
-		}
-	}
+    uint8_t i;
+    uint8_t x;
+    uint8_t y;
+    int8_t xinc;
+    int8_t yinc;
+    int8_t dx;
+    int8_t dy;
+    int8_t e;
+
+    /* swap x1,y1  with x2,y2 */
+    if (x1 > x2)
+    {
+        dx = x1;
+        x1 = x2;
+        x2 = dx;
+        dy = y1;
+        y1 = y2;
+        y2 = dy;
+    }
+
+    dx = x2 - x1;
+    dy = y2 - y1;
+
+    x = x1;
+    y = y1;
+
+    if (dx < 0)
+    {
+        xinc = -1;
+        dx = -dx;
+    } else {
+        xinc = 1;
+    }
+
+    if (dy < 0)
+    {
+        yinc = -1;
+        dy = -dy;
+    } else {
+        yinc = 1;
+    }
+
+    if (dx > dy)
+    {
+        e = dy - dx;
+        for (i = 0; i <= dx; i++)
+        {
+            gfx_mono_draw_pixel(x, y, color);
+            if (e >= 0)
+            {
+                e -= dx;
+                y += yinc;
+            }
+
+            e += dy;
+            x += xinc;
+        }
+    } else {
+        e = dx - dy;
+        for (i = 0; i <= dy; i++)
+        {
+            gfx_mono_draw_pixel(x, y, color);
+            if (e >= 0)
+            {
+                e -= dy;
+                x += xinc;
+            }
+
+            e += dx;
+            y += yinc;
+        }
+    }
 }
 
 /**
@@ -257,14 +276,14 @@ void gfx_mono_generic_draw_line(gfx_coord_t x1, gfx_coord_t y1,
  * \param[in] color       Pixel operation of the line.
  */
 void gfx_mono_generic_draw_rect(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t width, gfx_coord_t height,
-		enum gfx_mono_color color)
+        gfx_coord_t width, gfx_coord_t height,
+        enum gfx_mono_color color)
 {
-	gfx_mono_draw_horizontal_line(x, y, width, color);
-	gfx_mono_draw_horizontal_line(x, y + height - 1, width, color);
+    gfx_mono_draw_horizontal_line(x, y, width, color);
+    gfx_mono_draw_horizontal_line(x, y + height - 1, width, color);
 
-	gfx_mono_draw_vertical_line(x, y, height, color);
-	gfx_mono_draw_vertical_line(x + width - 1, y, height, color);
+    gfx_mono_draw_vertical_line(x, y, height, color);
+    gfx_mono_draw_vertical_line(x + width - 1, y, height, color);
 }
 
 /**
@@ -277,17 +296,19 @@ void gfx_mono_generic_draw_rect(gfx_coord_t x, gfx_coord_t y,
  * \param[in]  color       Pixel operation of the line
  */
 void gfx_mono_generic_draw_filled_rect(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t width, gfx_coord_t height,
-		enum gfx_mono_color color)
+        gfx_coord_t width, gfx_coord_t height,
+        enum gfx_mono_color color)
 {
-	if (height == 0) {
-		/* Nothing to do. Move along. */
-		return;
-	}
-
-	while (height-- > 0) {
-		gfx_mono_draw_horizontal_line(x, y + height, width, color);
-	}
+    if (height == 0)
+    {
+        /* Nothing to do. Move along. */
+        return;
+    }
+
+    while (height-- > 0)
+    {
+        gfx_mono_draw_horizontal_line(x, y + height, width, color);
+    }
 }
 
 /**
@@ -309,70 +330,81 @@ void gfx_mono_generic_draw_filled_rect(gfx_coord_t x, gfx_coord_t y,
  * \param[in]  octant_mask Bitmask indicating which octants to draw.
  */
 void gfx_mono_generic_draw_circle(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t radius, enum gfx_mono_color color,
-		uint8_t octant_mask)
+        gfx_coord_t radius, enum gfx_mono_color color,
+        uint8_t octant_mask)
 {
-	gfx_coord_t offset_x;
-	gfx_coord_t offset_y;
-	int16_t error;
-
-	/* Draw only a pixel if radius is zero. */
-	if (radius == 0) {
-		gfx_mono_draw_pixel(x, y, color);
-		return;
-	}
-
-	/* Set up start iterators. */
-	offset_x = 0;
-	offset_y = radius;
-	error = 3 - 2 * radius;
-
-	/* Iterate offsetX from 0 to radius. */
-	while (offset_x <= offset_y) {
-		/* Draw one pixel for each octant enabled in octant_mask. */
-		if (octant_mask & GFX_OCTANT0) {
-			gfx_mono_draw_pixel(x + offset_y, y - offset_x, color);
-		}
-
-		if (octant_mask & GFX_OCTANT1) {
-			gfx_mono_draw_pixel(x + offset_x, y - offset_y, color);
-		}
-
-		if (octant_mask & GFX_OCTANT2) {
-			gfx_mono_draw_pixel(x - offset_x, y - offset_y, color);
-		}
-
-		if (octant_mask & GFX_OCTANT3) {
-			gfx_mono_draw_pixel(x - offset_y, y - offset_x, color);
-		}
-
-		if (octant_mask & GFX_OCTANT4) {
-			gfx_mono_draw_pixel(x - offset_y, y + offset_x, color);
-		}
-
-		if (octant_mask & GFX_OCTANT5) {
-			gfx_mono_draw_pixel(x - offset_x, y + offset_y, color);
-		}
-
-		if (octant_mask & GFX_OCTANT6) {
-			gfx_mono_draw_pixel(x + offset_x, y + offset_y, color);
-		}
-
-		if (octant_mask & GFX_OCTANT7) {
-			gfx_mono_draw_pixel(x + offset_y, y + offset_x, color);
-		}
-
-		/* Update error value and step offset_y when required. */
-		if (error < 0) {
-			error += ((offset_x << 2) + 6);
-		} else {
-			error += (((offset_x - offset_y) << 2) + 10);
-			--offset_y;
-		}
-
-		/* Next X. */
-		++offset_x;
-	}
+    gfx_coord_t offset_x;
+    gfx_coord_t offset_y;
+    int16_t error;
+
+    /* Draw only a pixel if radius is zero. */
+    if (radius == 0)
+    {
+        gfx_mono_draw_pixel(x, y, color);
+        return;
+    }
+
+    /* Set up start iterators. */
+    offset_x = 0;
+    offset_y = radius;
+    error = 3 - 2 * radius;
+
+    /* Iterate offsetX from 0 to radius. */
+    while (offset_x <= offset_y)
+    {
+        /* Draw one pixel for each octant enabled in octant_mask. */
+        if (octant_mask & GFX_OCTANT0)
+        {
+            gfx_mono_draw_pixel(x + offset_y, y - offset_x, color);
+        }
+
+        if (octant_mask & GFX_OCTANT1)
+        {
+            gfx_mono_draw_pixel(x + offset_x, y - offset_y, color);
+        }
+
+        if (octant_mask & GFX_OCTANT2)
+        {
+            gfx_mono_draw_pixel(x - offset_x, y - offset_y, color);
+        }
+
+        if (octant_mask & GFX_OCTANT3)
+        {
+            gfx_mono_draw_pixel(x - offset_y, y - offset_x, color);
+        }
+
+        if (octant_mask & GFX_OCTANT4)
+        {
+            gfx_mono_draw_pixel(x - offset_y, y + offset_x, color);
+        }
+
+        if (octant_mask & GFX_OCTANT5)
+        {
+            gfx_mono_draw_pixel(x - offset_x, y + offset_y, color);
+        }
+
+        if (octant_mask & GFX_OCTANT6)
+        {
+            gfx_mono_draw_pixel(x + offset_x, y + offset_y, color);
+        }
+
+        if (octant_mask & GFX_OCTANT7)
+        {
+            gfx_mono_draw_pixel(x + offset_y, y + offset_x, color);
+        }
+
+        /* Update error value and step offset_y when required. */
+        if (error < 0)
+        {
+            error += ((offset_x << 2) + 6);
+        } else {
+            error += (((offset_x - offset_y) << 2) + 10);
+            --offset_y;
+        }
+
+        /* Next X. */
+        ++offset_x;
+    }
 }
 
 /**
@@ -398,66 +430,73 @@ void gfx_mono_generic_draw_circle(gfx_coord_t x, gfx_coord_t y,
  * \param[in]  quadrant_mask Bitmask indicating which quadrants to draw.
  */
 void gfx_mono_generic_draw_filled_circle(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t radius, enum gfx_mono_color color,
-		uint8_t quadrant_mask)
+        gfx_coord_t radius, enum gfx_mono_color color,
+        uint8_t quadrant_mask)
 {
-	gfx_coord_t offset_x;
-	gfx_coord_t offset_y;
-	int16_t error;
-
-	/* Draw only a pixel if radius is zero. */
-	if (radius == 0) {
-		gfx_mono_draw_pixel(x, y, color);
-		return;
-	}
-
-	/* Set up start iterators. */
-	offset_x = 0;
-	offset_y = radius;
-	error = 3 - 2 * radius;
-
-	/* Iterate offset_x from 0 to radius. */
-	while (offset_x <= offset_y) {
-		/* Draw vertical lines tracking each quadrant. */
-		if (quadrant_mask & GFX_QUADRANT0) {
-			gfx_mono_draw_vertical_line(x + offset_y,
-					y - offset_x, offset_x + 1, color);
-			gfx_mono_draw_vertical_line(x + offset_x,
-					y - offset_y, offset_y + 1, color);
-		}
-
-		if (quadrant_mask & GFX_QUADRANT1) {
-			gfx_mono_draw_vertical_line(x - offset_y,
-					y - offset_x, offset_x + 1, color);
-			gfx_mono_draw_vertical_line(x - offset_x,
-					y - offset_y, offset_y + 1, color);
-		}
-
-		if (quadrant_mask & GFX_QUADRANT2) {
-			gfx_mono_draw_vertical_line(x - offset_y,
-					y, offset_x + 1, color);
-			gfx_mono_draw_vertical_line(x - offset_x,
-					y, offset_y + 1, color);
-		}
-
-		if (quadrant_mask & GFX_QUADRANT3) {
-			gfx_mono_draw_vertical_line(x + offset_y,
-					y, offset_x + 1, color);
-			gfx_mono_draw_vertical_line(x + offset_x,
-					y, offset_y + 1, color);
-		}
-
-		/* Update error value and step offset_y when required. */
-		if (error < 0) {
-			error += ((offset_x << 2) + 6);
-		} else {
-			error += (((offset_x - offset_y) << 2) + 10);
-			--offset_y;
-		}
-
-		/* Next X. */
-		++offset_x;
-	}
+    gfx_coord_t offset_x;
+    gfx_coord_t offset_y;
+    int16_t error;
+
+    /* Draw only a pixel if radius is zero. */
+    if (radius == 0)
+    {
+        gfx_mono_draw_pixel(x, y, color);
+        return;
+    }
+
+    /* Set up start iterators. */
+    offset_x = 0;
+    offset_y = radius;
+    error = 3 - 2 * radius;
+
+    /* Iterate offset_x from 0 to radius. */
+    while (offset_x <= offset_y)
+    {
+        /* Draw vertical lines tracking each quadrant. */
+        if (quadrant_mask & GFX_QUADRANT0)
+        {
+            gfx_mono_draw_vertical_line(x + offset_y,
+                    y - offset_x, offset_x + 1, color);
+            gfx_mono_draw_vertical_line(x + offset_x,
+                    y - offset_y, offset_y + 1, color);
+        }
+
+        if (quadrant_mask & GFX_QUADRANT1)
+        {
+            gfx_mono_draw_vertical_line(x - offset_y,
+                    y - offset_x, offset_x + 1, color);
+            gfx_mono_draw_vertical_line(x - offset_x,
+                    y - offset_y, offset_y + 1, color);
+        }
+
+        if (quadrant_mask & GFX_QUADRANT2)
+        {
+            gfx_mono_draw_vertical_line(x - offset_y,
+                    y, offset_x + 1, color);
+            gfx_mono_draw_vertical_line(x - offset_x,
+                    y, offset_y + 1, color);
+        }
+
+        if (quadrant_mask & GFX_QUADRANT3)
+        {
+            gfx_mono_draw_vertical_line(x + offset_y,
+                    y, offset_x + 1, color);
+            gfx_mono_draw_vertical_line(x + offset_x,
+                    y, offset_y + 1, color);
+        }
+
+        /* Update error value and step offset_y when required. */
+        if (error < 0)
+        {
+            error += ((offset_x << 2) + 6);
+        } else {
+            error += (((offset_x - offset_y) << 2) + 10);
+            --offset_y;
+        }
+
+        /* Next X. */
+        ++offset_x;
+    }
 }
 
 /**
@@ -470,37 +509,41 @@ void gfx_mono_generic_draw_filled_circle(gfx_coord_t x, gfx_coord_t y,
  *
  */
 void gfx_mono_generic_put_bitmap(struct gfx_mono_bitmap *bitmap, gfx_coord_t x,
-		gfx_coord_t y)
+        gfx_coord_t y)
 {
-	gfx_coord_t num_pages = bitmap->height / 8;
-	gfx_coord_t page = y / 8;
-	gfx_coord_t column;
-	gfx_coord_t i;
-	gfx_mono_color_t temp;
-
-	switch (bitmap->type) {
-	case GFX_MONO_BITMAP_PROGMEM:
-		for (i = 0; i < num_pages; i++) {
-			for (column = 0; column < bitmap->width; column++) {
-				temp = PROGMEM_READ_BYTE(bitmap->data.progmem
-						+ (i * bitmap->width)
-						+ column);
-				gfx_mono_put_byte(i + page, column + x, temp);
-			}
-		}
-		break;
-
-	case GFX_MONO_BITMAP_RAM:
-		for (i = 0; i < num_pages; i++) {
-			gfx_mono_put_page(bitmap->data.pixmap
-					+ (i * bitmap->width), page + i, x,
-					bitmap->width);
-		}
-		break;
-
-	default:
-		break;
-	}
+    gfx_coord_t num_pages = bitmap->height / 8;
+    gfx_coord_t page = y / 8;
+    gfx_coord_t column;
+    gfx_coord_t i;
+    gfx_mono_color_t temp;
+
+    switch (bitmap->type)
+    {
+    case GFX_MONO_BITMAP_PROGMEM:
+        for (i = 0; i < num_pages; i++)
+        {
+            for (column = 0; column < bitmap->width; column++)
+            {
+                temp = PROGMEM_READ_BYTE(bitmap->data.progmem
+                        + (i * bitmap->width)
+                        + column);
+                gfx_mono_put_byte(i + page, column + x, temp);
+            }
+        }
+        break;
+
+    case GFX_MONO_BITMAP_RAM:
+        for (i = 0; i < num_pages; i++)
+        {
+            gfx_mono_put_page(bitmap->data.pixmap
+                    + (i * bitmap->width), page + i, x,
+                    bitmap->width);
+        }
+        break;
+
+    default:
+        break;
+    }
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h
index 10ae0b4b55fb..e7555e3626e0 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_generic.h
@@ -78,49 +78,49 @@ extern "C" {
  * \brief Storage structure for bitmap pixel data and metadata
  */
 struct gfx_mono_bitmap {
-	/** Width of bitmap */
-	gfx_coord_t width;
-	/** Height of bitmap */
-	gfx_coord_t height;
-	/** Bitmap type */
-	enum gfx_mono_bitmap_type type;
-	union {
-		/** Pointer to pixels for bitmap stored in RAM */
-		gfx_mono_color_t *pixmap;
-		/** Pointer to pixels for bitmap stored in progmem */
-		gfx_mono_color_t PROGMEM_T *progmem;
-	}
-	data;
+    /** Width of bitmap */
+    gfx_coord_t width;
+    /** Height of bitmap */
+    gfx_coord_t height;
+    /** Bitmap type */
+    enum gfx_mono_bitmap_type type;
+    union {
+        /** Pointer to pixels for bitmap stored in RAM */
+        gfx_mono_color_t *pixmap;
+        /** Pointer to pixels for bitmap stored in progmem */
+        gfx_mono_color_t PROGMEM_T *progmem;
+    }
+    data;
 };
 
 void gfx_mono_generic_draw_horizontal_line(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t length, enum gfx_mono_color color);
+        gfx_coord_t length, enum gfx_mono_color color);
 
 void gfx_mono_generic_draw_vertical_line(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t length, enum gfx_mono_color color);
+        gfx_coord_t length, enum gfx_mono_color color);
 
 void gfx_mono_generic_draw_line(gfx_coord_t x1, gfx_coord_t y1,
-		gfx_coord_t x2, gfx_coord_t y2,
-		enum gfx_mono_color color);
+        gfx_coord_t x2, gfx_coord_t y2,
+        enum gfx_mono_color color);
 
 void gfx_mono_generic_draw_rect(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t width, gfx_coord_t height,
-		enum gfx_mono_color color);
+        gfx_coord_t width, gfx_coord_t height,
+        enum gfx_mono_color color);
 
 void gfx_mono_generic_draw_filled_rect(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t width, gfx_coord_t height,
-		enum gfx_mono_color color);
+        gfx_coord_t width, gfx_coord_t height,
+        enum gfx_mono_color color);
 
 void gfx_mono_generic_draw_circle(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t radius, enum gfx_mono_color color,
-		uint8_t octant_mask);
+        gfx_coord_t radius, enum gfx_mono_color color,
+        uint8_t octant_mask);
 
 void gfx_mono_generic_draw_filled_circle(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t radius, enum gfx_mono_color color,
-		uint8_t quadrant_mask);
+        gfx_coord_t radius, enum gfx_mono_color color,
+        uint8_t quadrant_mask);
 
 void gfx_mono_generic_put_bitmap(struct gfx_mono_bitmap *bitmap, gfx_coord_t x,
-		gfx_coord_t y);
+        gfx_coord_t y);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c
index 4d66b7a74cfd..4905b02f96ce 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.c
@@ -53,15 +53,16 @@
  * @{
  */
 
-PROGMEM_DECLARE(gfx_mono_color_t, arrow_right_data[]) = {
-	GFX_MONO_MENU_INDICATOR_BITMAP
+PROGMEM_DECLARE(gfx_mono_color_t, arrow_right_data[])=
+{
+    GFX_MONO_MENU_INDICATOR_BITMAP
 };
 
 struct gfx_mono_bitmap menu_bitmap_indicator = {
-	.height = GFX_MONO_MENU_INDICATOR_HEIGHT,
-	.width = GFX_MONO_MENU_INDICATOR_WIDTH,
-	.type = GFX_MONO_BITMAP_PROGMEM,
-	.data.progmem = arrow_right_data
+    .height = GFX_MONO_MENU_INDICATOR_HEIGHT,
+    .width = GFX_MONO_MENU_INDICATOR_WIDTH,
+    .type = GFX_MONO_BITMAP_PROGMEM,
+    .data.progmem = arrow_right_data
 };
 
 /**
@@ -72,49 +73,52 @@ struct gfx_mono_bitmap menu_bitmap_indicator = {
  */
 static void menu_draw(struct gfx_mono_menu *menu, bool redraw)
 {
-	static bool redraw_state;
-	uint8_t i;
-	uint8_t line = 1;
-	uint8_t menu_page = menu->current_selection /
-			GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
-
-	if (menu->current_page != menu_page || redraw == true) {
-		/* clear screen if we have changed the page or menu and prepare
-		 * redraw */
-		gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
-				GFX_MONO_LCD_WIDTH,
-				GFX_MONO_LCD_HEIGHT - SYSFONT_LINESPACING,
-				GFX_PIXEL_CLR);
-		redraw_state = true;
-	}
-
-	menu->current_page = menu_page;
-
-	/* Clear old indicator icon */
-	gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
-			GFX_MONO_MENU_INDICATOR_WIDTH, GFX_MONO_LCD_HEIGHT -
-			SYSFONT_LINESPACING, GFX_PIXEL_CLR);
-
-	/* Put indicator icon on current selection */
-	gfx_mono_put_bitmap(&menu_bitmap_indicator, 0,
-			SYSFONT_LINESPACING * ((menu->current_selection %
-			GFX_MONO_MENU_ELEMENTS_PER_SCREEN) + 1));
-
-	/* Print visible options if page or menu has changed */
-	if (redraw_state == true) {
-		for (i = menu_page * GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
-				i < menu_page *
-				GFX_MONO_MENU_ELEMENTS_PER_SCREEN +
-				GFX_MONO_MENU_ELEMENTS_PER_SCREEN &&
-				i < menu->num_elements; i++) {
-			gfx_mono_draw_progmem_string(
-					(char PROGMEM_PTR_T)menu->strings[i],
-					GFX_MONO_MENU_INDICATOR_WIDTH + 1,
-					line * SYSFONT_LINESPACING, &sysfont);
-			line++;
-		}
-		redraw_state = false;
-	}
+    static bool redraw_state;
+    uint8_t i;
+    uint8_t line = 1;
+    uint8_t menu_page = menu->current_selection /
+            GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
+
+    if (menu->current_page != menu_page || redraw == true)
+    {
+        /* clear screen if we have changed the page or menu and prepare
+         * redraw */
+        gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
+                GFX_MONO_LCD_WIDTH,
+                GFX_MONO_LCD_HEIGHT - SYSFONT_LINESPACING,
+                GFX_PIXEL_CLR);
+        redraw_state = true;
+    }
+
+    menu->current_page = menu_page;
+
+    /* Clear old indicator icon */
+    gfx_mono_draw_filled_rect(0, SYSFONT_LINESPACING,
+            GFX_MONO_MENU_INDICATOR_WIDTH, GFX_MONO_LCD_HEIGHT -
+            SYSFONT_LINESPACING, GFX_PIXEL_CLR);
+
+    /* Put indicator icon on current selection */
+    gfx_mono_put_bitmap(&menu_bitmap_indicator, 0,
+            SYSFONT_LINESPACING * ((menu->current_selection %
+            GFX_MONO_MENU_ELEMENTS_PER_SCREEN) + 1));
+
+    /* Print visible options if page or menu has changed */
+    if (redraw_state == true)
+    {
+        for (i = menu_page * GFX_MONO_MENU_ELEMENTS_PER_SCREEN;
+                i < menu_page *
+                GFX_MONO_MENU_ELEMENTS_PER_SCREEN +
+                GFX_MONO_MENU_ELEMENTS_PER_SCREEN &&
+                i < menu->num_elements; i++)
+                {
+            gfx_mono_draw_progmem_string(
+                    (char PROGMEM_PTR_T)menu->strings[i],
+                    GFX_MONO_MENU_INDICATOR_WIDTH + 1,
+                    line * SYSFONT_LINESPACING, &sysfont);
+            line++;
+        }
+        redraw_state = false;
+    }
 }
 
 /**
@@ -125,16 +129,16 @@ static void menu_draw(struct gfx_mono_menu *menu, bool redraw)
  */
 void gfx_mono_menu_init(struct gfx_mono_menu *menu)
 {
-	/* Clear screen */
-	gfx_mono_draw_filled_rect(0, 0,
-			GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT, GFX_PIXEL_CLR);
+    /* Clear screen */
+    gfx_mono_draw_filled_rect(0, 0,
+            GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT, GFX_PIXEL_CLR);
 
-	/* Draw the menu title on the top of the screen */
-	gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)menu->title,
-			0, 0, &sysfont);
+    /* Draw the menu title on the top of the screen */
+    gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)menu->title,
+            0, 0, &sysfont);
 
-	/* Draw menu options below */
-	menu_draw(menu, true);
+    /* Draw menu options below */
+    menu_draw(menu, true);
 }
 
 /**
@@ -147,41 +151,44 @@ void gfx_mono_menu_init(struct gfx_mono_menu *menu)
  */
 uint8_t gfx_mono_menu_process_key(struct gfx_mono_menu *menu, uint8_t keycode)
 {
-	switch (keycode) {
-	case GFX_MONO_MENU_KEYCODE_DOWN:
-		if (menu->current_selection == menu->num_elements - 1) {
-			menu->current_selection = 0;
-		} else {
-			menu->current_selection++;
-		}
-
-		/* Update menu on display */
-		menu_draw(menu, false);
-		/* Nothing selected yet */
-		return GFX_MONO_MENU_EVENT_IDLE;
-
-	case GFX_MONO_MENU_KEYCODE_UP:
-		if (menu->current_selection) {
-			menu->current_selection--;
-		} else {
-			menu->current_selection = menu->num_elements - 1;
-		}
-
-		/* Update menu on display */
-		menu_draw(menu, false);
-		/* Nothing selected yet */
-		return GFX_MONO_MENU_EVENT_IDLE;
-
-	case GFX_MONO_MENU_KEYCODE_ENTER:
-		/* Got what we want. Return selection. */
-		return menu->current_selection;
-
-	case GFX_MONO_MENU_KEYCODE_BACK:
-		/* User pressed "back" key, inform user */
-		return GFX_MONO_MENU_EVENT_EXIT;
-
-	default:
-		/* Unknown key event */
-		return GFX_MONO_MENU_EVENT_IDLE;
-	}
+    switch (keycode)
+    {
+    case GFX_MONO_MENU_KEYCODE_DOWN:
+        if (menu->current_selection == menu->num_elements - 1)
+        {
+            menu->current_selection = 0;
+        } else {
+            menu->current_selection++;
+        }
+
+        /* Update menu on display */
+        menu_draw(menu, false);
+        /* Nothing selected yet */
+        return GFX_MONO_MENU_EVENT_IDLE;
+
+    case GFX_MONO_MENU_KEYCODE_UP:
+        if (menu->current_selection)
+        {
+            menu->current_selection--;
+        } else {
+            menu->current_selection = menu->num_elements - 1;
+        }
+
+        /* Update menu on display */
+        menu_draw(menu, false);
+        /* Nothing selected yet */
+        return GFX_MONO_MENU_EVENT_IDLE;
+
+    case GFX_MONO_MENU_KEYCODE_ENTER:
+        /* Got what we want. Return selection. */
+        return menu->current_selection;
+
+    case GFX_MONO_MENU_KEYCODE_BACK:
+        /* User pressed "back" key, inform user */
+        return GFX_MONO_MENU_EVENT_EXIT;
+
+    default:
+        /* Unknown key event */
+        return GFX_MONO_MENU_EVENT_IDLE;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h
index 6b88051de36c..6f1ba2d2cb6a 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_menu.h
@@ -113,15 +113,15 @@ extern "C" {
 
 /** Maximum number of menu elements on display */
 #define GFX_MONO_MENU_ELEMENTS_PER_SCREEN ((GFX_MONO_LCD_HEIGHT / \
-	SYSFONT_LINESPACING) - 1)
+    SYSFONT_LINESPACING) - 1)
 
 /** Menu struct */
 struct gfx_mono_menu {
-	PROGMEM_STRING_T title;
-	PROGMEM_STRING_T *strings;
-	uint8_t num_elements;
-	uint8_t current_selection;
-	uint8_t current_page;
+    PROGMEM_STRING_T title;
+    PROGMEM_STRING_T *strings;
+    uint8_t num_elements;
+    uint8_t current_selection;
+    uint8_t current_page;
 };
 
 void gfx_mono_menu_init(struct gfx_mono_menu *menu);
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c
index bf291a4ef16f..3dd6edc9e31d 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.c
@@ -58,7 +58,7 @@ static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
  */
 void gfx_mono_null_init(void)
 {
-	gfx_mono_set_framebuffer(framebuffer);
+    gfx_mono_set_framebuffer(framebuffer);
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h
index e799f252152e..1e9641d4e50c 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_null.h
@@ -69,63 +69,63 @@ extern "C" {
 #define GFX_MONO_LCD_HEIGHT             32
 #define GFX_MONO_LCD_PIXELS_PER_BYTE    8
 #define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
-	GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_PIXELS_PER_BYTE)
 #define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
-	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
 
 #define gfx_mono_draw_horizontal_line(x, y, length, color) \
-	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+    gfx_mono_generic_draw_horizontal_line(x, y, length, color)
 
 #define gfx_mono_draw_vertical_line(x, y, length, color) \
-	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+    gfx_mono_generic_draw_vertical_line(x, y, length, color)
 
 #define gfx_mono_draw_line(x1, y1, x2, y2, color) \
-	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+    gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
 
 #define gfx_mono_draw_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_rect(x, y, width, height, color)
+    gfx_mono_generic_draw_rect(x, y, width, height, color)
 
 #define gfx_mono_draw_filled_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
-		color)
+    gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+        color)
 
 #define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
-	gfx_mono_generic_draw_circle(x, y, radius, color, \
-		octant_mask)
+    gfx_mono_generic_draw_circle(x, y, radius, color, \
+        octant_mask)
 
-#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
-	gfx_mono_generic_draw_filled_circle(x, y, radius, \
-		color, quadrant_mask)
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask) \
+    gfx_mono_generic_draw_filled_circle(x, y, radius, \
+        color, quadrant_mask)
 
 #define gfx_mono_put_bitmap(bitmap, x, y) \
-	gfx_mono_generic_put_bitmap(bitmap, x, y)
+    gfx_mono_generic_put_bitmap(bitmap, x, y)
 
 #define gfx_mono_draw_pixel(x, y, color) \
-	gfx_mono_framebuffer_draw_pixel(x, y, color)
+    gfx_mono_framebuffer_draw_pixel(x, y, color)
 
 #define gfx_mono_get_pixel(x, y) \
-	gfx_mono_framebuffer_get_pixel(x, y)
+    gfx_mono_framebuffer_get_pixel(x, y)
 
-#define gfx_mono_init()	\
-	gfx_mono_null_init()
+#define gfx_mono_init() \
+    gfx_mono_null_init()
 
 #define gfx_mono_put_page(data, page, column, width) \
-	gfx_mono_framebuffer_put_page(data, page, column, width)
+    gfx_mono_framebuffer_put_page(data, page, column, width)
 
 #define gfx_mono_get_page(data, page, column, width) \
-	gfx_mono_framebuffer_get_page(data, page, column, width)
+    gfx_mono_framebuffer_get_page(data, page, column, width)
 
 #define gfx_mono_put_byte(page, column, data) \
-	gfx_mono_framebuffer_put_byte(page, column, data)
+    gfx_mono_framebuffer_put_byte(page, column, data)
 
-#define gfx_mono_get_byte(page, column)	\
-	gfx_mono_framebuffer_get_byte(page, column)
+#define gfx_mono_get_byte(page, column) \
+    gfx_mono_framebuffer_get_byte(page, column)
 
 #define gfx_mono_mask_byte(page, column, pixel_mask, color) \
-	gfx_mono_framebuffer_mask_byte(page, column, pixel_mask, color)
+    gfx_mono_framebuffer_mask_byte(page, column, pixel_mask, color)
 
 #define gfx_mono_put_framebuffer() \
-	;
+    ;
 
 void gfx_mono_null_init(void);
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h
index 677fb2a8fa68..7bc28771a2e4 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_screen_dump.h
@@ -81,10 +81,10 @@ extern "C" {
 #define str(s) # s
 
 #define _XPM_HEADER(w, h) "/* XPM */\r\n" \
-	"static char * asf_screen_dump[] = {\r\n" \
-	"\"" str(w) " " str(h) " 2 1\",\r\n" \
-	"\"   c #FFFFFF\",\r\n"	\
-	"\".  c #000000\",\r\n"
+    "static char * asf_screen_dump[] = {\r\n" \
+    "\"" str(w) " " str(h) " 2 1\",\r\n" \
+    "\"   c #FFFFFF\",\r\n" \
+    "\".  c #000000\",\r\n"
 
 #define XPM_HEADER _XPM_HEADER(GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT)
 
@@ -107,10 +107,10 @@ static const uint8_t xpm_header[] = XPM_HEADER;
  *
  */
 static inline void gfx_mono_screen_dump_init(dump_usart_t *usart,
-		const usart_serial_options_t *options)
+        const usart_serial_options_t *options)
 {
-	dump_usart = usart;
-	usart_serial_init(usart, options);
+    dump_usart = usart;
+    usart_serial_init(usart, options);
 }
 
 /**
@@ -120,33 +120,37 @@ static inline void gfx_mono_screen_dump_init(dump_usart_t *usart,
  */
 static inline void gfx_mono_screen_dump(void)
 {
-	uint8_t page_buffer[GFX_MONO_LCD_WIDTH];
-	/* wait to receive a character on UART before sending */
-	uint8_t dummy;
-	usart_serial_getchar(dump_usart, &dummy);
-
-	/* write the XPM header */
-	usart_serial_write_packet(dump_usart, xpm_header,
-			(sizeof(xpm_header) - 1));
-
-	for (uint8_t page = 0; page < GFX_MONO_LCD_PAGE_COUNT; ++page) {
-		gfx_mono_get_page(page_buffer, page, 0, GFX_MONO_LCD_WIDTH);
-		for (uint8_t row = 0; row < LCD_PAGE_HEIGHT; ++row) {
-			usart_putchar(dump_usart, '"');
-			for (uint16_t column = 0; column < GFX_MONO_LCD_WIDTH;
-					++column) {
-				if ((page_buffer[column] & (0x01 << row)) !=
-						0x00) {
-					usart_putchar(dump_usart, '.');
-				} else {
-					usart_putchar(dump_usart, ' ');
-				}
-			}
-			usart_serial_write_packet(dump_usart,
-					(uint8_t *)"\",\r\n", 4);
-		}
-	}
-	usart_serial_write_packet(dump_usart, (uint8_t *)"};\r\n", 4);
+    uint8_t page_buffer[GFX_MONO_LCD_WIDTH];
+    /* wait to receive a character on UART before sending */
+    uint8_t dummy;
+    usart_serial_getchar(dump_usart, &dummy);
+
+    /* write the XPM header */
+    usart_serial_write_packet(dump_usart, xpm_header,
+            (sizeof(xpm_header) - 1));
+
+    for (uint8_t page = 0; page < GFX_MONO_LCD_PAGE_COUNT; ++page)
+    {
+        gfx_mono_get_page(page_buffer, page, 0, GFX_MONO_LCD_WIDTH);
+        for (uint8_t row = 0; row < LCD_PAGE_HEIGHT; ++row)
+        {
+            usart_putchar(dump_usart, '"');
+            for (uint16_t column = 0; column < GFX_MONO_LCD_WIDTH;
+                    ++column)
+                    {
+                if ((page_buffer[column] & (0x01 << row)) !=
+                        0x00)
+                        {
+                    usart_putchar(dump_usart, '.');
+                } else {
+                    usart_putchar(dump_usart, ' ');
+                }
+            }
+            usart_serial_write_packet(dump_usart,
+                    (uint8_t *)"\",\r\n", 4);
+        }
+    }
+    usart_serial_write_packet(dump_usart, (uint8_t *)"};\r\n", 4);
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c
index 5978f5c5b246..34cbc2cf88e7 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.c
@@ -48,26 +48,28 @@
 #include "gfx_mono.h"
 #include "gfx_mono_spinctrl.h"
 
-PROGMEM_DECLARE(gfx_mono_color_t, spin_indicator_data[]) = {
-	GFX_MONO_SPINCTRL_SPIN_INDICATOR_BITMAP
+PROGMEM_DECLARE(gfx_mono_color_t, spin_indicator_data[])=
+{
+    GFX_MONO_SPINCTRL_SPIN_INDICATOR_BITMAP
 };
 
-PROGMEM_DECLARE(gfx_mono_color_t, indicator_data[]) = {
-	GFX_MONO_SPINCTRL_INDICATOR_BITMAP
+PROGMEM_DECLARE(gfx_mono_color_t, indicator_data[])=
+{
+    GFX_MONO_SPINCTRL_INDICATOR_BITMAP
 };
 
 struct gfx_mono_bitmap gfx_mono_spinctrl_bitmap_spin_indicator = {
-	.height = GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
-	.width = GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-	.type = GFX_MONO_BITMAP_PROGMEM,
-	.data.progmem = spin_indicator_data
+    .height = GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
+    .width = GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+    .type = GFX_MONO_BITMAP_PROGMEM,
+    .data.progmem = spin_indicator_data
 };
 
 struct gfx_mono_bitmap gfx_mono_spinctrl_bitmap_indicator = {
-	.height = GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
-	.width = GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-	.type = GFX_MONO_BITMAP_PROGMEM,
-	.data.progmem = indicator_data
+    .height = GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+    .width = GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+    .type = GFX_MONO_BITMAP_PROGMEM,
+    .data.progmem = indicator_data
 };
 
 /**
@@ -77,17 +79,18 @@ struct gfx_mono_bitmap gfx_mono_spinctrl_bitmap_indicator = {
  * \param[in] draw     true on draw, false on delete
  */
 static void gfx_mono_spinctrl_draw_indicator(struct gfx_mono_spinctrl *spinner,
-		bool draw)
+        bool draw)
 {
-	if (draw) {
-		gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator, 0,
-				spinner->y);
-	} else {
-		gfx_mono_draw_filled_rect(0, spinner->y,
-				GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-				GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
-				GFX_PIXEL_CLR);
-	}
+    if (draw)
+    {
+        gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator, 0,
+                spinner->y);
+    } else {
+        gfx_mono_draw_filled_rect(0, spinner->y,
+                GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+                GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+                GFX_PIXEL_CLR);
+    }
 }
 
 /**
@@ -97,20 +100,21 @@ static void gfx_mono_spinctrl_draw_indicator(struct gfx_mono_spinctrl *spinner,
  * \param[in] draw     true on draw, false on delete
  */
 static void gfx_mono_spinctrl_draw_spin_indicator(struct gfx_mono_spinctrl
-		*spinner, bool draw)
+        *spinner, bool draw)
 {
-	if (draw) {
-		gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_spin_indicator,
-				GFX_MONO_LCD_WIDTH - GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-				spinner->y);
-	} else {
-		gfx_mono_draw_filled_rect(GFX_MONO_LCD_WIDTH -
-				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-				spinner->y,
-				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-				GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
-				GFX_PIXEL_CLR);
-	}
+    if (draw)
+    {
+        gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_spin_indicator,
+                GFX_MONO_LCD_WIDTH - GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+                spinner->y);
+    } else {
+        gfx_mono_draw_filled_rect(GFX_MONO_LCD_WIDTH -
+                GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+                spinner->y,
+                GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+                GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT,
+                GFX_PIXEL_CLR);
+    }
 }
 
 /**
@@ -126,51 +130,53 @@ static void gfx_mono_spinctrl_draw_spin_indicator(struct gfx_mono_spinctrl
  */
 static void gfx_mono_spinctrl_draw_button(bool draw, bool indicator)
 {
-	uint8_t width;
-	uint8_t height;
-	uint8_t offset;
-	char string_buf[22];
-
-	/* Clear bottom line */
-	gfx_mono_draw_filled_rect(0,
-			(SYSFONT_HEIGHT + 1) *
-			GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
-			GFX_MONO_LCD_WIDTH, SYSFONT_HEIGHT, GFX_PIXEL_CLR);
-
-	snprintf(string_buf, sizeof(string_buf), "OK");
-	gfx_mono_get_string_bounding_box(string_buf, &sysfont, &width, &height);
-	offset = (GFX_MONO_LCD_WIDTH - width) / 2;
-
-	if (draw) {
-		/* Draw OK button in the middle of the last line */
-		gfx_mono_draw_string(string_buf, offset,
-				(SYSFONT_HEIGHT + 1) *
-				GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
-				&sysfont);
-		if (indicator) {
-			/* Draw indicator arrow in front of button */
-			gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator,
-					offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-					(SYSFONT_HEIGHT + 1) *
-					GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION);
-		} else {
-			/* Delete indicator */
-			gfx_mono_draw_filled_rect(offset -
-					GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-					(SYSFONT_HEIGHT + 1) *
-					GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
-					GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-					GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
-					GFX_PIXEL_CLR);
-		}
-	} else {
-		/* Delete OK button */
-		gfx_mono_draw_filled_rect(
-				offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
-				(SYSFONT_HEIGHT + 1) *
-				GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION, 20,
-				SYSFONT_HEIGHT, GFX_PIXEL_CLR);
-	}
+    uint8_t width;
+    uint8_t height;
+    uint8_t offset;
+    char string_buf[22];
+
+    /* Clear bottom line */
+    gfx_mono_draw_filled_rect(0,
+            (SYSFONT_HEIGHT + 1) *
+            GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+            GFX_MONO_LCD_WIDTH, SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+
+    snprintf(string_buf, sizeof(string_buf), "OK");
+    gfx_mono_get_string_bounding_box(string_buf, &sysfont, &width, &height);
+    offset = (GFX_MONO_LCD_WIDTH - width) / 2;
+
+    if (draw)
+    {
+        /* Draw OK button in the middle of the last line */
+        gfx_mono_draw_string(string_buf, offset,
+                (SYSFONT_HEIGHT + 1) *
+                GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+                &sysfont);
+        if (indicator)
+        {
+            /* Draw indicator arrow in front of button */
+            gfx_mono_put_bitmap(&gfx_mono_spinctrl_bitmap_indicator,
+                    offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+                    (SYSFONT_HEIGHT + 1) *
+                    GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION);
+        } else {
+            /* Delete indicator */
+            gfx_mono_draw_filled_rect(offset -
+                    GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+                    (SYSFONT_HEIGHT + 1) *
+                    GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION,
+                    GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+                    GFX_MONO_SPINCTRL_INDICATOR_HEIGHT,
+                    GFX_PIXEL_CLR);
+        }
+    } else {
+        /* Delete OK button */
+        gfx_mono_draw_filled_rect(
+                offset - GFX_MONO_SPINCTRL_INDICATOR_WIDTH,
+                (SYSFONT_HEIGHT + 1) *
+                GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION, 20,
+                SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+    }
 }
 
 /**
@@ -186,58 +192,62 @@ static void gfx_mono_spinctrl_draw_button(bool draw, bool indicator)
  */
 void gfx_mono_spinctrl_draw(struct gfx_mono_spinctrl *spinner, bool redraw)
 {
-	char string_buf[GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH];
-	uint8_t index;
-	uint8_t offset;
-
-	if (redraw) {
-		/* Clear line */
-		gfx_mono_draw_filled_rect(0, spinner->y, GFX_MONO_LCD_WIDTH,
-				SYSFONT_HEIGHT, GFX_PIXEL_CLR);
-		/* Draw title */
-		gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)spinner->title,
-				GFX_MONO_SPINCTRL_INDICATOR_WIDTH + 1,
-				spinner->y, &sysfont);
-	}
-
-	if (spinner->in_focus) {
-		gfx_mono_spinctrl_draw_spin_indicator(spinner, true);
-	} else {
-		gfx_mono_spinctrl_draw_spin_indicator(spinner, false);
-	}
-
-	if (spinner->datatype == SPINTYPE_INTEGER) {
-		offset = GFX_MONO_LCD_WIDTH -
-				(SYSFONT_WIDTH *
-				GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH);
-		snprintf(string_buf, sizeof(string_buf), "%d",
-				spinner->integer_data);
-		/* Delete previous spinner data */
-		gfx_mono_draw_filled_rect(offset, spinner->y,
-				GFX_MONO_LCD_WIDTH - offset -
-				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-				SYSFONT_HEIGHT,
-				GFX_PIXEL_CLR);
-		/* Draw integer data */
-		gfx_mono_draw_string(string_buf, offset, spinner->y, &sysfont);
-	} else if (spinner->datatype == SPINTYPE_STRING) {
-		index = spinner->strings.index;
-		offset = GFX_MONO_LCD_WIDTH -
-				(SYSFONT_WIDTH *
-				GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH);
-
-		/* Delete previous spinner data */
-		gfx_mono_draw_filled_rect(offset, spinner->y,
-				GFX_MONO_LCD_WIDTH - offset -
-				GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
-				SYSFONT_HEIGHT,
-				GFX_PIXEL_CLR);
-
-		/* Draw string data */
-		gfx_mono_draw_progmem_string(
-				(char PROGMEM_PTR_T)spinner->strings.data[index], offset,
-				spinner->y, &sysfont);
-	}
+    char string_buf[GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH];
+    uint8_t index;
+    uint8_t offset;
+
+    if (redraw)
+    {
+        /* Clear line */
+        gfx_mono_draw_filled_rect(0, spinner->y, GFX_MONO_LCD_WIDTH,
+                SYSFONT_HEIGHT, GFX_PIXEL_CLR);
+        /* Draw title */
+        gfx_mono_draw_progmem_string((char PROGMEM_PTR_T)spinner->title,
+                GFX_MONO_SPINCTRL_INDICATOR_WIDTH + 1,
+                spinner->y, &sysfont);
+    }
+
+    if (spinner->in_focus)
+    {
+        gfx_mono_spinctrl_draw_spin_indicator(spinner, true);
+    } else {
+        gfx_mono_spinctrl_draw_spin_indicator(spinner, false);
+    }
+
+    if (spinner->datatype == SPINTYPE_INTEGER)
+    {
+        offset = GFX_MONO_LCD_WIDTH -
+                (SYSFONT_WIDTH *
+                GFX_MONO_SPINCTRL_INT_SPINNER_WIDTH);
+        snprintf(string_buf, sizeof(string_buf), "%d",
+                spinner->integer_data);
+        /* Delete previous spinner data */
+        gfx_mono_draw_filled_rect(offset, spinner->y,
+                GFX_MONO_LCD_WIDTH - offset -
+                GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+                SYSFONT_HEIGHT,
+                GFX_PIXEL_CLR);
+        /* Draw integer data */
+        gfx_mono_draw_string(string_buf, offset, spinner->y, &sysfont);
+    } else if (spinner->datatype == SPINTYPE_STRING)
+    {
+        index = spinner->strings.index;
+        offset = GFX_MONO_LCD_WIDTH -
+                (SYSFONT_WIDTH *
+                GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH);
+
+        /* Delete previous spinner data */
+        gfx_mono_draw_filled_rect(offset, spinner->y,
+                GFX_MONO_LCD_WIDTH - offset -
+                GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH,
+                SYSFONT_HEIGHT,
+                GFX_PIXEL_CLR);
+
+        /* Draw string data */
+        gfx_mono_draw_progmem_string(
+                (char PROGMEM_PTR_T)spinner->strings.data[index], offset,
+                spinner->y, &sysfont);
+    }
 }
 
 /**
@@ -266,26 +276,27 @@ void gfx_mono_spinctrl_draw(struct gfx_mono_spinctrl *spinner, bool redraw)
  * \param[in] y            y position of spinner
  */
 void gfx_mono_spinctrl_init(struct gfx_mono_spinctrl *spinner,
-		gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
-		PROGMEM_STRING_T *data, int16_t lower_limit,
-		int16_t upper_limit,
-		gfx_coord_t y)
+        gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
+        PROGMEM_STRING_T *data, int16_t lower_limit,
+        int16_t upper_limit,
+        gfx_coord_t y)
 {
-	/* Initialization of spinner parameters */
-	spinner->title = title;
-	spinner->datatype = datatype;
-	spinner->lower_limit = lower_limit;
-	spinner->upper_limit = upper_limit;
-	spinner->y = y;
-	spinner->in_focus = false;
-	spinner->last_saved_value = spinner->lower_limit;
-
-	if (datatype == SPINTYPE_STRING) {
-		spinner->strings.data = data;
-		spinner->strings.index = lower_limit;
-	} else {
-		spinner->integer_data = lower_limit;
-	}
+    /* Initialization of spinner parameters */
+    spinner->title = title;
+    spinner->datatype = datatype;
+    spinner->lower_limit = lower_limit;
+    spinner->upper_limit = upper_limit;
+    spinner->y = y;
+    spinner->in_focus = false;
+    spinner->last_saved_value = spinner->lower_limit;
+
+    if (datatype == SPINTYPE_STRING)
+    {
+        spinner->strings.data = data;
+        spinner->strings.index = lower_limit;
+    } else {
+        spinner->integer_data = lower_limit;
+    }
 }
 
 /**
@@ -296,12 +307,12 @@ void gfx_mono_spinctrl_init(struct gfx_mono_spinctrl *spinner,
  * \param[out] collection pointer to gfx_mono_spinctrl_spincollection to Initialize
  */
 void gfx_mono_spinctrl_spincollection_init(struct
-		gfx_mono_spinctrl_spincollection *collection)
+        gfx_mono_spinctrl_spincollection *collection)
 {
-	collection->active_spinner = false;
-	collection->current_selection = 0;
-	collection->number_of_spinners = 0;
-	collection->init = true;
+    collection->active_spinner = false;
+    collection->current_selection = 0;
+    collection->number_of_spinners = 0;
+    collection->init = true;
 }
 
 /**
@@ -322,41 +333,44 @@ void gfx_mono_spinctrl_spincollection_init(struct
  *
  */
 void gfx_mono_spinctrl_spincollection_add_spinner(struct
-		gfx_mono_spinctrl *spinner,
-		struct gfx_mono_spinctrl_spincollection *spinners)
+        gfx_mono_spinctrl *spinner,
+        struct gfx_mono_spinctrl_spincollection *spinners)
 {
-	uint8_t i;
-	struct gfx_mono_spinctrl *lastspinner;
-
-	/* Do not add more spinner elements than maximum number of spinners */
-	if (spinners->number_of_spinners >=
-			GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION) {
-		return;
-	}
-
-	/* Place new spinner below previous spinners on screen */
-	spinner->y = (SYSFONT_HEIGHT + 1) * spinners->number_of_spinners;
-
-	/* Add pointer to the spinner in spincollection if empty */
-	if (spinners->number_of_spinners == 0) {
-		spinners->collection = spinner;
-	} else {
-		lastspinner = spinners->collection;
-		for (i = 1; i < spinners->number_of_spinners; i++) {
-			lastspinner = lastspinner->next;
-		}
-		/* Link the new spinner to the current last spinner in the
-		 * collection */
-		lastspinner->next = spinner;
-		/* Link the current last spinner as previous spinner for new
-		 * spinner */
-		spinner->prev = lastspinner;
-	}
-
-	/* Set added spinner as last spinner in collection */
-	spinners->collection_last = spinner;
-	/* Update number of spinners in collection */
-	spinners->number_of_spinners++;
+    uint8_t i;
+    struct gfx_mono_spinctrl *lastspinner;
+
+    /* Do not add more spinner elements than maximum number of spinners */
+    if (spinners->number_of_spinners >=
+            GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION)
+            {
+        return;
+    }
+
+    /* Place new spinner below previous spinners on screen */
+    spinner->y = (SYSFONT_HEIGHT + 1) * spinners->number_of_spinners;
+
+    /* Add pointer to the spinner in spincollection if empty */
+    if (spinners->number_of_spinners == 0)
+    {
+        spinners->collection = spinner;
+    } else {
+        lastspinner = spinners->collection;
+        for (i = 1; i < spinners->number_of_spinners; i++)
+        {
+            lastspinner = lastspinner->next;
+        }
+        /* Link the new spinner to the current last spinner in the
+         * collection */
+        lastspinner->next = spinner;
+        /* Link the current last spinner as previous spinner for new
+         * spinner */
+        spinner->prev = lastspinner;
+    }
+
+    /* Set added spinner as last spinner in collection */
+    spinners->collection_last = spinner;
+    /* Update number of spinners in collection */
+    spinners->number_of_spinners++;
 }
 
 /**
@@ -369,30 +383,32 @@ void gfx_mono_spinctrl_spincollection_add_spinner(struct
  * \param[in] spinners pointer to initialized spincollection to display
  */
 void gfx_mono_spinctrl_spincollection_show(struct
-		gfx_mono_spinctrl_spincollection *spinners)
+        gfx_mono_spinctrl_spincollection *spinners)
 {
-	uint8_t i;
-	struct gfx_mono_spinctrl *iterator;
-
-	/* Clear screen */
-	gfx_mono_draw_filled_rect(0, 0, GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT,
-			GFX_PIXEL_CLR);
-
-	/* Make sure there are spinners in the collection */
-	if (spinners->number_of_spinners == 0) {
-		return;
-	}
-
-	/* Draw spinners on screen */
-	iterator = spinners->collection;
-	for (i = 0; i < spinners->number_of_spinners; i++) {
-		gfx_mono_spinctrl_draw(iterator, true);
-		iterator = iterator->next;
-	}
-	/* Draw OK button at bottom of screen */
-	gfx_mono_spinctrl_draw_button(true, false);
-	/* Draw indicator arrow in front of first spinner */
-	gfx_mono_spinctrl_draw_indicator(spinners->collection, true);
+    uint8_t i;
+    struct gfx_mono_spinctrl *iterator;
+
+    /* Clear screen */
+    gfx_mono_draw_filled_rect(0, 0, GFX_MONO_LCD_WIDTH, GFX_MONO_LCD_HEIGHT,
+            GFX_PIXEL_CLR);
+
+    /* Make sure there are spinners in the collection */
+    if (spinners->number_of_spinners == 0)
+    {
+        return;
+    }
+
+    /* Draw spinners on screen */
+    iterator = spinners->collection;
+    for (i = 0; i < spinners->number_of_spinners; i++)
+    {
+        gfx_mono_spinctrl_draw(iterator, true);
+        iterator = iterator->next;
+    }
+    /* Draw OK button at bottom of screen */
+    gfx_mono_spinctrl_draw_button(true, false);
+    /* Draw indicator arrow in front of first spinner */
+    gfx_mono_spinctrl_draw_indicator(spinners->collection, true);
 }
 
 /**
@@ -405,22 +421,26 @@ void gfx_mono_spinctrl_spincollection_show(struct
  */
 static void gfx_mono_spinctrl_step_up(struct gfx_mono_spinctrl *spinner)
 {
-	/* Check if spinner type is integer or string, increment integer data or
-	 * move to next string index.
-	 */
-	if (spinner->datatype == SPINTYPE_INTEGER) {
-		if (spinner->integer_data < spinner->upper_limit) {
-			spinner->integer_data++;
-		} else {
-			spinner->integer_data = spinner->lower_limit;
-		}
-	} else if (spinner->datatype == SPINTYPE_STRING) {
-		if (spinner->strings.index < spinner->upper_limit) {
-			spinner->strings.index++;
-		} else {
-			(spinner->strings.index) = spinner->lower_limit;
-		}
-	}
+    /* Check if spinner type is integer or string, increment integer data or
+     * move to next string index.
+     */
+    if (spinner->datatype == SPINTYPE_INTEGER)
+    {
+        if (spinner->integer_data < spinner->upper_limit)
+        {
+            spinner->integer_data++;
+        } else {
+            spinner->integer_data = spinner->lower_limit;
+        }
+    } else if (spinner->datatype == SPINTYPE_STRING)
+    {
+        if (spinner->strings.index < spinner->upper_limit)
+        {
+            spinner->strings.index++;
+        } else {
+            (spinner->strings.index) = spinner->lower_limit;
+        }
+    }
 }
 
 /**
@@ -433,22 +453,26 @@ static void gfx_mono_spinctrl_step_up(struct gfx_mono_spinctrl *spinner)
  */
 static void gfx_mono_spinctrl_step_down(struct gfx_mono_spinctrl *spinner)
 {
-	/* Check if spinner type is integer or string, increment integer data,
-	 * move to next string index.
-	 */
-	if (spinner->datatype == SPINTYPE_INTEGER) {
-		if (spinner->integer_data > spinner->lower_limit) {
-			spinner->integer_data--;
-		} else {
-			spinner->integer_data = spinner->upper_limit;
-		}
-	} else if (spinner->datatype == SPINTYPE_STRING) {
-		if (spinner->strings.index > (spinner->lower_limit)) {
-			spinner->strings.index--;
-		} else {
-			spinner->strings.index = spinner->upper_limit;
-		}
-	}
+    /* Check if spinner type is integer or string, increment integer data,
+     * move to next string index.
+     */
+    if (spinner->datatype == SPINTYPE_INTEGER)
+    {
+        if (spinner->integer_data > spinner->lower_limit)
+        {
+            spinner->integer_data--;
+        } else {
+            spinner->integer_data = spinner->upper_limit;
+        }
+    } else if (spinner->datatype == SPINTYPE_STRING)
+    {
+        if (spinner->strings.index > (spinner->lower_limit))
+        {
+            spinner->strings.index--;
+        } else {
+            spinner->strings.index = spinner->upper_limit;
+        }
+    }
 }
 
 /**
@@ -462,74 +486,82 @@ static void gfx_mono_spinctrl_step_down(struct gfx_mono_spinctrl *spinner)
  * \retval GFX_MONO_SPINCTRL_EVENT_BACK spinner deselected
  */
 int16_t gfx_mono_spinctrl_process_key(struct gfx_mono_spinctrl *spinner,
-		uint8_t keycode)
+        uint8_t keycode)
 {
-	switch (keycode) {
-	case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
-		if (spinner->in_focus) {
-			gfx_mono_spinctrl_step_down(spinner);
-			/* Update spinner on display */
-			gfx_mono_spinctrl_draw(spinner, false);
-		}
-
-		/* Nothing selected yet */
-		return GFX_MONO_SPINCTRL_EVENT_IDLE;
-
-	case GFX_MONO_SPINCTRL_KEYCODE_UP:
-		if (spinner->in_focus) {
-			gfx_mono_spinctrl_step_up(spinner);
-			/* Update spinner on display */
-			gfx_mono_spinctrl_draw(spinner, false);
-		}
-
-		/* Nothing selected yet */
-		return GFX_MONO_SPINCTRL_EVENT_IDLE;
-
-	case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
-		if (spinner->in_focus) {
-			if (spinner->datatype == SPINTYPE_INTEGER) {
-				spinner->in_focus = false;
-				gfx_mono_spinctrl_draw(spinner, false);
-				/* Store saved value in case of aborting spinner
-				 * later */
-				spinner->last_saved_value
-					= spinner->integer_data;
-				/* Got what we want. Return selection. */
-				return spinner->integer_data;
-			} else if (spinner->datatype == SPINTYPE_STRING) {
-				spinner->in_focus = false;
-				gfx_mono_spinctrl_draw(spinner, false);
-				/* Store saved value in case of aborting spinner
-				 * later */
-				spinner->last_saved_value
-					= spinner->strings.index;
-				/* Got what we want. Return selection. */
-				return spinner->strings.index;
-			}
-		} else {
-			/* Spinner selected */
-			spinner->in_focus = true;
-			gfx_mono_spinctrl_draw(spinner, false);
-			return GFX_MONO_SPINCTRL_EVENT_IDLE;
-		}
-
-	case GFX_MONO_SPINCTRL_KEYCODE_BACK:
-		/* User pressed "back" key, */
-		spinner->in_focus = false;
-		/* Spinner choice aborted, show last saved value instead */
-		if (spinner->datatype == SPINTYPE_INTEGER) {
-			spinner->integer_data = spinner->last_saved_value;
-		} else if (spinner->datatype == SPINTYPE_STRING) {
-			spinner->strings.index = spinner->last_saved_value;
-		}
-
-		gfx_mono_spinctrl_draw(spinner, false);
-		return GFX_MONO_SPINCTRL_EVENT_BACK;
-
-	default:
-		/* Unknown key event */
-		return GFX_MONO_SPINCTRL_EVENT_IDLE;
-	}
+    switch (keycode)
+    {
+    case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
+        if (spinner->in_focus)
+        {
+            gfx_mono_spinctrl_step_down(spinner);
+            /* Update spinner on display */
+            gfx_mono_spinctrl_draw(spinner, false);
+        }
+
+        /* Nothing selected yet */
+        return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+    case GFX_MONO_SPINCTRL_KEYCODE_UP:
+        if (spinner->in_focus)
+        {
+            gfx_mono_spinctrl_step_up(spinner);
+            /* Update spinner on display */
+            gfx_mono_spinctrl_draw(spinner, false);
+        }
+
+        /* Nothing selected yet */
+        return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+    case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
+        if (spinner->in_focus)
+        {
+            if (spinner->datatype == SPINTYPE_INTEGER)
+            {
+                spinner->in_focus = false;
+                gfx_mono_spinctrl_draw(spinner, false);
+                /* Store saved value in case of aborting spinner
+                 * later */
+                spinner->last_saved_value
+                    = spinner->integer_data;
+                /* Got what we want. Return selection. */
+                return spinner->integer_data;
+            } else if (spinner->datatype == SPINTYPE_STRING)
+            {
+                spinner->in_focus = false;
+                gfx_mono_spinctrl_draw(spinner, false);
+                /* Store saved value in case of aborting spinner
+                 * later */
+                spinner->last_saved_value
+                    = spinner->strings.index;
+                /* Got what we want. Return selection. */
+                return spinner->strings.index;
+            }
+        } else {
+            /* Spinner selected */
+            spinner->in_focus = true;
+            gfx_mono_spinctrl_draw(spinner, false);
+            return GFX_MONO_SPINCTRL_EVENT_IDLE;
+        }
+
+    case GFX_MONO_SPINCTRL_KEYCODE_BACK:
+        /* User pressed "back" key, */
+        spinner->in_focus = false;
+        /* Spinner choice aborted, show last saved value instead */
+        if (spinner->datatype == SPINTYPE_INTEGER)
+        {
+            spinner->integer_data = spinner->last_saved_value;
+        } else if (spinner->datatype == SPINTYPE_STRING)
+        {
+            spinner->strings.index = spinner->last_saved_value;
+        }
+
+        gfx_mono_spinctrl_draw(spinner, false);
+        return GFX_MONO_SPINCTRL_EVENT_BACK;
+
+    default:
+        /* Unknown key event */
+        return GFX_MONO_SPINCTRL_EVENT_IDLE;
+    }
 }
 
 /**
@@ -556,142 +588,157 @@ int16_t gfx_mono_spinctrl_process_key(struct gfx_mono_spinctrl *spinner,
  * \retval GFX_MONO_SPINCTRL_EVENT_IDLE    user is navigating in spincollection
  */
 int16_t gfx_mono_spinctrl_spincollection_process_key(struct
-		gfx_mono_spinctrl_spincollection *spinners, uint8_t keycode,
-		int16_t results[])
+        gfx_mono_spinctrl_spincollection *spinners, uint8_t keycode,
+        int16_t results[])
 {
-	uint8_t i;
-	struct gfx_mono_spinctrl *iterator;
-
-	/* Make sure there are spinners in the collection, if not, cancel */
-	if (spinners->number_of_spinners == 0) {
-		return GFX_MONO_SPINCTRL_EVENT_BACK;
-	}
-
-	/* Store initial values in results array first time function is run */
-	if (spinners->init) {
-		iterator = spinners->collection;
-		for (i = 0; i < spinners->number_of_spinners; i++) {
-			if (iterator->datatype == SPINTYPE_INTEGER) {
-				results[i] = iterator->integer_data;
-			} else {
-				results[i] = iterator->strings.index;
-			}
-
-			iterator = iterator->next;
-		}
-		spinners->init = false;
-	}
-
-	/* Find current spinner selection */
-	iterator = spinners->collection;
-	if (spinners->current_selection != GFX_MONO_SPINCTRL_BUTTON) {
-		for (i = 0; i < spinners->current_selection; i++) {
-			iterator = iterator->next;
-		}
-	}
-
-	if (spinners->active_spinner) {
-		/* Process chosen spinner */
-		spinners->selection = gfx_mono_spinctrl_process_key(iterator,
-				keycode);
-		if (spinners->selection == GFX_MONO_SPINCTRL_EVENT_BACK) {
-			/* User has exited spinner without saving the result */
-			spinners->active_spinner = false;
-		} else if (spinners->selection !=
-				GFX_MONO_SPINCTRL_EVENT_IDLE) {
-			/* Value selected, store in array */
-			results[spinners->current_selection]
-				= spinners->selection;
-			/* Step out of spinner and into spincollection */
-			spinners->active_spinner = false;
-		}
-
-		return GFX_MONO_SPINCTRL_EVENT_IDLE;
-	} else {
-		switch (keycode) {
-		case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
-			if (spinners->current_selection ==
-					GFX_MONO_SPINCTRL_BUTTON) {
-				spinners->current_selection = 0;
-				/* Delete indicator arrow in front of button */
-				gfx_mono_spinctrl_draw_button(true, false);
-				/* Draw indicator arrow in front of first
-				 * spinner */
-				gfx_mono_spinctrl_draw_indicator(iterator,
-						true);
-			} else if (spinners->current_selection <
-					spinners->number_of_spinners - 1) {
-				/* Delete indicator arrow */
-				gfx_mono_spinctrl_draw_indicator(iterator,
-						false);
-				spinners->current_selection++;
-				/* Draw indicator arrow in front of new spinner */
-				gfx_mono_spinctrl_draw_indicator(iterator->next,
-						true);
-			} else {
-				/* Delete indicator arrow */
-				gfx_mono_spinctrl_draw_indicator(iterator,
-						false);
-				spinners->current_selection
-					= GFX_MONO_SPINCTRL_BUTTON;
-				/* Draw indicator arrow in front of button */
-				gfx_mono_spinctrl_draw_button(true, true);
-			}
-
-			return GFX_MONO_SPINCTRL_EVENT_IDLE;
-
-		case GFX_MONO_SPINCTRL_KEYCODE_UP:
-			if (spinners->current_selection ==
-					GFX_MONO_SPINCTRL_BUTTON) {
-				/* Delete indicator arrow in front of button */
-				gfx_mono_spinctrl_draw_button(true, false);
-				spinners->current_selection
-					= spinners->number_of_spinners - 1;
-				/* Draw indicator arrow in front of new spinner */
-				gfx_mono_spinctrl_draw_indicator(
-						spinners->collection_last,
-						true);
-			} else if (spinners->current_selection > 0) {
-				/* Delete indicator arrow */
-				gfx_mono_spinctrl_draw_indicator(iterator,
-						false);
-				spinners->current_selection--;
-				/* Draw indicator arrow in front of new spinner */
-				gfx_mono_spinctrl_draw_indicator(iterator->prev,
-						true);
-			} else {
-				/* Delete indicator arrow */
-				gfx_mono_spinctrl_draw_indicator(iterator,
-						false);
-				spinners->current_selection
-					= GFX_MONO_SPINCTRL_BUTTON;
-				/* Draw indicator arrow in front of button */
-				gfx_mono_spinctrl_draw_button(true, true);
-			}
-
-			return GFX_MONO_SPINCTRL_EVENT_IDLE;
-
-		case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
-			if (spinners->current_selection ==
-					GFX_MONO_SPINCTRL_BUTTON) {
-				/* Finished with all selections, return */
-				return GFX_MONO_SPINCTRL_EVENT_FINISH;
-			} else {
-				/* Spinner selected, send next keycode directly
-				 * to spinner */
-				gfx_mono_spinctrl_process_key(iterator,
-						keycode);
-				spinners->active_spinner = true;
-				return GFX_MONO_SPINCTRL_EVENT_IDLE;
-			}
-
-		case GFX_MONO_SPINCTRL_KEYCODE_BACK:
-			/* User pressed "back" key, */
-			return GFX_MONO_SPINCTRL_EVENT_BACK;
-
-		default:
-			/* Unknown key event */
-			return GFX_MONO_SPINCTRL_EVENT_IDLE;
-		}
-	}
+    uint8_t i;
+    struct gfx_mono_spinctrl *iterator;
+
+    /* Make sure there are spinners in the collection, if not, cancel */
+    if (spinners->number_of_spinners == 0)
+    {
+        return GFX_MONO_SPINCTRL_EVENT_BACK;
+    }
+
+    /* Store initial values in results array first time function is run */
+    if (spinners->init)
+    {
+        iterator = spinners->collection;
+        for (i = 0; i < spinners->number_of_spinners; i++)
+        {
+            if (iterator->datatype == SPINTYPE_INTEGER)
+            {
+                results[i] = iterator->integer_data;
+            } else {
+                results[i] = iterator->strings.index;
+            }
+
+            iterator = iterator->next;
+        }
+        spinners->init = false;
+    }
+
+    /* Find current spinner selection */
+    iterator = spinners->collection;
+    if (spinners->current_selection != GFX_MONO_SPINCTRL_BUTTON)
+    {
+        for (i = 0; i < spinners->current_selection; i++)
+        {
+            iterator = iterator->next;
+        }
+    }
+
+    if (spinners->active_spinner)
+    {
+        /* Process chosen spinner */
+        spinners->selection = gfx_mono_spinctrl_process_key(iterator,
+                keycode);
+        if (spinners->selection == GFX_MONO_SPINCTRL_EVENT_BACK)
+        {
+            /* User has exited spinner without saving the result */
+            spinners->active_spinner = false;
+        } else if (spinners->selection !=
+                GFX_MONO_SPINCTRL_EVENT_IDLE)
+                {
+            /* Value selected, store in array */
+            results[spinners->current_selection]
+                = spinners->selection;
+            /* Step out of spinner and into spincollection */
+            spinners->active_spinner = false;
+        }
+
+        return GFX_MONO_SPINCTRL_EVENT_IDLE;
+    } else {
+        switch (keycode)
+        {
+        case GFX_MONO_SPINCTRL_KEYCODE_DOWN:
+            if (spinners->current_selection ==
+                    GFX_MONO_SPINCTRL_BUTTON)
+                    {
+                spinners->current_selection = 0;
+                /* Delete indicator arrow in front of button */
+                gfx_mono_spinctrl_draw_button(true, false);
+                /* Draw indicator arrow in front of first
+                 * spinner */
+                gfx_mono_spinctrl_draw_indicator(iterator,
+                        true);
+            } else if (spinners->current_selection <
+                    spinners->number_of_spinners - 1)
+                    {
+                /* Delete indicator arrow */
+                gfx_mono_spinctrl_draw_indicator(iterator,
+                        false);
+                spinners->current_selection++;
+                /* Draw indicator arrow in front of new spinner */
+                gfx_mono_spinctrl_draw_indicator(iterator->next,
+                        true);
+            } else {
+                /* Delete indicator arrow */
+                gfx_mono_spinctrl_draw_indicator(iterator,
+                        false);
+                spinners->current_selection
+                    = GFX_MONO_SPINCTRL_BUTTON;
+                /* Draw indicator arrow in front of button */
+                gfx_mono_spinctrl_draw_button(true, true);
+            }
+
+            return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+        case GFX_MONO_SPINCTRL_KEYCODE_UP:
+            if (spinners->current_selection ==
+                    GFX_MONO_SPINCTRL_BUTTON)
+                    {
+                /* Delete indicator arrow in front of button */
+                gfx_mono_spinctrl_draw_button(true, false);
+                spinners->current_selection
+                    = spinners->number_of_spinners - 1;
+                /* Draw indicator arrow in front of new spinner */
+                gfx_mono_spinctrl_draw_indicator(
+                        spinners->collection_last,
+                        true);
+            } else if (spinners->current_selection > 0)
+            {
+                /* Delete indicator arrow */
+                gfx_mono_spinctrl_draw_indicator(iterator,
+                        false);
+                spinners->current_selection--;
+                /* Draw indicator arrow in front of new spinner */
+                gfx_mono_spinctrl_draw_indicator(iterator->prev,
+                        true);
+            } else {
+                /* Delete indicator arrow */
+                gfx_mono_spinctrl_draw_indicator(iterator,
+                        false);
+                spinners->current_selection
+                    = GFX_MONO_SPINCTRL_BUTTON;
+                /* Draw indicator arrow in front of button */
+                gfx_mono_spinctrl_draw_button(true, true);
+            }
+
+            return GFX_MONO_SPINCTRL_EVENT_IDLE;
+
+        case GFX_MONO_SPINCTRL_KEYCODE_ENTER:
+            if (spinners->current_selection ==
+                    GFX_MONO_SPINCTRL_BUTTON)
+                    {
+                /* Finished with all selections, return */
+                return GFX_MONO_SPINCTRL_EVENT_FINISH;
+            } else {
+                /* Spinner selected, send next keycode directly
+                 * to spinner */
+                gfx_mono_spinctrl_process_key(iterator,
+                        keycode);
+                spinners->active_spinner = true;
+                return GFX_MONO_SPINCTRL_EVENT_IDLE;
+            }
+
+        case GFX_MONO_SPINCTRL_KEYCODE_BACK:
+            /* User pressed "back" key, */
+            return GFX_MONO_SPINCTRL_EVENT_BACK;
+
+        default:
+            /* Unknown key event */
+            return GFX_MONO_SPINCTRL_EVENT_IDLE;
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h
index 968222334aa9..4452d78c904e 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_spinctrl.h
@@ -135,14 +135,14 @@ extern "C" {
 
 /** Maximum number of spinner elements on display */
 #define GFX_MONO_SPINCTRL_ELEMENTS_PER_SCREEN \
-	((GFX_MONO_LCD_HEIGHT / SYSFONT_LINESPACING) - 1)
+    ((GFX_MONO_LCD_HEIGHT / SYSFONT_LINESPACING) - 1)
 
 /**
  * Maximum numbers of spinner elements in a spincollection - limited to
  * one screen.
  */
 #define GFX_MONO_SPINCTRL_MAX_ELEMENTS_IN_SPINCOLLECTION \
-	GFX_MONO_SPINCTRL_ELEMENTS_PER_SCREEN
+    GFX_MONO_SPINCTRL_ELEMENTS_PER_SCREEN
 
 /** Width of string spinner choices */
 #define GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH 9
@@ -151,92 +151,92 @@ extern "C" {
 
 /** Enum to specify what kind of data spinner should spin */
 typedef enum gfx_mono_spinctrl_type_enum {
-	SPINTYPE_STRING,
-	SPINTYPE_INTEGER
+    SPINTYPE_STRING,
+    SPINTYPE_INTEGER
 } gfx_mono_spinctrl_type_t;
 
 /** String struct */
 struct gfx_mono_spinctrl_string {
-	/** Pointer to progmem strings to spin through
-	 * \note Each string must be shorter than
-	 * \ref  GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH characters.
-	 * If not, printing it to the screen will corrupt the spinner
-	 * appearance.
-	 */
-	PROGMEM_STRING_T *data;
-	/** Index in string array */
-	uint8_t index;
+    /** Pointer to progmem strings to spin through
+     * \note Each string must be shorter than
+     * \ref  GFX_MONO_SPINCTRL_STRING_SPINNER_WIDTH characters.
+     * If not, printing it to the screen will corrupt the spinner
+     * appearance.
+     */
+    PROGMEM_STRING_T *data;
+    /** Index in string array */
+    uint8_t index;
 };
 
 /** Spin control struct */
 struct gfx_mono_spinctrl {
-	/** Spinner title */
-	PROGMEM_STRING_T title;
-	/** Type of data to spin */
-	gfx_mono_spinctrl_type_t datatype;
-	/** Spinner data, depends on spinner datatype. */
-	union {
-		/** Spinner strings and index */
-		struct gfx_mono_spinctrl_string strings;
-		/** Spinner integer data */
-		int16_t integer_data;
-	};
-	/** Variable to store the last selected spinner value */
-	uint16_t last_saved_value;
-
-	/**
-	 * Lower limit for spinning, must be positive and fit in uin8_t for
-	 * spinner type SPINTYPE_STRING
-	 */
-	int16_t lower_limit;
-
-	/**
-	 * Upper limit for spinning, must be positive and fit in uin8_t for
-	 * spinner type SPINTYPE_STRING
-	 */
-	int16_t upper_limit;
-	/** Y coordinate for placement of spinner on screen */
-	gfx_coord_t y;
-	/** Boolean to tell if spinner is in focus or not */
-	bool in_focus;
-	/** Pointer to next spinner in a spincollection */
-	struct gfx_mono_spinctrl *next;
-	/** Pointer to previous spinner in a spincollection */
-	struct gfx_mono_spinctrl *prev;
+    /** Spinner title */
+    PROGMEM_STRING_T title;
+    /** Type of data to spin */
+    gfx_mono_spinctrl_type_t datatype;
+    /** Spinner data, depends on spinner datatype. */
+    union {
+        /** Spinner strings and index */
+        struct gfx_mono_spinctrl_string strings;
+        /** Spinner integer data */
+        int16_t integer_data;
+    };
+    /** Variable to store the last selected spinner value */
+    uint16_t last_saved_value;
+
+    /**
+     * Lower limit for spinning, must be positive and fit in uin8_t for
+     * spinner type SPINTYPE_STRING
+     */
+    int16_t lower_limit;
+
+    /**
+     * Upper limit for spinning, must be positive and fit in uin8_t for
+     * spinner type SPINTYPE_STRING
+     */
+    int16_t upper_limit;
+    /** Y coordinate for placement of spinner on screen */
+    gfx_coord_t y;
+    /** Boolean to tell if spinner is in focus or not */
+    bool in_focus;
+    /** Pointer to next spinner in a spincollection */
+    struct gfx_mono_spinctrl *next;
+    /** Pointer to previous spinner in a spincollection */
+    struct gfx_mono_spinctrl *prev;
 };
 
 /** Collection of spinners struct */
 struct gfx_mono_spinctrl_spincollection {
-	/** Pointer to the first spinner in the collection */
-	struct gfx_mono_spinctrl *collection;
-	/** Pointer to the last spinner in the collection */
-	struct gfx_mono_spinctrl *collection_last;
-	/** Number of spinners in collection */
-	uint8_t number_of_spinners;
-	/** Current spinner/button */
-	uint8_t current_selection;
-	/** Return value from selected spinner */
-	uint16_t selection;
-	/** Boolean to tell if input should be sent directly to a spinner */
-	bool active_spinner;
-	/** Boolean to initialize results array when starting key processing */
-	bool init;
+    /** Pointer to the first spinner in the collection */
+    struct gfx_mono_spinctrl *collection;
+    /** Pointer to the last spinner in the collection */
+    struct gfx_mono_spinctrl *collection_last;
+    /** Number of spinners in collection */
+    uint8_t number_of_spinners;
+    /** Current spinner/button */
+    uint8_t current_selection;
+    /** Return value from selected spinner */
+    uint16_t selection;
+    /** Boolean to tell if input should be sent directly to a spinner */
+    bool active_spinner;
+    /** Boolean to initialize results array when starting key processing */
+    bool init;
 };
 
 void gfx_mono_spinctrl_init(struct gfx_mono_spinctrl *spinner,
-		gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
-		PROGMEM_STRING_T *data, int16_t lower_limit,
-		int16_t upper_limit,
-		gfx_coord_t y);
+        gfx_mono_spinctrl_type_t datatype, PROGMEM_STRING_T title,
+        PROGMEM_STRING_T *data, int16_t lower_limit,
+        int16_t upper_limit,
+        gfx_coord_t y);
 void gfx_mono_spinctrl_draw(struct gfx_mono_spinctrl *spinner, bool redraw);
 void gfx_mono_spinctrl_spincollection_init(struct
-		gfx_mono_spinctrl_spincollection *collection);
+        gfx_mono_spinctrl_spincollection *collection);
 void gfx_mono_spinctrl_spincollection_add_spinner(struct gfx_mono_spinctrl
-		*spinner, struct gfx_mono_spinctrl_spincollection *spinners);
+        *spinner, struct gfx_mono_spinctrl_spincollection *spinners);
 void gfx_mono_spinctrl_spincollection_show(struct
-		gfx_mono_spinctrl_spincollection *spinners);
+        gfx_mono_spinctrl_spincollection *spinners);
 int16_t gfx_mono_spinctrl_process_key(struct gfx_mono_spinctrl *spinner,
-		uint8_t keycode);
+        uint8_t keycode);
 
 int16_t gfx_mono_spinctrl_spincollection_process_key(struct
 gfx_mono_spinctrl_spincollection *spinners, uint8_t keycode,
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c
index 2fa02379e8ce..99d1d603e496 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.c
@@ -77,70 +77,75 @@
  * \param[in] font     Font to draw character in
  */
 static void gfx_mono_draw_char_hugemem(const char ch, const gfx_coord_t x,
-		const gfx_coord_t y, const struct font *font)
+        const gfx_coord_t y, const struct font *font)
 {
-	uint8_t i;
-	uint8_t char_row_size;
-	uint8_t glyph_size;
-	uint16_t glyph_data_offset;
-	uint8_t char_buff[EXTMEM_BUF_SIZE];
-	uint8_t buffer_pos;
-	uint8_t rows_left;
-
-	/* Sanity check on parameters, assert if font is NULL. */
-	Assert(font != NULL);
-
-	gfx_coord_t inc_x = x;
-	gfx_coord_t inc_y = y;
-
-	char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
-	if (font->width % CONFIG_FONT_PIXELS_PER_BYTE) {
-		char_row_size++;
-	}
-
-	glyph_size = char_row_size * font->height;
-	glyph_data_offset = glyph_size * ((uint8_t)ch - font->first_char);
-	buffer_pos = EXTMEM_BUF_SIZE;
-	rows_left = font->height;
-
-	do {
-		static uint8_t glyph_byte = 0;
-		uint8_t pixelsToDraw = font->width;
-
-		for (i = 0; i < pixelsToDraw; i++) {
-			if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0) {
-				/* Read another byte from hugemem */
-				if (buffer_pos >= EXTMEM_BUF_SIZE) {
-					hugemem_ptr_t source
-						= font->data.hugemem;
-					source = (hugemem_ptr_t)
-							((uint32_t)source +
-							glyph_data_offset);
-
-					hugemem_read_block(char_buff, source,
-							EXTMEM_BUF_SIZE);
-
-					glyph_data_offset += EXTMEM_BUF_SIZE;
-					buffer_pos = 0;
-				}
-
-				glyph_byte = char_buff[buffer_pos];
-				buffer_pos++;
-			}
-
-			/* Draw bit of glyph to screen */
-			if ((glyph_byte & 0x80)) {
-				gfx_mono_draw_pixel(inc_x, inc_y,
-						GFX_PIXEL_SET);
-			}
-
-			inc_x += 1;
-			glyph_byte <<= 1;
-		}
-
-		inc_y += 1;
-		inc_x = x;
-	} while (--rows_left > 0);
+    uint8_t i;
+    uint8_t char_row_size;
+    uint8_t glyph_size;
+    uint16_t glyph_data_offset;
+    uint8_t char_buff[EXTMEM_BUF_SIZE];
+    uint8_t buffer_pos;
+    uint8_t rows_left;
+
+    /* Sanity check on parameters, assert if font is NULL. */
+    Assert(font != NULL);
+
+    gfx_coord_t inc_x = x;
+    gfx_coord_t inc_y = y;
+
+    char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
+    if (font->width % CONFIG_FONT_PIXELS_PER_BYTE)
+    {
+        char_row_size++;
+    }
+
+    glyph_size = char_row_size * font->height;
+    glyph_data_offset = glyph_size * ((uint8_t)ch - font->first_char);
+    buffer_pos = EXTMEM_BUF_SIZE;
+    rows_left = font->height;
+
+    do {
+        static uint8_t glyph_byte = 0;
+        uint8_t pixelsToDraw = font->width;
+
+        for (i = 0; i < pixelsToDraw; i++)
+        {
+            if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0)
+            {
+                /* Read another byte from hugemem */
+                if (buffer_pos >= EXTMEM_BUF_SIZE)
+                {
+                    hugemem_ptr_t source
+                        = font->data.hugemem;
+                    source = (hugemem_ptr_t)
+                            ((uint32_t)source +
+                            glyph_data_offset);
+
+                    hugemem_read_block(char_buff, source,
+                            EXTMEM_BUF_SIZE);
+
+                    glyph_data_offset += EXTMEM_BUF_SIZE;
+                    buffer_pos = 0;
+                }
+
+                glyph_byte = char_buff[buffer_pos];
+                buffer_pos++;
+            }
+
+            /* Draw bit of glyph to screen */
+            if ((glyph_byte & 0x80))
+            {
+                gfx_mono_draw_pixel(inc_x, inc_y,
+                        GFX_PIXEL_SET);
+            }
+
+            inc_x += 1;
+            glyph_byte <<= 1;
+        }
+
+        inc_y += 1;
+        inc_x = x;
+    } while (--rows_left > 0);
 }
 
 #endif
@@ -164,53 +169,57 @@ static void gfx_mono_draw_char_hugemem(const char ch, const gfx_coord_t x,
  * \param[in] font     Font to draw character in
  */
 static void gfx_mono_draw_char_progmem(const char ch, const gfx_coord_t x,
-		const gfx_coord_t y, const struct font *font)
+        const gfx_coord_t y, const struct font *font)
 {
-	uint8_t PROGMEM_PTR_T glyph_data;
-	uint16_t glyph_data_offset;
-	uint8_t char_row_size;
-	uint8_t rows_left;
-	uint8_t i;
-
-	/* Sanity check on parameters, assert if font is NULL. */
-	Assert(font != NULL);
-
-	gfx_coord_t inc_x = x;
-	gfx_coord_t inc_y = y;
-
-	char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
-	if (font->width % CONFIG_FONT_PIXELS_PER_BYTE) {
-		char_row_size++;
-	}
-
-	glyph_data_offset = char_row_size * font->height *
-			((uint8_t)ch - font->first_char);
-	glyph_data = font->data.progmem + glyph_data_offset;
-	rows_left = font->height;
-
-	do {
-		uint8_t glyph_byte = 0;
-		uint8_t pixelsToDraw = font->width;
-
-		for (i = 0; i < pixelsToDraw; i++) {
-			if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0) {
-				glyph_byte = PROGMEM_READ_BYTE(glyph_data);
-				glyph_data++;
-			}
-
-			if ((glyph_byte & 0x80)) {
-				gfx_mono_draw_pixel(inc_x, inc_y,
-						GFX_PIXEL_SET);
-			}
-
-			inc_x += 1;
-			glyph_byte <<= 1;
-		}
-
-		inc_y += 1;
-		inc_x = x;
-		rows_left--;
-	} while (rows_left > 0);
+    uint8_t PROGMEM_PTR_T glyph_data;
+    uint16_t glyph_data_offset;
+    uint8_t char_row_size;
+    uint8_t rows_left;
+    uint8_t i;
+
+    /* Sanity check on parameters, assert if font is NULL. */
+    Assert(font != NULL);
+
+    gfx_coord_t inc_x = x;
+    gfx_coord_t inc_y = y;
+
+    char_row_size = font->width / CONFIG_FONT_PIXELS_PER_BYTE;
+    if (font->width % CONFIG_FONT_PIXELS_PER_BYTE)
+    {
+        char_row_size++;
+    }
+
+    glyph_data_offset = char_row_size * font->height *
+            ((uint8_t)ch - font->first_char);
+    glyph_data = font->data.progmem + glyph_data_offset;
+    rows_left = font->height;
+
+    do {
+        uint8_t glyph_byte = 0;
+        uint8_t pixelsToDraw = font->width;
+
+        for (i = 0; i < pixelsToDraw; i++)
+        {
+            if (i % CONFIG_FONT_PIXELS_PER_BYTE == 0)
+            {
+                glyph_byte = PROGMEM_READ_BYTE(glyph_data);
+                glyph_data++;
+            }
+
+            if ((glyph_byte & 0x80))
+            {
+                gfx_mono_draw_pixel(inc_x, inc_y,
+                        GFX_PIXEL_SET);
+            }
+
+            inc_x += 1;
+            glyph_byte <<= 1;
+        }
+
+        inc_y += 1;
+        inc_x = x;
+        rows_left--;
+    } while (rows_left > 0);
 }
 
 /**
@@ -222,27 +231,28 @@ static void gfx_mono_draw_char_progmem(const char ch, const gfx_coord_t x,
  * \param[in] font     Font to draw character in
  */
 void gfx_mono_draw_char(const char c, const gfx_coord_t x, const gfx_coord_t y,
-		const struct font *font)
+        const struct font *font)
 {
-	gfx_mono_draw_filled_rect(x, y, font->width, font->height,
-			GFX_PIXEL_CLR);
+    gfx_mono_draw_filled_rect(x, y, font->width, font->height,
+            GFX_PIXEL_CLR);
 
-	switch (font->type) {
-	case FONT_LOC_PROGMEM:
-		gfx_mono_draw_char_progmem(c, x, y, font);
-		break;
+    switch (font->type)
+    {
+    case FONT_LOC_PROGMEM:
+        gfx_mono_draw_char_progmem(c, x, y, font);
+        break;
 
 #ifdef CONFIG_HUGEMEM
-	case FONT_LOC_HUGEMEM:
-		gfx_mono_draw_char_hugemem(c, x, y, font);
-		break;
+    case FONT_LOC_HUGEMEM:
+        gfx_mono_draw_char_hugemem(c, x, y, font);
+        break;
 
 #endif
-	default:
-		/* Unsupported mode, call assert */
-		Assert(false);
-		break;
-	}
+    default:
+        /* Unsupported mode, call assert */
+        Assert(false);
+        break;
+    }
 }
 
 /**
@@ -256,28 +266,30 @@ void gfx_mono_draw_char(const char c, const gfx_coord_t x, const gfx_coord_t y,
  * \param[in] font      Font to draw string in
  */
 void gfx_mono_draw_string(const char *str, gfx_coord_t x, gfx_coord_t y,
-		const struct font *font)
+        const struct font *font)
 {
-	/* Save X in order to know where to return to on CR. */
-	const gfx_coord_t start_of_string_position_x = x;
-
-	/* Sanity check on parameters, assert if str or font is NULL. */
-	Assert(str != NULL);
-	Assert(font != NULL);
-
-	/* Draw characters until trailing null byte */
-	do {
-		/* Handle '\n' as newline, draw normal characters. */
-		if (*str == '\n') {
-			x = start_of_string_position_x;
-			y += font->height + 1;
-		} else if (*str == '\r') {
-			/* Skip '\r' characters. */
-		} else {
-			gfx_mono_draw_char(*str, x, y, font);
-			x += font->width;
-		}
-	} while (*(++str));
+    /* Save X in order to know where to return to on CR. */
+    const gfx_coord_t start_of_string_position_x = x;
+
+    /* Sanity check on parameters, assert if str or font is NULL. */
+    Assert(str != NULL);
+    Assert(font != NULL);
+
+    /* Draw characters until trailing null byte */
+    do {
+        /* Handle '\n' as newline, draw normal characters. */
+        if (*str == '\n')
+        {
+            x = start_of_string_position_x;
+            y += font->height + 1;
+        } else if (*str == '\r')
+        {
+            /* Skip '\r' characters. */
+        } else {
+            gfx_mono_draw_char(*str, x, y, font);
+            x += font->width;
+        }
+    } while (*(++str));
 }
 
 /**
@@ -296,34 +308,37 @@ void gfx_mono_draw_string(const char *str, gfx_coord_t x, gfx_coord_t y,
  * \param[in] font      Font to draw string in
  */
 void gfx_mono_draw_progmem_string(char PROGMEM_PTR_T str, gfx_coord_t x,
-		gfx_coord_t y, const struct font *font)
+        gfx_coord_t y, const struct font *font)
 {
-	char temp_char;
-
-	/* Sanity check on parameters, assert if str or font is NULL. */
-	Assert(str != NULL);
-	Assert(font != NULL);
-
-	/* Save X in order to know where to return to on CR. */
-	const gfx_coord_t start_of_string_position_x = x;
-
-	/* Draw characters until trailing null byte */
-	temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
-
-	while (temp_char) {
-		/* Handle '\n' as newline, draw normal characters. */
-		if (temp_char == '\n') {
-			x = start_of_string_position_x;
-			y += font->height + 1;
-		} else if (temp_char == '\r') {
-			/* Skip '\r' characters. */
-		} else {
-			gfx_mono_draw_char(temp_char, x, y, font);
-			x += font->width;
-		}
-
-		temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
-	}
+    char temp_char;
+
+    /* Sanity check on parameters, assert if str or font is NULL. */
+    Assert(str != NULL);
+    Assert(font != NULL);
+
+    /* Save X in order to know where to return to on CR. */
+    const gfx_coord_t start_of_string_position_x = x;
+
+    /* Draw characters until trailing null byte */
+    temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
+
+    while (temp_char)
+    {
+        /* Handle '\n' as newline, draw normal characters. */
+        if (temp_char == '\n')
+        {
+            x = start_of_string_position_x;
+            y += font->height + 1;
+        } else if (temp_char == '\r')
+        {
+            /* Skip '\r' characters. */
+        } else {
+            gfx_mono_draw_char(temp_char, x, y, font);
+            x += font->width;
+        }
+
+        temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
+    }
 }
 
 /**
@@ -338,38 +353,41 @@ void gfx_mono_draw_progmem_string(char PROGMEM_PTR_T str, gfx_coord_t x,
  * \param[in] height   Pointer to height result
  */
 void gfx_mono_get_string_bounding_box(const char *str, const struct font *font,
-		gfx_coord_t *width, gfx_coord_t *height)
+        gfx_coord_t *width, gfx_coord_t *height)
 {
-	gfx_coord_t font_width = font->width;
-	gfx_coord_t font_height = font->height;
-
-	gfx_coord_t max_width = 1;
-	gfx_coord_t max_height = font_height;
-	gfx_coord_t x = 0;
-
-	/* Sanity check on parameters, assert if str or font is NULL. */
-	Assert(str != NULL);
-	Assert(font != NULL);
-
-	/* Handle each character until trailing null byte */
-	do {
-		/* Handle '\n' as newline, draw normal characters. */
-		if (*str == '\n') {
-			x = 0;
-			max_height += font_height;
-		} else if (*str == '\r') {
-			/* Skip '\r' characters. */
-		} else {
-			x += font_width;
-			if (x > max_width) {
-				max_width = x;
-			}
-		}
-	} while (*(++str));
-
-	/* Return values through references */
-	*width = max_width;
-	*height = max_height;
+    gfx_coord_t font_width = font->width;
+    gfx_coord_t font_height = font->height;
+
+    gfx_coord_t max_width = 1;
+    gfx_coord_t max_height = font_height;
+    gfx_coord_t x = 0;
+
+    /* Sanity check on parameters, assert if str or font is NULL. */
+    Assert(str != NULL);
+    Assert(font != NULL);
+
+    /* Handle each character until trailing null byte */
+    do {
+        /* Handle '\n' as newline, draw normal characters. */
+        if (*str == '\n')
+        {
+            x = 0;
+            max_height += font_height;
+        } else if (*str == '\r')
+        {
+            /* Skip '\r' characters. */
+        } else {
+            x += font_width;
+            if (x > max_width)
+            {
+                max_width = x;
+            }
+        }
+    } while (*(++str));
+
+    /* Return values through references */
+    *width = max_width;
+    *height = max_height;
 }
 
 /**
@@ -384,42 +402,46 @@ void gfx_mono_get_string_bounding_box(const char *str, const struct font *font,
  * \param[in] height   Pointer to height result
  */
 void gfx_mono_get_progmem_string_bounding_box(char PROGMEM_PTR_T str,
-		const struct font *font, gfx_coord_t *width,
-		gfx_coord_t *height)
+        const struct font *font, gfx_coord_t *width,
+        gfx_coord_t *height)
 {
-	gfx_coord_t font_width = font->width;
-	gfx_coord_t font_height = font->height;
-
-	char temp_char;
-	gfx_coord_t max_width = 1;
-	gfx_coord_t max_height = font_height;
-	gfx_coord_t x = 0;
-
-	/* Sanity check on parameters, assert if str or font is NULL. */
-	Assert(str != NULL);
-	Assert(font != NULL);
-
-	/* Handle each character until trailing null byte */
-	temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
-
-	while (temp_char) {
-		/* Handle '\n' as newline, draw normal characters. */
-		if (temp_char == '\n') {
-			x = 0;
-			max_height += font_height;
-		} else if (*str == '\r') {
-			/* Skip '\r' characters. */
-		} else {
-			x += font_width;
-			if (x > max_width) {
-				max_width = x;
-			}
-		}
-
-		temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
-	}
-
-	/* Return values through references */
-	*width = max_width;
-	*height = max_height;
+    gfx_coord_t font_width = font->width;
+    gfx_coord_t font_height = font->height;
+
+    char temp_char;
+    gfx_coord_t max_width = 1;
+    gfx_coord_t max_height = font_height;
+    gfx_coord_t x = 0;
+
+    /* Sanity check on parameters, assert if str or font is NULL. */
+    Assert(str != NULL);
+    Assert(font != NULL);
+
+    /* Handle each character until trailing null byte */
+    temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)str);
+
+    while (temp_char)
+    {
+        /* Handle '\n' as newline, draw normal characters. */
+        if (temp_char == '\n')
+        {
+            x = 0;
+            max_height += font_height;
+        } else if (*str == '\r')
+        {
+            /* Skip '\r' characters. */
+        } else {
+            x += font_width;
+            if (x > max_width)
+            {
+                max_width = x;
+            }
+        }
+
+        temp_char = PROGMEM_READ_BYTE((uint8_t PROGMEM_PTR_T)(++str));
+    }
+
+    /* Return values through references */
+    *width = max_width;
+    *height = max_height;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h
index 9884397a9541..f7d5964b018c 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_text.h
@@ -70,56 +70,56 @@ extern "C" {
  * Add support for fonts in regular ram
  */
 enum font_data_type {
-	/** Font data stored in program/flash memory. */
-	FONT_LOC_PROGMEM,
+    /** Font data stored in program/flash memory. */
+    FONT_LOC_PROGMEM,
 };
 
 /** Storage structure for font meta data. */
 struct font {
-	/** Type of storage used for binary font data. See \ref font_data_type. */
-	enum font_data_type type;
-	union {
-		/**
-		 * Pointer to where the binary font data is stored. This
-		 * variable is accessed either through hugemem or progmem
-		 * depending on the value of \a type.
-		 */
+    /** Type of storage used for binary font data. See \ref font_data_type. */
+    enum font_data_type type;
+    union {
+        /**
+         * Pointer to where the binary font data is stored. This
+         * variable is accessed either through hugemem or progmem
+         * depending on the value of \a type.
+         */
 #ifdef CONFIG_HAVE_HUGEMEM
-		hugemem_ptr_t hugemem;
+        hugemem_ptr_t hugemem;
 #endif
-		uint8_t PROGMEM_PTR_T progmem;
-	} data;
-	/** Width of one font character, in pixels. */
-	uint8_t width;
-	/** Height of one font character, in pixels. */
-	uint8_t height;
-	/** ASCII value of first character in font set. */
-	uint8_t first_char;
-	/** ASCII value of last character in the set. */
-	uint8_t last_char;
+        uint8_t PROGMEM_PTR_T progmem;
+    } data;
+    /** Width of one font character, in pixels. */
+    uint8_t width;
+    /** Height of one font character, in pixels. */
+    uint8_t height;
+    /** ASCII value of first character in font set. */
+    uint8_t first_char;
+    /** ASCII value of last character in the set. */
+    uint8_t last_char;
 };
 
 /** \name Strings and characters located in RAM */
 /** @{ */
 void gfx_mono_draw_char(const char c, const gfx_coord_t x, const gfx_coord_t y,
-		const struct font *font);
+        const struct font *font);
 
 void gfx_mono_draw_string(const char *str, const gfx_coord_t x,
-		const gfx_coord_t y, const struct font *font);
+        const gfx_coord_t y, const struct font *font);
 
 void gfx_mono_get_string_bounding_box(char const *str, const struct font *font,
-		gfx_coord_t *width, gfx_coord_t *height);
+        gfx_coord_t *width, gfx_coord_t *height);
 
 /** @} */
 
 /** \name Strings located in flash */
 /** @{ */
 void gfx_mono_draw_progmem_string(char PROGMEM_PTR_T str, gfx_coord_t x,
-		gfx_coord_t y, const struct font *font);
+        gfx_coord_t y, const struct font *font);
 
 void gfx_mono_get_progmem_string_bounding_box(char PROGMEM_PTR_T str,
-		const struct font *font, gfx_coord_t *width,
-		gfx_coord_t *height);
+        const struct font *font, gfx_coord_t *width,
+        gfx_coord_t *height);
 
 /** @} */
 
@@ -146,15 +146,16 @@ void gfx_mono_get_progmem_string_bounding_box(char PROGMEM_PTR_T str,
  * \subsection gfx_mono_font_basic_usage_code Example code
  * Add to, e.g., the main function in the application C-file:
  * \code
-	     system_init();
+         system_init();
 
-	     gfx_mono_init();
+         gfx_mono_init();
 
-	     gfx_mono_draw_string("Hello world!",0, 0, &sysfont);
+         gfx_mono_draw_string("Hello world!",0, 0, &sysfont);
 
-	     while (1) {
+         while (1)
+         {
 
-	     }
+         }
 \endcode
  *
  * \subsection asfdoc_common2_gfx_mono_font_basic_usage_workflow Workflow
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c
index bf049033b9f6..d17085197374 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.c
@@ -59,28 +59,30 @@ static uint8_t framebuffer[GFX_MONO_LCD_FRAMEBUFFER_SIZE];
  */
 void gfx_mono_ssd1306_init(void)
 {
-	uint8_t page;
-	uint8_t column;
+    uint8_t page;
+    uint8_t column;
 
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
-	gfx_mono_set_framebuffer(framebuffer);
+    gfx_mono_set_framebuffer(framebuffer);
 #endif
 
-	/* Initialize the low-level display controller. */
-	ssd1306_init();
-
-	/* Set display to output data from line 0 */
-	ssd1306_set_display_start_line_address(0);
-
-	/* Clear the contents of the display.
-	 * If using a framebuffer (SPI interface) it will both clear the
-	 * controller memory and the framebuffer.
-	 */
-	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
-		for (column = 0; column < GFX_MONO_LCD_WIDTH; column++) {
-			gfx_mono_ssd1306_put_byte(page, column, 0x00, true);
-		}
-	}
+    /* Initialize the low-level display controller. */
+    ssd1306_init();
+
+    /* Set display to output data from line 0 */
+    ssd1306_set_display_start_line_address(0);
+
+    /* Clear the contents of the display.
+     * If using a framebuffer (SPI interface) it will both clear the
+     * controller memory and the framebuffer.
+     */
+    for (page = 0; page < GFX_MONO_LCD_PAGES; page++)
+    {
+        for (column = 0; column < GFX_MONO_LCD_WIDTH; column++)
+        {
+            gfx_mono_ssd1306_put_byte(page, column, 0x00, true);
+        }
+    }
 }
 
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
@@ -95,15 +97,16 @@ void gfx_mono_ssd1306_init(void)
  */
 void gfx_mono_ssd1306_put_framebuffer(void)
 {
-	uint8_t page;
-
-	for (page = 0; page < GFX_MONO_LCD_PAGES; page++) {
-		ssd1306_set_page_address(page);
-		ssd1306_set_column_address(0);
-		gfx_mono_ssd1306_put_page(framebuffer
-				+ (page * GFX_MONO_LCD_WIDTH), page, 0,
-				GFX_MONO_LCD_WIDTH);
-	}
+    uint8_t page;
+
+    for (page = 0; page < GFX_MONO_LCD_PAGES; page++)
+    {
+        ssd1306_set_page_address(page);
+        ssd1306_set_column_address(0);
+        gfx_mono_ssd1306_put_page(framebuffer
+                + (page * GFX_MONO_LCD_WIDTH), page, 0,
+                GFX_MONO_LCD_WIDTH);
+    }
 }
 #endif
 
@@ -116,57 +119,59 @@ void gfx_mono_ssd1306_put_framebuffer(void)
  *
  * The following will set the pixel at x=10,y=10:
  * \code
-	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_SET);
+    gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_SET);
 \endcode
  * The following example will clear the pixel at x=10,y=10:
  * \code
-	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_CLR);
+    gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_CLR);
 \endcode
  * And the following will toggle the pixel at x=10,y=10:
  * \code
-	gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_XOR);
+    gfx_mono_ssd1306_draw_pixel(10, 10, GFX_PIXEL_XOR);
 \endcode
  */
 void gfx_mono_ssd1306_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_coord_t color)
+        gfx_coord_t color)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
-	uint8_t pixel_value;
-
-	/* Discard pixels drawn outside the screen */
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return;
-	}
-
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
-
-	/*
-	 * Read the page containing the pixel in interest, then perform the
-	 * requested action on this pixel before writing the page back to the
-	 * display.
-	 */
-	pixel_value = gfx_mono_get_byte(page, x);
-
-	switch (color) {
-	case GFX_PIXEL_SET:
-		pixel_value |= pixel_mask;
-		break;
-
-	case GFX_PIXEL_CLR:
-		pixel_value &= ~pixel_mask;
-		break;
-
-	case GFX_PIXEL_XOR:
-		pixel_value ^= pixel_mask;
-		break;
-
-	default:
-		break;
-	}
-
-	gfx_mono_put_byte(page, x, pixel_value);
+    uint8_t page;
+    uint8_t pixel_mask;
+    uint8_t pixel_value;
+
+    /* Discard pixels drawn outside the screen */
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return;
+    }
+
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
+
+    /*
+     * Read the page containing the pixel in interest, then perform the
+     * requested action on this pixel before writing the page back to the
+     * display.
+     */
+    pixel_value = gfx_mono_get_byte(page, x);
+
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        pixel_value |= pixel_mask;
+        break;
+
+    case GFX_PIXEL_CLR:
+        pixel_value &= ~pixel_mask;
+        break;
+
+    case GFX_PIXEL_XOR:
+        pixel_value ^= pixel_mask;
+        break;
+
+    default:
+        break;
+    }
+
+    gfx_mono_put_byte(page, x, pixel_value);
 }
 
 /**
@@ -178,22 +183,23 @@ void gfx_mono_ssd1306_draw_pixel(gfx_coord_t x, gfx_coord_t y,
  *
  * The following example will read the pixel value from x=10,y=10:
  * \code
-	pixelval = gfx_mono_ssd1306_get_pixel(10,10);
+    pixelval = gfx_mono_ssd1306_get_pixel(10,10);
 \endcode
  */
 uint8_t gfx_mono_ssd1306_get_pixel(gfx_coord_t x, gfx_coord_t y)
 {
-	uint8_t page;
-	uint8_t pixel_mask;
+    uint8_t page;
+    uint8_t pixel_mask;
 
-	if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1)) {
-		return 0;
-	}
+    if ((x > GFX_MONO_LCD_WIDTH - 1) || (y > GFX_MONO_LCD_HEIGHT - 1))
+    {
+        return 0;
+    }
 
-	page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
-	pixel_mask = (1 << (y - (page * 8)));
+    page = y / GFX_MONO_LCD_PIXELS_PER_BYTE;
+    pixel_mask = (1 << (y - (page * 8)));
 
-	return gfx_mono_get_byte(page, x) & pixel_mask;
+    return gfx_mono_get_byte(page, x) & pixel_mask;
 }
 
 /**
@@ -213,21 +219,21 @@ uint8_t gfx_mono_ssd1306_get_pixel(gfx_coord_t x, gfx_coord_t y)
  * column 10. This will place data_buf in the rectangle x1=10,y1=0,x2=42,y2=8
  * (10 pixels from the upper left corner of the screen):
  * \code
-	gfx_mono_ssd1306_put_page(data_buf, 0, 10, 32);
+    gfx_mono_ssd1306_put_page(data_buf, 0, 10, 32);
 \endcode
  */
 void gfx_mono_ssd1306_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
-	gfx_mono_framebuffer_put_page(data, page, column, width);
+    gfx_mono_framebuffer_put_page(data, page, column, width);
 #endif
-	ssd1306_set_page_address(page);
-	ssd1306_set_column_address(column);
+    ssd1306_set_page_address(page);
+    ssd1306_set_column_address(column);
 
-	do {
-		ssd1306_write_data(*data++);
-	} while (--width);
+    do {
+        ssd1306_write_data(*data++);
+    } while (--width);
 }
 
 /**
@@ -245,21 +251,21 @@ void gfx_mono_ssd1306_put_page(gfx_mono_color_t *data, gfx_coord_t page,
  * The following example will read back the first 128 bytes (first page) from
  * the display memory:
  * \code
-	gfx_mono_ssd1306_get_page(read_buffer, 0, 0, 128);
+    gfx_mono_ssd1306_get_page(read_buffer, 0, 0, 128);
 \endcode
  */
 void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t column, gfx_coord_t width)
+        gfx_coord_t column, gfx_coord_t width)
 {
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
-	gfx_mono_framebuffer_get_page(data, page, column, width);
+    gfx_mono_framebuffer_get_page(data, page, column, width);
 #else
-	ssd1306_set_page_address(page);
-	ssd1306_set_column_address(column);
+    ssd1306_set_page_address(page);
+    ssd1306_set_column_address(column);
 
-	do {
-		*data++ = ssd1306_read_data();
-	} while (--width);
+    do {
+        *data++ = ssd1306_read_data();
+    } while (--width);
 #endif
 }
 
@@ -278,23 +284,24 @@ void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
  * setting a 8 pixel high column of pixels in the upper left corner of the
  * display.
  * \code
-	gfx_mono_ssd1306_put_byte(0, 0, 0xFF, false);
+    gfx_mono_ssd1306_put_byte(0, 0, 0xFF, false);
 \endcode
   */
  void gfx_mono_ssd1306_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data, bool force)
+        uint8_t data, bool force)
 {
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
-	if (!force && data == gfx_mono_framebuffer_get_byte(page, column)) {
-		return;
-	}
-	gfx_mono_framebuffer_put_byte(page, column, data);
+    if (!force && data == gfx_mono_framebuffer_get_byte(page, column))
+    {
+        return;
+    }
+    gfx_mono_framebuffer_put_byte(page, column, data);
 #endif
 
-	ssd1306_set_page_address(page);
-	ssd1306_set_column_address(column);
+    ssd1306_set_page_address(page);
+    ssd1306_set_column_address(column);
 
-	ssd1306_write_data(data);
+    ssd1306_write_data(data);
 }
 
 /**
@@ -311,19 +318,19 @@ void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
  * local framebuffer if direct read is not possible. The data represents the
  * pixels from x = 0 and y = 0 to y = 7.
  * \code
-	data = gfx_mono_ssd1306_get_byte(0, 0);
+    data = gfx_mono_ssd1306_get_byte(0, 0);
 \endcode
  */
 uint8_t gfx_mono_ssd1306_get_byte(gfx_coord_t page, gfx_coord_t column)
 {
 #ifdef CONFIG_SSD1306_FRAMEBUFFER
-	return gfx_mono_framebuffer_get_byte(page, column);
+    return gfx_mono_framebuffer_get_byte(page, column);
 
 #else
-	ssd1306_set_page_address(page);
-	ssd1306_set_column_address(column);
+    ssd1306_set_page_address(page);
+    ssd1306_set_column_address(column);
 
-	return ssd1306_read_data();
+    return ssd1306_read_data();
 
 #endif
 }
@@ -343,30 +350,31 @@ uint8_t gfx_mono_ssd1306_get_byte(gfx_coord_t page, gfx_coord_t column)
  *
  * A small example that will XOR the first byte of display memory with 0xAA
  * \code
-	gfx_mono_ssd1306_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
+    gfx_mono_ssd1306_mask_byte(0,0,0xAA,GFX_PIXEL_XOR);
 \endcode
  */
 void gfx_mono_ssd1306_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color)
 {
-	gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
+    gfx_mono_color_t temp = gfx_mono_get_byte(page, column);
 
-	switch (color) {
-	case GFX_PIXEL_SET:
-		temp |= pixel_mask;
-		break;
+    switch (color)
+    {
+    case GFX_PIXEL_SET:
+        temp |= pixel_mask;
+        break;
 
-	case GFX_PIXEL_CLR:
-		temp &= ~pixel_mask;
-		break;
+    case GFX_PIXEL_CLR:
+        temp &= ~pixel_mask;
+        break;
 
-	case GFX_PIXEL_XOR:
-		temp ^= pixel_mask;
-		break;
+    case GFX_PIXEL_XOR:
+        temp ^= pixel_mask;
+        break;
 
-	default:
-		break;
-	}
+    default:
+        break;
+    }
 
-	gfx_mono_put_byte(page, column, temp);
+    gfx_mono_put_byte(page, column, temp);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h
index 5cb0ddd834ed..7d40c376daba 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/gfx_mono_ug_2832hsweg04.h
@@ -78,86 +78,86 @@ extern "C" {
 #endif
 #define GFX_MONO_LCD_PIXELS_PER_BYTE    8
 #define GFX_MONO_LCD_PAGES              (GFX_MONO_LCD_HEIGHT / \
-	GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_PIXELS_PER_BYTE)
 #define GFX_MONO_LCD_FRAMEBUFFER_SIZE   ((GFX_MONO_LCD_WIDTH * \
-	GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
+    GFX_MONO_LCD_HEIGHT) / GFX_MONO_LCD_PIXELS_PER_BYTE)
 
 #define gfx_mono_draw_horizontal_line(x, y, length, color) \
-	gfx_mono_generic_draw_horizontal_line(x, y, length, color)
+    gfx_mono_generic_draw_horizontal_line(x, y, length, color)
 
 #define gfx_mono_draw_vertical_line(x, y, length, color) \
-	gfx_mono_generic_draw_vertical_line(x, y, length, color)
+    gfx_mono_generic_draw_vertical_line(x, y, length, color)
 
 #define gfx_mono_draw_line(x1, y1, x2, y2, color) \
-	gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
+    gfx_mono_generic_draw_line(x1, y1, x2, y2, color)
 
 #define gfx_mono_draw_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_rect(x, y, width, height, color)
+    gfx_mono_generic_draw_rect(x, y, width, height, color)
 
 #define gfx_mono_draw_filled_rect(x, y, width, height, color) \
-	gfx_mono_generic_draw_filled_rect(x, y, width, height, \
-		color)
+    gfx_mono_generic_draw_filled_rect(x, y, width, height, \
+        color)
 
 #define gfx_mono_draw_circle(x, y, radius, color, octant_mask) \
-	gfx_mono_generic_draw_circle(x, y, radius, color, \
-		octant_mask)
+    gfx_mono_generic_draw_circle(x, y, radius, color, \
+        octant_mask)
 
-#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask)	\
-	gfx_mono_generic_draw_filled_circle(x, y, radius, \
-		color, quadrant_mask)
+#define gfx_mono_draw_filled_circle(x, y, radius, color, quadrant_mask) \
+    gfx_mono_generic_draw_filled_circle(x, y, radius, \
+        color, quadrant_mask)
 
 #define gfx_mono_put_bitmap(bitmap, x, y) \
-	gfx_mono_generic_put_bitmap(bitmap, x, y)
+    gfx_mono_generic_put_bitmap(bitmap, x, y)
 
 #define gfx_mono_draw_pixel(x, y, color) \
-	gfx_mono_ssd1306_draw_pixel(x, y, color)
+    gfx_mono_ssd1306_draw_pixel(x, y, color)
 
 #define gfx_mono_get_pixel(x, y) \
-	gfx_mono_ssd1306_get_pixel(x, y)
+    gfx_mono_ssd1306_get_pixel(x, y)
 
-#define gfx_mono_init()	\
-	gfx_mono_ssd1306_init()
+#define gfx_mono_init() \
+    gfx_mono_ssd1306_init()
 
 #define gfx_mono_put_page(data, page, column, width) \
-	gfx_mono_ssd1306_put_page(data, page, column, width)
+    gfx_mono_ssd1306_put_page(data, page, column, width)
 
 #define gfx_mono_get_page(data, page, column, width) \
-	gfx_mono_ssd1306_get_page(data, page, column, width)
+    gfx_mono_ssd1306_get_page(data, page, column, width)
 
 #define gfx_mono_put_byte(page, column, data) \
-	gfx_mono_ssd1306_put_byte(page, column, data, false)
+    gfx_mono_ssd1306_put_byte(page, column, data, false)
 
-#define gfx_mono_get_byte(page, column)	\
-	gfx_mono_ssd1306_get_byte(page, column)
+#define gfx_mono_get_byte(page, column) \
+    gfx_mono_ssd1306_get_byte(page, column)
 
 #define gfx_mono_mask_byte(page, column, pixel_mask, color) \
-	gfx_mono_ssd1306_mask_byte(page, column, pixel_mask, color)
+    gfx_mono_ssd1306_mask_byte(page, column, pixel_mask, color)
 
 #define gfx_mono_put_framebuffer() \
-	gfx_mono_ssd1306_put_framebuffer()
+    gfx_mono_ssd1306_put_framebuffer()
 
 void gfx_mono_ssd1306_put_framebuffer(void);
 
 void gfx_mono_ssd1306_put_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_ssd1306_get_page(gfx_mono_color_t *data, gfx_coord_t page,
-		gfx_coord_t page_offset, gfx_coord_t width);
+        gfx_coord_t page_offset, gfx_coord_t width);
 
 void gfx_mono_ssd1306_init(void);
 
 void gfx_mono_ssd1306_draw_pixel(gfx_coord_t x, gfx_coord_t y,
-		gfx_mono_color_t color);
+        gfx_mono_color_t color);
 
 uint8_t gfx_mono_ssd1306_get_pixel(gfx_coord_t x, gfx_coord_t y);
 
 void gfx_mono_ssd1306_put_byte(gfx_coord_t page, gfx_coord_t column,
-		uint8_t data, bool force);
+        uint8_t data, bool force);
 
 uint8_t gfx_mono_ssd1306_get_byte(gfx_coord_t page, gfx_coord_t column);
 
 void gfx_mono_ssd1306_mask_byte(gfx_coord_t page, gfx_coord_t column,
-		gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
+        gfx_mono_color_t pixel_mask, gfx_mono_color_t color);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h
index 5a765a77128b..221c44b266ea 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_menu.h
@@ -47,26 +47,26 @@
 #ifndef DEFAULT_MENU_H_INCLUDED
 #define DEFAULT_MENU_H_INCLUDED
 
-//! \name Indicator icon definitions
-//@{
-//! Bitmap data, row by row, MSB is leftmost pixel, one byte per row.
+/*! \name Indicator icon definitions*/
+/*@{*/
+/*! Bitmap data, row by row, MSB is leftmost pixel, one byte per row.*/
 #define GFX_MONO_MENU_INDICATOR_BITMAP 0xFF, 0x7E, 0x3C, 0x18
-//! Height in pixels of indicator icon
+/*! Height in pixels of indicator icon*/
 #define GFX_MONO_MENU_INDICATOR_HEIGHT 8
-//! Width in pixels of indicator icon
+/*! Width in pixels of indicator icon*/
 #define GFX_MONO_MENU_INDICATOR_WIDTH  4
-//@}
+/*@}*/
 
-//! \name Keyboard codes
-//@{
-//! Down
+/*! \name Keyboard codes*/
+/*@{*/
+/*! Down*/
 #define GFX_MONO_MENU_KEYCODE_DOWN  40
-//! Up
+/*! Up*/
 #define GFX_MONO_MENU_KEYCODE_UP    38
-//! Back/exit
+/*! Back/exit*/
 #define GFX_MONO_MENU_KEYCODE_BACK  8
-//! Enter/select
+/*! Enter/select*/
 #define GFX_MONO_MENU_KEYCODE_ENTER 13
-//@}
+/*@}*/
 
 #endif /* DEFAULT_MENU_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h
index 2090b6a13646..5d5b5771b834 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_spinctrl.h
@@ -47,29 +47,29 @@
 #ifndef DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED
 #define DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED
 
-//! Spinner value indicator
+/*! Spinner value indicator*/
 /* Bitmap data, row by row, MSB is leftmost pixel, one byte per row. */
 #define GFX_MONO_SPINCTRL_SPIN_INDICATOR_BITMAP 0x18, 0x3C, 0x7E, 0xFF
-//! Height of spinner value indicator
+/*! Height of spinner value indicator*/
 #define GFX_MONO_SPINCTRL_SPIN_INDICATOR_HEIGHT 8
-//! Width of spinner value indicator
+/*! Width of spinner value indicator*/
 #define GFX_MONO_SPINCTRL_SPIN_INDICATOR_WIDTH  4
 
-//! Spinner indicator
+/*! Spinner indicator*/
 /* Bitmap data, row by row, MSB is leftmost pixel, one byte per row. */
 #define GFX_MONO_SPINCTRL_INDICATOR_BITMAP 0xFF, 0x7E, 0x3C, 0x18
-//! Height of spinner indicator
+/*! Height of spinner indicator*/
 #define GFX_MONO_SPINCTRL_INDICATOR_HEIGHT 8
-//! Width of spinner indicator
+/*! Width of spinner indicator*/
 #define GFX_MONO_SPINCTRL_INDICATOR_WIDTH  4
 
-//! Keyboard code down
+/*! Keyboard code down*/
 #define GFX_MONO_SPINCTRL_KEYCODE_DOWN  40
-//! Keyboard code up
+/*! Keyboard code up*/
 #define GFX_MONO_SPINCTRL_KEYCODE_UP    38
-//! Keyboard code back
+/*! Keyboard code back*/
 #define GFX_MONO_SPINCTRL_KEYCODE_BACK  8
-//! Keyboard code enter
+/*! Keyboard code enter*/
 #define GFX_MONO_SPINCTRL_KEYCODE_ENTER 13
 
 #endif /* DEFAULT_GFX_MONO_SPINCTRL_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h
index 05daa73beef5..bbfb1450e666 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/module_config/conf_sysfont.h
@@ -73,385 +73,386 @@
 /** Define variable containing the font */
 #  define SYSFONT_DEFINE_GLYPHS \
         /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
-	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
-		/* "BPmono" font (http://www.backpacker.gr) at size 10x16 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /*   */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
-		0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ! */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
-		0x6C, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* " */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, \
-		0x48, 0x00, 0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, \
-		0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* # */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x3C, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
-		0x78, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* $ */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, \
-		0xA4, 0x00, 0xA8, 0x00, 0x48, 0x00, 0x10, 0x00, 0x14, 0x00, \
-		0x2A, 0x00, 0x4A, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* % */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x8A, 0x00, \
-		0x8A, 0x00, 0x8C, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* & */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ' */ \
-		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ( */ \
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ) */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x10, 0x00, \
-		0x7C, 0x00, 0x10, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* * */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* + */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x30, 0x00, 0x20, 0x00, \
-		0x00, 0x00, /* , */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* - */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* . */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* / */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 0 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
-		0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 1 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 2 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x88, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 3 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
-		0x28, 0x00, 0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0xFC, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 4 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x04, 0x00, 0x04, 0x00, \
-		0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 5 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x40, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0xB0, 0x00, 0xC8, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 6 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
-		0x04, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 7 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 8 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* 9 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* : */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x80, 0x00, \
-		0x00, 0x00, /* ; */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x04, 0x00, 0x18, 0x00, 0x60, 0x00, 0x80, 0x00, \
-		0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* < */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* = */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x40, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x02, 0x00, \
-		0x0C, 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* > */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ? */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x3C, 0x00, 0x42, 0x00, 0xBA, 0x00, 0xAA, 0x00, 0xAA, 0x00, \
-		0xAA, 0x00, 0xBC, 0x00, 0x40, 0x00, 0x3C, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* @ */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, \
-		0x44, 0x00, 0x82, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* A */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* B */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x44, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* C */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* D */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* E */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* F */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x44, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* G */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* H */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* I */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* J */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* K */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* L */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0xCC, 0x00, 0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* M */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
-		0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
-		0x8C, 0x00, 0x8C, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* N */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* O */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* P */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x20, 0x00, 0x1C, 0x00, \
-		0x00, 0x00, /* Q */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x90, 0x00, \
-		0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* R */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
-		0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* S */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* T */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* U */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x82, 0x00, \
-		0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
-		0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* V */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
-		0x78, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* W */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
-		0x44, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x28, 0x00, \
-		0x44, 0x00, 0x44, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* X */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
-		0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* Y */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* Z */ \
-		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xE0, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* [ */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* \ */ \
-		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xE0, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ] */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
-		0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ^ */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* _ */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
-		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* ` */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x78, 0x00, 0x04, 0x00, 0x04, 0x00, 0x7C, 0x00, \
-		0x84, 0x00, 0x8C, 0x00, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* a */ \
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* b */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* c */ \
-		0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, \
-		0x02, 0x00, 0x3E, 0x00, 0x42, 0x00, 0x82, 0x00, 0x82, 0x00, \
-		0x82, 0x00, 0x42, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* d */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0xFE, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* e */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* f */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, 0x44, 0x00, \
-		0x38, 0x00, /* g */ \
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* h */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* i */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, \
-		0xE0, 0x00, /* j */ \
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xE0, 0x00, \
-		0x90, 0x00, 0x88, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* k */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* l */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xAC, 0x00, 0xD4, 0x00, 0x94, 0x00, 0x94, 0x00, \
-		0x94, 0x00, 0x94, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* m */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* n */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* o */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, /* p */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, \
-		0x04, 0x00, /* q */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xCC, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* r */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x78, 0x00, \
-		0x04, 0x00, 0x04, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* s */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* t */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* u */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
-		0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* v */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
-		0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* w */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
-		0x28, 0x00, 0x44, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* x */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
-		0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, /* y */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* z */ \
-		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* { */ \
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* | */ \
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0x00, 0x00, /* } */ \
-	};
+    static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[])=
+    { \
+        /* "BPmono" font (http://www.backpacker.gr) at size 10x16 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /*   */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
+        0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ! */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
+        0x6C, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* " */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, \
+        0x48, 0x00, 0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, \
+        0xFC, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* # */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x3C, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
+        0x78, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* $ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, \
+        0xA4, 0x00, 0xA8, 0x00, 0x48, 0x00, 0x10, 0x00, 0x14, 0x00, \
+        0x2A, 0x00, 0x4A, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* % */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x8A, 0x00, \
+        0x8A, 0x00, 0x8C, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* & */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ' */ \
+        0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ( */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ) */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x10, 0x00, \
+        0x7C, 0x00, 0x10, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* * */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* + */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x30, 0x00, 0x20, 0x00, \
+        0x00, 0x00, /* , */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* - */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x18, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* . */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* / */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 0 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+        0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 1 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 2 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x88, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 3 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
+        0x28, 0x00, 0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0xFC, 0x00, 0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 4 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x04, 0x00, 0x04, 0x00, \
+        0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 5 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x40, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0xB0, 0x00, 0xC8, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 6 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+        0x04, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 7 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 8 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* 9 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* : */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x60, 0x00, 0x60, 0x00, 0xC0, 0x00, 0x80, 0x00, \
+        0x00, 0x00, /* ; */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x04, 0x00, 0x18, 0x00, 0x60, 0x00, 0x80, 0x00, \
+        0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* < */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* = */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x40, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x02, 0x00, \
+        0x0C, 0x00, 0x30, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* > */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ? */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x3C, 0x00, 0x42, 0x00, 0xBA, 0x00, 0xAA, 0x00, 0xAA, 0x00, \
+        0xAA, 0x00, 0xBC, 0x00, 0x40, 0x00, 0x3C, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* @ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, \
+        0x44, 0x00, 0x82, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* A */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* B */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x44, 0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* C */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* D */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* E */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x78, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* F */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x44, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x44, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* G */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* H */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* I */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* J */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* K */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* L */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0xCC, 0x00, 0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* M */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
+        0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+        0x8C, 0x00, 0x8C, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* N */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* O */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* P */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x48, 0x00, 0x30, 0x00, 0x20, 0x00, 0x1C, 0x00, \
+        0x00, 0x00, /* Q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x90, 0x00, \
+        0x88, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* R */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, 0x04, 0x00, \
+        0x04, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* S */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* T */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* U */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x82, 0x00, \
+        0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+        0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* V */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
+        0x78, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* W */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
+        0x44, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x28, 0x00, \
+        0x44, 0x00, 0x44, 0x00, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* X */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x82, 0x00, 0x44, 0x00, \
+        0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* Y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* Z */ \
+        0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xE0, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* [ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* \ */ \
+        0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xE0, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ] */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
+        0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ^ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* _ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* ` */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x78, 0x00, 0x04, 0x00, 0x04, 0x00, 0x7C, 0x00, \
+        0x84, 0x00, 0x8C, 0x00, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* a */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x88, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* b */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* c */ \
+        0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x02, 0x00, \
+        0x02, 0x00, 0x3E, 0x00, 0x42, 0x00, 0x82, 0x00, 0x82, 0x00, \
+        0x82, 0x00, 0x42, 0x00, 0x3E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* d */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x82, 0x00, 0x82, 0x00, 0xFE, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* e */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* f */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x8C, 0x00, 0x74, 0x00, 0x04, 0x00, 0x44, 0x00, \
+        0x38, 0x00, /* g */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* h */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* i */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x10, 0x00, \
+        0xE0, 0x00, /* j */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xE0, 0x00, \
+        0x90, 0x00, 0x88, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* k */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* l */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xAC, 0x00, 0xD4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+        0x94, 0x00, 0x94, 0x00, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* m */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* n */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* o */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, /* p */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, \
+        0x04, 0x00, /* q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xCC, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* r */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, 0x80, 0x00, 0x78, 0x00, \
+        0x04, 0x00, 0x04, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* s */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x20, 0x00, 0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* t */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* u */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+        0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* v */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x84, 0x00, 0x84, 0x00, 0xB4, 0x00, 0xB4, 0x00, \
+        0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* w */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x44, 0x00, 0x28, 0x00, 0x28, 0x00, 0x10, 0x00, \
+        0x28, 0x00, 0x44, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* x */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x82, 0x00, 0x44, 0x00, 0x44, 0x00, 0x28, 0x00, \
+        0x28, 0x00, 0x28, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, /* y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, 0x08, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* z */ \
+        0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* { */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* | */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0x00, 0x00, /* } */ \
+    };
 #elif defined(USE_FONT_BPMONO_10x14)
 /** Width of each glyph, including spacer column. */
 #  define SYSFONT_WIDTH           10
@@ -467,291 +468,292 @@
 /** Define variable containing the font */
 #  define SYSFONT_DEFINE_GLYPHS \
         /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
-	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
-		/* "BPmono" font (http://www.backpacker.gr) at size 10x14 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*   */	\
-		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ! */	\
-		0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
-		0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* " */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, \
-		0x7C, 0x00, 0x28, 0x00, 0x28, 0x00, 0x7C, 0x00, 0x28, 0x00, \
-		0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* # */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x3C, 0x00, 0x40, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00, 0x78, 0x00, \
-		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* $ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xA4, 0x00, \
-		0xA8, 0x00, 0x50, 0x00, 0x28, 0x00, 0x54, 0x00, 0x94, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* % */	\
-		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x90, 0x00, \
-		0x90, 0x00, 0x60, 0x00, 0x94, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* & */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ' */	\
-		0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* ( */	\
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* ) */	\
-		0x00, 0x00, 0x28, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x10, 0x00, \
-		0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* * */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* + */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x10, 0x00, 0x30, 0x00, 0x20, 0x00, 0x00, 0x00, /* , */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* - */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* . */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* / */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, 0x84, 0x00, \
-		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
-		0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 1 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, \
-		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 3 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
-		0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0xFC, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 4 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 5 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 7 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x10, 0x00, \
-		0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 9 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* : */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x60, 0x00, 0x40, 0x00, 0x00, 0x00, /* ; */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, \
-		0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* < */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* = */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* > */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ? */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, \
-		0x42, 0x00, 0x9A, 0x00, 0xAA, 0x00, 0xAA, 0x00, 0xBE, 0x00, \
-		0x80, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, /* @ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
-		0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, 0x44, 0x00, 0x44, 0x00, \
-		0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* A */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* B */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, \
-		0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* C */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, \
-		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* D */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* E */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* F */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, 0x44, 0x00, \
-		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* G */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* H */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* I */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* J */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x88, 0x00, \
-		0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* K */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* L */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xCC, 0x00, \
-		0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* M */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
-		0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
-		0x8C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* N */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* O */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* P */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x78, 0x00, 0x20, 0x00, 0x18, 0x00, 0x00, 0x00, /* Q */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* R */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x04, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* S */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* T */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* U */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
-		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* V */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xA8, 0x00, \
-		0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
-		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* W */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* X */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Y */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
-		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Z */	\
-		0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x40, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
-		0x40, 0x00, 0x40, 0x00, 0x70, 0x00, 0x00, 0x00, /* [ */	\
-		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* \ */	\
-		0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x38, 0x00, 0x00, 0x00, /* ] */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, 0x44, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* _ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ` */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x70, 0x00, 0x08, 0x00, 0x08, 0x00, 0x78, 0x00, 0x88, 0x00, \
-		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a */	\
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c */	\
-		0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, \
-		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, \
-		0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* d */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* e */	\
-		0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x7C, 0x00, 0x04, 0x00, 0x78, 0x00, 0x00, 0x00, /* g */	\
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* h */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
-		0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* i */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, /* j */	\
-		0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* k */	\
-		0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* l */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xA4, 0x00, 0xFC, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0xA4, 0x00, \
-		0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* m */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* n */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* o */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* p */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
-		0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, /* q */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xD8, 0x00, 0x60, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
-		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* r */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, \
-		0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* s */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
-		0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* t */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* u */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, \
-		0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* v */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
-		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* w */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* x */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, /* y */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* z */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* { */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* | */	\
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x10, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* } */	\
-	};
+    static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[])=
+    { \
+        /* "BPmono" font (http://www.backpacker.gr) at size 10x14 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*   */ \
+        0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ! */ \
+        0x00, 0x00, 0x00, 0x00, 0x6C, 0x00, 0x6C, 0x00, 0x6C, 0x00, \
+        0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* " */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x28, 0x00, \
+        0x7C, 0x00, 0x28, 0x00, 0x28, 0x00, 0x7C, 0x00, 0x28, 0x00, \
+        0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* # */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x04, 0x00, 0x78, 0x00, \
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* $ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0xA4, 0x00, \
+        0xA8, 0x00, 0x50, 0x00, 0x28, 0x00, 0x54, 0x00, 0x94, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* % */ \
+        0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x90, 0x00, 0x90, 0x00, \
+        0x90, 0x00, 0x60, 0x00, 0x94, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* & */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ' */ \
+        0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* ( */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* ) */ \
+        0x00, 0x00, 0x28, 0x00, 0x10, 0x00, 0x7C, 0x00, 0x10, 0x00, \
+        0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* * */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0xFE, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* + */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x10, 0x00, 0x30, 0x00, 0x20, 0x00, 0x00, 0x00, /* , */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* - */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* . */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* / */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x8C, 0x00, 0x94, 0x00, 0xA4, 0x00, 0xC4, 0x00, 0x84, 0x00, \
+        0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+        0x50, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 1 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 2 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, \
+        0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 3 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x18, 0x00, \
+        0x28, 0x00, 0x48, 0x00, 0x88, 0x00, 0xFC, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 4 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 5 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x40, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 7 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 8 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x10, 0x00, \
+        0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 9 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* : */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x30, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x60, 0x00, 0x40, 0x00, 0x00, 0x00, /* ; */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, \
+        0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* < */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* = */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* > */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x48, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ? */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, \
+        0x42, 0x00, 0x9A, 0x00, 0xAA, 0x00, 0xAA, 0x00, 0xBE, 0x00, \
+        0x80, 0x00, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, /* @ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, \
+        0x28, 0x00, 0x44, 0x00, 0x7C, 0x00, 0x44, 0x00, 0x44, 0x00, \
+        0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* A */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* B */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x40, 0x00, \
+        0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* C */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x88, 0x00, \
+        0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* D */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* E */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* F */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x40, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x9C, 0x00, 0x84, 0x00, 0x44, 0x00, \
+        0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* G */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* H */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* I */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* J */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x88, 0x00, \
+        0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* K */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* L */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xCC, 0x00, \
+        0xCC, 0x00, 0xB4, 0x00, 0xB4, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* M */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0xC4, 0x00, \
+        0xC4, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0x94, 0x00, 0x94, 0x00, \
+        0x8C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* N */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* O */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* P */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x78, 0x00, 0x20, 0x00, 0x18, 0x00, 0x00, 0x00, /* Q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* R */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x60, 0x00, 0x18, 0x00, 0x04, 0x00, 0x04, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* S */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* T */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* U */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* V */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xA8, 0x00, \
+        0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+        0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* W */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* X */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x04, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, \
+        0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* Z */ \
+        0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x40, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
+        0x40, 0x00, 0x40, 0x00, 0x70, 0x00, 0x00, 0x00, /* [ */ \
+        0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* \ */ \
+        0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x38, 0x00, 0x00, 0x00, /* ] */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x28, 0x00, 0x44, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* _ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ` */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x70, 0x00, 0x08, 0x00, 0x08, 0x00, 0x78, 0x00, 0x88, 0x00, \
+        0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* a */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xF8, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c */ \
+        0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00, 0x04, 0x00, \
+        0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x8C, 0x00, \
+        0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* d */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x84, 0x00, 0xFC, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* e */ \
+        0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* f */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x7C, 0x00, 0x04, 0x00, 0x78, 0x00, 0x00, 0x00, /* g */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* h */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, \
+        0x70, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* i */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, /* j */ \
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x88, 0x00, 0x90, 0x00, 0xA0, 0x00, 0xD0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* k */ \
+        0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* l */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xA4, 0x00, 0xFC, 0x00, 0xA4, 0x00, 0xA4, 0x00, 0xA4, 0x00, \
+        0xA4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* m */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* n */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* o */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xB8, 0x00, 0xC4, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0xF8, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* p */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x7C, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x84, 0x00, \
+        0x7C, 0x00, 0x04, 0x00, 0x04, 0x00, 0x00, 0x00, /* q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xD8, 0x00, 0x60, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, \
+        0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* r */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x80, 0x00, 0x40, 0x00, 0x30, 0x00, 0x08, 0x00, \
+        0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* s */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
+        0xFC, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* t */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x7C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* u */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, \
+        0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* v */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
+        0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* w */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, 0x50, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* x */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x84, 0x00, 0x84, 0x00, 0x48, 0x00, 0x48, 0x00, 0x30, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x00, 0x00, /* y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* z */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x10, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* { */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, /* | */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x10, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, /* } */ \
+    };
 #elif defined(USE_FONT_MONO_MMM_10x12)
 /** Width of each glyph, including spacer column. */
 #  define SYSFONT_WIDTH           10
@@ -767,291 +769,292 @@
 /** Define variable containing the font */
 #  define SYSFONT_DEFINE_GLYPHS \
         /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
-	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
-		/* "MonoMMM" font (http://www.dafont.com/monommm-5.font) size 10x12 */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /*   */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* ! */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x50, 0x00, \
-		0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* " */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0xF8, 0x00, \
-		0x50, 0x00, 0xF8, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* # */	\
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x70, 0x00, 0xA8, 0x00, \
-		0xA0, 0x00, 0x70, 0x00, 0x28, 0x00, 0xA8, 0x00, 0x70, 0x00, \
-		0x20, 0x00, 0x00, 0x00, /* $ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x00, 0xB0, 0x00, \
-		0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0x68, 0x00, 0x98, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* % */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x90, 0x00, \
-		0xA0, 0x00, 0x40, 0x00, 0xA8, 0x00, 0x90, 0x00, 0x68, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* & */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* ' */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x10, 0x00, 0x00, 0x00, /* ( */	\
-		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x40, 0x00, 0x00, 0x00, /* ) */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xF8, 0x00, \
-		0x70, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* * */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* + */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x40, 0x00, /* , */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* - */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* . */	\
-		0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x60, 0x00, 0x40, 0x00, \
-		0xC0, 0x00, 0x00, 0x00, /* / */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x98, 0x00, 0xA8, 0x00, 0xC8, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 0 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xE0, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 1 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 2 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 3 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
-		0x50, 0x00, 0x90, 0x00, 0xF8, 0x00, 0x10, 0x00, 0x10, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 4 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
-		0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 5 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 6 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 7 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 8 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* 9 */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* : */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x40, 0x00, /* ; */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, \
-		0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* < */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* = */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, \
-		0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* > */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* ? */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0xB8, 0x00, 0xA8, 0x00, 0xB8, 0x00, 0x80, 0x00, 0x78, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* @ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* A */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* B */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* C */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* D */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* E */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* F */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x80, 0x00, 0x98, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* G */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* H */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* I */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* J */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0xB0, 0x00, \
-		0xE0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0xB0, 0x00, 0x98, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* K */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* L */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xD8, 0x00, \
-		0xF8, 0x00, 0xA8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* M */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xC8, 0x00, \
-		0xC8, 0x00, 0xA8, 0x00, 0x98, 0x00, 0x98, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* N */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* O */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* P */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xA8, 0x00, 0x70, 0x00, \
-		0x08, 0x00, 0x00, 0x00, /* Q */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* R */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
-		0x80, 0x00, 0x70, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* S */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* T */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* U */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* V */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* W */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
-		0x70, 0x00, 0x20, 0x00, 0x70, 0x00, 0x50, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* X */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
-		0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* Y */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
-		0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* Z */	\
-		0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x30, 0x00, 0x00, 0x00, /* [ */	\
-		0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x40, 0x00, 0x60, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x04, 0x00, 0x00, 0x00, /* \ */	\
-		0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x60, 0x00, 0x00, 0x00, /* ] */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x00, \
-		0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* ^ */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0xFC, 0x00, /* _ */	\
-		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* ` */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF0, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x88, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* a */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* b */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x70, 0x00, 0x88, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* c */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
-		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* d */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x70, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x78, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* e */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x20, 0x00, \
-		0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* f */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
-		0x08, 0x00, 0x70, 0x00, /* g */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* h */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0x60, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* i */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
-		0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0xC0, 0x00, /* j */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x98, 0x00, 0xA0, 0x00, 0xE0, 0x00, 0x90, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* k */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* l */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* m */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* n */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* o */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
-		0x80, 0x00, 0x80, 0x00, /* p */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
-		0x08, 0x00, 0x08, 0x00, /* q */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0x88, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* r */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0x80, 0x00, 0xF8, 0x00, 0x08, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* s */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x78, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x18, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* t */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* u */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* v */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* w */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xD8, 0x00, 0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0xD8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* x */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
-		0x08, 0x00, 0x70, 0x00, /* y */	\
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
-		0xF8, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
-		0x00, 0x00, 0x00, 0x00, /* z */	\
-		0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x10, 0x00, 0x00, 0x00, /* { */	\
-		0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x00, 0x00, /* | */	\
-		0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x20, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
-		0x40, 0x00, 0x00, 0x00, /* } */	\
-	};
+    static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[])=
+    { \
+        /* "MonoMMM" font (http://www.dafont.com/monommm-5.font) size 10x12 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /*   */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* ! */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x50, 0x00, \
+        0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* " */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0xF8, 0x00, \
+        0x50, 0x00, 0xF8, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* # */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x70, 0x00, 0xA8, 0x00, \
+        0xA0, 0x00, 0x70, 0x00, 0x28, 0x00, 0xA8, 0x00, 0x70, 0x00, \
+        0x20, 0x00, 0x00, 0x00, /* $ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC8, 0x00, 0xB0, 0x00, \
+        0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0x68, 0x00, 0x98, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* % */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x90, 0x00, \
+        0xA0, 0x00, 0x40, 0x00, 0xA8, 0x00, 0x90, 0x00, 0x68, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* & */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* ' */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x10, 0x00, 0x00, 0x00, /* ( */ \
+        0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x40, 0x00, 0x00, 0x00, /* ) */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+        0x70, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* * */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0xF8, 0x00, 0x20, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* + */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x40, 0x00, /* , */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* - */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* . */ \
+        0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x10, 0x00, 0x20, 0x00, 0x60, 0x00, 0x40, 0x00, \
+        0xC0, 0x00, 0x00, 0x00, /* / */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x98, 0x00, 0xA8, 0x00, 0xC8, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 0 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0xE0, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 1 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 2 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x30, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 3 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x30, 0x00, \
+        0x50, 0x00, 0x90, 0x00, 0xF8, 0x00, 0x10, 0x00, 0x10, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 4 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+        0xF0, 0x00, 0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 5 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 6 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 7 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 8 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x78, 0x00, 0x08, 0x00, 0x08, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* 9 */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* : */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x40, 0x00, /* ; */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x10, 0x00, \
+        0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x10, 0x00, 0x08, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* < */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* = */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, \
+        0x10, 0x00, 0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* > */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x08, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* ? */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0xB8, 0x00, 0xA8, 0x00, 0xB8, 0x00, 0x80, 0x00, 0x78, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* @ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* A */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* B */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* C */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* D */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* E */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* F */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x80, 0x00, 0x98, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* G */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xF8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* H */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* I */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x08, 0x00, 0x08, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* J */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x98, 0x00, 0xB0, 0x00, \
+        0xE0, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0xB0, 0x00, 0x98, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* K */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* L */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xD8, 0x00, \
+        0xF8, 0x00, 0xA8, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* M */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0xC8, 0x00, \
+        0xC8, 0x00, 0xA8, 0x00, 0x98, 0x00, 0x98, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* N */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* O */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xF0, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* P */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xA8, 0x00, 0x70, 0x00, \
+        0x08, 0x00, 0x00, 0x00, /* Q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* R */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x88, 0x00, \
+        0x80, 0x00, 0x70, 0x00, 0x08, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* S */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* T */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* U */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* V */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x88, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* W */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
+        0x70, 0x00, 0x20, 0x00, 0x70, 0x00, 0x50, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* X */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x00, 0x50, 0x00, \
+        0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* Y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x00, 0x08, 0x00, \
+        0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0x80, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* Z */ \
+        0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x30, 0x00, 0x00, 0x00, /* [ */ \
+        0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0x40, 0x00, 0x60, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x10, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x04, 0x00, 0x00, 0x00, /* \ */ \
+        0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x60, 0x00, 0x00, 0x00, /* ] */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x50, 0x00, \
+        0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* ^ */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0xFC, 0x00, /* _ */ \
+        0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* ` */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF0, 0x00, 0x08, 0x00, 0xF8, 0x00, 0x88, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* a */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* b */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x70, 0x00, 0x88, 0x00, 0x80, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* c */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x00, \
+        0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* d */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x70, 0x00, 0x88, 0x00, 0xF8, 0x00, 0x80, 0x00, 0x78, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* e */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x00, 0x20, 0x00, \
+        0x70, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* f */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+        0x08, 0x00, 0x70, 0x00, /* g */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* h */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0x60, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* i */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, \
+        0xE0, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0xC0, 0x00, /* j */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x98, 0x00, 0xA0, 0x00, 0xE0, 0x00, 0x90, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* k */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* l */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* m */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* n */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x70, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x70, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* o */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF0, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0xF0, 0x00, \
+        0x80, 0x00, 0x80, 0x00, /* p */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x78, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+        0x08, 0x00, 0x08, 0x00, /* q */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0x88, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* r */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0x80, 0x00, 0xF8, 0x00, 0x08, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* s */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x78, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x18, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* t */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* u */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0x50, 0x00, 0x50, 0x00, 0x50, 0x00, 0x20, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* v */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0xA8, 0x00, 0x50, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* w */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xD8, 0x00, 0x50, 0x00, 0x20, 0x00, 0x50, 0x00, 0xD8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* x */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x88, 0x00, 0x78, 0x00, \
+        0x08, 0x00, 0x70, 0x00, /* y */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
+        0xF8, 0x00, 0x10, 0x00, 0x20, 0x00, 0x40, 0x00, 0xF8, 0x00, \
+        0x00, 0x00, 0x00, 0x00, /* z */ \
+        0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x10, 0x00, 0x00, 0x00, /* { */ \
+        0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x00, 0x00, /* | */ \
+        0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x20, 0x00, 0x10, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00, \
+        0x40, 0x00, 0x00, 0x00, /* } */ \
+    };
 #elif defined(USE_FONT_BASIC_6x7)
 /** Width of each glyph, including spacer column. */
 #  define SYSFONT_WIDTH           6
@@ -1067,102 +1070,103 @@
 /** Define variable containing the font */
 #  define SYSFONT_DEFINE_GLYPHS \
         /* Glyph data, row by row, MSB is leftmost pixel, one byte per row. */ \
-	static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[]) = { \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,          /* " " */ \
-		0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x20,          /* "!" */ \
-		0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00,          /* """ */ \
-		0x50, 0x50, 0xf8, 0x50, 0xf8, 0x50, 0x50,          /* "#" */ \
-		0x20, 0x78, 0xa0, 0x70, 0x28, 0xf0, 0x20,          /* "$" */ \
-		0xc0, 0xc8, 0x10, 0x20, 0x40, 0x98, 0x18,          /* "%" */ \
-		0x60, 0x90, 0xa0, 0x40, 0xa8, 0x90, 0x68,          /* "&" */ \
-		0x60, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00,          /* "'" */ \
-		0x10, 0x20, 0x40, 0x40, 0x40, 0x20, 0x10,          /* "(" */ \
-		0x40, 0x20, 0x10, 0x10, 0x10, 0x20, 0x40,          /* ")" */ \
-		0x00, 0x50, 0x20, 0xf8, 0x20, 0x50, 0x00,          /* "*" */ \
-		0x00, 0x20, 0x20, 0xf8, 0x20, 0x20, 0x00,          /* "+" */ \
-		0x00, 0x00, 0x00, 0x00, 0x60, 0x20, 0x40,          /* "," */ \
-		0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00,          /* "-" */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60,          /* "." */ \
-		0x00, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00,          /* "/" */ \
-		0x70, 0x88, 0x98, 0xa8, 0xc8, 0x88, 0x70,          /* "0" */ \
-		0x20, 0x60, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "1" */ \
-		0x70, 0x88, 0x08, 0x10, 0x20, 0x40, 0xf8,          /* "2" */ \
-		0xf8, 0x10, 0x20, 0x10, 0x08, 0x88, 0x70,          /* "3" */ \
-		0x10, 0x30, 0x50, 0x90, 0xf8, 0x10, 0x10,          /* "4" */ \
-		0xf8, 0x80, 0xf0, 0x08, 0x08, 0x88, 0x70,          /* "5" */ \
-		0x30, 0x40, 0x80, 0xf0, 0x88, 0x88, 0x70,          /* "6" */ \
-		0xf8, 0x08, 0x10, 0x20, 0x40, 0x40, 0x40,          /* "7" */ \
-		0x70, 0x88, 0x88, 0x70, 0x88, 0x88, 0x70,          /* "8" */ \
-		0x70, 0x88, 0x88, 0x78, 0x08, 0x10, 0x60,          /* "9" */ \
-		0x00, 0x60, 0x60, 0x00, 0x60, 0x60, 0x00,          /* ":" */ \
-		0x00, 0x60, 0x60, 0x00, 0x60, 0x20, 0x40,          /* ";" */ \
-		0x08, 0x10, 0x20, 0x40, 0x20, 0x10, 0x08,          /* "<" */ \
-		0x00, 0x00, 0xf8, 0x00, 0xf8, 0x00, 0x00,          /* "=" */ \
-		0x80, 0x40, 0x20, 0x10, 0x20, 0x40, 0x80,          /* ">" */ \
-		0x70, 0x88, 0x08, 0x10, 0x20, 0x00, 0x20,          /* "?" */ \
-		0x70, 0x88, 0x08, 0x68, 0xa8, 0xa8, 0x70,          /* "@" */ \
-		0x70, 0x88, 0x88, 0x88, 0xf8, 0x88, 0x88,          /* "A" */ \
-		0xf0, 0x88, 0x88, 0xf0, 0x88, 0x88, 0xf0,          /* "B" */ \
-		0x70, 0x88, 0x80, 0x80, 0x80, 0x88, 0x70,          /* "C" */ \
-		0xe0, 0x90, 0x88, 0x88, 0x88, 0x90, 0xe0,          /* "D" */ \
-		0xf8, 0x80, 0x80, 0xf0, 0x80, 0x80, 0xf8,          /* "E" */ \
-		0xf8, 0x80, 0x80, 0xe0, 0x80, 0x80, 0x80,          /* "F" */ \
-		0x70, 0x88, 0x80, 0x80, 0x98, 0x88, 0x70,          /* "G" */ \
-		0x88, 0x88, 0x88, 0xf8, 0x88, 0x88, 0x88,          /* "H" */ \
-		0x70, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "I" */ \
-		0x38, 0x10, 0x10, 0x10, 0x10, 0x90, 0x60,          /* "J" */ \
-		0x88, 0x90, 0xa0, 0xc0, 0xa0, 0x90, 0x88,          /* "K" */ \
-		0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xf8,          /* "L" */ \
-		0x88, 0xd8, 0xa8, 0x88, 0x88, 0x88, 0x88,          /* "M" */ \
-		0x88, 0x88, 0xc8, 0xa8, 0x98, 0x88, 0x88,          /* "N" */ \
-		0x70, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "O" */ \
-		0xf0, 0x88, 0x88, 0xf0, 0x80, 0x80, 0x80,          /* "P" */ \
-		0x70, 0x88, 0x88, 0x88, 0xa8, 0x90, 0x68,          /* "Q" */ \
-		0xf0, 0x88, 0x88, 0xf0, 0xa0, 0x90, 0x88,          /* "R" */ \
-		0x78, 0x80, 0x80, 0x70, 0x08, 0x08, 0xf0,          /* "S" */ \
-		0xf8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "T" */ \
-		0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "U" */ \
-		0x88, 0x88, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "V" */ \
-		0x88, 0x88, 0x88, 0xa8, 0xa8, 0xd8, 0x88,          /* "W" */ \
-		0x88, 0x88, 0x50, 0x20, 0x50, 0x88, 0x88,          /* "X" */ \
-		0x88, 0x88, 0x50, 0x20, 0x20, 0x20, 0x20,          /* "Y" */ \
-		0xf8, 0x08, 0x10, 0x20, 0x40, 0x80, 0xf8,          /* "Z" */ \
-		0x38, 0x20, 0x20, 0x20, 0x20, 0x20, 0x38,          /* "[" */ \
-		0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x00,          /* "\" */ \
-		0xe0, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe0,          /* "]" */ \
-		0x20, 0x50, 0x88, 0x00, 0x00, 0x00, 0x00,          /* "^" */ \
-		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,          /* "_" */ \
-		0x40, 0x20, 0x10, 0x00, 0x00, 0x00, 0x00,          /* "`" */ \
-		0x00, 0x00, 0x70, 0x08, 0x78, 0x88, 0x78,          /* "a" */ \
-		0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0xf0,          /* "b" */ \
-		0x00, 0x00, 0x70, 0x80, 0x80, 0x88, 0x70,          /* "c" */ \
-		0x08, 0x08, 0x68, 0x98, 0x88, 0x88, 0x78,          /* "d" */ \
-		0x00, 0x00, 0x70, 0x88, 0xf8, 0x80, 0x70,          /* "e" */ \
-		0x30, 0x48, 0x40, 0xe0, 0x40, 0x40, 0x40,          /* "f" */ \
-		0x00, 0x00, 0x78, 0x88, 0x78, 0x08, 0x30,          /* "g" */ \
-		0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "h" */ \
-		0x20, 0x00, 0x60, 0x20, 0x20, 0x20, 0x70,          /* "i" */ \
-		0x10, 0x00, 0x30, 0x10, 0x10, 0x90, 0x60,          /* "j" */ \
-		0x40, 0x40, 0x48, 0x50, 0x60, 0x50, 0x48,          /* "k" */ \
-		0x60, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "l" */ \
-		0x00, 0x00, 0xd0, 0xa8, 0xa8, 0x88, 0x88,          /* "m" */ \
-		0x00, 0x00, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "n" */ \
-		0x00, 0x00, 0x70, 0x88, 0x88, 0x88, 0x70,          /* "o" */ \
-		0x00, 0x00, 0xf0, 0x88, 0xf0, 0x80, 0x80,          /* "p" */ \
-		0x00, 0x00, 0x68, 0x98, 0x78, 0x08, 0x08,          /* "q" */ \
-		0x00, 0x00, 0xb0, 0xc8, 0x80, 0x80, 0x80,          /* "r" */ \
-		0x00, 0x00, 0x70, 0x80, 0x70, 0x08, 0xf0,          /* "s" */ \
-		0x40, 0x40, 0xe0, 0x40, 0x40, 0x48, 0x30,          /* "t" */ \
-		0x00, 0x00, 0x88, 0x88, 0x88, 0x98, 0x68,          /* "u" */ \
-		0x00, 0x00, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "v" */ \
-		0x00, 0x00, 0x88, 0x88, 0xa8, 0xa8, 0x50,          /* "w" */ \
-		0x00, 0x00, 0x88, 0x50, 0x20, 0x50, 0x88,          /* "x" */ \
-		0x00, 0x00, 0x88, 0x88, 0x78, 0x08, 0x70,          /* "y" */ \
-		0x00, 0x00, 0xf8, 0x10, 0x20, 0x40, 0xf8,          /* "z" */ \
-		0x10, 0x20, 0x20, 0x40, 0x20, 0x20, 0x10,          /* "{" */ \
-		0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "|" */ \
-		0x40, 0x20, 0x20, 0x10, 0x20, 0x20, 0x40,          /* "}" */ \
-	};
+    static PROGMEM_DECLARE(uint8_t, sysfont_glyphs[])=
+    { \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,          /* " " */ \
+        0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x20,          /* "!" */ \
+        0x50, 0x50, 0x50, 0x00, 0x00, 0x00, 0x00,          /* """ */ \
+        0x50, 0x50, 0xf8, 0x50, 0xf8, 0x50, 0x50,          /* "#" */ \
+        0x20, 0x78, 0xa0, 0x70, 0x28, 0xf0, 0x20,          /* "$" */ \
+        0xc0, 0xc8, 0x10, 0x20, 0x40, 0x98, 0x18,          /* "%" */ \
+        0x60, 0x90, 0xa0, 0x40, 0xa8, 0x90, 0x68,          /* "&" */ \
+        0x60, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00,          /* "'" */ \
+        0x10, 0x20, 0x40, 0x40, 0x40, 0x20, 0x10,          /* "(" */ \
+        0x40, 0x20, 0x10, 0x10, 0x10, 0x20, 0x40,          /* ")" */ \
+        0x00, 0x50, 0x20, 0xf8, 0x20, 0x50, 0x00,          /* "*" */ \
+        0x00, 0x20, 0x20, 0xf8, 0x20, 0x20, 0x00,          /* "+" */ \
+        0x00, 0x00, 0x00, 0x00, 0x60, 0x20, 0x40,          /* "," */ \
+        0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00,          /* "-" */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60,          /* "." */ \
+        0x00, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00,          /* "/" */ \
+        0x70, 0x88, 0x98, 0xa8, 0xc8, 0x88, 0x70,          /* "0" */ \
+        0x20, 0x60, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "1" */ \
+        0x70, 0x88, 0x08, 0x10, 0x20, 0x40, 0xf8,          /* "2" */ \
+        0xf8, 0x10, 0x20, 0x10, 0x08, 0x88, 0x70,          /* "3" */ \
+        0x10, 0x30, 0x50, 0x90, 0xf8, 0x10, 0x10,          /* "4" */ \
+        0xf8, 0x80, 0xf0, 0x08, 0x08, 0x88, 0x70,          /* "5" */ \
+        0x30, 0x40, 0x80, 0xf0, 0x88, 0x88, 0x70,          /* "6" */ \
+        0xf8, 0x08, 0x10, 0x20, 0x40, 0x40, 0x40,          /* "7" */ \
+        0x70, 0x88, 0x88, 0x70, 0x88, 0x88, 0x70,          /* "8" */ \
+        0x70, 0x88, 0x88, 0x78, 0x08, 0x10, 0x60,          /* "9" */ \
+        0x00, 0x60, 0x60, 0x00, 0x60, 0x60, 0x00,          /* ":" */ \
+        0x00, 0x60, 0x60, 0x00, 0x60, 0x20, 0x40,          /* ";" */ \
+        0x08, 0x10, 0x20, 0x40, 0x20, 0x10, 0x08,          /* "<" */ \
+        0x00, 0x00, 0xf8, 0x00, 0xf8, 0x00, 0x00,          /* "=" */ \
+        0x80, 0x40, 0x20, 0x10, 0x20, 0x40, 0x80,          /* ">" */ \
+        0x70, 0x88, 0x08, 0x10, 0x20, 0x00, 0x20,          /* "?" */ \
+        0x70, 0x88, 0x08, 0x68, 0xa8, 0xa8, 0x70,          /* "@" */ \
+        0x70, 0x88, 0x88, 0x88, 0xf8, 0x88, 0x88,          /* "A" */ \
+        0xf0, 0x88, 0x88, 0xf0, 0x88, 0x88, 0xf0,          /* "B" */ \
+        0x70, 0x88, 0x80, 0x80, 0x80, 0x88, 0x70,          /* "C" */ \
+        0xe0, 0x90, 0x88, 0x88, 0x88, 0x90, 0xe0,          /* "D" */ \
+        0xf8, 0x80, 0x80, 0xf0, 0x80, 0x80, 0xf8,          /* "E" */ \
+        0xf8, 0x80, 0x80, 0xe0, 0x80, 0x80, 0x80,          /* "F" */ \
+        0x70, 0x88, 0x80, 0x80, 0x98, 0x88, 0x70,          /* "G" */ \
+        0x88, 0x88, 0x88, 0xf8, 0x88, 0x88, 0x88,          /* "H" */ \
+        0x70, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "I" */ \
+        0x38, 0x10, 0x10, 0x10, 0x10, 0x90, 0x60,          /* "J" */ \
+        0x88, 0x90, 0xa0, 0xc0, 0xa0, 0x90, 0x88,          /* "K" */ \
+        0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xf8,          /* "L" */ \
+        0x88, 0xd8, 0xa8, 0x88, 0x88, 0x88, 0x88,          /* "M" */ \
+        0x88, 0x88, 0xc8, 0xa8, 0x98, 0x88, 0x88,          /* "N" */ \
+        0x70, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "O" */ \
+        0xf0, 0x88, 0x88, 0xf0, 0x80, 0x80, 0x80,          /* "P" */ \
+        0x70, 0x88, 0x88, 0x88, 0xa8, 0x90, 0x68,          /* "Q" */ \
+        0xf0, 0x88, 0x88, 0xf0, 0xa0, 0x90, 0x88,          /* "R" */ \
+        0x78, 0x80, 0x80, 0x70, 0x08, 0x08, 0xf0,          /* "S" */ \
+        0xf8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "T" */ \
+        0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x70,          /* "U" */ \
+        0x88, 0x88, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "V" */ \
+        0x88, 0x88, 0x88, 0xa8, 0xa8, 0xd8, 0x88,          /* "W" */ \
+        0x88, 0x88, 0x50, 0x20, 0x50, 0x88, 0x88,          /* "X" */ \
+        0x88, 0x88, 0x50, 0x20, 0x20, 0x20, 0x20,          /* "Y" */ \
+        0xf8, 0x08, 0x10, 0x20, 0x40, 0x80, 0xf8,          /* "Z" */ \
+        0x38, 0x20, 0x20, 0x20, 0x20, 0x20, 0x38,          /* "[" */ \
+        0x00, 0x80, 0x40, 0x20, 0x10, 0x08, 0x00,          /* "\" */ \
+        0xe0, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe0,          /* "]" */ \
+        0x20, 0x50, 0x88, 0x00, 0x00, 0x00, 0x00,          /* "^" */ \
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,          /* "_" */ \
+        0x40, 0x20, 0x10, 0x00, 0x00, 0x00, 0x00,          /* "`" */ \
+        0x00, 0x00, 0x70, 0x08, 0x78, 0x88, 0x78,          /* "a" */ \
+        0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0xf0,          /* "b" */ \
+        0x00, 0x00, 0x70, 0x80, 0x80, 0x88, 0x70,          /* "c" */ \
+        0x08, 0x08, 0x68, 0x98, 0x88, 0x88, 0x78,          /* "d" */ \
+        0x00, 0x00, 0x70, 0x88, 0xf8, 0x80, 0x70,          /* "e" */ \
+        0x30, 0x48, 0x40, 0xe0, 0x40, 0x40, 0x40,          /* "f" */ \
+        0x00, 0x00, 0x78, 0x88, 0x78, 0x08, 0x30,          /* "g" */ \
+        0x80, 0x80, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "h" */ \
+        0x20, 0x00, 0x60, 0x20, 0x20, 0x20, 0x70,          /* "i" */ \
+        0x10, 0x00, 0x30, 0x10, 0x10, 0x90, 0x60,          /* "j" */ \
+        0x40, 0x40, 0x48, 0x50, 0x60, 0x50, 0x48,          /* "k" */ \
+        0x60, 0x20, 0x20, 0x20, 0x20, 0x20, 0x70,          /* "l" */ \
+        0x00, 0x00, 0xd0, 0xa8, 0xa8, 0x88, 0x88,          /* "m" */ \
+        0x00, 0x00, 0xb0, 0xc8, 0x88, 0x88, 0x88,          /* "n" */ \
+        0x00, 0x00, 0x70, 0x88, 0x88, 0x88, 0x70,          /* "o" */ \
+        0x00, 0x00, 0xf0, 0x88, 0xf0, 0x80, 0x80,          /* "p" */ \
+        0x00, 0x00, 0x68, 0x98, 0x78, 0x08, 0x08,          /* "q" */ \
+        0x00, 0x00, 0xb0, 0xc8, 0x80, 0x80, 0x80,          /* "r" */ \
+        0x00, 0x00, 0x70, 0x80, 0x70, 0x08, 0xf0,          /* "s" */ \
+        0x40, 0x40, 0xe0, 0x40, 0x40, 0x48, 0x30,          /* "t" */ \
+        0x00, 0x00, 0x88, 0x88, 0x88, 0x98, 0x68,          /* "u" */ \
+        0x00, 0x00, 0x88, 0x88, 0x88, 0x50, 0x20,          /* "v" */ \
+        0x00, 0x00, 0x88, 0x88, 0xa8, 0xa8, 0x50,          /* "w" */ \
+        0x00, 0x00, 0x88, 0x50, 0x20, 0x50, 0x88,          /* "x" */ \
+        0x00, 0x00, 0x88, 0x88, 0x78, 0x08, 0x70,          /* "y" */ \
+        0x00, 0x00, 0xf8, 0x10, 0x20, 0x40, 0xf8,          /* "z" */ \
+        0x10, 0x20, 0x20, 0x40, 0x20, 0x20, 0x10,          /* "{" */ \
+        0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,          /* "|" */ \
+        0x40, 0x20, 0x20, 0x10, 0x20, 0x20, 0x40,          /* "}" */ \
+    };
 #endif
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c
index cd0d0275c448..dac7d2793f90 100644
--- a/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c
+++ b/bsp/samd21/sam_d2x_asflib/common2/services/gfx_mono/sysfont.c
@@ -53,7 +53,7 @@
 #include "gfx_mono.h"
 #include "sysfont.h"
 
-// Use macro from conf_sysfont.h to define font glyph data.
+/* Use macro from conf_sysfont.h to define font glyph data.*/
 SYSFONT_DEFINE_GLYPHS;
 
 /**
@@ -62,14 +62,14 @@ SYSFONT_DEFINE_GLYPHS;
  * This initializes a basic system font globally usable by the application.
  */
 struct font sysfont = {
-	.type           = FONT_LOC_PROGMEM,
-	.width          = SYSFONT_WIDTH,
-	.height         = SYSFONT_HEIGHT,
-	.first_char     = SYSFONT_FIRSTCHAR,
-	.last_char      = SYSFONT_LASTCHAR,
-	.data           = {
-		.progmem        = sysfont_glyphs,
-	},
+    .type           = FONT_LOC_PROGMEM,
+    .width          = SYSFONT_WIDTH,
+    .height         = SYSFONT_HEIGHT,
+    .first_char     = SYSFONT_FIRSTCHAR,
+    .last_char      = SYSFONT_LASTCHAR,
+    .data           = {
+        .progmem        = sysfont_glyphs,
+    },
 };
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h
index 5ea4d98a93be..d357adcd8fa9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/dummy/dummy_board.h
@@ -53,4 +53,4 @@
 #ifndef _DUMMY_BOARD_H_
 #define _DUMMY_BOARD_H_
 
-#endif  // _DUMMY_BOARD_H_
+#endif  /* _DUMMY_BOARD_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c
index 9a2327da50c8..c07342c67d54 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/board_init.c
@@ -58,40 +58,40 @@ void board_init(void);
 
 void system_board_init(void)
 {
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
 
-	/* Configure LEDs as outputs, turn them off */
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(LED_0_PIN, &pin_conf);
-	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+    /* Configure LEDs as outputs, turn them off */
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(LED_0_PIN, &pin_conf);
+    port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
 
-	/* Set buttons as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
+    /* Set buttons as inputs */
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    pin_conf.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(BUTTON_0_PIN, &pin_conf);
 #ifdef CONF_BOARD_AT86RFX
-	port_get_config_defaults(&pin_conf);
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
-	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
-	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
-	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
-	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
-	port_pin_set_output_level(AT86RFX_SPI_CS, true);
-	port_pin_set_output_level(AT86RFX_RST_PIN, true);
-	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
-#ifdef EXT_RF_FRONT_END_CTRL	
-	port_pin_set_config(AT86RFX_CPS, &pin_conf);
-	port_pin_set_output_level(AT86RFX_CPS, HIGH);	
-	port_pin_set_config(AT86RFX_CSD, &pin_conf);
-	port_pin_set_output_level(AT86RFX_CSD, HIGH);	
-#endif		
+    port_get_config_defaults(&pin_conf);
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+    port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+    port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+    port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+    port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+    port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+    port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+    port_pin_set_output_level(AT86RFX_SPI_CS, true);
+    port_pin_set_output_level(AT86RFX_RST_PIN, true);
+    port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+#ifdef EXT_RF_FRONT_END_CTRL
+    port_pin_set_config(AT86RFX_CPS, &pin_conf);
+    port_pin_set_output_level(AT86RFX_CPS, HIGH);
+    port_pin_set_config(AT86RFX_CSD, &pin_conf);
+    port_pin_set_output_level(AT86RFX_CSD, HIGH);
+#endif
+
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
 
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
-	
 #endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h
index e24a7b0ce0d3..7ee249692be6 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd20_xplained_pro/samd20_xplained_pro.h
@@ -113,7 +113,7 @@ void system_board_init(void);
 #define LED_0_PIN                 LED0_PIN
 #define LED_0_ACTIVE              LED0_ACTIVE
 #define LED_0_INACTIVE            LED0_INACTIVE
-#define LED0_GPIO 				  LED0_PIN
+#define LED0_GPIO                 LED0_PIN
 /** @} */
 
 /** Number of on-board LEDs */
@@ -553,27 +553,27 @@ void system_board_init(void);
 
 /** Enables the transceiver main interrupt. */
 #define ENABLE_TRX_IRQ()      \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /** Disables the transceiver main interrupt. */
 #define DISABLE_TRX_IRQ()     \
-		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /** Clears the transceiver main interrupt. */
 #define CLEAR_TRX_IRQ()       \
-		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+        extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
 
 /*
  * This macro saves the trx interrupt status and disables the trx interrupt.
  */
 #define ENTER_TRX_REGION()   \
-		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /*
  *  This macro restores the transceiver interrupt status
  */
 #define LEAVE_TRX_REGION()   \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+        extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
 
 /**
  * \brief Turns off the specified LEDs.
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c
index 66cedb3e4eb8..733b9b1b9699 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/board_init.c
@@ -58,33 +58,33 @@ void board_init(void);
 
 void system_board_init(void)
 {
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
 
-	/* Configure LEDs as outputs, turn them off */
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(LED_0_PIN, &pin_conf);
-	port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+    /* Configure LEDs as outputs, turn them off */
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(LED_0_PIN, &pin_conf);
+    port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
+
+    /* Set buttons as inputs */
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    pin_conf.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(BUTTON_0_PIN, &pin_conf);
 
-	/* Set buttons as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-	port_pin_set_config(BUTTON_0_PIN, &pin_conf);
-	
 #ifdef CONF_BOARD_AT86RFX
-	port_get_config_defaults(&pin_conf);
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
-	port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
-	port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
-	port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
-	port_pin_set_output_level(AT86RFX_SPI_SCK, true);
-	port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
-	port_pin_set_output_level(AT86RFX_SPI_CS, true);
-	port_pin_set_output_level(AT86RFX_RST_PIN, true);
-	port_pin_set_output_level(AT86RFX_SLP_PIN, true);
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
-#endif	
+    port_get_config_defaults(&pin_conf);
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
+    port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
+    port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
+    port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
+    port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
+    port_pin_set_output_level(AT86RFX_SPI_SCK, true);
+    port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
+    port_pin_set_output_level(AT86RFX_SPI_CS, true);
+    port_pin_set_output_level(AT86RFX_RST_PIN, true);
+    port_pin_set_output_level(AT86RFX_SLP_PIN, true);
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
+#endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
index 39e611773c28..90818e5d9833 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h
@@ -649,27 +649,27 @@ void system_board_init(void);
 #endif
 /** Enables the transceiver main interrupt. */
 #define ENABLE_TRX_IRQ()     \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /** Disables the transceiver main interrupt. */
 #define DISABLE_TRX_IRQ()    \
-		extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /** Clears the transceiver main interrupt. */
 #define CLEAR_TRX_IRQ()      \
-		extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
+        extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
 
 /*
  * This macro saves the trx interrupt status and disables the trx interrupt.
  */
 #define ENTER_TRX_REGION()   \
-		{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
+        { extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
 
 /*
  *  This macro restores the transceiver interrupt status
  */
 #define LEAVE_TRX_REGION()   \
-		extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
+        extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h
index 1003b9308876..954d070c2a23 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac.h
@@ -143,7 +143,7 @@
  * channel (note that these names refer to the logical operation that the unit
  * performs, and both voltages should be above GND), which are then compared with
  * one another. Both the positive and the negative channel inputs are connected to
- * a pair of multiplexers (MUXes), which allows one of several possible inputs to be 
+ * a pair of multiplexers (MUXes), which allows one of several possible inputs to be
  * selected for each comparator channel.
  *
  * The exact channels available for each comparator differ for the positive and
@@ -317,10 +317,10 @@ extern "C" {
 #endif
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
- 	/** Run in standby feature for each comparator */
+    /** Run in standby feature for each comparator */
 #  define FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
 #else
- 	/** Run in standby feature for comparator pair */
+    /** Run in standby feature for comparator pair */
 #  define FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
 #endif
 /* @} */
@@ -386,37 +386,37 @@ typedef void (*ac_callback_t)(struct ac_module *const module_inst);
 
 /** Enum for possible callback types for the AC module. */
 enum ac_callback {
-	/** Callback for comparator 0 */
-	AC_CALLBACK_COMPARATOR_0 = 0,
-	/** Callback for comparator 1 */
-	AC_CALLBACK_COMPARATOR_1 = 1,
-	/** Callback for window 0 */
-	AC_CALLBACK_WINDOW_0     = 4,
+    /** Callback for comparator 0 */
+    AC_CALLBACK_COMPARATOR_0 = 0,
+    /** Callback for comparator 1 */
+    AC_CALLBACK_COMPARATOR_1 = 1,
+    /** Callback for window 0 */
+    AC_CALLBACK_WINDOW_0     = 4,
 #if (AC_NUM_CMP > 2)
-	/** Callback for comparator 2 */
-	AC_CALLBACK_COMPARATOR_2 = 2,
-	/** Callback for comparator 3 */
-	AC_CALLBACK_COMPARATOR_3 = 3,
-	/** Callback for window 1 */
-	AC_CALLBACK_WINDOW_1     = 5,
-	/** Number of available callbacks */
+    /** Callback for comparator 2 */
+    AC_CALLBACK_COMPARATOR_2 = 2,
+    /** Callback for comparator 3 */
+    AC_CALLBACK_COMPARATOR_3 = 3,
+    /** Callback for window 1 */
+    AC_CALLBACK_WINDOW_1     = 5,
+    /** Number of available callbacks */
 #endif /* (AC_NUM_CMP == 2) */
 #if !defined(__DOXYGEN__)
-	AC_CALLBACK_N,
+    AC_CALLBACK_N,
 #endif /* !defined(__DOXYGEN__) */
 };
 
 #ifdef FEATURE_AC_HYSTERESIS_LEVEL
 /** Enum for possible hysteresis level types for AC module. */
 enum ac_hysteresis_level {
-	/** Hysteresis level of 50mV */
-	AC_HYSTERESIS_LEVEL_50 = 0,
-	/** Hysteresis level of 70mV */
-	AC_HYSTERESIS_LEVEL_70,
-	/** Hysteresis level of 90mV */
-	AC_HYSTERESIS_LEVEL_90,
-	/** Hysteresis level of 110mV */
-	AC_HYSTERESIS_LEVEL_110
+    /** Hysteresis level of 50mV */
+    AC_HYSTERESIS_LEVEL_50 = 0,
+    /** Hysteresis level of 70mV */
+    AC_HYSTERESIS_LEVEL_70,
+    /** Hysteresis level of 90mV */
+    AC_HYSTERESIS_LEVEL_90,
+    /** Hysteresis level of 110mV */
+    AC_HYSTERESIS_LEVEL_110
 };
 #endif
 
@@ -426,15 +426,15 @@ enum ac_hysteresis_level {
  * Enum for the possible comparator channels.
  */
 enum ac_chan_channel {
-	/** Comparator channel 0 (Pair 0, Comparator 0) */
-	AC_CHAN_CHANNEL_0 = 0,
-	/** Comparator channel 1 (Pair 0, Comparator 1) */
-	AC_CHAN_CHANNEL_1 = 1,
+    /** Comparator channel 0 (Pair 0, Comparator 0) */
+    AC_CHAN_CHANNEL_0 = 0,
+    /** Comparator channel 1 (Pair 0, Comparator 1) */
+    AC_CHAN_CHANNEL_1 = 1,
 #if defined(__DOXYGEN__) || (AC_NUM_CMP > 2)
-	/** Comparator channel 2 (Pair 1, Comparator 0) */
-	AC_CHAN_CHANNEL_2 = 2,
-	/** Comparator channel 3 (Pair 1, Comparator 1) */
-	AC_CHAN_CHANNEL_3 = 3,
+    /** Comparator channel 2 (Pair 1, Comparator 0) */
+    AC_CHAN_CHANNEL_2 = 2,
+    /** Comparator channel 3 (Pair 1, Comparator 1) */
+    AC_CHAN_CHANNEL_3 = 3,
 #endif
 };
 
@@ -444,12 +444,12 @@ enum ac_chan_channel {
  * Enum for the possible channel sampling modes of an Analog Comparator channel.
  */
 enum ac_chan_sample_mode {
-	/** Continuous sampling mode; when the channel is enabled the comparator
-	 *  output is available for reading at any time */
-	AC_CHAN_MODE_CONTINUOUS    = 0,
-	/** Single shot mode; when used the comparator channel must be triggered to
-	 *  perform a comparison before reading the result */
-	AC_CHAN_MODE_SINGLE_SHOT   = AC_COMPCTRL_SINGLE,
+    /** Continuous sampling mode; when the channel is enabled the comparator
+     *  output is available for reading at any time */
+    AC_CHAN_MODE_CONTINUOUS    = 0,
+    /** Single shot mode; when used the comparator channel must be triggered to
+     *  perform a comparison before reading the result */
+    AC_CHAN_MODE_SINGLE_SHOT   = AC_COMPCTRL_SINGLE,
 };
 
 /**
@@ -459,14 +459,14 @@ enum ac_chan_sample_mode {
  * channel.
  */
 enum ac_chan_pos_mux {
-	/** Positive comparator input is connected to physical AC input pin 0 */
-	AC_CHAN_POS_MUX_PIN0       = AC_COMPCTRL_MUXPOS_PIN0,
-	/** Positive comparator input is connected to physical AC input pin 1 */
-	AC_CHAN_POS_MUX_PIN1       = AC_COMPCTRL_MUXPOS_PIN1,
-	/** Positive comparator input is connected to physical AC input pin 2 */
-	AC_CHAN_POS_MUX_PIN2       = AC_COMPCTRL_MUXPOS_PIN2,
-	/** Positive comparator input is connected to physical AC input pin 3 */
-	AC_CHAN_POS_MUX_PIN3       = AC_COMPCTRL_MUXPOS_PIN3,
+    /** Positive comparator input is connected to physical AC input pin 0 */
+    AC_CHAN_POS_MUX_PIN0       = AC_COMPCTRL_MUXPOS_PIN0,
+    /** Positive comparator input is connected to physical AC input pin 1 */
+    AC_CHAN_POS_MUX_PIN1       = AC_COMPCTRL_MUXPOS_PIN1,
+    /** Positive comparator input is connected to physical AC input pin 2 */
+    AC_CHAN_POS_MUX_PIN2       = AC_COMPCTRL_MUXPOS_PIN2,
+    /** Positive comparator input is connected to physical AC input pin 3 */
+    AC_CHAN_POS_MUX_PIN3       = AC_COMPCTRL_MUXPOS_PIN3,
 };
 
 /**
@@ -476,32 +476,32 @@ enum ac_chan_pos_mux {
  * channel.
  */
 enum ac_chan_neg_mux {
-	/** Negative comparator input is connected to physical AC input pin 0 */
-	AC_CHAN_NEG_MUX_PIN0       = AC_COMPCTRL_MUXNEG_PIN0,
-	/** Negative comparator input is connected to physical AC input pin 1 */
-	AC_CHAN_NEG_MUX_PIN1       = AC_COMPCTRL_MUXNEG_PIN1,
-	/** Negative comparator input is connected to physical AC input pin 2 */
-	AC_CHAN_NEG_MUX_PIN2       = AC_COMPCTRL_MUXNEG_PIN2,
-	/** Negative comparator input is connected to physical AC input pin 3 */
-	AC_CHAN_NEG_MUX_PIN3       = AC_COMPCTRL_MUXNEG_PIN3,
-	/** Negative comparator input is connected to the internal ground plane */
-	AC_CHAN_NEG_MUX_GND        = AC_COMPCTRL_MUXNEG_GND,
-	/** Negative comparator input is connected to the channel's internal V<SUB>CC</SUB>
-	 *  plane voltage scalar */
-	AC_CHAN_NEG_MUX_SCALED_VCC = AC_COMPCTRL_MUXNEG_VSCALE,
-	/** Negative comparator input is connected to the internal band gap voltage
-	 *  reference */
-	AC_CHAN_NEG_MUX_BANDGAP    = AC_COMPCTRL_MUXNEG_BANDGAP,
+    /** Negative comparator input is connected to physical AC input pin 0 */
+    AC_CHAN_NEG_MUX_PIN0       = AC_COMPCTRL_MUXNEG_PIN0,
+    /** Negative comparator input is connected to physical AC input pin 1 */
+    AC_CHAN_NEG_MUX_PIN1       = AC_COMPCTRL_MUXNEG_PIN1,
+    /** Negative comparator input is connected to physical AC input pin 2 */
+    AC_CHAN_NEG_MUX_PIN2       = AC_COMPCTRL_MUXNEG_PIN2,
+    /** Negative comparator input is connected to physical AC input pin 3 */
+    AC_CHAN_NEG_MUX_PIN3       = AC_COMPCTRL_MUXNEG_PIN3,
+    /** Negative comparator input is connected to the internal ground plane */
+    AC_CHAN_NEG_MUX_GND        = AC_COMPCTRL_MUXNEG_GND,
+    /** Negative comparator input is connected to the channel's internal V<SUB>CC</SUB>
+     *  plane voltage scalar */
+    AC_CHAN_NEG_MUX_SCALED_VCC = AC_COMPCTRL_MUXNEG_VSCALE,
+    /** Negative comparator input is connected to the internal band gap voltage
+     *  reference */
+    AC_CHAN_NEG_MUX_BANDGAP    = AC_COMPCTRL_MUXNEG_BANDGAP,
 #if !(SAML22)
-	/**
-	 * For SAM D20/D21/D10/D11/R21/DA1/HA1:
-	 *     Negative comparator input is connected to the channel's internal DAC
-	 *     channel 0 output.
-	 * For SAM L21/C20/C21:
-	 *     Negative comparator input is connected to the channel's internal DAC
-	 *     channel 0 output for Comparator 0 or OPAMP output for Comparator 1.
-	 */
-	AC_CHAN_NEG_MUX_DAC0       = AC_COMPCTRL_MUXNEG_DAC,
+    /**
+     * For SAM D20/D21/D10/D11/R21/DA1/HA1:
+     *     Negative comparator input is connected to the channel's internal DAC
+     *     channel 0 output.
+     * For SAM L21/C20/C21:
+     *     Negative comparator input is connected to the channel's internal DAC
+     *     channel 0 output for Comparator 0 or OPAMP output for Comparator 1.
+     */
+    AC_CHAN_NEG_MUX_DAC0       = AC_COMPCTRL_MUXNEG_DAC,
 #endif
 };
 
@@ -512,14 +512,14 @@ enum ac_chan_neg_mux {
  * Comparator channel.
  */
 enum ac_chan_filter {
-	/** No output filtering is performed on the comparator channel */
-	AC_CHAN_FILTER_NONE        = AC_COMPCTRL_FLEN_OFF,
-	/** Comparator channel output is passed through a Majority-of-Three
-	 *  filter */
-	AC_CHAN_FILTER_MAJORITY_3  = AC_COMPCTRL_FLEN_MAJ3,
-	/** Comparator channel output is passed through a Majority-of-Five
-	 *  filter */
-	AC_CHAN_FILTER_MAJORITY_5  = AC_COMPCTRL_FLEN_MAJ5,
+    /** No output filtering is performed on the comparator channel */
+    AC_CHAN_FILTER_NONE        = AC_COMPCTRL_FLEN_OFF,
+    /** Comparator channel output is passed through a Majority-of-Three
+     *  filter */
+    AC_CHAN_FILTER_MAJORITY_3  = AC_COMPCTRL_FLEN_MAJ3,
+    /** Comparator channel output is passed through a Majority-of-Five
+     *  filter */
+    AC_CHAN_FILTER_MAJORITY_5  = AC_COMPCTRL_FLEN_MAJ5,
 };
 
 /**
@@ -529,15 +529,15 @@ enum ac_chan_filter {
  * Comparator channel.
  */
 enum ac_chan_output {
-	/** Comparator channel output is not routed to a physical GPIO pin, and is
-	 *  used internally only */
-	AC_CHAN_OUTPUT_INTERNAL    = AC_COMPCTRL_OUT_OFF,
-	/** Comparator channel output is routed to its matching physical GPIO pin,
-	 *  via an asynchronous path */
-	AC_CHAN_OUTPUT_ASYNCRONOUS = AC_COMPCTRL_OUT_ASYNC,
-	/** Comparator channel output is routed to its matching physical GPIO pin,
-	 *  via a synchronous path */
-	AC_CHAN_OUTPUT_SYNCHRONOUS = AC_COMPCTRL_OUT_SYNC,
+    /** Comparator channel output is not routed to a physical GPIO pin, and is
+     *  used internally only */
+    AC_CHAN_OUTPUT_INTERNAL    = AC_COMPCTRL_OUT_OFF,
+    /** Comparator channel output is routed to its matching physical GPIO pin,
+     *  via an asynchronous path */
+    AC_CHAN_OUTPUT_ASYNCRONOUS = AC_COMPCTRL_OUT_ASYNC,
+    /** Comparator channel output is routed to its matching physical GPIO pin,
+     *  via a synchronous path */
+    AC_CHAN_OUTPUT_SYNCHRONOUS = AC_COMPCTRL_OUT_SYNC,
 };
 
 /**
@@ -546,11 +546,11 @@ enum ac_chan_output {
  * Enum for the possible window comparator channels.
  */
 enum ac_win_channel {
-	/** Window channel 0 (Pair 0, Comparators 0 and 1) */
-	AC_WIN_CHANNEL_0 = 0,
+    /** Window channel 0 (Pair 0, Comparators 0 and 1) */
+    AC_WIN_CHANNEL_0 = 0,
 #if defined(__DOXYGEN__) || (AC_PAIRS > 1)
-	/** Window channel 1 (Pair 1, Comparators 2 and 3) */
-	AC_WIN_CHANNEL_1 = 1,
+    /** Window channel 1 (Pair 1, Comparators 2 and 3) */
+    AC_WIN_CHANNEL_1 = 1,
 #endif
 };
 
@@ -560,22 +560,22 @@ enum ac_win_channel {
  * This enum is used to select when a channel interrupt should occur.
  */
 enum ac_chan_interrupt_selection {
-	/** An interrupt will be generated when the comparator level is passed */
-	AC_CHAN_INTERRUPT_SELECTION_TOGGLE          = AC_COMPCTRL_INTSEL_TOGGLE,
-	/** An interrupt will be generated when the measurement goes above the
-	 *  compare level
-	 */
-	AC_CHAN_INTERRUPT_SELECTION_RISING          = AC_COMPCTRL_INTSEL_RISING,
-	/** An interrupt will be generated when the measurement goes below the
-	 *  compare level
-	 */
-	AC_CHAN_INTERRUPT_SELECTION_FALLING         = AC_COMPCTRL_INTSEL_FALLING,
-	/**
-	 * An interrupt will be generated when a new measurement is complete.
-	 * Interrupts will only be generated in single shot mode. This state needs
-	 * to be cleared by the use of ac_chan_cleare_status()
-	 */
-	AC_CHAN_INTERRUPT_SELECTION_END_OF_COMPARE  = AC_COMPCTRL_INTSEL_EOC,
+    /** An interrupt will be generated when the comparator level is passed */
+    AC_CHAN_INTERRUPT_SELECTION_TOGGLE          = AC_COMPCTRL_INTSEL_TOGGLE,
+    /** An interrupt will be generated when the measurement goes above the
+     *  compare level
+     */
+    AC_CHAN_INTERRUPT_SELECTION_RISING          = AC_COMPCTRL_INTSEL_RISING,
+    /** An interrupt will be generated when the measurement goes below the
+     *  compare level
+     */
+    AC_CHAN_INTERRUPT_SELECTION_FALLING         = AC_COMPCTRL_INTSEL_FALLING,
+    /**
+     * An interrupt will be generated when a new measurement is complete.
+     * Interrupts will only be generated in single shot mode. This state needs
+     * to be cleared by the use of ac_chan_cleare_status()
+     */
+    AC_CHAN_INTERRUPT_SELECTION_END_OF_COMPARE  = AC_COMPCTRL_INTSEL_EOC,
 };
 
 /**
@@ -584,14 +584,14 @@ enum ac_chan_interrupt_selection {
  * This enum is used to select when a window interrupt should occur.
  */
 enum ac_win_interrupt_selection {
-	/** Interrupt is generated when the compare value goes above the window */
-	AC_WIN_INTERRUPT_SELECTION_ABOVE    = AC_WINCTRL_WINTSEL0_ABOVE,
-	/** Interrupt is generated when the compare value goes inside the window */
-	AC_WIN_INTERRUPT_SELECTION_INSIDE   = AC_WINCTRL_WINTSEL0_INSIDE,
-	/** Interrupt is generated when the compare value goes below the window */
-	AC_WIN_INTERRUPT_SELECTION_BELOW    = AC_WINCTRL_WINTSEL0_BELOW,
-	/** Interrupt is generated when the compare value goes outside the window */
-	AC_WIN_INTERRUPT_SELECTION_OUTSIDE  = AC_WINCTRL_WINTSEL0_OUTSIDE,
+    /** Interrupt is generated when the compare value goes above the window */
+    AC_WIN_INTERRUPT_SELECTION_ABOVE    = AC_WINCTRL_WINTSEL0_ABOVE,
+    /** Interrupt is generated when the compare value goes inside the window */
+    AC_WIN_INTERRUPT_SELECTION_INSIDE   = AC_WINCTRL_WINTSEL0_INSIDE,
+    /** Interrupt is generated when the compare value goes below the window */
+    AC_WIN_INTERRUPT_SELECTION_BELOW    = AC_WINCTRL_WINTSEL0_BELOW,
+    /** Interrupt is generated when the compare value goes outside the window */
+    AC_WIN_INTERRUPT_SELECTION_OUTSIDE  = AC_WINCTRL_WINTSEL0_OUTSIDE,
 };
 
 /**
@@ -605,15 +605,15 @@ enum ac_win_interrupt_selection {
  */
 struct ac_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware module pointer of the associated Analog Comparator peripheral. */
-	Ac *hw;
+    /** Hardware module pointer of the associated Analog Comparator peripheral. */
+    Ac *hw;
 #  if AC_CALLBACK_MODE == true
-	/** Array of callbacks */
-	ac_callback_t callback[AC_CALLBACK_N];
-	/** Bit mask for callbacks registered */
-	uint8_t register_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enable_callback_mask;
+    /** Array of callbacks */
+    ac_callback_t callback[AC_CALLBACK_N];
+    /** Bit mask for callbacks registered */
+    uint8_t register_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enable_callback_mask;
 #  endif
 #endif
 };
@@ -625,17 +625,17 @@ struct ac_module {
  * disable events via \ref ac_enable_events() and \ref ac_disable_events().
  */
 struct ac_events {
-	/** If \c true, an event will be generated when a comparator window state
-	 *  changes */
-	bool generate_event_on_window[AC_PAIRS];
+    /** If \c true, an event will be generated when a comparator window state
+     *  changes */
+    bool generate_event_on_window[AC_PAIRS];
 
-	/** If \c true, an event will be generated when a comparator state
-	 *  changes */
-	bool generate_event_on_state[AC_NUM_CMP];
+    /** If \c true, an event will be generated when a comparator state
+     *  changes */
+    bool generate_event_on_state[AC_NUM_CMP];
 
-	/** If \c true, a comparator will be sampled each time an event is
-	 *  received */
-	bool on_event_sample[AC_NUM_CMP];
+    /** If \c true, a comparator will be sampled each time an event is
+     *  received */
+    bool on_event_sample[AC_NUM_CMP];
 };
 
 /**
@@ -646,19 +646,19 @@ struct ac_events {
  */
 struct ac_config {
 #ifdef FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
-	/** If \c true, the comparator pairs will continue to sample during sleep
-	 *  mode when triggered */
-	bool run_in_standby[AC_PAIRS];
+    /** If \c true, the comparator pairs will continue to sample during sleep
+     *  mode when triggered */
+    bool run_in_standby[AC_PAIRS];
 #endif
 
 #if (SAMD) || (SAMHA1) || (SAMR21)
-	/** Digital source generator for AC GCLK */
-	enum gclk_generator dig_source_generator;
-	/** Analog source generator for AC GCLK */
-	enum gclk_generator ana_source_generator;
+    /** Digital source generator for AC GCLK */
+    enum gclk_generator dig_source_generator;
+    /** Analog source generator for AC GCLK */
+    enum gclk_generator ana_source_generator;
 #else
-	/** Source generator for AC GCLK */
-	enum gclk_generator source_generator;
+    /** Source generator for AC GCLK */
+    enum gclk_generator source_generator;
 #endif
 };
 
@@ -669,51 +669,51 @@ struct ac_config {
  *  output settings of the comparator.
  */
 struct ac_chan_config {
-	/** Sampling mode of the comparator channel */
-	enum ac_chan_sample_mode sample_mode;
-	/** Filtering mode for the comparator output, when the comparator is used
-	 *  in a supported mode */
-	enum ac_chan_filter filter;
-	/** When \c true, hysteresis mode is enabled on the comparator inputs */
-	bool enable_hysteresis;
+    /** Sampling mode of the comparator channel */
+    enum ac_chan_sample_mode sample_mode;
+    /** Filtering mode for the comparator output, when the comparator is used
+     *  in a supported mode */
+    enum ac_chan_filter filter;
+    /** When \c true, hysteresis mode is enabled on the comparator inputs */
+    bool enable_hysteresis;
 #ifdef FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
-	/** If \c true, the comparator will continue to sample during sleep
-	 *  mode when triggered */
-	bool run_in_standby;
+    /** If \c true, the comparator will continue to sample during sleep
+     *  mode when triggered */
+    bool run_in_standby;
 #endif
 #ifdef FEATURE_AC_HYSTERESIS_LEVEL
-	/** Hysteresis level of the comparator channel */
-	enum ac_hysteresis_level hysteresis_level;
+    /** Hysteresis level of the comparator channel */
+    enum ac_hysteresis_level hysteresis_level;
 #endif
-	/** Output mode of the comparator, whether it should be available for
-	 *  internal use, or asynchronously/synchronously linked to a 
-	 *  general-purpose input/output (GPIO) pin */
-	enum ac_chan_output output_mode;
-	/** Input multiplexer selection for the comparator's positive input pin */
-	enum ac_chan_pos_mux positive_input;
-	/** Input multiplexer selection for the comparator's negative input pin.
-	 *  Any internal reference source, such as a bandgap reference voltage or
-	 *  the DAC, must be configured and enabled prior to its use as a
-	 *  comparator input.*/
-	enum ac_chan_neg_mux negative_input;
-	/** Scaled VCC voltage division factor for the channel, when a comparator
-	 *  pin is connected to the V<SUB>CC</SUB> voltage scalar input. The formular is:
-	 *      Vscale = Vdd * vcc_scale_factor / 64.
-	 *  If the V<SUB>CC</SUB> voltage scalar is not selected as a comparator
-	 *  channel pin's input, this value will be ignored. */
-	uint8_t vcc_scale_factor;
-	/** Interrupt criteria for the comparator channel, to select the condition
-	 *  that will trigger a callback */
-	enum ac_chan_interrupt_selection interrupt_selection;
+    /** Output mode of the comparator, whether it should be available for
+     *  internal use, or asynchronously/synchronously linked to a
+     *  general-purpose input/output (GPIO) pin */
+    enum ac_chan_output output_mode;
+    /** Input multiplexer selection for the comparator's positive input pin */
+    enum ac_chan_pos_mux positive_input;
+    /** Input multiplexer selection for the comparator's negative input pin.
+     *  Any internal reference source, such as a bandgap reference voltage or
+     *  the DAC, must be configured and enabled prior to its use as a
+     *  comparator input.*/
+    enum ac_chan_neg_mux negative_input;
+    /** Scaled VCC voltage division factor for the channel, when a comparator
+     *  pin is connected to the V<SUB>CC</SUB> voltage scalar input. The formular is:
+     *      Vscale = Vdd * vcc_scale_factor / 64.
+     *  If the V<SUB>CC</SUB> voltage scalar is not selected as a comparator
+     *  channel pin's input, this value will be ignored. */
+    uint8_t vcc_scale_factor;
+    /** Interrupt criteria for the comparator channel, to select the condition
+     *  that will trigger a callback */
+    enum ac_chan_interrupt_selection interrupt_selection;
 };
 
 /**
  * \brief Analog Comparator Window configuration structure.
  */
 struct ac_win_config {
-	/** Interrupt criteria for the comparator window channel, to select the
-	 *  condition that will trigger a callback */
-	enum ac_win_interrupt_selection interrupt_selection;
+    /** Interrupt criteria for the comparator window channel, to select the
+     *  condition that will trigger a callback */
+    enum ac_win_interrupt_selection interrupt_selection;
 };
 
 /**
@@ -722,12 +722,12 @@ struct ac_win_config {
  */
 
 enum status_code ac_reset(
-		struct ac_module *const module_inst);
+        struct ac_module *const module_inst);
 
 enum status_code ac_init(
-		struct ac_module *const module_inst,
-		Ac *const hw,
-		struct ac_config *const config);
+        struct ac_module *const module_inst,
+        Ac *const hw,
+        struct ac_config *const config);
 
 #if (AC_INST_NUM > 1) && !defined(__DOXYGEN__)
 /**
@@ -738,21 +738,23 @@ enum status_code ac_init(
  * \return Index of the given AC module instance.
  */
 static uint8_t _ac_get_inst_index(
-		Ac *const hw)
+        Ac *const hw)
 {
-	/* List of available AC modules. */
-	static Ac *const ac_modules[AC_INST_NUM] = AC_INSTS;
-
-	/* Find index for AC instance. */
-	for (uint32_t i = 0; i < AC_INST_NUM; i++) {
-		if (hw == ac_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given. */
-	Assert(false);
-	return 0;
+    /* List of available AC modules. */
+    static Ac *const ac_modules[AC_INST_NUM] = AC_INSTS;
+
+    /* Find index for AC instance. */
+    for (uint32_t i = 0; i < AC_INST_NUM; i++)
+    {
+        if (hw == ac_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given. */
+    Assert(false);
+    return 0;
 }
 #endif /* (AC_INST_NUM > 1) && !defined(__DOXYGEN__) */
 
@@ -775,23 +777,25 @@ static uint8_t _ac_get_inst_index(
 static inline bool ac_is_syncing(
         struct ac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
 #ifdef FEATURE_AC_SYNCBUSY_SCHEME_VERSION_2
-	if (ac_module->SYNCBUSY.reg & AC_SYNCBUSY_MASK) {
-		return true;
-	}
+    if (ac_module->SYNCBUSY.reg & AC_SYNCBUSY_MASK)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 #else
-	if (ac_module->STATUSB.reg & AC_STATUSB_SYNCBUSY) {
-		return true;
-	}
+    if (ac_module->STATUSB.reg & AC_STATUSB_SYNCBUSY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 #endif
 }
 
@@ -811,21 +815,22 @@ static inline bool ac_is_syncing(
  *  \param[out] config  Configuration structure to initialize to default values
  */
 static inline void ac_get_config_defaults(
-		struct ac_config *const config)
+        struct ac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 #ifdef FEATURE_AC_RUN_IN_STANDY_PAIR_COMPARATOR
-	/* Default configuration values */
-	for (uint32_t i = 0; i < AC_PAIRS; i++) {
-		config->run_in_standby[i] = false;
-	}
+    /* Default configuration values */
+    for (uint32_t i = 0; i < AC_PAIRS; i++)
+    {
+        config->run_in_standby[i] = false;
+    }
 #endif
 #if (SAMD) || (SAMHA1) || (SAMR21)
-	config->dig_source_generator = GCLK_GENERATOR_0;
-	config->ana_source_generator = GCLK_GENERATOR_3;
+    config->dig_source_generator = GCLK_GENERATOR_0;
+    config->ana_source_generator = GCLK_GENERATOR_3;
 #else
-	config->source_generator = GCLK_GENERATOR_0;
+    config->source_generator = GCLK_GENERATOR_0;
 #endif
 }
 
@@ -838,20 +843,21 @@ static inline void ac_get_config_defaults(
  * \param[in] module_inst  Software instance for the Analog Comparator peripheral
  */
 static inline void ac_enable(
-		struct ac_module *const module_inst)
+        struct ac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Write the new comparator module control configuration */
-	ac_module->CTRLA.reg |= AC_CTRLA_ENABLE;
+    /* Write the new comparator module control configuration */
+    ac_module->CTRLA.reg |= AC_CTRLA_ENABLE;
 }
 
 /**
@@ -863,25 +869,26 @@ static inline void ac_enable(
  * \param[in] module_inst  Software instance for the Analog Comparator peripheral
  */
 static inline void ac_disable(
-		struct ac_module *const module_inst)
+        struct ac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Disbale interrupt */
-	ac_module->INTENCLR.reg = AC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	ac_module->INTFLAG.reg = AC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    ac_module->INTENCLR.reg = AC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    ac_module->INTFLAG.reg = AC_INTFLAG_MASK;
 
-	/* Write the new comparator module control configuration */
-	ac_module->CTRLA.reg &= ~AC_CTRLA_ENABLE;
+    /* Write the new comparator module control configuration */
+    ac_module->CTRLA.reg &= ~AC_CTRLA_ENABLE;
 }
 
 /**
@@ -897,37 +904,42 @@ static inline void ac_disable(
  *  \param[in] events       Struct containing flags of events to enable
  */
 static inline void ac_enable_events(
-		struct ac_module *const module_inst,
-		struct ac_events *const events)
+        struct ac_module *const module_inst,
+        struct ac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Ac *const ac_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure window output events for each comparator pair */
-	for (uint8_t i = 0; i < AC_PAIRS; i++) {
-		if (events->generate_event_on_window[i] == true) {
-			event_mask |= (AC_EVCTRL_WINEO0 << i);
-		}
-	}
-
-	/* Configure sample input/output events for each comparator */
-	for (uint8_t i = 0; i < AC_NUM_CMP; i++) {
-		if (events->on_event_sample[i] == true) {
-			event_mask |= (AC_EVCTRL_COMPEI0 << i);
-		}
-
-		if (events->generate_event_on_state[i] == true) {
-			event_mask |= (AC_EVCTRL_COMPEO0 << i);
-		}
-	}
-
-	ac_module->EVCTRL.reg |= event_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Ac *const ac_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Configure window output events for each comparator pair */
+    for (uint8_t i = 0; i < AC_PAIRS; i++)
+    {
+        if (events->generate_event_on_window[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_WINEO0 << i);
+        }
+    }
+
+    /* Configure sample input/output events for each comparator */
+    for (uint8_t i = 0; i < AC_NUM_CMP; i++)
+    {
+        if (events->on_event_sample[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_COMPEI0 << i);
+        }
+
+        if (events->generate_event_on_state[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_COMPEO0 << i);
+        }
+    }
+
+    ac_module->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -943,37 +955,42 @@ static inline void ac_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 static inline void ac_disable_events(
-		struct ac_module *const module_inst,
-		struct ac_events *const events)
+        struct ac_module *const module_inst,
+        struct ac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Ac *const ac_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure window output events for each comparator pair */
-	for (uint8_t i = 0; i < AC_PAIRS; i++) {
-		if (events->generate_event_on_window[i] == true) {
-			event_mask |= (AC_EVCTRL_WINEO0 << i);
-		}
-	}
-
-	/* Configure sample input/output events for each comparator */
-	for (uint8_t i = 0; i < AC_NUM_CMP; i++) {
-		if (events->on_event_sample[i] == true) {
-			event_mask |= (AC_EVCTRL_COMPEI0 << i);
-		}
-
-		if (events->generate_event_on_state[i] == true) {
-			event_mask |= (AC_EVCTRL_COMPEO0 << i);
-		}
-	}
-
-	ac_module->EVCTRL.reg &= ~event_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Ac *const ac_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Configure window output events for each comparator pair */
+    for (uint8_t i = 0; i < AC_PAIRS; i++)
+    {
+        if (events->generate_event_on_window[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_WINEO0 << i);
+        }
+    }
+
+    /* Configure sample input/output events for each comparator */
+    for (uint8_t i = 0; i < AC_NUM_CMP; i++)
+    {
+        if (events->on_event_sample[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_COMPEI0 << i);
+        }
+
+        if (events->generate_event_on_state[i] == true)
+        {
+            event_mask |= (AC_EVCTRL_COMPEO0 << i);
+        }
+    }
+
+    ac_module->EVCTRL.reg &= ~event_mask;
 }
 
 /** @} */
@@ -1009,32 +1026,32 @@ static inline void ac_disable_events(
  *                       default values
  */
 static inline void ac_chan_get_config_defaults(
-		struct ac_chan_config *const config)
+        struct ac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->sample_mode         = AC_CHAN_MODE_CONTINUOUS;
-	config->filter              = AC_CHAN_FILTER_MAJORITY_5;
-	config->enable_hysteresis   = true;
+    /* Default configuration values */
+    config->sample_mode         = AC_CHAN_MODE_CONTINUOUS;
+    config->filter              = AC_CHAN_FILTER_MAJORITY_5;
+    config->enable_hysteresis   = true;
 #ifdef FEATURE_AC_RUN_IN_STANDY_EACH_COMPARATOR
-	config->run_in_standby      = false;
+    config->run_in_standby      = false;
 #endif
 #ifdef FEATURE_AC_HYSTERESIS_LEVEL
-	config->hysteresis_level    = AC_HYSTERESIS_LEVEL_50;
+    config->hysteresis_level    = AC_HYSTERESIS_LEVEL_50;
 #endif
-	config->output_mode         = AC_CHAN_OUTPUT_INTERNAL;
-	config->positive_input      = AC_CHAN_POS_MUX_PIN0;
-	config->negative_input      = AC_CHAN_NEG_MUX_SCALED_VCC;
-	config->vcc_scale_factor    = 32;
-	config->interrupt_selection = AC_CHAN_INTERRUPT_SELECTION_TOGGLE;
+    config->output_mode         = AC_CHAN_OUTPUT_INTERNAL;
+    config->positive_input      = AC_CHAN_POS_MUX_PIN0;
+    config->negative_input      = AC_CHAN_NEG_MUX_SCALED_VCC;
+    config->vcc_scale_factor    = 32;
+    config->interrupt_selection = AC_CHAN_INTERRUPT_SELECTION_TOGGLE;
 }
 
 enum status_code ac_chan_set_config(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel,
-		struct ac_chan_config *const config);
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel,
+        struct ac_chan_config *const config);
 
 /**
  * \brief Enables an Analog Comparator channel that was previously configured.
@@ -1046,21 +1063,22 @@ enum status_code ac_chan_set_config(
  *  \param[in] channel      Comparator channel to enable
  */
 static inline void ac_chan_enable(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Write the new comparator module control configuration */
-	ac_module->COMPCTRL[(uint8_t)channel].reg |= AC_COMPCTRL_ENABLE;
+    /* Write the new comparator module control configuration */
+    ac_module->COMPCTRL[(uint8_t)channel].reg |= AC_COMPCTRL_ENABLE;
 }
 
 /**
@@ -1073,21 +1091,22 @@ static inline void ac_chan_enable(
  *  \param[in] channel      Comparator channel to disable
  */
 static inline void ac_chan_disable(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Write the new comparator module control configuration */
-	ac_module->COMPCTRL[(uint8_t)channel].reg &= ~AC_COMPCTRL_ENABLE;
+    /* Write the new comparator module control configuration */
+    ac_module->COMPCTRL[(uint8_t)channel].reg &= ~AC_COMPCTRL_ENABLE;
 }
 
 /** @} */
@@ -1108,17 +1127,17 @@ static inline void ac_chan_disable(
  *  \param[in] channel      Comparator channel to trigger
  */
 static inline void ac_chan_trigger_single_shot(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	/* Write the new comparator module control configuration */
-	ac_module->CTRLB.reg |= (AC_CTRLB_START0 << (uint8_t)channel);
+    /* Write the new comparator module control configuration */
+    ac_module->CTRLB.reg |= (AC_CTRLB_START0 << (uint8_t)channel);
 }
 
 /**
@@ -1133,16 +1152,16 @@ static inline void ac_chan_trigger_single_shot(
  *  \return Comparator channel readiness state.
  */
 static inline bool ac_chan_is_ready(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	return (ac_module->STATUSB.reg & (AC_STATUSB_READY0 << (uint8_t)channel));
+    return (ac_module->STATUSB.reg & (AC_STATUSB_READY0 << (uint8_t)channel));
 }
 
 /**
@@ -1158,32 +1177,35 @@ static inline bool ac_chan_is_ready(
  *  \return Bit mask of comparator channel status flags.
  */
 static inline uint8_t ac_chan_get_status(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Ac *const ac_module = module_inst->hw;
-
-	uint8_t status_mask = 0;
-
-	if (ac_module->INTFLAG.reg & (1 << channel)) {
-		status_mask = AC_CHAN_STATUS_INTERRUPT_SET;
-	}
-
-	if (ac_chan_is_ready(module_inst, channel) == false) {
-		status_mask |= AC_CHAN_STATUS_UNKNOWN;
-		return status_mask;
-	}
-
-	if (ac_module->STATUSA.reg & (AC_STATUSA_STATE0 << (uint8_t)channel)) {
-		status_mask |= AC_CHAN_STATUS_POS_ABOVE_NEG;
-	} else {
-		status_mask |= AC_CHAN_STATUS_NEG_ABOVE_POS;
-	}
-	return status_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Ac *const ac_module = module_inst->hw;
+
+    uint8_t status_mask = 0;
+
+    if (ac_module->INTFLAG.reg & (1 << channel))
+    {
+        status_mask = AC_CHAN_STATUS_INTERRUPT_SET;
+    }
+
+    if (ac_chan_is_ready(module_inst, channel) == false)
+    {
+        status_mask |= AC_CHAN_STATUS_UNKNOWN;
+        return status_mask;
+    }
+
+    if (ac_module->STATUSA.reg & (AC_STATUSA_STATE0 << (uint8_t)channel))
+    {
+        status_mask |= AC_CHAN_STATUS_POS_ABOVE_NEG;
+    } else {
+        status_mask |= AC_CHAN_STATUS_NEG_ABOVE_POS;
+    }
+    return status_mask;
 }
 
 /**
@@ -1196,13 +1218,13 @@ static inline uint8_t ac_chan_get_status(
  * \param[in]  channel      Comparator channel to clear
  */
 static inline void ac_chan_clear_status(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->INTFLAG.reg = (1 << channel);
+    module_inst->hw->INTFLAG.reg = (1 << channel);
 }
 /** @} */
 
@@ -1226,27 +1248,27 @@ static inline void ac_chan_clear_status(
  *                       default values
  */
 static inline void ac_win_get_config_defaults(
-		struct ac_win_config *const config)
+        struct ac_win_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->interrupt_selection = AC_WIN_INTERRUPT_SELECTION_ABOVE;
+    /* Default configuration values */
+    config->interrupt_selection = AC_WIN_INTERRUPT_SELECTION_ABOVE;
 }
 
 enum status_code ac_win_set_config(
-		struct ac_module *const module_inst,
-		enum ac_win_channel const win_channel,
-		struct ac_win_config *const config);
+        struct ac_module *const module_inst,
+        enum ac_win_channel const win_channel,
+        struct ac_win_config *const config);
 
 enum status_code ac_win_enable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel);
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel);
 
 void ac_win_disable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel);
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel);
 
 /** @} */
 
@@ -1268,34 +1290,35 @@ void ac_win_disable(
  *  \return Window Comparator channel readiness state.
  */
 static inline bool ac_win_is_ready(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Convert a window channel index to the individual comparator channels */
-	enum ac_chan_channel win_pair_comp0 =
-			(enum ac_chan_channel)((uint8_t)win_channel * 2);
-	enum ac_chan_channel win_pair_comp1 =
-			(enum ac_chan_channel)(((uint8_t)win_channel * 2) + 1);
-
-	/* Check if the two comparators used in the window are ready */
-	bool win_pair_comp0_ready = ac_chan_is_ready(module_inst, win_pair_comp0);
-	bool win_pair_comp1_ready = ac_chan_is_ready(module_inst, win_pair_comp1);
-
-	/* If one or both window comparators not ready, return failure */
-	if ((win_pair_comp0_ready == false) || (win_pair_comp1_ready == false)) {
-		return false;
-	}
-
-	return true;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Convert a window channel index to the individual comparator channels */
+    enum ac_chan_channel win_pair_comp0 =
+            (enum ac_chan_channel)((uint8_t)win_channel * 2);
+    enum ac_chan_channel win_pair_comp1 =
+            (enum ac_chan_channel)(((uint8_t)win_channel * 2) + 1);
+
+    /* Check if the two comparators used in the window are ready */
+    bool win_pair_comp0_ready = ac_chan_is_ready(module_inst, win_pair_comp0);
+    bool win_pair_comp1_ready = ac_chan_is_ready(module_inst, win_pair_comp1);
+
+    /* If one or both window comparators not ready, return failure */
+    if ((win_pair_comp0_ready == false) || (win_pair_comp1_ready == false))
+    {
+        return false;
+    }
+
+    return true;
 }
 
 uint8_t ac_win_get_status(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel);
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel);
 
 /**
  * \brief Clears an interrupt status flag.
@@ -1307,13 +1330,13 @@ uint8_t ac_win_get_status(
  * \param[in]  win_channel      Window channel to clear
  */
 static inline void ac_win_clear_status(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->INTFLAG.reg = (1 << (win_channel + AC_INTFLAG_WIN0_Pos));
+    module_inst->hw->INTFLAG.reg = (1 << (win_channel + AC_INTFLAG_WIN0_Pos));
 }
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c
index 4f1fc7d1ac76..ff60460bef50 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.c
@@ -66,21 +66,21 @@ void _ac_interrupt_handler(const uint32_t instance_index);
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code ac_register_callback(
-		struct ac_module *const module,
-		ac_callback_t callback_func,
-		const enum ac_callback callback_type)
+        struct ac_module *const module,
+        ac_callback_t callback_func,
+        const enum ac_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set software flag for callback */
-	module->register_callback_mask |= (1 << callback_type);
+    /* Set software flag for callback */
+    module->register_callback_mask |= (1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -94,18 +94,18 @@ enum status_code ac_register_callback(
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code ac_unregister_callback(
-		struct ac_module *const module,
-		const enum ac_callback callback_type)
+        struct ac_module *const module,
+        const enum ac_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Sanity check arguments */
+    Assert(module);
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear software flag for callback */
-	module->register_callback_mask &= ~(1 << callback_type);
+    /* Clear software flag for callback */
+    module->register_callback_mask &= ~(1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -114,17 +114,17 @@ enum status_code ac_unregister_callback(
 #if (AC_INST_NUM == 1)
 void AC_Handler(void)
 {
-	_ac_interrupt_handler(0);
+    _ac_interrupt_handler(0);
 }
 #elif (AC_INST_NUM == 2)
 void AC_Handler(void)
 {
-	_ac_interrupt_handler(0);
+    _ac_interrupt_handler(0);
 }
 
 void AC1_Handler(void)
 {
-	_ac_interrupt_handler(1);
+    _ac_interrupt_handler(1);
 }
 #else
 #  error This driver is not support more than three AC instances.
@@ -140,67 +140,73 @@ void AC1_Handler(void)
  */
 void _ac_interrupt_handler(const uint32_t instance_index)
 {
-	/* Temporary variable */
-	uint8_t interrupt_and_callback_status_mask;
-
-	/* Get device instance from the look-up table */
-
-	struct ac_module *module = _ac_instance[instance_index];
-
-	/* Read and mask interrupt flag register */
-	interrupt_and_callback_status_mask =
-			_ac_instance[instance_index]->hw->INTFLAG.reg &
-			(module->register_callback_mask & module->enable_callback_mask);
-
-	/* Check if comparator channel 0 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP0) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_COMPARATOR_0])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_COMP0;
-	}
-
-	/* Check if comparator channel 1 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP1) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_COMPARATOR_1])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_COMP1;
-	}
-
-	/* Check if window 0 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN0) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_WINDOW_0])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_WIN0;
-	}
+    /* Temporary variable */
+    uint8_t interrupt_and_callback_status_mask;
+
+    /* Get device instance from the look-up table */
+
+    struct ac_module *module = _ac_instance[instance_index];
+
+    /* Read and mask interrupt flag register */
+    interrupt_and_callback_status_mask =
+            _ac_instance[instance_index]->hw->INTFLAG.reg &
+            (module->register_callback_mask & module->enable_callback_mask);
+
+    /* Check if comparator channel 0 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP0)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_COMPARATOR_0])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_COMP0;
+    }
+
+    /* Check if comparator channel 1 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP1)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_COMPARATOR_1])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_COMP1;
+    }
+
+    /* Check if window 0 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN0)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_WINDOW_0])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_WIN0;
+    }
 
 #if (AC_NUM_CMP > 2)
-		/* Check if comparator channel 2 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP2) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_COMPARATOR_2])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_COMP2;
-	}
-
-	/* Check if comparator channel 3 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP3) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_COMPARATOR_3])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_COMP3;
-	}
+        /* Check if comparator channel 2 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP2)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_COMPARATOR_2])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_COMP2;
+    }
+
+    /* Check if comparator channel 3 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_COMP3)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_COMPARATOR_3])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_COMP3;
+    }
 
 #  if !(SAMC20)
-		/* Check if window 1 needs to be serviced */
-	if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN1) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[AC_CALLBACK_WINDOW_1])(module);
-		/* Clear interrupt flag */
-		module->hw->INTFLAG.reg = AC_INTFLAG_WIN1;
-	}
+        /* Check if window 1 needs to be serviced */
+    if (interrupt_and_callback_status_mask & AC_INTFLAG_WIN1)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[AC_CALLBACK_WINDOW_1])(module);
+        /* Clear interrupt flag */
+        module->hw->INTFLAG.reg = AC_INTFLAG_WIN1;
+    }
 #  endif
 #endif /* (AC_NUM_CMP > 2) */
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h
index fa48a7c81725..82db186ff552 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_callback.h
@@ -64,20 +64,20 @@ extern "C" {
  * \return Interrupt vector for of the given TC module instance.
  */
 static enum system_interrupt_vector _ac_interrupt_get_interrupt_vector(
-		uint32_t inst_num)
+        uint32_t inst_num)
 {
-	static uint8_t ac_interrupt_vectors[AC_INST_NUM] =
-		{
-			SYSTEM_INTERRUPT_MODULE_AC,
+    static uint8_t ac_interrupt_vectors[AC_INST_NUM] =
+        {
+            SYSTEM_INTERRUPT_MODULE_AC,
 #if (AC_INST_NUM == 2)
-			SYSTEM_INTERRUPT_MODULE_AC1,
+            SYSTEM_INTERRUPT_MODULE_AC1,
 #endif
 #if (AC_INST_NUM >= 3)
 #  error This driver is not support more than three AC instances.
 #endif
-		};
+        };
 
-	return ac_interrupt_vectors[inst_num];
+    return ac_interrupt_vectors[inst_num];
 }
 #endif /* (AC_INST_NUM > 1) !defined(__DOXYGEN__)*/
 
@@ -87,13 +87,13 @@ static enum system_interrupt_vector _ac_interrupt_get_interrupt_vector(
  */
 
 enum status_code ac_register_callback(
-		struct ac_module *const module,
-		ac_callback_t callback_func,
-		const enum ac_callback callback_type);
+        struct ac_module *const module,
+        ac_callback_t callback_func,
+        const enum ac_callback callback_type);
 
 enum status_code ac_unregister_callback(
-		struct ac_module *const module,
-		const enum ac_callback callback_type);
+        struct ac_module *const module,
+        const enum ac_callback callback_type);
 
 /**
  * \brief Enables callback.
@@ -107,53 +107,53 @@ enum status_code ac_unregister_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void ac_enable_callback(
-		struct ac_module *const module,
-		const enum ac_callback callback_type)
+        struct ac_module *const module,
+        const enum ac_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Set software flag for the callback */
-	module->enable_callback_mask |= (1 << callback_type);
-
-	uint32_t inenset_temp = 0;
-
-	switch (callback_type)
-	{
-		case AC_CALLBACK_COMPARATOR_0:
-			inenset_temp |= AC_INTFLAG_COMP0;
-			break;
-		case AC_CALLBACK_COMPARATOR_1:
-			inenset_temp |= AC_INTFLAG_COMP1;
-			break;
-		case AC_CALLBACK_WINDOW_0:
-			inenset_temp |= AC_INTFLAG_WIN0;
-			break;
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Set software flag for the callback */
+    module->enable_callback_mask |= (1 << callback_type);
+
+    uint32_t inenset_temp = 0;
+
+    switch (callback_type)
+    {
+        case AC_CALLBACK_COMPARATOR_0:
+            inenset_temp |= AC_INTFLAG_COMP0;
+            break;
+        case AC_CALLBACK_COMPARATOR_1:
+            inenset_temp |= AC_INTFLAG_COMP1;
+            break;
+        case AC_CALLBACK_WINDOW_0:
+            inenset_temp |= AC_INTFLAG_WIN0;
+            break;
 #if (AC_NUM_CMP > 2)
-		case AC_CALLBACK_COMPARATOR_2:
-			inenset_temp |= AC_INTFLAG_COMP2;
-			break;
-		case AC_CALLBACK_COMPARATOR_3:
-			inenset_temp |= AC_INTFLAG_COMP3;
-			break;
+        case AC_CALLBACK_COMPARATOR_2:
+            inenset_temp |= AC_INTFLAG_COMP2;
+            break;
+        case AC_CALLBACK_COMPARATOR_3:
+            inenset_temp |= AC_INTFLAG_COMP3;
+            break;
 #  if !(SAMC20)
-		case AC_CALLBACK_WINDOW_1:
-			inenset_temp |= AC_INTFLAG_WIN1;
-			break;
+        case AC_CALLBACK_WINDOW_1:
+            inenset_temp |= AC_INTFLAG_WIN1;
+            break;
 #  endif
 #endif
-		default:
-			break;
-	}
+        default:
+            break;
+    }
 
-	/* Enable the interrupt for the callback */
-	module->hw->INTENSET.reg = inenset_temp;
+    /* Enable the interrupt for the callback */
+    module->hw->INTENSET.reg = inenset_temp;
 
 #if (AC_INST_NUM == 1)
-	/* Enable interrupts for AC module */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AC);
+    /* Enable interrupts for AC module */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AC);
 #elif (AC_INST_NUM > 1)
-	system_interrupt_enable(_ac_interrupt_get_interrupt_vector(_ac_get_inst_index(module->hw)));
+    system_interrupt_enable(_ac_interrupt_get_interrupt_vector(_ac_get_inst_index(module->hw)));
 #endif /* (AC_INST_NUM > 1) */
 }
 
@@ -169,47 +169,47 @@ static inline void ac_enable_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void ac_disable_callback(
-		struct ac_module *const module,
-		const enum ac_callback callback_type)
+        struct ac_module *const module,
+        const enum ac_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Clear software flag for the callback */
-	module->enable_callback_mask &= ~(1 << callback_type);
-
-	uint32_t inenclr_temp = 0;
-
-	switch (callback_type)
-	{
-		case AC_CALLBACK_COMPARATOR_0:
-			inenclr_temp |= AC_INTFLAG_COMP0;
-			break;
-		case AC_CALLBACK_COMPARATOR_1:
-			inenclr_temp |= AC_INTFLAG_COMP1;
-			break;
-		case AC_CALLBACK_WINDOW_0:
-			inenclr_temp |= AC_INTFLAG_WIN0;
-			break;
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Clear software flag for the callback */
+    module->enable_callback_mask &= ~(1 << callback_type);
+
+    uint32_t inenclr_temp = 0;
+
+    switch (callback_type)
+    {
+        case AC_CALLBACK_COMPARATOR_0:
+            inenclr_temp |= AC_INTFLAG_COMP0;
+            break;
+        case AC_CALLBACK_COMPARATOR_1:
+            inenclr_temp |= AC_INTFLAG_COMP1;
+            break;
+        case AC_CALLBACK_WINDOW_0:
+            inenclr_temp |= AC_INTFLAG_WIN0;
+            break;
 #if (AC_NUM_CMP > 2)
-		case AC_CALLBACK_COMPARATOR_2:
-			inenclr_temp |= AC_INTFLAG_COMP2;
-			break;
-		case AC_CALLBACK_COMPARATOR_3:
-			inenclr_temp |= AC_INTFLAG_COMP3;
-			break;
+        case AC_CALLBACK_COMPARATOR_2:
+            inenclr_temp |= AC_INTFLAG_COMP2;
+            break;
+        case AC_CALLBACK_COMPARATOR_3:
+            inenclr_temp |= AC_INTFLAG_COMP3;
+            break;
 #  if !(SAMC20)
-		case AC_CALLBACK_WINDOW_1:
-			inenclr_temp |= AC_INTFLAG_WIN1;
-			break;
+        case AC_CALLBACK_WINDOW_1:
+            inenclr_temp |= AC_INTFLAG_WIN1;
+            break;
 #  endif
 #endif
-		default:
-			break;
-	}
+        default:
+            break;
+    }
 
-	/* Disable the interrupt for the callback */
-	module->hw->INTENCLR.reg = inenclr_temp;
+    /* Disable the interrupt for the callback */
+    module->hw->INTENCLR.reg = inenclr_temp;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c
index 7eac51ea192b..6148fe66f5b0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_d_r_h/ac.c
@@ -46,34 +46,37 @@
 #include "ac.h"
 
 static enum status_code _ac_set_config(
-		struct ac_module *const module_inst,
-		struct ac_config *const config)
+        struct ac_module *const module_inst,
+        struct ac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
-
-	Ac *const ac_module = module_inst->hw;
-
-	/* Use a temporary register for computing the control bits */
-	uint32_t ctrla_temp = 0;
-
-	/* Check if the comparators should be enabled during sleep */
-	for (uint32_t i = 0; i < AC_PAIRS; i++) {
-		if (config->run_in_standby[i] == true) {
-			ctrla_temp |= (AC_CTRLA_RUNSTDBY_Msk << i);
-		}
-	}
-
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
-
-	/* Write the new comparator module control configuration */
-	ac_module->CTRLA.reg = ctrla_temp;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
+
+    Ac *const ac_module = module_inst->hw;
+
+    /* Use a temporary register for computing the control bits */
+    uint32_t ctrla_temp = 0;
+
+    /* Check if the comparators should be enabled during sleep */
+    for (uint32_t i = 0; i < AC_PAIRS; i++)
+    {
+        if (config->run_in_standby[i] == true)
+        {
+            ctrla_temp |= (AC_CTRLA_RUNSTDBY_Msk << i);
+        }
+    }
+
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
+
+    /* Write the new comparator module control configuration */
+    ac_module->CTRLA.reg = ctrla_temp;
+
+    return STATUS_OK;
 }
 
 /** \brief Resets and disables the Analog Comparator driver.
@@ -84,25 +87,26 @@ static enum status_code _ac_set_config(
  * \param[out] module_inst  Pointer to the AC software instance struct
  */
 enum status_code ac_reset(
-		struct ac_module *const module_inst)
+        struct ac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	/* Disable the hardware module */
-	ac_disable(module_inst);
+    /* Disable the hardware module */
+    ac_disable(module_inst);
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Software reset the module */
-	ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
+    /* Software reset the module */
+    ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Initializes and configures the Analog Comparator driver.
@@ -120,65 +124,68 @@ enum status_code ac_reset(
  *                          application
  */
 enum status_code ac_init(
-		struct ac_module *const module_inst,
-		Ac *const hw,
-		struct ac_config *const config)
+        struct ac_module *const module_inst,
+        Ac *const hw,
+        struct ac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
-
-	/* Initialize device instance */
-	module_inst->hw = hw;
-
-	/* Turn on the digital interface clock and GCLK */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-
-	if (hw == AC) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC);
-		gclk_chan_conf.source_generator = config->dig_source_generator;
-		system_gclk_chan_set_config(AC_GCLK_ID_DIG, &gclk_chan_conf);
-		system_gclk_chan_enable(AC_GCLK_ID_DIG);
-		gclk_chan_conf.source_generator = config->ana_source_generator;
-		system_gclk_chan_set_config(AC_GCLK_ID_ANA, &gclk_chan_conf);
-		system_gclk_chan_enable(AC_GCLK_ID_ANA);
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
+
+    /* Initialize device instance */
+    module_inst->hw = hw;
+
+    /* Turn on the digital interface clock and GCLK */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+
+    if (hw == AC)
+    {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC);
+        gclk_chan_conf.source_generator = config->dig_source_generator;
+        system_gclk_chan_set_config(AC_GCLK_ID_DIG, &gclk_chan_conf);
+        system_gclk_chan_enable(AC_GCLK_ID_DIG);
+        gclk_chan_conf.source_generator = config->ana_source_generator;
+        system_gclk_chan_set_config(AC_GCLK_ID_ANA, &gclk_chan_conf);
+        system_gclk_chan_enable(AC_GCLK_ID_ANA);
+    }
 #if (AC_INST_NUM == 2)
-	else if (hw == AC1) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC1);
-		gclk_chan_conf.source_generator = config->dig_source_generator;
-		system_gclk_chan_set_config(AC1_GCLK_ID_DIG, &gclk_chan_conf);
-		system_gclk_chan_enable(AC1_GCLK_ID_DIG);
-		gclk_chan_conf.source_generator = config->ana_source_generator;
-		system_gclk_chan_set_config(AC1_GCLK_ID_ANA, &gclk_chan_conf);
-		system_gclk_chan_enable(AC1_GCLK_ID_ANA);
-	}
+    else if (hw == AC1)
+    {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_AC1);
+        gclk_chan_conf.source_generator = config->dig_source_generator;
+        system_gclk_chan_set_config(AC1_GCLK_ID_DIG, &gclk_chan_conf);
+        system_gclk_chan_enable(AC1_GCLK_ID_DIG);
+        gclk_chan_conf.source_generator = config->ana_source_generator;
+        system_gclk_chan_set_config(AC1_GCLK_ID_ANA, &gclk_chan_conf);
+        system_gclk_chan_enable(AC1_GCLK_ID_ANA);
+    }
 #elif (AC_INST_NUM >= 3)
 #  error This driver is not support more than three AC instances.
 #endif
 
 #if AC_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < AC_CALLBACK_N; i++) {
-		module_inst->callback[i]        = NULL;
-	}
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < AC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i]        = NULL;
+    }
 
-	/* Initialize software flags*/
-	module_inst->register_callback_mask = 0x00;
-	module_inst->enable_callback_mask   = 0x00;
+    /* Initialize software flags*/
+    module_inst->register_callback_mask = 0x00;
+    module_inst->enable_callback_mask   = 0x00;
 
 #  if (AC_INST_NUM == 1)
-	_ac_instance[0] = module_inst;
+    _ac_instance[0] = module_inst;
 #  else
-	/* Register this instance for callbacks*/
-	_ac_instance[_ac_get_inst_index(hw)] = module_inst;
+    /* Register this instance for callbacks*/
+    _ac_instance[_ac_get_inst_index(hw)] = module_inst;
 #  endif
 #endif
 
-	/* Write configuration to module */
-	return _ac_set_config(module_inst, config);
+    /* Write configuration to module */
+    return _ac_set_config(module_inst, config);
 }
 
 /** \brief Writes an Analog Comparator channel configuration to the hardware module.
@@ -191,53 +198,55 @@ enum status_code ac_init(
  *  \param[in] config       Pointer to the channel configuration struct
  */
 enum status_code ac_chan_set_config(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel,
-		struct ac_chan_config *const config)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel,
+        struct ac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	/* Use a temporary variable to compute the comparator configuration */
-	uint32_t compctrl_temp = 0;
+    /* Use a temporary variable to compute the comparator configuration */
+    uint32_t compctrl_temp = 0;
 
-	/* Enable output filter mode */
-	compctrl_temp |= config->filter;
+    /* Enable output filter mode */
+    compctrl_temp |= config->filter;
 
-	/* Enable output hysteresis if required */
-	if (config->enable_hysteresis == true) {
-		compctrl_temp |= AC_COMPCTRL_HYST;
-	}
+    /* Enable output hysteresis if required */
+    if (config->enable_hysteresis == true)
+    {
+        compctrl_temp |= AC_COMPCTRL_HYST;
+    }
 
-	/* Set output signal routing mode */
-	compctrl_temp |= config->output_mode;
+    /* Set output signal routing mode */
+    compctrl_temp |= config->output_mode;
 
-	/* Configure comparator positive and negative pin MUX configurations */
-	compctrl_temp |=
-			(uint32_t)config->positive_input |
-			(uint32_t)config->negative_input;
+    /* Configure comparator positive and negative pin MUX configurations */
+    compctrl_temp |=
+            (uint32_t)config->positive_input |
+            (uint32_t)config->negative_input;
 
-	/* Set sampling mode (single shot or continuous) */
-	compctrl_temp |= config->sample_mode;
+    /* Set sampling mode (single shot or continuous) */
+    compctrl_temp |= config->sample_mode;
 
-	/* Set channel interrupt selection */
-	compctrl_temp |= config->interrupt_selection;
+    /* Set channel interrupt selection */
+    compctrl_temp |= config->interrupt_selection;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Write the final configuration to the module's control register */
-	ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
+    /* Write the final configuration to the module's control register */
+    ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
 
-	/* Configure VCC voltage scaling for the comparator */
-	ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
+    /* Configure VCC voltage scaling for the comparator */
+    ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -256,36 +265,38 @@ enum status_code ac_chan_set_config(
  * \retval  STATUS_ERR_INVALID_ARG  win_channel argument incorrect
  */
 enum status_code ac_win_set_config(
-		struct ac_module *const module_inst,
-		enum ac_win_channel const win_channel,
-		struct ac_win_config *const config)
+        struct ac_module *const module_inst,
+        enum ac_win_channel const win_channel,
+        struct ac_win_config *const config)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
 
-	uint8_t winctrl_mask;
+    uint8_t winctrl_mask;
 
-	winctrl_mask = module_inst->hw->WINCTRL.reg;
+    winctrl_mask = module_inst->hw->WINCTRL.reg;
 
-	if (win_channel == AC_WIN_CHANNEL_0) {
-		winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
-		winctrl_mask |= config->interrupt_selection;
-	}
+    if (win_channel == AC_WIN_CHANNEL_0)
+    {
+        winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
+        winctrl_mask |= config->interrupt_selection;
+    }
 #if (AC_PAIRS > 1)
-	else if (win_channel == AC_WIN_CHANNEL_1) {
-		winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
-		winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
-		AC_WINCTRL_WINTSEL0_Pos);
-	}
+    else if (win_channel == AC_WIN_CHANNEL_1)
+    {
+        winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
+        winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
+        AC_WINCTRL_WINTSEL0_Pos);
+    }
 #endif /* (AC_PAIRS > 1) */
-	else {
-		return STATUS_ERR_INVALID_ARG ;
-	}
+    else {
+        return STATUS_ERR_INVALID_ARG ;
+    }
 
-	module_inst->hw->WINCTRL.reg = winctrl_mask;
+    module_inst->hw->WINCTRL.reg = winctrl_mask;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Enables an Analog Comparator window channel that was previously configured.
@@ -309,51 +320,54 @@ enum status_code ac_win_set_config(
  *                                 were not configured correctly
  */
 enum status_code ac_win_enable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Ac *const ac_module = module_inst->hw;
-
-	/* Load the configurations of the two comparators used in the window */
-	uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
-	uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
-
-	/* Make sure both comparators in the window comparator pair are enabled */
-	if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
-			!(win_pair_comp1_conf & AC_COMPCTRL_ENABLE)) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Make sure the comparators are configured in the same way, other than the
-	 * negative pin multiplexers */
-	if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
-			(win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk)) {
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
-
-	/* Enable the requested window comparator */
-	switch (win_channel)
-	{
-		case AC_WIN_CHANNEL_0:
-			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
-			break;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Ac *const ac_module = module_inst->hw;
+
+    /* Load the configurations of the two comparators used in the window */
+    uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
+    uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
+
+    /* Make sure both comparators in the window comparator pair are enabled */
+    if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
+            !(win_pair_comp1_conf & AC_COMPCTRL_ENABLE))
+            {
+        return STATUS_ERR_IO;
+    }
+
+    /* Make sure the comparators are configured in the same way, other than the
+     * negative pin multiplexers */
+    if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
+            (win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk))
+            {
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
+
+    /* Enable the requested window comparator */
+    switch (win_channel)
+    {
+        case AC_WIN_CHANNEL_0:
+            ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
+            break;
 
 #if (AC_PAIRS > 1)
-		case AC_WIN_CHANNEL_1:
-			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
-			break;
+        case AC_WIN_CHANNEL_1:
+            ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
+            break;
 #endif
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Disables an Analog Comparator window channel that was previously enabled.
@@ -365,32 +379,33 @@ enum status_code ac_win_enable(
  *  \param[in] win_channel  Comparator window channel to disable
  */
 void ac_win_disable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Disable the requested window comparator */
-	switch (win_channel)
-	{
-		case AC_WIN_CHANNEL_0:
-			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
-			break;
+    /* Disable the requested window comparator */
+    switch (win_channel)
+    {
+        case AC_WIN_CHANNEL_0:
+            ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+            break;
 
 #if (AC_PAIRS > 1)
-		case AC_WIN_CHANNEL_1:
-			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
-			break;
+        case AC_WIN_CHANNEL_1:
+            ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
+            break;
 #endif
-	}
+    }
 }
 
 /** \brief Determines the state of a specified Window Comparator.
@@ -404,37 +419,41 @@ void ac_win_disable(
  *  \return Bit mask of Analog Comparator window channel status flags.
  */
 uint8_t ac_win_get_status(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Ac *const ac_module = module_inst->hw;
-
-	uint32_t win_status = 0;
-
-	/* Check if interrupt flag is set */
-	if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel)) {
-		win_status |= AC_WIN_STATUS_INTERRUPT_SET;
-	}
-
-	/* If one or both window comparators not ready, return unknown result */
-	if (ac_win_is_ready(module_inst, win_channel) == false) {
-		win_status |= AC_WIN_STATUS_UNKNOWN;
-		return win_status;
-	}
-
-	uint8_t statusa_tmp = ac_module->STATUSA.reg;
-
-	/* Map hardware comparison states to logical window states */
-	if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel)) {
-		return win_status | AC_WIN_STATUS_BELOW;
-	} else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel)) {
-		return win_status | AC_WIN_STATUS_INSIDE;
-	} else {
-		return win_status | AC_WIN_STATUS_ABOVE;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Ac *const ac_module = module_inst->hw;
+
+    uint32_t win_status = 0;
+
+    /* Check if interrupt flag is set */
+    if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel))
+    {
+        win_status |= AC_WIN_STATUS_INTERRUPT_SET;
+    }
+
+    /* If one or both window comparators not ready, return unknown result */
+    if (ac_win_is_ready(module_inst, win_channel) == false)
+    {
+        win_status |= AC_WIN_STATUS_UNKNOWN;
+        return win_status;
+    }
+
+    uint8_t statusa_tmp = ac_module->STATUSA.reg;
+
+    /* Map hardware comparison states to logical window states */
+    if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel))
+    {
+        return win_status | AC_WIN_STATUS_BELOW;
+    } else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel))
+    {
+        return win_status | AC_WIN_STATUS_INSIDE;
+    } else {
+        return win_status | AC_WIN_STATUS_ABOVE;
+    }
 
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c
index 58aa561d0d59..1b55447137e7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ac/ac_sam_l_c/ac.c
@@ -46,33 +46,33 @@
 #include "ac.h"
 
 static enum status_code _ac_set_config(
-		struct ac_module *const module_inst,
-		struct ac_config *const config)
+        struct ac_module *const module_inst,
+        struct ac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
 
-	UNUSED(module_inst);
+    UNUSED(module_inst);
 
-	/* Set up GCLK */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->source_generator;
+    /* Set up GCLK */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->source_generator;
 #if (SAMC21) || (SAMC20)
-	/* The Analog Comparators and ADC1 use the same generic clock configuration.
- 	 * GCLK_ADC1 must be used to configure the clock for AC as GCLK_AC is not 
- 	 * functional. Errata reference: 13404 
- 	 */
-	system_gclk_chan_set_config(34, &gclk_chan_conf);
-	system_gclk_chan_enable(34);
+    /* The Analog Comparators and ADC1 use the same generic clock configuration.
+     * GCLK_ADC1 must be used to configure the clock for AC as GCLK_AC is not
+     * functional. Errata reference: 13404
+     */
+    system_gclk_chan_set_config(34, &gclk_chan_conf);
+    system_gclk_chan_enable(34);
 #else
-	system_gclk_chan_set_config(AC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(AC_GCLK_ID);
+    system_gclk_chan_set_config(AC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(AC_GCLK_ID);
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Resets and disables the Analog Comparator driver.
@@ -83,25 +83,26 @@ static enum status_code _ac_set_config(
  * \param[out] module_inst  Pointer to the AC software instance struct
  */
 enum status_code ac_reset(
-		struct ac_module *const module_inst)
+        struct ac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	/* Disable the hardware module */
-	ac_disable(module_inst);
+    /* Disable the hardware module */
+    ac_disable(module_inst);
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Software reset the module */
-	ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
+    /* Software reset the module */
+    ac_module->CTRLA.reg |= AC_CTRLA_SWRST;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Initializes and configures the Analog Comparator driver.
@@ -119,46 +120,47 @@ enum status_code ac_reset(
  *                          application
  */
 enum status_code ac_init(
-		struct ac_module *const module_inst,
-		Ac *const hw,
-		struct ac_config *const config)
+        struct ac_module *const module_inst,
+        Ac *const hw,
+        struct ac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module_inst->hw = hw;
+    /* Initialize device instance */
+    module_inst->hw = hw;
 
 #if (SAML21) || (SAMR30)
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_AC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_AC);
 #else
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AC);
 #endif
 
 #if AC_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < AC_CALLBACK_N; i++) {
-		module_inst->callback[i]        = NULL;
-	}
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < AC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i]        = NULL;
+    }
 
-	/* Initialize software flags*/
-	module_inst->register_callback_mask = 0x00;
-	module_inst->enable_callback_mask   = 0x00;
+    /* Initialize software flags*/
+    module_inst->register_callback_mask = 0x00;
+    module_inst->enable_callback_mask   = 0x00;
 
 #  if (AC_INST_NUM == 1)
-	_ac_instance[0] = module_inst;
+    _ac_instance[0] = module_inst;
 #  else
-	/* Register this instance for callbacks*/
-	_ac_instance[_ac_get_inst_index(hw)] = module_inst;
+    /* Register this instance for callbacks*/
+    _ac_instance[_ac_get_inst_index(hw)] = module_inst;
 #  endif
 #endif
 
-	/* Write configuration to module */
-	return _ac_set_config(module_inst, config);
+    /* Write configuration to module */
+    return _ac_set_config(module_inst, config);
 }
 
 /** \brief Writes an Analog Comparator channel configuration to the hardware module.
@@ -171,53 +173,55 @@ enum status_code ac_init(
  *  \param[in] config       Pointer to the channel configuration struct
  */
 enum status_code ac_chan_set_config(
-		struct ac_module *const module_inst,
-		const enum ac_chan_channel channel,
-		struct ac_chan_config *const config)
+        struct ac_module *const module_inst,
+        const enum ac_chan_channel channel,
+        struct ac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	/* Use a temporary variable to compute the comparator configuration */
-	uint32_t compctrl_temp = 0;
+    /* Use a temporary variable to compute the comparator configuration */
+    uint32_t compctrl_temp = 0;
 
-	/* Enable output filter mode */
-	compctrl_temp |= config->filter;
+    /* Enable output filter mode */
+    compctrl_temp |= config->filter;
 
-	/* Comparators should be enabled during sleep */
-	if (config->run_in_standby == true) {
-		compctrl_temp |= AC_COMPCTRL_RUNSTDBY;
-	}
+    /* Comparators should be enabled during sleep */
+    if (config->run_in_standby == true)
+    {
+        compctrl_temp |= AC_COMPCTRL_RUNSTDBY;
+    }
 
-	/* Set output signal routing mode */
-	compctrl_temp |= config->output_mode;
+    /* Set output signal routing mode */
+    compctrl_temp |= config->output_mode;
 
-	/* Configure comparator positive and negative pin MUX configurations */
-	compctrl_temp |=
-			(uint32_t)config->positive_input |
-			(uint32_t)config->negative_input;
+    /* Configure comparator positive and negative pin MUX configurations */
+    compctrl_temp |=
+            (uint32_t)config->positive_input |
+            (uint32_t)config->negative_input;
 
-	/* Set sampling mode (single shot or continuous) */
-	compctrl_temp |= config->sample_mode;
+    /* Set sampling mode (single shot or continuous) */
+    compctrl_temp |= config->sample_mode;
 
-	/* Set channel interrupt selection */
-	compctrl_temp |= config->interrupt_selection;
+    /* Set channel interrupt selection */
+    compctrl_temp |= config->interrupt_selection;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Write the final configuration to the module's control register */
-	ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
+    /* Write the final configuration to the module's control register */
+    ac_module->COMPCTRL[(uint8_t)channel].reg = compctrl_temp;
 
-	/* Configure VCC voltage scaling for the comparator */
-	ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
+    /* Configure VCC voltage scaling for the comparator */
+    ac_module->SCALER[(uint8_t)channel].reg   = config->vcc_scale_factor - 1;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -236,36 +240,38 @@ enum status_code ac_chan_set_config(
  * \retval  STATUS_ERR_INVALID_ARG  win_channel argument incorrect
  */
 enum status_code ac_win_set_config(
-		struct ac_module *const module_inst,
-		enum ac_win_channel const win_channel,
-		struct ac_win_config *const config)
+        struct ac_module *const module_inst,
+        enum ac_win_channel const win_channel,
+        struct ac_win_config *const config)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
 
-	uint8_t winctrl_mask;
+    uint8_t winctrl_mask;
 
-	winctrl_mask = module_inst->hw->WINCTRL.reg;
+    winctrl_mask = module_inst->hw->WINCTRL.reg;
 
-	if (win_channel == AC_WIN_CHANNEL_0) {
-		winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
-		winctrl_mask |= config->interrupt_selection;
-	}
+    if (win_channel == AC_WIN_CHANNEL_0)
+    {
+        winctrl_mask &= ~AC_WINCTRL_WINTSEL0_Msk;
+        winctrl_mask |= config->interrupt_selection;
+    }
 #if (AC_PAIRS > 1)
-	else if (win_channel == AC_WIN_CHANNEL_1) {
-		winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
-		winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
-		AC_WINCTRL_WINTSEL0_Pos));
-	}
+    else if (win_channel == AC_WIN_CHANNEL_1)
+    {
+        winctrl_mask &= ~AC_WINCTRL_WINTSEL1_Msk;
+        winctrl_mask = (config->interrupt_selection << (AC_WINCTRL_WINTSEL1_Pos -
+        AC_WINCTRL_WINTSEL0_Pos));
+    }
 #endif /* (AC_PAIRS > 1) */
-	else {
-		return STATUS_ERR_INVALID_ARG ;
-	}
+    else {
+        return STATUS_ERR_INVALID_ARG ;
+    }
 
-	module_inst->hw->WINCTRL.reg = winctrl_mask;
+    module_inst->hw->WINCTRL.reg = winctrl_mask;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Enables an Analog Comparator window channel that was previously configured.
@@ -289,51 +295,54 @@ enum status_code ac_win_set_config(
  *                                 were not configured correctly
  */
 enum status_code ac_win_enable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Ac *const ac_module = module_inst->hw;
-
-	/* Load the configurations of the two comparators used in the window */
-	uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
-	uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
-
-	/* Make sure both comparators in the window comparator pair are enabled */
-	if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
-			!(win_pair_comp1_conf & AC_COMPCTRL_ENABLE)) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Make sure the comparators are configured in the same way, other than the
-	 * negative pin multiplexers */
-	if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
-			(win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk)) {
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
-
-	/* Enable the requested window comparator */
-	switch (win_channel)
-	{
-		case AC_WIN_CHANNEL_0:
-			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
-			break;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Ac *const ac_module = module_inst->hw;
+
+    /* Load the configurations of the two comparators used in the window */
+    uint32_t win_pair_comp0_conf = ac_module->COMPCTRL[win_channel * 2].reg;
+    uint32_t win_pair_comp1_conf = ac_module->COMPCTRL[win_channel * 2 + 1].reg;
+
+    /* Make sure both comparators in the window comparator pair are enabled */
+    if (!(win_pair_comp0_conf & AC_COMPCTRL_ENABLE) ||
+            !(win_pair_comp1_conf & AC_COMPCTRL_ENABLE))
+            {
+        return STATUS_ERR_IO;
+    }
+
+    /* Make sure the comparators are configured in the same way, other than the
+     * negative pin multiplexers */
+    if ((win_pair_comp0_conf & ~AC_COMPCTRL_MUXNEG_Msk) !=
+            (win_pair_comp1_conf & ~AC_COMPCTRL_MUXNEG_Msk))
+            {
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
+
+    /* Enable the requested window comparator */
+    switch (win_channel)
+    {
+        case AC_WIN_CHANNEL_0:
+            ac_module->WINCTRL.reg |= AC_WINCTRL_WEN0;
+            break;
 
 #if (AC_PAIRS > 1)
-		case AC_WIN_CHANNEL_1:
-			ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
-			break;
+        case AC_WIN_CHANNEL_1:
+            ac_module->WINCTRL.reg |= AC_WINCTRL_WEN1;
+            break;
 #endif
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \brief Disables an Analog Comparator window channel that was previously enabled.
@@ -345,32 +354,33 @@ enum status_code ac_win_enable(
  *  \param[in] win_channel  Comparator window channel to disable
  */
 void ac_win_disable(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Ac *const ac_module = module_inst->hw;
+    Ac *const ac_module = module_inst->hw;
 
-	while (ac_is_syncing(module_inst)) {
-		/* Wait until synchronization is complete */
-	}
+    while (ac_is_syncing(module_inst))
+    {
+        /* Wait until synchronization is complete */
+    }
 
-	/* Disable the requested window comparator */
-	switch (win_channel)
-	{
-		case AC_WIN_CHANNEL_0:
-			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
-			break;
+    /* Disable the requested window comparator */
+    switch (win_channel)
+    {
+        case AC_WIN_CHANNEL_0:
+            ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN0;
+            break;
 
 #if (AC_PAIRS > 1)
-		case AC_WIN_CHANNEL_1:
-			ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
-			break;
+        case AC_WIN_CHANNEL_1:
+            ac_module->WINCTRL.reg &= ~AC_WINCTRL_WEN1;
+            break;
 #endif
-	}
+    }
 }
 
 /** \brief Determines the state of a specified Window Comparator.
@@ -384,37 +394,41 @@ void ac_win_disable(
  *  \return Bit mask of Analog Comparator window channel status flags.
  */
 uint8_t ac_win_get_status(
-		struct ac_module *const module_inst,
-		const enum ac_win_channel win_channel)
+        struct ac_module *const module_inst,
+        const enum ac_win_channel win_channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Ac *const ac_module = module_inst->hw;
-
-	uint32_t win_status = 0;
-
-	/* Check if interrupt flag is set */
-	if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel)) {
-		win_status |= AC_WIN_STATUS_INTERRUPT_SET;
-	}
-
-	/* If one or both window comparators not ready, return unknown result */
-	if (ac_win_is_ready(module_inst, win_channel) == false) {
-		win_status |= AC_WIN_STATUS_UNKNOWN;
-		return win_status;
-	}
-
-	uint8_t statusa_tmp = ac_module->STATUSA.reg;
-
-	/* Map hardware comparison states to logical window states */
-	if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel)) {
-		return win_status | AC_WIN_STATUS_BELOW;
-	} else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel)) {
-		return win_status | AC_WIN_STATUS_INSIDE;
-	} else {
-		return win_status | AC_WIN_STATUS_ABOVE;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Ac *const ac_module = module_inst->hw;
+
+    uint32_t win_status = 0;
+
+    /* Check if interrupt flag is set */
+    if (ac_module->INTFLAG.reg & (AC_INTFLAG_WIN0 << win_channel))
+    {
+        win_status |= AC_WIN_STATUS_INTERRUPT_SET;
+    }
+
+    /* If one or both window comparators not ready, return unknown result */
+    if (ac_win_is_ready(module_inst, win_channel) == false)
+    {
+        win_status |= AC_WIN_STATUS_UNKNOWN;
+        return win_status;
+    }
+
+    uint8_t statusa_tmp = ac_module->STATUSA.reg;
+
+    /* Map hardware comparison states to logical window states */
+    if (statusa_tmp & (AC_STATUSA_WSTATE0_BELOW << win_channel))
+    {
+        return win_status | AC_WIN_STATUS_BELOW;
+    } else if (statusa_tmp & (AC_STATUSA_WSTATE0_INSIDE << win_channel))
+    {
+        return win_status | AC_WIN_STATUS_INSIDE;
+    } else {
+        return win_status | AC_WIN_STATUS_ABOVE;
+    }
 
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h
index f273e6093764..f2cb22acc23a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc.h
@@ -173,27 +173,27 @@
  *
  * \anchor asfdoc_sam0_adc_module_conversion_rate
  * <table>
- *	<caption>Effective ADC Conversion Speed Using Oversampling</caption>
- *	<tr>
- *		<th>Resolution</th>
- *		<th>Effective conversion rate</th>
- *	</tr>
- *	<tr>
- *		<td>13-bit</td>
- *		<td>Conversion rate divided by 4</td>
- *	</tr>
- *	<tr>
- *		<td>14-bit</td>
- *		<td>Conversion rate divided by 16</td>
- *	</tr>
- *	<tr>
- *		<td>15-bit</td>
- *		<td>Conversion rate divided by 64</td>
- *	</tr>
- *	<tr>
- *		<td>16-bit</td>
- *		<td>Conversion rate divided by 256</td>
- *	</tr>
+ *  <caption>Effective ADC Conversion Speed Using Oversampling</caption>
+ *  <tr>
+ *      <th>Resolution</th>
+ *      <th>Effective conversion rate</th>
+ *  </tr>
+ *  <tr>
+ *      <td>13-bit</td>
+ *      <td>Conversion rate divided by 4</td>
+ *  </tr>
+ *  <tr>
+ *      <td>14-bit</td>
+ *      <td>Conversion rate divided by 16</td>
+ *  </tr>
+ *  <tr>
+ *      <td>15-bit</td>
+ *      <td>Conversion rate divided by 64</td>
+ *  </tr>
+ *  <tr>
+ *      <td>16-bit</td>
+ *      <td>Conversion rate divided by 256</td>
+ *  </tr>
  * </table>
  *
  * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes
@@ -222,7 +222,9 @@
  *
  * The resulting sampling time is given by the following equation:
  * \f[
- * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2}
+ * t_{SAMPLE} = (sample\_length+1)\times \frac{ADC_
+ {CLK}}
+ {2}
  * \f]
  *
  * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging
@@ -313,7 +315,8 @@
  *
  * The equation for both offset and gain error compensation is shown below:
  * \f[
- * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN}
+ * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET})\times CORR_
+ {GAIN}
  * \f]
  *
  * When enabled, a given set of offset and gain correction values can be applied
@@ -442,7 +445,7 @@ extern "C" {
 #if ADC_CALLBACK_MODE == true
 #   if (ADC_INST_NUM > 1)
 #       define _ADC_INTERRUPT_VECT_NUM(n, unused) \
-			SYSTEM_INTERRUPT_MODULE_ADC##n,
+            SYSTEM_INTERRUPT_MODULE_ADC##n,
 /**
  * \internal Get the interrupt vector for the given device instance
  *
@@ -451,20 +454,20 @@ extern "C" {
  * \return Interrupt vector for of the given ADC module instance.
  */
 static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector(
-		uint32_t inst_num)
+        uint32_t inst_num)
 {
-	static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = {
-		MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0)
-	};
+    static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = {
+        MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0)
+    };
 
-	return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num];
+    return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num];
 }
 #   endif
 #endif
 
 #if !defined(__DOXYGEN__)
 uint8_t _adc_get_inst_index(
-		Adc *const hw);
+        Adc *const hw);
 #endif
 
 /**
@@ -472,16 +475,16 @@ uint8_t _adc_get_inst_index(
  * @{
  */
 enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config);
+        struct adc_module *const module_inst,
+        Adc *hw,
+        struct adc_config *config);
 
 void adc_get_config_defaults(
-		struct adc_config *const config);
+        struct adc_config *const config);
 
 #if (SAMD) || (SAMHA1) || (SAMR21)
 void adc_regular_ain_channel(
-		uint32_t *pin_array, uint8_t size);
+        uint32_t *pin_array, uint8_t size);
 #endif
 
 /** @} */
@@ -506,34 +509,37 @@ void adc_regular_ain_channel(
  * \retval ADC_STATUS_OVERRUN       ADC result has overrun
  */
 static inline uint32_t adc_get_status(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	uint32_t int_flags = adc_module->INTFLAG.reg;
+    uint32_t int_flags = adc_module->INTFLAG.reg;
 
-	uint32_t status_flags = 0;
+    uint32_t status_flags = 0;
 
-	/* Check for ADC Result Ready */
-	if (int_flags & ADC_INTFLAG_RESRDY) {
-		status_flags |= ADC_STATUS_RESULT_READY;
-	}
+    /* Check for ADC Result Ready */
+    if (int_flags & ADC_INTFLAG_RESRDY)
+    {
+        status_flags |= ADC_STATUS_RESULT_READY;
+    }
 
-	/* Check for ADC Window Match */
-	if (int_flags & ADC_INTFLAG_WINMON) {
-		status_flags |= ADC_STATUS_WINDOW;
-	}
+    /* Check for ADC Window Match */
+    if (int_flags & ADC_INTFLAG_WINMON)
+    {
+        status_flags |= ADC_STATUS_WINDOW;
+    }
 
-	/* Check for ADC Overrun */
-	if (int_flags & ADC_INTFLAG_OVERRUN) {
-		status_flags |= ADC_STATUS_OVERRUN;
-	}
+    /* Check for ADC Overrun */
+    if (int_flags & ADC_INTFLAG_OVERRUN)
+    {
+        status_flags |= ADC_STATUS_OVERRUN;
+    }
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -545,34 +551,37 @@ static inline uint32_t adc_get_status(
  * \param[in] status_flags  Bitmask of \c ADC_STATUS_* flags to clear
  */
 static inline void adc_clear_status(
-		struct adc_module *const module_inst,
-		const uint32_t status_flags)
+        struct adc_module *const module_inst,
+        const uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	uint32_t int_flags = 0;
-
-	/* Check for ADC Result Ready */
-	if (status_flags & ADC_STATUS_RESULT_READY) {
-		int_flags |= ADC_INTFLAG_RESRDY;
-	}
-
-	/* Check for ADC Window Match */
-	if (status_flags & ADC_STATUS_WINDOW) {
-		int_flags |= ADC_INTFLAG_WINMON;
-	}
-
-	/* Check for ADC Overrun */
-	if (status_flags & ADC_STATUS_OVERRUN) {
-		int_flags |= ADC_INTFLAG_OVERRUN;
-	}
-
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = int_flags;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Adc *const adc_module = module_inst->hw;
+
+    uint32_t int_flags = 0;
+
+    /* Check for ADC Result Ready */
+    if (status_flags & ADC_STATUS_RESULT_READY)
+    {
+        int_flags |= ADC_INTFLAG_RESRDY;
+    }
+
+    /* Check for ADC Window Match */
+    if (status_flags & ADC_STATUS_WINDOW)
+    {
+        int_flags |= ADC_INTFLAG_WINMON;
+    }
+
+    /* Check for ADC Overrun */
+    if (status_flags & ADC_STATUS_OVERRUN)
+    {
+        int_flags |= ADC_INTFLAG_OVERRUN;
+    }
+
+    /* Clear interrupt flag */
+    adc_module->INTFLAG.reg = int_flags;
 }
 /** @} */
 
@@ -590,39 +599,41 @@ static inline void adc_clear_status(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline enum status_code adc_enable(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
 #if ADC_CALLBACK_MODE == true
 #   if (ADC_INST_NUM > 1)
-	system_interrupt_enable(_adc_interrupt_get_interrupt_vector(
-			_adc_get_inst_index(adc_module)));
+    system_interrupt_enable(_adc_interrupt_get_interrupt_vector(
+            _adc_get_inst_index(adc_module)));
 #   elif (SAMC20)
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0);
-#	else
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
+        system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#   else
+        system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC);
 #   endif
 #endif
 
-	/* Disbale interrupt */
-	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
 
-	adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
+    adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -633,39 +644,41 @@ static inline enum status_code adc_enable(
  * \param[in] module_inst Pointer to the ADC software instance struct
  */
 static inline enum status_code adc_disable(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
 #if ADC_CALLBACK_MODE == true
 #   if (ADC_INST_NUM > 1)
-	system_interrupt_disable(_adc_interrupt_get_interrupt_vector(
-			_adc_get_inst_index(adc_module)));
+    system_interrupt_disable(_adc_interrupt_get_interrupt_vector(
+            _adc_get_inst_index(adc_module)));
 #   elif (SAMC20)
-		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0);
-#	else
-		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
+        system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0);
+#   else
+        system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC);
 #   endif
 #endif
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    adc_module->INTENCLR.reg = ADC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    adc_module->INTFLAG.reg = ADC_INTFLAG_MASK;
 
-	adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
+    adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -677,24 +690,25 @@ static inline enum status_code adc_disable(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline enum status_code adc_reset(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	/* Disable to make sure the pipeline is flushed before reset */
-	adc_disable(module_inst);
+    /* Disable to make sure the pipeline is flushed before reset */
+    adc_disable(module_inst);
 
-	/* Software reset the module */
-	adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
+    /* Software reset the module */
+    adc_module->CTRLA.reg |= ADC_CTRLA_SWRST;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+    return STATUS_OK;
 }
 
 
@@ -710,29 +724,31 @@ static inline enum status_code adc_reset(
  *  \param[in] events       Struct containing flags of events to enable
  */
 static inline void adc_enable_events(
-		struct adc_module *const module_inst,
-		struct adc_events *const events)
+        struct adc_module *const module_inst,
+        struct adc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= ADC_EVCTRL_WINMONEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= ADC_EVCTRL_WINMONEO;
+    }
 
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= ADC_EVCTRL_RESRDYEO;
-	}
+    /* Configure Result Ready event */
+    if (events->generate_event_on_conversion_done)
+    {
+        event_mask |= ADC_EVCTRL_RESRDYEO;
+    }
 
-	adc_module->EVCTRL.reg |= event_mask;
+    adc_module->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -747,29 +763,31 @@ static inline void adc_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 static inline void adc_disable_events(
-		struct adc_module *const module_inst,
-		struct adc_events *const events)
+        struct adc_module *const module_inst,
+        struct adc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= ADC_EVCTRL_WINMONEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= ADC_EVCTRL_WINMONEO;
+    }
 
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= ADC_EVCTRL_RESRDYEO;
-	}
+    /* Configure Result Ready event */
+    if (events->generate_event_on_conversion_done)
+    {
+        event_mask |= ADC_EVCTRL_RESRDYEO;
+    }
 
-	adc_module->EVCTRL.reg &= ~event_mask;
+    adc_module->EVCTRL.reg &= ~event_mask;
 }
 
 /**
@@ -780,22 +798,24 @@ static inline void adc_disable_events(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline void adc_start_conversion(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
+    adc_module->SWTRIG.reg |= ADC_SWTRIG_START;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -813,38 +833,41 @@ static inline void adc_start_conversion(
  *                             ADC module before the result was read by the software
  */
 static inline enum status_code adc_read(
-		struct adc_module *const module_inst,
-		uint16_t *result)
+        struct adc_module *const module_inst,
+        uint16_t *result)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(result);
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(result);
 
-	if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) {
-		/* Result not ready */
-		return STATUS_BUSY;
-	}
+    if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY))
+    {
+        /* Result not ready */
+        return STATUS_BUSY;
+    }
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
 #if (SAMD) || (SAMHA1) || (SAMR21)
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 #endif
 
-	/* Get ADC result */
-	*result = adc_module->RESULT.reg;
+    /* Get ADC result */
+    *result = adc_module->RESULT.reg;
 
-	/* Reset ready flag */
-	adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
+    /* Reset ready flag */
+    adc_clear_status(module_inst, ADC_STATUS_RESULT_READY);
 
-	if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) {
-		adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
-		return STATUS_ERR_OVERFLOW;
-	}
+    if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN)
+    {
+        adc_clear_status(module_inst, ADC_STATUS_OVERRUN);
+        return STATUS_ERR_OVERFLOW;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** @} */
@@ -864,28 +887,30 @@ static inline enum status_code adc_read(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline void adc_flush(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
+    adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 }
 void adc_set_window_mode(
-		struct adc_module *const module_inst,
-		const enum adc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value);
+        struct adc_module *const module_inst,
+        const enum adc_window_mode window_mode,
+        const int16_t window_lower_value,
+        const int16_t window_upper_value);
 
 /**
  * \brief Sets positive ADC input pin.
@@ -896,27 +921,29 @@ void adc_set_window_mode(
  * \param[in] positive_input  Positive input pin
  */
 static inline void adc_set_positive_input(
-		struct adc_module *const module_inst,
-		const enum adc_positive_input positive_input)
+        struct adc_module *const module_inst,
+        const enum adc_positive_input positive_input)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set positive input pin */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
-			(positive_input);
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Adc *const adc_module = module_inst->hw;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set positive input pin */
+    adc_module->INPUTCTRL.reg =
+            (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) |
+            (positive_input);
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 
@@ -930,27 +957,29 @@ static inline void adc_set_positive_input(
  * \param[in] negative_input  Negative input pin
  */
 static inline void adc_set_negative_input(
-		struct adc_module *const module_inst,
-		const enum adc_negative_input negative_input)
+        struct adc_module *const module_inst,
+        const enum adc_negative_input negative_input)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set negative input pin */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
-			(negative_input);
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Adc *const adc_module = module_inst->hw;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set negative input pin */
+    adc_module->INPUTCTRL.reg =
+            (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) |
+            (negative_input);
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /** @} */
@@ -970,15 +999,15 @@ static inline void adc_set_negative_input(
  * \param[in] interrupt Interrupt to enable
  */
 static inline void adc_enable_interrupt(struct adc_module *const module_inst,
-		enum adc_interrupt_flag interrupt)
+        enum adc_interrupt_flag interrupt)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
-	/* Enable interrupt */
-	adc_module->INTENSET.reg = interrupt;
+    Adc *const adc_module = module_inst->hw;
+    /* Enable interrupt */
+    adc_module->INTENSET.reg = interrupt;
 }
 
 /**
@@ -990,15 +1019,15 @@ static inline void adc_enable_interrupt(struct adc_module *const module_inst,
  * \param[in] interrupt Interrupt to disable
  */
 static inline void adc_disable_interrupt(struct adc_module *const module_inst,
-		enum adc_interrupt_flag interrupt)
+        enum adc_interrupt_flag interrupt)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
-	/* Enable interrupt */
-	adc_module->INTENCLR.reg = interrupt;
+    Adc *const adc_module = module_inst->hw;
+    /* Enable interrupt */
+    adc_module->INTENCLR.reg = interrupt;
 }
 
 /** @} */
@@ -1019,30 +1048,30 @@ static inline void adc_disable_interrupt(struct adc_module *const module_inst,
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DAC</td>
+ *      <td>Digital-to-Analog Converter</td>
+ *  </tr>
  *  <tr>
- *		<td>DAC</td>
- *		<td>Digital-to-Analog Converter</td>
- *	</tr>
- *	<tr>
- *		<td>LSB</td>
- *		<td>Least Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>MSB</td>
- *		<td>Most Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
+ *      <td>LSB</td>
+ *      <td>Least Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MSB</td>
+ *      <td>Most Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1063,27 +1092,27 @@ static inline void adc_disable_interrupt(struct adc_module *const module_inst,
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
  * \if DEVICE_SAML21_SUPPORT
  *  <tr>
- *		<td>Initial Release</td>
+ *      <td>Initial Release</td>
  * </tr>
  * \else
- *	<tr>
- *		<td>Added support for SAM R21</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for SAM D21 and new DMA quick start guide</td>
- *	</tr>
- *	<tr>
- *		<td>Added ADC calibration constant loading from the device signature
+ *  <tr>
+ *      <td>Added support for SAM R21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for SAM D21 and new DMA quick start guide</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added ADC calibration constant loading from the device signature
  *          row when the module is initialized</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * \endif
  * </table>
  */
@@ -1106,49 +1135,49 @@ static inline void adc_disable_interrupt(struct adc_module *const module_inst,
  * \page asfdoc_sam0_adc_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
  * \if DEVICE_SAML21_SUPPORT
- *	<tr>
- *		<td>42451B</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L22</td>
- *	</tr>
+ *  <tr>
+ *      <td>42451B</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L22</td>
+ *  </tr>
  *  <tr>
  *      <td>42451A</td>
  *      <td>07/2015</td>
  *      <td>Initial document release</td>
  * </tr>
  * \else
- *	<tr>
- *		<td>42109E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1 and SAM D09</td>
- *	</tr>
- *	<tr>
- *		<td>42109D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42109C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42109B</td>
- *		<td>06/2013</td>
- *		<td>Added additional documentation on the event system. Corrected
+ *  <tr>
+ *      <td>42109E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42109D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42109C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42109B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
  *          documentation typos.</td>
- *	</tr>
- *	<tr>
- *		<td>42109A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>42109A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * \endif
  * </table>
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h
index f6b30e86ed51..3560861ed4e7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_callback.h
@@ -64,8 +64,8 @@ extern "C" {
  * the driver.
  */
 enum adc_job_type {
-	/** Asynchronous ADC read into a user provided buffer */
-	ADC_JOB_READ_BUFFER,
+    /** Asynchronous ADC read into a user provided buffer */
+    ADC_JOB_READ_BUFFER,
 };
 
 /**
@@ -73,13 +73,13 @@ enum adc_job_type {
  * @{
  */
 void adc_register_callback(
-		struct adc_module *const module,
-		adc_callback_t callback_func,
-		enum adc_callback callback_type);
+        struct adc_module *const module,
+        adc_callback_t callback_func,
+        enum adc_callback callback_type);
 
 void adc_unregister_callback(
-		struct adc_module *module,
-		enum adc_callback callback_type);
+        struct adc_module *module,
+        enum adc_callback callback_type);
 
 /**
  * \brief Enables callback.
@@ -98,23 +98,25 @@ void adc_unregister_callback(
  *
  */
 static inline void adc_enable_callback(
-		struct adc_module *const module,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Enable callback */
-	module->enabled_callback_mask |= (1 << callback_type);
-
-	/* Enable window interrupt if this is a window callback */
-	if (callback_type == ADC_CALLBACK_WINDOW) {
-		adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW);
-	}
-	/* Enable overrun interrupt if error callback is registered */
-	if (callback_type == ADC_CALLBACK_ERROR) {
-		adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Enable callback */
+    module->enabled_callback_mask |= (1 << callback_type);
+
+    /* Enable window interrupt if this is a window callback */
+    if (callback_type == ADC_CALLBACK_WINDOW)
+    {
+        adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW);
+    }
+    /* Enable overrun interrupt if error callback is registered */
+    if (callback_type == ADC_CALLBACK_ERROR)
+    {
+        adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+    }
 }
 
 /**
@@ -133,23 +135,25 @@ static inline void adc_enable_callback(
  *
  */
 static inline void adc_disable_callback(
-		struct adc_module *const module,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Disable callback */
-	module->enabled_callback_mask &= ~(1 << callback_type);
-
-	/* Disable window interrupt if this is a window callback */
-	if (callback_type == ADC_CALLBACK_WINDOW) {
-		adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW);
-	}
-	/* Disable overrun interrupt if this is the error callback */
-	if (callback_type == ADC_CALLBACK_ERROR) {
-		adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Disable callback */
+    module->enabled_callback_mask &= ~(1 << callback_type);
+
+    /* Disable window interrupt if this is a window callback */
+    if (callback_type == ADC_CALLBACK_WINDOW)
+    {
+        adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW);
+    }
+    /* Disable overrun interrupt if this is the error callback */
+    if (callback_type == ADC_CALLBACK_ERROR)
+    {
+        adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN);
+    }
 }
 
 /** @} */
@@ -160,17 +164,17 @@ static inline void adc_disable_callback(
  * @{
  */
 enum status_code adc_read_buffer_job(
-		struct adc_module *const module_inst,
-		uint16_t *buffer,
-		uint16_t samples);
+        struct adc_module *const module_inst,
+        uint16_t *buffer,
+        uint16_t samples);
 
 enum status_code adc_get_job_status(
-		struct adc_module *module_inst,
-		enum adc_job_type type);
+        struct adc_module *module_inst,
+        enum adc_job_type type);
 
 void adc_abort_job(
-		struct adc_module *module_inst,
-		enum adc_job_type type);
+        struct adc_module *module_inst,
+        enum adc_job_type type);
 /** @} */
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h
index 5323ad92a11f..e136e4cefa3d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b.h
@@ -156,38 +156,38 @@ extern "C" {
  *
  */
 enum adc_internal_buf {
-	/** Internal buffer voltage level: 0.5V */
-	ADC_INTERNAL_BUF_0_5 = 0,
-	/** Internal buffer voltage level: 0.6V */
-	ADC_INTERNAL_BUF_0_6,
-	/** Internal buffer voltage level: 0.7V */
-	ADC_INTERNAL_BUF_0_7,
-	/** Internal buffer voltage level: 0.8V */
-	ADC_INTERNAL_BUF_0_8,
-	/** Internal buffer voltage level: 0.9V */
-	ADC_INTERNAL_BUF_0_9,
-	/** Internal buffer voltage level: 1.0V */
-	ADC_INTERNAL_BUF_1_0,
-	/** Internal buffer voltage level: 1.1V */
-	ADC_INTERNAL_BUF_1_1,
-	/** Internal buffer voltage level: 1.2V */
-	ADC_INTERNAL_BUF_1_2,
-	/** Internal buffer voltage level: 1.3V */
-	ADC_INTERNAL_BUF_1_3,
-	/** Internal buffer voltage level: 1.4V */
-	ADC_INTERNAL_BUF_1_4,
-	/** Internal buffer voltage level: 1.5V */
-	ADC_INTERNAL_BUF_1_5,
-	/** Internal buffer voltage level: 1.6V */
-	ADC_INTERNAL_BUF_1_6,
-	/** Internal buffer voltage level: 1.7V */
-	ADC_INTERNAL_BUF_1_7,
-	/** Internal buffer voltage level: 1.8V */
-	ADC_INTERNAL_BUF_1_8,
-	/** Internal buffer voltage level: 1.9V */
-	ADC_INTERNAL_BUF_1_9,
-	/** Internal buffer voltage level: 2.0V */
-	ADC_INTERNAL_BUF_2_0,
+    /** Internal buffer voltage level: 0.5V */
+    ADC_INTERNAL_BUF_0_5 = 0,
+    /** Internal buffer voltage level: 0.6V */
+    ADC_INTERNAL_BUF_0_6,
+    /** Internal buffer voltage level: 0.7V */
+    ADC_INTERNAL_BUF_0_7,
+    /** Internal buffer voltage level: 0.8V */
+    ADC_INTERNAL_BUF_0_8,
+    /** Internal buffer voltage level: 0.9V */
+    ADC_INTERNAL_BUF_0_9,
+    /** Internal buffer voltage level: 1.0V */
+    ADC_INTERNAL_BUF_1_0,
+    /** Internal buffer voltage level: 1.1V */
+    ADC_INTERNAL_BUF_1_1,
+    /** Internal buffer voltage level: 1.2V */
+    ADC_INTERNAL_BUF_1_2,
+    /** Internal buffer voltage level: 1.3V */
+    ADC_INTERNAL_BUF_1_3,
+    /** Internal buffer voltage level: 1.4V */
+    ADC_INTERNAL_BUF_1_4,
+    /** Internal buffer voltage level: 1.5V */
+    ADC_INTERNAL_BUF_1_5,
+    /** Internal buffer voltage level: 1.6V */
+    ADC_INTERNAL_BUF_1_6,
+    /** Internal buffer voltage level: 1.7V */
+    ADC_INTERNAL_BUF_1_7,
+    /** Internal buffer voltage level: 1.8V */
+    ADC_INTERNAL_BUF_1_8,
+    /** Internal buffer voltage level: 1.9V */
+    ADC_INTERNAL_BUF_1_9,
+    /** Internal buffer voltage level: 2.0V */
+    ADC_INTERNAL_BUF_2_0,
 };
 
 /**
@@ -197,22 +197,22 @@ enum adc_internal_buf {
  *
  */
 enum adc_reference {
-	/** Internal form buffer reference */
-	ADC_REFERENCE_INTERNAL_BUF = 0,
-	/** Internal from IxR reference */
-	ADC_REFERENCE_INTERNAL_IR,
-	/**  VBATT/2 reference */
-	ADC_REFERENCE_VBATT_2,
-	/** GPIO_MS1 reference */
-	ADC_REFERENCE_GPIO_MS1,
-	/** GPIO_MS2 reference */
-	ADC_REFERENCE_GPIO_MS2,
-	/** GPIO_MS3 reference */
-	ADC_REFERENCE_GPIO_MS3,
-	/** GPIO_MS4 reference */
-	ADC_REFERENCE_GPIO_MS4,
-	/** VBATTERY reference */
-	ADC_REFERENCE_VBATT,
+    /** Internal form buffer reference */
+    ADC_REFERENCE_INTERNAL_BUF = 0,
+    /** Internal from IxR reference */
+    ADC_REFERENCE_INTERNAL_IR,
+    /**  VBATT/2 reference */
+    ADC_REFERENCE_VBATT_2,
+    /** GPIO_MS1 reference */
+    ADC_REFERENCE_GPIO_MS1,
+    /** GPIO_MS2 reference */
+    ADC_REFERENCE_GPIO_MS2,
+    /** GPIO_MS3 reference */
+    ADC_REFERENCE_GPIO_MS3,
+    /** GPIO_MS4 reference */
+    ADC_REFERENCE_GPIO_MS4,
+    /** VBATTERY reference */
+    ADC_REFERENCE_VBATT,
 };
 
 /**
@@ -222,22 +222,22 @@ enum adc_reference {
  *
  */
 enum adc_input_channel {
-	/** GPIO_MS1 input */
-	ADC_INPUT_CH_GPIO_MS1 = 0,
-	/** GPIO_MS2 input */
-	ADC_INPUT_CH_GPIO_MS2,
-	/** GPIO_MS3 input */
-	ADC_INPUT_CH_GPIO_MS3,
-	/** GPIO_MS4 input */
-	ADC_INPUT_CH_GPIO_MS4,
-	/** On chip temperature measurement input */
-	ADC_INPUT_CH_TEMPERATURE,
-	/** VBATT divided by 4 voltage level */
-	ADC_INPUT_CH_VBATT_4,
-	/** LP_LDO_OUT_1P2 low power domain voltage */
-	ADC_INPUT_CH_LPD0_LDO,
-	/**  ADC reference voltage level */
-	ADC_INPUT_CH_VREF,
+    /** GPIO_MS1 input */
+    ADC_INPUT_CH_GPIO_MS1 = 0,
+    /** GPIO_MS2 input */
+    ADC_INPUT_CH_GPIO_MS2,
+    /** GPIO_MS3 input */
+    ADC_INPUT_CH_GPIO_MS3,
+    /** GPIO_MS4 input */
+    ADC_INPUT_CH_GPIO_MS4,
+    /** On chip temperature measurement input */
+    ADC_INPUT_CH_TEMPERATURE,
+    /** VBATT divided by 4 voltage level */
+    ADC_INPUT_CH_VBATT_4,
+    /** LP_LDO_OUT_1P2 low power domain voltage */
+    ADC_INPUT_CH_LPD0_LDO,
+    /**  ADC reference voltage level */
+    ADC_INPUT_CH_VREF,
 };
 
 /**
@@ -247,18 +247,18 @@ enum adc_input_channel {
  *
  */
 enum adc_channel_mode {
-	/**
-	 * Input channels time multiplexing is between channel 0 to channel 3.
-	 * In this mode, ADC input channel selection is invalid.
-	 */
-	ADC_CH_MODE_CH0_TO_CH3,
-	/**
-	 * Input channels time multiplexing is between channel 4 to channel 7.
-	 * In this mode, ADC input channel selection is invalid.
-	 */
-	ADC_CH_MODE_CH4_TO_CH7,
-	/** Assign a specific input channel using \ref adc_input_channel */
-	ADC_CH_MODE_ASSIGN,
+    /**
+     * Input channels time multiplexing is between channel 0 to channel 3.
+     * In this mode, ADC input channel selection is invalid.
+     */
+    ADC_CH_MODE_CH0_TO_CH3,
+    /**
+     * Input channels time multiplexing is between channel 4 to channel 7.
+     * In this mode, ADC input channel selection is invalid.
+     */
+    ADC_CH_MODE_CH4_TO_CH7,
+    /** Assign a specific input channel using \ref adc_input_channel */
+    ADC_CH_MODE_ASSIGN,
 };
 
 /**
@@ -268,14 +268,14 @@ enum adc_channel_mode {
  *
  */
 enum adc_input_dynamic_range{
-	/** Input dynamic range from 0V to VBATT voltage level */
-	ADC_INPUT_DYNAMIC_RANGE_0 = 0,
-	/** Input dynamic range from 0.08*VBATT to 0.92*VBATT voltage level */
-	ADC_INPUT_DYNAMIC_RANGE_1,
-	/** Input dynamic range from 0.17*VBATT to 0.83*VBATT voltage level */
-	ADC_INPUT_DYNAMIC_RANGE_2,
-	/** Input dynamic range from 0.25*VBATT to 0.75*VBATT voltage level */
-	ADC_INPUT_DYNAMIC_RANGE_3,
+    /** Input dynamic range from 0V to VBATT voltage level */
+    ADC_INPUT_DYNAMIC_RANGE_0 = 0,
+    /** Input dynamic range from 0.08*VBATT to 0.92*VBATT voltage level */
+    ADC_INPUT_DYNAMIC_RANGE_1,
+    /** Input dynamic range from 0.17*VBATT to 0.83*VBATT voltage level */
+    ADC_INPUT_DYNAMIC_RANGE_2,
+    /** Input dynamic range from 0.25*VBATT to 0.75*VBATT voltage level */
+    ADC_INPUT_DYNAMIC_RANGE_3,
 };
 
 /**
@@ -286,14 +286,14 @@ enum adc_input_dynamic_range{
  *
  */
 enum adc_bias_current {
-	/** Comparator bias current is 4uA for throughput 100KS/s */
-	ADC_BIAS_CURRENT_0 = 0,
-	/** Comparator bias current is 8uA */
-	ADC_BIAS_CURRENT_1,
-	/** Comparator bias current is 20uA */
-	ADC_BIAS_CURRENT_2,
-	/** Comparator bias current is 24uA for throughput 1MS/s */
-	ADC_BIAS_CURRENT_3,
+    /** Comparator bias current is 4uA for throughput 100KS/s */
+    ADC_BIAS_CURRENT_0 = 0,
+    /** Comparator bias current is 8uA */
+    ADC_BIAS_CURRENT_1,
+    /** Comparator bias current is 20uA */
+    ADC_BIAS_CURRENT_2,
+    /** Comparator bias current is 24uA for throughput 1MS/s */
+    ADC_BIAS_CURRENT_3,
 };
 
 /**
@@ -304,24 +304,24 @@ enum adc_bias_current {
  * function before being modified by the user application.
  */
 struct adc_config {
-	/** Voltage reference */
-	enum adc_reference reference;
-	/** Internal reference voltage level */
-	enum adc_internal_buf internal_vref;
-	/** Input channel */
-	enum adc_input_channel input_channel;
-	/** Input channel selection */
-	enum adc_channel_mode channel_mode;
-	/** Input channel time multiplexing selection mode */
-	enum adc_input_dynamic_range input_dynamic_range;
-	/** Comparator biasing current selection */
-	enum adc_bias_current bias_current;
-	/** Invert ADC Clock */
-	bool invert_clock;
-	/** Fractional part for the clock divider */
-	uint8_t frac_part;
-	/** Integer part for the clock divider */
-	uint16_t int_part;
+    /** Voltage reference */
+    enum adc_reference reference;
+    /** Internal reference voltage level */
+    enum adc_internal_buf internal_vref;
+    /** Input channel */
+    enum adc_input_channel input_channel;
+    /** Input channel selection */
+    enum adc_channel_mode channel_mode;
+    /** Input channel time multiplexing selection mode */
+    enum adc_input_dynamic_range input_dynamic_range;
+    /** Comparator biasing current selection */
+    enum adc_bias_current bias_current;
+    /** Invert ADC Clock */
+    bool invert_clock;
+    /** Fractional part for the clock divider */
+    uint8_t frac_part;
+    /** Integer part for the clock divider */
+    uint16_t int_part;
 };
 
 /** \name Configuration, initialization and get status
@@ -361,14 +361,14 @@ enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
  * </table>
  *
  *
@@ -387,12 +387,12 @@ enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -410,11 +410,11 @@ enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result
  * \page asfdoc_samb_adc_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
  *  <tr>
  *      <td>A</td>
  *      <td>09/2015</td>
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c
index 1db4725f2fa0..92357b132253 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_b/adc_sam_b.c
@@ -48,28 +48,29 @@
 
 static enum status_code _adc_gpio_ms_enable(enum adc_input_channel channel)
 {
-	switch (channel) {
-		case ADC_INPUT_CH_GPIO_MS1:
-			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
-				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_44;
-			break;
-		case ADC_INPUT_CH_GPIO_MS2:
-			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
-				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_45;
-		break;
-		case ADC_INPUT_CH_GPIO_MS3:
-			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
-				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_46;
-		break;
-		case ADC_INPUT_CH_GPIO_MS4:
-			AON_GP_REGS0->MS_GPIO_MODE.reg |= \
-				AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_47;
-		break;
+    switch (channel)
+    {
+        case ADC_INPUT_CH_GPIO_MS1:
+            AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+                AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_44;
+            break;
+        case ADC_INPUT_CH_GPIO_MS2:
+            AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+                AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_45;
+        break;
+        case ADC_INPUT_CH_GPIO_MS3:
+            AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+                AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_46;
+        break;
+        case ADC_INPUT_CH_GPIO_MS4:
+            AON_GP_REGS0->MS_GPIO_MODE.reg |= \
+                AON_GP_REGS_MS_GPIO_MODE_ANALOG_ENABLE_47;
+        break;
 
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -95,16 +96,16 @@ static enum status_code _adc_gpio_ms_enable(enum adc_input_channel channel)
  */
 void adc_get_config_defaults(struct adc_config *const config)
 {
-	Assert(config);
-	config->reference = ADC_REFERENCE_VBATT_2;
-	config->internal_vref = ADC_INTERNAL_BUF_1_5;
-	config->input_channel = ADC_INPUT_CH_GPIO_MS1;
-	config->channel_mode = ADC_CH_MODE_ASSIGN;
-	config->input_dynamic_range = ADC_INPUT_DYNAMIC_RANGE_3;
-	config->bias_current = ADC_BIAS_CURRENT_3;
-	config->invert_clock = false;
-	config->frac_part = 0;
-	config->int_part = 0x12;
+    Assert(config);
+    config->reference = ADC_REFERENCE_VBATT_2;
+    config->internal_vref = ADC_INTERNAL_BUF_1_5;
+    config->input_channel = ADC_INPUT_CH_GPIO_MS1;
+    config->channel_mode = ADC_CH_MODE_ASSIGN;
+    config->input_dynamic_range = ADC_INPUT_DYNAMIC_RANGE_3;
+    config->bias_current = ADC_BIAS_CURRENT_3;
+    config->invert_clock = false;
+    config->frac_part = 0;
+    config->int_part = 0x12;
 }
 
 /**
@@ -118,50 +119,56 @@ void adc_get_config_defaults(struct adc_config *const config)
  */
 void adc_init(struct adc_config *config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	if (config->invert_clock) {
-		LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg = LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INVERT;
-	} else {
-		LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg &= ~LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_MASK;
-	}
+    if (config->invert_clock)
+    {
+        LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg = LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INVERT;
+    } else {
+        LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg &= ~LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_MASK;
+    }
 
-	/* Setting ADC clock */
-	LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg |= \
-			LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_FRAC_PART(config->frac_part) | \
-			LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INT_PART(config->int_part);
+    /* Setting ADC clock */
+    LPMCU_MISC_REGS0->SENS_ADC_CLK_CTRL.reg |= \
+            LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_FRAC_PART(config->frac_part) | \
+            LPMCU_MISC_REGS_SENS_ADC_CLK_CTRL_INT_PART(config->int_part);
 
-	if ((config->reference == ADC_REFERENCE_GPIO_MS1) || \
-		(config->reference == ADC_REFERENCE_GPIO_MS2) || \
-		(config->reference == ADC_REFERENCE_GPIO_MS3) || \
-		(config->reference == ADC_REFERENCE_GPIO_MS4)) {
-		_adc_gpio_ms_enable(config->reference - ADC_REFERENCE_GPIO_MS1);
-	}
+    if ((config->reference == ADC_REFERENCE_GPIO_MS1) || \
+        (config->reference == ADC_REFERENCE_GPIO_MS2) || \
+        (config->reference == ADC_REFERENCE_GPIO_MS3) || \
+        (config->reference == ADC_REFERENCE_GPIO_MS4))
+        {
+        _adc_gpio_ms_enable(config->reference - ADC_REFERENCE_GPIO_MS1);
+    }
 
-	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_REF_SEL = config->reference;
-	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_BIAS_RES_CTRL = config->internal_vref;
+    AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_REF_SEL = config->reference;
+    AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_BIAS_RES_CTRL = config->internal_vref;
 
-	if (config->channel_mode == ADC_CH_MODE_ASSIGN) {
-		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_CTRL = \
-				AON_GP_REGS_RF_PMU_REGS_1_SADC_CHN_CTRL_1_Val;
-		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = config->input_channel;
-		
-		if (config->input_channel <= ADC_INPUT_CH_GPIO_MS4) {
-			/* Enable GPIO_MS pin */
-			_adc_gpio_ms_enable(config->input_channel);
-		}
-	} else if (config->channel_mode == ADC_CH_MODE_CH0_TO_CH3) {
-		/* Input channels time multiplexing is between channel 0 to channel 3 */
-		/* Config GPIO_MS1 ~ GPIO_MS4 pin */
-		AON_GP_REGS0->MS_GPIO_MODE.reg = AON_GP_REGS_MS_GPIO_MODE_MASK;
-	} else if (config->channel_mode == ADC_CH_MODE_CH4_TO_CH7) {
-		/* Input channels time multiplexing is between channel 4 to channel 7 */
-		AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = 0x4;
-	}
+    if (config->channel_mode == ADC_CH_MODE_ASSIGN)
+    {
+        AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_CTRL = \
+                AON_GP_REGS_RF_PMU_REGS_1_SADC_CHN_CTRL_1_Val;
+        AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = config->input_channel;
 
-	AON_GP_REGS0->RF_PMU_REGS_1.bit.CODE_IN = config->input_dynamic_range;
-	AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_LP_CTRL = config->bias_current;
+        if (config->input_channel <= ADC_INPUT_CH_GPIO_MS4)
+        {
+            /* Enable GPIO_MS pin */
+            _adc_gpio_ms_enable(config->input_channel);
+        }
+    } else if (config->channel_mode == ADC_CH_MODE_CH0_TO_CH3)
+    {
+        /* Input channels time multiplexing is between channel 0 to channel 3 */
+        /* Config GPIO_MS1 ~ GPIO_MS4 pin */
+        AON_GP_REGS0->MS_GPIO_MODE.reg = AON_GP_REGS_MS_GPIO_MODE_MASK;
+    } else if (config->channel_mode == ADC_CH_MODE_CH4_TO_CH7)
+    {
+        /* Input channels time multiplexing is between channel 4 to channel 7 */
+        AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_CHN_SEL = 0x4;
+    }
+
+    AON_GP_REGS0->RF_PMU_REGS_1.bit.CODE_IN = config->input_dynamic_range;
+    AON_GP_REGS0->RF_PMU_REGS_1.bit.SADC_LP_CTRL = config->bias_current;
 }
 
 /**
@@ -173,7 +180,7 @@ void adc_init(struct adc_config *config)
  */
 uint32_t adc_get_status(void)
 {
-	return (LPMCU_MISC_REGS0->SENS_ADC_RAW_STATUS.reg);
+    return (LPMCU_MISC_REGS0->SENS_ADC_RAW_STATUS.reg);
 }
 
 /**
@@ -184,18 +191,19 @@ uint32_t adc_get_status(void)
  */
 void adc_enable(void)
 {
-	///* Enable ADC clock */
-	system_clock_peripheral_enable(PERIPHERAL_ADC);
+    /*/* Enable ADC clock */
+    system_clock_peripheral_enable(PERIPHERAL_ADC);
 
-	/* Enable ADC module */
-	AON_GP_REGS0->AON_PMU_CTRL.reg &= \
-		~AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_RST;
-	AON_GP_REGS0->AON_PMU_CTRL.reg |= \
-			AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
-			AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN;
-	for (uint16_t i = 0; i < 0xFF; i++) {
-		/* Waiting... */
-	}
+    /* Enable ADC module */
+    AON_GP_REGS0->AON_PMU_CTRL.reg &= \
+        ~AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_RST;
+    AON_GP_REGS0->AON_PMU_CTRL.reg |= \
+            AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
+            AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN;
+    for (uint16_t i = 0; i < 0xFF; i++)
+    {
+        /* Waiting... */
+    }
 }
 
 /**
@@ -206,13 +214,13 @@ void adc_enable(void)
  */
 void adc_disable(void)
 {
-	/* Disable ADC clock */
-	system_clock_peripheral_disable(PERIPHERAL_ADC);
+    /* Disable ADC clock */
+    system_clock_peripheral_disable(PERIPHERAL_ADC);
 
-	/* Disable ADC module */
-	AON_GP_REGS0->AON_PMU_CTRL.reg &= \
-			~(AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
-			AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN);
+    /* Disable ADC module */
+    AON_GP_REGS0->AON_PMU_CTRL.reg &= \
+            ~(AON_GP_REGS_AON_PMU_CTRL_PMU_SENS_ADC_EN | \
+            AON_GP_REGS_AON_PMU_CTRL_PMU_BGR_EN);
 }
 
 /**
@@ -223,8 +231,8 @@ void adc_disable(void)
  */
 void adc_reset(void)
 {
-	/* Reset ADC module */
-	system_peripheral_reset(PERIPHERAL_ADC);
+    /* Reset ADC module */
+    system_peripheral_reset(PERIPHERAL_ADC);
 }
 
 /**
@@ -242,39 +250,42 @@ void adc_reset(void)
 enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result)
 
 {
-	Assert(result);
+    Assert(result);
 
-	/* The transition of the ADC_DONE signal from LO to HI indicates that the
-	 * ADC conversion is done. */
-	while (adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE) {
-		/* Waiting... */
-	}
+    /* The transition of the ADC_DONE signal from LO to HI indicates that the
+     * ADC conversion is done. */
+    while (adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE)
+    {
+        /* Waiting... */
+    }
 
-	while(!(adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE)) {
-		/* Waiting... */
-	}
+    while(!(adc_get_status() & LPMCU_MISC_REGS_SENS_ADC_RAW_STATUS_ADC_DONE))
+    {
+        /* Waiting... */
+    }
 
-	switch (input_channel) {
-		case ADC_INPUT_CH_GPIO_MS1:
-		case ADC_INPUT_CH_TEMPERATURE:
-			*result = LPMCU_MISC_REGS0->SENS_ADC_CH0_DATA.reg;
-			break;
+    switch (input_channel)
+    {
+        case ADC_INPUT_CH_GPIO_MS1:
+        case ADC_INPUT_CH_TEMPERATURE:
+            *result = LPMCU_MISC_REGS0->SENS_ADC_CH0_DATA.reg;
+            break;
 
-		case ADC_INPUT_CH_GPIO_MS2:
-		case ADC_INPUT_CH_VBATT_4:
-			*result = LPMCU_MISC_REGS0->SENS_ADC_CH1_DATA.reg;
-			break;
+        case ADC_INPUT_CH_GPIO_MS2:
+        case ADC_INPUT_CH_VBATT_4:
+            *result = LPMCU_MISC_REGS0->SENS_ADC_CH1_DATA.reg;
+            break;
 
-		case ADC_INPUT_CH_GPIO_MS3:
-		case ADC_INPUT_CH_LPD0_LDO:
-			*result = LPMCU_MISC_REGS0->SENS_ADC_CH2_DATA.reg;
-			break;
+        case ADC_INPUT_CH_GPIO_MS3:
+        case ADC_INPUT_CH_LPD0_LDO:
+            *result = LPMCU_MISC_REGS0->SENS_ADC_CH2_DATA.reg;
+            break;
 
-		case ADC_INPUT_CH_GPIO_MS4:
-		case ADC_INPUT_CH_VREF:
-			*result = LPMCU_MISC_REGS0->SENS_ADC_CH3_DATA.reg;
-			break;
-	}
+        case ADC_INPUT_CH_GPIO_MS4:
+        case ADC_INPUT_CH_VREF:
+            *result = LPMCU_MISC_REGS0->SENS_ADC_CH3_DATA.reg;
+            break;
+    }
 
-	return STATUS_OK;
-}
\ No newline at end of file
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c
index ddc2cfbd72da..9ed5a7ce806d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc.c
@@ -84,35 +84,35 @@
  */
 void adc_get_config_defaults(struct adc_config *const config)
 {
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-	config->reference                     = ADC_REFERENCE_INT1V;
-	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
-	config->resolution                    = ADC_RESOLUTION_12BIT;
-	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
-	config->window.window_upper_value     = 0;
-	config->window.window_lower_value     = 0;
-	config->gain_factor                   = ADC_GAIN_FACTOR_1X;
+    Assert(config);
+    config->clock_source                  = GCLK_GENERATOR_0;
+    config->reference                     = ADC_REFERENCE_INT1V;
+    config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV4;
+    config->resolution                    = ADC_RESOLUTION_12BIT;
+    config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+    config->window.window_upper_value     = 0;
+    config->window.window_lower_value     = 0;
+    config->gain_factor                   = ADC_GAIN_FACTOR_1X;
 #if SAMR21
-	config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
+    config->positive_input                = ADC_POSITIVE_INPUT_PIN6 ;
 #else
- 	config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
+    config->positive_input                = ADC_POSITIVE_INPUT_PIN0 ;
 #endif
-	config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
-	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
-	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
-	config->left_adjust                   = false;
-	config->differential_mode             = false;
-	config->freerunning                   = false;
-	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
-	config->run_in_standby                = false;
-	config->reference_compensation_enable = false;
-	config->correction.correction_enable  = false;
-	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
-	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
-	config->sample_length                 = 0;
-	config->pin_scan.offset_start_scan    = 0;
-	config->pin_scan.inputs_to_scan       = 0;
+    config->negative_input                = ADC_NEGATIVE_INPUT_GND ;
+    config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+    config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+    config->left_adjust                   = false;
+    config->differential_mode             = false;
+    config->freerunning                   = false;
+    config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+    config->run_in_standby                = false;
+    config->reference_compensation_enable = false;
+    config->correction.correction_enable  = false;
+    config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+    config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+    config->sample_length                 = 0;
+    config->pin_scan.offset_start_scan    = 0;
+    config->pin_scan.inputs_to_scan       = 0;
 }
 
 /**
@@ -126,37 +126,40 @@ void adc_get_config_defaults(struct adc_config *const config)
  * \param[in] window_upper_value  Upper window monitor threshold value
   */
 void adc_set_window_mode(
-		struct adc_module *const module_inst,
-		const enum adc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value)
+        struct adc_module *const module_inst,
+        const enum adc_window_mode window_mode,
+        const int16_t window_lower_value,
+        const int16_t window_upper_value)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set window mode */
-	adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
+    /* Set window mode */
+    adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set lower window monitor threshold value */
-	adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
+    /* Set lower window monitor threshold value */
+    adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set upper window monitor threshold value */
-	adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
+    /* Set upper window monitor threshold value */
+    adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
 }
 
 /**
@@ -172,140 +175,141 @@ static inline void _adc_configure_ain_pin(uint32_t pin)
 {
 #define PIN_INVALID_ADC_AIN    0xFFFFUL
 
-	/* Pinmapping table for AINxx -> GPIO pin number */
-	const uint32_t pinmapping[] = {
+    /* Pinmapping table for AINxx -> GPIO pin number */
+    const uint32_t pinmapping[] = {
 #if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
 #elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
 #elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+            PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
 #elif SAMR21E
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif SAMR21G
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAMD09C) || (SAMD10C) || (SAMD11C)
-			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAMD09D)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+            PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+            PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU)
-			PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+            PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+            PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAMD10DM) || (SAMD11DM)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
-			PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
-			PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
-			PIN_PA10B_ADC_AIN8,  PIN_PA11B_ADC_AIN9,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PA04B_ADC_AIN2,  PIN_PA05B_ADC_AIN3,
+            PIN_PA06B_ADC_AIN4,  PIN_PA07B_ADC_AIN5,
+            PIN_PA14B_ADC_AIN6,  PIN_PA15B_ADC_AIN7,
+            PIN_PA10B_ADC_AIN8,  PIN_PA11B_ADC_AIN9,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif SAM_PART_IS_DEFINED(SAMHA1G14A) || SAM_PART_IS_DEFINED(SAMHA1G15A) || \
-		SAM_PART_IS_DEFINED(SAMHA1G16A)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+        SAM_PART_IS_DEFINED(SAMHA1G16A)
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_PB03B_ADC_AIN11,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
 #else
 #  error ADC pin mappings are not defined for this device.
 #endif
-		};
+        };
 
-	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+    uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
 
-	if (pin <= ADC_EXTCHANNEL_MSB) {
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+    if (pin <= ADC_EXTCHANNEL_MSB)
+    {
+        pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
 
-		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+        Assert(pin_map_result != PIN_INVALID_ADC_AIN);
 
-		struct system_pinmux_config config;
-		system_pinmux_get_config_defaults(&config);
+        struct system_pinmux_config config;
+        system_pinmux_get_config_defaults(&config);
 
-		/* Analog functions are all on MUX setting B */
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-		config.mux_position = 1;
+        /* Analog functions are all on MUX setting B */
+        config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+        config.mux_position = 1;
 
-		system_pinmux_pin_set_config(pin_map_result, &config);
-	}
+        system_pinmux_pin_set_config(pin_map_result, &config);
+    }
 }
 
 /**
@@ -321,323 +325,349 @@ static inline void _adc_configure_ain_pin(uint32_t pin)
  * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
  */
 static enum status_code _adc_set_config(
-		struct adc_module *const module_inst,
-		struct adc_config *const config)
+        struct adc_module *const module_inst,
+        struct adc_config *const config)
 {
-	uint8_t adjres = 0;
-	uint32_t resolution = ADC_RESOLUTION_16BIT;
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+    uint8_t adjres = 0;
+    uint32_t resolution = ADC_RESOLUTION_16BIT;
+    enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
 #if SAMD20
-	uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
+    uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
 #endif
 
-	/* Get the hardware module pointer */
-	Adc *const adc_module = module_inst->hw;
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(ADC_GCLK_ID);
-
-	/* Setup pinmuxing for analog inputs */
-	if (config->pin_scan.inputs_to_scan != 0) {
-		uint8_t offset = config->pin_scan.offset_start_scan;
-		uint8_t start_pin =
-				offset +(uint8_t)config->positive_input;
-		uint8_t end_pin =
-				start_pin + config->pin_scan.inputs_to_scan;
-
-		while (start_pin < end_pin) {
-			_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
-			start_pin++;
-			offset++;
-		}
-		_adc_configure_ain_pin(config->negative_input);
-	} else {
-		_adc_configure_ain_pin(config->positive_input);
-		_adc_configure_ain_pin(config->negative_input);
-	}
-
-	/* Configure run in standby */
-	adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
-
-	/* Configure reference */
-	adc_module->REFCTRL.reg =
-			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
-			(config->reference);
-
-	/* Set adjusting result and number of samples */
-	switch (config->resolution) {
-
-	case ADC_RESOLUTION_CUSTOM:
-		adjres = config->divide_result;
-		accumulate = config->accumulate_samples;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_13BIT:
-		/* Increase resolution by 1 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_4;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_14BIT:
-		/* Increase resolution by 2 bit */
-		adjres = ADC_DIVIDE_RESULT_4;
-		accumulate = ADC_ACCUMULATE_SAMPLES_16;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
+    /* Get the hardware module pointer */
+    Adc *const adc_module = module_inst->hw;
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(ADC_GCLK_ID);
+
+    /* Setup pinmuxing for analog inputs */
+    if (config->pin_scan.inputs_to_scan != 0)
+    {
+        uint8_t offset = config->pin_scan.offset_start_scan;
+        uint8_t start_pin =
+                offset +(uint8_t)config->positive_input;
+        uint8_t end_pin =
+                start_pin + config->pin_scan.inputs_to_scan;
+
+        while (start_pin < end_pin)
+        {
+            _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
+            start_pin++;
+            offset++;
+        }
+        _adc_configure_ain_pin(config->negative_input);
+    } else {
+        _adc_configure_ain_pin(config->positive_input);
+        _adc_configure_ain_pin(config->negative_input);
+    }
+
+    /* Configure run in standby */
+    adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
+
+    /* Configure reference */
+    adc_module->REFCTRL.reg =
+            (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
+            (config->reference);
+
+    /* Set adjusting result and number of samples */
+    switch (config->resolution)
+    {
+
+    case ADC_RESOLUTION_CUSTOM:
+        adjres = config->divide_result;
+        accumulate = config->accumulate_samples;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_13BIT:
+        /* Increase resolution by 1 bit */
+        adjres = ADC_DIVIDE_RESULT_2;
+        accumulate = ADC_ACCUMULATE_SAMPLES_4;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_14BIT:
+        /* Increase resolution by 2 bit */
+        adjres = ADC_DIVIDE_RESULT_4;
+        accumulate = ADC_ACCUMULATE_SAMPLES_16;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
 #if SAMD20
-	/* See $35.1.8 for ADC errata of SAM D20.
-	   The revisions before D have this issue.*/
-	case ADC_RESOLUTION_15BIT:
-		/* Increase resolution by 3 bit */
-		if(revision_num < REVISON_D_NUM) {
-			adjres = ADC_DIVIDE_RESULT_8;
-		} else {
-			adjres = ADC_DIVIDE_RESULT_2;
-		}
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_16BIT:
-		if(revision_num < REVISON_D_NUM) {
-			/* Increase resolution by 4 bit */
-			adjres = ADC_DIVIDE_RESULT_16;
-		} else {
-			adjres = ADC_DIVIDE_RESULT_DISABLE;
-		}
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
+    /* See $35.1.8 for ADC errata of SAM D20.
+       The revisions before D have this issue.*/
+    case ADC_RESOLUTION_15BIT:
+        /* Increase resolution by 3 bit */
+        if(revision_num < REVISON_D_NUM)
+        {
+            adjres = ADC_DIVIDE_RESULT_8;
+        } else {
+            adjres = ADC_DIVIDE_RESULT_2;
+        }
+        accumulate = ADC_ACCUMULATE_SAMPLES_64;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_16BIT:
+        if(revision_num < REVISON_D_NUM)
+        {
+            /* Increase resolution by 4 bit */
+            adjres = ADC_DIVIDE_RESULT_16;
+        } else {
+            adjres = ADC_DIVIDE_RESULT_DISABLE;
+        }
+        accumulate = ADC_ACCUMULATE_SAMPLES_256;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
 #else
-	case ADC_RESOLUTION_15BIT:
-		/* Increase resolution by 3 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_16BIT:
-		/* Increase resolution by 4 bit */
-		adjres = ADC_DIVIDE_RESULT_DISABLE;
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
+    case ADC_RESOLUTION_15BIT:
+        /* Increase resolution by 3 bit */
+        adjres = ADC_DIVIDE_RESULT_2;
+        accumulate = ADC_ACCUMULATE_SAMPLES_64;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_16BIT:
+        /* Increase resolution by 4 bit */
+        adjres = ADC_DIVIDE_RESULT_DISABLE;
+        accumulate = ADC_ACCUMULATE_SAMPLES_256;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
 #endif
-	case ADC_RESOLUTION_8BIT:
-		/* 8-bit result register */
-		resolution = ADC_RESOLUTION_8BIT;
-		break;
-	case ADC_RESOLUTION_10BIT:
-		/* 10-bit result register */
-		resolution = ADC_RESOLUTION_10BIT;
-		break;
-	case ADC_RESOLUTION_12BIT:
-		/* 12-bit result register */
-		resolution = ADC_RESOLUTION_12BIT;
-		break;
-
-	default:
-		/* Unknown. Abort. */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
-
-	/* Check validity of sample length value */
-	if (config->sample_length > 63) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		/* Configure sample length */
-		adc_module->SAMPCTRL.reg =
-				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure CTRLB */
-	adc_module->CTRLB.reg =
-			config->clock_prescaler |
-			resolution |
-			(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
-			(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
-			(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
-			(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
-
-	/* Check validity of window thresholds */
-	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
-		switch (resolution) {
-		case ADC_RESOLUTION_8BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 127 ||
-					config->window.window_lower_value < -128 ||
-					config->window.window_upper_value > 127 ||
-					config->window.window_upper_value < -128)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 255 ||
-					config->window.window_upper_value > 255){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_10BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 511 ||
-					config->window.window_lower_value < -512 ||
-					config->window.window_upper_value > 511 ||
-					config->window.window_upper_value < -512)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 1023 ||
-					config->window.window_upper_value > 1023){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_12BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 2047 ||
-					config->window.window_lower_value < -2048 ||
-					config->window.window_upper_value > 2047 ||
-					config->window.window_upper_value < -2048)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 4095 ||
-					config->window.window_upper_value > 4095){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_16BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 32767 ||
-					config->window.window_lower_value < -32768 ||
-					config->window.window_upper_value > 32767 ||
-					config->window.window_upper_value < -32768)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 65535 ||
-					config->window.window_upper_value > 65535){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		}
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure window mode */
-	adc_module->WINCTRL.reg = config->window.window_mode;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINLT.reg =
-			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINUT.reg = config->window.window_upper_value <<
-			ADC_WINUT_WINUT_Pos;
-
-	uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
-	if (inputs_to_scan > 0) {
-		/*
-		* Number of input sources included is the value written to INPUTSCAN
-		* plus 1.
-		*/
-		inputs_to_scan--;
-	}
-
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-			config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
-		/* Invalid number of input pins or input offset */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure pin scan mode and positive and negative input pins */
-	adc_module->INPUTCTRL.reg =
-			config->gain_factor |
-			(config->pin_scan.offset_start_scan <<
-			ADC_INPUTCTRL_INPUTOFFSET_Pos) |
-			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
-			config->negative_input |
-			config->positive_input;
-
-	/* Configure events */
-	adc_module->EVCTRL.reg = config->event_action;
-
-	/* Disable all interrupts */
-	adc_module->INTENCLR.reg =
-			(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
-			(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
-
-	if (config->correction.correction_enable){
-		/* Make sure gain_correction value is valid */
-		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set gain correction value */
-			adc_module->GAINCORR.reg = config->correction.gain_correction <<
-					ADC_GAINCORR_GAINCORR_Pos;
-		}
-
-		/* Make sure offset correction value is valid */
-		if (config->correction.offset_correction > 2047 ||
-				config->correction.offset_correction < -2048) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set offset correction value */
-			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
-					ADC_OFFSETCORR_OFFSETCORR_Pos;
-		}
-	}
-
-	/* Load in the fixed device ADC calibration constants */
-	adc_module->CALIB.reg =
-			ADC_CALIB_BIAS_CAL(
-				(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
-			) |
-			ADC_CALIB_LINEARITY_CAL(
-				(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
-			);
-
-	return STATUS_OK;
+    case ADC_RESOLUTION_8BIT:
+        /* 8-bit result register */
+        resolution = ADC_RESOLUTION_8BIT;
+        break;
+    case ADC_RESOLUTION_10BIT:
+        /* 10-bit result register */
+        resolution = ADC_RESOLUTION_10BIT;
+        break;
+    case ADC_RESOLUTION_12BIT:
+        /* 12-bit result register */
+        resolution = ADC_RESOLUTION_12BIT;
+        break;
+
+    default:
+        /* Unknown. Abort. */
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+    /* Check validity of sample length value */
+    if (config->sample_length > 63)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        /* Configure sample length */
+        adc_module->SAMPCTRL.reg =
+                (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
+    }
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure CTRLB */
+    adc_module->CTRLB.reg =
+            config->clock_prescaler |
+            resolution |
+            (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
+            (config->freerunning << ADC_CTRLB_FREERUN_Pos) |
+            (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
+            (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
+
+    /* Check validity of window thresholds */
+    if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE)
+    {
+        switch (resolution)
+        {
+        case ADC_RESOLUTION_8BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 127 ||
+                    config->window.window_lower_value < -128 ||
+                    config->window.window_upper_value > 127 ||
+                    config->window.window_upper_value < -128))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 255 ||
+                    config->window.window_upper_value > 255)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_10BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 511 ||
+                    config->window.window_lower_value < -512 ||
+                    config->window.window_upper_value > 511 ||
+                    config->window.window_upper_value < -512))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 1023 ||
+                    config->window.window_upper_value > 1023)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_12BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 2047 ||
+                    config->window.window_lower_value < -2048 ||
+                    config->window.window_upper_value > 2047 ||
+                    config->window.window_upper_value < -2048))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 4095 ||
+                    config->window.window_upper_value > 4095)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_16BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 32767 ||
+                    config->window.window_lower_value < -32768 ||
+                    config->window.window_upper_value > 32767 ||
+                    config->window.window_upper_value < -32768))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 65535 ||
+                    config->window.window_upper_value > 65535)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        }
+    }
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure window mode */
+    adc_module->WINCTRL.reg = config->window.window_mode;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    adc_module->WINLT.reg =
+            config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    adc_module->WINUT.reg = config->window.window_upper_value <<
+            ADC_WINUT_WINUT_Pos;
+
+    uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
+    if (inputs_to_scan > 0)
+    {
+        /*
+        * Number of input sources included is the value written to INPUTSCAN
+        * plus 1.
+        */
+        inputs_to_scan--;
+    }
+
+    if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+            config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos))
+            {
+        /* Invalid number of input pins or input offset */
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure pin scan mode and positive and negative input pins */
+    adc_module->INPUTCTRL.reg =
+            config->gain_factor |
+            (config->pin_scan.offset_start_scan <<
+            ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+            (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
+            config->negative_input |
+            config->positive_input;
+
+    /* Configure events */
+    adc_module->EVCTRL.reg = config->event_action;
+
+    /* Disable all interrupts */
+    adc_module->INTENCLR.reg =
+            (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
+            (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
+
+    if (config->correction.correction_enable)
+    {
+        /* Make sure gain_correction value is valid */
+        if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        } else {
+            /* Set gain correction value */
+            adc_module->GAINCORR.reg = config->correction.gain_correction <<
+                    ADC_GAINCORR_GAINCORR_Pos;
+        }
+
+        /* Make sure offset correction value is valid */
+        if (config->correction.offset_correction > 2047 ||
+                config->correction.offset_correction < -2048)
+                {
+            return STATUS_ERR_INVALID_ARG;
+        } else {
+            /* Set offset correction value */
+            adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+                    ADC_OFFSETCORR_OFFSETCORR_Pos;
+        }
+    }
+
+    /* Load in the fixed device ADC calibration constants */
+    adc_module->CALIB.reg =
+            ADC_CALIB_BIAS_CAL(
+                (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
+            ) |
+            ADC_CALIB_LINEARITY_CAL(
+                (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
+            );
+
+    return STATUS_OK;
 }
 
 /**
  * \brief Initializes the ADC channel sequence
  *
- * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one 
- * automatically after a conversion done, causing the next conversion 
- * to be done with the positive input equal to MUXPOS + INPUTOFFSET, 
+ * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
+ * automatically after a conversion done, causing the next conversion
+ * to be done with the positive input equal to MUXPOS + INPUTOFFSET,
  * it is scanning continuously one by one even ADC channels are not continuous.
  *
  * Initializes the ADC channel sequence by the sequence of pin_array.
@@ -647,10 +677,11 @@ static enum status_code _adc_set_config(
  */
 void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
 {
-	for (int i = 0; i < size; i++) {
-		_adc_configure_ain_pin(pin_array[i]);
-  	}
-}	
+    for (int i = 0; i < size; i++)
+    {
+        _adc_configure_ain_pin(pin_array[i]);
+    }
+}
 
 /**
  * \brief Initializes the ADC
@@ -669,59 +700,64 @@ void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
  * \retval STATUS_ERR_DENIED        The module is enabled
  */
 enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config)
+        struct adc_module *const module_inst,
+        Adc *hw,
+        struct adc_config *config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
-
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
-
-	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
-
-	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Store the selected reference for later use */
-	module_inst->reference = config->reference;
-
-	/* Make sure bandgap is enabled if requested by the config */
-	if (module_inst->reference == ADC_REFERENCE_INT1V) {
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
+
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
+
+    if (hw->CTRLA.reg & ADC_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
+
+    if (hw->CTRLA.reg & ADC_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Store the selected reference for later use */
+    module_inst->reference = config->reference;
+
+    /* Make sure bandgap is enabled if requested by the config */
+    if (module_inst->reference == ADC_REFERENCE_INT1V)
+    {
+        system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+    }
 
 #if ADC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	};
-
-	module_inst->registered_callback_mask = 0;
-	module_inst->enabled_callback_mask = 0;
-	module_inst->remaining_conversions = 0;
-	module_inst->job_status = STATUS_OK;
-
-	_adc_instances[0] = module_inst;
-
-	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
-			!config->freerunning) {
-		module_inst->software_trigger = true;
-	} else {
-		module_inst->software_trigger = false;
-	}
+    for (uint8_t i = 0; i < ADC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    };
+
+    module_inst->registered_callback_mask = 0;
+    module_inst->enabled_callback_mask = 0;
+    module_inst->remaining_conversions = 0;
+    module_inst->job_status = STATUS_OK;
+
+    _adc_instances[0] = module_inst;
+
+    if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+            !config->freerunning)
+            {
+        module_inst->software_trigger = true;
+    } else {
+        module_inst->software_trigger = false;
+    }
 #endif
 
-	/* Write configuration to module */
-	return _adc_set_config(module_inst, config);
+    /* Write configuration to module */
+    return _adc_set_config(module_inst, config);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
index bc66eb5158b7..cd1070054581 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_callback.c
@@ -49,63 +49,73 @@ struct adc_module *_adc_instances[ADC_INST_NUM];
 
 static void _adc_interrupt_handler(const uint8_t instance)
 {
-	struct adc_module *module = _adc_instances[instance];
-
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->INTFLAG.reg;
-
-	if (flags & ADC_INTFLAG_RESRDY) {
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER))) {
-			/* clear interrupt flag */
-			module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
-
-			while (adc_is_syncing(module)) {
-				/* Wait for synchronization */
-			}
-
-			/* store ADC result in job buffer */
-			*(module->job_buffer++) = module->hw->RESULT.reg;
-
-			if (--module->remaining_conversions > 0) {
-				if (module->software_trigger == true) {
-					adc_start_conversion(module);
-				}
-			} else {
-				if (module->job_status == STATUS_BUSY) {
-					/* job is complete. update status,disable interrupt
-					 *and call callback */
-					module->job_status = STATUS_OK;
-					adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
-
-					(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
-				}
-			}
-		}
-	}
-
-	if (flags & ADC_INTFLAG_WINMON) {
-		module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
-			(module->callback[ADC_CALLBACK_WINDOW])(module);
-		}
-
-	}
-
-	if (flags & ADC_INTFLAG_OVERRUN) {
-		module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
-			(module->callback[ADC_CALLBACK_ERROR])(module);
-		}
-	}
+    struct adc_module *module = _adc_instances[instance];
+
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->INTFLAG.reg;
+
+    if (flags & ADC_INTFLAG_RESRDY)
+    {
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)))
+                {
+            /* clear interrupt flag */
+            module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+
+            while (adc_is_syncing(module))
+            {
+                /* Wait for synchronization */
+            }
+
+            /* store ADC result in job buffer */
+            *(module->job_buffer++) = module->hw->RESULT.reg;
+
+            if (--module->remaining_conversions > 0)
+            {
+                if (module->software_trigger == true)
+                {
+                    adc_start_conversion(module);
+                }
+            } else {
+                if (module->job_status == STATUS_BUSY)
+                {
+                    /* job is complete. update status,disable interrupt
+                     *and call callback */
+                    module->job_status = STATUS_OK;
+                    adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
+
+                    (module->callback[ADC_CALLBACK_READ_BUFFER])(module);
+                }
+            }
+        }
+    }
+
+    if (flags & ADC_INTFLAG_WINMON)
+    {
+        module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW)))
+                {
+            (module->callback[ADC_CALLBACK_WINDOW])(module);
+        }
+
+    }
+
+    if (flags & ADC_INTFLAG_OVERRUN)
+    {
+        module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR)))
+                {
+            (module->callback[ADC_CALLBACK_ERROR])(module);
+        }
+    }
 }
 
 /** Interrupt handler for the ADC module. */
 void ADC_Handler(void)
 {
-	_adc_interrupt_handler(0);
+    _adc_interrupt_handler(0);
 }
 
 /**
@@ -122,19 +132,19 @@ void ADC_Handler(void)
  *
  */
 void adc_register_callback(
-		struct adc_module *const module,
-		adc_callback_t callback_func,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        adc_callback_t callback_func,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->registered_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->registered_callback_mask |= (1 << callback_type);
 }
 
 /**
@@ -147,17 +157,17 @@ void adc_register_callback(
  *
  */
 void adc_unregister_callback(
-		struct adc_module *const module,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->registered_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->registered_callback_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -179,30 +189,32 @@ void adc_unregister_callback(
  * \retval STATUS_BUSY      The ADC is already busy with another job
  */
 enum status_code adc_read_buffer_job(
-		struct adc_module *const module_inst,
-		uint16_t *buffer,
-		uint16_t samples)
+        struct adc_module *const module_inst,
+        uint16_t *buffer,
+        uint16_t samples)
 {
-	Assert(module_inst);
-	Assert(samples);
-	Assert(buffer);
+    Assert(module_inst);
+    Assert(samples);
+    Assert(buffer);
 
-	if(module_inst->remaining_conversions != 0 ||
-			module_inst->job_status == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
+    if(module_inst->remaining_conversions != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	module_inst->job_status = STATUS_BUSY;
-	module_inst->remaining_conversions = samples;
-	module_inst->job_buffer = buffer;
+    module_inst->job_status = STATUS_BUSY;
+    module_inst->remaining_conversions = samples;
+    module_inst->job_buffer = buffer;
 
-	adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+    adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
 
-	if(module_inst->software_trigger == true) {
-		adc_start_conversion(module_inst);
-	}
+    if(module_inst->software_trigger == true)
+    {
+        adc_start_conversion(module_inst);
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -216,17 +228,18 @@ enum status_code adc_read_buffer_job(
  * \return Status of the job.
  */
 enum status_code adc_get_job_status(
-		struct adc_module *module_inst,
-		enum adc_job_type type)
+        struct adc_module *module_inst,
+        enum adc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == ADC_JOB_READ_BUFFER ) {
-		return module_inst->job_status;
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == ADC_JOB_READ_BUFFER )
+    {
+        return module_inst->job_status;
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -238,18 +251,19 @@ enum status_code adc_get_job_status(
  * \param [in]  type        Type of job to abort
  */
 void adc_abort_job(
-		struct adc_module *module_inst,
-		enum adc_job_type type)
+        struct adc_module *module_inst,
+        enum adc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == ADC_JOB_READ_BUFFER) {
-		/* Disable interrupt */
-		adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
-		/* Mark job as aborted */
-		module_inst->job_status = STATUS_ABORTED;
-		module_inst->remaining_conversions = 0;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == ADC_JOB_READ_BUFFER)
+    {
+        /* Disable interrupt */
+        adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+        /* Mark job as aborted */
+        module_inst->job_status = STATUS_ABORTED;
+        module_inst->remaining_conversions = 0;
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
index 203f15be1459..38cd6a35248d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_d_r_h/adc_feature.h
@@ -75,15 +75,15 @@ typedef void (*adc_callback_t)(struct adc_module *const module);
  *
  */
 enum adc_callback {
-	/** Callback for buffer received */
-	ADC_CALLBACK_READ_BUFFER,
-	/** Callback when window is hit */
-	ADC_CALLBACK_WINDOW,
-	/** Callback for error */
-	ADC_CALLBACK_ERROR,
+    /** Callback for buffer received */
+    ADC_CALLBACK_READ_BUFFER,
+    /** Callback when window is hit */
+    ADC_CALLBACK_WINDOW,
+    /** Callback for error */
+    ADC_CALLBACK_ERROR,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	ADC_CALLBACK_N,
+    /** Number of available callbacks */
+    ADC_CALLBACK_N,
 #  endif
 };
 
@@ -96,16 +96,16 @@ enum adc_callback {
  *
  */
 enum adc_reference {
-	/** 1.0V voltage reference */
-	ADC_REFERENCE_INT1V   = ADC_REFCTRL_REFSEL_INT1V,
-	/** 1/1.48V<SUB>CC</SUB> reference */
-	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
-	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
-	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
-	/** External reference A */
-	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
-	/** External reference B */
-	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+    /** 1.0V voltage reference */
+    ADC_REFERENCE_INT1V   = ADC_REFCTRL_REFSEL_INT1V,
+    /** 1/1.48V<SUB>CC</SUB> reference */
+    ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+    /** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+    ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+    /** External reference A */
+    ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+    /** External reference B */
+    ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
 };
 
 /**
@@ -115,22 +115,22 @@ enum adc_reference {
  *
  */
 enum adc_clock_prescaler {
-	/** ADC clock division factor 4 */
-	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
-	/** ADC clock division factor 8 */
-	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
-	/** ADC clock division factor 16 */
-	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
-	/** ADC clock division factor 32 */
-	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
-	/** ADC clock division factor 64 */
-	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
-	/** ADC clock division factor 128 */
-	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
-	/** ADC clock division factor 256 */
-	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
-	/** ADC clock division factor 512 */
-	ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
+    /** ADC clock division factor 4 */
+    ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+    /** ADC clock division factor 8 */
+    ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+    /** ADC clock division factor 16 */
+    ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+    /** ADC clock division factor 32 */
+    ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+    /** ADC clock division factor 64 */
+    ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+    /** ADC clock division factor 128 */
+    ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+    /** ADC clock division factor 256 */
+    ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+    /** ADC clock division factor 512 */
+    ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
 };
 
 /**
@@ -140,27 +140,27 @@ enum adc_clock_prescaler {
  *
  */
 enum adc_resolution {
-	/** ADC 12-bit resolution */
-	ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
-	/** ADC 16-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
-	/** ADC 10-bit resolution */
-	ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
-	/** ADC 8-bit resolution */
-	ADC_RESOLUTION_8BIT  = ADC_CTRLB_RESSEL_8BIT,
-	/** ADC 13-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_13BIT,
-	/** ADC 14-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_14BIT,
-	/** ADC 15-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_15BIT,
-	/** ADC 16-bit result register for use with averaging. When using this mode
-	  * the ADC result register will be set to 16-bit wide, and the number of
-	  * samples to accumulate and the division factor is configured by the
-	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
-	  * members in the configuration struct.
-	  */
-	ADC_RESOLUTION_CUSTOM,
+    /** ADC 12-bit resolution */
+    ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
+    /** ADC 16-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
+    /** ADC 10-bit resolution */
+    ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
+    /** ADC 8-bit resolution */
+    ADC_RESOLUTION_8BIT  = ADC_CTRLB_RESSEL_8BIT,
+    /** ADC 13-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_13BIT,
+    /** ADC 14-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_14BIT,
+    /** ADC 15-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_15BIT,
+    /** ADC 16-bit result register for use with averaging. When using this mode
+      * the ADC result register will be set to 16-bit wide, and the number of
+      * samples to accumulate and the division factor is configured by the
+      * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+      * members in the configuration struct.
+      */
+    ADC_RESOLUTION_CUSTOM,
 };
 
 /**
@@ -170,16 +170,16 @@ enum adc_resolution {
  *
  */
 enum adc_window_mode {
-	/** No window mode */
-	ADC_WINDOW_MODE_DISABLE          = ADC_WINCTRL_WINMODE_DISABLE,
-	/** RESULT > WINLT */
-	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_WINCTRL_WINMODE_MODE1,
-	/** RESULT < WINUT */
-	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_WINCTRL_WINMODE_MODE2,
-	/** WINLT < RESULT < WINUT */
-	ADC_WINDOW_MODE_BETWEEN          = ADC_WINCTRL_WINMODE_MODE3,
-	/** !(WINLT < RESULT < WINUT) */
-	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
+    /** No window mode */
+    ADC_WINDOW_MODE_DISABLE          = ADC_WINCTRL_WINMODE_DISABLE,
+    /** RESULT > WINLT */
+    ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_WINCTRL_WINMODE_MODE1,
+    /** RESULT < WINUT */
+    ADC_WINDOW_MODE_BELOW_UPPER      = ADC_WINCTRL_WINMODE_MODE2,
+    /** WINLT < RESULT < WINUT */
+    ADC_WINDOW_MODE_BETWEEN          = ADC_WINCTRL_WINMODE_MODE3,
+    /** !(WINLT < RESULT < WINUT) */
+    ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
 };
 
 /**
@@ -189,18 +189,18 @@ enum adc_window_mode {
  *
  */
 enum adc_gain_factor {
-	/** 1x gain */
-	ADC_GAIN_FACTOR_1X   = ADC_INPUTCTRL_GAIN_1X,
-	/** 2x gain */
-	ADC_GAIN_FACTOR_2X   = ADC_INPUTCTRL_GAIN_2X,
-	/** 4x gain */
-	ADC_GAIN_FACTOR_4X   = ADC_INPUTCTRL_GAIN_4X,
-	/** 8x gain */
-	ADC_GAIN_FACTOR_8X   = ADC_INPUTCTRL_GAIN_8X,
-	/** 16x gain */
-	ADC_GAIN_FACTOR_16X  = ADC_INPUTCTRL_GAIN_16X,
-	/** 1/2x gain */
-	ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
+    /** 1x gain */
+    ADC_GAIN_FACTOR_1X   = ADC_INPUTCTRL_GAIN_1X,
+    /** 2x gain */
+    ADC_GAIN_FACTOR_2X   = ADC_INPUTCTRL_GAIN_2X,
+    /** 4x gain */
+    ADC_GAIN_FACTOR_4X   = ADC_INPUTCTRL_GAIN_4X,
+    /** 8x gain */
+    ADC_GAIN_FACTOR_8X   = ADC_INPUTCTRL_GAIN_8X,
+    /** 16x gain */
+    ADC_GAIN_FACTOR_16X  = ADC_INPUTCTRL_GAIN_16X,
+    /** 1/2x gain */
+    ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
 };
 
 /**
@@ -210,12 +210,12 @@ enum adc_gain_factor {
  *
  */
 enum adc_event_action {
-	/** Event action disabled */
-	ADC_EVENT_ACTION_DISABLED         = 0,
-	/** Flush ADC and start conversion */
-	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
-	/** Start conversion */
-	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+    /** Event action disabled */
+    ADC_EVENT_ACTION_DISABLED         = 0,
+    /** Flush ADC and start conversion */
+    ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
+    /** Start conversion */
+    ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
 };
 
 /**
@@ -225,56 +225,56 @@ enum adc_event_action {
  *
  */
 enum adc_positive_input {
-	/** ADC0 pin */
-	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_PIN0,
-	/** ADC1 pin */
-	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_PIN1,
-	/** ADC2 pin */
-	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_PIN2,
-	/** ADC3 pin */
-	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_PIN3,
-	/** ADC4 pin */
-	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_PIN4,
-	/** ADC5 pin */
-	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_PIN5,
-	/** ADC6 pin */
-	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_PIN6,
-	/** ADC7 pin */
-	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_PIN7,
-	/** ADC8 pin */
-	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_PIN8,
-	/** ADC9 pin */
-	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_PIN9,
-	/** ADC10 pin */
-	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_PIN10,
-	/** ADC11 pin */
-	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_PIN11,
-	/** ADC12 pin */
-	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_PIN12,
-	/** ADC13 pin */
-	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_PIN13,
-	/** ADC14 pin */
-	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_PIN14,
-	/** ADC15 pin */
-	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_PIN15,
-	/** ADC16 pin */
-	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_PIN16,
-	/** ADC17 pin */
-	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_PIN17,
-	/** ADC18 pin */
-	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_PIN18,
-	/** ADC19 pin */
-	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_PIN19,
-	/** Temperature reference */
-	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
-	/** Bandgap voltage */
-	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
-	/** 1/4 scaled core supply */
-	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
-	/** 1/4 scaled I/O supply */
-	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
-	/** DAC input */
-	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+    /** ADC0 pin */
+    ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_PIN0,
+    /** ADC1 pin */
+    ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_PIN1,
+    /** ADC2 pin */
+    ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_PIN2,
+    /** ADC3 pin */
+    ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_PIN3,
+    /** ADC4 pin */
+    ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_PIN4,
+    /** ADC5 pin */
+    ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_PIN5,
+    /** ADC6 pin */
+    ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_PIN6,
+    /** ADC7 pin */
+    ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_PIN7,
+    /** ADC8 pin */
+    ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_PIN8,
+    /** ADC9 pin */
+    ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_PIN9,
+    /** ADC10 pin */
+    ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_PIN10,
+    /** ADC11 pin */
+    ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_PIN11,
+    /** ADC12 pin */
+    ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_PIN12,
+    /** ADC13 pin */
+    ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_PIN13,
+    /** ADC14 pin */
+    ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_PIN14,
+    /** ADC15 pin */
+    ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_PIN15,
+    /** ADC16 pin */
+    ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_PIN16,
+    /** ADC17 pin */
+    ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_PIN17,
+    /** ADC18 pin */
+    ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_PIN18,
+    /** ADC19 pin */
+    ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_PIN19,
+    /** Temperature reference */
+    ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+    /** Bandgap voltage */
+    ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+    /** 1/4 scaled core supply */
+    ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+    /** 1/4 scaled I/O supply */
+    ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+    /** DAC input */
+    ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
 };
 
 /**
@@ -284,26 +284,26 @@ enum adc_positive_input {
  *
  */
 enum adc_negative_input {
-	/** ADC0 pin */
-	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_PIN0,
-	/** ADC1 pin */
-	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_PIN1,
-	/** ADC2 pin */
-	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_PIN2,
-	/** ADC3 pin */
-	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_PIN3,
-	/** ADC4 pin */
-	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_PIN4,
-	/** ADC5 pin */
-	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_PIN5,
-	/** ADC6 pin */
-	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_PIN6,
-	/** ADC7 pin */
-	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_PIN7,
-	/** Internal ground */
-	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG_GND,
-	/** I/O ground */
-	ADC_NEGATIVE_INPUT_IOGND         = ADC_INPUTCTRL_MUXNEG_IOGND,
+    /** ADC0 pin */
+    ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_PIN0,
+    /** ADC1 pin */
+    ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_PIN1,
+    /** ADC2 pin */
+    ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_PIN2,
+    /** ADC3 pin */
+    ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_PIN3,
+    /** ADC4 pin */
+    ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_PIN4,
+    /** ADC5 pin */
+    ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_PIN5,
+    /** ADC6 pin */
+    ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_PIN6,
+    /** ADC7 pin */
+    ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_PIN7,
+    /** Internal ground */
+    ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG_GND,
+    /** I/O ground */
+    ADC_NEGATIVE_INPUT_IOGND         = ADC_INPUTCTRL_MUXNEG_IOGND,
 };
 
 /**
@@ -315,28 +315,28 @@ enum adc_negative_input {
  *
  */
 enum adc_accumulate_samples {
-	/** No averaging */
-	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
-	/** Average 2 samples */
-	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
-	/** Average 4 samples */
-	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
-	/** Average 8 samples */
-	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
-	/** Average 16 samples */
-	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
-	/** Average 32 samples */
-	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
-	/** Average 64 samples */
-	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
-	/** Average 128 samples */
-	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
-	/** Average 256 samples */
-	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
-	/** Average 512 samples */
-	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
-	/** Average 1024 samples */
-	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+    /** No averaging */
+    ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+    /** Average 2 samples */
+    ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+    /** Average 4 samples */
+    ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+    /** Average 8 samples */
+    ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+    /** Average 16 samples */
+    ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+    /** Average 32 samples */
+    ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+    /** Average 64 samples */
+    ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+    /** Average 128 samples */
+    ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+    /** Average 256 samples */
+    ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+    /** Average 512 samples */
+    ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+    /** Average 1024 samples */
+    ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
 };
 
 /**
@@ -349,22 +349,22 @@ enum adc_accumulate_samples {
  * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
  */
 enum adc_divide_result {
-	/** Don't divide result register after accumulation */
-	ADC_DIVIDE_RESULT_DISABLE = 0,
-	/** Divide result register by 2 after accumulation */
-	ADC_DIVIDE_RESULT_2       = 1,
-	/** Divide result register by 4 after accumulation */
-	ADC_DIVIDE_RESULT_4       = 2,
-	/** Divide result register by 8 after accumulation */
-	ADC_DIVIDE_RESULT_8       = 3,
-	/** Divide result register by 16 after accumulation */
-	ADC_DIVIDE_RESULT_16      = 4,
-	/** Divide result register by 32 after accumulation */
-	ADC_DIVIDE_RESULT_32      = 5,
-	/** Divide result register by 64 after accumulation */
-	ADC_DIVIDE_RESULT_64      = 6,
-	/** Divide result register by 128 after accumulation */
-	ADC_DIVIDE_RESULT_128     = 7,
+    /** Don't divide result register after accumulation */
+    ADC_DIVIDE_RESULT_DISABLE = 0,
+    /** Divide result register by 2 after accumulation */
+    ADC_DIVIDE_RESULT_2       = 1,
+    /** Divide result register by 4 after accumulation */
+    ADC_DIVIDE_RESULT_4       = 2,
+    /** Divide result register by 8 after accumulation */
+    ADC_DIVIDE_RESULT_8       = 3,
+    /** Divide result register by 16 after accumulation */
+    ADC_DIVIDE_RESULT_16      = 4,
+    /** Divide result register by 32 after accumulation */
+    ADC_DIVIDE_RESULT_32      = 5,
+    /** Divide result register by 64 after accumulation */
+    ADC_DIVIDE_RESULT_64      = 6,
+    /** Divide result register by 128 after accumulation */
+    ADC_DIVIDE_RESULT_128     = 7,
 };
 
 #if ADC_CALLBACK_MODE == true
@@ -372,12 +372,12 @@ enum adc_divide_result {
  * Enum for the possible ADC interrupt flags.
  */
 enum adc_interrupt_flag {
-	/** ADC result ready */
-	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
-	/** Window monitor match */
-	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
-	/** ADC result overwritten before read */
-	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+    /** ADC result ready */
+    ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+    /** Window monitor match */
+    ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+    /** ADC result overwritten before read */
+    ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
 };
 #endif
 
@@ -389,16 +389,16 @@ enum adc_interrupt_flag {
  *
  */
 enum adc_oversampling_and_decimation {
-	/** Don't use oversampling and decimation mode */
-	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
-	/** 1-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
-	/** 2-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
-	/** 3-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
-	/** 4-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+    /** Don't use oversampling and decimation mode */
+    ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+    /** 1-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+    /** 2-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+    /** 3-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+    /** 4-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_4BIT
 };
 
 /**
@@ -407,12 +407,12 @@ enum adc_oversampling_and_decimation {
  * Window monitor configuration structure.
  */
 struct adc_window_config {
-	/** Selected window mode */
-	enum adc_window_mode window_mode;
-	/** Lower window value */
-	int32_t window_lower_value;
-	/** Upper window value */
-	int32_t window_upper_value;
+    /** Selected window mode */
+    enum adc_window_mode window_mode;
+    /** Lower window value */
+    int32_t window_lower_value;
+    /** Upper window value */
+    int32_t window_upper_value;
 };
 
 /**
@@ -422,10 +422,10 @@ struct adc_window_config {
  * disable events via \ref adc_enable_events() and \ref adc_disable_events().
  */
 struct adc_events {
-	/** Enable event generation on conversion done */
-	bool generate_event_on_conversion_done;
-	/** Enable event generation on window monitor */
-	bool generate_event_on_window_monitor;
+    /** Enable event generation on conversion done */
+    bool generate_event_on_conversion_done;
+    /** Enable event generation on window monitor */
+    bool generate_event_on_window_monitor;
 };
 
 /**
@@ -436,25 +436,25 @@ struct adc_events {
  * \ref adc_get_config_defaults.
  */
 struct adc_correction_config {
-	/**
-	 * Enables correction for gain and offset based on values of gain_correction and
-	 * offset_correction if set to true
-	 */
-	bool correction_enable;
-	/**
-	 * This value defines how the ADC conversion result is compensated for gain
-	 * error before written to the result register. This is a fractional value,
-	 * 1-bit integer plus an 11-bit fraction, therefore
-	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
-	 * \c 0b010000000000 to \c 0b111111111111.
-	 */
-	uint16_t gain_correction;
-	/**
-	 * This value defines how the ADC conversion result is compensated for
-	 * offset error before written to the result register. This is a 12-bit
-	 * value in two's complement format.
-	 */
-	int16_t offset_correction;
+    /**
+     * Enables correction for gain and offset based on values of gain_correction and
+     * offset_correction if set to true
+     */
+    bool correction_enable;
+    /**
+     * This value defines how the ADC conversion result is compensated for gain
+     * error before written to the result register. This is a fractional value,
+     * 1-bit integer plus an 11-bit fraction, therefore
+     * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+     * \c 0b010000000000 to \c 0b111111111111.
+     */
+    uint16_t gain_correction;
+    /**
+     * This value defines how the ADC conversion result is compensated for
+     * offset error before written to the result register. This is a 12-bit
+     * value in two's complement format.
+     */
+    int16_t offset_correction;
 };
 
 /**
@@ -464,16 +464,16 @@ struct adc_correction_config {
  * be initialized by \ref adc_get_config_defaults.
  */
 struct adc_pin_scan_config {
-	/**
-	 * Offset (relative to selected positive input) of the first input pin to be
-	 * used in pin scan mode
-	 */
-	uint8_t offset_start_scan;
-	/**
-	 * Number of input pins to scan in pin scan mode. A value below two will
-	 * disable pin scan mode.
-	 */
-	uint8_t inputs_to_scan;
+    /**
+     * Offset (relative to selected positive input) of the first input pin to be
+     * used in pin scan mode
+     */
+    uint8_t offset_start_scan;
+    /**
+     * Number of input pins to scan in pin scan mode. A value below two will
+     * disable pin scan mode.
+     */
+    uint8_t inputs_to_scan;
 };
 
 /**
@@ -484,60 +484,60 @@ struct adc_pin_scan_config {
  * function before being modified by the user application.
  */
 struct adc_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Voltage reference */
-	enum adc_reference reference;
-	/** Clock prescaler */
-	enum adc_clock_prescaler clock_prescaler;
-	/** Result resolution */
-	enum adc_resolution resolution;
-	/** Gain factor */
-	enum adc_gain_factor gain_factor;
-	/** Positive Multiplexer (MUX) input */
-	enum adc_positive_input positive_input;
-	/** Negative MUX input. For singled-ended conversion mode, the negative
-	 * input must be connected to ground. This ground could be the internal
-	 * GND, IOGND or an external ground connected to a pin. */
-	enum adc_negative_input negative_input;
-	/** Number of ADC samples to accumulate when using the
-	 *  \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
-	 *  result resolution will be changed accordingly.
-	 */
-	enum adc_accumulate_samples accumulate_samples;
-	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
-	enum adc_divide_result divide_result;
-	/** Left adjusted result */
-	bool left_adjust;
-	/** Enables differential mode if true. 
-	 * if false, ADC will run in singled-ended mode. */
-	bool differential_mode;
-	/** Enables free running mode if true */
-	bool freerunning;
-	/** Enables ADC in standby sleep mode if true */
-	bool run_in_standby;
-	/**
-	 * Enables reference buffer offset compensation if true.
-	 * This will increase the accuracy of the gain stage, but decreases the input
-	 * impedance; therefore the startup time of the reference must be increased.
-	 */
-	bool reference_compensation_enable;
-	/**
-	 * This value (0-63) control the ADC sampling time in number of half ADC
-	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
-	 * controlling the ADC input impedance. Sampling time is set according to
-	 * the formula:
-	 * Sample time = (sample_length+1) * (ADCclk / 2).
-	 */
-	uint8_t sample_length;
-	/** Window monitor configuration structure */
-	struct adc_window_config window;
-	/** Gain and offset correction configuration structure */
-	struct adc_correction_config correction;
-	/** Event action to take on incoming event */
-	enum adc_event_action event_action;
-	/** Pin scan configuration structure */
-	struct adc_pin_scan_config pin_scan;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** Voltage reference */
+    enum adc_reference reference;
+    /** Clock prescaler */
+    enum adc_clock_prescaler clock_prescaler;
+    /** Result resolution */
+    enum adc_resolution resolution;
+    /** Gain factor */
+    enum adc_gain_factor gain_factor;
+    /** Positive Multiplexer (MUX) input */
+    enum adc_positive_input positive_input;
+    /** Negative MUX input. For singled-ended conversion mode, the negative
+     * input must be connected to ground. This ground could be the internal
+     * GND, IOGND or an external ground connected to a pin. */
+    enum adc_negative_input negative_input;
+    /** Number of ADC samples to accumulate when using the
+     *  \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases,
+     *  result resolution will be changed accordingly.
+     */
+    enum adc_accumulate_samples accumulate_samples;
+    /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+    enum adc_divide_result divide_result;
+    /** Left adjusted result */
+    bool left_adjust;
+    /** Enables differential mode if true.
+     * if false, ADC will run in singled-ended mode. */
+    bool differential_mode;
+    /** Enables free running mode if true */
+    bool freerunning;
+    /** Enables ADC in standby sleep mode if true */
+    bool run_in_standby;
+    /**
+     * Enables reference buffer offset compensation if true.
+     * This will increase the accuracy of the gain stage, but decreases the input
+     * impedance; therefore the startup time of the reference must be increased.
+     */
+    bool reference_compensation_enable;
+    /**
+     * This value (0-63) control the ADC sampling time in number of half ADC
+     * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+     * controlling the ADC input impedance. Sampling time is set according to
+     * the formula:
+     * Sample time = (sample_length+1) * (ADCclk / 2).
+     */
+    uint8_t sample_length;
+    /** Window monitor configuration structure */
+    struct adc_window_config window;
+    /** Gain and offset correction configuration structure */
+    struct adc_correction_config correction;
+    /** Event action to take on incoming event */
+    enum adc_event_action event_action;
+    /** Pin scan configuration structure */
+    struct adc_pin_scan_config pin_scan;
 };
 
 /**
@@ -551,25 +551,25 @@ struct adc_config {
  */
 struct adc_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to ADC hardware module */
-	Adc *hw;
-	/** Keep reference configuration so we know when enable is called */
-	enum adc_reference reference;
+    /** Pointer to ADC hardware module */
+    Adc *hw;
+    /** Keep reference configuration so we know when enable is called */
+    enum adc_reference reference;
 #  if ADC_CALLBACK_MODE == true
-	/** Array to store callback functions */
-	adc_callback_t callback[ADC_CALLBACK_N];
-	/** Pointer to buffer used for ADC results */
-	volatile uint16_t *job_buffer;
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback_mask;
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status;
-	/** If software triggering is needed */
-	bool software_trigger;
+    /** Array to store callback functions */
+    adc_callback_t callback[ADC_CALLBACK_N];
+    /** Pointer to buffer used for ADC results */
+    volatile uint16_t *job_buffer;
+    /** Remaining number of conversions in current job */
+    volatile uint16_t remaining_conversions;
+    /** Bit mask for callbacks registered */
+    uint8_t registered_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enabled_callback_mask;
+    /** Holds the status of the ongoing or last conversion job */
+    volatile enum status_code job_status;
+    /** If software triggering is needed */
+    bool software_trigger;
 #  endif
 #endif
 };
@@ -593,18 +593,19 @@ struct adc_module {
  * \retval false if the module has completed synchronization
  */
 static inline bool adc_is_syncing(
-	struct adc_module *const module_inst)
+    struct adc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
-		return true;
-	}
+    if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 #endif
 
@@ -622,23 +623,24 @@ static inline bool adc_is_syncing(
  * \param[in] gain_factor  Gain factor value to set
  */
 static inline void adc_set_gain(
-		struct adc_module *const module_inst,
-		const enum adc_gain_factor gain_factor)
+        struct adc_module *const module_inst,
+        const enum adc_gain_factor gain_factor)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set new gain factor */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
-			(gain_factor);
+    /* Set new gain factor */
+    adc_module->INPUTCTRL.reg =
+            (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
+            (gain_factor);
 }
 
 /**
@@ -662,43 +664,46 @@ static inline void adc_set_gain(
  *                                 an invalid value
  */
 static inline enum status_code adc_set_pin_scan_mode(
-		struct adc_module *const module_inst,
-		uint8_t inputs_to_scan,
-		const uint8_t start_offset)
+        struct adc_module *const module_inst,
+        uint8_t inputs_to_scan,
+        const uint8_t start_offset)
 
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Adc *const adc_module = module_inst->hw;
-
-	if (inputs_to_scan > 0) {
-		/*
-		* Number of input sources included is the value written to INPUTSCAN
-		* plus 1.
-		*/
-		inputs_to_scan--;
-	}
-
-	if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
-			start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
-		/* Invalid number of input pins */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set pin scan mode */
-	adc_module->INPUTCTRL.reg =
-			(adc_module->INPUTCTRL.reg &
-			~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
-			(start_offset   << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
-			(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Adc *const adc_module = module_inst->hw;
+
+    if (inputs_to_scan > 0)
+    {
+        /*
+        * Number of input sources included is the value written to INPUTSCAN
+        * plus 1.
+        */
+        inputs_to_scan--;
+    }
+
+    if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
+            start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos))
+            {
+        /* Invalid number of input pins */
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set pin scan mode */
+    adc_module->INPUTCTRL.reg =
+            (adc_module->INPUTCTRL.reg &
+            ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
+            (start_offset   << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
+            (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
+
+    return STATUS_OK;
 }
 
 /**
@@ -710,10 +715,10 @@ static inline enum status_code adc_set_pin_scan_mode(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline void adc_disable_pin_scan_mode(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	/* Disable pin scan mode */
-	adc_set_pin_scan_mode(module_inst, 0, 0);
+    /* Disable pin scan mode */
+    adc_set_pin_scan_mode(module_inst, 0, 0);
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c
index 77d02388d805..4fa929e72bca 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc.c
@@ -99,21 +99,23 @@ const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos };
  * \return Index of the given ADC module instance.
  */
 uint8_t _adc_get_inst_index(
-		Adc *const hw)
+        Adc *const hw)
 {
-	/* List of available ADC modules. */
-	Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS;
-
-	/* Find index for ADC instance. */
-	for (uint32_t i = 0; i < ADC_INST_NUM; i++) {
-		if (hw == adc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given. */
-	Assert(false);
-	return 0;
+    /* List of available ADC modules. */
+    Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS;
+
+    /* Find index for ADC instance. */
+    for (uint32_t i = 0; i < ADC_INST_NUM; i++)
+    {
+        if (hw == adc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given. */
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -150,35 +152,35 @@ uint8_t _adc_get_inst_index(
  */
 void adc_get_config_defaults(struct adc_config *const config)
 {
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-	config->reference                     = ADC_REFERENCE_INTREF;
-	config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV2;
-	config->resolution                    = ADC_RESOLUTION_12BIT;
-	config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
-	config->window.window_upper_value     = 0;
-	config->window.window_lower_value     = 0;
+    Assert(config);
+    config->clock_source                  = GCLK_GENERATOR_0;
+    config->reference                     = ADC_REFERENCE_INTREF;
+    config->clock_prescaler               = ADC_CLOCK_PRESCALER_DIV2;
+    config->resolution                    = ADC_RESOLUTION_12BIT;
+    config->window.window_mode            = ADC_WINDOW_MODE_DISABLE;
+    config->window.window_upper_value     = 0;
+    config->window.window_lower_value     = 0;
 #if SAMR30
-	config->positive_input                = ADC_POSITIVE_INPUT_PIN6;
+    config->positive_input                = ADC_POSITIVE_INPUT_PIN6;
 #else
-	config->positive_input                = ADC_POSITIVE_INPUT_PIN1;
+    config->positive_input                = ADC_POSITIVE_INPUT_PIN1;
 #endif
-	config->negative_input                = ADC_NEGATIVE_INPUT_GND;
-	config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
-	config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
-	config->left_adjust                   = false;
-	config->differential_mode             = false;
-	config->freerunning                   = false;
-	config->event_action                  = ADC_EVENT_ACTION_DISABLED;
-	config->run_in_standby                = false;
-	config->on_demand                     = false;
-	config->sampling_time_compensation_enable  = false;
-	config->positive_input_sequence_mask_enable = 0;
-	config->reference_compensation_enable = false;
-	config->correction.correction_enable  = false;
-	config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
-	config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
-	config->sample_length                 = 0;
+    config->negative_input                = ADC_NEGATIVE_INPUT_GND;
+    config->accumulate_samples            = ADC_ACCUMULATE_DISABLE;
+    config->divide_result                 = ADC_DIVIDE_RESULT_DISABLE;
+    config->left_adjust                   = false;
+    config->differential_mode             = false;
+    config->freerunning                   = false;
+    config->event_action                  = ADC_EVENT_ACTION_DISABLED;
+    config->run_in_standby                = false;
+    config->on_demand                     = false;
+    config->sampling_time_compensation_enable  = false;
+    config->positive_input_sequence_mask_enable = 0;
+    config->reference_compensation_enable = false;
+    config->correction.correction_enable  = false;
+    config->correction.gain_correction    = ADC_GAINCORR_RESETVALUE;
+    config->correction.offset_correction  = ADC_OFFSETCORR_RESETVALUE;
+    config->sample_length                 = 0;
 }
 
 /**
@@ -192,41 +194,45 @@ void adc_get_config_defaults(struct adc_config *const config)
  * \param[in] window_upper_value  Upper window monitor threshold value
   */
 void adc_set_window_mode(
-		struct adc_module *const module_inst,
-		const enum adc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value)
+        struct adc_module *const module_inst,
+        const enum adc_window_mode window_mode,
+        const int16_t window_lower_value,
+        const int16_t window_upper_value)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set window mode */
-	adc_module->CTRLC.reg = window_mode;
+    /* Set window mode */
+    adc_module->CTRLC.reg = window_mode;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set lower window monitor threshold value */
-	adc_module->WINLT.reg = window_lower_value;
+    /* Set lower window monitor threshold value */
+    adc_module->WINLT.reg = window_lower_value;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set upper window monitor threshold value */
-	adc_module->WINUT.reg = window_upper_value;
+    /* Set upper window monitor threshold value */
+    adc_module->WINUT.reg = window_upper_value;
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -243,206 +249,208 @@ static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin)
 {
 #define PIN_INVALID_ADC_AIN    0xFFFFUL
 
-	/* Pinmapping table for AINxx -> GPIO pin number */
+    /* Pinmapping table for AINxx -> GPIO pin number */
 #if (SAML21) || (SAML22) || (SAMR30)
-	const uint32_t pinmapping[] = {
+    const uint32_t pinmapping[] = {
 #if (SAML21E) || (SAMR30E)
 #if !(SAMR30)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
 #endif
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAML21G) || (SAMR30G)
 #if !(SAMR30)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
 #endif
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAML21J)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
-			PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+            PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+            PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
+            PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAML22G)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAML22J)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+            PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #elif (SAML22N)
-			PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
-			PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
-			PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
-			PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
-			PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
-			PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
-			PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
-			PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
-			PIN_PC00B_ADC_AIN16, PIN_PC01B_ADC_AIN17,
-			PIN_PC02B_ADC_AIN18, PIN_PC03B_ADC_AIN19,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
-			PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_PA02B_ADC_AIN0,  PIN_PA03B_ADC_AIN1,
+            PIN_PB08B_ADC_AIN2,  PIN_PB09B_ADC_AIN3,
+            PIN_PA04B_ADC_AIN4,  PIN_PA05B_ADC_AIN5,
+            PIN_PA06B_ADC_AIN6,  PIN_PA07B_ADC_AIN7,
+            PIN_PB00B_ADC_AIN8,  PIN_PB01B_ADC_AIN9,
+            PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
+            PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
+            PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
+            PIN_PC00B_ADC_AIN16, PIN_PC01B_ADC_AIN17,
+            PIN_PC02B_ADC_AIN18, PIN_PC03B_ADC_AIN19,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
+            PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
 #   else
 #       error ADC pin mappings are not defined for this device.
 #   endif
-	};
+    };
 #elif (SAMC20)
-	const uint32_t pinmapping[] = {
+    const uint32_t pinmapping[] = {
 #   if (SAMC20E)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   elif (SAMC20G)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   elif (SAMC20J)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   else
 #       error ADC pin mappings are not defined for this device.
 #   endif
-	};
+    };
 #elif (SAMC21)
-	const uint32_t *pinmapping = NULL;;
-	const uint32_t pinmapping0[] = {
+    const uint32_t *pinmapping = NULL;;
+    const uint32_t pinmapping0[] = {
 #   if (SAMC21E)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   elif (SAMC21G)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   elif (SAMC21J)
-			PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
-			PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
-			PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
-			PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
-			PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
-			PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
+            PIN_PA02B_ADC0_AIN0,  PIN_PA03B_ADC0_AIN1,
+            PIN_PB08B_ADC0_AIN2,  PIN_PB09B_ADC0_AIN3,
+            PIN_PA04B_ADC0_AIN4,  PIN_PA05B_ADC0_AIN5,
+            PIN_PA06B_ADC0_AIN6,  PIN_PA07B_ADC0_AIN7,
+            PIN_PA08B_ADC0_AIN8,  PIN_PA09B_ADC0_AIN9,
+            PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
 #   else
 #       error ADC pin mappings are not defined for this device.
 #   endif
-		};
-	const uint32_t pinmapping1[] = {
+        };
+    const uint32_t pinmapping1[] = {
 #   if (SAMC21E)
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
 #   elif (SAMC21G)
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
-		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
-		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+        PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_INVALID_ADC_AIN,  PIN_INVALID_ADC_AIN,
+        PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
 #   elif (SAMC21J)
-		PIN_PB00B_ADC1_AIN0,  PIN_PB01B_ADC1_AIN1,
-		PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
-		PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
-		PIN_PB04B_ADC1_AIN6,  PIN_PB05B_ADC1_AIN7,
-		PIN_PB06B_ADC1_AIN8,  PIN_PB07B_ADC1_AIN9,
-		PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
+        PIN_PB00B_ADC1_AIN0,  PIN_PB01B_ADC1_AIN1,
+        PIN_PB02B_ADC1_AIN2,  PIN_PB03B_ADC1_AIN3,
+        PIN_PB08B_ADC1_AIN4,  PIN_PB09B_ADC1_AIN5,
+        PIN_PB04B_ADC1_AIN6,  PIN_PB05B_ADC1_AIN7,
+        PIN_PB06B_ADC1_AIN8,  PIN_PB07B_ADC1_AIN9,
+        PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
 #   else
 #       error ADC pin mappings are not defined for this device.
 #   endif
-	};
-
-	switch(index) {
-	case 0:
-		pinmapping = pinmapping0;
-		break;
-	case 1:
-		pinmapping = pinmapping1;
-		break;
-	default:
-		break;
-	}
-	Assert(pinmapping);
+    };
+
+    switch(index)
+    {
+    case 0:
+        pinmapping = pinmapping0;
+        break;
+    case 1:
+        pinmapping = pinmapping1;
+        break;
+    default:
+        break;
+    }
+    Assert(pinmapping);
 #endif
 
-	uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
+    uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
 
-	if (pin <= _adc_extchannel_msb[index]) {
-		pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
+    if (pin <= _adc_extchannel_msb[index])
+    {
+        pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
 
-		Assert(pin_map_result != PIN_INVALID_ADC_AIN);
+        Assert(pin_map_result != PIN_INVALID_ADC_AIN);
 
-		struct system_pinmux_config config;
-		system_pinmux_get_config_defaults(&config);
+        struct system_pinmux_config config;
+        system_pinmux_get_config_defaults(&config);
 
-		/* Analog functions are all on MUX setting B */
-		config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-		config.mux_position = 1;
+        /* Analog functions are all on MUX setting B */
+        config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+        config.mux_position = 1;
 
-		system_pinmux_pin_set_config(pin_map_result, &config);
-	}
+        system_pinmux_pin_set_config(pin_map_result, &config);
+    }
 }
 
 /**
@@ -459,277 +467,303 @@ static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin)
  * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
  */
 static enum status_code _adc_set_config(
-		uint8_t index,
-		struct adc_module *const module_inst,
-		struct adc_config *const config)
+        uint8_t index,
+        struct adc_module *const module_inst,
+        struct adc_config *const config)
 {
-	uint8_t adjres = 0;
-	uint32_t resolution = ADC_RESOLUTION_16BIT;
-	enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
-
-	/* Get the hardware module pointer */
-	Adc *const adc_module = module_inst->hw;
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf);
-	system_gclk_chan_enable(_adc_gclk_ids[index]);
-
-	/* Setup pinmuxing for analog inputs */
-	_adc_configure_ain_pin(index, config->positive_input);
-	_adc_configure_ain_pin(index, config->negative_input);
-
-	/* Set pinmux for positive input sequence*/
-	for(uint8_t i=0;i <= _adc_extchannel_msb[index];i++){
-		if(config->positive_input_sequence_mask_enable & (1 << i)){
-			_adc_configure_ain_pin(index, i);
-		}
-	}
-
-	/* Configure run in standby and on demand */
-	adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos)
-						    | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ;
-
-	/* Configure reference */
-	adc_module->REFCTRL.reg =
-			(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos)
-			| (config->reference);
-
-	/* Set adjusting result and number of samples */
-	switch (config->resolution) {
-
-	case ADC_RESOLUTION_CUSTOM:
-		adjres = config->divide_result;
-		accumulate = config->accumulate_samples;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_13BIT:
-		/* Increase resolution by 1 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_4;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_14BIT:
-		/* Increase resolution by 2 bit */
-		adjres = ADC_DIVIDE_RESULT_4;
-		accumulate = ADC_ACCUMULATE_SAMPLES_16;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-	case ADC_RESOLUTION_15BIT:
-		/* Increase resolution by 3 bit */
-		adjres = ADC_DIVIDE_RESULT_2;
-		accumulate = ADC_ACCUMULATE_SAMPLES_64;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-
-	case ADC_RESOLUTION_16BIT:
-		/* Increase resolution by 4 bit */
-		adjres = ADC_DIVIDE_RESULT_DISABLE;
-		accumulate = ADC_ACCUMULATE_SAMPLES_256;
-		/* 16-bit result register */
-		resolution = ADC_RESOLUTION_16BIT;
-		break;
-	case ADC_RESOLUTION_8BIT:
-		/* 8-bit result register */
-		resolution = ADC_RESOLUTION_8BIT;
-		break;
-	case ADC_RESOLUTION_10BIT:
-		/* 10-bit result register */
-		resolution = ADC_RESOLUTION_10BIT;
-		break;
-	case ADC_RESOLUTION_12BIT:
-		/* 12-bit result register */
-		resolution = ADC_RESOLUTION_12BIT;
-		break;
-
-	default:
-		/* Unknown. Abort. */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Check validity of sample length value */
-	if (config->sample_length > 63) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		/* Configure sample length */
-		adc_module->SAMPCTRL.reg =
-				(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos)
-				| (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos);
-	}
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure CTRLB */
-	adc_module->CTRLB.reg =
-			config->clock_prescaler;
-	adc_module->CTRLC.reg =
-			resolution |
-			(config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) |
-			(config->freerunning << ADC_CTRLC_FREERUN_Pos) |
-			(config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) |
-			(config->differential_mode << ADC_CTRLC_DIFFMODE_Pos);
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Check validity of window thresholds */
-	if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
-		switch (resolution) {
-		case ADC_RESOLUTION_8BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 127 ||
-					config->window.window_lower_value < -128 ||
-					config->window.window_upper_value > 127 ||
-					config->window.window_upper_value < -128)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 255 ||
-					config->window.window_upper_value > 255){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_10BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 511 ||
-					config->window.window_lower_value < -512 ||
-					config->window.window_upper_value > 511 ||
-					config->window.window_upper_value < -512)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 1023 ||
-					config->window.window_upper_value > 1023){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_12BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 2047 ||
-					config->window.window_lower_value < -2048 ||
-					config->window.window_upper_value > 2047 ||
-					config->window.window_upper_value < -2048)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 4095 ||
-					config->window.window_upper_value > 4095){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case ADC_RESOLUTION_16BIT:
-			if (config->differential_mode &&
-					(config->window.window_lower_value > 32767 ||
-					config->window.window_lower_value < -32768 ||
-					config->window.window_upper_value > 32767 ||
-					config->window.window_upper_value < -32768)) {
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			} else if (config->window.window_lower_value > 65535 ||
-					config->window.window_upper_value > 65535){
-				/* Invalid value */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		}
-	}
-
-	/* Configure window mode */
-	adc_module->CTRLC.reg |= config->window.window_mode;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINLT.reg =
-			config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	adc_module->WINUT.reg = config->window.window_upper_value <<
-			ADC_WINUT_WINUT_Pos;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure pin scan mode and positive and negative input pins */
-	adc_module->INPUTCTRL.reg =
-			config->negative_input |
-			config->positive_input;
-
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure events */
-	adc_module->EVCTRL.reg = config->event_action;
-
-	/* Disable all interrupts */
-	adc_module->INTENCLR.reg =
-			(1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos)
-			| (1 << ADC_INTENCLR_RESRDY_Pos);
-
-	if (config->correction.correction_enable){
-		/* Make sure gain_correction value is valid */
-		if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set gain correction value */
-			adc_module->GAINCORR.reg = config->correction.gain_correction <<
-					ADC_GAINCORR_GAINCORR_Pos;
-		}
-
-		while (adc_is_syncing(module_inst)) {
-			/* Wait for synchronization */
-		}
-
-		/* Make sure offset correction value is valid */
-		if (config->correction.offset_correction > 2047 ||
-				config->correction.offset_correction < -2048) {
-			return STATUS_ERR_INVALID_ARG;
-		} else {
-			/* Set offset correction value */
-			adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
-					ADC_OFFSETCORR_OFFSETCORR_Pos;
-		}
-
-		while (adc_is_syncing(module_inst)) {
-			/* Wait for synchronization */
-		}
-	}
-
-	/* Load in the fixed device ADC calibration constants */
-	adc_module->CALIB.reg =
-			ADC_CALIB_BIASREFBUF(
-				(*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index])
-			) |
-			ADC_CALIB_BIASCOMP(
-				(*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index])
-			);
-
-	return STATUS_OK;
+    uint8_t adjres = 0;
+    uint32_t resolution = ADC_RESOLUTION_16BIT;
+    enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
+
+    /* Get the hardware module pointer */
+    Adc *const adc_module = module_inst->hw;
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf);
+    system_gclk_chan_enable(_adc_gclk_ids[index]);
+
+    /* Setup pinmuxing for analog inputs */
+    _adc_configure_ain_pin(index, config->positive_input);
+    _adc_configure_ain_pin(index, config->negative_input);
+
+    /* Set pinmux for positive input sequence*/
+    for(uint8_t i=0;i <= _adc_extchannel_msb[index];i++)
+    {
+        if(config->positive_input_sequence_mask_enable & (1 << i))
+        {
+            _adc_configure_ain_pin(index, i);
+        }
+    }
+
+    /* Configure run in standby and on demand */
+    adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos)
+                            | (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ;
+
+    /* Configure reference */
+    adc_module->REFCTRL.reg =
+            (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos)
+            | (config->reference);
+
+    /* Set adjusting result and number of samples */
+    switch (config->resolution)
+    {
+
+    case ADC_RESOLUTION_CUSTOM:
+        adjres = config->divide_result;
+        accumulate = config->accumulate_samples;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_13BIT:
+        /* Increase resolution by 1 bit */
+        adjres = ADC_DIVIDE_RESULT_2;
+        accumulate = ADC_ACCUMULATE_SAMPLES_4;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_14BIT:
+        /* Increase resolution by 2 bit */
+        adjres = ADC_DIVIDE_RESULT_4;
+        accumulate = ADC_ACCUMULATE_SAMPLES_16;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+    case ADC_RESOLUTION_15BIT:
+        /* Increase resolution by 3 bit */
+        adjres = ADC_DIVIDE_RESULT_2;
+        accumulate = ADC_ACCUMULATE_SAMPLES_64;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+
+    case ADC_RESOLUTION_16BIT:
+        /* Increase resolution by 4 bit */
+        adjres = ADC_DIVIDE_RESULT_DISABLE;
+        accumulate = ADC_ACCUMULATE_SAMPLES_256;
+        /* 16-bit result register */
+        resolution = ADC_RESOLUTION_16BIT;
+        break;
+    case ADC_RESOLUTION_8BIT:
+        /* 8-bit result register */
+        resolution = ADC_RESOLUTION_8BIT;
+        break;
+    case ADC_RESOLUTION_10BIT:
+        /* 10-bit result register */
+        resolution = ADC_RESOLUTION_10BIT;
+        break;
+    case ADC_RESOLUTION_12BIT:
+        /* 12-bit result register */
+        resolution = ADC_RESOLUTION_12BIT;
+        break;
+
+    default:
+        /* Unknown. Abort. */
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Check validity of sample length value */
+    if (config->sample_length > 63)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        /* Configure sample length */
+        adc_module->SAMPCTRL.reg =
+                (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos)
+                | (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos);
+    }
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure CTRLB */
+    adc_module->CTRLB.reg =
+            config->clock_prescaler;
+    adc_module->CTRLC.reg =
+            resolution |
+            (config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) |
+            (config->freerunning << ADC_CTRLC_FREERUN_Pos) |
+            (config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) |
+            (config->differential_mode << ADC_CTRLC_DIFFMODE_Pos);
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Check validity of window thresholds */
+    if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE)
+    {
+        switch (resolution)
+        {
+        case ADC_RESOLUTION_8BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 127 ||
+                    config->window.window_lower_value < -128 ||
+                    config->window.window_upper_value > 127 ||
+                    config->window.window_upper_value < -128))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 255 ||
+                    config->window.window_upper_value > 255)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_10BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 511 ||
+                    config->window.window_lower_value < -512 ||
+                    config->window.window_upper_value > 511 ||
+                    config->window.window_upper_value < -512))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 1023 ||
+                    config->window.window_upper_value > 1023)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_12BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 2047 ||
+                    config->window.window_lower_value < -2048 ||
+                    config->window.window_upper_value > 2047 ||
+                    config->window.window_upper_value < -2048))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 4095 ||
+                    config->window.window_upper_value > 4095)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case ADC_RESOLUTION_16BIT:
+            if (config->differential_mode &&
+                    (config->window.window_lower_value > 32767 ||
+                    config->window.window_lower_value < -32768 ||
+                    config->window.window_upper_value > 32767 ||
+                    config->window.window_upper_value < -32768))
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            } else if (config->window.window_lower_value > 65535 ||
+                    config->window.window_upper_value > 65535)
+                    {
+                /* Invalid value */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        }
+    }
+
+    /* Configure window mode */
+    adc_module->CTRLC.reg |= config->window.window_mode;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    adc_module->WINLT.reg =
+            config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    adc_module->WINUT.reg = config->window.window_upper_value <<
+            ADC_WINUT_WINUT_Pos;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure pin scan mode and positive and negative input pins */
+    adc_module->INPUTCTRL.reg =
+            config->negative_input |
+            config->positive_input;
+
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure events */
+    adc_module->EVCTRL.reg = config->event_action;
+
+    /* Disable all interrupts */
+    adc_module->INTENCLR.reg =
+            (1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos)
+            | (1 << ADC_INTENCLR_RESRDY_Pos);
+
+    if (config->correction.correction_enable)
+    {
+        /* Make sure gain_correction value is valid */
+        if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        } else {
+            /* Set gain correction value */
+            adc_module->GAINCORR.reg = config->correction.gain_correction <<
+                    ADC_GAINCORR_GAINCORR_Pos;
+        }
+
+        while (adc_is_syncing(module_inst))
+        {
+            /* Wait for synchronization */
+        }
+
+        /* Make sure offset correction value is valid */
+        if (config->correction.offset_correction > 2047 ||
+                config->correction.offset_correction < -2048)
+                {
+            return STATUS_ERR_INVALID_ARG;
+        } else {
+            /* Set offset correction value */
+            adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+                    ADC_OFFSETCORR_OFFSETCORR_Pos;
+        }
+
+        while (adc_is_syncing(module_inst))
+        {
+            /* Wait for synchronization */
+        }
+    }
+
+    /* Load in the fixed device ADC calibration constants */
+    adc_module->CALIB.reg =
+            ADC_CALIB_BIASREFBUF(
+                (*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index])
+            ) |
+            ADC_CALIB_BIASCOMP(
+                (*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index])
+            );
+
+    return STATUS_OK;
 }
 
 /**
@@ -749,72 +783,78 @@ static enum status_code _adc_set_config(
  * \retval STATUS_ERR_DENIED        The module is enabled
  */
 enum status_code adc_init(
-		struct adc_module *const module_inst,
-		Adc *hw,
-		struct adc_config *config)
+        struct adc_module *const module_inst,
+        Adc *hw,
+        struct adc_config *config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
 
-	/* Temporary variable to hold ADC instance number */
-	uint8_t instance = _adc_get_inst_index(hw);
+    /* Temporary variable to hold ADC instance number */
+    uint8_t instance = _adc_get_inst_index(hw);
 
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
 #if (SAML22)
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_ADC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_ADC);
 #elif (SAML21) || (SAMR30)
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_ADC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_ADC);
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]);
 #endif
 
-	if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
+    if (hw->CTRLA.reg & ADC_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
 
-	while (adc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (adc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
+    if (hw->CTRLA.reg & ADC_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
 
-	/* Store the selected reference for later use */
-	module_inst->reference = config->reference;
+    /* Store the selected reference for later use */
+    module_inst->reference = config->reference;
 
-	/* Make sure the voltage reference is enabled if requested by the config */
-	if (module_inst->reference == ADC_REFERENCE_INTREF) {
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
-	}
+    /* Make sure the voltage reference is enabled if requested by the config */
+    if (module_inst->reference == ADC_REFERENCE_INTREF)
+    {
+        system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+    }
 
 #if ADC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	};
-
-	module_inst->registered_callback_mask = 0;
-	module_inst->enabled_callback_mask = 0;
-	module_inst->remaining_conversions = 0;
-	module_inst->job_status = STATUS_OK;
-
-	_adc_instances[instance] = module_inst;
-
-	if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
-			!config->freerunning) {
-		module_inst->software_trigger = true;
-	} else {
-		module_inst->software_trigger = false;
-	}
+    for (uint8_t i = 0; i < ADC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    };
+
+    module_inst->registered_callback_mask = 0;
+    module_inst->enabled_callback_mask = 0;
+    module_inst->remaining_conversions = 0;
+    module_inst->job_status = STATUS_OK;
+
+    _adc_instances[instance] = module_inst;
+
+    if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
+            !config->freerunning)
+            {
+        module_inst->software_trigger = true;
+    } else {
+        module_inst->software_trigger = false;
+    }
 #endif
 
-	/* Write configuration to module */
-	return _adc_set_config(instance, module_inst, config);
+    /* Write configuration to module */
+    return _adc_set_config(instance, module_inst, config);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c
index 555956b06bdb..c7f32b7b32a9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_callback.c
@@ -49,68 +49,77 @@ struct adc_module *_adc_instances[ADC_INST_NUM];
 
 static void _adc_interrupt_handler(const uint8_t instance)
 {
-	struct adc_module *module = _adc_instances[instance];
+    struct adc_module *module = _adc_instances[instance];
 
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->INTFLAG.reg;
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->INTFLAG.reg;
 
-	if (flags & ADC_INTFLAG_RESRDY) {
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER))) {
-			/* clear interrupt flag */
-			module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
+    if (flags & ADC_INTFLAG_RESRDY)
+    {
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)))
+                {
+            /* clear interrupt flag */
+            module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY;
 
-			/* store ADC result in job buffer */
-			*(module->job_buffer++) = module->hw->RESULT.reg;
+            /* store ADC result in job buffer */
+            *(module->job_buffer++) = module->hw->RESULT.reg;
 
-			if (--module->remaining_conversions > 0) {
-				if (module->software_trigger == true
-					&& (!(module->hw->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY))) {
-					adc_start_conversion(module);
-				}
-			} else {
-				if (module->job_status == STATUS_BUSY) {
-					/* job is complete. update status,disable interrupt
-					 *and call callback */
-					module->job_status = STATUS_OK;
-					adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
-					(module->callback[ADC_CALLBACK_READ_BUFFER])(module);
-				}
-			}
-		}
-	}
+            if (--module->remaining_conversions > 0)
+            {
+                if (module->software_trigger == true
+                    && (!(module->hw->SEQSTATUS.reg & ADC_SEQSTATUS_SEQBUSY)))
+                    {
+                    adc_start_conversion(module);
+                }
+            } else {
+                if (module->job_status == STATUS_BUSY)
+                {
+                    /* job is complete. update status,disable interrupt
+                     *and call callback */
+                    module->job_status = STATUS_OK;
+                    adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY);
+                    (module->callback[ADC_CALLBACK_READ_BUFFER])(module);
+                }
+            }
+        }
+    }
 
-	if (flags & ADC_INTFLAG_WINMON) {
-		module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) {
-			(module->callback[ADC_CALLBACK_WINDOW])(module);
-		}
+    if (flags & ADC_INTFLAG_WINMON)
+    {
+        module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON;
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW)))
+                {
+            (module->callback[ADC_CALLBACK_WINDOW])(module);
+        }
 
-	}
+    }
 
-	if (flags & ADC_INTFLAG_OVERRUN) {
-		module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
-		if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
-				(module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) {
-			(module->callback[ADC_CALLBACK_ERROR])(module);
-		}
-	}
+    if (flags & ADC_INTFLAG_OVERRUN)
+    {
+        module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN;
+        if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) &&
+                (module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR)))
+                {
+            (module->callback[ADC_CALLBACK_ERROR])(module);
+        }
+    }
 }
 
 /** Interrupt handler for the ADC module. */
 #if (ADC_INST_NUM > 1) || (SAMC20)
 #   define _ADC_INTERRUPT_HANDLER(n, m) \
-		void ADC##n##_Handler(void) \
-		{ \
-			_adc_interrupt_handler(n); \
-		}
+        void ADC##n##_Handler(void) \
+        { \
+            _adc_interrupt_handler(n); \
+        }
 
-	MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_HANDLER, 0)
+    MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_HANDLER, 0)
 #else
 void ADC_Handler(void)
 {
-	_adc_interrupt_handler(0);
+    _adc_interrupt_handler(0);
 }
 #endif
 
@@ -128,19 +137,19 @@ void ADC_Handler(void)
  *
  */
 void adc_register_callback(
-		struct adc_module *const module,
-		adc_callback_t callback_func,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        adc_callback_t callback_func,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->registered_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->registered_callback_mask |= (1 << callback_type);
 }
 
 /**
@@ -153,17 +162,17 @@ void adc_register_callback(
  *
  */
 void adc_unregister_callback(
-		struct adc_module *const module,
-		enum adc_callback callback_type)
+        struct adc_module *const module,
+        enum adc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->registered_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->registered_callback_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -185,30 +194,32 @@ void adc_unregister_callback(
  * \retval STATUS_BUSY      The ADC is already busy with another job
  */
 enum status_code adc_read_buffer_job(
-		struct adc_module *const module_inst,
-		uint16_t *buffer,
-		uint16_t samples)
+        struct adc_module *const module_inst,
+        uint16_t *buffer,
+        uint16_t samples)
 {
-	Assert(module_inst);
-	Assert(samples);
-	Assert(buffer);
+    Assert(module_inst);
+    Assert(samples);
+    Assert(buffer);
 
-	if(module_inst->remaining_conversions != 0 ||
-			module_inst->job_status == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
+    if(module_inst->remaining_conversions != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	module_inst->job_status = STATUS_BUSY;
-	module_inst->remaining_conversions = samples;
-	module_inst->job_buffer = buffer;
+    module_inst->job_status = STATUS_BUSY;
+    module_inst->remaining_conversions = samples;
+    module_inst->job_buffer = buffer;
 
-	adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+    adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
 
-	if(module_inst->software_trigger == true) {
-		adc_start_conversion(module_inst);
-	}
+    if(module_inst->software_trigger == true)
+    {
+        adc_start_conversion(module_inst);
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -222,17 +233,18 @@ enum status_code adc_read_buffer_job(
  * \return Status of the job.
  */
 enum status_code adc_get_job_status(
-		struct adc_module *module_inst,
-		enum adc_job_type type)
+        struct adc_module *module_inst,
+        enum adc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	if (type == ADC_JOB_READ_BUFFER ) {
-		return module_inst->job_status;
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (type == ADC_JOB_READ_BUFFER )
+    {
+        return module_inst->job_status;
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -244,18 +256,19 @@ enum status_code adc_get_job_status(
  * \param [in]  type        Type of job to abort
  */
 void adc_abort_job(
-		struct adc_module *module_inst,
-		enum adc_job_type type)
+        struct adc_module *module_inst,
+        enum adc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	if (type == ADC_JOB_READ_BUFFER) {
-		/* Disable interrupt */
-		adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
-		/* Mark job as aborted */
-		module_inst->job_status = STATUS_ABORTED;
-		module_inst->remaining_conversions = 0;
-	}
+    if (type == ADC_JOB_READ_BUFFER)
+    {
+        /* Disable interrupt */
+        adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
+        /* Mark job as aborted */
+        module_inst->job_status = STATUS_ABORTED;
+        module_inst->remaining_conversions = 0;
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h
index 0274cd7c928f..53b39a028af1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/adc/adc_sam_l_c/adc_feature.h
@@ -82,15 +82,15 @@ typedef void (*adc_callback_t)(struct adc_module *const module);
  *
  */
 enum adc_callback {
-	/** Callback for buffer received */
-	ADC_CALLBACK_READ_BUFFER,
-	/** Callback when window is hit */
-	ADC_CALLBACK_WINDOW,
-	/** Callback for error */
-	ADC_CALLBACK_ERROR,
+    /** Callback for buffer received */
+    ADC_CALLBACK_READ_BUFFER,
+    /** Callback when window is hit */
+    ADC_CALLBACK_WINDOW,
+    /** Callback for error */
+    ADC_CALLBACK_ERROR,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	ADC_CALLBACK_N,
+    /** Number of available callbacks */
+    ADC_CALLBACK_N,
 #  endif
 };
 
@@ -103,24 +103,24 @@ enum adc_callback {
  *
  */
 enum adc_reference {
-	/** Internal Bandgap Reference */
-	ADC_REFERENCE_INTREF  = ADC_REFCTRL_REFSEL_INTREF,
-	/** 1/1.48V<SUB>CC</SUB> reference */
-	ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
-	/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
-	ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
-	/** External reference A */
-	ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
+    /** Internal Bandgap Reference */
+    ADC_REFERENCE_INTREF  = ADC_REFCTRL_REFSEL_INTREF,
+    /** 1/1.48V<SUB>CC</SUB> reference */
+    ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
+    /** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
+    ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
+    /** External reference A */
+    ADC_REFERENCE_AREFA   = ADC_REFCTRL_REFSEL_AREFA,
 #if (SAML21) || (SAMR30)
-	/** External reference B */
-	ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
+    /** External reference B */
+    ADC_REFERENCE_AREFB   = ADC_REFCTRL_REFSEL_AREFB,
 #endif
 #if (SAMC20) || (SAMC21)
-	/** DAC */
-	ADC_REFERENCE_DAC     = ADC_REFCTRL_REFSEL_DAC,
+    /** DAC */
+    ADC_REFERENCE_DAC     = ADC_REFCTRL_REFSEL_DAC,
 #endif
-	/** VDDANA */
-	ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2,
+    /** VDDANA */
+    ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2,
 };
 
 /**
@@ -130,22 +130,22 @@ enum adc_reference {
  *
  */
 enum adc_clock_prescaler {
-	/** ADC clock division factor 2 */
-	ADC_CLOCK_PRESCALER_DIV2   = ADC_CTRLB_PRESCALER_DIV2,
-	/** ADC clock division factor 4 */
-	ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
-	/** ADC clock division factor 8 */
-	ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
-	/** ADC clock division factor 16 */
-	ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
-	/** ADC clock division factor 32 */
-	ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
-	/** ADC clock division factor 64 */
-	ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
-	/** ADC clock division factor 128 */
-	ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
-	/** ADC clock division factor 256 */
-	ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
+    /** ADC clock division factor 2 */
+    ADC_CLOCK_PRESCALER_DIV2   = ADC_CTRLB_PRESCALER_DIV2,
+    /** ADC clock division factor 4 */
+    ADC_CLOCK_PRESCALER_DIV4   = ADC_CTRLB_PRESCALER_DIV4,
+    /** ADC clock division factor 8 */
+    ADC_CLOCK_PRESCALER_DIV8   = ADC_CTRLB_PRESCALER_DIV8,
+    /** ADC clock division factor 16 */
+    ADC_CLOCK_PRESCALER_DIV16  = ADC_CTRLB_PRESCALER_DIV16,
+    /** ADC clock division factor 32 */
+    ADC_CLOCK_PRESCALER_DIV32  = ADC_CTRLB_PRESCALER_DIV32,
+    /** ADC clock division factor 64 */
+    ADC_CLOCK_PRESCALER_DIV64  = ADC_CTRLB_PRESCALER_DIV64,
+    /** ADC clock division factor 128 */
+    ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
+    /** ADC clock division factor 256 */
+    ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
 };
 
 /**
@@ -155,27 +155,27 @@ enum adc_clock_prescaler {
  *
  */
 enum adc_resolution {
-	/** ADC 12-bit resolution */
-	ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT,
-	/** ADC 16-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT,
-	/** ADC 10-bit resolution */
-	ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT,
-	/** ADC 8-bit resolution */
-	ADC_RESOLUTION_8BIT  = ADC_CTRLC_RESSEL_8BIT,
-	/** ADC 13-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_13BIT,
-	/** ADC 14-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_14BIT,
-	/** ADC 15-bit resolution using oversampling and decimation */
-	ADC_RESOLUTION_15BIT,
-	/** ADC 16-bit result register for use with averaging. When using this mode
-	  * the ADC result register will be set to 16-bit wide, and the number of
-	  * samples to accumulate and the division factor is configured by the
-	  * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
-	  * members in the configuration struct.
-	  */
-	ADC_RESOLUTION_CUSTOM,
+    /** ADC 12-bit resolution */
+    ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT,
+    /** ADC 16-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT,
+    /** ADC 10-bit resolution */
+    ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT,
+    /** ADC 8-bit resolution */
+    ADC_RESOLUTION_8BIT  = ADC_CTRLC_RESSEL_8BIT,
+    /** ADC 13-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_13BIT,
+    /** ADC 14-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_14BIT,
+    /** ADC 15-bit resolution using oversampling and decimation */
+    ADC_RESOLUTION_15BIT,
+    /** ADC 16-bit result register for use with averaging. When using this mode
+      * the ADC result register will be set to 16-bit wide, and the number of
+      * samples to accumulate and the division factor is configured by the
+      * \ref adc_config.accumulate_samples and \ref adc_config.divide_result
+      * members in the configuration struct.
+      */
+    ADC_RESOLUTION_CUSTOM,
 };
 
 /**
@@ -185,16 +185,16 @@ enum adc_resolution {
  *
  */
 enum adc_window_mode {
-	/** No window mode */
-	ADC_WINDOW_MODE_DISABLE          = ADC_CTRLC_WINMODE_DISABLE,
-	/** RESULT > WINLT */
-	ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_CTRLC_WINMODE_MODE1,
-	/** RESULT < WINUT */
-	ADC_WINDOW_MODE_BELOW_UPPER      = ADC_CTRLC_WINMODE_MODE2,
-	/** WINLT < RESULT < WINUT */
-	ADC_WINDOW_MODE_BETWEEN          = ADC_CTRLC_WINMODE_MODE3,
-	/** !(WINLT < RESULT < WINUT) */
-	ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4,
+    /** No window mode */
+    ADC_WINDOW_MODE_DISABLE          = ADC_CTRLC_WINMODE_DISABLE,
+    /** RESULT > WINLT */
+    ADC_WINDOW_MODE_ABOVE_LOWER      = ADC_CTRLC_WINMODE_MODE1,
+    /** RESULT < WINUT */
+    ADC_WINDOW_MODE_BELOW_UPPER      = ADC_CTRLC_WINMODE_MODE2,
+    /** WINLT < RESULT < WINUT */
+    ADC_WINDOW_MODE_BETWEEN          = ADC_CTRLC_WINMODE_MODE3,
+    /** !(WINLT < RESULT < WINUT) */
+    ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4,
 };
 
 /**
@@ -204,12 +204,12 @@ enum adc_window_mode {
  *
  */
 enum adc_event_action {
-	/** Event action disabled */
-	ADC_EVENT_ACTION_DISABLED         = 0,
-	/** Flush ADC and start conversion */
-	ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI,
-	/** Start conversion */
-	ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
+    /** Event action disabled */
+    ADC_EVENT_ACTION_DISABLED         = 0,
+    /** Flush ADC and start conversion */
+    ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI,
+    /** Start conversion */
+    ADC_EVENT_ACTION_START_CONV       = ADC_EVCTRL_STARTEI,
 };
 
 /**
@@ -219,84 +219,84 @@ enum adc_event_action {
  *
  */
 enum adc_positive_input {
-	/** ADC0 pin */
-	ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_AIN0,
-	/** ADC1 pin */
-	ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_AIN1,
-	/** ADC2 pin */
-	ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_AIN2,
-	/** ADC3 pin */
-	ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_AIN3,
-	/** ADC4 pin */
-	ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_AIN4,
-	/** ADC5 pin */
-	ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_AIN5,
-	/** ADC6 pin */
-	ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_AIN6,
-	/** ADC7 pin */
-	ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_AIN7,
-	/** ADC8 pin */
-	ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_AIN8,
-	/** ADC9 pin */
-	ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_AIN9,
-	/** ADC10 pin */
-	ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_AIN10,
-	/** ADC11 pin */
-	ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_AIN11,
+    /** ADC0 pin */
+    ADC_POSITIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXPOS_AIN0,
+    /** ADC1 pin */
+    ADC_POSITIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXPOS_AIN1,
+    /** ADC2 pin */
+    ADC_POSITIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXPOS_AIN2,
+    /** ADC3 pin */
+    ADC_POSITIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXPOS_AIN3,
+    /** ADC4 pin */
+    ADC_POSITIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXPOS_AIN4,
+    /** ADC5 pin */
+    ADC_POSITIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXPOS_AIN5,
+    /** ADC6 pin */
+    ADC_POSITIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXPOS_AIN6,
+    /** ADC7 pin */
+    ADC_POSITIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXPOS_AIN7,
+    /** ADC8 pin */
+    ADC_POSITIVE_INPUT_PIN8          = ADC_INPUTCTRL_MUXPOS_AIN8,
+    /** ADC9 pin */
+    ADC_POSITIVE_INPUT_PIN9          = ADC_INPUTCTRL_MUXPOS_AIN9,
+    /** ADC10 pin */
+    ADC_POSITIVE_INPUT_PIN10         = ADC_INPUTCTRL_MUXPOS_AIN10,
+    /** ADC11 pin */
+    ADC_POSITIVE_INPUT_PIN11         = ADC_INPUTCTRL_MUXPOS_AIN11,
 #if !(SAMC20) && !(SAMC21)
-	/** ADC12 pin */
-	ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_AIN12,
-	/** ADC13 pin */
-	ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_AIN13,
-	/** ADC14 pin */
-	ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_AIN14,
-	/** ADC15 pin */
-	ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_AIN15,
-	/** ADC16 pin */
-	ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_AIN16,
-	/** ADC17 pin */
-	ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_AIN17,
-	/** ADC18 pin */
-	ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_AIN18,
-	/** ADC19 pin */
-	ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_AIN19,
+    /** ADC12 pin */
+    ADC_POSITIVE_INPUT_PIN12         = ADC_INPUTCTRL_MUXPOS_AIN12,
+    /** ADC13 pin */
+    ADC_POSITIVE_INPUT_PIN13         = ADC_INPUTCTRL_MUXPOS_AIN13,
+    /** ADC14 pin */
+    ADC_POSITIVE_INPUT_PIN14         = ADC_INPUTCTRL_MUXPOS_AIN14,
+    /** ADC15 pin */
+    ADC_POSITIVE_INPUT_PIN15         = ADC_INPUTCTRL_MUXPOS_AIN15,
+    /** ADC16 pin */
+    ADC_POSITIVE_INPUT_PIN16         = ADC_INPUTCTRL_MUXPOS_AIN16,
+    /** ADC17 pin */
+    ADC_POSITIVE_INPUT_PIN17         = ADC_INPUTCTRL_MUXPOS_AIN17,
+    /** ADC18 pin */
+    ADC_POSITIVE_INPUT_PIN18         = ADC_INPUTCTRL_MUXPOS_AIN18,
+    /** ADC19 pin */
+    ADC_POSITIVE_INPUT_PIN19         = ADC_INPUTCTRL_MUXPOS_AIN19,
 #if !(SAML22 || SAMR30)
-	/** ADC20 pin. */
-	ADC_POSITIVE_INPUT_PIN20         = ADC_INPUTCTRL_MUXPOS_AIN20,
-	/** ADC21 pin */
-	ADC_POSITIVE_INPUT_PIN21         = ADC_INPUTCTRL_MUXPOS_AIN21,
-	/** ADC22 pin */
-	ADC_POSITIVE_INPUT_PIN22         = ADC_INPUTCTRL_MUXPOS_AIN22,
-	/** ADC23 pin */
-	ADC_POSITIVE_INPUT_PIN23         = ADC_INPUTCTRL_MUXPOS_AIN23,
+    /** ADC20 pin. */
+    ADC_POSITIVE_INPUT_PIN20         = ADC_INPUTCTRL_MUXPOS_AIN20,
+    /** ADC21 pin */
+    ADC_POSITIVE_INPUT_PIN21         = ADC_INPUTCTRL_MUXPOS_AIN21,
+    /** ADC22 pin */
+    ADC_POSITIVE_INPUT_PIN22         = ADC_INPUTCTRL_MUXPOS_AIN22,
+    /** ADC23 pin */
+    ADC_POSITIVE_INPUT_PIN23         = ADC_INPUTCTRL_MUXPOS_AIN23,
 #endif
-	/** Temperature reference. */
-	ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
+    /** Temperature reference. */
+    ADC_POSITIVE_INPUT_TEMP          = ADC_INPUTCTRL_MUXPOS_TEMP,
 #endif
-	/** Bandgap voltage */
-	ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
-	/** 1/4 scaled core supply */
-	ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
-	/** 1/4 scaled I/O supply */
-	ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
+    /** Bandgap voltage */
+    ADC_POSITIVE_INPUT_BANDGAP       = ADC_INPUTCTRL_MUXPOS_BANDGAP,
+    /** 1/4 scaled core supply */
+    ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
+    /** 1/4 scaled I/O supply */
+    ADC_POSITIVE_INPUT_SCALEDIOVCC   = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
 #if !(SAML22|| SAMR30)
-	/** DAC input */
-	ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
+    /** DAC input */
+    ADC_POSITIVE_INPUT_DAC           = ADC_INPUTCTRL_MUXPOS_DAC,
 #endif
 
 #if (SAML21)
-	/** SCALEDVBAT */
-	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
-	/** OPAMP01 */
-	ADC_POSITIVE_INPUT_OPAMP01       = ADC_INPUTCTRL_MUXPOS_OPAMP01,
-	/** OPAMP02 */
-	ADC_POSITIVE_INPUT_OPAMP2        = ADC_INPUTCTRL_MUXPOS_OPAMP2,
+    /** SCALEDVBAT */
+    ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+    /** OPAMP01 */
+    ADC_POSITIVE_INPUT_OPAMP01       = ADC_INPUTCTRL_MUXPOS_OPAMP01,
+    /** OPAMP02 */
+    ADC_POSITIVE_INPUT_OPAMP2        = ADC_INPUTCTRL_MUXPOS_OPAMP2,
 #endif
 #if (SAML22)
-	/** SCALEDVBAT */
-	ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
-	/** CTAT. */
-	ADC_POSITIVE_INPUT_CTAT          = ADC_INPUTCTRL_MUXPOS_CTAT,
+    /** SCALEDVBAT */
+    ADC_POSITIVE_INPUT_SCALEDVBAT    = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
+    /** CTAT. */
+    ADC_POSITIVE_INPUT_CTAT          = ADC_INPUTCTRL_MUXPOS_CTAT,
 #endif
 };
 
@@ -307,26 +307,26 @@ enum adc_positive_input {
  *
  */
 enum adc_negative_input {
-	/** ADC0 pin */
-	ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_AIN0,
-	/** ADC1 pin */
-	ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_AIN1,
-	/** ADC2 pin */
-	ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_AIN2,
-	/** ADC3 pin */
-	ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_AIN3,
-	/** ADC4 pin */
-	ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_AIN4,
-	/** ADC5 pin */
-	ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_AIN5,
+    /** ADC0 pin */
+    ADC_NEGATIVE_INPUT_PIN0          = ADC_INPUTCTRL_MUXNEG_AIN0,
+    /** ADC1 pin */
+    ADC_NEGATIVE_INPUT_PIN1          = ADC_INPUTCTRL_MUXNEG_AIN1,
+    /** ADC2 pin */
+    ADC_NEGATIVE_INPUT_PIN2          = ADC_INPUTCTRL_MUXNEG_AIN2,
+    /** ADC3 pin */
+    ADC_NEGATIVE_INPUT_PIN3          = ADC_INPUTCTRL_MUXNEG_AIN3,
+    /** ADC4 pin */
+    ADC_NEGATIVE_INPUT_PIN4          = ADC_INPUTCTRL_MUXNEG_AIN4,
+    /** ADC5 pin */
+    ADC_NEGATIVE_INPUT_PIN5          = ADC_INPUTCTRL_MUXNEG_AIN5,
 #if !(SAMC20) && !(SAMC21) && !(SAMR30)
-	/** ADC6 pin */
-	ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_AIN6,
-	/** ADC7 pin */
-	ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_AIN7,
+    /** ADC6 pin */
+    ADC_NEGATIVE_INPUT_PIN6          = ADC_INPUTCTRL_MUXNEG_AIN6,
+    /** ADC7 pin */
+    ADC_NEGATIVE_INPUT_PIN7          = ADC_INPUTCTRL_MUXNEG_AIN7,
 #endif
-	/** Internal ground */
-	ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG(0x18u),
+    /** Internal ground */
+    ADC_NEGATIVE_INPUT_GND           = ADC_INPUTCTRL_MUXNEG(0x18u),
 };
 
 /**
@@ -338,28 +338,28 @@ enum adc_negative_input {
  *
  */
 enum adc_accumulate_samples {
-	/** No averaging */
-	ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
-	/** Average 2 samples */
-	ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
-	/** Average 4 samples */
-	ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
-	/** Average 8 samples */
-	ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
-	/** Average 16 samples */
-	ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
-	/** Average 32 samples */
-	ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
-	/** Average 64 samples */
-	ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
-	/** Average 128 samples */
-	ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
-	/** Average 256 samples */
-	ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
-	/** Average 512 samples */
-	ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
-	/** Average 1024 samples */
-	ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
+    /** No averaging */
+    ADC_ACCUMULATE_DISABLE      = ADC_AVGCTRL_SAMPLENUM_1,
+    /** Average 2 samples */
+    ADC_ACCUMULATE_SAMPLES_2    = ADC_AVGCTRL_SAMPLENUM_2,
+    /** Average 4 samples */
+    ADC_ACCUMULATE_SAMPLES_4    = ADC_AVGCTRL_SAMPLENUM_4,
+    /** Average 8 samples */
+    ADC_ACCUMULATE_SAMPLES_8    = ADC_AVGCTRL_SAMPLENUM_8,
+    /** Average 16 samples */
+    ADC_ACCUMULATE_SAMPLES_16   = ADC_AVGCTRL_SAMPLENUM_16,
+    /** Average 32 samples */
+    ADC_ACCUMULATE_SAMPLES_32   = ADC_AVGCTRL_SAMPLENUM_32,
+    /** Average 64 samples */
+    ADC_ACCUMULATE_SAMPLES_64   = ADC_AVGCTRL_SAMPLENUM_64,
+    /** Average 128 samples */
+    ADC_ACCUMULATE_SAMPLES_128  = ADC_AVGCTRL_SAMPLENUM_128,
+    /** Average 256 samples */
+    ADC_ACCUMULATE_SAMPLES_256  = ADC_AVGCTRL_SAMPLENUM_256,
+    /** Average 512 samples */
+    ADC_ACCUMULATE_SAMPLES_512  = ADC_AVGCTRL_SAMPLENUM_512,
+    /** Average 1024 samples */
+    ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
 };
 
 /**
@@ -372,22 +372,22 @@ enum adc_accumulate_samples {
  * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
  */
 enum adc_divide_result {
-	/** Don't divide result register after accumulation */
-	ADC_DIVIDE_RESULT_DISABLE = 0,
-	/** Divide result register by 2 after accumulation */
-	ADC_DIVIDE_RESULT_2       = 1,
-	/** Divide result register by 4 after accumulation */
-	ADC_DIVIDE_RESULT_4       = 2,
-	/** Divide result register by 8 after accumulation */
-	ADC_DIVIDE_RESULT_8       = 3,
-	/** Divide result register by 16 after accumulation */
-	ADC_DIVIDE_RESULT_16      = 4,
-	/** Divide result register by 32 after accumulation */
-	ADC_DIVIDE_RESULT_32      = 5,
-	/** Divide result register by 64 after accumulation */
-	ADC_DIVIDE_RESULT_64      = 6,
-	/** Divide result register by 128 after accumulation */
-	ADC_DIVIDE_RESULT_128     = 7,
+    /** Don't divide result register after accumulation */
+    ADC_DIVIDE_RESULT_DISABLE = 0,
+    /** Divide result register by 2 after accumulation */
+    ADC_DIVIDE_RESULT_2       = 1,
+    /** Divide result register by 4 after accumulation */
+    ADC_DIVIDE_RESULT_4       = 2,
+    /** Divide result register by 8 after accumulation */
+    ADC_DIVIDE_RESULT_8       = 3,
+    /** Divide result register by 16 after accumulation */
+    ADC_DIVIDE_RESULT_16      = 4,
+    /** Divide result register by 32 after accumulation */
+    ADC_DIVIDE_RESULT_32      = 5,
+    /** Divide result register by 64 after accumulation */
+    ADC_DIVIDE_RESULT_64      = 6,
+    /** Divide result register by 128 after accumulation */
+    ADC_DIVIDE_RESULT_128     = 7,
 };
 
 #if ADC_CALLBACK_MODE == true
@@ -395,12 +395,12 @@ enum adc_divide_result {
  * Enum for the possible ADC interrupt flags.
  */
 enum adc_interrupt_flag {
-	/** ADC result ready */
-	ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
-	/** Window monitor match */
-	ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
-	/** ADC result overwritten before read */
-	ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
+    /** ADC result ready */
+    ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
+    /** Window monitor match */
+    ADC_INTERRUPT_WINDOW       = ADC_INTFLAG_WINMON,
+    /** ADC result overwritten before read */
+    ADC_INTERRUPT_OVERRUN      = ADC_INTFLAG_OVERRUN,
 };
 #endif
 
@@ -412,16 +412,16 @@ enum adc_interrupt_flag {
  *
  */
 enum adc_oversampling_and_decimation {
-	/** Don't use oversampling and decimation mode */
-	ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
-	/** 1-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
-	/** 2-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
-	/** 3-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
-	/** 4-bit resolution increase */
-	ADC_OVERSAMPLING_AND_DECIMATION_4BIT
+    /** Don't use oversampling and decimation mode */
+    ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
+    /** 1-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
+    /** 2-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
+    /** 3-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
+    /** 4-bit resolution increase */
+    ADC_OVERSAMPLING_AND_DECIMATION_4BIT
 };
 
 #ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
@@ -429,10 +429,10 @@ enum adc_oversampling_and_decimation {
  * Enum for the trigger selection in dual mode.
  */
 enum adc_dual_mode_trigger_selection {
-	/** Start event or software trigger will start a conversion on both ADCs */
-	ADC_DUAL_MODE_BOTH         = ADC_CTRLC_DUALSEL_BOTH,
-	/** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
-	ADC_DUAL_MODE_INTERLEAVE   = ADC_CTRLC_DUALSEL_INTERLEAVE,
+    /** Start event or software trigger will start a conversion on both ADCs */
+    ADC_DUAL_MODE_BOTH         = ADC_CTRLC_DUALSEL_BOTH,
+    /** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
+    ADC_DUAL_MODE_INTERLEAVE   = ADC_CTRLC_DUALSEL_INTERLEAVE,
 };
 #endif
 
@@ -442,12 +442,12 @@ enum adc_dual_mode_trigger_selection {
  * Window monitor configuration structure.
  */
 struct adc_window_config {
-	/** Selected window mode */
-	enum adc_window_mode window_mode;
-	/** Lower window value */
-	int32_t window_lower_value;
-	/** Upper window value */
-	int32_t window_upper_value;
+    /** Selected window mode */
+    enum adc_window_mode window_mode;
+    /** Lower window value */
+    int32_t window_lower_value;
+    /** Upper window value */
+    int32_t window_upper_value;
 };
 
 /**
@@ -457,10 +457,10 @@ struct adc_window_config {
  * disable events via \ref adc_enable_events() and \ref adc_disable_events().
  */
 struct adc_events {
-	/** Enable event generation on conversion done */
-	bool generate_event_on_conversion_done;
-	/** Enable event generation on window monitor */
-	bool generate_event_on_window_monitor;
+    /** Enable event generation on conversion done */
+    bool generate_event_on_conversion_done;
+    /** Enable event generation on window monitor */
+    bool generate_event_on_window_monitor;
 };
 
 /**
@@ -471,25 +471,25 @@ struct adc_events {
  * \ref adc_get_config_defaults.
  */
 struct adc_correction_config {
-	/**
-	 * Enables correction for gain and offset based on values of gain_correction and
-	 * offset_correction if set to true
-	 */
-	bool correction_enable;
-	/**
-	 * This value defines how the ADC conversion result is compensated for gain
-	 * error before written to the result register. This is a fractional value,
-	 * 1-bit integer plus an 11-bit fraction, therefore
-	 * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
-	 * \c 0b010000000000 to \c 0b111111111111.
-	 */
-	uint16_t gain_correction;
-	/**
-	 * This value defines how the ADC conversion result is compensated for
-	 * offset error before written to the result register. This is a 12-bit
-	 * value in two's complement format.
-	 */
-	int16_t offset_correction;
+    /**
+     * Enables correction for gain and offset based on values of gain_correction and
+     * offset_correction if set to true
+     */
+    bool correction_enable;
+    /**
+     * This value defines how the ADC conversion result is compensated for gain
+     * error before written to the result register. This is a fractional value,
+     * 1-bit integer plus an 11-bit fraction, therefore
+     * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
+     * \c 0b010000000000 to \c 0b111111111111.
+     */
+    uint16_t gain_correction;
+    /**
+     * This value defines how the ADC conversion result is compensated for
+     * offset error before written to the result register. This is a 12-bit
+     * value in two's complement format.
+     */
+    int16_t offset_correction;
 };
 
 /**
@@ -500,65 +500,65 @@ struct adc_correction_config {
  * function before being modified by the user application.
  */
 struct adc_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Voltage reference */
-	enum adc_reference reference;
-	/** Clock prescaler */
-	enum adc_clock_prescaler clock_prescaler;
-	/** Result resolution */
-	enum adc_resolution resolution;
-	/** Positive MUX input */
-	enum adc_positive_input positive_input;
-	/** Negative MUX input */
-	enum adc_negative_input negative_input;
-	/** Number of ADC samples to accumulate when using the
-	 *  \c ADC_RESOLUTION_CUSTOM mode
-	 */
-	enum adc_accumulate_samples accumulate_samples;
-	/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
-	enum adc_divide_result divide_result;
-	/** Left adjusted result */
-	bool left_adjust;
-	/** Enables differential mode if true */
-	bool differential_mode;
-	/** Enables free running mode if true */
-	bool freerunning;
-	/** ADC run in standby control */
-	bool run_in_standby;
-	/** ADC On demand control */
-	bool on_demand;
-	/**
-	 * Enables sampling period offset compensation if true
-	 */
-	bool sampling_time_compensation_enable;
-	/**
-	 * Positive input enabled mask for conversion sequence.
-	 * The sequence start from the lowest input, and go to the next enabled input
-	 * automatically when the conversion is done. If no bits are set the
-	 * sequence is disabled.
-	 */
-	uint32_t positive_input_sequence_mask_enable;
-	/**
-	 * Enables reference buffer offset compensation if true.
-	 * This will increase the accuracy of the gain stage, but decreases the input
-	 * impedance; therefore the startup time of the reference must be increased.
-	 */
-	bool reference_compensation_enable;
-	/**
-	 * This value (0-63) control the ADC sampling time in number of half ADC
-	 * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
-	 * controlling the ADC input impedance. Sampling time is set according to
-	 * the formula:
-	 * Sample time = (sample_length+1) * (ADCclk / 2).
-	 */
-	uint8_t sample_length;
-	/** Window monitor configuration structure */
-	struct adc_window_config window;
-	/** Gain and offset correction configuration structure */
-	struct adc_correction_config correction;
-	/** Event action to take on incoming event */
-	enum adc_event_action event_action;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** Voltage reference */
+    enum adc_reference reference;
+    /** Clock prescaler */
+    enum adc_clock_prescaler clock_prescaler;
+    /** Result resolution */
+    enum adc_resolution resolution;
+    /** Positive MUX input */
+    enum adc_positive_input positive_input;
+    /** Negative MUX input */
+    enum adc_negative_input negative_input;
+    /** Number of ADC samples to accumulate when using the
+     *  \c ADC_RESOLUTION_CUSTOM mode
+     */
+    enum adc_accumulate_samples accumulate_samples;
+    /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
+    enum adc_divide_result divide_result;
+    /** Left adjusted result */
+    bool left_adjust;
+    /** Enables differential mode if true */
+    bool differential_mode;
+    /** Enables free running mode if true */
+    bool freerunning;
+    /** ADC run in standby control */
+    bool run_in_standby;
+    /** ADC On demand control */
+    bool on_demand;
+    /**
+     * Enables sampling period offset compensation if true
+     */
+    bool sampling_time_compensation_enable;
+    /**
+     * Positive input enabled mask for conversion sequence.
+     * The sequence start from the lowest input, and go to the next enabled input
+     * automatically when the conversion is done. If no bits are set the
+     * sequence is disabled.
+     */
+    uint32_t positive_input_sequence_mask_enable;
+    /**
+     * Enables reference buffer offset compensation if true.
+     * This will increase the accuracy of the gain stage, but decreases the input
+     * impedance; therefore the startup time of the reference must be increased.
+     */
+    bool reference_compensation_enable;
+    /**
+     * This value (0-63) control the ADC sampling time in number of half ADC
+     * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
+     * controlling the ADC input impedance. Sampling time is set according to
+     * the formula:
+     * Sample time = (sample_length+1) * (ADCclk / 2).
+     */
+    uint8_t sample_length;
+    /** Window monitor configuration structure */
+    struct adc_window_config window;
+    /** Gain and offset correction configuration structure */
+    struct adc_correction_config correction;
+    /** Event action to take on incoming event */
+    enum adc_event_action event_action;
 };
 
 /**
@@ -572,25 +572,25 @@ struct adc_config {
  */
 struct adc_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to ADC hardware module */
-	Adc *hw;
-	/** Keep reference configuration so we know when enable is called */
-	enum adc_reference reference;
+    /** Pointer to ADC hardware module */
+    Adc *hw;
+    /** Keep reference configuration so we know when enable is called */
+    enum adc_reference reference;
 #  if ADC_CALLBACK_MODE == true
-	/** Array to store callback functions */
-	adc_callback_t callback[ADC_CALLBACK_N];
-	/** Pointer to buffer used for ADC results */
-	volatile uint16_t *job_buffer;
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback_mask;
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status;
-	/** If software triggering is needed */
-	bool software_trigger;
+    /** Array to store callback functions */
+    adc_callback_t callback[ADC_CALLBACK_N];
+    /** Pointer to buffer used for ADC results */
+    volatile uint16_t *job_buffer;
+    /** Remaining number of conversions in current job */
+    volatile uint16_t remaining_conversions;
+    /** Bit mask for callbacks registered */
+    uint8_t registered_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enabled_callback_mask;
+    /** Holds the status of the ongoing or last conversion job */
+    volatile enum status_code job_status;
+    /** If software triggering is needed */
+    bool software_trigger;
 #  endif
 #endif
 };
@@ -614,18 +614,19 @@ struct adc_module {
  * \retval false if the module has completed synchronization
  */
 static inline bool adc_is_syncing(
-	struct adc_module *const module_inst)
+    struct adc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Adc *const adc_module = module_inst->hw;
+    Adc *const adc_module = module_inst->hw;
 
-	if (adc_module->SYNCBUSY.reg) {
-		return true;
-	}
+    if (adc_module->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 #endif
 
@@ -645,14 +646,14 @@ static inline bool adc_is_syncing(
  * \param[in] eanble_seq_mask  Sequence mask
  */
 static inline void adc_enable_positive_input_sequence(
-		struct adc_module *const module_inst,
-		uint32_t positive_input_sequence_mask_enable)
+        struct adc_module *const module_inst,
+        uint32_t positive_input_sequence_mask_enable)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Adc *const adc_module = module_inst->hw;
-	adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable;
+    Adc *const adc_module = module_inst->hw;
+    adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable;
 }
 
 /**
@@ -663,13 +664,13 @@ static inline void adc_enable_positive_input_sequence(
  * \param[in] module_inst  Pointer to the ADC software instance struct
  */
 static inline void adc_disable_positive_input_sequence(
-		struct adc_module *const module_inst)
+        struct adc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Adc *const adc_module = module_inst->hw;
-	adc_module->SEQCTRL.reg = 0;
+    Adc *const adc_module = module_inst->hw;
+    adc_module->SEQCTRL.reg = 0;
 }
 
 /**
@@ -683,19 +684,20 @@ static inline void adc_disable_positive_input_sequence(
  *             done in the sequence
  */
 static inline void adc_get_sequence_status(
-		struct adc_module *const module_inst,
-		bool  * is_sequence_busy,
-		uint8_t *sequence_state)
+        struct adc_module *const module_inst,
+        bool  * is_sequence_busy,
+        uint8_t *sequence_state)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	uint8_t temp = false;
-	Adc *const adc_module = module_inst->hw;
-	temp = adc_module->SEQSTATUS.reg;
-	if(temp & ADC_SEQSTATUS_SEQBUSY){
-		*is_sequence_busy = true;
-	}
-	*sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    uint8_t temp = false;
+    Adc *const adc_module = module_inst->hw;
+    temp = adc_module->SEQSTATUS.reg;
+    if(temp & ADC_SEQSTATUS_SEQBUSY)
+    {
+        *is_sequence_busy = true;
+    }
+    *sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk;
 }
 
 /** @} */
@@ -712,16 +714,16 @@ static inline void adc_get_sequence_status(
  *
  */
 static inline void adc_set_master_slave_mode(
-		struct adc_module *const master_inst,
-		struct adc_module *const slave_inst,
-		enum adc_dual_mode_trigger_selection dualsel)
+        struct adc_module *const master_inst,
+        struct adc_module *const slave_inst,
+        enum adc_dual_mode_trigger_selection dualsel)
 {
-	/* Sanity check arguments */
-	Assert(master_inst);
-	Assert(slave_inst);
+    /* Sanity check arguments */
+    Assert(master_inst);
+    Assert(slave_inst);
 
-	slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
-	master_inst->hw->CTRLC.reg |= dualsel;
+    slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
+    master_inst->hw->CTRLC.reg |= dualsel;
 
 };
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c
index 078a6a73a1b4..6ea699920e3d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.c
@@ -74,20 +74,20 @@
  *  \param[out] config Pointer to an AES configuration structure
  */
 void aes_get_config_defaults(
-		struct aes_config *const config)
+        struct aes_config *const config)
 {
 
-	/* Sanity check arguments */
-	Assert(config);
-	config->encrypt_mode = AES_ENCRYPTION;
-	config->key_size = AES_KEY_SIZE_128;
-	config->start_mode = AES_MANUAL_START;
-	config->opmode= AES_ECB_MODE;
-	config->cfb_size = AES_CFB_SIZE_128;
-	config->ctype = AES_COUNTERMEASURE_TYPE_ALL;
-	config->enable_xor_key = false;
-	config->enable_key_gen = false;
-	config->lod = false;
+    /* Sanity check arguments */
+    Assert(config);
+    config->encrypt_mode = AES_ENCRYPTION;
+    config->key_size = AES_KEY_SIZE_128;
+    config->start_mode = AES_MANUAL_START;
+    config->opmode= AES_ECB_MODE;
+    config->cfb_size = AES_CFB_SIZE_128;
+    config->ctype = AES_COUNTERMEASURE_TYPE_ALL;
+    config->enable_xor_key = false;
+    config->enable_key_gen = false;
+    config->lod = false;
 }
 
 /**
@@ -98,23 +98,23 @@ void aes_get_config_defaults(
  * \param[in] config  Pointer to an AES configuration structure
  */
 void aes_init(
-		struct aes_module *const module,
-		Aes *const hw,
-		struct aes_config *const config)
+        struct aes_module *const module,
+        Aes *const hw,
+        struct aes_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(config);
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(config);
+    Assert(module);
 
-	/* Enable clock for AES */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AES);
+    /* Enable clock for AES */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_AES);
 
-	/* Perform a software reset */
-	hw->CTRLA.reg = AES_CTRLA_SWRST;
+    /* Perform a software reset */
+    hw->CTRLA.reg = AES_CTRLA_SWRST;
 
-	/* Initialize the AES with new configurations */
-	aes_set_config(module,hw, config);
+    /* Initialize the AES with new configurations */
+    aes_set_config(module,hw, config);
 }
 
 /**
@@ -124,9 +124,9 @@ void aes_init(
  */
 void aes_enable(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
-	module->hw->CTRLA.reg |= AES_CTRLA_ENABLE;
+    Assert(module);
+    Assert(module->hw);
+    module->hw->CTRLA.reg |= AES_CTRLA_ENABLE;
 
 }
 
@@ -136,15 +136,15 @@ void aes_enable(struct aes_module *const module)
  */
 void aes_disable(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	/* Disbale interrupt */
-	module->hw->INTENCLR.reg = AES_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	module->hw->INTFLAG.reg = AES_INTFLAG_MASK;
+    /* Disbale interrupt */
+    module->hw->INTENCLR.reg = AES_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    module->hw->INTFLAG.reg = AES_INTFLAG_MASK;
 
-	module->hw->CTRLA.reg &= (~AES_CTRLA_ENABLE);
+    module->hw->CTRLA.reg &= (~AES_CTRLA_ENABLE);
 }
 
 /**
@@ -155,38 +155,39 @@ void aes_disable(struct aes_module *const module)
  * \param[in] config  Pointer to an AES configuration structure
  */
 void aes_set_config(
-		struct aes_module *const module,
-		Aes *const hw,
-		struct aes_config *const config)
+        struct aes_module *const module,
+        Aes *const hw,
+        struct aes_config *const config)
 {
-	uint32_t ul_mode = 0;
-
-	/* Validate arguments. */
-	Assert(hw);
-	Assert(config);
-	Assert(module);
-
-	module->opmode = config->opmode;
-	module->hw = hw;
-	module->key_size = config->key_size;
-	module->cfb_size = config->cfb_size;
-
-	ul_mode |= (config->encrypt_mode << AES_CTRLA_CIPHER_Pos)
-			 | (config->start_mode << AES_CTRLA_STARTMODE_Pos)
-			 | (config->key_size << AES_CTRLA_KEYSIZE_Pos)
-			 | (config->opmode << AES_CTRLA_AESMODE_Pos)
-			 | (config->cfb_size << AES_CTRLA_CFBS_Pos)
-			 | (AES_CTRLA_CTYPE(config->ctype))
-			 | (config->enable_xor_key << AES_CTRLA_XORKEY_Pos)
-			 | (config->enable_key_gen << AES_CTRLA_KEYGEN_Pos)
-			 | (config->lod << AES_CTRLA_LOD_Pos);
-	if (hw->CTRLA.reg & AES_CTRLA_ENABLE) {
-		aes_disable(module);
-		hw->CTRLA.reg = ul_mode;
-		aes_enable(module);
-	} else {
-		hw->CTRLA.reg = ul_mode;
-	}
+    uint32_t ul_mode = 0;
+
+    /* Validate arguments. */
+    Assert(hw);
+    Assert(config);
+    Assert(module);
+
+    module->opmode = config->opmode;
+    module->hw = hw;
+    module->key_size = config->key_size;
+    module->cfb_size = config->cfb_size;
+
+    ul_mode |= (config->encrypt_mode << AES_CTRLA_CIPHER_Pos)
+             | (config->start_mode << AES_CTRLA_STARTMODE_Pos)
+             | (config->key_size << AES_CTRLA_KEYSIZE_Pos)
+             | (config->opmode << AES_CTRLA_AESMODE_Pos)
+             | (config->cfb_size << AES_CTRLA_CFBS_Pos)
+             | (AES_CTRLA_CTYPE(config->ctype))
+             | (config->enable_xor_key << AES_CTRLA_XORKEY_Pos)
+             | (config->enable_key_gen << AES_CTRLA_KEYGEN_Pos)
+             | (config->lod << AES_CTRLA_LOD_Pos);
+    if (hw->CTRLA.reg & AES_CTRLA_ENABLE)
+    {
+        aes_disable(module);
+        hw->CTRLA.reg = ul_mode;
+        aes_enable(module);
+    } else {
+        hw->CTRLA.reg = ul_mode;
+    }
 }
 
 /**
@@ -198,37 +199,39 @@ void aes_set_config(
  * \note The key size depends on the current AES configuration.
  */
 void aes_write_key(
-		struct aes_module *const module,
-		const uint32_t *key)
+        struct aes_module *const module,
+        const uint32_t *key)
 {
-	uint32_t i, key_length = 0;
-
-	/* Validate arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(key);
-
-	switch (module->key_size) {
-	case AES_KEY_SIZE_128:
-		key_length = 4;
-		break;
-
-	case AES_KEY_SIZE_192:
-		key_length = 6;
-		break;
-
-	case AES_KEY_SIZE_256:
-		key_length = 8;
-		break;
-
-	default:
-		break;
-	}
-
-	for (i = 0; i < key_length; i++) {
-		module->hw->KEYWORD[i].reg = *key;
-		key++;
-	}
+    uint32_t i, key_length = 0;
+
+    /* Validate arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(key);
+
+    switch (module->key_size)
+    {
+    case AES_KEY_SIZE_128:
+        key_length = 4;
+        break;
+
+    case AES_KEY_SIZE_192:
+        key_length = 6;
+        break;
+
+    case AES_KEY_SIZE_256:
+        key_length = 8;
+        break;
+
+    default:
+        break;
+    }
+
+    for (i = 0; i < key_length; i++)
+    {
+        module->hw->KEYWORD[i].reg = *key;
+        key++;
+    }
 }
 
 /**
@@ -239,20 +242,21 @@ void aes_write_key(
  * \param[in] vector Pointer to four contiguous 32-bit words
  */
 void aes_write_init_vector(
-		struct aes_module *const module,
-		const uint32_t *vector)
+        struct aes_module *const module,
+        const uint32_t *vector)
 {
-	uint32_t i;
-
-	/* Validate arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(module->opmode != AES_ECB_MODE);
-
-	for (i = 0; i < 4; i++) {
-		module->hw->INTVECTV[i].reg = *vector;
-		vector++;
-	}
+    uint32_t i;
+
+    /* Validate arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(module->opmode != AES_ECB_MODE);
+
+    for (i = 0; i < 4; i++)
+    {
+        module->hw->INTVECTV[i].reg = *vector;
+        vector++;
+    }
 }
 
 /**
@@ -262,32 +266,36 @@ void aes_write_init_vector(
  * \param[in] input_data_buffer Pointer to an input data buffer
  */
 void aes_write_input_data(
-		struct aes_module *const module,
-		const uint32_t *input_data_buffer)
+        struct aes_module *const module,
+        const uint32_t *input_data_buffer)
 {
-	uint32_t i;
-
-	/* Validate arguments. */
-	Assert(module);
-	Assert(module->hw);;
-	Assert(input_data_buffer);
-
-	module->hw->DATABUFPTR.reg = 0;
-	if (module->opmode == AES_CFB_MODE
-		&& module->cfb_size == AES_CFB_SIZE_64){
-		for (i = 0; i < 2; i++) {
-			module->hw->INDATA.reg = *input_data_buffer;
-			input_data_buffer++;
-		}
-	} else if (module->opmode == AES_CFB_MODE
-		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
-		module->hw->INDATA.reg = *input_data_buffer;
-	} else {
-		for (i = 0; i < 4; i++) {
-			module->hw->INDATA.reg = *input_data_buffer;
-			input_data_buffer++;
-		}
-	}
+    uint32_t i;
+
+    /* Validate arguments. */
+    Assert(module);
+    Assert(module->hw);;
+    Assert(input_data_buffer);
+
+    module->hw->DATABUFPTR.reg = 0;
+    if (module->opmode == AES_CFB_MODE
+        && module->cfb_size == AES_CFB_SIZE_64)
+        {
+        for (i = 0; i < 2; i++)
+        {
+            module->hw->INDATA.reg = *input_data_buffer;
+            input_data_buffer++;
+        }
+    } else if (module->opmode == AES_CFB_MODE
+        && (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16))
+        {
+        module->hw->INDATA.reg = *input_data_buffer;
+    } else {
+        for (i = 0; i < 4; i++)
+        {
+            module->hw->INDATA.reg = *input_data_buffer;
+            input_data_buffer++;
+        }
+    }
 }
 
 /**
@@ -300,30 +308,34 @@ void aes_write_input_data(
  * \param[in] output_data_buffer Pointer to an output buffer
  */
 void aes_read_output_data(
-		struct aes_module *const module,
-		uint32_t *output_data_buffer)
+        struct aes_module *const module,
+        uint32_t *output_data_buffer)
 {
-	uint32_t i;
-
-	/* Validate arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(output_data_buffer);
-
-	module->hw->DATABUFPTR.reg = 0;
-	if (module->opmode == AES_CFB_MODE
-		&& module->cfb_size == AES_CFB_SIZE_64){
-		for (i = 0; i < 2; i++) {
-			*output_data_buffer = module->hw->INDATA.reg;
-			output_data_buffer++;
-		}
-	} else if (module->opmode == AES_CFB_MODE
-		&& (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16)){
-		*output_data_buffer = module->hw->INDATA.reg;
-	} else {
-		for (i = 0; i < 4; i++) {
-			*output_data_buffer = module->hw->INDATA.reg;
-			output_data_buffer++;
-		}
-	}
+    uint32_t i;
+
+    /* Validate arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(output_data_buffer);
+
+    module->hw->DATABUFPTR.reg = 0;
+    if (module->opmode == AES_CFB_MODE
+        && module->cfb_size == AES_CFB_SIZE_64)
+        {
+        for (i = 0; i < 2; i++)
+        {
+            *output_data_buffer = module->hw->INDATA.reg;
+            output_data_buffer++;
+        }
+    } else if (module->opmode == AES_CFB_MODE
+        && (module->cfb_size == AES_CFB_SIZE_32 || module->cfb_size == AES_CFB_SIZE_16))
+        {
+        *output_data_buffer = module->hw->INDATA.reg;
+    } else {
+        for (i = 0; i < 4; i++)
+        {
+            *output_data_buffer = module->hw->INDATA.reg;
+            output_data_buffer++;
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h
index 4d064018a47d..6dc9e8432084 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes.h
@@ -183,51 +183,51 @@ extern "C" {
 
 /** AES processing mode. */
 enum aes_encrypt_mode {
-	AES_DECRYPTION = 0,     /**< Decryption of data will be performed */
-	AES_ENCRYPTION,         /**< Encryption of data will be performed */
+    AES_DECRYPTION = 0,     /**< Decryption of data will be performed */
+    AES_ENCRYPTION,         /**< Encryption of data will be performed */
 };
 
 /** AES cryptographic key size. */
 enum aes_key_size {
-	AES_KEY_SIZE_128 = 0,   /**< AES key size is 128-bit */
-	AES_KEY_SIZE_192,       /**< AES key size is 192-bit */
-	AES_KEY_SIZE_256,       /**< AES key size is 256-bit */
+    AES_KEY_SIZE_128 = 0,   /**< AES key size is 128-bit */
+    AES_KEY_SIZE_192,       /**< AES key size is 192-bit */
+    AES_KEY_SIZE_256,       /**< AES key size is 256-bit */
 };
 
 /** AES start mode. */
 enum aes_start_mode {
-	AES_MANUAL_START = 0,   /**< Manual start mode */
-	AES_AUTO_START,         /**< Auto start mode */
+    AES_MANUAL_START = 0,   /**< Manual start mode */
+    AES_AUTO_START,         /**< Auto start mode */
 };
 
 /** AES operation mode. */
 enum aes_operation_mode {
-	AES_ECB_MODE = 0,       /**< Electronic Codebook (ECB) */
-	AES_CBC_MODE,           /**< Cipher Block Chaining (CBC) */
-	AES_OFB_MODE,           /**< Output Feedback (OFB) */
-	AES_CFB_MODE,           /**< Cipher Feedback (CFB) */
-	AES_CTR_MODE,           /**< Counter (CTR) */
-	AES_CCM_MODE,           /**< Counter (CCM) */
-	AES_GCM_MODE,           /**< Galois Counter Mode (GCM) */
+    AES_ECB_MODE = 0,       /**< Electronic Codebook (ECB) */
+    AES_CBC_MODE,           /**< Cipher Block Chaining (CBC) */
+    AES_OFB_MODE,           /**< Output Feedback (OFB) */
+    AES_CFB_MODE,           /**< Cipher Feedback (CFB) */
+    AES_CTR_MODE,           /**< Counter (CTR) */
+    AES_CCM_MODE,           /**< Counter (CCM) */
+    AES_GCM_MODE,           /**< Galois Counter Mode (GCM) */
 };
 
 /** AES Cipher FeedBack (CFB) size. */
 enum aes_cfb_size {
-	AES_CFB_SIZE_128 = 0,   /**< Cipher feedback data size is 128-bit */
-	AES_CFB_SIZE_64,        /**< Cipher feedback data size is 64-bit */
-	AES_CFB_SIZE_32,        /**< Cipher feedback data size is 32-bit */
-	AES_CFB_SIZE_16,        /**< Cipher feedback data size is 16-bit */
-	AES_CFB_SIZE_8,         /**< Cipher feedback data size is 8-bit */
+    AES_CFB_SIZE_128 = 0,   /**< Cipher feedback data size is 128-bit */
+    AES_CFB_SIZE_64,        /**< Cipher feedback data size is 64-bit */
+    AES_CFB_SIZE_32,        /**< Cipher feedback data size is 32-bit */
+    AES_CFB_SIZE_16,        /**< Cipher feedback data size is 16-bit */
+    AES_CFB_SIZE_8,         /**< Cipher feedback data size is 8-bit */
 };
 
 /** AES countermeasure type */
 enum aes_countermeature_type {
-	AES_COUNTERMEASURE_TYPE_disabled = 0x0,    /**< Countermeasure type all disabled */
-	AES_COUNTERMEASURE_TYPE_1 = 0x01,          /**< Countermeasure1 enabled */
-	AES_COUNTERMEASURE_TYPE_2 = 0x02,          /**< Countermeasure2 enabled */
-	AES_COUNTERMEASURE_TYPE_3 = 0x04,          /**< Countermeasure3 enabled */
-	AES_COUNTERMEASURE_TYPE_4 = 0x08,          /**< Countermeasure4 enabled */
-	AES_COUNTERMEASURE_TYPE_ALL = 0x0F,        /**< Countermeasure type all enabled */
+    AES_COUNTERMEASURE_TYPE_disabled = 0x0,    /**< Countermeasure type all disabled */
+    AES_COUNTERMEASURE_TYPE_1 = 0x01,          /**< Countermeasure1 enabled */
+    AES_COUNTERMEASURE_TYPE_2 = 0x02,          /**< Countermeasure2 enabled */
+    AES_COUNTERMEASURE_TYPE_3 = 0x04,          /**< Countermeasure3 enabled */
+    AES_COUNTERMEASURE_TYPE_4 = 0x08,          /**< Countermeasure4 enabled */
+    AES_COUNTERMEASURE_TYPE_ALL = 0x0F,        /**< Countermeasure type all enabled */
 };
 
 /**
@@ -251,24 +251,24 @@ enum aes_countermeature_type {
 
 /** AES Configuration structure. */
 struct aes_config {
-	/** AES data mode (decryption or encryption) */
-	enum aes_encrypt_mode encrypt_mode;
-	/** AES key size */
-	enum aes_key_size key_size;
-	/** Start mode */
-	enum aes_start_mode start_mode;
-	/** AES cipher operation mode*/
-	enum aes_operation_mode opmode;
-	/** Cipher feedback data size */
-	enum aes_cfb_size cfb_size;
-	/** Countermeasure type */
-	enum aes_countermeature_type ctype;
-	/** Enable XOR key */
-	bool enable_xor_key;
-	/** Enable key generation */
-	bool enable_key_gen;
-	/** Last output data mode enable/disable */
-	bool lod;
+    /** AES data mode (decryption or encryption) */
+    enum aes_encrypt_mode encrypt_mode;
+    /** AES key size */
+    enum aes_key_size key_size;
+    /** Start mode */
+    enum aes_start_mode start_mode;
+    /** AES cipher operation mode*/
+    enum aes_operation_mode opmode;
+    /** Cipher feedback data size */
+    enum aes_cfb_size cfb_size;
+    /** Countermeasure type */
+    enum aes_countermeature_type ctype;
+    /** Enable XOR key */
+    bool enable_xor_key;
+    /** Enable key generation */
+    bool enable_key_gen;
+    /** Last output data mode enable/disable */
+    bool lod;
 };
 
 #if !defined(__DOXYGEN__)
@@ -276,14 +276,14 @@ struct aes_config {
  * \brief Device structure.
  */
 struct aes_module {
-	/** AES hardware module. */
-	Aes *hw;
-	/** AES cipher operation mode.*/
-	enum aes_operation_mode opmode;
-	/** AES key size. */
-	enum aes_key_size key_size;
-	/** Cipher feedback data size. */
-	enum aes_cfb_size cfb_size;
+    /** AES hardware module. */
+    Aes *hw;
+    /** AES cipher operation mode.*/
+    enum aes_operation_mode opmode;
+    /** AES key size. */
+    enum aes_key_size key_size;
+    /** Cipher feedback data size. */
+    enum aes_cfb_size cfb_size;
 };
 #endif
 
@@ -294,12 +294,12 @@ struct aes_module {
 void aes_get_config_defaults(struct aes_config *const config);
 
 void aes_set_config(struct aes_module *const module,
-					Aes *const hw,
-					struct aes_config *const config);
+                    Aes *const hw,
+                    struct aes_config *const config);
 
 void aes_init(struct aes_module *const module,
-				Aes *const hw,
-				struct aes_config *const config);
+                Aes *const hw,
+                struct aes_config *const config);
 
 /** @} */
 
@@ -315,10 +315,10 @@ void aes_init(struct aes_module *const module,
  */
 static inline void aes_start(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->CTRLB.reg |= AES_CTRLB_START;
+    module->hw->CTRLB.reg |= AES_CTRLB_START;
 }
 /**
  * \brief Notifies the module that the next input data block
@@ -329,9 +329,9 @@ static inline void aes_start(struct aes_module *const module)
  */
 static inline void aes_set_new_message(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
-	module->hw->CTRLB.reg |= AES_CTRLB_NEWMSG;
+    Assert(module);
+    Assert(module->hw);
+    module->hw->CTRLB.reg |= AES_CTRLB_NEWMSG;
 }
 /**
  * \brief Clear the indication of the beginning for a new message
@@ -341,9 +341,9 @@ static inline void aes_set_new_message(struct aes_module *const module)
  */
 static inline void aes_clear_new_message(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
-	module->hw->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
+    Assert(module);
+    Assert(module->hw);
+    module->hw->CTRLB.reg &= ~AES_CTRLB_NEWMSG;
 }
 
 void aes_enable(struct aes_module *const module);
@@ -355,10 +355,10 @@ void aes_write_key(struct aes_module *const module, const uint32_t *key);
 void aes_write_init_vector(struct aes_module *const module, const uint32_t *vector);
 
 void aes_write_input_data(struct aes_module *const module,
-		const uint32_t *p_input_data_buffer);
+        const uint32_t *p_input_data_buffer);
 
 void aes_read_output_data(struct aes_module *const module,
-		uint32_t *p_output_data_buffer);
+        uint32_t *p_output_data_buffer);
 
 /**
  * \brief Write AES random seed.
@@ -367,12 +367,12 @@ void aes_read_output_data(struct aes_module *const module,
  * \param[in] seed Seed for the random number generator
  */
 static inline void aes_write_random_seed(struct aes_module *const module,
-										uint32_t seed)
+                                        uint32_t seed)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->RANDSEED.reg = seed;
+    module->hw->RANDSEED.reg = seed;
 }
 
 /** @} */
@@ -394,22 +394,24 @@ static inline void aes_write_random_seed(struct aes_module *const module,
  */
 static inline uint32_t aes_get_status(struct aes_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	uint32_t int_flags = module->hw->INTFLAG.reg;
-	uint32_t status_flags = 0;
+    uint32_t int_flags = module->hw->INTFLAG.reg;
+    uint32_t status_flags = 0;
 
-	if (int_flags & AES_INTFLAG_ENCCMP) {
-		status_flags |= AES_ENCRYPTION_COMPLETE;
-	}
+    if (int_flags & AES_INTFLAG_ENCCMP)
+    {
+        status_flags |= AES_ENCRYPTION_COMPLETE;
+    }
 
-	if (int_flags & AES_INTFLAG_GFMCMP) {
-		status_flags |= AES_GF_MULTI_COMPLETE;
-	}
+    if (int_flags & AES_INTFLAG_GFMCMP)
+    {
+        status_flags |= AES_GF_MULTI_COMPLETE;
+    }
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -421,25 +423,27 @@ static inline uint32_t aes_get_status(struct aes_module *const module)
  * \param[in] status_flags Bitmask flags to clear
  */
 static inline void aes_clear_status(
-		struct aes_module *const module,
-		const uint32_t status_flags)
+        struct aes_module *const module,
+        const uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	uint32_t int_flags = 0;
+    uint32_t int_flags = 0;
 
-	if (status_flags & AES_ENCRYPTION_COMPLETE) {
-		int_flags |= AES_INTENCLR_ENCCMP;
-	}
+    if (status_flags & AES_ENCRYPTION_COMPLETE)
+    {
+        int_flags |= AES_INTENCLR_ENCCMP;
+    }
 
-	if (status_flags & AES_GF_MULTI_COMPLETE) {
-		int_flags |= AES_INTENCLR_GFMCMP;
-	}
+    if (status_flags & AES_GF_MULTI_COMPLETE)
+    {
+        int_flags |= AES_INTENCLR_GFMCMP;
+    }
 
-	/* Clear interrupt flag */
-	module->hw->INTFLAG.reg = int_flags;
+    /* Clear interrupt flag */
+    module->hw->INTFLAG.reg = int_flags;
 }
 
 /** @} */
@@ -459,10 +463,10 @@ static inline void aes_clear_status(
  */
 static inline uint32_t aes_gcm_read_ghash(struct aes_module *const module, uint32_t id)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	return module->hw->GHASH[id].reg;
+    return module->hw->GHASH[id].reg;
 }
 
 /**
@@ -473,12 +477,12 @@ static inline uint32_t aes_gcm_read_ghash(struct aes_module *const module, uint3
  * \param[in] ghash GCM hash value
  */
 static inline void aes_gcm_write_ghash(struct aes_module *const module,
-									uint32_t id,uint32_t ghash)
+                                    uint32_t id,uint32_t ghash)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->GHASH[id].reg = ghash;
+    module->hw->GHASH[id].reg = ghash;
 }
 
 
@@ -491,12 +495,12 @@ static inline void aes_gcm_write_ghash(struct aes_module *const module,
  * \return The contents of the HASHKEYx[x = 0...3] specified.
  */
 static inline uint32_t aes_gcm_read_hash_key(struct aes_module *const module,
-											uint32_t id)
+                                            uint32_t id)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	return module->hw->HASHKEY[id].reg;
+    return module->hw->HASHKEY[id].reg;
 }
 
 /**
@@ -507,12 +511,12 @@ static inline uint32_t aes_gcm_read_hash_key(struct aes_module *const module,
  * \param[in] key GCM Hash key
  */
 static inline void aes_gcm_write_hash_key(struct aes_module *const module,
-										uint32_t id, uint32_t key)
+                                        uint32_t id, uint32_t key)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->HASHKEY[id].reg = key;
+    module->hw->HASHKEY[id].reg = key;
 }
 
 /**
@@ -524,10 +528,10 @@ static inline void aes_gcm_write_hash_key(struct aes_module *const module,
  */
 static inline uint32_t aes_gcm_read_cipher_len(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	return (module->hw->CIPLEN.reg);
+    return (module->hw->CIPLEN.reg);
 }
 
 /**
@@ -537,12 +541,12 @@ static inline uint32_t aes_gcm_read_cipher_len(struct aes_module *const module)
  * \param[in] len Cipher length
  */
 static inline void aes_gcm_write_cipher_len(struct aes_module *const module,
-										uint32_t len)
+                                        uint32_t len)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->CIPLEN.reg = len;
+    module->hw->CIPLEN.reg = len;
 }
 
 /**
@@ -552,10 +556,10 @@ static inline void aes_gcm_write_cipher_len(struct aes_module *const module,
  */
 static inline void aes_gcm_set_end_message_status(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->CTRLB.reg |= AES_CTRLB_EOM;
+    module->hw->CTRLB.reg |= AES_CTRLB_EOM;
 }
 
 /**
@@ -565,10 +569,10 @@ static inline void aes_gcm_set_end_message_status(struct aes_module *const modul
  */
 static inline void aes_gcm_clear_end_message_status(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->CTRLB.reg &= ~AES_CTRLB_EOM;
+    module->hw->CTRLB.reg &= ~AES_CTRLB_EOM;
 }
 
 /**
@@ -578,10 +582,10 @@ static inline void aes_gcm_clear_end_message_status(struct aes_module *const mod
  */
 static inline void aes_gcm_set_gf_multiplication(struct aes_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	module->hw->CTRLB.reg |= AES_CTRLB_GFMUL;
+    module->hw->CTRLB.reg |= AES_CTRLB_GFMUL;
 }
 
 /** @} */
@@ -664,12 +668,12 @@ static inline void aes_gcm_set_gf_multiplication(struct aes_module *const module
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -689,21 +693,21 @@ static inline void aes_gcm_set_gf_multiplication(struct aes_module *const module
  * \page asfdoc_sam0_drivers_aes_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
+ *  <tr>
  *      <th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
  *      <td>42445B</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L22</td>
- *	</tr>
- *	<tr>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L22</td>
+ *  </tr>
+ *  <tr>
  *      <td>42445A</td>
- *		<td>06/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *      <td>06/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  *
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c
index ee30a5ae0297..06bee9423152 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.c
@@ -61,29 +61,31 @@ aes_callback_t aes_callback_pointer[AES_CALLBACK_TYPE_NUM]={NULL,NULL};
 
 
 enum status_code aes_register_callback(
-	const aes_callback_t callback,
-	const enum aes_callback_type type)
+    const aes_callback_t callback,
+    const enum aes_callback_type type)
 {
-	if (type >= AES_CALLBACK_TYPE_NUM){
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (type >= AES_CALLBACK_TYPE_NUM)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	aes_callback_pointer[type] = callback;
-	return STATUS_OK;
+    aes_callback_pointer[type] = callback;
+    return STATUS_OK;
 }
 
 enum status_code aes_unregister_callback(
-	const aes_callback_t callback,
-	const enum aes_callback_type type)
+    const aes_callback_t callback,
+    const enum aes_callback_type type)
 {
-	if (type >= AES_CALLBACK_TYPE_NUM){
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (type >= AES_CALLBACK_TYPE_NUM)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	aes_callback_pointer[type] = NULL;
-	return STATUS_OK;
+    aes_callback_pointer[type] = NULL;
+    return STATUS_OK;
 }
 
 
@@ -93,19 +95,23 @@ enum status_code aes_unregister_callback(
 */
 void AES_Handler(void)
 {
-	uint32_t status = AES->INTFLAG.reg;
+    uint32_t status = AES->INTFLAG.reg;
 
-	if (status & AES_INTFLAG_ENCCMP) {
-		if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]) {
-			AES->INTFLAG.reg = AES_INTFLAG_ENCCMP;
-			aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
-		}
-	}
+    if (status & AES_INTFLAG_ENCCMP)
+    {
+        if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE])
+        {
+            AES->INTFLAG.reg = AES_INTFLAG_ENCCMP;
+            aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
+        }
+    }
 
-	if (status & AES_INTFLAG_GFMCMP) {
-		if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]) {
-			AES->INTFLAG.reg = AES_INTFLAG_GFMCMP;
-			aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
-		}
-	}
+    if (status & AES_INTFLAG_GFMCMP)
+    {
+        if (aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE])
+        {
+            AES->INTFLAG.reg = AES_INTFLAG_GFMCMP;
+            aes_callback_pointer[AES_CALLBACK_ENCRYPTION_COMPLETE]();
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h
index bf6f9a50ff65..02511d39570a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aes/aes_callback.h
@@ -63,27 +63,27 @@ extern "C" {
  */
 
 /** AES interrupt callback function type. */
-typedef void (*aes_callback_t)(void); 
+typedef void (*aes_callback_t)(void);
 
 /** AES callback type. */
 enum aes_callback_type {
-	/** Encryption complete callback */
-	AES_CALLBACK_ENCRYPTION_COMPLETE = 0,
-	/** GF Multiplication Complete callback */
-	AES_CALLBACK_GF_MULTI_COMPLETE = 1,
+    /** Encryption complete callback */
+    AES_CALLBACK_ENCRYPTION_COMPLETE = 0,
+    /** GF Multiplication Complete callback */
+    AES_CALLBACK_GF_MULTI_COMPLETE = 1,
 };
- 
+
 /** \name Callback Configuration and Initialization
  * @{
  */
- 
+
 enum status_code aes_register_callback(
-	const aes_callback_t callback,
-	const enum aes_callback_type type);
+    const aes_callback_t callback,
+    const enum aes_callback_type type);
 
 enum status_code aes_unregister_callback(
-	const aes_callback_t callback,
-	const enum aes_callback_type type);
+    const aes_callback_t callback,
+    const enum aes_callback_type type);
 
 /** @} */
 
@@ -103,19 +103,21 @@ enum status_code aes_unregister_callback(
  * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
  */
 static inline enum status_code aes_enable_callback(struct aes_module *const module,
-		const enum aes_callback_type type)
+        const enum aes_callback_type type)
 {
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AES);
-	if (type == AES_CALLBACK_ENCRYPTION_COMPLETE){
-		module->hw->INTENSET.reg = AES_INTENSET_ENCCMP;
-	} else if (type == AES_CALLBACK_GF_MULTI_COMPLETE){
-		module->hw->INTENSET.reg = AES_INTENSET_GFMCMP;
-	} else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_AES);
+    if (type == AES_CALLBACK_ENCRYPTION_COMPLETE)
+    {
+        module->hw->INTENSET.reg = AES_INTENSET_ENCCMP;
+    } else if (type == AES_CALLBACK_GF_MULTI_COMPLETE)
+    {
+        module->hw->INTENSET.reg = AES_INTENSET_GFMCMP;
+    } else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -129,19 +131,21 @@ static inline enum status_code aes_enable_callback(struct aes_module *const modu
  * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
  */
 static inline enum status_code aes_disable_callback(struct aes_module *const module,
-		 const enum aes_callback_type type)
+         const enum aes_callback_type type)
 {
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_AES);
-	if (type == AES_CALLBACK_ENCRYPTION_COMPLETE){
-		module->hw->INTENCLR.reg = AES_INTENCLR_ENCCMP;
-	} else if (type == AES_CALLBACK_GF_MULTI_COMPLETE){
-		module->hw->INTENCLR.reg = AES_INTENCLR_GFMCMP;
-	} else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_AES);
+    if (type == AES_CALLBACK_ENCRYPTION_COMPLETE)
+    {
+        module->hw->INTENCLR.reg = AES_INTENCLR_ENCCMP;
+    } else if (type == AES_CALLBACK_GF_MULTI_COMPLETE)
+    {
+        module->hw->INTENCLR.reg = AES_INTENCLR_GFMCMP;
+    } else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c
index a469f8a86973..933f61f6da69 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.c
@@ -49,11 +49,12 @@ static aon_sleep_timer_callback_t aon_sleep_timer_callback = NULL;
 
 static void delay_cycle(uint32_t cycles)
 {
-	volatile uint32_t i = 0;
+    volatile uint32_t i = 0;
 
-	for (i = 0; i < cycles*100; i++) {
-		asm volatile ("nop");
-	}
+    for (i = 0; i < cycles*100; i++)
+    {
+        asm volatile ("nop");
+    }
 }
 
 /**
@@ -68,10 +69,10 @@ static void delay_cycle(uint32_t cycles)
  */
 void aon_sleep_timer_get_config_defaults(struct aon_sleep_timer_config *config)
 {
-	/* Default configuration values */
-	config->wakeup = AON_SLEEP_TIMER_WAKEUP_ARM;
-	config->mode = AON_SLEEP_TIMER_SINGLE_MODE;
-	config->counter = 32000;
+    /* Default configuration values */
+    config->wakeup = AON_SLEEP_TIMER_WAKEUP_ARM;
+    config->mode = AON_SLEEP_TIMER_SINGLE_MODE;
+    config->counter = 32000;
 }
 
 /**
@@ -81,16 +82,17 @@ void aon_sleep_timer_get_config_defaults(struct aon_sleep_timer_config *config)
  */
 void aon_sleep_timer_disable(void)
 {
-	uint32_t regval;
+    uint32_t regval;
 
-	AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = 0;
-	regval = AON_SLEEP_TIMER0->CONTROL.reg;
-	regval &= ~AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
-	regval &= ~AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
-	AON_SLEEP_TIMER0->CONTROL.reg = regval;
+    AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = 0;
+    regval = AON_SLEEP_TIMER0->CONTROL.reg;
+    regval &= ~AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
+    regval &= ~AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
+    AON_SLEEP_TIMER0->CONTROL.reg = regval;
 
-	while (AON_SLEEP_TIMER0->CONTROL.reg & (1 << 14)) {
-	}
+    while (AON_SLEEP_TIMER0->CONTROL.reg & (1 << 14))
+    {
+    }
 }
 
 /**
@@ -100,7 +102,7 @@ void aon_sleep_timer_disable(void)
  */
 uint32_t aon_sleep_timer_get_current_value(void)
 {
-	return AON_SLEEP_TIMER0->CURRENT_COUNT_VALUE.reg;
+    return AON_SLEEP_TIMER0->CURRENT_COUNT_VALUE.reg;
 }
 
 /**
@@ -110,7 +112,7 @@ uint32_t aon_sleep_timer_get_current_value(void)
  */
 bool aon_sleep_timer_sleep_timer_active(void)
 {
-	return AON_SLEEP_TIMER0->CONTROL.bit.SLEEP_TIMER_ACTIVE;
+    return AON_SLEEP_TIMER0->CONTROL.bit.SLEEP_TIMER_ACTIVE;
 }
 
 /**
@@ -121,7 +123,7 @@ bool aon_sleep_timer_sleep_timer_active(void)
  */
 void aon_sleep_timer_clear_interrup(void)
 {
-	AON_SLEEP_TIMER0->CONTROL.reg |= AON_SLEEP_TIMER_CONTROL_IRQ_CLEAR;
+    AON_SLEEP_TIMER0->CONTROL.reg |= AON_SLEEP_TIMER_CONTROL_IRQ_CLEAR;
 }
 
 /**
@@ -133,7 +135,7 @@ void aon_sleep_timer_clear_interrup(void)
  */
 void aon_sleep_timer_register_callback(aon_sleep_timer_callback_t fun)
 {
-	aon_sleep_timer_callback = fun;
+    aon_sleep_timer_callback = fun;
 }
 
 /**
@@ -144,7 +146,7 @@ void aon_sleep_timer_register_callback(aon_sleep_timer_callback_t fun)
  */
 void aon_sleep_timer_unregister_callback(void)
 {
-	aon_sleep_timer_callback = NULL;
+    aon_sleep_timer_callback = NULL;
 }
 
 /**
@@ -155,11 +157,12 @@ void aon_sleep_timer_unregister_callback(void)
  */
 static void aon_sleep_timer_isr_handler(void)
 {
-	aon_sleep_timer_clear_interrup();
+    aon_sleep_timer_clear_interrup();
 
-	if (aon_sleep_timer_callback) {
-		aon_sleep_timer_callback();
-	}
+    if (aon_sleep_timer_callback)
+    {
+        aon_sleep_timer_callback();
+    }
 }
 
 /**
@@ -173,45 +176,52 @@ static void aon_sleep_timer_isr_handler(void)
  */
 void aon_sleep_timer_init(const struct aon_sleep_timer_config *config)
 {
-	uint32_t aon_st_ctrl = 0;
-
-	AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg = AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_RESETVALUE;
-	if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM_BLE) {
-		AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
-				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE |
-				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_BLE_ENABLE;
-	} else if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM) {
-		AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
-				AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE;
-	}
-
-	aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
-	while (aon_st_ctrl & ((1UL << 31) - 1)) {
-		AON_SLEEP_TIMER0->CONTROL.reg = 0;
-		delay_cycle(3);
-		while (aon_st_ctrl & ((config->mode == AON_SLEEP_TIMER_RELOAD_MODE) ?
-				(1 << 9) : (1 << 14))) {
-			aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
-		}
-		aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
-	}
-
-	if (config->mode == AON_SLEEP_TIMER_RELOAD_MODE) {
-		/* Reload counter will start here */
-		AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
-		AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
-	} else {
-		/* Single counter will start here */
-		AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
-		AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
-	}
-
-	if (config->mode == AON_SLEEP_TIMER_SINGLE_MODE) {
-		while ((AON_SLEEP_TIMER0->CONTROL.reg &
-				AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk)
-				!= AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk) {
-		}
-	}
-
-	system_register_isr(RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX, (uint32_t)aon_sleep_timer_isr_handler);
+    uint32_t aon_st_ctrl = 0;
+
+    AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg = AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_RESETVALUE;
+    if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM_BLE)
+    {
+        AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
+                AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE |
+                AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_BLE_ENABLE;
+    } else if (config->wakeup == AON_SLEEP_TIMER_WAKEUP_ARM)
+    {
+        AON_PWR_SEQ0->AON_ST_WAKEUP_CTRL.reg |=
+                AON_PWR_SEQ_AON_ST_WAKEUP_CTRL_ARM_ENABLE;
+    }
+
+    aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+    while (aon_st_ctrl & ((1UL << 31) - 1))
+    {
+        AON_SLEEP_TIMER0->CONTROL.reg = 0;
+        delay_cycle(3);
+        while (aon_st_ctrl & ((config->mode == AON_SLEEP_TIMER_RELOAD_MODE) ?
+                (1 << 9) : (1 << 14)))
+                {
+            aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+        }
+        aon_st_ctrl = AON_SLEEP_TIMER0->CONTROL.reg;
+    }
+
+    if (config->mode == AON_SLEEP_TIMER_RELOAD_MODE)
+    {
+        /* Reload counter will start here */
+        AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
+        AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_RELOAD_ENABLE;
+    } else {
+        /* Single counter will start here */
+        AON_SLEEP_TIMER0->SINGLE_COUNT_DURATION.reg = config->counter;
+        AON_SLEEP_TIMER0->CONTROL.reg = AON_SLEEP_TIMER_CONTROL_SINGLE_COUNT_ENABLE;
+    }
+
+    if (config->mode == AON_SLEEP_TIMER_SINGLE_MODE)
+    {
+        while ((AON_SLEEP_TIMER0->CONTROL.reg &
+                AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk)
+                != AON_SLEEP_TIMER_CONTROL_SLP_TIMER_SINGLE_COUNT_ENABLE_DLY_Msk)
+                {
+        }
+    }
+
+    system_register_isr(RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX, (uint32_t)aon_sleep_timer_isr_handler);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h
index 27bfa52fde28..6afc0ec05216 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/aon_sleep_timer/aon_sleep_timer.h
@@ -133,10 +133,10 @@ typedef void (*aon_sleep_timer_callback_t)(void);
  * This enum specifies counter with reload or single mode.
  */
 enum aon_sleep_timer_mode {
-	/** Counter in reload mode */
-	AON_SLEEP_TIMER_RELOAD_MODE = 0,
-	/** Counter in single mode */
-	AON_SLEEP_TIMER_SINGLE_MODE,
+    /** Counter in reload mode */
+    AON_SLEEP_TIMER_RELOAD_MODE = 0,
+    /** Counter in single mode */
+    AON_SLEEP_TIMER_SINGLE_MODE,
 };
 
 /**
@@ -145,12 +145,12 @@ enum aon_sleep_timer_mode {
  * This enum specifies arm wakeup enable or disable.
  */
 enum aon_sleep_timer_wakeup {
-	/** Wakeup disable */
-	AON_SLEEP_TIMER_WAKEUP_DIS = 0,
-	/** Arm wakeup */
-	AON_SLEEP_TIMER_WAKEUP_ARM,
-	/** Arm and blue-tooth wakeup */
-	AON_SLEEP_TIMER_WAKEUP_ARM_BLE,
+    /** Wakeup disable */
+    AON_SLEEP_TIMER_WAKEUP_DIS = 0,
+    /** Arm wakeup */
+    AON_SLEEP_TIMER_WAKEUP_ARM,
+    /** Arm and blue-tooth wakeup */
+    AON_SLEEP_TIMER_WAKEUP_ARM_BLE,
 };
 
 /**
@@ -161,13 +161,13 @@ enum aon_sleep_timer_wakeup {
  *  modified by the user application.
  */
 struct aon_sleep_timer_config {
-	/** Enable wakeup arm or wakeup arm and blue-tooth 
-	  * or disable arm wakeup */
-	enum aon_sleep_timer_wakeup wakeup;
-	/** Counter is reload or single mode */
-	enum aon_sleep_timer_mode mode;
-	/** Counter value */
-	uint32_t counter;
+    /** Enable wakeup arm or wakeup arm and blue-tooth
+      * or disable arm wakeup */
+    enum aon_sleep_timer_wakeup wakeup;
+    /** Counter is reload or single mode */
+    enum aon_sleep_timer_mode mode;
+    /** Counter value */
+    uint32_t counter;
 };
 
 /**
@@ -209,14 +209,14 @@ void aon_sleep_timer_unregister_callback(void);
  * Below is a table listing the acronyms used in this module, along with their
  * intended meanings.
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>AON SLEEP TIMER</td>
- *		<td>    </td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>AON SLEEP TIMER</td>
+ *      <td>    </td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_aon_sleep_timer_extra_dependencies Dependencies
@@ -270,4 +270,4 @@ void aon_sleep_timer_unregister_callback(void);
  * </table>
  */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c
index ee20b004e460..8b07c51988ed 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod.c
@@ -58,35 +58,39 @@
  * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
  */
 enum status_code bodvdd_set_config(
-		struct bodvdd_config *const conf)
+        struct bodvdd_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	uint32_t temp = 0;
+    uint32_t temp = 0;
 
-	/* Check if module is enabled. */
-	if (SUPC->BODVDD.reg & SUPC_BODVDD_ENABLE) {
-		SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
-	}
+    /* Check if module is enabled. */
+    if (SUPC->BODVDD.reg & SUPC_BODVDD_ENABLE)
+    {
+        SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
+    }
 
-	/* Convert BOD prescaler, trigger action and mode to a bitmask */
-	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
-			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+    /* Convert BOD prescaler, trigger action and mode to a bitmask */
+    temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+            (uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
 
-	if (conf->hysteresis == true) {
-		temp |= SUPC_BODVDD_HYST;
-	}
+    if (conf->hysteresis == true)
+    {
+        temp |= SUPC_BODVDD_HYST;
+    }
 
-	if (conf->run_in_standby == true) {
-		temp |= SUPC_BODVDD_RUNSTDBY;
-	}
+    if (conf->run_in_standby == true)
+    {
+        temp |= SUPC_BODVDD_RUNSTDBY;
+    }
 
-	if (conf->level > 0x3F) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (conf->level > 0x3F)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	SUPC->BODVDD.reg = SUPC_BODVDD_LEVEL(conf->level) | temp;
+    SUPC->BODVDD.reg = SUPC_BODVDD_LEVEL(conf->level) | temp;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h
index ad35d381a742..24d4ee33dae0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_c/bod_feature.h
@@ -120,38 +120,38 @@ extern "C" {
  * speed of a BODVDD to lower the power consumption.
  */
 enum bodvdd_prescale {
-	/** Divide input prescaler clock by 2 */
-	BODVDD_PRESCALE_DIV_2       = SUPC_BODVDD_PSEL(0),
-	/** Divide input prescaler clock by 4 */
-	BODVDD_PRESCALE_DIV_4       = SUPC_BODVDD_PSEL(1),
-	/** Divide input prescaler clock by 8 */
-	BODVDD_PRESCALE_DIV_8       = SUPC_BODVDD_PSEL(2),
-	/** Divide input prescaler clock by 16 */
-	BODVDD_PRESCALE_DIV_16      = SUPC_BODVDD_PSEL(3),
-	/** Divide input prescaler clock by 32 */
-	BODVDD_PRESCALE_DIV_32      = SUPC_BODVDD_PSEL(4),
-	/** Divide input prescaler clock by 64 */
-	BODVDD_PRESCALE_DIV_64      = SUPC_BODVDD_PSEL(5),
-	/** Divide input prescaler clock by 128 */
-	BODVDD_PRESCALE_DIV_128     = SUPC_BODVDD_PSEL(6),
-	/** Divide input prescaler clock by 256 */
-	BODVDD_PRESCALE_DIV_256     = SUPC_BODVDD_PSEL(7),
-	/** Divide input prescaler clock by 512 */
-	BODVDD_PRESCALE_DIV_512     = SUPC_BODVDD_PSEL(8),
-	/** Divide input prescaler clock by 1024 */
-	BODVDD_PRESCALE_DIV_1024    = SUPC_BODVDD_PSEL(9),
-	/** Divide input prescaler clock by 2048 */
-	BODVDD_PRESCALE_DIV_2048    = SUPC_BODVDD_PSEL(10),
-	/** Divide input prescaler clock by 4096 */
-	BODVDD_PRESCALE_DIV_4096    = SUPC_BODVDD_PSEL(11),
-	/** Divide input prescaler clock by 8192 */
-	BODVDD_PRESCALE_DIV_8192    = SUPC_BODVDD_PSEL(12),
-	/** Divide input prescaler clock by 16384 */
-	BODVDD_PRESCALE_DIV_16384   = SUPC_BODVDD_PSEL(13),
-	/** Divide input prescaler clock by 32768 */
-	BODVDD_PRESCALE_DIV_32768   = SUPC_BODVDD_PSEL(14),
-	/** Divide input prescaler clock by 65536 */
-	BODVDD_PRESCALE_DIV_65536   = SUPC_BODVDD_PSEL(15),
+    /** Divide input prescaler clock by 2 */
+    BODVDD_PRESCALE_DIV_2       = SUPC_BODVDD_PSEL(0),
+    /** Divide input prescaler clock by 4 */
+    BODVDD_PRESCALE_DIV_4       = SUPC_BODVDD_PSEL(1),
+    /** Divide input prescaler clock by 8 */
+    BODVDD_PRESCALE_DIV_8       = SUPC_BODVDD_PSEL(2),
+    /** Divide input prescaler clock by 16 */
+    BODVDD_PRESCALE_DIV_16      = SUPC_BODVDD_PSEL(3),
+    /** Divide input prescaler clock by 32 */
+    BODVDD_PRESCALE_DIV_32      = SUPC_BODVDD_PSEL(4),
+    /** Divide input prescaler clock by 64 */
+    BODVDD_PRESCALE_DIV_64      = SUPC_BODVDD_PSEL(5),
+    /** Divide input prescaler clock by 128 */
+    BODVDD_PRESCALE_DIV_128     = SUPC_BODVDD_PSEL(6),
+    /** Divide input prescaler clock by 256 */
+    BODVDD_PRESCALE_DIV_256     = SUPC_BODVDD_PSEL(7),
+    /** Divide input prescaler clock by 512 */
+    BODVDD_PRESCALE_DIV_512     = SUPC_BODVDD_PSEL(8),
+    /** Divide input prescaler clock by 1024 */
+    BODVDD_PRESCALE_DIV_1024    = SUPC_BODVDD_PSEL(9),
+    /** Divide input prescaler clock by 2048 */
+    BODVDD_PRESCALE_DIV_2048    = SUPC_BODVDD_PSEL(10),
+    /** Divide input prescaler clock by 4096 */
+    BODVDD_PRESCALE_DIV_4096    = SUPC_BODVDD_PSEL(11),
+    /** Divide input prescaler clock by 8192 */
+    BODVDD_PRESCALE_DIV_8192    = SUPC_BODVDD_PSEL(12),
+    /** Divide input prescaler clock by 16384 */
+    BODVDD_PRESCALE_DIV_16384   = SUPC_BODVDD_PSEL(13),
+    /** Divide input prescaler clock by 32768 */
+    BODVDD_PRESCALE_DIV_32768   = SUPC_BODVDD_PSEL(14),
+    /** Divide input prescaler clock by 65536 */
+    BODVDD_PRESCALE_DIV_65536   = SUPC_BODVDD_PSEL(15),
 };
 
 /**
@@ -160,10 +160,10 @@ enum bodvdd_prescale {
  * List of possible BODVDD module voltage sampling modes in active sleep mode.
  */
 enum bodvdd_mode_in_active {
-	/** BODVDD will sample the supply line continuously */
-	BODVDD_ACTCFG_CONTINUOUS = 0,
-	/** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
-	BODVDD_ACTCFG_SAMPLED    = SUPC_BODVDD_ACTCFG,
+    /** BODVDD will sample the supply line continuously */
+    BODVDD_ACTCFG_CONTINUOUS = 0,
+    /** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
+    BODVDD_ACTCFG_SAMPLED    = SUPC_BODVDD_ACTCFG,
 };
 
 /**
@@ -172,10 +172,10 @@ enum bodvdd_mode_in_active {
  * List of possible BODVDD module voltage sampling modes in standby sleep mode.
  */
 enum bodvdd_mode_in_standby {
-	/** BODVDD will sample the supply line continuously */
-	BODVDD_STDBYCFG_CONTINUOUS = 0,
-	/** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
-	BODVDD_STDBYCFG_SAMPLED    = SUPC_BODVDD_STDBYCFG,
+    /** BODVDD will sample the supply line continuously */
+    BODVDD_STDBYCFG_CONTINUOUS = 0,
+    /** BODVDD will use the BODVDD sampling clock (1kHz) to sample the supply line */
+    BODVDD_STDBYCFG_SAMPLED    = SUPC_BODVDD_STDBYCFG,
 };
 
 /**
@@ -184,33 +184,33 @@ enum bodvdd_mode_in_standby {
  * List of possible BODVDD actions when a BODVDD module detects a brown-out condition.
  */
 enum bodvdd_action {
-	/** A BODVDD detect will do nothing, and the BODVDD state must be polled */
-	BODVDD_ACTION_NONE      = SUPC_BODVDD_ACTION(0),
-	/** A BODVDD detect will reset the device */
-	BODVDD_ACTION_RESET     = SUPC_BODVDD_ACTION(1),
-	/** A BODVDD detect will fire an interrupt */
-	BODVDD_ACTION_INTERRUPT = SUPC_BODVDD_ACTION(2),
-	/** A BODVDD detect will put the device in backup sleep mode */
-	BODVDD_ACTION_BACKUP    = SUPC_BODVDD_ACTION(3),
+    /** A BODVDD detect will do nothing, and the BODVDD state must be polled */
+    BODVDD_ACTION_NONE      = SUPC_BODVDD_ACTION(0),
+    /** A BODVDD detect will reset the device */
+    BODVDD_ACTION_RESET     = SUPC_BODVDD_ACTION(1),
+    /** A BODVDD detect will fire an interrupt */
+    BODVDD_ACTION_INTERRUPT = SUPC_BODVDD_ACTION(2),
+    /** A BODVDD detect will put the device in backup sleep mode */
+    BODVDD_ACTION_BACKUP    = SUPC_BODVDD_ACTION(3),
 };
 
 /** Configuration structure for a BODVDD module. */
 struct bodvdd_config {
-	/** Input sampler clock prescaler factor, to reduce the 1kHz clock from the
-	 *  ULP32K to lower the sampling rate of the BODVDD */
-	enum bodvdd_prescale prescaler;
-	/** BODVDD configuration in active mode */
-	enum bodvdd_mode_in_active mode_in_active;
-	/** BODVDD configuration in backup sleep mode */
-	enum bodvdd_mode_in_standby mode_in_standby;
-	/** Action to perform when a low power detection is made */
-	enum bodvdd_action action;
-	/** BODVDD level to trigger at when monitors VDD except in backup sleep mode */
-	uint8_t level;
-	/** If \c true, the BODVDD is kept enabled and sampled during standby */
-	bool run_in_standby;
-	/** If \c true, enables detection hysteresis */
-	bool hysteresis;
+    /** Input sampler clock prescaler factor, to reduce the 1kHz clock from the
+     *  ULP32K to lower the sampling rate of the BODVDD */
+    enum bodvdd_prescale prescaler;
+    /** BODVDD configuration in active mode */
+    enum bodvdd_mode_in_active mode_in_active;
+    /** BODVDD configuration in backup sleep mode */
+    enum bodvdd_mode_in_standby mode_in_standby;
+    /** Action to perform when a low power detection is made */
+    enum bodvdd_action action;
+    /** BODVDD level to trigger at when monitors VDD except in backup sleep mode */
+    uint8_t level;
+    /** If \c true, the BODVDD is kept enabled and sampled during standby */
+    bool run_in_standby;
+    /** If \c true, enables detection hysteresis */
+    bool hysteresis;
 };
 
 /**
@@ -233,22 +233,22 @@ struct bodvdd_config {
  * \param[out] conf  BODVDD configuration struct to set to default settings
  */
 static inline void bodvdd_get_config_defaults(
-		struct bodvdd_config *const conf)
+        struct bodvdd_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	conf->prescaler       = BODVDD_PRESCALE_DIV_2;
-	conf->mode_in_active  = BODVDD_ACTCFG_CONTINUOUS;
-	conf->mode_in_standby = BODVDD_STDBYCFG_CONTINUOUS;
-	conf->action          = BODVDD_ACTION_RESET;
-	conf->level           = 0x2A;
-	conf->run_in_standby  = true;
-	conf->hysteresis      = true;
+    conf->prescaler       = BODVDD_PRESCALE_DIV_2;
+    conf->mode_in_active  = BODVDD_ACTCFG_CONTINUOUS;
+    conf->mode_in_standby = BODVDD_STDBYCFG_CONTINUOUS;
+    conf->action          = BODVDD_ACTION_RESET;
+    conf->level           = 0x2A;
+    conf->run_in_standby  = true;
+    conf->hysteresis      = true;
 }
 
 enum status_code bodvdd_set_config(
-		struct bodvdd_config *const conf);
+        struct bodvdd_config *const conf);
 
 /**
  * \brief Enables a configured BODVDD module.
@@ -261,12 +261,13 @@ enum status_code bodvdd_set_config(
  */
 static inline enum status_code bodvdd_enable(void)
 {
-	SUPC->BODVDD.reg |= SUPC_BODVDD_ENABLE;
-	while (!(SUPC->STATUS.reg & SUPC_STATUS_BVDDSRDY)) {
-		/* Wait for BODVDD register sync ready */
-	}
+    SUPC->BODVDD.reg |= SUPC_BODVDD_ENABLE;
+    while (!(SUPC->STATUS.reg & SUPC_STATUS_BVDDSRDY))
+    {
+        /* Wait for BODVDD register sync ready */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -280,10 +281,10 @@ static inline enum status_code bodvdd_enable(void)
  */
 static inline enum status_code bodvdd_disable(void)
 {
-	SUPC->INTENCLR.reg = SUPC_INTENCLR_BODVDDRDY | SUPC_INTENCLR_BODVDDDET | SUPC_INTENCLR_BVDDSRDY;
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY | SUPC_INTFLAG_BODVDDDET | SUPC_INTFLAG_BVDDSRDY;
-	SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
-	return STATUS_OK;
+    SUPC->INTENCLR.reg = SUPC_INTENCLR_BODVDDRDY | SUPC_INTENCLR_BODVDDDET | SUPC_INTENCLR_BVDDSRDY;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDRDY | SUPC_INTFLAG_BODVDDDET | SUPC_INTFLAG_BVDDSRDY;
+    SUPC->BODVDD.reg &= ~SUPC_BODVDD_ENABLE;
+    return STATUS_OK;
 }
 
 /**
@@ -299,7 +300,7 @@ static inline enum status_code bodvdd_disable(void)
  */
 static inline bool bodvdd_is_detected(void)
 {
-	return SUPC->STATUS.bit.BODVDDDET;
+    return SUPC->STATUS.bit.BODVDDDET;
 }
 
 /**
@@ -311,8 +312,8 @@ static inline bool bodvdd_is_detected(void)
  */
 static inline void bodvdd_clear_detected(void)
 {
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET;
-	return;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BODVDDDET;
+    return;
 }
 
 
@@ -358,12 +359,12 @@ static inline void bodvdd_clear_detected(void)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -393,16 +394,16 @@ static inline void bodvdd_clear_detected(void)
  * \page asfdoc_sam0_bod_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42701A</td>
- *		<td>07/2016</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42701A</td>
+ *      <td>07/2016</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c
index 1c1fa1188a3a..1ddf6f44b01d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod.c
@@ -59,51 +59,58 @@
  * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
  */
 enum status_code bod_set_config(
-		const enum bod bod_id,
-		struct bod_config *const conf)
+        const enum bod bod_id,
+        struct bod_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	uint32_t temp = 0;
+    uint32_t temp = 0;
 
-	/* Check if module is enabled. */
-	if (SYSCTRL->BOD33.reg & SYSCTRL_BOD33_ENABLE) {
-		SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
-	}
+    /* Check if module is enabled. */
+    if (SYSCTRL->BOD33.reg & SYSCTRL_BOD33_ENABLE)
+    {
+        SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
+    }
 
-	/* Convert BOD prescaler, trigger action and mode to a bitmask */
-	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
-			(uint32_t)conf->mode;
+    /* Convert BOD prescaler, trigger action and mode to a bitmask */
+    temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+            (uint32_t)conf->mode;
 
-	if (conf->mode == BOD_MODE_SAMPLED) {
-		/* Enable sampling clock if sampled mode */
-		temp |= SYSCTRL_BOD33_CEN;
-	}
+    if (conf->mode == BOD_MODE_SAMPLED)
+    {
+        /* Enable sampling clock if sampled mode */
+        temp |= SYSCTRL_BOD33_CEN;
+    }
 
-	if (conf->hysteresis == true) {
-		temp |= SYSCTRL_BOD33_HYST;
-	}
+    if (conf->hysteresis == true)
+    {
+        temp |= SYSCTRL_BOD33_HYST;
+    }
 
-	if (conf->run_in_standby == true) {
-		temp |= SYSCTRL_BOD33_RUNSTDBY;
-	}
+    if (conf->run_in_standby == true)
+    {
+        temp |= SYSCTRL_BOD33_RUNSTDBY;
+    }
 
-	switch (bod_id) {
-		case BOD_BOD33:
-			if (conf->level > 0x3F) {
-				return STATUS_ERR_INVALID_ARG;
-			}
+    switch (bod_id)
+    {
+        case BOD_BOD33:
+            if (conf->level > 0x3F)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
 
-			SYSCTRL->BOD33.reg = SYSCTRL_BOD33_LEVEL(conf->level) | temp;
+            SYSCTRL->BOD33.reg = SYSCTRL_BOD33_LEVEL(conf->level) | temp;
 
-			while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY)) {
-				/* Wait for BOD33 register sync ready */
-			}
-			break;
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
+            while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY))
+            {
+                /* Wait for BOD33 register sync ready */
+            }
+            break;
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h
index d8cbb078ea96..6df3411e79d7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_d_r_h/bod_feature.h
@@ -86,7 +86,7 @@ extern "C" {
  *
  * The SAM devices contain a number of Brown Out Detector (BOD) modules.
  * Each BOD monitors the supply voltage for any dips that go below the set
- * threshold for the module. In case of a BOD detection the BOD will either 
+ * threshold for the module. In case of a BOD detection the BOD will either
  * reset the system or raise a hardware interrupt so that a safe power-down
  * sequence can be attempted.
  *
@@ -123,8 +123,8 @@ extern "C" {
  * List of possible BOD controllers within the device.
  */
 enum bod {
-	/** BOD33 External I/O voltage */
-	BOD_BOD33,
+    /** BOD33 External I/O voltage */
+    BOD_BOD33,
 };
 
 /**
@@ -134,38 +134,38 @@ enum bod {
  * speed of a BOD to lower the power consumption.
  */
 enum bod_prescale {
-	/** Divide input prescaler clock by 2 */
-	BOD_PRESCALE_DIV_2       = SYSCTRL_BOD33_PSEL(0),
-	/** Divide input prescaler clock by 4 */
-	BOD_PRESCALE_DIV_4       = SYSCTRL_BOD33_PSEL(1),
-	/** Divide input prescaler clock by 8 */
-	BOD_PRESCALE_DIV_8       = SYSCTRL_BOD33_PSEL(2),
-	/** Divide input prescaler clock by 16 */
-	BOD_PRESCALE_DIV_16      = SYSCTRL_BOD33_PSEL(3),
-	/** Divide input prescaler clock by 32*/
-	BOD_PRESCALE_DIV_32      = SYSCTRL_BOD33_PSEL(4),
-	/** Divide input prescaler clock by 64 */
-	BOD_PRESCALE_DIV_64      = SYSCTRL_BOD33_PSEL(5),
-	/** Divide input prescaler clock by 128 */
-	BOD_PRESCALE_DIV_128     = SYSCTRL_BOD33_PSEL(6),
-	/** Divide input prescaler clock by 256 */
-	BOD_PRESCALE_DIV_256     = SYSCTRL_BOD33_PSEL(7),
-	/** Divide input prescaler clock by 512 */
-	BOD_PRESCALE_DIV_512     = SYSCTRL_BOD33_PSEL(8),
-	/** Divide input prescaler clock by 1024 */
-	BOD_PRESCALE_DIV_1024    = SYSCTRL_BOD33_PSEL(9),
-	/** Divide input prescaler clock by 2048 */
-	BOD_PRESCALE_DIV_2048    = SYSCTRL_BOD33_PSEL(10),
-	/** Divide input prescaler clock by 4096 */
-	BOD_PRESCALE_DIV_4096    = SYSCTRL_BOD33_PSEL(11),
-	/** Divide input prescaler clock by 8192 */
-	BOD_PRESCALE_DIV_8192    = SYSCTRL_BOD33_PSEL(12),
-	/** Divide input prescaler clock by 16384 */
-	BOD_PRESCALE_DIV_16384   = SYSCTRL_BOD33_PSEL(13),
-	/** Divide input prescaler clock by 32768 */
-	BOD_PRESCALE_DIV_32768   = SYSCTRL_BOD33_PSEL(14),
-	/** Divide input prescaler clock by 65536 */
-	BOD_PRESCALE_DIV_65536   = SYSCTRL_BOD33_PSEL(15),
+    /** Divide input prescaler clock by 2 */
+    BOD_PRESCALE_DIV_2       = SYSCTRL_BOD33_PSEL(0),
+    /** Divide input prescaler clock by 4 */
+    BOD_PRESCALE_DIV_4       = SYSCTRL_BOD33_PSEL(1),
+    /** Divide input prescaler clock by 8 */
+    BOD_PRESCALE_DIV_8       = SYSCTRL_BOD33_PSEL(2),
+    /** Divide input prescaler clock by 16 */
+    BOD_PRESCALE_DIV_16      = SYSCTRL_BOD33_PSEL(3),
+    /** Divide input prescaler clock by 32*/
+    BOD_PRESCALE_DIV_32      = SYSCTRL_BOD33_PSEL(4),
+    /** Divide input prescaler clock by 64 */
+    BOD_PRESCALE_DIV_64      = SYSCTRL_BOD33_PSEL(5),
+    /** Divide input prescaler clock by 128 */
+    BOD_PRESCALE_DIV_128     = SYSCTRL_BOD33_PSEL(6),
+    /** Divide input prescaler clock by 256 */
+    BOD_PRESCALE_DIV_256     = SYSCTRL_BOD33_PSEL(7),
+    /** Divide input prescaler clock by 512 */
+    BOD_PRESCALE_DIV_512     = SYSCTRL_BOD33_PSEL(8),
+    /** Divide input prescaler clock by 1024 */
+    BOD_PRESCALE_DIV_1024    = SYSCTRL_BOD33_PSEL(9),
+    /** Divide input prescaler clock by 2048 */
+    BOD_PRESCALE_DIV_2048    = SYSCTRL_BOD33_PSEL(10),
+    /** Divide input prescaler clock by 4096 */
+    BOD_PRESCALE_DIV_4096    = SYSCTRL_BOD33_PSEL(11),
+    /** Divide input prescaler clock by 8192 */
+    BOD_PRESCALE_DIV_8192    = SYSCTRL_BOD33_PSEL(12),
+    /** Divide input prescaler clock by 16384 */
+    BOD_PRESCALE_DIV_16384   = SYSCTRL_BOD33_PSEL(13),
+    /** Divide input prescaler clock by 32768 */
+    BOD_PRESCALE_DIV_32768   = SYSCTRL_BOD33_PSEL(14),
+    /** Divide input prescaler clock by 65536 */
+    BOD_PRESCALE_DIV_65536   = SYSCTRL_BOD33_PSEL(15),
 };
 
 /**
@@ -174,12 +174,12 @@ enum bod_prescale {
  * List of possible BOD actions when a BOD module detects a brown out condition.
  */
 enum bod_action {
-	/** A BOD detect will do nothing, and the BOD state can't be polled */
-	BOD_ACTION_NONE      = SYSCTRL_BOD33_ACTION(0),
-	/** A BOD detect will reset the device */
-	BOD_ACTION_RESET     = SYSCTRL_BOD33_ACTION(1),
-	/** A BOD detect will fire an interrupt */
-	BOD_ACTION_INTERRUPT = SYSCTRL_BOD33_ACTION(2),
+    /** A BOD detect will do nothing, and the BOD state can't be polled */
+    BOD_ACTION_NONE      = SYSCTRL_BOD33_ACTION(0),
+    /** A BOD detect will reset the device */
+    BOD_ACTION_RESET     = SYSCTRL_BOD33_ACTION(1),
+    /** A BOD detect will fire an interrupt */
+    BOD_ACTION_INTERRUPT = SYSCTRL_BOD33_ACTION(2),
 };
 
 /**
@@ -188,27 +188,27 @@ enum bod_action {
  * List of possible BOD module voltage sampling modes.
  */
 enum bod_mode {
-	/** BOD will sample the supply line continuously */
-	BOD_MODE_CONTINUOUS  = 0,
-	/** BOD will use the BOD sampling clock (1KHz) to sample the supply line */
-	BOD_MODE_SAMPLED     = SYSCTRL_BOD33_MODE,
+    /** BOD will sample the supply line continuously */
+    BOD_MODE_CONTINUOUS  = 0,
+    /** BOD will use the BOD sampling clock (1KHz) to sample the supply line */
+    BOD_MODE_SAMPLED     = SYSCTRL_BOD33_MODE,
 };
 
 /** Configuration structure for a BOD module. */
 struct bod_config {
-	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
-	 *  ULP32K to lower the sampling rate of the BOD */
-	enum bod_prescale prescaler;
-	/** Sampling configuration mode for the BOD */
-	enum bod_mode mode;
-	/** Action to perform when a low power detection is made */
-	enum bod_action action;
-	/** BOD level to trigger at (see electrical section of device datasheet) */
-	uint8_t level;
-	/** If \c true, enables detection hysteresis */
-	bool hysteresis;
-	/** If \c true, the BOD is kept enabled and sampled during device sleep */
-	bool run_in_standby;
+    /** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+     *  ULP32K to lower the sampling rate of the BOD */
+    enum bod_prescale prescaler;
+    /** Sampling configuration mode for the BOD */
+    enum bod_mode mode;
+    /** Action to perform when a low power detection is made */
+    enum bod_action action;
+    /** BOD level to trigger at (see electrical section of device datasheet) */
+    uint8_t level;
+    /** If \c true, enables detection hysteresis */
+    bool hysteresis;
+    /** If \c true, the BOD is kept enabled and sampled during device sleep */
+    bool run_in_standby;
 };
 
 /**
@@ -230,22 +230,22 @@ struct bod_config {
  * \param[out] conf  BOD configuration struct to set to default settings
  */
 static inline void bod_get_config_defaults(
-		struct bod_config *const conf)
+        struct bod_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	conf->prescaler      = BOD_PRESCALE_DIV_2;
-	conf->mode           = BOD_MODE_CONTINUOUS;
-	conf->action         = BOD_ACTION_RESET;
-	conf->level          = 0x27;
-	conf->hysteresis     = true;
-	conf->run_in_standby = true;
+    conf->prescaler      = BOD_PRESCALE_DIV_2;
+    conf->mode           = BOD_MODE_CONTINUOUS;
+    conf->action         = BOD_ACTION_RESET;
+    conf->level          = 0x27;
+    conf->hysteresis     = true;
+    conf->run_in_standby = true;
 }
 
 enum status_code bod_set_config(
-		const enum bod bod_id,
-		struct bod_config *const conf);
+        const enum bod bod_id,
+        struct bod_config *const conf);
 
 /**
  * \brief Enables a configured BOD module.
@@ -260,18 +260,19 @@ enum status_code bod_set_config(
  * \retval STATUS_ERR_INVALID_ARG  An invalid BOD was supplied
  */
 static inline enum status_code bod_enable(
-		const enum bod bod_id)
+        const enum bod bod_id)
 {
-	switch (bod_id) {
-		case BOD_BOD33:
-			SYSCTRL->BOD33.reg |= SYSCTRL_BOD33_ENABLE;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+    switch (bod_id)
+    {
+        case BOD_BOD33:
+            SYSCTRL->BOD33.reg |= SYSCTRL_BOD33_ENABLE;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -287,20 +288,21 @@ static inline enum status_code bod_enable(
  * \retval STATUS_ERR_INVALID_ARG  An invalid BOD was supplied
  */
 static inline enum status_code bod_disable(
-		const enum bod bod_id)
+        const enum bod bod_id)
 {
-	switch (bod_id) {
-		case BOD_BOD33:
-			SYSCTRL->INTENCLR.reg = SYSCTRL_INTENCLR_BOD33RDY | SYSCTRL_INTENCLR_BOD33DET | SYSCTRL_INTENCLR_B33SRDY;
-			SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | SYSCTRL_INTFLAG_B33SRDY;
-			SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+    switch (bod_id)
+    {
+        case BOD_BOD33:
+            SYSCTRL->INTENCLR.reg = SYSCTRL_INTENCLR_BOD33RDY | SYSCTRL_INTENCLR_BOD33DET | SYSCTRL_INTENCLR_B33SRDY;
+            SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | SYSCTRL_INTFLAG_B33SRDY;
+            SYSCTRL->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -317,15 +319,16 @@ static inline enum status_code bod_disable(
  * \retval false  If the BOD has not detected a low voltage condition
  */
 static inline bool bod_is_detected(
-		const enum bod bod_id)
+        const enum bod bod_id)
 {
-	switch (bod_id) {
-		case BOD_BOD33:
-			return SYSCTRL->INTFLAG.bit.BOD33DET;
-		default:
-			Assert(false);
-			return false;
-	}
+    switch (bod_id)
+    {
+        case BOD_BOD33:
+            return SYSCTRL->INTFLAG.bit.BOD33DET;
+        default:
+            Assert(false);
+            return false;
+    }
 }
 
 /**
@@ -337,16 +340,17 @@ static inline bool bod_is_detected(
  * \param[in] bod_id  BOD module to clear
  */
 static inline void bod_clear_detected(
-		const enum bod bod_id)
+        const enum bod bod_id)
 {
-	switch (bod_id) {
-		case BOD_BOD33:
-			SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET;
-			return;
-		default:
-			Assert(false);
-			return;
-	}
+    switch (bod_id)
+    {
+        case BOD_BOD33:
+            SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET;
+            return;
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /** @} */
@@ -392,15 +396,15 @@ static inline void bod_clear_detected(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Removed BOD12 reference</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Removed BOD12 reference</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -430,36 +434,36 @@ static inline void bod_clear_detected(
  * \page asfdoc_sam0_bod_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42149E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42149D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21, and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42149C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42149B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42149A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42149E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42149D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21, and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42149C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42149B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42149A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c
index 97bdaa6dff60..b4de93e7a11d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod.c
@@ -58,42 +58,47 @@
  * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
  */
 enum status_code bod33_set_config(
-		struct bod33_config *const conf)
+        struct bod33_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	uint32_t temp = 0;
+    uint32_t temp = 0;
 
-	/* Check if module is enabled. */
-	if (SUPC->BOD33.reg & SUPC_BOD33_ENABLE) {
-		SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
-	}
+    /* Check if module is enabled. */
+    if (SUPC->BOD33.reg & SUPC_BOD33_ENABLE)
+    {
+        SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+    }
 
-	/* Convert BOD prescaler, trigger action and mode to a bitmask */
-	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action | (uint32_t)conf->monitor |
-			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+    /* Convert BOD prescaler, trigger action and mode to a bitmask */
+    temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action | (uint32_t)conf->monitor |
+            (uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
 
-	if (conf->hysteresis == true) {
-		temp |= SUPC_BOD33_HYST;
-	}
+    if (conf->hysteresis == true)
+    {
+        temp |= SUPC_BOD33_HYST;
+    }
 
-	if (conf->run_in_standby == true) {
-		temp |= SUPC_BOD33_RUNSTDBY;
-	}
+    if (conf->run_in_standby == true)
+    {
+        temp |= SUPC_BOD33_RUNSTDBY;
+    }
 
-	if (conf->run_in_backup == true) {
-		temp |= SUPC_BOD33_RUNBKUP;
-	}
+    if (conf->run_in_backup == true)
+    {
+        temp |= SUPC_BOD33_RUNBKUP;
+    }
 
-	if (conf->level > 0x3F || conf->backuplevel > 0x3F) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (conf->level > 0x3F || conf->backuplevel > 0x3F)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	SUPC->BOD33.reg = SUPC_BOD33_LEVEL(conf->level) |
-			SUPC_BOD33_BKUPLEVEL(conf->backuplevel) | temp;
+    SUPC->BOD33.reg = SUPC_BOD33_LEVEL(conf->level) |
+            SUPC_BOD33_BKUPLEVEL(conf->backuplevel) | temp;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -109,35 +114,39 @@ enum status_code bod33_set_config(
  * \retval STATUS_ERR_INVALID_OPTION  The requested BOD level was outside the acceptable range
  */
 enum status_code bod12_set_config(
-		struct bod12_config *const conf)
+        struct bod12_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
+    /* Sanity check arguments */
+    Assert(conf);
 
-	uint32_t temp = 0;
+    uint32_t temp = 0;
 
-	/* Check if module is enabled. */
-	if (SUPC->BOD12.reg & SUPC_BOD12_ENABLE) {
-		SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
-	}
+    /* Check if module is enabled. */
+    if (SUPC->BOD12.reg & SUPC_BOD12_ENABLE)
+    {
+        SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+    }
 
 /* Convert BOD prescaler, trigger action and mode to a bitmask */
-	temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
-			(uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
+    temp |= (uint32_t)conf->prescaler | (uint32_t)conf->action |
+            (uint32_t)conf->mode_in_active | (uint32_t)conf->mode_in_standby;
 
-	if (conf->hysteresis == true) {
-		temp |= SUPC_BOD12_HYST;
-	}
+    if (conf->hysteresis == true)
+    {
+        temp |= SUPC_BOD12_HYST;
+    }
 
-	if (conf->run_in_standby == true) {
-		temp |= SUPC_BOD12_RUNSTDBY;
-	}
+    if (conf->run_in_standby == true)
+    {
+        temp |= SUPC_BOD12_RUNSTDBY;
+    }
 
-	if (conf->level > 0x3F) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (conf->level > 0x3F)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	SUPC->BOD12.reg = SUPC_BOD12_LEVEL(conf->level) | temp;
+    SUPC->BOD12.reg = SUPC_BOD12_LEVEL(conf->level) | temp;
 
-	return STATUS_OK;
-}
\ No newline at end of file
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h
index ae191464e750..de981b91f49d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/bod/bod_sam_l/bod_feature.h
@@ -120,38 +120,38 @@ extern "C" {
  * speed of a BOD33 to lower the power consumption.
  */
 enum bod33_prescale {
-	/** Divide input prescaler clock by 2 */
-	BOD33_PRESCALE_DIV_2       = SUPC_BOD33_PSEL(0),
-	/** Divide input prescaler clock by 4 */
-	BOD33_PRESCALE_DIV_4       = SUPC_BOD33_PSEL(1),
-	/** Divide input prescaler clock by 8 */
-	BOD33_PRESCALE_DIV_8       = SUPC_BOD33_PSEL(2),
-	/** Divide input prescaler clock by 16 */
-	BOD33_PRESCALE_DIV_16      = SUPC_BOD33_PSEL(3),
-	/** Divide input prescaler clock by 32 */
-	BOD33_PRESCALE_DIV_32      = SUPC_BOD33_PSEL(4),
-	/** Divide input prescaler clock by 64 */
-	BOD33_PRESCALE_DIV_64      = SUPC_BOD33_PSEL(5),
-	/** Divide input prescaler clock by 128 */
-	BOD33_PRESCALE_DIV_128     = SUPC_BOD33_PSEL(6),
-	/** Divide input prescaler clock by 256 */
-	BOD33_PRESCALE_DIV_256     = SUPC_BOD33_PSEL(7),
-	/** Divide input prescaler clock by 512 */
-	BOD33_PRESCALE_DIV_512     = SUPC_BOD33_PSEL(8),
-	/** Divide input prescaler clock by 1024 */
-	BOD33_PRESCALE_DIV_1024    = SUPC_BOD33_PSEL(9),
-	/** Divide input prescaler clock by 2048 */
-	BOD33_PRESCALE_DIV_2048    = SUPC_BOD33_PSEL(10),
-	/** Divide input prescaler clock by 4096 */
-	BOD33_PRESCALE_DIV_4096    = SUPC_BOD33_PSEL(11),
-	/** Divide input prescaler clock by 8192 */
-	BOD33_PRESCALE_DIV_8192    = SUPC_BOD33_PSEL(12),
-	/** Divide input prescaler clock by 16384 */
-	BOD33_PRESCALE_DIV_16384   = SUPC_BOD33_PSEL(13),
-	/** Divide input prescaler clock by 32768 */
-	BOD33_PRESCALE_DIV_32768   = SUPC_BOD33_PSEL(14),
-	/** Divide input prescaler clock by 65536 */
-	BOD33_PRESCALE_DIV_65536   = SUPC_BOD33_PSEL(15),
+    /** Divide input prescaler clock by 2 */
+    BOD33_PRESCALE_DIV_2       = SUPC_BOD33_PSEL(0),
+    /** Divide input prescaler clock by 4 */
+    BOD33_PRESCALE_DIV_4       = SUPC_BOD33_PSEL(1),
+    /** Divide input prescaler clock by 8 */
+    BOD33_PRESCALE_DIV_8       = SUPC_BOD33_PSEL(2),
+    /** Divide input prescaler clock by 16 */
+    BOD33_PRESCALE_DIV_16      = SUPC_BOD33_PSEL(3),
+    /** Divide input prescaler clock by 32 */
+    BOD33_PRESCALE_DIV_32      = SUPC_BOD33_PSEL(4),
+    /** Divide input prescaler clock by 64 */
+    BOD33_PRESCALE_DIV_64      = SUPC_BOD33_PSEL(5),
+    /** Divide input prescaler clock by 128 */
+    BOD33_PRESCALE_DIV_128     = SUPC_BOD33_PSEL(6),
+    /** Divide input prescaler clock by 256 */
+    BOD33_PRESCALE_DIV_256     = SUPC_BOD33_PSEL(7),
+    /** Divide input prescaler clock by 512 */
+    BOD33_PRESCALE_DIV_512     = SUPC_BOD33_PSEL(8),
+    /** Divide input prescaler clock by 1024 */
+    BOD33_PRESCALE_DIV_1024    = SUPC_BOD33_PSEL(9),
+    /** Divide input prescaler clock by 2048 */
+    BOD33_PRESCALE_DIV_2048    = SUPC_BOD33_PSEL(10),
+    /** Divide input prescaler clock by 4096 */
+    BOD33_PRESCALE_DIV_4096    = SUPC_BOD33_PSEL(11),
+    /** Divide input prescaler clock by 8192 */
+    BOD33_PRESCALE_DIV_8192    = SUPC_BOD33_PSEL(12),
+    /** Divide input prescaler clock by 16384 */
+    BOD33_PRESCALE_DIV_16384   = SUPC_BOD33_PSEL(13),
+    /** Divide input prescaler clock by 32768 */
+    BOD33_PRESCALE_DIV_32768   = SUPC_BOD33_PSEL(14),
+    /** Divide input prescaler clock by 65536 */
+    BOD33_PRESCALE_DIV_65536   = SUPC_BOD33_PSEL(15),
 };
 
 /**
@@ -160,10 +160,10 @@ enum bod33_prescale {
  * List of possible BOD33 module voltage monitored in active and standby mode.
  */
 enum bod33_vol_monitor {
-	/** The BOD33 monitors the VDD power pin in active and standby mode */
-	BOD33_VMON_VDD  = 0,
-	/** The BOD33 monitors the VBAT power pin in active and standby mode */
-	BOD33_VMON_VBAT = SUPC_BOD33_VMON,
+    /** The BOD33 monitors the VDD power pin in active and standby mode */
+    BOD33_VMON_VDD  = 0,
+    /** The BOD33 monitors the VBAT power pin in active and standby mode */
+    BOD33_VMON_VBAT = SUPC_BOD33_VMON,
 };
 
 /**
@@ -172,10 +172,10 @@ enum bod33_vol_monitor {
  * List of possible BOD33 module voltage sampling modes in active sleep mode.
  */
 enum bod33_mode_in_active {
-	/** BOD33 will sample the supply line continuously */
-	BOD33_ACTCFG_CONTINUOUS = 0,
-	/** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
-	BOD33_ACTCFG_SAMPLED    = SUPC_BOD33_ACTCFG,
+    /** BOD33 will sample the supply line continuously */
+    BOD33_ACTCFG_CONTINUOUS = 0,
+    /** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
+    BOD33_ACTCFG_SAMPLED    = SUPC_BOD33_ACTCFG,
 };
 
 /**
@@ -184,10 +184,10 @@ enum bod33_mode_in_active {
  * List of possible BOD33 module voltage sampling modes in standby sleep mode.
  */
 enum bod33_mode_in_standby {
-	/** BOD33 will sample the supply line continuously */
-	BOD33_STDBYCFG_CONTINUOUS = 0,
-	/** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
-	BOD33_STDBYCFG_SAMPLED    = SUPC_BOD33_STDBYCFG,
+    /** BOD33 will sample the supply line continuously */
+    BOD33_STDBYCFG_CONTINUOUS = 0,
+    /** BOD33 will use the BOD33 sampling clock (1KHz) to sample the supply line */
+    BOD33_STDBYCFG_SAMPLED    = SUPC_BOD33_STDBYCFG,
 };
 
 /**
@@ -196,39 +196,39 @@ enum bod33_mode_in_standby {
  * List of possible BOD33 actions when a BOD33 module detects a brown-out condition.
  */
 enum bod33_action {
-	/** A BOD33 detect will do nothing, and the BOD33 state must be polled */
-	BOD33_ACTION_NONE      = SUPC_BOD33_ACTION(0),
-	/** A BOD33 detect will reset the device */
-	BOD33_ACTION_RESET     = SUPC_BOD33_ACTION(1),
-	/** A BOD33 detect will fire an interrupt */
-	BOD33_ACTION_INTERRUPT = SUPC_BOD33_ACTION(2),
-	/** A BOD33 detect will put the device in backup sleep mode */
-	BOD33_ACTION_BACKUP    = SUPC_BOD33_ACTION(3),
+    /** A BOD33 detect will do nothing, and the BOD33 state must be polled */
+    BOD33_ACTION_NONE      = SUPC_BOD33_ACTION(0),
+    /** A BOD33 detect will reset the device */
+    BOD33_ACTION_RESET     = SUPC_BOD33_ACTION(1),
+    /** A BOD33 detect will fire an interrupt */
+    BOD33_ACTION_INTERRUPT = SUPC_BOD33_ACTION(2),
+    /** A BOD33 detect will put the device in backup sleep mode */
+    BOD33_ACTION_BACKUP    = SUPC_BOD33_ACTION(3),
 };
 
 /** Configuration structure for a BOD33 module. */
 struct bod33_config {
-	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
-	 *  ULP32K to lower the sampling rate of the BOD33 */
-	enum bod33_prescale prescaler;
-	/** Voltage monitored in active and standby mode */
-	enum bod33_vol_monitor monitor;
-	/** BOD33 configuration in active mode */
-	enum bod33_mode_in_active mode_in_active;
-	/** BOD33 configuration in backup sleep mode */
-	enum bod33_mode_in_standby mode_in_standby;
-	/** Action to perform when a low power detection is made */
-	enum bod33_action action;
-	/** BOD33 level to trigger at when monitors VBAT or in backup sleep mode */
-	uint8_t backuplevel;
-	/** BOD33 level to trigger at when monitors VDD excpt in backup sleep mode */
-	uint8_t level;
-	/** If \c true, the BOD33 is kept enabled and sampled during device sleep */
-	bool run_in_backup;
-	/** If \c true, the BOD33 is kept enabled and sampled during standby */
-	bool run_in_standby;
-	/** If \c true, enables detection hysteresis */
-	bool hysteresis;
+    /** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+     *  ULP32K to lower the sampling rate of the BOD33 */
+    enum bod33_prescale prescaler;
+    /** Voltage monitored in active and standby mode */
+    enum bod33_vol_monitor monitor;
+    /** BOD33 configuration in active mode */
+    enum bod33_mode_in_active mode_in_active;
+    /** BOD33 configuration in backup sleep mode */
+    enum bod33_mode_in_standby mode_in_standby;
+    /** Action to perform when a low power detection is made */
+    enum bod33_action action;
+    /** BOD33 level to trigger at when monitors VBAT or in backup sleep mode */
+    uint8_t backuplevel;
+    /** BOD33 level to trigger at when monitors VDD excpt in backup sleep mode */
+    uint8_t level;
+    /** If \c true, the BOD33 is kept enabled and sampled during device sleep */
+    bool run_in_backup;
+    /** If \c true, the BOD33 is kept enabled and sampled during standby */
+    bool run_in_standby;
+    /** If \c true, enables detection hysteresis */
+    bool hysteresis;
 };
 
 
@@ -239,38 +239,38 @@ struct bod33_config {
  * speed of a BOD12 to lower the power consumption.
  */
 enum bod12_prescale {
-	/** Divide input prescaler clock by 2 */
-	BOD12_PRESCALE_DIV_2       = SUPC_BOD12_PSEL(0),
-	/** Divide input prescaler clock by 4 */
-	BOD12_PRESCALE_DIV_4       = SUPC_BOD12_PSEL(1),
-	/** Divide input prescaler clock by 8 */
-	BOD12_PRESCALE_DIV_8       = SUPC_BOD12_PSEL(2),
-	/** Divide input prescaler clock by 16 */
-	BOD12_PRESCALE_DIV_16      = SUPC_BOD12_PSEL(3),
-	/** Divide input prescaler clock by 32 */
-	BOD12_PRESCALE_DIV_32      = SUPC_BOD12_PSEL(4),
-	/** Divide input prescaler clock by 64 */
-	BOD12_PRESCALE_DIV_64      = SUPC_BOD12_PSEL(5),
-	/** Divide input prescaler clock by 128 */
-	BOD12_PRESCALE_DIV_128     = SUPC_BOD12_PSEL(6),
-	/** Divide input prescaler clock by 256 */
-	BOD12_PRESCALE_DIV_256     = SUPC_BOD12_PSEL(7),
-	/** Divide input prescaler clock by 512 */
-	BOD12_PRESCALE_DIV_512     = SUPC_BOD12_PSEL(8),
-	/** Divide input prescaler clock by 1024 */
-	BOD12_PRESCALE_DIV_1024    = SUPC_BOD12_PSEL(9),
-	/** Divide input prescaler clock by 2048 */
-	BOD12_PRESCALE_DIV_2048    = SUPC_BOD12_PSEL(10),
-	/** Divide input prescaler clock by 4096 */
-	BOD12_PRESCALE_DIV_4096    = SUPC_BOD12_PSEL(11),
-	/** Divide input prescaler clock by 8192 */
-	BOD12_PRESCALE_DIV_8192    = SUPC_BOD12_PSEL(12),
-	/** Divide input prescaler clock by 16384 */
-	BOD12_PRESCALE_DIV_16384   = SUPC_BOD12_PSEL(13),
-	/** Divide input prescaler clock by 32768 */
-	BOD12_PRESCALE_DIV_32768   = SUPC_BOD12_PSEL(14),
-	/** Divide input prescaler clock by 65536 */
-	BOD12_PRESCALE_DIV_65536   = SUPC_BOD12_PSEL(15),
+    /** Divide input prescaler clock by 2 */
+    BOD12_PRESCALE_DIV_2       = SUPC_BOD12_PSEL(0),
+    /** Divide input prescaler clock by 4 */
+    BOD12_PRESCALE_DIV_4       = SUPC_BOD12_PSEL(1),
+    /** Divide input prescaler clock by 8 */
+    BOD12_PRESCALE_DIV_8       = SUPC_BOD12_PSEL(2),
+    /** Divide input prescaler clock by 16 */
+    BOD12_PRESCALE_DIV_16      = SUPC_BOD12_PSEL(3),
+    /** Divide input prescaler clock by 32 */
+    BOD12_PRESCALE_DIV_32      = SUPC_BOD12_PSEL(4),
+    /** Divide input prescaler clock by 64 */
+    BOD12_PRESCALE_DIV_64      = SUPC_BOD12_PSEL(5),
+    /** Divide input prescaler clock by 128 */
+    BOD12_PRESCALE_DIV_128     = SUPC_BOD12_PSEL(6),
+    /** Divide input prescaler clock by 256 */
+    BOD12_PRESCALE_DIV_256     = SUPC_BOD12_PSEL(7),
+    /** Divide input prescaler clock by 512 */
+    BOD12_PRESCALE_DIV_512     = SUPC_BOD12_PSEL(8),
+    /** Divide input prescaler clock by 1024 */
+    BOD12_PRESCALE_DIV_1024    = SUPC_BOD12_PSEL(9),
+    /** Divide input prescaler clock by 2048 */
+    BOD12_PRESCALE_DIV_2048    = SUPC_BOD12_PSEL(10),
+    /** Divide input prescaler clock by 4096 */
+    BOD12_PRESCALE_DIV_4096    = SUPC_BOD12_PSEL(11),
+    /** Divide input prescaler clock by 8192 */
+    BOD12_PRESCALE_DIV_8192    = SUPC_BOD12_PSEL(12),
+    /** Divide input prescaler clock by 16384 */
+    BOD12_PRESCALE_DIV_16384   = SUPC_BOD12_PSEL(13),
+    /** Divide input prescaler clock by 32768 */
+    BOD12_PRESCALE_DIV_32768   = SUPC_BOD12_PSEL(14),
+    /** Divide input prescaler clock by 65536 */
+    BOD12_PRESCALE_DIV_65536   = SUPC_BOD12_PSEL(15),
 };
 
 /**
@@ -279,10 +279,10 @@ enum bod12_prescale {
  * List of possible BOD12 module voltage sampling modes in active sleep mode.
  */
 enum bod12_mode_in_active {
-	/** BOD12 will sample the supply line continuously */
-	BOD12_ACTCFG_CONTINUOUS = 0,
-	/** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
-	BOD12_ACTCFG_SAMPLED    = SUPC_BOD12_ACTCFG,
+    /** BOD12 will sample the supply line continuously */
+    BOD12_ACTCFG_CONTINUOUS = 0,
+    /** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
+    BOD12_ACTCFG_SAMPLED    = SUPC_BOD12_ACTCFG,
 };
 
 /**
@@ -291,10 +291,10 @@ enum bod12_mode_in_active {
  * List of possible BOD12 module voltage sampling modes in standby sleep mode.
  */
 enum bod12_mode_in_standby {
-	/** BOD12 will sample the supply line continuously */
-	BOD12_STDBYCFG_CONTINUOUS = 0,
-	/** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
-	BOD12_STDBYCFG_SAMPLED    = SUPC_BOD12_STDBYCFG,
+    /** BOD12 will sample the supply line continuously */
+    BOD12_STDBYCFG_CONTINUOUS = 0,
+    /** BOD12 will use the BOD12 sampling clock (1KHz) to sample the supply line */
+    BOD12_STDBYCFG_SAMPLED    = SUPC_BOD12_STDBYCFG,
 };
 
 /**
@@ -303,31 +303,31 @@ enum bod12_mode_in_standby {
  * List of possible BOD12 actions when a BOD12 module detects a brown-out condition.
  */
 enum bod12_action {
-	/** A BOD12 detect will do nothing, and the BOD12 state must be polled */
-	BOD12_ACTION_NONE      = SUPC_BOD12_ACTION(0),
-	/** A BOD12 detect will reset the device */
-	BOD12_ACTION_RESET     = SUPC_BOD12_ACTION(1),
-	/** A BOD12 detect will fire an interrupt */
-	BOD12_ACTION_INTERRUPT = SUPC_BOD12_ACTION(2),
+    /** A BOD12 detect will do nothing, and the BOD12 state must be polled */
+    BOD12_ACTION_NONE      = SUPC_BOD12_ACTION(0),
+    /** A BOD12 detect will reset the device */
+    BOD12_ACTION_RESET     = SUPC_BOD12_ACTION(1),
+    /** A BOD12 detect will fire an interrupt */
+    BOD12_ACTION_INTERRUPT = SUPC_BOD12_ACTION(2),
 };
 
 /** Configuration structure for a BOD12 module. */
 struct bod12_config {
-	/** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
-	 *  ULP32K to lower the sampling rate of the BOD12 */
-	enum bod12_prescale prescaler;
-	/** BOD12 configuration in active mode */
-	enum bod12_mode_in_active mode_in_active;
-	/** BOD12 configuration in backup sleep mode */
-	enum bod12_mode_in_standby mode_in_standby;
-	/** Action to perform when a low power detection is made */
-	enum bod12_action action;
-	/** BOD12 level to trigger at (see electrical section of device datasheet) */
-	uint8_t level;
-	/** If \c true, the BOD12 is kept enabled and sampled during device sleep */
-	bool run_in_standby;
-	/** If \c true, enables detection hysteresis */
-	bool hysteresis;
+    /** Input sampler clock prescaler factor, to reduce the 1KHz clock from the
+     *  ULP32K to lower the sampling rate of the BOD12 */
+    enum bod12_prescale prescaler;
+    /** BOD12 configuration in active mode */
+    enum bod12_mode_in_active mode_in_active;
+    /** BOD12 configuration in backup sleep mode */
+    enum bod12_mode_in_standby mode_in_standby;
+    /** Action to perform when a low power detection is made */
+    enum bod12_action action;
+    /** BOD12 level to trigger at (see electrical section of device datasheet) */
+    uint8_t level;
+    /** If \c true, the BOD12 is kept enabled and sampled during device sleep */
+    bool run_in_standby;
+    /** If \c true, enables detection hysteresis */
+    bool hysteresis;
 };
 
 
@@ -354,25 +354,25 @@ struct bod12_config {
  * \param[out] conf  BOD33 configuration struct to set to default settings
  */
 static inline void bod33_get_config_defaults(
-		struct bod33_config *const conf)
+        struct bod33_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
-
-	conf->prescaler       = BOD33_PRESCALE_DIV_2;
-	conf->monitor         = BOD33_VMON_VDD;
-	conf->mode_in_active  = BOD33_ACTCFG_CONTINUOUS;
-	conf->mode_in_standby = BOD33_STDBYCFG_CONTINUOUS;
-	conf->action          = BOD33_ACTION_NONE;
-	conf->level           = 0x7;
-	conf->backuplevel     = 0x7;
-	conf->run_in_backup   = true;
-	conf->run_in_standby  = true;
-	conf->hysteresis      = true;
+    /* Sanity check arguments */
+    Assert(conf);
+
+    conf->prescaler       = BOD33_PRESCALE_DIV_2;
+    conf->monitor         = BOD33_VMON_VDD;
+    conf->mode_in_active  = BOD33_ACTCFG_CONTINUOUS;
+    conf->mode_in_standby = BOD33_STDBYCFG_CONTINUOUS;
+    conf->action          = BOD33_ACTION_NONE;
+    conf->level           = 0x7;
+    conf->backuplevel     = 0x7;
+    conf->run_in_backup   = true;
+    conf->run_in_standby  = true;
+    conf->hysteresis      = true;
 }
 
 enum status_code bod33_set_config(
-		struct bod33_config *const conf);
+        struct bod33_config *const conf);
 
 /**
  * \brief Enables a configured BOD33 module.
@@ -385,12 +385,13 @@ enum status_code bod33_set_config(
  */
 static inline enum status_code bod33_enable(void)
 {
-	SUPC->BOD33.reg |= SUPC_BOD33_ENABLE;
-	while (!(SUPC->STATUS.reg & SUPC_STATUS_B33SRDY)) {
-		/* Wait for BOD33 register sync ready */
-	}
+    SUPC->BOD33.reg |= SUPC_BOD33_ENABLE;
+    while (!(SUPC->STATUS.reg & SUPC_STATUS_B33SRDY))
+    {
+        /* Wait for BOD33 register sync ready */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -404,10 +405,10 @@ static inline enum status_code bod33_enable(void)
  */
 static inline enum status_code bod33_disable(void)
 {
-	SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD33RDY | SUPC_INTENCLR_BOD33DET | SUPC_INTENCLR_B33SRDY;
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET | SUPC_INTFLAG_B33SRDY;
-	SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
-	return STATUS_OK;
+    SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD33RDY | SUPC_INTENCLR_BOD33DET | SUPC_INTENCLR_B33SRDY;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY | SUPC_INTFLAG_BOD33DET | SUPC_INTFLAG_B33SRDY;
+    SUPC->BOD33.reg &= ~SUPC_BOD33_ENABLE;
+    return STATUS_OK;
 }
 
 /**
@@ -423,7 +424,7 @@ static inline enum status_code bod33_disable(void)
  */
 static inline bool bod33_is_detected(void)
 {
-	return SUPC->STATUS.bit.BOD33DET;
+    return SUPC->STATUS.bit.BOD33DET;
 }
 
 /**
@@ -435,8 +436,8 @@ static inline bool bod33_is_detected(void)
  */
 static inline void bod33_clear_detected(void)
 {
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
-	return;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD33DET;
+    return;
 }
 
 /**
@@ -454,22 +455,22 @@ static inline void bod33_clear_detected(void)
  * \param[out] conf  BOD12 configuration struct to set to default settings
  */
 static inline void bod12_get_config_defaults(
-		struct bod12_config *const conf)
+        struct bod12_config *const conf)
 {
-	/* Sanity check arguments */
-	Assert(conf);
-
-	conf->prescaler       = BOD12_PRESCALE_DIV_2;
-	conf->mode_in_active  = BOD12_ACTCFG_CONTINUOUS;
-	conf->mode_in_standby = BOD12_STDBYCFG_CONTINUOUS;
-	conf->action          = BOD12_ACTION_RESET;
-	conf->level           = 0x12;
-	conf->run_in_standby  = true;
-	conf->hysteresis      = true;
+    /* Sanity check arguments */
+    Assert(conf);
+
+    conf->prescaler       = BOD12_PRESCALE_DIV_2;
+    conf->mode_in_active  = BOD12_ACTCFG_CONTINUOUS;
+    conf->mode_in_standby = BOD12_STDBYCFG_CONTINUOUS;
+    conf->action          = BOD12_ACTION_RESET;
+    conf->level           = 0x12;
+    conf->run_in_standby  = true;
+    conf->hysteresis      = true;
 }
 
 enum status_code bod12_set_config(
-		struct bod12_config *const conf);
+        struct bod12_config *const conf);
 
 /**
  * \brief Enables a configured BOD12 module.
@@ -482,12 +483,13 @@ enum status_code bod12_set_config(
  */
 static inline enum status_code bod12_enable(void)
 {
-	SUPC->BOD12.reg |= SUPC_BOD12_ENABLE;
-	while (!(SUPC->STATUS.reg & SUPC_STATUS_B12SRDY)) {
-		/* Wait for BOD12 register sync ready */
-	}
+    SUPC->BOD12.reg |= SUPC_BOD12_ENABLE;
+    while (!(SUPC->STATUS.reg & SUPC_STATUS_B12SRDY))
+    {
+        /* Wait for BOD12 register sync ready */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -501,10 +503,10 @@ static inline enum status_code bod12_enable(void)
  */
 static inline enum status_code bod12_disable(void)
 {
-	SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD12RDY | SUPC_INTENCLR_BOD12DET | SUPC_INTENCLR_B12SRDY;
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY | SUPC_INTFLAG_BOD12DET | SUPC_INTFLAG_B12SRDY;
-	SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
-	return STATUS_OK;
+    SUPC->INTENCLR.reg = SUPC_INTENCLR_BOD12RDY | SUPC_INTENCLR_BOD12DET | SUPC_INTENCLR_B12SRDY;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY | SUPC_INTFLAG_BOD12DET | SUPC_INTFLAG_B12SRDY;
+    SUPC->BOD12.reg &= ~SUPC_BOD12_ENABLE;
+    return STATUS_OK;
 }
 
 /**
@@ -520,7 +522,7 @@ static inline enum status_code bod12_disable(void)
  */
 static inline bool bod12_is_detected(void)
 {
-	return SUPC->STATUS.bit.BOD12DET;
+    return SUPC->STATUS.bit.BOD12DET;
 }
 
 /**
@@ -532,8 +534,8 @@ static inline bool bod12_is_detected(void)
  */
 static inline void bod12_clear_detected(void)
 {
-	SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
-	return;
+    SUPC->INTFLAG.reg = SUPC_INTFLAG_BOD12DET;
+    return;
 }
 
 
@@ -579,12 +581,12 @@ static inline void bod12_clear_detected(void)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -614,21 +616,21 @@ static inline void bod12_clear_detected(void)
  * \page asfdoc_sam0_bod_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42453B</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L22</td>
- *	</tr>
- *	<tr>
- *		<td>42453A</td>
- *		<td>06/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42453B</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L22</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42453A</td>
+ *      <td>06/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c
index 8065ff24705a..2cbf6153c495 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.c
@@ -83,445 +83,487 @@ static struct can_extended_message_filter_element can1_rx_extended_filter[CONF_C
 
 static void _can_message_memory_init(Can *hw)
 {
-	if (hw == CAN0) {
-		hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can0_rx_standard_filter) |
-				CAN_SIDFC_LSS(CONF_CAN0_RX_STANDARD_ID_FILTER_NUM);
-		hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can0_rx_extended_filter) |
-				CAN_XIDFC_LSE(CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM);
-		hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo_0) |
-				CAN_RXF0C_F0S(CONF_CAN0_RX_FIFO_0_NUM);
-		hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can0_rx_fifo_1) |
-				CAN_RXF1C_F1S(CONF_CAN0_RX_FIFO_1_NUM);
-		hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can0_rx_buffer);
-		hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can0_tx_buffer) |
-				CAN_TXBC_NDTB(CONF_CAN0_TX_BUFFER_NUM) |
-				CAN_TXBC_TFQS(CONF_CAN0_TX_FIFO_QUEUE_NUM);
-		hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo) |
-				CAN_TXEFC_EFS(CONF_CAN0_TX_EVENT_FIFO);
-	} else if (hw == CAN1) {
-		hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can1_rx_standard_filter) |
-				CAN_SIDFC_LSS(CONF_CAN1_RX_STANDARD_ID_FILTER_NUM);
-		hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can1_rx_extended_filter) |
-				CAN_XIDFC_LSE(CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM);
-		hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo_0) |
-				CAN_RXF0C_F0S(CONF_CAN1_RX_FIFO_0_NUM);
-		hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can1_rx_fifo_1) |
-				CAN_RXF1C_F1S(CONF_CAN1_RX_FIFO_1_NUM);
-		hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can1_rx_buffer);
-		hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can1_tx_buffer) |
-				CAN_TXBC_NDTB(CONF_CAN1_TX_BUFFER_NUM) |
-				CAN_TXBC_TFQS(CONF_CAN1_TX_FIFO_QUEUE_NUM);
-		hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo) |
-				CAN_TXEFC_EFS(CONF_CAN1_TX_EVENT_FIFO);
-	}
-
-	/**
-	 * The data size in conf_can.h should be 8/12/16/20/24/32/48/64,
-	 * The corresponding setting value in register is 0/1//2/3/4/5/6/7.
-	 * To simplify the calculation, seperate to two group 8/12/16/20/24 which
-	 * increased with 4 and 32/48/64 which increased with 16.
-	 */
-	if (CONF_CAN_ELEMENT_DATA_SIZE <= 24) {
-		hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
-				CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
-				CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
-		hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
-	} else {
-		hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
-				CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
-				CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
-		hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
-	}
+    if (hw == CAN0)
+    {
+        hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can0_rx_standard_filter) |
+                CAN_SIDFC_LSS(CONF_CAN0_RX_STANDARD_ID_FILTER_NUM);
+        hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can0_rx_extended_filter) |
+                CAN_XIDFC_LSE(CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM);
+        hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can0_rx_fifo_0) |
+                CAN_RXF0C_F0S(CONF_CAN0_RX_FIFO_0_NUM);
+        hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can0_rx_fifo_1) |
+                CAN_RXF1C_F1S(CONF_CAN0_RX_FIFO_1_NUM);
+        hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can0_rx_buffer);
+        hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can0_tx_buffer) |
+                CAN_TXBC_NDTB(CONF_CAN0_TX_BUFFER_NUM) |
+                CAN_TXBC_TFQS(CONF_CAN0_TX_FIFO_QUEUE_NUM);
+        hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can0_tx_event_fifo) |
+                CAN_TXEFC_EFS(CONF_CAN0_TX_EVENT_FIFO);
+    } else if (hw == CAN1)
+    {
+        hw->SIDFC.reg = CAN_SIDFC_FLSSA((uint32_t)can1_rx_standard_filter) |
+                CAN_SIDFC_LSS(CONF_CAN1_RX_STANDARD_ID_FILTER_NUM);
+        hw->XIDFC.reg = CAN_XIDFC_FLESA((uint32_t)can1_rx_extended_filter) |
+                CAN_XIDFC_LSE(CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM);
+        hw->RXF0C.reg = CAN_RXF0C_F0SA((uint32_t)can1_rx_fifo_0) |
+                CAN_RXF0C_F0S(CONF_CAN1_RX_FIFO_0_NUM);
+        hw->RXF1C.reg = CAN_RXF1C_F1SA((uint32_t)can1_rx_fifo_1) |
+                CAN_RXF1C_F1S(CONF_CAN1_RX_FIFO_1_NUM);
+        hw->RXBC.reg = CAN_RXBC_RBSA((uint32_t)can1_rx_buffer);
+        hw->TXBC.reg = CAN_TXBC_TBSA((uint32_t)can1_tx_buffer) |
+                CAN_TXBC_NDTB(CONF_CAN1_TX_BUFFER_NUM) |
+                CAN_TXBC_TFQS(CONF_CAN1_TX_FIFO_QUEUE_NUM);
+        hw->TXEFC.reg = CAN_TXEFC_EFSA((uint32_t)can1_tx_event_fifo) |
+                CAN_TXEFC_EFS(CONF_CAN1_TX_EVENT_FIFO);
+    }
+
+    /**
+     * The data size in conf_can.h should be 8/12/16/20/24/32/48/64,
+     * The corresponding setting value in register is 0/1//2/3/4/5/6/7.
+     * To simplify the calculation, seperate to two group 8/12/16/20/24 which
+     * increased with 4 and 32/48/64 which increased with 16.
+     */
+    if (CONF_CAN_ELEMENT_DATA_SIZE <= 24)
+    {
+        hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
+                CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4) |
+                CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
+        hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 8) / 4);
+    } else {
+        hw->RXESC.reg = CAN_RXESC_RBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
+                CAN_RXESC_F0DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5) |
+                CAN_RXESC_F1DS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
+        hw->TXESC.reg = CAN_TXESC_TBDS((CONF_CAN_ELEMENT_DATA_SIZE - 32) / 16 + 5);
+    }
 }
 
 static void _can_set_configuration(Can *hw, struct can_config *config)
 {
-	/* Timing setting. */
-	hw->NBTP.reg = CAN_NBTP_NBRP(CONF_CAN_NBTP_NBRP_VALUE) |
-			CAN_NBTP_NSJW(CONF_CAN_NBTP_NSJW_VALUE) |
-			CAN_NBTP_NTSEG1(CONF_CAN_NBTP_NTSEG1_VALUE) |
-			CAN_NBTP_NTSEG2(CONF_CAN_NBTP_NTSEG2_VALUE);
-	hw->DBTP.reg = CAN_DBTP_DBRP(CONF_CAN_DBTP_DBRP_VALUE) |
-			CAN_DBTP_DSJW(CONF_CAN_DBTP_DSJW_VALUE) |
-			CAN_DBTP_DTSEG1(CONF_CAN_DBTP_DTSEG1_VALUE) |
-			CAN_DBTP_DTSEG2(CONF_CAN_DBTP_DTSEG2_VALUE);
-
-	if (config->tdc_enable) {
-		hw->DBTP.reg |= CAN_DBTP_TDC;
-	}
-	
-	if (config->run_in_standby) {
-		hw->MRCFG.reg |= 0x01<<6;
-	}
-
-	hw->RWD.reg |= CAN_RWD_WDC(config->watchdog_configuration);
-
-	if (config->transmit_pause) {
-		hw->CCCR.reg |= CAN_CCCR_TXP;
-	}
-
-	if (config->edge_filtering) {
-		hw->CCCR.reg |= CAN_CCCR_EFBI;
-	}
-
-	if (config->protocol_exception_handling) {
-		hw->CCCR.reg |= CAN_CCCR_PXHD;
-	}
-
-	if (!config->automatic_retransmission) {
-		hw->CCCR.reg |= CAN_CCCR_DAR;
-	}
-
-	if (config->clock_stop_request) {
-		hw->CCCR.reg |= CAN_CCCR_CSR;
-	}
-
-	if (config->clock_stop_acknowledge) {
-		hw->CCCR.reg |= CAN_CCCR_CSA;
-	}
-
-	hw->TSCC.reg = CAN_TSCC_TCP(config->timestamp_prescaler) |
-			CAN_TSCC_TSS_INC_Val;
-
-	hw->TOCC.reg = CAN_TOCC_TOP(config->timeout_period) |
-			config->timeout_mode | config->timeout_enable;
-
-	hw->TDCR.reg = CAN_TDCR_TDCO(config->delay_compensation_offset) |
-			CAN_TDCR_TDCF(config->delay_compensation_filter_window_length);
-
-	hw->GFC.reg = CAN_GFC_ANFS(config->nonmatching_frames_action_standard) |
-			CAN_GFC_ANFE(config->nonmatching_frames_action_extended);
-	if (config->remote_frames_standard_reject) {
-		hw->GFC.reg |= CAN_GFC_RRFS;
-	}
-	if (config->remote_frames_extended_reject) {
-		hw->GFC.reg |= CAN_GFC_RRFE;
-	}
-
-	hw->XIDAM.reg = config->extended_id_mask;
-
-	if (config->rx_fifo_0_overwrite) {
-		hw->RXF0C.reg |= CAN_RXF0C_F0OM;
-	}
-	hw->RXF0C.reg |= CAN_RXF0C_F0WM(config->rx_fifo_0_watermark);
-
-	if (config->rx_fifo_1_overwrite) {
-		hw->RXF1C.reg |= CAN_RXF1C_F1OM;
-	}
-	hw->RXF1C.reg |= CAN_RXF1C_F1WM(config->rx_fifo_1_watermark);
-
-	if (config->tx_queue_mode) {
-		hw->TXBC.reg |= CAN_TXBC_TFQM;
-	}
-
-	hw->TXEFC.reg |= CAN_TXEFC_EFWM(config->tx_event_fifo_watermark);
+    /* Timing setting. */
+    hw->NBTP.reg = CAN_NBTP_NBRP(CONF_CAN_NBTP_NBRP_VALUE) |
+            CAN_NBTP_NSJW(CONF_CAN_NBTP_NSJW_VALUE) |
+            CAN_NBTP_NTSEG1(CONF_CAN_NBTP_NTSEG1_VALUE) |
+            CAN_NBTP_NTSEG2(CONF_CAN_NBTP_NTSEG2_VALUE);
+    hw->DBTP.reg = CAN_DBTP_DBRP(CONF_CAN_DBTP_DBRP_VALUE) |
+            CAN_DBTP_DSJW(CONF_CAN_DBTP_DSJW_VALUE) |
+            CAN_DBTP_DTSEG1(CONF_CAN_DBTP_DTSEG1_VALUE) |
+            CAN_DBTP_DTSEG2(CONF_CAN_DBTP_DTSEG2_VALUE);
+
+    if (config->tdc_enable)
+    {
+        hw->DBTP.reg |= CAN_DBTP_TDC;
+    }
+
+    if (config->run_in_standby)
+    {
+        hw->MRCFG.reg |= 0x01<<6;
+    }
+
+    hw->RWD.reg |= CAN_RWD_WDC(config->watchdog_configuration);
+
+    if (config->transmit_pause)
+    {
+        hw->CCCR.reg |= CAN_CCCR_TXP;
+    }
+
+    if (config->edge_filtering)
+    {
+        hw->CCCR.reg |= CAN_CCCR_EFBI;
+    }
+
+    if (config->protocol_exception_handling)
+    {
+        hw->CCCR.reg |= CAN_CCCR_PXHD;
+    }
+
+    if (!config->automatic_retransmission)
+    {
+        hw->CCCR.reg |= CAN_CCCR_DAR;
+    }
+
+    if (config->clock_stop_request)
+    {
+        hw->CCCR.reg |= CAN_CCCR_CSR;
+    }
+
+    if (config->clock_stop_acknowledge)
+    {
+        hw->CCCR.reg |= CAN_CCCR_CSA;
+    }
+
+    hw->TSCC.reg = CAN_TSCC_TCP(config->timestamp_prescaler) |
+            CAN_TSCC_TSS_INC_Val;
+
+    hw->TOCC.reg = CAN_TOCC_TOP(config->timeout_period) |
+            config->timeout_mode | config->timeout_enable;
+
+    hw->TDCR.reg = CAN_TDCR_TDCO(config->delay_compensation_offset) |
+            CAN_TDCR_TDCF(config->delay_compensation_filter_window_length);
+
+    hw->GFC.reg = CAN_GFC_ANFS(config->nonmatching_frames_action_standard) |
+            CAN_GFC_ANFE(config->nonmatching_frames_action_extended);
+    if (config->remote_frames_standard_reject)
+    {
+        hw->GFC.reg |= CAN_GFC_RRFS;
+    }
+    if (config->remote_frames_extended_reject)
+    {
+        hw->GFC.reg |= CAN_GFC_RRFE;
+    }
+
+    hw->XIDAM.reg = config->extended_id_mask;
+
+    if (config->rx_fifo_0_overwrite)
+    {
+        hw->RXF0C.reg |= CAN_RXF0C_F0OM;
+    }
+    hw->RXF0C.reg |= CAN_RXF0C_F0WM(config->rx_fifo_0_watermark);
+
+    if (config->rx_fifo_1_overwrite)
+    {
+        hw->RXF1C.reg |= CAN_RXF1C_F1OM;
+    }
+    hw->RXF1C.reg |= CAN_RXF1C_F1WM(config->rx_fifo_1_watermark);
+
+    if (config->tx_queue_mode)
+    {
+        hw->TXBC.reg |= CAN_TXBC_TFQM;
+    }
+
+    hw->TXEFC.reg |= CAN_TXEFC_EFWM(config->tx_event_fifo_watermark);
 }
 
 static void _can_enable_peripheral_clock(struct can_module *const module_inst)
 {
-	if (module_inst->hw == CAN0) {
-		/* Turn on the digital interface clock. */
-		system_ahb_clock_set_mask(MCLK_AHBMASK_CAN0);
-	} else if (module_inst->hw == CAN1) {
-		/* Turn on the digital interface clock. */
-		system_ahb_clock_set_mask(MCLK_AHBMASK_CAN1);
-	}
+    if (module_inst->hw == CAN0)
+    {
+        /* Turn on the digital interface clock. */
+        system_ahb_clock_set_mask(MCLK_AHBMASK_CAN0);
+    } else if (module_inst->hw == CAN1)
+    {
+        /* Turn on the digital interface clock. */
+        system_ahb_clock_set_mask(MCLK_AHBMASK_CAN1);
+    }
 }
 
 void can_init(struct can_module *const module_inst, Can *hw,
-		struct can_config *config)
+        struct can_config *config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
 
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
 
-	/* Enable peripheral clock */
-	_can_enable_peripheral_clock(module_inst);
+    /* Enable peripheral clock */
+    _can_enable_peripheral_clock(module_inst);
 
-	/* Configure GCLK channel */
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
+    /* Configure GCLK channel */
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
 
-	if (hw == CAN0) {
-		system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(CAN0_GCLK_ID);
-	} else if (hw == CAN1) {
-		system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(CAN1_GCLK_ID);
-	}
+    if (hw == CAN0)
+    {
+        system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
+        system_gclk_chan_enable(CAN0_GCLK_ID);
+    } else if (hw == CAN1)
+    {
+        system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
+        system_gclk_chan_enable(CAN1_GCLK_ID);
+    }
 
 
-	/* Configuration Change Enable. */
-	hw->CCCR.reg |= CAN_CCCR_CCE;
+    /* Configuration Change Enable. */
+    hw->CCCR.reg |= CAN_CCCR_CCE;
 
-	/* Initialize the message memory address. */
-	_can_message_memory_init(hw);
+    /* Initialize the message memory address. */
+    _can_message_memory_init(hw);
 
-	/* Set the configuration. */
-	_can_set_configuration(hw, config);
+    /* Set the configuration. */
+    _can_set_configuration(hw, config);
 
-	/* Enable the interrupt setting which no need change. */
-	hw->ILE.reg = CAN_ILE_EINT0 | CAN_ILE_EINT1;
-	hw->TXBTIE.reg = CAN_TXBTIE_MASK;
-	hw->TXBCIE.reg = CAN_TXBCIE_MASK;
+    /* Enable the interrupt setting which no need change. */
+    hw->ILE.reg = CAN_ILE_EINT0 | CAN_ILE_EINT1;
+    hw->TXBTIE.reg = CAN_TXBTIE_MASK;
+    hw->TXBCIE.reg = CAN_TXBCIE_MASK;
 }
 
 void can_set_baudrate(Can *hw, uint32_t baudrate)
 {
-	uint32_t gclk_can_value = 0;
-	uint32_t can_nbtp_nbrp_value;
-	uint32_t can_nbtp_nsgw_value = 3, can_nbtp_ntseg1_value = 10, can_nbtp_ntseg2_value = 3;
-	
-	if (hw == CAN0) {
-		gclk_can_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
-		} else if (hw == CAN1) {
-		gclk_can_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
-	}
-	
-	can_nbtp_nbrp_value = gclk_can_value / baudrate / (3 + can_nbtp_ntseg1_value + can_nbtp_ntseg2_value);
-	
-	hw->NBTP.reg = CAN_NBTP_NBRP(can_nbtp_nbrp_value) |
-			CAN_NBTP_NSJW(can_nbtp_nsgw_value) |
-			CAN_NBTP_NTSEG1(can_nbtp_ntseg1_value) |
-			CAN_NBTP_NTSEG2(can_nbtp_ntseg2_value);
+    uint32_t gclk_can_value = 0;
+    uint32_t can_nbtp_nbrp_value;
+    uint32_t can_nbtp_nsgw_value = 3, can_nbtp_ntseg1_value = 10, can_nbtp_ntseg2_value = 3;
+
+    if (hw == CAN0)
+    {
+        gclk_can_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
+        } else if (hw == CAN1)
+        {
+        gclk_can_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
+    }
+
+    can_nbtp_nbrp_value = gclk_can_value / baudrate / (3 + can_nbtp_ntseg1_value + can_nbtp_ntseg2_value);
+
+    hw->NBTP.reg = CAN_NBTP_NBRP(can_nbtp_nbrp_value) |
+            CAN_NBTP_NSJW(can_nbtp_nsgw_value) |
+            CAN_NBTP_NTSEG1(can_nbtp_ntseg1_value) |
+            CAN_NBTP_NTSEG2(can_nbtp_ntseg2_value);
 }
 
 void can_fd_set_baudrate(Can *hw, uint32_t baudrate)
 {
-	uint32_t gclk_can_fd_value = 0;
-	uint32_t can_fd_dbtp_dbrp_value;
-	uint32_t can_fd_dbtp_dsgw_value = 3, can_fd_dbtp_dtseg1_value = 10, can_fd_dbtp_dtseg2_value = 3;
-	
-	if (hw == CAN0) {
-		gclk_can_fd_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
-		} else if (hw == CAN1) {
-		gclk_can_fd_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
-	}
-	
-	can_fd_dbtp_dbrp_value = gclk_can_fd_value / baudrate / (3 + can_fd_dbtp_dtseg1_value + can_fd_dbtp_dtseg2_value);
-	
-	hw->NBTP.reg = CAN_DBTP_DBRP(can_fd_dbtp_dbrp_value) |
-			CAN_DBTP_DSJW(can_fd_dbtp_dsgw_value) |
-			CAN_DBTP_DTSEG1(can_fd_dbtp_dtseg1_value) |
-			CAN_DBTP_DTSEG2(can_fd_dbtp_dtseg2_value);
+    uint32_t gclk_can_fd_value = 0;
+    uint32_t can_fd_dbtp_dbrp_value;
+    uint32_t can_fd_dbtp_dsgw_value = 3, can_fd_dbtp_dtseg1_value = 10, can_fd_dbtp_dtseg2_value = 3;
+
+    if (hw == CAN0)
+    {
+        gclk_can_fd_value = system_gclk_chan_get_hz(CAN0_GCLK_ID);
+        } else if (hw == CAN1)
+        {
+        gclk_can_fd_value = system_gclk_chan_get_hz(CAN1_GCLK_ID);
+    }
+
+    can_fd_dbtp_dbrp_value = gclk_can_fd_value / baudrate / (3 + can_fd_dbtp_dtseg1_value + can_fd_dbtp_dtseg2_value);
+
+    hw->NBTP.reg = CAN_DBTP_DBRP(can_fd_dbtp_dbrp_value) |
+            CAN_DBTP_DSJW(can_fd_dbtp_dsgw_value) |
+            CAN_DBTP_DTSEG1(can_fd_dbtp_dtseg1_value) |
+            CAN_DBTP_DTSEG2(can_fd_dbtp_dtseg2_value);
 }
 
 void can_start(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg &= ~CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (module_inst->hw->CCCR.reg & CAN_CCCR_INIT);
+    module_inst->hw->CCCR.reg &= ~CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (module_inst->hw->CCCR.reg & CAN_CCCR_INIT);
 }
 
 void can_stop(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
 }
 
 void can_enable_fd_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
-	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
 
-	module_inst->hw->CCCR.reg |= CAN_CCCR_FDOE;
-	module_inst->hw->CCCR.reg |= CAN_CCCR_BRSE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_FDOE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_BRSE;
 }
 
 void can_disable_fd_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg &= ~CAN_CCCR_FDOE;
+    module_inst->hw->CCCR.reg &= ~CAN_CCCR_FDOE;
 }
 
 void can_enable_restricted_operation_mode(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
-	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
 
-	module_inst->hw->CCCR.reg |= CAN_CCCR_ASM;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_ASM;
 }
 
 void can_disable_restricted_operation_mode(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg &= ~CAN_CCCR_ASM;
+    module_inst->hw->CCCR.reg &= ~CAN_CCCR_ASM;
 }
 
 void can_enable_bus_monitor_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
-	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
 
-	module_inst->hw->CCCR.reg |= CAN_CCCR_MON;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_MON;
 }
 
 void can_disable_bus_monitor_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg &= ~CAN_CCCR_MON;
+    module_inst->hw->CCCR.reg &= ~CAN_CCCR_MON;
 }
 
 void can_enable_sleep_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_CSR;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_CSR;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
 
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
 }
 
 void can_disable_sleep_mode(struct can_module *const module_inst)
 {
-	/* Enable peripheral clock */
-	_can_enable_peripheral_clock(module_inst);
-	if (module_inst->hw == CAN0) {
-		system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(CAN0_GCLK_ID);
-	}
-
-	if (module_inst->hw == CAN1) {
-		system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(CAN1_GCLK_ID);
-	}
-	module_inst->hw->CCCR.reg &= CAN_CCCR_CSR;
-	while ((module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
+    /* Enable peripheral clock */
+    _can_enable_peripheral_clock(module_inst);
+    if (module_inst->hw == CAN0)
+    {
+        system_gclk_chan_set_config(CAN0_GCLK_ID, &gclk_chan_conf);
+        system_gclk_chan_enable(CAN0_GCLK_ID);
+    }
+
+    if (module_inst->hw == CAN1)
+    {
+        system_gclk_chan_set_config(CAN1_GCLK_ID, &gclk_chan_conf);
+        system_gclk_chan_enable(CAN1_GCLK_ID);
+    }
+    module_inst->hw->CCCR.reg &= CAN_CCCR_CSR;
+    while ((module_inst->hw->CCCR.reg & CAN_CCCR_CSA));
 }
 
 void can_enable_test_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
-	/* Wait for the sync. */
-	while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
-	module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_INIT;
+    /* Wait for the sync. */
+    while (!(module_inst->hw->CCCR.reg & CAN_CCCR_INIT));
+    module_inst->hw->CCCR.reg |= CAN_CCCR_CCE;
 
-	module_inst->hw->CCCR.reg |= CAN_CCCR_TEST;
-	module_inst->hw->TEST.reg |= CAN_TEST_LBCK;
+    module_inst->hw->CCCR.reg |= CAN_CCCR_TEST;
+    module_inst->hw->TEST.reg |= CAN_TEST_LBCK;
 }
 
 void can_disable_test_mode(struct can_module *const module_inst)
 {
-	module_inst->hw->CCCR.reg &= ~CAN_CCCR_TEST;
+    module_inst->hw->CCCR.reg &= ~CAN_CCCR_TEST;
 }
 
 enum status_code can_set_rx_standard_filter(
-		struct can_module *const module_inst,
-		struct can_standard_message_filter_element *sd_filter, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_standard_message_filter_element *sd_filter, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		can0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		can1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        can0_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        can1_rx_standard_filter[index].S0.reg = sd_filter->S0.reg;
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_set_rx_extended_filter(
-		struct can_module *const module_inst,
-		struct can_extended_message_filter_element *et_filter, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_extended_message_filter_element *et_filter, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		can0_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
-		can0_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		can1_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
-		can1_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        can0_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
+        can0_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        can1_rx_extended_filter[index].F0.reg = et_filter->F0.reg;
+        can1_rx_extended_filter[index].F1.reg = et_filter->F1.reg;
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_get_rx_buffer_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_buffer *rx_element, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_rx_element_buffer *rx_element, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		memcpy(rx_element, &can0_rx_buffer[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		memcpy(rx_element, &can1_rx_buffer[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        memcpy(rx_element, &can0_rx_buffer[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        memcpy(rx_element, &can1_rx_buffer[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_get_rx_fifo_0_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_fifo_0 *rx_element, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_rx_element_fifo_0 *rx_element, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		memcpy(rx_element, &can0_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		memcpy(rx_element, &can1_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        memcpy(rx_element, &can0_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        memcpy(rx_element, &can1_rx_fifo_0[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_get_rx_fifo_1_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_fifo_1 *rx_element, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_rx_element_fifo_1 *rx_element, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		memcpy(rx_element, &can0_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		memcpy(rx_element, &can1_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        memcpy(rx_element, &can0_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        memcpy(rx_element, &can1_rx_fifo_1[index], sizeof(struct can_rx_element_buffer));
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_set_tx_buffer_element(
-		struct can_module *const module_inst,
-		struct can_tx_element *tx_element, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_tx_element *tx_element, uint32_t index)
 {
-	uint32_t i;
-	if (module_inst->hw == CAN0) {
-		can0_tx_buffer[index].T0.reg = tx_element->T0.reg;
-		can0_tx_buffer[index].T1.reg = tx_element->T1.reg;
-		for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
-			can0_tx_buffer[index].data[i] = tx_element->data[i];
-		}
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		can1_tx_buffer[index].T0.reg = tx_element->T0.reg;
-		can1_tx_buffer[index].T1.reg = tx_element->T1.reg;
-		for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++) {
-			can1_tx_buffer[index].data[i] = tx_element->data[i];
-		}
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    uint32_t i;
+    if (module_inst->hw == CAN0)
+    {
+        can0_tx_buffer[index].T0.reg = tx_element->T0.reg;
+        can0_tx_buffer[index].T1.reg = tx_element->T1.reg;
+        for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++)
+        {
+            can0_tx_buffer[index].data[i] = tx_element->data[i];
+        }
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        can1_tx_buffer[index].T0.reg = tx_element->T0.reg;
+        can1_tx_buffer[index].T1.reg = tx_element->T1.reg;
+        for (i = 0; i < CONF_CAN_ELEMENT_DATA_SIZE; i++)
+        {
+            can1_tx_buffer[index].data[i] = tx_element->data[i];
+        }
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
 enum status_code can_get_tx_event_fifo_element(
-		struct can_module *const module_inst,
-		struct can_tx_event_element *tx_event_element, uint32_t index)
+        struct can_module *const module_inst,
+        struct can_tx_event_element *tx_event_element, uint32_t index)
 {
-	if (module_inst->hw == CAN0) {
-		tx_event_element->E0.reg = can0_tx_event_fifo[index].E0.reg;
-		tx_event_element->E1.reg = can0_tx_event_fifo[index].E1.reg;
-		return STATUS_OK;
-	} else if (module_inst->hw == CAN1) {
-		tx_event_element->E0.reg = can1_tx_event_fifo[index].E0.reg;
-		tx_event_element->E1.reg = can1_tx_event_fifo[index].E1.reg;
-		return STATUS_OK;
-	}
-	return STATUS_ERR_INVALID_ARG;
+    if (module_inst->hw == CAN0)
+    {
+        tx_event_element->E0.reg = can0_tx_event_fifo[index].E0.reg;
+        tx_event_element->E1.reg = can0_tx_event_fifo[index].E1.reg;
+        return STATUS_OK;
+    } else if (module_inst->hw == CAN1)
+    {
+        tx_event_element->E0.reg = can1_tx_event_fifo[index].E0.reg;
+        tx_event_element->E1.reg = can1_tx_event_fifo[index].E1.reg;
+        return STATUS_OK;
+    }
+    return STATUS_ERR_INVALID_ARG;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h
index 653780dc56b8..7c786a76a321 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/can.h
@@ -111,27 +111,27 @@ typedef union {
  * \brief CAN receive element structure for buffer.
  */
 struct can_rx_element_buffer {
-	__IO CAN_RX_ELEMENT_R0_Type R0;
-	__IO CAN_RX_ELEMENT_R1_Type R1;
-	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+    __IO CAN_RX_ELEMENT_R0_Type R0;
+    __IO CAN_RX_ELEMENT_R1_Type R1;
+    uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
 };
 
 /**
  * \brief CAN receive element structure for FIFO 0.
  */
 struct can_rx_element_fifo_0 {
-	__IO CAN_RX_ELEMENT_R0_Type R0;
-	__IO CAN_RX_ELEMENT_R1_Type R1;
-	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+    __IO CAN_RX_ELEMENT_R0_Type R0;
+    __IO CAN_RX_ELEMENT_R1_Type R1;
+    uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
 };
 
 /**
  * \brief CAN receive element structure for FIFO 1.
  */
 struct can_rx_element_fifo_1 {
-	__IO CAN_RX_ELEMENT_R0_Type R0;
-	__IO CAN_RX_ELEMENT_R1_Type R1;
-	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+    __IO CAN_RX_ELEMENT_R0_Type R0;
+    __IO CAN_RX_ELEMENT_R1_Type R1;
+    uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
 };
 
 /* -------- CAN_TX_ELEMENT_T0 : (CAN TX element: 0x00) (R/W 32) Tx Element T0 Configuration -------- */
@@ -199,9 +199,9 @@ typedef union {
  *  Common element structure for transfer buffer and FIFO/QUEUE.
  */
 struct can_tx_element {
-	__IO CAN_TX_ELEMENT_T0_Type T0;
-	__IO CAN_TX_ELEMENT_T1_Type T1;
-	uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
+    __IO CAN_TX_ELEMENT_T0_Type T0;
+    __IO CAN_TX_ELEMENT_T1_Type T1;
+    uint8_t data[CONF_CAN_ELEMENT_DATA_SIZE];
 };
 
 /* -------- CAN_TX_EVENT_ELEMENT_E0 : (CAN TX event element: 0x00) (R/W 32) Tx Event Element E0 Configuration -------- */
@@ -261,8 +261,8 @@ typedef union {
  *  Common element structure for transfer event FIFO.
  */
 struct can_tx_event_element {
-	__IO CAN_TX_EVENT_ELEMENT_E0_Type E0;
-	__IO CAN_TX_EVENT_ELEMENT_E1_Type E1;
+    __IO CAN_TX_EVENT_ELEMENT_E0_Type E0;
+    __IO CAN_TX_EVENT_ELEMENT_E1_Type E1;
 };
 
 /* -------- CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0 : (CAN standard message ID filter element: 0x00) (R/W 32) Standard Message ID Filter Element S0 Configuration -------- */
@@ -307,7 +307,7 @@ typedef union {
  *  Common element structure for standard message ID filter element.
  */
 struct can_standard_message_filter_element {
-	__IO CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0;
+    __IO CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_Type S0;
 };
 
 /* -------- CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0 : (CAN extended message ID filter element: 0x00) (R/W 32) Extended Message ID Filter Element F0 Configuration -------- */
@@ -361,8 +361,8 @@ typedef union {
  *  Common element structure for extended message ID filter element.
  */
 struct can_extended_message_filter_element {
-	__IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0;
-	__IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1;
+    __IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_Type F0;
+    __IO CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_Type F1;
 };
 /** @} */
 
@@ -446,26 +446,26 @@ extern "C" {
  * \brief Can time out modes.
  */
 enum can_timeout_mode {
-	/** Continuous operation. */
-	CAN_TIMEOUT_CONTINUES = CAN_TOCC_TOS_CONT,
-	/** Timeout controlled by TX Event FIFO. */
-	CAN_TIMEOUT_TX_EVEN_FIFO = CAN_TOCC_TOS_TXEF,
-	/** Timeout controlled by Rx FIFO 0. */
-	CAN_TIMEOUT_RX_FIFO_0 = CAN_TOCC_TOS_RXF0,
-	/** Timeout controlled by Rx FIFO 1. */
-	CAN_TIMEOUT_RX_FIFO_1 = CAN_TOCC_TOS_RXF1,
+    /** Continuous operation. */
+    CAN_TIMEOUT_CONTINUES = CAN_TOCC_TOS_CONT,
+    /** Timeout controlled by TX Event FIFO. */
+    CAN_TIMEOUT_TX_EVEN_FIFO = CAN_TOCC_TOS_TXEF,
+    /** Timeout controlled by Rx FIFO 0. */
+    CAN_TIMEOUT_RX_FIFO_0 = CAN_TOCC_TOS_RXF0,
+    /** Timeout controlled by Rx FIFO 1. */
+    CAN_TIMEOUT_RX_FIFO_1 = CAN_TOCC_TOS_RXF1,
 };
 
 /**
  * \brief Can nonmatching frames action.
  */
 enum can_nonmatching_frames_action {
-	/** Accept in Rx FIFO 0. */
-	CAN_NONMATCHING_FRAMES_FIFO_0,
-	/** Accept in Rx FIFO 1. */
-	CAN_NONMATCHING_FRAMES_FIFO_1,
-	/** Reject. */
-	CAN_NONMATCHING_FRAMES_REJECT,
+    /** Accept in Rx FIFO 0. */
+    CAN_NONMATCHING_FRAMES_FIFO_0,
+    /** Accept in Rx FIFO 1. */
+    CAN_NONMATCHING_FRAMES_FIFO_1,
+    /** Reject. */
+    CAN_NONMATCHING_FRAMES_REJECT,
 };
 
 /**
@@ -479,8 +479,8 @@ enum can_nonmatching_frames_action {
  */
 struct can_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to CAN hardware module. */
-	Can *hw;
+    /** Pointer to CAN hardware module. */
+    Can *hw;
 #endif
 };
 
@@ -492,60 +492,60 @@ struct can_module {
  * function before being modified by the user application.
  */
 struct can_config {
-	/** GCLK generator used to clock the peripheral. */
-	enum gclk_generator clock_source;
-	/** CAN run in standby control. */
-	bool run_in_standby;
-	/** Start value of the Message RAM Watchdog Counter */
-	uint8_t watchdog_configuration;
-	/** Transmit Pause. */
-	bool transmit_pause;
-	/** Edge Filtering during Bus Integration. */
-	bool edge_filtering;
-	/** Protocol Exception Handling. */
-	bool protocol_exception_handling;
-	/** Automatic Retransmission. */
-	bool automatic_retransmission;
-	/** Clock Stop Request. */
-	bool clock_stop_request;
-	/** Clock Stop Acknowledge. */
-	bool clock_stop_acknowledge;
-	/** Timestamp Counter Prescaler: 0x0-0xF */
-	uint8_t timestamp_prescaler;
-	/** Timeout Period. */
-	uint16_t timeout_period;
-	/** Timeout Mode. */
-	enum can_timeout_mode timeout_mode;
-	/** Timeout enable. */
-	bool timeout_enable;
-	/** Transceiver Delay Compensation enable. */		
-	bool tdc_enable;
-	/** Transmitter Delay Compensation Offset : 0x0-0x7F */
-	uint8_t delay_compensation_offset;
-	/** Transmitter Delay Compensation Filter Window Length : 0x0-0x7F */
-	uint8_t delay_compensation_filter_window_length;
-	/** Nonmatching frames action for standard frames. */
-	enum can_nonmatching_frames_action nonmatching_frames_action_standard;
-	/** Nonmatching frames action for extended frames. */
-	enum can_nonmatching_frames_action nonmatching_frames_action_extended;
-	/** Reject Remote Standard Frames. */
-	bool remote_frames_standard_reject;
-	/** Reject Remote Extended Frames. */
-	bool remote_frames_extended_reject;
-	/** Extended ID Mask: 0x0-0x1FFFFFFF. */
-	uint32_t extended_id_mask;
-	/** Rx FIFO 0 Operation Mode. */
-	bool rx_fifo_0_overwrite;
-	/** Rx FIFO 0 Watermark: 1-64, other value disable it. */
-	uint8_t rx_fifo_0_watermark;
-	/** Rx FIFO 1 Operation Mode. */
-	bool rx_fifo_1_overwrite;
-	/** Rx FIFO 1 Watermark: 1-64, other value disable it. */
-	uint8_t rx_fifo_1_watermark;
-	/** Tx FIFO/Queue Mode, 0 for FIFO and 1 for Queue. */
-	bool tx_queue_mode;
-	/** Tx Event FIFO Watermark: 1-32, other value disable it. */
-	uint8_t tx_event_fifo_watermark;
+    /** GCLK generator used to clock the peripheral. */
+    enum gclk_generator clock_source;
+    /** CAN run in standby control. */
+    bool run_in_standby;
+    /** Start value of the Message RAM Watchdog Counter */
+    uint8_t watchdog_configuration;
+    /** Transmit Pause. */
+    bool transmit_pause;
+    /** Edge Filtering during Bus Integration. */
+    bool edge_filtering;
+    /** Protocol Exception Handling. */
+    bool protocol_exception_handling;
+    /** Automatic Retransmission. */
+    bool automatic_retransmission;
+    /** Clock Stop Request. */
+    bool clock_stop_request;
+    /** Clock Stop Acknowledge. */
+    bool clock_stop_acknowledge;
+    /** Timestamp Counter Prescaler: 0x0-0xF */
+    uint8_t timestamp_prescaler;
+    /** Timeout Period. */
+    uint16_t timeout_period;
+    /** Timeout Mode. */
+    enum can_timeout_mode timeout_mode;
+    /** Timeout enable. */
+    bool timeout_enable;
+    /** Transceiver Delay Compensation enable. */
+    bool tdc_enable;
+    /** Transmitter Delay Compensation Offset : 0x0-0x7F */
+    uint8_t delay_compensation_offset;
+    /** Transmitter Delay Compensation Filter Window Length : 0x0-0x7F */
+    uint8_t delay_compensation_filter_window_length;
+    /** Nonmatching frames action for standard frames. */
+    enum can_nonmatching_frames_action nonmatching_frames_action_standard;
+    /** Nonmatching frames action for extended frames. */
+    enum can_nonmatching_frames_action nonmatching_frames_action_extended;
+    /** Reject Remote Standard Frames. */
+    bool remote_frames_standard_reject;
+    /** Reject Remote Extended Frames. */
+    bool remote_frames_extended_reject;
+    /** Extended ID Mask: 0x0-0x1FFFFFFF. */
+    uint32_t extended_id_mask;
+    /** Rx FIFO 0 Operation Mode. */
+    bool rx_fifo_0_overwrite;
+    /** Rx FIFO 0 Watermark: 1-64, other value disable it. */
+    uint8_t rx_fifo_0_watermark;
+    /** Rx FIFO 1 Operation Mode. */
+    bool rx_fifo_1_overwrite;
+    /** Rx FIFO 1 Watermark: 1-64, other value disable it. */
+    uint8_t rx_fifo_1_watermark;
+    /** Tx FIFO/Queue Mode, 0 for FIFO and 1 for Queue. */
+    bool tx_queue_mode;
+    /** Tx Event FIFO Watermark: 1-32, other value disable it. */
+    uint8_t tx_event_fifo_watermark;
 
 };
 
@@ -588,39 +588,39 @@ struct can_config {
  *                     default values
  */
 static inline void can_get_config_defaults(
-		struct can_config *const config)
+        struct can_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->clock_source = GCLK_GENERATOR_8;
-	config->run_in_standby = false;
-	config->watchdog_configuration = 0x00;
-	config->transmit_pause = true;
-	config->edge_filtering = true;
-	config->protocol_exception_handling = true;
-	config->automatic_retransmission = true;
-	config->clock_stop_request = false;
-	config->clock_stop_acknowledge = false;
-	config->timestamp_prescaler = 0;
-	config->timeout_period = 0xFFFF;
-	config->timeout_mode = CAN_TIMEOUT_CONTINUES;
-	config->timeout_enable = false;
-	config->tdc_enable = false;
-	config->delay_compensation_offset = 0;
-	config->delay_compensation_filter_window_length = 0;
-	config->nonmatching_frames_action_standard = CAN_NONMATCHING_FRAMES_REJECT;
-	config->nonmatching_frames_action_extended = CAN_NONMATCHING_FRAMES_REJECT;
-	config->remote_frames_standard_reject = true;
-	config->remote_frames_extended_reject = true;
-	config->extended_id_mask = 0x1FFFFFFF;
-	config->rx_fifo_0_overwrite = true;
-	config->rx_fifo_0_watermark = 0;
-	config->rx_fifo_1_overwrite = true;
-	config->rx_fifo_1_watermark = 0;
-	config->tx_queue_mode = false;
-	config->tx_event_fifo_watermark = 0;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->clock_source = GCLK_GENERATOR_8;
+    config->run_in_standby = false;
+    config->watchdog_configuration = 0x00;
+    config->transmit_pause = true;
+    config->edge_filtering = true;
+    config->protocol_exception_handling = true;
+    config->automatic_retransmission = true;
+    config->clock_stop_request = false;
+    config->clock_stop_acknowledge = false;
+    config->timestamp_prescaler = 0;
+    config->timeout_period = 0xFFFF;
+    config->timeout_mode = CAN_TIMEOUT_CONTINUES;
+    config->timeout_enable = false;
+    config->tdc_enable = false;
+    config->delay_compensation_offset = 0;
+    config->delay_compensation_filter_window_length = 0;
+    config->nonmatching_frames_action_standard = CAN_NONMATCHING_FRAMES_REJECT;
+    config->nonmatching_frames_action_extended = CAN_NONMATCHING_FRAMES_REJECT;
+    config->remote_frames_standard_reject = true;
+    config->remote_frames_extended_reject = true;
+    config->extended_id_mask = 0x1FFFFFFF;
+    config->rx_fifo_0_overwrite = true;
+    config->rx_fifo_0_watermark = 0;
+    config->rx_fifo_1_overwrite = true;
+    config->rx_fifo_1_watermark = 0;
+    config->tx_queue_mode = false;
+    config->tx_event_fifo_watermark = 0;
 }
 
 
@@ -632,7 +632,7 @@ static inline void can_get_config_defaults(
  * \param[in]  config      Pointer to the configuration struct
  */
 void can_init(struct can_module *const module_inst, Can *hw,
-		struct can_config *config);
+        struct can_config *config);
 
 /**
  * \brief Set CAN baudrate.
@@ -690,7 +690,7 @@ void can_disable_fd_mode(struct can_module *const module_inst);
  * \param[in] module_inst  Pointer to the CAN software instance struct
  */
 void can_enable_restricted_operation_mode(
-		struct can_module *const module_inst);
+        struct can_module *const module_inst);
 
 /**
  * \brief Disable CAN restricted operation mode.
@@ -698,7 +698,7 @@ void can_enable_restricted_operation_mode(
  * \param[in] module_inst  Pointer to the CAN software instance struct
  */
 void can_disable_restricted_operation_mode(
-		struct can_module *const module_inst);
+        struct can_module *const module_inst);
 
 /**
  * \brief Enable CAN bus monitor mode.
@@ -756,9 +756,9 @@ void can_disable_test_mode(struct can_module *const module_inst);
  * \return Timestamp count value.
  */
 static inline uint16_t can_read_timestamp_count_value(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TSCV.bit.TSC;
+    return module_inst->hw->TSCV.bit.TSC;
 }
 
 /**
@@ -769,9 +769,9 @@ static inline uint16_t can_read_timestamp_count_value(
  * \return Timeout count value.
  */
 static inline uint16_t can_read_timeout_count_value(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TOCV.bit.TOC;
+    return module_inst->hw->TOCV.bit.TOC;
 }
 
 /**
@@ -782,9 +782,9 @@ static inline uint16_t can_read_timeout_count_value(
  * \return Error count value.
  */
 static inline uint32_t can_read_error_count(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->ECR.reg;
+    return module_inst->hw->ECR.reg;
 }
 
 /**
@@ -795,9 +795,9 @@ static inline uint32_t can_read_error_count(
  * \return protocol status value.
  */
 static inline uint32_t can_read_protocal_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->PSR.reg;
+    return module_inst->hw->PSR.reg;
 }
 
 /** @} */
@@ -815,9 +815,9 @@ static inline uint32_t can_read_protocal_status(
  * \return High priority message status value.
  */
 static inline uint32_t can_read_high_priority_message_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->HPMS.reg;
+    return module_inst->hw->HPMS.reg;
 }
 
 /**
@@ -832,22 +832,25 @@ static inline uint32_t can_read_high_priority_message_status(
  *  \retval false Rx Buffer not updated.
  */
 static inline bool can_rx_get_buffer_status(
-		struct can_module *const module_inst, uint32_t index)
+        struct can_module *const module_inst, uint32_t index)
 {
-	if (index < 32) {
-		if (module_inst->hw->NDAT1.reg & (1 << index)) {
-			return true;
-		} else {
-			return false;
-		}
-	} else {
-		index -= 32;
-		if (module_inst->hw->NDAT2.reg & (1 << index)) {
-			return true;
-		} else {
-			return false;
-		}
-	}
+    if (index < 32)
+    {
+        if (module_inst->hw->NDAT1.reg & (1 << index))
+        {
+            return true;
+        } else {
+            return false;
+        }
+    } else {
+        index -= 32;
+        if (module_inst->hw->NDAT2.reg & (1 << index))
+        {
+            return true;
+        } else {
+            return false;
+        }
+    }
 }
 
 /**
@@ -858,14 +861,15 @@ static inline bool can_rx_get_buffer_status(
  *
  */
 static inline void can_rx_clear_buffer_status(
-		struct can_module *const module_inst, uint32_t index)
+        struct can_module *const module_inst, uint32_t index)
 {
-	if (index < 32) {
-		module_inst->hw->NDAT1.reg = (1 << index);
-	} else {
-		index -= 32;
-		module_inst->hw->NDAT2.reg = (1 << index);
-	}
+    if (index < 32)
+    {
+        module_inst->hw->NDAT1.reg = (1 << index);
+    } else {
+        index -= 32;
+        module_inst->hw->NDAT2.reg = (1 << index);
+    }
 }
 
 /**
@@ -877,13 +881,14 @@ static inline void can_rx_clear_buffer_status(
  * \return Rx FIFO status value.
  */
 static inline uint32_t can_rx_get_fifo_status(
-		struct can_module *const module_inst, bool fifo_number)
+        struct can_module *const module_inst, bool fifo_number)
 {
-	if (!fifo_number) {
-		return module_inst->hw->RXF0S.reg;
-	} else {
-		return module_inst->hw->RXF1S.reg;
-	}
+    if (!fifo_number)
+    {
+        return module_inst->hw->RXF0S.reg;
+    } else {
+        return module_inst->hw->RXF1S.reg;
+    }
 }
 
 /**
@@ -894,13 +899,14 @@ static inline uint32_t can_rx_get_fifo_status(
  * \param[in] index  Index offset in FIFO
  */
 static inline void can_rx_fifo_acknowledge(
-		struct can_module *const module_inst, bool fifo_number, uint32_t index)
+        struct can_module *const module_inst, bool fifo_number, uint32_t index)
 {
-	if (!fifo_number) {
-		module_inst->hw->RXF0A.reg = CAN_RXF0A_F0AI(index);
-	} else {
-		module_inst->hw->RXF1A.reg = CAN_RXF1A_F1AI(index);
-	}
+    if (!fifo_number)
+    {
+        module_inst->hw->RXF0A.reg = CAN_RXF0A_F0AI(index);
+    } else {
+        module_inst->hw->RXF1A.reg = CAN_RXF1A_F1AI(index);
+    }
 }
 
 /**
@@ -915,13 +921,13 @@ static inline void can_rx_fifo_acknowledge(
  * \param[out] sd_filter  Pointer to standard filter element struct to initialize to default values
  */
 static inline void can_get_standard_message_filter_element_default(
-		struct can_standard_message_filter_element *sd_filter)
+        struct can_standard_message_filter_element *sd_filter)
 {
-	sd_filter->S0.reg = CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk |
-			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(0) |
-			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(
-			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val) |
-			CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC;
+    sd_filter->S0.reg = CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID2_Msk |
+            CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFID1(0) |
+            CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC(
+            CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFEC_STF0M_Val) |
+            CAN_STANDARD_MESSAGE_FILTER_ELEMENT_S0_SFT_CLASSIC;
 }
 
 /**
@@ -937,8 +943,8 @@ static inline void can_get_standard_message_filter_element_default(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_set_rx_standard_filter(
-		struct can_module *const module_inst,
-		struct can_standard_message_filter_element *sd_filter, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_standard_message_filter_element *sd_filter, uint32_t index);
 
 /**
  * \brief Get the extended message filter default value.
@@ -952,13 +958,13 @@ enum status_code can_set_rx_standard_filter(
  * \param[out] et_filter  Pointer to extended filter element struct to initialize to default values
  */
 static inline void can_get_extended_message_filter_element_default(
-		struct can_extended_message_filter_element *et_filter)
+        struct can_extended_message_filter_element *et_filter)
 {
-	et_filter->F0.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(0) |
-			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(
-			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val);
-	et_filter->F1.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk |
-			CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC;
+    et_filter->F0.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFID1(0) |
+            CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC(
+            CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F0_EFEC_STF1M_Val);
+    et_filter->F1.reg = CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFID2_Msk |
+            CAN_EXTENDED_MESSAGE_FILTER_ELEMENT_F1_EFT_CLASSIC;
 }
 
 /**
@@ -974,8 +980,8 @@ static inline void can_get_extended_message_filter_element_default(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_set_rx_extended_filter(
-		struct can_module *const module_inst,
-		struct can_extended_message_filter_element *et_filter, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_extended_message_filter_element *et_filter, uint32_t index);
 
 /**
  * \brief Get the pointer to the receive buffer element.
@@ -990,8 +996,8 @@ enum status_code can_set_rx_extended_filter(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_get_rx_buffer_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_buffer *rx_element, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_rx_element_buffer *rx_element, uint32_t index);
 
 /**
  * \brief Get the pointer to the receive FIFO 0 element.
@@ -1006,8 +1012,8 @@ enum status_code can_get_rx_buffer_element(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_get_rx_fifo_0_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_fifo_0 *rx_element, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_rx_element_fifo_0 *rx_element, uint32_t index);
 
 /**
  * \brief Get the pointer to the receive FIFO 1 element.
@@ -1022,8 +1028,8 @@ enum status_code can_get_rx_fifo_0_element(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_get_rx_fifo_1_element(
-		struct can_module *const module_inst,
-		struct can_rx_element_fifo_1 *rx_element, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_rx_element_fifo_1 *rx_element, uint32_t index);
 
 /** @} */
 
@@ -1040,9 +1046,9 @@ enum status_code can_get_rx_fifo_1_element(
  * \return Tx FIFO/Queue status value.
  */
 static inline uint32_t can_tx_get_fifo_queue_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TXFQS.reg;
+    return module_inst->hw->TXFQS.reg;
 }
 
 /**
@@ -1053,9 +1059,9 @@ static inline uint32_t can_tx_get_fifo_queue_status(
  * \return Bit mask of Tx buffer request pending status value.
  */
 static inline uint32_t can_tx_get_pending_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TXBRP.reg;
+    return module_inst->hw->TXBRP.reg;
 }
 
 /**
@@ -1070,13 +1076,14 @@ static inline uint32_t can_tx_get_pending_status(
  *  \retval STATUS_BUSY The module is in configuration.
  */
 static inline enum status_code can_tx_transfer_request(
-		struct can_module *const module_inst, uint32_t trig_mask)
+        struct can_module *const module_inst, uint32_t trig_mask)
 {
-	if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE) {
-		return STATUS_BUSY;
-	}
-	module_inst->hw->TXBAR.reg = trig_mask;
-	return STATUS_OK;
+    if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE)
+    {
+        return STATUS_BUSY;
+    }
+    module_inst->hw->TXBAR.reg = trig_mask;
+    return STATUS_OK;
 }
 
 /**
@@ -1091,13 +1098,14 @@ static inline enum status_code can_tx_transfer_request(
  *  \retval STATUS_BUSY The module is in configuration.
  */
 static inline enum status_code can_tx_cancel_request(
-		struct can_module *const module_inst, uint32_t trig_mask)
+        struct can_module *const module_inst, uint32_t trig_mask)
 {
-	if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE) {
-		return STATUS_BUSY;
-	}
-	module_inst->hw->TXBCR.reg = trig_mask;
-	return STATUS_OK;
+    if (module_inst->hw->CCCR.reg & CAN_CCCR_CCE)
+    {
+        return STATUS_BUSY;
+    }
+    module_inst->hw->TXBCR.reg = trig_mask;
+    return STATUS_OK;
 }
 
 /**
@@ -1108,9 +1116,9 @@ static inline enum status_code can_tx_cancel_request(
  * \return Bit mask of Tx transmission status value.
  */
 static inline uint32_t can_tx_get_transmission_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TXBTO.reg;
+    return module_inst->hw->TXBTO.reg;
 }
 
 /**
@@ -1121,9 +1129,9 @@ static inline uint32_t can_tx_get_transmission_status(
  * \return Bit mask of Tx cancellation status value.
  */
 static inline uint32_t can_tx_get_cancellation_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TXBCF.reg;
+    return module_inst->hw->TXBCF.reg;
 }
 
 /**
@@ -1134,9 +1142,9 @@ static inline uint32_t can_tx_get_cancellation_status(
  * \return Tx event FIFO status value.
  */
 static inline uint32_t can_tx_get_event_fifo_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->TXEFS.reg;
+    return module_inst->hw->TXEFS.reg;
 }
 
 /**
@@ -1146,9 +1154,9 @@ static inline uint32_t can_tx_get_event_fifo_status(
  * \param[in] index  Index for the transfer FIFO
  */
 static inline void can_tx_event_fifo_acknowledge(
-		struct can_module *const module_inst, uint32_t index)
+        struct can_module *const module_inst, uint32_t index)
 {
-	module_inst->hw->TXEFA.reg = CAN_TXEFA_EFAI(index);
+    module_inst->hw->TXEFA.reg = CAN_TXEFA_EFAI(index);
 }
 
 /**
@@ -1165,11 +1173,11 @@ static inline void can_tx_event_fifo_acknowledge(
  * \param[out] tx_element  Pointer to transfer element struct to initialize to default values
  */
 static inline void can_get_tx_buffer_element_defaults(
-		struct can_tx_element *tx_element)
+        struct can_tx_element *tx_element)
 {
-	tx_element->T0.reg = 0;
-	tx_element->T1.reg = CAN_TX_ELEMENT_T1_EFC |
-			CAN_TX_ELEMENT_T1_DLC(CAN_TX_ELEMENT_T1_DLC_DATA8_Val);
+    tx_element->T0.reg = 0;
+    tx_element->T1.reg = CAN_TX_ELEMENT_T1_EFC |
+            CAN_TX_ELEMENT_T1_DLC(CAN_TX_ELEMENT_T1_DLC_DATA8_Val);
 }
 
 /**
@@ -1185,8 +1193,8 @@ static inline void can_get_tx_buffer_element_defaults(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_set_tx_buffer_element(
-		struct can_module *const module_inst,
-		struct can_tx_element *tx_element, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_tx_element *tx_element, uint32_t index);
 
 /**
  * \brief Get the pointer to the transfer event FIFO element.
@@ -1201,8 +1209,8 @@ enum status_code can_set_tx_buffer_element(
  *  \retval STATUS_ERR_INVALID_ARG The parameter is not correct.
  */
 enum status_code can_get_tx_event_fifo_element(
-		struct can_module *const module_inst,
-		struct can_tx_event_element *tx_event_element, uint32_t index);
+        struct can_module *const module_inst,
+        struct can_tx_event_element *tx_event_element, uint32_t index);
 
 /** @} */
 
@@ -1217,66 +1225,66 @@ enum status_code can_get_tx_event_fifo_element(
  * Enum for the interrupt source.
  */
 enum can_interrupt_source {
-	/** Rx FIFO 0 New Message Interrupt Enable. */
-	CAN_RX_FIFO_0_NEW_MESSAGE = CAN_IE_RF0NE,
-	/** Rx FIFO 0 Watermark Reached Interrupt Enable. */
-	CAN_RX_FIFO_0_WATERMARK = CAN_IE_RF0WE,
-	/** Rx FIFO 0 Full Interrupt Enable. */
-	CAN_RX_FIFO_0_FULL = CAN_IE_RF0FE,
-	/** Rx FIFO 0 Message Lost Interrupt Enable. */
-	CAN_RX_FIFO_0_LOST_MESSAGE = CAN_IE_RF0LE,
-	/** Rx FIFO 1 New Message Interrupt Enable. */
-	CAN_RX_FIFO_1_NEW_MESSAGE = CAN_IE_RF1NE,
-	/** Rx FIFO 1 Watermark Reached Interrupt Enable. */
-	CAN_RX_FIFO_1_WATERMARK = CAN_IE_RF1WE,
-	/** Rx FIFO 1 Full Interrupt Enable. */
-	CAN_RX_FIFO_1_FULL = CAN_IE_RF1FE,
-	/** Rx FIFO 1 Message Lost Interrupt Enable. */
-	CAN_RX_FIFO_1_MESSAGE_LOST = CAN_IE_RF1LE,
-	/** High Priority Message Interrupt Enable. */
-	CAN_RX_HIGH_PRIORITY_MESSAGE = CAN_IE_HPME,
-	/** Timestamp Completed Interrupt Enable. */
-	CAN_TIMESTAMP_COMPLETE = CAN_IE_TCE,
-	/** Transmission Cancellation Finished Interrupt Enable. */
-	CAN_TX_CANCELLATION_FINISH = CAN_IE_TCFE,
-	/** Tx FIFO Empty Interrupt Enable. */
-	CAN_TX_FIFO_EMPTY = CAN_IE_TFEE,
-	/** Tx Event FIFO New Entry Interrupt Enable. */
-	CAN_TX_EVENT_FIFO_NEW_ENTRY = CAN_IE_TEFNE,
-	/** Tx Event FIFO Watermark Reached Interrupt Enable. */
-	CAN_TX_EVENT_FIFO_WATERMARK = CAN_IE_TEFWE,
-	/** Tx Event FIFO Full Interrupt Enable. */
-	CAN_TX_EVENT_FIFO_FULL = CAN_IE_TEFFE,
-	/** Tx Event FIFO Element Lost Interrupt Enable. */
-	CAN_TX_EVENT_FIFO_ELEMENT_LOST = CAN_IE_TEFLE,
-	/** Timestamp Wraparound Interrupt Enable. */
-	CAN_TIMESTAMP_WRAPAROUND = CAN_IE_TSWE,
-	/** Message RAM Access Failure Interrupt Enable. */
-	CAN_MESSAGE_RAM_ACCESS_FAILURE = CAN_IE_MRAFE,
-	/** Timeout Occurred Interrupt Enable. */
-	CAN_TIMEOUT_OCCURRED = CAN_IE_TOOE,
-	/** Message stored to Dedicated Rx Buffer Interrupt Enable. */
-	CAN_RX_BUFFER_NEW_MESSAGE = CAN_IE_DRXE,
-	/** Bit Error Corrected Interrupt Enable. */
-	CAN_BIT_ERROR_CORRECTED = CAN_IE_BECE,
-	/** Bit Error Uncorrected Interrupt Enable. */
-	CAN_BIT_ERROR_UNCORRECTED = CAN_IE_BEUE,
-	/** Error Logging Overflow Interrupt Enable. */
-	CAN_ERROR_LOGGING_OVERFLOW = CAN_IE_ELOE,
-	/** Error Passive Interrupt Enable. */
-	CAN_ERROR_PASSIVE = CAN_IE_EPE,
-	/** Warning Status Interrupt Enable. */
-	CAN_WARNING_STATUS = CAN_IE_EWE,
-	/** Bus_Off Status Interrupt Enable. */
-	CAN_BUS_OFF = CAN_IE_BOE,
-	/** Watchdog Interrupt Interrupt Enable. */
-	CAN_WATCHDOG = CAN_IE_WDIE,
-	/** Protocol Error in Arbitration Phase Enable. */
-	CAN_PROTOCOL_ERROR_ARBITRATION = CAN_IE_PEAE,
-	/** Protocol Error in Data Phase Enable. */
-	CAN_PROTOCOL_ERROR_DATA = CAN_IE_PEDE,
-	/** Access to Reserved Address Enable. */
-	CAN_ACCESS_RESERVED_ADDRESS = CAN_IE_ARAE,
+    /** Rx FIFO 0 New Message Interrupt Enable. */
+    CAN_RX_FIFO_0_NEW_MESSAGE = CAN_IE_RF0NE,
+    /** Rx FIFO 0 Watermark Reached Interrupt Enable. */
+    CAN_RX_FIFO_0_WATERMARK = CAN_IE_RF0WE,
+    /** Rx FIFO 0 Full Interrupt Enable. */
+    CAN_RX_FIFO_0_FULL = CAN_IE_RF0FE,
+    /** Rx FIFO 0 Message Lost Interrupt Enable. */
+    CAN_RX_FIFO_0_LOST_MESSAGE = CAN_IE_RF0LE,
+    /** Rx FIFO 1 New Message Interrupt Enable. */
+    CAN_RX_FIFO_1_NEW_MESSAGE = CAN_IE_RF1NE,
+    /** Rx FIFO 1 Watermark Reached Interrupt Enable. */
+    CAN_RX_FIFO_1_WATERMARK = CAN_IE_RF1WE,
+    /** Rx FIFO 1 Full Interrupt Enable. */
+    CAN_RX_FIFO_1_FULL = CAN_IE_RF1FE,
+    /** Rx FIFO 1 Message Lost Interrupt Enable. */
+    CAN_RX_FIFO_1_MESSAGE_LOST = CAN_IE_RF1LE,
+    /** High Priority Message Interrupt Enable. */
+    CAN_RX_HIGH_PRIORITY_MESSAGE = CAN_IE_HPME,
+    /** Timestamp Completed Interrupt Enable. */
+    CAN_TIMESTAMP_COMPLETE = CAN_IE_TCE,
+    /** Transmission Cancellation Finished Interrupt Enable. */
+    CAN_TX_CANCELLATION_FINISH = CAN_IE_TCFE,
+    /** Tx FIFO Empty Interrupt Enable. */
+    CAN_TX_FIFO_EMPTY = CAN_IE_TFEE,
+    /** Tx Event FIFO New Entry Interrupt Enable. */
+    CAN_TX_EVENT_FIFO_NEW_ENTRY = CAN_IE_TEFNE,
+    /** Tx Event FIFO Watermark Reached Interrupt Enable. */
+    CAN_TX_EVENT_FIFO_WATERMARK = CAN_IE_TEFWE,
+    /** Tx Event FIFO Full Interrupt Enable. */
+    CAN_TX_EVENT_FIFO_FULL = CAN_IE_TEFFE,
+    /** Tx Event FIFO Element Lost Interrupt Enable. */
+    CAN_TX_EVENT_FIFO_ELEMENT_LOST = CAN_IE_TEFLE,
+    /** Timestamp Wraparound Interrupt Enable. */
+    CAN_TIMESTAMP_WRAPAROUND = CAN_IE_TSWE,
+    /** Message RAM Access Failure Interrupt Enable. */
+    CAN_MESSAGE_RAM_ACCESS_FAILURE = CAN_IE_MRAFE,
+    /** Timeout Occurred Interrupt Enable. */
+    CAN_TIMEOUT_OCCURRED = CAN_IE_TOOE,
+    /** Message stored to Dedicated Rx Buffer Interrupt Enable. */
+    CAN_RX_BUFFER_NEW_MESSAGE = CAN_IE_DRXE,
+    /** Bit Error Corrected Interrupt Enable. */
+    CAN_BIT_ERROR_CORRECTED = CAN_IE_BECE,
+    /** Bit Error Uncorrected Interrupt Enable. */
+    CAN_BIT_ERROR_UNCORRECTED = CAN_IE_BEUE,
+    /** Error Logging Overflow Interrupt Enable. */
+    CAN_ERROR_LOGGING_OVERFLOW = CAN_IE_ELOE,
+    /** Error Passive Interrupt Enable. */
+    CAN_ERROR_PASSIVE = CAN_IE_EPE,
+    /** Warning Status Interrupt Enable. */
+    CAN_WARNING_STATUS = CAN_IE_EWE,
+    /** Bus_Off Status Interrupt Enable. */
+    CAN_BUS_OFF = CAN_IE_BOE,
+    /** Watchdog Interrupt Interrupt Enable. */
+    CAN_WATCHDOG = CAN_IE_WDIE,
+    /** Protocol Error in Arbitration Phase Enable. */
+    CAN_PROTOCOL_ERROR_ARBITRATION = CAN_IE_PEAE,
+    /** Protocol Error in Data Phase Enable. */
+    CAN_PROTOCOL_ERROR_DATA = CAN_IE_PEDE,
+    /** Access to Reserved Address Enable. */
+    CAN_ACCESS_RESERVED_ADDRESS = CAN_IE_ARAE,
 };
 
 /**
@@ -1286,9 +1294,9 @@ enum can_interrupt_source {
  * \param[in] source  Interrupt source type
  */
 static inline void can_enable_interrupt(struct can_module *const module_inst,
-		const enum can_interrupt_source source)
+        const enum can_interrupt_source source)
 {
-	module_inst->hw->IE.reg |= source;
+    module_inst->hw->IE.reg |= source;
 }
 
 /**
@@ -1298,9 +1306,9 @@ static inline void can_enable_interrupt(struct can_module *const module_inst,
  * \param[in] source  Interrupt source type
  */
 static inline void can_disable_interrupt(struct can_module *const module_inst,
-		const enum can_interrupt_source source)
+        const enum can_interrupt_source source)
 {
-	module_inst->hw->IE.reg &= ~source;
+    module_inst->hw->IE.reg &= ~source;
 }
 
 /**
@@ -1309,9 +1317,9 @@ static inline void can_disable_interrupt(struct can_module *const module_inst,
  * \param[in] module_inst  Pointer to the CAN software instance struct
  */
 static inline uint32_t can_read_interrupt_status(
-		struct can_module *const module_inst)
+        struct can_module *const module_inst)
 {
-	return module_inst->hw->IR.reg;
+    return module_inst->hw->IR.reg;
 }
 
 /**
@@ -1323,10 +1331,10 @@ static inline uint32_t can_read_interrupt_status(
  * \return Bit mask of interrupt status value.
  */
 static inline void can_clear_interrupt_status(
-		struct can_module *const module_inst,
-		const enum can_interrupt_source source)
+        struct can_module *const module_inst,
+        const enum can_interrupt_source source)
 {
-	module_inst->hw->IR.reg = source;
+    module_inst->hw->IR.reg = source;
 }
 
 /** @} */
@@ -1347,18 +1355,18 @@ static inline void can_clear_interrupt_status(
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>CAN</td>
- *		<td>Control Area Network (CAN) Controller</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
  *  <tr>
- *		<td>CAN FD</td>
- *		<td>CAN with Flexible Data-Rate</td>
- *	</tr>
+ *      <td>CAN</td>
+ *      <td>Control Area Network (CAN) Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>CAN FD</td>
+ *      <td>CAN with Flexible Data-Rate</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1377,12 +1385,12 @@ static inline void can_clear_interrupt_status(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1402,16 +1410,16 @@ static inline void can_clear_interrupt_status(
  * \page asfdoc_sam0_can_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>03/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>03/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h
index c70c0b623ab3..b010f17aa73a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/can/module_config/conf_can.h
@@ -50,25 +50,25 @@
  * Below is the message RAM setting, it will be stored in the system RAM.
  * Please adjust the message size according to your application.
  */
-#define CONF_CAN0_RX_FIFO_0_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN0_RX_FIFO_1_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN0_RX_BUFFER_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN0_TX_BUFFER_NUM         4             /* Range: 1..16 */ 
-#define CONF_CAN0_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */ 
-#define CONF_CAN0_TX_EVENT_FIFO         8             /* Range: 1..32 */ 
+#define CONF_CAN0_RX_FIFO_0_NUM         16            /* Range: 1..64 */
+#define CONF_CAN0_RX_FIFO_1_NUM         16            /* Range: 1..64 */
+#define CONF_CAN0_RX_BUFFER_NUM         16            /* Range: 1..64 */
+#define CONF_CAN0_TX_BUFFER_NUM         4             /* Range: 1..16 */
+#define CONF_CAN0_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */
+#define CONF_CAN0_TX_EVENT_FIFO         8             /* Range: 1..32 */
 
-#define CONF_CAN0_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */ 
-#define CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */ 
+#define CONF_CAN0_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */
+#define CONF_CAN0_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */
 
-#define CONF_CAN1_RX_FIFO_0_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN1_RX_FIFO_1_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN1_RX_BUFFER_NUM         16            /* Range: 1..64 */ 
-#define CONF_CAN1_TX_BUFFER_NUM         4             /* Range: 1..16 */ 
-#define CONF_CAN1_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */ 
-#define CONF_CAN1_TX_EVENT_FIFO         8             /* Range: 1..32 */ 
+#define CONF_CAN1_RX_FIFO_0_NUM         16            /* Range: 1..64 */
+#define CONF_CAN1_RX_FIFO_1_NUM         16            /* Range: 1..64 */
+#define CONF_CAN1_RX_BUFFER_NUM         16            /* Range: 1..64 */
+#define CONF_CAN1_TX_BUFFER_NUM         4             /* Range: 1..16 */
+#define CONF_CAN1_TX_FIFO_QUEUE_NUM     4             /* Range: 1..16 */
+#define CONF_CAN1_TX_EVENT_FIFO         8             /* Range: 1..32 */
 
-#define CONF_CAN1_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */ 
-#define CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */ 
+#define CONF_CAN1_RX_STANDARD_ID_FILTER_NUM     32    /* Range: 1..128 */
+#define CONF_CAN1_RX_EXTENDED_ID_FILTER_NUM     16    /* Range: 1..64 */
 
 /* The value should be 8/12/16/20/24/32/48/64. */
 #define CONF_CAN_ELEMENT_DATA_SIZE         8
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c
index abcf7d6c3e04..b0536779fb28 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.c
@@ -49,106 +49,111 @@
 void ccl_init(struct ccl_config *const config)
 {
 #if (SAML22) || (SAMC20) || (SAMC21)
-	/* Turn on the digital interface clock. */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_CCL);
+    /* Turn on the digital interface clock. */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_CCL);
 #else
-	/* Turn on the digital interface clock. */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_CCL);
+    /* Turn on the digital interface clock. */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_CCL);
 #endif
-	/* Reset module. */
-	ccl_module_reset();
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(CCL_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(CCL_GCLK_ID);
-
-	if(config->run_in_standby) {
-		/* Enable run in standy mode. */
-		CCL->CTRL.reg |= CCL_CTRL_RUNSTDBY;
-	} else {
-		/* Disable run in standy mode. */
-		CCL->CTRL.reg &= ~ CCL_CTRL_RUNSTDBY;
-	}
+    /* Reset module. */
+    ccl_module_reset();
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(CCL_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(CCL_GCLK_ID);
+
+    if(config->run_in_standby)
+    {
+        /* Enable run in standy mode. */
+        CCL->CTRL.reg |= CCL_CTRL_RUNSTDBY;
+    } else {
+        /* Disable run in standy mode. */
+        CCL->CTRL.reg &= ~ CCL_CTRL_RUNSTDBY;
+    }
 }
 
 void ccl_lut_get_config_defaults(struct ccl_lut_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->truth_table_value = 0x00;
-	config->event_output_enable = false;
-	config->event_input_enable = false;
-	config->event_input_inverted_enable = false;
-	config->input0_src_sel = CCL_LUT_INPUT_SRC_MASK;
-	config->input1_src_sel = CCL_LUT_INPUT_SRC_MASK;
-	config->input2_src_sel = CCL_LUT_INPUT_SRC_MASK;
-	config->edge_selection_enable = false;
-	config->filter_sel = CCL_LUT_FILTER_DISABLE;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->truth_table_value = 0x00;
+    config->event_output_enable = false;
+    config->event_input_enable = false;
+    config->event_input_inverted_enable = false;
+    config->input0_src_sel = CCL_LUT_INPUT_SRC_MASK;
+    config->input1_src_sel = CCL_LUT_INPUT_SRC_MASK;
+    config->input2_src_sel = CCL_LUT_INPUT_SRC_MASK;
+    config->edge_selection_enable = false;
+    config->filter_sel = CCL_LUT_FILTER_DISABLE;
 }
 
 enum status_code ccl_lut_set_config(const enum ccl_lut_id number,
-		struct ccl_lut_config *const config)
+        struct ccl_lut_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	uint32_t temp = 0;
-
-	if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
-		return STATUS_BUSY;
-
-	if (config->event_output_enable) {
-		temp |= CCL_LUTCTRL_LUTEO;
-	}
-
-	if (config->event_input_enable) {
-		temp |= CCL_LUTCTRL_LUTEI;
-	}
-
-	if (config->event_input_inverted_enable) {
-		temp |= CCL_LUTCTRL_INVEI;
-	}
-
-	if (config->edge_selection_enable) {
-		temp |= CCL_LUTCTRL_EDGESEL;
-	}
-
-	CCL->LUTCTRL[number].reg = temp |
-		CCL_LUTCTRL_INSEL0(config->input0_src_sel) |
-		CCL_LUTCTRL_INSEL1(config->input1_src_sel) |
-		CCL_LUTCTRL_INSEL2(config->input2_src_sel) |
-		CCL_LUTCTRL_TRUTH(config->truth_table_value) |
-		config->filter_sel;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(config);
+
+    uint32_t temp = 0;
+
+    if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
+        return STATUS_BUSY;
+
+    if (config->event_output_enable)
+    {
+        temp |= CCL_LUTCTRL_LUTEO;
+    }
+
+    if (config->event_input_enable)
+    {
+        temp |= CCL_LUTCTRL_LUTEI;
+    }
+
+    if (config->event_input_inverted_enable)
+    {
+        temp |= CCL_LUTCTRL_INVEI;
+    }
+
+    if (config->edge_selection_enable)
+    {
+        temp |= CCL_LUTCTRL_EDGESEL;
+    }
+
+    CCL->LUTCTRL[number].reg = temp |
+        CCL_LUTCTRL_INSEL0(config->input0_src_sel) |
+        CCL_LUTCTRL_INSEL1(config->input1_src_sel) |
+        CCL_LUTCTRL_INSEL2(config->input2_src_sel) |
+        CCL_LUTCTRL_TRUTH(config->truth_table_value) |
+        config->filter_sel;
+
+    return STATUS_OK;
 }
 
 enum status_code ccl_seq_config(const enum ccl_seq_id number,
-		const enum ccl_seq_selection seq_selection)
+        const enum ccl_seq_selection seq_selection)
 {
-	if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
-		return STATUS_BUSY;
+    if(CCL->CTRL.reg & CCL_CTRL_ENABLE)
+        return STATUS_BUSY;
 
-	CCL->SEQCTRL[number].reg = seq_selection;
+    CCL->SEQCTRL[number].reg = seq_selection;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 void ccl_lut_enable(const enum ccl_lut_id number)
 {
-	/* Enable the LUTx */
-	CCL->LUTCTRL[number].reg |= CCL_LUTCTRL_ENABLE;
+    /* Enable the LUTx */
+    CCL->LUTCTRL[number].reg |= CCL_LUTCTRL_ENABLE;
 }
 
 void ccl_lut_disable(const enum ccl_lut_id number)
 {
-	/* Disable the LUTx */
-	CCL->LUTCTRL[number].reg &= ~CCL_LUTCTRL_ENABLE;
+    /* Disable the LUTx */
+    CCL->LUTCTRL[number].reg &= ~CCL_LUTCTRL_ENABLE;
 }
 
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h
index b9294edd531c..2a8350e26b86 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/ccl/ccl.h
@@ -126,24 +126,24 @@ extern "C" {
  * \brief CCL LUT(look up table) ID number enum.
  */
 enum ccl_lut_id {
-	/** CCL LUT 0 */
-	CCL_LUT_0 = 0,
-	/** CCL LUT 1 */
-	CCL_LUT_1 = 1,
-	/** CCL LUT 2 */
-	CCL_LUT_2 = 2,
-	/** CCL LUT 3 */
-	CCL_LUT_3 = 3,
+    /** CCL LUT 0 */
+    CCL_LUT_0 = 0,
+    /** CCL LUT 1 */
+    CCL_LUT_1 = 1,
+    /** CCL LUT 2 */
+    CCL_LUT_2 = 2,
+    /** CCL LUT 3 */
+    CCL_LUT_3 = 3,
 };
 
 /**
  * \brief CCL sequential module ID number enum.
  */
 enum ccl_seq_id {
-	/** CCL SEQ 0 */
-	CCL_SEQ_0 = 0,
-	/** CCL SEQ 1 */
-	CCL_SEQ_1 = 1,
+    /** CCL SEQ 0 */
+    CCL_SEQ_0 = 0,
+    /** CCL SEQ 1 */
+    CCL_SEQ_1 = 1,
 };
 
 /**
@@ -152,16 +152,16 @@ enum ccl_seq_id {
  * Enum for the sequential selection configuration.
  */
 enum ccl_seq_selection {
-	/** Sequential logic is disabled */
-	CCL_SEQ_DISABLED = CCL_SEQCTRL_SEQSEL_DISABLE,
-	/** D flip flop */
-	CCL_SEQ_D_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_DFF,
-	/** JK flip flop */
-	CCL_SEQ_JK_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_JK,
-	/** D latch */
-	CCL_SEQ_D_LATCH = CCL_SEQCTRL_SEQSEL_LATCH,
-	/** RS latch */
-	CCL_SEQ_RS_LATCH = CCL_SEQCTRL_SEQSEL_RS,
+    /** Sequential logic is disabled */
+    CCL_SEQ_DISABLED = CCL_SEQCTRL_SEQSEL_DISABLE,
+    /** D flip flop */
+    CCL_SEQ_D_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_DFF,
+    /** JK flip flop */
+    CCL_SEQ_JK_FLIP_FLOP = CCL_SEQCTRL_SEQSEL_JK,
+    /** D latch */
+    CCL_SEQ_D_LATCH = CCL_SEQCTRL_SEQSEL_LATCH,
+    /** RS latch */
+    CCL_SEQ_RS_LATCH = CCL_SEQCTRL_SEQSEL_RS,
 };
 
 /**
@@ -170,26 +170,26 @@ enum ccl_seq_selection {
  * Enum for the LUT Input source selection.
  */
 enum ccl_lut_input_src_sel {
-	/** Masked input */
-	CCL_LUT_INPUT_SRC_MASK = 0,
-	/** Feedback input source */
-	CCL_LUT_INPUT_SRC_FEEDBACK = 1,
-	/** Linked LUT input source */
-	CCL_LUT_INPUT_SRC_LINK = 2,
-	/** Event input source */
-	CCL_LUT_INPUT_SRC_EVENT = 3,
-	/** I/O pin input source */
-	CCL_LUT_INPUT_SRC_IO = 4,
-	/** AC input source */
-	CCL_LUT_INPUT_SRC_AC = 5,
-	/** TC input source */
-	CCL_LUT_INPUT_SRC_TC = 6,
-	/** Alternative TC input source */
-	CCL_LUT_INPUT_SRC_ALTTC = 7,
-	/** TCC input source */
-	CCL_LUT_INPUT_SRC_TCC = 8,
-	/** SERCOM input source */
-	CCL_LUT_INPUT_SRC_SERCOM = 9,
+    /** Masked input */
+    CCL_LUT_INPUT_SRC_MASK = 0,
+    /** Feedback input source */
+    CCL_LUT_INPUT_SRC_FEEDBACK = 1,
+    /** Linked LUT input source */
+    CCL_LUT_INPUT_SRC_LINK = 2,
+    /** Event input source */
+    CCL_LUT_INPUT_SRC_EVENT = 3,
+    /** I/O pin input source */
+    CCL_LUT_INPUT_SRC_IO = 4,
+    /** AC input source */
+    CCL_LUT_INPUT_SRC_AC = 5,
+    /** TC input source */
+    CCL_LUT_INPUT_SRC_TC = 6,
+    /** Alternative TC input source */
+    CCL_LUT_INPUT_SRC_ALTTC = 7,
+    /** TCC input source */
+    CCL_LUT_INPUT_SRC_TCC = 8,
+    /** SERCOM input source */
+    CCL_LUT_INPUT_SRC_SERCOM = 9,
 };
 
 /**
@@ -198,12 +198,12 @@ enum ccl_lut_input_src_sel {
  * Enum for the LUT output filter options.
  */
 enum ccl_lut_filter_sel {
-	/** Filter disabled */
-	CCL_LUT_FILTER_DISABLE = CCL_LUTCTRL_FILTSEL_DISABLE,
-	/** Synchronizer enabled */
-	CCL_LUT_FILTER_SYNC = CCL_LUTCTRL_FILTSEL_SYNCH,
-	/** Filter enabled */
-	CCL_LUT_FILTER_ENABLE = CCL_LUTCTRL_FILTSEL_FILTER,
+    /** Filter disabled */
+    CCL_LUT_FILTER_DISABLE = CCL_LUTCTRL_FILTSEL_DISABLE,
+    /** Synchronizer enabled */
+    CCL_LUT_FILTER_SYNC = CCL_LUTCTRL_FILTSEL_SYNCH,
+    /** Filter enabled */
+    CCL_LUT_FILTER_ENABLE = CCL_LUTCTRL_FILTSEL_FILTER,
 };
 
 /**
@@ -212,10 +212,10 @@ enum ccl_lut_filter_sel {
  *  Configuration structure for CCL module.
  */
 struct ccl_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** If \c true, the GCLK_CCL clock will not stop in standby sleep mode */
-	bool run_in_standby;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** If \c true, the GCLK_CCL clock will not stop in standby sleep mode */
+    bool run_in_standby;
 };
 
 /**
@@ -224,24 +224,24 @@ struct ccl_config {
  *  Configuration structure for CCL LUT 0 to 3.
  */
 struct ccl_lut_config {
-	/**  The value of truth logic as a function of inputs IN[2:0] */
-	uint8_t truth_table_value;
-	/** If \c true, LUT event output is enabled */
-	bool event_output_enable;
-	/** If \c true, LUT incoming event is enabled */
-	bool event_input_enable;
-	/** If \c true, incoming event is inverted */
-	bool event_input_inverted_enable;
-	/** Selection of the input0 source */
-	enum ccl_lut_input_src_sel input0_src_sel;
-	/** Selection of the input1 source */
-	enum ccl_lut_input_src_sel input1_src_sel;
-	/** Selection of the input2 source */
-	enum ccl_lut_input_src_sel input2_src_sel;
-	/** If \c true, Edge detector is enabled */
-	bool edge_selection_enable;
-	/**  Selection of the LUT output filter options */
-	enum ccl_lut_filter_sel filter_sel;
+    /**  The value of truth logic as a function of inputs IN[2:0] */
+    uint8_t truth_table_value;
+    /** If \c true, LUT event output is enabled */
+    bool event_output_enable;
+    /** If \c true, LUT incoming event is enabled */
+    bool event_input_enable;
+    /** If \c true, incoming event is inverted */
+    bool event_input_inverted_enable;
+    /** Selection of the input0 source */
+    enum ccl_lut_input_src_sel input0_src_sel;
+    /** Selection of the input1 source */
+    enum ccl_lut_input_src_sel input1_src_sel;
+    /** Selection of the input2 source */
+    enum ccl_lut_input_src_sel input2_src_sel;
+    /** If \c true, Edge detector is enabled */
+    bool edge_selection_enable;
+    /**  Selection of the LUT output filter options */
+    enum ccl_lut_filter_sel filter_sel;
 };
 
 /**
@@ -273,14 +273,14 @@ void ccl_init(struct ccl_config *const config);
  *  \param[out] config  Configuration structure to initialize to default values
  */
 static inline void ccl_get_config_defaults(
-		struct ccl_config *const config)
+        struct ccl_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	config->clock_source = GCLK_GENERATOR_0;
-	/* Default configuration values */
-	config->run_in_standby = false;
+    config->clock_source = GCLK_GENERATOR_0;
+    /* Default configuration values */
+    config->run_in_standby = false;
 }
 
 /**
@@ -291,10 +291,10 @@ static inline void ccl_get_config_defaults(
  */
 static inline void ccl_module_reset(void)
 {
-	/* Reset CCL. */
-	CCL->CTRL.reg |= CCL_CTRL_SWRST;
+    /* Reset CCL. */
+    CCL->CTRL.reg |= CCL_CTRL_SWRST;
 
-	while((CCL->CTRL.reg & CCL_CTRL_SWRST));
+    while((CCL->CTRL.reg & CCL_CTRL_SWRST));
 }
 /** @} */
 
@@ -311,8 +311,8 @@ static inline void ccl_module_reset(void)
  */
 static inline void ccl_module_enable(void)
 {
-	/* Enable CCL. */
-	CCL->CTRL.reg |= CCL_CTRL_ENABLE;
+    /* Enable CCL. */
+    CCL->CTRL.reg |= CCL_CTRL_ENABLE;
 }
 
 /**
@@ -322,8 +322,8 @@ static inline void ccl_module_enable(void)
  */
 static inline void ccl_module_disable(void)
 {
-	/* Disable CCL. */
-	CCL->CTRL.reg &= ~CCL_CTRL_ENABLE;
+    /* Disable CCL. */
+    CCL->CTRL.reg &= ~CCL_CTRL_ENABLE;
 }
 
 /** @} */
@@ -344,7 +344,7 @@ static inline void ccl_module_disable(void)
  *  \param[in] number     SEQ unit number to config
  */
 enum status_code ccl_seq_config(const enum ccl_seq_id number,
-		const enum ccl_seq_selection seq_selection);
+        const enum ccl_seq_selection seq_selection);
 
 /**
  * \brief Initializes all members of LUT configuration
@@ -379,7 +379,7 @@ void ccl_lut_get_config_defaults(struct ccl_lut_config *const config);
  *  \param[in] number     LUT number to config
  */
 enum status_code ccl_lut_set_config(const enum ccl_lut_id number,
-		struct ccl_lut_config *const config);
+        struct ccl_lut_config *const config);
 /** @} */
 
 /**
@@ -423,14 +423,14 @@ void ccl_lut_disable(const enum ccl_lut_id number);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>CCL</td>
- *		<td>Configurable Custom Logic</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>CCL</td>
+ *      <td>Configurable Custom Logic</td>
+ *  </tr>
  * </table>
  *
  *
@@ -449,12 +449,12 @@ void ccl_lut_disable(const enum ccl_lut_id number);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -472,21 +472,21 @@ void ccl_lut_disable(const enum ccl_lut_id number);
  * \page asfdoc_sam0_ccl_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42448B</td>
- *		<td>08/2015</td>
- *		<td>Add support for SAM L22</td>
- *	</tr>
- *	<tr>
- *		<td>42448A</td>
- *		<td>06/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42448B</td>
+ *      <td>08/2015</td>
+ *      <td>Add support for SAM L22</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42448A</td>
+ *      <td>06/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h
index 1841b2fd0c3c..dcaa2604415a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac.h
@@ -89,19 +89,19 @@ typedef void (*dac_callback_t)(uint8_t channel);
 
 /** Enum for the possible callback types for the DAC module. */
 enum dac_callback {
-	/** Callback type for when a DAC channel data empty condition occurs
-	 *  (requires event triggered mode) */
-	DAC_CALLBACK_DATA_EMPTY,
+    /** Callback type for when a DAC channel data empty condition occurs
+     *  (requires event triggered mode) */
+    DAC_CALLBACK_DATA_EMPTY,
 
-	/** Callback type for when a DAC channel data underrun condition occurs
-	 *  (requires event triggered mode) */
-	DAC_CALLBACK_DATA_UNDERRUN,
+    /** Callback type for when a DAC channel data underrun condition occurs
+     *  (requires event triggered mode) */
+    DAC_CALLBACK_DATA_UNDERRUN,
 
-	/** Callback type for when a DAC channel write buffer job complete (requires
-	 *  event triggered mode) */
-	DAC_CALLBACK_TRANSFER_COMPLETE,
+    /** Callback type for when a DAC channel write buffer job complete (requires
+     *  event triggered mode) */
+    DAC_CALLBACK_TRANSFER_COMPLETE,
 #if !defined(__DOXYGEN__)
-	DAC_CALLBACK_N,
+    DAC_CALLBACK_N,
 #endif
 };
 
@@ -115,32 +115,32 @@ enum dac_callback {
  */
 
 bool dac_is_syncing(
-		struct dac_module *const dev_inst);
+        struct dac_module *const dev_inst);
 
 void dac_get_config_defaults(
-		struct dac_config *const config);
+        struct dac_config *const config);
 
 enum status_code dac_init(
-		struct dac_module *const dev_inst,
-		Dac *const module,
-		struct dac_config *const config);
+        struct dac_module *const dev_inst,
+        Dac *const module,
+        struct dac_config *const config);
 
 void dac_reset(
-		struct dac_module *const dev_inst);
+        struct dac_module *const dev_inst);
 
 void dac_enable(
-		struct dac_module *const dev_inst);
+        struct dac_module *const dev_inst);
 
 void dac_disable(
-		struct dac_module *const dev_inst);
+        struct dac_module *const dev_inst);
 
 void dac_enable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events);
+        struct dac_module *const module_inst,
+        struct dac_events *const events);
 
 void dac_disable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events);
+        struct dac_module *const module_inst,
+        struct dac_events *const events);
 
 /** @} */
 
@@ -150,20 +150,20 @@ void dac_disable_events(
  */
 
 void dac_chan_get_config_defaults(
-		struct dac_chan_config *const config);
+        struct dac_chan_config *const config);
 
 void dac_chan_set_config(
-		struct dac_module *const dev_inst,
-		const enum dac_channel channel,
-		struct dac_chan_config *const config);
+        struct dac_module *const dev_inst,
+        const enum dac_channel channel,
+        struct dac_chan_config *const config);
 
 void dac_chan_enable(
-		struct dac_module *const dev_inst,
-		enum dac_channel channel);
+        struct dac_module *const dev_inst,
+        enum dac_channel channel);
 
 void dac_chan_disable(
-		struct dac_module *const dev_inst,
-		enum dac_channel channel);
+        struct dac_module *const dev_inst,
+        enum dac_channel channel);
 
 /** @} */
 
@@ -173,15 +173,15 @@ void dac_chan_disable(
  */
 
 enum status_code dac_chan_write(
-		struct dac_module *const dev_inst,
-		enum dac_channel channel,
-		const uint16_t data);
+        struct dac_module *const dev_inst,
+        enum dac_channel channel,
+        const uint16_t data);
 
 enum status_code dac_chan_write_buffer_wait(
-		struct dac_module *const module_inst,
-		enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t length);
+        struct dac_module *const module_inst,
+        enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t length);
 
 /** @} */
 
@@ -190,10 +190,10 @@ enum status_code dac_chan_write_buffer_wait(
  * @{
  */
 uint32_t dac_get_status(
-		struct dac_module *const module_inst);
+        struct dac_module *const module_inst);
 void dac_clear_status(
-		struct dac_module *const module_inst,
-		uint32_t status_flags);
+        struct dac_module *const module_inst,
+        uint32_t status_flags);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h
index 0de73056b054..b0955b4fbb56 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_callback.h
@@ -63,26 +63,26 @@ extern "C" {
  * @{
  */
 enum status_code dac_chan_write_buffer_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t buffer_size);
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t buffer_size);
 
 enum status_code dac_chan_write_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t data);
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t data);
 
 enum status_code dac_register_callback(
-		struct dac_module *const module,
-		const enum dac_channel channel,
-		const dac_callback_t callback,
-		const enum dac_callback type);
+        struct dac_module *const module,
+        const enum dac_channel channel,
+        const dac_callback_t callback,
+        const enum dac_callback type);
 
 enum status_code dac_unregister_callback(
-		struct dac_module *const module,
-		const enum dac_channel channel,
-		const enum dac_callback type);
+        struct dac_module *const module,
+        const enum dac_channel channel,
+        const enum dac_callback type);
 
 /** @} */
 
@@ -91,22 +91,22 @@ enum status_code dac_unregister_callback(
  */
 
 enum status_code dac_chan_enable_callback(
-		struct dac_module *const module,
-		const enum dac_channel channel,
-		const enum dac_callback type);
+        struct dac_module *const module,
+        const enum dac_channel channel,
+        const enum dac_callback type);
 
 enum status_code dac_chan_disable_callback(
-		struct dac_module *const module,
-		const enum dac_channel channel,
-		const enum dac_callback type);
+        struct dac_module *const module,
+        const enum dac_channel channel,
+        const enum dac_callback type);
 
 enum status_code dac_chan_get_job_status(
-		struct dac_module *module_inst,
-		const enum dac_channel channel);
+        struct dac_module *module_inst,
+        const enum dac_channel channel);
 
 void dac_chan_abort_job(
-		struct dac_module *module_inst,
-		const enum dac_channel channel);
+        struct dac_module *module_inst,
+        const enum dac_channel channel);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c
index aa73badd3ab0..17fd9b12418f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac.c
@@ -57,56 +57,61 @@
  *
  */
 static void _dac_set_config(
-		struct dac_module *const module_inst,
-		struct dac_config *const config)
+        struct dac_module *const module_inst,
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(config);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(config);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Set selected DAC output to be enabled when enabling the module */
-	module_inst->output = config->output;
-	module_inst->start_on_event = false;
+    /* Set selected DAC output to be enabled when enabling the module */
+    module_inst->output = config->output;
+    module_inst->start_on_event = false;
 
-	uint32_t new_ctrla = 0;
-	uint32_t new_ctrlb = 0;
+    uint32_t new_ctrla = 0;
+    uint32_t new_ctrlb = 0;
 
-	/* Enable DAC in standby sleep mode if configured */
-	if (config->run_in_standby) {
-		new_ctrla |= DAC_CTRLA_RUNSTDBY;
-	}
+    /* Enable DAC in standby sleep mode if configured */
+    if (config->run_in_standby)
+    {
+        new_ctrla |= DAC_CTRLA_RUNSTDBY;
+    }
 
-	/* Set reference voltage */
-	new_ctrlb |= config->reference;
+    /* Set reference voltage */
+    new_ctrlb |= config->reference;
 
-	/* Left adjust data if configured */
-	if (config->left_adjust) {
-		new_ctrlb |= DAC_CTRLB_LEFTADJ;
-	}
+    /* Left adjust data if configured */
+    if (config->left_adjust)
+    {
+        new_ctrlb |= DAC_CTRLB_LEFTADJ;
+    }
 
 #ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
-	/* Bypass DATABUF write protection if configured */
-	if (config->databuf_protection_bypass) {
-		new_ctrlb |= DAC_CTRLB_BDWP;
-	}
+    /* Bypass DATABUF write protection if configured */
+    if (config->databuf_protection_bypass)
+    {
+        new_ctrlb |= DAC_CTRLB_BDWP;
+    }
 #endif
 
-	/* Voltage pump disable if configured */
-	if (config->voltage_pump_disable) {
-		new_ctrlb |= DAC_CTRLB_VPD;
-	}
+    /* Voltage pump disable if configured */
+    if (config->voltage_pump_disable)
+    {
+        new_ctrlb |= DAC_CTRLB_VPD;
+    }
 
-	/* Apply the new configuration to the hardware module */
-	dac_module->CTRLA.reg = new_ctrla;
+    /* Apply the new configuration to the hardware module */
+    dac_module->CTRLA.reg = new_ctrla;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	dac_module->CTRLB.reg = new_ctrlb;
+    dac_module->CTRLB.reg = new_ctrlb;
 }
 
 /**
@@ -126,22 +131,24 @@ static void _dac_set_config(
  * \retval false If the module has completed synchronization
  */
 bool dac_is_syncing(
-		struct dac_module *const dev_inst)
+        struct dac_module *const dev_inst)
 {
-	/* Sanity check arguments */
-	Assert(dev_inst);
+    /* Sanity check arguments */
+    Assert(dev_inst);
 
-	Dac *const dac_module = dev_inst->hw;
+    Dac *const dac_module = dev_inst->hw;
 
 #if (SAMC21)
-	if (dac_module->SYNCBUSY.reg) {
+    if (dac_module->SYNCBUSY.reg)
+    {
 #else
-	if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY) {
+    if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY)
+    {
 #endif
-		return true;
-	}
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -163,23 +170,23 @@ bool dac_is_syncing(
  * \param[out] config  Configuration structure to initialize to default values
  */
 void dac_get_config_defaults(
-		struct dac_config *const config)
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->reference      = DAC_REFERENCE_INT1V;
-	config->output         = DAC_OUTPUT_EXTERNAL;
-	config->left_adjust    = false;
+    /* Default configuration values */
+    config->reference      = DAC_REFERENCE_INT1V;
+    config->output         = DAC_OUTPUT_EXTERNAL;
+    config->left_adjust    = false;
 #ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
-	config->databuf_protection_bypass = false;
+    config->databuf_protection_bypass = false;
 #endif
-	config->voltage_pump_disable = false;
-	config->clock_source   = GCLK_GENERATOR_0;
-	config->run_in_standby = false;
+    config->voltage_pump_disable = false;
+    config->clock_source   = GCLK_GENERATOR_0;
+    config->run_in_standby = false;
 #if (SAMC21)
-	config->dither_mode    = false;
+    config->dither_mode    = false;
 #endif
 }
 
@@ -202,67 +209,70 @@ void dac_get_config_defaults(
  * \retval STATUS_BUSY        If module is busy resetting
  */
 enum status_code dac_init(
-		struct dac_module *const module_inst,
-		Dac *const module,
-		struct dac_config *const config)
+        struct dac_module *const module_inst,
+        Dac *const module,
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module);
+    Assert(config);
 
-	/* Initialize device instance */
-	module_inst->hw = module;
+    /* Initialize device instance */
+    module_inst->hw = module;
 
-	/* Turn on the digital interface clock */
+    /* Turn on the digital interface clock */
 #if (SAMC21)
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC);
 #endif
 
-	/* Check if module is enabled. */
-	if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress. */
-	if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(DAC_GCLK_ID);
-
-	/* MUX the DAC VOUT pin */
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	/* Set up the DAC VOUT pin */
-	pin_conf.mux_position = MUX_PA02B_DAC_VOUT;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-	system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf);
-
-	/* Write configuration to module */
-	_dac_set_config(module_inst, config);
-
-	/* Store reference selection for later use */
-	module_inst->reference = config->reference;
+    /* Check if module is enabled. */
+    if (module->CTRLA.reg & DAC_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress. */
+    if (module->CTRLA.reg & DAC_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(DAC_GCLK_ID);
+
+    /* MUX the DAC VOUT pin */
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    /* Set up the DAC VOUT pin */
+    pin_conf.mux_position = MUX_PA02B_DAC_VOUT;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+    system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf);
+
+    /* Write configuration to module */
+    _dac_set_config(module_inst, config);
+
+    /* Store reference selection for later use */
+    module_inst->reference = config->reference;
 
 #if DAC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < DAC_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	};
+    for (uint8_t i = 0; i < DAC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    };
 
-	_dac_instances[0] = module_inst;
+    _dac_instances[0] = module_inst;
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -274,20 +284,21 @@ enum status_code dac_init(
  * \param[in] module_inst  Pointer to the DAC software instance struct
  */
 void dac_reset(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Software reset the module */
-	dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
+    /* Software reset the module */
+    dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
 }
 
 /**
@@ -300,37 +311,41 @@ void dac_reset(
  *
  */
 void dac_enable(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Enable selected output */
-	dac_module->CTRLB.reg |= module_inst->output;
+    /* Enable selected output */
+    dac_module->CTRLB.reg |= module_inst->output;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Enable the module */
-	dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
+    /* Enable the module */
+    dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
 
-	/* Enable internal bandgap reference if selected in the configuration */
-	if (module_inst->reference == DAC_REFERENCE_INT1V) {
+    /* Enable internal bandgap reference if selected in the configuration */
+    if (module_inst->reference == DAC_REFERENCE_INT1V)
+    {
 #if (SAMC21)
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
-	}
-
-	if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE) {
-		while(! (dac_module->STATUS.reg & DAC_STATUS_READY)) {
-		};
-	}
+        system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+    }
+
+    if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE)
+    {
+        while(! (dac_module->STATUS.reg & DAC_STATUS_READY))
+        {
+        };
+    }
 #else
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
-	}
+        system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
+    }
 
 #endif
 }
@@ -344,25 +359,26 @@ void dac_enable(
  *
  */
 void dac_disable(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Wait until the synchronization is complete */
-	while (dac_is_syncing(module_inst)) {
-	};
+    /* Wait until the synchronization is complete */
+    while (dac_is_syncing(module_inst))
+    {
+    };
 
-	/* Disbale interrupt */
-	dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
 
-	/* Disable DAC */
-	dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+    /* Disable DAC */
+    dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
 }
 
 /**
@@ -377,37 +393,40 @@ void dac_disable(
  *  \param[in] events       Struct containing flags of events to enable
  */
 void dac_enable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events)
+        struct dac_module *const module_inst,
+        struct dac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
 #if(SAMC21)
-	/* Configure Enable Inversion of input event */
-	if (events->generate_event_on_chan_falling_edge) {
-		event_mask |= DAC_EVCTRL_INVEI;
-	}
+    /* Configure Enable Inversion of input event */
+    if (events->generate_event_on_chan_falling_edge)
+    {
+        event_mask |= DAC_EVCTRL_INVEI;
+    }
 #endif
 
-	/* Configure Buffer Empty event */
-	if (events->generate_event_on_buffer_empty) {
-		event_mask |= DAC_EVCTRL_EMPTYEO;
-	}
+    /* Configure Buffer Empty event */
+    if (events->generate_event_on_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO;
+    }
 
-	/* Configure Conversion Start event */
-	if (events->on_event_start_conversion) {
-		event_mask |= DAC_EVCTRL_STARTEI;
-		module_inst->start_on_event = true;
-	}
+    /* Configure Conversion Start event */
+    if (events->on_event_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI;
+        module_inst->start_on_event = true;
+    }
 
-	dac_module->EVCTRL.reg |= event_mask;
+    dac_module->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -422,30 +441,32 @@ void dac_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 void dac_disable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events)
+        struct dac_module *const module_inst,
+        struct dac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Buffer Empty event */
-	if (events->generate_event_on_buffer_empty) {
-		event_mask |= DAC_EVCTRL_EMPTYEO;
-	}
+    /* Configure Buffer Empty event */
+    if (events->generate_event_on_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO;
+    }
 
-	/* Configure Conversion Start event */
-	if (events->on_event_start_conversion) {
-		event_mask |= DAC_EVCTRL_STARTEI;
-		module_inst->start_on_event = false;
-	}
+    /* Configure Conversion Start event */
+    if (events->on_event_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI;
+        module_inst->start_on_event = false;
+    }
 
-	dac_module->EVCTRL.reg &= ~event_mask;
+    dac_module->EVCTRL.reg &= ~event_mask;
 }
 
 /**
@@ -463,10 +484,10 @@ void dac_disable_events(
  * \param[out] config  Configuration structure to initialize to default values
  */
 void dac_chan_get_config_defaults(
-		struct dac_chan_config *const config)
+        struct dac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 }
 
 /**
@@ -483,12 +504,12 @@ void dac_chan_get_config_defaults(
  *
  */
 void dac_chan_set_config(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		struct dac_chan_config *const config)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        struct dac_chan_config *const config)
 {
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 }
 
 /**
@@ -501,11 +522,11 @@ void dac_chan_set_config(
  *
  */
 void dac_chan_enable(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 }
 
 /**
@@ -518,11 +539,11 @@ void dac_chan_enable(
  *
  */
 void dac_chan_disable(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 }
 
 /**
@@ -534,20 +555,20 @@ void dac_chan_disable(
  * \param[in] channel      DAC channel to alter
  */
 void dac_chan_enable_output_buffer(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Enable output buffer */
-	dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL;
+    /* Enable output buffer */
+    dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL;
 }
 
 /**
@@ -563,20 +584,20 @@ void dac_chan_enable_output_buffer(
  * \param[in] channel      DAC channel to alter
  */
 void dac_chan_disable_output_buffer(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* Sanity check arguments*/
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments*/
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Disable output buffer */
-	dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL;
+    /* Disable output buffer */
+    dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL;
 }
 
 /**
@@ -601,32 +622,34 @@ void dac_chan_disable_output_buffer(
  * \retval STATUS_OK           If the data was written
  */
 enum status_code dac_chan_write(
-		struct dac_module *const module_inst,
-		enum dac_channel channel,
-		const uint16_t data)
+        struct dac_module *const module_inst,
+        enum dac_channel channel,
+        const uint16_t data)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* No channel support yet */
-	UNUSED(channel);
-
-	Dac *const dac_module = module_inst->hw;
-
-	/* Wait until the synchronization is complete */
-	while (dac_is_syncing(module_inst)) {
-	};
-
-	if (module_inst->start_on_event) {
-		/* Write the new value to the buffered DAC data register */
-		dac_module->DATABUF.reg = data;
-	} else {
-		/* Write the new value to the DAC data register */
-		dac_module->DATA.reg = data;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* No channel support yet */
+    UNUSED(channel);
+
+    Dac *const dac_module = module_inst->hw;
+
+    /* Wait until the synchronization is complete */
+    while (dac_is_syncing(module_inst))
+    {
+    };
+
+    if (module_inst->start_on_event)
+    {
+        /* Write the new value to the buffered DAC data register */
+        dac_module->DATABUF.reg = data;
+    } else {
+        /* Write the new value to the DAC data register */
+        dac_module->DATA.reg = data;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -652,58 +675,66 @@ enum status_code dac_chan_write(
  * \retval STATUS_BUSY                 The DAC is busy to convert
  */
 enum status_code dac_chan_write_buffer_wait(
-		struct dac_module *const module_inst,
-		enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t length)
+        struct dac_module *const module_inst,
+        enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t length)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* No channel support yet */
-	UNUSED(channel);
+    /* No channel support yet */
+    UNUSED(channel);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Wait until the synchronization is complete */
-	while (dac_is_syncing(module_inst)) {
-	};
+    /* Wait until the synchronization is complete */
+    while (dac_is_syncing(module_inst))
+    {
+    };
 
-	/* Zero length request */
-	if (length == 0) {
-		/* No data to be converted */
-		return STATUS_OK;
-	}
+    /* Zero length request */
+    if (length == 0)
+    {
+        /* No data to be converted */
+        return STATUS_OK;
+    }
 
 #if DAC_CALLBACK_MODE == true
-	/* Check if busy */
-	if (module_inst->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if busy */
+    if (module_inst->job_status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	/* Only support event triggered conversion */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	/* Blocks while buffer is being transferred */
-	while (length--) {
-		/* Convert one data */
-		dac_chan_write(module_inst, channel, buffer[length]);
-
-		/* Wait until Transmit is complete or timeout */
-		for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
-			if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY) {
-				break;
-			} else if (i == DAC_TIMEOUT) {
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-	}
-
-	return STATUS_OK;
+    /* Only support event triggered conversion */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    /* Blocks while buffer is being transferred */
+    while (length--)
+    {
+        /* Convert one data */
+        dac_chan_write(module_inst, channel, buffer[length]);
+
+        /* Wait until Transmit is complete or timeout */
+        for (uint32_t i = 0; i <= DAC_TIMEOUT; i++)
+        {
+            if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY)
+            {
+                break;
+            } else if (i == DAC_TIMEOUT)
+            {
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -724,26 +755,28 @@ enum status_code dac_chan_write_buffer_wait(
  *
  */
 uint32_t dac_get_status(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint8_t intflags = dac_module->INTFLAG.reg;
-	uint32_t status_flags = 0;
+    uint8_t intflags = dac_module->INTFLAG.reg;
+    uint32_t status_flags = 0;
 
-	if (intflags & DAC_INTFLAG_EMPTY) {
-		status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
-	}
+    if (intflags & DAC_INTFLAG_EMPTY)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
+    }
 
-	if (intflags & DAC_INTFLAG_UNDERRUN) {
-		status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
-	}
+    if (intflags & DAC_INTFLAG_UNDERRUN)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
+    }
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -756,24 +789,26 @@ uint32_t dac_get_status(
  *
  */
 void dac_clear_status(
-		struct dac_module *const module_inst,
-		uint32_t status_flags)
+        struct dac_module *const module_inst,
+        uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint32_t intflags = 0;
+    uint32_t intflags = 0;
 
-	if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
-		intflags |= DAC_INTFLAG_EMPTY;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY)
+    {
+        intflags |= DAC_INTFLAG_EMPTY;
+    }
 
-	if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
-		intflags |= DAC_INTFLAG_UNDERRUN;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN)
+    {
+        intflags |= DAC_INTFLAG_UNDERRUN;
+    }
 
-	dac_module->INTFLAG.reg = intflags;
+    dac_module->INTFLAG.reg = intflags;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c
index 24542cc74b91..dce66473db99 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_callback.c
@@ -73,47 +73,50 @@ struct dac_module *_dac_instances[DAC_INST_NUM];
  * \retval STATUS_BUSY      The DAC is busy to accept new job
  */
 enum status_code dac_chan_write_buffer_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t length)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t length)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(buffer);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(buffer);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	if(module_inst->remaining_conversions != 0 ||
-			module_inst->job_status == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
+    if(module_inst->remaining_conversions != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	/* Wait until the synchronization is complete */
-	while (dac_is_syncing(module_inst)) {
-	};
+    /* Wait until the synchronization is complete */
+    while (dac_is_syncing(module_inst))
+    {
+    };
 
-	module_inst->job_status = STATUS_BUSY;
+    module_inst->job_status = STATUS_BUSY;
 
-	module_inst->remaining_conversions = length;
-	module_inst->job_buffer = buffer;
-	module_inst->transferred_conversions = 0;
+    module_inst->remaining_conversions = length;
+    module_inst->job_buffer = buffer;
+    module_inst->transferred_conversions = 0;
 
-	/* Enable interrupt */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
-	dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
-	dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN | DAC_INTENSET_EMPTY;
+    /* Enable interrupt */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
+    dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
+    dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN | DAC_INTENSET_EMPTY;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -140,30 +143,32 @@ enum status_code dac_chan_write_buffer_job(
  * \retval STATUS_BUSY      The DAC is busy to accept new job
  */
 enum status_code dac_chan_write_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t data)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t data)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	if(module_inst->remaining_conversions != 0 ||
-			module_inst->job_status == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
+    if(module_inst->remaining_conversions != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	dac_chan_write_buffer_job(module_inst, channel, &data, 1);
+    dac_chan_write_buffer_job(module_inst, channel, &data, 1);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -185,29 +190,31 @@ enum status_code dac_chan_write_job(
  *                                     configured in non-event mode
  */
 enum status_code dac_register_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const dac_callback_t callback,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const dac_callback_t callback,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback);
-
-	UNUSED(channel);
-
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if ((uint8_t)type < DAC_CALLBACK_N) {
-		module_inst->callback[(uint8_t)type] = callback;
-		return STATUS_OK;
-	}
-
-	return STATUS_ERR_INVALID_ARG;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback);
+
+    UNUSED(channel);
+
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if ((uint8_t)type < DAC_CALLBACK_N)
+    {
+        module_inst->callback[(uint8_t)type] = callback;
+        return STATUS_OK;
+    }
+
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -228,27 +235,29 @@ enum status_code dac_register_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_unregister_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	if ((uint8_t)type < DAC_CALLBACK_N) {
-		module_inst->callback[(uint8_t)type] = NULL;
-		return STATUS_OK;
-	}
+    if ((uint8_t)type < DAC_CALLBACK_N)
+    {
+        module_inst->callback[(uint8_t)type] = NULL;
+        return STATUS_OK;
+    }
 
-	return STATUS_ERR_INVALID_ARG;
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -268,24 +277,25 @@ enum status_code dac_unregister_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_chan_enable_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	module_inst->callback_enable[type] = true;
+    module_inst->callback_enable[type] = true;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -304,24 +314,25 @@ enum status_code dac_chan_enable_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_chan_disable_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	module_inst->callback_enable[type] = false;
+    module_inst->callback_enable[type] = false;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \internal
@@ -331,58 +342,65 @@ enum status_code dac_chan_disable_callback(
  */
 static void _dac_interrupt_handler(const uint8_t instance)
 {
-	struct dac_module *module = _dac_instances[instance];
-	Dac *const dac_hw = module->hw;
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CALLBACK_DATA_UNDERRUN])){
-			module->callback[DAC_CALLBACK_DATA_UNDERRUN](0);
-		}
-	}
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
-
-		/* If in a write buffer job */
-		if (module->remaining_conversions) {
-
-			/* Fill the data buffer with next data in write buffer */
-			dac_hw->DATABUF.reg =
-				module->job_buffer[module->transferred_conversions++];
-
-			/* Write buffer size decrement */
-			module->remaining_conversions --;
-
-			/* If in a write buffer job and all the data are converted */
-			if (module->remaining_conversions == 0) {
-				module->job_status = STATUS_OK;
-
-				/* Disable interrupt */
-				dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY;
-				dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
-				system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
-
-				if ((module->callback) &&
-					 (module->callback_enable[DAC_CALLBACK_TRANSFER_COMPLETE])) {
-					module->callback[DAC_CALLBACK_TRANSFER_COMPLETE](0);
-				}
-			}
-		}
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CALLBACK_DATA_EMPTY])) {
-			module->callback[DAC_CALLBACK_DATA_EMPTY](0);
-		}
-	}
+    struct dac_module *module = _dac_instances[instance];
+    Dac *const dac_hw = module->hw;
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN;
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CALLBACK_DATA_UNDERRUN]))
+             {
+            module->callback[DAC_CALLBACK_DATA_UNDERRUN](0);
+        }
+    }
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+
+        /* If in a write buffer job */
+        if (module->remaining_conversions)
+        {
+
+            /* Fill the data buffer with next data in write buffer */
+            dac_hw->DATABUF.reg =
+                module->job_buffer[module->transferred_conversions++];
+
+            /* Write buffer size decrement */
+            module->remaining_conversions --;
+
+            /* If in a write buffer job and all the data are converted */
+            if (module->remaining_conversions == 0)
+            {
+                module->job_status = STATUS_OK;
+
+                /* Disable interrupt */
+                dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY;
+                dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY;
+                system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+                if ((module->callback) &&
+                     (module->callback_enable[DAC_CALLBACK_TRANSFER_COMPLETE]))
+                     {
+                    module->callback[DAC_CALLBACK_TRANSFER_COMPLETE](0);
+                }
+            }
+        }
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CALLBACK_DATA_EMPTY]))
+             {
+            module->callback[DAC_CALLBACK_DATA_EMPTY](0);
+        }
+    }
 }
 
 /** Handler for the DAC hardware module interrupt. */
 void DAC_Handler(void)
 {
-	_dac_interrupt_handler(0);
+    _dac_interrupt_handler(0);
 }
 
 /**
@@ -396,15 +414,15 @@ void DAC_Handler(void)
  * \return Status of the job.
  */
 enum status_code dac_chan_get_job_status(
-		struct dac_module *module_inst,
-		const enum dac_channel channel)
+        struct dac_module *module_inst,
+        const enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	return module_inst->job_status;
+    return module_inst->job_status;
 }
 
 /**
@@ -416,20 +434,20 @@ enum status_code dac_chan_get_job_status(
  * \param[in]  channel     Logical channel to enable callback function
  */
 void dac_chan_abort_job(
-		struct dac_module *module_inst,
-		const enum dac_channel channel)
+        struct dac_module *module_inst,
+        const enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* Disable interrupt */
-	module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
-	module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN | DAC_INTENCLR_EMPTY;
+    /* Disable interrupt */
+    module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY;
+    module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN | DAC_INTENCLR_EMPTY;
 
-	/* Mark job as aborted */
-	module_inst->job_status = STATUS_ABORTED;
-	module_inst->remaining_conversions = 0;
+    /* Mark job as aborted */
+    module_inst->job_status = STATUS_ABORTED;
+    module_inst->remaining_conversions = 0;
 
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h
index 3718e557d323..0e3ab0e86015 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_d_c_h/dac_feature.h
@@ -342,12 +342,12 @@ extern "C" {
  * Enum for the possible reference voltages for the DAC.
  */
 enum dac_reference {
-	/** 1V from the internal band-gap reference*/
-	DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0),
-	/** Analog V<SUB>CC</SUB> as reference */
-	DAC_REFERENCE_AVCC  = DAC_CTRLB_REFSEL(1),
-	/** External reference on AREF */
-	DAC_REFERENCE_AREF  = DAC_CTRLB_REFSEL(2),
+    /** 1V from the internal band-gap reference*/
+    DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0),
+    /** Analog V<SUB>CC</SUB> as reference */
+    DAC_REFERENCE_AVCC  = DAC_CTRLB_REFSEL(1),
+    /** External reference on AREF */
+    DAC_REFERENCE_AREF  = DAC_CTRLB_REFSEL(2),
 };
 
 /**
@@ -356,12 +356,12 @@ enum dac_reference {
  * Enum for the DAC output selection.
  */
 enum dac_output {
-	/** DAC output to VOUT pin */
-	DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN,
-	/** DAC output as internal reference */
-	DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN,
-	/** No output */
-	DAC_OUTPUT_NONE     = 0,
+    /** DAC output to VOUT pin */
+    DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN,
+    /** DAC output as internal reference */
+    DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN,
+    /** No output */
+    DAC_OUTPUT_NONE     = 0,
 };
 
 /**
@@ -370,8 +370,8 @@ enum dac_output {
  * Enum for the DAC channel selection.
  */
 enum dac_channel {
-	/** DAC output channel 0 */
-	DAC_CHANNEL_0,
+    /** DAC output channel 0 */
+    DAC_CHANNEL_0,
 };
 
 /**
@@ -385,27 +385,27 @@ enum dac_channel {
  */
 struct dac_module {
 #if !defined(__DOXYGEN__)
-	/** DAC hardware module */
-	Dac *hw;
-	/** DAC output selection */
-	enum dac_output output;
-	/** Reference selection */
-	enum dac_reference reference;
-	/** DAC event selection */
-	bool start_on_event;
+    /** DAC hardware module */
+    Dac *hw;
+    /** DAC output selection */
+    enum dac_output output;
+    /** Reference selection */
+    enum dac_reference reference;
+    /** DAC event selection */
+    bool start_on_event;
 #  if DAC_CALLBACK_MODE == true
-	/** Pointer to buffer used for ADC results */
-	volatile uint16_t *job_buffer;
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions;
-	/** Transferred number of conversions in current job */
-	volatile uint16_t transferred_conversions;
-	/** DAC callback enable */
-	bool callback_enable[DAC_CALLBACK_N];
-	/** DAC registered callback functions */
-	dac_callback_t callback[DAC_CALLBACK_N];
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status;
+    /** Pointer to buffer used for ADC results */
+    volatile uint16_t *job_buffer;
+    /** Remaining number of conversions in current job */
+    volatile uint16_t remaining_conversions;
+    /** Transferred number of conversions in current job */
+    volatile uint16_t transferred_conversions;
+    /** DAC callback enable */
+    bool callback_enable[DAC_CALLBACK_N];
+    /** DAC registered callback functions */
+    dac_callback_t callback[DAC_CALLBACK_N];
+    /** Holds the status of the ongoing or last conversion job */
+    volatile enum status_code job_status;
 #  endif
 #endif
 };
@@ -418,28 +418,28 @@ struct dac_module {
  * function before being modified by the user application.
  */
 struct dac_config {
-	/** Reference voltage */
-	enum dac_reference reference;
-	/** Select DAC output */
-	enum dac_output output;
-	/** Left adjusted data */
-	bool left_adjust;
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
+    /** Reference voltage */
+    enum dac_reference reference;
+    /** Select DAC output */
+    enum dac_output output;
+    /** Left adjusted data */
+    bool left_adjust;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
 #ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
-	/** Bypass DATABUF write protection */
-	bool databuf_protection_bypass;
+    /** Bypass DATABUF write protection */
+    bool databuf_protection_bypass;
 #endif
-	/** Voltage pump disable */
-	bool voltage_pump_disable;
-	/**
-	 * The DAC behaves as in normal mode when the chip enters STANDBY sleep
-	 * mode
-	 */
-	bool run_in_standby;
+    /** Voltage pump disable */
+    bool voltage_pump_disable;
+    /**
+     * The DAC behaves as in normal mode when the chip enters STANDBY sleep
+     * mode
+     */
+    bool run_in_standby;
 #if (SAMC21)
-	/** Dither mode enable data */
-	bool dither_mode;
+    /** Dither mode enable data */
+    bool dither_mode;
 #endif
 };
 
@@ -450,13 +450,13 @@ struct dac_config {
  * disable events via \ref dac_enable_events() and \ref dac_disable_events().
  */
 struct dac_events {
-	/** Start a new DAC conversion */
-	bool on_event_start_conversion;
-	/** Enable event generation on data buffer empty */
-	bool generate_event_on_buffer_empty;
+    /** Start a new DAC conversion */
+    bool on_event_start_conversion;
+    /** Enable event generation on data buffer empty */
+    bool generate_event_on_buffer_empty;
 #if (SAMC21)
-	/** Enable the falling edge of the input event for DAC1 */
-	bool generate_event_on_chan_falling_edge;
+    /** Enable the falling edge of the input event for DAC1 */
+    bool generate_event_on_chan_falling_edge;
 #endif
 };
 
@@ -469,8 +469,8 @@ struct dac_events {
  */
 struct dac_chan_config {
 #if !defined(__DOXYGEN__)
-	/** Dummy value to ensure the struct has at least one member */
-	uint8_t _dummy;
+    /** Dummy value to ensure the struct has at least one member */
+    uint8_t _dummy;
 #endif
 };
 
@@ -480,12 +480,12 @@ struct dac_chan_config {
  */
 
 void dac_chan_enable_output_buffer(
-		struct dac_module *const dev_inst,
-		const enum dac_channel channel);
+        struct dac_module *const dev_inst,
+        const enum dac_channel channel);
 
 void dac_chan_disable_output_buffer(
-		struct dac_module *const dev_inst,
-		const enum dac_channel channel);
+        struct dac_module *const dev_inst,
+        const enum dac_channel channel);
 
 /** @} */
 
@@ -498,34 +498,34 @@ void dac_chan_disable_output_buffer(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
- *	<tr>
- *		<td>AC</td>
- *		<td>Analog Comparator</td>
- *	</tr>
- *	<tr>
- *		<td>DAC</td>
- *		<td>Digital-to-Analog Converter</td>
- *	</tr>
- *	<tr>
- *		<td>LSB</td>
- *		<td>Least Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>MSB</td>
- *		<td>Most Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>AC</td>
+ *      <td>Analog Comparator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DAC</td>
+ *      <td>Digital-to-Analog Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>LSB</td>
+ *      <td>Least Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MSB</td>
+ *      <td>Most Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
  * </table>
  *
  *
@@ -546,23 +546,23 @@ void dac_chan_disable_output_buffer(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Add configuration for using 14-bit hardware dithering (SAMC21 support)</td>
- *	</tr>
- *	<tr>
- *		<td>Added new configuration parameters \c databuf_protection_bypass,
- *		\c voltage_pump_disable. Added new callback functions
- *		\c dac_chan_write_buffer_wait,
- *		\c dac_chan_write_buffer_job, \c dac_chan_write_job,
- *		\c dac_get_job_status, \c dac_abort_job and new callback type
- *		\c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Add configuration for using 14-bit hardware dithering (SAMC21 support)</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new configuration parameters \c databuf_protection_bypass,
+ *      \c voltage_pump_disable. Added new callback functions
+ *      \c dac_chan_write_buffer_wait,
+ *      \c dac_chan_write_buffer_job, \c dac_chan_write_job,
+ *      \c dac_get_job_status, \c dac_abort_job and new callback type
+ *      \c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -592,37 +592,37 @@ void dac_chan_disable_output_buffer(
  * \page asfdoc_sam0_dac_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42110E</td>
- *		<td>09/2015</td>
- *		<td>Add SAM C21 and SAM DA1 support</td>
- *	</tr>
- *	<tr>
- *		<td>42110D</td>
- *		<td>12/2014</td>
- *		<td>Add SAM D10/D11 support</td>
- *	</tr>
- *	<tr>
- *		<td>42110C</td>
- *		<td>01/2014</td>
- *		<td>Add SAM D21 support</td>
- *	</tr>
- *	<tr>
- *		<td>42110B</td>
- *		<td>06/2013</td>
- *		<td>Added additional documentation on the event system. Corrected
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42110E</td>
+ *      <td>09/2015</td>
+ *      <td>Add SAM C21 and SAM DA1 support</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42110D</td>
+ *      <td>12/2014</td>
+ *      <td>Add SAM D10/D11 support</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42110C</td>
+ *      <td>01/2014</td>
+ *      <td>Add SAM D21 support</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42110B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
  *          documentation typos.</td>
- *	</tr>
- *	<tr>
- *		<td>42110A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>42110A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c
index 484b14f9d920..1e63f863a9d3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac.c
@@ -57,32 +57,33 @@
  *
  */
 static void _dac_set_config(
-		struct dac_module *const module_inst,
-		struct dac_config *const config)
+        struct dac_module *const module_inst,
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(config);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(config);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Set selected DAC start on event to be disable when enabling the module */
-	module_inst->start_on_event[DAC_CHANNEL_0] = false;
-	module_inst->start_on_event[DAC_CHANNEL_1] = false;
+    /* Set selected DAC start on event to be disable when enabling the module */
+    module_inst->start_on_event[DAC_CHANNEL_0] = false;
+    module_inst->start_on_event[DAC_CHANNEL_1] = false;
 
-	uint32_t new_ctrlb = 0;
+    uint32_t new_ctrlb = 0;
 
-	/* Enable DAC in differential mode if configured */
-	if (config->differential_mode) {
-		new_ctrlb |= DAC_CTRLB_DIFF;
-	}
+    /* Enable DAC in differential mode if configured */
+    if (config->differential_mode)
+    {
+        new_ctrlb |= DAC_CTRLB_DIFF;
+    }
 
-	/* Set reference voltage */
-	new_ctrlb |= config->reference;
+    /* Set reference voltage */
+    new_ctrlb |= config->reference;
 
-	/* Apply the new configuration to the hardware module */
-	dac_module->CTRLB.reg = new_ctrlb;
+    /* Apply the new configuration to the hardware module */
+    dac_module->CTRLB.reg = new_ctrlb;
 }
 
 /**
@@ -102,18 +103,19 @@ static void _dac_set_config(
  * \retval false If the module has completed synchronization
  */
 bool dac_is_syncing(
-		struct dac_module *const dev_inst)
+        struct dac_module *const dev_inst)
 {
-	/* Sanity check arguments */
-	Assert(dev_inst);
+    /* Sanity check arguments */
+    Assert(dev_inst);
 
-	Dac *const dac_module = dev_inst->hw;
+    Dac *const dac_module = dev_inst->hw;
 
-	if (dac_module->SYNCBUSY.reg) {
-		return true;
-	}
+    if (dac_module->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -135,15 +137,15 @@ bool dac_is_syncing(
  * \param[out] config  Configuration structure to initialize to default values
  */
 void dac_get_config_defaults(
-		struct dac_config *const config)
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->differential_mode = false;
+    /* Default configuration values */
+    config->differential_mode = false;
     config->reference      = DAC_REFERENCE_INTREF;
-	config->clock_source   = GCLK_GENERATOR_0;
+    config->clock_source   = GCLK_GENERATOR_0;
 }
 
 /**
@@ -165,55 +167,59 @@ void dac_get_config_defaults(
  * \retval STATUS_BUSY        If module is busy resetting
  */
 enum status_code dac_init(
-		struct dac_module *const module_inst,
-		Dac *const module,
-		struct dac_config *const config)
+        struct dac_module *const module_inst,
+        Dac *const module,
+        struct dac_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module);
-	Assert(config);
-
-	/* Initialize device instance */
-	module_inst->hw = module;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
-
-	/* Check if module is enabled. */
-	if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress. */
-	if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(DAC_GCLK_ID);
-
-	/* Write configuration to module */
-	_dac_set_config(module_inst, config);
-
-	/* Store reference selection for later use */
-	module_inst->reference = config->reference;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module);
+    Assert(config);
+
+    /* Initialize device instance */
+    module_inst->hw = module;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
+
+    /* Check if module is enabled. */
+    if (module->CTRLA.reg & DAC_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress. */
+    if (module->CTRLA.reg & DAC_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(DAC_GCLK_ID);
+
+    /* Write configuration to module */
+    _dac_set_config(module_inst, config);
+
+    /* Store reference selection for later use */
+    module_inst->reference = config->reference;
 
 #if DAC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < DAC_CHANNEL_N; i++) {
-		for (uint8_t j = 0; j < DAC_CALLBACK_N; j++) {
-			module_inst->callback[i][j] = NULL;
-		}
-	};
-
-	_dac_instances[0] = module_inst;
+    for (uint8_t i = 0; i < DAC_CHANNEL_N; i++)
+    {
+        for (uint8_t j = 0; j < DAC_CALLBACK_N; j++)
+        {
+            module_inst->callback[i][j] = NULL;
+        }
+    };
+
+    _dac_instances[0] = module_inst;
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -225,20 +231,21 @@ enum status_code dac_init(
  * \param[in] module_inst  Pointer to the DAC software instance struct
  */
 void dac_reset(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Software reset the module */
-	dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
+    /* Software reset the module */
+    dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
 }
 
 /**
@@ -251,33 +258,39 @@ void dac_reset(
  *
  */
 void dac_enable(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Dac *const dac_module = module_inst->hw;
-
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
-
-	/* Enable the module */
-	dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
-
-	/* Enable internal bandgap reference if selected in the configuration */
-	if (module_inst->reference == DAC_REFERENCE_INTREF) {
-		system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
-	}
-
-	if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE) {
-		while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1))) {
-		};
-	} else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE) {
-		while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1))) {
-		};
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Dac *const dac_module = module_inst->hw;
+
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
+
+    /* Enable the module */
+    dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
+
+    /* Enable internal bandgap reference if selected in the configuration */
+    if (module_inst->reference == DAC_REFERENCE_INTREF)
+    {
+        system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
+    }
+
+    if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE)
+    {
+        while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1)))
+        {
+        };
+    } else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE)
+    {
+        while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1)))
+        {
+        };
+    }
 }
 
 /**
@@ -289,25 +302,26 @@ void dac_enable(
  *
  */
 void dac_disable(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Disbale interrupt */
-	dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    dac_module->INTENCLR.reg = DAC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    dac_module->INTFLAG.reg = DAC_INTFLAG_MASK;
 
-	/* Disable DAC */
-	dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
+    /* Disable DAC */
+    dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
 }
 
 /**
@@ -322,51 +336,57 @@ void dac_disable(
  *  \param[in] events       Struct containing flags of events to enable
  */
 void dac_enable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events)
+        struct dac_module *const module_inst,
+        struct dac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Dac *const dac_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure Enable Inversion of input event */
-	if (events->generate_event_on_chan0_falling_edge) {
-		event_mask |= DAC_EVCTRL_INVEI0;
-	}
-
-	/* Configure Enable Inversion of input event */
-	if (events->generate_event_on_chan1_falling_edge) {
-		event_mask |= DAC_EVCTRL_INVEI1;
-	}
-
-	/* Configure Buffer Empty event */
-	if (events->generate_event_on_chan0_buffer_empty) {
-		event_mask |= DAC_EVCTRL_EMPTYEO0;
-	}
-
-	/* Configure Buffer Empty event */
-	if (events->generate_event_on_chan1_buffer_empty) {
-		event_mask |= DAC_EVCTRL_EMPTYEO1;
-	}
-
-	/* Configure Conversion Start event */
-	if (events->on_event_chan0_start_conversion) {
-		event_mask |= DAC_EVCTRL_STARTEI0;
-		module_inst->start_on_event[DAC_CHANNEL_0] = true;
-	}
-
-	/* Configure Conversion Start event */
-	if (events->on_event_chan1_start_conversion) {
-		event_mask |= DAC_EVCTRL_STARTEI1;
-		module_inst->start_on_event[DAC_CHANNEL_1] = true;
-	}
-
-	dac_module->EVCTRL.reg |= event_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Dac *const dac_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Configure Enable Inversion of input event */
+    if (events->generate_event_on_chan0_falling_edge)
+    {
+        event_mask |= DAC_EVCTRL_INVEI0;
+    }
+
+    /* Configure Enable Inversion of input event */
+    if (events->generate_event_on_chan1_falling_edge)
+    {
+        event_mask |= DAC_EVCTRL_INVEI1;
+    }
+
+    /* Configure Buffer Empty event */
+    if (events->generate_event_on_chan0_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO0;
+    }
+
+    /* Configure Buffer Empty event */
+    if (events->generate_event_on_chan1_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO1;
+    }
+
+    /* Configure Conversion Start event */
+    if (events->on_event_chan0_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI0;
+        module_inst->start_on_event[DAC_CHANNEL_0] = true;
+    }
+
+    /* Configure Conversion Start event */
+    if (events->on_event_chan1_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI1;
+        module_inst->start_on_event[DAC_CHANNEL_1] = true;
+    }
+
+    dac_module->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -381,55 +401,59 @@ void dac_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 void dac_disable_events(
-		struct dac_module *const module_inst,
-		struct dac_events *const events)
+        struct dac_module *const module_inst,
+        struct dac_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Dac *const dac_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Configure Buffer Empty event */
-	if (events->on_event_chan0_start_conversion) {
-		event_mask |= DAC_EVCTRL_EMPTYEO0;
-	}
-
-	/* Configure Buffer Empty event */
-	if (events->on_event_chan1_start_conversion) {
-		event_mask |= DAC_EVCTRL_EMPTYEO1;
-	}
-
-	/* Configure Conversion Start event */
-	if (events->generate_event_on_chan0_buffer_empty) {
-		event_mask |= DAC_EVCTRL_STARTEI0;
-		module_inst->start_on_event[DAC_CHANNEL_0] = false;
-	}
-
-	/* Configure Conversion Start event */
-	if (events->generate_event_on_chan0_buffer_empty) {
-		event_mask |= DAC_EVCTRL_STARTEI1;
-		module_inst->start_on_event[DAC_CHANNEL_1] = false;
-	}
-
-	dac_module->EVCTRL.reg &= ~event_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Dac *const dac_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Configure Buffer Empty event */
+    if (events->on_event_chan0_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO0;
+    }
+
+    /* Configure Buffer Empty event */
+    if (events->on_event_chan1_start_conversion)
+    {
+        event_mask |= DAC_EVCTRL_EMPTYEO1;
+    }
+
+    /* Configure Conversion Start event */
+    if (events->generate_event_on_chan0_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI0;
+        module_inst->start_on_event[DAC_CHANNEL_0] = false;
+    }
+
+    /* Configure Conversion Start event */
+    if (events->generate_event_on_chan0_buffer_empty)
+    {
+        event_mask |= DAC_EVCTRL_STARTEI1;
+        module_inst->start_on_event[DAC_CHANNEL_1] = false;
+    }
+
+    dac_module->EVCTRL.reg &= ~event_mask;
 }
 
 void dac_chan_get_config_defaults(
-		struct dac_chan_config *const config)
+        struct dac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Dac channel default configuration values */
-	config->left_adjust    = false;
-	config->current        = DAC_CURRENT_12M;
-	config->run_in_standby = false;
-	config->dither_mode    = false;
-	config->refresh_period = 2;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Dac channel default configuration values */
+    config->left_adjust    = false;
+    config->current        = DAC_CURRENT_12M;
+    config->run_in_standby = false;
+    config->dither_mode    = false;
+    config->refresh_period = 2;
 }
 
 
@@ -447,59 +471,64 @@ void dac_chan_get_config_defaults(
  *
  */
 void dac_chan_set_config(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		struct dac_chan_config *const config)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        struct dac_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(config);
-
-	/* MUX the DAC VOUT pin */
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-
-	if(channel == DAC_CHANNEL_0) {
-		/* Set up the DAC VOUT0 pin */
-		pin_conf.mux_position = MUX_PA02B_DAC_VOUT0;
-		system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf);
-	}
-	else if(channel == DAC_CHANNEL_1) {
-		/* Set up the DAC VOUT1 pin */
-		pin_conf.mux_position = MUX_PA05B_DAC_VOUT1;
-		system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf);
-	}
-
-	Dac *const dac_module = module_inst->hw;
-
-	uint32_t new_dacctrl = 0;
-
-	/* Left adjust data if configured */
-	if (config->left_adjust) {
-		new_dacctrl |= DAC_DACCTRL_LEFTADJ;
-	}
-
-	/* Set current control */
-	new_dacctrl |= config->current;
-
-	/* Enable DAC in standby sleep mode if configured */
-	if (config->run_in_standby) {
-		new_dacctrl |= DAC_DACCTRL_RUNSTDBY;
-	}
-
-	/* Voltage pump disable if configured */
-	if (config->dither_mode) {
-		new_dacctrl |= DAC_DACCTRL_DITHER;
-	}
-
-	new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period);
-
-	/* Apply the new configuration to the hardware module */
-	dac_module->DACCTRL[channel].reg = new_dacctrl;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(config);
+
+    /* MUX the DAC VOUT pin */
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pin_conf.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+    if(channel == DAC_CHANNEL_0)
+    {
+        /* Set up the DAC VOUT0 pin */
+        pin_conf.mux_position = MUX_PA02B_DAC_VOUT0;
+        system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf);
+    }
+    else if(channel == DAC_CHANNEL_1)
+    {
+        /* Set up the DAC VOUT1 pin */
+        pin_conf.mux_position = MUX_PA05B_DAC_VOUT1;
+        system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf);
+    }
+
+    Dac *const dac_module = module_inst->hw;
+
+    uint32_t new_dacctrl = 0;
+
+    /* Left adjust data if configured */
+    if (config->left_adjust)
+    {
+        new_dacctrl |= DAC_DACCTRL_LEFTADJ;
+    }
+
+    /* Set current control */
+    new_dacctrl |= config->current;
+
+    /* Enable DAC in standby sleep mode if configured */
+    if (config->run_in_standby)
+    {
+        new_dacctrl |= DAC_DACCTRL_RUNSTDBY;
+    }
+
+    /* Voltage pump disable if configured */
+    if (config->dither_mode)
+    {
+        new_dacctrl |= DAC_DACCTRL_DITHER;
+    }
+
+    new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period);
+
+    /* Apply the new configuration to the hardware module */
+    dac_module->DACCTRL[channel].reg = new_dacctrl;
 }
 
 /**
@@ -512,17 +541,17 @@ void dac_chan_set_config(
  *
  */
 void dac_chan_enable(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Enable the module */
-	dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE;
+    /* Enable the module */
+    dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE;
 }
 
 /**
@@ -535,17 +564,17 @@ void dac_chan_enable(
  *
  */
 void dac_chan_disable(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	/* Enable the module */
-	dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE;
+    /* Enable the module */
+    dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE;
 
 }
 
@@ -571,29 +600,31 @@ void dac_chan_disable(
  * \retval STATUS_OK           If the data was written
  */
 enum status_code dac_chan_write(
-		struct dac_module *const module_inst,
-		enum dac_channel channel,
-		const uint16_t data)
+        struct dac_module *const module_inst,
+        enum dac_channel channel,
+        const uint16_t data)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Dac *const dac_module = module_inst->hw;
-
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
-
-	if (module_inst->start_on_event[channel]) {
-		/* Write the new value to the buffered DAC data register */
-		dac_module->DATABUF[channel].reg = data;
-	} else {
-		/* Write the new value to the DAC data register */
-		dac_module->DATA[channel].reg = data;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Dac *const dac_module = module_inst->hw;
+
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
+
+    if (module_inst->start_on_event[channel])
+    {
+        /* Write the new value to the buffered DAC data register */
+        dac_module->DATABUF[channel].reg = data;
+    } else {
+        /* Write the new value to the DAC data register */
+        dac_module->DATA[channel].reg = data;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -619,63 +650,75 @@ enum status_code dac_chan_write(
  * \retval STATUS_BUSY                 The DAC is busy and can not do the conversion
  */
 enum status_code dac_chan_write_buffer_wait(
-		struct dac_module *const module_inst,
-		enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t length)
+        struct dac_module *const module_inst,
+        enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t length)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	while (dac_is_syncing(module_inst)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (dac_is_syncing(module_inst))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Zero length request */
-	if (length == 0) {
-		/* No data to be converted */
-		return STATUS_OK;
-	}
+    /* Zero length request */
+    if (length == 0)
+    {
+        /* No data to be converted */
+        return STATUS_OK;
+    }
 
 #if DAC_CALLBACK_MODE == true
-	/* Check if busy */
-	if (module_inst->job_status[channel] == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if busy */
+    if (module_inst->job_status[channel] == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	/* Only support event triggered conversion */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	/* Blocks while buffer is being transferred */
-	while (length--) {
-		/* Convert one data */
-		dac_chan_write(module_inst, channel, buffer[length]);
-
-		/* Wait until Transmit is complete or timeout */
-		for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
-			if(channel == DAC_CHANNEL_0) {
-				if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0) {
-					break;
-				} else if (i == DAC_TIMEOUT) {
-					return STATUS_ERR_TIMEOUT;
-				}
-			} else if(channel == DAC_CHANNEL_1) {
-				if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1) {
-					break;
-				} else if (i == DAC_TIMEOUT) {
-					return STATUS_ERR_TIMEOUT;
-				}
-			}
-		}
-	}
-
-	return STATUS_OK;
+    /* Only support event triggered conversion */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    /* Blocks while buffer is being transferred */
+    while (length--)
+    {
+        /* Convert one data */
+        dac_chan_write(module_inst, channel, buffer[length]);
+
+        /* Wait until Transmit is complete or timeout */
+        for (uint32_t i = 0; i <= DAC_TIMEOUT; i++)
+        {
+            if(channel == DAC_CHANNEL_0)
+            {
+                if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0)
+                {
+                    break;
+                } else if (i == DAC_TIMEOUT)
+                {
+                    return STATUS_ERR_TIMEOUT;
+                }
+            } else if(channel == DAC_CHANNEL_1)
+            {
+                if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1)
+                {
+                    break;
+                } else if (i == DAC_TIMEOUT)
+                {
+                    return STATUS_ERR_TIMEOUT;
+                }
+            }
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -691,20 +734,21 @@ enum status_code dac_chan_write_buffer_wait(
  * \retval false    No conversion completed since last load of DATA
  */
 bool dac_chan_is_end_of_conversion(
-		struct dac_module *const module_inst,
-		enum dac_channel channel)
+        struct dac_module *const module_inst,
+        enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Dac *const dac_module = module_inst->hw;
-
-	if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1)) {
-		return true;
-	} else {
-		return false;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Dac *const dac_module = module_inst->hw;
+
+    if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1))
+    {
+        return true;
+    } else {
+        return false;
+    }
 }
 
 /**
@@ -725,34 +769,38 @@ bool dac_chan_is_end_of_conversion(
  *
  */
 uint32_t dac_get_status(
-		struct dac_module *const module_inst)
+        struct dac_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint8_t intflags = dac_module->INTFLAG.reg;
-	uint32_t status_flags = 0;
+    uint8_t intflags = dac_module->INTFLAG.reg;
+    uint32_t status_flags = 0;
 
-	if (intflags & DAC_INTFLAG_EMPTY0) {
-		status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
-	}
+    if (intflags & DAC_INTFLAG_EMPTY0)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
+    }
 
-	if (intflags & DAC_INTFLAG_EMPTY1) {
-		status_flags |= DAC_STATUS_CHANNEL_1_EMPTY;
-	}
+    if (intflags & DAC_INTFLAG_EMPTY1)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_1_EMPTY;
+    }
 
-	if (intflags & DAC_INTFLAG_UNDERRUN0) {
-		status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
-	}
+    if (intflags & DAC_INTFLAG_UNDERRUN0)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
+    }
 
-	if (intflags & DAC_INTFLAG_UNDERRUN1) {
-		status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN;
-	}
+    if (intflags & DAC_INTFLAG_UNDERRUN1)
+    {
+        status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN;
+    }
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -765,32 +813,36 @@ uint32_t dac_get_status(
  *
  */
 void dac_clear_status(
-		struct dac_module *const module_inst,
-		uint32_t status_flags)
+        struct dac_module *const module_inst,
+        uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Dac *const dac_module = module_inst->hw;
+    Dac *const dac_module = module_inst->hw;
 
-	uint32_t intflags = 0;
+    uint32_t intflags = 0;
 
-	if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
-		intflags |= DAC_INTFLAG_EMPTY0;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY)
+    {
+        intflags |= DAC_INTFLAG_EMPTY0;
+    }
 
-	if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY) {
-		intflags |= DAC_INTFLAG_EMPTY1;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY)
+    {
+        intflags |= DAC_INTFLAG_EMPTY1;
+    }
 
-	if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
-		intflags |= DAC_INTFLAG_UNDERRUN0;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN)
+    {
+        intflags |= DAC_INTFLAG_UNDERRUN0;
+    }
 
-	if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN) {
-		intflags |= DAC_INTFLAG_UNDERRUN1;
-	}
+    if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN)
+    {
+        intflags |= DAC_INTFLAG_UNDERRUN1;
+    }
 
-	dac_module->INTFLAG.reg = intflags;
+    dac_module->INTFLAG.reg = intflags;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c
index f15688a9b48d..b2b7d1df90a8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_callback.c
@@ -73,55 +73,59 @@ struct dac_module *_dac_instances[DAC_INST_NUM];
  * \retval STATUS_BUSY      The DAC is busy and can not accept a new job
  */
 enum status_code dac_chan_write_buffer_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t *buffer,
-		uint32_t length)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t *buffer,
+        uint32_t length)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(buffer);
-
-	Dac *const dac_module = module_inst->hw;
-
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if(module_inst->remaining_conversions[channel] != 0 ||
-			module_inst->job_status[channel] == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
-
-	/* Wait until the synchronization is complete */
-	while (dac_is_syncing(module_inst)) {
-	};
-
-	module_inst->job_status[channel] = STATUS_BUSY;
-
-	module_inst->remaining_conversions[channel] = length;
-	module_inst->job_buffer[channel] = buffer;
-	module_inst->transferred_conversions[channel] = 0;
-
-	/* Enable interrupt */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
-	switch(channel){
-	case DAC_CHANNEL_0:
-		dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
-		dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN0 | DAC_INTENSET_EMPTY0;
-		break;
-	case DAC_CHANNEL_1:
-		dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
-		dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN1 | DAC_INTENSET_EMPTY1;
-		break;
-	default:
-		break;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(buffer);
+
+    Dac *const dac_module = module_inst->hw;
+
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if(module_inst->remaining_conversions[channel] != 0 ||
+            module_inst->job_status[channel] == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
+
+    /* Wait until the synchronization is complete */
+    while (dac_is_syncing(module_inst))
+    {
+    };
+
+    module_inst->job_status[channel] = STATUS_BUSY;
+
+    module_inst->remaining_conversions[channel] = length;
+    module_inst->job_buffer[channel] = buffer;
+    module_inst->transferred_conversions[channel] = 0;
+
+    /* Enable interrupt */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC);
+    switch(channel)
+    {
+    case DAC_CHANNEL_0:
+        dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
+        dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN0 | DAC_INTENSET_EMPTY0;
+        break;
+    case DAC_CHANNEL_1:
+        dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
+        dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN1 | DAC_INTENSET_EMPTY1;
+        break;
+    default:
+        break;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -148,28 +152,30 @@ enum status_code dac_chan_write_buffer_job(
  * \retval STATUS_BUSY      The DAC is busy and can not accept a new job
  */
 enum status_code dac_chan_write_job(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		uint16_t data)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        uint16_t data)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if(module_inst->remaining_conversions[channel] != 0 ||
-			module_inst->job_status[channel] == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
-
-	dac_chan_write_buffer_job(module_inst, channel, &data, 1);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if(module_inst->remaining_conversions[channel] != 0 ||
+            module_inst->job_status[channel] == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
+
+    dac_chan_write_buffer_job(module_inst, channel, &data, 1);
+
+    return STATUS_OK;
 }
 
 /**
@@ -191,27 +197,29 @@ enum status_code dac_chan_write_job(
  *                                     configured in non-event mode
  */
 enum status_code dac_register_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const dac_callback_t callback,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const dac_callback_t callback,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback);
-
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if ((uint8_t)type < DAC_CALLBACK_N) {
-		module_inst->callback[channel][(uint8_t)type] = callback;
-		return STATUS_OK;
-	}
-
-	return STATUS_ERR_INVALID_ARG;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback);
+
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if ((uint8_t)type < DAC_CALLBACK_N)
+    {
+        module_inst->callback[channel][(uint8_t)type] = callback;
+        return STATUS_OK;
+    }
+
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -232,25 +240,27 @@ enum status_code dac_register_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_unregister_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if ((uint8_t)type < DAC_CALLBACK_N) {
-		module_inst->callback[channel][(uint8_t)type] = NULL;
-		return STATUS_OK;
-	}
-
-	return STATUS_ERR_INVALID_ARG;
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if ((uint8_t)type < DAC_CALLBACK_N)
+    {
+        module_inst->callback[channel][(uint8_t)type] = NULL;
+        return STATUS_OK;
+    }
+
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -270,22 +280,23 @@ enum status_code dac_unregister_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_chan_enable_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	module_inst->callback_enable[channel][type] = true;
+    module_inst->callback_enable[channel][type] = true;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -304,24 +315,25 @@ enum status_code dac_chan_enable_callback(
  *                                     configured in non-event mode
  */
 enum status_code dac_chan_disable_callback(
-		struct dac_module *const module_inst,
-		const enum dac_channel channel,
-		const enum dac_callback type)
+        struct dac_module *const module_inst,
+        const enum dac_channel channel,
+        const enum dac_callback type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	UNUSED(channel);
+    UNUSED(channel);
 
-	/* DAC interrupts require it to be driven by events to work, fail if in
-	 * unbuffered (polled) mode */
-	if (module_inst->start_on_event[channel] == false) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* DAC interrupts require it to be driven by events to work, fail if in
+     * unbuffered (polled) mode */
+    if (module_inst->start_on_event[channel] == false)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	module_inst->callback_enable[channel][type] = false;
+    module_inst->callback_enable[channel][type] = false;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** \internal
@@ -331,101 +343,115 @@ enum status_code dac_chan_disable_callback(
  */
 static void _dac_interrupt_handler(const uint8_t instance)
 {
-	struct dac_module *module = _dac_instances[instance];
-	Dac *const dac_hw = module->hw;
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN])) {
-			module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN](0);
-		}
-	}
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN])) {
-			module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN](0);
-		}
-	}
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY0) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY])) {
-			module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY](0);
-		}
-	}
-
-	/* If in a write buffer job */
-	if (module->remaining_conversions[DAC_CHANNEL_0]) {
-
-		/* Fill the data buffer with next data in write buffer */
-		dac_hw->DATABUF[DAC_CHANNEL_0].reg =
-			module->job_buffer[DAC_CHANNEL_0][module->transferred_conversions[DAC_CHANNEL_0]++];
-
-		/* Write buffer size decrement */
-		module->remaining_conversions[DAC_CHANNEL_0] --;
-
-		/* If in a write buffer job and all the data are converted */
-		if (module->remaining_conversions[DAC_CHANNEL_0] == 0) {
-			module->job_status[DAC_CHANNEL_0] = STATUS_OK;
-
-			/* Disable interrupt */
-			dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY0;
-			dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
-			system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
-
-			if ((module->callback) &&
-				 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE])) {
-				module->callback[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE](0);
-			}
-		}
-	}
-
-	if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY1) {
-		dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
-
-		if ((module->callback) &&
-			 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY])) {
-			module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY](0);
-		}
-	}
-	/* If in a write buffer job */
-	if (module->remaining_conversions[DAC_CHANNEL_1]) {
-
-		/* Fill the data buffer with next data in write buffer */
-		dac_hw->DATABUF[DAC_CHANNEL_1].reg =
-			module->job_buffer[DAC_CHANNEL_1][module->transferred_conversions[DAC_CHANNEL_1]++];
-
-		/* Write buffer size decrement */
-		module->remaining_conversions[DAC_CHANNEL_1] --;
-
-		/* If in a write buffer job and all the data are converted */
-		if (module->remaining_conversions[DAC_CHANNEL_1] == 0) {
-			module->job_status[DAC_CHANNEL_1] = STATUS_OK;
-
-			/* Disable interrupt */
-			dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY1;
-			dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
-			system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
-
-			if ((module->callback) &&
-				 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE])) {
-				module->callback[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE](0);
-			}
-		}
-	}
+    struct dac_module *module = _dac_instances[instance];
+    Dac *const dac_hw = module->hw;
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0;
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN]))
+             {
+            module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_UNDERRUN](0);
+        }
+    }
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1;
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN]))
+             {
+            module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_UNDERRUN](0);
+        }
+    }
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY0)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY]))
+             {
+            module->callback[DAC_CHANNEL_0][DAC_CALLBACK_DATA_EMPTY](0);
+        }
+    }
+
+    /* If in a write buffer job */
+    if (module->remaining_conversions[DAC_CHANNEL_0])
+    {
+
+        /* Fill the data buffer with next data in write buffer */
+        dac_hw->DATABUF[DAC_CHANNEL_0].reg =
+            module->job_buffer[DAC_CHANNEL_0][module->transferred_conversions[DAC_CHANNEL_0]++];
+
+        /* Write buffer size decrement */
+        module->remaining_conversions[DAC_CHANNEL_0] --;
+
+        /* If in a write buffer job and all the data are converted */
+        if (module->remaining_conversions[DAC_CHANNEL_0] == 0)
+        {
+            module->job_status[DAC_CHANNEL_0] = STATUS_OK;
+
+            /* Disable interrupt */
+            dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY0;
+            dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY0;
+            system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+            if ((module->callback) &&
+                 (module->callback_enable[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE]))
+                 {
+                module->callback[DAC_CHANNEL_0][DAC_CALLBACK_TRANSFER_COMPLETE](0);
+            }
+        }
+    }
+
+    if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY1)
+    {
+        dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+
+        if ((module->callback) &&
+             (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY]))
+             {
+            module->callback[DAC_CHANNEL_1][DAC_CALLBACK_DATA_EMPTY](0);
+        }
+    }
+    /* If in a write buffer job */
+    if (module->remaining_conversions[DAC_CHANNEL_1])
+    {
+
+        /* Fill the data buffer with next data in write buffer */
+        dac_hw->DATABUF[DAC_CHANNEL_1].reg =
+            module->job_buffer[DAC_CHANNEL_1][module->transferred_conversions[DAC_CHANNEL_1]++];
+
+        /* Write buffer size decrement */
+        module->remaining_conversions[DAC_CHANNEL_1] --;
+
+        /* If in a write buffer job and all the data are converted */
+        if (module->remaining_conversions[DAC_CHANNEL_1] == 0)
+        {
+            module->job_status[DAC_CHANNEL_1] = STATUS_OK;
+
+            /* Disable interrupt */
+            dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY1;
+            dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY1;
+            system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC);
+
+            if ((module->callback) &&
+                 (module->callback_enable[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE]))
+                 {
+                module->callback[DAC_CHANNEL_1][DAC_CALLBACK_TRANSFER_COMPLETE](0);
+            }
+        }
+    }
 }
 
 /** Handler for the DAC hardware module interrupt. */
 void DAC_Handler(void)
 {
-	_dac_interrupt_handler(0);
+    _dac_interrupt_handler(0);
 }
 
 /**
@@ -439,13 +465,13 @@ void DAC_Handler(void)
  * \return Status of the job.
  */
 enum status_code dac_chan_get_job_status(
-		struct dac_module *module_inst,
-		const enum dac_channel channel)
+        struct dac_module *module_inst,
+        const enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	return module_inst->job_status[channel];
+    return module_inst->job_status[channel];
 }
 
 /**
@@ -457,28 +483,29 @@ enum status_code dac_chan_get_job_status(
  * \param[in]  channel     Logical channel to enable callback function
  */
 void dac_chan_abort_job(
-		struct dac_module *module_inst,
-		const enum dac_channel channel)
+        struct dac_module *module_inst,
+        const enum dac_channel channel)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	/* Disable interrupt */
-	switch(channel) {
-	case DAC_CHANNEL_0:
-		module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
-		module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN0 | DAC_INTENCLR_EMPTY0;
-		break;
-	case DAC_CHANNEL_1:
-		module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
-		module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN1 | DAC_INTENCLR_EMPTY1;
-		break;
-	default:
-		break;
-	}
-
-	/* Mark job as aborted */
-	module_inst->job_status[channel] = STATUS_ABORTED;
-	module_inst->remaining_conversions[channel] = 0;
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    /* Disable interrupt */
+    switch(channel)
+    {
+    case DAC_CHANNEL_0:
+        module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0 | DAC_INTFLAG_EMPTY0;
+        module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN0 | DAC_INTENCLR_EMPTY0;
+        break;
+    case DAC_CHANNEL_1:
+        module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1 | DAC_INTFLAG_EMPTY1;
+        module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN1 | DAC_INTENCLR_EMPTY1;
+        break;
+    default:
+        break;
+    }
+
+    /* Mark job as aborted */
+    module_inst->job_status[channel] = STATUS_ABORTED;
+    module_inst->remaining_conversions[channel] = 0;
 
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h
index 3385396e61af..ff88a9e8de00 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dac/dac_sam_l/dac_feature.h
@@ -351,14 +351,14 @@ extern "C" {
  * Enum for the possible reference voltages for the DAC.
  */
 enum dac_reference {
-	/** Unbuffered external voltage reference */
-	DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0),
-	/** Analog VCC as reference */
-	DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1),
-	/** Buffered external voltage reference */
-	DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2),
-	/** Internal bandgap reference */
-	DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3),
+    /** Unbuffered external voltage reference */
+    DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0),
+    /** Analog VCC as reference */
+    DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1),
+    /** Buffered external voltage reference */
+    DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2),
+    /** Internal bandgap reference */
+    DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3),
 };
 
 /**
@@ -367,14 +367,14 @@ enum dac_reference {
  * Enum for the current in output buffer according the conversion rate.
  */
 enum dac_current_ctrl {
-	/** GCLK_DAC <= 1.2MHz */
-	DAC_CURRENT_100K  = DAC_DACCTRL_CCTRL(0),
-	/** 1.2MHz < GCLK_DAC <= 6MHz */
-	DAC_CURRENT_1M   = DAC_DACCTRL_CCTRL(1),
-	/** 6MHz < GCLK_DAC <= 12MHz */
-	DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(2),
-	/** Reserved */
-	DAC_CURRENT_RESERVED  = DAC_DACCTRL_CCTRL(3),
+    /** GCLK_DAC <= 1.2MHz */
+    DAC_CURRENT_100K  = DAC_DACCTRL_CCTRL(0),
+    /** 1.2MHz < GCLK_DAC <= 6MHz */
+    DAC_CURRENT_1M   = DAC_DACCTRL_CCTRL(1),
+    /** 6MHz < GCLK_DAC <= 12MHz */
+    DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(2),
+    /** Reserved */
+    DAC_CURRENT_RESERVED  = DAC_DACCTRL_CCTRL(3),
 };
 
 /**
@@ -383,12 +383,12 @@ enum dac_current_ctrl {
  * Enum for the DAC channel selection.
  */
 enum dac_channel {
-	/** DAC output channel 0 */
-	DAC_CHANNEL_0,
-	/** DAC output channel 1 */
-	DAC_CHANNEL_1,
+    /** DAC output channel 0 */
+    DAC_CHANNEL_0,
+    /** DAC output channel 1 */
+    DAC_CHANNEL_1,
 #if !defined(__DOXYGEN__)
-	DAC_CHANNEL_N,
+    DAC_CHANNEL_N,
 #endif
 };
 
@@ -403,25 +403,25 @@ enum dac_channel {
  */
 struct dac_module {
 #if !defined(__DOXYGEN__)
-	/** DAC hardware module */
-	Dac *hw;
-	/** Reference selection */
-	enum dac_reference reference;
-	/** DAC event selection */
-	bool start_on_event[DAC_CHANNEL_N];
+    /** DAC hardware module */
+    Dac *hw;
+    /** Reference selection */
+    enum dac_reference reference;
+    /** DAC event selection */
+    bool start_on_event[DAC_CHANNEL_N];
 #  if DAC_CALLBACK_MODE == true
-	/** Pointer to buffer used for ADC results */
-	volatile uint16_t *job_buffer[DAC_CHANNEL_N];
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions[DAC_CHANNEL_N];
-	/** Transferred number of conversions in current job */
-	volatile uint16_t transferred_conversions[DAC_CHANNEL_N];
-	/** DAC callback enable */
-	bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N];
-	/** DAC registered callback functions */
-	dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N];
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status[DAC_CHANNEL_N];
+    /** Pointer to buffer used for ADC results */
+    volatile uint16_t *job_buffer[DAC_CHANNEL_N];
+    /** Remaining number of conversions in current job */
+    volatile uint16_t remaining_conversions[DAC_CHANNEL_N];
+    /** Transferred number of conversions in current job */
+    volatile uint16_t transferred_conversions[DAC_CHANNEL_N];
+    /** DAC callback enable */
+    bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N];
+    /** DAC registered callback functions */
+    dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N];
+    /** Holds the status of the ongoing or last conversion job */
+    volatile enum status_code job_status[DAC_CHANNEL_N];
 #  endif
 #endif
 };
@@ -434,12 +434,12 @@ struct dac_module {
  * function before being modified by the user application.
  */
 struct dac_config {
-	/** Differential mode enable data */
-	bool differential_mode;
-	/** Reference voltage */
-	enum dac_reference reference;
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
+    /** Differential mode enable data */
+    bool differential_mode;
+    /** Reference voltage */
+    enum dac_reference reference;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
 };
 
 /**
@@ -450,22 +450,22 @@ struct dac_config {
  * user application.
  */
 struct dac_chan_config {
-	/** Left adjusted data */
-	bool left_adjust;
-	/** Current control data */
-	enum dac_current_ctrl current;
-	/**
-	 * The DAC behaves as in normal mode when the chip enters STANDBY sleep
-	 * mode
-	 */
-	bool run_in_standby;
-	/** Dither mode enable data */
-	bool dither_mode;
-	/**
-	 * The DAC conversion refreshed periodically when used to generate a static
-	 * voltage
-	 */
-	uint8_t refresh_period;
+    /** Left adjusted data */
+    bool left_adjust;
+    /** Current control data */
+    enum dac_current_ctrl current;
+    /**
+     * The DAC behaves as in normal mode when the chip enters STANDBY sleep
+     * mode
+     */
+    bool run_in_standby;
+    /** Dither mode enable data */
+    bool dither_mode;
+    /**
+     * The DAC conversion refreshed periodically when used to generate a static
+     * voltage
+     */
+    uint8_t refresh_period;
 };
 
 /**
@@ -475,18 +475,18 @@ struct dac_chan_config {
  * disable events via \ref dac_enable_events() and \ref dac_disable_events().
  */
 struct dac_events {
-	/** Start a new DAC0 conversion */
-	bool on_event_chan0_start_conversion;
-	/** Start a new DAC1 conversion */
-	bool on_event_chan1_start_conversion;
-	/** Enable event generation on DAC0 data buffer empty */
-	bool generate_event_on_chan0_buffer_empty;
-	/** Enable event generation on DAC1 data buffer empty */
-	bool generate_event_on_chan1_buffer_empty;
-	/** Enable the falling edge of the input event for DAC0 */
-	bool generate_event_on_chan0_falling_edge;
-	/** Enable the falling edge of the input event for DAC1 */
-	bool generate_event_on_chan1_falling_edge;
+    /** Start a new DAC0 conversion */
+    bool on_event_chan0_start_conversion;
+    /** Start a new DAC1 conversion */
+    bool on_event_chan1_start_conversion;
+    /** Enable event generation on DAC0 data buffer empty */
+    bool generate_event_on_chan0_buffer_empty;
+    /** Enable event generation on DAC1 data buffer empty */
+    bool generate_event_on_chan1_buffer_empty;
+    /** Enable the falling edge of the input event for DAC0 */
+    bool generate_event_on_chan0_falling_edge;
+    /** Enable the falling edge of the input event for DAC1 */
+    bool generate_event_on_chan1_falling_edge;
 };
 
 /**
@@ -494,8 +494,8 @@ struct dac_events {
  * @{
  */
 bool dac_chan_is_end_of_conversion(
-		struct dac_module *const module_inst,
-		enum dac_channel channel);
+        struct dac_module *const module_inst,
+        enum dac_channel channel);
 /** @} */
 
 /** @} */
@@ -507,34 +507,34 @@ bool dac_chan_is_end_of_conversion(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
- *	<tr>
- *		<td>AC</td>
- *		<td>Analog Comparator</td>
- *	</tr>
- *	<tr>
- *		<td>DAC</td>
- *		<td>Digital-to-Analog Converter</td>
- *	</tr>
- *	<tr>
- *		<td>LSB</td>
- *		<td>Least Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>MSB</td>
- *		<td>Most Significant Bit</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>AC</td>
+ *      <td>Analog Comparator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DAC</td>
+ *      <td>Digital-to-Analog Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>LSB</td>
+ *      <td>Least Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MSB</td>
+ *      <td>Most Significant Bit</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
  * </table>
  *
  *
@@ -555,12 +555,12 @@ bool dac_chan_is_end_of_conversion(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -590,16 +590,16 @@ bool dac_chan_is_end_of_conversion(
  * \page asfdoc_sam0_dac_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42450A</td>
- *		<td>07/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42450A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c
index 9cbfbd78c3f7..7a9ee5d57d1c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.c
@@ -59,10 +59,10 @@
 void _system_divas_init(void);
 void _system_divas_init(void)
 {
-	/* Turn on the digital interface clock. */
-	system_ahb_clock_set_mask(MCLK_AHBMASK_DIVAS);
+    /* Turn on the digital interface clock. */
+    system_ahb_clock_set_mask(MCLK_AHBMASK_DIVAS);
 
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
 }
 
 /**
@@ -77,27 +77,28 @@ void _system_divas_init(void)
  */
 int32_t divas_idiv(int32_t numerator, int32_t denominator)
 {
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Signed division. */
-	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+    /* Signed division. */
+    DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	int32_t quotient = DIVAS->RESULT.reg;
+    int32_t quotient = DIVAS->RESULT.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return quotient;
+    return quotient;
 }
 
 /**
@@ -112,27 +113,28 @@ int32_t divas_idiv(int32_t numerator, int32_t denominator)
  */
 uint32_t divas_uidiv(uint32_t numerator, uint32_t denominator)
 {
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Unsigned division. */
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+    /* Unsigned division. */
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	uint32_t quotient = DIVAS->RESULT.reg;
+    uint32_t quotient = DIVAS->RESULT.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return quotient;
+    return quotient;
 }
 
 /**
@@ -147,27 +149,28 @@ uint32_t divas_uidiv(uint32_t numerator, uint32_t denominator)
  */
 int32_t divas_idivmod(int32_t numerator, int32_t denominator)
 {
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Signed division. */
-	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+    /* Signed division. */
+    DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	int32_t remainder = DIVAS->REM.reg;
+    int32_t remainder = DIVAS->REM.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return remainder;
+    return remainder;
 }
 
 /**
@@ -182,27 +185,28 @@ int32_t divas_idivmod(int32_t numerator, int32_t denominator)
  */
 uint32_t divas_uidivmod(uint32_t numerator, uint32_t denominator)
 {
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Unsigned division. */
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+    /* Unsigned division. */
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	uint32_t remainder = DIVAS->REM.reg;
+    uint32_t remainder = DIVAS->REM.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return remainder;
+    return remainder;
 }
 
 /**
@@ -216,22 +220,23 @@ uint32_t divas_uidivmod(uint32_t numerator, uint32_t denominator)
  */
 uint32_t  divas_sqrt(uint32_t radicand)
 {
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Write the radicand to DIVIDEND register. */
-	DIVAS->SQRNUM.reg = radicand;
+    /* Write the radicand to DIVIDEND register. */
+    DIVAS->SQRNUM.reg = radicand;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the square root is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the square root is complete. */
+    }
 
-	uint32_t result_sqrt = DIVAS->RESULT.reg;
+    uint32_t result_sqrt = DIVAS->RESULT.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return result_sqrt;
+    return result_sqrt;
 }
 
 /**
@@ -254,7 +259,7 @@ uint32_t  divas_sqrt(uint32_t radicand)
  */
 int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
 {
-	return divas_idiv(numerator, denominator);
+    return divas_idiv(numerator, denominator);
 }
 
 /**
@@ -269,7 +274,7 @@ int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
  */
 uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
 {
-	return divas_uidiv(numerator, denominator);
+    return divas_uidiv(numerator, denominator);
 }
 
 /**
@@ -284,36 +289,37 @@ uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
  */
 uint64_t __aeabi_idivmod(int32_t numerator, int32_t denominator)
 {
-	uint64_t uret;
-	int32_t quotient, remainder;
+    uint64_t uret;
+    int32_t quotient, remainder;
 
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Signed division. */
-	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+    /* Signed division. */
+    DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	/* Read out the result. */
-	quotient = DIVAS->RESULT.reg;
-	remainder = DIVAS->REM.reg;
+    /* Read out the result. */
+    quotient = DIVAS->RESULT.reg;
+    remainder = DIVAS->REM.reg;
 
-	/* quotient in r0, remainder in r1 */
-	uret = ((uint64_t)quotient & 0x00000000FFFFFFFF ) |
-			(((uint64_t)remainder ) << 32);
+    /* quotient in r0, remainder in r1 */
+    uret = ((uint64_t)quotient & 0x00000000FFFFFFFF ) |
+            (((uint64_t)remainder ) << 32);
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return uret;
+    return uret;
 }
 
 /**
@@ -328,35 +334,36 @@ uint64_t __aeabi_idivmod(int32_t numerator, int32_t denominator)
  */
 uint64_t __aeabi_uidivmod(uint32_t numerator, uint32_t denominator)
 {
-	uint64_t uret;
-	uint32_t quotient, remainder;
+    uint64_t uret;
+    uint32_t quotient, remainder;
 
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Unsigned division. */
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+    /* Unsigned division. */
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-	/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+    /* Wait the division is complete. */
+    }
 
-	/* Read out the result. */
-	quotient = DIVAS->RESULT.reg;
-	remainder = DIVAS->REM.reg;
+    /* Read out the result. */
+    quotient = DIVAS->RESULT.reg;
+    remainder = DIVAS->REM.reg;
 
-	/* quotient in r0, remainder in r1 */
-	uret = quotient | (((uint64_t)remainder) << 32);
+    /* quotient in r0, remainder in r1 */
+    uret = quotient | (((uint64_t)remainder) << 32);
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return uret;
+    return uret;
 }
 
 #  elif defined ( __ICCARM__ )
@@ -372,7 +379,7 @@ uint64_t __aeabi_uidivmod(uint32_t numerator, uint32_t denominator)
  */
 int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
 {
-	return divas_idiv(numerator, denominator);
+    return divas_idiv(numerator, denominator);
 }
 
 /**
@@ -387,7 +394,7 @@ int32_t __aeabi_idiv(int32_t numerator, int32_t denominator)
  */
 uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
 {
-	return divas_uidiv(numerator, denominator);
+    return divas_uidiv(numerator, denominator);
 }
 
 /**
@@ -401,31 +408,32 @@ uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator)
  */
 __value_in_regs idiv_return __aeabi_idivmod(int numerator, int denominator)
 {
-	idiv_return result;
+    idiv_return result;
 
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Signed division. */
-	DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
+    /* Signed division. */
+    DIVAS->CTRLA.reg |= DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	/* Read out the result. */
-	result.quotient = DIVAS->RESULT.reg;
-	result.remainder = DIVAS->REM.reg;
+    /* Read out the result. */
+    result.quotient = DIVAS->RESULT.reg;
+    result.remainder = DIVAS->REM.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return result;
+    return result;
 }
 
 /**
@@ -439,31 +447,32 @@ __value_in_regs idiv_return __aeabi_idivmod(int numerator, int denominator)
  */
 __value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denominator)
 {
-	uidiv_return result;
+    uidiv_return result;
 
-	/* Disable interrupt. */
-	cpu_irq_enter_critical();
+    /* Disable interrupt. */
+    cpu_irq_enter_critical();
 
-	/* Unsigned division. */
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
+    /* Unsigned division. */
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_SIGNED;
 
-	/* Write the dividend to DIVIDEND register. */
-	DIVAS->DIVIDEND.reg = numerator;
-	/* Write the divisor to DIVISOR register. */
-	DIVAS->DIVISOR.reg = denominator;
+    /* Write the dividend to DIVIDEND register. */
+    DIVAS->DIVIDEND.reg = numerator;
+    /* Write the divisor to DIVISOR register. */
+    DIVAS->DIVISOR.reg = denominator;
 
-	while(DIVAS->STATUS.bit.BUSY){
-		/* Wait the division is complete. */
-	}
+    while(DIVAS->STATUS.bit.BUSY)
+    {
+        /* Wait the division is complete. */
+    }
 
-	/* Read out the result. */
-	result.quotient = DIVAS->RESULT.reg;
-	result.remainder = DIVAS->REM.reg;
+    /* Read out the result. */
+    result.quotient = DIVAS->RESULT.reg;
+    result.remainder = DIVAS->REM.reg;
 
-	/* Enable interrupt. */
-	cpu_irq_leave_critical();
+    /* Enable interrupt. */
+    cpu_irq_leave_critical();
 
-	return result;
+    return result;
 }
 
 #  endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h
index c2d9dd749256..e79d202da680 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/divas/divas.h
@@ -79,22 +79,22 @@
  * This driver provides an interface for the Divide and Square Root Accelerator
  * on the device.
  *
- * The DIVAS is a programmable 32-bit signed or unsigned hardware divider and a 
- * 32-bit unsigned square root hardware engine. When running signed division, 
+ * The DIVAS is a programmable 32-bit signed or unsigned hardware divider and a
+ * 32-bit unsigned square root hardware engine. When running signed division,
  * both the input and the result will be in two's complement format. The result of
- * signed division is that the remainder has the same sign as the dividend and 
+ * signed division is that the remainder has the same sign as the dividend and
  * the quotient is negative if the dividend and divisor have opposite signs.
- * When the square root input register is programmed, the square root function 
+ * When the square root input register is programmed, the square root function
  * starts and the result will be stored in the Remainder register.
  *
  * There are two ways to calculate the results:
  * - Call the DIVAS API
  * - Overload "/" and "%" operation
  * \note Square root operation can't implement overload operation.
- 
+
  * \subsection asfdoc_sam0_divas_module_overview_overload Overload Operation
- * The operation is implemented automatically by EABI (Enhanced Application Binary 
- * Interface). EABI is a standard calling convention, which is defined by ARM. 
+ * The operation is implemented automatically by EABI (Enhanced Application Binary
+ * Interface). EABI is a standard calling convention, which is defined by ARM.
  * The four functions interface can implement division and mod operation in EABI.
  *
  * The following prototypes for EABI division operation in ICCARM tool chain:
@@ -102,19 +102,19 @@
     int __aeabi_idiv(int numerator, int denominator);
     unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
     __value_in_regs idiv_return __aeabi_idivmod( int numerator, int denominator);
-    __value_in_regs uidiv_return __aeabi_uidivmod( unsigned numerator, 
-												unsigned denominator);
+    __value_in_regs uidiv_return __aeabi_uidivmod( unsigned numerator,
+                                                unsigned denominator);
    \endcode
  * The following prototypes for EABI division operation in GNUC tool chain:
  * \code
     int __aeabi_idiv(int numerator, int denominator);
     unsigned __aeabi_uidiv(unsigned numerator, unsigned denominator);
     uint64_t __aeabi_idivmod( int numerator, int denominator);
-    uint64_t uidiv_return __aeabi_uidivmod( unsigned numerator, 
-											unsigned denominator);
+    uint64_t uidiv_return __aeabi_uidivmod( unsigned numerator,
+                                            unsigned denominator);
    \endcode
- * No matter what kind of tool chain, by using DIVAS module in the four functions 
- * body, the user can transparently access the DIVAS module when writing normal C 
+ * No matter what kind of tool chain, by using DIVAS module in the four functions
+ * body, the user can transparently access the DIVAS module when writing normal C
  * code. For example:
  * \code
     void division(int32_t b, int32_t c)
@@ -124,30 +124,30 @@
         return a;
     }
    \endcode
- * Similarly, the user can use the "a = b % c;" symbol to implement the operation with 
+ * Similarly, the user can use the "a = b % c;" symbol to implement the operation with
  * DIVAS, and needn't to care about the internal operation process.
- * 
+ *
  * \subsection asfdoc_sam0_divas_module_overview_operand Operand Size
  *  - Divide: The DIVAS can perform 32-bit signed and unsigned division.
  *  - Square Root: The DIVAS can perform 32-bit unsigned division.
- 
+
  * \subsection asfdoc_sam0_divas_module_overview_Signed Signed Division
- *  When the signed flag is one, both the input and the result will be in two's 
- *  complement format. The result of signed division is that the remainder has 
- *  the same sign as the dividend and the quotient is negative if the dividend 
+ *  When the signed flag is one, both the input and the result will be in two's
+ *  complement format. The result of signed division is that the remainder has
+ *  the same sign as the dividend and the quotient is negative if the dividend
  *  and divisor have opposite signs.
- *  \note When the maximum negative number is divided by the minimum negative 
- *  number, the resulting quotient overflows the signed integer range and will 
- *  return the maximum negative number with no indication of the overflow. This 
- *  occurs for 0x80000000 / 0xFFFFFFFF in 32-bit operation and 0x8000 / 0xFFFF 
+ *  \note When the maximum negative number is divided by the minimum negative
+ *  number, the resulting quotient overflows the signed integer range and will
+ *  return the maximum negative number with no indication of the overflow. This
+ *  occurs for 0x80000000 / 0xFFFFFFFF in 32-bit operation and 0x8000 / 0xFFFF
  *  in 16-bit operation.
  *
  * \subsection asfdoc_sam0_divas_module_overview_zero Divide By Zero
- *  A divide by zero will cause a fault if the DIVISOR is programmed to zero. The 
+ *  A divide by zero will cause a fault if the DIVISOR is programmed to zero. The
  *  result is that the quotient is zero and the reminder is equal to the dividend.
  *
  * \subsection asfdoc_sam0_divas_module_overview_square Unsigned Square Root
- *  When the square root input register is programmed, the square root function 
+ *  When the square root input register is programmed, the square root function
  *  starts and the result will be stored in the Result and Remainder registers.
  * \note The square root function can't overload.
  *
@@ -188,10 +188,10 @@ extern "C" {
  *  DIVAS signed division operator output data structure.
  */
 typedef struct {
-	/** Signed division operator result: quotient */
-	int32_t quotient; 
-	/** Signed division operator result: remainder */
-	int32_t remainder;
+    /** Signed division operator result: quotient */
+    int32_t quotient;
+    /** Signed division operator result: remainder */
+    int32_t remainder;
 } idiv_return;
 
 /**
@@ -200,45 +200,45 @@ typedef struct {
  *  DIVAS unsigned division operator output data structure.
  */
 typedef struct {
-	/** Unsigned division operator result: quotient */
-	uint32_t quotient; 
-	/** Unsigned division operator result: remainder */
-	uint32_t remainder;
-} uidiv_return; 
+    /** Unsigned division operator result: quotient */
+    uint32_t quotient;
+    /** Unsigned division operator result: remainder */
+    uint32_t remainder;
+} uidiv_return;
 
 /**
  * \brief Enables DIVAS leading zero optimization.
  *
  *  Enable leading zero optimization from the Divide and Square Root Accelerator
- *  module. When leading zero optimization is enable, 16-bit division completes 
+ *  module. When leading zero optimization is enable, 16-bit division completes
  *  in 2-8 cycles and 32-bit division completes in 2-16 cycles.
  *
  */
 static inline void divas_enable_dlz(void)
 {
-	/* Enable DLZ. */
-	DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
+    /* Enable DLZ. */
+    DIVAS->CTRLA.reg &= ~DIVAS_CTRLA_DLZ;
 }
 
 /**
  * \brief Disables DIVAS leading zero optimization.
  *
  *  Disable leading zero optimization from the Divide and Square Root Accelerator
- *  module. When leading zero optimization is disable, 16-bit division completes 
+ *  module. When leading zero optimization is disable, 16-bit division completes
  *  in 8 cycles and 32-bit division completes in 16 cycles.
  *
  */
 static inline void divas_disable_dlz(void)
 {
-	/* Disable DLZ. */
-	DIVAS->CTRLA.reg |= DIVAS_CTRLA_DLZ;
+    /* Disable DLZ. */
+    DIVAS->CTRLA.reg |= DIVAS_CTRLA_DLZ;
 }
 
 /**
  * \name Call the DIVAS API Operation
  * @{
- * In this mode, the way that directly call the DIVAS API implement division or 
- * mod operation. 
+ * In this mode, the way that directly call the DIVAS API implement division or
+ * mod operation.
  */
 
 int32_t divas_idiv(int32_t numerator, int32_t denominator);
@@ -252,8 +252,8 @@ uint32_t divas_sqrt(uint32_t radicand);
 /**
  * \name DIVAS Overload '/' and '%' Operation
  * @{
- * In this mode, the user can transparently access the DIVAS module when writing 
- * normal C code. E.g. "a = b / c;" or "a = b % c;" will be translated to a 
+ * In this mode, the user can transparently access the DIVAS module when writing
+ * normal C code. E.g. "a = b / c;" or "a = b % c;" will be translated to a
  * subroutine call, which uses the DIVAS.
  */
 
@@ -268,7 +268,7 @@ uint64_t __aeabi_uidivmod(uint32_t numerator, uint32_t denominator);
 int32_t __aeabi_idiv(int32_t numerator, int32_t denominator);
 uint32_t __aeabi_uidiv(uint32_t numerator, uint32_t denominator);
 __value_in_regs idiv_return __aeabi_idivmod(int numerator, int denominator);
-__value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denominator); 
+__value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denominator);
 #  endif
 #endif
 
@@ -286,18 +286,18 @@ __value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denom
  * \section asfdoc_sam0_divas_extra_acronyms Acronyms
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>DIVAS</td>
- *		<td>Divide and Square Root Accelerator</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>DIVAS</td>
+ *      <td>Divide and Square Root Accelerator</td>
+ *  </tr>
  *  <tr>
- *		<td>EABI</td>
- *		<td>Enhanced Application Binary Interface</td>
- *	</tr>
+ *      <td>EABI</td>
+ *      <td>Enhanced Application Binary Interface</td>
+ *  </tr>
  * </table>
  *
  *
@@ -316,12 +316,12 @@ __value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denom
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -340,16 +340,16 @@ __value_in_regs uidiv_return __aeabi_uidivmod(unsigned numerator, unsigned denom
  * \page asfdoc_sam0_divas_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42644A</td>
- *		<td>01/2016</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42644A</td>
+ *      <td>01/2016</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c
index 23592cda314b..f12b542d5da8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.c
@@ -50,15 +50,15 @@
 #include "system_interrupt.h"
 
 struct _dma_module {
-	volatile bool _dma_init;
-	volatile uint32_t allocated_channels;
-	uint8_t free_channels;
+    volatile bool _dma_init;
+    volatile uint32_t allocated_channels;
+    uint8_t free_channels;
 };
 
 struct _dma_module _dma_inst = {
-	._dma_init = false,
-	.allocated_channels = 0,
-	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
+    ._dma_init = false,
+    .allocated_channels = 0,
+    .free_channels = CONF_MAX_USED_CHANNEL_NUM,
 };
 
 /** Maximum retry counter for resuming a job transfer. */
@@ -91,36 +91,39 @@ uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0};
  */
 static uint8_t _dma_find_first_free_channel_and_allocate(void)
 {
-	uint8_t count;
-	uint32_t tmp;
-	bool allocated = false;
+    uint8_t count;
+    uint32_t tmp;
+    bool allocated = false;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	tmp = _dma_inst.allocated_channels;
+    tmp = _dma_inst.allocated_channels;
 
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-		if (!(tmp & 0x00000001)) {
-			/* If free channel found, set as allocated and return
-			 *number */
+    for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count)
+    {
+        if (!(tmp & 0x00000001))
+        {
+            /* If free channel found, set as allocated and return
+             *number */
 
-			_dma_inst.allocated_channels |= 1 << count;
-			_dma_inst.free_channels--;
-			allocated = true;
+            _dma_inst.allocated_channels |= 1 << count;
+            _dma_inst.free_channels--;
+            allocated = true;
 
-			break;
-		}
+            break;
+        }
 
-		tmp = tmp >> 1;
-	}
+        tmp = tmp >> 1;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	if (!allocated) {
-		return DMA_INVALID_CHANNEL;
-	} else {
-		return count;
-	}
+    if (!allocated)
+    {
+        return DMA_INVALID_CHANNEL;
+    } else {
+        return count;
+    }
 }
 
 /**
@@ -131,8 +134,8 @@ static uint8_t _dma_find_first_free_channel_and_allocate(void)
  */
 static void _dma_release_channel(uint8_t channel)
 {
-	_dma_inst.allocated_channels &= ~(1 << channel);
-	_dma_inst.free_channels++;
+    _dma_inst.allocated_channels &= ~(1 << channel);
+    _dma_inst.free_channels++;
 }
 
 /**
@@ -143,39 +146,41 @@ static void _dma_release_channel(uint8_t channel)
  *
  */
 static void _dma_set_config(struct dma_resource *resource,
-		struct dma_resource_config *resource_config)
+        struct dma_resource_config *resource_config)
 {
-	Assert(resource);
-	Assert(resource_config);
-	uint32_t temp_CHCTRLB_reg;
-	system_interrupt_enter_critical_section();
+    Assert(resource);
+    Assert(resource_config);
+    uint32_t temp_CHCTRLB_reg;
+    system_interrupt_enter_critical_section();
 
-	/** Select the DMA channel and clear software trigger */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
+    /** Select the DMA channel and clear software trigger */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
 
-	temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
-			DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
-			DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
+    temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
+            DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
+            DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
 
 
-	if(resource_config->event_config.input_action){
-	temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
-				resource_config->event_config.input_action);
-	}
+    if(resource_config->event_config.input_action)
+    {
+    temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
+                resource_config->event_config.input_action);
+    }
 
-	/** Enable event output, the event output selection is configured in
-	 * each transfer descriptor  */
-	if (resource_config->event_config.event_output_enable) {
-		temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
-	}
+    /** Enable event output, the event output selection is configured in
+     * each transfer descriptor  */
+    if (resource_config->event_config.event_output_enable)
+    {
+        temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
+    }
 
-	/* Write config to CTRLB register */
-	DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
+    /* Write config to CTRLB register */
+    DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
 
 
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -184,71 +189,77 @@ static void _dma_set_config(struct dma_resource *resource,
  */
 void DMAC_Handler( void )
 {
-	uint8_t active_channel;
-	struct dma_resource *resource;
-	uint8_t isr;
-	uint32_t write_size;
-	uint32_t total_size;
-
-	system_interrupt_enter_critical_section();
-
-	/* Get Pending channel */
-	active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
-
-	Assert(_dma_active_resource[active_channel]);
-
-	/* Get active DMA resource based on channel */
-	resource = _dma_active_resource[active_channel];
-
-	/* Select the active channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	isr = DMAC->CHINTFLAG.reg;
-
-	/* Calculate block transfer size of the DMA transfer */
-	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
-	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
-	resource->transfered_size = total_size - write_size;
-
-	/* DMA channel interrupt handler */
-	if (isr & DMAC_CHINTENCLR_TERR) {
-		/* Clear transfer error flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
-
-		/* Set I/O ERROR status */
-		resource->job_status = STATUS_ERR_IO;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
-				(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
-			resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
-		}
-	} else if (isr & DMAC_CHINTENCLR_TCMPL) {
-		/* Clear the transfer complete flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
-
-		/* Set job status */
-		resource->job_status = STATUS_OK;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
-				(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
-			resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
-		}
-	} else if (isr & DMAC_CHINTENCLR_SUSP) {
-		/* Clear channel suspend flag */
-		DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
-
-		/* Set job status */
-		resource->job_status = STATUS_SUSPEND;
-
-		/* Execute the callback function */
-		if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
-			(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){
-			resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
-		}
-	}
-
-	system_interrupt_leave_critical_section();
+    uint8_t active_channel;
+    struct dma_resource *resource;
+    uint8_t isr;
+    uint32_t write_size;
+    uint32_t total_size;
+
+    system_interrupt_enter_critical_section();
+
+    /* Get Pending channel */
+    active_channel =  DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
+
+    Assert(_dma_active_resource[active_channel]);
+
+    /* Get active DMA resource based on channel */
+    resource = _dma_active_resource[active_channel];
+
+    /* Select the active channel */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    isr = DMAC->CHINTFLAG.reg;
+
+    /* Calculate block transfer size of the DMA transfer */
+    total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+    write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+    resource->transfered_size = total_size - write_size;
+
+    /* DMA channel interrupt handler */
+    if (isr & DMAC_CHINTENCLR_TERR)
+    {
+        /* Clear transfer error flag */
+        DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
+
+        /* Set I/O ERROR status */
+        resource->job_status = STATUS_ERR_IO;
+
+        /* Execute the callback function */
+        if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
+                (resource->callback[DMA_CALLBACK_TRANSFER_ERROR]))
+                {
+            resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
+        }
+    } else if (isr & DMAC_CHINTENCLR_TCMPL)
+    {
+        /* Clear the transfer complete flag */
+        DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
+
+        /* Set job status */
+        resource->job_status = STATUS_OK;
+
+        /* Execute the callback function */
+        if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
+                (resource->callback[DMA_CALLBACK_TRANSFER_DONE]))
+                {
+            resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
+        }
+    } else if (isr & DMAC_CHINTENCLR_SUSP)
+    {
+        /* Clear channel suspend flag */
+        DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
+
+        /* Set job status */
+        resource->job_status = STATUS_SUSPEND;
+
+        /* Execute the callback function */
+        if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
+            (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND]))
+            {
+            resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
+        }
+    }
+
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -271,19 +282,19 @@ void DMAC_Handler( void )
  */
 void dma_get_config_defaults(struct dma_resource_config *config)
 {
-	Assert(config);
-	/* Set as priority 0 */
-	config->priority = DMA_PRIORITY_LEVEL_0;
-	/* Only software/event trigger */
-	config->peripheral_trigger = 0;
-	/* Transaction trigger */
-	config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
-
-	/* Event configurations, no event input/output */
-	config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
-	config->event_config.event_output_enable = false;
+    Assert(config);
+    /* Set as priority 0 */
+    config->priority = DMA_PRIORITY_LEVEL_0;
+    /* Only software/event trigger */
+    config->peripheral_trigger = 0;
+    /* Transaction trigger */
+    config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION;
+
+    /* Event configurations, no event input/output */
+    config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
+    config->event_config.event_output_enable = false;
 #ifdef FEATURE_DMA_CHANNEL_STANDBY
-	config->run_in_standby = false;
+    config->run_in_standby = false;
 #endif
 }
 
@@ -301,74 +312,77 @@ void dma_get_config_defaults(struct dma_resource_config *config)
  * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
  */
 enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config)
+        struct dma_resource_config *config)
 {
-	uint8_t new_channel;
+    uint8_t new_channel;
 
-	Assert(resource);
+    Assert(resource);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (!_dma_inst._dma_init) {
-		/* Initialize clocks for DMA */
+    if (!_dma_inst._dma_init)
+    {
+        /* Initialize clocks for DMA */
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-		system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
+        system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
 #else
-		system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
-				PM_APBBMASK_DMAC);
+        system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
+                PM_APBBMASK_DMAC);
 #endif
 
-		/* Perform a software reset before enable DMA controller */
-		DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
-		DMAC->CTRL.reg = DMAC_CTRL_SWRST;
+        /* Perform a software reset before enable DMA controller */
+        DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
+        DMAC->CTRL.reg = DMAC_CTRL_SWRST;
 
-		/* Setup descriptor base address and write back section base
-		 * address */
-		DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
-		DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
+        /* Setup descriptor base address and write back section base
+         * address */
+        DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
+        DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
 
-		/* Enable all priority level at the same time */
-		DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
+        /* Enable all priority level at the same time */
+        DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
 
-		_dma_inst._dma_init = true;
-	}
+        _dma_inst._dma_init = true;
+    }
 
-	/* Find the proper channel */
-	new_channel = _dma_find_first_free_channel_and_allocate();
+    /* Find the proper channel */
+    new_channel = _dma_find_first_free_channel_and_allocate();
 
-	/* If no channel available, return not found */
-	if (new_channel == DMA_INVALID_CHANNEL) {
-		system_interrupt_leave_critical_section();
+    /* If no channel available, return not found */
+    if (new_channel == DMA_INVALID_CHANNEL)
+    {
+        system_interrupt_leave_critical_section();
 
-		return STATUS_ERR_NOT_FOUND;
-	}
+        return STATUS_ERR_NOT_FOUND;
+    }
 
-	/* Set the channel */
-	resource->channel_id = new_channel;
+    /* Set the channel */
+    resource->channel_id = new_channel;
 
-	/** Perform a reset for the allocated channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
-	DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
+    /** Perform a reset for the allocated channel */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
+    DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
 
 #ifdef FEATURE_DMA_CHANNEL_STANDBY
-	if(config->run_in_standby){
-		DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
-	}
+    if(config->run_in_standby)
+    {
+        DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
+    }
 #endif
 
-	/** Configure the DMA control,channel registers and descriptors here */
-	_dma_set_config(resource, config);
+    /** Configure the DMA control,channel registers and descriptors here */
+    _dma_set_config(resource, config);
 
-	resource->descriptor = NULL;
+    resource->descriptor = NULL;
 
-	/* Log the DMA resource into the internal DMA resource pool */
-	_dma_active_resource[resource->channel_id] = resource;
+    /* Log the DMA resource into the internal DMA resource pool */
+    _dma_active_resource[resource->channel_id] = resource;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -386,32 +400,34 @@ enum status_code dma_allocate(struct dma_resource *resource,
  */
 enum status_code dma_free(struct dma_resource *resource)
 {
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+    Assert(resource);
+    Assert(resource->channel_id != DMA_INVALID_CHANNEL);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Check if channel is busy */
-	if (dma_is_busy(resource)) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
+    /* Check if channel is busy */
+    if (dma_is_busy(resource))
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_BUSY;
+    }
 
-	/* Check if DMA resource was not allocated */
-	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
-		system_interrupt_leave_critical_section();
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
+    /* Check if DMA resource was not allocated */
+    if (!(_dma_inst.allocated_channels & (1 << resource->channel_id)))
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
 
-	/* Release the DMA resource */
-	_dma_release_channel(resource->channel_id);
+    /* Release the DMA resource */
+    _dma_release_channel(resource->channel_id);
 
-	/* Reset the item in the DMA resource pool */
-	_dma_active_resource[resource->channel_id] = NULL;
+    /* Reset the item in the DMA resource pool */
+    _dma_active_resource[resource->channel_id] = NULL;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -429,42 +445,44 @@ enum status_code dma_free(struct dma_resource *resource)
  */
 enum status_code dma_start_transfer_job(struct dma_resource *resource)
 {
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+    Assert(resource);
+    Assert(resource->channel_id != DMA_INVALID_CHANNEL);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Check if resource was busy */
-	if (resource->job_status == STATUS_BUSY) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
+    /* Check if resource was busy */
+    if (resource->job_status == STATUS_BUSY)
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_BUSY;
+    }
 
-	/* Check if transfer size is valid */
-	if (resource->descriptor->BTCNT.reg == 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if transfer size is valid */
+    if (resource->descriptor->BTCNT.reg == 0)
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Enable DMA interrupt */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
+    /* Enable DMA interrupt */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
 
-	/* Set the interrupt flag */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
-	/* Set job status */
-	resource->job_status = STATUS_BUSY;
+    /* Set the interrupt flag */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
+    /* Set job status */
+    resource->job_status = STATUS_BUSY;
 
-	/* Set channel x descriptor 0 to the descriptor base address */
-	memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
-						sizeof(DmacDescriptor));
+    /* Set channel x descriptor 0 to the descriptor base address */
+    memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
+                        sizeof(DmacDescriptor));
 
-	/* Enable the transfer channel */
-	DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
+    /* Enable the transfer channel */
+    DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -483,25 +501,25 @@ enum status_code dma_start_transfer_job(struct dma_resource *resource)
  */
 void dma_abort_job(struct dma_resource *resource)
 {
-	uint32_t write_size;
-	uint32_t total_size;
+    uint32_t write_size;
+    uint32_t total_size;
 
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+    Assert(resource);
+    Assert(resource->channel_id != DMA_INVALID_CHANNEL);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLA.reg = 0;
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    DMAC->CHCTRLA.reg = 0;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	/* Get transferred size */
-	total_size = descriptor_section[resource->channel_id].BTCNT.reg;
-	write_size = _write_back_section[resource->channel_id].BTCNT.reg;
-	resource->transfered_size = total_size - write_size;
+    /* Get transferred size */
+    total_size = descriptor_section[resource->channel_id].BTCNT.reg;
+    write_size = _write_back_section[resource->channel_id].BTCNT.reg;
+    resource->transfered_size = total_size - write_size;
 
-	resource->job_status = STATUS_ABORTED;
+    resource->job_status = STATUS_ABORTED;
 }
 
 /**
@@ -521,18 +539,18 @@ void dma_abort_job(struct dma_resource *resource)
  */
 void dma_suspend_job(struct dma_resource *resource)
 {
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+    Assert(resource);
+    Assert(resource->channel_id != DMA_INVALID_CHANNEL);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the channel */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    /* Select the channel */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
 
-	/* Send the suspend request */
-	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
+    /* Send the suspend request */
+    DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -545,42 +563,46 @@ void dma_suspend_job(struct dma_resource *resource)
  */
 void dma_resume_job(struct dma_resource *resource)
 {
-	uint32_t bitmap_channel;
-	uint32_t count = 0;
-
-	Assert(resource);
-	Assert(resource->channel_id != DMA_INVALID_CHANNEL);
-
-	/* Get bitmap of the allocated DMA channel */
-	bitmap_channel = (1 << resource->channel_id);
-
-	/* Check if channel was suspended */
-	if (resource->job_status != STATUS_SUSPEND) {
-		return;
-	}
-
-	system_interrupt_enter_critical_section();
-
-	/* Send resume request */
-	DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
-	DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
-
-	system_interrupt_leave_critical_section();
-
-	/* Check if transfer job resumed */
-	for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
-		if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
-			break;
-		}
-	}
-
-	if (count < MAX_JOB_RESUME_COUNT) {
-		/* Job resumed */
-		resource->job_status = STATUS_BUSY;
-	} else {
-		/* Job resume timeout */
-		resource->job_status = STATUS_ERR_TIMEOUT;
-	}
+    uint32_t bitmap_channel;
+    uint32_t count = 0;
+
+    Assert(resource);
+    Assert(resource->channel_id != DMA_INVALID_CHANNEL);
+
+    /* Get bitmap of the allocated DMA channel */
+    bitmap_channel = (1 << resource->channel_id);
+
+    /* Check if channel was suspended */
+    if (resource->job_status != STATUS_SUSPEND)
+    {
+        return;
+    }
+
+    system_interrupt_enter_critical_section();
+
+    /* Send resume request */
+    DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
+    DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
+
+    system_interrupt_leave_critical_section();
+
+    /* Check if transfer job resumed */
+    for (count = 0; count < MAX_JOB_RESUME_COUNT; count++)
+    {
+        if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel)
+        {
+            break;
+        }
+    }
+
+    if (count < MAX_JOB_RESUME_COUNT)
+    {
+        /* Job resumed */
+        resource->job_status = STATUS_BUSY;
+    } else {
+        /* Job resume timeout */
+        resource->job_status = STATUS_ERR_TIMEOUT;
+    }
 }
 
 /**
@@ -594,25 +616,25 @@ void dma_resume_job(struct dma_resource *resource)
  *
  */
 void dma_descriptor_create(DmacDescriptor* descriptor,
-	struct dma_descriptor_config *config)
+    struct dma_descriptor_config *config)
 {
-	/* Set block transfer control */
-	descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
-	descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
-	descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
-	descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
-	descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
-	descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
-	descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
-	descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
-
-	/* Set transfer size, source address and destination address */
-	descriptor->BTCNT.reg = config->block_transfer_count;
-	descriptor->SRCADDR.reg = config->source_address;
-	descriptor->DSTADDR.reg = config->destination_address;
-
-	/* Set next transfer descriptor address */
-	descriptor->DESCADDR.reg = config->next_descriptor_address;
+    /* Set block transfer control */
+    descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
+    descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
+    descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
+    descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
+    descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
+    descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
+    descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
+    descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
+
+    /* Set transfer size, source address and destination address */
+    descriptor->BTCNT.reg = config->block_transfer_count;
+    descriptor->SRCADDR.reg = config->source_address;
+    descriptor->DSTADDR.reg = config->destination_address;
+
+    /* Set next transfer descriptor address */
+    descriptor->DESCADDR.reg = config->next_descriptor_address;
 }
 
 /**
@@ -629,26 +651,29 @@ void dma_descriptor_create(DmacDescriptor* descriptor,
  * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
  */
 enum status_code dma_add_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor)
+        DmacDescriptor* descriptor)
 {
-	DmacDescriptor* desc = resource->descriptor;
-
-	if (resource->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Look up for an empty space for the descriptor */
-	if (desc == NULL) {
-		resource->descriptor = descriptor;
-	} else {
-		/* Looking for end of descriptor link */
-		while(desc->DESCADDR.reg != 0) {
-			desc = (DmacDescriptor*)(desc->DESCADDR.reg);
-		}
-
-		/* Set to the end of descriptor list */
-		desc->DESCADDR.reg = (uint32_t)descriptor;
-	}
-
-	return STATUS_OK;
+    DmacDescriptor* desc = resource->descriptor;
+
+    if (resource->job_status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Look up for an empty space for the descriptor */
+    if (desc == NULL)
+    {
+        resource->descriptor = descriptor;
+    } else {
+        /* Looking for end of descriptor link */
+        while(desc->DESCADDR.reg != 0)
+        {
+            desc = (DmacDescriptor*)(desc->DESCADDR.reg);
+        }
+
+        /* Set to the end of descriptor list */
+        desc->DESCADDR.reg = (uint32_t)descriptor;
+    }
+
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h
index 6aea77a9d04f..f2a4e723e3d0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma.h
@@ -336,32 +336,32 @@ extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM];
 
 /** DMA priority level. */
 enum dma_priority_level {
-	/** Priority level 0. */
-	DMA_PRIORITY_LEVEL_0,
-	/** Priority level 1. */
-	DMA_PRIORITY_LEVEL_1,
-	/** Priority level 2. */
-	DMA_PRIORITY_LEVEL_2,
-	/** Priority level 3. */
-	DMA_PRIORITY_LEVEL_3,
+    /** Priority level 0. */
+    DMA_PRIORITY_LEVEL_0,
+    /** Priority level 1. */
+    DMA_PRIORITY_LEVEL_1,
+    /** Priority level 2. */
+    DMA_PRIORITY_LEVEL_2,
+    /** Priority level 3. */
+    DMA_PRIORITY_LEVEL_3,
 };
 
 /** DMA input actions. */
 enum dma_event_input_action {
-	/** No action. */
-	DMA_EVENT_INPUT_NOACT,
-	/** Normal transfer and periodic transfer trigger. */
-	DMA_EVENT_INPUT_TRIG,
-	/** Conditional transfer trigger. */
-	DMA_EVENT_INPUT_CTRIG,
-	/** Conditional block transfer. */
-	DMA_EVENT_INPUT_CBLOCK,
-	/** Channel suspend operation. */
-	DMA_EVENT_INPUT_SUSPEND,
-	/** Channel resume operation. */
-	DMA_EVENT_INPUT_RESUME,
-	/** Skip next block suspend action. */
-	DMA_EVENT_INPUT_SSKIP,
+    /** No action. */
+    DMA_EVENT_INPUT_NOACT,
+    /** Normal transfer and periodic transfer trigger. */
+    DMA_EVENT_INPUT_TRIG,
+    /** Conditional transfer trigger. */
+    DMA_EVENT_INPUT_CTRIG,
+    /** Conditional block transfer. */
+    DMA_EVENT_INPUT_CBLOCK,
+    /** Channel suspend operation. */
+    DMA_EVENT_INPUT_SUSPEND,
+    /** Channel resume operation. */
+    DMA_EVENT_INPUT_RESUME,
+    /** Skip next block suspend action. */
+    DMA_EVENT_INPUT_SSKIP,
 };
 
 /**
@@ -370,22 +370,22 @@ enum dma_event_input_action {
  * STEPSEL setting.
  */
 enum dma_address_increment_stepsize {
-	/** The address is incremented by (beat size * 1). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
-	/** The address is incremented by (beat size * 2). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
-	/** The address is incremented by (beat size * 4). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
-	/** The address is incremented by (beat size * 8). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
-	/** The address is incremented by (beat size * 16). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
-	/** The address is incremented by (beat size * 32). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
-	/** The address is incremented by (beat size * 64). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
-	/** The address is incremented by (beat size * 128). */
-	DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
+    /** The address is incremented by (beat size * 1). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0,
+    /** The address is incremented by (beat size * 2). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_2,
+    /** The address is incremented by (beat size * 4). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_4,
+    /** The address is incremented by (beat size * 8). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_8,
+    /** The address is incremented by (beat size * 16). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_16,
+    /** The address is incremented by (beat size * 32). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_32,
+    /** The address is incremented by (beat size * 64). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_64,
+    /** The address is incremented by (beat size * 128). */
+    DMA_ADDRESS_INCREMENT_STEP_SIZE_128,
 };
 
 /**
@@ -393,78 +393,78 @@ enum dma_address_increment_stepsize {
  * is applied to source or destination address.
  */
 enum dma_step_selection {
-	/** Step size settings apply to the destination address. */
-	DMA_STEPSEL_DST = 0,
-	/** Step size settings apply to the source address. */
-	DMA_STEPSEL_SRC,
+    /** Step size settings apply to the destination address. */
+    DMA_STEPSEL_DST = 0,
+    /** Step size settings apply to the source address. */
+    DMA_STEPSEL_SRC,
 };
 
 /** The basic transfer unit in DMAC is a beat, which is defined as a
  *  single bus access. Its size is configurable and applies to both read
  *  and write. */
 enum dma_beat_size {
-	/** 8-bit access. */
-	DMA_BEAT_SIZE_BYTE = 0,
-	/** 16-bit access. */
-	DMA_BEAT_SIZE_HWORD,
-	/** 32-bit access. */
-	DMA_BEAT_SIZE_WORD,
+    /** 8-bit access. */
+    DMA_BEAT_SIZE_BYTE = 0,
+    /** 16-bit access. */
+    DMA_BEAT_SIZE_HWORD,
+    /** 32-bit access. */
+    DMA_BEAT_SIZE_WORD,
 };
 
 /**
  * Block action definitions.
  */
 enum dma_block_action {
-	/** No action. */
-	DMA_BLOCK_ACTION_NOACT = 0,
-	/** Channel in normal operation and sets transfer complete interrupt flag
-	 *  after block transfer. */
-	DMA_BLOCK_ACTION_INT,
-	/** Trigger channel suspend after block transfer and sets channel
-	 *  suspend interrupt flag once the channel is suspended. */
-	DMA_BLOCK_ACTION_SUSPEND,
-	/** Sets transfer complete interrupt flag after a block transfer and
-	 *  trigger channel suspend. The channel suspend interrupt flag will be set
-	 *  once the channel is suspended. */
-	DMA_BLOCK_ACTION_BOTH,
+    /** No action. */
+    DMA_BLOCK_ACTION_NOACT = 0,
+    /** Channel in normal operation and sets transfer complete interrupt flag
+     *  after block transfer. */
+    DMA_BLOCK_ACTION_INT,
+    /** Trigger channel suspend after block transfer and sets channel
+     *  suspend interrupt flag once the channel is suspended. */
+    DMA_BLOCK_ACTION_SUSPEND,
+    /** Sets transfer complete interrupt flag after a block transfer and
+     *  trigger channel suspend. The channel suspend interrupt flag will be set
+     *  once the channel is suspended. */
+    DMA_BLOCK_ACTION_BOTH,
 };
 
 /** Event output selection. */
 enum dma_event_output_selection {
-	/** Event generation disable. */
-	DMA_EVENT_OUTPUT_DISABLE = 0,
-	/** Event strobe when block transfer complete. */
-	DMA_EVENT_OUTPUT_BLOCK,
-	/** Event output reserved. */
-	DMA_EVENT_OUTPUT_RESERVED,
-	/** Event strobe when beat transfer complete. */
-	DMA_EVENT_OUTPUT_BEAT,
+    /** Event generation disable. */
+    DMA_EVENT_OUTPUT_DISABLE = 0,
+    /** Event strobe when block transfer complete. */
+    DMA_EVENT_OUTPUT_BLOCK,
+    /** Event output reserved. */
+    DMA_EVENT_OUTPUT_RESERVED,
+    /** Event strobe when beat transfer complete. */
+    DMA_EVENT_OUTPUT_BEAT,
 };
 
 /** DMA trigger action type. */
 enum dma_transfer_trigger_action{
-	/** Perform a block transfer when triggered. */
-	DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
-	/** Perform a beat transfer when triggered. */
-	DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
-	/** Perform a transaction when triggered. */
-	DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
+    /** Perform a block transfer when triggered. */
+    DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val,
+    /** Perform a beat transfer when triggered. */
+    DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val,
+    /** Perform a transaction when triggered. */
+    DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val,
 };
 
 /**
  * Callback types for DMA callback driver.
  */
 enum dma_callback_type {
-	/** Callback for any of transfer errors. A transfer error is flagged
-     *	if a bus error is detected during an AHB access or when the DMAC
-	 *  fetches an invalid descriptor. */
-	DMA_CALLBACK_TRANSFER_ERROR,
-	/** Callback for transfer complete. */
-	DMA_CALLBACK_TRANSFER_DONE,
-	/** Callback for channel suspend. */
-	DMA_CALLBACK_CHANNEL_SUSPEND,
-	/** Number of available callbacks. */
-	DMA_CALLBACK_N,
+    /** Callback for any of transfer errors. A transfer error is flagged
+     *  if a bus error is detected during an AHB access or when the DMAC
+     *  fetches an invalid descriptor. */
+    DMA_CALLBACK_TRANSFER_ERROR,
+    /** Callback for transfer complete. */
+    DMA_CALLBACK_TRANSFER_DONE,
+    /** Callback for channel suspend. */
+    DMA_CALLBACK_CHANNEL_SUSPEND,
+    /** Number of available callbacks. */
+    DMA_CALLBACK_N,
 };
 
 /**
@@ -474,61 +474,61 @@ enum dma_callback_type {
  *
  */
 struct dma_descriptor_config {
-	/** Descriptor valid flag used to identify whether a descriptor is
-	    valid or not */
-	bool descriptor_valid;
-	/** This is used to generate an event on specific transfer action in
-	    a channel. Supported only in four lower channels. */
-	enum dma_event_output_selection event_output_selection;
-	/** Action taken when a block transfer is completed */
-	enum dma_block_action block_action;
-	/** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
-	enum dma_beat_size beat_size;
-	/** Used for enabling the source address increment */
-	bool src_increment_enable;
-	/** Used for enabling the destination address increment */
-	bool dst_increment_enable;
-	/** This bit selects whether the source or destination address is
-	    using the step size settings */
-	enum dma_step_selection step_selection;
-	/** The step size for source/destination address increment.
-	    The next address is calculated
-	    as next_addr = addr + (2^step_size * beat size). */
-	enum dma_address_increment_stepsize step_size;
-	/** It is the number of beats in a block. This count value is
-	 * decremented by one after each beat data transfer. */
-	uint16_t block_transfer_count;
-	/** Transfer source address */
-	uint32_t source_address;
-	/** Transfer destination address */
-	uint32_t destination_address;
-	/** Set to zero for static descriptors. This must have a valid memory
-	    address for linked descriptors. */
-	uint32_t next_descriptor_address;
+    /** Descriptor valid flag used to identify whether a descriptor is
+        valid or not */
+    bool descriptor_valid;
+    /** This is used to generate an event on specific transfer action in
+        a channel. Supported only in four lower channels. */
+    enum dma_event_output_selection event_output_selection;
+    /** Action taken when a block transfer is completed */
+    enum dma_block_action block_action;
+    /** Beat size is configurable as 8-bit, 16-bit, or 32-bit */
+    enum dma_beat_size beat_size;
+    /** Used for enabling the source address increment */
+    bool src_increment_enable;
+    /** Used for enabling the destination address increment */
+    bool dst_increment_enable;
+    /** This bit selects whether the source or destination address is
+        using the step size settings */
+    enum dma_step_selection step_selection;
+    /** The step size for source/destination address increment.
+        The next address is calculated
+        as next_addr = addr + (2^step_size * beat size). */
+    enum dma_address_increment_stepsize step_size;
+    /** It is the number of beats in a block. This count value is
+     * decremented by one after each beat data transfer. */
+    uint16_t block_transfer_count;
+    /** Transfer source address */
+    uint32_t source_address;
+    /** Transfer destination address */
+    uint32_t destination_address;
+    /** Set to zero for static descriptors. This must have a valid memory
+        address for linked descriptors. */
+    uint32_t next_descriptor_address;
 };
 
 /** Configurations for DMA events. */
 struct dma_events_config {
-	/** Event input actions */
-	enum dma_event_input_action input_action;
-	/** Enable DMA event output */
-	bool event_output_enable;
+    /** Event input actions */
+    enum dma_event_input_action input_action;
+    /** Enable DMA event output */
+    bool event_output_enable;
 };
 
 /** DMA configurations for transfer. */
 struct dma_resource_config {
-	/** DMA transfer priority */
-	enum dma_priority_level priority;
-	/**DMA peripheral trigger index */
-	uint8_t peripheral_trigger;
-	/** DMA trigger action */
-	enum dma_transfer_trigger_action trigger_action;
+    /** DMA transfer priority */
+    enum dma_priority_level priority;
+    /**DMA peripheral trigger index */
+    uint8_t peripheral_trigger;
+    /** DMA trigger action */
+    enum dma_transfer_trigger_action trigger_action;
 #ifdef FEATURE_DMA_CHANNEL_STANDBY
-	/** Keep DMA channel enabled in standby sleep mode if true */
-	bool run_in_standby;
+    /** Keep DMA channel enabled in standby sleep mode if true */
+    bool run_in_standby;
 #endif
-	/** DMA events configurations */
-	struct dma_events_config event_config;
+    /** DMA events configurations */
+    struct dma_events_config event_config;
 };
 
 /** Forward definition of the DMA resource. */
@@ -538,18 +538,18 @@ typedef void (*dma_callback_t)(struct dma_resource *const resource);
 
 /** Structure for DMA transfer resource. */
 struct dma_resource {
-	/** Allocated DMA channel ID */
-	uint8_t channel_id;
-	/** Array of callback functions for DMA transfer job */
-	dma_callback_t callback[DMA_CALLBACK_N];
-	/** Bit mask for enabled callbacks */
-	uint8_t callback_enable;
-	/** Status of the last job */
-	volatile enum status_code job_status;
-	/** Transferred data size */
-	uint32_t transfered_size;
-	/** DMA transfer descriptor */
-	DmacDescriptor* descriptor;
+    /** Allocated DMA channel ID */
+    uint8_t channel_id;
+    /** Array of callback functions for DMA transfer job */
+    dma_callback_t callback[DMA_CALLBACK_N];
+    /** Bit mask for enabled callbacks */
+    uint8_t callback_enable;
+    /** Status of the last job */
+    volatile enum status_code job_status;
+    /** Transferred data size */
+    uint32_t transfered_size;
+    /** DMA transfer descriptor */
+    DmacDescriptor* descriptor;
 };
 
 /**
@@ -561,9 +561,9 @@ struct dma_resource {
  */
 static inline enum status_code dma_get_job_status(struct dma_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return resource->job_status;
+    return resource->job_status;
 }
 
 /**
@@ -578,9 +578,9 @@ static inline enum status_code dma_get_job_status(struct dma_resource *resource)
  */
 static inline bool dma_is_busy(struct dma_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return (resource->job_status == STATUS_BUSY);
+    return (resource->job_status == STATUS_BUSY);
 }
 
 /**
@@ -591,12 +591,12 @@ static inline bool dma_is_busy(struct dma_resource *resource)
  *
  */
 static inline void dma_enable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->callback_enable |= 1 << type;
-	g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
+    resource->callback_enable |= 1 << type;
+    g_chan_interrupt_flag[resource->channel_id] |= (1UL << type);
 }
 
 /**
@@ -607,13 +607,13 @@ static inline void dma_enable_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_disable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->callback_enable &= ~(1 << type);
-	g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
-	DMAC->CHINTENCLR.reg = (1UL << type);
+    resource->callback_enable &= ~(1 << type);
+    g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK);
+    DMAC->CHINTENCLR.reg = (1UL << type);
 }
 
 /**
@@ -630,11 +630,11 @@ static inline void dma_disable_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_register_callback(struct dma_resource *resource,
-		dma_callback_t callback, enum dma_callback_type type)
+        dma_callback_t callback, enum dma_callback_type type)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->callback[type] = callback;
+    resource->callback[type] = callback;
 }
 
 /**
@@ -653,11 +653,11 @@ static inline void dma_register_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_unregister_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->callback[type] = NULL;
+    resource->callback[type] = NULL;
 }
 
 /**
@@ -669,10 +669,11 @@ static inline void dma_unregister_callback(struct dma_resource *resource,
  *
  * \param[in] resource Pointer to the DMA resource
  */
-static inline void dma_trigger_transfer(struct dma_resource *resource) {
-	Assert(resource);
+static inline void dma_trigger_transfer(struct dma_resource *resource)
+{
+    Assert(resource);
 
-	DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
+    DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id);
 }
 
 /**
@@ -701,32 +702,32 @@ static inline void dma_trigger_transfer(struct dma_resource *resource) {
  */
 static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config)
 {
-	Assert(config);
-
-	/* Set descriptor as valid */
-	config->descriptor_valid = true;
-	/* Disable event output */
-	config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
-	/* No block action */
-	config->block_action = DMA_BLOCK_ACTION_NOACT;
-	/* Set beat size to one byte */
-	config->beat_size = DMA_BEAT_SIZE_BYTE;
-	/* Enable source increment */
-	config->src_increment_enable = true;
-	/* Enable destination increment */
-	config->dst_increment_enable = true;
-	/* Step size is applied to the destination address */
-	config->step_selection = DMA_STEPSEL_DST;
-	/* Address increment is beat size multiplied by 1*/
-	config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
-	/* Default transfer size is set to 0 */
-	config->block_transfer_count = 0;
-	/* Default source address is set to NULL */
-	config->source_address = (uint32_t)NULL;
-	/* Default destination address is set to NULL */
-	config->destination_address = (uint32_t)NULL;
-	/** Next descriptor address set to 0 */
-	config->next_descriptor_address = 0;
+    Assert(config);
+
+    /* Set descriptor as valid */
+    config->descriptor_valid = true;
+    /* Disable event output */
+    config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE;
+    /* No block action */
+    config->block_action = DMA_BLOCK_ACTION_NOACT;
+    /* Set beat size to one byte */
+    config->beat_size = DMA_BEAT_SIZE_BYTE;
+    /* Enable source increment */
+    config->src_increment_enable = true;
+    /* Enable destination increment */
+    config->dst_increment_enable = true;
+    /* Step size is applied to the destination address */
+    config->step_selection = DMA_STEPSEL_DST;
+    /* Address increment is beat size multiplied by 1*/
+    config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1;
+    /* Default transfer size is set to 0 */
+    config->block_transfer_count = 0;
+    /* Default source address is set to NULL */
+    config->source_address = (uint32_t)NULL;
+    /* Default destination address is set to NULL */
+    config->destination_address = (uint32_t)NULL;
+    /** Next descriptor address set to 0 */
+    config->next_descriptor_address = 0;
 }
 
 /**
@@ -736,11 +737,11 @@ static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_conf
  *
  */
 static inline void dma_update_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor)
+        DmacDescriptor* descriptor)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->descriptor = descriptor;
+    resource->descriptor = descriptor;
 }
 
 /**
@@ -751,23 +752,23 @@ static inline void dma_update_descriptor(struct dma_resource *resource,
  */
 static inline void dma_reset_descriptor(struct dma_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	resource->descriptor = NULL;
+    resource->descriptor = NULL;
 }
 
 void dma_get_config_defaults(struct dma_resource_config *config);
 enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config);
+        struct dma_resource_config *config);
 enum status_code dma_free(struct dma_resource *resource);
 enum status_code dma_start_transfer_job(struct dma_resource *resource);
 void dma_abort_job(struct dma_resource *resource);
 void dma_suspend_job(struct dma_resource *resource);
 void dma_resume_job(struct dma_resource *resource);
 void dma_descriptor_create(DmacDescriptor* descriptor,
-	struct dma_descriptor_config *config);
+    struct dma_descriptor_config *config);
 enum status_code dma_add_descriptor(struct dma_resource *resource,
-		DmacDescriptor* descriptor);
+        DmacDescriptor* descriptor);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h
index 3d8c27c197d5..1cf8fe714dd2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_crc.h
@@ -57,28 +57,28 @@ extern "C" {
 
 /** CRC Polynomial Type. */
 enum crc_polynomial_type {
-	/** CRC16 (CRC-CCITT). */
-	CRC_TYPE_16,
-	/** CRC32 (IEEE 802.3). */
-	CRC_TYPE_32,
+    /** CRC16 (CRC-CCITT). */
+    CRC_TYPE_16,
+    /** CRC32 (IEEE 802.3). */
+    CRC_TYPE_32,
 };
 
 /** CRC Beat Type. */
 enum crc_beat_size {
-	/** Byte bus access. */
-	CRC_BEAT_SIZE_BYTE,
-	/** Half-word bus access. */
-	CRC_BEAT_SIZE_HWORD,
-	/** Word bus access. */
-	CRC_BEAT_SIZE_WORD,
+    /** Byte bus access. */
+    CRC_BEAT_SIZE_BYTE,
+    /** Half-word bus access. */
+    CRC_BEAT_SIZE_HWORD,
+    /** Word bus access. */
+    CRC_BEAT_SIZE_WORD,
 };
 
 /** Configurations for CRC calculation. */
 struct dma_crc_config {
-	/** CRC polynomial type. */
-	enum crc_polynomial_type type;
-	/** CRC beat size. */
-	enum crc_beat_size size;
+    /** CRC polynomial type. */
+    enum crc_polynomial_type type;
+    /** CRC beat size. */
+    enum crc_beat_size size;
 };
 
 /**
@@ -92,10 +92,10 @@ struct dma_crc_config {
  */
 static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->type = CRC_TYPE_16;
-	config->size = CRC_BEAT_SIZE_BYTE;
+    config->type = CRC_TYPE_16;
+    config->size = CRC_BEAT_SIZE_BYTE;
 }
 
 /**
@@ -112,19 +112,20 @@ static inline void dma_crc_get_config_defaults(struct dma_crc_config *config)
  * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
  */
 static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
-		struct dma_crc_config *config)
+        struct dma_crc_config *config)
 {
-	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
-		return STATUS_BUSY;
-	}
+    if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
-		DMAC_CRCCTRL_CRCPOLY(config->type) |
-		DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
+    DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+        DMAC_CRCCTRL_CRCPOLY(config->type) |
+        DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET);
 
-	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+    DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -133,8 +134,8 @@ static inline enum status_code dma_crc_channel_enable(uint32_t channel_id,
  */
 static inline void dma_crc_disable(void)
 {
-	DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
-	DMAC->CRCCTRL.reg = 0;
+    DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
+    DMAC->CRCCTRL.reg = 0;
 }
 
 /**
@@ -144,11 +145,12 @@ static inline void dma_crc_disable(void)
  */
 static inline uint32_t dma_crc_get_checksum(void)
 {
-	if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) {
-		DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
-	}
+    if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val)
+    {
+        DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
+    }
 
-	return DMAC->CRCCHKSUM.reg;
+    return DMAC->CRCCHKSUM.reg;
 }
 
 /**
@@ -163,27 +165,30 @@ static inline uint32_t dma_crc_get_checksum(void)
  * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet
  */
 static inline enum status_code dma_crc_io_enable(
-		struct dma_crc_config *config)
+        struct dma_crc_config *config)
 {
-	if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) {
-		return STATUS_BUSY;
-	}
+    if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) {
-		return STATUS_BUSY;
-	}
+    if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE)
+    {
+        return STATUS_BUSY;
+    }
 
-	DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
-		DMAC_CRCCTRL_CRCPOLY(config->type) |
-		DMAC_CRCCTRL_CRCSRC_IO;
+    DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) |
+        DMAC_CRCCTRL_CRCPOLY(config->type) |
+        DMAC_CRCCTRL_CRCSRC_IO;
 
-	if (config->type == CRC_TYPE_32) {
-		DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
-	}
+    if (config->type == CRC_TYPE_32)
+    {
+        DMAC->CRCCHKSUM.reg = 0xFFFFFFFF;
+    }
 
-	DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
+    DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -197,30 +202,34 @@ static inline enum status_code dma_crc_io_enable(
  * \return Calculated CRC checksum value.
  */
 static inline void dma_crc_io_calculation(void *buffer,
-		 uint32_t total_beat_size)
+         uint32_t total_beat_size)
 {
-	uint32_t counter = total_beat_size;
-	uint8_t *buffer_8;
-	uint16_t *buffer_16;
-	uint32_t *buffer_32;
-
-	for (counter=0; counter<total_beat_size; counter++) {
-		if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) {
-			buffer_8 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_8[counter];
-		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) {
-			buffer_16 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_16[counter];
-		} else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) {
-			buffer_32 = buffer;
-			DMAC->CRCDATAIN.reg = buffer_32[counter];
-		}
-		/* Wait several cycle to make sure CRC complete */
-		nop();
-		nop();
-		nop();
-		nop();
-	}
+    uint32_t counter = total_beat_size;
+    uint8_t *buffer_8;
+    uint16_t *buffer_16;
+    uint32_t *buffer_32;
+
+    for (counter=0; counter<total_beat_size; counter++)
+    {
+        if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE)
+        {
+            buffer_8 = buffer;
+            DMAC->CRCDATAIN.reg = buffer_8[counter];
+        } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD)
+        {
+            buffer_16 = buffer;
+            DMAC->CRCDATAIN.reg = buffer_16[counter];
+        } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD)
+        {
+            buffer_32 = buffer;
+            DMAC->CRCDATAIN.reg = buffer_32[counter];
+        }
+        /* Wait several cycle to make sure CRC complete */
+        nop();
+        nop();
+        nop();
+        nop();
+    }
 }
 
 #ifdef __cplusplus
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c
index d14f0e5ee2aa..74029c01dd35 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.c
@@ -48,15 +48,15 @@
 #include "dma_sam_b.h"
 
 struct _dma_module {
-	volatile bool _dma_init;
-	volatile uint32_t allocated_channels;
-	uint8_t free_channels;
+    volatile bool _dma_init;
+    volatile uint32_t allocated_channels;
+    uint8_t free_channels;
 };
 
 struct _dma_module _dma_inst = {
-	._dma_init = false,
-	.allocated_channels = 0,
-	.free_channels = CONF_MAX_USED_CHANNEL_NUM,
+    ._dma_init = false,
+    .allocated_channels = 0,
+    .free_channels = CONF_MAX_USED_CHANNEL_NUM,
 };
 
 /** Internal DMA resource pool. */
@@ -72,7 +72,7 @@ static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
  */
 static uint32_t get_channel_reg_val(uint8_t channel, uint32_t reg)
 {
-	return *(uint32_t*)(reg + 0x100*channel);
+    return *(uint32_t*)(reg + 0x100*channel);
 }
 
 /**
@@ -85,7 +85,7 @@ static uint32_t get_channel_reg_val(uint8_t channel, uint32_t reg)
  */
 static void set_channel_reg_val(uint8_t channel, uint32_t reg, uint32_t val)
 {
-	*(uint32_t*)(reg + 0x100*channel) = val;
+    *(uint32_t*)(reg + 0x100*channel) = val;
 }
 
 /**
@@ -97,7 +97,7 @@ static void set_channel_reg_val(uint8_t channel, uint32_t reg, uint32_t val)
  */
 uint8_t dma_get_status(uint8_t channel)
 {
-	return (uint8_t)get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_RAWSTAT_REG.reg);
+    return (uint8_t)get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_RAWSTAT_REG.reg);
 }
 
 /**
@@ -109,7 +109,7 @@ uint8_t dma_get_status(uint8_t channel)
  */
 uint8_t dma_get_interrupt_status(uint8_t channel)
 {
-	return get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+    return get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
 }
 
 /**
@@ -121,7 +121,7 @@ uint8_t dma_get_interrupt_status(uint8_t channel)
  */
 void dma_clear_interrupt_status(uint8_t channel, uint8_t flag)
 {
-	set_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1 << flag);
+    set_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1 << flag);
 }
 
 /**
@@ -135,32 +135,35 @@ void dma_clear_interrupt_status(uint8_t channel, uint8_t flag)
  */
 static uint8_t _dma_find_first_free_channel_and_allocate(void)
 {
-	uint8_t count;
-	uint32_t tmp;
-	bool allocated = false;
-
-	tmp = _dma_inst.allocated_channels;
-
-	for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
-		if (!(tmp & 0x00000001)) {
-			/* If free channel found, set as allocated and return
-			 *number */
-
-			_dma_inst.allocated_channels |= 1 << count;
-			_dma_inst.free_channels--;
-			allocated = true;
-
-			break;
-		}
-
-		tmp = tmp >> 1;
-	}
-
-	if (!allocated) {
-		return DMA_INVALID_CHANNEL;
-	} else {
-		return count;
-	}
+    uint8_t count;
+    uint32_t tmp;
+    bool allocated = false;
+
+    tmp = _dma_inst.allocated_channels;
+
+    for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count)
+    {
+        if (!(tmp & 0x00000001))
+        {
+            /* If free channel found, set as allocated and return
+             *number */
+
+            _dma_inst.allocated_channels |= 1 << count;
+            _dma_inst.free_channels--;
+            allocated = true;
+
+            break;
+        }
+
+        tmp = tmp >> 1;
+    }
+
+    if (!allocated)
+    {
+        return DMA_INVALID_CHANNEL;
+    } else {
+        return count;
+    }
 }
 
 /**
@@ -171,8 +174,8 @@ static uint8_t _dma_find_first_free_channel_and_allocate(void)
  */
 static void _dma_release_channel(uint8_t channel)
 {
-	_dma_inst.allocated_channels &= ~(1 << channel);
-	_dma_inst.free_channels++;
+    _dma_inst.allocated_channels &= ~(1 << channel);
+    _dma_inst.free_channels++;
 }
 
 /**
@@ -207,29 +210,29 @@ static void _dma_release_channel(uint8_t channel)
  */
 void dma_get_config_defaults(struct dma_resource_config *config)
 {
-	/* DMA source configuration */
-	config->src.max_burst = 1;
-	config->src.tokens = 1;
-	config->src.enable_inc_addr = true;
-	config->src.periph = MEMORY_DMA_PERIPHERAL;
-	config->src.periph_delay = 0;
-	config->src.enable_proi_top = false;
-	config->src.proi_top_index = 0;
-	config->src.enable_proi_high = false;
-	config->src.proi_high_index = 0;
-	/* DMA destination configuration */
-	config->des.max_burst = 1;
-	config->des.tokens = 1;
-	config->des.enable_inc_addr = true;
-	config->des.periph = MEMORY_DMA_PERIPHERAL;
-	config->des.periph_delay = 0;
-	config->des.enable_proi_top = false;
-	config->des.proi_top_index = 0;
-	config->des.enable_proi_high = false;
-	config->des.proi_high_index = 0;
-	/* DMA channel configuration */
-	config->enable_joint_mode = false;
-	config->swap = DMA_ENDIAN_NO_SWAP;
+    /* DMA source configuration */
+    config->src.max_burst = 1;
+    config->src.tokens = 1;
+    config->src.enable_inc_addr = true;
+    config->src.periph = MEMORY_DMA_PERIPHERAL;
+    config->src.periph_delay = 0;
+    config->src.enable_proi_top = false;
+    config->src.proi_top_index = 0;
+    config->src.enable_proi_high = false;
+    config->src.proi_high_index = 0;
+    /* DMA destination configuration */
+    config->des.max_burst = 1;
+    config->des.tokens = 1;
+    config->des.enable_inc_addr = true;
+    config->des.periph = MEMORY_DMA_PERIPHERAL;
+    config->des.periph_delay = 0;
+    config->des.enable_proi_top = false;
+    config->des.proi_top_index = 0;
+    config->des.enable_proi_high = false;
+    config->des.proi_high_index = 0;
+    /* DMA channel configuration */
+    config->enable_joint_mode = false;
+    config->swap = DMA_ENDIAN_NO_SWAP;
 }
 
 /**
@@ -240,45 +243,46 @@ void dma_get_config_defaults(struct dma_resource_config *config)
  *
  */
 static void _dma_set_config(struct dma_resource *resource,
-		struct dma_resource_config *config)
+        struct dma_resource_config *config)
 {
-	uint32_t regval = 0;
-
-	/* Static register configuration */
-	regval = PROV_DMA_CTRL_CH0_STATIC_REG0_RD_BURST_MAX_SIZE(config->src.max_burst)|
-			PROV_DMA_CTRL_CH0_STATIC_REG0_RD_TOKENS(config->src.tokens) |
-			(config->src.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG0.reg, regval);
-	/* Static register1 configuration */
-	regval = PROV_DMA_CTRL_CH0_STATIC_REG1_WR_BURST_MAX_SIZE(config->des.max_burst) |
-			PROV_DMA_CTRL_CH0_STATIC_REG1_WR_TOKENS(config->des.tokens) | 
-			(config->des.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG1.reg, regval);
-	/* Static register2 configuration */
-	regval = (config->enable_joint_mode << PROV_DMA_CTRL_CH0_STATIC_REG2_JOINT_Pos) |
-			PROV_DMA_CTRL_CH0_STATIC_REG2_END_SWAP(config->swap);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG2.reg, regval);
-	/* Static register4 configuration */
-	regval = PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_NUM(config->src.periph) |
-			PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_DELAY(config->src.periph_delay) |
-			PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_NUM(config->des.periph) |
-			PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_DELAY(config->des.periph_delay);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG4.reg, regval);
-	/* Priority channels configuration */
-	regval = PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP_NUM(config->src.proi_top_index) |
-			(PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP << config->src.enable_proi_top) |
-			PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH_NUM(config->src.proi_high_index) |
-			(PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH << config->src.enable_proi_high) |
-			PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP_NUM(config->des.proi_top_index) |
-			(PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP << config->des.enable_proi_top) |
-			PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH_NUM(config->des.proi_high_index) |
-			(PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH << config->des.enable_proi_high);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CORE_PRIORITY.reg, regval);
-	/* Initial the global variety */
-	for (int i = 0; i < DMA_CALLBACK_N; i++) {
-		resource->callback[i] = NULL;
-	}
-	resource->callback_enable = 0;
+    uint32_t regval = 0;
+
+    /* Static register configuration */
+    regval = PROV_DMA_CTRL_CH0_STATIC_REG0_RD_BURST_MAX_SIZE(config->src.max_burst)|
+            PROV_DMA_CTRL_CH0_STATIC_REG0_RD_TOKENS(config->src.tokens) |
+            (config->src.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG0.reg, regval);
+    /* Static register1 configuration */
+    regval = PROV_DMA_CTRL_CH0_STATIC_REG1_WR_BURST_MAX_SIZE(config->des.max_burst) |
+            PROV_DMA_CTRL_CH0_STATIC_REG1_WR_TOKENS(config->des.tokens) |
+            (config->des.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG1.reg, regval);
+    /* Static register2 configuration */
+    regval = (config->enable_joint_mode << PROV_DMA_CTRL_CH0_STATIC_REG2_JOINT_Pos) |
+            PROV_DMA_CTRL_CH0_STATIC_REG2_END_SWAP(config->swap);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG2.reg, regval);
+    /* Static register4 configuration */
+    regval = PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_NUM(config->src.periph) |
+            PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_DELAY(config->src.periph_delay) |
+            PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_NUM(config->des.periph) |
+            PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_DELAY(config->des.periph_delay);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG4.reg, regval);
+    /* Priority channels configuration */
+    regval = PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP_NUM(config->src.proi_top_index) |
+            (PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP << config->src.enable_proi_top) |
+            PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH_NUM(config->src.proi_high_index) |
+            (PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH << config->src.enable_proi_high) |
+            PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP_NUM(config->des.proi_top_index) |
+            (PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP << config->des.enable_proi_top) |
+            PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH_NUM(config->des.proi_high_index) |
+            (PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH << config->des.enable_proi_high);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CORE_PRIORITY.reg, regval);
+    /* Initial the global variety */
+    for (int i = 0; i < DMA_CALLBACK_N; i++)
+    {
+        resource->callback[i] = NULL;
+    }
+    resource->callback_enable = 0;
 }
 
 /**
@@ -296,23 +300,25 @@ static void _dma_set_config(struct dma_resource *resource,
  */
 enum status_code dma_free(struct dma_resource *resource)
 {
-	/* Check if channel is busy */
-	if (dma_get_job_status(resource) == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if channel is busy */
+    if (dma_get_job_status(resource) == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Check if DMA resource was not allocated */
-	if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
+    /* Check if DMA resource was not allocated */
+    if (!(_dma_inst.allocated_channels & (1 << resource->channel_id)))
+    {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
 
-	/* Release the DMA resource */
-	_dma_release_channel(resource->channel_id);
+    /* Release the DMA resource */
+    _dma_release_channel(resource->channel_id);
 
-	/* Reset the item in the DMA resource pool */
-	_dma_active_resource[resource->channel_id] = NULL;
+    /* Reset the item in the DMA resource pool */
+    _dma_active_resource[resource->channel_id] = NULL;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -329,40 +335,45 @@ enum status_code dma_free(struct dma_resource *resource)
  * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
  */
 enum status_code dma_add_descriptor(struct dma_resource *resource,
-		struct dma_descriptor *descriptor)
+        struct dma_descriptor *descriptor)
 {
-	struct dma_descriptor *desc = resource->descriptor;
-
-	/* Check if channel is busy */
-	if (dma_get_job_status(resource) == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Look up for an empty space for the descriptor */
-	if (desc == NULL) {
-		resource->descriptor = descriptor;
-		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG0.reg, descriptor->read_start_addr);
-		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG1.reg, descriptor->write_start_addr);
-		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG2.reg, descriptor->buffer_size);
-		set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, 3);
-	} else {
-		/* Looking for end of descriptor link */
-		while(((uint32_t)desc->cmd.next_addr) != 0) {
-			desc = (struct dma_descriptor*)((uint32_t)desc->next);
-		}
-		if (resource->descriptor->cmd.next_addr == 0x0) {
-			set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, ((uint32_t)descriptor & (~0x3)));
-		}
-		/* Set to the end of descriptor list */
-		desc->next = (uint32_t)descriptor;
-		/* The end of list should point to 0 */
-		if (descriptor->cmd.next_addr != 0) {
-			/* Enable transferred interrupt, and channel stops when buffer done */
-			descriptor->next = 0x3;
-		}
-	}
-
-	return STATUS_OK;
+    struct dma_descriptor *desc = resource->descriptor;
+
+    /* Check if channel is busy */
+    if (dma_get_job_status(resource) == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Look up for an empty space for the descriptor */
+    if (desc == NULL)
+    {
+        resource->descriptor = descriptor;
+        set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG0.reg, descriptor->read_start_addr);
+        set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG1.reg, descriptor->write_start_addr);
+        set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG2.reg, descriptor->buffer_size);
+        set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, 3);
+    } else {
+        /* Looking for end of descriptor link */
+        while(((uint32_t)desc->cmd.next_addr) != 0)
+        {
+            desc = (struct dma_descriptor*)((uint32_t)desc->next);
+        }
+        if (resource->descriptor->cmd.next_addr == 0x0)
+        {
+            set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, ((uint32_t)descriptor & (~0x3)));
+        }
+        /* Set to the end of descriptor list */
+        desc->next = (uint32_t)descriptor;
+        /* The end of list should point to 0 */
+        if (descriptor->cmd.next_addr != 0)
+        {
+            /* Enable transferred interrupt, and channel stops when buffer done */
+            descriptor->next = 0x3;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -380,33 +391,35 @@ enum status_code dma_add_descriptor(struct dma_resource *resource,
  */
 enum status_code dma_start_transfer_job(struct dma_resource *resource)
 {
-	volatile uint32_t regval;
-
-	/* Check if resource was busy */
-	if (resource->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Check if transfer size is valid */
-	if (resource->descriptor->buffer_size == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	
-	/* Clear the interrupt flag */
-	regval = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, regval);
-	/* Set the interrupt flag */
-	regval = PROV_DMA_CTRL_CH0_INT_ENABLE_REG_MASK & resource->callback_enable;
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_ENABLE_REG.reg, regval);
-	/* Set job status */
-	resource->job_status = STATUS_BUSY;
-
-	/* Enable the transfer channel */
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_ENABLE_REG.reg, 1);
-	/* Start the transfer channel */
-	set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_START_REG.reg, 1);
-
-	return STATUS_OK;
+    volatile uint32_t regval;
+
+    /* Check if resource was busy */
+    if (resource->job_status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Check if transfer size is valid */
+    if (resource->descriptor->buffer_size == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Clear the interrupt flag */
+    regval = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, regval);
+    /* Set the interrupt flag */
+    regval = PROV_DMA_CTRL_CH0_INT_ENABLE_REG_MASK & resource->callback_enable;
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_ENABLE_REG.reg, regval);
+    /* Set job status */
+    resource->job_status = STATUS_BUSY;
+
+    /* Enable the transfer channel */
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_ENABLE_REG.reg, 1);
+    /* Start the transfer channel */
+    set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_START_REG.reg, 1);
+
+    return STATUS_OK;
 }
 /**
  * \brief Get the channel index
@@ -416,15 +429,15 @@ enum status_code dma_start_transfer_job(struct dma_resource *resource)
  */
 static uint8_t get_channel_index(uint8_t channel)
 {
-	uint8_t index = 0;
-
-	channel = channel & 0x0f;
-	do {
-		channel = channel >> 1;
-		index++;
-	} while (channel);
-	
-	return (index - 1);
+    uint8_t index = 0;
+
+    channel = channel & 0x0f;
+    do {
+        channel = channel >> 1;
+        index++;
+    } while (channel);
+
+    return (index - 1);
 }
 
 /**
@@ -433,80 +446,90 @@ static uint8_t get_channel_index(uint8_t channel)
  */
 static void dma_isr_handler( void )
 {
-	uint8_t active_channel;
-	static uint8_t channel_index; //
-	struct dma_resource *resource;
-	uint8_t isr;
-	uint8_t isr_flag = 0;
-
-	/* Get active channel */
-	active_channel =  PROV_DMA_CTRL0->CORE_INT_STATUS.reg & 
-			PROV_DMA_CTRL_CORE_INT_STATUS_CHANNEL__Msk;
-				
-	do {
-		channel_index = get_channel_index(active_channel);
-		/* Get active DMA resource based on channel */
-		resource = _dma_active_resource[channel_index];
-		isr = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
-		/* Calculate block transfer size of the DMA transfer */
-		resource->transfered_size = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_COUNT_REG.reg);
-
-		/* DMA channel interrupt handler */
-		if (isr & (1 << DMA_CALLBACK_TRANSFER_DONE)) {
-			/* Transfer complete flag */
-			isr_flag = DMA_CALLBACK_TRANSFER_DONE;
-			/* Set job status */
-			resource->job_status = STATUS_OK;
-		} else if (isr & (1 << DMA_CALLBACK_READ_ERR)) {
-			/* Read error flag */
-			isr_flag = DMA_CALLBACK_READ_ERR;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_WRITE_ERR)) {
-			/* Write error flag */
-			isr_flag = DMA_CALLBACK_WRITE_ERR;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_FIFO_OVERFLOW)) {
-			/* Overflow flag */
-			isr_flag = DMA_CALLBACK_FIFO_OVERFLOW;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_FIFO_UNDERFLOW)) {
-			/* Underflow flag */
-			isr_flag = DMA_CALLBACK_FIFO_UNDERFLOW;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_READ_TIMEOUT)) {
-			/* Read timeout flag */
-			isr_flag = DMA_CALLBACK_READ_TIMEOUT;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_WRITE_TIMEOUT)) {
-			/* Write timeout flag */
-			isr_flag = DMA_CALLBACK_WRITE_TIMEOUT;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		} else if (isr & (1 << DMA_CALLBACK_WDT_TRIGGER)) {
-			/* Watchdog error flag */
-			isr_flag = DMA_CALLBACK_WDT_TRIGGER;
-			/* Set I/O ERROR status */
-			resource->job_status = STATUS_ERR_IO;
-		}
-		
-		if (isr) {
-			/* Clear the watch dog error flag */
-			set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1<<isr_flag);
-			/* Execute the callback function */
-			if ((resource->callback_enable & (1<<isr_flag)) &&
-					(resource->callback[isr_flag])) {
-				resource->callback[isr_flag](resource);
-			}
-		}
-		isr &= ~(1<<isr_flag);
-	} while (isr);
-
-	NVIC_ClearPendingIRQ(PROV_DMA_CTRL0_IRQn);
+    uint8_t active_channel;
+    static uint8_t channel_index; */
+    struct dma_resource *resource;
+    uint8_t isr;
+    uint8_t isr_flag = 0;
+
+    /* Get active channel */
+    active_channel =  PROV_DMA_CTRL0->CORE_INT_STATUS.reg &
+            PROV_DMA_CTRL_CORE_INT_STATUS_CHANNEL__Msk;
+
+    do {
+        channel_index = get_channel_index(active_channel);
+        /* Get active DMA resource based on channel */
+        resource = _dma_active_resource[channel_index];
+        isr = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg);
+        /* Calculate block transfer size of the DMA transfer */
+        resource->transfered_size = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_COUNT_REG.reg);
+
+        /* DMA channel interrupt handler */
+        if (isr & (1 << DMA_CALLBACK_TRANSFER_DONE))
+        {
+            /* Transfer complete flag */
+            isr_flag = DMA_CALLBACK_TRANSFER_DONE;
+            /* Set job status */
+            resource->job_status = STATUS_OK;
+        } else if (isr & (1 << DMA_CALLBACK_READ_ERR))
+        {
+            /* Read error flag */
+            isr_flag = DMA_CALLBACK_READ_ERR;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_WRITE_ERR))
+        {
+            /* Write error flag */
+            isr_flag = DMA_CALLBACK_WRITE_ERR;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_FIFO_OVERFLOW))
+        {
+            /* Overflow flag */
+            isr_flag = DMA_CALLBACK_FIFO_OVERFLOW;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_FIFO_UNDERFLOW))
+        {
+            /* Underflow flag */
+            isr_flag = DMA_CALLBACK_FIFO_UNDERFLOW;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_READ_TIMEOUT))
+        {
+            /* Read timeout flag */
+            isr_flag = DMA_CALLBACK_READ_TIMEOUT;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_WRITE_TIMEOUT))
+        {
+            /* Write timeout flag */
+            isr_flag = DMA_CALLBACK_WRITE_TIMEOUT;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        } else if (isr & (1 << DMA_CALLBACK_WDT_TRIGGER))
+        {
+            /* Watchdog error flag */
+            isr_flag = DMA_CALLBACK_WDT_TRIGGER;
+            /* Set I/O ERROR status */
+            resource->job_status = STATUS_ERR_IO;
+        }
+
+        if (isr)
+        {
+            /* Clear the watch dog error flag */
+            set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1<<isr_flag);
+            /* Execute the callback function */
+            if ((resource->callback_enable & (1<<isr_flag)) &&
+                    (resource->callback[isr_flag]))
+                    {
+                resource->callback[isr_flag](resource);
+            }
+        }
+        isr &= ~(1<<isr_flag);
+    } while (isr);
+
+    NVIC_ClearPendingIRQ(PROV_DMA_CTRL0_IRQn);
 }
 
 /**
@@ -523,35 +546,37 @@ static void dma_isr_handler( void )
  * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
  */
 enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config)
+        struct dma_resource_config *config)
 {
-	uint8_t new_channel;
-
-	if (!_dma_inst._dma_init) {
-		/* Perform a reset before enable DMA controller */
-		system_peripheral_reset(PERIPHERAL_DMA);
-		/* Select Mux 15 as PROV_DMA_CTRL0 interrupt source */
-		LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_3.bit.MUX_15 = LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_3_MUX_15_16_Val;
-		system_register_isr(31, (uint32_t)dma_isr_handler);
-		
-		_dma_inst._dma_init = true;
-	}
-
-	new_channel = _dma_find_first_free_channel_and_allocate();
-	/* If no channel available, return not found */
-	if (new_channel == DMA_INVALID_CHANNEL) {
-		return STATUS_ERR_NOT_FOUND;
-	}
-	
-	/* Set the channel */
-	resource->channel_id = new_channel;
-	/* Configure the DMA control,channel registers and descriptors here */
-	_dma_set_config(resource, config);
-	
-	resource->descriptor = NULL;
-
-	/* Log the DMA resource into the internal DMA resource pool */
-	_dma_active_resource[resource->channel_id] = resource;
-
-	return STATUS_OK;
-}
\ No newline at end of file
+    uint8_t new_channel;
+
+    if (!_dma_inst._dma_init)
+    {
+        /* Perform a reset before enable DMA controller */
+        system_peripheral_reset(PERIPHERAL_DMA);
+        /* Select Mux 15 as PROV_DMA_CTRL0 interrupt source */
+        LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_3.bit.MUX_15 = LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_3_MUX_15_16_Val;
+        system_register_isr(31, (uint32_t)dma_isr_handler);
+
+        _dma_inst._dma_init = true;
+    }
+
+    new_channel = _dma_find_first_free_channel_and_allocate();
+    /* If no channel available, return not found */
+    if (new_channel == DMA_INVALID_CHANNEL)
+    {
+        return STATUS_ERR_NOT_FOUND;
+    }
+
+    /* Set the channel */
+    resource->channel_id = new_channel;
+    /* Configure the DMA control,channel registers and descriptors here */
+    _dma_set_config(resource, config);
+
+    resource->descriptor = NULL;
+
+    /* Log the DMA resource into the internal DMA resource pool */
+    _dma_active_resource[resource->channel_id] = resource;
+
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h
index ae3ecede8550..8b16f56566f0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dma/dma_sam_b.h
@@ -103,8 +103,8 @@ extern "C" {
  *      <td>4</td>
  *    </tr>
  * </table>
- * The DMA channel operation can be suspended at any time by software, 
- * or after selectable descriptor execution. The DMAC driver for SAM 
+ * The DMA channel operation can be suspended at any time by software,
+ * or after selectable descriptor execution. The DMAC driver for SAM
  * supports four types of transfers such as peripheral to peripheral,
  * peripheral to memory, memory to peripheral, and memory to memory.
  *
@@ -264,75 +264,75 @@ extern "C" {
 #include "conf_dma.h"
 
 /** DMA IRQn number. */
-#define PROV_DMA_CTRL0_IRQn		15
+#define PROV_DMA_CTRL0_IRQn     15
 
 /** DMA invalid channel number. */
 #define DMA_INVALID_CHANNEL        0xff
 
 /** DMA peripheral index */
 enum dma_peripheral_index {
-	MEMORY_DMA_PERIPHERAL = 0,
-	UART0RX_DMA_PERIPHERAL,
-	UART0TX_DMA_PERIPHERAL,
-	UART1RX_DMA_PERIPHERAL,
-	UART1TX_DMA_PERIPHERAL,
-	SPI0RX_DMA_PERIPHERAL,
-	SPI0TX_DMA_PERIPHERAL,
-	SPI1RX_DMA_PERIPHERAL,
-	SPI1TX_DMA_PERIPHERAL,
-	I2C0RX_DMA_PERIPHERAL,
-	I2C0TX_DMA_PERIPHERAL,
-	I2C1RX_DMA_PERIPHERAL,
-	I2C1TX_DMA_PERIPHERAL,
-	DUALTIMER0_DMA_PERIPHERAL = 15,
-	TIMER0_DMA_PERIPHERAL,
+    MEMORY_DMA_PERIPHERAL = 0,
+    UART0RX_DMA_PERIPHERAL,
+    UART0TX_DMA_PERIPHERAL,
+    UART1RX_DMA_PERIPHERAL,
+    UART1TX_DMA_PERIPHERAL,
+    SPI0RX_DMA_PERIPHERAL,
+    SPI0TX_DMA_PERIPHERAL,
+    SPI1RX_DMA_PERIPHERAL,
+    SPI1TX_DMA_PERIPHERAL,
+    I2C0RX_DMA_PERIPHERAL,
+    I2C0TX_DMA_PERIPHERAL,
+    I2C1RX_DMA_PERIPHERAL,
+    I2C1TX_DMA_PERIPHERAL,
+    DUALTIMER0_DMA_PERIPHERAL = 15,
+    TIMER0_DMA_PERIPHERAL,
 };
 
 /** DMA channel index */
 enum dma_ch_index {
-	/** DMA channel 0 */
-	DMA_CHANNEL_0 = 0,
-	/** DMA channel 1 */
-	DMA_CHANNEL_1,
-	/** DMA channel 2 */
-	DMA_CHANNEL_2,
-	/** DMA channel 3 */
-	DMA_CHANNEL_3,
+    /** DMA channel 0 */
+    DMA_CHANNEL_0 = 0,
+    /** DMA channel 1 */
+    DMA_CHANNEL_1,
+    /** DMA channel 2 */
+    DMA_CHANNEL_2,
+    /** DMA channel 3 */
+    DMA_CHANNEL_3,
 };
 
 enum dma_endian_swap {
-	/** DMA endian no swap */
-	DMA_ENDIAN_NO_SWAP,
-	/** DMA endian 16-bit */
-	DMA_ENDIAN_SIZE_16,
-	/** DMA endian 32-bit */
-	DMA_ENDIAN_SIZE_32,
-	/** DMA endian 64-bit */
-	DMA_ENDIAN_SIZE_64,
+    /** DMA endian no swap */
+    DMA_ENDIAN_NO_SWAP,
+    /** DMA endian 16-bit */
+    DMA_ENDIAN_SIZE_16,
+    /** DMA endian 32-bit */
+    DMA_ENDIAN_SIZE_32,
+    /** DMA endian 64-bit */
+    DMA_ENDIAN_SIZE_64,
 };
 
 /**
  * Callback types for DMA callback driver.
  */
 enum dma_callback_type {
-	/** Callback for transfer complete */
-	DMA_CALLBACK_TRANSFER_DONE,
-	/** AHB read slave error */
-	DMA_CALLBACK_READ_ERR,
-	/**  AHB write slave error */
-	DMA_CALLBACK_WRITE_ERR,
-	/** FIFO has been overflown */
-	DMA_CALLBACK_FIFO_OVERFLOW,
-	/** FIFO has been underflows */
-	DMA_CALLBACK_FIFO_UNDERFLOW,
-	/** Read timeout on AHB bus (timeout value fixed at 1024 cycles) */
-	DMA_CALLBACK_READ_TIMEOUT,
-	/** Write timeout on AHB bus (timeout value fixed at 1024 cycles) */
-	DMA_CALLBACK_WRITE_TIMEOUT,
-	/** Channel active but did not start a burst for 2048 cycles */
-	DMA_CALLBACK_WDT_TRIGGER,
-	/** Number of available callbacks */
-	DMA_CALLBACK_N,
+    /** Callback for transfer complete */
+    DMA_CALLBACK_TRANSFER_DONE,
+    /** AHB read slave error */
+    DMA_CALLBACK_READ_ERR,
+    /**  AHB write slave error */
+    DMA_CALLBACK_WRITE_ERR,
+    /** FIFO has been overflown */
+    DMA_CALLBACK_FIFO_OVERFLOW,
+    /** FIFO has been underflows */
+    DMA_CALLBACK_FIFO_UNDERFLOW,
+    /** Read timeout on AHB bus (timeout value fixed at 1024 cycles) */
+    DMA_CALLBACK_READ_TIMEOUT,
+    /** Write timeout on AHB bus (timeout value fixed at 1024 cycles) */
+    DMA_CALLBACK_WRITE_TIMEOUT,
+    /** Channel active but did not start a burst for 2048 cycles */
+    DMA_CALLBACK_WDT_TRIGGER,
+    /** Number of available callbacks */
+    DMA_CALLBACK_N,
 };
 
 /**
@@ -341,57 +341,57 @@ enum dma_callback_type {
  * must correspond to the end of the transfer.
  */
 struct dma_descriptor {
-	/** Start address of read buffer */
-	uint32_t read_start_addr;
-	/** Start address of write buffer */
-	uint32_t write_start_addr;
-	/** Size (in bytes) of buffer to transfer */
-	uint32_t buffer_size;
-	union {
-		struct {
-			/** Active high interrupt enable once buffer has been transferred */
-			uint32_t set_interrupt:1;
-			/** If set, channel stops when buffer done, otherwise load from cmd_next_addr */
-			uint32_t last:1;
-			/** Address of next command if cmd_last is not set */
-			uint32_t next_addr:30;
-		} cmd;
-		uint32_t next;
-	};
+    /** Start address of read buffer */
+    uint32_t read_start_addr;
+    /** Start address of write buffer */
+    uint32_t write_start_addr;
+    /** Size (in bytes) of buffer to transfer */
+    uint32_t buffer_size;
+    union {
+        struct {
+            /** Active high interrupt enable once buffer has been transferred */
+            uint32_t set_interrupt:1;
+            /** If set, channel stops when buffer done, otherwise load from cmd_next_addr */
+            uint32_t last:1;
+            /** Address of next command if cmd_last is not set */
+            uint32_t next_addr:30;
+        } cmd;
+        uint32_t next;
+    };
 };
 /** Structure for DMA source/description */
 struct dma_config {
-	/** Maximum number of bytes of an AHB read/write burst */
-	uint8_t max_burst;
-	/** Number of AHB read/write commands to issue before channel is released */
-	uint8_t tokens;
-	/** If true, the controller will increment the next burst address */
-	bool enable_inc_addr;
-	/** Index of peripheral to read/write from (0 if memory or no peripheral flow control) */
-	enum dma_peripheral_index periph;
-	/** 
-	 * Number of cycles to wait for read/write request signal to update 
-	 * after issuing the read/write clear signal
-	 */
-	uint8_t periph_delay;
-	/** Top priority enable */
-	bool enable_proi_top;
-	/** Top priority channel index */
-	uint8_t proi_top_index;
-	/** High priority enable */
-	bool enable_proi_high;
-	/** High priority channel index */
-	uint8_t proi_high_index;
+    /** Maximum number of bytes of an AHB read/write burst */
+    uint8_t max_burst;
+    /** Number of AHB read/write commands to issue before channel is released */
+    uint8_t tokens;
+    /** If true, the controller will increment the next burst address */
+    bool enable_inc_addr;
+    /** Index of peripheral to read/write from (0 if memory or no peripheral flow control) */
+    enum dma_peripheral_index periph;
+    /**
+     * Number of cycles to wait for read/write request signal to update
+     * after issuing the read/write clear signal
+     */
+    uint8_t periph_delay;
+    /** Top priority enable */
+    bool enable_proi_top;
+    /** Top priority channel index */
+    uint8_t proi_top_index;
+    /** High priority enable */
+    bool enable_proi_high;
+    /** High priority channel index */
+    uint8_t proi_high_index;
 };
 
 /** Structure for DMA transfer resource */
 struct dma_resource_config {
-	struct dma_config src;
-	struct dma_config des;
-	/** If true, channel will work in joint mode */
-	bool enable_joint_mode;
-	/** Endian Byte Swapping */
-	enum dma_endian_swap swap;
+    struct dma_config src;
+    struct dma_config des;
+    /** If true, channel will work in joint mode */
+    bool enable_joint_mode;
+    /** Endian Byte Swapping */
+    enum dma_endian_swap swap;
 };
 
 /** Forward definition of the DMA resource */
@@ -401,18 +401,18 @@ typedef void (*dma_callback_t)(struct dma_resource *const resource);
 
 /** Structure for DMA transfer resource */
 struct dma_resource {
-	/** Allocated DMA channel ID */
-	uint8_t channel_id;
-	/** Array of callback functions for DMA transfer job */
-	dma_callback_t callback[DMA_CALLBACK_N];
-	/** Bit mask for enabled callbacks */
-	uint8_t callback_enable;
-	/** Status of the last job */
-	volatile enum status_code job_status;
-	/** Transferred data size */
-	uint32_t transfered_size;
-	/** DMA transfer descriptor */
-	struct dma_descriptor* descriptor;
+    /** Allocated DMA channel ID */
+    uint8_t channel_id;
+    /** Array of callback functions for DMA transfer job */
+    dma_callback_t callback[DMA_CALLBACK_N];
+    /** Bit mask for enabled callbacks */
+    uint8_t callback_enable;
+    /** Status of the last job */
+    volatile enum status_code job_status;
+    /** Transferred data size */
+    uint32_t transfered_size;
+    /** DMA transfer descriptor */
+    struct dma_descriptor* descriptor;
 };
 
 /**
@@ -424,7 +424,7 @@ struct dma_resource {
  */
 static inline enum status_code dma_get_job_status(struct dma_resource *resource)
 {
-	return resource->job_status;
+    return resource->job_status;
 }
 
 /**
@@ -435,9 +435,9 @@ static inline enum status_code dma_get_job_status(struct dma_resource *resource)
  *
  */
 static inline void dma_enable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	resource->callback_enable |= 1 << type;
+    resource->callback_enable |= 1 << type;
 }
 
 /**
@@ -448,9 +448,9 @@ static inline void dma_enable_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_disable_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	resource->callback_enable &= ~(1 << type);
+    resource->callback_enable &= ~(1 << type);
 }
 
 /**
@@ -467,9 +467,9 @@ static inline void dma_disable_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_register_callback(struct dma_resource *resource,
-		dma_callback_t callback, enum dma_callback_type type)
+        dma_callback_t callback, enum dma_callback_type type)
 {
-	resource->callback[type] = callback;
+    resource->callback[type] = callback;
 }
 
 /**
@@ -488,9 +488,9 @@ static inline void dma_register_callback(struct dma_resource *resource,
  *
  */
 static inline void dma_unregister_callback(struct dma_resource *resource,
-		enum dma_callback_type type)
+        enum dma_callback_type type)
 {
-	resource->callback[type] = NULL;
+    resource->callback[type] = NULL;
 }
 
 /**
@@ -514,18 +514,18 @@ static inline void dma_unregister_callback(struct dma_resource *resource,
  */
 static inline void dma_descriptor_get_config_defaults(struct dma_descriptor *config)
 {
-	/* Default read buffer size is set to 0 */
-	config->read_start_addr = 0;
-	/* Default write buffer size is set to 0 */
-	config->write_start_addr = 0;
-	/* Set beat size to one byte */
-	config->buffer_size = 1;
-	/* Enable transferred interrupt */
-	config->cmd.set_interrupt = 1;
-	/* Channel stops when buffer done */
-	config->cmd.last = 1;
-	/* Set next command to 0 */
-	config->cmd.next_addr = 0;
+    /* Default read buffer size is set to 0 */
+    config->read_start_addr = 0;
+    /* Default write buffer size is set to 0 */
+    config->write_start_addr = 0;
+    /* Set beat size to one byte */
+    config->buffer_size = 1;
+    /* Enable transferred interrupt */
+    config->cmd.set_interrupt = 1;
+    /* Channel stops when buffer done */
+    config->cmd.last = 1;
+    /* Set next command to 0 */
+    config->cmd.next_addr = 0;
 }
 
 /**
@@ -535,9 +535,9 @@ static inline void dma_descriptor_get_config_defaults(struct dma_descriptor *con
  *
  */
 static inline void dma_update_descriptor(struct dma_resource *resource,
-		struct dma_descriptor* descriptor)
+        struct dma_descriptor* descriptor)
 {
-	resource->descriptor = descriptor;
+    resource->descriptor = descriptor;
 }
 
 /**
@@ -548,14 +548,14 @@ static inline void dma_update_descriptor(struct dma_resource *resource,
  */
 static inline void dma_reset_descriptor(struct dma_resource *resource)
 {
-	resource->descriptor = NULL;
+    resource->descriptor = NULL;
 }
 
 void dma_get_config_defaults(struct dma_resource_config *config);
 enum status_code dma_allocate(struct dma_resource *resource,
-		struct dma_resource_config *config);
+        struct dma_resource_config *config);
 enum status_code dma_add_descriptor(struct dma_resource *resource,
-		struct dma_descriptor* descriptor);
+        struct dma_descriptor* descriptor);
 enum status_code dma_start_transfer_job(struct dma_resource *resource);
 enum status_code dma_free(struct dma_resource *resource);
 uint8_t dma_get_status(uint8_t channel);
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c
index 6c37d26cd72a..361d51c92638 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.c
@@ -67,36 +67,39 @@
  *
  * \retval STATUS_OK      If CRC32 calculation OK
  * \retval STATUS_ERR_BAD_ADDRESS  The address was not aligned with 4 bytes.
- 
+
  * \retval STATUS_ERR_IO  A bus error is detected
  */
 enum status_code dsu_crc32_cal(const uint32_t addr, const uint32_t len, uint32_t *pcrc32)
 {
-	if (addr & 0x00000003) {
-		return STATUS_ERR_BAD_ADDRESS;
-	}
+    if (addr & 0x00000003)
+    {
+        return STATUS_ERR_BAD_ADDRESS;
+    }
 
-	system_interrupt_disable_global();
-	system_peripheral_unlock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+    system_interrupt_disable_global();
+    system_peripheral_unlock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
 
-	DSU->DATA.reg = *pcrc32;
-	DSU->ADDR.reg = addr;
-	DSU->LENGTH.reg = len;
+    DSU->DATA.reg = *pcrc32;
+    DSU->ADDR.reg = addr;
+    DSU->LENGTH.reg = len;
 
-	DSU->CTRL.bit.CRC = 1;
-	while ((DSU->STATUSA.reg & DSU_STATUSA_DONE) != 1) {	
-	}
+    DSU->CTRL.bit.CRC = 1;
+    while ((DSU->STATUSA.reg & DSU_STATUSA_DONE) != 1)
+    {
+    }
 
-	if (DSU->STATUSA.reg & DSU_STATUSA_BERR) {
-		system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
-		system_interrupt_enable_global();
-		return STATUS_ERR_IO;
-	}
+    if (DSU->STATUSA.reg & DSU_STATUSA_BERR)
+    {
+        system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+        system_interrupt_enable_global();
+        return STATUS_ERR_IO;
+    }
 
-	*pcrc32 = DSU->DATA.reg;
-	DSU->STATUSA.reg = DSU_STATUSA_DONE;
+    *pcrc32 = DSU->DATA.reg;
+    DSU->STATUSA.reg = DSU_STATUSA_DONE;
 
-	system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
-	system_interrupt_enable_global();
-	return STATUS_OK;
-}
\ No newline at end of file
+    system_peripheral_lock(SYSTEM_PERIPHERAL_ID(DSU), ~SYSTEM_PERIPHERAL_ID(DSU));
+    system_interrupt_enable_global();
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h
index 5f4625052e84..78d9b11ad00b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dsu/crc32/crc32.h
@@ -117,11 +117,11 @@ extern "C" {
 static inline void dsu_crc32_init(void)
 {
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-		/* Turn on the digital interface clock */
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_DSU);
+        /* Turn on the digital interface clock */
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_DSU);
 #else
-		/* Turn on the digital interface clock */
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_DSU);
+        /* Turn on the digital interface clock */
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_DSU);
 #endif
 
 }
@@ -174,12 +174,12 @@ enum status_code dsu_crc32_cal(const uint32_t addr, const uint32_t len, uint32_t
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -197,15 +197,15 @@ enum status_code dsu_crc32_cal(const uint32_t addr, const uint32_t len, uint32_t
  * \page asfdoc_sam0_drivers_crc32_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
+ *  <tr>
  *      <th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>06/2016</td>
- *		<td>Initial release</td>
- *	</tr>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>06/2016</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  *
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c
index 9e235d6542a6..1c12b9131b9c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.c
@@ -59,25 +59,25 @@ static dualtimer_callback_t dualtimer_callback_timer2 = NULL;
  */
 void dualtimer_get_config_defaults(struct dualtimer_config *config)
 {
-	config->timer1.timer_enable = true;
-	config->timer2.timer_enable = true;
+    config->timer1.timer_enable = true;
+    config->timer2.timer_enable = true;
 
-	config->timer1.counter_mode = DUALTIMER_PERIODIC_MODE;
-	config->timer2.counter_mode = DUALTIMER_PERIODIC_MODE;
+    config->timer1.counter_mode = DUALTIMER_PERIODIC_MODE;
+    config->timer2.counter_mode = DUALTIMER_PERIODIC_MODE;
 
-	config->timer1.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
-	config->timer2.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
+    config->timer1.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
+    config->timer2.counter_size = DUALTIMER_COUNTER_SIZE_32BIT;
 
-	config->timer1.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
-	config->timer2.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
+    config->timer1.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
+    config->timer2.clock_prescaler = DUALTIMER_CLOCK_PRESCALER_DIV1;
 
-	config->timer1.interrup_enable = true;
-	config->timer2.interrup_enable = true;
+    config->timer1.interrup_enable = true;
+    config->timer2.interrup_enable = true;
 
-	config->timer1.load_value = 0;
-	config->timer2.load_value = 0;
+    config->timer1.load_value = 0;
+    config->timer2.load_value = 0;
 
-	config->clock_source = DUALTIMER_CLK_INPUT_0;
+    config->clock_source = DUALTIMER_CLK_INPUT_0;
 }
 
 
@@ -90,11 +90,12 @@ void dualtimer_get_config_defaults(struct dualtimer_config *config)
  */
 uint32_t dualtimer_get_value(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		return DUALTIMER0->TIMER1VALUE.reg;
-	} else {
-		return DUALTIMER0->TIMER2VALUE.reg;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        return DUALTIMER0->TIMER1VALUE.reg;
+    } else {
+        return DUALTIMER0->TIMER2VALUE.reg;
+    }
 }
 
 /**
@@ -105,21 +106,24 @@ uint32_t dualtimer_get_value(enum dualtimer_timer timer)
  * \param[in]     value        Load value
  */
 void dualtimer_set_counter(enum dualtimer_timer timer,
-		enum dualtimer_set_register cur_bg, uint32_t value)
+        enum dualtimer_set_register cur_bg, uint32_t value)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		if (cur_bg == DUALTIMER_SET_CURRUNT_REG) {
-			DUALTIMER0->TIMER1LOAD.reg = value;
-		} else {
-			DUALTIMER0->TIMER1BGLOAD.reg = value;
-		}
-	} else {
-		if (cur_bg == DUALTIMER_SET_CURRUNT_REG) {
-			DUALTIMER0->TIMER2LOAD.reg = value;
-			} else {
-			DUALTIMER0->TIMER2BGLOAD.reg = value;
-		}
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        if (cur_bg == DUALTIMER_SET_CURRUNT_REG)
+        {
+            DUALTIMER0->TIMER1LOAD.reg = value;
+        } else {
+            DUALTIMER0->TIMER1BGLOAD.reg = value;
+        }
+    } else {
+        if (cur_bg == DUALTIMER_SET_CURRUNT_REG)
+        {
+            DUALTIMER0->TIMER2LOAD.reg = value;
+            } else {
+            DUALTIMER0->TIMER2BGLOAD.reg = value;
+        }
+    }
 }
 
 /**
@@ -131,11 +135,12 @@ void dualtimer_set_counter(enum dualtimer_timer timer,
  */
 uint8_t dualtimer_get_status(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		return DUALTIMER0->TIMER1RIS.reg;
-	} else {
-		return DUALTIMER0->TIMER2RIS.reg;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        return DUALTIMER0->TIMER1RIS.reg;
+    } else {
+        return DUALTIMER0->TIMER2RIS.reg;
+    }
 }
 
 /**
@@ -147,11 +152,12 @@ uint8_t dualtimer_get_status(enum dualtimer_timer timer)
  */
 uint8_t dualtimer_get_interrupt_status(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		return DUALTIMER0->TIMER1MIS.reg;
-	} else {
-		return DUALTIMER0->TIMER2MIS.reg;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        return DUALTIMER0->TIMER1MIS.reg;
+    } else {
+        return DUALTIMER0->TIMER2MIS.reg;
+    }
 }
 
 /**
@@ -163,11 +169,12 @@ uint8_t dualtimer_get_interrupt_status(enum dualtimer_timer timer)
  */
 void dualtimer_clear_interrupt_status(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		DUALTIMER0->TIMER1INTCLR.reg = 1;
-	} else {
-		DUALTIMER0->TIMER2INTCLR.reg = 1;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        DUALTIMER0->TIMER1INTCLR.reg = 1;
+    } else {
+        DUALTIMER0->TIMER2INTCLR.reg = 1;
+    }
 }
 
 /**
@@ -179,11 +186,12 @@ void dualtimer_clear_interrupt_status(enum dualtimer_timer timer)
  */
 void dualtimer_enable(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		DUALTIMER0->TIMER1CONTROL.reg |= DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
-	} else {
-		DUALTIMER0->TIMER2CONTROL.reg |= DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        DUALTIMER0->TIMER1CONTROL.reg |= DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
+    } else {
+        DUALTIMER0->TIMER2CONTROL.reg |= DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
+    }
 }
 
 /**
@@ -195,11 +203,12 @@ void dualtimer_enable(enum dualtimer_timer timer)
  */
 void dualtimer_disable(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		DUALTIMER0->TIMER1CONTROL.reg &= ~DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
-	} else {
-		DUALTIMER0->TIMER2CONTROL.reg &= ~DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        DUALTIMER0->TIMER1CONTROL.reg &= ~DUALTIMER_TIMER1CONTROL_TIMER_ENABLE;
+    } else {
+        DUALTIMER0->TIMER2CONTROL.reg &= ~DUALTIMER_TIMER2CONTROL_TIMER_ENABLE;
+    }
 }
 
 /**
@@ -210,16 +219,18 @@ void dualtimer_disable(enum dualtimer_timer timer)
  */
 static void dualtimer_isr_handler(void)
 {
-	if (dualtimer_get_interrupt_status(DUALTIMER_TIMER1)) {
-		dualtimer_clear_interrupt_status(DUALTIMER_TIMER1);
-		if (dualtimer_callback_timer1)
-			dualtimer_callback_timer1();
-	}
-	if (dualtimer_get_interrupt_status(DUALTIMER_TIMER2)) {
-		dualtimer_clear_interrupt_status(DUALTIMER_TIMER2);
-		if (dualtimer_callback_timer2)
-			dualtimer_callback_timer2();
-	}
+    if (dualtimer_get_interrupt_status(DUALTIMER_TIMER1))
+    {
+        dualtimer_clear_interrupt_status(DUALTIMER_TIMER1);
+        if (dualtimer_callback_timer1)
+            dualtimer_callback_timer1();
+    }
+    if (dualtimer_get_interrupt_status(DUALTIMER_TIMER2))
+    {
+        dualtimer_clear_interrupt_status(DUALTIMER_TIMER2);
+        if (dualtimer_callback_timer2)
+            dualtimer_callback_timer2();
+    }
 }
 
 /**
@@ -234,61 +245,72 @@ static void dualtimer_isr_handler(void)
  */
 void dualtimer_init(const struct dualtimer_config *config)
 {
-	uint8_t regval = 0;
+    uint8_t regval = 0;
 
-	/* Global reset */
-	system_peripheral_reset(PERIPHERAL_DUALT_TIMER);
+    /* Global reset */
+    system_peripheral_reset(PERIPHERAL_DUALT_TIMER);
 
-	/* Common config */
-	if (config->timer1.timer_enable || config->timer2.timer_enable) {
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
-		LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
-		LPMCU_MISC_REGS0->LPMCU_CTRL.bit.DUALTIMER0_CLK_SEL = config->clock_source;
-	}
-	
-	/* Timer1 config */
-	if (config->timer1.timer_enable) {
-		if (config->timer1.counter_mode == DUALTIMER_ONE_SHOT_MODE) {
-			regval = DUALTIMER_TIMER1CONTROL_ONE_SHOT_COUNT_1;
-		} else if (config->timer1.counter_mode == DUALTIMER_FREE_RUNNING_MODE) {
-			regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_0;
-		} else if (config->timer1.counter_mode == DUALTIMER_PERIODIC_MODE) {
-			regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_1;
-		}
-		regval |= (DUALTIMER_TIMER1CONTROL_TIMER_SIZE &
-				((config->timer1.counter_size) << DUALTIMER_TIMER1CONTROL_TIMER_SIZE_Pos)) |
-				DUALTIMER_TIMER1CONTROL_TIMERPRE(config->timer1.clock_prescaler);
-		if (config->timer1.interrup_enable) {
-			regval |= DUALTIMER_TIMER1CONTROL_INTERRUPT_ENABLE;
-		}
-		DUALTIMER0->TIMER1LOAD.reg = config->timer1.load_value;
-		DUALTIMER0->TIMER1CONTROL.reg = regval;
-		LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_1_ENABLE;
-		dualtimer_enable(DUALTIMER_TIMER1);
-	}
+    /* Common config */
+    if (config->timer1.timer_enable || config->timer2.timer_enable)
+    {
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+        LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+        LPMCU_MISC_REGS0->LPMCU_CTRL.bit.DUALTIMER0_CLK_SEL = config->clock_source;
+    }
 
-	/* Timer2 config */
-	if (config->timer2.timer_enable) {
-		if (config->timer2.counter_mode == DUALTIMER_ONE_SHOT_MODE) {
-			regval = DUALTIMER_TIMER2CONTROL_ONE_SHOT_COUNT_1;
-		} else if (config->timer2.counter_mode == DUALTIMER_FREE_RUNNING_MODE) {
-			regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_0;
-		} else if (config->timer2.counter_mode == DUALTIMER_PERIODIC_MODE) {
-			regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_1;
-		}
-		regval |= (DUALTIMER_TIMER2CONTROL_TIMER_SIZE &
-				((config->timer2.counter_size) << DUALTIMER_TIMER2CONTROL_TIMER_SIZE_Pos)) |
-				DUALTIMER_TIMER2CONTROL_TIMERPRE(config->timer2.clock_prescaler);
-		if (config->timer2.interrup_enable) {
-			regval |= DUALTIMER_TIMER2CONTROL_INTERRUPT_ENABLE;
-		}
-		DUALTIMER0->TIMER2LOAD.reg = config->timer2.load_value;
-		DUALTIMER0->TIMER2CONTROL.reg = regval;
-		LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_2_ENABLE;
-		dualtimer_enable(DUALTIMER_TIMER2);
-	}
+    /* Timer1 config */
+    if (config->timer1.timer_enable)
+    {
+        if (config->timer1.counter_mode == DUALTIMER_ONE_SHOT_MODE)
+        {
+            regval = DUALTIMER_TIMER1CONTROL_ONE_SHOT_COUNT_1;
+        } else if (config->timer1.counter_mode == DUALTIMER_FREE_RUNNING_MODE)
+        {
+            regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_0;
+        } else if (config->timer1.counter_mode == DUALTIMER_PERIODIC_MODE)
+        {
+            regval = DUALTIMER_TIMER1CONTROL_TIMER_MODE_1;
+        }
+        regval |= (DUALTIMER_TIMER1CONTROL_TIMER_SIZE &
+                ((config->timer1.counter_size) << DUALTIMER_TIMER1CONTROL_TIMER_SIZE_Pos)) |
+                DUALTIMER_TIMER1CONTROL_TIMERPRE(config->timer1.clock_prescaler);
+        if (config->timer1.interrup_enable)
+        {
+            regval |= DUALTIMER_TIMER1CONTROL_INTERRUPT_ENABLE;
+        }
+        DUALTIMER0->TIMER1LOAD.reg = config->timer1.load_value;
+        DUALTIMER0->TIMER1CONTROL.reg = regval;
+        LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_1_ENABLE;
+        dualtimer_enable(DUALTIMER_TIMER1);
+    }
 
-	system_register_isr(RAM_ISR_TABLE_DUALTIMER_INDEX, (uint32_t)dualtimer_isr_handler);
+    /* Timer2 config */
+    if (config->timer2.timer_enable)
+    {
+        if (config->timer2.counter_mode == DUALTIMER_ONE_SHOT_MODE)
+        {
+            regval = DUALTIMER_TIMER2CONTROL_ONE_SHOT_COUNT_1;
+        } else if (config->timer2.counter_mode == DUALTIMER_FREE_RUNNING_MODE)
+        {
+            regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_0;
+        } else if (config->timer2.counter_mode == DUALTIMER_PERIODIC_MODE)
+        {
+            regval = DUALTIMER_TIMER2CONTROL_TIMER_MODE_1;
+        }
+        regval |= (DUALTIMER_TIMER2CONTROL_TIMER_SIZE &
+                ((config->timer2.counter_size) << DUALTIMER_TIMER2CONTROL_TIMER_SIZE_Pos)) |
+                DUALTIMER_TIMER2CONTROL_TIMERPRE(config->timer2.clock_prescaler);
+        if (config->timer2.interrup_enable)
+        {
+            regval |= DUALTIMER_TIMER2CONTROL_INTERRUPT_ENABLE;
+        }
+        DUALTIMER0->TIMER2LOAD.reg = config->timer2.load_value;
+        DUALTIMER0->TIMER2CONTROL.reg = regval;
+        LPMCU_MISC_REGS0->DUALTIMER0_CTRL.reg |= LPMCU_MISC_REGS_DUALTIMER0_CTRL_CNTR_2_ENABLE;
+        dualtimer_enable(DUALTIMER_TIMER2);
+    }
+
+    system_register_isr(RAM_ISR_TABLE_DUALTIMER_INDEX, (uint32_t)dualtimer_isr_handler);
 }
 
 /**
@@ -300,11 +322,12 @@ void dualtimer_init(const struct dualtimer_config *config)
  */
 void dualtimer_register_callback(enum dualtimer_timer timer, dualtimer_callback_t fun)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		dualtimer_callback_timer1 = fun;
-	} else {
-		dualtimer_callback_timer2 = fun;
-	}
+    if (timer == DUALTIMER_TIMER1)
+    {
+        dualtimer_callback_timer1 = fun;
+    } else {
+        dualtimer_callback_timer2 = fun;
+    }
 }
 
 /**
@@ -315,9 +338,10 @@ void dualtimer_register_callback(enum dualtimer_timer timer, dualtimer_callback_
  */
 void dualtimer_unregister_callback(enum dualtimer_timer timer)
 {
-	if (timer == DUALTIMER_TIMER1) {
-		dualtimer_callback_timer1 = NULL;
-	} else {
-		dualtimer_callback_timer2 = NULL;
-	}
-}
\ No newline at end of file
+    if (timer == DUALTIMER_TIMER1)
+    {
+        dualtimer_callback_timer1 = NULL;
+    } else {
+        dualtimer_callback_timer2 = NULL;
+    }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h
index 6d6c7784db65..ded86667dce9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/dualtimer/dualtimer.h
@@ -86,7 +86,7 @@
  *
  *   1. Clearing the one-shot count bit in the control register, in which case the
  *     count proceeds according to the selection of Free-running or Periodic mode.
- *   
+ *
  *   2. Writing a new value to the Load Value register.
  * - Free-running Mode
  *
@@ -131,7 +131,7 @@
  * clock, and is used by the register interface. TIMCLK is the input to the prescale
  * units and the decrementing counters.
  *
- * This provision of two clock inputs enables the counters to continue to run while 
+ * This provision of two clock inputs enables the counters to continue to run while
  * the APB system is in a sleep state when PCLK is disabled. External system control
  * logic must handle the changeover periods when PCLK is disabled and enabled to ensure
  * that the PCLK and TIMCLK inputs are fed with synchronous signals when any register
@@ -182,10 +182,10 @@ typedef void (*dualtimer_callback_t)(void);
  * This enum specifies duatimer timer1 or timer2.
  */
 enum dualtimer_timer {
-	/** Dualtimer timer1 */
-	DUALTIMER_TIMER1 = 0,
-	/** Dualtimer timer2 */
-	DUALTIMER_TIMER2,
+    /** Dualtimer timer1 */
+    DUALTIMER_TIMER1 = 0,
+    /** Dualtimer timer2 */
+    DUALTIMER_TIMER2,
 };
 
 /**
@@ -194,14 +194,14 @@ enum dualtimer_timer {
  * DUALTIMER module clock.
  */
 enum dualtimer_clock_input {
-	/** source from clock input 0: 26MHz */
-	DUALTIMER_CLK_INPUT_0 = 0,
-	/** source from clock input 1: 13MHz */
-	DUALTIMER_CLK_INPUT_1,
-	/** source from clock input 2: 6.5MHz */
-	DUALTIMER_CLK_INPUT_2,
-	/** source from clock input 3: 3MHz*/
-	DUALTIMER_CLK_INPUT_3,
+    /** source from clock input 0: 26MHz */
+    DUALTIMER_CLK_INPUT_0 = 0,
+    /** source from clock input 1: 13MHz */
+    DUALTIMER_CLK_INPUT_1,
+    /** source from clock input 2: 6.5MHz */
+    DUALTIMER_CLK_INPUT_2,
+    /** source from clock input 3: 3MHz*/
+    DUALTIMER_CLK_INPUT_3,
 };
 
 /**
@@ -210,12 +210,12 @@ enum dualtimer_clock_input {
  * This enum specifies counter with one-shot, free running or periodic counter mode.
  */
 enum dualtimer_counter_mode {
-	/** Counter in one-shot mode */
-	DUALTIMER_ONE_SHOT_MODE = 0,
-	/** Counter is in free-running mode */
-	DUALTIMER_FREE_RUNNING_MODE,
-	/** Counter is in periodic mode */
-	DUALTIMER_PERIODIC_MODE,
+    /** Counter in one-shot mode */
+    DUALTIMER_ONE_SHOT_MODE = 0,
+    /** Counter is in free-running mode */
+    DUALTIMER_FREE_RUNNING_MODE,
+    /** Counter is in periodic mode */
+    DUALTIMER_PERIODIC_MODE,
 };
 
 /**
@@ -224,10 +224,10 @@ enum dualtimer_counter_mode {
  * This enum specify the maximum value it is possible to count to.
  */
 enum dualtimer_counter_size {
-	/** 16-bit counter */
-	DUALTIMER_COUNTER_SIZE_16BIT = 0,
-	/** 32-bit counter */
-	DUALTIMER_COUNTER_SIZE_32BIT,
+    /** 16-bit counter */
+    DUALTIMER_COUNTER_SIZE_16BIT = 0,
+    /** 32-bit counter */
+    DUALTIMER_COUNTER_SIZE_32BIT,
 };
 
 /**
@@ -238,12 +238,12 @@ enum dualtimer_counter_size {
  * Dual Timer module to make the counter count slower.
  */
 enum dualtimer_clock_prescaler {
-	/** Divide clock by 1 */
-	DUALTIMER_CLOCK_PRESCALER_DIV1 = 0,
-	/** Divide clock by 16 */
-	DUALTIMER_CLOCK_PRESCALER_DIV16,
-	/** Divide clock by 256 */
-	DUALTIMER_CLOCK_PRESCALER_DIV256,
+    /** Divide clock by 1 */
+    DUALTIMER_CLOCK_PRESCALER_DIV1 = 0,
+    /** Divide clock by 16 */
+    DUALTIMER_CLOCK_PRESCALER_DIV16,
+    /** Divide clock by 256 */
+    DUALTIMER_CLOCK_PRESCALER_DIV256,
 };
 
 /**
@@ -255,10 +255,10 @@ enum dualtimer_clock_prescaler {
  * cause the counter to immediately restart from the new value.
  */
 enum dualtimer_set_register {
-	/** Set current counter */
-	DUALTIMER_SET_CURRUNT_REG = 0,
-	/** Set background counter */
-	DUALTIMER_SET_BG_REG,
+    /** Set current counter */
+    DUALTIMER_SET_CURRUNT_REG = 0,
+    /** Set background counter */
+    DUALTIMER_SET_BG_REG,
 };
 
 /**
@@ -267,18 +267,18 @@ enum dualtimer_set_register {
  * Private configuration struct for Dualtimer instance.
  */
 struct dualtimer_private_config {
-	/** Enable timer */
-	bool timer_enable;
-	/** Selects one-shot or wrapping counter mode */
-	enum dualtimer_counter_mode counter_mode;
-	/** Selects 16-bit or 32- bit counter size */
-	enum dualtimer_counter_size counter_size;
-	/** Selects the prescaler value */
-	enum dualtimer_clock_prescaler clock_prescaler;
-	/** Enable the interrupt */
-	bool interrup_enable;
-	/** Counter load value */
-	uint32_t load_value;
+    /** Enable timer */
+    bool timer_enable;
+    /** Selects one-shot or wrapping counter mode */
+    enum dualtimer_counter_mode counter_mode;
+    /** Selects 16-bit or 32- bit counter size */
+    enum dualtimer_counter_size counter_size;
+    /** Selects the prescaler value */
+    enum dualtimer_clock_prescaler clock_prescaler;
+    /** Enable the interrupt */
+    bool interrup_enable;
+    /** Counter load value */
+    uint32_t load_value;
 };
 
 /**
@@ -289,12 +289,12 @@ struct dualtimer_private_config {
  * modified by the user application.
  */
 struct dualtimer_config {
-	/** Timer1 private configuration */
-	struct dualtimer_private_config timer1;
-	/** Timer2 private configuration */
-	struct dualtimer_private_config timer2;
-	/** Selects Dualtimer clock frequency */
-	enum dualtimer_clock_input clock_source;
+    /** Timer1 private configuration */
+    struct dualtimer_private_config timer1;
+    /** Timer2 private configuration */
+    struct dualtimer_private_config timer2;
+    /** Selects Dualtimer clock frequency */
+    enum dualtimer_clock_input clock_source;
 };
 
 /**
@@ -311,7 +311,7 @@ void dualtimer_init(const struct dualtimer_config *config);
  */
 uint32_t dualtimer_get_value(enum dualtimer_timer timer);
 void dualtimer_set_counter(enum dualtimer_timer timer,
-		enum dualtimer_set_register cur_bg, uint32_t value);
+        enum dualtimer_set_register cur_bg, uint32_t value);
 /** @} */
 
 /**
@@ -352,14 +352,14 @@ void dualtimer_unregister_callback(enum dualtimer_timer timer);
  * Below is a table listing the acronyms used in this module, along with their
  * intended meanings.
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>DUALTIMER</td>
- *		<td>Dualtimer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>DUALTIMER</td>
+ *      <td>Dualtimer</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_dualtimer_extra_dependencies Dependencies
@@ -413,4 +413,4 @@ void dualtimer_unregister_callback(enum dualtimer_timer timer);
  * </table>
  */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h
index 78ee2bd4bc65..0b7b176d35d3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events.h
@@ -324,14 +324,14 @@ extern "C" {
  *
  */
 enum events_edge_detect {
-	/** No event output */
-	EVENTS_EDGE_DETECT_NONE,
-	/** Event on rising edge */
-	EVENTS_EDGE_DETECT_RISING,
-	/** Event on falling edge */
-	EVENTS_EDGE_DETECT_FALLING,
-	/** Event on both edges */
-	EVENTS_EDGE_DETECT_BOTH,
+    /** No event output */
+    EVENTS_EDGE_DETECT_NONE,
+    /** Event on rising edge */
+    EVENTS_EDGE_DETECT_RISING,
+    /** Event on falling edge */
+    EVENTS_EDGE_DETECT_FALLING,
+    /** Event on both edges */
+    EVENTS_EDGE_DETECT_BOTH,
 };
 
 /**
@@ -341,12 +341,12 @@ enum events_edge_detect {
  *
  */
 enum events_path_selection {
-	/** Select the synchronous path for this event channel */
-	EVENTS_PATH_SYNCHRONOUS,
-	/** Select the resynchronizer path for this event channel */
-	EVENTS_PATH_RESYNCHRONIZED,
-	/** Select the asynchronous path for this event channel */
-	EVENTS_PATH_ASYNCHRONOUS,
+    /** Select the synchronous path for this event channel */
+    EVENTS_PATH_SYNCHRONOUS,
+    /** Select the resynchronizer path for this event channel */
+    EVENTS_PATH_RESYNCHRONIZED,
+    /** Select the asynchronous path for this event channel */
+    EVENTS_PATH_ASYNCHRONOUS,
 };
 
 /**
@@ -356,19 +356,19 @@ enum events_path_selection {
  *
  */
 struct events_config {
-	/** Select edge detection mode */
-	enum events_edge_detect    edge_detect;
-	/** Select events channel path */
-	enum events_path_selection path;
-	/** Set event generator for the channel */
-	uint8_t                    generator;
-	/** Clock source for the event channel */
-	uint8_t                    clock_source;
+    /** Select edge detection mode */
+    enum events_edge_detect    edge_detect;
+    /** Select events channel path */
+    enum events_path_selection path;
+    /** Set event generator for the channel */
+    uint8_t                    generator;
+    /** Clock source for the event channel */
+    uint8_t                    clock_source;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Run in standby mode for the channel */
-	bool                       run_in_standby;
-	/** Run On Demand */
-	bool                       on_demand;
+    /** Run in standby mode for the channel */
+    bool                       run_in_standby;
+    /** Run On Demand */
+    bool                       on_demand;
 #endif
 };
 
@@ -380,7 +380,7 @@ struct events_config {
  *
  */
 
-///@cond INTERNAL
+/*/@cond INTERNAL*/
 /**
  * \internal
  * Status bit offsets in the status register/interrupt register.
@@ -399,7 +399,7 @@ struct events_config {
 #  define _EVENTS_START_OFFSET_OVERRUN_BIT         0
 #endif
 /** @} */
-///@endcond
+/*/@endcond*/
 
 /**
 *  Definition for no generator selection.
@@ -416,10 +416,10 @@ struct events_config {
  */
 struct events_resource {
 #if !defined(__DOXYGEN__)
-	/** Channel allocated for the event resource */
-	uint8_t channel;
-	/** Channel setting in CHANNEL register */
-	uint32_t channel_reg;
+    /** Channel allocated for the event resource */
+    uint8_t channel;
+    /** Channel setting in CHANNEL register */
+    uint32_t channel_reg;
 #endif
 };
 
@@ -433,12 +433,12 @@ typedef void (*events_interrupt_hook)(struct events_resource *resource);
  *
  */
 struct events_hook {
-	/** Event resource */
-	struct events_resource *resource;
-	/** Event hook function */
-	events_interrupt_hook hook_func;
-	/** Next event hook */
-	struct events_hook *next;
+    /** Event resource */
+    struct events_resource *resource;
+    /** Event hook function */
+    events_interrupt_hook hook_func;
+    /** Next event hook */
+    struct events_hook *next;
 };
 #endif
 
@@ -591,7 +591,7 @@ enum status_code events_release(struct events_resource *resource);
 uint8_t events_get_free_channels(void);
 
 
-///@cond INTERNAL
+/*/@cond INTERNAL*/
 /**
  * \internal
  * Function to find bit position in the CHSTATUS and INTFLAG register,
@@ -601,7 +601,7 @@ uint8_t events_get_free_channels(void);
  */
 uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset);
 /** @} */
-///@endcond
+/*/@endcond*/
 
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h
index b40db7cec881..341b110621be 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_common.h
@@ -52,19 +52,19 @@
  *
  */
 struct _events_module {
-	/* Allocated channels bitmask where 1 means allocated */
-	volatile uint32_t allocated_channels;
-	/* Free channels */
-	uint8_t           free_channels;
+    /* Allocated channels bitmask where 1 means allocated */
+    volatile uint32_t allocated_channels;
+    /* Free channels */
+    uint8_t           free_channels;
 
 #if EVENTS_INTERRUPT_HOOKS_MODE == true
-	/* Buffer to store a copy of the current interrupt flags */
-	volatile uint32_t interrupt_flag_buffer;
-	/* Buffer to store acknowledged interrupt sources */
-	volatile uint32_t interrupt_flag_ack_buffer;
+    /* Buffer to store a copy of the current interrupt flags */
+    volatile uint32_t interrupt_flag_buffer;
+    /* Buffer to store acknowledged interrupt sources */
+    volatile uint32_t interrupt_flag_ack_buffer;
 
-	/* Interrup hook linked list start pointer */
-	struct events_hook *hook_list;
+    /* Interrup hook linked list start pointer */
+    struct events_hook *hook_list;
 #endif
 };
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c
index ee912b060e0a..93e7bf8d0150 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.c
@@ -60,175 +60,191 @@ extern struct _events_module _events_inst;
 
 enum status_code events_create_hook(struct events_hook *hook, events_interrupt_hook func)
 {
-	/* Initialize the hook struct members */
-	hook->next      = NULL;
-	hook->resource  = NULL;
-	hook->hook_func = func;
+    /* Initialize the hook struct members */
+    hook->next      = NULL;
+    hook->resource  = NULL;
+    hook->hook_func = func;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 enum status_code events_add_hook(struct events_resource *resource, struct events_hook *hook)
 {
-	struct events_hook *tmp_hook = NULL;
-
-	/* Associate the hook with the resource */
-	hook->resource = resource;
-
-	/* Check if this is the first hook in the list */
-	if (_events_inst.hook_list == NULL) {
-		_events_inst.hook_list = hook;
-	} else {
-		tmp_hook = _events_inst.hook_list;
-
-		/* Find the first free place in the list */
-		while (tmp_hook->next != NULL) {
-			tmp_hook = tmp_hook->next;
-		}
-
-		/* Put the hook into the next free place in the list */
-		tmp_hook->next = hook;
-	}
-
-	/* Check if interrupts from the EVSYS module is enabled in the interrupt controller */
-	if (!system_interrupt_is_enabled(SYSTEM_INTERRUPT_MODULE_EVSYS)) {
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EVSYS);
-	}
-
-	return STATUS_OK;
+    struct events_hook *tmp_hook = NULL;
+
+    /* Associate the hook with the resource */
+    hook->resource = resource;
+
+    /* Check if this is the first hook in the list */
+    if (_events_inst.hook_list == NULL)
+    {
+        _events_inst.hook_list = hook;
+    } else {
+        tmp_hook = _events_inst.hook_list;
+
+        /* Find the first free place in the list */
+        while (tmp_hook->next != NULL)
+        {
+            tmp_hook = tmp_hook->next;
+        }
+
+        /* Put the hook into the next free place in the list */
+        tmp_hook->next = hook;
+    }
+
+    /* Check if interrupts from the EVSYS module is enabled in the interrupt controller */
+    if (!system_interrupt_is_enabled(SYSTEM_INTERRUPT_MODULE_EVSYS))
+    {
+        system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EVSYS);
+    }
+
+    return STATUS_OK;
 }
 
 enum status_code events_del_hook(struct events_resource *resource, struct events_hook *hook)
 {
-	struct events_hook *tmp_hook = _events_inst.hook_list;
-	struct events_hook *last_hook = NULL;
-
-	if (tmp_hook != NULL) {
-		/* Check if the first hook in the list is the one we are looking for */
-		if (tmp_hook != hook) {
-			/* Don't double check the first hook */
-			tmp_hook = tmp_hook->next;
-
-			/* Check if the current hook is the one we are looking for */
-			while (tmp_hook != hook) {
-
-				/* If the current hook pointer is NULL the hook is not found in the list */
-				if(tmp_hook == NULL) {
-					return STATUS_ERR_NOT_FOUND;
-				}
-
-				last_hook = tmp_hook;
-				tmp_hook = tmp_hook->next;
-
-			}
-			/* Remove the current hook from the list */
-			last_hook->next = tmp_hook->next;
-		} else {
-			_events_inst.hook_list = tmp_hook->next;
-		}
-	} else {
-		/* No hooks where found in the list */
-		return STATUS_ERR_NO_MEMORY;
-	}
-
-	return STATUS_OK;
+    struct events_hook *tmp_hook = _events_inst.hook_list;
+    struct events_hook *last_hook = NULL;
+
+    if (tmp_hook != NULL)
+    {
+        /* Check if the first hook in the list is the one we are looking for */
+        if (tmp_hook != hook)
+        {
+            /* Don't double check the first hook */
+            tmp_hook = tmp_hook->next;
+
+            /* Check if the current hook is the one we are looking for */
+            while (tmp_hook != hook)
+            {
+
+                /* If the current hook pointer is NULL the hook is not found in the list */
+                if(tmp_hook == NULL)
+                {
+                    return STATUS_ERR_NOT_FOUND;
+                }
+
+                last_hook = tmp_hook;
+                tmp_hook = tmp_hook->next;
+
+            }
+            /* Remove the current hook from the list */
+            last_hook->next = tmp_hook->next;
+        } else {
+            _events_inst.hook_list = tmp_hook->next;
+        }
+    } else {
+        /* No hooks where found in the list */
+        return STATUS_ERR_NO_MEMORY;
+    }
+
+    return STATUS_OK;
 }
 
 enum status_code events_enable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source)
 {
-	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
-
-	if (source == EVENTS_INTERRUPT_DETECT) {
-		EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_DETECTION_BIT);
-	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
-		EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_OVERRUN_BIT);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+    if (source == EVENTS_INTERRUPT_DETECT)
+    {
+        EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_DETECTION_BIT);
+    } else if (source == EVENTS_INTERRUPT_OVERRUN)
+    {
+        EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_OVERRUN_BIT);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 enum status_code events_disable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source)
 {
-	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
-
-	if (source == EVENTS_INTERRUPT_DETECT) {
-		EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_DETECTION_BIT);
-	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
-		EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_OVERRUN_BIT);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+    if (source == EVENTS_INTERRUPT_DETECT)
+    {
+        EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_DETECTION_BIT);
+    } else if (source == EVENTS_INTERRUPT_OVERRUN)
+    {
+        EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_OVERRUN_BIT);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 
 bool events_is_interrupt_set(struct events_resource *resource, enum events_interrupt_source source)
 {
-	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
-
-	uint32_t bitpos;
-
-	if (source == EVENTS_INTERRUPT_DETECT) {
-		bitpos = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_DETECTION_BIT);
-	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
-		bitpos = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_OVERRUN_BIT);
-	} else {
-		return false;
-	}
-
-	return (bool)(_events_inst.interrupt_flag_buffer & bitpos);
+    Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+
+    uint32_t bitpos;
+
+    if (source == EVENTS_INTERRUPT_DETECT)
+    {
+        bitpos = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_DETECTION_BIT);
+    } else if (source == EVENTS_INTERRUPT_OVERRUN)
+    {
+        bitpos = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_OVERRUN_BIT);
+    } else {
+        return false;
+    }
+
+    return (bool)(_events_inst.interrupt_flag_buffer & bitpos);
 }
 
 enum status_code events_ack_interrupt(struct events_resource *resource, enum events_interrupt_source source)
 {
-	Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
+    Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN));
 
-	uint32_t bitpos;
+    uint32_t bitpos;
 
-	if (source == EVENTS_INTERRUPT_DETECT) {
-		bitpos = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_DETECTION_BIT);
-	} else if (source == EVENTS_INTERRUPT_OVERRUN) {
-		bitpos = _events_find_bit_position(resource->channel,
-				_EVENTS_START_OFFSET_OVERRUN_BIT);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (source == EVENTS_INTERRUPT_DETECT)
+    {
+        bitpos = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_DETECTION_BIT);
+    } else if (source == EVENTS_INTERRUPT_OVERRUN)
+    {
+        bitpos = _events_find_bit_position(resource->channel,
+                _EVENTS_START_OFFSET_OVERRUN_BIT);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	_events_inst.interrupt_flag_ack_buffer |= bitpos;
+    _events_inst.interrupt_flag_ack_buffer |= bitpos;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 void EVSYS_Handler(void)
 {
-	struct events_hook *current_hook = _events_inst.hook_list;
-	uint32_t flag;
-
-	/* Synch the interrupt flag buffer with the hardware register */
-	flag = EVSYS->INTFLAG.reg;
-	_events_inst.interrupt_flag_buffer |= flag;
-	/* Clear all hardware interrupt flags */
-	EVSYS->INTFLAG.reg = _EVENTS_INTFLAGS_MASK;
-
-	/* Traverse the linked list */
-	while (current_hook != NULL) {
-		current_hook->hook_func(current_hook->resource);
-		current_hook = current_hook->next;
-	}
-
-	/* Clear acknowledged interrupt sources from the interrupt flag buffer */
-	flag = _events_inst.interrupt_flag_ack_buffer;
-	_events_inst.interrupt_flag_buffer &= ~flag;
+    struct events_hook *current_hook = _events_inst.hook_list;
+    uint32_t flag;
+
+    /* Synch the interrupt flag buffer with the hardware register */
+    flag = EVSYS->INTFLAG.reg;
+    _events_inst.interrupt_flag_buffer |= flag;
+    /* Clear all hardware interrupt flags */
+    EVSYS->INTFLAG.reg = _EVENTS_INTFLAGS_MASK;
+
+    /* Traverse the linked list */
+    while (current_hook != NULL)
+    {
+        current_hook->hook_func(current_hook->resource);
+        current_hook = current_hook->next;
+    }
+
+    /* Clear acknowledged interrupt sources from the interrupt flag buffer */
+    flag = _events_inst.interrupt_flag_ack_buffer;
+    _events_inst.interrupt_flag_buffer &= ~flag;
 }
 
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h
index f16e5e33630c..b1aa3f8f995f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_hooks.h
@@ -66,10 +66,10 @@ extern "C" {
  *
  */
 enum events_interrupt_source {
-	/** Overrun in event channel detected interrupt */
-	EVENTS_INTERRUPT_OVERRUN,
-	/** Event signal propagation in event channel detected interrupt */
-	EVENTS_INTERRUPT_DETECT,
+    /** Overrun in event channel detected interrupt */
+    EVENTS_INTERRUPT_OVERRUN,
+    /** Event signal propagation in event channel detected interrupt */
+    EVENTS_INTERRUPT_DETECT,
 };
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c
index ed8784417ef9..bda20148578f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_d_r_h/events.c
@@ -52,14 +52,14 @@
 #define EVENTS_INVALID_CHANNEL                  0xff
 
 struct _events_module _events_inst = {
-		.allocated_channels = 0,
-		.free_channels      = EVSYS_CHANNELS,
+        .allocated_channels = 0,
+        .free_channels      = EVSYS_CHANNELS,
 
 #if EVENTS_INTERRUPT_HOOKS_MODE == true
-		.interrupt_flag_buffer     = 0,
-		.interrupt_flag_ack_buffer = 0,
+        .interrupt_flag_buffer     = 0,
+        .interrupt_flag_ack_buffer = 0,
 
-		.hook_list                 = NULL,
+        .hook_list                 = NULL,
 #endif
 };
 
@@ -69,60 +69,64 @@ struct _events_module _events_inst = {
  */
 uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset)
 {
-	uint32_t pos;
+    uint32_t pos;
 
-	if (channel < _EVENTS_START_OFFSET_BUSY_BITS) {
-		pos = 0x01UL << (start_offset + channel);
-	} else {
-		pos = 0x01UL << (start_offset + channel + _EVENTS_START_OFFSET_BUSY_BITS);
-	}
+    if (channel < _EVENTS_START_OFFSET_BUSY_BITS)
+    {
+        pos = 0x01UL << (start_offset + channel);
+    } else {
+        pos = 0x01UL << (start_offset + channel + _EVENTS_START_OFFSET_BUSY_BITS);
+    }
 
-	return pos;
+    return pos;
 }
 
 static uint8_t _events_find_first_free_channel_and_allocate(void)
 {
-	uint8_t count;
-	uint32_t tmp;
-	bool allocated = false;
+    uint8_t count;
+    uint32_t tmp;
+    bool allocated = false;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	tmp = _events_inst.allocated_channels;
+    tmp = _events_inst.allocated_channels;
 
-	for(count = 0; count < EVSYS_CHANNELS; ++count) {
+    for(count = 0; count < EVSYS_CHANNELS; ++count)
+    {
 
-		if(!(tmp & 0x00000001)) {
-			/* If free channel found, set as allocated and return number */
+        if(!(tmp & 0x00000001))
+        {
+            /* If free channel found, set as allocated and return number */
 
-			_events_inst.allocated_channels |= 1 << count;
-			_events_inst.free_channels--;
-			allocated = true;
+            _events_inst.allocated_channels |= 1 << count;
+            _events_inst.free_channels--;
+            allocated = true;
 
-			break;
+            break;
 
-		}
+        }
 
-		tmp = tmp >> 1;
-	}
+        tmp = tmp >> 1;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	if(!allocated) {
-		return EVENTS_INVALID_CHANNEL;
-	} else {
-		return count;
-	}
+    if(!allocated)
+    {
+        return EVENTS_INVALID_CHANNEL;
+    } else {
+        return count;
+    }
 }
 
 static void _events_release_channel(uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	_events_inst.allocated_channels &= ~(1 << channel);
-	_events_inst.free_channels++;
+    _events_inst.allocated_channels &= ~(1 << channel);
+    _events_inst.free_channels++;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 
@@ -133,14 +137,15 @@ static void _events_release_channel(uint8_t channel)
 #endif
 void _system_events_init(void)
 {
-	/* Enable EVSYS register interface */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_EVSYS);
+    /* Enable EVSYS register interface */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_EVSYS);
 
-	/* Make sure the EVSYS module is properly reset */
-	EVSYS->CTRL.reg = EVSYS_CTRL_SWRST;
+    /* Make sure the EVSYS module is properly reset */
+    EVSYS->CTRL.reg = EVSYS_CTRL_SWRST;
 
-	while (EVSYS->CTRL.reg & EVSYS_CTRL_SWRST) {
-	}
+    while (EVSYS->CTRL.reg & EVSYS_CTRL_SWRST)
+    {
+    }
 }
 #if defined(__GNUC__)
 #  pragma GCC diagnostic pop
@@ -148,181 +153,189 @@ void _system_events_init(void)
 
 void events_get_config_defaults(struct events_config *config)
 {
-	/* Check that config is something other than NULL */
-	Assert(config);
+    /* Check that config is something other than NULL */
+    Assert(config);
 
-	config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
-	config->path         = EVENTS_PATH_SYNCHRONOUS;
-	config->generator    = EVSYS_ID_GEN_NONE;
-	config->clock_source = GCLK_GENERATOR_0;
+    config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
+    config->path         = EVENTS_PATH_SYNCHRONOUS;
+    config->generator    = EVSYS_ID_GEN_NONE;
+    config->clock_source = GCLK_GENERATOR_0;
 }
 
 enum status_code events_allocate(
-		struct events_resource *resource,
-		struct events_config *config)
+        struct events_resource *resource,
+        struct events_config *config)
 {
-	uint8_t new_channel;
+    uint8_t new_channel;
 
-	Assert(resource);
+    Assert(resource);
 
-	new_channel = _events_find_first_free_channel_and_allocate();
+    new_channel = _events_find_first_free_channel_and_allocate();
 
-	if(new_channel == EVENTS_INVALID_CHANNEL) {
-		return STATUS_ERR_NOT_FOUND;
-	}
+    if(new_channel == EVENTS_INVALID_CHANNEL)
+    {
+        return STATUS_ERR_NOT_FOUND;
+    }
 
-	resource->channel = new_channel;
+    resource->channel = new_channel;
 
-	if (config->path != EVENTS_PATH_ASYNCHRONOUS) {
-		/* Set up a GLCK channel to use with the specific channel */
-		struct system_gclk_chan_config gclk_chan_conf;
+    if (config->path != EVENTS_PATH_ASYNCHRONOUS)
+    {
+        /* Set up a GLCK channel to use with the specific channel */
+        struct system_gclk_chan_config gclk_chan_conf;
 
-		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-		gclk_chan_conf.source_generator =
-				(enum gclk_generator)config->clock_source;
-		system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
-		system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
-	}
+        system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+        gclk_chan_conf.source_generator =
+                (enum gclk_generator)config->clock_source;
+        system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
+        system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
+    }
 
-	/* Save channel setting and configure it after user multiplexer */
-	resource->channel_reg = EVSYS_CHANNEL_CHANNEL(new_channel)       |
-			     EVSYS_CHANNEL_EVGEN(config->generator)   |
-			     EVSYS_CHANNEL_PATH(config->path)         |
-			     EVSYS_CHANNEL_EDGSEL(config->edge_detect);
+    /* Save channel setting and configure it after user multiplexer */
+    resource->channel_reg = EVSYS_CHANNEL_CHANNEL(new_channel)       |
+                 EVSYS_CHANNEL_EVGEN(config->generator)   |
+                 EVSYS_CHANNEL_PATH(config->path)         |
+                 EVSYS_CHANNEL_EDGSEL(config->edge_detect);
 
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 
 enum status_code events_release(struct events_resource *resource)
 {
-	enum status_code err = STATUS_OK;
+    enum status_code err = STATUS_OK;
 
-	Assert(resource);
+    Assert(resource);
 
-	/* Check if channel is busy */
-	if(events_is_busy(resource)) {
-		return STATUS_BUSY;
-	}
+    /* Check if channel is busy */
+    if(events_is_busy(resource))
+    {
+        return STATUS_BUSY;
+    }
 
-	if (!(_events_inst.allocated_channels & (1<<resource->channel))) {
-		err = STATUS_ERR_NOT_INITIALIZED;
-	} else {
-		_events_release_channel(resource->channel);
-	}
+    if (!(_events_inst.allocated_channels & (1<<resource->channel)))
+    {
+        err = STATUS_ERR_NOT_INITIALIZED;
+    } else {
+        _events_release_channel(resource->channel);
+    }
 
-	return err;
+    return err;
 }
 
 enum status_code events_trigger(struct events_resource *resource)
 {
 
-	Assert(resource);
+    Assert(resource);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Because of indirect access the channel must be set first */
-	((uint8_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel);
+    /* Because of indirect access the channel must be set first */
+    ((uint8_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel);
 
-	/* Assert if event path is asynchronous */
-	if (EVSYS->CHANNEL.reg & EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS)) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Assert if event path is asynchronous */
+    if (EVSYS->CHANNEL.reg & EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS))
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	/* Assert if event edge detection is not set to RISING */
-	if (!(EVSYS->CHANNEL.reg & EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING))) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Assert if event edge detection is not set to RISING */
+    if (!(EVSYS->CHANNEL.reg & EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING)))
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
 
-	/* The GCLKREQ bit has to be set while triggering the software event */
-	EVSYS->CTRL.reg = EVSYS_CTRL_GCLKREQ;
+    /* The GCLKREQ bit has to be set while triggering the software event */
+    EVSYS->CTRL.reg = EVSYS_CTRL_GCLKREQ;
 
-	((uint16_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel) |
-					  EVSYS_CHANNEL_SWEVT;
+    ((uint16_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel) |
+                      EVSYS_CHANNEL_SWEVT;
 
-	EVSYS->CTRL.reg &= ~EVSYS_CTRL_GCLKREQ;
+    EVSYS->CTRL.reg &= ~EVSYS_CTRL_GCLKREQ;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 bool events_is_busy(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_BUSY_BITS));
+    return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_BUSY_BITS));
 }
 
 bool events_is_users_ready(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_USER_READY_BIT));
+    return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_USER_READY_BIT));
 }
 
 bool events_is_detected(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	uint32_t flag = _events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_DETECTION_BIT);
+    uint32_t flag = _events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_DETECTION_BIT);
 
-	/* Clear flag when read */
-	if (EVSYS->INTFLAG.reg & flag) {
-		EVSYS->INTFLAG.reg = flag;
-		return true;
-	}
+    /* Clear flag when read */
+    if (EVSYS->INTFLAG.reg & flag)
+    {
+        EVSYS->INTFLAG.reg = flag;
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 bool events_is_overrun(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	uint32_t flag = _events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_OVERRUN_BIT);
+    uint32_t flag = _events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_OVERRUN_BIT);
 
-	/* Clear flag when read */
-	if (EVSYS->INTFLAG.reg & flag) {
-		EVSYS->INTFLAG.reg = flag;
-		return true;
-	}
+    /* Clear flag when read */
+    if (EVSYS->INTFLAG.reg & flag)
+    {
+        EVSYS->INTFLAG.reg = flag;
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id)
 {
-	Assert(resource);
+    Assert(resource);
 
-	/* First configure user multiplexer: channel number is n + 1 */
-	EVSYS->USER.reg = EVSYS_USER_CHANNEL(resource->channel + 1) |
-			  EVSYS_USER_USER(user_id);
+    /* First configure user multiplexer: channel number is n + 1 */
+    EVSYS->USER.reg = EVSYS_USER_CHANNEL(resource->channel + 1) |
+              EVSYS_USER_USER(user_id);
 
-	/* Then configure the channel */
-	EVSYS->CHANNEL.reg = resource->channel_reg;
+    /* Then configure the channel */
+    EVSYS->CHANNEL.reg = resource->channel_reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id)
 {
 
-	Assert(resource);
+    Assert(resource);
 
-	/* Write 0 to the channel bit field to select no input */
-	EVSYS->USER.reg = EVSYS_USER_USER(user_id);
+    /* Write 0 to the channel bit field to select no input */
+    EVSYS->USER.reg = EVSYS_USER_USER(user_id);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 uint8_t events_get_free_channels()
 {
-	return _events_inst.free_channels;
+    return _events_inst.free_channels;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c
index 5c8e876ccf85..1d104024fae4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/events/events_sam_l_c/events.c
@@ -52,14 +52,14 @@
 #define EVENTS_INVALID_CHANNEL                  0xff
 
 struct _events_module _events_inst = {
-		.allocated_channels = 0,
-		.free_channels      = EVSYS_CHANNELS,
+        .allocated_channels = 0,
+        .free_channels      = EVSYS_CHANNELS,
 
 #if EVENTS_INTERRUPT_HOOKS_MODE == true
-		.interrupt_flag_buffer     = 0,
-		.interrupt_flag_ack_buffer = 0,
+        .interrupt_flag_buffer     = 0,
+        .interrupt_flag_ack_buffer = 0,
 
-		.hook_list                 = NULL,
+        .hook_list                 = NULL,
 #endif
 };
 
@@ -69,56 +69,59 @@ struct _events_module _events_inst = {
  */
 uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset)
 {
-	uint32_t pos;
+    uint32_t pos;
 
-	pos = 0x01UL << (start_offset + channel);
+    pos = 0x01UL << (start_offset + channel);
 
-	return pos;
+    return pos;
 }
 
 static uint8_t _events_find_first_free_channel_and_allocate(void)
 {
-	uint8_t count;
-	uint32_t tmp;
-	bool allocated = false;
+    uint8_t count;
+    uint32_t tmp;
+    bool allocated = false;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	tmp = _events_inst.allocated_channels;
+    tmp = _events_inst.allocated_channels;
 
-	for(count = 0; count < EVSYS_CHANNELS; ++count) {
+    for(count = 0; count < EVSYS_CHANNELS; ++count)
+    {
 
-		if(!(tmp & 0x00000001)) {
-			/* If free channel found, set as allocated and return number */
+        if(!(tmp & 0x00000001))
+        {
+            /* If free channel found, set as allocated and return number */
 
-			_events_inst.allocated_channels |= 1 << count;
-			_events_inst.free_channels--;
-			allocated = true;
+            _events_inst.allocated_channels |= 1 << count;
+            _events_inst.free_channels--;
+            allocated = true;
 
-			break;
+            break;
 
-		}
+        }
 
-		tmp = tmp >> 1;
-	}
+        tmp = tmp >> 1;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	if(!allocated) {
-		return EVENTS_INVALID_CHANNEL;
-	} else {
-		return count;
-	}
+    if(!allocated)
+    {
+        return EVENTS_INVALID_CHANNEL;
+    } else {
+        return count;
+    }
 }
 
 static void _events_release_channel(uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	_events_inst.allocated_channels &= ~(1 << channel);
-	_events_inst.free_channels++;
+    _events_inst.allocated_channels &= ~(1 << channel);
+    _events_inst.free_channels++;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 
@@ -130,18 +133,19 @@ static void _events_release_channel(uint8_t channel)
 void _system_events_init(void)
 {
 #if (SAML22) || (SAMC20) || (SAMC21)
-	/* Enable EVSYS register interface */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_EVSYS);
+    /* Enable EVSYS register interface */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_EVSYS);
 #else
-	/* Enable EVSYS register interface */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_EVSYS);
+    /* Enable EVSYS register interface */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_EVSYS);
 #endif
 
-	/* Make sure the EVSYS module is properly reset */
-	EVSYS->CTRLA.reg = EVSYS_CTRLA_SWRST;
+    /* Make sure the EVSYS module is properly reset */
+    EVSYS->CTRLA.reg = EVSYS_CTRLA_SWRST;
 
-	while (EVSYS->CTRLA.reg & EVSYS_CTRLA_SWRST) {
-	}
+    while (EVSYS->CTRLA.reg & EVSYS_CTRLA_SWRST)
+    {
+    }
 }
 #if defined(__GNUC__)
 #  pragma GCC diagnostic pop
@@ -149,173 +153,181 @@ void _system_events_init(void)
 
 void events_get_config_defaults(struct events_config *config)
 {
-	/* Check that config is something other than NULL */
-	Assert(config);
-
-	config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
-	config->path         = EVENTS_PATH_SYNCHRONOUS;
-	config->generator    = EVSYS_ID_GEN_NONE;
-	config->clock_source = GCLK_GENERATOR_0;
-	config->run_in_standby = false;
-	config->on_demand    = false;
+    /* Check that config is something other than NULL */
+    Assert(config);
+
+    config->edge_detect  = EVENTS_EDGE_DETECT_RISING;
+    config->path         = EVENTS_PATH_SYNCHRONOUS;
+    config->generator    = EVSYS_ID_GEN_NONE;
+    config->clock_source = GCLK_GENERATOR_0;
+    config->run_in_standby = false;
+    config->on_demand    = false;
 }
 
 enum status_code events_allocate(
-		struct events_resource *resource,
-		struct events_config *config)
+        struct events_resource *resource,
+        struct events_config *config)
 {
-	uint8_t new_channel;
+    uint8_t new_channel;
 
-	Assert(resource);
+    Assert(resource);
 
-	new_channel = _events_find_first_free_channel_and_allocate();
+    new_channel = _events_find_first_free_channel_and_allocate();
 
-	if(new_channel == EVENTS_INVALID_CHANNEL) {
-		return STATUS_ERR_NOT_FOUND;
-	}
+    if(new_channel == EVENTS_INVALID_CHANNEL)
+    {
+        return STATUS_ERR_NOT_FOUND;
+    }
 
-	resource->channel = new_channel;
+    resource->channel = new_channel;
 
-	if (config->path != EVENTS_PATH_ASYNCHRONOUS) {
-		/* Set up a GLCK channel to use with the specific channel */
-		struct system_gclk_chan_config gclk_chan_conf;
+    if (config->path != EVENTS_PATH_ASYNCHRONOUS)
+    {
+        /* Set up a GLCK channel to use with the specific channel */
+        struct system_gclk_chan_config gclk_chan_conf;
 
-		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-		gclk_chan_conf.source_generator =
-				(enum gclk_generator)config->clock_source;
-		system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
-		system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
-	}
+        system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+        gclk_chan_conf.source_generator =
+                (enum gclk_generator)config->clock_source;
+        system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf);
+        system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel);
+    }
 
-	/* Save channel setting and configure it after user multiplexer */
-	resource->channel_reg = EVSYS_CHANNEL_EVGEN(config->generator)           |
-			EVSYS_CHANNEL_PATH(config->path)                                 |
-			((uint32_t)config->run_in_standby << EVSYS_CHANNEL_RUNSTDBY_Pos) |
-			((uint32_t)config->on_demand << EVSYS_CHANNEL_ONDEMAND_Pos) |
-			EVSYS_CHANNEL_EDGSEL(config->edge_detect);
+    /* Save channel setting and configure it after user multiplexer */
+    resource->channel_reg = EVSYS_CHANNEL_EVGEN(config->generator)           |
+            EVSYS_CHANNEL_PATH(config->path)                                 |
+            ((uint32_t)config->run_in_standby << EVSYS_CHANNEL_RUNSTDBY_Pos) |
+            ((uint32_t)config->on_demand << EVSYS_CHANNEL_ONDEMAND_Pos) |
+            EVSYS_CHANNEL_EDGSEL(config->edge_detect);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 
 enum status_code events_release(struct events_resource *resource)
 {
-	enum status_code err = STATUS_OK;
+    enum status_code err = STATUS_OK;
 
-	Assert(resource);
+    Assert(resource);
 
-	/* Check if channel is busy */
-	if(events_is_busy(resource)) {
-		return STATUS_BUSY;
-	}
+    /* Check if channel is busy */
+    if(events_is_busy(resource))
+    {
+        return STATUS_BUSY;
+    }
 
-	if (!(_events_inst.allocated_channels & (1<<resource->channel))) {
-		err = STATUS_ERR_NOT_INITIALIZED;
-	} else {
-		_events_release_channel(resource->channel);
-	}
+    if (!(_events_inst.allocated_channels & (1<<resource->channel)))
+    {
+        err = STATUS_ERR_NOT_INITIALIZED;
+    } else {
+        _events_release_channel(resource->channel);
+    }
 
-	return err;
+    return err;
 }
 
 enum status_code events_trigger(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Assert if event path is asynchronous */
-	if (EVSYS->CHANNEL[resource->channel].reg &
-			EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS)) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Assert if event path is asynchronous */
+    if (EVSYS->CHANNEL[resource->channel].reg &
+            EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS))
+            {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	/* Assert if event edge detection is not set to RISING */
-	if (!(EVSYS->CHANNEL[resource->channel].reg &
-			EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING))) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Assert if event edge detection is not set to RISING */
+    if (!(EVSYS->CHANNEL[resource->channel].reg &
+            EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING)))
+            {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	EVSYS->SWEVT.reg = (0x01UL << resource->channel);
+    EVSYS->SWEVT.reg = (0x01UL << resource->channel);
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 bool events_is_busy(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_BUSY_BITS));
+    return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_BUSY_BITS));
 }
 
 bool events_is_users_ready(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_USER_READY_BIT));
+    return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_USER_READY_BIT));
 }
 
 bool events_is_detected(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	uint32_t flag = _events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_DETECTION_BIT);
+    uint32_t flag = _events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_DETECTION_BIT);
 
-	/* Clear flag when read */
-	if (EVSYS->INTFLAG.reg & flag) {
-		EVSYS->INTFLAG.reg = flag;
-		return true;
-	}
+    /* Clear flag when read */
+    if (EVSYS->INTFLAG.reg & flag)
+    {
+        EVSYS->INTFLAG.reg = flag;
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 bool events_is_overrun(struct events_resource *resource)
 {
-	Assert(resource);
+    Assert(resource);
 
-	uint32_t flag = _events_find_bit_position(resource->channel,
-			_EVENTS_START_OFFSET_OVERRUN_BIT);
+    uint32_t flag = _events_find_bit_position(resource->channel,
+            _EVENTS_START_OFFSET_OVERRUN_BIT);
 
-	/* Clear flag when read */
-	if (EVSYS->INTFLAG.reg & flag) {
-		EVSYS->INTFLAG.reg = flag;
-		return true;
-	}
+    /* Clear flag when read */
+    if (EVSYS->INTFLAG.reg & flag)
+    {
+        EVSYS->INTFLAG.reg = flag;
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id)
 {
-	Assert(resource);
+    Assert(resource);
 
-	/* First configure user multiplexer: channel number is n + 1 */
-	EVSYS->USER[user_id].reg = EVSYS_USER_CHANNEL(resource->channel + 1);
+    /* First configure user multiplexer: channel number is n + 1 */
+    EVSYS->USER[user_id].reg = EVSYS_USER_CHANNEL(resource->channel + 1);
 
-	/* Then configure the channel */
-	EVSYS->CHANNEL[resource->channel].reg = resource->channel_reg;
+    /* Then configure the channel */
+    EVSYS->CHANNEL[resource->channel].reg = resource->channel_reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id)
 {
 
-	Assert(resource);
+    Assert(resource);
 
-	/* Write 0 to the channel bit field to select no input */
-	EVSYS->USER[user_id].reg = 0;
+    /* Write 0 to the channel bit field to select no input */
+    EVSYS->USER[user_id].reg = 0;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 uint8_t events_get_free_channels()
 {
-	return _events_inst.free_channels;
+    return _events_inst.free_channels;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h
index 1225881c3be2..4b6f00c84221 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint.h
@@ -238,19 +238,19 @@ extern "C" {
  * Interrupt Controller module.
  */
 enum extint_detect {
-	/** No edge detection. Not allowed as a NMI detection mode on some
-	 *  devices. */
-	EXTINT_DETECT_NONE    = 0,
-	/** Detect rising signal edges */
-	EXTINT_DETECT_RISING  = 1,
-	/** Detect falling signal edges */
-	EXTINT_DETECT_FALLING = 2,
-	/** Detect both signal edges */
-	EXTINT_DETECT_BOTH    = 3,
-	/** Detect high signal levels */
-	EXTINT_DETECT_HIGH    = 4,
-	/** Detect low signal levels */
-	EXTINT_DETECT_LOW     = 5,
+    /** No edge detection. Not allowed as a NMI detection mode on some
+     *  devices. */
+    EXTINT_DETECT_NONE    = 0,
+    /** Detect rising signal edges */
+    EXTINT_DETECT_RISING  = 1,
+    /** Detect falling signal edges */
+    EXTINT_DETECT_FALLING = 2,
+    /** Detect both signal edges */
+    EXTINT_DETECT_BOTH    = 3,
+    /** Detect high signal levels */
+    EXTINT_DETECT_HIGH    = 4,
+    /** Detect low signal levels */
+    EXTINT_DETECT_LOW     = 5,
 };
 
 /**
@@ -263,12 +263,12 @@ enum extint_detect {
  *       inputs generating continuous interrupts.
  */
 enum extint_pull {
-	/** Internal pull-up resistor is enabled on the pin */
-	EXTINT_PULL_UP        = SYSTEM_PINMUX_PIN_PULL_UP,
-	/** Internal pull-down resistor is enabled on the pin */
-	EXTINT_PULL_DOWN      = SYSTEM_PINMUX_PIN_PULL_DOWN,
-	/** Internal pull resistor is disconnected from the pin */
-	EXTINT_PULL_NONE      = SYSTEM_PINMUX_PIN_PULL_NONE,
+    /** Internal pull-up resistor is enabled on the pin */
+    EXTINT_PULL_UP        = SYSTEM_PINMUX_PIN_PULL_UP,
+    /** Internal pull-down resistor is enabled on the pin */
+    EXTINT_PULL_DOWN      = SYSTEM_PINMUX_PIN_PULL_DOWN,
+    /** Internal pull resistor is disconnected from the pin */
+    EXTINT_PULL_NONE      = SYSTEM_PINMUX_PIN_PULL_NONE,
 };
 
 /** The EIC is clocked by GCLK_EIC. */
@@ -283,24 +283,24 @@ enum extint_pull {
  *  interrupt channel.
  */
 struct extint_chan_conf {
-	/** GPIO pin the NMI should be connected to */
-	uint32_t gpio_pin;
-	/** MUX position the GPIO pin should be configured to */
-	uint32_t gpio_pin_mux;
-	/** Internal pull to enable on the input pin */
-	enum extint_pull gpio_pin_pull;
+    /** GPIO pin the NMI should be connected to */
+    uint32_t gpio_pin;
+    /** MUX position the GPIO pin should be configured to */
+    uint32_t gpio_pin_mux;
+    /** Internal pull to enable on the input pin */
+    enum extint_pull gpio_pin_pull;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Enable asynchronous edge detection. */
-	bool enable_async_edge_detection;
+    /** Enable asynchronous edge detection. */
+    bool enable_async_edge_detection;
 #else
-	/** Wake up the device if the channel interrupt fires during sleep mode */
-	bool wake_if_sleeping;
+    /** Wake up the device if the channel interrupt fires during sleep mode */
+    bool wake_if_sleeping;
 #endif
-	/** Filter the raw input signal to prevent noise from triggering an
-	 *  interrupt accidentally, using a three sample majority filter */
-	bool filter_input_signal;
-	/** Edge detection mode to use */
-	enum extint_detect detection_criteria;
+    /** Filter the raw input signal to prevent noise from triggering an
+     *  interrupt accidentally, using a three sample majority filter */
+    bool filter_input_signal;
+    /** Edge detection mode to use */
+    enum extint_detect detection_criteria;
 };
 
 /**
@@ -310,9 +310,9 @@ struct extint_chan_conf {
  * \ref extint_disable_events().
  */
 struct extint_events {
-	/** If \c true, an event will be generated when an external interrupt
-	 *  channel detection state changes */
-	bool generate_event_on_detect[32 * EIC_INST_NUM];
+    /** If \c true, an event will be generated when an external interrupt
+     *  channel detection state changes */
+    bool generate_event_on_detect[32 * EIC_INST_NUM];
 };
 
 /**
@@ -322,22 +322,22 @@ struct extint_events {
  *  interrupt NMI channel.
  */
 struct extint_nmi_conf {
-	/** GPIO pin the NMI should be connected to */
-	uint32_t gpio_pin;
-	/** MUX position the GPIO pin should be configured to */
-	uint32_t gpio_pin_mux;
-	/** Internal pull to enable on the input pin */
-	enum extint_pull gpio_pin_pull;
-	/** Filter the raw input signal to prevent noise from triggering an
-	 *  interrupt accidentally, using a three sample majority filter */
-	bool filter_input_signal;
-	/** Edge detection mode to use. Not all devices support all possible
-	 *  detection modes for NMIs.
-	 */
-	enum extint_detect detection_criteria;
+    /** GPIO pin the NMI should be connected to */
+    uint32_t gpio_pin;
+    /** MUX position the GPIO pin should be configured to */
+    uint32_t gpio_pin_mux;
+    /** Internal pull to enable on the input pin */
+    enum extint_pull gpio_pin_pull;
+    /** Filter the raw input signal to prevent noise from triggering an
+     *  interrupt accidentally, using a three sample majority filter */
+    bool filter_input_signal;
+    /** Edge detection mode to use. Not all devices support all possible
+     *  detection modes for NMIs.
+     */
+    enum extint_detect detection_criteria;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Enable asynchronous edge detection. */
-	bool enable_async_edge_detection;
+    /** Enable asynchronous edge detection. */
+    bool enable_async_edge_detection;
 #endif
 };
 
@@ -357,11 +357,11 @@ typedef void (*extint_callback_t)(void);
 struct _extint_module
 {
 #  if EXTINT_CALLBACK_MODE == true
-	/** Asynchronous channel callback table, for user-registered handlers */
-	extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
+    /** Asynchronous channel callback table, for user-registered handlers */
+    extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS];
 #  else
-	/** Dummy value to ensure the struct has at least one member */
-	uint8_t _dummy;
+    /** Dummy value to ensure the struct has at least one member */
+    uint8_t _dummy;
 #  endif
 };
 
@@ -376,19 +376,20 @@ struct _extint_module
  * \return Base address of the associated EIC module.
  */
 static inline Eic * _extint_get_eic_from_channel(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	uint8_t eic_index = (channel / 32);
-
-	if (eic_index < EIC_INST_NUM) {
-		/* Array of available EICs */
-		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-		return eics[eic_index];
-	} else {
-		Assert(false);
-		return NULL;
-	}
+    uint8_t eic_index = (channel / 32);
+
+    if (eic_index < EIC_INST_NUM)
+    {
+        /* Array of available EICs */
+        Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+        return eics[eic_index];
+    } else {
+        Assert(false);
+        return NULL;
+    }
 }
 
 /**
@@ -402,19 +403,20 @@ static inline Eic * _extint_get_eic_from_channel(
  * \return Base address of the associated EIC module.
  */
 static inline Eic * _extint_get_eic_from_nmi(
-		const uint8_t nmi_channel)
+        const uint8_t nmi_channel)
 {
-	uint8_t eic_index = nmi_channel;
-
-	if (eic_index < EIC_INST_NUM) {
-		/* Array of available EICs */
-		Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-		return eics[eic_index];
-	} else {
-		Assert(false);
-		return NULL;
-	}
+    uint8_t eic_index = nmi_channel;
+
+    if (eic_index < EIC_INST_NUM)
+    {
+        /* Array of available EICs */
+        Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+        return eics[eic_index];
+    } else {
+        Assert(false);
+        return NULL;
+    }
 }
 #endif
 
@@ -423,10 +425,10 @@ static inline Eic * _extint_get_eic_from_nmi(
  */
 
 void extint_enable_events(
-		struct extint_events *const events);
+        struct extint_events *const events);
 
 void extint_disable_events(
-		struct extint_events *const events);
+        struct extint_events *const events);
 
 /** @} */
 
@@ -435,11 +437,11 @@ void extint_disable_events(
  */
 
 void extint_chan_get_config_defaults(
-		struct extint_chan_conf *const config);
+        struct extint_chan_conf *const config);
 
 void extint_chan_set_config(
-		const uint8_t channel,
-		const struct extint_chan_conf *const config);
+        const uint8_t channel,
+        const struct extint_chan_conf *const config);
 
 /** @} */
 
@@ -463,26 +465,26 @@ void extint_chan_set_config(
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void extint_nmi_get_config_defaults(
-		struct extint_nmi_conf *const config)
+        struct extint_nmi_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->gpio_pin            = 0;
-	config->gpio_pin_mux        = 0;
-	config->gpio_pin_pull       = EXTINT_PULL_UP;
-	config->filter_input_signal = false;
-	config->detection_criteria  = EXTINT_DETECT_FALLING;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->gpio_pin            = 0;
+    config->gpio_pin_mux        = 0;
+    config->gpio_pin_pull       = EXTINT_PULL_UP;
+    config->filter_input_signal = false;
+    config->detection_criteria  = EXTINT_DETECT_FALLING;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	 config->enable_async_edge_detection = false;
+     config->enable_async_edge_detection = false;
 #endif
 
 }
 
 enum status_code extint_nmi_set_config(
-		const uint8_t nmi_channel,
-		const struct extint_nmi_conf *const config);
+        const uint8_t nmi_channel,
+        const struct extint_nmi_conf *const config);
 
 /** @} */
 
@@ -503,12 +505,12 @@ enum status_code extint_nmi_set_config(
  *  \retval false  If the channel has not detected its configured criteria
  */
 static inline bool extint_chan_is_detected(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	Eic *const eic_module = _extint_get_eic_from_channel(channel);
-	uint32_t eic_mask   = (1UL << (channel % 32));
+    Eic *const eic_module = _extint_get_eic_from_channel(channel);
+    uint32_t eic_mask   = (1UL << (channel % 32));
 
-	return (eic_module->INTFLAG.reg & eic_mask);
+    return (eic_module->INTFLAG.reg & eic_mask);
 }
 
 /**
@@ -520,12 +522,12 @@ static inline bool extint_chan_is_detected(
  *  \param[in] channel  External Interrupt channel index to check
  */
 static inline void extint_chan_clear_detected(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	Eic *const eic_module = _extint_get_eic_from_channel(channel);
-	uint32_t eic_mask   = (1UL << (channel % 32));
+    Eic *const eic_module = _extint_get_eic_from_channel(channel);
+    uint32_t eic_mask   = (1UL << (channel % 32));
 
-	eic_module->INTFLAG.reg = eic_mask;
+    eic_module->INTFLAG.reg = eic_mask;
 }
 
 /** @} */
@@ -547,11 +549,11 @@ static inline void extint_chan_clear_detected(
  *  \retval false  If the NMI channel has not detected its configured criteria
  */
 static inline bool extint_nmi_is_detected(
-		const uint8_t nmi_channel)
+        const uint8_t nmi_channel)
 {
-	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+    Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
 
-	return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
+    return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI);
 }
 
 /**
@@ -563,11 +565,11 @@ static inline bool extint_nmi_is_detected(
  *  \param[in] nmi_channel  External Interrupt NMI channel index to check
  */
 static inline void extint_nmi_clear_detected(
-		const uint8_t nmi_channel)
+        const uint8_t nmi_channel)
 {
-	Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
+    Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel);
 
-	eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
+    eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c
index 52424d7863a7..4cdfd971d53c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.c
@@ -81,26 +81,29 @@ uint8_t _current_channel;
  *                                  registered, need unregister first
  */
 enum status_code extint_register_callback(
-	const extint_callback_t callback,
-	const uint8_t channel,
-	const enum extint_callback_type type)
+    const extint_callback_t callback,
+    const uint8_t channel,
+    const enum extint_callback_type type)
 {
-	/* Sanity check arguments */
-	Assert(callback);
-
-	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	if (_extint_dev.callbacks[channel] == NULL) {
-		_extint_dev.callbacks[channel] = callback;
-		return STATUS_OK;
-	} else if (_extint_dev.callbacks[channel] == callback) {
-		return STATUS_OK;
-	}
-
-	return STATUS_ERR_ALREADY_INITIALIZED;
+    /* Sanity check arguments */
+    Assert(callback);
+
+    if (type != EXTINT_CALLBACK_TYPE_DETECT)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    if (_extint_dev.callbacks[channel] == NULL)
+    {
+        _extint_dev.callbacks[channel] = callback;
+        return STATUS_OK;
+    } else if (_extint_dev.callbacks[channel] == callback)
+    {
+        return STATUS_OK;
+    }
+
+    return STATUS_ERR_ALREADY_INITIALIZED;
 }
 
 /**
@@ -120,24 +123,26 @@ enum status_code extint_register_callback(
  *                                 registration table
  */
 enum status_code extint_unregister_callback(
-	const extint_callback_t callback,
-	const uint8_t channel,
-	const enum extint_callback_type type)
+    const extint_callback_t callback,
+    const uint8_t channel,
+    const enum extint_callback_type type)
 {
-	/* Sanity check arguments */
-	Assert(callback);
-
-	if (type != EXTINT_CALLBACK_TYPE_DETECT) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	if (_extint_dev.callbacks[channel] == callback) {
-		_extint_dev.callbacks[channel] = NULL;
-		return STATUS_OK;
-	}
-
-	return STATUS_ERR_BAD_ADDRESS;
+    /* Sanity check arguments */
+    Assert(callback);
+
+    if (type != EXTINT_CALLBACK_TYPE_DETECT)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    if (_extint_dev.callbacks[channel] == callback)
+    {
+        _extint_dev.callbacks[channel] = NULL;
+        return STATUS_OK;
+    }
+
+    return STATUS_ERR_BAD_ADDRESS;
 }
 
 /**
@@ -155,20 +160,21 @@ enum status_code extint_unregister_callback(
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code extint_chan_enable_callback(
-	const uint8_t channel,
-	const enum extint_callback_type type)
+    const uint8_t channel,
+    const enum extint_callback_type type)
 {
-	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
-		Eic *const eic = _extint_get_eic_from_channel(channel);
-
-		eic->INTENSET.reg = (1UL << channel);
-	}
-	else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    if (type == EXTINT_CALLBACK_TYPE_DETECT)
+    {
+        Eic *const eic = _extint_get_eic_from_channel(channel);
+
+        eic->INTENSET.reg = (1UL << channel);
+    }
+    else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -185,20 +191,21 @@ enum status_code extint_chan_enable_callback(
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code extint_chan_disable_callback(
-	const uint8_t channel,
-	const enum extint_callback_type type)
+    const uint8_t channel,
+    const enum extint_callback_type type)
 {
-	if (type == EXTINT_CALLBACK_TYPE_DETECT) {
-		Eic *const eic = _extint_get_eic_from_channel(channel);
-
-		eic->INTENCLR.reg = (1UL << channel);
-	}
-	else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    if (type == EXTINT_CALLBACK_TYPE_DETECT)
+    {
+        Eic *const eic = _extint_get_eic_from_channel(channel);
+
+        eic->INTENCLR.reg = (1UL << channel);
+    }
+    else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -211,22 +218,25 @@ enum status_code extint_chan_disable_callback(
  */
 uint8_t extint_get_current_channel(void)
 {
-	return _current_channel;
+    return _current_channel;
 }
 
 /** Handler for the EXTINT hardware module interrupt. */
 void EIC_Handler(void)
 {
-	/* Find any triggered channels, run associated callback handlers */
-	for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) {
-		if (extint_chan_is_detected(_current_channel)) {
-			/* Clear flag */
-			extint_chan_clear_detected(_current_channel);
-			/* Find any associated callback entries in the callback table */
-			if (_extint_dev.callbacks[_current_channel] != NULL) {
-				/* Run the registered callback */
-				_extint_dev.callbacks[_current_channel]();
-			}
-		}
-	}
+    /* Find any triggered channels, run associated callback handlers */
+    for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++)
+    {
+        if (extint_chan_is_detected(_current_channel))
+        {
+            /* Clear flag */
+            extint_chan_clear_detected(_current_channel);
+            /* Find any associated callback entries in the callback table */
+            if (_extint_dev.callbacks[_current_channel] != NULL)
+            {
+                /* Run the registered callback */
+                _extint_dev.callbacks[_current_channel]();
+            }
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h
index 35cf23018554..e1e0289ae0e8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_callback.h
@@ -65,21 +65,21 @@ extern "C" {
 /** Enum for the possible callback types for the EXTINT module. */
 enum extint_callback_type
 {
-	/** Callback type for when an external interrupt detects the configured
-	 *  channel criteria (i.e. edge or level detection)
-	 */
-	EXTINT_CALLBACK_TYPE_DETECT,
+    /** Callback type for when an external interrupt detects the configured
+     *  channel criteria (i.e. edge or level detection)
+     */
+    EXTINT_CALLBACK_TYPE_DETECT,
 };
 
 enum status_code extint_register_callback(
-	const extint_callback_t callback,
-	const uint8_t channel,
-	const enum extint_callback_type type);
+    const extint_callback_t callback,
+    const uint8_t channel,
+    const enum extint_callback_type type);
 
 enum status_code extint_unregister_callback(
-	const extint_callback_t callback,
-	const uint8_t channel,
-	const enum extint_callback_type type);
+    const extint_callback_t callback,
+    const uint8_t channel,
+    const enum extint_callback_type type);
 
 uint8_t extint_get_current_channel(void);
 
@@ -90,12 +90,12 @@ uint8_t extint_get_current_channel(void);
  */
 
 enum status_code extint_chan_enable_callback(
-	const uint8_t channel,
-	const enum extint_callback_type type);
+    const uint8_t channel,
+    const enum extint_callback_type type);
 
 enum status_code extint_chan_disable_callback(
-	const uint8_t channel,
-	const enum extint_callback_type type);
+    const uint8_t channel,
+    const enum extint_callback_type type);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c
index 4fe9e8e695bb..47324a989a70 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_d_r_h/extint.c
@@ -71,10 +71,10 @@ struct _extint_module _extint_dev;
  * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
  */
 #define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
-		((filter_input_signal) ? true : (\
-			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
-			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
-			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+        ((filter_input_signal) ? true : (\
+            (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+            (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+            (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
 
 static void _extint_enable(void);
 static void _extint_disable(void);
@@ -95,14 +95,16 @@ static void _extint_disable(void);
  */
 static inline bool extint_is_syncing(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) {
-			return true;
-		}
-	}
-	return false;
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY)
+        {
+            return true;
+        }
+    }
+    return false;
 }
 /**
  * \internal
@@ -124,41 +126,44 @@ static inline bool extint_is_syncing(void)
 void _system_extint_init(void);
 void _system_extint_init(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC);
 
-	/* Configure the generic clock for the module and enable it */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
-	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+    /* Configure the generic clock for the module and enable it */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+    system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
 
-	/* Enable the clock anyway, since when needed it will be requested
-	 * by External Interrupt driver */
-	system_gclk_chan_enable(EIC_GCLK_ID);
+    /* Enable the clock anyway, since when needed it will be requested
+     * by External Interrupt driver */
+    system_gclk_chan_enable(EIC_GCLK_ID);
 
-	/* Reset all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
-	}
+    /* Reset all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRL.reg |= EIC_CTRL_SWRST;
+    }
 
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 
-	/* Reset the software module */
+    /* Reset the software module */
 #if EXTINT_CALLBACK_MODE == true
-	/* Clear callback registration table */
-	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
-		_extint_dev.callbacks[j] = NULL;
-	}
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+    /* Clear callback registration table */
+    for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++)
+    {
+        _extint_dev.callbacks[j] = NULL;
+    }
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
 #endif
 
-	/* Enables the driver for further use */
-	_extint_enable();
+    /* Enables the driver for further use */
+    _extint_enable();
 }
 
 /**
@@ -170,16 +175,18 @@ void _system_extint_init(void)
  */
 void _extint_enable(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Enable all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
-	}
-
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Enable all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRL.reg |= EIC_CTRL_ENABLE;
+    }
+
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /**
@@ -192,16 +199,18 @@ void _extint_enable(void)
  */
 void _extint_disable(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Disable all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
-	}
-
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Disable all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE;
+    }
+
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /**
@@ -221,18 +230,18 @@ void _extint_disable(void)
  * \param[out] config  Configuration structure to initialize to default values
  */
 void extint_chan_get_config_defaults(
-		struct extint_chan_conf *const config)
+        struct extint_chan_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->gpio_pin            = 0;
-	config->gpio_pin_mux        = 0;
-	config->gpio_pin_pull       = EXTINT_PULL_UP;
-	config->wake_if_sleeping    = true;
-	config->filter_input_signal = false;
-	config->detection_criteria  = EXTINT_DETECT_FALLING;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->gpio_pin            = 0;
+    config->gpio_pin_mux        = 0;
+    config->gpio_pin_pull       = EXTINT_PULL_UP;
+    config->wake_if_sleeping    = true;
+    config->filter_input_signal = false;
+    config->detection_criteria  = EXTINT_DETECT_FALLING;
 }
 
 /**
@@ -247,50 +256,52 @@ void extint_chan_get_config_defaults(
 
  */
 void extint_chan_set_config(
-		const uint8_t channel,
-		const struct extint_chan_conf *const config)
+        const uint8_t channel,
+        const struct extint_chan_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-	/* Sanity check clock requirements */
-	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
-		_extint_is_gclk_required(config->filter_input_signal,
-			config->detection_criteria)));
-
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
-
-	pinmux_config.mux_position = config->gpio_pin_mux;
-	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
-	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
-
-	/* Get a pointer to the module hardware instance */
-	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
-
-	uint32_t config_pos = (4 * (channel % 8));
-	uint32_t new_config;
-
-	/* Determine the channel's new edge detection configuration */
-	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
-
-	/* Enable the hardware signal filter if requested in the config */
-	if (config->filter_input_signal) {
-		new_config |= EIC_CONFIG_FILTEN0;
-	}
-
-	/* Clear the existing and set the new channel configuration */
-	EIC_module->CONFIG[channel / 8].reg
-		= (EIC_module->CONFIG[channel / 8].reg &
-			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
-			(new_config << config_pos);
-
-	/* Set the channel's new wake up mode setting */
-	if (config->wake_if_sleeping) {
-		EIC_module->WAKEUP.reg |=  (1UL << channel);
-	} else {
-		EIC_module->WAKEUP.reg &= ~(1UL << channel);
-	}
+    /* Sanity check arguments */
+    Assert(config);
+    /* Sanity check clock requirements */
+    Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+        _extint_is_gclk_required(config->filter_input_signal,
+            config->detection_criteria)));
+
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
+
+    pinmux_config.mux_position = config->gpio_pin_mux;
+    pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+    system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+    /* Get a pointer to the module hardware instance */
+    Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+    uint32_t config_pos = (4 * (channel % 8));
+    uint32_t new_config;
+
+    /* Determine the channel's new edge detection configuration */
+    new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+    /* Enable the hardware signal filter if requested in the config */
+    if (config->filter_input_signal)
+    {
+        new_config |= EIC_CONFIG_FILTEN0;
+    }
+
+    /* Clear the existing and set the new channel configuration */
+    EIC_module->CONFIG[channel / 8].reg
+        = (EIC_module->CONFIG[channel / 8].reg &
+            ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+            (new_config << config_pos);
+
+    /* Set the channel's new wake up mode setting */
+    if (config->wake_if_sleeping)
+    {
+        EIC_module->WAKEUP.reg |=  (1UL << channel);
+    } else {
+        EIC_module->WAKEUP.reg &= ~(1UL << channel);
+    }
 }
 
 /**
@@ -309,49 +320,50 @@ void extint_chan_set_config(
  * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
  */
 enum status_code extint_nmi_set_config(
-		const uint8_t nmi_channel,
-		const struct extint_nmi_conf *const config)
+        const uint8_t nmi_channel,
+        const struct extint_nmi_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-	/* Sanity check clock requirements */
-	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
-		_extint_is_gclk_required(config->filter_input_signal,
-			config->detection_criteria)));
+    /* Sanity check arguments */
+    Assert(config);
+    /* Sanity check clock requirements */
+    Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+        _extint_is_gclk_required(config->filter_input_signal,
+            config->detection_criteria)));
 
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
 
-	pinmux_config.mux_position = config->gpio_pin_mux;
-	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
-	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+    pinmux_config.mux_position = config->gpio_pin_mux;
+    pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+    system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
 
-	/* Get a pointer to the module hardware instance */
-	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+    /* Get a pointer to the module hardware instance */
+    Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
 
-	uint32_t new_config;
+    uint32_t new_config;
 
-	/* Determine the NMI's new edge detection configuration */
-	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+    /* Determine the NMI's new edge detection configuration */
+    new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
 
-	/* Enable the hardware signal filter if requested in the config */
-	if (config->filter_input_signal) {
-		new_config |= EIC_NMICTRL_NMIFILTEN;
-	}
+    /* Enable the hardware signal filter if requested in the config */
+    if (config->filter_input_signal)
+    {
+        new_config |= EIC_NMICTRL_NMIFILTEN;
+    }
 
-	/* Disable EIC and general clock to configure NMI */
-	_extint_disable();
-	system_gclk_chan_disable(EIC_GCLK_ID);
+    /* Disable EIC and general clock to configure NMI */
+    _extint_disable();
+    system_gclk_chan_disable(EIC_GCLK_ID);
 
-	EIC_module->NMICTRL.reg = new_config;
+    EIC_module->NMICTRL.reg = new_config;
 
-	/* Enable the general clock and EIC after configure NMI */
-	system_gclk_chan_enable(EIC_GCLK_ID);
-	_extint_enable();
+    /* Enable the general clock and EIC after configure NMI */
+    system_gclk_chan_enable(EIC_GCLK_ID);
+    _extint_enable();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -365,28 +377,31 @@ enum status_code extint_nmi_set_config(
  *  \param[in] events    Struct containing flags of events to enable
  */
 void extint_enable_events(
-		struct extint_events *const events)
+        struct extint_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
-
-	/* Array of available EICs. */
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Update the event control register for each physical EIC instance */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		uint32_t event_mask = 0;
-
-		/* Create an enable mask for the current EIC module */
-		for (uint32_t j = 0; j < 32; j++) {
-			if (events->generate_event_on_detect[(32 * i) + j]) {
-				event_mask |= (1UL << j);
-			}
-		}
-
-		/* Enable the masked events */
-		eics[i]->EVCTRL.reg |= event_mask;
-	}
+    /* Sanity check arguments */
+    Assert(events);
+
+    /* Array of available EICs. */
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Update the event control register for each physical EIC instance */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        uint32_t event_mask = 0;
+
+        /* Create an enable mask for the current EIC module */
+        for (uint32_t j = 0; j < 32; j++)
+        {
+            if (events->generate_event_on_detect[(32 * i) + j])
+            {
+                event_mask |= (1UL << j);
+            }
+        }
+
+        /* Enable the masked events */
+        eics[i]->EVCTRL.reg |= event_mask;
+    }
 }
 
 /**
@@ -400,26 +415,29 @@ void extint_enable_events(
  *  \param[in] events    Struct containing flags of events to disable
  */
 void extint_disable_events(
-		struct extint_events *const events)
+        struct extint_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
-
-	/* Array of available EICs. */
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Update the event control register for each physical EIC instance */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		uint32_t event_mask = 0;
-
-		/* Create a disable mask for the current EIC module */
-		for (uint32_t j = 0; j < 32; j++) {
-			if (events->generate_event_on_detect[(32 * i) + j]) {
-				event_mask |= (1UL << j);
-			}
-		}
-
-		/* Disable the masked events */
-		eics[i]->EVCTRL.reg &= ~event_mask;
-	}
+    /* Sanity check arguments */
+    Assert(events);
+
+    /* Array of available EICs. */
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Update the event control register for each physical EIC instance */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        uint32_t event_mask = 0;
+
+        /* Create a disable mask for the current EIC module */
+        for (uint32_t j = 0; j < 32; j++)
+        {
+            if (events->generate_event_on_detect[(32 * i) + j])
+            {
+                event_mask |= (1UL << j);
+            }
+        }
+
+        /* Disable the masked events */
+        eics[i]->EVCTRL.reg &= ~event_mask;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c
index 1f5236222e05..4a2a43fc181b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/extint_sam_l_c/extint.c
@@ -83,10 +83,10 @@ struct _extint_module _extint_dev;
  * \param[in] detection_criteria  Edge detection mode to use (\ref extint_detect)
  */
 #define _extint_is_gclk_required(filter_input_signal, detection_criteria) \
-		((filter_input_signal) ? true : (\
-			(EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
-			(EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
-			(EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
+        ((filter_input_signal) ? true : (\
+            (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\
+            (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\
+            (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false))))
 
 static void _extint_enable(void);
 static void _extint_disable(void);
@@ -107,15 +107,17 @@ static void _extint_disable(void);
  */
 static inline bool extint_is_syncing(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE)
-		 || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)){
-			return true;
-		}
-	}
-	return false;
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE)
+         || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST))
+         {
+            return true;
+        }
+    }
+    return false;
 }
 
 /**
@@ -138,53 +140,58 @@ static inline bool extint_is_syncing(void)
 void _system_extint_init(void);
 void _system_extint_init(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC);
 
 #if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
-	/* Configure the generic clock for the module and enable it */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
-	system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
-
-	/* Enable the clock anyway, since when needed it will be requested
-	 * by External Interrupt driver */
-	system_gclk_chan_enable(EIC_GCLK_ID);
+    /* Configure the generic clock for the module and enable it */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE;
+    system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf);
+
+    /* Enable the clock anyway, since when needed it will be requested
+     * by External Interrupt driver */
+    system_gclk_chan_enable(EIC_GCLK_ID);
 #endif
 
-	/* Reset all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST;
-	}
+    /* Reset all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST;
+    }
 
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 
 #if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
-	}
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+    }
 #else
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
-	}
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+    }
 #endif
 
-	/* Reset the software module */
+    /* Reset the software module */
 #if EXTINT_CALLBACK_MODE == true
-	/* Clear callback registration table */
-	for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) {
-		_extint_dev.callbacks[j] = NULL;
-	}
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
+    /* Clear callback registration table */
+    for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++)
+    {
+        _extint_dev.callbacks[j] = NULL;
+    }
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC);
 #endif
 
-	/* Enables the driver for further use */
-	_extint_enable();
+    /* Enables the driver for further use */
+    _extint_enable();
 }
 
 /**
@@ -196,16 +203,18 @@ void _system_extint_init(void)
  */
 void _extint_enable(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Enable all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE;
-	}
-
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Enable all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE;
+    }
+
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /**
@@ -218,16 +227,18 @@ void _extint_enable(void)
  */
 void _extint_disable(void)
 {
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	/* Disable all EIC hardware modules. */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
-	}
-
-	while (extint_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    /* Disable all EIC hardware modules. */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE;
+    }
+
+    while (extint_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /**
@@ -247,18 +258,18 @@ void _extint_disable(void)
  * \param[out] config  Configuration structure to initialize to default values
  */
 void extint_chan_get_config_defaults(
-		struct extint_chan_conf *const config)
+        struct extint_chan_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->gpio_pin            = 0;
-	config->gpio_pin_mux        = 0;
-	config->gpio_pin_pull       = EXTINT_PULL_UP;
-	config->filter_input_signal = false;
-	config->detection_criteria  = EXTINT_DETECT_FALLING;
-	config->enable_async_edge_detection = false;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->gpio_pin            = 0;
+    config->gpio_pin_mux        = 0;
+    config->gpio_pin_pull       = EXTINT_PULL_UP;
+    config->filter_input_signal = false;
+    config->detection_criteria  = EXTINT_DETECT_FALLING;
+    config->enable_async_edge_detection = false;
 }
 
 /**
@@ -273,62 +284,65 @@ void extint_chan_get_config_defaults(
 
  */
 void extint_chan_set_config(
-		const uint8_t channel,
-		const struct extint_chan_conf *const config)
+        const uint8_t channel,
+        const struct extint_chan_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-	_extint_disable();
+    /* Sanity check arguments */
+    Assert(config);
+    _extint_disable();
 #if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
-	/* Sanity check clock requirements */
-	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
-		_extint_is_gclk_required(config->filter_input_signal,
-			config->detection_criteria)));
+    /* Sanity check clock requirements */
+    Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+        _extint_is_gclk_required(config->filter_input_signal,
+            config->detection_criteria)));
 #endif
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
-
-	pinmux_config.mux_position = config->gpio_pin_mux;
-	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
-	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
-
-	/* Get a pointer to the module hardware instance */
-	Eic *const EIC_module = _extint_get_eic_from_channel(channel);
-
-	uint32_t config_pos = (4 * (channel % 8));
-	uint32_t new_config;
-
-	/* Determine the channel's new edge detection configuration */
-	new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
-
-	/* Enable the hardware signal filter if requested in the config */
-	if (config->filter_input_signal) {
-		new_config |= EIC_CONFIG_FILTEN0;
-	}
-
-	/* Clear the existing and set the new channel configuration */
-	EIC_module->CONFIG[channel / 8].reg
-		= (EIC_module->CONFIG[channel / 8].reg &
-			~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
-			(new_config << config_pos);
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
+
+    pinmux_config.mux_position = config->gpio_pin_mux;
+    pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+    system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+
+    /* Get a pointer to the module hardware instance */
+    Eic *const EIC_module = _extint_get_eic_from_channel(channel);
+
+    uint32_t config_pos = (4 * (channel % 8));
+    uint32_t new_config;
+
+    /* Determine the channel's new edge detection configuration */
+    new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos);
+
+    /* Enable the hardware signal filter if requested in the config */
+    if (config->filter_input_signal)
+    {
+        new_config |= EIC_CONFIG_FILTEN0;
+    }
+
+    /* Clear the existing and set the new channel configuration */
+    EIC_module->CONFIG[channel / 8].reg
+        = (EIC_module->CONFIG[channel / 8].reg &
+            ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) |
+            (new_config << config_pos);
 #if (SAML22) || (SAML21XXXB) || (SAMC20) || (SAMR30)
-	/* Config asynchronous edge detection */
-	if (config->enable_async_edge_detection) {
-		EIC_module->ASYNCH.reg |= (1UL << channel);
-	} else {
-		EIC_module->ASYNCH.reg &= (EIC_ASYNCH_MASK & (~(1UL << channel)));
-	}
+    /* Config asynchronous edge detection */
+    if (config->enable_async_edge_detection)
+    {
+        EIC_module->ASYNCH.reg |= (1UL << channel);
+    } else {
+        EIC_module->ASYNCH.reg &= (EIC_ASYNCH_MASK & (~(1UL << channel)));
+    }
 #endif
 #if (SAMC21)
-	/* Config asynchronous edge detection */
-	if (config->enable_async_edge_detection) {
-		EIC_module->EIC_ASYNCH.reg |= (1UL << channel);
-	} else {
-		EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel)));
-	}
+    /* Config asynchronous edge detection */
+    if (config->enable_async_edge_detection)
+    {
+        EIC_module->EIC_ASYNCH.reg |= (1UL << channel);
+    } else {
+        EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel)));
+    }
 #endif
-	_extint_enable();
+    _extint_enable();
 }
 
 /**
@@ -347,71 +361,75 @@ void extint_chan_set_config(
  * \retval  STATUS_ERR_BAD_FORMAT       An invalid detection mode was requested
  */
 enum status_code extint_nmi_set_config(
-		const uint8_t nmi_channel,
-		const struct extint_nmi_conf *const config)
+        const uint8_t nmi_channel,
+        const struct extint_nmi_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Sanity check clock requirements */
-	Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
-		_extint_is_gclk_required(config->filter_input_signal,
-			config->detection_criteria)));
+    /* Sanity check clock requirements */
+    Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) &&
+        _extint_is_gclk_required(config->filter_input_signal,
+            config->detection_criteria)));
 
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
 
-	pinmux_config.mux_position = config->gpio_pin_mux;
-	pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
-	system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
+    pinmux_config.mux_position = config->gpio_pin_mux;
+    pinmux_config.direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pinmux_config.input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->gpio_pin_pull;
+    system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config);
 
-	/* Get a pointer to the module hardware instance */
-	Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
+    /* Get a pointer to the module hardware instance */
+    Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel);
 
-	uint32_t new_config;
+    uint32_t new_config;
 
-	/* Determine the NMI's new edge detection configuration */
-	new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
+    /* Determine the NMI's new edge detection configuration */
+    new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos);
 
-	/* Enable the hardware signal filter if requested in the config */
-	if (config->filter_input_signal) {
-		new_config |= EIC_NMICTRL_NMIFILTEN;
-	}
+    /* Enable the hardware signal filter if requested in the config */
+    if (config->filter_input_signal)
+    {
+        new_config |= EIC_NMICTRL_NMIFILTEN;
+    }
 
 #if (SAML21XXXB) || (SAML22) || (SAMC21) || (SAMR30)
-	/* Enable asynchronous edge detection if requested in the config */
-	if (config->enable_async_edge_detection) {
-		new_config |= EIC_NMICTRL_NMIASYNCH;
-	}
+    /* Enable asynchronous edge detection if requested in the config */
+    if (config->enable_async_edge_detection)
+    {
+        new_config |= EIC_NMICTRL_NMIASYNCH;
+    }
 #endif
-	
-	/* Disable EIC and general clock to configure NMI */
-	_extint_disable();
+
+    /* Disable EIC and general clock to configure NMI */
+    _extint_disable();
 #if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
-	system_gclk_chan_disable(EIC_GCLK_ID);
+    system_gclk_chan_disable(EIC_GCLK_ID);
 #else
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
-		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
-		system_gclk_chan_disable(EIC_GCLK_ID);
-	}
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK;
+        system_gclk_chan_disable(EIC_GCLK_ID);
+    }
 #endif
 
-	EIC_module->NMICTRL.reg = new_config;
+    EIC_module->NMICTRL.reg = new_config;
 
-	/* Enable the EIC clock and EIC after configure NMI */
+    /* Enable the EIC clock and EIC after configure NMI */
 #if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK)
-	system_gclk_chan_enable(EIC_GCLK_ID);
+    system_gclk_chan_enable(EIC_GCLK_ID);
 #else
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++){
-		eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
-	}
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K;
+    }
 #endif
-	_extint_enable();
+    _extint_enable();
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -425,31 +443,34 @@ enum status_code extint_nmi_set_config(
  *  \param[in] events    Struct containing flags of events to enable
  */
 void extint_enable_events(
-		struct extint_events *const events)
+        struct extint_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
-
-	/* Array of available EICs. */
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	_extint_disable();
-
-	/* Update the event control register for each physical EIC instance */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		uint32_t event_mask = 0;
-
-		/* Create an enable mask for the current EIC module */
-		for (uint32_t j = 0; j < 32; j++) {
-			if (events->generate_event_on_detect[(32 * i) + j]) {
-				event_mask |= (1UL << j);
-			}
-		}
-
-		/* Enable the masked events */
-		eics[i]->EVCTRL.reg |= event_mask;
-	}
-	_extint_enable();
+    /* Sanity check arguments */
+    Assert(events);
+
+    /* Array of available EICs. */
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    _extint_disable();
+
+    /* Update the event control register for each physical EIC instance */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        uint32_t event_mask = 0;
+
+        /* Create an enable mask for the current EIC module */
+        for (uint32_t j = 0; j < 32; j++)
+        {
+            if (events->generate_event_on_detect[(32 * i) + j])
+            {
+                event_mask |= (1UL << j);
+            }
+        }
+
+        /* Enable the masked events */
+        eics[i]->EVCTRL.reg |= event_mask;
+    }
+    _extint_enable();
 }
 
 /**
@@ -463,29 +484,32 @@ void extint_enable_events(
  *  \param[in] events    Struct containing flags of events to disable
  */
 void extint_disable_events(
-		struct extint_events *const events)
+        struct extint_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
-
-	/* Array of available EICs. */
-	Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
-
-	_extint_disable();
-
-	/* Update the event control register for each physical EIC instance */
-	for (uint32_t i = 0; i < EIC_INST_NUM; i++) {
-		uint32_t event_mask = 0;
-
-		/* Create a disable mask for the current EIC module */
-		for (uint32_t j = 0; j < 32; j++) {
-			if (events->generate_event_on_detect[(32 * i) + j]) {
-				event_mask |= (1UL << j);
-			}
-		}
-
-		/* Disable the masked events */
-		eics[i]->EVCTRL.reg &= ~event_mask;
-	}
-	_extint_enable();
+    /* Sanity check arguments */
+    Assert(events);
+
+    /* Array of available EICs. */
+    Eic *const eics[EIC_INST_NUM] = EIC_INSTS;
+
+    _extint_disable();
+
+    /* Update the event control register for each physical EIC instance */
+    for (uint32_t i = 0; i < EIC_INST_NUM; i++)
+    {
+        uint32_t event_mask = 0;
+
+        /* Create a disable mask for the current EIC module */
+        for (uint32_t j = 0; j < 32; j++)
+        {
+            if (events->generate_event_on_detect[(32 * i) + j])
+            {
+                event_mask |= (1UL << j);
+            }
+        }
+
+        /* Disable the masked events */
+        eics[i]->EVCTRL.reg &= ~event_mask;
+    }
+    _extint_enable();
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h
index fd8611ec1a2e..6dc3c428b0e1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/extint/module_config/conf_extint.h
@@ -46,7 +46,7 @@
 #ifndef CONF_EXTINT_H_INCLUDED
 #define CONF_EXTINT_H_INCLUDED
 
-/** 
+/**
  * Define which clock type is used to clock EIC peripheral:
  *     - EXTINT_CLK_GCLK
  *     - EXTINT_CLK_ULP32K
@@ -54,7 +54,7 @@
  * EXTINT_CLK_ULP32K is available for SAM L21/C21.
  */
 #define EXTINT_CLOCK_SELECTION   EXTINT_CLK_GCLK
- 
+
 /**
  * Define which GCLK source is used when selecting EXTINT_CLK_GCLK type.
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c
index 7eb58f481842..22275bc94fa0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.c
@@ -66,55 +66,57 @@
  * \retval STATUS_OK           The module was initialized successfully
  */
 enum status_code freqm_init(
-		struct freqm_module *const module_inst,
-		Freqm *const hw,
-		struct freqm_config *const config)
+        struct freqm_module *const module_inst,
+        Freqm *const hw,
+        struct freqm_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
-	Assert(config->ref_clock_circles);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
+    Assert(config->ref_clock_circles);
 
-	/* Initialize device instance */
-	module_inst->hw = hw;
+    /* Initialize device instance */
+    module_inst->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_FREQM);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_FREQM);
 
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->msr_clock_source;
-	system_gclk_chan_set_config(FREQM_GCLK_ID_MSR, &gclk_chan_conf);
-	system_gclk_chan_enable(FREQM_GCLK_ID_MSR);
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->msr_clock_source;
+    system_gclk_chan_set_config(FREQM_GCLK_ID_MSR, &gclk_chan_conf);
+    system_gclk_chan_enable(FREQM_GCLK_ID_MSR);
 
-	gclk_chan_conf.source_generator = config->ref_clock_source;
-	system_gclk_chan_set_config(FREQM_GCLK_ID_REF, &gclk_chan_conf);
-	system_gclk_chan_enable(FREQM_GCLK_ID_REF);
-	
-	module_inst->ref_clock_freq = system_gclk_gen_get_hz(config->ref_clock_source);
+    gclk_chan_conf.source_generator = config->ref_clock_source;
+    system_gclk_chan_set_config(FREQM_GCLK_ID_REF, &gclk_chan_conf);
+    system_gclk_chan_enable(FREQM_GCLK_ID_REF);
 
-	/* Perform a software reset */
-	hw->CTRLA.reg = FREQM_CTRLA_SWRST;
+    module_inst->ref_clock_freq = system_gclk_gen_get_hz(config->ref_clock_source);
 
-	while (freqm_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    /* Perform a software reset */
+    hw->CTRLA.reg = FREQM_CTRLA_SWRST;
 
-	/* Initialize the FREQM with new configurations */
-	hw->CFGA.reg = config->ref_clock_circles;
+    while (freqm_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    /* Initialize the FREQM with new configurations */
+    hw->CFGA.reg = config->ref_clock_circles;
 
 #if FREQM_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < FREQM_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	}
-	/* Register this instance for callbacks*/
-	_freqm_instance = module_inst;
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < FREQM_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    }
+    /* Register this instance for callbacks*/
+    _freqm_instance = module_inst;
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -129,35 +131,37 @@ enum status_code freqm_init(
  * \retval FREQM_STATUS_MEASURE_DONE   Measurement result was retrieved successfully
  * \retval FREQM_STATUS_MEASURE_BUSY   Measurement result was not ready
  * \retval FREQM_STATUS_CNT_OVERFLOW   Measurement result was overflow
- *                              
+ *
  * \note If overflow occurred, configure faster reference clock or reduce reference clock cycles.
  */
 enum freqm_status freqm_get_result_value(
-		struct freqm_module *const module_inst, uint32_t *result)
+        struct freqm_module *const module_inst, uint32_t *result)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(result);
-
-	Freqm *const freqm_hw = module_inst->hw;
-	uint32_t result_cal;
-	*result = result_cal= 0;
-
-	if (freqm_hw->STATUS.reg & FREQM_STATUS_BUSY) {
-		/* Result not ready */
-		return FREQM_STATUS_MEASURE_BUSY;
-	} else {
-		if (freqm_hw->STATUS.reg & FREQM_STATUS_OVF) {
-			/* Overflow */
-			return FREQM_STATUS_CNT_OVERFLOW;
-		} else {
-			/* Get measurement output data (it will clear data done flag) */
-			result_cal = freqm_hw->VALUE.reg;
-			freqm_hw->INTFLAG.reg = FREQM_INTFLAG_DONE;
-
-			*result = result_cal * module_inst->ref_clock_freq / freqm_hw->CFGA.reg;
-			return FREQM_STATUS_MEASURE_DONE;
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(result);
+
+    Freqm *const freqm_hw = module_inst->hw;
+    uint32_t result_cal;
+    *result = result_cal= 0;
+
+    if (freqm_hw->STATUS.reg & FREQM_STATUS_BUSY)
+    {
+        /* Result not ready */
+        return FREQM_STATUS_MEASURE_BUSY;
+    } else {
+        if (freqm_hw->STATUS.reg & FREQM_STATUS_OVF)
+        {
+            /* Overflow */
+            return FREQM_STATUS_CNT_OVERFLOW;
+        } else {
+            /* Get measurement output data (it will clear data done flag) */
+            result_cal = freqm_hw->VALUE.reg;
+            freqm_hw->INTFLAG.reg = FREQM_INTFLAG_DONE;
+
+            *result = result_cal * module_inst->ref_clock_freq / freqm_hw->CFGA.reg;
+            return FREQM_STATUS_MEASURE_DONE;
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h
index de97b009739d..98f648906653 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm.h
@@ -138,11 +138,11 @@ typedef void (*freqm_callback_t)(void);
 
 /** Enum for possible callback types for the FREQM module. */
 enum freqm_callback {
-	/** Callback for measurement done */
-	FREQM_CALLBACK_DONE = 0,
-	/** Number of available callbacks */
+    /** Callback for measurement done */
+    FREQM_CALLBACK_DONE = 0,
+    /** Number of available callbacks */
 #if !defined(__DOXYGEN__)
-	FREQM_CALLBACK_N,
+    FREQM_CALLBACK_N,
 #endif
 };
 #endif
@@ -158,25 +158,25 @@ enum freqm_callback {
  */
 struct freqm_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware module pointer of the associated FREQM peripheral */
-	Freqm *hw;
-	/** The frequency of reference clock in Hz*/
-	uint32_t ref_clock_freq;
+    /** Hardware module pointer of the associated FREQM peripheral */
+    Freqm *hw;
+    /** The frequency of reference clock in Hz*/
+    uint32_t ref_clock_freq;
 #  if FREQM_CALLBACK_MODE == true
-	/** Array of callbacks */
-	freqm_callback_t callback[FREQM_CALLBACK_N];
+    /** Array of callbacks */
+    freqm_callback_t callback[FREQM_CALLBACK_N];
 #  endif
 #endif
 };
 
 /** Enum for the possible status types for the FREQM module. */
 enum freqm_status {
-	/** FREQM measurement is finish */
-	FREQM_STATUS_MEASURE_DONE =  0,
-	/** FREQM measurement is ongoing or not */
-	FREQM_STATUS_MEASURE_BUSY =  1,
-	/** FREQM sticky count value overflow */
-	FREQM_STATUS_CNT_OVERFLOW =  2,
+    /** FREQM measurement is finish */
+    FREQM_STATUS_MEASURE_DONE =  0,
+    /** FREQM measurement is ongoing or not */
+    FREQM_STATUS_MEASURE_BUSY =  1,
+    /** FREQM sticky count value overflow */
+    FREQM_STATUS_CNT_OVERFLOW =  2,
 };
 
 /**
@@ -185,12 +185,12 @@ enum freqm_status {
  *  Configuration structure for a Frequency Meter.
  */
 struct freqm_config {
-	/** GCLK source select for measurement */
-	enum gclk_generator msr_clock_source;
-	/** GCLK source select for reference */
-	enum gclk_generator ref_clock_source;
-	/** Measurement duration in number of reference clock cycles. Range 1~255 */
-	uint16_t ref_clock_circles;
+    /** GCLK source select for measurement */
+    enum gclk_generator msr_clock_source;
+    /** GCLK source select for reference */
+    enum gclk_generator ref_clock_source;
+    /** Measurement duration in number of reference clock cycles. Range 1~255 */
+    uint16_t ref_clock_circles;
 };
 
 /**
@@ -209,13 +209,14 @@ struct freqm_config {
  */
 static inline bool freqm_is_syncing(void)
 {
-	Freqm *const freqm_module = FREQM;
+    Freqm *const freqm_module = FREQM;
 
-	if (freqm_module->SYNCBUSY.reg) {
-		return true;
-	}
+    if (freqm_module->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -223,9 +224,9 @@ static inline bool freqm_is_syncing(void)
  * @{
  */
 enum status_code freqm_init(
-		struct freqm_module *const module_inst,
-		Freqm *const hw,
-		struct freqm_config *const config);
+        struct freqm_module *const module_inst,
+        Freqm *const hw,
+        struct freqm_config *const config);
 
 /**
  * \brief Initializes all members of a FREQM configuration structure
@@ -244,15 +245,15 @@ enum status_code freqm_init(
  *  \param[in] config  Configuration structure to initialize to default values
  */
 static inline void freqm_get_config_defaults(
-		struct freqm_config *const config)
+        struct freqm_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->msr_clock_source = GCLK_GENERATOR_0;
-	config->ref_clock_source = GCLK_GENERATOR_1;
-	config->ref_clock_circles = 127;
+    /* Default configuration values */
+    config->msr_clock_source = GCLK_GENERATOR_0;
+    config->ref_clock_source = GCLK_GENERATOR_1;
+    config->ref_clock_circles = 127;
 }
 
 /**
@@ -264,20 +265,21 @@ static inline void freqm_get_config_defaults(
  * \param[in] module_inst  Software instance for the Frequency Meter peripheral
  */
 static inline void freqm_enable(
-		struct freqm_module *const module_inst)
+        struct freqm_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Freqm *const freqm_module = module_inst->hw;
+    Freqm *const freqm_module = module_inst->hw;
 
-	/* Enable FREQM */
-	freqm_module->CTRLA.reg |= FREQM_CTRLA_ENABLE;
+    /* Enable FREQM */
+    freqm_module->CTRLA.reg |= FREQM_CTRLA_ENABLE;
 
-	while (freqm_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    while (freqm_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /**
@@ -289,25 +291,26 @@ static inline void freqm_enable(
  * \param[in] module_inst  Software instance for the Frequency Meter peripheral
  */
 static inline void freqm_disable(
-		struct freqm_module *const module_inst)
+        struct freqm_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Freqm *const freqm_module = module_inst->hw;
+    Freqm *const freqm_module = module_inst->hw;
 
-	/* Disbale interrupt */
-	freqm_module->INTENCLR.reg = FREQM_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	freqm_module->INTFLAG.reg = FREQM_INTFLAG_MASK;
+    /* Disbale interrupt */
+    freqm_module->INTENCLR.reg = FREQM_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    freqm_module->INTFLAG.reg = FREQM_INTFLAG_MASK;
 
-	/* Disable FREQM */
-	freqm_module->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
+    /* Disable FREQM */
+    freqm_module->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
 
-	while (freqm_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    while (freqm_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
 
 /** @} */
@@ -323,12 +326,12 @@ static inline void freqm_disable(
  */
 static inline void freqm_start_measure(struct freqm_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Trigger measurement */
-	module->hw->CTRLB.reg |= FREQM_CTRLB_START;
+    /* Trigger measurement */
+    module->hw->CTRLB.reg |= FREQM_CTRLB_START;
 }
 
 /**
@@ -340,16 +343,16 @@ static inline void freqm_start_measure(struct freqm_module *const module)
  */
 static inline void freqm_clear_overflow(struct freqm_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Clear overflow flag */
-	module->hw->STATUS.reg = FREQM_STATUS_OVF;
+    /* Clear overflow flag */
+    module->hw->STATUS.reg = FREQM_STATUS_OVF;
 }
 
 enum freqm_status freqm_get_result_value(
-		struct freqm_module *const module_inst, uint32_t *result);
+        struct freqm_module *const module_inst, uint32_t *result);
 
 /** @} */
 
@@ -367,14 +370,14 @@ enum freqm_status freqm_get_result_value(
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>FREQM</td>
- *		<td>Frequency Meter</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>FREQM</td>
+ *      <td>Frequency Meter</td>
+ *  </tr>
  * </table>
  *
  *
@@ -393,12 +396,12 @@ enum freqm_status freqm_get_result_value(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -419,16 +422,16 @@ enum freqm_status freqm_get_result_value(
  * \page asfdoc_sam0_freqm_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42506A</td>
- *		<td>08/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42506A</td>
+ *      <td>08/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c
index 7de2ee3215d0..d12a933bcf9b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.c
@@ -72,22 +72,23 @@ struct freqm_module *_freqm_instance;
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code freqm_register_callback(
-		struct freqm_module *const module,
-		freqm_callback_t callback_func,
-		enum freqm_callback callback_type)
+        struct freqm_module *const module,
+        freqm_callback_t callback_func,
+        enum freqm_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
-
-	if (callback_type >= FREQM_CALLBACK_TYPE_NUM) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
+
+    if (callback_type >= FREQM_CALLBACK_TYPE_NUM)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
+
+    return STATUS_OK;
 }
 
 /**
@@ -102,20 +103,21 @@ enum status_code freqm_register_callback(
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code freqm_unregister_callback(
-		struct freqm_module *module,
-		enum freqm_callback callback_type)
+        struct freqm_module *module,
+        enum freqm_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	if (callback_type >= FREQM_CALLBACK_TYPE_NUM) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+
+    if (callback_type >= FREQM_CALLBACK_TYPE_NUM)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
+
+    return STATUS_OK;
 }
 
 
@@ -125,18 +127,20 @@ enum status_code freqm_unregister_callback(
 */
 void FREQM_Handler(void)
 {
-	/* Get device instance from the look-up table */
-	struct freqm_module *module = _freqm_instance;
-
-	/* Read and mask interrupt flag register */
-	uint32_t status = FREQM->INTFLAG.reg;
-
-	/* Check if data ready needs to be serviced */
-	if (status & FREQM_INTFLAG_DONE) {
-		if (module->callback[FREQM_CALLBACK_MEASURE_DONE]) {
-			FREQM->INTFLAG.reg = FREQM_INTFLAG_DONE;
-			module->callback[FREQM_CALLBACK_MEASURE_DONE]();
-		}
-	}
+    /* Get device instance from the look-up table */
+    struct freqm_module *module = _freqm_instance;
+
+    /* Read and mask interrupt flag register */
+    uint32_t status = FREQM->INTFLAG.reg;
+
+    /* Check if data ready needs to be serviced */
+    if (status & FREQM_INTFLAG_DONE)
+    {
+        if (module->callback[FREQM_CALLBACK_MEASURE_DONE])
+        {
+            FREQM->INTFLAG.reg = FREQM_INTFLAG_DONE;
+            module->callback[FREQM_CALLBACK_MEASURE_DONE]();
+        }
+    }
 
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h
index 0fe46e05d7c2..f9129cf1aa71 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/freqm/freqm_callback.h
@@ -64,22 +64,22 @@ extern "C" {
 
 /** FREQM callback type. */
 enum freqm_callback_type {
-	/** Measurement done callback.*/
-	FREQM_CALLBACK_MEASURE_DONE = 0,
+    /** Measurement done callback.*/
+    FREQM_CALLBACK_MEASURE_DONE = 0,
 };
- 
+
 /** \name Callback Configuration and Initialization
  * @{
  */
- 
+
 enum status_code freqm_register_callback(
-		struct freqm_module *const module,
-		freqm_callback_t callback_func,
-		enum freqm_callback callback_type);
+        struct freqm_module *const module,
+        freqm_callback_t callback_func,
+        enum freqm_callback callback_type);
 
 enum status_code freqm_unregister_callback(
-		struct freqm_module *module,
-		enum freqm_callback callback_type);
+        struct freqm_module *module,
+        enum freqm_callback callback_type);
 
 /** @} */
 
@@ -99,20 +99,21 @@ enum status_code freqm_unregister_callback(
  * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
  */
 static inline enum status_code freqm_enable_callback(struct freqm_module *const module,
-		const enum freqm_callback_type type)
+        const enum freqm_callback_type type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	if (type == FREQM_CALLBACK_MEASURE_DONE){
-		module->hw->INTENSET.reg = FREQM_INTENSET_DONE;
-	} else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_FREQM);
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+
+    if (type == FREQM_CALLBACK_MEASURE_DONE)
+    {
+        module->hw->INTENSET.reg = FREQM_INTENSET_DONE;
+    } else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_FREQM);
+    return STATUS_OK;
 }
 
 /**
@@ -126,20 +127,21 @@ static inline enum status_code freqm_enable_callback(struct freqm_module *const
  * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied
  */
 static inline enum status_code freqm_disable_callback(struct freqm_module *const module,
-		 const enum freqm_callback_type type)
+         const enum freqm_callback_type type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	if (type == FREQM_CALLBACK_MEASURE_DONE){
-		module->hw->INTENCLR.reg = FREQM_INTENCLR_DONE;
-	} else {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_FREQM);
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+
+    if (type == FREQM_CALLBACK_MEASURE_DONE)
+    {
+        module->hw->INTENCLR.reg = FREQM_INTENCLR_DONE;
+    } else {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_FREQM);
+    return STATUS_OK;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c
index 7c871f4eb9db..498cacb8c014 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.c
@@ -67,11 +67,11 @@ static void (*aon_handle_ext_wakeup_isr)(void) = (void (*)(void))0x1bc51;
  */
 void gpio_get_config_defaults(struct gpio_config *const config)
 {
-	/* Default configuration values */
-	config->direction  = GPIO_PIN_DIR_INPUT;
-	config->input_pull = GPIO_PIN_PULL_UP;
-	config->powersave  = false;
-	config->aon_wakeup = false;
+    /* Default configuration values */
+    config->direction  = GPIO_PIN_DIR_INPUT;
+    config->input_pull = GPIO_PIN_PULL_UP;
+    config->powersave  = false;
+    config->aon_wakeup = false;
 }
 
 /**
@@ -96,84 +96,99 @@ void gpio_get_config_defaults(struct gpio_config *const config)
  *
  */
 enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
-		const struct gpio_config *config)
+        const struct gpio_config *config)
 {
-	enum status_code status = STATUS_OK;
-
-	/* Following GPIO's should never be modified by user.
-	* GPIO_0 & GPIO_1 are used for SWD.
-	*/
-	if ((gpio_pin == PIN_LP_GPIO_0) || \
-		(gpio_pin == PIN_LP_GPIO_1))
-	{
-		status = STATUS_ERR_INVALID_ARG;
-	} else {
-		if (gpio_pin <= 7) {
-			LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		} else if (gpio_pin <= 15) {
-			LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		} else if (gpio_pin <= 23) {
-			LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		} else if (44 <= gpio_pin  && gpio_pin < 48) {
-			/* Set GPIO_MSx as digital mode */
-			AON_GP_REGS0->MS_GPIO_MODE.vec.ANALOG_ENABLE_ &= ~(1 << (gpio_pin - PIN_GPIO_MS4));
-		}
-	
-		if ((gpio_pin == PIN_AO_GPIO_0) || (gpio_pin == PIN_AO_GPIO_1) ||
-				(gpio_pin == PIN_AO_GPIO_2)) {
-			/* Active Low, Always On Pull Enable Control */
-			if (config->input_pull == GPIO_PIN_PULL_UP) {
-				AON_GP_REGS0->AON_PULL_ENABLE.reg &= ~(1 << (31 - gpio_pin));
-			} else {
-				AON_GP_REGS0->AON_PULL_ENABLE.reg |= 1 << (31 - gpio_pin);
-			}
-			if (config->aon_wakeup) {
-				/* Enable AON_GPIO_x to be a wakeup MCU from sleep mode */
-				AON_GP_REGS0->AON_PINMUX_SEL.reg |= 1 << (4 * (31 - gpio_pin));
-				/* Enable AON_GPIO_x to wake up the BLE domain from sleep mode */
-				AON_PWR_SEQ0->GPIO_WAKEUP_CTRL.bit.BLE_ENABLE = 1;
-			}
-		} else {
-			if(config->direction == GPIO_PIN_DIR_INPUT) {
-				if(gpio_pin < 16) {
-					GPIO0->OUTENCLR.reg = (1 << gpio_pin);
-				} else if (gpio_pin < 32){
-					GPIO1->OUTENCLR.reg = (1 << (gpio_pin % 16));
-				} else {
-					GPIO2->OUTENCLR.reg = (1 << (gpio_pin % 16));
-				}
-				/* pull_enable. */
-				if (gpio_pin < 32) {
-					switch(config->input_pull) {
-						case GPIO_PIN_PULL_NONE:
-							LPMCU_MISC_REGS0->PULL_ENABLE.reg |= (1 << gpio_pin);
-							break;
-						case GPIO_PIN_PULL_UP:
-							LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
-							break;
-						case GPIO_PIN_PULL_DOWN:
-							/* Set R-Type */
-							LPMCU_MISC_REGS0->RTYPE_PAD_0.reg |= (1 << gpio_pin);
-							/* Set REN */
-							LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
-							break;
-						default:
-							status = STATUS_ERR_INVALID_ARG;
-							break;
-					}
-				}
-			} else if(config->direction == GPIO_PIN_DIR_OUTPUT) {
-				if (gpio_pin < 16) {
-					GPIO0->OUTENSET.reg = (1 << gpio_pin);
-				} else if (gpio_pin < 32) {
-					GPIO1->OUTENSET.reg = (1 << (gpio_pin % 16));
-				} else {
-					GPIO2->OUTENSET.reg = (1 << (gpio_pin % 16));
-				}
-			}
-		}
-	}
-	return status;
+    enum status_code status = STATUS_OK;
+
+    /* Following GPIO's should never be modified by user.
+    * GPIO_0 & GPIO_1 are used for SWD.
+    */
+    if ((gpio_pin == PIN_LP_GPIO_0) || \
+        (gpio_pin == PIN_LP_GPIO_1))
+    {
+        status = STATUS_ERR_INVALID_ARG;
+    } else {
+        if (gpio_pin <= 7)
+        {
+            LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        } else if (gpio_pin <= 15)
+        {
+            LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        } else if (gpio_pin <= 23)
+        {
+            LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        } else if (44 <= gpio_pin  && gpio_pin < 48)
+        {
+            /* Set GPIO_MSx as digital mode */
+            AON_GP_REGS0->MS_GPIO_MODE.vec.ANALOG_ENABLE_ &= ~(1 << (gpio_pin - PIN_GPIO_MS4));
+        }
+
+        if ((gpio_pin == PIN_AO_GPIO_0) || (gpio_pin == PIN_AO_GPIO_1) ||
+                (gpio_pin == PIN_AO_GPIO_2))
+                {
+            /* Active Low, Always On Pull Enable Control */
+            if (config->input_pull == GPIO_PIN_PULL_UP)
+            {
+                AON_GP_REGS0->AON_PULL_ENABLE.reg &= ~(1 << (31 - gpio_pin));
+            } else {
+                AON_GP_REGS0->AON_PULL_ENABLE.reg |= 1 << (31 - gpio_pin);
+            }
+            if (config->aon_wakeup)
+            {
+                /* Enable AON_GPIO_x to be a wakeup MCU from sleep mode */
+                AON_GP_REGS0->AON_PINMUX_SEL.reg |= 1 << (4 * (31 - gpio_pin));
+                /* Enable AON_GPIO_x to wake up the BLE domain from sleep mode */
+                AON_PWR_SEQ0->GPIO_WAKEUP_CTRL.bit.BLE_ENABLE = 1;
+            }
+        } else {
+            if(config->direction == GPIO_PIN_DIR_INPUT)
+            {
+                if(gpio_pin < 16)
+                {
+                    GPIO0->OUTENCLR.reg = (1 << gpio_pin);
+                } else if (gpio_pin < 32)
+                {
+                    GPIO1->OUTENCLR.reg = (1 << (gpio_pin % 16));
+                } else {
+                    GPIO2->OUTENCLR.reg = (1 << (gpio_pin % 16));
+                }
+                /* pull_enable. */
+                if (gpio_pin < 32)
+                {
+                    switch(config->input_pull)
+                    {
+                        case GPIO_PIN_PULL_NONE:
+                            LPMCU_MISC_REGS0->PULL_ENABLE.reg |= (1 << gpio_pin);
+                            break;
+                        case GPIO_PIN_PULL_UP:
+                            LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
+                            break;
+                        case GPIO_PIN_PULL_DOWN:
+                            /* Set R-Type */
+                            LPMCU_MISC_REGS0->RTYPE_PAD_0.reg |= (1 << gpio_pin);
+                            /* Set REN */
+                            LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~(1 << gpio_pin);
+                            break;
+                        default:
+                            status = STATUS_ERR_INVALID_ARG;
+                            break;
+                    }
+                }
+            } else if(config->direction == GPIO_PIN_DIR_OUTPUT)
+            {
+                if (gpio_pin < 16)
+                {
+                    GPIO0->OUTENSET.reg = (1 << gpio_pin);
+                } else if (gpio_pin < 32)
+                {
+                    GPIO1->OUTENSET.reg = (1 << (gpio_pin % 16));
+                } else {
+                    GPIO2->OUTENSET.reg = (1 << (gpio_pin % 16));
+                }
+            }
+        }
+    }
+    return status;
 }
 
 /**
@@ -188,20 +203,22 @@ enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
  */
 bool gpio_pin_get_input_level(const uint8_t gpio_pin)
 {
-	uint32_t regval = 0;
-
-	if (gpio_pin < 16) {
-		regval = GPIO0->DATA.reg;
-		regval &= (1 << gpio_pin);
-	} else if (gpio_pin < 32) {
-		regval = GPIO1->DATA.reg;
-		regval &= (1 << (gpio_pin % 16));
-	} else {
-		regval = GPIO2->DATA.reg;
-		regval &= (1 << (gpio_pin % 16));
-	}
-
-	return regval;
+    uint32_t regval = 0;
+
+    if (gpio_pin < 16)
+    {
+        regval = GPIO0->DATA.reg;
+        regval &= (1 << gpio_pin);
+    } else if (gpio_pin < 32)
+    {
+        regval = GPIO1->DATA.reg;
+        regval &= (1 << (gpio_pin % 16));
+    } else {
+        regval = GPIO2->DATA.reg;
+        regval &= (1 << (gpio_pin % 16));
+    }
+
+    return regval;
 }
 
 /**
@@ -216,20 +233,22 @@ bool gpio_pin_get_input_level(const uint8_t gpio_pin)
  */
 bool gpio_pin_get_output_level(const uint8_t gpio_pin)
 {
-	uint32_t regval = 0;
-
-	if (gpio_pin < 16) {
-		regval = GPIO0->DATAOUT.reg;
-		regval &= (1 << gpio_pin);
-	} else if (gpio_pin < 32) {
-		regval = GPIO1->DATAOUT.reg;
-		regval &= (1 << (gpio_pin % 16));
-	} else {
-		regval = GPIO2->DATAOUT.reg;
-		regval &= (1 << (gpio_pin % 16));
-	}
-
-	return regval;
+    uint32_t regval = 0;
+
+    if (gpio_pin < 16)
+    {
+        regval = GPIO0->DATAOUT.reg;
+        regval &= (1 << gpio_pin);
+    } else if (gpio_pin < 32)
+    {
+        regval = GPIO1->DATAOUT.reg;
+        regval &= (1 << (gpio_pin % 16));
+    } else {
+        regval = GPIO2->DATAOUT.reg;
+        regval &= (1 << (gpio_pin % 16));
+    }
+
+    return regval;
 }
 
 /**
@@ -242,25 +261,30 @@ bool gpio_pin_get_output_level(const uint8_t gpio_pin)
  */
 void gpio_pin_set_output_level(const uint8_t gpio_pin, const bool level)
 {
-	if (gpio_pin < 16) {
-		if(level) {
-			GPIO0->DATAOUT.reg |= (1 << gpio_pin);
-		} else {
-			GPIO0->DATAOUT.reg &= ~(1 << gpio_pin);
-		}
-	} else if (gpio_pin < 32) {
-		if(level) {
-			GPIO1->DATAOUT.reg |= (1 << (gpio_pin % 16));
-		} else {
-			GPIO1->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
-		}
-	} else {
-		if(level) {
-			GPIO2->DATAOUT.reg |= (1 << (gpio_pin % 16));
-		} else {
-			GPIO2->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
-		}
-	}
+    if (gpio_pin < 16)
+    {
+        if(level)
+        {
+            GPIO0->DATAOUT.reg |= (1 << gpio_pin);
+        } else {
+            GPIO0->DATAOUT.reg &= ~(1 << gpio_pin);
+        }
+    } else if (gpio_pin < 32)
+    {
+        if(level)
+        {
+            GPIO1->DATAOUT.reg |= (1 << (gpio_pin % 16));
+        } else {
+            GPIO1->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
+        }
+    } else {
+        if(level)
+        {
+            GPIO2->DATAOUT.reg |= (1 << (gpio_pin % 16));
+        } else {
+            GPIO2->DATAOUT.reg &= ~(1 << (gpio_pin % 16));
+        }
+    }
 }
 
 /**
@@ -272,13 +296,15 @@ void gpio_pin_set_output_level(const uint8_t gpio_pin, const bool level)
  */
 void gpio_pin_toggle_output_level(const uint8_t gpio_pin)
 {
-	if (gpio_pin < 16) {
-		GPIO0->DATAOUT.reg ^= (1 << gpio_pin);
-	} else if (gpio_pin < 32) {
-		GPIO1->DATAOUT.reg ^= (1 << (gpio_pin % 16));
-	} else {
-		GPIO2->DATAOUT.reg ^= (1 << (gpio_pin % 16));
-	}
+    if (gpio_pin < 16)
+    {
+        GPIO0->DATAOUT.reg ^= (1 << gpio_pin);
+    } else if (gpio_pin < 32)
+    {
+        GPIO1->DATAOUT.reg ^= (1 << (gpio_pin % 16));
+    } else {
+        GPIO2->DATAOUT.reg ^= (1 << (gpio_pin % 16));
+    }
 }
 
 /**
@@ -292,47 +318,59 @@ void gpio_pin_toggle_output_level(const uint8_t gpio_pin)
  */
 void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel)
 {
-	uint8_t megamux_sel = (pinmux_sel >> 8) & 0xFF;
-
-	pinmux_sel &= 0xFF;
-
-	if (gpio_pin <= 7) {
-		LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		LPMCU_MISC_REGS0->PINMUX_SEL_0.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
-		if (pinmux_sel == 0x01) {
-			if (gpio_pin <= 3) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			} else if (gpio_pin <= 7) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			}
-		}
-	} else if (gpio_pin <= 15) {
-		LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		LPMCU_MISC_REGS0->PINMUX_SEL_1.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
-		if (pinmux_sel == 0x01) {
-			if (gpio_pin <= 11) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			} else if (gpio_pin <= 15) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			}
-		}
-	} else if (gpio_pin <= 23) {
-		LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
-		LPMCU_MISC_REGS0->PINMUX_SEL_2.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
-		if (pinmux_sel == 0x01) {
-			if (gpio_pin <= 19) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			} else if (gpio_pin <= 23) {
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
-				LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
-			}
-		}
-	}
+    uint8_t megamux_sel = (pinmux_sel >> 8) & 0xFF;
+
+    pinmux_sel &= 0xFF;
+
+    if (gpio_pin <= 7)
+    {
+        LPMCU_MISC_REGS0->PINMUX_SEL_0.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        LPMCU_MISC_REGS0->PINMUX_SEL_0.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+        if (pinmux_sel == 0x01)
+        {
+            if (gpio_pin <= 3)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_0.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            } else if (gpio_pin <= 7)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_1.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            }
+        }
+    } else if (gpio_pin <= 15)
+    {
+        LPMCU_MISC_REGS0->PINMUX_SEL_1.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        LPMCU_MISC_REGS0->PINMUX_SEL_1.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+        if (pinmux_sel == 0x01)
+        {
+            if (gpio_pin <= 11)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_2.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            } else if (gpio_pin <= 15)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_3.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            }
+        }
+    } else if (gpio_pin <= 23)
+    {
+        LPMCU_MISC_REGS0->PINMUX_SEL_2.reg &= ~(7 << ((gpio_pin % 8) * 4));
+        LPMCU_MISC_REGS0->PINMUX_SEL_2.reg |= (pinmux_sel << ((gpio_pin % 8)*4));
+        if (pinmux_sel == 0x01)
+        {
+            if (gpio_pin <= 19)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_4.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            } else if (gpio_pin <= 23)
+            {
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg &= ~(0x3F << ((gpio_pin % 4) * 8));
+                LPMCU_MISC_REGS0->MEGA_MUX_IO_SEL_5.reg |= (megamux_sel << ((gpio_pin % 4) * 8));
+            }
+        }
+    }
 }
 
 /**
@@ -350,49 +388,52 @@ void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel)
  *
  */
 void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
-				enum gpio_callback callback_type)
+                enum gpio_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(callback_func);
-	Assert(gpio_pin < 48);
-
-	uint8_t gpio_port = 0;
-
-	if (gpio_pin < 16) {
-		gpio_port = 0;
-	} else if (gpio_pin < 32) {
-		gpio_port = 1;
-	} else {
-		gpio_port = 2;
-	}
-	switch (callback_type) {
-	case GPIO_CALLBACK_LOW:
-		_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
-		_gpio_instances[gpio_port].hw->INTPOLCLR.reg = 1 << (gpio_pin % 16);
-		break;
-
-	case GPIO_CALLBACK_HIGH:
-		_gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
-		_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
-		break;
-
-	case GPIO_CALLBACK_RISING:
-		_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
-		_gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
-		break;
-
-	case GPIO_CALLBACK_FALLING:
-		_gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
-		_gpio_instances[gpio_port].hw->INTPOLCLR.reg = (1 << (gpio_pin % 16));
-		break;
-
-	case GPIO_CALLBACK_N:
-		break;
-	}
-	/* Register callback function */
-	_gpio_instances[gpio_port].callback[gpio_pin % 16] = callback_func;
-	/* Set the bit corresponding to the gpio pin */
-	_gpio_instances[gpio_port].callback_reg_mask |= (1 << (gpio_pin % 16));
+    /* Sanity check arguments */
+    Assert(callback_func);
+    Assert(gpio_pin < 48);
+
+    uint8_t gpio_port = 0;
+
+    if (gpio_pin < 16)
+    {
+        gpio_port = 0;
+    } else if (gpio_pin < 32)
+    {
+        gpio_port = 1;
+    } else {
+        gpio_port = 2;
+    }
+    switch (callback_type)
+    {
+    case GPIO_CALLBACK_LOW:
+        _gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
+        _gpio_instances[gpio_port].hw->INTPOLCLR.reg = 1 << (gpio_pin % 16);
+        break;
+
+    case GPIO_CALLBACK_HIGH:
+        _gpio_instances[gpio_port].hw->INTTYPECLR.reg = 1 << (gpio_pin % 16);
+        _gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
+        break;
+
+    case GPIO_CALLBACK_RISING:
+        _gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
+        _gpio_instances[gpio_port].hw->INTPOLSET.reg = 1 << (gpio_pin % 16);
+        break;
+
+    case GPIO_CALLBACK_FALLING:
+        _gpio_instances[gpio_port].hw->INTTYPESET.reg = 1 << (gpio_pin % 16);
+        _gpio_instances[gpio_port].hw->INTPOLCLR.reg = (1 << (gpio_pin % 16));
+        break;
+
+    case GPIO_CALLBACK_N:
+        break;
+    }
+    /* Register callback function */
+    _gpio_instances[gpio_port].callback[gpio_pin % 16] = callback_func;
+    /* Set the bit corresponding to the gpio pin */
+    _gpio_instances[gpio_port].callback_reg_mask |= (1 << (gpio_pin % 16));
 }
 
 /**
@@ -406,26 +447,28 @@ void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
  *
  */
 void gpio_unregister_callback(uint8_t gpio_pin,
-				enum gpio_callback callback_type)
+                enum gpio_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(callback_func);
-	Assert(gpio_pin < 48);
-
-	uint8_t gpio_port = 0;
-
-	if (gpio_pin < 16) {
-		gpio_port = 0;
-	} else if (gpio_pin < 32) {
-		gpio_port = 1;
-	} else {
-		gpio_port = 2;
-	}
-
-	/* Unregister callback function */
-	_gpio_instances[gpio_port].callback[gpio_pin % 16] = NULL;
-	/* Set the bit corresponding to the gpio pin */
-	_gpio_instances[gpio_port].callback_reg_mask &= ~(1 << (gpio_pin % 16));
+    /* Sanity check arguments */
+    Assert(callback_func);
+    Assert(gpio_pin < 48);
+
+    uint8_t gpio_port = 0;
+
+    if (gpio_pin < 16)
+    {
+        gpio_port = 0;
+    } else if (gpio_pin < 32)
+    {
+        gpio_port = 1;
+    } else {
+        gpio_port = 2;
+    }
+
+    /* Unregister callback function */
+    _gpio_instances[gpio_port].callback[gpio_pin % 16] = NULL;
+    /* Set the bit corresponding to the gpio pin */
+    _gpio_instances[gpio_port].callback_reg_mask &= ~(1 << (gpio_pin % 16));
 }
 
 /**
@@ -439,24 +482,26 @@ void gpio_unregister_callback(uint8_t gpio_pin,
  */
 void gpio_enable_callback(uint8_t gpio_pin)
 {
-	Assert(gpio_pin < 48);
-
-	uint8_t gpio_port = 0;
-
-	if (gpio_pin < 16) {
-		gpio_port = 0;
-		NVIC_EnableIRQ(GPIO0_IRQn);
-	} else if (gpio_pin < 32) {
-		gpio_port = 1;
-		NVIC_EnableIRQ(GPIO1_IRQn);
-	} else {
-		gpio_port = 2;
-		NVIC_EnableIRQ(GPIO2_IRQn);
-	}
-
-	/* Enable callback */
-	_gpio_instances[gpio_port].callback_enable_mask |= (1 << (gpio_pin % 16));
-	_gpio_instances[gpio_port].hw->INTENSET.reg = (1 << (gpio_pin % 16));
+    Assert(gpio_pin < 48);
+
+    uint8_t gpio_port = 0;
+
+    if (gpio_pin < 16)
+    {
+        gpio_port = 0;
+        NVIC_EnableIRQ(GPIO0_IRQn);
+    } else if (gpio_pin < 32)
+    {
+        gpio_port = 1;
+        NVIC_EnableIRQ(GPIO1_IRQn);
+    } else {
+        gpio_port = 2;
+        NVIC_EnableIRQ(GPIO2_IRQn);
+    }
+
+    /* Enable callback */
+    _gpio_instances[gpio_port].callback_enable_mask |= (1 << (gpio_pin % 16));
+    _gpio_instances[gpio_port].hw->INTENSET.reg = (1 << (gpio_pin % 16));
 }
 
 /**
@@ -469,21 +514,23 @@ void gpio_enable_callback(uint8_t gpio_pin)
  */
 void gpio_disable_callback(uint8_t gpio_pin)
 {
-	Assert(gpio_pin < 48);
-
-	uint8_t gpio_port = 0;
-
-	if (gpio_pin < 16) {
-		gpio_port = 0;
-	} else if (gpio_pin < 32) {
-		gpio_port = 1;
-	} else {
-		gpio_port = 2;
-	}
-
-	/* Enable callback */
-	_gpio_instances[gpio_port].callback_enable_mask &= ~(1 << (gpio_pin % 16));
-	_gpio_instances[gpio_port].hw->INTENCLR.reg = (1 << (gpio_pin % 16));
+    Assert(gpio_pin < 48);
+
+    uint8_t gpio_port = 0;
+
+    if (gpio_pin < 16)
+    {
+        gpio_port = 0;
+    } else if (gpio_pin < 32)
+    {
+        gpio_port = 1;
+    } else {
+        gpio_port = 2;
+    }
+
+    /* Enable callback */
+    _gpio_instances[gpio_port].callback_enable_mask &= ~(1 << (gpio_pin % 16));
+    _gpio_instances[gpio_port].hw->INTENCLR.reg = (1 << (gpio_pin % 16));
 }
 
 /**
@@ -494,19 +541,21 @@ void gpio_disable_callback(uint8_t gpio_pin)
  */
 static void gpio_port0_isr_handler(void)
 {
-	uint32_t flag = _gpio_instances[0].hw->INTSTATUSCLEAR.reg;
-
-	for (uint8_t i = 0; i < 16; i++){
-		if (flag & (1 << i)) {
-			/* Clear interrupt flag */
-			_gpio_instances[0].hw->INTSTATUSCLEAR.reg = (1 << i);
-			if ((_gpio_instances[0].callback_enable_mask & (1 << i)) && \
+    uint32_t flag = _gpio_instances[0].hw->INTSTATUSCLEAR.reg;
+
+    for (uint8_t i = 0; i < 16; i++)
+    {
+        if (flag & (1 << i))
+        {
+            /* Clear interrupt flag */
+            _gpio_instances[0].hw->INTSTATUSCLEAR.reg = (1 << i);
+            if ((_gpio_instances[0].callback_enable_mask & (1 << i)) && \
                     (_gpio_instances[0].callback_reg_mask & (1 << i)))
                 _gpio_instances[0].callback[i]();
-			break;
-		}
-	}
-	NVIC_ClearPendingIRQ(GPIO0_IRQn);
+            break;
+        }
+    }
+    NVIC_ClearPendingIRQ(GPIO0_IRQn);
 }
 
 /**
@@ -517,25 +566,29 @@ static void gpio_port0_isr_handler(void)
  */
 static void gpio_port1_isr_handler(void)
 {
-	uint32_t flag = _gpio_instances[1].hw->INTSTATUSCLEAR.reg;
-
-	for (uint8_t i = 0; i < 16; i++){
-		/* For AON wakeup pin clear interrupt */
-		if (flag & ((1<<15) | (1<<14) | (1<<13))) {
-			aon_handle_ext_wakeup_isr();
-		}
-
-		if (flag & (1 << i)) {
-			/* Clear interrupt flag */
-			_gpio_instances[1].hw->INTSTATUSCLEAR.reg = (1 << i);
-			if ((_gpio_instances[1].callback_enable_mask & (1 << i)) && \
-			(_gpio_instances[1].callback_reg_mask & (1 << i))) {
-				_gpio_instances[1].callback[i]();
-				break;
-			}
-		}
-	}
-	NVIC_ClearPendingIRQ(GPIO1_IRQn);
+    uint32_t flag = _gpio_instances[1].hw->INTSTATUSCLEAR.reg;
+
+    for (uint8_t i = 0; i < 16; i++)
+    {
+        /* For AON wakeup pin clear interrupt */
+        if (flag & ((1<<15) | (1<<14) | (1<<13)))
+        {
+            aon_handle_ext_wakeup_isr();
+        }
+
+        if (flag & (1 << i))
+        {
+            /* Clear interrupt flag */
+            _gpio_instances[1].hw->INTSTATUSCLEAR.reg = (1 << i);
+            if ((_gpio_instances[1].callback_enable_mask & (1 << i)) && \
+            (_gpio_instances[1].callback_reg_mask & (1 << i)))
+            {
+                _gpio_instances[1].callback[i]();
+                break;
+            }
+        }
+    }
+    NVIC_ClearPendingIRQ(GPIO1_IRQn);
 }
 
 /**
@@ -546,19 +599,21 @@ static void gpio_port1_isr_handler(void)
  */
 static void gpio_port2_isr_handler(void)
 {
-	uint32_t flag = _gpio_instances[2].hw->INTSTATUSCLEAR.reg;
-
-	for (uint8_t i = 12; i < 16; i++){
-		if (flag & (1 << i)) {
-			/* Clear interrupt flag */
-			_gpio_instances[2].hw->INTSTATUSCLEAR.reg = (1 << i);
-			if ((_gpio_instances[2].callback_enable_mask & (1 << i)) && \
+    uint32_t flag = _gpio_instances[2].hw->INTSTATUSCLEAR.reg;
+
+    for (uint8_t i = 12; i < 16; i++)
+    {
+        if (flag & (1 << i))
+        {
+            /* Clear interrupt flag */
+            _gpio_instances[2].hw->INTSTATUSCLEAR.reg = (1 << i);
+            if ((_gpio_instances[2].callback_enable_mask & (1 << i)) && \
                     (_gpio_instances[2].callback_reg_mask & (1 << i)))
                 _gpio_instances[2].callback[i]();
-			break;
-		}
-	}
-	NVIC_ClearPendingIRQ(GPIO2_IRQn);
+            break;
+        }
+    }
+    NVIC_ClearPendingIRQ(GPIO2_IRQn);
 }
 
 /**
@@ -569,20 +624,22 @@ static void gpio_port2_isr_handler(void)
  */
 void gpio_init(void)
 {
-	uint8_t i, j;
-
-	for(i = 0; i < 3; i++) {
-		for(j = 0; j < 16; j++) {
-			_gpio_instances[i].callback[j] = NULL;
-		}
-		_gpio_instances[i].callback_enable_mask = 0;
-		_gpio_instances[i].callback_reg_mask = 0;
-	}
-	_gpio_instances[0].hw = (void *)GPIO0;
-	_gpio_instances[1].hw = (void *)GPIO1;
-	_gpio_instances[2].hw = (void *)GPIO2;
-	system_register_isr(RAM_ISR_TABLE_PORT0_COMB_INDEX, (uint32_t)gpio_port0_isr_handler);
-	system_register_isr(RAM_ISR_TABLE_PORT1_COMB_INDEX, (uint32_t)gpio_port1_isr_handler);
-	system_register_isr(RAM_ISR_TABLE_PORT2_COMB_INDEX, (uint32_t)gpio_port2_isr_handler);
+    uint8_t i, j;
+
+    for(i = 0; i < 3; i++)
+    {
+        for(j = 0; j < 16; j++)
+        {
+            _gpio_instances[i].callback[j] = NULL;
+        }
+        _gpio_instances[i].callback_enable_mask = 0;
+        _gpio_instances[i].callback_reg_mask = 0;
+    }
+    _gpio_instances[0].hw = (void *)GPIO0;
+    _gpio_instances[1].hw = (void *)GPIO1;
+    _gpio_instances[2].hw = (void *)GPIO2;
+    system_register_isr(RAM_ISR_TABLE_PORT0_COMB_INDEX, (uint32_t)gpio_port0_isr_handler);
+    system_register_isr(RAM_ISR_TABLE_PORT1_COMB_INDEX, (uint32_t)gpio_port1_isr_handler);
+    system_register_isr(RAM_ISR_TABLE_PORT2_COMB_INDEX, (uint32_t)gpio_port2_isr_handler);
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h
index dbb020b9d234..a1d6305a7049 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/gpio/gpio.h
@@ -144,12 +144,12 @@ extern "C" {
  *  structure, to indicate the direction the pin should use.
  */
 enum gpio_pin_dir {
-	/** The pin's input buffer should be enabled, so that the pin state can
-	 *  be read. */
-	GPIO_PIN_DIR_INPUT,
-	/** The pin's output buffer should be enabled, so that the pin state can
-	 *  be set. */
-	GPIO_PIN_DIR_OUTPUT,
+    /** The pin's input buffer should be enabled, so that the pin state can
+     *  be read. */
+    GPIO_PIN_DIR_INPUT,
+    /** The pin's output buffer should be enabled, so that the pin state can
+     *  be set. */
+    GPIO_PIN_DIR_OUTPUT,
 };
 
 /**
@@ -159,12 +159,12 @@ enum gpio_pin_dir {
  *  structure, to indicate the type of logic level pull the pin should use.
  */
 enum gpio_pin_pull {
-	/** No logical pull should be applied to the pin */
-	GPIO_PIN_PULL_NONE,
-	/** Pin should be pulled up when idle */
-	GPIO_PIN_PULL_UP ,
-	/** Pin should be pulled down when idle */
-	GPIO_PIN_PULL_DOWN,
+    /** No logical pull should be applied to the pin */
+    GPIO_PIN_PULL_NONE,
+    /** Pin should be pulled up when idle */
+    GPIO_PIN_PULL_UP ,
+    /** Pin should be pulled down when idle */
+    GPIO_PIN_PULL_DOWN,
 };
 
 /**
@@ -173,22 +173,22 @@ enum gpio_pin_pull {
  *  Enum for the pinmux settings of the GPIO pin configuration.
  */
 enum gpio_pinmux_sel {
-	/** PINMUX selection 0 */
-	GPIO_PINMUX_SEL_0 = 0,
-	/** PINMUX selection 1 */
-	GPIO_PINMUX_SEL_1,
-	/** PINMUX selection 2 */
-	GPIO_PINMUX_SEL_2,
-	/** PINMUX selection 3 */
-	GPIO_PINMUX_SEL_3,
-	/** PINMUX selection 4 */
-	GPIO_PINMUX_SEL_4,
-	/** PINMUX selection 5 */
-	GPIO_PINMUX_SEL_5,
-	/** PINMUX selection 6 */
-	GPIO_PINMUX_SEL_6,
-	/** PINMUX selection 7 */
-	GPIO_PINMUX_SEL_7,
+    /** PINMUX selection 0 */
+    GPIO_PINMUX_SEL_0 = 0,
+    /** PINMUX selection 1 */
+    GPIO_PINMUX_SEL_1,
+    /** PINMUX selection 2 */
+    GPIO_PINMUX_SEL_2,
+    /** PINMUX selection 3 */
+    GPIO_PINMUX_SEL_3,
+    /** PINMUX selection 4 */
+    GPIO_PINMUX_SEL_4,
+    /** PINMUX selection 5 */
+    GPIO_PINMUX_SEL_5,
+    /** PINMUX selection 6 */
+    GPIO_PINMUX_SEL_6,
+    /** PINMUX selection 7 */
+    GPIO_PINMUX_SEL_7,
 };
 
 /**
@@ -211,16 +211,16 @@ typedef void (*gpio_callback_t)(void);
  * Callbacks for the GPIO driver.
  */
 enum gpio_callback {
-	/** Callback for low level */
-	GPIO_CALLBACK_LOW,
-	/** Callback for high level */
-	GPIO_CALLBACK_HIGH,
-	/** Callback for rising edge */
-	GPIO_CALLBACK_RISING,
-	/** Callback for falling edge */
-	GPIO_CALLBACK_FALLING,
-	/** Number of available callbacks */
-	GPIO_CALLBACK_N,
+    /** Callback for low level */
+    GPIO_CALLBACK_LOW,
+    /** Callback for high level */
+    GPIO_CALLBACK_HIGH,
+    /** Callback for rising edge */
+    GPIO_CALLBACK_RISING,
+    /** Callback for falling edge */
+    GPIO_CALLBACK_FALLING,
+    /** Number of available callbacks */
+    GPIO_CALLBACK_N,
 };
 
 /**
@@ -231,22 +231,22 @@ enum gpio_callback {
  *  modified by the user application.
  */
 struct gpio_config {
-	/** GPIO buffer input/output direction */
-	enum gpio_pin_dir  direction;
+    /** GPIO buffer input/output direction */
+    enum gpio_pin_dir  direction;
 
-	/** GPIO pull-up/pull-down for input pins */
-	enum gpio_pin_pull input_pull;
+    /** GPIO pull-up/pull-down for input pins */
+    enum gpio_pin_pull input_pull;
 
-	/** Enable lowest possible powerstate on the pin
-	 *
-	 *  \note All other configurations will be ignored, the pin will be disabled
-	 */
-	bool powersave;
-	/** Enable AON_GPIOs to wakeup MCU from ULP mode 
-	 *
-	 *  \note Only AON_GPIO_0, AON_GPIO_1, and AON_GPIO_2 could enable this feature
-	 */
-	bool aon_wakeup;
+    /** Enable lowest possible powerstate on the pin
+     *
+     *  \note All other configurations will be ignored, the pin will be disabled
+     */
+    bool powersave;
+    /** Enable AON_GPIOs to wakeup MCU from ULP mode
+     *
+     *  \note Only AON_GPIO_0, AON_GPIO_1, and AON_GPIO_2 could enable this feature
+     */
+    bool aon_wakeup;
 };
 
 /**
@@ -260,14 +260,14 @@ struct gpio_config {
  */
 struct gpio_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to the hardware instance */
-	Gpio *hw;
-	/** Array to store callback function pointers in */
-	gpio_callback_t callback[16];
-	/** Bit mask for callbacks registered */
-	uint16_t callback_reg_mask;
-	/** Bit mask for callbacks enabled */
-	uint16_t callback_enable_mask;
+    /** Pointer to the hardware instance */
+    Gpio *hw;
+    /** Array to store callback function pointers in */
+    gpio_callback_t callback[16];
+    /** Bit mask for callbacks registered */
+    uint16_t callback_reg_mask;
+    /** Bit mask for callbacks enabled */
+    uint16_t callback_enable_mask;
 #endif
 };
 
@@ -277,7 +277,7 @@ struct gpio_module {
 
 void gpio_get_config_defaults(struct gpio_config *const config);
 enum status_code gpio_pin_set_config(const uint8_t gpio_pin,
-		const struct gpio_config *config);
+        const struct gpio_config *config);
 
 /** @} */
 
@@ -301,9 +301,9 @@ void gpio_pinmux_cofiguration(const uint8_t gpio_pin, uint16_t pinmux_sel);
  * @{
  */
 void gpio_register_callback(uint8_t gpio_pin, gpio_callback_t callback_func,
-				enum gpio_callback callback_type);
+                enum gpio_callback callback_type);
 void gpio_unregister_callback(uint8_t gpio_pin,
-				enum gpio_callback callback_type);
+                enum gpio_callback callback_type);
 void gpio_enable_callback(uint8_t gpio_pin);
 void gpio_disable_callback(uint8_t gpio_pin);
 void gpio_init(void);
@@ -324,14 +324,14 @@ void gpio_init(void);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>GPIO</td>
- *		<td>General Purpose Input/Output</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>GPIO</td>
+ *      <td>General Purpose Input/Output</td>
+ *  </tr>
  * </table>
  *
  *
@@ -350,12 +350,12 @@ void gpio_init(void);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -373,16 +373,16 @@ void gpio_init(void);
  * \page asfdoc_samb_gpio_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h
index fb40afda6923..09d6ff04a8be 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_common.h
@@ -273,27 +273,27 @@ extern "C" {
  * For slave: direction of request from master.
  */
 enum i2c_transfer_direction {
-	/** Master write operation is in progress */
-	I2C_TRANSFER_WRITE = 0,
-	/** Master read operation is in progress */
-	I2C_TRANSFER_READ  = 1,
+    /** Master write operation is in progress */
+    I2C_TRANSFER_WRITE = 0,
+    /** Master read operation is in progress */
+    I2C_TRANSFER_READ  = 1,
 };
 
 /**
- * \brief I2C module clock input 
+ * \brief I2C module clock input
  *
  * I2C module clock.
  *
  */
 enum i2c_clock_input {
-	/** source from clock input 0: 26MHz */
-	I2C_CLK_INPUT_0 = 0,
-	/** source from clock input 1: 13MHz */
-	I2C_CLK_INPUT_1,
-	/** source from clock input 2: 6.5MHz */
-	I2C_CLK_INPUT_2,
-	/** source from clock input 3: 3MHz */
-	I2C_CLK_INPUT_3,
+    /** source from clock input 0: 26MHz */
+    I2C_CLK_INPUT_0 = 0,
+    /** source from clock input 1: 13MHz */
+    I2C_CLK_INPUT_1,
+    /** source from clock input 2: 6.5MHz */
+    I2C_CLK_INPUT_2,
+    /** source from clock input 3: 3MHz */
+    I2C_CLK_INPUT_3,
 };
 
 /**
@@ -305,9 +305,10 @@ enum i2c_clock_input {
  */
 static inline void i2c_wait_for_idle(I2c *const i2c_module)
 {
-	while (i2c_module->I2C_STATUS.bit.I2C_ACTIVE) {
-		/* Wait for I2C module to sync. */
-	}
+    while (i2c_module->I2C_STATUS.bit.I2C_ACTIVE)
+    {
+        /* Wait for I2C module to sync. */
+    }
 }
 
 /**
@@ -320,10 +321,10 @@ static inline void i2c_wait_for_idle(I2c *const i2c_module)
  */
 static inline void i2c_enable(I2c *const i2c_module)
 {
-	/* Wait for module to sync. */
-	i2c_wait_for_idle(i2c_module);
-	/* Enable module. */
-	i2c_module->I2C_MODULE_ENABLE.reg = (1 << I2C_MODULE_ENABLE_ENABLE_Pos);
+    /* Wait for module to sync. */
+    i2c_wait_for_idle(i2c_module);
+    /* Enable module. */
+    i2c_module->I2C_MODULE_ENABLE.reg = (1 << I2C_MODULE_ENABLE_ENABLE_Pos);
 }
 
 /**
@@ -336,8 +337,8 @@ static inline void i2c_enable(I2c *const i2c_module)
  */
 static inline void i2c_disable(I2c *const i2c_module)
 {
-	i2c_wait_for_idle(i2c_module);
-	i2c_module->I2C_MODULE_ENABLE.reg = 0;
+    i2c_wait_for_idle(i2c_module);
+    i2c_module->I2C_MODULE_ENABLE.reg = 0;
 }
 
 /**
@@ -350,8 +351,8 @@ static inline void i2c_disable(I2c *const i2c_module)
  */
 static inline void i2c_slave_flush_fifo(I2c *const i2c_module)
 {
-	i2c_wait_for_idle(i2c_module);
-	i2c_module->I2C_FLUSH.reg = 1;
+    i2c_wait_for_idle(i2c_module);
+    i2c_module->I2C_FLUSH.reg = 1;
 }
 
 /**
@@ -365,11 +366,12 @@ static inline void i2c_slave_flush_fifo(I2c *const i2c_module)
  */
 static inline void i2c_slave_rx_interrupt(I2c *const i2c_module, bool enable)
 {
-	if (enable) {
-		i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 1;
-	} else {
-		i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 0;
-	}
+    if (enable)
+    {
+        i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 1;
+    } else {
+        i2c_module->RX_INTERRUPT_MASK.bit.RX_FIFO_NOT_EMPTY_MASK = 0;
+    }
 }
 
 /**
@@ -383,13 +385,14 @@ static inline void i2c_slave_rx_interrupt(I2c *const i2c_module, bool enable)
  */
 static inline void i2c_slave_tx_interrupt(I2c *const i2c_module, bool enable)
 {
-	if (enable) {
-		i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 1;
-		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 1;
-	} else {
-		i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 0;
-		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
-	}
+    if (enable)
+    {
+        i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 1;
+        i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 1;
+    } else {
+        i2c_module->TX_INTERRUPT_MASK.bit.TX_FIFO_NOT_FULL_MASK = 0;
+        i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+    }
 }
 /** @} */
 
@@ -407,18 +410,18 @@ static inline void i2c_slave_tx_interrupt(I2c *const i2c_module, bool enable)
  * \anchor asfdoc_samb_i2c_acronyms_table
  * <table>
  *  <caption>Acronyms</caption>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>SDA</td>
- *		<td>Serial Data Line</td>
- *	</tr>
- *	<tr>
- *		<td>SCL</td>
- *		<td>Serial Clock Line</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SDA</td>
+ *      <td>Serial Data Line</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SCL</td>
+ *      <td>Serial Clock Line</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_i2c_extra_dependencies Dependencies
@@ -438,12 +441,12 @@ static inline void i2c_slave_tx_interrupt(I2c *const i2c_module, bool enable)
  * \anchor asfdoc_samb_i2c_extra_history_table
  * <table>
  *  <caption>Module History</caption>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -472,16 +475,16 @@ static inline void i2c_slave_tx_interrupt(I2c *const i2c_module, bool enable)
  * \page asfdoc_samb_i2c_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c
index 1f8d59dd0593..2271e2fcdbc3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.c
@@ -64,17 +64,17 @@
  * \param[out] config  Pointer to configuration structure to be initiated
  */
 void i2c_master_get_config_defaults(
-		struct i2c_master_config *const config)
+        struct i2c_master_config *const config)
 {
-	/* Sanity check */
-	Assert(config);
-	
-	config->clock_source    = I2C_CLK_INPUT_3;
-	config->clock_divider   = 0x10;
-	config->pin_number_pad0 = PIN_LP_GPIO_8;
-	config->pin_number_pad1 = PIN_LP_GPIO_9;
-	config->pinmux_sel_pad0 = MUX_LP_GPIO_8_I2C0_SDA;
-	config->pinmux_sel_pad1 = MUX_LP_GPIO_9_I2C0_SCL;
+    /* Sanity check */
+    Assert(config);
+
+    config->clock_source    = I2C_CLK_INPUT_3;
+    config->clock_divider   = 0x10;
+    config->pin_number_pad0 = PIN_LP_GPIO_8;
+    config->pin_number_pad1 = PIN_LP_GPIO_9;
+    config->pinmux_sel_pad0 = MUX_LP_GPIO_8_I2C0_SDA;
+    config->pinmux_sel_pad1 = MUX_LP_GPIO_9_I2C0_SCL;
 }
 
 #if !defined(__DOXYGEN__)
@@ -86,24 +86,24 @@ void i2c_master_get_config_defaults(
  *
  */
 static void _i2c_master_set_config(
-		struct i2c_master_module *const module,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-
-	I2c *const i2c_module = (module->hw);
-
-	/* Set the pinmux for this i2c module. */
-	gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
-	gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
-	/* Set clock. */
-	i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
-	i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
-	/* Enable master mode. */
-	i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_1;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    I2c *const i2c_module = (module->hw);
+
+    /* Set the pinmux for this i2c module. */
+    gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
+    gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
+    /* Set clock. */
+    i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+    i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
+    /* Enable master mode. */
+    i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_1;
 }
 #endif /* __DOXYGEN__ */
 
@@ -124,57 +124,61 @@ static void _i2c_master_set_config(
  *
  */
 enum status_code i2c_master_init(
-		struct i2c_master_module *const module,
-		I2c *const hw,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        I2c *const hw,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-	
-	module->hw = hw;
-
-	/* Sanity check arguments. */
-	if ((module == NULL) || (config == NULL))
-		return STATUS_ERR_INVALID_ARG;
-
-	i2c_disable(module->hw);
-	if (module->hw == I2C0) {
-		system_peripheral_reset(PERIPHERAL_I2C0_CORE);
-	} else if (module->hw == I2C1) {
-		system_peripheral_reset(PERIPHERAL_I2C1_CORE);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    module->hw = hw;
+
+    /* Sanity check arguments. */
+    if ((module == NULL) || (config == NULL))
+        return STATUS_ERR_INVALID_ARG;
+
+    i2c_disable(module->hw);
+    if (module->hw == I2C0)
+    {
+        system_peripheral_reset(PERIPHERAL_I2C0_CORE);
+    } else if (module->hw == I2C1)
+    {
+        system_peripheral_reset(PERIPHERAL_I2C1_CORE);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Initialize values in module. */
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
-	module->buffer_length       = 0;
-	module->buffer_remaining    = 0;
-	module->status              = STATUS_OK;
-	module->buffer              = NULL;
-
-	_i2c_instances = (void*)module;
-	if (module->hw == I2C0) {
-		system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_master_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_master_isr_handler);
-		NVIC_EnableIRQ(I2C0_RX_IRQn);
-		NVIC_EnableIRQ(I2C0_TX_IRQn);
-	} else if (module->hw == I2C1) {
-		system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_master_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_master_isr_handler);
-		NVIC_EnableIRQ(I2C1_RX_IRQn);
-		NVIC_EnableIRQ(I2C1_TX_IRQn);
-	}
+    /* Initialize values in module. */
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
+    module->buffer_length       = 0;
+    module->buffer_remaining    = 0;
+    module->status              = STATUS_OK;
+    module->buffer              = NULL;
+
+    _i2c_instances = (void*)module;
+    if (module->hw == I2C0)
+    {
+        system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_master_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_master_isr_handler);
+        NVIC_EnableIRQ(I2C0_RX_IRQn);
+        NVIC_EnableIRQ(I2C0_TX_IRQn);
+    } else if (module->hw == I2C1)
+    {
+        system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_master_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_master_isr_handler);
+        NVIC_EnableIRQ(I2C1_RX_IRQn);
+        NVIC_EnableIRQ(I2C1_TX_IRQn);
+    }
 #endif
 
-	/* Set config and return status. */
-	_i2c_master_set_config(module, config);
+    /* Set config and return status. */
+    _i2c_master_set_config(module, config);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -194,51 +198,54 @@ enum status_code i2c_master_init(
  *                                      acknowledged the address
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-	
-	uint16_t counter = 0;
-	uint32_t status  = 0;
-	I2c *const i2c_module    = (module->hw);
-	uint16_t length = packet->data_length;
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	i2c_wait_for_idle(i2c_module);
-
-	/* Flush the FIFO */
-	i2c_module->I2C_FLUSH.reg = 1;
-
-	/* Enable I2C on bus (start condition). */
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
-	/* Address I2C slave in case of Master mode enabled. */
-	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
-			(packet->address << 1) | I2C_TRANSFER_READ;
-
-	/* Now check whether the core has sent the data out and free the bus. */
-	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
-		status = i2c_module->TRANSMIT_STATUS.reg;
-	}
-
-	do {
-		/* Send stop condition. */
-		if ((!module->no_stop) && (counter == (length - 1))) {
-			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
-		}
-
-		status = i2c_module->RECEIVE_STATUS.reg;
-		if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
-			packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
-	} while (counter < length);
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    uint16_t counter = 0;
+    uint32_t status  = 0;
+    I2c *const i2c_module    = (module->hw);
+    uint16_t length = packet->data_length;
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    i2c_wait_for_idle(i2c_module);
+
+    /* Flush the FIFO */
+    i2c_module->I2C_FLUSH.reg = 1;
+
+    /* Enable I2C on bus (start condition). */
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+    /* Address I2C slave in case of Master mode enabled. */
+    i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+            (packet->address << 1) | I2C_TRANSFER_READ;
+
+    /* Now check whether the core has sent the data out and free the bus. */
+    while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY))
+    {
+        status = i2c_module->TRANSMIT_STATUS.reg;
+    }
+
+    do {
+        /* Send stop condition. */
+        if ((!module->no_stop) && (counter == (length - 1)))
+        {
+            i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+        }
+
+        status = i2c_module->RECEIVE_STATUS.reg;
+        if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+            packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
+    } while (counter < length);
+
+    return STATUS_OK;
 }
 
 /**
@@ -260,27 +267,28 @@ static enum status_code _i2c_master_read_packet(
  * \retval STATUS_BUSY                  If module has a pending request.
  */
 enum status_code i2c_master_read_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	if((module == NULL) || (packet == NULL))
-		return STATUS_ERR_INVALID_ARG;
+    if((module == NULL) || (packet == NULL))
+        return STATUS_ERR_INVALID_ARG;
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->no_stop = false;
+    module->no_stop = false;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -306,27 +314,28 @@ enum status_code i2c_master_read_packet_wait(
  * \retval STATUS_BUSY                  If module has a pending request.
  */
 enum status_code i2c_master_read_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	if((module == NULL) || (packet == NULL))
-		return STATUS_ERR_INVALID_ARG;
+    if((module == NULL) || (packet == NULL))
+        return STATUS_ERR_INVALID_ARG;
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->no_stop = true;
+    module->no_stop = true;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -340,49 +349,52 @@ enum status_code i2c_master_read_packet_wait_no_stop(
  * \retval STATUS_OK                    The packet was write successfully
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-	
-	I2c *const i2c_module = (module->hw);
-	uint16_t counter = 0;
-	uint32_t status  = 0;
-
-	uint16_t length = packet->data_length;
-
-	i2c_wait_for_idle(i2c_module);
-
-	/* Flush the FIFO */
-	i2c_module->I2C_FLUSH.reg = 1;
-
-	/* Enable I2C on bus (start condition) */
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
-
-	/* Address I2C slave in case of Master mode enabled */
-	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 | 
-			((packet->address) << 1) | I2C_TRANSFER_WRITE;
-	do {
-		status = i2c_module->TRANSMIT_STATUS.reg;
-		if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk) {
-			i2c_module->TRANSMIT_DATA.reg = packet->data[counter++];
-		}
-	} while (counter < length); 
-
-	/* Now check whether the core has sent the data out and free the bus */
-	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
-			status = i2c_module->TRANSMIT_STATUS.reg;
-	}
-
-	/* Send stop condition */
-	if (!module->no_stop) {
-		i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
-	}
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    I2c *const i2c_module = (module->hw);
+    uint16_t counter = 0;
+    uint32_t status  = 0;
+
+    uint16_t length = packet->data_length;
+
+    i2c_wait_for_idle(i2c_module);
+
+    /* Flush the FIFO */
+    i2c_module->I2C_FLUSH.reg = 1;
+
+    /* Enable I2C on bus (start condition) */
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+
+    /* Address I2C slave in case of Master mode enabled */
+    i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+            ((packet->address) << 1) | I2C_TRANSFER_WRITE;
+    do {
+        status = i2c_module->TRANSMIT_STATUS.reg;
+        if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk)
+        {
+            i2c_module->TRANSMIT_DATA.reg = packet->data[counter++];
+        }
+    } while (counter < length);
+
+    /* Now check whether the core has sent the data out and free the bus */
+    while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY))
+    {
+            status = i2c_module->TRANSMIT_STATUS.reg;
+    }
+
+    /* Send stop condition */
+    if (!module->no_stop)
+    {
+        i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -404,27 +416,29 @@ static enum status_code _i2c_master_write_packet(
  * \retval STATUS_BUSY                  If module has a pending request.
  */
 enum status_code i2c_master_write_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	if ((module == NULL) || (packet == NULL)) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    if ((module == NULL) || (packet == NULL))
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->no_stop = false;
+    module->no_stop = false;
 
-	return _i2c_master_write_packet(module, packet);
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -449,27 +463,29 @@ enum status_code i2c_master_write_packet_wait(
  * \retval STATUS_BUSY                  If module has a pending request.
  */
 enum status_code i2c_master_write_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	if((module == NULL) || (packet == NULL)) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    if((module == NULL) || (packet == NULL))
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->no_stop = true;
+    module->no_stop = true;
 
-	return _i2c_master_write_packet(module, packet);
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -486,16 +502,16 @@ enum status_code i2c_master_write_packet_wait_no_stop(
  */
 void i2c_master_send_stop(struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	
-	I2c *const i2c_module = (module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Send stop command */
-	i2c_wait_for_idle(i2c_module);
+    I2c *const i2c_module = (module->hw);
 
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+    /* Send stop command */
+    i2c_wait_for_idle(i2c_module);
+
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
 }
 
 /**
@@ -512,12 +528,12 @@ void i2c_master_send_stop(struct i2c_master_module *const module)
  */
 void i2c_master_send_start(struct i2c_master_module *const module)
 {
-	I2c *const i2c_module = (module->hw);
+    I2c *const i2c_module = (module->hw);
 
-	i2c_wait_for_idle(i2c_module);
+    i2c_wait_for_idle(i2c_module);
 
-	/* Send start command */
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+    /* Send start command */
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
 }
 
 /**
@@ -530,17 +546,17 @@ void i2c_master_send_start(struct i2c_master_module *const module)
  * \retval STATUS_OK                    The packet was read successfully
  */
 enum status_code i2c_master_read_byte(
-		struct i2c_master_module *const module,
-		uint8_t *byte)
+        struct i2c_master_module *const module,
+        uint8_t *byte)
 {
-	I2c *const i2c_module = (module->hw);
+    I2c *const i2c_module = (module->hw);
 
-	/* Read a byte from slave. */
-	i2c_wait_for_idle(i2c_module);
+    /* Read a byte from slave. */
+    i2c_wait_for_idle(i2c_module);
 
-	*byte = i2c_module->RECEIVE_DATA.bit.RX_BYTE;
+    *byte = i2c_module->RECEIVE_DATA.bit.RX_BYTE;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -554,19 +570,19 @@ enum status_code i2c_master_read_byte(
  * \retval STATUS_OK   The Address and command was written successfully
  */
 enum status_code i2c_master_write_address(
-		struct i2c_master_module *const module,
-		uint8_t address,
-		uint8_t command)
+        struct i2c_master_module *const module,
+        uint8_t address,
+        uint8_t command)
 {
-	I2c *const i2c_module = (module->hw);
+    I2c *const i2c_module = (module->hw);
 
-	/* Write byte to slave. */
-	i2c_wait_for_idle(i2c_module);
+    /* Write byte to slave. */
+    i2c_wait_for_idle(i2c_module);
 
-	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 | 
-			(address << 1) | command;
+    i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+            (address << 1) | command;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 
@@ -580,15 +596,15 @@ enum status_code i2c_master_write_address(
  * \retval STATUS_OK   One byte was written successfully
  */
 enum status_code i2c_master_write_byte(
-		struct i2c_master_module *const module,
-		uint8_t byte)
+        struct i2c_master_module *const module,
+        uint8_t byte)
 {
-	I2c *const i2c_module = (module->hw);
+    I2c *const i2c_module = (module->hw);
 
-	/* Write byte to slave. */
-	i2c_wait_for_idle(i2c_module);
+    /* Write byte to slave. */
+    i2c_wait_for_idle(i2c_module);
 
-	i2c_module->TRANSMIT_DATA.reg = (uint16_t)I2C_TRANSMIT_DATA_TX_DATA(byte);
+    i2c_module->TRANSMIT_DATA.reg = (uint16_t)I2C_TRANSMIT_DATA_TX_DATA(byte);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h
index 223da345e0fa..7cef34461872 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master.h
@@ -67,12 +67,12 @@ extern "C" {
  * Structure to be used when transferring I<SUP>2</SUP>C master packets.
  */
 struct i2c_master_packet {
-	/** Address to slave device */
-	uint16_t address;
-	/** Length of data array */
-	uint16_t data_length;
-	/** Data array containing all data to be transferred */
-	uint8_t *data;
+    /** Address to slave device */
+    uint16_t address;
+    /** Length of data array */
+    uint16_t data_length;
+    /** Data array containing all data to be transferred */
+    uint8_t *data;
 };
 
 /** \brief Interrupt flags
@@ -80,23 +80,23 @@ struct i2c_master_packet {
  * Flags used when reading or setting interrupt flags.
  */
 enum i2c_master_interrupt_flag {
-	/** Interrupt flag used for write */
-	I2C_MASTER_INTERRUPT_WRITE = 0,
-	/** Interrupt flag used for read */
-	I2C_MASTER_INTERRUPT_READ  = 1,
+    /** Interrupt flag used for write */
+    I2C_MASTER_INTERRUPT_WRITE = 0,
+    /** Interrupt flag used for read */
+    I2C_MASTER_INTERRUPT_READ  = 1,
 };
 
 /**
  * \brief I<SUP>2</SUP>C frequencies
  *
- * Values for I<SUP>2</SUP>C speeds supported by the module. 
+ * Values for I<SUP>2</SUP>C speeds supported by the module.
  *
  */
 enum i2c_master_baud_rate {
-	/** Baud rate at 100KHz (Standard-mode) */
-	I2C_MASTER_BAUD_RATE_100KHZ = 100,
-	/** Baud rate at 400KHz (Fast-mode) */
-	I2C_MASTER_BAUD_RATE_400KHZ = 400,
+    /** Baud rate at 100KHz (Standard-mode) */
+    I2C_MASTER_BAUD_RATE_100KHZ = 100,
+    /** Baud rate at 400KHz (Fast-mode) */
+    I2C_MASTER_BAUD_RATE_400KHZ = 400,
 };
 
 
@@ -107,13 +107,13 @@ enum i2c_master_baud_rate {
  * The available callback types for the I<SUP>2</SUP>C master module.
  */
 enum i2c_master_callback {
-	/** Callback for packet write complete */
-	I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
-	/** Callback for packet read complete */
-	I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
+    /** Callback for packet write complete */
+    I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+    /** Callback for packet read complete */
+    I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_I2C_MASTER_CALLBACK_N             = 2,
+    /** Total number of callbacks */
+    _I2C_MASTER_CALLBACK_N             = 2,
 #  endif
 };
 
@@ -123,7 +123,7 @@ struct i2c_master_module;
 
 /** Prototype for I2C Callback function */
 typedef void (*i2c_master_callback_t)(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 #  endif
 #endif
 
@@ -138,32 +138,32 @@ typedef void (*i2c_master_callback_t)(
  */
 struct i2c_master_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware instance initialized for the struct */
-	I2c *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** If true, stop condition will be sent after a read/write */
-	bool no_stop;
+    /** Hardware instance initialized for the struct */
+    I2c *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** If true, stop condition will be sent after a read/write */
+    bool no_stop;
 #  if I2C_MASTER_CALLBACK_MODE == true
-	/** Pointers to callback functions */
-	volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint8_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint8_t enabled_callback;
-	/** The total number of bytes to transfer */
-	volatile uint16_t buffer_length;
-	/**
-	 * Counter used for bytes left to send in write and to count number of
-	 * obtained bytes in read
-	 */
-	volatile uint16_t buffer_remaining;
-	/** Data buffer for packet write and read */
-	volatile uint8_t *buffer;
-	/** Save direction of async request. 1 = read, 0 = write */
-	volatile enum i2c_transfer_direction transfer_direction;
-	/** Status for status read back in error callback */
-	volatile enum status_code status;
+    /** Pointers to callback functions */
+    volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint8_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint8_t enabled_callback;
+    /** The total number of bytes to transfer */
+    volatile uint16_t buffer_length;
+    /**
+     * Counter used for bytes left to send in write and to count number of
+     * obtained bytes in read
+     */
+    volatile uint16_t buffer_remaining;
+    /** Data buffer for packet write and read */
+    volatile uint8_t *buffer;
+    /** Save direction of async request. 1 = read, 0 = write */
+    volatile enum i2c_transfer_direction transfer_direction;
+    /** Status for status read back in error callback */
+    volatile enum status_code status;
 #  endif
 #endif
 };
@@ -177,62 +177,62 @@ struct i2c_master_module {
  * \ref i2c_master_get_config_defaults .
  */
 struct i2c_master_config {
-	/** CLOCK INPUT to use as clock source */
-	enum i2c_clock_input clock_source;
-	/** Divide ratio used to generate the sck clock */
-	uint16_t clock_divider;
-	/** PAD0 (SDA) pin number */
-	uint32_t pin_number_pad0;
-	/** PAD0 (SDA) pinmux selection */
-	uint32_t pinmux_sel_pad0;
-	/** PAD1 (SCL) pin numer */
-	uint32_t pin_number_pad1;
-	/** PAD1 (SCL) pinmux selection */
-	uint32_t pinmux_sel_pad1;
+    /** CLOCK INPUT to use as clock source */
+    enum i2c_clock_input clock_source;
+    /** Divide ratio used to generate the sck clock */
+    uint16_t clock_divider;
+    /** PAD0 (SDA) pin number */
+    uint32_t pin_number_pad0;
+    /** PAD0 (SDA) pinmux selection */
+    uint32_t pinmux_sel_pad0;
+    /** PAD1 (SCL) pin numer */
+    uint32_t pin_number_pad1;
+    /** PAD1 (SCL) pinmux selection */
+    uint32_t pinmux_sel_pad1;
 };
 
 void i2c_master_get_config_defaults(
-		struct i2c_master_config *const config);
+        struct i2c_master_config *const config);
 
  enum status_code i2c_master_init(
-		struct i2c_master_module *const module,
-		I2c *const hw,
-		const struct i2c_master_config *const config);
+        struct i2c_master_module *const module,
+        I2c *const hw,
+        const struct i2c_master_config *const config);
 
 void i2c_master_reset(struct i2c_master_module *const module);
 
 enum status_code i2c_master_write_address(
-		struct i2c_master_module *const module,
-		uint8_t address,
-		uint8_t command);
+        struct i2c_master_module *const module,
+        uint8_t address,
+        uint8_t command);
 
 enum status_code i2c_master_read_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_read_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 void i2c_master_send_stop(struct i2c_master_module *const module);
 
 void i2c_master_send_start(struct i2c_master_module *const module);
 
 enum status_code i2c_master_read_byte(
-		struct i2c_master_module *const module,
-		uint8_t *byte);
+        struct i2c_master_module *const module,
+        uint8_t *byte);
 
 enum status_code i2c_master_write_byte(
-		struct i2c_master_module *const module,
-		uint8_t byte);
+        struct i2c_master_module *const module,
+        uint8_t byte);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c
index 5a00d942cf83..6be33fd47ec5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.c
@@ -55,20 +55,20 @@ void *_i2c_instances;
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_master_read(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
 
-	I2c *const i2c_module = module->hw;
+    I2c *const i2c_module = module->hw;
 
-	/* Find index to save next value in buffer */
-	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+    /* Find index to save next value in buffer */
+    uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
 
-	module->buffer_remaining--;
+    module->buffer_remaining--;
 
-	module->buffer[buffer_index] = i2c_module->RECEIVE_DATA.reg;
+    module->buffer[buffer_index] = i2c_module->RECEIVE_DATA.reg;
 }
 
 /**
@@ -80,23 +80,24 @@ static void _i2c_master_read(
  */
 static void _i2c_master_write(struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
 
-	I2c *const i2c_module = module->hw;
+    I2c *const i2c_module = module->hw;
 
-	/* Find index to get next byte in buffer */
-	volatile uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+    /* Find index to get next byte in buffer */
+    volatile uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
 
-	module->buffer_remaining--;
+    module->buffer_remaining--;
 
-	/* Write byte from buffer to slave */
-	i2c_module->TRANSMIT_DATA.reg = module->buffer[buffer_index];
-	
-	if (module->buffer_remaining <= 0) {
-		i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-	}
+    /* Write byte from buffer to slave */
+    i2c_module->TRANSMIT_DATA.reg = module->buffer[buffer_index];
+
+    if (module->buffer_remaining <= 0)
+    {
+        i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+    }
 }
 
 
@@ -115,20 +116,20 @@ static void _i2c_master_write(struct i2c_master_module *const module)
  * \param[in]      callback_type  Callback type to register
  */
 void i2c_master_register_callback(
-		struct i2c_master_module *const module,
-		const i2c_master_callback_t callback,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        const i2c_master_callback_t callback,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback */
-	module->callbacks[callback_type] = callback;
+    /* Register callback */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as registered */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as registered */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -141,18 +142,18 @@ void i2c_master_register_callback(
  * \param[in]     callback_type  Specifies the callback type to unregister
  */
 void i2c_master_unregister_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	
-	/* Register callback */
-	module->callbacks[callback_type] = NULL;
-
-	/* Clear corresponding bit to set callback as unregistered */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Register callback */
+    module->callbacks[callback_type] = NULL;
+
+    /* Clear corresponding bit to set callback as unregistered */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -167,34 +168,34 @@ void i2c_master_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	I2c *const i2c_module = module->hw;
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_READ;
-	module->status             = STATUS_BUSY;
-	
-	i2c_wait_for_idle(i2c_module);
-	/* Flush the FIFO */
-	i2c_module->I2C_FLUSH.reg = 1;
-	/* Enable I2C on bus (start condition) */
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
-	/* Set address and direction bit. Will send start command on bus */
-	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
-			(packet->address << 1) | module->transfer_direction;
-	/* Enable interrupts */
-	i2c_module->RX_INTERRUPT_MASK.reg = I2C_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
-	
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_READ;
+    module->status             = STATUS_BUSY;
+
+    i2c_wait_for_idle(i2c_module);
+    /* Flush the FIFO */
+    i2c_module->I2C_FLUSH.reg = 1;
+    /* Enable I2C on bus (start condition) */
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+    /* Set address and direction bit. Will send start command on bus */
+    i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+            (packet->address << 1) | module->transfer_direction;
+    /* Enable interrupts */
+    i2c_module->RX_INTERRUPT_MASK.reg = I2C_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+    return STATUS_OK;
 }
 
 /**
@@ -211,23 +212,24 @@ static enum status_code _i2c_master_read_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_read_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP */
-	module->no_stop = false;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP */
+    module->no_stop = false;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -249,23 +251,24 @@ enum status_code i2c_master_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another operation
  */
 enum status_code i2c_master_read_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we don't send STOP */
-	module->no_stop = true;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we don't send STOP */
+    module->no_stop = true;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 
@@ -280,31 +283,31 @@ enum status_code i2c_master_read_packet_job_no_stop(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	I2c *const i2c_module = module->hw;
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_WRITE;
-	module->status             = STATUS_BUSY;
-
-	/* Enable I2C on bus (start condition) */
-	i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
-	/* Set address and direction bit, will send start command on bus */
-	i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
-			(packet->address << 1) | module->transfer_direction;
-	/* Enable interrupts */
-	i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_WRITE;
+    module->status             = STATUS_BUSY;
+
+    /* Enable I2C on bus (start condition) */
+    i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_1;
+    /* Set address and direction bit, will send start command on bus */
+    i2c_module->TRANSMIT_DATA.reg = I2C_TRANSMIT_DATA_ADDRESS_FLAG_1 |
+            (packet->address << 1) | module->transfer_direction;
+    /* Enable interrupts */
+    i2c_module->TX_INTERRUPT_MASK.reg = I2C_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+    return STATUS_OK;
 }
 
 /**
@@ -321,23 +324,24 @@ static enum status_code _i2c_master_write_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_write_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP at end*/
-	module->no_stop = false;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP at end*/
+    module->no_stop = false;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -359,23 +363,24 @@ enum status_code i2c_master_write_packet_job(
  * \retval STATUS_BUSY  If module is currently busy with another
  */
 enum status_code i2c_master_write_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Do not send stop condition when done */
-	module->no_stop = true;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Do not send stop condition when done */
+    module->no_stop = true;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -383,79 +388,93 @@ enum status_code i2c_master_write_packet_job_no_stop(
  */
 void _i2c_master_isr_handler(void)
 {
-	/* Get software module for callback handling */
-	struct i2c_master_module *module =
-			(struct i2c_master_module*)_i2c_instances;
-
-	Assert(module);
-
-	I2c *const i2c_module = module->hw;
-
-	/* Combine callback registered and enabled masks */
-	uint8_t callback_mask = module->enabled_callback &
-			module->registered_callback;
-
-	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
-		module->buffer_length = module->buffer_remaining;
-	/* Check if buffer write is done */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
-		/* Disable write interrupt flag */
-		i2c_module->TX_INTERRUPT_MASK.reg = 0;
-
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		if (!module->no_stop) {
-			/* Send stop condition */
-			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
-		} 
-
-		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
-			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
-		}
-
-	/* Continue buffer write/read */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
-		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-			_i2c_master_write(module);
-		} else {
-			_i2c_master_read(module);
-		}
-	}
-
-	/* Check if read buffer transfer is complete */
-	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_READ)) {
-		/* Disable read interrupt flag */
-		i2c_module->RX_INTERRUPT_MASK.reg = 0;
-
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		if (!module->no_stop) {
-			/* Send stop condition */
-			i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
-		}
-		
-		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
-				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
-			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
-		}
-	}
-	if (module->transfer_direction == I2C_TRANSFER_READ) {
-		if (module->hw == I2C0) {
-			NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
-		} else if (module->hw == I2C1) {
-			NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
-		} 
-	} else {
-		if (module->hw == I2C0) {
-			NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
-		} else if (module->hw == I2C1) {
-			NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
-		}
-	}
+    /* Get software module for callback handling */
+    struct i2c_master_module *module =
+            (struct i2c_master_module*)_i2c_instances;
+
+    Assert(module);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Combine callback registered and enabled masks */
+    uint8_t callback_mask = module->enabled_callback &
+            module->registered_callback;
+
+    if ((module->buffer_length <= 0) && (module->buffer_remaining > 0))
+    {
+        module->buffer_length = module->buffer_remaining;
+    /* Check if buffer write is done */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_WRITE))
+            {
+        /* Disable write interrupt flag */
+        i2c_module->TX_INTERRUPT_MASK.reg = 0;
+
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        if (!module->no_stop)
+        {
+            /* Send stop condition */
+            i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+        }
+
+        if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+        {
+            module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+        }
+
+    /* Continue buffer write/read */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0))
+    {
+        if (module->transfer_direction == I2C_TRANSFER_WRITE)
+        {
+            _i2c_master_write(module);
+        } else {
+            _i2c_master_read(module);
+        }
+    }
+
+    /* Check if read buffer transfer is complete */
+    if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_READ))
+            {
+        /* Disable read interrupt flag */
+        i2c_module->RX_INTERRUPT_MASK.reg = 0;
+
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        if (!module->no_stop)
+        {
+            /* Send stop condition */
+            i2c_module->I2C_ONBUS.reg = I2C_ONBUS_ONBUS_ENABLE_0;
+        }
+
+        if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+                && (module->transfer_direction == I2C_TRANSFER_READ))
+                {
+            module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+        }
+    }
+    if (module->transfer_direction == I2C_TRANSFER_READ)
+    {
+        if (module->hw == I2C0)
+        {
+            NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
+        } else if (module->hw == I2C1)
+        {
+            NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
+        }
+    } else {
+        if (module->hw == I2C0)
+        {
+            NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
+        } else if (module->hw == I2C1)
+        {
+            NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h
index c814f4c8adb0..391a89e88eee 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_master_interrupt.h
@@ -69,13 +69,13 @@ void _i2c_master_isr_handler(void);
 #endif
 
 void i2c_master_register_callback(
-		struct i2c_master_module *const module,
-		i2c_master_callback_t callback,
-		enum i2c_master_callback callback_type);
+        struct i2c_master_module *const module,
+        i2c_master_callback_t callback,
+        enum i2c_master_callback callback_type);
 
 void i2c_master_unregister_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type);
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -86,15 +86,15 @@ void i2c_master_unregister_callback(
  * \param[in]     callback_type  Callback type to enable
  */
 static inline void i2c_master_enable_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as enabled. */
-	module->enabled_callback |= (1 << callback_type);
+    /* Mark callback as enabled. */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -106,15 +106,15 @@ static inline void i2c_master_enable_callback(
  * \param[in]     callback_type  Callback type to disable
  */
 static inline void i2c_master_disable_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as disabled. */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled. */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /** @} */
@@ -124,22 +124,22 @@ static inline void i2c_master_disable_callback(
  * \name Read and Write, Interrupt-Driven
  * @{
  */
- 
+
 enum status_code i2c_master_read_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_read_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c
index 8e6125a05ff7..b0850a8400cc 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.c
@@ -64,17 +64,17 @@
  * \param[out] config  Pointer to configuration structure to be initiated
  */
 void i2c_slave_get_config_defaults(
-		struct i2c_slave_config *const config)
+        struct i2c_slave_config *const config)
 {
-	/* Sanity check */
-	Assert(config);
-	
-	config->clock_source    = I2C_CLK_INPUT_3;
-	config->clock_divider   = 0x10;
-	config->pin_number_pad0 = PIN_LP_GPIO_8;
-	config->pin_number_pad1 = PIN_LP_GPIO_9;
-	config->pinmux_sel_pad0 = ((PIN_LP_GPIO_8 << 16) | MUX_LP_GPIO_8_I2C0_SDA);
-	config->pinmux_sel_pad1 = ((PIN_LP_GPIO_9 << 16) | MUX_LP_GPIO_9_I2C0_SCL);
+    /* Sanity check */
+    Assert(config);
+
+    config->clock_source    = I2C_CLK_INPUT_3;
+    config->clock_divider   = 0x10;
+    config->pin_number_pad0 = PIN_LP_GPIO_8;
+    config->pin_number_pad1 = PIN_LP_GPIO_9;
+    config->pinmux_sel_pad0 = ((PIN_LP_GPIO_8 << 16) | MUX_LP_GPIO_8_I2C0_SDA);
+    config->pinmux_sel_pad1 = ((PIN_LP_GPIO_9 << 16) | MUX_LP_GPIO_9_I2C0_SCL);
 }
 
 /**
@@ -91,29 +91,29 @@ void i2c_slave_get_config_defaults(
  *                                          with set GCLK frequency
  */
 static enum status_code _i2c_slave_set_config(
-		struct i2c_slave_module *const module,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        const struct i2c_slave_config *const config)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
 
-	enum status_code status = STATUS_OK;
-	I2c *const i2c_module = (module->hw);
+    enum status_code status = STATUS_OK;
+    I2c *const i2c_module = (module->hw);
 
-	/* Set the pinmux for this i2c module. */
-	gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
-	gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
+    /* Set the pinmux for this i2c module. */
+    gpio_pinmux_cofiguration(config->pin_number_pad0, (uint16_t)(config->pinmux_sel_pad0));
+    gpio_pinmux_cofiguration(config->pin_number_pad1, (uint16_t)(config->pinmux_sel_pad1));
 
-	/* Find and set baudrate. */
-	i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
-	i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
-	/* I2C slave address */
-	i2c_module->I2C_SLAVE_ADDRESS.reg = I2C_SLAVE_ADDRESS_ADDRESS(config->address);
-	/* I2C slave mode */
-	i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_0;
-	return status;
+    /* Find and set baudrate. */
+    i2c_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+    i2c_module->I2C_CLK_DIVIDER.reg = I2C_CLK_DIVIDER_I2C_DIVIDE_RATIO(config->clock_divider);
+    /* I2C slave address */
+    i2c_module->I2C_SLAVE_ADDRESS.reg = I2C_SLAVE_ADDRESS_ADDRESS(config->address);
+    /* I2C slave mode */
+    i2c_module->I2C_MASTER_MODE.reg = I2C_MASTER_MODE_MASTER_ENABLE_0;
+    return status;
 }
 
 /**
@@ -133,59 +133,62 @@ static enum status_code _i2c_slave_set_config(
  *
  */
 enum status_code i2c_slave_init(
-		struct i2c_slave_module *const module,
-		I2c *const hw,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        I2c *const hw,
+        const struct i2c_slave_config *const config)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    module->hw = hw;
+
+    /* Sanity check arguments. */
+    if ((module == NULL) || (config == NULL))
+        return STATUS_ERR_INVALID_ARG;
 
-	module->hw = hw;
-	
-	/* Sanity check arguments. */
-	if ((module == NULL) || (config == NULL))
-		return STATUS_ERR_INVALID_ARG;
+    i2c_disable(module->hw);
 
-	i2c_disable(module->hw);
-	
-	if (module->hw == I2C0)
-		system_peripheral_reset(PERIPHERAL_I2C0_CORE);
-	else if (module->hw == I2C1) {
-		system_peripheral_reset(PERIPHERAL_I2C1_CORE);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (module->hw == I2C0)
+        system_peripheral_reset(PERIPHERAL_I2C0_CORE);
+    else if (module->hw == I2C1)
+    {
+        system_peripheral_reset(PERIPHERAL_I2C1_CORE);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Initialize values in module. */
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
-	module->buffer_length       = 0;
-	module->buffer_remaining    = 0;
-	module->buffer              = NULL;
-	module->status              = STATUS_OK;
+    /* Initialize values in module. */
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
+    module->buffer_length       = 0;
+    module->buffer_remaining    = 0;
+    module->buffer              = NULL;
+    module->status              = STATUS_OK;
 
-	_i2c_instances = (void*)module;
-	if (module->hw == I2C0) {
-		system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
-		NVIC_EnableIRQ(I2C0_RX_IRQn);
-		NVIC_EnableIRQ(I2C0_TX_IRQn);
-	} else if (module->hw == I2C1) {
-		system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
-		NVIC_EnableIRQ(I2C1_RX_IRQn);
-		NVIC_EnableIRQ(I2C1_TX_IRQn);
-	}
+    _i2c_instances = (void*)module;
+    if (module->hw == I2C0)
+    {
+        system_register_isr(RAM_ISR_TABLE_I2CRX0_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_I2CTX0_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
+        NVIC_EnableIRQ(I2C0_RX_IRQn);
+        NVIC_EnableIRQ(I2C0_TX_IRQn);
+    } else if (module->hw == I2C1)
+    {
+        system_register_isr(RAM_ISR_TABLE_I2CRX1_INDEX, (uint32_t)_i2c_slave_rx_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_I2CTX1_INDEX, (uint32_t)_i2c_slave_tx_isr_handler);
+        NVIC_EnableIRQ(I2C1_RX_IRQn);
+        NVIC_EnableIRQ(I2C1_TX_IRQn);
+    }
 #endif
 
-	/* Set config and return status. */
-	if(_i2c_slave_set_config(module, config) != STATUS_OK)
-		return STATUS_ERR_NOT_INITIALIZED;
+    /* Set config and return status. */
+    if(_i2c_slave_set_config(module, config) != STATUS_OK)
+        return STATUS_ERR_NOT_INITIALIZED;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -202,35 +205,37 @@ enum status_code i2c_slave_init(
  * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
  */
 enum status_code i2c_slave_read_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	I2c *const i2c_module = (module->hw);
-	uint16_t counter = 0;
-	uint32_t status  = 0;
-	uint16_t length  = packet->data_length;
+    I2c *const i2c_module = (module->hw);
+    uint16_t counter = 0;
+    uint32_t status  = 0;
+    uint16_t length  = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	do {
-		status = i2c_module->RECEIVE_STATUS.reg;
-		if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
-			packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
-	} while (counter < length);
+    do {
+        status = i2c_module->RECEIVE_STATUS.reg;
+        if (status & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+            packet->data[counter++] = i2c_module->RECEIVE_DATA.reg;
+    } while (counter < length);
 
-	/* Now check whether the core has sent the data out and free the bus. */
-	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
-		status = i2c_module->TRANSMIT_STATUS.reg;
-	}
+    /* Now check whether the core has sent the data out and free the bus. */
+    while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY))
+    {
+        status = i2c_module->TRANSMIT_STATUS.reg;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -247,34 +252,37 @@ enum status_code i2c_slave_read_packet_wait(
  * \retval STATUS_ERR_INVALID_ARG   Invalid argument(s) was provided
  */
 enum status_code i2c_slave_write_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	I2c *const i2c_module = (module->hw);
-	uint16_t i = 0;
-	uint32_t status = 0;
-	uint16_t length = packet->data_length;
+    I2c *const i2c_module = (module->hw);
+    uint16_t i = 0;
+    uint32_t status = 0;
+    uint16_t length = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	i2c_wait_for_idle(i2c_module);
-	
-	/* Flush the FIFO */
-	i2c_module->I2C_FLUSH.reg = 1;
+    i2c_wait_for_idle(i2c_module);
 
-	do {
-		status = i2c_module->TRANSMIT_STATUS.reg;
-		if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk) {
-			i2c_module->TRANSMIT_DATA.reg = packet->data[i++];
-		}
-	} while (i < length);
+    /* Flush the FIFO */
+    i2c_module->I2C_FLUSH.reg = 1;
 
-	/* Now check whether the core has sent the data out and its good to free the bus */
-	while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY)) {
-		status = i2c_module->TRANSMIT_STATUS.reg;
-	}
+    do {
+        status = i2c_module->TRANSMIT_STATUS.reg;
+        if (status & I2C_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_Msk)
+        {
+            i2c_module->TRANSMIT_DATA.reg = packet->data[i++];
+        }
+    } while (i < length);
 
-	return STATUS_OK;
-}
\ No newline at end of file
+    /* Now check whether the core has sent the data out and its good to free the bus */
+    while (!(status & I2C_TRANSMIT_STATUS_TX_FIFO_EMPTY))
+    {
+        status = i2c_module->TRANSMIT_STATUS.reg;
+    }
+
+    return STATUS_OK;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h
index 6a5faa91936b..fa114e952774 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave.h
@@ -66,10 +66,10 @@ extern "C" {
  * Structure to be used when transferring I<SUP>2</SUP>C slave packets.
  */
 struct i2c_slave_packet {
-	/** Length of data array */
-	uint16_t data_length;
-	/** Data array containing all data to be transferred */
-	uint8_t *data;
+    /** Length of data array */
+    uint16_t data_length;
+    /** Data array containing all data to be transferred */
+    uint8_t *data;
 };
 
 #if I2C_SLAVE_CALLBACK_MODE == true
@@ -79,24 +79,24 @@ struct i2c_slave_packet {
  * The available callback types for the I<SUP>2</SUP>C slave.
  */
 enum i2c_slave_callback {
-	/** Callback for packet write complete */
-	I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
-	/** Callback for packet read complete */
-	I2C_SLAVE_CALLBACK_READ_COMPLETE,
-	/**
-	 * Callback for read request from master - can be used to
-	 * issue a write
-	 */
-	I2C_SLAVE_CALLBACK_READ_REQUEST,
-	/**
-	 * Callback for write request from master - can be used to issue a read
-	 */
-	I2C_SLAVE_CALLBACK_WRITE_REQUEST,
-	/** Callback for error */
-	I2C_SLAVE_CALLBACK_ERROR,
+    /** Callback for packet write complete */
+    I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
+    /** Callback for packet read complete */
+    I2C_SLAVE_CALLBACK_READ_COMPLETE,
+    /**
+     * Callback for read request from master - can be used to
+     * issue a write
+     */
+    I2C_SLAVE_CALLBACK_READ_REQUEST,
+    /**
+     * Callback for write request from master - can be used to issue a read
+     */
+    I2C_SLAVE_CALLBACK_WRITE_REQUEST,
+    /** Callback for error */
+    I2C_SLAVE_CALLBACK_ERROR,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_I2C_SLAVE_CALLBACK_N,
+    /** Total number of callbacks */
+    _I2C_SLAVE_CALLBACK_N,
 #  endif
 };
 
@@ -106,7 +106,7 @@ struct i2c_slave_module;
 
 /** Callback type. */
 typedef void (*i2c_slave_callback_t)(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 #  endif
 #endif
 
@@ -116,12 +116,12 @@ typedef void (*i2c_slave_callback_t)(
  * Enum for the direction of a request.
  */
 enum i2c_slave_direction {
-	/** Read */
-	I2C_SLAVE_DIRECTION_READ,
-	/** Write */
-	I2C_SLAVE_DIRECTION_WRITE,
-	/** No direction */
-	I2C_SLAVE_DIRECTION_NONE,
+    /** Read */
+    I2C_SLAVE_DIRECTION_READ,
+    /** Write */
+    I2C_SLAVE_DIRECTION_WRITE,
+    /** No direction */
+    I2C_SLAVE_DIRECTION_NONE,
 };
 
 /**
@@ -135,32 +135,32 @@ enum i2c_slave_direction {
  */
 struct i2c_slave_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware instance initialized for the struct */
-	I2c *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** Timeout value for polled functions */
-	uint16_t buffer_timeout;
+    /** Hardware instance initialized for the struct */
+    I2c *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** Timeout value for polled functions */
+    uint16_t buffer_timeout;
 #  if I2C_SLAVE_CALLBACK_MODE == true
-	/** Pointers to callback functions */
-	volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint8_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint8_t enabled_callback;
-	/** The total number of bytes to transfer */
-	volatile uint16_t buffer_length;
-	/**
-	 * Counter used for bytes left to send in write and to count number of
-	 * obtained bytes in read
-	 */
-	uint16_t buffer_remaining;
-	/** Data buffer for packet write and read */
-	volatile uint8_t *buffer;
-	/** Save direction of request from master. 1 = read, 0 = write. */
-	volatile enum i2c_transfer_direction transfer_direction;
-	/** Status for status read back in error callback */
-	volatile enum status_code status;
+    /** Pointers to callback functions */
+    volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint8_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint8_t enabled_callback;
+    /** The total number of bytes to transfer */
+    volatile uint16_t buffer_length;
+    /**
+     * Counter used for bytes left to send in write and to count number of
+     * obtained bytes in read
+     */
+    uint16_t buffer_remaining;
+    /** Data buffer for packet write and read */
+    volatile uint8_t *buffer;
+    /** Save direction of request from master. 1 = read, 0 = write. */
+    volatile enum i2c_transfer_direction transfer_direction;
+    /** Status for status read back in error callback */
+    volatile enum status_code status;
 #  endif
 #endif
 };
@@ -174,22 +174,22 @@ struct i2c_slave_module {
  * \ref i2c_slave_get_config_defaults.
  */
 struct i2c_slave_config {
-	/** Timeout to wait for master in polled functions */
-	uint16_t buffer_timeout;
-	/** Address or upper limit of address range */
-	uint16_t address;
-	/** CLOCK INPUT to use as clock source */
-	enum i2c_clock_input clock_source;
-	/** Divide ratio used to generate the sck clock */
-	uint16_t clock_divider;
-	/** PAD0 (SDA) pin number */
-	uint32_t pin_number_pad0;
-	/** PAD0 (SDA) pinmux selection */
-	uint32_t pinmux_sel_pad0;
-	/** PAD1 (SCL) pin numer */
-	uint32_t pin_number_pad1;
-	/** PAD1 (SCL) pinmux selection */
-	uint32_t pinmux_sel_pad1;
+    /** Timeout to wait for master in polled functions */
+    uint16_t buffer_timeout;
+    /** Address or upper limit of address range */
+    uint16_t address;
+    /** CLOCK INPUT to use as clock source */
+    enum i2c_clock_input clock_source;
+    /** Divide ratio used to generate the sck clock */
+    uint16_t clock_divider;
+    /** PAD0 (SDA) pin number */
+    uint32_t pin_number_pad0;
+    /** PAD0 (SDA) pinmux selection */
+    uint32_t pinmux_sel_pad0;
+    /** PAD1 (SCL) pin numer */
+    uint32_t pin_number_pad1;
+    /** PAD1 (SCL) pinmux selection */
+    uint32_t pinmux_sel_pad1;
 };
 
 /**
@@ -198,16 +198,16 @@ struct i2c_slave_config {
  */
 
 void i2c_slave_get_config_defaults(
-		struct i2c_slave_config *const config);
+        struct i2c_slave_config *const config);
 enum status_code i2c_slave_init(struct i2c_slave_module *const module,
-		I2c *const hw,
-		const struct i2c_slave_config *const config);
+        I2c *const hw,
+        const struct i2c_slave_config *const config);
 enum status_code i2c_slave_write_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 enum status_code i2c_slave_read_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 
 /** @} */
 
@@ -216,10 +216,10 @@ enum status_code i2c_slave_read_packet_wait(
  * @{
  */
 uint32_t i2c_slave_get_status(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 void i2c_slave_clear_status(
-		struct i2c_slave_module *const module,
-		uint32_t status_flags);
+        struct i2c_slave_module *const module,
+        uint32_t status_flags);
 /** @} */
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c
index 510af6f7c602..f5df0322660f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.c
@@ -55,19 +55,19 @@ void *_i2c_instances;
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_read(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	
-	I2c *const i2c_module = module->hw;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Read byte from master and put in buffer. */
-	*(module->buffer++) = i2c_module->RECEIVE_DATA.reg;
+    I2c *const i2c_module = module->hw;
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /* Read byte from master and put in buffer. */
+    *(module->buffer++) = i2c_module->RECEIVE_DATA.reg;
+
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -77,19 +77,19 @@ static void _i2c_slave_read(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_write(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	
-	I2c *const i2c_module = module->hw;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    I2c *const i2c_module = module->hw;
 
-	/* Write byte from buffer to master */
-	i2c_module->TRANSMIT_DATA.reg = *(module->buffer++);
+    /* Write byte from buffer to master */
+    i2c_module->TRANSMIT_DATA.reg = *(module->buffer++);
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -105,20 +105,20 @@ static void _i2c_slave_write(
  * \param[in]     callback_type  Callback type to register
  */
 void i2c_slave_register_callback(
-		struct i2c_slave_module *const module,
-		i2c_slave_callback_t callback,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        i2c_slave_callback_t callback,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = callback;
+    /* Register callback. */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -131,18 +131,18 @@ void i2c_slave_register_callback(
  * \param[in]      callback_type  Callback type to unregister
  */
 void i2c_slave_unregister_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = NULL;
+    /* Register callback. */
+    module->callbacks[callback_type] = NULL;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -162,31 +162,32 @@ void i2c_slave_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_slave_read_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	I2c *const i2c_module = module->hw;
-	
-	/* Check if the I2C module is busy doing async operation. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status           = STATUS_BUSY;
-
-	/* Enable interrupts */
-	i2c_slave_rx_interrupt(i2c_module, true);
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Check if the I2C module is busy doing async operation. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    i2c_slave_rx_interrupt(i2c_module, true);
+
+    return STATUS_OK;
 }
 
 /**
@@ -206,30 +207,31 @@ enum status_code i2c_slave_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 enum status_code i2c_slave_write_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-	
-	I2c *const i2c_module = module->hw;
-	
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status			 = STATUS_BUSY;
-
-	/* Enable interrupts */
-	i2c_slave_tx_interrupt(i2c_module, true);
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    I2c *const i2c_module = module->hw;
+
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    i2c_slave_tx_interrupt(i2c_module, true);
+
+    return STATUS_OK;
 }
 
 /**
@@ -239,92 +241,110 @@ enum status_code i2c_slave_write_packet_job(
  */
 void _i2c_slave_rx_isr_handler(void)
 {
-	/* Get software module for callback handling. */
-	struct i2c_slave_module *module =
-			(struct i2c_slave_module*)_i2c_instances;
-
-	Assert(module);
-
-	I2c *const i2c_module = module->hw;
-
-	/* Combine callback registered and enabled masks. */
-	uint8_t callback_mask =
-			module->enabled_callback & module->registered_callback;
-
-	if (i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		if (!module->buffer_length && (module->buffer_length == module->buffer_remaining)) {
-			module->transfer_direction = I2C_TRANSFER_WRITE;
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
-				/* Write to master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
-			}
-		} 
-		/* Continue buffer write/read */
-		if (module->buffer_length > 0 && module->buffer_remaining > 0) {
-				_i2c_slave_read(module);
-		}
-		if (!module->buffer_remaining) {
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)) {
-				/* Write to master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
-			}
-		}
-	}
-	if ((i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_NAK)) { //&&
-			//module->transfer_direction == I2C_TRANSFER_READ) {
-		/* Received NAK, master received completed. */
-		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
-		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) {
-			module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-		}
-	}
-	
-	if (module->hw == I2C0) {
-		NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
-	} else if (module->hw == I2C1) {
-		NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
-	}
+    /* Get software module for callback handling. */
+    struct i2c_slave_module *module =
+            (struct i2c_slave_module*)_i2c_instances;
+
+    Assert(module);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Combine callback registered and enabled masks. */
+    uint8_t callback_mask =
+            module->enabled_callback & module->registered_callback;
+
+    if (i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        if (!module->buffer_length && (module->buffer_length == module->buffer_remaining))
+        {
+            module->transfer_direction = I2C_TRANSFER_WRITE;
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST))
+            {
+                /* Write to master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+            }
+        }
+        /* Continue buffer write/read */
+        if (module->buffer_length > 0 && module->buffer_remaining > 0)
+        {
+                _i2c_slave_read(module);
+        }
+        if (!module->buffer_remaining)
+        {
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
+            {
+                /* Write to master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+            }
+        }
+    }
+    if ((i2c_module->RECEIVE_STATUS.reg & I2C_RECEIVE_STATUS_NAK))
+    { /*&&*/
+            /*module->transfer_direction == I2C_TRANSFER_READ)*/
+            {
+        /* Received NAK, master received completed. */
+        i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+        if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+        {
+            module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+        }
+    }
+
+    if (module->hw == I2C0)
+    {
+        NVIC_ClearPendingIRQ(I2C0_RX_IRQn);
+    } else if (module->hw == I2C1)
+    {
+        NVIC_ClearPendingIRQ(I2C1_RX_IRQn);
+    }
 }
 
 void _i2c_slave_tx_isr_handler(void)
 {
-	/* Get software module for callback handling. */
-	struct i2c_slave_module *module =
-			(struct i2c_slave_module*)_i2c_instances;
-
-	Assert(module);
-
-	I2c *const i2c_module = module->hw;
-
-	/* Combine callback registered and enabled masks. */
-	uint8_t callback_mask =
-			module->enabled_callback & module->registered_callback;
-	
-	if (!module->buffer_length && (module->buffer_length == module->buffer_remaining)) {
-		/* First timer interrupt */
-		module->transfer_direction = I2C_TRANSFER_READ;
-		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
-			/* Write to master complete */
-			module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
-		}
-	} 
-	if (module->buffer_length > 0 && module->buffer_remaining > 0) {
-		_i2c_slave_write(module);
-	}
-	if (!module->buffer_remaining) {
-		module->status = STATUS_OK;
-		module->buffer_length = 0;
-		i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
-		if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) {
-			module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-		}
-	}
-	
-	if (module->hw == I2C0) {
-		NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
-	} else if (module->hw == I2C1) {
-		NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
-	}
-}
\ No newline at end of file
+    /* Get software module for callback handling. */
+    struct i2c_slave_module *module =
+            (struct i2c_slave_module*)_i2c_instances;
+
+    Assert(module);
+
+    I2c *const i2c_module = module->hw;
+
+    /* Combine callback registered and enabled masks. */
+    uint8_t callback_mask =
+            module->enabled_callback & module->registered_callback;
+
+    if (!module->buffer_length && (module->buffer_length == module->buffer_remaining))
+    {
+        /* First timer interrupt */
+        module->transfer_direction = I2C_TRANSFER_READ;
+        if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+        {
+            /* Write to master complete */
+            module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+        }
+    }
+    if (module->buffer_length > 0 && module->buffer_remaining > 0)
+    {
+        _i2c_slave_write(module);
+    }
+    if (!module->buffer_remaining)
+    {
+        module->status = STATUS_OK;
+        module->buffer_length = 0;
+        i2c_module->RX_INTERRUPT_MASK.bit.NAK_MASK = 0;
+        if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+        {
+            module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+        }
+    }
+
+    if (module->hw == I2C0)
+    {
+        NVIC_ClearPendingIRQ(I2C0_TX_IRQn);
+    } else if (module->hw == I2C1)
+    {
+        NVIC_ClearPendingIRQ(I2C1_TX_IRQn);
+    }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h
index aade2ecab333..a43ec7dc3c3b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2c/i2c_slave_interrupt.h
@@ -70,13 +70,13 @@ void _i2c_slave_tx_isr_handler(void);
 #endif
 
 void i2c_slave_register_callback(
-		struct i2c_slave_module *const module,
-		i2c_slave_callback_t callback,
-		enum i2c_slave_callback callback_type);
+        struct i2c_slave_module *const module,
+        i2c_slave_callback_t callback,
+        enum i2c_slave_callback callback_type);
 
 void i2c_slave_unregister_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type);
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -87,15 +87,15 @@ void i2c_slave_unregister_callback(
  * \param[in]      callback_type  Callback type to enable
  */
 static inline void i2c_slave_enable_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as enabled */
-	module->enabled_callback |= (1 << callback_type);
+    /* Mark callback as enabled */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -107,15 +107,15 @@ static inline void i2c_slave_enable_callback(
  * \param[in]      callback_type  Callback type to disable
  */
 static inline void i2c_slave_disable_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as disabled */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /** @} */
@@ -127,12 +127,12 @@ static inline void i2c_slave_disable_callback(
 
 
 enum status_code i2c_slave_read_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 
 enum status_code i2c_slave_write_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c
index bbf04620bbd2..a6ab0c6b67d3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.c
@@ -62,55 +62,59 @@
  * \retval STATUS_ERR_DENIED   Hardware module was already enabled
  */
 enum status_code i2s_init(
-		struct i2s_module *const module_inst,
-		I2s *hw)
+        struct i2s_module *const module_inst,
+        I2s *hw)
 {
-	Assert(module_inst);
-	Assert(hw);
-
-	/* Enable the user interface clock in the PM */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_I2S);
-
-	/* Status check */
-	uint32_t ctrla;
-	ctrla = module_inst->hw->CTRLA.reg;
-	if (ctrla & I2S_CTRLA_ENABLE) {
-		if (ctrla & (I2S_CTRLA_SEREN1 |
-				I2S_CTRLA_SEREN0 | I2S_CTRLA_CKEN1 | I2S_CTRLA_CKEN0)) {
-			return STATUS_BUSY;
-		} else {
-			return STATUS_ERR_DENIED;
-		}
-	}
-
-	/* Initialize module */
-	module_inst->hw = hw;
-
-	/* Initialize serializers */
+    Assert(module_inst);
+    Assert(hw);
+
+    /* Enable the user interface clock in the PM */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_I2S);
+
+    /* Status check */
+    uint32_t ctrla;
+    ctrla = module_inst->hw->CTRLA.reg;
+    if (ctrla & I2S_CTRLA_ENABLE)
+    {
+        if (ctrla & (I2S_CTRLA_SEREN1 |
+                I2S_CTRLA_SEREN0 | I2S_CTRLA_CKEN1 | I2S_CTRLA_CKEN0))
+                {
+            return STATUS_BUSY;
+        } else {
+            return STATUS_ERR_DENIED;
+        }
+    }
+
+    /* Initialize module */
+    module_inst->hw = hw;
+
+    /* Initialize serializers */
 #if I2S_CALLBACK_MODE == true
-	int i, j;
-	for (i = 0; i < 2; i ++) {
-		for (j = 0; j < I2S_SERIALIZER_CALLBACK_N; j ++) {
-			module_inst->serializer[i].callback[j] = NULL;
-		}
-		module_inst->serializer[i].registered_callback_mask = 0;
-		module_inst->serializer[i].enabled_callback_mask = 0;
-
-		module_inst->serializer[i].job_buffer = NULL;
-		module_inst->serializer[i].job_status = STATUS_OK;
-		module_inst->serializer[i].requested_words = 0;
-		module_inst->serializer[i].transferred_words = 0;
-
-		module_inst->serializer[i].mode = I2S_SERIALIZER_RECEIVE;
-		module_inst->serializer[i].data_size = I2S_DATA_SIZE_32BIT;
-	}
-
-	_i2s_instances[0] = module_inst;
-
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_I2S);
+    int i, j;
+    for (i = 0; i < 2; i ++)
+    {
+        for (j = 0; j < I2S_SERIALIZER_CALLBACK_N; j ++)
+        {
+            module_inst->serializer[i].callback[j] = NULL;
+        }
+        module_inst->serializer[i].registered_callback_mask = 0;
+        module_inst->serializer[i].enabled_callback_mask = 0;
+
+        module_inst->serializer[i].job_buffer = NULL;
+        module_inst->serializer[i].job_status = STATUS_OK;
+        module_inst->serializer[i].requested_words = 0;
+        module_inst->serializer[i].transferred_words = 0;
+
+        module_inst->serializer[i].mode = I2S_SERIALIZER_RECEIVE;
+        module_inst->serializer[i].data_size = I2S_DATA_SIZE_32BIT;
+    }
+
+    _i2s_instances[0] = module_inst;
+
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_I2S);
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 
@@ -135,100 +139,110 @@ enum status_code i2s_init(
  *                                MCK direction setting conflict
  */
 enum status_code i2s_clock_unit_set_config(
-		struct i2s_module *const module_inst,
-		const enum i2s_clock_unit clock_unit,
-		const struct i2s_clock_unit_config *config)
+        struct i2s_module *const module_inst,
+        const enum i2s_clock_unit clock_unit,
+        const struct i2s_clock_unit_config *config)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(clock_unit < I2S_CLOCK_UNIT_N);
-	Assert(config);
-
-	/* Status check */
-	uint32_t ctrla, syncbusy;
-	syncbusy = module_inst->hw->SYNCBUSY.reg;
-	ctrla = module_inst->hw->CTRLA.reg;
-
-	/* Busy ? */
-	if (syncbusy & (I2S_SYNCBUSY_CKEN0 << clock_unit)) {
-		return STATUS_BUSY;
-	}
-	/* Already enabled ? */
-	if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit)) {
-		return STATUS_ERR_DENIED;
-	}
-	/* Parameter check */
-	if (config->clock.mck_src && config->clock.mck_out_enable) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Initialize Clock Unit */
-	uint32_t clkctrl =
-		(config->clock.mck_out_invert ? I2S_CLKCTRL_MCKOUTINV : 0) |
-		(config->clock.sck_out_invert ? I2S_CLKCTRL_SCKOUTINV : 0) |
-		(config->frame.frame_sync.invert_out ? I2S_CLKCTRL_FSOUTINV : 0) |
-		(config->clock.mck_out_enable ? I2S_CLKCTRL_MCKEN : 0) |
-		(config->clock.mck_src ? I2S_CLKCTRL_MCKSEL : 0) |
-		(config->clock.sck_src ? I2S_CLKCTRL_SCKSEL : 0) |
-		(config->frame.frame_sync.invert_use ? I2S_CLKCTRL_FSINV : 0) |
-		(config->frame.frame_sync.source ? I2S_CLKCTRL_FSSEL : 0) |
-		(config->frame.data_delay ? I2S_CLKCTRL_BITDELAY : 0);
-
-	uint8_t div_val = config->clock.mck_out_div;
-	if ((div_val > 0x21) || (div_val == 0)) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		div_val --;
-	}
-	clkctrl |= I2S_CLKCTRL_MCKOUTDIV(div_val);
-
-	div_val = config->clock.sck_div;
-	if ((div_val > 0x21) || (div_val == 0)) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		div_val --;
-	}
-	clkctrl |= I2S_CLKCTRL_MCKDIV(div_val);
-
-	uint8_t number_slots = config->frame.number_slots;
-	if (number_slots > 8) {
-		return STATUS_ERR_INVALID_ARG;
-	} else if (number_slots > 0) {
-		number_slots --;
-	}
-	clkctrl |=
-			I2S_CLKCTRL_NBSLOTS(number_slots) |
-			I2S_CLKCTRL_FSWIDTH(config->frame.frame_sync.width) |
-			I2S_CLKCTRL_SLOTSIZE(config->frame.slot_size);
-
-	/* Write clock unit configurations */
-	module_inst->hw->CLKCTRL[clock_unit].reg = clkctrl;
-
-	/* Select general clock source */
-	const uint8_t i2s_gclk_ids[2] = {I2S_GCLK_ID_0, I2S_GCLK_ID_1};
-	struct system_gclk_chan_config gclk_chan_config;
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = config->clock.gclk_src;
-	system_gclk_chan_set_config(i2s_gclk_ids[clock_unit], &gclk_chan_config);
-	system_gclk_chan_enable(i2s_gclk_ids[clock_unit]);
-
-	/* Initialize pins */
-	struct system_pinmux_config pin_config;
-	system_pinmux_get_config_defaults(&pin_config);
-	if (config->mck_pin.enable) {
-		pin_config.mux_position = config->mck_pin.mux;
-		system_pinmux_pin_set_config(config->mck_pin.gpio, &pin_config);
-	}
-	if (config->sck_pin.enable) {
-		pin_config.mux_position = config->sck_pin.mux;
-		system_pinmux_pin_set_config(config->sck_pin.gpio, &pin_config);
-	}
-	if (config->fs_pin.enable) {
-		pin_config.mux_position = config->fs_pin.mux;
-		system_pinmux_pin_set_config(config->fs_pin.gpio, &pin_config);
-	}
-
-	return STATUS_OK;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(clock_unit < I2S_CLOCK_UNIT_N);
+    Assert(config);
+
+    /* Status check */
+    uint32_t ctrla, syncbusy;
+    syncbusy = module_inst->hw->SYNCBUSY.reg;
+    ctrla = module_inst->hw->CTRLA.reg;
+
+    /* Busy ? */
+    if (syncbusy & (I2S_SYNCBUSY_CKEN0 << clock_unit))
+    {
+        return STATUS_BUSY;
+    }
+    /* Already enabled ? */
+    if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit))
+    {
+        return STATUS_ERR_DENIED;
+    }
+    /* Parameter check */
+    if (config->clock.mck_src && config->clock.mck_out_enable)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Initialize Clock Unit */
+    uint32_t clkctrl =
+        (config->clock.mck_out_invert ? I2S_CLKCTRL_MCKOUTINV : 0) |
+        (config->clock.sck_out_invert ? I2S_CLKCTRL_SCKOUTINV : 0) |
+        (config->frame.frame_sync.invert_out ? I2S_CLKCTRL_FSOUTINV : 0) |
+        (config->clock.mck_out_enable ? I2S_CLKCTRL_MCKEN : 0) |
+        (config->clock.mck_src ? I2S_CLKCTRL_MCKSEL : 0) |
+        (config->clock.sck_src ? I2S_CLKCTRL_SCKSEL : 0) |
+        (config->frame.frame_sync.invert_use ? I2S_CLKCTRL_FSINV : 0) |
+        (config->frame.frame_sync.source ? I2S_CLKCTRL_FSSEL : 0) |
+        (config->frame.data_delay ? I2S_CLKCTRL_BITDELAY : 0);
+
+    uint8_t div_val = config->clock.mck_out_div;
+    if ((div_val > 0x21) || (div_val == 0))
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        div_val --;
+    }
+    clkctrl |= I2S_CLKCTRL_MCKOUTDIV(div_val);
+
+    div_val = config->clock.sck_div;
+    if ((div_val > 0x21) || (div_val == 0))
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        div_val --;
+    }
+    clkctrl |= I2S_CLKCTRL_MCKDIV(div_val);
+
+    uint8_t number_slots = config->frame.number_slots;
+    if (number_slots > 8)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else if (number_slots > 0)
+    {
+        number_slots --;
+    }
+    clkctrl |=
+            I2S_CLKCTRL_NBSLOTS(number_slots) |
+            I2S_CLKCTRL_FSWIDTH(config->frame.frame_sync.width) |
+            I2S_CLKCTRL_SLOTSIZE(config->frame.slot_size);
+
+    /* Write clock unit configurations */
+    module_inst->hw->CLKCTRL[clock_unit].reg = clkctrl;
+
+    /* Select general clock source */
+    const uint8_t i2s_gclk_ids[2] = {I2S_GCLK_ID_0, I2S_GCLK_ID_1};
+    struct system_gclk_chan_config gclk_chan_config;
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = config->clock.gclk_src;
+    system_gclk_chan_set_config(i2s_gclk_ids[clock_unit], &gclk_chan_config);
+    system_gclk_chan_enable(i2s_gclk_ids[clock_unit]);
+
+    /* Initialize pins */
+    struct system_pinmux_config pin_config;
+    system_pinmux_get_config_defaults(&pin_config);
+    if (config->mck_pin.enable)
+    {
+        pin_config.mux_position = config->mck_pin.mux;
+        system_pinmux_pin_set_config(config->mck_pin.gpio, &pin_config);
+    }
+    if (config->sck_pin.enable)
+    {
+        pin_config.mux_position = config->sck_pin.mux;
+        system_pinmux_pin_set_config(config->sck_pin.gpio, &pin_config);
+    }
+    if (config->fs_pin.enable)
+    {
+        pin_config.mux_position = config->fs_pin.mux;
+        system_pinmux_pin_set_config(config->fs_pin.gpio, &pin_config);
+    }
+
+    return STATUS_OK;
 }
 
 
@@ -251,75 +265,79 @@ enum status_code i2s_clock_unit_set_config(
  * \retval STATUS_ERR_DENIED   Hardware module was already enabled
  */
 enum status_code i2s_serializer_set_config(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const struct i2s_serializer_config *config)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const struct i2s_serializer_config *config)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-	Assert(config);
-
-	/* Status check */
-	uint32_t ctrla, syncbusy;
-	syncbusy = module_inst->hw->SYNCBUSY.reg;
-	ctrla = module_inst->hw->CTRLA.reg;
-
-	/* Busy ? */
-	if (syncbusy & ((I2S_SYNCBUSY_SEREN0 | I2S_SYNCBUSY_DATA0) << serializer)) {
-		return STATUS_BUSY;
-	}
-	/* Already enabled ? */
-	if (ctrla & (I2S_CTRLA_CKEN0 << serializer)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Initialize Serializer */
-	uint32_t serctrl =
-			(config->loop_back ? I2S_SERCTRL_RXLOOP : 0) |
-			(config->dma_usage ? I2S_SERCTRL_DMA : 0) |
-			(config->mono_mode ? I2S_SERCTRL_MONO : 0) |
-			(config->disable_data_slot[7] ? I2S_SERCTRL_SLOTDIS7 : 0) |
-			(config->disable_data_slot[6] ? I2S_SERCTRL_SLOTDIS6 : 0) |
-			(config->disable_data_slot[5] ? I2S_SERCTRL_SLOTDIS5 : 0) |
-			(config->disable_data_slot[4] ? I2S_SERCTRL_SLOTDIS4 : 0) |
-			(config->disable_data_slot[3] ? I2S_SERCTRL_SLOTDIS3 : 0) |
-			(config->disable_data_slot[2] ? I2S_SERCTRL_SLOTDIS2 : 0) |
-			(config->disable_data_slot[1] ? I2S_SERCTRL_SLOTDIS1 : 0) |
-			(config->disable_data_slot[0] ? I2S_SERCTRL_SLOTDIS0 : 0) |
-			(config->transfer_lsb_first ? I2S_SERCTRL_BITREV : 0) |
-			(config->data_adjust_left_in_word ? I2S_SERCTRL_WORDADJ : 0) |
-			(config->data_adjust_left_in_slot ? I2S_SERCTRL_SLOTADJ : 0) |
-			(config->data_padding ? I2S_SERCTRL_TXSAME : 0);
-
-	if (config->clock_unit < I2S_CLOCK_UNIT_N) {
-		serctrl |= (config->clock_unit ? I2S_SERCTRL_CLKSEL : 0);
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	serctrl |=
-			I2S_SERCTRL_SERMODE(config->mode) |
-			I2S_SERCTRL_TXDEFAULT(config->line_default_state) |
-			I2S_SERCTRL_DATASIZE(config->data_size) |
-			I2S_SERCTRL_EXTEND(config->bit_padding);
-
-	/* Write Serializer configuration */
-	module_inst->hw->SERCTRL[serializer].reg = serctrl;
-
-	/* Initialize pins */
-	struct system_pinmux_config pin_config;
-	system_pinmux_get_config_defaults(&pin_config);
-	if (config->data_pin.enable) {
-		pin_config.mux_position = config->data_pin.mux;
-		system_pinmux_pin_set_config(config->data_pin.gpio, &pin_config);
-	}
-
-	/* Save configure */
-	module_inst->serializer[serializer].mode = config->mode;
-	module_inst->serializer[serializer].data_size = config->data_size;
-
-	return STATUS_OK;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+    Assert(config);
+
+    /* Status check */
+    uint32_t ctrla, syncbusy;
+    syncbusy = module_inst->hw->SYNCBUSY.reg;
+    ctrla = module_inst->hw->CTRLA.reg;
+
+    /* Busy ? */
+    if (syncbusy & ((I2S_SYNCBUSY_SEREN0 | I2S_SYNCBUSY_DATA0) << serializer))
+    {
+        return STATUS_BUSY;
+    }
+    /* Already enabled ? */
+    if (ctrla & (I2S_CTRLA_CKEN0 << serializer))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Initialize Serializer */
+    uint32_t serctrl =
+            (config->loop_back ? I2S_SERCTRL_RXLOOP : 0) |
+            (config->dma_usage ? I2S_SERCTRL_DMA : 0) |
+            (config->mono_mode ? I2S_SERCTRL_MONO : 0) |
+            (config->disable_data_slot[7] ? I2S_SERCTRL_SLOTDIS7 : 0) |
+            (config->disable_data_slot[6] ? I2S_SERCTRL_SLOTDIS6 : 0) |
+            (config->disable_data_slot[5] ? I2S_SERCTRL_SLOTDIS5 : 0) |
+            (config->disable_data_slot[4] ? I2S_SERCTRL_SLOTDIS4 : 0) |
+            (config->disable_data_slot[3] ? I2S_SERCTRL_SLOTDIS3 : 0) |
+            (config->disable_data_slot[2] ? I2S_SERCTRL_SLOTDIS2 : 0) |
+            (config->disable_data_slot[1] ? I2S_SERCTRL_SLOTDIS1 : 0) |
+            (config->disable_data_slot[0] ? I2S_SERCTRL_SLOTDIS0 : 0) |
+            (config->transfer_lsb_first ? I2S_SERCTRL_BITREV : 0) |
+            (config->data_adjust_left_in_word ? I2S_SERCTRL_WORDADJ : 0) |
+            (config->data_adjust_left_in_slot ? I2S_SERCTRL_SLOTADJ : 0) |
+            (config->data_padding ? I2S_SERCTRL_TXSAME : 0);
+
+    if (config->clock_unit < I2S_CLOCK_UNIT_N)
+    {
+        serctrl |= (config->clock_unit ? I2S_SERCTRL_CLKSEL : 0);
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    serctrl |=
+            I2S_SERCTRL_SERMODE(config->mode) |
+            I2S_SERCTRL_TXDEFAULT(config->line_default_state) |
+            I2S_SERCTRL_DATASIZE(config->data_size) |
+            I2S_SERCTRL_EXTEND(config->bit_padding);
+
+    /* Write Serializer configuration */
+    module_inst->hw->SERCTRL[serializer].reg = serctrl;
+
+    /* Initialize pins */
+    struct system_pinmux_config pin_config;
+    system_pinmux_get_config_defaults(&pin_config);
+    if (config->data_pin.enable)
+    {
+        pin_config.mux_position = config->data_pin.mux;
+        system_pinmux_pin_set_config(config->data_pin.gpio, &pin_config);
+    }
+
+    /* Save configure */
+    module_inst->serializer[serializer].mode = config->mode;
+    module_inst->serializer[serializer].data_size = config->data_size;
+
+    return STATUS_OK;
 }
 
 
@@ -342,46 +360,55 @@ enum status_code i2s_serializer_set_config(
  *                                         read
  */
 uint32_t i2s_get_status(
-		const struct i2s_module *const module_inst)
+        const struct i2s_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint32_t intflag = module_inst->hw->INTFLAG.reg;
-	uint32_t status;
-	if (module_inst->hw->SYNCBUSY.reg) {
-		status = I2S_STATUS_SYNC_BUSY;
-	} else {
-		status = 0;
-	}
-	if (intflag & I2S_INTFLAG_TXUR0) {
-		status |= I2S_STATUS_TRANSMIT_UNDERRUN(0);
-	}
-	if (intflag & I2S_INTFLAG_TXUR1) {
-		status |= I2S_STATUS_TRANSMIT_UNDERRUN(1);
-	}
-	if ((intflag & I2S_INTFLAG_TXRDY0) &&
-		!module_inst->hw->SYNCBUSY.bit.DATA0) {
-		status |= I2S_STATUS_TRANSMIT_READY(0);
-	}
-	if ((intflag & I2S_INTFLAG_TXRDY1) &&
-		!module_inst->hw->SYNCBUSY.bit.DATA1) {
-		status |= I2S_STATUS_TRANSMIT_READY(1);
-	}
-	if (intflag & I2S_INTFLAG_RXOR0) {
-		status |= I2S_STATUS_RECEIVE_OVERRUN(0);
-	}
-	if (intflag & I2S_INTFLAG_RXOR1) {
-		status |= I2S_STATUS_RECEIVE_OVERRUN(1);
-	}
-	if (intflag & I2S_INTFLAG_RXRDY0) {
-		status |= I2S_STATUS_RECEIVE_READY(0);
-	}
-	if (intflag & I2S_INTFLAG_RXRDY1) {
-		status |= I2S_STATUS_RECEIVE_READY(1);
-	}
-	return status;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint32_t intflag = module_inst->hw->INTFLAG.reg;
+    uint32_t status;
+    if (module_inst->hw->SYNCBUSY.reg)
+    {
+        status = I2S_STATUS_SYNC_BUSY;
+    } else {
+        status = 0;
+    }
+    if (intflag & I2S_INTFLAG_TXUR0)
+    {
+        status |= I2S_STATUS_TRANSMIT_UNDERRUN(0);
+    }
+    if (intflag & I2S_INTFLAG_TXUR1)
+    {
+        status |= I2S_STATUS_TRANSMIT_UNDERRUN(1);
+    }
+    if ((intflag & I2S_INTFLAG_TXRDY0) &&
+        !module_inst->hw->SYNCBUSY.bit.DATA0)
+        {
+        status |= I2S_STATUS_TRANSMIT_READY(0);
+    }
+    if ((intflag & I2S_INTFLAG_TXRDY1) &&
+        !module_inst->hw->SYNCBUSY.bit.DATA1)
+        {
+        status |= I2S_STATUS_TRANSMIT_READY(1);
+    }
+    if (intflag & I2S_INTFLAG_RXOR0)
+    {
+        status |= I2S_STATUS_RECEIVE_OVERRUN(0);
+    }
+    if (intflag & I2S_INTFLAG_RXOR1)
+    {
+        status |= I2S_STATUS_RECEIVE_OVERRUN(1);
+    }
+    if (intflag & I2S_INTFLAG_RXRDY0)
+    {
+        status |= I2S_STATUS_RECEIVE_READY(0);
+    }
+    if (intflag & I2S_INTFLAG_RXRDY1)
+    {
+        status |= I2S_STATUS_RECEIVE_READY(1);
+    }
+    return status;
 }
 
 /**
@@ -393,40 +420,48 @@ uint32_t i2s_get_status(
  * \param[in] status        Bitmask of \c I2S_STATUS_* flags to clear
  */
 void i2s_clear_status(
-		const struct i2s_module *const module_inst,
-		uint32_t status)
+        const struct i2s_module *const module_inst,
+        uint32_t status)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint32_t intflag = 0;
-
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
-		intflag = I2S_INTFLAG_TXUR0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
-		intflag = I2S_INTFLAG_TXUR1;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
-		intflag = I2S_INTFLAG_TXRDY0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
-		intflag = I2S_INTFLAG_TXRDY1;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
-		intflag = I2S_INTFLAG_RXOR0;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
-		intflag = I2S_INTFLAG_RXOR1;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(0)) {
-		intflag = I2S_INTFLAG_RXRDY0;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(1)) {
-		intflag = I2S_INTFLAG_RXRDY1;
-	}
-	module_inst->hw->INTFLAG.reg = intflag;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint32_t intflag = 0;
+
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0))
+    {
+        intflag = I2S_INTFLAG_TXUR0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1))
+    {
+        intflag = I2S_INTFLAG_TXUR1;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(0))
+    {
+        intflag = I2S_INTFLAG_TXRDY0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(1))
+    {
+        intflag = I2S_INTFLAG_TXRDY1;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(0))
+    {
+        intflag = I2S_INTFLAG_RXOR0;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(1))
+    {
+        intflag = I2S_INTFLAG_RXOR1;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(0))
+    {
+        intflag = I2S_INTFLAG_RXRDY0;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(1))
+    {
+        intflag = I2S_INTFLAG_RXRDY1;
+    }
+    module_inst->hw->INTFLAG.reg = intflag;
 }
 
 /**
@@ -443,45 +478,54 @@ void i2s_clear_status(
  * \retval STATUS_ERR_INVALID_ARG Status with no interrupt is passed
  */
 enum status_code i2s_enable_status_interrupt(
-		struct i2s_module *const module_inst,
-		uint32_t status)
+        struct i2s_module *const module_inst,
+        uint32_t status)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	/* No sync busy interrupt */
-	if (status & I2S_STATUS_SYNC_BUSY) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	Assert(module_inst->hw);
-
-	uint32_t intflag = 0;
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
-		intflag = I2S_INTFLAG_TXUR0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
-		intflag = I2S_INTFLAG_TXUR1;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
-		intflag = I2S_INTFLAG_TXRDY0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
-		intflag = I2S_INTFLAG_TXRDY1;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
-		intflag = I2S_INTFLAG_RXOR0;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
-		intflag = I2S_INTFLAG_RXOR1;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(0)) {
-		intflag = I2S_INTFLAG_RXRDY0;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(1)) {
-		intflag = I2S_INTFLAG_RXRDY1;
-	}
-	module_inst->hw->INTENSET.reg = intflag;
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    /* No sync busy interrupt */
+    if (status & I2S_STATUS_SYNC_BUSY)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    Assert(module_inst->hw);
+
+    uint32_t intflag = 0;
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0))
+    {
+        intflag = I2S_INTFLAG_TXUR0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1))
+    {
+        intflag = I2S_INTFLAG_TXUR1;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(0))
+    {
+        intflag = I2S_INTFLAG_TXRDY0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(1))
+    {
+        intflag = I2S_INTFLAG_TXRDY1;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(0))
+    {
+        intflag = I2S_INTFLAG_RXOR0;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(1))
+    {
+        intflag = I2S_INTFLAG_RXOR1;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(0))
+    {
+        intflag = I2S_INTFLAG_RXRDY0;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(1))
+    {
+        intflag = I2S_INTFLAG_RXRDY1;
+    }
+    module_inst->hw->INTENSET.reg = intflag;
+    return STATUS_OK;
 }
 
 /**
@@ -493,39 +537,47 @@ enum status_code i2s_enable_status_interrupt(
  * \param[in] status Status interrupts to disable
  */
 void i2s_disable_status_interrupt(
-		struct i2s_module *const module_inst,
-		uint32_t status)
+        struct i2s_module *const module_inst,
+        uint32_t status)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint32_t intflag = 0;
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) {
-		intflag = I2S_INTFLAG_TXUR0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) {
-		intflag = I2S_INTFLAG_TXUR1;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(0)) {
-		intflag = I2S_INTFLAG_TXRDY0;
-	}
-	if (status & I2S_STATUS_TRANSMIT_READY(1)) {
-		intflag = I2S_INTFLAG_TXRDY1;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) {
-		intflag = I2S_INTFLAG_RXOR0;
-	}
-	if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) {
-		intflag = I2S_INTFLAG_RXOR1;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(0)) {
-		intflag = I2S_INTFLAG_RXRDY0;
-	}
-	if (status & I2S_STATUS_RECEIVE_READY(1)) {
-		intflag = I2S_INTFLAG_RXRDY1;
-	}
-	module_inst->hw->INTENCLR.reg = intflag;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint32_t intflag = 0;
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0))
+    {
+        intflag = I2S_INTFLAG_TXUR0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1))
+    {
+        intflag = I2S_INTFLAG_TXUR1;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(0))
+    {
+        intflag = I2S_INTFLAG_TXRDY0;
+    }
+    if (status & I2S_STATUS_TRANSMIT_READY(1))
+    {
+        intflag = I2S_INTFLAG_TXRDY1;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(0))
+    {
+        intflag = I2S_INTFLAG_RXOR0;
+    }
+    if (status & I2S_STATUS_RECEIVE_OVERRUN(1))
+    {
+        intflag = I2S_INTFLAG_RXOR1;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(0))
+    {
+        intflag = I2S_INTFLAG_RXRDY0;
+    }
+    if (status & I2S_STATUS_RECEIVE_READY(1))
+    {
+        intflag = I2S_INTFLAG_RXRDY1;
+    }
+    module_inst->hw->INTENCLR.reg = intflag;
 }
 
 
@@ -544,94 +596,110 @@ void i2s_disable_status_interrupt(
  * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
  */
 enum status_code i2s_serializer_write_buffer_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer,
-		void *buffer, uint32_t size)
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer,
+        void *buffer, uint32_t size)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-	Assert(buffer);
-
-	if (size == 0) {
-		return STATUS_OK;
-	}
-
-	uint8_t data_size = 1; /* number of bytes */
-	struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
-			&module_inst->serializer[serializer];
-
-	/* Check buffer */
-	switch(data_module->data_size) {
-	case I2S_DATA_SIZE_32BIT:
-	case I2S_DATA_SIZE_24BIT:
-	case I2S_DATA_SIZE_20BIT:
-	case I2S_DATA_SIZE_18BIT:
-		if ((uint32_t)buffer & 0x3) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		data_size = 4;
-		break;
-	case I2S_DATA_SIZE_16BIT:
-	case I2S_DATA_SIZE_16BIT_COMPACT:
-		if ((uint32_t)buffer & 0x1) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		data_size = 2;
-		break;
-	default:
-		break;
-	}
-
-	/* Check status */
-	if (!(module_inst->hw->CTRLA.reg &
-		(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Write */
-	uint32_t i;
-	uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
-	uint32_t ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
-	if (4 == data_size) {
-		uint32_t *p32 = (uint32_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Tx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			module_inst->hw->DATA[serializer].reg = p32[i];
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	} else if (2 == data_size) {
-		uint16_t *p16 = (uint16_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Tx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			module_inst->hw->DATA[serializer].reg = p16[i];
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	} else {
-		uint8_t *p8 = (uint8_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Tx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			module_inst->hw->DATA[serializer].reg = p8[i];
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	}
-
-	return STATUS_OK;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+    Assert(buffer);
+
+    if (size == 0)
+    {
+        return STATUS_OK;
+    }
+
+    uint8_t data_size = 1; /* number of bytes */
+    struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
+            &module_inst->serializer[serializer];
+
+    /* Check buffer */
+    switch(data_module->data_size)
+    {
+    case I2S_DATA_SIZE_32BIT:
+    case I2S_DATA_SIZE_24BIT:
+    case I2S_DATA_SIZE_20BIT:
+    case I2S_DATA_SIZE_18BIT:
+        if ((uint32_t)buffer & 0x3)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        data_size = 4;
+        break;
+    case I2S_DATA_SIZE_16BIT:
+    case I2S_DATA_SIZE_16BIT_COMPACT:
+        if ((uint32_t)buffer & 0x1)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        data_size = 2;
+        break;
+    default:
+        break;
+    }
+
+    /* Check status */
+    if (!(module_inst->hw->CTRLA.reg &
+        (I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer))))
+        {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Write */
+    uint32_t i;
+    uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+    uint32_t ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
+    if (4 == data_size)
+    {
+        uint32_t *p32 = (uint32_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Tx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            module_inst->hw->DATA[serializer].reg = p32[i];
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    } else if (2 == data_size)
+    {
+        uint16_t *p16 = (uint16_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Tx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            module_inst->hw->DATA[serializer].reg = p16[i];
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    } else {
+        uint8_t *p8 = (uint8_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Tx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            module_inst->hw->DATA[serializer].reg = p8[i];
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -649,102 +717,122 @@ enum status_code i2s_serializer_write_buffer_wait(
  * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
  */
 enum status_code i2s_serializer_read_buffer_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer,
-		void *buffer, uint32_t size)
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer,
+        void *buffer, uint32_t size)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	if (size == 0) {
-		return STATUS_OK;
-	}
-
-	uint8_t data_size = 1; /* number of bytes */
-	struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
-			&module_inst->serializer[serializer];
-
-	/* Check buffer */
-	switch(data_module->data_size) {
-		case I2S_DATA_SIZE_32BIT:
-		case I2S_DATA_SIZE_24BIT:
-		case I2S_DATA_SIZE_20BIT:
-		case I2S_DATA_SIZE_18BIT:
-		if ((uint32_t)buffer & 0x3) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		data_size = 4;
-		break;
-		case I2S_DATA_SIZE_16BIT:
-		case I2S_DATA_SIZE_16BIT_COMPACT:
-		if ((uint32_t)buffer & 0x1) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		data_size = 2;
-		break;
-	default:
-		break;
-	}
-
-	/* Check status */
-	if (!(module_inst->hw->CTRLA.reg &
-		(I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Read */
-	uint32_t i;
-	uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
-	uint32_t ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
-	if (buffer == NULL) {
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Rx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			module_inst->hw->DATA[serializer].reg;
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	}
-	else if (4 == data_size) {
-		uint32_t *p32 = (uint32_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Rx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			p32[i] = module_inst->hw->DATA[serializer].reg;
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	} else if (2 == data_size) {
-		uint16_t *p16 = (uint16_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Rx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			p16[i] = module_inst->hw->DATA[serializer].reg;
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	} else {
-		uint8_t *p8 = (uint8_t*)buffer;
-		for (i = 0; i < size; i ++) {
-			while(!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-				/* Wait Tx ready */
-			}
-			while(module_inst->hw->SYNCBUSY.reg & sync_bit) {
-				/* Wait Sync */
-			}
-			p8[i] = module_inst->hw->DATA[serializer].reg;
-			module_inst->hw->INTFLAG.reg = ready_bit;
-		}
-	}
-
-	return STATUS_OK;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    if (size == 0)
+    {
+        return STATUS_OK;
+    }
+
+    uint8_t data_size = 1; /* number of bytes */
+    struct i2s_serializer_module *data_module = (struct i2s_serializer_module *)
+            &module_inst->serializer[serializer];
+
+    /* Check buffer */
+    switch(data_module->data_size)
+    {
+        case I2S_DATA_SIZE_32BIT:
+        case I2S_DATA_SIZE_24BIT:
+        case I2S_DATA_SIZE_20BIT:
+        case I2S_DATA_SIZE_18BIT:
+        if ((uint32_t)buffer & 0x3)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        data_size = 4;
+        break;
+        case I2S_DATA_SIZE_16BIT:
+        case I2S_DATA_SIZE_16BIT_COMPACT:
+        if ((uint32_t)buffer & 0x1)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        data_size = 2;
+        break;
+    default:
+        break;
+    }
+
+    /* Check status */
+    if (!(module_inst->hw->CTRLA.reg &
+        (I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer))))
+        {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Read */
+    uint32_t i;
+    uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+    uint32_t ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
+    if (buffer == NULL)
+    {
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Rx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            module_inst->hw->DATA[serializer].reg;
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    }
+    else if (4 == data_size)
+    {
+        uint32_t *p32 = (uint32_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Rx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            p32[i] = module_inst->hw->DATA[serializer].reg;
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    } else if (2 == data_size)
+    {
+        uint16_t *p16 = (uint16_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Rx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            p16[i] = module_inst->hw->DATA[serializer].reg;
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    } else {
+        uint8_t *p8 = (uint8_t*)buffer;
+        for (i = 0; i < size; i ++)
+        {
+            while(!(module_inst->hw->INTFLAG.reg & ready_bit))
+            {
+                /* Wait Tx ready */
+            }
+            while(module_inst->hw->SYNCBUSY.reg & sync_bit)
+            {
+                /* Wait Sync */
+            }
+            p8[i] = module_inst->hw->DATA[serializer].reg;
+            module_inst->hw->INTFLAG.reg = ready_bit;
+        }
+    }
+
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h
index 0e965d8d3a94..1ca9059efcd3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s.h
@@ -209,12 +209,12 @@
  * the FS width, the FS to data bits delay, etc., the module is able to handle
  * I<SUP>2</SUP>S compliant data stream.
  *
- * Also the Serializer can receive PDM format data stream, which allows the 
+ * Also the Serializer can receive PDM format data stream, which allows the
  * I<SUP>2</SUP>S module receive 1 PDM data on each SCK edge.
  *
  * \subsubsection asfdoc_sam0_i2s_module_overview_data_i2s I2S Stream Reception/Transmission
  *
- * For 2-channel I<SUP>2</SUP>S compliant data stream format the I<SUP>2</SUP>S 
+ * For 2-channel I<SUP>2</SUP>S compliant data stream format the I<SUP>2</SUP>S
  * module uses the FS line as word select (WS) signal and will send left channel
  * data word on low WS level and right channel data word on high WS level as
  * specified in the I<SUP>2</SUP>S standard. The supported word sizes are 8-,
@@ -350,18 +350,18 @@ struct i2s_module;
 
 /** Type of the callback functions. */
 typedef void (*i2s_serializer_callback_t)
-		(struct i2s_module *const module);
+        (struct i2s_module *const module);
 
 /**
  * \brief I<SUP>2</SUP>S Serializer Callback enum
  */
 enum i2s_serializer_callback {
-	/** Callback for buffer read/write finished */
-	I2S_SERIALIZER_CALLBACK_BUFFER_DONE,
-	/** Callback for Serializer overrun/underrun */
-	I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN,
+    /** Callback for buffer read/write finished */
+    I2S_SERIALIZER_CALLBACK_BUFFER_DONE,
+    /** Callback for Serializer overrun/underrun */
+    I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN,
 #  if !defined(__DOXYGEN__)
-	I2S_SERIALIZER_CALLBACK_N
+    I2S_SERIALIZER_CALLBACK_N
 #  endif
 };
 
@@ -393,229 +393,229 @@ enum i2s_serializer_callback {
  * Master Clock (MCK) source selection.
  */
 enum i2s_master_clock_source {
-	/** Master Clock (MCK) is from general clock */
-	I2S_MASTER_CLOCK_SOURCE_GCLK,
-	/** Master Clock (MCK) is from MCK input pin */
-	I2S_MASTER_CLOCK_SOURCE_MCKPIN
+    /** Master Clock (MCK) is from general clock */
+    I2S_MASTER_CLOCK_SOURCE_GCLK,
+    /** Master Clock (MCK) is from MCK input pin */
+    I2S_MASTER_CLOCK_SOURCE_MCKPIN
 };
 
 /**
  * Serial Clock (SCK) source selection.
  */
 enum i2s_serial_clock_source {
-	/** Serial Clock (SCK) is divided from Master Clock */
-	I2S_SERIAL_CLOCK_SOURCE_MCKDIV,
-	/** Serial Clock (SCK) is input from SCK input pin */
-	I2S_SERIAL_CLOCK_SOURCE_SCKPIN
+    /** Serial Clock (SCK) is divided from Master Clock */
+    I2S_SERIAL_CLOCK_SOURCE_MCKDIV,
+    /** Serial Clock (SCK) is input from SCK input pin */
+    I2S_SERIAL_CLOCK_SOURCE_SCKPIN
 };
 
 /**
  * Data delay from Frame Sync (FS).
  */
 enum i2s_data_delay {
-	/** Left Justified (no delay) */
-	I2S_DATA_DELAY_0,
-	/** I<SUP>2</SUP>S data delay (1-bit delay) */
-	I2S_DATA_DELAY_1,
-	/** Left Justified (no delay) */
-	I2S_DATA_DELAY_LEFT_JUSTIFIED = I2S_DATA_DELAY_0,
-	/** I<SUP>2</SUP>S data delay (1-bit delay) */
-	I2S_DATA_DELAY_I2S = I2S_DATA_DELAY_1
+    /** Left Justified (no delay) */
+    I2S_DATA_DELAY_0,
+    /** I<SUP>2</SUP>S data delay (1-bit delay) */
+    I2S_DATA_DELAY_1,
+    /** Left Justified (no delay) */
+    I2S_DATA_DELAY_LEFT_JUSTIFIED = I2S_DATA_DELAY_0,
+    /** I<SUP>2</SUP>S data delay (1-bit delay) */
+    I2S_DATA_DELAY_I2S = I2S_DATA_DELAY_1
 };
 
 /**
  * Frame Sync (FS) source.
  */
 enum i2s_frame_sync_source {
-	/** Frame Sync (FS) is divided from I<SUP>2</SUP>S Serial Clock */
-	I2S_FRAME_SYNC_SOURCE_SCKDIV,
-	/** Frame Sync (FS) is input from FS input pin */
-	I2S_FRAME_SYNC_SOURCE_FSPIN
+    /** Frame Sync (FS) is divided from I<SUP>2</SUP>S Serial Clock */
+    I2S_FRAME_SYNC_SOURCE_SCKDIV,
+    /** Frame Sync (FS) is input from FS input pin */
+    I2S_FRAME_SYNC_SOURCE_FSPIN
 };
 
 /**
  * Frame Sync (FS) output pulse width.
  */
 enum i2s_frame_sync_width {
-	/** Frame Sync (FS) Pulse is one slot width */
-	I2S_FRAME_SYNC_WIDTH_SLOT,
-	/** Frame Sync (FS) Pulse is half a frame width */
-	I2S_FRAME_SYNC_WIDTH_HALF_FRAME,
-	/** Frame Sync (FS) Pulse is one bit width */
-	I2S_FRAME_SYNC_WIDTH_BIT,
-	/** 1-bit wide Frame Sync (FS) per Data sample, only used when Data transfer
-	 *  is requested */
-	I2S_FRAME_SYNC_WIDTH_BURST
+    /** Frame Sync (FS) Pulse is one slot width */
+    I2S_FRAME_SYNC_WIDTH_SLOT,
+    /** Frame Sync (FS) Pulse is half a frame width */
+    I2S_FRAME_SYNC_WIDTH_HALF_FRAME,
+    /** Frame Sync (FS) Pulse is one bit width */
+    I2S_FRAME_SYNC_WIDTH_BIT,
+    /** 1-bit wide Frame Sync (FS) per Data sample, only used when Data transfer
+     *  is requested */
+    I2S_FRAME_SYNC_WIDTH_BURST
 };
 
 /**
  * Time Slot Size in number of I<SUP>2</SUP>S serial clocks (bits).
  */
 enum i2s_slot_size {
-	/** 8-bit slot */
-	I2S_SLOT_SIZE_8_BIT,
-	/** 16-bit slot */
-	I2S_SLOT_SIZE_16_BIT,
-	/** 24-bit slot */
-	I2S_SLOT_SIZE_24_BIT,
-	/** 32-bit slot */
-	I2S_SLOT_SIZE_32_BIT
+    /** 8-bit slot */
+    I2S_SLOT_SIZE_8_BIT,
+    /** 16-bit slot */
+    I2S_SLOT_SIZE_16_BIT,
+    /** 24-bit slot */
+    I2S_SLOT_SIZE_24_BIT,
+    /** 32-bit slot */
+    I2S_SLOT_SIZE_32_BIT
 };
 
 /**
  * DMA channels usage for I<SUP>2</SUP>S.
  */
 enum i2s_dma_usage {
-	/** Single DMA channel for all I<SUP>2</SUP>S channels */
-	I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL,
-	/** One DMA channel per data channel */
-	I2S_DMA_USE_ONE_CHANNEL_PER_DATA_CHANNEL
+    /** Single DMA channel for all I<SUP>2</SUP>S channels */
+    I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL,
+    /** One DMA channel per data channel */
+    I2S_DMA_USE_ONE_CHANNEL_PER_DATA_CHANNEL
 };
 
 /**
  * I<SUP>2</SUP>S data format, to extend mono data to two channels.
  */
 enum i2s_data_format {
-	/** Normal mode, keep data to its right channel */
-	I2S_DATA_FORMAT_STEREO,
-	/** Assume input is mono data for left channel, the data is duplicated to
-	 *  right channel */
-	I2S_DATA_FORMAT_MONO
+    /** Normal mode, keep data to its right channel */
+    I2S_DATA_FORMAT_STEREO,
+    /** Assume input is mono data for left channel, the data is duplicated to
+     *  right channel */
+    I2S_DATA_FORMAT_MONO
 };
 
 /**
  * I<SUP>2</SUP>S data bit order.
  */
 enum i2s_bit_order {
-	/** Transfer Data Most Significant Bit first 
-	 * (Default for I<SUP>2</SUP>S protocol) 
-	 */
-	I2S_BIT_ORDER_MSB_FIRST,
-	/** Transfer Data Least Significant Bit first */
-	I2S_BIT_ORDER_LSB_FIRST
+    /** Transfer Data Most Significant Bit first
+     * (Default for I<SUP>2</SUP>S protocol)
+     */
+    I2S_BIT_ORDER_MSB_FIRST,
+    /** Transfer Data Least Significant Bit first */
+    I2S_BIT_ORDER_LSB_FIRST
 };
 
 /**
  * I<SUP>2</SUP>S data bit padding.
  */
 enum i2s_bit_padding {
-	/** Padding with 0 */
-	I2S_BIT_PADDING_0,
-	/** Padding with 1 */
-	I2S_BIT_PADDING_1,
-	/** Padding with MSBit */
-	I2S_BIT_PADDING_MSB,
-	/** Padding with LSBit */
-	I2S_BIT_PADDING_LSB,
+    /** Padding with 0 */
+    I2S_BIT_PADDING_0,
+    /** Padding with 1 */
+    I2S_BIT_PADDING_1,
+    /** Padding with MSBit */
+    I2S_BIT_PADDING_MSB,
+    /** Padding with LSBit */
+    I2S_BIT_PADDING_LSB,
 };
 
 /**
  * I<SUP>2</SUP>S data word adjust.
  */
 enum i2s_data_adjust {
-	/** Data is right adjusted in word */
-	I2S_DATA_ADJUST_RIGHT,
-	/** Data is left adjusted in word */
-	I2S_DATA_ADJUST_LEFT
+    /** Data is right adjusted in word */
+    I2S_DATA_ADJUST_RIGHT,
+    /** Data is left adjusted in word */
+    I2S_DATA_ADJUST_LEFT
 };
 
 /**
  * I<SUP>2</SUP>S data word size.
  */
 enum i2s_data_size {
-	/** 32-bit */
-	I2S_DATA_SIZE_32BIT,
-	/** 24-bit */
-	I2S_DATA_SIZE_24BIT,
-	/** 20-bit */
-	I2S_DATA_SIZE_20BIT,
-	/** 18-bit */
-	I2S_DATA_SIZE_18BIT,
-	/** 16-bit */
-	I2S_DATA_SIZE_16BIT,
-	/** 16-bit compact stereo */
-	I2S_DATA_SIZE_16BIT_COMPACT,
-	/** 8-bit */
-	I2S_DATA_SIZE_8BIT,
-	/** 8-bit compact stereo */
-	I2S_DATA_SIZE_8BIT_COMPACT
+    /** 32-bit */
+    I2S_DATA_SIZE_32BIT,
+    /** 24-bit */
+    I2S_DATA_SIZE_24BIT,
+    /** 20-bit */
+    I2S_DATA_SIZE_20BIT,
+    /** 18-bit */
+    I2S_DATA_SIZE_18BIT,
+    /** 16-bit */
+    I2S_DATA_SIZE_16BIT,
+    /** 16-bit compact stereo */
+    I2S_DATA_SIZE_16BIT_COMPACT,
+    /** 8-bit */
+    I2S_DATA_SIZE_8BIT,
+    /** 8-bit compact stereo */
+    I2S_DATA_SIZE_8BIT_COMPACT
 };
 
 /**
  * I<SUP>2</SUP>S data slot adjust.
  */
 enum i2s_slot_adjust {
-	/** Data is right adjusted in slot */
-	I2S_SLOT_ADJUST_RIGHT,
-	/** Data is left adjusted in slot */
-	I2S_SLOT_ADJUST_LEFT
+    /** Data is right adjusted in slot */
+    I2S_SLOT_ADJUST_RIGHT,
+    /** Data is left adjusted in slot */
+    I2S_SLOT_ADJUST_LEFT
 };
 
 /**
  * I<SUP>2</SUP>S data padding.
  */
 enum i2s_data_padding {
-	/** Padding 0 in case of under-run */
-	I2S_DATA_PADDING_0,
-	/** Padding last data in case of under-run */
-	I2S_DATA_PADDING_SAME_AS_LAST,
-	/** Padding last data in case of under-run
-	 *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
-	I2S_DATA_PADDING_LAST = I2S_DATA_PADDING_SAME_AS_LAST,
-	/** Padding last data in case of under-run
-	 *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
-	I2S_DATA_PADDING_SAME = I2S_DATA_PADDING_SAME_AS_LAST
+    /** Padding 0 in case of under-run */
+    I2S_DATA_PADDING_0,
+    /** Padding last data in case of under-run */
+    I2S_DATA_PADDING_SAME_AS_LAST,
+    /** Padding last data in case of under-run
+     *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
+    I2S_DATA_PADDING_LAST = I2S_DATA_PADDING_SAME_AS_LAST,
+    /** Padding last data in case of under-run
+     *  (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */
+    I2S_DATA_PADDING_SAME = I2S_DATA_PADDING_SAME_AS_LAST
 };
 
 /**
  * I<SUP>2</SUP>S line default value when slot disabled.
  */
 enum i2s_line_default_state {
-	/** Output default value is 0 */
-	I2S_LINE_DEFAULT_0,
-	/** Output default value is 1 */
-	I2S_LINE_DEFAULT_1,
-	/** Output default value is high impedance */
-	I2S_LINE_DEFAULT_HIGH_IMPEDANCE = 3,
-	/** Output default value is high impedance
-	 *  (abbr. \c I2S_LINE_DEFAULT_HIGH_IMPEDANCE) */
-	I2S_LINE_DEFAULT_HIZ = I2S_LINE_DEFAULT_HIGH_IMPEDANCE
+    /** Output default value is 0 */
+    I2S_LINE_DEFAULT_0,
+    /** Output default value is 1 */
+    I2S_LINE_DEFAULT_1,
+    /** Output default value is high impedance */
+    I2S_LINE_DEFAULT_HIGH_IMPEDANCE = 3,
+    /** Output default value is high impedance
+     *  (abbr. \c I2S_LINE_DEFAULT_HIGH_IMPEDANCE) */
+    I2S_LINE_DEFAULT_HIZ = I2S_LINE_DEFAULT_HIGH_IMPEDANCE
 };
 
 /**
  * I<SUP>2</SUP>S Serializer mode.
  */
 enum i2s_serializer_mode {
-	/** Serializer is used to receive data */
-	I2S_SERIALIZER_RECEIVE,
-	/** Serializer is used to transmit data */
-	I2S_SERIALIZER_TRANSMIT,
-	/** Serializer is used to receive PDM data on each clock edge */
-	I2S_SERIALIZER_PDM2
+    /** Serializer is used to receive data */
+    I2S_SERIALIZER_RECEIVE,
+    /** Serializer is used to transmit data */
+    I2S_SERIALIZER_TRANSMIT,
+    /** Serializer is used to receive PDM data on each clock edge */
+    I2S_SERIALIZER_PDM2
 };
 
 /**
  * I<SUP>2</SUP>S clock unit selection.
  */
 enum i2s_clock_unit {
-	/** Clock Unit channel 0 */
-	I2S_CLOCK_UNIT_0,
-	/** Clock Unit channel 1 */
-	I2S_CLOCK_UNIT_1,
-	/** Number of Clock Unit channels */
-	I2S_CLOCK_UNIT_N
+    /** Clock Unit channel 0 */
+    I2S_CLOCK_UNIT_0,
+    /** Clock Unit channel 1 */
+    I2S_CLOCK_UNIT_1,
+    /** Number of Clock Unit channels */
+    I2S_CLOCK_UNIT_N
 };
 
 /**
  * I<SUP>2</SUP>S Serializer selection.
  */
 enum i2s_serializer {
-	/** Serializer channel 0 */
-	I2S_SERIALIZER_0,
-	/** Serializer channel 1 */
-	I2S_SERIALIZER_1,
-	/** Number of Serializer channels */
-	I2S_SERIALIZER_N
+    /** Serializer channel 0 */
+    I2S_SERIALIZER_0,
+    /** Serializer channel 1 */
+    I2S_SERIALIZER_1,
+    /** Number of Serializer channels */
+    I2S_SERIALIZER_N
 };
 
 
@@ -623,125 +623,125 @@ enum i2s_serializer {
  * Configure for I<SUP>2</SUP>S pin.
  */
 struct i2s_pin_config {
-	/** GPIO index to access the pin */
-	uint8_t gpio;
-	/** Pin function MUX */
-	uint8_t mux;
-	/** Enable this pin for I<SUP>2</SUP>S module */
-	bool enable;
+    /** GPIO index to access the pin */
+    uint8_t gpio;
+    /** Pin function MUX */
+    uint8_t mux;
+    /** Enable this pin for I<SUP>2</SUP>S module */
+    bool enable;
 };
 
 /**
  * Configure for I<SUP>2</SUP>S clock (SCK).
  */
 struct i2s_clock_config {
-	/** Divide generic clock to master clock output (1~32, 0,1 means no div) */
-	uint8_t mck_out_div;
-	/** Divide generic clock to serial clock (1~32, 0,1 means no div) */
-	uint8_t sck_div;
-	/** Clock source selection */
-	enum gclk_generator gclk_src;
-	/** Master clock source selection: generated or input from pin */
-	enum i2s_master_clock_source mck_src;
-	/** Serial clock source selection: generated or input from pin */
-	enum i2s_serial_clock_source sck_src;
-	/** Invert master clock output */
-	bool mck_out_invert;
-	/** Invert serial clock output */
-	bool sck_out_invert;
-	/** Generate MCK clock output */
-	bool mck_out_enable;
+    /** Divide generic clock to master clock output (1~32, 0,1 means no div) */
+    uint8_t mck_out_div;
+    /** Divide generic clock to serial clock (1~32, 0,1 means no div) */
+    uint8_t sck_div;
+    /** Clock source selection */
+    enum gclk_generator gclk_src;
+    /** Master clock source selection: generated or input from pin */
+    enum i2s_master_clock_source mck_src;
+    /** Serial clock source selection: generated or input from pin */
+    enum i2s_serial_clock_source sck_src;
+    /** Invert master clock output */
+    bool mck_out_invert;
+    /** Invert serial clock output */
+    bool sck_out_invert;
+    /** Generate MCK clock output */
+    bool mck_out_enable;
 };
 
 /**
  * Configure for I<SUP>2</SUP>S frame sync (FS).
  */
 struct i2s_frame_sync_config {
-	/** Frame Sync (FS) generated or input from pin */
-	enum i2s_frame_sync_source source;
-	/** Frame Sync (FS) width */
-	enum i2s_frame_sync_width width;
-	/** Invert Frame Sync (FS) signal before use */
-	bool invert_use;
-	/** Invert Frame Sync (FS) signal before output */
-	bool invert_out;
+    /** Frame Sync (FS) generated or input from pin */
+    enum i2s_frame_sync_source source;
+    /** Frame Sync (FS) width */
+    enum i2s_frame_sync_width width;
+    /** Invert Frame Sync (FS) signal before use */
+    bool invert_use;
+    /** Invert Frame Sync (FS) signal before output */
+    bool invert_out;
 };
 
 /**
  * Configure for I<SUP>2</SUP>S frame.
  */
 struct i2s_frame_config {
-	/** Number of slots in a frame (1~8, 0,1 means minimum 1) */
-	uint8_t number_slots;
-	/** Size of each slot in frame */
-	enum i2s_slot_size slot_size;
-	/** Data delay from Frame Sync (FS) to first data bit */
-	enum i2s_data_delay data_delay;
-	/** Frame sync (FS) */
-	struct i2s_frame_sync_config frame_sync;
+    /** Number of slots in a frame (1~8, 0,1 means minimum 1) */
+    uint8_t number_slots;
+    /** Size of each slot in frame */
+    enum i2s_slot_size slot_size;
+    /** Data delay from Frame Sync (FS) to first data bit */
+    enum i2s_data_delay data_delay;
+    /** Frame sync (FS) */
+    struct i2s_frame_sync_config frame_sync;
 };
 
 /**
  * Configure for I<SUP>2</SUP>S clock unit.
  */
 struct i2s_clock_unit_config {
-	/** Configure clock generation */
-	struct i2s_clock_config clock;
-	/** Configure frame generation */
-	struct i2s_frame_config frame;
-
-	/** Configure master clock pin */
-	struct i2s_pin_config mck_pin;
-	/** Configure serial clock pin */
-	struct i2s_pin_config sck_pin;
-	/** Configure frame sync pin */
-	struct i2s_pin_config fs_pin;
+    /** Configure clock generation */
+    struct i2s_clock_config clock;
+    /** Configure frame generation */
+    struct i2s_frame_config frame;
+
+    /** Configure master clock pin */
+    struct i2s_pin_config mck_pin;
+    /** Configure serial clock pin */
+    struct i2s_pin_config sck_pin;
+    /** Configure frame sync pin */
+    struct i2s_pin_config fs_pin;
 };
 
 /**
  * Configure for I<SUP>2</SUP>S Serializer.
  */
 struct i2s_serializer_config {
-	/** Configure Serializer data pin */
-	struct i2s_pin_config data_pin;
-
-	/** Set to \c true to loop-back output to input pin for test */
-	bool loop_back;
-
-	/** Set to \c true to assumes mono input and duplicate it (left channel) to
-	 *  right channel */
-	bool mono_mode;
-
-	/** Disable data slot */
-	bool disable_data_slot[8];
-
-	/** Set to \c true to transfer LSB first, \c false to transfer MSB first */
-	bool transfer_lsb_first;
-	/** Data Word Formatting Adjust,
-	 *  set to \c true to adjust bits in word to left */
-	bool data_adjust_left_in_word;
-	/** Data Slot Formatting Adjust,
-	 *  set to \c true to adjust words in slot to left */
-	bool data_adjust_left_in_slot;
-
-	/** Data Word Size */
-	enum i2s_data_size data_size;
-	/** Data Formatting Bit Extension */
-	enum i2s_bit_padding bit_padding;
-	/** Data padding when under-run */
-	enum i2s_data_padding data_padding;
-
-	/** DMA usage */
-	enum i2s_dma_usage dma_usage;
-
-	/** Clock unit selection */
-	enum i2s_clock_unit clock_unit;
-
-	/** Line default state where slot is disabled */
-	enum i2s_line_default_state line_default_state;
-
-	/** Serializer Mode */
-	enum i2s_serializer_mode mode;
+    /** Configure Serializer data pin */
+    struct i2s_pin_config data_pin;
+
+    /** Set to \c true to loop-back output to input pin for test */
+    bool loop_back;
+
+    /** Set to \c true to assumes mono input and duplicate it (left channel) to
+     *  right channel */
+    bool mono_mode;
+
+    /** Disable data slot */
+    bool disable_data_slot[8];
+
+    /** Set to \c true to transfer LSB first, \c false to transfer MSB first */
+    bool transfer_lsb_first;
+    /** Data Word Formatting Adjust,
+     *  set to \c true to adjust bits in word to left */
+    bool data_adjust_left_in_word;
+    /** Data Slot Formatting Adjust,
+     *  set to \c true to adjust words in slot to left */
+    bool data_adjust_left_in_slot;
+
+    /** Data Word Size */
+    enum i2s_data_size data_size;
+    /** Data Formatting Bit Extension */
+    enum i2s_bit_padding bit_padding;
+    /** Data padding when under-run */
+    enum i2s_data_padding data_padding;
+
+    /** DMA usage */
+    enum i2s_dma_usage dma_usage;
+
+    /** Clock unit selection */
+    enum i2s_clock_unit clock_unit;
+
+    /** Line default state where slot is disabled */
+    enum i2s_line_default_state line_default_state;
+
+    /** Serializer Mode */
+    enum i2s_serializer_mode mode;
 };
 
 /**
@@ -750,40 +750,40 @@ struct i2s_serializer_config {
 struct i2s_serializer_module {
 
 #if I2S_CALLBACK_MODE == true
-	/** Callbacks list for Serializer */
-	i2s_serializer_callback_t callback[I2S_SERIALIZER_CALLBACK_N];
-
-	/** Job buffer */
-	void *job_buffer;
-	/** Requested data words to read/write */
-	uint32_t requested_words;
-	/** Transferred data words for read/write */
-	uint32_t transferred_words;
-
-	/** Callback mask for registered callbacks */
-	uint8_t registered_callback_mask;
-	/** Callback mask for enabled callbacks */
-	uint8_t enabled_callback_mask;
-
-	/** Status of the ongoing or last transfer job */
-	enum status_code job_status;
+    /** Callbacks list for Serializer */
+    i2s_serializer_callback_t callback[I2S_SERIALIZER_CALLBACK_N];
+
+    /** Job buffer */
+    void *job_buffer;
+    /** Requested data words to read/write */
+    uint32_t requested_words;
+    /** Transferred data words for read/write */
+    uint32_t transferred_words;
+
+    /** Callback mask for registered callbacks */
+    uint8_t registered_callback_mask;
+    /** Callback mask for enabled callbacks */
+    uint8_t enabled_callback_mask;
+
+    /** Status of the ongoing or last transfer job */
+    enum status_code job_status;
 #endif
 
-	/** Serializer mode */
-	enum i2s_serializer_mode mode;
-	/** Serializer data word size */
-	enum i2s_data_size data_size;
+    /** Serializer mode */
+    enum i2s_serializer_mode mode;
+    /** Serializer data word size */
+    enum i2s_data_size data_size;
 };
 
 /**
  * \brief I<SUP>2</SUP>S Software Module instance struct.
  */
 struct i2s_module {
-	/** Module HW register access base */
-	I2s *hw;
+    /** Module HW register access base */
+    I2s *hw;
 
-	/** Module Serializer used */
-	struct i2s_serializer_module serializer[2];
+    /** Module Serializer used */
+    struct i2s_serializer_module serializer[2];
 };
 
 /**
@@ -803,13 +803,13 @@ struct i2s_module {
  * \retval true If the module synchronization is ongoing
  */
 static inline bool i2s_is_syncing(
-		const struct i2s_module *const module_inst)
+        const struct i2s_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return (module_inst->hw->SYNCBUSY.reg > 0);
+    return (module_inst->hw->SYNCBUSY.reg > 0);
 }
 
 /**
@@ -818,8 +818,8 @@ static inline bool i2s_is_syncing(
  */
 
 enum status_code i2s_init(
-		struct i2s_module *const module_inst,
-		I2s *hw);
+        struct i2s_module *const module_inst,
+        I2s *hw);
 
 /** @} */
 
@@ -837,13 +837,14 @@ enum status_code i2s_init(
  */
 static inline void i2s_enable(const struct i2s_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
-		/* Sync wait */
-	}
-	module_inst->hw->CTRLA.reg |= I2S_SYNCBUSY_ENABLE;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE)
+    {
+        /* Sync wait */
+    }
+    module_inst->hw->CTRLA.reg |= I2S_SYNCBUSY_ENABLE;
 }
 
 /**
@@ -855,16 +856,17 @@ static inline void i2s_enable(const struct i2s_module *const module_inst)
  */
 static inline void i2s_disable(const struct i2s_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) {
-		/* Sync wait */
-	}
+    while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE)
+    {
+        /* Sync wait */
+    }
 
-	module_inst->hw->INTENCLR.reg = I2S_INTENCLR_MASK;
-	module_inst->hw->INTFLAG.reg = I2S_INTFLAG_MASK;
-	module_inst->hw->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE;
+    module_inst->hw->INTENCLR.reg = I2S_INTENCLR_MASK;
+    module_inst->hw->INTFLAG.reg = I2S_INTFLAG_MASK;
+    module_inst->hw->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE;
 }
 
 /**
@@ -878,18 +880,20 @@ static inline void i2s_disable(const struct i2s_module *const module_inst)
  */
 static inline void i2s_reset(const struct i2s_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Disable the module if it is running */
-	if (module_inst->hw->CTRLA.reg & I2S_CTRLA_ENABLE) {
-		i2s_disable(module_inst);
-		while (i2s_is_syncing(module_inst)) {
-			/* Sync wait */
-		}
-	}
-	/* Reset the HW module */
-	module_inst->hw->CTRLA.reg = I2S_CTRLA_SWRST;
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Disable the module if it is running */
+    if (module_inst->hw->CTRLA.reg & I2S_CTRLA_ENABLE)
+    {
+        i2s_disable(module_inst);
+        while (i2s_is_syncing(module_inst))
+        {
+            /* Sync wait */
+        }
+    }
+    /* Reset the HW module */
+    module_inst->hw->CTRLA.reg = I2S_CTRLA_SWRST;
 }
 
 /** @} */
@@ -915,47 +919,47 @@ static inline void i2s_reset(const struct i2s_module *const module_inst)
  *                      to set
  */
 static inline void i2s_clock_unit_get_config_defaults(
-		struct i2s_clock_unit_config *const config)
+        struct i2s_clock_unit_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->clock.mck_out_enable = false;
-	config->clock.gclk_src = GCLK_GENERATOR_0;
+    config->clock.mck_out_enable = false;
+    config->clock.gclk_src = GCLK_GENERATOR_0;
 
-	config->clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK;
-	config->clock.mck_out_div = 1;
-	config->clock.mck_out_invert = false;
+    config->clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK;
+    config->clock.mck_out_div = 1;
+    config->clock.mck_out_invert = false;
 
-	config->clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV;
-	config->clock.sck_div = 1;
-	config->clock.sck_out_invert = false;
+    config->clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV;
+    config->clock.sck_div = 1;
+    config->clock.sck_out_invert = false;
 
-	config->frame.number_slots = 1;
-	config->frame.slot_size = I2S_SLOT_SIZE_32_BIT;
-	config->frame.data_delay = I2S_DATA_DELAY_I2S;
+    config->frame.number_slots = 1;
+    config->frame.slot_size = I2S_SLOT_SIZE_32_BIT;
+    config->frame.data_delay = I2S_DATA_DELAY_I2S;
 
-	config->frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV;
-	config->frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME;
-	config->frame.frame_sync.invert_use = false;
-	config->frame.frame_sync.invert_out = false;
+    config->frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV;
+    config->frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME;
+    config->frame.frame_sync.invert_use = false;
+    config->frame.frame_sync.invert_out = false;
 
-	config->mck_pin.enable = false;
-	config->mck_pin.mux = 0;
-	config->mck_pin.gpio = 0;
+    config->mck_pin.enable = false;
+    config->mck_pin.mux = 0;
+    config->mck_pin.gpio = 0;
 
-	config->sck_pin.enable = false;
-	config->sck_pin.mux = 0;
-	config->sck_pin.gpio = 0;
+    config->sck_pin.enable = false;
+    config->sck_pin.mux = 0;
+    config->sck_pin.gpio = 0;
 
-	config->fs_pin.enable = false;
-	config->fs_pin.mux = 0;
-	config->fs_pin.gpio = 0;
+    config->fs_pin.enable = false;
+    config->fs_pin.mux = 0;
+    config->fs_pin.gpio = 0;
 }
 
 enum status_code i2s_clock_unit_set_config(
-		struct i2s_module *const module_inst,
-		const enum i2s_clock_unit clock_unit,
-		const struct i2s_clock_unit_config *config);
+        struct i2s_module *const module_inst,
+        const enum i2s_clock_unit clock_unit,
+        const struct i2s_clock_unit_config *config);
 
 /** @} */
 
@@ -974,20 +978,21 @@ enum status_code i2s_clock_unit_set_config(
  * \param[in] clock_unit    I<SUP>2</SUP>S Clock Unit to enable
  */
 static inline void i2s_clock_unit_enable(
-		const struct i2s_module *const module_inst,
-		const enum i2s_clock_unit clock_unit)
+        const struct i2s_module *const module_inst,
+        const enum i2s_clock_unit clock_unit)
 {
-	uint32_t cken_bit;
+    uint32_t cken_bit;
 
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
+    cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
 
-	while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
-		/* Sync wait */
-	}
-	module_inst->hw->CTRLA.reg |= cken_bit;
+    while (module_inst->hw->SYNCBUSY.reg & cken_bit)
+    {
+        /* Sync wait */
+    }
+    module_inst->hw->CTRLA.reg |= cken_bit;
 }
 
 /**
@@ -999,20 +1004,21 @@ static inline void i2s_clock_unit_enable(
  * \param[in] clock_unit    I<SUP>2</SUP>S Clock Unit to disable
  */
 static inline void i2s_clock_unit_disable(
-		const struct i2s_module *const module_inst,
-		const enum i2s_clock_unit clock_unit)
+        const struct i2s_module *const module_inst,
+        const enum i2s_clock_unit clock_unit)
 {
-	uint32_t cken_bit;
+    uint32_t cken_bit;
 
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
+    cken_bit = I2S_CTRLA_CKEN0 << clock_unit;
 
-	while (module_inst->hw->SYNCBUSY.reg & cken_bit) {
-		/* Sync wait */
-	}
-	module_inst->hw->CTRLA.reg &= ~cken_bit;
+    while (module_inst->hw->SYNCBUSY.reg & cken_bit)
+    {
+        /* Sync wait */
+    }
+    module_inst->hw->CTRLA.reg &= ~cken_bit;
 }
 
 /** @} */
@@ -1051,47 +1057,47 @@ static inline void i2s_clock_unit_disable(
  *                      to set
  */
 static inline void i2s_serializer_get_config_defaults(
-		struct i2s_serializer_config *const config)
+        struct i2s_serializer_config *const config)
 {
-	config->loop_back = false;
+    config->loop_back = false;
 
-	config->mono_mode = false;
+    config->mono_mode = false;
 
-	config->disable_data_slot[0] = false;
-	config->disable_data_slot[1] = false;
-	config->disable_data_slot[2] = false;
-	config->disable_data_slot[3] = false;
-	config->disable_data_slot[4] = false;
-	config->disable_data_slot[5] = false;
-	config->disable_data_slot[6] = false;
-	config->disable_data_slot[7] = false;
+    config->disable_data_slot[0] = false;
+    config->disable_data_slot[1] = false;
+    config->disable_data_slot[2] = false;
+    config->disable_data_slot[3] = false;
+    config->disable_data_slot[4] = false;
+    config->disable_data_slot[5] = false;
+    config->disable_data_slot[6] = false;
+    config->disable_data_slot[7] = false;
 
-	config->transfer_lsb_first = false;
-	config->data_adjust_left_in_word = false;
-	config->data_adjust_left_in_slot = true;
+    config->transfer_lsb_first = false;
+    config->data_adjust_left_in_word = false;
+    config->data_adjust_left_in_slot = true;
 
-	config->data_size = I2S_DATA_SIZE_16BIT;
+    config->data_size = I2S_DATA_SIZE_16BIT;
 
-	config->bit_padding = I2S_BIT_PADDING_0;
-	config->data_padding = I2S_DATA_PADDING_0;
+    config->bit_padding = I2S_BIT_PADDING_0;
+    config->data_padding = I2S_DATA_PADDING_0;
 
-	config->dma_usage = I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL;
+    config->dma_usage = I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL;
 
-	config->clock_unit = I2S_CLOCK_UNIT_0;
+    config->clock_unit = I2S_CLOCK_UNIT_0;
 
-	config->line_default_state = I2S_LINE_DEFAULT_0;
+    config->line_default_state = I2S_LINE_DEFAULT_0;
 
-	config->mode = I2S_SERIALIZER_TRANSMIT;
+    config->mode = I2S_SERIALIZER_TRANSMIT;
 
-	config->data_pin.enable = false;
-	config->data_pin.gpio = 0;
-	config->data_pin.mux = 0;
+    config->data_pin.enable = false;
+    config->data_pin.gpio = 0;
+    config->data_pin.mux = 0;
 }
 
 enum status_code i2s_serializer_set_config(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const struct i2s_serializer_config *config);
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const struct i2s_serializer_config *config);
 /** @} */
 
 /**
@@ -1108,20 +1114,21 @@ enum status_code i2s_serializer_set_config(
  * \param[in]  serializer    I<SUP>2</SUP>S Serializer to enable
  */
 static inline void i2s_serializer_enable(
-		const struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer)
+        const struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer)
 {
-	uint32_t seren_bit;
+    uint32_t seren_bit;
 
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	seren_bit = I2S_CTRLA_SEREN0 << serializer;
+    seren_bit = I2S_CTRLA_SEREN0 << serializer;
 
-	while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
-		/* Sync wait */
-	}
-	module_inst->hw->CTRLA.reg |= seren_bit;
+    while (module_inst->hw->SYNCBUSY.reg & seren_bit)
+    {
+        /* Sync wait */
+    }
+    module_inst->hw->CTRLA.reg |= seren_bit;
 }
 
 /**
@@ -1133,20 +1140,21 @@ static inline void i2s_serializer_enable(
  * \param[in]  serializer    I<SUP>2</SUP>S Serializer to disable
  */
 static inline void i2s_serializer_disable(
-		const struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer)
+        const struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer)
 {
-	uint32_t seren_bit;
+    uint32_t seren_bit;
 
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	seren_bit = I2S_CTRLA_SEREN0 << serializer;
+    seren_bit = I2S_CTRLA_SEREN0 << serializer;
 
-	while (module_inst->hw->SYNCBUSY.reg & seren_bit) {
-		/* Sync wait */
-	}
-	module_inst->hw->CTRLA.reg &= ~seren_bit;
+    while (module_inst->hw->SYNCBUSY.reg & seren_bit)
+    {
+        /* Sync wait */
+    }
+    module_inst->hw->CTRLA.reg &= ~seren_bit;
 }
 /** @} */
 
@@ -1156,20 +1164,20 @@ static inline void i2s_serializer_disable(
  */
 
 uint32_t i2s_get_status(
-		const struct i2s_module *const module_inst);
+        const struct i2s_module *const module_inst);
 
 void i2s_clear_status(
-		const struct i2s_module *const module_inst,
-		uint32_t status);
+        const struct i2s_module *const module_inst,
+        uint32_t status);
 
 
 enum status_code i2s_enable_status_interrupt(
-		struct i2s_module *const module_inst,
-		uint32_t status);
+        struct i2s_module *const module_inst,
+        uint32_t status);
 
 void i2s_disable_status_interrupt(
-		struct i2s_module *const module_inst,
-		uint32_t status);
+        struct i2s_module *const module_inst,
+        uint32_t status);
 
 /** @}*/
 
@@ -1187,26 +1195,28 @@ void i2s_disable_status_interrupt(
  *
  */
 static inline void i2s_serializer_write_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer,
-		uint32_t data)
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer,
+        uint32_t data)
 {
-	uint32_t sync_bit, ready_bit;
-
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
-	while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-		/* Wait until ready to transmit */
-	}
-	sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
-	while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
-		/* Wait sync */
-	}
-	/* Write data */
-	module_inst->hw->DATA[serializer].reg = data;
-	module_inst->hw->INTFLAG.reg = ready_bit;
+    uint32_t sync_bit, ready_bit;
+
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    ready_bit = I2S_INTFLAG_TXRDY0 << serializer;
+    while (!(module_inst->hw->INTFLAG.reg & ready_bit))
+    {
+        /* Wait until ready to transmit */
+    }
+    sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+    while (module_inst->hw->SYNCBUSY.reg & sync_bit)
+    {
+        /* Wait sync */
+    }
+    /* Write data */
+    module_inst->hw->DATA[serializer].reg = data;
+    module_inst->hw->INTFLAG.reg = ready_bit;
 }
 
 /**
@@ -1216,38 +1226,40 @@ static inline void i2s_serializer_write_wait(
  * \param[in]  serializer    The Serializer to read
  */
 static inline uint32_t i2s_serializer_read_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer)
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer)
 {
-	uint32_t sync_bit, ready_bit;
-	uint32_t data;
-
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
-	while (!(module_inst->hw->INTFLAG.reg & ready_bit)) {
-		/* Wait until ready to transmit */
-	}
-	sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
-	while (module_inst->hw->SYNCBUSY.reg & sync_bit) {
-		/* Wait sync */
-	}
-	/* Read data */
-	data = module_inst->hw->DATA[serializer].reg;
-	module_inst->hw->INTFLAG.reg = ready_bit;
-	return data;
+    uint32_t sync_bit, ready_bit;
+    uint32_t data;
+
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    ready_bit = I2S_INTFLAG_RXRDY0 << serializer;
+    while (!(module_inst->hw->INTFLAG.reg & ready_bit))
+    {
+        /* Wait until ready to transmit */
+    }
+    sync_bit = I2S_SYNCBUSY_DATA0 << serializer;
+    while (module_inst->hw->SYNCBUSY.reg & sync_bit)
+    {
+        /* Wait sync */
+    }
+    /* Read data */
+    data = module_inst->hw->DATA[serializer].reg;
+    module_inst->hw->INTFLAG.reg = ready_bit;
+    return data;
 }
 
 enum status_code i2s_serializer_write_buffer_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer,
-		void *buffer, uint32_t size);
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer,
+        void *buffer, uint32_t size);
 
 enum status_code i2s_serializer_read_buffer_wait(
-		const struct i2s_module *const module_inst,
-		enum i2s_serializer serializer,
-		void *buffer, uint32_t size);
+        const struct i2s_module *const module_inst,
+        enum i2s_serializer serializer,
+        void *buffer, uint32_t size);
 
 /** @} */
 
@@ -1338,12 +1350,12 @@ enum status_code i2s_serializer_read_buffer_wait(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1365,21 +1377,21 @@ enum status_code i2s_serializer_read_buffer_wait(
  * \page asfdoc_sam0_i2s_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42255B</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42255A</td>
- *		<td>01/2014</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42255B</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42255A</td>
+ *      <td>01/2014</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c
index fae543c11981..a2475a5edcfe 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.c
@@ -50,147 +50,162 @@ struct i2s_module *_i2s_instances[I2S_INST_NUM];
 
 static void _i2s_interrupt_handler(const uint8_t instance)
 {
-	struct i2s_module *module = _i2s_instances[instance];
-	struct i2s_serializer_module *data_module;
-
-	/* Get interrupt flags */
-	uint32_t intflag = module->hw->INTFLAG.reg;
-	uint32_t inten = intflag & module->hw->INTENSET.reg;
-	uint32_t run_flags = (I2S_INTFLAG_TXUR0 | I2S_INTFLAG_RXOR0);
-	uint32_t ready_flags = (I2S_INTFLAG_TXRDY0 | I2S_INTFLAG_RXRDY0);
-	uint32_t call_mask;
-	uint8_t serializer;
-
-	for (serializer = 0; serializer < 2; serializer ++) {
-		data_module = &module->serializer[serializer];
-		call_mask = data_module->registered_callback_mask &
-				data_module->enabled_callback_mask;
-
-		if (intflag & (run_flags | ready_flags)) {
-			/* Serializer Tx ready */
-			if ((I2S_INTFLAG_TXRDY0 << serializer) & inten) {
-
-				if (data_module->transferred_words <
-					data_module->requested_words) {
-
-					/* Write data word */
-					while (module->hw->SYNCBUSY.reg &
-						(I2S_SYNCBUSY_DATA0 << serializer)) {
-						/* Wait sync */
-					}
-					switch(data_module->data_size) {
-					case I2S_DATA_SIZE_32BIT:
-					case I2S_DATA_SIZE_24BIT:
-					case I2S_DATA_SIZE_20BIT:
-					case I2S_DATA_SIZE_18BIT:
-						module->hw->DATA[serializer].reg =
-							((uint32_t*)data_module->job_buffer) \
-								[data_module->transferred_words];
-						break;
-					case I2S_DATA_SIZE_16BIT:
-					case I2S_DATA_SIZE_16BIT_COMPACT:
-						module->hw->DATA[serializer].reg =
-							((uint16_t*)data_module->job_buffer) \
-								[data_module->transferred_words];
-						break;
-					default:
-						module->hw->DATA[serializer].reg =
-							((uint8_t*)data_module->job_buffer) \
-								[data_module->transferred_words];
-					}
-					/* Clear interrupt status */
-					module->hw->INTFLAG.reg = I2S_INTFLAG_TXRDY0 << serializer;
-
-					/* Count data */
-					data_module->transferred_words ++;
-				}
-
-				/* Check if the buffer is done */
-				if (data_module->transferred_words >=
-					data_module->requested_words) {
-					/* It's done */
-					data_module->job_status = STATUS_OK;
-					/* Disable interrupt */
-					module->hw->INTENCLR.reg =
-							I2S_INTFLAG_TXRDY0 << serializer;
-					/* Invoke callback */
-					if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
-						call_mask) {
-						(data_module->callback \
-							[I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
-					}
-				}
-				return;
-			}
-			/* Serializer Rx ready */
-			if ((I2S_INTFLAG_RXRDY0 << serializer) & inten) {
-				/* Read data word */
-				switch(data_module->data_size) {
-				case I2S_DATA_SIZE_32BIT:
-				case I2S_DATA_SIZE_24BIT:
-				case I2S_DATA_SIZE_20BIT:
-				case I2S_DATA_SIZE_18BIT:
-					((uint32_t*)data_module->job_buffer) \
-							[data_module->transferred_words] =
-									module->hw->DATA[serializer].reg;
-					break;
-				case I2S_DATA_SIZE_16BIT:
-				case I2S_DATA_SIZE_16BIT_COMPACT:
-					((uint16_t*)data_module->job_buffer) \
-							[data_module->transferred_words] =
-									(uint16_t)module->hw->DATA[serializer].reg;
-					break;
-				default:
-					((uint8_t*)data_module->job_buffer) \
-							[data_module->transferred_words] =
-									(uint8_t)module->hw->DATA[serializer].reg;
-
-				}
-				/* Clear interrupt status */
-				module->hw->INTFLAG.reg = I2S_INTFLAG_RXRDY0 << serializer;
-
-				/* Count data */
-				data_module->transferred_words ++;
-
-				/* Check if the buffer is done */
-				if (data_module->transferred_words >=
-					data_module->requested_words) {
-					if (data_module->job_status == STATUS_BUSY) {
-						data_module->job_status = STATUS_OK;
-						/* Disable interrupt */
-						module->hw->INTENCLR.reg =
-								I2S_INTFLAG_RXRDY0 << serializer;
-						/* Invoke callback */
-						if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
-							call_mask) {
-							(data_module->callback \
-								[I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
-						}
-					}
-				}
-				return;
-			}
-			/* Serializer Tx undrerun or Rx overrun */
-			if (run_flags & inten) {
-				module->hw->INTFLAG.reg = I2S_INTFLAG_TXUR0 << serializer;
-				if ((1 << I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN) &
-					call_mask) {
-					(data_module->callback \
-						[I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN])(module);
-				}
-				return;
-			}
-		}
-		run_flags <<= 1;
-		ready_flags <<= 1;
-	}
+    struct i2s_module *module = _i2s_instances[instance];
+    struct i2s_serializer_module *data_module;
+
+    /* Get interrupt flags */
+    uint32_t intflag = module->hw->INTFLAG.reg;
+    uint32_t inten = intflag & module->hw->INTENSET.reg;
+    uint32_t run_flags = (I2S_INTFLAG_TXUR0 | I2S_INTFLAG_RXOR0);
+    uint32_t ready_flags = (I2S_INTFLAG_TXRDY0 | I2S_INTFLAG_RXRDY0);
+    uint32_t call_mask;
+    uint8_t serializer;
+
+    for (serializer = 0; serializer < 2; serializer ++)
+    {
+        data_module = &module->serializer[serializer];
+        call_mask = data_module->registered_callback_mask &
+                data_module->enabled_callback_mask;
+
+        if (intflag & (run_flags | ready_flags))
+        {
+            /* Serializer Tx ready */
+            if ((I2S_INTFLAG_TXRDY0 << serializer) & inten)
+            {
+
+                if (data_module->transferred_words <
+                    data_module->requested_words)
+                    {
+
+                    /* Write data word */
+                    while (module->hw->SYNCBUSY.reg &
+                        (I2S_SYNCBUSY_DATA0 << serializer))
+                        {
+                        /* Wait sync */
+                    }
+                    switch(data_module->data_size)
+                    {
+                    case I2S_DATA_SIZE_32BIT:
+                    case I2S_DATA_SIZE_24BIT:
+                    case I2S_DATA_SIZE_20BIT:
+                    case I2S_DATA_SIZE_18BIT:
+                        module->hw->DATA[serializer].reg =
+                            ((uint32_t*)data_module->job_buffer) \
+                                [data_module->transferred_words];
+                        break;
+                    case I2S_DATA_SIZE_16BIT:
+                    case I2S_DATA_SIZE_16BIT_COMPACT:
+                        module->hw->DATA[serializer].reg =
+                            ((uint16_t*)data_module->job_buffer) \
+                                [data_module->transferred_words];
+                        break;
+                    default:
+                        module->hw->DATA[serializer].reg =
+                            ((uint8_t*)data_module->job_buffer) \
+                                [data_module->transferred_words];
+                    }
+                    /* Clear interrupt status */
+                    module->hw->INTFLAG.reg = I2S_INTFLAG_TXRDY0 << serializer;
+
+                    /* Count data */
+                    data_module->transferred_words ++;
+                }
+
+                /* Check if the buffer is done */
+                if (data_module->transferred_words >=
+                    data_module->requested_words)
+                    {
+                    /* It's done */
+                    data_module->job_status = STATUS_OK;
+                    /* Disable interrupt */
+                    module->hw->INTENCLR.reg =
+                            I2S_INTFLAG_TXRDY0 << serializer;
+                    /* Invoke callback */
+                    if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
+                        call_mask)
+                        {
+                        (data_module->callback \
+                            [I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
+                    }
+                }
+                return;
+            }
+            /* Serializer Rx ready */
+            if ((I2S_INTFLAG_RXRDY0 << serializer) & inten)
+            {
+                /* Read data word */
+                switch(data_module->data_size)
+                {
+                case I2S_DATA_SIZE_32BIT:
+                case I2S_DATA_SIZE_24BIT:
+                case I2S_DATA_SIZE_20BIT:
+                case I2S_DATA_SIZE_18BIT:
+                    ((uint32_t*)data_module->job_buffer) \
+                            [data_module->transferred_words] =
+                                    module->hw->DATA[serializer].reg;
+                    break;
+                case I2S_DATA_SIZE_16BIT:
+                case I2S_DATA_SIZE_16BIT_COMPACT:
+                    ((uint16_t*)data_module->job_buffer) \
+                            [data_module->transferred_words] =
+                                    (uint16_t)module->hw->DATA[serializer].reg;
+                    break;
+                default:
+                    ((uint8_t*)data_module->job_buffer) \
+                            [data_module->transferred_words] =
+                                    (uint8_t)module->hw->DATA[serializer].reg;
+
+                }
+                /* Clear interrupt status */
+                module->hw->INTFLAG.reg = I2S_INTFLAG_RXRDY0 << serializer;
+
+                /* Count data */
+                data_module->transferred_words ++;
+
+                /* Check if the buffer is done */
+                if (data_module->transferred_words >=
+                    data_module->requested_words)
+                    {
+                    if (data_module->job_status == STATUS_BUSY)
+                    {
+                        data_module->job_status = STATUS_OK;
+                        /* Disable interrupt */
+                        module->hw->INTENCLR.reg =
+                                I2S_INTFLAG_RXRDY0 << serializer;
+                        /* Invoke callback */
+                        if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) &
+                            call_mask)
+                            {
+                            (data_module->callback \
+                                [I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module);
+                        }
+                    }
+                }
+                return;
+            }
+            /* Serializer Tx undrerun or Rx overrun */
+            if (run_flags & inten)
+            {
+                module->hw->INTFLAG.reg = I2S_INTFLAG_TXUR0 << serializer;
+                if ((1 << I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN) &
+                    call_mask)
+                    {
+                    (data_module->callback \
+                        [I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN])(module);
+                }
+                return;
+            }
+        }
+        run_flags <<= 1;
+        ready_flags <<= 1;
+    }
 
 }
 
 /** Interrupt handler for the I<SUP>2</SUP>S module */
 void I2S_Handler(void)
 {
-	_i2s_interrupt_handler(0);
+    _i2s_interrupt_handler(0);
 }
 
 /**
@@ -208,58 +223,63 @@ void I2S_Handler(void)
  * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
  */
 enum status_code i2s_serializer_write_buffer_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const void *buffer,
-		const uint32_t size)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const void *buffer,
+        const uint32_t size)
 {
-	struct i2s_serializer_module *data_module;
-
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-	
-	data_module = &module_inst->serializer[serializer];
-
-	/* Serializer must in transmit mode */
-	if (data_module->mode != I2S_SERIALIZER_TRANSMIT) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Buffer should be aligned */
-	switch(data_module->data_size) {
-	case I2S_DATA_SIZE_32BIT:
-	case I2S_DATA_SIZE_24BIT:
-	case I2S_DATA_SIZE_20BIT:
-	case I2S_DATA_SIZE_18BIT:
-		if ((uint32_t)buffer & 0x3) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		break;
-	case I2S_DATA_SIZE_16BIT:
-	case I2S_DATA_SIZE_16BIT_COMPACT:
-		if ((uint32_t)buffer & 0x1) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		break;
-	default:
-		break;
-	}
-
-	data_module = &module_inst->serializer[serializer];
-	if (data_module->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	data_module->job_status = STATUS_BUSY;
-	data_module->requested_words = size;
-	data_module->transferred_words = 0;
-	data_module->job_buffer = (void*)buffer;
-
-	module_inst->hw->INTENSET.reg = (I2S_INTENSET_TXRDY0 << serializer);
-
-	return STATUS_OK;
+    struct i2s_serializer_module *data_module;
+
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    data_module = &module_inst->serializer[serializer];
+
+    /* Serializer must in transmit mode */
+    if (data_module->mode != I2S_SERIALIZER_TRANSMIT)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Buffer should be aligned */
+    switch(data_module->data_size)
+    {
+    case I2S_DATA_SIZE_32BIT:
+    case I2S_DATA_SIZE_24BIT:
+    case I2S_DATA_SIZE_20BIT:
+    case I2S_DATA_SIZE_18BIT:
+        if ((uint32_t)buffer & 0x3)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        break;
+    case I2S_DATA_SIZE_16BIT:
+    case I2S_DATA_SIZE_16BIT_COMPACT:
+        if ((uint32_t)buffer & 0x1)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        break;
+    default:
+        break;
+    }
+
+    data_module = &module_inst->serializer[serializer];
+    if (data_module->job_status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    data_module->job_status = STATUS_BUSY;
+    data_module->requested_words = size;
+    data_module->transferred_words = 0;
+    data_module->job_buffer = (void*)buffer;
+
+    module_inst->hw->INTENSET.reg = (I2S_INTENSET_TXRDY0 << serializer);
+
+    return STATUS_OK;
 }
 
 /**
@@ -277,59 +297,64 @@ enum status_code i2s_serializer_write_buffer_job(
  * \retval STATUS_ERR_INVALID_ARG  An invalid buffer pointer was supplied
  */
 enum status_code i2s_serializer_read_buffer_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		void *buffer,
-		const uint32_t size)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        void *buffer,
+        const uint32_t size)
 {
-	struct i2s_serializer_module *data_module;
-
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-
-	data_module = &module_inst->serializer[serializer];
-
-	/* Serializer must in receive mode */
-	if (data_module->mode == I2S_SERIALIZER_TRANSMIT) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Data buffer must be aligned */
-	switch(data_module->data_size) {
-	case I2S_DATA_SIZE_32BIT:
-	case I2S_DATA_SIZE_24BIT:
-	case I2S_DATA_SIZE_20BIT:
-	case I2S_DATA_SIZE_18BIT:
-		if ((uint32_t)buffer & 0x3) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		break;
-	case I2S_DATA_SIZE_16BIT:
-	case I2S_DATA_SIZE_16BIT_COMPACT:
-		if ((uint32_t)buffer & 0x1) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		break;
-	default:
-		break;
-	}
-
-	data_module = &module_inst->serializer[serializer];
-	if (data_module->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	data_module->job_status = STATUS_BUSY;
-	data_module->requested_words = size;
-	data_module->transferred_words = 0;
-	data_module->job_buffer = (void*)buffer;
-
-	module_inst->hw->INTENCLR.reg = (I2S_INTENSET_RXRDY0 << serializer);
-	module_inst->hw->INTENSET.reg = (I2S_INTENSET_RXRDY0 << serializer);
-
-	return STATUS_OK;
+    struct i2s_serializer_module *data_module;
+
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    data_module = &module_inst->serializer[serializer];
+
+    /* Serializer must in receive mode */
+    if (data_module->mode == I2S_SERIALIZER_TRANSMIT)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Data buffer must be aligned */
+    switch(data_module->data_size)
+    {
+    case I2S_DATA_SIZE_32BIT:
+    case I2S_DATA_SIZE_24BIT:
+    case I2S_DATA_SIZE_20BIT:
+    case I2S_DATA_SIZE_18BIT:
+        if ((uint32_t)buffer & 0x3)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        break;
+    case I2S_DATA_SIZE_16BIT:
+    case I2S_DATA_SIZE_16BIT_COMPACT:
+        if ((uint32_t)buffer & 0x1)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        break;
+    default:
+        break;
+    }
+
+    data_module = &module_inst->serializer[serializer];
+    if (data_module->job_status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    data_module->job_status = STATUS_BUSY;
+    data_module->requested_words = size;
+    data_module->transferred_words = 0;
+    data_module->job_buffer = (void*)buffer;
+
+    module_inst->hw->INTENCLR.reg = (I2S_INTENSET_RXRDY0 << serializer);
+    module_inst->hw->INTENSET.reg = (I2S_INTENSET_RXRDY0 << serializer);
+
+    return STATUS_OK;
 }
 
 /**
@@ -342,26 +367,28 @@ enum status_code i2s_serializer_read_buffer_job(
  * \param[in]  job_type      Type of job to abort
  */
 void i2s_serializer_abort_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_job_type job_type)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_job_type job_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-
-	if (job_type == I2S_JOB_WRITE_BUFFER) {
-		/* Disable interrupt */
-		module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_TXRDY0 << serializer);
-		/* Mark job as aborted */
-		module_inst->serializer[serializer].job_status = STATUS_ABORTED;
-	} else if (job_type == I2S_JOB_READ_BUFFER) {
-		/* Disable interrupt */
-		module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_RXRDY0 << serializer);
-		/* Mark job as aborted */
-		module_inst->serializer[serializer].job_status = STATUS_ABORTED;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    if (job_type == I2S_JOB_WRITE_BUFFER)
+    {
+        /* Disable interrupt */
+        module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_TXRDY0 << serializer);
+        /* Mark job as aborted */
+        module_inst->serializer[serializer].job_status = STATUS_ABORTED;
+    } else if (job_type == I2S_JOB_READ_BUFFER)
+    {
+        /* Disable interrupt */
+        module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_RXRDY0 << serializer);
+        /* Mark job as aborted */
+        module_inst->serializer[serializer].job_status = STATUS_ABORTED;
+    }
 }
 
 /**
@@ -376,17 +403,18 @@ void i2s_serializer_abort_job(
  * \return Status of the job.
  */
 enum status_code i2s_serializer_get_job_status(
-		const struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_job_type job_type)
+        const struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_job_type job_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(serializer < I2S_SERIALIZER_N);
-
-	if (job_type == I2S_JOB_WRITE_BUFFER || job_type == I2S_JOB_READ_BUFFER) {
-		return module_inst->serializer[serializer].job_status;
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    if (job_type == I2S_JOB_WRITE_BUFFER || job_type == I2S_JOB_READ_BUFFER)
+    {
+        return module_inst->serializer[serializer].job_status;
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h
index 6fa98f3e177b..98959ab0d468 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/i2s/i2s_callback.h
@@ -64,10 +64,10 @@ extern "C" {
  * the driver.
  */
 enum i2s_job_type {
-	/** Asynchronous I<SUP>2</SUP>S write from a user provided buffer */
-	I2S_JOB_WRITE_BUFFER,
-	/** Asynchronous I<SUP>2</SUP>S read into a user provided buffer */
-	I2S_JOB_READ_BUFFER
+    /** Asynchronous I<SUP>2</SUP>S write from a user provided buffer */
+    I2S_JOB_WRITE_BUFFER,
+    /** Asynchronous I<SUP>2</SUP>S read into a user provided buffer */
+    I2S_JOB_READ_BUFFER
 };
 
 /**
@@ -90,18 +90,18 @@ enum i2s_job_type {
  *
  */
 static inline void i2s_serializer_register_callback(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const i2s_serializer_callback_t callback_func,
-		const enum i2s_serializer_callback callback_type)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const i2s_serializer_callback_t callback_func,
+        const enum i2s_serializer_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(serializer < I2S_SERIALIZER_N);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(serializer < I2S_SERIALIZER_N);
 
-	module_inst->serializer[serializer].callback[callback_type] = callback_func;
-	module_inst->serializer[serializer].registered_callback_mask |=
-			(1u << callback_type);
+    module_inst->serializer[serializer].callback[callback_type] = callback_func;
+    module_inst->serializer[serializer].registered_callback_mask |=
+            (1u << callback_type);
 }
 
 /**
@@ -115,17 +115,17 @@ static inline void i2s_serializer_register_callback(
  *
  */
 static inline void i2s_serializer_unregister_callback(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_serializer_callback callback_type)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_serializer_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(serializer < I2S_SERIALIZER_N);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(serializer < I2S_SERIALIZER_N);
 
-	module_inst->serializer[serializer].callback[callback_type] = NULL;
-	module_inst->serializer[serializer].registered_callback_mask &=
-			~(1u << callback_type);
+    module_inst->serializer[serializer].callback[callback_type] = NULL;
+    module_inst->serializer[serializer].registered_callback_mask &=
+            ~(1u << callback_type);
 }
 
 /**
@@ -141,24 +141,25 @@ static inline void i2s_serializer_unregister_callback(
  *
  */
 static inline void i2s_serializer_enable_callback(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_serializer_callback callback_type)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_serializer_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-
-	module_inst->serializer[serializer].enabled_callback_mask |=
-			(1u << callback_type);
-	if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) {
-		return;
-	}
-	module_inst->hw->INTENSET.reg =
-		(module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
-			(I2S_INTFLAG_TXUR0 << serializer) :
-			(I2S_INTFLAG_RXOR0 << serializer);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    module_inst->serializer[serializer].enabled_callback_mask |=
+            (1u << callback_type);
+    if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type)
+    {
+        return;
+    }
+    module_inst->hw->INTENSET.reg =
+        (module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
+            (I2S_INTFLAG_TXUR0 << serializer) :
+            (I2S_INTFLAG_RXOR0 << serializer);
 }
 
 /**
@@ -173,24 +174,25 @@ static inline void i2s_serializer_enable_callback(
  *
  */
 static inline void i2s_serializer_disable_callback(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_serializer_callback callback_type)
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_serializer_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(serializer < I2S_SERIALIZER_N);
-
-	module_inst->serializer[serializer].enabled_callback_mask &=
-			~(1u << callback_type);
-	if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) {
-		return;
-	}
-	module_inst->hw->INTENCLR.reg =
-		(module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
-			(I2S_INTFLAG_TXUR0 << serializer) :
-			(I2S_INTFLAG_RXOR0 << serializer);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(serializer < I2S_SERIALIZER_N);
+
+    module_inst->serializer[serializer].enabled_callback_mask &=
+            ~(1u << callback_type);
+    if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type)
+    {
+        return;
+    }
+    module_inst->hw->INTENCLR.reg =
+        (module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ?
+            (I2S_INTFLAG_TXUR0 << serializer) :
+            (I2S_INTFLAG_RXOR0 << serializer);
 }
 
 /** @} */
@@ -202,26 +204,26 @@ static inline void i2s_serializer_disable_callback(
  */
 
 enum status_code i2s_serializer_write_buffer_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const void *buffer,
-		const uint32_t size);
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const void *buffer,
+        const uint32_t size);
 
 enum status_code i2s_serializer_read_buffer_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		void *buffer,
-		const uint32_t size);
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        void *buffer,
+        const uint32_t size);
 
 void i2s_serializer_abort_job(
-		struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_job_type job_type);
+        struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_job_type job_type);
 
 enum status_code i2s_serializer_get_job_status(
-		const struct i2s_module *const module_inst,
-		const enum i2s_serializer serializer,
-		const enum i2s_job_type job_type);
+        const struct i2s_module *const module_inst,
+        const enum i2s_serializer serializer,
+        const enum i2s_job_type job_type);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c
index 2a34ab1b691e..32fb79be1f82 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.c
@@ -56,13 +56,13 @@
  * into the struct in the nvm_init() function.
  */
 struct _nvm_module {
-	/** Number of bytes contained per page. */
-	uint16_t page_size;
-	/** Total number of pages in the NVM memory. */
-	uint16_t number_of_pages;
-	/** If \c false, a page write command will be issued automatically when the
-	 *  page buffer is full. */
-	bool manual_page_write;
+    /** Number of bytes contained per page. */
+    uint16_t page_size;
+    /** Total number of pages in the NVM memory. */
+    uint16_t number_of_pages;
+    /** If \c false, a page write command will be issued automatically when the
+     *  page buffer is full. */
+    bool manual_page_write;
 };
 
 /**
@@ -101,65 +101,68 @@ static struct _nvm_module _nvm_dev;
  *                        altered
  */
 enum status_code nvm_set_config(
-		const struct nvm_config *const config)
+        const struct nvm_config *const config)
 {
-	/* Sanity check argument */
-	Assert(config);
+    /* Sanity check argument */
+    Assert(config);
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_NVMCTRL);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_NVMCTRL);
 #else
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL);
 #endif
 
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
 
-	/* Check if the module is busy */
-	if (!nvm_is_ready()) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy */
+    if (!nvm_is_ready())
+    {
+        return STATUS_BUSY;
+    }
 
 #if (!SAMC20) && (!SAMC21)
-	/* Writing configuration to the CTRLB register */
-	nvm_module->CTRLB.reg =
-			NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
-			((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
-			NVMCTRL_CTRLB_RWS(config->wait_states) |
-			((config->disable_cache & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) |
-			NVMCTRL_CTRLB_READMODE(config->cache_readmode);
+    /* Writing configuration to the CTRLB register */
+    nvm_module->CTRLB.reg =
+            NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
+            ((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
+            NVMCTRL_CTRLB_RWS(config->wait_states) |
+            ((config->disable_cache & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) |
+            NVMCTRL_CTRLB_READMODE(config->cache_readmode);
 #else
-	uint8_t cache_disable_value =  0;
-	if (config->disable_rww_cache == false) {
-		cache_disable_value = 0x02;
-	} else {
-		cache_disable_value = (config->disable_cache & 0x01);
-	}
-	/* Writing configuration to the CTRLB register */
-	nvm_module->CTRLB.reg =
-			NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
-			((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
-			NVMCTRL_CTRLB_RWS(config->wait_states) |
-			(cache_disable_value << NVMCTRL_CTRLB_CACHEDIS_Pos) |
-			NVMCTRL_CTRLB_READMODE(config->cache_readmode);
+    uint8_t cache_disable_value =  0;
+    if (config->disable_rww_cache == false)
+    {
+        cache_disable_value = 0x02;
+    } else {
+        cache_disable_value = (config->disable_cache & 0x01);
+    }
+    /* Writing configuration to the CTRLB register */
+    nvm_module->CTRLB.reg =
+            NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) |
+            ((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) |
+            NVMCTRL_CTRLB_RWS(config->wait_states) |
+            (cache_disable_value << NVMCTRL_CTRLB_CACHEDIS_Pos) |
+            NVMCTRL_CTRLB_READMODE(config->cache_readmode);
 #endif
 
-	/* Initialize the internal device struct */
-	_nvm_dev.page_size         = (8 << nvm_module->PARAM.bit.PSZ);
-	_nvm_dev.number_of_pages   = nvm_module->PARAM.bit.NVMP;
-	_nvm_dev.manual_page_write = config->manual_page_write;
+    /* Initialize the internal device struct */
+    _nvm_dev.page_size         = (8 << nvm_module->PARAM.bit.PSZ);
+    _nvm_dev.number_of_pages   = nvm_module->PARAM.bit.NVMP;
+    _nvm_dev.manual_page_write = config->manual_page_write;
 
-	/* If the security bit is set, the auxiliary space cannot be written */
-	if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) {
-		return STATUS_ERR_IO;
-	}
+    /* If the security bit is set, the auxiliary space cannot be written */
+    if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB)
+    {
+        return STATUS_ERR_IO;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -191,102 +194,108 @@ enum status_code nvm_set_config(
  * \retval STATUS_ERR_BAD_ADDRESS  If the given address was invalid
  */
 enum status_code nvm_execute_command(
-		const enum nvm_command command,
-		const uint32_t address,
-		const uint32_t parameter)
+        const enum nvm_command command,
+        const uint32_t address,
+        const uint32_t parameter)
 {
-	uint32_t ctrlb_bak;
+    uint32_t ctrlb_bak;
 
-	/* Check that the address given is valid  */
-	if (address > ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)
-		&& !(address >= NVMCTRL_AUX0_ADDRESS && address <= NVMCTRL_AUX1_ADDRESS )){
+    /* Check that the address given is valid  */
+    if (address > ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)
+        && !(address >= NVMCTRL_AUX0_ADDRESS && address <= NVMCTRL_AUX1_ADDRESS ))
+        {
 #ifdef FEATURE_NVM_RWWEE
-		if (address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
-			|| address < NVMCTRL_RWW_EEPROM_ADDR){
-			return STATUS_ERR_BAD_ADDRESS;
-		}
+        if (address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+            || address < NVMCTRL_RWW_EEPROM_ADDR)
+            {
+            return STATUS_ERR_BAD_ADDRESS;
+        }
 #else
-		return STATUS_ERR_BAD_ADDRESS;
+        return STATUS_ERR_BAD_ADDRESS;
 #endif
-	}
+    }
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	/* Turn off cache before issuing flash commands */
-	ctrlb_bak = nvm_module->CTRLB.reg;
+    /* Turn off cache before issuing flash commands */
+    ctrlb_bak = nvm_module->CTRLB.reg;
 #if (SAMC20) || (SAMC21)
-	nvm_module->CTRLB.reg = ((ctrlb_bak &(~(NVMCTRL_CTRLB_CACHEDIS(0x2)))) 
-							| NVMCTRL_CTRLB_CACHEDIS(0x1));
+    nvm_module->CTRLB.reg = ((ctrlb_bak &(~(NVMCTRL_CTRLB_CACHEDIS(0x2))))
+                            | NVMCTRL_CTRLB_CACHEDIS(0x1));
 #else
-	nvm_module->CTRLB.reg = ctrlb_bak | NVMCTRL_CTRLB_CACHEDIS;
+    nvm_module->CTRLB.reg = ctrlb_bak | NVMCTRL_CTRLB_CACHEDIS;
 #endif
 
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
-
-	/* Check if the module is busy */
-	if (!nvm_is_ready()) {
-		/* Restore the setting */
-		nvm_module->CTRLB.reg = ctrlb_bak;
-		return STATUS_BUSY;
-	}
-
-	switch (command) {
-
-		/* Commands requiring address (protected) */
-		case NVM_COMMAND_ERASE_AUX_ROW:
-		case NVM_COMMAND_WRITE_AUX_ROW:
-
-			/* Auxiliary space cannot be accessed if the security bit is set */
-			if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) {
-				/* Restore the setting */
-				nvm_module->CTRLB.reg = ctrlb_bak;
-				return STATUS_ERR_IO;
-			}
-
-			/* Set address, command will be issued elsewhere */
-			nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
-			break;
-
-		/* Commands requiring address (unprotected) */
-		case NVM_COMMAND_ERASE_ROW:
-		case NVM_COMMAND_WRITE_PAGE:
-		case NVM_COMMAND_LOCK_REGION:
-		case NVM_COMMAND_UNLOCK_REGION:
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+    /* Check if the module is busy */
+    if (!nvm_is_ready())
+    {
+        /* Restore the setting */
+        nvm_module->CTRLB.reg = ctrlb_bak;
+        return STATUS_BUSY;
+    }
+
+    switch (command)
+    {
+
+        /* Commands requiring address (protected) */
+        case NVM_COMMAND_ERASE_AUX_ROW:
+        case NVM_COMMAND_WRITE_AUX_ROW:
+
+            /* Auxiliary space cannot be accessed if the security bit is set */
+            if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB)
+            {
+                /* Restore the setting */
+                nvm_module->CTRLB.reg = ctrlb_bak;
+                return STATUS_ERR_IO;
+            }
+
+            /* Set address, command will be issued elsewhere */
+            nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
+            break;
+
+        /* Commands requiring address (unprotected) */
+        case NVM_COMMAND_ERASE_ROW:
+        case NVM_COMMAND_WRITE_PAGE:
+        case NVM_COMMAND_LOCK_REGION:
+        case NVM_COMMAND_UNLOCK_REGION:
 #ifdef FEATURE_NVM_RWWEE
-		case NVM_COMMAND_RWWEE_ERASE_ROW:
-		case NVM_COMMAND_RWWEE_WRITE_PAGE:
+        case NVM_COMMAND_RWWEE_ERASE_ROW:
+        case NVM_COMMAND_RWWEE_WRITE_PAGE:
 #endif
 
-			/* Set address, command will be issued elsewhere */
-			nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
-			break;
+            /* Set address, command will be issued elsewhere */
+            nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4];
+            break;
 
-		/* Commands not requiring address */
-		case NVM_COMMAND_PAGE_BUFFER_CLEAR:
-		case NVM_COMMAND_SET_SECURITY_BIT:
-		case NVM_COMMAND_ENTER_LOW_POWER_MODE:
-		case NVM_COMMAND_EXIT_LOW_POWER_MODE:
-			break;
+        /* Commands not requiring address */
+        case NVM_COMMAND_PAGE_BUFFER_CLEAR:
+        case NVM_COMMAND_SET_SECURITY_BIT:
+        case NVM_COMMAND_ENTER_LOW_POWER_MODE:
+        case NVM_COMMAND_EXIT_LOW_POWER_MODE:
+            break;
 
-		default:
-			/* Restore the setting */
-			nvm_module->CTRLB.reg = ctrlb_bak;
-			return STATUS_ERR_INVALID_ARG;
-	}
+        default:
+            /* Restore the setting */
+            nvm_module->CTRLB.reg = ctrlb_bak;
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Set command */
-	nvm_module->CTRLA.reg = command | NVMCTRL_CTRLA_CMDEX_KEY;
+    /* Set command */
+    nvm_module->CTRLA.reg = command | NVMCTRL_CTRLA_CMDEX_KEY;
 
-	/* Wait for the NVM controller to become ready */
-	while (!nvm_is_ready()) {
-	}
+    /* Wait for the NVM controller to become ready */
+    while (!nvm_is_ready())
+    {
+    }
 
-	/* Restore the setting */
-	nvm_module->CTRLB.reg = ctrlb_bak;
+    /* Restore the setting */
+    nvm_module->CTRLB.reg = ctrlb_bak;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -321,78 +330,85 @@ enum status_code nvm_execute_command(
  * \retval STATUS_ERR_INVALID_ARG  The supplied length and offset was invalid
  */
 enum status_code nvm_update_buffer(
-		const uint32_t destination_address,
-		uint8_t *const buffer,
-		uint16_t offset,
-		uint16_t length)
+        const uint32_t destination_address,
+        uint8_t *const buffer,
+        uint16_t offset,
+        uint16_t length)
 {
-	enum status_code error_code = STATUS_OK;
-	uint8_t row_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
-
-	/* Ensure the read does not overflow the page size */
-	if ((offset + length) > _nvm_dev.page_size) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Calculate the starting row address of the page to update */
-	uint32_t row_start_address =
-			destination_address & ~((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1);
-
-	/* Read in the current row contents */
-	for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) {
-		do
-		{
-			error_code = nvm_read_buffer(
-					row_start_address + (i * _nvm_dev.page_size),
-					row_buffer[i], _nvm_dev.page_size);
-		} while (error_code == STATUS_BUSY);
-
-		if (error_code != STATUS_OK) {
-			return error_code;
-		}
-	}
-
-	/* Calculate the starting page in the row that is to be updated */
-	uint8_t page_in_row =
-			(destination_address % (_nvm_dev.page_size * NVMCTRL_ROW_PAGES)) /
-			_nvm_dev.page_size;
-
-	/* Update the specified bytes in the page buffer */
-	for (uint32_t i = 0; i < length; i++) {
-		row_buffer[page_in_row][offset + i] = buffer[i];
-	}
-
-	system_interrupt_enter_critical_section();
-
-	/* Erase the row */
-	do
-	{
-		error_code = nvm_erase_row(row_start_address);
-	} while (error_code == STATUS_BUSY);
-
-	if (error_code != STATUS_OK) {
-		system_interrupt_leave_critical_section();
-		return error_code;
-	}
-
-	/* Write the updated row contents to the erased row */
-	for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) {
-		do
-		{
-			error_code = nvm_write_buffer(
-					row_start_address + (i * _nvm_dev.page_size),
-					row_buffer[i], _nvm_dev.page_size);
-		} while (error_code == STATUS_BUSY);
-
-		if (error_code != STATUS_OK) {
-			system_interrupt_leave_critical_section();
-			return error_code;
-		}
-	}
-
-	system_interrupt_leave_critical_section();
-
-	return error_code;
+    enum status_code error_code = STATUS_OK;
+    uint8_t row_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE];
+
+    /* Ensure the read does not overflow the page size */
+    if ((offset + length) > _nvm_dev.page_size)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Calculate the starting row address of the page to update */
+    uint32_t row_start_address =
+            destination_address & ~((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1);
+
+    /* Read in the current row contents */
+    for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++)
+    {
+        do
+        {
+            error_code = nvm_read_buffer(
+                    row_start_address + (i * _nvm_dev.page_size),
+                    row_buffer[i], _nvm_dev.page_size);
+        } while (error_code == STATUS_BUSY);
+
+        if (error_code != STATUS_OK)
+        {
+            return error_code;
+        }
+    }
+
+    /* Calculate the starting page in the row that is to be updated */
+    uint8_t page_in_row =
+            (destination_address % (_nvm_dev.page_size * NVMCTRL_ROW_PAGES)) /
+            _nvm_dev.page_size;
+
+    /* Update the specified bytes in the page buffer */
+    for (uint32_t i = 0; i < length; i++)
+    {
+        row_buffer[page_in_row][offset + i] = buffer[i];
+    }
+
+    system_interrupt_enter_critical_section();
+
+    /* Erase the row */
+    do
+    {
+        error_code = nvm_erase_row(row_start_address);
+    } while (error_code == STATUS_BUSY);
+
+    if (error_code != STATUS_OK)
+    {
+        system_interrupt_leave_critical_section();
+        return error_code;
+    }
+
+    /* Write the updated row contents to the erased row */
+    for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++)
+    {
+        do
+        {
+            error_code = nvm_write_buffer(
+                    row_start_address + (i * _nvm_dev.page_size),
+                    row_buffer[i], _nvm_dev.page_size);
+        } while (error_code == STATUS_BUSY);
+
+        if (error_code != STATUS_OK)
+        {
+            system_interrupt_leave_critical_section();
+            return error_code;
+        }
+    }
+
+    system_interrupt_leave_critical_section();
+
+    return error_code;
 }
 
 /**
@@ -428,92 +444,101 @@ enum status_code nvm_update_buffer(
  * \retval STATUS_ERR_INVALID_ARG  The supplied write length was invalid
  */
 enum status_code nvm_write_buffer(
-		const uint32_t destination_address,
-		const uint8_t *buffer,
-		uint16_t length)
+        const uint32_t destination_address,
+        const uint8_t *buffer,
+        uint16_t length)
 {
 #ifdef FEATURE_NVM_RWWEE
-	bool is_rww_eeprom = false;
+    bool is_rww_eeprom = false;
 #endif
 
-	/* Check if the destination address is valid */
-	if (destination_address >
-			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+    /* Check if the destination address is valid */
+    if (destination_address >
+            ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages))
+            {
 #ifdef FEATURE_NVM_RWWEE
-		if (destination_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
-			|| destination_address < NVMCTRL_RWW_EEPROM_ADDR){
-			return STATUS_ERR_BAD_ADDRESS;
-		}
-		is_rww_eeprom = true;
+        if (destination_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+            || destination_address < NVMCTRL_RWW_EEPROM_ADDR)
+            {
+            return STATUS_ERR_BAD_ADDRESS;
+        }
+        is_rww_eeprom = true;
 #else
-		return STATUS_ERR_BAD_ADDRESS;
+        return STATUS_ERR_BAD_ADDRESS;
 #endif
-	}
-
-	/* Check if the write address not aligned to the start of a page */
-	if (destination_address & (_nvm_dev.page_size - 1)) {
-		return STATUS_ERR_BAD_ADDRESS;
-	}
-
-	/* Check if the write length is longer than an NVM page */
-	if (length > _nvm_dev.page_size) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
-
-	/* Check if the module is busy */
-	if (!nvm_is_ready()) {
-		return STATUS_BUSY;
-	}
-
-	/* Erase the page buffer before buffering new data */
-	nvm_module->CTRLA.reg = NVM_COMMAND_PAGE_BUFFER_CLEAR | NVMCTRL_CTRLA_CMDEX_KEY;
-
-	/* Check if the module is busy */
-	while (!nvm_is_ready()) {
-		/* Force-wait for the buffer clear to complete */
-	}
-
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
-
-	uint32_t nvm_address = destination_address / 2;
-
-	/* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
-	 * to ensure alignment */
-	for (uint16_t i = 0; i < length; i += 2) {
-		uint16_t data;
-
-		/* Copy first byte of the 16-bit chunk to the temporary buffer */
-		data = buffer[i];
-
-		/* If we are not at the end of a write request with an odd byte count,
-		 * store the next byte of data as well */
-		if (i < (length - 1)) {
-			data |= (buffer[i + 1] << 8);
-		}
-
-		/* Store next 16-bit chunk to the NVM memory space */
-		NVM_MEMORY[nvm_address++] = data;
-	}
-
-	/* If automatic page write mode is enable, then perform a manual NVM
-	 * write when the length of data to be programmed is less than page size
-	 */
-	if ((_nvm_dev.manual_page_write == false) && (length < NVMCTRL_PAGE_SIZE)) {
+    }
+
+    /* Check if the write address not aligned to the start of a page */
+    if (destination_address & (_nvm_dev.page_size - 1))
+    {
+        return STATUS_ERR_BAD_ADDRESS;
+    }
+
+    /* Check if the write length is longer than an NVM page */
+    if (length > _nvm_dev.page_size)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
+
+    /* Check if the module is busy */
+    if (!nvm_is_ready())
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Erase the page buffer before buffering new data */
+    nvm_module->CTRLA.reg = NVM_COMMAND_PAGE_BUFFER_CLEAR | NVMCTRL_CTRLA_CMDEX_KEY;
+
+    /* Check if the module is busy */
+    while (!nvm_is_ready())
+    {
+        /* Force-wait for the buffer clear to complete */
+    }
+
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+    uint32_t nvm_address = destination_address / 2;
+
+    /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
+     * to ensure alignment */
+    for (uint16_t i = 0; i < length; i += 2)
+    {
+        uint16_t data;
+
+        /* Copy first byte of the 16-bit chunk to the temporary buffer */
+        data = buffer[i];
+
+        /* If we are not at the end of a write request with an odd byte count,
+         * store the next byte of data as well */
+        if (i < (length - 1))
+        {
+            data |= (buffer[i + 1] << 8);
+        }
+
+        /* Store next 16-bit chunk to the NVM memory space */
+        NVM_MEMORY[nvm_address++] = data;
+    }
+
+    /* If automatic page write mode is enable, then perform a manual NVM
+     * write when the length of data to be programmed is less than page size
+     */
+    if ((_nvm_dev.manual_page_write == false) && (length < NVMCTRL_PAGE_SIZE))
+    {
 #ifdef FEATURE_NVM_RWWEE
-	 return ((is_rww_eeprom) ?
-				(nvm_execute_command(NVM_COMMAND_RWWEE_WRITE_PAGE,destination_address, 0)):
-	 			(nvm_execute_command(NVM_COMMAND_WRITE_PAGE,destination_address, 0)));
+     return ((is_rww_eeprom) ?
+                (nvm_execute_command(NVM_COMMAND_RWWEE_WRITE_PAGE,destination_address, 0)):
+                (nvm_execute_command(NVM_COMMAND_WRITE_PAGE,destination_address, 0)));
 #else
-		return nvm_execute_command(NVM_COMMAND_WRITE_PAGE,
-				destination_address, 0);
+        return nvm_execute_command(NVM_COMMAND_WRITE_PAGE,
+                destination_address, 0);
 #endif
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -539,63 +564,70 @@ enum status_code nvm_write_buffer(
  * \retval STATUS_ERR_INVALID_ARG  The supplied read length was invalid
  */
 enum status_code nvm_read_buffer(
-		const uint32_t source_address,
-		uint8_t *const buffer,
-		uint16_t length)
+        const uint32_t source_address,
+        uint8_t *const buffer,
+        uint16_t length)
 {
-	/* Check if the source address is valid */
-	if (source_address >
-			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+    /* Check if the source address is valid */
+    if (source_address >
+            ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages))
+            {
 #ifdef FEATURE_NVM_RWWEE
-		if (source_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
-			|| source_address < NVMCTRL_RWW_EEPROM_ADDR){
-			return STATUS_ERR_BAD_ADDRESS;
-		}
+        if (source_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+            || source_address < NVMCTRL_RWW_EEPROM_ADDR)
+            {
+            return STATUS_ERR_BAD_ADDRESS;
+        }
 #else
-		return STATUS_ERR_BAD_ADDRESS;
+        return STATUS_ERR_BAD_ADDRESS;
 #endif
-	}
-
-	/* Check if the read address is not aligned to the start of a page */
-	if (source_address & (_nvm_dev.page_size - 1)) {
-		return STATUS_ERR_BAD_ADDRESS;
-	}
-
-	/* Check if the write length is longer than an NVM page */
-	if (length > _nvm_dev.page_size) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
-
-	/* Check if the module is busy */
-	if (!nvm_is_ready()) {
-		return STATUS_BUSY;
-	}
-
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
-
-	uint32_t page_address = source_address / 2;
-
-	/* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
-	 * to ensure alignment */
-	for (uint16_t i = 0; i < length; i += 2) {
-		/* Fetch next 16-bit chunk from the NVM memory space */
-		uint16_t data = NVM_MEMORY[page_address++];
-
-		/* Copy first byte of the 16-bit chunk to the destination buffer */
-		buffer[i] = (data & 0xFF);
-
-		/* If we are not at the end of a read request with an odd byte count,
-		 * store the next byte of data as well */
-		if (i < (length - 1)) {
-			buffer[i + 1] = (data >> 8);
-		}
-	}
-
-	return STATUS_OK;
+    }
+
+    /* Check if the read address is not aligned to the start of a page */
+    if (source_address & (_nvm_dev.page_size - 1))
+    {
+        return STATUS_ERR_BAD_ADDRESS;
+    }
+
+    /* Check if the write length is longer than an NVM page */
+    if (length > _nvm_dev.page_size)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
+
+    /* Check if the module is busy */
+    if (!nvm_is_ready())
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+
+    uint32_t page_address = source_address / 2;
+
+    /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy
+     * to ensure alignment */
+    for (uint16_t i = 0; i < length; i += 2)
+    {
+        /* Fetch next 16-bit chunk from the NVM memory space */
+        uint16_t data = NVM_MEMORY[page_address++];
+
+        /* Copy first byte of the 16-bit chunk to the destination buffer */
+        buffer[i] = (data & 0xFF);
+
+        /* If we are not at the end of a read request with an odd byte count,
+         * store the next byte of data as well */
+        if (i < (length - 1))
+        {
+            buffer[i + 1] = (data >> 8);
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -617,68 +649,75 @@ enum status_code nvm_read_buffer(
  * \retval STATUS_ABORTED          NVM erased error
  */
 enum status_code nvm_erase_row(
-		const uint32_t row_address)
+        const uint32_t row_address)
 {
 #ifdef FEATURE_NVM_RWWEE
-		bool is_rww_eeprom = false;
+        bool is_rww_eeprom = false;
 #endif
 
-	/* Check if the row address is valid */
-	if (row_address >
-			((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) {
+    /* Check if the row address is valid */
+    if (row_address >
+            ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages))
+            {
 #ifdef FEATURE_NVM_RWWEE
-		if (row_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
-			|| row_address < NVMCTRL_RWW_EEPROM_ADDR){
-			return STATUS_ERR_BAD_ADDRESS;
-		}
-		is_rww_eeprom = true;
+        if (row_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR)
+            || row_address < NVMCTRL_RWW_EEPROM_ADDR)
+            {
+            return STATUS_ERR_BAD_ADDRESS;
+        }
+        is_rww_eeprom = true;
 #else
-		return STATUS_ERR_BAD_ADDRESS;
+        return STATUS_ERR_BAD_ADDRESS;
 #endif
-	}
+    }
 
-	/* Check if the address to erase is not aligned to the start of a row */
-	if (row_address & ((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1)) {
-		return STATUS_ERR_BAD_ADDRESS;
-	}
+    /* Check if the address to erase is not aligned to the start of a row */
+    if (row_address & ((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1))
+    {
+        return STATUS_ERR_BAD_ADDRESS;
+    }
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	/* Check if the module is busy */
-	if (!nvm_is_ready()) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy */
+    if (!nvm_is_ready())
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
 
-	/* Set address and command */
-	nvm_module->ADDR.reg  = (uintptr_t)&NVM_MEMORY[row_address / 4];
+    /* Set address and command */
+    nvm_module->ADDR.reg  = (uintptr_t)&NVM_MEMORY[row_address / 4];
 
 #ifdef SAMD21_64K
-	if (is_rww_eeprom) {
-		NVM_MEMORY[row_address / 2] = 0x0;
-	}
+    if (is_rww_eeprom)
+    {
+        NVM_MEMORY[row_address / 2] = 0x0;
+    }
 #endif
 
 #ifdef FEATURE_NVM_RWWEE
-	nvm_module->CTRLA.reg = ((is_rww_eeprom) ?
-								(NVM_COMMAND_RWWEE_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY):
-								(NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY));
+    nvm_module->CTRLA.reg = ((is_rww_eeprom) ?
+                                (NVM_COMMAND_RWWEE_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY):
+                                (NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY));
 #else
-	nvm_module->CTRLA.reg = NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY;
+    nvm_module->CTRLA.reg = NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY;
 #endif
 
-	while (!nvm_is_ready()) {
-	}
+    while (!nvm_is_ready())
+    {
+    }
 
-	/* There existed error in NVM erase operation */
-	if ((enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK) != NVM_ERROR_NONE) {
-		return STATUS_ABORTED;
-	}
+    /* There existed error in NVM erase operation */
+    if ((enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK) != NVM_ERROR_NONE)
+    {
+        return STATUS_ABORTED;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -691,61 +730,63 @@ enum status_code nvm_erase_row(
  *                           number of pages in the NVM memory
  */
 void nvm_get_parameters(
-		struct nvm_parameters *const parameters)
+        struct nvm_parameters *const parameters)
 {
-	/* Sanity check parameters */
-	Assert(parameters);
+    /* Sanity check parameters */
+    Assert(parameters);
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK;
 
-	/* Read out from the PARAM register */
-	uint32_t param_reg = nvm_module->PARAM.reg;
+    /* Read out from the PARAM register */
+    uint32_t param_reg = nvm_module->PARAM.reg;
 
-	/* Mask out page size exponent and convert to a number of bytes */
-	parameters->page_size =
-			8 << ((param_reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos);
+    /* Mask out page size exponent and convert to a number of bytes */
+    parameters->page_size =
+            8 << ((param_reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos);
 
-	/* Mask out number of pages count */
-	parameters->nvm_number_of_pages =
-			(param_reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
+    /* Mask out number of pages count */
+    parameters->nvm_number_of_pages =
+            (param_reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos;
 
 #ifdef FEATURE_NVM_RWWEE
-	/* Mask out rwwee number of pages count */
-	parameters->rww_eeprom_number_of_pages =
-			(param_reg & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos;
+    /* Mask out rwwee number of pages count */
+    parameters->rww_eeprom_number_of_pages =
+            (param_reg & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos;
 #endif
 
-	/* Read the current EEPROM fuse value from the USER row */
-	uint16_t eeprom_fuse_value =
-			(NVM_USER_MEMORY[NVMCTRL_FUSES_EEPROM_SIZE_Pos / 16] &
-			NVMCTRL_FUSES_EEPROM_SIZE_Msk) >> NVMCTRL_FUSES_EEPROM_SIZE_Pos;
-
-	/* Translate the EEPROM fuse byte value to a number of NVM pages */
-	if (eeprom_fuse_value == 7) {
-		parameters->eeprom_number_of_pages = 0;
-	}
-	else {
-		parameters->eeprom_number_of_pages =
-				NVMCTRL_ROW_PAGES << (6 - eeprom_fuse_value);
-	}
-
-	/* Read the current BOOTSZ fuse value from the USER row */
-	uint16_t boot_fuse_value =
-			(NVM_USER_MEMORY[NVMCTRL_FUSES_BOOTPROT_Pos / 16] &
-			NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos;
-
-	/* Translate the BOOTSZ fuse byte value to a number of NVM pages */
-	if (boot_fuse_value == 7) {
-		parameters->bootloader_number_of_pages = 0;
-	}
-	else {
-		parameters->bootloader_number_of_pages =
-				NVMCTRL_ROW_PAGES << (7 - boot_fuse_value);
-	}
+    /* Read the current EEPROM fuse value from the USER row */
+    uint16_t eeprom_fuse_value =
+            (NVM_USER_MEMORY[NVMCTRL_FUSES_EEPROM_SIZE_Pos / 16] &
+            NVMCTRL_FUSES_EEPROM_SIZE_Msk) >> NVMCTRL_FUSES_EEPROM_SIZE_Pos;
+
+    /* Translate the EEPROM fuse byte value to a number of NVM pages */
+    if (eeprom_fuse_value == 7)
+    {
+        parameters->eeprom_number_of_pages = 0;
+    }
+    else {
+        parameters->eeprom_number_of_pages =
+                NVMCTRL_ROW_PAGES << (6 - eeprom_fuse_value);
+    }
+
+    /* Read the current BOOTSZ fuse value from the USER row */
+    uint16_t boot_fuse_value =
+            (NVM_USER_MEMORY[NVMCTRL_FUSES_BOOTPROT_Pos / 16] &
+            NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos;
+
+    /* Translate the BOOTSZ fuse byte value to a number of NVM pages */
+    if (boot_fuse_value == 7)
+    {
+        parameters->bootloader_number_of_pages = 0;
+    }
+    else {
+        parameters->bootloader_number_of_pages =
+                NVMCTRL_ROW_PAGES << (7 - boot_fuse_value);
+    }
 }
 
 /**
@@ -764,26 +805,26 @@ void nvm_get_parameters(
  */
 bool nvm_is_page_locked(uint16_t page_number)
 {
-	uint16_t pages_in_region;
-	uint16_t region_number;
+    uint16_t pages_in_region;
+    uint16_t region_number;
 
 #ifdef FEATURE_NVM_RWWEE
-	Assert(page_number < _nvm_dev.number_of_pages);
+    Assert(page_number < _nvm_dev.number_of_pages);
 #endif
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	/* Get number of pages in a region */
-	pages_in_region = _nvm_dev.number_of_pages / 16;
+    /* Get number of pages in a region */
+    pages_in_region = _nvm_dev.number_of_pages / 16;
 
-	/* Get region for given page */
-	region_number = page_number / pages_in_region;
+    /* Get region for given page */
+    region_number = page_number / pages_in_region;
 
-	return !(nvm_module->LOCK.reg & (1 << region_number));
+    return !(nvm_module->LOCK.reg & (1 << region_number));
 }
 
-///@cond INTERNAL
+/*/@cond INTERNAL*/
 
 /**
  * \internal
@@ -792,65 +833,65 @@ bool nvm_is_page_locked(uint16_t page_number)
  *
  */
 static void _nvm_translate_raw_fusebits_to_struct (
-		uint32_t *raw_user_row,
-		struct nvm_fusebits *fusebits)
+        uint32_t *raw_user_row,
+        struct nvm_fusebits *fusebits)
 {
 
-	fusebits->bootloader_size = (enum nvm_bootloader_size)
-			((raw_user_row[0] & NVMCTRL_FUSES_BOOTPROT_Msk)
-			>> NVMCTRL_FUSES_BOOTPROT_Pos);
+    fusebits->bootloader_size = (enum nvm_bootloader_size)
+            ((raw_user_row[0] & NVMCTRL_FUSES_BOOTPROT_Msk)
+            >> NVMCTRL_FUSES_BOOTPROT_Pos);
 
-	fusebits->eeprom_size = (enum nvm_eeprom_emulator_size)
-			((raw_user_row[0] & NVMCTRL_FUSES_EEPROM_SIZE_Msk)
-			>> NVMCTRL_FUSES_EEPROM_SIZE_Pos);
+    fusebits->eeprom_size = (enum nvm_eeprom_emulator_size)
+            ((raw_user_row[0] & NVMCTRL_FUSES_EEPROM_SIZE_Msk)
+            >> NVMCTRL_FUSES_EEPROM_SIZE_Pos);
 
 #if (SAML21) || (SAML22) || (SAMR30)
-	fusebits->bod33_level = (uint8_t)
-			((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
-			>> FUSES_BOD33USERLEVEL_Pos);
+    fusebits->bod33_level = (uint8_t)
+            ((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
+            >> FUSES_BOD33USERLEVEL_Pos);
 
-	fusebits->bod33_enable = (bool)
-			(!((raw_user_row[0] & FUSES_BOD33_DIS_Msk)
-			>> FUSES_BOD33_DIS_Pos));
+    fusebits->bod33_enable = (bool)
+            (!((raw_user_row[0] & FUSES_BOD33_DIS_Msk)
+            >> FUSES_BOD33_DIS_Pos));
 
-	fusebits->bod33_action = (enum nvm_bod33_action)
-			((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
-			>> FUSES_BOD33_ACTION_Pos);
+    fusebits->bod33_action = (enum nvm_bod33_action)
+            ((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
+            >> FUSES_BOD33_ACTION_Pos);
 
-	fusebits->bod33_hysteresis = (bool)
-			((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
-			>> FUSES_BOD33_HYST_Pos);
+    fusebits->bod33_hysteresis = (bool)
+            ((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
+            >> FUSES_BOD33_HYST_Pos);
 
 #elif (SAMD20) || (SAMD21) || (SAMR21)|| (SAMDA1) || (SAMD09) || (SAMD10) || (SAMD11) || (SAMHA1)
-	fusebits->bod33_level = (uint8_t)
-			((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
-			>> FUSES_BOD33USERLEVEL_Pos);
-
-	fusebits->bod33_enable = (bool)
-			((raw_user_row[0] & FUSES_BOD33_EN_Msk)
-			>> FUSES_BOD33_EN_Pos);
-
-	fusebits->bod33_action = (enum nvm_bod33_action)
-			((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
-			>> FUSES_BOD33_ACTION_Pos);
-	fusebits->bod33_hysteresis = (bool)
-			((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
-			>> FUSES_BOD33_HYST_Pos);
+    fusebits->bod33_level = (uint8_t)
+            ((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk)
+            >> FUSES_BOD33USERLEVEL_Pos);
+
+    fusebits->bod33_enable = (bool)
+            ((raw_user_row[0] & FUSES_BOD33_EN_Msk)
+            >> FUSES_BOD33_EN_Pos);
+
+    fusebits->bod33_action = (enum nvm_bod33_action)
+            ((raw_user_row[0] & FUSES_BOD33_ACTION_Msk)
+            >> FUSES_BOD33_ACTION_Pos);
+    fusebits->bod33_hysteresis = (bool)
+            ((raw_user_row[1] & FUSES_BOD33_HYST_Msk)
+            >> FUSES_BOD33_HYST_Pos);
 #elif (SAMC20) || (SAMC21)
-	fusebits->bodvdd_level = (uint8_t)
-			((raw_user_row[0] & FUSES_BODVDDUSERLEVEL_Msk)
-			>> FUSES_BODVDDUSERLEVEL_Pos);
+    fusebits->bodvdd_level = (uint8_t)
+            ((raw_user_row[0] & FUSES_BODVDDUSERLEVEL_Msk)
+            >> FUSES_BODVDDUSERLEVEL_Pos);
 
-	fusebits->bodvdd_enable = (bool)
-			(!((raw_user_row[0] & FUSES_BODVDD_DIS_Msk)
-			>> FUSES_BODVDD_DIS_Pos));
+    fusebits->bodvdd_enable = (bool)
+            (!((raw_user_row[0] & FUSES_BODVDD_DIS_Msk)
+            >> FUSES_BODVDD_DIS_Pos));
 
-	fusebits->bodvdd_action = (enum nvm_bod33_action)
-			((raw_user_row[0] & FUSES_BODVDD_ACTION_Msk)
-			>> FUSES_BODVDD_ACTION_Pos);
+    fusebits->bodvdd_action = (enum nvm_bod33_action)
+            ((raw_user_row[0] & FUSES_BODVDD_ACTION_Msk)
+            >> FUSES_BODVDD_ACTION_Pos);
 
-	fusebits->bodvdd_hysteresis = (raw_user_row[1] & FUSES_BODVDD_HYST_Msk)
-									>> FUSES_BODVDD_HYST_Pos;
+    fusebits->bodvdd_hysteresis = (raw_user_row[1] & FUSES_BODVDD_HYST_Msk)
+                                    >> FUSES_BODVDD_HYST_Pos;
 #endif
 
 #ifdef FEATURE_BOD12
@@ -867,56 +908,56 @@ static void _nvm_translate_raw_fusebits_to_struct (
 #define FUSES_BOD12_ACTION_Pos 24
 #define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos)
 #endif
-	
-	fusebits->bod12_level = (uint8_t)
-			((raw_user_row[0] & FUSES_BOD12USERLEVEL_Msk)
-			>> FUSES_BOD12USERLEVEL_Pos);
-
-	fusebits->bod12_enable = (bool)
-			(!((raw_user_row[0] & FUSES_BOD12_DIS_Msk)
-			>> FUSES_BOD12_DIS_Pos));
-
-	fusebits->bod12_action = (enum nvm_bod12_action)
-			((raw_user_row[0] & FUSES_BOD12_ACTION_Msk)
-			>> FUSES_BOD33_ACTION_Pos);
-
-	fusebits->bod12_hysteresis = (bool)
-			((raw_user_row[1] & FUSES_BOD12_HYST_Msk)
-			>> FUSES_BOD12_HYST_Pos);
+
+    fusebits->bod12_level = (uint8_t)
+            ((raw_user_row[0] & FUSES_BOD12USERLEVEL_Msk)
+            >> FUSES_BOD12USERLEVEL_Pos);
+
+    fusebits->bod12_enable = (bool)
+            (!((raw_user_row[0] & FUSES_BOD12_DIS_Msk)
+            >> FUSES_BOD12_DIS_Pos));
+
+    fusebits->bod12_action = (enum nvm_bod12_action)
+            ((raw_user_row[0] & FUSES_BOD12_ACTION_Msk)
+            >> FUSES_BOD33_ACTION_Pos);
+
+    fusebits->bod12_hysteresis = (bool)
+            ((raw_user_row[1] & FUSES_BOD12_HYST_Msk)
+            >> FUSES_BOD12_HYST_Pos);
 #endif
 
-	fusebits->wdt_enable = (bool)
-			((raw_user_row[0] & WDT_FUSES_ENABLE_Msk) >> WDT_FUSES_ENABLE_Pos);
+    fusebits->wdt_enable = (bool)
+            ((raw_user_row[0] & WDT_FUSES_ENABLE_Msk) >> WDT_FUSES_ENABLE_Pos);
 
-	fusebits->wdt_always_on = (bool)
-			((raw_user_row[0] & WDT_FUSES_ALWAYSON_Msk) >> WDT_FUSES_ALWAYSON_Pos);
+    fusebits->wdt_always_on = (bool)
+            ((raw_user_row[0] & WDT_FUSES_ALWAYSON_Msk) >> WDT_FUSES_ALWAYSON_Pos);
 
-	fusebits->wdt_timeout_period = (uint8_t)
-			((raw_user_row[0] & WDT_FUSES_PER_Msk) >> WDT_FUSES_PER_Pos);
+    fusebits->wdt_timeout_period = (uint8_t)
+            ((raw_user_row[0] & WDT_FUSES_PER_Msk) >> WDT_FUSES_PER_Pos);
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
-			((raw_user_row[1] & WDT_FUSES_WINDOW_Msk) >> WDT_FUSES_WINDOW_Pos);
+    fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
+            ((raw_user_row[1] & WDT_FUSES_WINDOW_Msk) >> WDT_FUSES_WINDOW_Pos);
 #else
-	/* WDT Windows timout lay between two 32-bit words in the user row. Because only one bit lays in word[0],
-	   bits in word[1] must be left sifted by one to make the correct number */
-	fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
-			(((raw_user_row[0] & WDT_FUSES_WINDOW_0_Msk) >> WDT_FUSES_WINDOW_0_Pos) |
-			((raw_user_row[1] & WDT_FUSES_WINDOW_1_Msk) << 1));
+    /* WDT Windows timout lay between two 32-bit words in the user row. Because only one bit lays in word[0],
+       bits in word[1] must be left sifted by one to make the correct number */
+    fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout)
+            (((raw_user_row[0] & WDT_FUSES_WINDOW_0_Msk) >> WDT_FUSES_WINDOW_0_Pos) |
+            ((raw_user_row[1] & WDT_FUSES_WINDOW_1_Msk) << 1));
 #endif
-	fusebits->wdt_early_warning_offset = (enum nvm_wdt_early_warning_offset)
-			((raw_user_row[1] & WDT_FUSES_EWOFFSET_Msk) >> WDT_FUSES_EWOFFSET_Pos);
+    fusebits->wdt_early_warning_offset = (enum nvm_wdt_early_warning_offset)
+            ((raw_user_row[1] & WDT_FUSES_EWOFFSET_Msk) >> WDT_FUSES_EWOFFSET_Pos);
 
-	fusebits->wdt_window_mode_enable_at_poweron = (bool)
-			((raw_user_row[1] & WDT_FUSES_WEN_Msk) >> WDT_FUSES_WEN_Pos);
+    fusebits->wdt_window_mode_enable_at_poweron = (bool)
+            ((raw_user_row[1] & WDT_FUSES_WEN_Msk) >> WDT_FUSES_WEN_Pos);
 
-	fusebits->lockbits = (uint16_t)
-			((raw_user_row[1] & NVMCTRL_FUSES_REGION_LOCKS_Msk)
-			>> NVMCTRL_FUSES_REGION_LOCKS_Pos);
+    fusebits->lockbits = (uint16_t)
+            ((raw_user_row[1] & NVMCTRL_FUSES_REGION_LOCKS_Msk)
+            >> NVMCTRL_FUSES_REGION_LOCKS_Pos);
 
 }
 
-///@endcond
+/*/@endcond*/
 
 /**
  * \brief Get fuses from user row.
@@ -930,24 +971,25 @@ static void _nvm_translate_raw_fusebits_to_struct (
  * \retval STATUS_OK   This function will always return STATUS_OK
  */
 enum status_code nvm_get_fuses (
-		struct nvm_fusebits *fusebits)
+        struct nvm_fusebits *fusebits)
 {
-	enum status_code error_code = STATUS_OK;
-	uint32_t raw_fusebits[2];
+    enum status_code error_code = STATUS_OK;
+    uint32_t raw_fusebits[2];
 
-	/* Make sure the module is ready */
-	while (!nvm_is_ready()) {
-	}
+    /* Make sure the module is ready */
+    while (!nvm_is_ready())
+    {
+    }
 
-	/* Read the fuse settings in the user row, 64 bit */
-	((uint16_t*)&raw_fusebits)[0] = (uint16_t)NVM_MEMORY[NVMCTRL_USER / 2];
-	((uint16_t*)&raw_fusebits)[1] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 1];
-	((uint16_t*)&raw_fusebits)[2] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 2];
-	((uint16_t*)&raw_fusebits)[3] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 3];
+    /* Read the fuse settings in the user row, 64 bit */
+    ((uint16_t*)&raw_fusebits)[0] = (uint16_t)NVM_MEMORY[NVMCTRL_USER / 2];
+    ((uint16_t*)&raw_fusebits)[1] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 1];
+    ((uint16_t*)&raw_fusebits)[2] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 2];
+    ((uint16_t*)&raw_fusebits)[3] = (uint16_t)NVM_MEMORY[(NVMCTRL_USER / 2) + 3];
 
-	_nvm_translate_raw_fusebits_to_struct(raw_fusebits, fusebits);
+    _nvm_translate_raw_fusebits_to_struct(raw_fusebits, fusebits);
 
-	return error_code;
+    return error_code;
 }
 
 /**
@@ -977,96 +1019,97 @@ enum status_code nvm_get_fuses (
 enum status_code nvm_set_fuses(struct nvm_fusebits *fb)
 {
     uint32_t fusebits[2];
-	enum status_code error_code = STATUS_OK;
+    enum status_code error_code = STATUS_OK;
 
-	if (fb == NULL) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (fb == NULL)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
     /* Read the fuse settings in the user row, 64 bit */
     fusebits[0] = *((uint32_t *)NVMCTRL_AUX0_ADDRESS);
     fusebits[1] = *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1);
 
-	/* Set user fuses bit */
-	fusebits[0] &= (~NVMCTRL_FUSES_BOOTPROT_Msk);
-	fusebits[0] |= NVMCTRL_FUSES_BOOTPROT(fb->bootloader_size);
+    /* Set user fuses bit */
+    fusebits[0] &= (~NVMCTRL_FUSES_BOOTPROT_Msk);
+    fusebits[0] |= NVMCTRL_FUSES_BOOTPROT(fb->bootloader_size);
 
-	fusebits[0] &= (~NVMCTRL_FUSES_EEPROM_SIZE_Msk);
-	fusebits[0] |= NVMCTRL_FUSES_EEPROM_SIZE(fb->eeprom_size);
+    fusebits[0] &= (~NVMCTRL_FUSES_EEPROM_SIZE_Msk);
+    fusebits[0] |= NVMCTRL_FUSES_EEPROM_SIZE(fb->eeprom_size);
 
 #if (SAML21) || (SAML22) || (SAMR30)
-	fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
-	fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
+    fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
+    fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
 
-	fusebits[0] &= (~FUSES_BOD33_DIS_Msk);
-	fusebits[0] |= (!fb->bod33_enable) << FUSES_BOD33_DIS_Pos;
+    fusebits[0] &= (~FUSES_BOD33_DIS_Msk);
+    fusebits[0] |= (!fb->bod33_enable) << FUSES_BOD33_DIS_Pos;
 
-	fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
-	fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
+    fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
+    fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
 
-	fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
-	fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
+    fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
+    fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
 
 #elif (SAMD20) || (SAMD21) || (SAMR21) || (SAMDA1) || (SAMD09) || (SAMD10) || (SAMD11) || (SAMHA1)
-	fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
-	fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
+    fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk);
+    fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level);
 
-	fusebits[0] &= (~FUSES_BOD33_EN_Msk);
-	fusebits[0] |= (fb->bod33_enable) << FUSES_BOD33_EN_Pos;
+    fusebits[0] &= (~FUSES_BOD33_EN_Msk);
+    fusebits[0] |= (fb->bod33_enable) << FUSES_BOD33_EN_Pos;
 
-	fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
-	fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
+    fusebits[0] &= (~FUSES_BOD33_ACTION_Msk);
+    fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos;
 
-	fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
-	fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
+    fusebits[1] &= (~FUSES_BOD33_HYST_Msk);
+    fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos;
 
 #elif (SAMC20) || (SAMC21)
-	fusebits[0] &= (~FUSES_BODVDDUSERLEVEL_Msk);
-	fusebits[0] |= FUSES_BODVDDUSERLEVEL(fb->bodvdd_level);
+    fusebits[0] &= (~FUSES_BODVDDUSERLEVEL_Msk);
+    fusebits[0] |= FUSES_BODVDDUSERLEVEL(fb->bodvdd_level);
 
-	fusebits[0] &= (~FUSES_BODVDD_DIS_Msk);
-	fusebits[0] |= (!fb->bodvdd_enable) << FUSES_BODVDD_DIS_Pos;
+    fusebits[0] &= (~FUSES_BODVDD_DIS_Msk);
+    fusebits[0] |= (!fb->bodvdd_enable) << FUSES_BODVDD_DIS_Pos;
 
-	fusebits[0] &= (~FUSES_BODVDD_ACTION_Msk);
-	fusebits[0] |= fb->bodvdd_action << FUSES_BODVDD_ACTION_Pos;
+    fusebits[0] &= (~FUSES_BODVDD_ACTION_Msk);
+    fusebits[0] |= fb->bodvdd_action << FUSES_BODVDD_ACTION_Pos;
 
-	fusebits[1] &= (~FUSES_BODVDD_HYST_Msk);
-	fusebits[1] |= fb->bodvdd_hysteresis << FUSES_BODVDD_HYST_Pos;
+    fusebits[1] &= (~FUSES_BODVDD_HYST_Msk);
+    fusebits[1] |= fb->bodvdd_hysteresis << FUSES_BODVDD_HYST_Pos;
 
 #endif
 
-	fusebits[0] &= (~WDT_FUSES_ENABLE_Msk);
-	fusebits[0] |= fb->wdt_enable << WDT_FUSES_ENABLE_Pos;
+    fusebits[0] &= (~WDT_FUSES_ENABLE_Msk);
+    fusebits[0] |= fb->wdt_enable << WDT_FUSES_ENABLE_Pos;
 
-	fusebits[0] &= (~WDT_FUSES_ALWAYSON_Msk);
-	fusebits[0] |= (fb->wdt_always_on) << WDT_FUSES_ALWAYSON_Pos;
+    fusebits[0] &= (~WDT_FUSES_ALWAYSON_Msk);
+    fusebits[0] |= (fb->wdt_always_on) << WDT_FUSES_ALWAYSON_Pos;
 
-	fusebits[0] &= (~WDT_FUSES_PER_Msk);
-	fusebits[0] |= fb->wdt_timeout_period << WDT_FUSES_PER_Pos;
+    fusebits[0] &= (~WDT_FUSES_PER_Msk);
+    fusebits[0] |= fb->wdt_timeout_period << WDT_FUSES_PER_Pos;
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	fusebits[1] &= (~WDT_FUSES_WINDOW_Msk);
-	fusebits[1] |= fb->wdt_window_timeout << WDT_FUSES_WINDOW_Pos;
+    fusebits[1] &= (~WDT_FUSES_WINDOW_Msk);
+    fusebits[1] |= fb->wdt_window_timeout << WDT_FUSES_WINDOW_Pos;
 #else
    /* WDT Windows timout lay between two 32-bit words in the user row. the last one bit lays in word[0],
-	   and the other bits in word[1] */
-	fusebits[0] &= (~WDT_FUSES_WINDOW_0_Msk);
-	fusebits[0] |= (fb->wdt_window_timeout & 0x1) << WDT_FUSES_WINDOW_0_Pos;
+       and the other bits in word[1] */
+    fusebits[0] &= (~WDT_FUSES_WINDOW_0_Msk);
+    fusebits[0] |= (fb->wdt_window_timeout & 0x1) << WDT_FUSES_WINDOW_0_Pos;
 
-	fusebits[1] &= (~WDT_FUSES_WINDOW_1_Msk);
-	fusebits[1] |= (fb->wdt_window_timeout >> 1) << WDT_FUSES_WINDOW_1_Pos;
+    fusebits[1] &= (~WDT_FUSES_WINDOW_1_Msk);
+    fusebits[1] |= (fb->wdt_window_timeout >> 1) << WDT_FUSES_WINDOW_1_Pos;
 
 #endif
-	fusebits[1] &= (~WDT_FUSES_EWOFFSET_Msk);
-	fusebits[1] |= fb->wdt_early_warning_offset << WDT_FUSES_EWOFFSET_Pos;
+    fusebits[1] &= (~WDT_FUSES_EWOFFSET_Msk);
+    fusebits[1] |= fb->wdt_early_warning_offset << WDT_FUSES_EWOFFSET_Pos;
 
-	fusebits[1] &= (~WDT_FUSES_WEN_Msk);
-	fusebits[1] |= fb->wdt_window_mode_enable_at_poweron << WDT_FUSES_WEN_Pos;
+    fusebits[1] &= (~WDT_FUSES_WEN_Msk);
+    fusebits[1] |= fb->wdt_window_mode_enable_at_poweron << WDT_FUSES_WEN_Pos;
 
-	fusebits[1] &= (~NVMCTRL_FUSES_REGION_LOCKS_Msk);
-	fusebits[1] |= fb->lockbits << NVMCTRL_FUSES_REGION_LOCKS_Pos;
+    fusebits[1] &= (~NVMCTRL_FUSES_REGION_LOCKS_Msk);
+    fusebits[1] |= fb->lockbits << NVMCTRL_FUSES_REGION_LOCKS_Pos;
 
 #ifdef FEATURE_BOD12
-	
+
 #ifndef FUSES_BOD12USERLEVEL_Pos
 #define FUSES_BOD12USERLEVEL_Pos 17
 #define FUSES_BOD12USERLEVEL_Msk (0x3Ful << FUSES_BOD12USERLEVEL_Pos)
@@ -1079,38 +1122,41 @@ enum status_code nvm_set_fuses(struct nvm_fusebits *fb)
 #define FUSES_BOD12_ACTION_Pos 24
 #define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos)
 #endif
-		
-	fusebits[0] &= (~FUSES_BOD12USERLEVEL_Msk);
-	fusebits[0] |= ((FUSES_BOD12USERLEVEL_Msk & ((fb->bod12_level) << 
-						FUSES_BOD12USERLEVEL_Pos)));
 
-	fusebits[0] &= (~FUSES_BOD12_DIS_Msk);
-	fusebits[0] |= (!fb->bod12_enable) << FUSES_BOD12_DIS_Pos;
+    fusebits[0] &= (~FUSES_BOD12USERLEVEL_Msk);
+    fusebits[0] |= ((FUSES_BOD12USERLEVEL_Msk & ((fb->bod12_level) <<
+                        FUSES_BOD12USERLEVEL_Pos)));
+
+    fusebits[0] &= (~FUSES_BOD12_DIS_Msk);
+    fusebits[0] |= (!fb->bod12_enable) << FUSES_BOD12_DIS_Pos;
 
-	fusebits[0] &= (~FUSES_BOD12_ACTION_Msk);
-	fusebits[0] |= fb->bod12_action << FUSES_BOD12_ACTION_Pos;
+    fusebits[0] &= (~FUSES_BOD12_ACTION_Msk);
+    fusebits[0] |= fb->bod12_action << FUSES_BOD12_ACTION_Pos;
 
-	fusebits[1] &= (~FUSES_BOD12_HYST_Msk);
-	fusebits[1] |= fb->bod12_hysteresis << FUSES_BOD12_HYST_Pos;
+    fusebits[1] &= (~FUSES_BOD12_HYST_Msk);
+    fusebits[1] |= fb->bod12_hysteresis << FUSES_BOD12_HYST_Pos;
 #endif
 
-	error_code = nvm_execute_command(NVM_COMMAND_ERASE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
-	if (error_code != STATUS_OK) {
-		return error_code;
-	}
+    error_code = nvm_execute_command(NVM_COMMAND_ERASE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
+    if (error_code != STATUS_OK)
+    {
+        return error_code;
+    }
 
-	error_code = nvm_execute_command(NVM_COMMAND_PAGE_BUFFER_CLEAR,NVMCTRL_AUX0_ADDRESS,0);
-	if (error_code != STATUS_OK) {
-		return error_code;
-	}
+    error_code = nvm_execute_command(NVM_COMMAND_PAGE_BUFFER_CLEAR,NVMCTRL_AUX0_ADDRESS,0);
+    if (error_code != STATUS_OK)
+    {
+        return error_code;
+    }
 
-	*((uint32_t *)NVMCTRL_AUX0_ADDRESS) = fusebits[0];
+    *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = fusebits[0];
     *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = fusebits[1];
 
-	error_code = nvm_execute_command(NVM_COMMAND_WRITE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
-	if (error_code != STATUS_OK) {
-		return error_code;
-	}
+    error_code = nvm_execute_command(NVM_COMMAND_WRITE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0);
+    if (error_code != STATUS_OK)
+    {
+        return error_code;
+    }
 
-	return error_code;
+    return error_code;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h
index 73b127d51759..119e8a578ea1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/nvm/nvm.h
@@ -276,11 +276,11 @@ extern "C" {
 
 /* Define SAMD21-64K devices */
 #if defined(SAMD21E15L) || defined(SAMD21E16L) || defined(__SAMD21E15L__) || defined(__SAMD21E16L__) \
-	|| defined(SAMD21E15B) || defined(SAMD21E16B) || defined(__SAMD21E15B__) || defined(__SAMD21E16B__) \
-	|| defined(SAMD21E15BU) || defined(SAMD21E16BU) || defined(__SAMD21E15BU__) || defined(__SAMD21E16BU__) \
-	|| defined(SAMD21G15L) || defined(SAMD21G16L) || defined(__SAMD21G15L__) || defined(__SAMD21G16L__) \
-	|| defined(SAMD21G15B) || defined(SAMD21G16B) || defined(__SAMD21G15B__) || defined(__SAMD21G16B__) \
-	|| defined(SAMD21J15B) || defined(SAMD21J16B) || defined(__SAMD21J15B__) || defined(__SAMD21J16B__)
+    || defined(SAMD21E15B) || defined(SAMD21E16B) || defined(__SAMD21E15B__) || defined(__SAMD21E16B__) \
+    || defined(SAMD21E15BU) || defined(SAMD21E16BU) || defined(__SAMD21E15BU__) || defined(__SAMD21E16BU__) \
+    || defined(SAMD21G15L) || defined(SAMD21G16L) || defined(__SAMD21G15L__) || defined(__SAMD21G16L__) \
+    || defined(SAMD21G15B) || defined(SAMD21G16B) || defined(__SAMD21G15B__) || defined(__SAMD21G16B__) \
+    || defined(SAMD21J15B) || defined(SAMD21J16B) || defined(__SAMD21J15B__) || defined(__SAMD21J16B__)
 
 #  define SAMD21_64K
 
@@ -293,7 +293,7 @@ extern "C" {
  * @{
 */
 #if (SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || (SAMR30) || defined(SAMD21_64K) || (SAMHA1) \
-	|| defined(__DOXYGEN__)
+    || defined(__DOXYGEN__)
 /** Read while write EEPROM emulation feature. */
 #  define FEATURE_NVM_RWWEE
 #endif
@@ -319,71 +319,71 @@ extern "C" {
  * controller after a command is issued.
  */
 enum nvm_error {
-	/** No errors */
-	NVM_ERROR_NONE = 0,
-	/** Lock error, a locked region was attempted accessed */
-	NVM_ERROR_LOCK = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_LOCKE,
-	/** Program error, invalid command was executed */
-	NVM_ERROR_PROG = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_PROGE,
+    /** No errors */
+    NVM_ERROR_NONE = 0,
+    /** Lock error, a locked region was attempted accessed */
+    NVM_ERROR_LOCK = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_LOCKE,
+    /** Program error, invalid command was executed */
+    NVM_ERROR_PROG = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_PROGE,
 };
 
 /**
  * \brief NVM controller commands.
  */
 enum nvm_command {
-	/** Erases the addressed memory row */
-	NVM_COMMAND_ERASE_ROW                  = NVMCTRL_CTRLA_CMD_ER,
-
-	/** Write the contents of the page buffer to the addressed memory page */
-	NVM_COMMAND_WRITE_PAGE                 = NVMCTRL_CTRLA_CMD_WP,
-
-	/** Erases the addressed auxiliary memory row.
-	 *
-	 *  \note This command can only be given when the security bit is not set.
-	 */
-	NVM_COMMAND_ERASE_AUX_ROW              = NVMCTRL_CTRLA_CMD_EAR,
-
-	/** Write the contents of the page buffer to the addressed auxiliary memory
-	 *  row.
-	 *
-	 *  \note This command can only be given when the security bit is not set.
-	 */
-	NVM_COMMAND_WRITE_AUX_ROW              = NVMCTRL_CTRLA_CMD_WAP,
-
-	/** Locks the addressed memory region, preventing further modifications
-	 *  until the region is unlocked or the device is erased
-	 */
-	NVM_COMMAND_LOCK_REGION                = NVMCTRL_CTRLA_CMD_LR,
-
-	/** Unlocks the addressed memory region, allowing the region contents to be
-	 *  modified
-	 */
-	NVM_COMMAND_UNLOCK_REGION              = NVMCTRL_CTRLA_CMD_UR,
-
-	/** Clears the page buffer of the NVM controller, resetting the contents to
-	 *  all zero values
-	 */
-	NVM_COMMAND_PAGE_BUFFER_CLEAR          = NVMCTRL_CTRLA_CMD_PBC,
-
-	/** Sets the device security bit, disallowing the changing of lock bits and
-	 *  auxiliary row data until a chip erase has been performed
-	 */
-	NVM_COMMAND_SET_SECURITY_BIT           = NVMCTRL_CTRLA_CMD_SSB,
-
-	/** Enter power reduction mode in the NVM controller to reduce the power
-	 *  consumption of the system
-	 */
-	NVM_COMMAND_ENTER_LOW_POWER_MODE       = NVMCTRL_CTRLA_CMD_SPRM,
-
-	/** Exit power reduction mode in the NVM controller to allow other NVM
-	 *  commands to be issued
-	 */
-	NVM_COMMAND_EXIT_LOW_POWER_MODE        = NVMCTRL_CTRLA_CMD_CPRM,
+    /** Erases the addressed memory row */
+    NVM_COMMAND_ERASE_ROW                  = NVMCTRL_CTRLA_CMD_ER,
+
+    /** Write the contents of the page buffer to the addressed memory page */
+    NVM_COMMAND_WRITE_PAGE                 = NVMCTRL_CTRLA_CMD_WP,
+
+    /** Erases the addressed auxiliary memory row.
+     *
+     *  \note This command can only be given when the security bit is not set.
+     */
+    NVM_COMMAND_ERASE_AUX_ROW              = NVMCTRL_CTRLA_CMD_EAR,
+
+    /** Write the contents of the page buffer to the addressed auxiliary memory
+     *  row.
+     *
+     *  \note This command can only be given when the security bit is not set.
+     */
+    NVM_COMMAND_WRITE_AUX_ROW              = NVMCTRL_CTRLA_CMD_WAP,
+
+    /** Locks the addressed memory region, preventing further modifications
+     *  until the region is unlocked or the device is erased
+     */
+    NVM_COMMAND_LOCK_REGION                = NVMCTRL_CTRLA_CMD_LR,
+
+    /** Unlocks the addressed memory region, allowing the region contents to be
+     *  modified
+     */
+    NVM_COMMAND_UNLOCK_REGION              = NVMCTRL_CTRLA_CMD_UR,
+
+    /** Clears the page buffer of the NVM controller, resetting the contents to
+     *  all zero values
+     */
+    NVM_COMMAND_PAGE_BUFFER_CLEAR          = NVMCTRL_CTRLA_CMD_PBC,
+
+    /** Sets the device security bit, disallowing the changing of lock bits and
+     *  auxiliary row data until a chip erase has been performed
+     */
+    NVM_COMMAND_SET_SECURITY_BIT           = NVMCTRL_CTRLA_CMD_SSB,
+
+    /** Enter power reduction mode in the NVM controller to reduce the power
+     *  consumption of the system
+     */
+    NVM_COMMAND_ENTER_LOW_POWER_MODE       = NVMCTRL_CTRLA_CMD_SPRM,
+
+    /** Exit power reduction mode in the NVM controller to allow other NVM
+     *  commands to be issued
+     */
+    NVM_COMMAND_EXIT_LOW_POWER_MODE        = NVMCTRL_CTRLA_CMD_CPRM,
 #ifdef FEATURE_NVM_RWWEE
-	/** Read while write (RWW) EEPROM area erase row */
-	NVM_COMMAND_RWWEE_ERASE_ROW            = NVMCTRL_CTRLA_CMD_RWWEEER,
-	/** RWW EEPROM write page */
-	NVM_COMMAND_RWWEE_WRITE_PAGE           = NVMCTRL_CTRLA_CMD_RWWEEWP,
+    /** Read while write (RWW) EEPROM area erase row */
+    NVM_COMMAND_RWWEE_ERASE_ROW            = NVMCTRL_CTRLA_CMD_RWWEEER,
+    /** RWW EEPROM write page */
+    NVM_COMMAND_RWWEE_WRITE_PAGE           = NVMCTRL_CTRLA_CMD_RWWEEWP,
 #endif
 };
 
@@ -394,12 +394,12 @@ enum nvm_command {
  * device is in sleep.
  */
 enum nvm_sleep_power_mode {
-	/** NVM controller exits low-power mode on first access after sleep */
-	NVM_SLEEP_POWER_MODE_WAKEONACCESS  = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val,
-	/** NVM controller exits low-power mode when the device exits sleep mode */
-	NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val,
-	/** Power reduction mode in the NVM controller disabled */
-	NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE  = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val,
+    /** NVM controller exits low-power mode on first access after sleep */
+    NVM_SLEEP_POWER_MODE_WAKEONACCESS  = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val,
+    /** NVM controller exits low-power mode when the device exits sleep mode */
+    NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val,
+    /** Power reduction mode in the NVM controller disabled */
+    NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE  = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val,
 };
 
 /**
@@ -409,19 +409,19 @@ enum nvm_sleep_power_mode {
  *
  */
 enum nvm_cache_readmode {
-	/** The NVM Controller (cache system) does not insert wait states on
-	 *  a cache miss. Gives the best system performance.
-	 */
-	NVM_CACHE_READMODE_NO_MISS_PENALTY,
-	/** Reduces power consumption of the cache system, but inserts a
-	 *  wait state each time there is a cache miss
-	 */
-	NVM_CACHE_READMODE_LOW_POWER,
-	/** The cache system ensures that a cache hit or miss takes the same
-	 *  amount of time, determined by the number of programmed flash
-	 *  wait states
-	 */
-	NVM_CACHE_READMODE_DETERMINISTIC,
+    /** The NVM Controller (cache system) does not insert wait states on
+     *  a cache miss. Gives the best system performance.
+     */
+    NVM_CACHE_READMODE_NO_MISS_PENALTY,
+    /** Reduces power consumption of the cache system, but inserts a
+     *  wait state each time there is a cache miss
+     */
+    NVM_CACHE_READMODE_LOW_POWER,
+    /** The cache system ensures that a cache hit or miss takes the same
+     *  amount of time, determined by the number of programmed flash
+     *  wait states
+     */
+    NVM_CACHE_READMODE_DETERMINISTIC,
 };
 
 /**
@@ -430,39 +430,39 @@ enum nvm_cache_readmode {
  * Configuration structure for the NVM controller within the device.
  */
 struct nvm_config {
-	/** Power reduction mode during device sleep */
-	enum nvm_sleep_power_mode sleep_power_mode;
-	/** Manual write mode; if enabled, pages loaded into the NVM buffer will
-	 *  not be written until a separate write command is issued. If disabled,
-	 *  writing to the last byte in the NVM page buffer will trigger an automatic
-	 *  write.
-	 *
-	 *  \note If a partial page is to be written, a manual write command must be
-	 *        executed in either mode.
-	 */
-	bool manual_page_write;
-	/** Number of wait states to insert when reading from flash, to prevent
-	 *  invalid data from being read at high clock frequencies
-	 */
-	uint8_t wait_states;
-
-	/**
-	 * Setting this to true will disable the pre-fetch cache in front of the
-	 * NVM controller
-	 */
-	bool disable_cache;
+    /** Power reduction mode during device sleep */
+    enum nvm_sleep_power_mode sleep_power_mode;
+    /** Manual write mode; if enabled, pages loaded into the NVM buffer will
+     *  not be written until a separate write command is issued. If disabled,
+     *  writing to the last byte in the NVM page buffer will trigger an automatic
+     *  write.
+     *
+     *  \note If a partial page is to be written, a manual write command must be
+     *        executed in either mode.
+     */
+    bool manual_page_write;
+    /** Number of wait states to insert when reading from flash, to prevent
+     *  invalid data from being read at high clock frequencies
+     */
+    uint8_t wait_states;
+
+    /**
+     * Setting this to true will disable the pre-fetch cache in front of the
+     * NVM controller
+     */
+    bool disable_cache;
 #if (SAMC20) || (SAMC21)
-	/**
-	 * Setting this to true will disable the pre-fetch RWW cache in front of the
-	 * NVM controller.
-	 * If RWW cache is enabled, NVM cache will also be enabled.
-	 */
-	bool disable_rww_cache;
+    /**
+     * Setting this to true will disable the pre-fetch RWW cache in front of the
+     * NVM controller.
+     * If RWW cache is enabled, NVM cache will also be enabled.
+     */
+    bool disable_rww_cache;
 #endif
-	/**
-	 * Select the mode for  how the cache will pre-fetch data from the flash
-	 */
-	enum nvm_cache_readmode cache_readmode;
+    /**
+     * Select the mode for  how the cache will pre-fetch data from the flash
+     */
+    enum nvm_cache_readmode cache_readmode;
 };
 
 /**
@@ -471,19 +471,19 @@ struct nvm_config {
  * Structure containing the memory layout parameters of the NVM module.
  */
 struct nvm_parameters {
-	/** Number of bytes per page */
-	uint8_t  page_size;
-	/** Number of pages in the main array */
-	uint16_t nvm_number_of_pages;
-	/** Size of the emulated EEPROM memory section configured in the NVM
-	 *  auxiliary memory space */
-	uint32_t eeprom_number_of_pages;
-	/** Size of the Bootloader memory section configured in the NVM auxiliary
-	 *  memory space */
-	uint32_t bootloader_number_of_pages;
+    /** Number of bytes per page */
+    uint8_t  page_size;
+    /** Number of pages in the main array */
+    uint16_t nvm_number_of_pages;
+    /** Size of the emulated EEPROM memory section configured in the NVM
+     *  auxiliary memory space */
+    uint32_t eeprom_number_of_pages;
+    /** Size of the Bootloader memory section configured in the NVM auxiliary
+     *  memory space */
+    uint32_t bootloader_number_of_pages;
 #ifdef FEATURE_NVM_RWWEE
-	/** Number of pages in read while write EEPROM (RWWEE) emulation area */
-	uint16_t rww_eeprom_number_of_pages;
+    /** Number of pages in read while write EEPROM (RWWEE) emulation area */
+    uint16_t rww_eeprom_number_of_pages;
 #endif
 };
 
@@ -494,22 +494,22 @@ struct nvm_parameters {
  *
  */
 enum nvm_bootloader_size {
-	/** Boot Loader Size is 32768 bytes */
-	NVM_BOOTLOADER_SIZE_128,
-	/** Boot Loader Size is 16384 bytes */
-	NVM_BOOTLOADER_SIZE_64,
-	/** Boot Loader Size is 8192 bytes */
-	NVM_BOOTLOADER_SIZE_32,
-	/** Boot Loader Size is 4096 bytes */
-	NVM_BOOTLOADER_SIZE_16,
-	/** Boot Loader Size is 2048 bytes */
-	NVM_BOOTLOADER_SIZE_8,
-	/** Boot Loader Size is 1024 bytes */
-	NVM_BOOTLOADER_SIZE_4,
-	/** Boot Loader Size is 512 bytes */
-	NVM_BOOTLOADER_SIZE_2,
-	/** Boot Loader Size is 0 bytes */
-	NVM_BOOTLOADER_SIZE_0,
+    /** Boot Loader Size is 32768 bytes */
+    NVM_BOOTLOADER_SIZE_128,
+    /** Boot Loader Size is 16384 bytes */
+    NVM_BOOTLOADER_SIZE_64,
+    /** Boot Loader Size is 8192 bytes */
+    NVM_BOOTLOADER_SIZE_32,
+    /** Boot Loader Size is 4096 bytes */
+    NVM_BOOTLOADER_SIZE_16,
+    /** Boot Loader Size is 2048 bytes */
+    NVM_BOOTLOADER_SIZE_8,
+    /** Boot Loader Size is 1024 bytes */
+    NVM_BOOTLOADER_SIZE_4,
+    /** Boot Loader Size is 512 bytes */
+    NVM_BOOTLOADER_SIZE_2,
+    /** Boot Loader Size is 0 bytes */
+    NVM_BOOTLOADER_SIZE_0,
 };
 
 /**
@@ -519,22 +519,22 @@ enum nvm_bootloader_size {
  *
  */
 enum nvm_eeprom_emulator_size {
-	/** EEPROM Size for EEPROM emulation is 16384 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_16384,
-	/** EEPROM Size for EEPROM emulation is 8192 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_8192,
-	/** EEPROM Size for EEPROM emulation is 4096 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_4096,
-	/** EEPROM Size for EEPROM emulation is 2048 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_2048,
-	/** EEPROM Size for EEPROM emulation is 1024 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_1024,
-	/** EEPROM Size for EEPROM emulation is 512 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_512,
-	/** EEPROM Size for EEPROM emulation is 256 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_256,
-	/** EEPROM Size for EEPROM emulation is 0 bytes */
-	NVM_EEPROM_EMULATOR_SIZE_0,
+    /** EEPROM Size for EEPROM emulation is 16384 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_16384,
+    /** EEPROM Size for EEPROM emulation is 8192 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_8192,
+    /** EEPROM Size for EEPROM emulation is 4096 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_4096,
+    /** EEPROM Size for EEPROM emulation is 2048 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_2048,
+    /** EEPROM Size for EEPROM emulation is 1024 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_1024,
+    /** EEPROM Size for EEPROM emulation is 512 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_512,
+    /** EEPROM Size for EEPROM emulation is 256 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_256,
+    /** EEPROM Size for EEPROM emulation is 0 bytes */
+    NVM_EEPROM_EMULATOR_SIZE_0,
 };
 
 /**
@@ -544,12 +544,12 @@ enum nvm_eeprom_emulator_size {
  *
  */
 enum nvm_bod33_action {
-	/** No action */
-	NVM_BOD33_ACTION_NONE,
-	/** The BOD33 generates a reset */
-	NVM_BOD33_ACTION_RESET,
-	/** The BOD33 generates an interrupt */
-	NVM_BOD33_ACTION_INTERRUPT,
+    /** No action */
+    NVM_BOD33_ACTION_NONE,
+    /** The BOD33 generates a reset */
+    NVM_BOD33_ACTION_RESET,
+    /** The BOD33 generates an interrupt */
+    NVM_BOD33_ACTION_INTERRUPT,
 };
 
 #ifdef FEATURE_BOD12
@@ -560,12 +560,12 @@ enum nvm_bod33_action {
  *
  */
 enum nvm_bod12_action {
-	/** No action */
-	NVM_BOD12_ACTION_NONE,
-	/** The BOD12 generates a reset */
-	NVM_BOD12_ACTION_RESET,
-	/** The BOD12 generates an interrupt */
-	NVM_BOD12_ACTION_INTERRUPT,
+    /** No action */
+    NVM_BOD12_ACTION_NONE,
+    /** The BOD12 generates a reset */
+    NVM_BOD12_ACTION_RESET,
+    /** The BOD12 generates an interrupt */
+    NVM_BOD12_ACTION_INTERRUPT,
 };
 #endif
 
@@ -576,30 +576,30 @@ enum nvm_bod12_action {
  *
  */
 enum nvm_wdt_window_timeout {
-	/** 8 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8,
-	/** 16 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16,
-	/** 32 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_32,
-	/** 64 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_64,
-	/** 128 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_128,
-	/** 256 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_256,
-	/** 512 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_512,
-	/** 1024 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_1024,
-	/** 2048 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_2048,
-	/** 4096 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_4096,
-	/** 8192 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_8192,
-	/** 16384 clock cycles */
-	NVM_WDT_WINDOW_TIMEOUT_PERIOD_16384,
+    /** 8 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_8,
+    /** 16 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_16,
+    /** 32 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_32,
+    /** 64 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_64,
+    /** 128 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_128,
+    /** 256 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_256,
+    /** 512 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_512,
+    /** 1024 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_1024,
+    /** 2048 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_2048,
+    /** 4096 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_4096,
+    /** 8192 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_8192,
+    /** 16384 clock cycles */
+    NVM_WDT_WINDOW_TIMEOUT_PERIOD_16384,
 };
 
 /**
@@ -610,30 +610,30 @@ enum nvm_wdt_window_timeout {
  *
  */
 enum nvm_wdt_early_warning_offset {
-	/** 8 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_8,
-	/** 16 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_16,
-	/** 32 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_32,
-	/** 64 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_64,
-	/** 128 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_128,
-	/** 256 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_256,
-	/** 512 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_512,
-	/** 1024 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_1024,
-	/** 2048 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_2048,
-	/** 4096 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_4096,
-	/** 8192 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_8192,
-	/** 16384 clock cycles */
-	NVM_WDT_EARLY_WARNING_OFFSET_16384,
+    /** 8 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_8,
+    /** 16 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_16,
+    /** 32 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_32,
+    /** 64 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_64,
+    /** 128 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_128,
+    /** 256 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_256,
+    /** 512 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_512,
+    /** 1024 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_1024,
+    /** 2048 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_2048,
+    /** 4096 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_4096,
+    /** 8192 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_8192,
+    /** 16384 clock cycles */
+    NVM_WDT_EARLY_WARNING_OFFSET_16384,
 };
 
 /**
@@ -643,52 +643,52 @@ enum nvm_wdt_early_warning_offset {
  * which contain the fuse settings.
  */
 struct nvm_fusebits {
-	/** Bootloader size */
-	enum nvm_bootloader_size          bootloader_size;
-	/** EEPROM emulation area size */
-	enum nvm_eeprom_emulator_size     eeprom_size;
+    /** Bootloader size */
+    enum nvm_bootloader_size          bootloader_size;
+    /** EEPROM emulation area size */
+    enum nvm_eeprom_emulator_size     eeprom_size;
 #if (SAMC20) || (SAMC21)
-	/** BODVDD Threshold level at power on */
-	uint8_t                           bodvdd_level;
-	/** BODVDD Enable at power on */
-	bool                              bodvdd_enable;
-	/** BODVDD Action at power on */
-	enum nvm_bod33_action             bodvdd_action;
-	/* BODVDD Hysteresis at power on */
-	bool                              bodvdd_hysteresis;
+    /** BODVDD Threshold level at power on */
+    uint8_t                           bodvdd_level;
+    /** BODVDD Enable at power on */
+    bool                              bodvdd_enable;
+    /** BODVDD Action at power on */
+    enum nvm_bod33_action             bodvdd_action;
+    /* BODVDD Hysteresis at power on */
+    bool                              bodvdd_hysteresis;
 #else
-	/** BOD33 Threshold level at power on */
-	uint8_t                           bod33_level;
-	/** BOD33 Enable at power on */
-	bool                              bod33_enable;
-	/** BOD33 Action at power on */
-	enum nvm_bod33_action             bod33_action;
-	/* BOD33 Hysteresis at power on */
-	bool                              bod33_hysteresis;
+    /** BOD33 Threshold level at power on */
+    uint8_t                           bod33_level;
+    /** BOD33 Enable at power on */
+    bool                              bod33_enable;
+    /** BOD33 Action at power on */
+    enum nvm_bod33_action             bod33_action;
+    /* BOD33 Hysteresis at power on */
+    bool                              bod33_hysteresis;
 #endif
-	/** WDT Enable at power on */
-	bool                              wdt_enable;
-	/** WDT Always-on at power on */
-	bool                              wdt_always_on;
-	/** WDT Period at power on */
-	uint8_t                           wdt_timeout_period;
-	/** WDT Window mode time-out at power on */
-	enum nvm_wdt_window_timeout       wdt_window_timeout;
-	/** WDT Early warning interrupt time offset at power on */
-	enum nvm_wdt_early_warning_offset wdt_early_warning_offset;
-	/** WDT Window mode enabled at power on */
-	bool                              wdt_window_mode_enable_at_poweron;
-	/** NVM Lock bits */
-	uint16_t                          lockbits;
+    /** WDT Enable at power on */
+    bool                              wdt_enable;
+    /** WDT Always-on at power on */
+    bool                              wdt_always_on;
+    /** WDT Period at power on */
+    uint8_t                           wdt_timeout_period;
+    /** WDT Window mode time-out at power on */
+    enum nvm_wdt_window_timeout       wdt_window_timeout;
+    /** WDT Early warning interrupt time offset at power on */
+    enum nvm_wdt_early_warning_offset wdt_early_warning_offset;
+    /** WDT Window mode enabled at power on */
+    bool                              wdt_window_mode_enable_at_poweron;
+    /** NVM Lock bits */
+    uint16_t                          lockbits;
 #ifdef FEATURE_BOD12
-	/** BOD12 Threshold level at power on */
-	uint8_t                           bod12_level;
-	/** BOD12 Enable at power on */
-	bool                              bod12_enable;
-	/** BOD12 Action at power on */
-	enum nvm_bod12_action             bod12_action;
-	/* BOD12 Hysteresis at power on */
-	bool                              bod12_hysteresis;
+    /** BOD12 Threshold level at power on */
+    uint8_t                           bod12_level;
+    /** BOD12 Enable at power on */
+    bool                              bod12_enable;
+    /** BOD12 Action at power on */
+    enum nvm_bod12_action             bod12_action;
+    /* BOD12 Hysteresis at power on */
+    bool                              bod12_hysteresis;
 #endif
 };
 
@@ -714,24 +714,24 @@ struct nvm_fusebits {
  *
  */
 static inline void nvm_get_config_defaults(
-		struct nvm_config *const config)
+        struct nvm_config *const config)
 {
-	/* Sanity check the parameters */
-	Assert(config);
-
-	/* Write the default configuration for the NVM configuration */
-	config->sleep_power_mode  = NVM_SLEEP_POWER_MODE_WAKEONACCESS;
-	config->manual_page_write = true;
-	config->wait_states       = NVMCTRL->CTRLB.bit.RWS;
-	config->disable_cache     = false;
+    /* Sanity check the parameters */
+    Assert(config);
+
+    /* Write the default configuration for the NVM configuration */
+    config->sleep_power_mode  = NVM_SLEEP_POWER_MODE_WAKEONACCESS;
+    config->manual_page_write = true;
+    config->wait_states       = NVMCTRL->CTRLB.bit.RWS;
+    config->disable_cache     = false;
 #if (SAMC20) || (SAMC21)
-	config->disable_rww_cache = false;
+    config->disable_rww_cache = false;
 #endif
-	config->cache_readmode    = NVM_CACHE_READMODE_NO_MISS_PENALTY;
+    config->cache_readmode    = NVM_CACHE_READMODE_NO_MISS_PENALTY;
 }
 
 enum status_code nvm_set_config(
-		const struct nvm_config *const config);
+        const struct nvm_config *const config);
 
 /**
  * \brief Checks if the NVM controller is ready to accept a new command.
@@ -747,10 +747,10 @@ enum status_code nvm_set_config(
  */
 static inline bool nvm_is_ready(void)
 {
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
+    return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
 }
 
 /** @} */
@@ -761,31 +761,31 @@ static inline bool nvm_is_ready(void)
  */
 
 void nvm_get_parameters(
-		struct nvm_parameters *const parameters);
+        struct nvm_parameters *const parameters);
 
 enum status_code nvm_write_buffer(
-		const uint32_t destination_address,
-		const uint8_t *buffer,
-		uint16_t length);
+        const uint32_t destination_address,
+        const uint8_t *buffer,
+        uint16_t length);
 
 enum status_code nvm_read_buffer(
-		const uint32_t source_address,
-		uint8_t *const buffer,
-		uint16_t length);
+        const uint32_t source_address,
+        uint8_t *const buffer,
+        uint16_t length);
 
 enum status_code nvm_update_buffer(
-		const uint32_t destination_address,
-		uint8_t *const buffer,
-		uint16_t offset,
-		uint16_t length);
+        const uint32_t destination_address,
+        uint8_t *const buffer,
+        uint16_t offset,
+        uint16_t length);
 
 enum status_code nvm_erase_row(
-		const uint32_t row_address);
+        const uint32_t row_address);
 
 enum status_code nvm_execute_command(
-		const enum nvm_command command,
-		const uint32_t address,
-		const uint32_t parameter);
+        const enum nvm_command command,
+        const uint32_t address,
+        const uint32_t parameter);
 
 enum status_code nvm_get_fuses(struct nvm_fusebits *fusebits);
 enum status_code nvm_set_fuses(struct nvm_fusebits *fb);
@@ -812,19 +812,19 @@ bool nvm_is_page_locked(uint16_t page_number);
  */
 static inline enum nvm_error nvm_get_error(void)
 {
-	enum nvm_error ret_val;
+    enum nvm_error ret_val;
 
-	/* Get a pointer to the module hardware instance */
-	Nvmctrl *const nvm_module = NVMCTRL;
+    /* Get a pointer to the module hardware instance */
+    Nvmctrl *const nvm_module = NVMCTRL;
 
-	/* Mask out non-error bits */
-	ret_val = (enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK);
+    /* Mask out non-error bits */
+    ret_val = (enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK);
 
-	/* Clear error flags */
-	nvm_module->STATUS.reg = NVM_ERRORS_MASK;
+    /* Clear error flags */
+    nvm_module->STATUS.reg = NVM_ERRORS_MASK;
 
-	/* Return error code from the NVM controller */
-	return ret_val;
+    /* Return error code from the NVM controller */
+    return ret_val;
 }
 
 /** @} */
@@ -874,25 +874,25 @@ static inline enum nvm_error nvm_get_error(void)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Removed BOD12 reference, removed nvm_set_fuses() API</td>
- *	</tr>
- *	<tr>
- *		<td>Added functions to read/write fuse settings</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for NVM cache configuration</td>
- *	</tr>
- *	<tr>
- *		<td>Updated initialization function to also enable the digital interface
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Removed BOD12 reference, removed nvm_set_fuses() API</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added functions to read/write fuse settings</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for NVM cache configuration</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Updated initialization function to also enable the digital interface
  *          clock to the module if it is disabled</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -910,36 +910,36 @@ static inline enum nvm_error nvm_get_error(void)
  * \page asfdoc_sam0_nvm_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42114E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42114D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42114C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42114B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42114A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42114E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42114D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42114C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42114B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42114A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c
index 96fb85e11cfb..b2a1323afd8a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.c
@@ -48,230 +48,257 @@
 
 void opamp_module_init(void)
 {
-	struct system_clock_source_osculp32k_config config;
+    struct system_clock_source_osculp32k_config config;
 
-	/* Enable the OSCULP32K clock. */
-	system_clock_source_osculp32k_get_config_defaults(&config);
-	system_clock_source_osculp32k_set_config(&config);
+    /* Enable the OSCULP32K clock. */
+    system_clock_source_osculp32k_get_config_defaults(&config);
+    system_clock_source_osculp32k_set_config(&config);
 
-	/* Turn on the digital interface clock. */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_OPAMP);
+    /* Turn on the digital interface clock. */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_OPAMP);
 
-	/* Reset module. */
-	opamp_module_reset();
+    /* Reset module. */
+    opamp_module_reset();
 
-	/* Enable module. */
-	opamp_module_enable();
+    /* Enable module. */
+    opamp_module_enable();
 }
 
 static inline void _opamp_get_config_common_defaults(
-		struct opamp_config_common *const config)
+        struct opamp_config_common *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->potentiometer_selection = OPAMP_POT_MUX_8R_8R;
-	config->r1_enable = false;
-	config->r2_vcc = false;
-	config->r2_out = false;
-	config->on_demand = false;
-	config->run_in_standby = false;
-	config->bias_value = OPAMP_BIAS_MODE_0;
-	config->analog_out = false;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->potentiometer_selection = OPAMP_POT_MUX_8R_8R;
+    config->r1_enable = false;
+    config->r2_vcc = false;
+    config->r2_out = false;
+    config->on_demand = false;
+    config->run_in_standby = false;
+    config->bias_value = OPAMP_BIAS_MODE_0;
+    config->analog_out = false;
 }
 
 void opamp0_get_config_defaults(struct opamp0_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	_opamp_get_config_common_defaults(&(config->config_common));
+    _opamp_get_config_common_defaults(&(config->config_common));
 
-	/* Default configuration values */
-	config->negative_input = OPAMP0_NEG_MUX_OUT0;
-	config->positive_input = OPAMP0_POS_MUX_PIN0;
-	config->r1_connection = OPAMP0_RES1_MUX_GND;
+    /* Default configuration values */
+    config->negative_input = OPAMP0_NEG_MUX_OUT0;
+    config->positive_input = OPAMP0_POS_MUX_PIN0;
+    config->r1_connection = OPAMP0_RES1_MUX_GND;
 }
 
 void opamp1_get_config_defaults(struct opamp1_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	_opamp_get_config_common_defaults(&(config->config_common));
+    _opamp_get_config_common_defaults(&(config->config_common));
 
-	/* Default configuration values */
-	config->negative_input = OPAMP1_NEG_MUX_OUT1;
-	config->positive_input = OPAMP1_POS_MUX_PIN1;
-	config->r1_connection = OPAMP1_RES1_MUX_GND;
+    /* Default configuration values */
+    config->negative_input = OPAMP1_NEG_MUX_OUT1;
+    config->positive_input = OPAMP1_POS_MUX_PIN1;
+    config->r1_connection = OPAMP1_RES1_MUX_GND;
 }
 
 void opamp2_get_config_defaults(struct opamp2_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	_opamp_get_config_common_defaults(&(config->config_common));
+    _opamp_get_config_common_defaults(&(config->config_common));
 
-	/* Default configuration values */
-	config->negative_input = OPAMP2_NEG_MUX_OUT2;
-	config->positive_input = OPAMP2_POS_MUX_PIN2;
-	config->r1_connection = OPAMP2_RES1_MUX_GND;
+    /* Default configuration values */
+    config->negative_input = OPAMP2_NEG_MUX_OUT2;
+    config->positive_input = OPAMP2_POS_MUX_PIN2;
+    config->r1_connection = OPAMP2_RES1_MUX_GND;
 }
 
 void opamp0_set_config(struct opamp0_config *const config)
 {
-	uint32_t temp = 0;
-
-	if (config->config_common.r1_enable) {
-		temp |= OPAMP_OPAMPCTRL_RES1EN;
-	}
-
-	if (config->config_common.r2_vcc) {
-		temp |= OPAMP_OPAMPCTRL_RES2VCC;
-	}
-
-	if (config->config_common.r2_out) {
-		temp |= OPAMP_OPAMPCTRL_RES2OUT;
-	}
-
-	if (config->config_common.on_demand) {
-		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
-	}
-
-	if (config->config_common.run_in_standby) {
-		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
-	}
-
-	if (config->config_common.analog_out) {
-		temp |= OPAMP_OPAMPCTRL_ANAOUT;
-	}
-
-	OPAMP->OPAMPCTRL[0].reg = temp |
-		config->config_common.potentiometer_selection |
-		config->config_common.bias_value |
-		config->negative_input |
-		config->positive_input|
-		config->r1_connection;
+    uint32_t temp = 0;
+
+    if (config->config_common.r1_enable)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES1EN;
+    }
+
+    if (config->config_common.r2_vcc)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2VCC;
+    }
+
+    if (config->config_common.r2_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2OUT;
+    }
+
+    if (config->config_common.on_demand)
+    {
+        temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+    }
+
+    if (config->config_common.run_in_standby)
+    {
+        temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+    }
+
+    if (config->config_common.analog_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_ANAOUT;
+    }
+
+    OPAMP->OPAMPCTRL[0].reg = temp |
+        config->config_common.potentiometer_selection |
+        config->config_common.bias_value |
+        config->negative_input |
+        config->positive_input|
+        config->r1_connection;
 }
 
 void opamp1_set_config(struct opamp1_config *const config)
 {
-	uint32_t temp = 0;
-
-	if (config->config_common.r1_enable) {
-		temp |= OPAMP_OPAMPCTRL_RES1EN;
-	}
-
-	if (config->config_common.r2_vcc) {
-		temp |= OPAMP_OPAMPCTRL_RES2VCC;
-	}
-
-	if (config->config_common.r2_out) {
-		temp |= OPAMP_OPAMPCTRL_RES2OUT;
-	}
-
-	if (config->config_common.on_demand) {
-		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
-	}
-
-	if (config->config_common.run_in_standby) {
-		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
-	}
-
-	if (config->config_common.analog_out) {
-		temp |= OPAMP_OPAMPCTRL_ANAOUT;
-	}
-
-	OPAMP->OPAMPCTRL[1].reg = temp |
-		config->config_common.potentiometer_selection |
-		config->config_common.bias_value |
-		config->negative_input |
-		config->positive_input|
-		config->r1_connection;
+    uint32_t temp = 0;
+
+    if (config->config_common.r1_enable)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES1EN;
+    }
+
+    if (config->config_common.r2_vcc)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2VCC;
+    }
+
+    if (config->config_common.r2_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2OUT;
+    }
+
+    if (config->config_common.on_demand)
+    {
+        temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+    }
+
+    if (config->config_common.run_in_standby)
+    {
+        temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+    }
+
+    if (config->config_common.analog_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_ANAOUT;
+    }
+
+    OPAMP->OPAMPCTRL[1].reg = temp |
+        config->config_common.potentiometer_selection |
+        config->config_common.bias_value |
+        config->negative_input |
+        config->positive_input|
+        config->r1_connection;
 }
 
 void opamp2_set_config(struct opamp2_config *const config)
 {
-	uint32_t temp = 0;
-
-	if (config->config_common.r1_enable) {
-		temp |= OPAMP_OPAMPCTRL_RES1EN;
-	}
-
-	if (config->config_common.r2_vcc) {
-		temp |= OPAMP_OPAMPCTRL_RES2VCC;
-	}
-
-	if (config->config_common.r2_out) {
-		temp |= OPAMP_OPAMPCTRL_RES2OUT;
-	}
-
-	if (config->config_common.on_demand) {
-		temp |= OPAMP_OPAMPCTRL_ONDEMAND;
-	}
-
-	if (config->config_common.run_in_standby) {
-		temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
-	}
-
-	if (config->config_common.analog_out) {
-		temp |= OPAMP_OPAMPCTRL_ANAOUT;
-	}
-
-	OPAMP->OPAMPCTRL[2].reg = temp |
-		config->config_common.potentiometer_selection |
-		config->config_common.bias_value |
-		config->negative_input |
-		config->positive_input|
-		config->r1_connection;
+    uint32_t temp = 0;
+
+    if (config->config_common.r1_enable)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES1EN;
+    }
+
+    if (config->config_common.r2_vcc)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2VCC;
+    }
+
+    if (config->config_common.r2_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_RES2OUT;
+    }
+
+    if (config->config_common.on_demand)
+    {
+        temp |= OPAMP_OPAMPCTRL_ONDEMAND;
+    }
+
+    if (config->config_common.run_in_standby)
+    {
+        temp |= OPAMP_OPAMPCTRL_RUNSTDBY;
+    }
+
+    if (config->config_common.analog_out)
+    {
+        temp |= OPAMP_OPAMPCTRL_ANAOUT;
+    }
+
+    OPAMP->OPAMPCTRL[2].reg = temp |
+        config->config_common.potentiometer_selection |
+        config->config_common.bias_value |
+        config->negative_input |
+        config->positive_input|
+        config->r1_connection;
 }
 
 void opamp_enable(const enum opamp_id number)
 {
-	/* Sanity check arguments */
-	Assert(number);
-
-	/* Enable the OPAMP */
-	if (number == OPAMP_0) {
-		OPAMP->OPAMPCTRL[0].reg |= OPAMP_OPAMPCTRL_ENABLE;
-	} else if (number == OPAMP_1) {
-		OPAMP->OPAMPCTRL[1].reg |= OPAMP_OPAMPCTRL_ENABLE;
-	} else if (number == OPAMP_2) {
-		OPAMP->OPAMPCTRL[2].reg |= OPAMP_OPAMPCTRL_ENABLE;
-	}
+    /* Sanity check arguments */
+    Assert(number);
+
+    /* Enable the OPAMP */
+    if (number == OPAMP_0)
+    {
+        OPAMP->OPAMPCTRL[0].reg |= OPAMP_OPAMPCTRL_ENABLE;
+    } else if (number == OPAMP_1)
+    {
+        OPAMP->OPAMPCTRL[1].reg |= OPAMP_OPAMPCTRL_ENABLE;
+    } else if (number == OPAMP_2)
+    {
+        OPAMP->OPAMPCTRL[2].reg |= OPAMP_OPAMPCTRL_ENABLE;
+    }
 }
 
 void opamp_disable(const enum opamp_id number)
 {
-	/* Sanity check arguments */
-	Assert(number);
-
-	/* Disable the OPAMP */
-	if (number == OPAMP_0) {
-		OPAMP->OPAMPCTRL[0].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
-	} else if (number == OPAMP_1) {
-		OPAMP->OPAMPCTRL[1].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
-	} else if (number == OPAMP_2) {
-		OPAMP->OPAMPCTRL[2].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
-	}
+    /* Sanity check arguments */
+    Assert(number);
+
+    /* Disable the OPAMP */
+    if (number == OPAMP_0)
+    {
+        OPAMP->OPAMPCTRL[0].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+    } else if (number == OPAMP_1)
+    {
+        OPAMP->OPAMPCTRL[1].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+    } else if (number == OPAMP_2)
+    {
+        OPAMP->OPAMPCTRL[2].reg &= ~OPAMP_OPAMPCTRL_ENABLE;
+    }
 }
 
 bool opamp_is_ready(const enum opamp_id number)
 {
-	/* Sanity check arguments */
-	Assert(number);
-
-	/* Get the OPAMP output ready status*/
-	if (number == OPAMP_0) {
-		return OPAMP->STATUS.bit.READY0;
-	} else if (number == OPAMP_1) {
-		return OPAMP->STATUS.bit.READY1;
-	} else if (number == OPAMP_2) {
-		return OPAMP->STATUS.bit.READY2;
-	}
-
-	return false;
+    /* Sanity check arguments */
+    Assert(number);
+
+    /* Get the OPAMP output ready status*/
+    if (number == OPAMP_0)
+    {
+        return OPAMP->STATUS.bit.READY0;
+    } else if (number == OPAMP_1)
+    {
+        return OPAMP->STATUS.bit.READY1;
+    } else if (number == OPAMP_2)
+    {
+        return OPAMP->STATUS.bit.READY2;
+    }
+
+    return false;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h
index 7178ff7525bb..9abb6abb1a91 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/opamp/opamp.h
@@ -130,14 +130,14 @@ extern "C" {
  * \brief OPAMP ID number enum.
  */
 enum opamp_id {
-	/** OPAMP 0  */
-	OPAMP_0 = 0,
-	/** OPAMP 1  */
-	OPAMP_1 = 1,
-	/** OPAMP 2  */
-	OPAMP_2 = 2,
-	/** OPAMP number  */
-	OPAMP_NUM,
+    /** OPAMP 0  */
+    OPAMP_0 = 0,
+    /** OPAMP 1  */
+    OPAMP_1 = 1,
+    /** OPAMP 2  */
+    OPAMP_2 = 2,
+    /** OPAMP number  */
+    OPAMP_NUM,
 };
 
 /**
@@ -146,14 +146,14 @@ enum opamp_id {
  * Enum for the negative input of OPAMP0.
  */
 enum opamp0_neg_mux {
-	/** Negative I/O pin 0 */
-	OPAMP0_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(0),
-	/** Resistor ladder 0 taps */
-	OPAMP0_NEG_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXNEG(1),
-	/** OPAMP output */
-	OPAMP0_NEG_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXNEG(2),
-	/** DAC output */
-	OPAMP0_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
+    /** Negative I/O pin 0 */
+    OPAMP0_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(0),
+    /** Resistor ladder 0 taps */
+    OPAMP0_NEG_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXNEG(1),
+    /** OPAMP output */
+    OPAMP0_NEG_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXNEG(2),
+    /** DAC output */
+    OPAMP0_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
 };
 
 /**
@@ -162,14 +162,14 @@ enum opamp0_neg_mux {
  * Enum for the negative input of OPAMP1.
  */
 enum opamp1_neg_mux {
-	/** Negative I/O pin 1 */
-	OPAMP1_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(0),
-	/** Resistor ladder 1 taps */
-	OPAMP1_NEG_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXNEG(1),
-	/** OPAMP output */
-	OPAMP1_NEG_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXNEG(2),
-	/** DAC output */
-	OPAMP1_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
+    /** Negative I/O pin 1 */
+    OPAMP1_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(0),
+    /** Resistor ladder 1 taps */
+    OPAMP1_NEG_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXNEG(1),
+    /** OPAMP output */
+    OPAMP1_NEG_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXNEG(2),
+    /** DAC output */
+    OPAMP1_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(3),
 };
 
 /**
@@ -178,18 +178,18 @@ enum opamp1_neg_mux {
  * Enum for the negative input of OPAMP2.
  */
 enum opamp2_neg_mux {
-	/** Negative I/O pin 2 */
-	OPAMP2_NEG_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXNEG(0),
-	/** Resistor ladder 2 taps */
-	OPAMP2_NEG_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXNEG(1),
-	/** OPAMP output */
-	OPAMP2_NEG_MUX_OUT2 = OPAMP_OPAMPCTRL_MUXNEG(2),
-	/** Negative I/O pin 0 */
-	OPAMP2_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(3),
-	/** Negative I/O pin 1 */
-	OPAMP2_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(4),
-	/** DAC output */
-	OPAMP2_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(5),
+    /** Negative I/O pin 2 */
+    OPAMP2_NEG_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXNEG(0),
+    /** Resistor ladder 2 taps */
+    OPAMP2_NEG_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXNEG(1),
+    /** OPAMP output */
+    OPAMP2_NEG_MUX_OUT2 = OPAMP_OPAMPCTRL_MUXNEG(2),
+    /** Negative I/O pin 0 */
+    OPAMP2_NEG_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXNEG(3),
+    /** Negative I/O pin 1 */
+    OPAMP2_NEG_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXNEG(4),
+    /** DAC output */
+    OPAMP2_NEG_MUX_DAC = OPAMP_OPAMPCTRL_MUXNEG(5),
 };
 
 /**
@@ -198,14 +198,14 @@ enum opamp2_neg_mux {
  * Enum for the positive input of OPAMP0.
  */
 enum opamp0_pos_mux {
-	/** Positive I/O pin 0 */
-	OPAMP0_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(0),
-	/** Resistor ladder 0 taps */
-	OPAMP0_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(1),
-	/** DAC output */
-	OPAMP0_POS_MUX_DAC = OPAMP_OPAMPCTRL_MUXPOS(2),
-	/** Ground */
-	OPAMP0_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+    /** Positive I/O pin 0 */
+    OPAMP0_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(0),
+    /** Resistor ladder 0 taps */
+    OPAMP0_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(1),
+    /** DAC output */
+    OPAMP0_POS_MUX_DAC = OPAMP_OPAMPCTRL_MUXPOS(2),
+    /** Ground */
+    OPAMP0_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
 };
 
 /**
@@ -214,14 +214,14 @@ enum opamp0_pos_mux {
  * Enum for the positive input of OPAMP1.
  */
 enum opamp1_pos_mux {
-	/** Positive I/O pin 1 */
-	OPAMP1_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(0),
-	/** Resistor ladder 1 taps */
-	OPAMP1_POS_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXPOS(1),
-	/** OPAMP0 output */
-	OPAMP1_POS_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXPOS(2),
-	/** Ground */
-	OPAMP1_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+    /** Positive I/O pin 1 */
+    OPAMP1_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(0),
+    /** Resistor ladder 1 taps */
+    OPAMP1_POS_MUX_TAP1 = OPAMP_OPAMPCTRL_MUXPOS(1),
+    /** OPAMP0 output */
+    OPAMP1_POS_MUX_OUT0 = OPAMP_OPAMPCTRL_MUXPOS(2),
+    /** Ground */
+    OPAMP1_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
 };
 
 /**
@@ -230,20 +230,20 @@ enum opamp1_pos_mux {
  * Enum for the positive input of OPAMP2.
  */
 enum opamp2_pos_mux {
-	/** Positive I/O pin 2 */
-	OPAMP2_POS_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXPOS(0),
-	/** Resistor ladder 2 taps */
-	OPAMP2_POS_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXPOS(1),
-	/** OPAMP1 output */
-	OPAMP2_POS_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXPOS(2),
-	/** Ground */
-	OPAMP2_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
-	/** Positive I/O pin 0 */
-	OPAMP2_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(4),
-	/** Positive I/O pin 1 */
-	OPAMP2_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(5),
-	/** Resistor ladder 0 taps */
-	OPAMP2_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(6),
+    /** Positive I/O pin 2 */
+    OPAMP2_POS_MUX_PIN2 = OPAMP_OPAMPCTRL_MUXPOS(0),
+    /** Resistor ladder 2 taps */
+    OPAMP2_POS_MUX_TAP2 = OPAMP_OPAMPCTRL_MUXPOS(1),
+    /** OPAMP1 output */
+    OPAMP2_POS_MUX_OUT1 = OPAMP_OPAMPCTRL_MUXPOS(2),
+    /** Ground */
+    OPAMP2_POS_MUX_GND = OPAMP_OPAMPCTRL_MUXPOS(3),
+    /** Positive I/O pin 0 */
+    OPAMP2_POS_MUX_PIN0 = OPAMP_OPAMPCTRL_MUXPOS(4),
+    /** Positive I/O pin 1 */
+    OPAMP2_POS_MUX_PIN1 = OPAMP_OPAMPCTRL_MUXPOS(5),
+    /** Resistor ladder 0 taps */
+    OPAMP2_POS_MUX_TAP0 = OPAMP_OPAMPCTRL_MUXPOS(6),
 };
 
 /**
@@ -252,22 +252,22 @@ enum opamp2_pos_mux {
  * Enum for the potentiometer selection of OPAMP 0 to 2.
  */
 enum opamp_pot_mux {
-	/** Gain = R2/R1 = 1/7 */
-	OPAMP_POT_MUX_14R_2R = OPAMP_OPAMPCTRL_POTMUX(0),
-	/** Gain = R2/R1 = 1/3 */
-	OPAMP_POT_MUX_12R_4R = OPAMP_OPAMPCTRL_POTMUX(1),
-	/** Gain = R2/R1 = 1 */
-	OPAMP_POT_MUX_8R_8R = OPAMP_OPAMPCTRL_POTMUX(2),
-	/** Gain = R2/R1 = 1 + 2/3 */
-	OPAMP_POT_MUX_6R_10R = OPAMP_OPAMPCTRL_POTMUX(3),
-	/** Gain = R2/R1 = 3 */
-	OPAMP_POT_MUX_4R_12R = OPAMP_OPAMPCTRL_POTMUX(4),
-	/** Gain = R2/R1 = 4 + 1/3 */
-	OPAMP_POT_MUX_3R_13R = OPAMP_OPAMPCTRL_POTMUX(5),
-	/** Gain = R2/R1 = 7 */
-	OPAMP_POT_MUX_2R_14R = OPAMP_OPAMPCTRL_POTMUX(6),
-	/** Gain = R2/R1 = 15 */
-	OPAMP_POT_MUX_R_15R = OPAMP_OPAMPCTRL_POTMUX(7),
+    /** Gain = R2/R1 = 1/7 */
+    OPAMP_POT_MUX_14R_2R = OPAMP_OPAMPCTRL_POTMUX(0),
+    /** Gain = R2/R1 = 1/3 */
+    OPAMP_POT_MUX_12R_4R = OPAMP_OPAMPCTRL_POTMUX(1),
+    /** Gain = R2/R1 = 1 */
+    OPAMP_POT_MUX_8R_8R = OPAMP_OPAMPCTRL_POTMUX(2),
+    /** Gain = R2/R1 = 1 + 2/3 */
+    OPAMP_POT_MUX_6R_10R = OPAMP_OPAMPCTRL_POTMUX(3),
+    /** Gain = R2/R1 = 3 */
+    OPAMP_POT_MUX_4R_12R = OPAMP_OPAMPCTRL_POTMUX(4),
+    /** Gain = R2/R1 = 4 + 1/3 */
+    OPAMP_POT_MUX_3R_13R = OPAMP_OPAMPCTRL_POTMUX(5),
+    /** Gain = R2/R1 = 7 */
+    OPAMP_POT_MUX_2R_14R = OPAMP_OPAMPCTRL_POTMUX(6),
+    /** Gain = R2/R1 = 15 */
+    OPAMP_POT_MUX_R_15R = OPAMP_OPAMPCTRL_POTMUX(7),
 };
 
 /**
@@ -276,14 +276,14 @@ enum opamp_pot_mux {
  * Enum for the Resistor 1 of OPAMP0.
  */
 enum opamp0_res1_mux {
-	/** Positive input of OPAMP0 */
-	OPAMP0_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
-	/** Negative input of OPAMP0 */
-	OPAMP0_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
-	/** DAC output */
-	OPAMP0_RES1_MUX_DAC = OPAMP_OPAMPCTRL_RES1MUX(2),
-	/** Ground */
-	OPAMP0_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+    /** Positive input of OPAMP0 */
+    OPAMP0_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+    /** Negative input of OPAMP0 */
+    OPAMP0_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+    /** DAC output */
+    OPAMP0_RES1_MUX_DAC = OPAMP_OPAMPCTRL_RES1MUX(2),
+    /** Ground */
+    OPAMP0_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
 };
 
 /**
@@ -292,14 +292,14 @@ enum opamp0_res1_mux {
  * Enum for the Resistor 1 of OPAMP1.
  */
 enum opamp1_res1_mux {
-	/** Positive input of OPAMP1 */
-	OPAMP1_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
-	/** Negative input of OPAMP1 */
-	OPAMP1_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
-	/** OPAMP0 output */
-	OPAMP1_RES1_MUX_OUT0 = OPAMP_OPAMPCTRL_RES1MUX(2),
-	/** Ground */
-	OPAMP1_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+    /** Positive input of OPAMP1 */
+    OPAMP1_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+    /** Negative input of OPAMP1 */
+    OPAMP1_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+    /** OPAMP0 output */
+    OPAMP1_RES1_MUX_OUT0 = OPAMP_OPAMPCTRL_RES1MUX(2),
+    /** Ground */
+    OPAMP1_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
 };
 
 /**
@@ -308,14 +308,14 @@ enum opamp1_res1_mux {
  * Enum for the Resistor 1 of OPAMP2.
  */
 enum opamp2_res1_mux {
-	/** Positive input of OPAMP2 */
-	OPAMP2_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
-	/** Negative input of OPAMP2 */
-	OPAMP2_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
-	/** OPAMP1 output */
-	OPAMP2_RES1_MUX_OUT1 = OPAMP_OPAMPCTRL_RES1MUX(2),
-	/** Ground */
-	OPAMP2_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
+    /** Positive input of OPAMP2 */
+    OPAMP2_RES1_MUX_POS_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(0),
+    /** Negative input of OPAMP2 */
+    OPAMP2_RES1_MUX_NEG_PIN0 = OPAMP_OPAMPCTRL_RES1MUX(1),
+    /** OPAMP1 output */
+    OPAMP2_RES1_MUX_OUT1 = OPAMP_OPAMPCTRL_RES1MUX(2),
+    /** Ground */
+    OPAMP2_RES1_MUX_GND = OPAMP_OPAMPCTRL_RES1MUX(3),
 };
 
 /**
@@ -324,14 +324,14 @@ enum opamp2_res1_mux {
  * Enum for the Bias mode selection of OPAMP 0 to 2.
  */
 enum opamp_bias_selection {
-	/** Minimum current consumption but the slowest mode */
-	OPAMP_BIAS_MODE_0 = OPAMP_OPAMPCTRL_BIAS(0),
-	/** Low current consumption, slow speed */
-	OPAMP_BIAS_MODE_1 = OPAMP_OPAMPCTRL_BIAS(1),
-	/** High current consumption, fast speed */
-	OPAMP_BIAS_MODE_2 = OPAMP_OPAMPCTRL_BIAS(2),
-	/** Maximum current consumption but the fastest mode */
-	OPAMP_BIAS_MODE_3 = OPAMP_OPAMPCTRL_BIAS(3),
+    /** Minimum current consumption but the slowest mode */
+    OPAMP_BIAS_MODE_0 = OPAMP_OPAMPCTRL_BIAS(0),
+    /** Low current consumption, slow speed */
+    OPAMP_BIAS_MODE_1 = OPAMP_OPAMPCTRL_BIAS(1),
+    /** High current consumption, fast speed */
+    OPAMP_BIAS_MODE_2 = OPAMP_OPAMPCTRL_BIAS(2),
+    /** Maximum current consumption but the fastest mode */
+    OPAMP_BIAS_MODE_3 = OPAMP_OPAMPCTRL_BIAS(3),
 };
 
 /**
@@ -340,25 +340,25 @@ enum opamp_bias_selection {
  *  Common configuration structure for OPAMP 0 to 2.
  */
 struct opamp_config_common {
-	/**  Potentiometer selection */
-	enum opamp_pot_mux potentiometer_selection;
-	/** If \c true, R1 connected to RES1MUX */
-	bool r1_enable;
-	/** If \c true, resistor ladder to V<SUB>CC</SUB> */
-	bool r2_vcc;
-	/** If \c true, resistor ladder to output */
-	bool r2_out;
-	/** If \c true, the OPAMPx is enabled when a peripheral is requesting
-	 * the OPAMPx to be used as an input. The OPAMPx is
+    /**  Potentiometer selection */
+    enum opamp_pot_mux potentiometer_selection;
+    /** If \c true, R1 connected to RES1MUX */
+    bool r1_enable;
+    /** If \c true, resistor ladder to V<SUB>CC</SUB> */
+    bool r2_vcc;
+    /** If \c true, resistor ladder to output */
+    bool r2_out;
+    /** If \c true, the OPAMPx is enabled when a peripheral is requesting
+     * the OPAMPx to be used as an input. The OPAMPx is
         * disabled if no peripheral is requesting it as an input. */
-	bool on_demand;
-	/** If \c true, the OPAMPx is not stopped during sleep
-	 *  mode when triggered */
-	bool run_in_standby;
-	/**  Bias mode selection */
-	enum opamp_bias_selection bias_value;
-	/** If \c true, OPAMP output is connected to the ADC or AC input */
-	bool analog_out;
+    bool on_demand;
+    /** If \c true, the OPAMPx is not stopped during sleep
+     *  mode when triggered */
+    bool run_in_standby;
+    /**  Bias mode selection */
+    enum opamp_bias_selection bias_value;
+    /** If \c true, OPAMP output is connected to the ADC or AC input */
+    bool analog_out;
 };
 
 /**
@@ -367,15 +367,15 @@ struct opamp_config_common {
  *  Configuration structure for OPAMP 0.
  */
 struct opamp0_config {
-	/** Negative input MUX selection */
-	enum opamp0_neg_mux negative_input;
-	/** Positive input MUX selection */
-	enum opamp0_pos_mux positive_input;
-	/** Resistor 1 MUX selection */
-	enum opamp0_res1_mux r1_connection;
-	/** If \c true, the comparator will continue to sample during sleep
-	 *  mode when triggered */
-	struct opamp_config_common config_common;
+    /** Negative input MUX selection */
+    enum opamp0_neg_mux negative_input;
+    /** Positive input MUX selection */
+    enum opamp0_pos_mux positive_input;
+    /** Resistor 1 MUX selection */
+    enum opamp0_res1_mux r1_connection;
+    /** If \c true, the comparator will continue to sample during sleep
+     *  mode when triggered */
+    struct opamp_config_common config_common;
 };
 
 /**
@@ -384,15 +384,15 @@ struct opamp0_config {
  *  Configuration structure for OPAMP 1.
  */
 struct opamp1_config {
-	/** Negative input MUX selection */
-	enum opamp1_neg_mux negative_input;
-	/** Positive input MUX selection */
-	enum opamp1_pos_mux positive_input;
-	/** Resistor 1 MUX selection */
-	enum opamp1_res1_mux r1_connection;
-	/** If \c true, the comparator will continue to sample during sleep
-	 *  mode when triggered */
-	struct opamp_config_common config_common;
+    /** Negative input MUX selection */
+    enum opamp1_neg_mux negative_input;
+    /** Positive input MUX selection */
+    enum opamp1_pos_mux positive_input;
+    /** Resistor 1 MUX selection */
+    enum opamp1_res1_mux r1_connection;
+    /** If \c true, the comparator will continue to sample during sleep
+     *  mode when triggered */
+    struct opamp_config_common config_common;
 };
 
 /**
@@ -401,15 +401,15 @@ struct opamp1_config {
  *  Configuration structure for OPAMP 2.
  */
 struct opamp2_config {
-	/** Negative input MUX selection */
-	enum opamp2_neg_mux negative_input;
-	/** Positive input MUX selection */
-	enum opamp2_pos_mux positive_input;
-	/** Resistor 1 MUX selection */
-	enum opamp2_res1_mux r1_connection;
-	/** If \c true, the comparator will continue to sample during sleep
-	 *  mode when triggered */
-	struct opamp_config_common config_common;
+    /** Negative input MUX selection */
+    enum opamp2_neg_mux negative_input;
+    /** Positive input MUX selection */
+    enum opamp2_pos_mux positive_input;
+    /** Resistor 1 MUX selection */
+    enum opamp2_res1_mux r1_connection;
+    /** If \c true, the comparator will continue to sample during sleep
+     *  mode when triggered */
+    struct opamp_config_common config_common;
 };
 
 /**
@@ -428,8 +428,8 @@ void opamp_module_init(void);
  */
 static inline void opamp_module_reset(void)
 {
-	/* Reset OPAMP. */
-	OPAMP->CTRLA.reg |= OPAMP_CTRLA_SWRST;
+    /* Reset OPAMP. */
+    OPAMP->CTRLA.reg |= OPAMP_CTRLA_SWRST;
 }
 
 /**
@@ -441,8 +441,8 @@ static inline void opamp_module_reset(void)
  */
 static inline void opamp_module_enable(void)
 {
-	/* Enable OPAMP. */
-	OPAMP->CTRLA.reg |= OPAMP_CTRLA_ENABLE;
+    /* Enable OPAMP. */
+    OPAMP->CTRLA.reg |= OPAMP_CTRLA_ENABLE;
 }
 
 /**
@@ -452,8 +452,8 @@ static inline void opamp_module_enable(void)
  */
 static inline void opamp_module_disable(void)
 {
-	/* Disable OPAMP. */
-	OPAMP->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE;
+    /* Disable OPAMP. */
+    OPAMP->CTRLA.reg &= ~OPAMP_CTRLA_ENABLE;
 }
 
 /**
@@ -465,14 +465,14 @@ static inline void opamp_module_disable(void)
  */
 static inline void opamp_voltage_doubler_enable(void)
 {
-	struct system_clock_source_osculp32k_config config;
+    struct system_clock_source_osculp32k_config config;
 
-	/* Enable the OSCULP32K clock. */
-	system_clock_source_osculp32k_get_config_defaults(&config);
-	system_clock_source_osculp32k_set_config(&config);
+    /* Enable the OSCULP32K clock. */
+    system_clock_source_osculp32k_get_config_defaults(&config);
+    system_clock_source_osculp32k_set_config(&config);
 
-	/* Enable Voltage Doubler. */
-	OPAMP->CTRLA.reg &= ~ OPAMP_CTRLA_LPMUX;
+    /* Enable Voltage Doubler. */
+    OPAMP->CTRLA.reg &= ~ OPAMP_CTRLA_LPMUX;
 }
 
 /**
@@ -483,8 +483,8 @@ static inline void opamp_voltage_doubler_enable(void)
  */
 static inline void opamp_voltage_doubler_disable(void)
 {
-	/* Disable Voltage Doubler. */
-	OPAMP->CTRLA.reg |= OPAMP_CTRLA_LPMUX;
+    /* Disable Voltage Doubler. */
+    OPAMP->CTRLA.reg |= OPAMP_CTRLA_LPMUX;
 }
 
 /**
@@ -612,14 +612,14 @@ bool opamp_is_ready(const enum opamp_id number);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>OPAMP</td>
- *		<td>Operational Amplifier Controller</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>OPAMP</td>
+ *      <td>Operational Amplifier Controller</td>
+ *  </tr>
  * </table>
  *
  *
@@ -638,12 +638,12 @@ bool opamp_is_ready(const enum opamp_id number);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -661,16 +661,16 @@ bool opamp_is_ready(const enum opamp_id number);
  * \page asfdoc_sam0_opamp_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42446A</td>
- *		<td>07/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42446A</td>
+ *      <td>07/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h
index 701acf6621fc..cca528dd4673 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac.h
@@ -117,36 +117,36 @@
  *
  * \anchor asfdoc_sam0_pac_rec_imp_diagram
  * \dot
- *	digraph correct {
- *		subgraph cluster_a {
- *			style="filled, dotted";
- *			coler=lightgray;
- *			init [label="Initialize Peripheral", shape=box];
- *			lock [label="Lock peripheral", shape=box];
- *			label="Initialization and code";
- *			init -> lock;
- *		}
- *		subgraph cluster_b {
- *			cli [label="Disable global interrupts", shape=box,
- *				style=dotted];
- *			unlock [label="Unlock peripheral", shape=box];
- *			sanity [label="Sanity Check", shape=box, style=dotted];
- *			modify [label="Modify peripheral", shape=box];
- *			lock2 [label="Lock peripheral", shape=box];
- *			sei [label="Enable global interrupts", shape=box
- *				style=dotted];
+ *  digraph correct {
+ *      subgraph cluster_a {
+ *          style="filled, dotted";
+ *          coler=lightgray;
+ *          init [label="Initialize Peripheral", shape=box];
+ *          lock [label="Lock peripheral", shape=box];
+ *          label="Initialization and code";
+ *          init -> lock;
+ *      }
+ *      subgraph cluster_b {
+ *          cli [label="Disable global interrupts", shape=box,
+ *              style=dotted];
+ *          unlock [label="Unlock peripheral", shape=box];
+ *          sanity [label="Sanity Check", shape=box, style=dotted];
+ *          modify [label="Modify peripheral", shape=box];
+ *          lock2 [label="Lock peripheral", shape=box];
+ *          sei [label="Enable global interrupts", shape=box
+ *              style=dotted];
 *
- *			label="Peripheral Modification";
- *			cli -> unlock;
- *			unlock -> sanity
- *			sanity -> modify;
- *			modify -> lock2;
- *			lock2 -> sei;
- *		}
- *		lock -> cli [label=
- *			"Other initialization\n and enable interrupts if applicable"
- *				, style=dotted];
- *	}
+ *          label="Peripheral Modification";
+ *          cli -> unlock;
+ *          unlock -> sanity
+ *          sanity -> modify;
+ *          modify -> lock2;
+ *          lock2 -> sei;
+ *      }
+ *      lock -> cli [label=
+ *          "Other initialization\n and enable interrupts if applicable"
+ *              , style=dotted];
+ *  }
  * \enddot
  *
  * \subsection asfdoc_sam0_pac_enabled_interrupt Why Disable Interrupts
@@ -165,33 +165,33 @@
  *
  * \anchor asfdoc_sam0_pac_int_hazard_diagram
  * \dot
- *	digraph enabled_interrupt {
- *		subgraph cluster_0{
- *			label="Main routine";
- *			{node [style="filled", color=black, fillcolor=white]
- *			init [label="Initialize and lock peripherals", shape=box];
- *			main_unlock [label="Unlock peripheral",	shape=box,
- *				fillcolor=green];
- *			main_modify [label="Modify peripheral", shape=box];}
- *			main_lock [label="Lock peripheral", shape=box];
- *			init -> main_unlock [label="User code"];
- *			main_unlock -> main_modify;
- *			main_modify -> main_lock [style=dotted];
- *		}
- *		subgraph cluster_1 {
- *			label="Interrupt handler";
- *			int_unlock [label="Unlock peripheral", shape=box,
- *				style=filled, fillcolor=red];
- *			int_modify [label="Modify peripheral", shape=box];
- *			int_lock [label="Lock peripheral", shape=box];
- *			int_unlock -> int_modify [style=dotted];
- *			int_modify -> int_lock [style=dotted];
- *		}
- *		exception [label="Exception", shape=box, style=filled, fillcolor=red];
- *		main_modify -> int_unlock [label=" Interrupt"];
- *		int_unlock -> exception;
- *		exception -> exception;
- *	}
+ *  digraph enabled_interrupt {
+ *      subgraph cluster_0{
+ *          label="Main routine";
+ *          {node [style="filled", color=black, fillcolor=white]
+ *          init [label="Initialize and lock peripherals", shape=box];
+ *          main_unlock [label="Unlock peripheral", shape=box,
+ *              fillcolor=green];
+ *          main_modify [label="Modify peripheral", shape=box];}
+ *          main_lock [label="Lock peripheral", shape=box];
+ *          init -> main_unlock [label="User code"];
+ *          main_unlock -> main_modify;
+ *          main_modify -> main_lock [style=dotted];
+ *      }
+ *      subgraph cluster_1 {
+ *          label="Interrupt handler";
+ *          int_unlock [label="Unlock peripheral", shape=box,
+ *              style=filled, fillcolor=red];
+ *          int_modify [label="Modify peripheral", shape=box];
+ *          int_lock [label="Lock peripheral", shape=box];
+ *          int_unlock -> int_modify [style=dotted];
+ *          int_modify -> int_lock [style=dotted];
+ *      }
+ *      exception [label="Exception", shape=box, style=filled, fillcolor=red];
+ *      main_modify -> int_unlock [label=" Interrupt"];
+ *      int_unlock -> exception;
+ *      exception -> exception;
+ *  }
  * \enddot
  *
  * \subsection asfdoc_sam0_pac_code_run_away Run-away Code
@@ -207,254 +207,254 @@
  *
  * \anchor asfdoc_sam0_pac_code_runaway_diagram
  * \dot
- *	digraph run_away {
- *	   subgraph cluster_away1{
- *		rankdir=TB;
- *		color=white;
- *		runaway1 [label="Run-away code", shape=box];
- *		node [shape=plaintext];
- *		program1 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td>0x0020</td>
- *					<td>initialize peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0025</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>...</td>
- *					<td>...</td>
- *				</tr>
- *				<tr>
- *					<td>0x0080</td>
- *					<td>set sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="green">...</td>
- *					<td BGCOLOR="green">...</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0115</td>
- *					<td BGCOLOR="green">disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0120</td>
- *					<td BGCOLOR="green">unlock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="red">0x0125</td>
- *					<td BGCOLOR="red">check sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td>0x0130</td>
- *					<td>modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0140</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0145</td>
- *					<td>disable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway1 -> program1:f0;
- *			label="1. Run-away code is caught in sanity check.\nA CPU exception is executed."
- *		}
- *	   subgraph cluster_away2{
- *		rankdir=TB;
- *		runaway2 [label="Run-away code", shape=box];
- *		color=white;
- *		node [shape=plaintext];
- *		program2 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td>0x0020</td>
- *					<td>initialize peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0025</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>...</td>
- *					<td>...</td>
- *				</tr>
- *				<tr>
- *					<td>0x0080</td>
- *					<td>set sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td >...</td>
- *					<td >...</td>
- *				</tr>
- *				<tr>
- *					<td >0x0115</td>
- *					<td >disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td >0x0120</td>
- *					<td >unlock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td >0x0125</td>
- *					<td >check sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="red">0x0130</td>
- *					<td BGCOLOR="red">modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0140</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0145</td>
- *					<td>disable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway2 -> program2:f0;
- *			label="2. Run-away code is caught when modifying\nlocked peripheral. A CPU exception is executed."
- *		}
- *	}
+ *  digraph run_away {
+ *     subgraph cluster_away1{
+ *      rankdir=TB;
+ *      color=white;
+ *      runaway1 [label="Run-away code", shape=box];
+ *      node [shape=plaintext];
+ *      program1 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0020</td>
+ *                  <td>initialize peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0025</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>...</td>
+ *                  <td>...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0080</td>
+ *                  <td>set sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="green">...</td>
+ *                  <td BGCOLOR="green">...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0115</td>
+ *                  <td BGCOLOR="green">disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0120</td>
+ *                  <td BGCOLOR="green">unlock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="red">0x0125</td>
+ *                  <td BGCOLOR="red">check sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0130</td>
+ *                  <td>modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0140</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0145</td>
+ *                  <td>disable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway1 -> program1:f0;
+ *          label="1. Run-away code is caught in sanity check.\nA CPU exception is executed."
+ *      }
+ *     subgraph cluster_away2{
+ *      rankdir=TB;
+ *      runaway2 [label="Run-away code", shape=box];
+ *      color=white;
+ *      node [shape=plaintext];
+ *      program2 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0020</td>
+ *                  <td>initialize peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0025</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>...</td>
+ *                  <td>...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0080</td>
+ *                  <td>set sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >...</td>
+ *                  <td >...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0115</td>
+ *                  <td >disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0120</td>
+ *                  <td >unlock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0125</td>
+ *                  <td >check sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="red">0x0130</td>
+ *                  <td BGCOLOR="red">modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0140</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0145</td>
+ *                  <td>disable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway2 -> program2:f0;
+ *          label="2. Run-away code is caught when modifying\nlocked peripheral. A CPU exception is executed."
+ *      }
+ *  }
  * \enddot
  *
  * \anchor asfdoc_sam0_pac_code_runaway_diagram2
  * \dot
- *	digraph run_away2 {
- *	   subgraph cluster_away3{
- *		rankdir=TB;
- *		runaway3 [label="Run-away code", shape=box];
- *		color=white;
- *		node [shape=plaintext];
- *		program3 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td>0x0020</td>
- *					<td>initialize peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0025</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>...</td>
- *					<td>...</td>
- *				</tr>
- *				<tr>
- *					<td>0x0080</td>
- *					<td>set sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td >...</td>
- *					<td >...</td>
- *				</tr>
- *				<tr>
- *					<td >0x0115</td>
- *					<td >disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td >0x0120</td>
- *					<td >unlock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td >0x0125</td>
- *					<td >check sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td >0x0130</td>
- *					<td >modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="red">0x0140</td>
- *					<td BGCOLOR="red">lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0145</td>
- *					<td>disable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway3 -> program3:f0;
- *			label="3. Run-away code is caught when locking\nlocked peripheral. A CPU exception is executed."
- *		}
- *	subgraph cluster_away4 {
- *		rankdir=TB;
- *		runaway4 [label="Run-away code", shape=box];
- *		color=white;
- *		node [shape=plaintext];
- *		program4 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td>0x0020</td>
- *					<td>initialize peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0025</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="green">...</td>
- *					<td BGCOLOR="green">...</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0080</td>
- *					<td BGCOLOR="green">set sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">...</td>
- *					<td BGCOLOR="green">...</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0115</td>
- *					<td BGCOLOR="green">disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0120</td>
- *					<td BGCOLOR="green">unlock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0125</td>
- *					<td BGCOLOR="green">check sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0130</td>
- *					<td BGCOLOR="green">modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0140</td>
- *					<td BGCOLOR="green">lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0145</td>
- *					<td BGCOLOR="green">disable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway4 -> program4:f0;
- *			label="4. Run-away code is not caught.\n "
- *		}
- *	}
+ *  digraph run_away2 {
+ *     subgraph cluster_away3{
+ *      rankdir=TB;
+ *      runaway3 [label="Run-away code", shape=box];
+ *      color=white;
+ *      node [shape=plaintext];
+ *      program3 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0020</td>
+ *                  <td>initialize peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0025</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>...</td>
+ *                  <td>...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0080</td>
+ *                  <td>set sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >...</td>
+ *                  <td >...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0115</td>
+ *                  <td >disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0120</td>
+ *                  <td >unlock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0125</td>
+ *                  <td >check sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td >0x0130</td>
+ *                  <td >modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="red">0x0140</td>
+ *                  <td BGCOLOR="red">lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0145</td>
+ *                  <td>disable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway3 -> program3:f0;
+ *          label="3. Run-away code is caught when locking\nlocked peripheral. A CPU exception is executed."
+ *      }
+ *  subgraph cluster_away4 {
+ *      rankdir=TB;
+ *      runaway4 [label="Run-away code", shape=box];
+ *      color=white;
+ *      node [shape=plaintext];
+ *      program4 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0020</td>
+ *                  <td>initialize peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0025</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="green">...</td>
+ *                  <td BGCOLOR="green">...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0080</td>
+ *                  <td BGCOLOR="green">set sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">...</td>
+ *                  <td BGCOLOR="green">...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0115</td>
+ *                  <td BGCOLOR="green">disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0120</td>
+ *                  <td BGCOLOR="green">unlock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0125</td>
+ *                  <td BGCOLOR="green">check sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0130</td>
+ *                  <td BGCOLOR="green">modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0140</td>
+ *                  <td BGCOLOR="green">lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0145</td>
+ *                  <td BGCOLOR="green">disable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway4 -> program4:f0;
+ *          label="4. Run-away code is not caught.\n "
+ *      }
+ *  }
  * \enddot
  *
  * In the example, green indicates that the command is allowed, red indicates
@@ -472,8 +472,8 @@
  * the bitwise inverse of the module flag, i.e.
  *
  * \code
-	system_peripheral_<lock_state>(SYSTEM_PERIPHERAL_<module>,
-			~SYSTEM_PERIPHERAL_<module>);
+    system_peripheral_<lock_state>(SYSTEM_PERIPHERAL_<module>,
+            ~SYSTEM_PERIPHERAL_<module>);
 \endcode
  *
  * Where the lock state can be either lock or unlock, and module refer to the
@@ -498,25 +498,25 @@
  * \anchor asfdoc_sam0_pac_int_connections
  * \dot
  * digraph overview {
- *	nodesep = .05;
- *	rankdir=LR;
- *
- *	ahb [label="Peripheral bus", shape=ellipse, style=filled, fillcolor=lightgray];
- *	pac [label="<f0>PAC|<f1>Lock|<f2>Open|<f3>Open",
- *		 height=2.5, shape=record, width=.1];
- *	per1 [label="Peripheral1", shape=ellipse, style=filled, fillcolor=lightgray];
- *	per2 [label="Peripheral2", shape=ellipse, style=filled, fillcolor=lightgray];
- *	per3 [label="Peripheral3", shape=ellipse, style=filled, fillcolor=lightgray];
- *	edge [dir="both"];
- *	ahb -> pac:f1 [label="Read/Write"];
- *	ahb -> pac:f2 [label="Read/Write"];
- *	ahb -> pac:f3 [label="Read/Write"];
- *	edge [dir="back"];
- *	pac:f1 -> per1 [label="Read"];
- *	edge [dir="both"];
- *	pac:f2 -> per2 [label="Read/Write"];
- *	pac:f3 -> per3 [label="Read/Write"];
- *	{rank=same; per1 per2 per3 }
+ *  nodesep = .05;
+ *  rankdir=LR;
+ *
+ *  ahb [label="Peripheral bus", shape=ellipse, style=filled, fillcolor=lightgray];
+ *  pac [label="<f0>PAC|<f1>Lock|<f2>Open|<f3>Open",
+ *       height=2.5, shape=record, width=.1];
+ *  per1 [label="Peripheral1", shape=ellipse, style=filled, fillcolor=lightgray];
+ *  per2 [label="Peripheral2", shape=ellipse, style=filled, fillcolor=lightgray];
+ *  per3 [label="Peripheral3", shape=ellipse, style=filled, fillcolor=lightgray];
+ *  edge [dir="both"];
+ *  ahb -> pac:f1 [label="Read/Write"];
+ *  ahb -> pac:f2 [label="Read/Write"];
+ *  ahb -> pac:f3 [label="Read/Write"];
+ *  edge [dir="back"];
+ *  pac:f1 -> per1 [label="Read"];
+ *  edge [dir="both"];
+ *  pac:f2 -> per2 [label="Read/Write"];
+ *  pac:f3 -> per3 [label="Read/Write"];
+ *  {rank=same; per1 per2 per3 }
  * }
  * \enddot
  *
@@ -538,101 +538,101 @@
  *
  * \anchor asfdoc_sam0_pac_lock_errors_diagram
  * \dot
- *	digraph read_lock {
- *	   subgraph cluster_read1{
- *		rankdir=TB;
- *		color=white;
- *		runaway1 [label="Run-away code\nwith peripheral unlocked", shape=box];
- *		node [shape=plaintext];
- *		program1 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="green">...</td>
- *					<td BGCOLOR="green">...</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0100</td>
- *					<td BGCOLOR="green">check if locked</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0102</td>
- *					<td BGCOLOR="green">disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0105</td>
- *					<td BGCOLOR="green">unlock if locked</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0110</td>
- *					<td BGCOLOR="green">check sanity</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0115</td>
- *					<td BGCOLOR="green">modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0120</td>
- *					<td BGCOLOR="green">lock if previously locked</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0125</td>
- *					<td BGCOLOR="green">enable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway1 -> program1:f0;
- *			label="1. Wrong implementation.\n "
- *		}
- *	   subgraph cluster_read2{
- *		rankdir=TB;
- *		color=white;
- *		runaway2 [label="Run-away code\nwith peripheral unlocked", shape=box];
- *		node [shape=plaintext];
- *		program2 [label=<
- *			<table>
- *				<tr>
- *					<td>PC#</td>
- *					<td>Code</td>
- *				</tr>
- *				<tr>
- *					<td port="f0" BGCOLOR="green">...</td>
- *					<td BGCOLOR="green">...</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="green">0x0100</td>
- *					<td BGCOLOR="green">disable interrupts</td>
- *				</tr>
- *				<tr>
- *					<td BGCOLOR="red">0x0120</td>
- *					<td BGCOLOR="red">unlock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0125</td>
- *					<td>check sanity argument</td>
- *				</tr>
- *				<tr>
- *					<td>0x0130</td>
- *					<td>modify peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0140</td>
- *					<td>lock peripheral</td>
- *				</tr>
- *				<tr>
- *					<td>0x0145</td>
- *					<td>disable interrupts</td>
- *				</tr>
- *			</table>
- *			>]
- *			runaway2 -> program2:f0;
- *
- *			label="2. Correct implementation.\n "
- *		}
- *	}
+ *  digraph read_lock {
+ *     subgraph cluster_read1{
+ *      rankdir=TB;
+ *      color=white;
+ *      runaway1 [label="Run-away code\nwith peripheral unlocked", shape=box];
+ *      node [shape=plaintext];
+ *      program1 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="green">...</td>
+ *                  <td BGCOLOR="green">...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0100</td>
+ *                  <td BGCOLOR="green">check if locked</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0102</td>
+ *                  <td BGCOLOR="green">disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0105</td>
+ *                  <td BGCOLOR="green">unlock if locked</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0110</td>
+ *                  <td BGCOLOR="green">check sanity</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0115</td>
+ *                  <td BGCOLOR="green">modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0120</td>
+ *                  <td BGCOLOR="green">lock if previously locked</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0125</td>
+ *                  <td BGCOLOR="green">enable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway1 -> program1:f0;
+ *          label="1. Wrong implementation.\n "
+ *      }
+ *     subgraph cluster_read2{
+ *      rankdir=TB;
+ *      color=white;
+ *      runaway2 [label="Run-away code\nwith peripheral unlocked", shape=box];
+ *      node [shape=plaintext];
+ *      program2 [label=<
+ *          <table>
+ *              <tr>
+ *                  <td>PC#</td>
+ *                  <td>Code</td>
+ *              </tr>
+ *              <tr>
+ *                  <td port="f0" BGCOLOR="green">...</td>
+ *                  <td BGCOLOR="green">...</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="green">0x0100</td>
+ *                  <td BGCOLOR="green">disable interrupts</td>
+ *              </tr>
+ *              <tr>
+ *                  <td BGCOLOR="red">0x0120</td>
+ *                  <td BGCOLOR="red">unlock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0125</td>
+ *                  <td>check sanity argument</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0130</td>
+ *                  <td>modify peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0140</td>
+ *                  <td>lock peripheral</td>
+ *              </tr>
+ *              <tr>
+ *                  <td>0x0145</td>
+ *                  <td>disable interrupts</td>
+ *              </tr>
+ *          </table>
+ *          >]
+ *          runaway2 -> program2:f0;
+ *
+ *          label="2. Correct implementation.\n "
+ *      }
+ *  }
  * \enddot
  *
  * In the left figure above, one can see the runaway code continues as all
@@ -679,12 +679,12 @@ extern "C" {
  * @{
  */
 __no_inline enum status_code system_peripheral_lock(
-		const uint32_t peripheral_id,
-		const uint32_t key);
+        const uint32_t peripheral_id,
+        const uint32_t key);
 
 __no_inline enum status_code system_peripheral_unlock(
-		const uint32_t peripheral_id,
-		const uint32_t key);
+        const uint32_t peripheral_id,
+        const uint32_t key);
 /** @}  */
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__)
@@ -692,8 +692,8 @@ __no_inline enum status_code system_peripheral_unlock(
  * @{
  */
 __no_inline enum status_code system_peripheral_lock_always(
-		const uint32_t peripheral_id,
-		const uint32_t key);
+        const uint32_t peripheral_id,
+        const uint32_t key);
 
 /**
  * \brief Enable PAC interrupt.
@@ -704,7 +704,7 @@ __no_inline enum status_code system_peripheral_lock_always(
  */
 static inline void system_pac_enable_interrupt(void)
 {
-	PAC->INTENSET.reg = PAC_INTENSET_ERR;
+    PAC->INTENSET.reg = PAC_INTENSET_ERR;
 }
 
 /**
@@ -715,7 +715,7 @@ static inline void system_pac_enable_interrupt(void)
  */
 static inline void system_pac_disable_interrupt(void)
 {
-	PAC->INTENCLR.reg = PAC_INTENCLR_ERR;
+    PAC->INTENCLR.reg = PAC_INTENCLR_ERR;
 }
 
 /**
@@ -726,7 +726,7 @@ static inline void system_pac_disable_interrupt(void)
  */
 static inline void system_pac_enable_event(void)
 {
-	PAC->EVCTRL.reg = PAC_EVCTRL_ERREO;
+    PAC->EVCTRL.reg = PAC_EVCTRL_ERREO;
 }
 
 /**
@@ -737,7 +737,7 @@ static inline void system_pac_enable_event(void)
  */
 static inline void system_pac_disable_event(void)
 {
-	PAC->EVCTRL.reg &= (~PAC_EVCTRL_ERREO);
+    PAC->EVCTRL.reg &= (~PAC_EVCTRL_ERREO);
 }
 
 /** @}  */
@@ -757,58 +757,58 @@ static inline void system_pac_disable_event(void)
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</td>
- *		<th>Description</td>
- *	</tr>
- *  <tr>
- *		<td>AC</td>
- *		<td>Analog Comparator</td>
- *	</tr>
- *	<tr>
- *		<td>ADC</td>
- *		<td>Analog-to-Digital Converter</td>
- *	</tr>
- *	<tr>
- *		<td>EVSYS</td>
- *		<td>Event System</td>
- *	</tr>
- *	<tr>
- *		<td>NMI</td>
- *		<td>Non-Maskable Interrupt</td>
- *	</tr>
- *	<tr>
- *		<td>NVMCTRL</td>
- *		<td>Non-Volatile Memory Controller</td>
- *	</tr>
- *	<tr>
- *		<td>PAC</td>
- *		<td>Peripheral Access Controller</td>
- *	</tr>
-  *	<tr>
- *		<td>PM</td>
- *		<td>Power Manager</td>
- *	</tr>
- *	<tr>
- *		<td>RTC</td>
- *		<td>Real-Time Counter</td>
- *	</tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>Serial Communication Interface</td>
- *	</tr>
- *	<tr>
- *		<td>SYSCTRL</td>
- *		<td>System Controller</td>
- *	</tr>
- *	<tr>
- *		<td>TC</td>
- *		<td>Timer/Counter</td>
- *	</tr>
- *	<tr>
- *		<td>WDT</td>
- *		<td>Watch Dog Timer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</td>
+ *      <th>Description</td>
+ *  </tr>
+ *  <tr>
+ *      <td>AC</td>
+ *      <td>Analog Comparator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>Analog-to-Digital Converter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>EVSYS</td>
+ *      <td>Event System</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NMI</td>
+ *      <td>Non-Maskable Interrupt</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NVMCTRL</td>
+ *      <td>Non-Volatile Memory Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PAC</td>
+ *      <td>Peripheral Access Controller</td>
+ *  </tr>
+  * <tr>
+ *      <td>PM</td>
+ *      <td>Power Manager</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RTC</td>
+ *      <td>Real-Time Counter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SERCOM</td>
+ *      <td>Serial Communication Interface</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>System Controller</td>
+ *  </tr>
+ *  <tr>
+ *      <td>TC</td>
+ *      <td>Timer/Counter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>WDT</td>
+ *      <td>Watch Dog Timer</td>
+ *  </tr>
  * </table>
  *
  *
@@ -829,12 +829,12 @@ static inline void system_pac_disable_event(void)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -856,160 +856,160 @@ static inline void system_pac_disable_event(void)
  * Look in device datasheet peripheral's subsection "Register Access
  * Protection" to see which is actually available for your device.
  * <table>
- *	<tr>
- *		<th>Module</th>
- *		<th>Non-write protected register</th>
- *	</tr>
- *	<tr>
- *		<td>AC</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUSA</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUSB</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUSC</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>ADC</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>RESULT</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>EVSYS</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>CHSTATUS</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>NVMCTRL</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>PM</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>PORT</td>
- *		<td>N/A</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>RTC</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>READREQ</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>SYSCTRL</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>INTFALG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>DATA</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>TC</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr><td colspan="2"/></tr>
- *	<tr>
- *		<td>WDT</td>
- *		<td>INTFLAG</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>STATUS</td>
- *	</tr>
- *	<tr>
- *		<td></td>
- *		<td>(CLEAR)</td>
- *	</tr>
+ *  <tr>
+ *      <th>Module</th>
+ *      <th>Non-write protected register</th>
+ *  </tr>
+ *  <tr>
+ *      <td>AC</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUSA</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUSB</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUSC</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>ADC</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>RESULT</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>EVSYS</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>CHSTATUS</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>NVMCTRL</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>PM</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>PORT</td>
+ *      <td>N/A</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>RTC</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>READREQ</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>SYSCTRL</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>SERCOM</td>
+ *      <td>INTFALG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>DATA</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>TC</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr><td colspan="2"/></tr>
+ *  <tr>
+ *      <td>WDT</td>
+ *      <td>INTFLAG</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>STATUS</td>
+ *  </tr>
+ *  <tr>
+ *      <td></td>
+ *      <td>(CLEAR)</td>
+ *  </tr>
  * </table>
  *
  * \page asfdoc_sam0_pac_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42107F</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM C20/C21, SAM D09, and SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42107E</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42107D</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42107C</td>
- *		<td>10/2013</td>
- *		<td>Extended acronyms list</td>
- *	</tr>
- *	<tr>
- *		<td>42107B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42107A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107F</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C20/C21, SAM D09, and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107E</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107D</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107C</td>
+ *      <td>10/2013</td>
+ *      <td>Extended acronyms list</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42107A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c
index 71c2e2bc0d3e..56eb3f3e8f54 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_d_r_h/pac.c
@@ -63,49 +63,51 @@
  *
  * \return Status of the peripheral lock procedure.
  * \retval STATUS_OK                If the peripheral was successfully locked.
- * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied.
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied.
  */
 __no_inline enum status_code system_peripheral_lock(
-		const uint32_t peripheral_id,
-		const uint32_t key)
+        const uint32_t peripheral_id,
+        const uint32_t key)
 {
-	/* Bit to be set in desired register is given by bit 5:0 */
-	uint8_t register_bit_pos = peripheral_id % 32;
-	UNUSED(register_bit_pos);
+    /* Bit to be set in desired register is given by bit 5:0 */
+    uint8_t register_bit_pos = peripheral_id % 32;
+    UNUSED(register_bit_pos);
 
-	/* Value of which PAC register to use is given by bit 31:6 */
-	uint8_t register_pos = peripheral_id / 32;
+    /* Value of which PAC register to use is given by bit 31:6 */
+    uint8_t register_pos = peripheral_id / 32;
 
-	/* Check if key is correct. */
-	if (~peripheral_id != key) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if key is correct. */
+    if (~peripheral_id != key)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	switch (register_pos) {
+    switch (register_pos)
+    {
 #ifdef PAC0
-		case 0:
-			PAC0->WPSET.reg = (1 << register_bit_pos);
-			break;
+        case 0:
+            PAC0->WPSET.reg = (1 << register_bit_pos);
+            break;
 #endif
 #ifdef PAC1
-		case 1:
-			PAC1->WPSET.reg = (1 << register_bit_pos);
-			break;
+        case 1:
+            PAC1->WPSET.reg = (1 << register_bit_pos);
+            break;
 #endif
 #ifdef PAC2
-		case 2:
-			/* Turn on the digital interface clock */
-			system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
-			PAC2->WPSET.reg = (1 << register_bit_pos);
-			break;
+        case 2:
+            /* Turn on the digital interface clock */
+            system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
+            PAC2->WPSET.reg = (1 << register_bit_pos);
+            break;
 #endif
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -125,47 +127,49 @@ __no_inline enum status_code system_peripheral_lock(
  *
  * \return Status of the peripheral unlock procedure.
  * \retval STATUS_OK                If the peripheral was successfully locked.
- * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied.
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied.
  */
 __no_inline enum status_code system_peripheral_unlock(
-		const uint32_t peripheral_id,
-		const uint32_t key)
+        const uint32_t peripheral_id,
+        const uint32_t key)
 {
-	/* Bit to be set in desired register is given by bit 5:0 */
-	uint8_t register_bit_pos = peripheral_id % 32;
-	UNUSED(register_bit_pos);
+    /* Bit to be set in desired register is given by bit 5:0 */
+    uint8_t register_bit_pos = peripheral_id % 32;
+    UNUSED(register_bit_pos);
 
-	/* Value of which PAC register to use is given by bit 31:6 */
-	uint8_t register_pos = peripheral_id / 32;
+    /* Value of which PAC register to use is given by bit 31:6 */
+    uint8_t register_pos = peripheral_id / 32;
 
-	/* Check if key is correct. */
-	if (~peripheral_id != key) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if key is correct. */
+    if (~peripheral_id != key)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	switch (register_pos) {
+    switch (register_pos)
+    {
 #ifdef PAC0
-		case 0:
-			PAC0->WPCLR.reg = (1 << register_bit_pos);
-			break;
+        case 0:
+            PAC0->WPCLR.reg = (1 << register_bit_pos);
+            break;
 #endif
 #ifdef PAC1
-		case 1:
-			PAC1->WPCLR.reg = (1 << register_bit_pos);
-			break;
+        case 1:
+            PAC1->WPCLR.reg = (1 << register_bit_pos);
+            break;
 #endif
 #ifdef PAC2
-		case 2:
-			/* Turn on the digital interface clock */
-			system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
-			PAC2->WPCLR.reg = (1 << register_bit_pos);
-			break;
+        case 2:
+            /* Turn on the digital interface clock */
+            system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_PAC2);
+            PAC2->WPCLR.reg = (1 << register_bit_pos);
+            break;
 #endif
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c
index 4e61cd53d50a..e564093164d9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pac/pac_sam_l_c/pac.c
@@ -63,21 +63,22 @@
  *
  * \return Status of the peripheral lock procedure.
  * \retval STATUS_OK                If the peripheral was successfully locked
- * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied
  */
 __no_inline enum status_code system_peripheral_lock(
-		const uint32_t peripheral_id,
-		const uint32_t key)
+        const uint32_t peripheral_id,
+        const uint32_t key)
 {
-	/* Check if key is correct. */
-	if (~peripheral_id != key) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if key is correct. */
+    if (~peripheral_id != key)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SET_Val);
+    PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SET_Val);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -98,21 +99,22 @@ __no_inline enum status_code system_peripheral_lock(
  *
  * \return Status of the peripheral lock procedure.
  * \retval STATUS_OK                If the peripheral was successfully locked
- * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied
  */
 __no_inline enum status_code system_peripheral_lock_always(
-		const uint32_t peripheral_id,
-		const uint32_t key)
+        const uint32_t peripheral_id,
+        const uint32_t key)
 {
-	/* Check if key is correct. */
-	if (~peripheral_id != key) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if key is correct. */
+    if (~peripheral_id != key)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SETLCK_Val);
+    PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_SETLCK_Val);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -132,19 +134,20 @@ __no_inline enum status_code system_peripheral_lock_always(
  *
  * \return Status of the peripheral unlock procedure.
  * \retval STATUS_OK                If the peripheral was successfully locked
- * \retval STATUS_ERR_INVALID_ARG	If invalid argument(s) were supplied
+ * \retval STATUS_ERR_INVALID_ARG   If invalid argument(s) were supplied
  */
 __no_inline enum status_code system_peripheral_unlock(
-		const uint32_t peripheral_id,
-		const uint32_t key)
+        const uint32_t peripheral_id,
+        const uint32_t key)
 {
-	/* Check if key is correct. */
-	if (~peripheral_id != key) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if key is correct. */
+    if (~peripheral_id != key)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_CLR_Val);
+    PAC->WRCTRL.reg = peripheral_id | PAC_WRCTRL_KEY(PAC_WRCTRL_KEY_CLR_Val);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c
index 64787c6e54ac..fb3635a0c253 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.c
@@ -58,21 +58,21 @@
  *  \param[in] config    Configuration settings for the pin
  */
 void port_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct port_config *const config)
+        const uint8_t gpio_pin,
+        const struct port_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
 
-	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
-	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
-	pinmux_config.powersave    = config->powersave;
+    pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+    pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+    pinmux_config.powersave    = config->powersave;
 
-	system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
+    system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
 }
 
 /**
@@ -89,21 +89,21 @@ void port_pin_set_config(
  *  \param[in]  config  Configuration settings for the pin group
  */
 void port_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct port_config *const config)
+        PortGroup *const port,
+        const uint32_t mask,
+        const struct port_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(port);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(port);
+    Assert(config);
 
-	struct system_pinmux_config pinmux_config;
-	system_pinmux_get_config_defaults(&pinmux_config);
+    struct system_pinmux_config pinmux_config;
+    system_pinmux_get_config_defaults(&pinmux_config);
 
-	pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
-	pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
-	pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
-	pinmux_config.powersave    = config->powersave;
+    pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
+    pinmux_config.direction    = (enum system_pinmux_pin_dir)config->direction;
+    pinmux_config.input_pull   = (enum system_pinmux_pin_pull)config->input_pull;
+    pinmux_config.powersave    = config->powersave;
 
-	system_pinmux_group_set_config(port, mask, &pinmux_config);
+    system_pinmux_group_set_config(port, mask, &pinmux_config);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h
index cdb342ec9510..58a71412ce2f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/port/port.h
@@ -215,15 +215,15 @@ extern "C" {
  *  structure, to indicate the direction the pin should use.
  */
 enum port_pin_dir {
-	/** The pin's input buffer should be enabled, so that the pin state can
-	 *  be read */
-	PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
-	/** The pin's output buffer should be enabled, so that the pin state can
-	 *  be set */
-	PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
-	/** The pin's output and input buffers should be enabled, so that the pin
-	 *  state can be set and read back */
-	PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+    /** The pin's input buffer should be enabled, so that the pin state can
+     *  be read */
+    PORT_PIN_DIR_INPUT               = SYSTEM_PINMUX_PIN_DIR_INPUT,
+    /** The pin's output buffer should be enabled, so that the pin state can
+     *  be set */
+    PORT_PIN_DIR_OUTPUT              = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+    /** The pin's output and input buffers should be enabled, so that the pin
+     *  state can be set and read back */
+    PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
 };
 
 /**
@@ -233,12 +233,12 @@ enum port_pin_dir {
  *  structure, to indicate the type of logic level pull the pin should use.
  */
 enum port_pin_pull {
-	/** No logical pull should be applied to the pin */
-	PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
-	/** Pin should be pulled up when idle */
-	PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
-	/** Pin should be pulled down when idle */
-	PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
+    /** No logical pull should be applied to the pin */
+    PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
+    /** Pin should be pulled up when idle */
+    PORT_PIN_PULL_UP   = SYSTEM_PINMUX_PIN_PULL_UP,
+    /** Pin should be pulled down when idle */
+    PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
 };
 
 #ifdef FEATURE_PORT_INPUT_EVENT
@@ -248,14 +248,14 @@ enum port_pin_pull {
  *  List of port input events action on pin.
  */
 enum port_input_event_action {
-	/** Event out to pin */
-	PORT_INPUT_EVENT_ACTION_OUT = 0,
-	/** Set output register of pin on event */
-	PORT_INPUT_EVENT_ACTION_SET,
-	/** Clear output register pin on event */
-	PORT_INPUT_EVENT_ACTION_CLR,
-	/** Toggle output register pin on event */
-	PORT_INPUT_EVENT_ACTION_TGL,
+    /** Event out to pin */
+    PORT_INPUT_EVENT_ACTION_OUT = 0,
+    /** Set output register of pin on event */
+    PORT_INPUT_EVENT_ACTION_SET,
+    /** Clear output register pin on event */
+    PORT_INPUT_EVENT_ACTION_CLR,
+    /** Toggle output register pin on event */
+    PORT_INPUT_EVENT_ACTION_TGL,
 };
 
 /**
@@ -264,14 +264,14 @@ enum port_input_event_action {
  *  List of port input events.
  */
 enum port_input_event{
-	/** Port input event 0 */
-	PORT_INPUT_EVENT_0 = 0,
-	/** Port input event 1 */
-	PORT_INPUT_EVENT_1 = 1,
-	/** Port input event 2 */
-	PORT_INPUT_EVENT_2 = 2,
-	/** Port input event 3 */
-	PORT_INPUT_EVENT_3 = 3,
+    /** Port input event 0 */
+    PORT_INPUT_EVENT_0 = 0,
+    /** Port input event 1 */
+    PORT_INPUT_EVENT_1 = 1,
+    /** Port input event 2 */
+    PORT_INPUT_EVENT_2 = 2,
+    /** Port input event 3 */
+    PORT_INPUT_EVENT_3 = 3,
 };
 
 /**
@@ -280,10 +280,10 @@ enum port_input_event{
  *  Configuration structure for a port input event.
  */
 struct port_input_event_config{
-	/** Port input event action */
-	enum port_input_event_action  action;
-	/** GPIO pin */
-	uint8_t gpio_pin;
+    /** Port input event action */
+    enum port_input_event_action  action;
+    /** GPIO pin */
+    uint8_t gpio_pin;
 };
 #endif
 
@@ -295,17 +295,17 @@ struct port_input_event_config{
  *  modified by the user application.
  */
 struct port_config {
-	/** Port buffer input/output direction */
-	enum port_pin_dir  direction;
+    /** Port buffer input/output direction */
+    enum port_pin_dir  direction;
 
-	/** Port pull-up/pull-down for input pins */
-	enum port_pin_pull input_pull;
+    /** Port pull-up/pull-down for input pins */
+    enum port_pin_pull input_pull;
 
-	/** Enable lowest possible powerstate on the pin
-	 *
-	 *  \note All other configurations will be ignored, the pin will be disabled.
-	 */
-	bool powersave;
+    /** Enable lowest possible powerstate on the pin
+     *
+     *  \note All other configurations will be ignored, the pin will be disabled.
+     */
+    bool powersave;
 };
 
 /** \name State Reading/Writing (Physical Group Orientated)
@@ -323,9 +323,9 @@ struct port_config {
  *  \return Base address of the associated PORT module.
  */
 static inline PortGroup* port_get_group_from_gpio_pin(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	return system_pinmux_get_group_from_gpio_pin(gpio_pin);
+    return system_pinmux_get_group_from_gpio_pin(gpio_pin);
 }
 
 /**
@@ -340,13 +340,13 @@ static inline PortGroup* port_get_group_from_gpio_pin(
  *  \return Status of the port pin(s) input buffers.
  */
 static inline uint32_t port_group_get_input_level(
-		const PortGroup *const port,
-		const uint32_t mask)
+        const PortGroup *const port,
+        const uint32_t mask)
 {
-	/* Sanity check arguments */
-	Assert(port);
+    /* Sanity check arguments */
+    Assert(port);
 
-	return (port->IN.reg & mask);
+    return (port->IN.reg & mask);
 }
 
 /**
@@ -361,13 +361,13 @@ static inline uint32_t port_group_get_input_level(
  *  \return Status of the port pin(s) output buffers.
  */
 static inline uint32_t port_group_get_output_level(
-		const PortGroup *const port,
-		const uint32_t mask)
+        const PortGroup *const port,
+        const uint32_t mask)
 {
-	/* Sanity check arguments */
-	Assert(port);
+    /* Sanity check arguments */
+    Assert(port);
 
-	return (port->OUT.reg & mask);
+    return (port->OUT.reg & mask);
 }
 
 /**
@@ -381,15 +381,15 @@ static inline uint32_t port_group_get_output_level(
  *  \param[in]  level_mask  Mask of the port level(s) to set
  */
 static inline void port_group_set_output_level(
-		PortGroup *const port,
-		const uint32_t mask,
-		const uint32_t level_mask)
+        PortGroup *const port,
+        const uint32_t mask,
+        const uint32_t level_mask)
 {
-	/* Sanity check arguments */
-	Assert(port);
+    /* Sanity check arguments */
+    Assert(port);
 
-	port->OUTSET.reg = (mask &  level_mask);
-	port->OUTCLR.reg = (mask & ~level_mask);
+    port->OUTSET.reg = (mask &  level_mask);
+    port->OUTCLR.reg = (mask & ~level_mask);
 }
 
 /**
@@ -401,13 +401,13 @@ static inline void port_group_set_output_level(
  *  \param[in]  mask  Mask of the port pin(s) to toggle
  */
 static inline void port_group_toggle_output_level(
-		PortGroup *const port,
-		const uint32_t mask)
+        PortGroup *const port,
+        const uint32_t mask)
 {
-	/* Sanity check arguments */
-	Assert(port);
+    /* Sanity check arguments */
+    Assert(port);
 
-	port->OUTTGL.reg = mask;
+    port->OUTTGL.reg = mask;
 }
 
 /** @} */
@@ -430,25 +430,25 @@ static inline void port_group_toggle_output_level(
  *  \param[out] config  Configuration structure to initialize to default values
  */
 static inline void port_get_config_defaults(
-		struct port_config *const config)
+        struct port_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->direction  = PORT_PIN_DIR_INPUT;
-	config->input_pull = PORT_PIN_PULL_UP;
-	config->powersave  = false;
+    /* Default configuration values */
+    config->direction  = PORT_PIN_DIR_INPUT;
+    config->input_pull = PORT_PIN_PULL_UP;
+    config->powersave  = false;
 }
 
 void port_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct port_config *const config);
+        const uint8_t gpio_pin,
+        const struct port_config *const config);
 
 void port_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct port_config *const config);
+        PortGroup *const port,
+        const uint32_t mask,
+        const struct port_config *const config);
 
 /** @} */
 
@@ -467,12 +467,12 @@ void port_group_set_config(
  *  \return Status of the port pin's input buffer.
  */
 static inline bool port_pin_get_input_level(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_mask  = (1UL << (gpio_pin % 32));
 
-	return (port_base->IN.reg & pin_mask);
+    return (port_base->IN.reg & pin_mask);
 }
 
 /**
@@ -486,12 +486,12 @@ static inline bool port_pin_get_input_level(
  *  \return Status of the port pin's output buffer.
  */
 static inline bool port_pin_get_output_level(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_mask  = (1UL << (gpio_pin % 32));
 
-	return (port_base->OUT.reg & pin_mask);
+    return (port_base->OUT.reg & pin_mask);
 }
 
 /**
@@ -503,18 +503,19 @@ static inline bool port_pin_get_output_level(
  *  \param[in] level     Logical level to set the given pin to
  */
 static inline void port_pin_set_output_level(
-		const uint8_t gpio_pin,
-		const bool level)
+        const uint8_t gpio_pin,
+        const bool level)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
-
-	/* Set the pin to high or low atomically based on the requested level */
-	if (level) {
-		port_base->OUTSET.reg = pin_mask;
-	} else {
-		port_base->OUTCLR.reg = pin_mask;
-	}
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+
+    /* Set the pin to high or low atomically based on the requested level */
+    if (level)
+    {
+        port_base->OUTSET.reg = pin_mask;
+    } else {
+        port_base->OUTCLR.reg = pin_mask;
+    }
 }
 
 /**
@@ -525,13 +526,13 @@ static inline void port_pin_set_output_level(
  *  \param[in] gpio_pin  Index of the GPIO pin to toggle
  */
 static inline void port_pin_toggle_output_level(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask  = (1UL << (gpio_pin % 32));
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_mask  = (1UL << (gpio_pin % 32));
 
-	/* Toggle pin output level */
-	port_base->OUTTGL.reg = pin_mask;
+    /* Toggle pin output level */
+    port_base->OUTTGL.reg = pin_mask;
 }
 
 /** @} */
@@ -554,28 +555,29 @@ static inline void port_pin_toggle_output_level(
  * \retval STATUS_OK               Successfully
  */
 static inline enum status_code port_enable_input_event(
-		const uint8_t gpio_pin,
-		const enum port_input_event n)
+        const uint8_t gpio_pin,
+        const enum port_input_event n)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    switch (n)
+    {
+        case PORT_INPUT_EVENT_0:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0;
+            break;
+        case PORT_INPUT_EVENT_1:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1;
+            break;
+        case PORT_INPUT_EVENT_2:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2;
+            break;
+        case PORT_INPUT_EVENT_3:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -590,28 +592,29 @@ static inline enum status_code port_enable_input_event(
  * \retval STATUS_OK               Successfully
  */
 static inline enum status_code port_disable_input_event(
-		const uint8_t gpio_pin,
-		const enum port_input_event n)
+        const uint8_t gpio_pin,
+        const enum port_input_event n)
 {
-	PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
+    switch (n)
+    {
+        case PORT_INPUT_EVENT_0:
+            port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0;
+            break;
+        case PORT_INPUT_EVENT_1:
+            port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1;
+            break;
+        case PORT_INPUT_EVENT_2:
+            port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2;
+            break;
+        case PORT_INPUT_EVENT_3:
+            port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -624,11 +627,11 @@ static inline enum status_code port_disable_input_event(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void port_input_event_get_config_defaults(
-		struct port_input_event_config *const config)
+        struct port_input_event_config *const config)
 {
-	Assert(config);
-	config->action   = PORT_INPUT_EVENT_ACTION_OUT;
-	config->gpio_pin = 0;
+    Assert(config);
+    config->action   = PORT_INPUT_EVENT_ACTION_OUT;
+    config->gpio_pin = 0;
 }
 
 /**
@@ -643,41 +646,42 @@ static inline void port_input_event_get_config_defaults(
  */
 
 static inline enum status_code port_input_event_set_config(
-		const enum port_input_event n,
-		struct port_input_event_config *const config)
+        const enum port_input_event n,
+        struct port_input_event_config *const config)
 {
-	Assert(config);
-	PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
-	uint8_t pin_index = config->gpio_pin % 32;
-	struct port_config pin_conf;
-
-	port_get_config_defaults(&pin_conf);
-	/* Configure the GPIO pin as outputs*/
-	pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
-	port_pin_set_config(config->gpio_pin, &pin_conf);
-
-	switch (n) {
-		case PORT_INPUT_EVENT_0:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
-									| PORT_EVCTRL_PID0(pin_index);
-			break;
-		case PORT_INPUT_EVENT_1:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
-						   		   | PORT_EVCTRL_PID1(pin_index);
-			break;
-		case PORT_INPUT_EVENT_2:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
-						   		   | PORT_EVCTRL_PID2(pin_index);
-			break;
-		case PORT_INPUT_EVENT_3:
-			port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
-						   		   | PORT_EVCTRL_PID3(pin_index);
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    Assert(config);
+    PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin);
+    uint8_t pin_index = config->gpio_pin % 32;
+    struct port_config pin_conf;
+
+    port_get_config_defaults(&pin_conf);
+    /* Configure the GPIO pin as outputs*/
+    pin_conf.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(config->gpio_pin, &pin_conf);
+
+    switch (n)
+    {
+        case PORT_INPUT_EVENT_0:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action)
+                                    | PORT_EVCTRL_PID0(pin_index);
+            break;
+        case PORT_INPUT_EVENT_1:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action)
+                                   | PORT_EVCTRL_PID1(pin_index);
+            break;
+        case PORT_INPUT_EVENT_2:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action)
+                                   | PORT_EVCTRL_PID2(pin_index);
+            break;
+        case PORT_INPUT_EVENT_3:
+            port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action)
+                                   | PORT_EVCTRL_PID3(pin_index);
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /** @} */
@@ -698,18 +702,18 @@ static inline enum status_code port_input_event_set_config(
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>GPIO</td>
- *		<td>General Purpose Input/Output</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>GPIO</td>
+ *      <td>General Purpose Input/Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
  * </table>
  *
  *
@@ -730,15 +734,15 @@ static inline enum status_code port_input_event_set_config(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added input event feature</td>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Added input event feature</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -756,37 +760,37 @@ static inline enum status_code port_input_event_set_config(
  * \page asfdoc_sam0_port_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42113E</td>
- *		<td>12/2015</td>
- *		<td>Added input event feature.
- *			Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1.</td>
- *	</tr>
- *	<tr>
- *		<td>42113D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42113C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42113B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42113A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42113E</td>
+ *      <td>12/2015</td>
+ *      <td>Added input event feature.
+ *          Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42113D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42113C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42113B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42113A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c
index 05ebbad5a140..654d886131a2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.c
@@ -51,19 +51,20 @@
  */
 static uint32_t _pwm_reg_output_polarity(enum pwm_device_select device_select)
 {
-	switch (device_select) {
-		case PWM0:
-			return LPMCU_MISC_REGS_PWM0_CTRL_OUTPUT_POLARITY;
-		case PWM1:
-			return LPMCU_MISC_REGS_PWM1_CTRL_OUTPUT_POLARITY;
-		case PWM2:
-			return LPMCU_MISC_REGS_PWM2_CTRL_OUTPUT_POLARITY;
-		case PWM3:
-			return LPMCU_MISC_REGS_PWM3_CTRL_OUTPUT_POLARITY;
-
-		default:
-			return 0;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            return LPMCU_MISC_REGS_PWM0_CTRL_OUTPUT_POLARITY;
+        case PWM1:
+            return LPMCU_MISC_REGS_PWM1_CTRL_OUTPUT_POLARITY;
+        case PWM2:
+            return LPMCU_MISC_REGS_PWM2_CTRL_OUTPUT_POLARITY;
+        case PWM3:
+            return LPMCU_MISC_REGS_PWM3_CTRL_OUTPUT_POLARITY;
+
+        default:
+            return 0;
+    }
 }
 
 /**
@@ -71,19 +72,20 @@ static uint32_t _pwm_reg_output_polarity(enum pwm_device_select device_select)
  */
 static uint32_t _pwm_reg_agcdata_fmt(enum pwm_device_select device_select)
 {
-	switch (device_select) {
-		case PWM0:
-			return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_FMT;
-		case PWM1:
-			return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_FMT;
-		case PWM2:
-			return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_FMT;
-		case PWM3:
-			return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_FMT;
-
-		default:
-			return 0;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_FMT;
+        case PWM1:
+            return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_FMT;
+        case PWM2:
+            return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_FMT;
+        case PWM3:
+            return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_FMT;
+
+        default:
+            return 0;
+    }
 }
 
 /**
@@ -91,23 +93,24 @@ static uint32_t _pwm_reg_agcdata_fmt(enum pwm_device_select device_select)
  */
 static uint32_t _pwm_reg_sample_method(enum pwm_device_select device_select, bool value)
 {
-	switch (device_select) {
-		case PWM0:
-			return (LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD &
-					((value) << LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD_Pos));
-		case PWM1:
-			return (LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD &
-					((value) << LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD_Pos));
-		case PWM2:
-			return (LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD &
-					((value) << LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD_Pos));
-		case PWM3:
-			return (LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD & 
-					((value) << LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD_Pos));
-
-		default:
-			return 0;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            return (LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD &
+                    ((value) << LPMCU_MISC_REGS_PWM0_CTRL_SAMPLE_METHOD_Pos));
+        case PWM1:
+            return (LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD &
+                    ((value) << LPMCU_MISC_REGS_PWM1_CTRL_SAMPLE_METHOD_Pos));
+        case PWM2:
+            return (LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD &
+                    ((value) << LPMCU_MISC_REGS_PWM2_CTRL_SAMPLE_METHOD_Pos));
+        case PWM3:
+            return (LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD &
+                    ((value) << LPMCU_MISC_REGS_PWM3_CTRL_SAMPLE_METHOD_Pos));
+
+        default:
+            return 0;
+    }
 }
 
 /**
@@ -115,49 +118,52 @@ static uint32_t _pwm_reg_sample_method(enum pwm_device_select device_select, boo
  */
 static uint32_t _pwm_reg_period(enum pwm_device_select device_select, enum pwm_period value)
 {
-	switch (device_select) {
-		case PWM0:
-			return LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD(value);
-		case PWM1:
-			return LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD(value);
-		case PWM2:
-			return LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD(value);
-		case PWM3:
-			return LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD(value);
-
-		default:
-			return 0;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            return LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD(value);
+        case PWM1:
+            return LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD(value);
+        case PWM2:
+            return LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD(value);
+        case PWM3:
+            return LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD(value);
+
+        default:
+            return 0;
+    }
 }
 
 /**
  * \internal Get the register configuration values by PWM device
  */
 static uint32_t _pwm_reg_agcdata_in(
-				enum pwm_device_select device_select, \
-				bool agcdata_format, \
-				uint8_t duty_cycle)
+                enum pwm_device_select device_select, \
+                bool agcdata_format, \
+                uint8_t duty_cycle)
 {
-	int32_t agcdata_in;
-
-	if (agcdata_format) {
-		agcdata_in = (uint16_t)((1024 * duty_cycle) / 100);
-	} else {
-		agcdata_in = (int16_t)((1024 * duty_cycle) / 100 - 512);
-	}
-	switch (device_select) {
-		case PWM0:
-			return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN(agcdata_in);
-		case PWM1:
-			return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN(agcdata_in);
-		case PWM2:
-			return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN(agcdata_in);
-		case PWM3:
-			return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN(agcdata_in);
-
-		default:
-			return 0;
-	}
+    int32_t agcdata_in;
+
+    if (agcdata_format)
+    {
+        agcdata_in = (uint16_t)((1024 * duty_cycle) / 100);
+    } else {
+        agcdata_in = (int16_t)((1024 * duty_cycle) / 100 - 512);
+    }
+    switch (device_select)
+    {
+        case PWM0:
+            return LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN(agcdata_in);
+        case PWM1:
+            return LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN(agcdata_in);
+        case PWM2:
+            return LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN(agcdata_in);
+        case PWM3:
+            return LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN(agcdata_in);
+
+        default:
+            return 0;
+    }
 }
 
 /**
@@ -165,19 +171,20 @@ static uint32_t _pwm_reg_agcdata_in(
  */
 static uint32_t _pwm_reg_clock_sel(enum pwm_device_select device_select, enum pwm_clock_select value)
 {
-	switch (device_select) {
-		case PWM0:
-			return LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(value);
-		case PWM1:
-			return LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(value);
-		case PWM2:
-			return LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(value);
-		case PWM3:
-			return LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(value);
-
-		default:
-			return 0;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            return LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(value);
+        case PWM1:
+            return LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(value);
+        case PWM2:
+            return LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(value);
+        case PWM3:
+            return LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(value);
+
+        default:
+            return 0;
+    }
 }
 
 /**
@@ -201,14 +208,14 @@ static uint32_t _pwm_reg_clock_sel(enum pwm_device_select device_select, enum pw
  */
 void pwm_get_config_defaults(struct pwm_config *const config)
 {
-	config->output_polarity = false;
-	config->agcdata_format = false;
-	config->sample_method = PWM_SAMPLE_METHOD_0;
-	config->period = PWM_PERIOD_4;
-	config->duty_cycle = 50;
-	config->clock_select = PWM_CLOCK_SELECT_26_0;
-	config->pin_number_pad = 0;
-	config->pinmux_sel_pad = 0;
+    config->output_polarity = false;
+    config->agcdata_format = false;
+    config->sample_method = PWM_SAMPLE_METHOD_0;
+    config->period = PWM_PERIOD_4;
+    config->duty_cycle = 50;
+    config->clock_select = PWM_CLOCK_SELECT_26_0;
+    config->pin_number_pad = 0;
+    config->pinmux_sel_pad = 0;
 }
 
 /**
@@ -221,44 +228,45 @@ void pwm_get_config_defaults(struct pwm_config *const config)
  * \param[in]   duty_cycle      This value specifies the duty cycle(%)
  */
 void pwm_set_duty_cycle(enum pwm_device_select device_select, \
-					uint8_t duty_cycle)
+                    uint8_t duty_cycle)
 {
-	bool agcdata_format;
-	uint32_t temp;
-
-	switch(device_select) {
-		case PWM0:
-			agcdata_format = LPMCU_MISC_REGS0->PWM0_CTRL.bit.AGCDATA_FMT;
-			temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN_Msk;
-			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
-			break;
-
-		case PWM1:
-			agcdata_format = LPMCU_MISC_REGS0->PWM1_CTRL.bit.AGCDATA_FMT;
-			temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN_Msk;
-			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
-			break;
-
-		case PWM2:
-			agcdata_format = LPMCU_MISC_REGS0->PWM2_CTRL.bit.AGCDATA_FMT;
-			temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN_Msk;
-			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
-			break;
-
-		case PWM3:
-			agcdata_format = LPMCU_MISC_REGS0->PWM3_CTRL.bit.AGCDATA_FMT;
-			temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN_Msk;
-			temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
-			break;
-	}
+    bool agcdata_format;
+    uint32_t temp;
+
+    switch(device_select)
+    {
+        case PWM0:
+            agcdata_format = LPMCU_MISC_REGS0->PWM0_CTRL.bit.AGCDATA_FMT;
+            temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_AGCDATA_IN_Msk;
+            temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
+            break;
+
+        case PWM1:
+            agcdata_format = LPMCU_MISC_REGS0->PWM1_CTRL.bit.AGCDATA_FMT;
+            temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_AGCDATA_IN_Msk;
+            temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
+            break;
+
+        case PWM2:
+            agcdata_format = LPMCU_MISC_REGS0->PWM2_CTRL.bit.AGCDATA_FMT;
+            temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_AGCDATA_IN_Msk;
+            temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
+            break;
+
+        case PWM3:
+            agcdata_format = LPMCU_MISC_REGS0->PWM3_CTRL.bit.AGCDATA_FMT;
+            temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_AGCDATA_IN_Msk;
+            temp |= _pwm_reg_agcdata_in(device_select, agcdata_format, duty_cycle);
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
+            break;
+    }
 }
 
 /**
@@ -271,45 +279,47 @@ void pwm_set_duty_cycle(enum pwm_device_select device_select, \
  * \param[in]   period          Programmable PWM update period
  */
 void pwm_set_period(enum pwm_device_select device_select, \
-					enum pwm_period period)
+                    enum pwm_period period)
 {
-	uint32_t reg_value;
-	uint32_t temp;
-
-	if (period > PWM_PERIOD_8) {
-		reg_value = PWM_PERIOD_4;
-	}
-	reg_value = _pwm_reg_period(device_select, period);
-
-	switch(device_select) {
-		case PWM0:
-			temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD_Msk;
-			temp |= reg_value;
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
-			break;
-
-		case PWM1:
-			temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD_Msk;
-			temp |= reg_value;
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
-			break;
-
-		case PWM2:
-			temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD_Msk;
-			temp |= reg_value;
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
-			break;
-
-		case PWM3:
-			temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
-			temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD_Msk;
-			temp |= reg_value;
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
-			break;
-	}
+    uint32_t reg_value;
+    uint32_t temp;
+
+    if (period > PWM_PERIOD_8)
+    {
+        reg_value = PWM_PERIOD_4;
+    }
+    reg_value = _pwm_reg_period(device_select, period);
+
+    switch(device_select)
+    {
+        case PWM0:
+            temp = LPMCU_MISC_REGS0->PWM0_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_PERIOD_Msk;
+            temp |= reg_value;
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg = temp;
+            break;
+
+        case PWM1:
+            temp = LPMCU_MISC_REGS0->PWM1_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_PERIOD_Msk;
+            temp |= reg_value;
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg = temp;
+            break;
+
+        case PWM2:
+            temp = LPMCU_MISC_REGS0->PWM2_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_PERIOD_Msk;
+            temp |= reg_value;
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg = temp;
+            break;
+
+        case PWM3:
+            temp = LPMCU_MISC_REGS0->PWM3_CTRL.reg;
+            temp &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_PERIOD_Msk;
+            temp |= reg_value;
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg = temp;
+            break;
+    }
 }
 
 /**
@@ -326,61 +336,66 @@ void pwm_set_period(enum pwm_device_select device_select, \
  * \retval STATUS_OK                   If the configuration was written
  */
 enum status_code pwm_init(enum pwm_device_select device_select, \
-		const struct pwm_config *const config)
+        const struct pwm_config *const config)
 {
-	uint32_t reg_value = 0;
-
-	if (device_select > PWM3) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	if (config->output_polarity) {
-		reg_value |= _pwm_reg_output_polarity(device_select);
-	}
-
-	if (config->agcdata_format) {
-		reg_value |= _pwm_reg_agcdata_fmt(device_select);
-	}
-
-	reg_value |= _pwm_reg_sample_method(device_select, config->sample_method);
-
-	/* If period > 8 will be set to 4 as default. */
-	if (config->period > PWM_PERIOD_8) {
-		reg_value |= _pwm_reg_period(device_select, PWM_PERIOD_4);
-	} else {
-		reg_value |= _pwm_reg_period(device_select, config->period);
-	}
-	reg_value |= _pwm_reg_agcdata_in(device_select, config->agcdata_format, \
-									config->duty_cycle);
-
-	reg_value |= _pwm_reg_clock_sel(device_select, config->clock_select);
-
-	switch(device_select) {
-		case PWM0:
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg = reg_value;
-			break;
-
-		case PWM1:
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg = reg_value;
-			break;
-
-		case PWM2:
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg = reg_value;
-			break;
-
-		case PWM3:
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg = reg_value;
-			break;
-	}
-
-	struct gpio_config config_gpio;
-	gpio_get_config_defaults(&config_gpio);
-	config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
-	gpio_pin_set_config(config->pin_number_pad, &config_gpio);
-	gpio_pinmux_cofiguration(config->pin_number_pad, \
-							(uint16_t)(config->pinmux_sel_pad));
-
-	return STATUS_OK;
+    uint32_t reg_value = 0;
+
+    if (device_select > PWM3)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    if (config->output_polarity)
+    {
+        reg_value |= _pwm_reg_output_polarity(device_select);
+    }
+
+    if (config->agcdata_format)
+    {
+        reg_value |= _pwm_reg_agcdata_fmt(device_select);
+    }
+
+    reg_value |= _pwm_reg_sample_method(device_select, config->sample_method);
+
+    /* If period > 8 will be set to 4 as default. */
+    if (config->period > PWM_PERIOD_8)
+    {
+        reg_value |= _pwm_reg_period(device_select, PWM_PERIOD_4);
+    } else {
+        reg_value |= _pwm_reg_period(device_select, config->period);
+    }
+    reg_value |= _pwm_reg_agcdata_in(device_select, config->agcdata_format, \
+                                    config->duty_cycle);
+
+    reg_value |= _pwm_reg_clock_sel(device_select, config->clock_select);
+
+    switch(device_select)
+    {
+        case PWM0:
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg = reg_value;
+            break;
+
+        case PWM1:
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg = reg_value;
+            break;
+
+        case PWM2:
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg = reg_value;
+            break;
+
+        case PWM3:
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg = reg_value;
+            break;
+    }
+
+    struct gpio_config config_gpio;
+    gpio_get_config_defaults(&config_gpio);
+    config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+    gpio_pin_set_config(config->pin_number_pad, &config_gpio);
+    gpio_pinmux_cofiguration(config->pin_number_pad, \
+                            (uint16_t)(config->pinmux_sel_pad));
+
+    return STATUS_OK;
 }
 
 /**
@@ -392,27 +407,28 @@ enum status_code pwm_init(enum pwm_device_select device_select, \
  */
 void pwm_enable(enum pwm_device_select device_select)
 {
-	switch (device_select) {
-		case PWM0:
-			system_clock_peripheral_enable(PERIPHERAL_PWM0);
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg |= LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
-			break;
-
-		case PWM1:
-			system_clock_peripheral_enable(PERIPHERAL_PWM1);
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg |= LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
-			break;
-
-		case PWM2:
-			system_clock_peripheral_enable(PERIPHERAL_PWM2);
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg |= LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
-			break;
-
-		case PWM3:
-			system_clock_peripheral_enable(PERIPHERAL_PWM3);
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg |= LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
-			break;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            system_clock_peripheral_enable(PERIPHERAL_PWM0);
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg |= LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
+            break;
+
+        case PWM1:
+            system_clock_peripheral_enable(PERIPHERAL_PWM1);
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg |= LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
+            break;
+
+        case PWM2:
+            system_clock_peripheral_enable(PERIPHERAL_PWM2);
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg |= LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
+            break;
+
+        case PWM3:
+            system_clock_peripheral_enable(PERIPHERAL_PWM3);
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg |= LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
+            break;
+    }
 }
 
 /**
@@ -424,27 +440,28 @@ void pwm_enable(enum pwm_device_select device_select)
  */
 void pwm_disable(enum pwm_device_select device_select)
 {
-	switch (device_select) {
-		case PWM0:
-			system_clock_peripheral_disable(PERIPHERAL_PWM0);
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
-			break;
-
-		case PWM1:
-			system_clock_peripheral_disable(PERIPHERAL_PWM1);
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
-			break;
-
-		case PWM2:
-			system_clock_peripheral_disable(PERIPHERAL_PWM2);
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
-			break;
-
-		case PWM3:
-			system_clock_peripheral_disable(PERIPHERAL_PWM3);
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
-			break;
-	}
+    switch (device_select)
+    {
+        case PWM0:
+            system_clock_peripheral_disable(PERIPHERAL_PWM0);
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg &= ~LPMCU_MISC_REGS_PWM0_CTRL_PWM_EN;
+            break;
+
+        case PWM1:
+            system_clock_peripheral_disable(PERIPHERAL_PWM1);
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg &= ~LPMCU_MISC_REGS_PWM1_CTRL_PWM_EN;
+            break;
+
+        case PWM2:
+            system_clock_peripheral_disable(PERIPHERAL_PWM2);
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg &= ~LPMCU_MISC_REGS_PWM2_CTRL_PWM_EN;
+            break;
+
+        case PWM3:
+            system_clock_peripheral_disable(PERIPHERAL_PWM3);
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg &= ~LPMCU_MISC_REGS_PWM3_CTRL_PWM_EN;
+            break;
+    }
 }
 
 /**
@@ -456,21 +473,22 @@ void pwm_disable(enum pwm_device_select device_select)
  */
 void pwm_reset(enum pwm_device_select device_select)
 {
-	switch (device_select) {
-		case PWM0:
-			system_peripheral_reset(PERIPHERAL_PWM0);
-			break;
-
-		case PWM1:
-			system_peripheral_reset(PERIPHERAL_PWM1);
-			break;
-
-		case PWM2:
-			system_peripheral_reset(PERIPHERAL_PWM2);
-			break;
-
-		case PWM3:
-			system_peripheral_reset(PERIPHERAL_PWM3);
-			break;
-	}
-}
\ No newline at end of file
+    switch (device_select)
+    {
+        case PWM0:
+            system_peripheral_reset(PERIPHERAL_PWM0);
+            break;
+
+        case PWM1:
+            system_peripheral_reset(PERIPHERAL_PWM1);
+            break;
+
+        case PWM2:
+            system_peripheral_reset(PERIPHERAL_PWM2);
+            break;
+
+        case PWM3:
+            system_peripheral_reset(PERIPHERAL_PWM3);
+            break;
+    }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h
index 366c1b32b904..547ffa81dd38 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/pwm/pwm.h
@@ -159,14 +159,14 @@ extern "C" {
  *  Enum for the possible settings of pwm device configuration.
  */
 enum pwm_device_select {
-	/** PWM module 0 */
-	PWM0 = 0,
-	/** PWM module 1 */
-	PWM1,
-	/** PWM module 2 */
-	PWM2,
-	/** PWM module 3 */
-	PWM3,
+    /** PWM module 0 */
+    PWM0 = 0,
+    /** PWM module 1 */
+    PWM1,
+    /** PWM module 2 */
+    PWM2,
+    /** PWM module 3 */
+    PWM3,
 };
 
 /**
@@ -175,10 +175,10 @@ enum pwm_device_select {
  *  Enum for the possible settings of pwm sample method configuration.
  */
 enum pwm_sample_method {
-	/** Samples agcdata at >= 1024 cycles and does not lose precision */
-	PWM_SAMPLE_METHOD_0 = 0,
-	/** Samples at PWM period but will lose LSBs if less than 1024 */
-	PWM_SAMPLE_METHOD_1,
+    /** Samples agcdata at >= 1024 cycles and does not lose precision */
+    PWM_SAMPLE_METHOD_0 = 0,
+    /** Samples at PWM period but will lose LSBs if less than 1024 */
+    PWM_SAMPLE_METHOD_1,
 };
 
 /**
@@ -187,24 +187,24 @@ enum pwm_sample_method {
  *  Enum for the possible settings of pwm period configuration.
  */
 enum pwm_period {
-	/** PWM perid 0 */
-	PWM_PERIOD_0 = 0,
-	/** PWM perid 1 */
-	PWM_PERIOD_1,
-	/** PWM perid 2 */
-	PWM_PERIOD_2,
-	/** PWM perid 3 */
-	PWM_PERIOD_3,
-	/** PWM perid 4 */
-	PWM_PERIOD_4,
-	/** PWM perid 5 */
-	PWM_PERIOD_5,
-	/** PWM perid 6 */
-	PWM_PERIOD_6,
-	/** PWM perid 7 */
-	PWM_PERIOD_7,
-	/** PWM perid 8 */
-	PWM_PERIOD_8,
+    /** PWM perid 0 */
+    PWM_PERIOD_0 = 0,
+    /** PWM perid 1 */
+    PWM_PERIOD_1,
+    /** PWM perid 2 */
+    PWM_PERIOD_2,
+    /** PWM perid 3 */
+    PWM_PERIOD_3,
+    /** PWM perid 4 */
+    PWM_PERIOD_4,
+    /** PWM perid 5 */
+    PWM_PERIOD_5,
+    /** PWM perid 6 */
+    PWM_PERIOD_6,
+    /** PWM perid 7 */
+    PWM_PERIOD_7,
+    /** PWM perid 8 */
+    PWM_PERIOD_8,
 };
 
 /**
@@ -213,14 +213,14 @@ enum pwm_period {
  *  Enum for the possible settings of pwm clock select configuration.
  */
 enum pwm_clock_select {
-	/** Clock 26MHz */
-	PWM_CLOCK_SELECT_26_0 = 0,
-	/** Clock 13MHz */
-	PWM_CLOCK_SELECT_13_0,
-	/** Clock 6.5MHz */
-	PWM_CLOCK_SELECT_6_5,
-	/** Clock 3.25MHz */
-	PWM_CLOCK_SELECT_3_25,
+    /** Clock 26MHz */
+    PWM_CLOCK_SELECT_26_0 = 0,
+    /** Clock 13MHz */
+    PWM_CLOCK_SELECT_13_0,
+    /** Clock 6.5MHz */
+    PWM_CLOCK_SELECT_6_5,
+    /** Clock 3.25MHz */
+    PWM_CLOCK_SELECT_3_25,
 };
 
 /**
@@ -231,22 +231,22 @@ enum pwm_clock_select {
  *  modified by the user application.
  */
 struct pwm_config {
-	/** 1 to inverse the polarity */
-	bool output_polarity;
-	/** AGC data format */
-	bool agcdata_format;
-	/** Sample method */
-	enum pwm_sample_method sample_method;
-	/** Programmable PWM update period */
-	enum pwm_period period;
-	/** This value specifies the duty cycle(%) */
-	uint8_t duty_cycle;
-	/** PWM Source Clock Frequency Select */
-	enum pwm_clock_select clock_select;
-	/** PWM PAD pin number */
-	uint32_t pin_number_pad;
-	/** PWM PAD pinmux selection */
-	uint32_t pinmux_sel_pad;
+    /** 1 to inverse the polarity */
+    bool output_polarity;
+    /** AGC data format */
+    bool agcdata_format;
+    /** Sample method */
+    enum pwm_sample_method sample_method;
+    /** Programmable PWM update period */
+    enum pwm_period period;
+    /** This value specifies the duty cycle(%) */
+    uint8_t duty_cycle;
+    /** PWM Source Clock Frequency Select */
+    enum pwm_clock_select clock_select;
+    /** PWM PAD pin number */
+    uint32_t pin_number_pad;
+    /** PWM PAD pinmux selection */
+    uint32_t pinmux_sel_pad;
 };
 
 /** \name Configuration and initialization
@@ -255,11 +255,11 @@ struct pwm_config {
 
 void pwm_get_config_defaults(struct pwm_config *const config);
 void pwm_set_duty_cycle(enum pwm_device_select device_select, \
-					uint8_t duty_cycle);
+                    uint8_t duty_cycle);
 void pwm_set_period(enum pwm_device_select device_select, \
-					enum pwm_period period);
+                    enum pwm_period period);
 enum status_code pwm_init(enum pwm_device_select device_select, \
-					const struct pwm_config *const config);
+                    const struct pwm_config *const config);
 
 /** @} */
 
@@ -289,14 +289,14 @@ void pwm_reset(enum pwm_device_select device_select);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>PWM</td>
- *		<td>Pulse Width Modulation</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>PWM</td>
+ *      <td>Pulse Width Modulation</td>
+ *  </tr>
  * </table>
  *
  *
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c
index 3b023db12c04..fbc49d2545e9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.c
@@ -68,33 +68,33 @@ static quad_decoder_callback_t quad_decoder2_callback = NULL;
  */
 void quad_decoder_get_config_defaults(struct quad_decoder_config *config)
 {
-	/* Axis X */
-	config->qdec0.clock_sel = QDEC_CLK_INPUT_0;
-	config->qdec0.threshold_upper = 32767;
-	config->qdec0.threshold_lower = -32768;
-	config->qdec0.pin_number_pad[0] = 0;
-	config->qdec0.pin_number_pad[1] = 0;
-	config->qdec0.pinmux_sel_pad[0] = 0;
-	config->qdec0.pinmux_sel_pad[1] = 0;
-	config->qdec_enalbe = (1 << QDEC_AXIS_X);
-	/* Axis Y */
-	config->qdec1.clock_sel = QDEC_CLK_INPUT_0;
-	config->qdec1.threshold_upper = 32767;
-	config->qdec1.threshold_lower = -32768;
-	config->qdec1.pin_number_pad[0] = 0;
-	config->qdec1.pin_number_pad[1] = 0;
-	config->qdec1.pinmux_sel_pad[0] = 0;
-	config->qdec1.pinmux_sel_pad[1] = 0;
-	config->qdec_enalbe |= (1 << QDEC_AXIS_Y);
-	/* Axis Z */
-	config->qdec2.clock_sel = QDEC_CLK_INPUT_0;
-	config->qdec2.threshold_upper = 32767;
-	config->qdec2.threshold_lower = -32768;
-	config->qdec2.pin_number_pad[0] = 0;
-	config->qdec2.pin_number_pad[1] = 0;
-	config->qdec2.pinmux_sel_pad[0] = 0;
-	config->qdec2.pinmux_sel_pad[1] = 0;
-	config->qdec_enalbe |= (1 << QDEC_AXIS_Z);
+    /* Axis X */
+    config->qdec0.clock_sel = QDEC_CLK_INPUT_0;
+    config->qdec0.threshold_upper = 32767;
+    config->qdec0.threshold_lower = -32768;
+    config->qdec0.pin_number_pad[0] = 0;
+    config->qdec0.pin_number_pad[1] = 0;
+    config->qdec0.pinmux_sel_pad[0] = 0;
+    config->qdec0.pinmux_sel_pad[1] = 0;
+    config->qdec_enalbe = (1 << QDEC_AXIS_X);
+    /* Axis Y */
+    config->qdec1.clock_sel = QDEC_CLK_INPUT_0;
+    config->qdec1.threshold_upper = 32767;
+    config->qdec1.threshold_lower = -32768;
+    config->qdec1.pin_number_pad[0] = 0;
+    config->qdec1.pin_number_pad[1] = 0;
+    config->qdec1.pinmux_sel_pad[0] = 0;
+    config->qdec1.pinmux_sel_pad[1] = 0;
+    config->qdec_enalbe |= (1 << QDEC_AXIS_Y);
+    /* Axis Z */
+    config->qdec2.clock_sel = QDEC_CLK_INPUT_0;
+    config->qdec2.threshold_upper = 32767;
+    config->qdec2.threshold_lower = -32768;
+    config->qdec2.pin_number_pad[0] = 0;
+    config->qdec2.pin_number_pad[1] = 0;
+    config->qdec2.pinmux_sel_pad[0] = 0;
+    config->qdec2.pinmux_sel_pad[1] = 0;
+    config->qdec_enalbe |= (1 << QDEC_AXIS_Z);
 }
 
 /**
@@ -105,31 +105,37 @@ void quad_decoder_get_config_defaults(struct quad_decoder_config *config)
  */
 static void quad_decoder_isr_handler(void)
 {
-	uint8_t status = LPMCU_MISC_REGS0->QUAD_DEC_IRQS.reg;
-	
-	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC0_IRQ) {
-		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLR_IRQ;
-		if (quad_decoder0_callback) {
-			quad_decoder0_callback();
-		}
-	}
-	
-	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC1_IRQ) {
-		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLR_IRQ;
-		if (quad_decoder1_callback) {
-			quad_decoder1_callback();
-		}
-	}
+    uint8_t status = LPMCU_MISC_REGS0->QUAD_DEC_IRQS.reg;
 
-	if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC2_IRQ) {
-		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLR_IRQ;
-		if (quad_decoder2_callback) {
-			quad_decoder2_callback();
-		}
-	}
+    if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC0_IRQ)
+    {
+        LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLR_IRQ;
+        if (quad_decoder0_callback)
+        {
+            quad_decoder0_callback();
+        }
+    }
+
+    if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC1_IRQ)
+    {
+        LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLR_IRQ;
+        if (quad_decoder1_callback)
+        {
+            quad_decoder1_callback();
+        }
+    }
+
+    if (status & LPMCU_MISC_REGS_QUAD_DEC_IRQS_QUAD_DEC2_IRQ)
+    {
+        LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLR_IRQ;
+        if (quad_decoder2_callback)
+        {
+            quad_decoder2_callback();
+        }
+    }
 }
 
 /**
@@ -143,41 +149,44 @@ static void quad_decoder_isr_handler(void)
  */
 void quad_decoder_init(const struct quad_decoder_config *config)
 {
-	if (config->qdec_enalbe & (1 << QDEC_AXIS_X)) {
-		system_peripheral_reset(PERIPHERAL_QDEC0);
-		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.bit.CLOCK_SEL  = config->qdec0.clock_sel;
-		LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.UPPER = config->qdec0.threshold_upper;
-		LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.LOWER = config->qdec0.threshold_lower;
-		gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[0],
-				(uint16_t)(config->qdec0.pinmux_sel_pad[0]));
-		gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[1],
-				(uint16_t)(config->qdec0.pinmux_sel_pad[1]));
-		quad_decoder_enable(QDEC_AXIS_X);
-	}
-	if (config->qdec_enalbe & (1 << QDEC_AXIS_Y)) {
-		system_peripheral_reset(PERIPHERAL_QDEC1);
-		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.bit.CLOCK_SEL  = config->qdec1.clock_sel;
-		LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.UPPER = config->qdec1.threshold_upper;
-		LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.LOWER = config->qdec1.threshold_lower;
-		gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[0],
-				(uint16_t)(config->qdec1.pinmux_sel_pad[0]));
-		gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[1],
-				(uint16_t)(config->qdec1.pinmux_sel_pad[1]));
-		quad_decoder_enable(QDEC_AXIS_Y);
-	}
-	if (config->qdec_enalbe & (1 << QDEC_AXIS_Z)) {
-		system_peripheral_reset(PERIPHERAL_QDEC2);
-		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.bit.CLOCK_SEL  = config->qdec2.clock_sel;
-		LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.UPPER = config->qdec2.threshold_upper;
-		LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.LOWER = config->qdec2.threshold_lower;
-		gpio_pinmux_cofiguration(config->qdec2.pin_number_pad[0],
-				(uint16_t)(config->qdec2.pinmux_sel_pad[0]));
-		gpio_pinmux_cofiguration(config->qdec2.pinmux_sel_pad[1],
-				(uint16_t)(config->qdec2.pinmux_sel_pad[1]));
-		quad_decoder_enable(QDEC_AXIS_Z);
-	}
-	LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_4.bit.MUX_18 =  LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_4_MUX_18_19_Val;
-	system_register_isr(33, (uint32_t)quad_decoder_isr_handler);
+    if (config->qdec_enalbe & (1 << QDEC_AXIS_X))
+    {
+        system_peripheral_reset(PERIPHERAL_QDEC0);
+        LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.bit.CLOCK_SEL  = config->qdec0.clock_sel;
+        LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.UPPER = config->qdec0.threshold_upper;
+        LPMCU_MISC_REGS0->QUAD_DEC0_THRESHOLD.bit.LOWER = config->qdec0.threshold_lower;
+        gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[0],
+                (uint16_t)(config->qdec0.pinmux_sel_pad[0]));
+        gpio_pinmux_cofiguration(config->qdec0.pin_number_pad[1],
+                (uint16_t)(config->qdec0.pinmux_sel_pad[1]));
+        quad_decoder_enable(QDEC_AXIS_X);
+    }
+    if (config->qdec_enalbe & (1 << QDEC_AXIS_Y))
+    {
+        system_peripheral_reset(PERIPHERAL_QDEC1);
+        LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.bit.CLOCK_SEL  = config->qdec1.clock_sel;
+        LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.UPPER = config->qdec1.threshold_upper;
+        LPMCU_MISC_REGS0->QUAD_DEC1_THRESHOLD.bit.LOWER = config->qdec1.threshold_lower;
+        gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[0],
+                (uint16_t)(config->qdec1.pinmux_sel_pad[0]));
+        gpio_pinmux_cofiguration(config->qdec1.pin_number_pad[1],
+                (uint16_t)(config->qdec1.pinmux_sel_pad[1]));
+        quad_decoder_enable(QDEC_AXIS_Y);
+    }
+    if (config->qdec_enalbe & (1 << QDEC_AXIS_Z))
+    {
+        system_peripheral_reset(PERIPHERAL_QDEC2);
+        LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.bit.CLOCK_SEL  = config->qdec2.clock_sel;
+        LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.UPPER = config->qdec2.threshold_upper;
+        LPMCU_MISC_REGS0->QUAD_DEC2_THRESHOLD.bit.LOWER = config->qdec2.threshold_lower;
+        gpio_pinmux_cofiguration(config->qdec2.pin_number_pad[0],
+                (uint16_t)(config->qdec2.pinmux_sel_pad[0]));
+        gpio_pinmux_cofiguration(config->qdec2.pinmux_sel_pad[1],
+                (uint16_t)(config->qdec2.pinmux_sel_pad[1]));
+        quad_decoder_enable(QDEC_AXIS_Z);
+    }
+    LPMCU_MISC_REGS0->IRQ_MUX_IO_SEL_4.bit.MUX_18 =  LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_4_MUX_18_19_Val;
+    system_register_isr(33, (uint32_t)quad_decoder_isr_handler);
 }
 
 /**
@@ -189,26 +198,27 @@ void quad_decoder_init(const struct quad_decoder_config *config)
  */
 void quad_decoder_enable(enum quad_decoder_axis qdec)
 {
-	switch (qdec) {
-	case QDEC_AXIS_X:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
-		break;
-	case QDEC_AXIS_Y:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
-		break;
-	case QDEC_AXIS_Z:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
-				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
-		break;
-	}
+    switch (qdec)
+    {
+    case QDEC_AXIS_X:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
+        break;
+    case QDEC_AXIS_Y:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
+        break;
+    case QDEC_AXIS_Z:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |=
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |=
+                LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
+        break;
+    }
 }
 
 /**
@@ -220,26 +230,27 @@ void quad_decoder_enable(enum quad_decoder_axis qdec)
  */
 void quad_decoder_disable(enum quad_decoder_axis qdec)
 {
-	switch (qdec) {
-	case QDEC_AXIS_X:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &=
-				~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
-		break;
-	case QDEC_AXIS_Y:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &=
-				~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
-		break;
-	case QDEC_AXIS_Z:
-		LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
-		LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &=
-				~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
-		break;
-	}
+    switch (qdec)
+    {
+    case QDEC_AXIS_X:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &=
+                ~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_ENABLE;
+        break;
+    case QDEC_AXIS_Y:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &=
+                ~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_ENABLE;
+        break;
+    case QDEC_AXIS_Z:
+        LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &=
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+        LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &=
+                ~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_ENABLE;
+        break;
+    }
 }
 
 /**
@@ -253,15 +264,16 @@ void quad_decoder_disable(enum quad_decoder_axis qdec)
  */
 int16_t quad_decoder_get_counter(enum quad_decoder_axis qdec)
 {
-	switch (qdec) {
-	case QDEC_AXIS_X:
-		return LPMCU_MISC_REGS0->QUAD_DEC0_STATUS.bit.COUNT;
-	case QDEC_AXIS_Y:
-		return LPMCU_MISC_REGS0->QUAD_DEC1_STATUS.bit.COUNT;
-	case QDEC_AXIS_Z:
-		return LPMCU_MISC_REGS0->QUAD_DEC2_STATUS.bit.COUNT;
-	}
-	return 0;
+    switch (qdec)
+    {
+    case QDEC_AXIS_X:
+        return LPMCU_MISC_REGS0->QUAD_DEC0_STATUS.bit.COUNT;
+    case QDEC_AXIS_Y:
+        return LPMCU_MISC_REGS0->QUAD_DEC1_STATUS.bit.COUNT;
+    case QDEC_AXIS_Z:
+        return LPMCU_MISC_REGS0->QUAD_DEC2_STATUS.bit.COUNT;
+    }
+    return 0;
 }
 
 /**
@@ -273,17 +285,18 @@ int16_t quad_decoder_get_counter(enum quad_decoder_axis qdec)
  */
 void quad_decoder_register_callback(enum quad_decoder_axis qdec, quad_decoder_callback_t fun)
 {
-	switch (qdec) {
-	case QDEC_AXIS_X:
-		quad_decoder0_callback = fun;
-		break;
-	case QDEC_AXIS_Y:
-		quad_decoder1_callback = fun;
-		break;
-	case QDEC_AXIS_Z:
-		quad_decoder2_callback = fun;
-		break;
-	}
+    switch (qdec)
+    {
+    case QDEC_AXIS_X:
+        quad_decoder0_callback = fun;
+        break;
+    case QDEC_AXIS_Y:
+        quad_decoder1_callback = fun;
+        break;
+    case QDEC_AXIS_Z:
+        quad_decoder2_callback = fun;
+        break;
+    }
 }
 
 /**
@@ -294,15 +307,16 @@ void quad_decoder_register_callback(enum quad_decoder_axis qdec, quad_decoder_ca
  */
 void quad_decoder_unregister_callback(enum quad_decoder_axis qdec)
 {
-	switch (qdec) {
-	case QDEC_AXIS_X:
-		quad_decoder0_callback = NULL;
-		break;
-	case QDEC_AXIS_Y:
-		quad_decoder1_callback = NULL;
-		break;
-	case QDEC_AXIS_Z:
-		quad_decoder2_callback = NULL;
-		break;
-	}
-}
\ No newline at end of file
+    switch (qdec)
+    {
+    case QDEC_AXIS_X:
+        quad_decoder0_callback = NULL;
+        break;
+    case QDEC_AXIS_Y:
+        quad_decoder1_callback = NULL;
+        break;
+    case QDEC_AXIS_Z:
+        quad_decoder2_callback = NULL;
+        break;
+    }
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h
index 74927445dafd..b8643508fc64 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/quad_decoder/quad_decoder.h
@@ -77,7 +77,7 @@
  * it can be used for precision measurement of speed, acceleration, and position
  * of a motor's rotor and with rotary knobs to determine user input. The SAMB11
  * contains 3 Quadrature Decoder. Each one may be programmed independently.
- * The Quadrature Decoder require initialization prior to being enabled. 
+ * The Quadrature Decoder require initialization prior to being enabled.
  * Quadrature Decoder is a flexible fully configurable module which has the following features:
  *
  *   - 3 independent configurable Quadrature Decoder blocks.
@@ -158,12 +158,12 @@ typedef void (*quad_decoder_callback_t)(void);
  * Values is the axis(x,y,z) of QUAD DECODER instance.
  */
 enum quad_decoder_axis {
-	/** AXIS X */
-	QDEC_AXIS_X = 0,
-	/** AXIS Y */
-	QDEC_AXIS_Y,
-	/** AXIS Z */
-	QDEC_AXIS_Z,
+    /** AXIS X */
+    QDEC_AXIS_X = 0,
+    /** AXIS Y */
+    QDEC_AXIS_Y,
+    /** AXIS Z */
+    QDEC_AXIS_Z,
 };
 
 /**
@@ -173,14 +173,14 @@ enum quad_decoder_axis {
  *
  */
 enum quad_decoder_clock_input {
-	/** Source from clock input 0: 26MHz */
-	QDEC_CLK_INPUT_0 = 0,
-	/** Source from clock input 1: 13MHz */
-	QDEC_CLK_INPUT_1,
-	/** Source from clock input 2: 6.5MHz */
-	QDEC_CLK_INPUT_2,
-	/** Source from clock input 3: 3MHz */
-	QDEC_CLK_INPUT_3,
+    /** Source from clock input 0: 26MHz */
+    QDEC_CLK_INPUT_0 = 0,
+    /** Source from clock input 1: 13MHz */
+    QDEC_CLK_INPUT_1,
+    /** Source from clock input 2: 6.5MHz */
+    QDEC_CLK_INPUT_2,
+    /** Source from clock input 3: 3MHz */
+    QDEC_CLK_INPUT_3,
 };
 
 /**
@@ -189,18 +189,18 @@ enum quad_decoder_clock_input {
  * Private configuration struct for Quad Decoder instance.
  */
 struct quad_decoder_private_config {
-	/** Quad Decoder Source Clock Frequency Select */
-	enum quad_decoder_clock_input clock_sel;
-	/** Upper Threshold of counter for Quad Decoder */
-	int16_t threshold_upper;
-	/** Lower Threshold of counter for Quad Decoder */
-	int16_t threshold_lower;
-	/** Dec_in_a pin number */
-	/** Dec_in_b pin number */
-	uint32_t pin_number_pad[2];
-	/** Dec_in_a pinmux selection */
-	/** Dec_in_b pinmux selection */
-	uint32_t pinmux_sel_pad[2];
+    /** Quad Decoder Source Clock Frequency Select */
+    enum quad_decoder_clock_input clock_sel;
+    /** Upper Threshold of counter for Quad Decoder */
+    int16_t threshold_upper;
+    /** Lower Threshold of counter for Quad Decoder */
+    int16_t threshold_lower;
+    /** Dec_in_a pin number */
+    /** Dec_in_b pin number */
+    uint32_t pin_number_pad[2];
+    /** Dec_in_a pinmux selection */
+    /** Dec_in_b pinmux selection */
+    uint32_t pinmux_sel_pad[2];
 };
 
 /**
@@ -212,10 +212,10 @@ struct quad_decoder_private_config {
  * before being modified by the user application.
  */
 struct quad_decoder_config {
-	uint8_t qdec_enalbe;
-	struct quad_decoder_private_config qdec0;
-	struct quad_decoder_private_config qdec1;
-	struct quad_decoder_private_config qdec2;
+    uint8_t qdec_enalbe;
+    struct quad_decoder_private_config qdec0;
+    struct quad_decoder_private_config qdec1;
+    struct quad_decoder_private_config qdec2;
 };
 
 /**
@@ -223,7 +223,7 @@ struct quad_decoder_config {
  * @{
  */
 void quad_decoder_get_config_defaults(
-		struct quad_decoder_config *config);
+        struct quad_decoder_config *config);
 void quad_decoder_init(const struct quad_decoder_config *config);
 /** @} */
 
@@ -247,7 +247,7 @@ int16_t quad_decoder_get_counter(enum quad_decoder_axis qdec);
  * @{
  */
 void quad_decoder_register_callback(enum quad_decoder_axis qdec,
-		quad_decoder_callback_t fun);
+        quad_decoder_callback_t fun);
 void quad_decoder_unregister_callback(enum quad_decoder_axis qdec);
 /** @} */
 
@@ -263,14 +263,14 @@ void quad_decoder_unregister_callback(enum quad_decoder_axis qdec);
  * Below is a table listing the acronyms used in this module, along with their
  * intended meanings.
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>Quadrature Decoder</td>
- *		<td>Quadrature Decoder</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Quadrature Decoder</td>
+ *      <td>Quadrature Decoder</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_quad_decoder_extra_dependencies Dependencies
@@ -324,4 +324,4 @@ void quad_decoder_unregister_callback(enum quad_decoder_axis qdec);
  * </table>
  */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h
index 339535bd5f82..7c6ed0b07d37 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar.h
@@ -223,7 +223,9 @@
  * applied the specified number of time (maximum 127) over 976 of these periods. The
  * corresponding correction in parts per million (PPM) will be given by:
  *
- * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ * \f[ Correction(PPM)= \frac
+ {VALUE}
+ {999424}10^6 \f]
  *
  * The RTC clock will tick faster if provided with a positive correction value,
  * and slower when given a negative correction value.
@@ -412,20 +414,20 @@ extern "C" {
  * RTC clock source.
  */
 enum rtc_clock_sel {
-	/** 1.024kHz from 32KHz internal ULP oscillator */
-	RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
-	/** 32.768kHz from 32KHz internal ULP oscillator */
-	RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
+    /** 1.024kHz from 32KHz internal ULP oscillator */
+    RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
+    /** 32.768kHz from 32KHz internal ULP oscillator */
+    RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
 #if !(SAML22)
-	/** 1.024kHz from 32KHz internal oscillator */
-	RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
-	/** 32.768kHz from 32KHz internal oscillator */
-	RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
+    /** 1.024kHz from 32KHz internal oscillator */
+    RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
+    /** 32.768kHz from 32KHz internal oscillator */
+    RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
 #endif
-	/** 1.024kHz from 32KHz internal oscillator */
-	RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
-	/** 32.768kHz from 32.768kHz external crystal oscillator */
-	RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
+    /** 1.024kHz from 32KHz internal oscillator */
+    RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
+    /** 32.768kHz from 32.768kHz external crystal oscillator */
+    RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
 };
 #endif
 
@@ -441,19 +443,19 @@ enum rtc_clock_sel {
  * \note Not all alarm channels are available on all devices.
  */
 enum rtc_calendar_alarm {
-	/** Alarm channel 0 */
-	RTC_CALENDAR_ALARM_0 = 0,
+    /** Alarm channel 0 */
+    RTC_CALENDAR_ALARM_0 = 0,
 #if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
-	/** Alarm channel 1 */
-	RTC_CALENDAR_ALARM_1 = 1,
+    /** Alarm channel 1 */
+    RTC_CALENDAR_ALARM_1 = 1,
 #endif
 #if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
-	/** Alarm channel 2 */
-	RTC_CALENDAR_ALARM_2 = 2,
+    /** Alarm channel 2 */
+    RTC_CALENDAR_ALARM_2 = 2,
 #endif
 #if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
-	/** Alarm channel 3 */
-	RTC_CALENDAR_ALARM_3 = 3,
+    /** Alarm channel 3 */
+    RTC_CALENDAR_ALARM_3 = 3,
 #endif
 };
 
@@ -462,22 +464,22 @@ enum rtc_calendar_alarm {
  * \brief Available periodic interval source.
  */
 enum rtc_calendar_periodic_interval{
-	/** Periodic interval 0 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_0 = 0,
-	/** Periodic interval 1 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_1 = 1,
-	/** Periodic interval 2 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_2 = 2,
-	/** Periodic interval 3 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_3 = 3,
-	/** Periodic interval 4 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_4 = 4,
-	/** Periodic interval 5 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_5 = 5,
-	/** Periodic interval 6 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_6 = 6,
-	/** Periodic interval 7 */
-	RTC_CALENDAR_PERIODIC_INTERVAL_7 = 7,
+    /** Periodic interval 0 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_0 = 0,
+    /** Periodic interval 1 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_1 = 1,
+    /** Periodic interval 2 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_2 = 2,
+    /** Periodic interval 3 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_3 = 3,
+    /** Periodic interval 4 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_4 = 4,
+    /** Periodic interval 5 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_5 = 5,
+    /** Periodic interval 6 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_6 = 6,
+    /** Periodic interval 7 */
+    RTC_CALENDAR_PERIODIC_INTERVAL_7 = 7,
 };
 #endif
 
@@ -489,45 +491,45 @@ enum rtc_calendar_periodic_interval{
  * The available callback types for the RTC calendar module.
  */
 enum rtc_calendar_callback {
-	/** Callback for Periodic Interval 0 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0,
-	/** Callback for Periodic Interval 1 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1,
-	/** Callback for Periodic Interval 2 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2,
-	/** Callback for Periodic Interval 3 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3,
-	/** Callback for Periodic Interval 4 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4,
-	/** Callback for Periodic Interval 5 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5,
-	/** Callback for Periodic Interval 6 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6,
-	/** Callback for Periodic Interval 7 Interrupt */
-	RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7,
-	/** Callback for alarm 0 */
-	RTC_CALENDAR_CALLBACK_ALARM_0,
+    /** Callback for Periodic Interval 0 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0 = 0,
+    /** Callback for Periodic Interval 1 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_1,
+    /** Callback for Periodic Interval 2 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_2,
+    /** Callback for Periodic Interval 3 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_3,
+    /** Callback for Periodic Interval 4 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_4,
+    /** Callback for Periodic Interval 5 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_5,
+    /** Callback for Periodic Interval 6 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_6,
+    /** Callback for Periodic Interval 7 Interrupt */
+    RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7,
+    /** Callback for alarm 0 */
+    RTC_CALENDAR_CALLBACK_ALARM_0,
 #  if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
-	/** Callback for alarm 1 */
-	RTC_CALENDAR_CALLBACK_ALARM_1,
+    /** Callback for alarm 1 */
+    RTC_CALENDAR_CALLBACK_ALARM_1,
 #  endif
 #  if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
-	/** Callback for alarm 2 */
-	RTC_CALENDAR_CALLBACK_ALARM_2,
+    /** Callback for alarm 2 */
+    RTC_CALENDAR_CALLBACK_ALARM_2,
 #  endif
 #  if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
-	/** Callback for alarm 3 */
-	RTC_CALENDAR_CALLBACK_ALARM_3,
+    /** Callback for alarm 3 */
+    RTC_CALENDAR_CALLBACK_ALARM_3,
 #  endif
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Callback for tamper */
-	RTC_CALENDAR_CALLBACK_TAMPER,
+    /** Callback for tamper */
+    RTC_CALENDAR_CALLBACK_TAMPER,
 #endif
-	/** Callback for  overflow */
-	RTC_CALENDAR_CALLBACK_OVERFLOW,
+    /** Callback for  overflow */
+    RTC_CALENDAR_CALLBACK_OVERFLOW,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_RTC_CALENDAR_CALLBACK_N
+    /** Total number of callbacks */
+    _RTC_CALENDAR_CALLBACK_N
 #  endif
 };
 #else
@@ -537,29 +539,29 @@ enum rtc_calendar_callback {
  * The available callback types for the RTC calendar module.
  */
 enum rtc_calendar_callback {
-	/** Callback for alarm 0 */
-	RTC_CALENDAR_CALLBACK_ALARM_0 = 0,
+    /** Callback for alarm 0 */
+    RTC_CALENDAR_CALLBACK_ALARM_0 = 0,
 #  if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
-	/** Callback for alarm 1 */
-	RTC_CALENDAR_CALLBACK_ALARM_1,
+    /** Callback for alarm 1 */
+    RTC_CALENDAR_CALLBACK_ALARM_1,
 #  endif
 #  if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
-	/** Callback for alarm 2 */
-	RTC_CALENDAR_CALLBACK_ALARM_2,
+    /** Callback for alarm 2 */
+    RTC_CALENDAR_CALLBACK_ALARM_2,
 #  endif
 #  if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
-	/** Callback for alarm 3 */
-	RTC_CALENDAR_CALLBACK_ALARM_3,
+    /** Callback for alarm 3 */
+    RTC_CALENDAR_CALLBACK_ALARM_3,
 #  endif
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Callback for tamper */
-	RTC_CALENDAR_CALLBACK_TAMPER,
+    /** Callback for tamper */
+    RTC_CALENDAR_CALLBACK_TAMPER,
 #endif
-	/** Callback for  overflow */
-	RTC_CALENDAR_CALLBACK_OVERFLOW,
+    /** Callback for  overflow */
+    RTC_CALENDAR_CALLBACK_OVERFLOW,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_RTC_CALENDAR_CALLBACK_N
+    /** Total number of callbacks */
+    _RTC_CALENDAR_CALLBACK_N
 #  endif
 };
 #endif
@@ -576,31 +578,31 @@ typedef void (*rtc_calendar_callback_t)(void);
  * The available input clock prescaler values for the RTC calendar module.
  */
 enum rtc_calendar_prescaler {
-	/** RTC prescaler is off, and the input clock frequency is
-	prescaled by a factor of 1 */
-	RTC_CALENDAR_PRESCALER_OFF      = RTC_MODE2_CTRLA_PRESCALER_OFF,
-	/** RTC input clock frequency is prescaled by a factor of 1 */
-	RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRLA_PRESCALER_DIV1,
-	/** RTC input clock frequency is prescaled by a factor of 2 */
-	RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRLA_PRESCALER_DIV2,
-	/** RTC input clock frequency is prescaled by a factor of 4 */
-	RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRLA_PRESCALER_DIV4,
-	/** RTC input clock frequency is prescaled by a factor of 8 */
-	RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRLA_PRESCALER_DIV8,
-	/** RTC input clock frequency is prescaled by a factor of 16 */
-	RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRLA_PRESCALER_DIV16,
-	/** RTC input clock frequency is prescaled by a factor of 32 */
-	RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRLA_PRESCALER_DIV32,
-	/** RTC input clock frequency is prescaled by a factor of 64 */
-	RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRLA_PRESCALER_DIV64,
-	/** RTC input clock frequency is prescaled by a factor of 128 */
-	RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRLA_PRESCALER_DIV128,
-	/** RTC input clock frequency is prescaled by a factor of 256 */
-	RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRLA_PRESCALER_DIV256,
-	/** RTC input clock frequency is prescaled by a factor of 512 */
-	RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRLA_PRESCALER_DIV512,
-	/** RTC input clock frequency is prescaled by a factor of 1024 */
-	RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024,
+    /** RTC prescaler is off, and the input clock frequency is
+    prescaled by a factor of 1 */
+    RTC_CALENDAR_PRESCALER_OFF      = RTC_MODE2_CTRLA_PRESCALER_OFF,
+    /** RTC input clock frequency is prescaled by a factor of 1 */
+    RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRLA_PRESCALER_DIV1,
+    /** RTC input clock frequency is prescaled by a factor of 2 */
+    RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRLA_PRESCALER_DIV2,
+    /** RTC input clock frequency is prescaled by a factor of 4 */
+    RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRLA_PRESCALER_DIV4,
+    /** RTC input clock frequency is prescaled by a factor of 8 */
+    RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRLA_PRESCALER_DIV8,
+    /** RTC input clock frequency is prescaled by a factor of 16 */
+    RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRLA_PRESCALER_DIV16,
+    /** RTC input clock frequency is prescaled by a factor of 32 */
+    RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRLA_PRESCALER_DIV32,
+    /** RTC input clock frequency is prescaled by a factor of 64 */
+    RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRLA_PRESCALER_DIV64,
+    /** RTC input clock frequency is prescaled by a factor of 128 */
+    RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRLA_PRESCALER_DIV128,
+    /** RTC input clock frequency is prescaled by a factor of 256 */
+    RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRLA_PRESCALER_DIV256,
+    /** RTC input clock frequency is prescaled by a factor of 512 */
+    RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRLA_PRESCALER_DIV512,
+    /** RTC input clock frequency is prescaled by a factor of 1024 */
+    RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRLA_PRESCALER_DIV1024,
 };
 
 #else
@@ -610,28 +612,28 @@ enum rtc_calendar_prescaler {
  * The available input clock prescaler values for the RTC calendar module.
  */
 enum rtc_calendar_prescaler {
-	/** RTC input clock frequency is prescaled by a factor of 1 */
-	RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRL_PRESCALER_DIV1,
-	/** RTC input clock frequency is prescaled by a factor of 2 */
-	RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRL_PRESCALER_DIV2,
-	/** RTC input clock frequency is prescaled by a factor of 4 */
-	RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRL_PRESCALER_DIV4,
-	/** RTC input clock frequency is prescaled by a factor of 8 */
-	RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRL_PRESCALER_DIV8,
-	/** RTC input clock frequency is prescaled by a factor of 16 */
-	RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRL_PRESCALER_DIV16,
-	/** RTC input clock frequency is prescaled by a factor of 32 */
-	RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRL_PRESCALER_DIV32,
-	/** RTC input clock frequency is prescaled by a factor of 64 */
-	RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRL_PRESCALER_DIV64,
-	/** RTC input clock frequency is prescaled by a factor of 128 */
-	RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRL_PRESCALER_DIV128,
-	/** RTC input clock frequency is prescaled by a factor of 256 */
-	RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRL_PRESCALER_DIV256,
-	/** RTC input clock frequency is prescaled by a factor of 512 */
-	RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRL_PRESCALER_DIV512,
-	/** RTC input clock frequency is prescaled by a factor of 1024 */
-	RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024,
+    /** RTC input clock frequency is prescaled by a factor of 1 */
+    RTC_CALENDAR_PRESCALER_DIV_1    = RTC_MODE2_CTRL_PRESCALER_DIV1,
+    /** RTC input clock frequency is prescaled by a factor of 2 */
+    RTC_CALENDAR_PRESCALER_DIV_2    = RTC_MODE2_CTRL_PRESCALER_DIV2,
+    /** RTC input clock frequency is prescaled by a factor of 4 */
+    RTC_CALENDAR_PRESCALER_DIV_4    = RTC_MODE2_CTRL_PRESCALER_DIV4,
+    /** RTC input clock frequency is prescaled by a factor of 8 */
+    RTC_CALENDAR_PRESCALER_DIV_8    = RTC_MODE2_CTRL_PRESCALER_DIV8,
+    /** RTC input clock frequency is prescaled by a factor of 16 */
+    RTC_CALENDAR_PRESCALER_DIV_16   = RTC_MODE2_CTRL_PRESCALER_DIV16,
+    /** RTC input clock frequency is prescaled by a factor of 32 */
+    RTC_CALENDAR_PRESCALER_DIV_32   = RTC_MODE2_CTRL_PRESCALER_DIV32,
+    /** RTC input clock frequency is prescaled by a factor of 64 */
+    RTC_CALENDAR_PRESCALER_DIV_64   = RTC_MODE2_CTRL_PRESCALER_DIV64,
+    /** RTC input clock frequency is prescaled by a factor of 128 */
+    RTC_CALENDAR_PRESCALER_DIV_128  = RTC_MODE2_CTRL_PRESCALER_DIV128,
+    /** RTC input clock frequency is prescaled by a factor of 256 */
+    RTC_CALENDAR_PRESCALER_DIV_256  = RTC_MODE2_CTRL_PRESCALER_DIV256,
+    /** RTC input clock frequency is prescaled by a factor of 512 */
+    RTC_CALENDAR_PRESCALER_DIV_512  = RTC_MODE2_CTRL_PRESCALER_DIV512,
+    /** RTC input clock frequency is prescaled by a factor of 1024 */
+    RTC_CALENDAR_PRESCALER_DIV_1024 = RTC_MODE2_CTRL_PRESCALER_DIV1024,
 };
 #endif
 
@@ -640,23 +642,23 @@ enum rtc_calendar_prescaler {
  * \brief Device structure.
  */
 struct rtc_module {
-	/** RTC hardware module */
-	Rtc *hw;
-	/** If clock mode 24h */
-	bool clock_24h;
+    /** RTC hardware module */
+    Rtc *hw;
+    /** If clock mode 24h */
+    bool clock_24h;
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	/** If continuously update clock register */
-	bool continuously_update;
+    /** If continuously update clock register */
+    bool continuously_update;
 #endif
-	/** Initial year for counter value 0 */
-	uint16_t year_init_value;
+    /** Initial year for counter value 0 */
+    uint16_t year_init_value;
 #  if RTC_CALENDAR_ASYNC == true
-	/** Pointers to callback functions */
-	volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint16_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint16_t enabled_callback;
+    /** Pointers to callback functions */
+    volatile rtc_calendar_callback_t callbacks[_RTC_CALENDAR_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint16_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint16_t enabled_callback;
 #  endif
 };
 #endif
@@ -667,20 +669,20 @@ struct rtc_module {
  * Available mask options for alarms.
  */
 enum rtc_calendar_alarm_mask {
-	/** Alarm disabled */
-	RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF,
-	/** Alarm match on second */
-	RTC_CALENDAR_ALARM_MASK_SEC      = RTC_MODE2_MASK_SEL_SS,
-	/** Alarm match on second and minute */
-	RTC_CALENDAR_ALARM_MASK_MIN      = RTC_MODE2_MASK_SEL_MMSS,
-	/** Alarm match on second, minute, and hour */
-	RTC_CALENDAR_ALARM_MASK_HOUR     = RTC_MODE2_MASK_SEL_HHMMSS,
-	/** Alarm match on second, minute, hour, and day */
-	RTC_CALENDAR_ALARM_MASK_DAY      = RTC_MODE2_MASK_SEL_DDHHMMSS,
-	/** Alarm match on second, minute, hour, day, and month */
-	RTC_CALENDAR_ALARM_MASK_MONTH    = RTC_MODE2_MASK_SEL_MMDDHHMMSS,
-	/** Alarm match on second, minute, hour, day, month, and year */
-	RTC_CALENDAR_ALARM_MASK_YEAR     = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS,
+    /** Alarm disabled */
+    RTC_CALENDAR_ALARM_MASK_DISABLED = RTC_MODE2_MASK_SEL_OFF,
+    /** Alarm match on second */
+    RTC_CALENDAR_ALARM_MASK_SEC      = RTC_MODE2_MASK_SEL_SS,
+    /** Alarm match on second and minute */
+    RTC_CALENDAR_ALARM_MASK_MIN      = RTC_MODE2_MASK_SEL_MMSS,
+    /** Alarm match on second, minute, and hour */
+    RTC_CALENDAR_ALARM_MASK_HOUR     = RTC_MODE2_MASK_SEL_HHMMSS,
+    /** Alarm match on second, minute, hour, and day */
+    RTC_CALENDAR_ALARM_MASK_DAY      = RTC_MODE2_MASK_SEL_DDHHMMSS,
+    /** Alarm match on second, minute, hour, day, and month */
+    RTC_CALENDAR_ALARM_MASK_MONTH    = RTC_MODE2_MASK_SEL_MMDDHHMMSS,
+    /** Alarm match on second, minute, hour, day, month, and year */
+    RTC_CALENDAR_ALARM_MASK_YEAR     = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS,
 };
 
 /**
@@ -690,20 +692,20 @@ enum rtc_calendar_alarm_mask {
  * \ref rtc_calendar_disable_events().
  */
 struct rtc_calendar_events {
-	/** Generate an output event on each overflow of the RTC count */
-	bool generate_event_on_overflow;
-	/** Generate an output event on an alarm channel match against the RTC
-	 *  count */
-	bool generate_event_on_alarm[RTC_NUM_OF_ALARMS];
-	/** Generate an output event periodically at a binary division of the RTC
-	 *  counter frequency
-	 */
-	bool generate_event_on_periodic[8];
+    /** Generate an output event on each overflow of the RTC count */
+    bool generate_event_on_overflow;
+    /** Generate an output event on an alarm channel match against the RTC
+     *  count */
+    bool generate_event_on_alarm[RTC_NUM_OF_ALARMS];
+    /** Generate an output event periodically at a binary division of the RTC
+     *  counter frequency
+     */
+    bool generate_event_on_periodic[8];
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Generate an output event on every tamper input */
-	bool generate_event_on_tamper;
-	/** Tamper input event and capture the CLOCK value */
-	bool on_event_to_tamper;
+    /** Generate an output event on every tamper input */
+    bool generate_event_on_tamper;
+    /** Tamper input event and capture the CLOCK value */
+    bool on_event_to_tamper;
 #endif
 };
 
@@ -716,20 +718,20 @@ struct rtc_calendar_events {
  * \ref rtc_calendar_get_time_defaults() function before use.
  */
 struct rtc_calendar_time {
-	/** Second value */
-	uint8_t  second;
-	/** Minute value */
-	uint8_t  minute;
-	/** Hour value */
-	uint8_t  hour;
-	/** PM/AM value, \c true for PM, or \c false for AM */
-	bool     pm;
-	/** Day value, where day 1 is the first day of the month */
-	uint8_t  day;
-	/** Month value, where month 1 is January */
-	uint8_t  month;
-	/** Year value */
-	uint16_t year;
+    /** Second value */
+    uint8_t  second;
+    /** Minute value */
+    uint8_t  minute;
+    /** Hour value */
+    uint8_t  hour;
+    /** PM/AM value, \c true for PM, or \c false for AM */
+    bool     pm;
+    /** Day value, where day 1 is the first day of the month */
+    uint8_t  day;
+    /** Month value, where month 1 is January */
+    uint8_t  month;
+    /** Year value */
+    uint16_t year;
 };
 
 /**
@@ -739,10 +741,10 @@ struct rtc_calendar_time {
  * the alarm will trigger.
  */
 struct rtc_calendar_alarm_time {
-	/** Alarm time */
-	struct rtc_calendar_time time;
-	/** Alarm mask to determine on what precision the alarm will match */
-	enum rtc_calendar_alarm_mask mask;
+    /** Alarm time */
+    struct rtc_calendar_time time;
+    /** Alarm mask to determine on what precision the alarm will match */
+    enum rtc_calendar_alarm_mask mask;
 };
 
 /**
@@ -753,28 +755,28 @@ struct rtc_calendar_alarm_time {
  * user configurations are set.
  */
 struct rtc_calendar_config {
-	/** Input clock prescaler for the RTC module */
-	enum rtc_calendar_prescaler prescaler;
-	/** If \c true, clears the clock on alarm match */
-	bool clear_on_match;
+    /** Input clock prescaler for the RTC module */
+    enum rtc_calendar_prescaler prescaler;
+    /** If \c true, clears the clock on alarm match */
+    bool clear_on_match;
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	/** If \c true, the digital counter registers will be continuously updated
-	 *  so that internal synchronization is not needed when reading the current
-	 *  count */
-	bool continuously_update;
+    /** If \c true, the digital counter registers will be continuously updated
+     *  so that internal synchronization is not needed when reading the current
+     *  count */
+    bool continuously_update;
 #endif
-	/** If \c true, time is represented in 24 hour mode */
-	bool clock_24h;
-	/** Initial year for counter value 0 */
-	uint16_t year_init_value;
+    /** If \c true, time is represented in 24 hour mode */
+    bool clock_24h;
+    /** Initial year for counter value 0 */
+    uint16_t year_init_value;
 #if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Enable count read synchronization. The CLOCK value requires
-	 * synchronization when reading. Disabling the synchronization
-	 * will prevent the CLOCK value from displaying the current value. */
-	bool enable_read_sync;
+    /** Enable count read synchronization. The CLOCK value requires
+     * synchronization when reading. Disabling the synchronization
+     * will prevent the CLOCK value from displaying the current value. */
+    bool enable_read_sync;
 #endif
-	/** Alarm values */
-	struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS];
+    /** Alarm values */
+    struct rtc_calendar_alarm_time alarm[RTC_NUM_OF_ALARMS];
 };
 
 
@@ -792,15 +794,15 @@ struct rtc_calendar_config {
  * \param[out] time  Time structure to initialize
  */
 static inline void rtc_calendar_get_time_defaults(
-		struct rtc_calendar_time *const time)
+        struct rtc_calendar_time *const time)
 {
-	time->second = 0;
-	time->minute = 0;
-	time->hour   = 0;
-	time->pm     = 0;
-	time->day    = 1;
-	time->month  = 1;
-	time->year   = 2000;
+    time->second = 0;
+    time->minute = 0;
+    time->hour   = 0;
+    time->pm     = 0;
+    time->day    = 1;
+    time->month  = 1;
+    time->year   = 2000;
 }
 
 /**
@@ -824,30 +826,31 @@ static inline void rtc_calendar_get_time_defaults(
  *                      values
  */
 static inline void rtc_calendar_get_config_defaults(
-		struct rtc_calendar_config *const config)
+        struct rtc_calendar_config *const config)
 {
-	/* Sanity check argument */
-	Assert(config);
+    /* Sanity check argument */
+    Assert(config);
 
-	/* Initialize and set time structure to default */
-	struct rtc_calendar_time time;
-	rtc_calendar_get_time_defaults(&time);
+    /* Initialize and set time structure to default */
+    struct rtc_calendar_time time;
+    rtc_calendar_get_time_defaults(&time);
 
-	/* Set defaults into configuration structure */
-	config->prescaler           = RTC_CALENDAR_PRESCALER_DIV_1024;
-	config->clear_on_match      = false;
+    /* Set defaults into configuration structure */
+    config->prescaler           = RTC_CALENDAR_PRESCALER_DIV_1024;
+    config->clear_on_match      = false;
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	config->continuously_update = false;
+    config->continuously_update = false;
 #endif
-	config->clock_24h           = false;
-	config->year_init_value     = 2000;
+    config->clock_24h           = false;
+    config->year_init_value     = 2000;
 #if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	config->enable_read_sync    = true;
+    config->enable_read_sync    = true;
 #endif
-	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-		config->alarm[i].time = time;
-		config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR;
-	}
+    for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+    {
+        config->alarm[i].time = time;
+        config->alarm[i].mask = RTC_CALENDAR_ALARM_MASK_YEAR;
+    }
 }
 
 void rtc_calendar_reset(struct rtc_module *const module);
@@ -863,34 +866,36 @@ void rtc_calendar_disable(struct rtc_module *const module);
  * \return Index of the given RTC module instance.
  */
 uint8_t _rtc_get_inst_index(
-		Rtc *const hw)
+        Rtc *const hw)
 {
-	/* List of available RTC modules */
-	static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
-
-	/* Find index for RTC instance */
-	for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
-		if (hw == rtc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given */
-	Assert(false);
-	return 0;
+    /* List of available RTC modules */
+    static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+    /* Find index for RTC instance */
+    for (uint32_t i = 0; i < RTC_INST_NUM; i++)
+    {
+        if (hw == rtc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given */
+    Assert(false);
+    return 0;
 }
 #endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
 
 void rtc_calendar_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_calendar_config *const config);
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_calendar_config *const config);
 
 void rtc_calendar_swap_time_mode(struct rtc_module *const module);
 
 enum status_code rtc_calendar_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value);
+        struct rtc_module *const module,
+        const int8_t value);
 
 /** @} */
 
@@ -899,30 +904,30 @@ enum status_code rtc_calendar_frequency_correction(
  * @{
  */
 uint32_t rtc_calendar_time_to_register_value(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time);
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time);
 void rtc_calendar_register_value_to_time(
-		struct rtc_module *const module,
-		const uint32_t register_value,
-		struct rtc_calendar_time *const time);
+        struct rtc_module *const module,
+        const uint32_t register_value,
+        struct rtc_calendar_time *const time);
 
 void rtc_calendar_set_time(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time);
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time);
 
 void rtc_calendar_get_time(
-		struct rtc_module *const module,
-		struct rtc_calendar_time *const time);
+        struct rtc_module *const module,
+        struct rtc_calendar_time *const time);
 
 enum status_code rtc_calendar_set_alarm(
-		struct rtc_module *const module,
-		const struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index);
+        struct rtc_module *const module,
+        const struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index);
 
 enum status_code rtc_calendar_get_alarm(
-		struct rtc_module *const module,
-		struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index);
+        struct rtc_module *const module,
+        struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index);
 
 /** @} */
 
@@ -946,14 +951,14 @@ enum status_code rtc_calendar_get_alarm(
  */
 static inline bool rtc_calendar_is_overflow(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Return status of flag */
-	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF);
+    /* Return status of flag */
+    return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF);
 }
 
 /**
@@ -966,14 +971,14 @@ static inline bool rtc_calendar_is_overflow(struct rtc_module *const module)
  */
 static inline void rtc_calendar_clear_overflow(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Clear flag */
-	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+    /* Clear flag */
+    rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
 }
 
 #ifdef FEATURE_RTC_PERIODIC_INT
@@ -991,16 +996,16 @@ static inline void rtc_calendar_clear_overflow(struct rtc_module *const module)
  * \retval false  RTC periodic interval interrupt doesn't occur
  */
 static inline bool rtc_calendar_is_periodic_interval(struct rtc_module *const module,
-										enum rtc_calendar_periodic_interval n)
+                                        enum rtc_calendar_periodic_interval n)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Return status of flag */
-	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER(1 << n));
+    /* Return status of flag */
+    return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER(1 << n));
 }
 
 /**
@@ -1013,16 +1018,16 @@ static inline bool rtc_calendar_is_periodic_interval(struct rtc_module *const mo
  * \param[in]  n  RTC periodic interval interrupt
  */
 static inline void rtc_calendar_clear_periodic_interval(struct rtc_module *const module,
-											enum rtc_calendar_periodic_interval n)
+                                            enum rtc_calendar_periodic_interval n)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Clear periodic interval flag */
-	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1 << n);
+    /* Clear periodic interval flag */
+    rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1 << n);
 }
 #endif
 
@@ -1041,23 +1046,24 @@ static inline void rtc_calendar_clear_periodic_interval(struct rtc_module *const
  * \retval false  If the specified alarm has not matched the current time
  */
 static inline bool rtc_calendar_is_alarm_match(
-		struct rtc_module *const module,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		Assert(false);
-		return false;
-	}
+    /* Sanity check */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        Assert(false);
+        return false;
+    }
 
-	/* Return int flag status */
-	return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index));
+    /* Return int flag status */
+    return (rtc_module->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(1 << alarm_index));
 }
 
 /**
@@ -1075,25 +1081,26 @@ static inline bool rtc_calendar_is_alarm_match(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 static inline enum status_code rtc_calendar_clear_alarm_match(
-		struct rtc_module *const module,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Clear flag */
-	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index);
+    /* Clear flag */
+    rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << alarm_index);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** @} */
@@ -1116,50 +1123,57 @@ static inline enum status_code rtc_calendar_clear_alarm_match(
  *  \param[in] events    Struct containing flags of events to enable
  */
 static inline void rtc_calendar_enable_events(
-		struct rtc_module *const module,
-		struct rtc_calendar_events *const events)
+        struct rtc_module *const module,
+        struct rtc_calendar_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Check if the user has requested an overflow event */
-	if (events->generate_event_on_overflow) {
-		event_mask |= RTC_MODE2_EVCTRL_OVFEO;
-	}
-
-	/* Check if the user has requested any alarm events */
-	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-		if (events->generate_event_on_alarm[i]) {
-			event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
-		}
-	}
-
-	/* Check if the user has requested any periodic events */
-	for (uint8_t i = 0; i < 8; i++) {
-		if (events->generate_event_on_periodic[i]) {
-			event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Check if the user has requested an overflow event */
+    if (events->generate_event_on_overflow)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+    }
+
+    /* Check if the user has requested any alarm events */
+    for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+    {
+        if (events->generate_event_on_alarm[i])
+        {
+            event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+        }
+    }
+
+    /* Check if the user has requested any periodic events */
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if (events->generate_event_on_periodic[i])
+        {
+            event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+        }
+    }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/* Check if the user has requested a tamper event output */
-	if (events->generate_event_on_tamper) {
-		event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
-	}
-
-	/* Check if the user has requested a tamper event input */
-	if (events->on_event_to_tamper) {
-		event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
-	}
+    /* Check if the user has requested a tamper event output */
+    if (events->generate_event_on_tamper)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
+    }
+
+    /* Check if the user has requested a tamper event input */
+    if (events->on_event_to_tamper)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
+    }
 #endif
 
-	/* Enable given event(s) */
-	rtc_module->MODE2.EVCTRL.reg |= event_mask;
+    /* Enable given event(s) */
+    rtc_module->MODE2.EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -1174,50 +1188,57 @@ static inline void rtc_calendar_enable_events(
  *  \param[in] events    Struct containing flags of events to disable
  */
 static inline void rtc_calendar_disable_events(
-		struct rtc_module *const module,
-		struct rtc_calendar_events *const events)
+        struct rtc_module *const module,
+        struct rtc_calendar_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Check if the user has requested an overflow event */
-	if (events->generate_event_on_overflow) {
-		event_mask |= RTC_MODE2_EVCTRL_OVFEO;
-	}
-
-	/* Check if the user has requested any alarm events */
-	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-		if (events->generate_event_on_alarm[i]) {
-			event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
-		}
-	}
-
-	/* Check if the user has requested any periodic events */
-	for (uint8_t i = 0; i < 8; i++) {
-		if (events->generate_event_on_periodic[i]) {
-			event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Check if the user has requested an overflow event */
+    if (events->generate_event_on_overflow)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_OVFEO;
+    }
+
+    /* Check if the user has requested any alarm events */
+    for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+    {
+        if (events->generate_event_on_alarm[i])
+        {
+            event_mask |= RTC_MODE2_EVCTRL_ALARMEO(1 << i);
+        }
+    }
+
+    /* Check if the user has requested any periodic events */
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if (events->generate_event_on_periodic[i])
+        {
+            event_mask |= RTC_MODE2_EVCTRL_PEREO(1 << i);
+        }
+    }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/* Check if the user has requested a tamper event output */
-	if (events->generate_event_on_tamper) {
-		event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
-	}
-
-	/* Check if the user has requested a tamper event input */
-	if (events->on_event_to_tamper) {
-		event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
-	}
+    /* Check if the user has requested a tamper event output */
+    if (events->generate_event_on_tamper)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_TAMPEREO;
+    }
+
+    /* Check if the user has requested a tamper event input */
+    if (events->on_event_to_tamper)
+    {
+        event_mask |= RTC_MODE2_EVCTRL_TAMPEVEI;
+    }
 #endif
 
-	/* Disable given event(s) */
-	rtc_module->MODE2.EVCTRL.reg &= ~event_mask;
+    /* Disable given event(s) */
+    rtc_module->MODE2.EVCTRL.reg &= ~event_mask;
 }
 
 /** @} */
@@ -1237,18 +1258,18 @@ static inline void rtc_calendar_disable_events(
  *
  */
 static inline void rtc_write_general_purpose_reg(
-	struct rtc_module *const module,
-	const  uint8_t index,
-	uint32_t value)
+    struct rtc_module *const module,
+    const  uint8_t index,
+    uint32_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(index <= 3);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(index <= 3);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	rtc_module->MODE0.GP[index].reg = value;
+    rtc_module->MODE0.GP[index].reg = value;
 }
 
 /**
@@ -1260,17 +1281,17 @@ static inline void rtc_write_general_purpose_reg(
  * \return Value of general purpose register.
  */
 static inline uint32_t rtc_read_general_purpose_reg(
-	struct rtc_module *const module,
-	const  uint8_t index)
+    struct rtc_module *const module,
+    const  uint8_t index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(index <= 3);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(index <= 3);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	return rtc_module->MODE0.GP[index].reg;
+    return rtc_module->MODE0.GP[index].reg;
 }
 
 /** @} */
@@ -1285,7 +1306,7 @@ static inline uint32_t rtc_read_general_purpose_reg(
  * \param[out] time  Pointer to value that filled with tamper stamp time
  */
 void rtc_tamper_get_stamp (struct rtc_module *const module,
-		struct rtc_calendar_time *const time);
+        struct rtc_calendar_time *const time);
 #endif
 
 /** @} */
@@ -1303,22 +1324,22 @@ void rtc_tamper_get_stamp (struct rtc_module *const module,
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</td>
- *		<th>Description</td>
- *	</tr>
- *	<tr>
- *		<td>RTC</td>
- *		<td>Real Time Counter</td>
- *	</tr>
- *	<tr>
- *		<td>PPM</td>
- *		<td>Part Per Million</td>
- *	</tr>
- *	<tr>
- *		<td>RC</td>
- *		<td>Resistor/Capacitor</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</td>
+ *      <th>Description</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RTC</td>
+ *      <td>Real Time Counter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PPM</td>
+ *      <td>Part Per Million</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RC</td>
+ *      <td>Resistor/Capacitor</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1339,23 +1360,23 @@ void rtc_tamper_get_stamp (struct rtc_module *const module,
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added support for RTC tamper feature</td>
- *	</tr>
- *	<tr>
- *		<td>Added driver instance parameter to all API function calls, except
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for RTC tamper feature</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added driver instance parameter to all API function calls, except
  *          get_config_defaults</td>
- *	</tr>
- *	<tr>
- *		<td>Updated initialization function to also enable the digital interface
+ *  </tr>
+ *  <tr>
+ *      <td>Updated initialization function to also enable the digital interface
  *          clock to the module if it is disabled</td>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1376,37 +1397,37 @@ void rtc_tamper_get_stamp (struct rtc_module *const module,
  * \page asfdoc_sam0_rtc_calendar_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42126E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAMR30, SAM C21, SAM D09, and SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42126D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42126C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42126B</td>
- *		<td>06/2013</td>
- *		<td>Added additional documentation on the event system. Corrected
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42126E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAMR30, SAM C21, SAM D09, and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42126D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42126C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42126B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
  *          documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42126A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>42126A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h
index 21615b0f3192..2865d8ddae3f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_calendar_interrupt.h
@@ -63,21 +63,21 @@ extern "C" {
  * @{
  */
 enum status_code rtc_calendar_register_callback(
-		struct rtc_module *const module,
-		rtc_calendar_callback_t callback,
-		enum rtc_calendar_callback callback_type);
+        struct rtc_module *const module,
+        rtc_calendar_callback_t callback,
+        enum rtc_calendar_callback callback_type);
 
 enum status_code rtc_calendar_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type);
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type);
 
 void rtc_calendar_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type);
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type);
 
 void rtc_calendar_disable_callback(
-	struct rtc_module *const module,
-	enum rtc_calendar_callback callback_type);
+    struct rtc_module *const module,
+    enum rtc_calendar_callback callback_type);
 
 /** @} */
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h
index e1c7a651e7ef..bc0190f9c82d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count.h
@@ -226,7 +226,9 @@
  * applied the specified number of time (maximum 127) over 976 of these periods. The
  * corresponding correction in PPM will be given by:
  *
- * \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
+ * \f[ Correction(PPM)= \frac
+ {VALUE}
+ {999424}10^6 \f]
  *
  * The RTC clock will tick faster if provided with a positive correction value,
  * and slower when given a negative correction value.
@@ -404,20 +406,20 @@ extern "C" {
  * RTC clock source.
  */
 enum rtc_clock_sel {
-	/** 1.024KHz from 32KHz internal ULP oscillator */
-	RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
-	/** 32.768KHz from 32KHz internal ULP oscillator */
-	RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
+    /** 1.024KHz from 32KHz internal ULP oscillator */
+    RTC_CLOCK_SELECTION_ULP1K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val,
+    /** 32.768KHz from 32KHz internal ULP oscillator */
+    RTC_CLOCK_SELECTION_ULP32K = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val,
 #if !(SAML22)
-	/** 1.024KHz from 32KHz internal oscillator */
-	RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
-	/** 32.768KHz from 32KHz internal oscillator */
-	RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
+    /** 1.024KHz from 32KHz internal oscillator */
+    RTC_CLOCK_SELECTION_OSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val,
+    /** 32.768KHz from 32KHz internal oscillator */
+    RTC_CLOCK_SELECTION_OSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val,
 #endif
-	/** 1.024KHz from 32KHz external oscillator */
-	RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
-	/** 32.768KHz from 32.768KHz external crystal oscillator */
-	RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
+    /** 1.024KHz from 32KHz external oscillator */
+    RTC_CLOCK_SELECTION_XOSC1K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val,
+    /** 32.768KHz from 32.768KHz external crystal oscillator */
+    RTC_CLOCK_SELECTION_XOSC32K = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val,
 };
 #endif
 
@@ -428,10 +430,10 @@ enum rtc_clock_sel {
  * operation.
  */
 enum rtc_count_mode {
-	/** RTC Count module operates in 16-bit mode */
-	RTC_COUNT_MODE_16BIT = 0,
-	/** RTC Count module operates in 32-bit mode */
-	RTC_COUNT_MODE_32BIT = 1,
+    /** RTC Count module operates in 16-bit mode */
+    RTC_COUNT_MODE_16BIT = 0,
+    /** RTC Count module operates in 32-bit mode */
+    RTC_COUNT_MODE_32BIT = 1,
 };
 
 #if !defined (RTC_NUM_OF_COMP16) && defined(RTC_COMP16_NUM)
@@ -444,27 +446,27 @@ enum rtc_count_mode {
  * \note Not all compare channels are available in all devices and modes.
  */
 enum rtc_count_compare {
-	/** Compare channel 0 */
-	RTC_COUNT_COMPARE_0 = 0,
+    /** Compare channel 0 */
+    RTC_COUNT_COMPARE_0 = 0,
 #if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
-	/** Compare channel 1 */
-	RTC_COUNT_COMPARE_1 = 1,
+    /** Compare channel 1 */
+    RTC_COUNT_COMPARE_1 = 1,
 #endif
 #if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
-	/** Compare channel 2 */
-	RTC_COUNT_COMPARE_2 = 2,
+    /** Compare channel 2 */
+    RTC_COUNT_COMPARE_2 = 2,
 #endif
-#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
-	/** Compare channel 3 */
-	RTC_COUNT_COMPARE_3 = 3,
+#if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+    /** Compare channel 3 */
+    RTC_COUNT_COMPARE_3 = 3,
 #endif
 #if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
-	/** Compare channel 4 */
-	RTC_COUNT_COMPARE_4 = 4,
+    /** Compare channel 4 */
+    RTC_COUNT_COMPARE_4 = 4,
 #endif
 #if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
-	/** Compare channel 5 */
-	RTC_COUNT_COMPARE_5 = 5,
+    /** Compare channel 5 */
+    RTC_COUNT_COMPARE_5 = 5,
 #endif
 };
 
@@ -473,22 +475,22 @@ enum rtc_count_compare {
  * \brief Available periodic interval source.
  */
 enum rtc_count_periodic_interval{
-	/** Periodic interval 0 */
-	RTC_COUNT_PERIODIC_INTERVAL_0 = 0,
-	/** Periodic interval 1 */
-	RTC_COUNT_PERIODIC_INTERVAL_1 = 1,
-	/** Periodic interval 2 */
-	RTC_COUNT_PERIODIC_INTERVAL_2 = 2,
-	/** Periodic interval 3 */
-	RTC_COUNT_PERIODIC_INTERVAL_3 = 3,
-	/** Periodic interval 4 */
-	RTC_COUNT_PERIODIC_INTERVAL_4 = 4,
-	/** Periodic interval 5 */
-	RTC_COUNT_PERIODIC_INTERVAL_5 = 5,
-	/** Periodic interval 6 */
-	RTC_COUNT_PERIODIC_INTERVAL_6 = 6,
-	/** Periodic interval 7 */
-	RTC_COUNT_PERIODIC_INTERVAL_7 = 7,
+    /** Periodic interval 0 */
+    RTC_COUNT_PERIODIC_INTERVAL_0 = 0,
+    /** Periodic interval 1 */
+    RTC_COUNT_PERIODIC_INTERVAL_1 = 1,
+    /** Periodic interval 2 */
+    RTC_COUNT_PERIODIC_INTERVAL_2 = 2,
+    /** Periodic interval 3 */
+    RTC_COUNT_PERIODIC_INTERVAL_3 = 3,
+    /** Periodic interval 4 */
+    RTC_COUNT_PERIODIC_INTERVAL_4 = 4,
+    /** Periodic interval 5 */
+    RTC_COUNT_PERIODIC_INTERVAL_5 = 5,
+    /** Periodic interval 6 */
+    RTC_COUNT_PERIODIC_INTERVAL_6 = 6,
+    /** Periodic interval 7 */
+    RTC_COUNT_PERIODIC_INTERVAL_7 = 7,
 };
 #endif
 
@@ -500,55 +502,55 @@ enum rtc_count_periodic_interval{
  * The available callback types for the RTC count module.
  */
 enum rtc_count_callback {
-	/** Callback for Periodic Interval 0 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0 = 0,
-	/** Callback for Periodic Interval 1 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_1,
-	/** Callback for Periodic Interval 2 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_2,
-	/** Callback for Periodic Interval 3 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_3,
-	/** Callback for Periodic Interval 4 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_4,
-	/** Callback for Periodic Interval 5 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_5,
-	/** Callback for Periodic Interval 6 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_6,
-	/** Callback for Periodic Interval 7 Interrupt */
-	RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7,
-	/** Callback for compare channel 0 */
-	RTC_COUNT_CALLBACK_COMPARE_0,
+    /** Callback for Periodic Interval 0 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0 = 0,
+    /** Callback for Periodic Interval 1 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_1,
+    /** Callback for Periodic Interval 2 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_2,
+    /** Callback for Periodic Interval 3 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_3,
+    /** Callback for Periodic Interval 4 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_4,
+    /** Callback for Periodic Interval 5 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_5,
+    /** Callback for Periodic Interval 6 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_6,
+    /** Callback for Periodic Interval 7 Interrupt */
+    RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7,
+    /** Callback for compare channel 0 */
+    RTC_COUNT_CALLBACK_COMPARE_0,
 #  if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
-	/** Callback for compare channel 1 */
-	RTC_COUNT_CALLBACK_COMPARE_1,
+    /** Callback for compare channel 1 */
+    RTC_COUNT_CALLBACK_COMPARE_1,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
-	/** Callback for compare channel 2 */
-	RTC_COUNT_CALLBACK_COMPARE_2,
+    /** Callback for compare channel 2 */
+    RTC_COUNT_CALLBACK_COMPARE_2,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
-	/** Callback for compare channel 3 */
-	RTC_COUNT_CALLBACK_COMPARE_3,
+    /** Callback for compare channel 3 */
+    RTC_COUNT_CALLBACK_COMPARE_3,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
-	/** Callback for compare channel 4 */
-	RTC_COUNT_CALLBACK_COMPARE_4,
+    /** Callback for compare channel 4 */
+    RTC_COUNT_CALLBACK_COMPARE_4,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
-	/** Callback for compare channel 5 */
-	RTC_COUNT_CALLBACK_COMPARE_5,
+    /** Callback for compare channel 5 */
+    RTC_COUNT_CALLBACK_COMPARE_5,
 #  endif
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Callback for tamper */
-	RTC_COUNT_CALLBACK_TAMPER,
+    /** Callback for tamper */
+    RTC_COUNT_CALLBACK_TAMPER,
 #endif
 
-	/** Callback for overflow */
-	RTC_COUNT_CALLBACK_OVERFLOW,
+    /** Callback for overflow */
+    RTC_COUNT_CALLBACK_OVERFLOW,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_RTC_COUNT_CALLBACK_N
+    /** Total number of callbacks */
+    _RTC_COUNT_CALLBACK_N
 #  endif
 };
 #else
@@ -558,39 +560,39 @@ enum rtc_count_callback {
  * The available callback types for the RTC count module.
  */
 enum rtc_count_callback {
-	/** Callback for compare channel 0 */
-	RTC_COUNT_CALLBACK_COMPARE_0 = 0,
+    /** Callback for compare channel 0 */
+    RTC_COUNT_CALLBACK_COMPARE_0 = 0,
 #  if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
-	/** Callback for compare channel 1 */
-	RTC_COUNT_CALLBACK_COMPARE_1,
+    /** Callback for compare channel 1 */
+    RTC_COUNT_CALLBACK_COMPARE_1,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
-	/** Callback for compare channel 2 */
-	RTC_COUNT_CALLBACK_COMPARE_2,
+    /** Callback for compare channel 2 */
+    RTC_COUNT_CALLBACK_COMPARE_2,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
-	/** Callback for compare channel 3 */
-	RTC_COUNT_CALLBACK_COMPARE_3,
+    /** Callback for compare channel 3 */
+    RTC_COUNT_CALLBACK_COMPARE_3,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
-	/** Callback for compare channel 4 */
-	RTC_COUNT_CALLBACK_COMPARE_4,
+    /** Callback for compare channel 4 */
+    RTC_COUNT_CALLBACK_COMPARE_4,
 #  endif
 #  if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
-	/** Callback for compare channel 5 */
-	RTC_COUNT_CALLBACK_COMPARE_5,
+    /** Callback for compare channel 5 */
+    RTC_COUNT_CALLBACK_COMPARE_5,
 #  endif
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Callback for tamper */
-	RTC_COUNT_CALLBACK_TAMPER,
+    /** Callback for tamper */
+    RTC_COUNT_CALLBACK_TAMPER,
 #endif
 
-	/** Callback for overflow */
-	RTC_COUNT_CALLBACK_OVERFLOW,
+    /** Callback for overflow */
+    RTC_COUNT_CALLBACK_OVERFLOW,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_RTC_COUNT_CALLBACK_N
+    /** Total number of callbacks */
+    _RTC_COUNT_CALLBACK_N
 #  endif
 };
 #endif
@@ -607,31 +609,31 @@ typedef void (*rtc_count_callback_t)(void);
  * The available input clock prescaler values for the RTC count module.
  */
 enum rtc_count_prescaler {
-	/** RTC prescaler is off, and the input clock frequency is
-	prescaled by a factor of 1 */
-	RTC_COUNT_PRESCALER_OFF      = RTC_MODE0_CTRLA_PRESCALER_OFF,
-	/** RTC input clock frequency is prescaled by a factor of 1 */
-	RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRLA_PRESCALER_DIV1,
-	/** RTC input clock frequency is prescaled by a factor of 2 */
-	RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRLA_PRESCALER_DIV2,
-	/** RTC input clock frequency is prescaled by a factor of 4 */
-	RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRLA_PRESCALER_DIV4,
-	/** RTC input clock frequency is prescaled by a factor of 8 */
-	RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRLA_PRESCALER_DIV8,
-	/** RTC input clock frequency is prescaled by a factor of 16 */
-	RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRLA_PRESCALER_DIV16,
-	/** RTC input clock frequency is prescaled by a factor of 32 */
-	RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRLA_PRESCALER_DIV32,
-	/** RTC input clock frequency is prescaled by a factor of 64 */
-	RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRLA_PRESCALER_DIV64,
-	/** RTC input clock frequency is prescaled by a factor of 128 */
-	RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRLA_PRESCALER_DIV128,
-	/** RTC input clock frequency is prescaled by a factor of 256 */
-	RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRLA_PRESCALER_DIV256,
-	/** RTC input clock frequency is prescaled by a factor of 512 */
-	RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRLA_PRESCALER_DIV512,
-	/** RTC input clock frequency is prescaled by a factor of 1024 */
-	RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRLA_PRESCALER_DIV1024,
+    /** RTC prescaler is off, and the input clock frequency is
+    prescaled by a factor of 1 */
+    RTC_COUNT_PRESCALER_OFF      = RTC_MODE0_CTRLA_PRESCALER_OFF,
+    /** RTC input clock frequency is prescaled by a factor of 1 */
+    RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRLA_PRESCALER_DIV1,
+    /** RTC input clock frequency is prescaled by a factor of 2 */
+    RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRLA_PRESCALER_DIV2,
+    /** RTC input clock frequency is prescaled by a factor of 4 */
+    RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRLA_PRESCALER_DIV4,
+    /** RTC input clock frequency is prescaled by a factor of 8 */
+    RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRLA_PRESCALER_DIV8,
+    /** RTC input clock frequency is prescaled by a factor of 16 */
+    RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRLA_PRESCALER_DIV16,
+    /** RTC input clock frequency is prescaled by a factor of 32 */
+    RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRLA_PRESCALER_DIV32,
+    /** RTC input clock frequency is prescaled by a factor of 64 */
+    RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRLA_PRESCALER_DIV64,
+    /** RTC input clock frequency is prescaled by a factor of 128 */
+    RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRLA_PRESCALER_DIV128,
+    /** RTC input clock frequency is prescaled by a factor of 256 */
+    RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRLA_PRESCALER_DIV256,
+    /** RTC input clock frequency is prescaled by a factor of 512 */
+    RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRLA_PRESCALER_DIV512,
+    /** RTC input clock frequency is prescaled by a factor of 1024 */
+    RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRLA_PRESCALER_DIV1024,
 };
 #else
 /**
@@ -640,28 +642,28 @@ enum rtc_count_prescaler {
  * The available input clock prescaler values for the RTC count module.
  */
 enum rtc_count_prescaler {
-	/** RTC input clock frequency is prescaled by a factor of 1 */
-	RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRL_PRESCALER_DIV1,
-	/** RTC input clock frequency is prescaled by a factor of 2 */
-	RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRL_PRESCALER_DIV2,
-	/** RTC input clock frequency is prescaled by a factor of 4 */
-	RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRL_PRESCALER_DIV4,
-	/** RTC input clock frequency is prescaled by a factor of 8 */
-	RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRL_PRESCALER_DIV8,
-	/** RTC input clock frequency is prescaled by a factor of 16 */
-	RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRL_PRESCALER_DIV16,
-	/** RTC input clock frequency is prescaled by a factor of 32 */
-	RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRL_PRESCALER_DIV32,
-	/** RTC input clock frequency is prescaled by a factor of 64 */
-	RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRL_PRESCALER_DIV64,
-	/** RTC input clock frequency is prescaled by a factor of 128 */
-	RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRL_PRESCALER_DIV128,
-	/** RTC input clock frequency is prescaled by a factor of 256 */
-	RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRL_PRESCALER_DIV256,
-	/** RTC input clock frequency is prescaled by a factor of 512 */
-	RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRL_PRESCALER_DIV512,
-	/** RTC input clock frequency is prescaled by a factor of 1024 */
-	RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024,
+    /** RTC input clock frequency is prescaled by a factor of 1 */
+    RTC_COUNT_PRESCALER_DIV_1    = RTC_MODE0_CTRL_PRESCALER_DIV1,
+    /** RTC input clock frequency is prescaled by a factor of 2 */
+    RTC_COUNT_PRESCALER_DIV_2    = RTC_MODE0_CTRL_PRESCALER_DIV2,
+    /** RTC input clock frequency is prescaled by a factor of 4 */
+    RTC_COUNT_PRESCALER_DIV_4    = RTC_MODE0_CTRL_PRESCALER_DIV4,
+    /** RTC input clock frequency is prescaled by a factor of 8 */
+    RTC_COUNT_PRESCALER_DIV_8    = RTC_MODE0_CTRL_PRESCALER_DIV8,
+    /** RTC input clock frequency is prescaled by a factor of 16 */
+    RTC_COUNT_PRESCALER_DIV_16   = RTC_MODE0_CTRL_PRESCALER_DIV16,
+    /** RTC input clock frequency is prescaled by a factor of 32 */
+    RTC_COUNT_PRESCALER_DIV_32   = RTC_MODE0_CTRL_PRESCALER_DIV32,
+    /** RTC input clock frequency is prescaled by a factor of 64 */
+    RTC_COUNT_PRESCALER_DIV_64   = RTC_MODE0_CTRL_PRESCALER_DIV64,
+    /** RTC input clock frequency is prescaled by a factor of 128 */
+    RTC_COUNT_PRESCALER_DIV_128  = RTC_MODE0_CTRL_PRESCALER_DIV128,
+    /** RTC input clock frequency is prescaled by a factor of 256 */
+    RTC_COUNT_PRESCALER_DIV_256  = RTC_MODE0_CTRL_PRESCALER_DIV256,
+    /** RTC input clock frequency is prescaled by a factor of 512 */
+    RTC_COUNT_PRESCALER_DIV_512  = RTC_MODE0_CTRL_PRESCALER_DIV512,
+    /** RTC input clock frequency is prescaled by a factor of 1024 */
+    RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024,
 };
 #endif
 
@@ -672,19 +674,19 @@ enum rtc_count_prescaler {
  * \ref rtc_count_disable_events().
  */
 struct rtc_count_events {
-	/** Generate an output event on each overflow of the RTC count */
-	bool generate_event_on_overflow;
-	/** Generate an output event on a compare channel match against the RTC
-	 *  count */
-	bool generate_event_on_compare[RTC_NUM_OF_COMP16];
-	/** Generate an output event periodically at a binary division of the RTC
-	 *  counter frequency */
-	bool generate_event_on_periodic[8];
+    /** Generate an output event on each overflow of the RTC count */
+    bool generate_event_on_overflow;
+    /** Generate an output event on a compare channel match against the RTC
+     *  count */
+    bool generate_event_on_compare[RTC_NUM_OF_COMP16];
+    /** Generate an output event periodically at a binary division of the RTC
+     *  counter frequency */
+    bool generate_event_on_periodic[8];
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/** Generate an output event on every tamper input */
-	bool generate_event_on_tamper;
-	/** Tamper input event and capture the COUNT value */
-	bool on_event_to_tamper;
+    /** Generate an output event on every tamper input */
+    bool generate_event_on_tamper;
+    /** Tamper input event and capture the COUNT value */
+    bool on_event_to_tamper;
 #endif
 };
 
@@ -693,21 +695,21 @@ struct rtc_count_events {
  * \brief Device structure.
  */
 struct rtc_module {
-	/** RTC hardware module */
-	Rtc *hw;
-	/** Operation mode of count */
-	enum rtc_count_mode mode;
+    /** RTC hardware module */
+    Rtc *hw;
+    /** Operation mode of count */
+    enum rtc_count_mode mode;
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	/** Set if counter value should be continuously updated */
-	bool continuously_update;
+    /** Set if counter value should be continuously updated */
+    bool continuously_update;
 #endif
 #  if RTC_COUNT_ASYNC == true
-	/** Pointers to callback functions */
-	volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint16_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint16_t enabled_callback;
+    /** Pointers to callback functions */
+    volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint16_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint16_t enabled_callback;
 #  endif
 };
 #endif
@@ -720,28 +722,28 @@ struct rtc_module {
  * user configurations are set.
  */
 struct rtc_count_config {
-	/** Input clock prescaler for the RTC module */
-	enum rtc_count_prescaler prescaler;
-	/** Select the operation mode of the RTC */
-	enum rtc_count_mode mode;
-	/** If true, clears the counter value on compare match. Only available
-	 *  whilst running in 32-bit mode */
-	bool clear_on_match;
+    /** Input clock prescaler for the RTC module */
+    enum rtc_count_prescaler prescaler;
+    /** Select the operation mode of the RTC */
+    enum rtc_count_mode mode;
+    /** If true, clears the counter value on compare match. Only available
+     *  whilst running in 32-bit mode */
+    bool clear_on_match;
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	/** Continuously update the counter value so no synchronization is
-	 *  needed for reading */
-	bool continuously_update;
+    /** Continuously update the counter value so no synchronization is
+     *  needed for reading */
+    bool continuously_update;
 #endif
 #if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Enable count read synchronization. The COUNT value requires
-	 * synchronization when reading. Disabling the synchronization
-	 * will prevent the COUNT value from displaying the current value. */
-	bool enable_read_sync;
+    /** Enable count read synchronization. The COUNT value requires
+     * synchronization when reading. Disabling the synchronization
+     * will prevent the COUNT value from displaying the current value. */
+    bool enable_read_sync;
 #endif
 
-	/** Array of Compare values. Not all Compare values are available in 32-bit
-	 *  mode */
-	uint32_t compare_values[RTC_NUM_OF_COMP16];
+    /** Array of Compare values. Not all Compare values are available in 32-bit
+     *  mode */
+    uint32_t compare_values[RTC_NUM_OF_COMP16];
 };
 
 
@@ -769,26 +771,27 @@ struct rtc_count_config {
  *                      values
  */
 static inline void rtc_count_get_config_defaults(
-		struct rtc_count_config *const config)
+        struct rtc_count_config *const config)
 {
-	/* Sanity check argument */
-	Assert(config);
+    /* Sanity check argument */
+    Assert(config);
 
-	/* Set default into configuration structure */
-	config->prescaler           = RTC_COUNT_PRESCALER_DIV_1024;
-	config->mode                = RTC_COUNT_MODE_32BIT;
-	config->clear_on_match      = false;
+    /* Set default into configuration structure */
+    config->prescaler           = RTC_COUNT_PRESCALER_DIV_1024;
+    config->mode                = RTC_COUNT_MODE_32BIT;
+    config->clear_on_match      = false;
 
 #ifdef FEATURE_RTC_CONTINUOUSLY_UPDATED
-	config->continuously_update = false;
+    config->continuously_update = false;
 #endif
 #if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	config->enable_read_sync    = true;
+    config->enable_read_sync    = true;
 #endif
 
-	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
-		config->compare_values[i] = 0;
-	}
+    for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++)
+    {
+        config->compare_values[i] = 0;
+    }
 }
 
 void rtc_count_reset(struct rtc_module *const module);
@@ -804,32 +807,34 @@ void rtc_count_disable(struct rtc_module *const module);
  * \return Index of the given AC module instance.
  */
 uint8_t _rtc_get_inst_index(
-		Rtc *const hw)
+        Rtc *const hw)
 {
-	/* List of available RTC modules */
-	static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
-
-	/* Find index for RTC instance */
-	for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
-		if (hw == rtc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given */
-	Assert(false);
-	return 0;
+    /* List of available RTC modules */
+    static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
+
+    /* Find index for RTC instance */
+    for (uint32_t i = 0; i < RTC_INST_NUM; i++)
+    {
+        if (hw == rtc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given */
+    Assert(false);
+    return 0;
 }
 #endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
 
 enum status_code rtc_count_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_count_config *const config);
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_count_config *const config);
 
 enum status_code rtc_count_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value);
+        struct rtc_module *const module,
+        const int8_t value);
 
 /** @} */
 
@@ -837,28 +842,28 @@ enum status_code rtc_count_frequency_correction(
  * @{
  */
 enum status_code rtc_count_set_count(
-		struct rtc_module *const module,
-		const uint32_t count_value);
+        struct rtc_module *const module,
+        const uint32_t count_value);
 
 uint32_t rtc_count_get_count(struct rtc_module *const module);
 
 enum status_code rtc_count_set_compare(
-		struct rtc_module *const module,
-		const uint32_t comp_value,
-		const enum rtc_count_compare comp_index);
+        struct rtc_module *const module,
+        const uint32_t comp_value,
+        const enum rtc_count_compare comp_index);
 
 enum status_code rtc_count_get_compare(
-		struct rtc_module *const module,
-		uint32_t *const comp_value,
-		const enum rtc_count_compare comp_index);
+        struct rtc_module *const module,
+        uint32_t *const comp_value,
+        const enum rtc_count_compare comp_index);
 
 enum status_code rtc_count_set_period(
-		struct rtc_module *const module,
-		uint16_t period_value);
+        struct rtc_module *const module,
+        uint16_t period_value);
 
 enum status_code rtc_count_get_period(
-		struct rtc_module *const module,
-		uint16_t *const period_value);
+        struct rtc_module *const module,
+        uint16_t *const period_value);
 
 /** @} */
 
@@ -883,14 +888,14 @@ enum status_code rtc_count_get_period(
 
 static inline bool rtc_count_is_overflow(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Return status of flag */
-	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF);
+    /* Return status of flag */
+    return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF);
 }
 
 /**
@@ -903,14 +908,14 @@ static inline bool rtc_count_is_overflow(struct rtc_module *const module)
  */
 static inline void rtc_count_clear_overflow(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Clear OVF flag */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+    /* Clear OVF flag */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
 }
 
 #ifdef FEATURE_RTC_PERIODIC_INT
@@ -928,16 +933,16 @@ static inline void rtc_count_clear_overflow(struct rtc_module *const module)
  * \retval false  RTC periodic interval interrupt doesn't occur
  */
 static inline bool rtc_count_is_periodic_interval(struct rtc_module *const module,
-										enum rtc_count_periodic_interval n)
+                                        enum rtc_count_periodic_interval n)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Return status of flag */
-	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER(1 << n));
+    /* Return status of flag */
+    return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER(1 << n));
 }
 
 /**
@@ -950,25 +955,25 @@ static inline bool rtc_count_is_periodic_interval(struct rtc_module *const modul
  * \param[in]  n  RTC periodic interval interrupt
  */
 static inline void rtc_count_clear_periodic_interval(struct rtc_module *const module,
-												enum rtc_count_periodic_interval n)
+                                                enum rtc_count_periodic_interval n)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Clear periodic interval flag */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER(1 << n);
+    /* Clear periodic interval flag */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER(1 << n);
 }
 #endif
 bool rtc_count_is_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index);
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index);
 
 enum status_code rtc_count_clear_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index);
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index);
 
 /** @} */
 
@@ -990,50 +995,57 @@ enum status_code rtc_count_clear_compare_match(
  *  \param[in] events    Struct containing flags of events to enable
  */
 static inline void rtc_count_enable_events(
-		struct rtc_module *const module,
-		struct rtc_count_events *const events)
+        struct rtc_module *const module,
+        struct rtc_count_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Check if the user has requested an overflow event */
-	if (events->generate_event_on_overflow) {
-		event_mask |= RTC_MODE0_EVCTRL_OVFEO;
-	}
-
-	/* Check if the user has requested any compare events */
-	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
-		if (events->generate_event_on_compare[i]) {
-			event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
-		}
-	}
-
-	/* Check if the user has requested any periodic events */
-	for (uint8_t i = 0; i < 8; i++) {
-		if (events->generate_event_on_periodic[i]) {
-			event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Check if the user has requested an overflow event */
+    if (events->generate_event_on_overflow)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+    }
+
+    /* Check if the user has requested any compare events */
+    for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++)
+    {
+        if (events->generate_event_on_compare[i])
+        {
+            event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+        }
+    }
+
+    /* Check if the user has requested any periodic events */
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if (events->generate_event_on_periodic[i])
+        {
+            event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+        }
+    }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/* Check if the user has requested a tamper event output. */
-	if (events->generate_event_on_tamper) {
-		event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
-	}
-
-	/* Check if the user has requested a tamper event input. */
-	if (events->on_event_to_tamper) {
-		event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
-	}
+    /* Check if the user has requested a tamper event output. */
+    if (events->generate_event_on_tamper)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
+    }
+
+    /* Check if the user has requested a tamper event input. */
+    if (events->on_event_to_tamper)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
+    }
 #endif
 
-	/* Enable given event(s). */
-	rtc_module->MODE0.EVCTRL.reg |= event_mask;
+    /* Enable given event(s). */
+    rtc_module->MODE0.EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -1048,50 +1060,57 @@ static inline void rtc_count_enable_events(
  *  \param[in] events    Struct containing flags of events to disable
  */
 static inline void rtc_count_disable_events(
-		struct rtc_module *const module,
-		struct rtc_count_events *const events)
+        struct rtc_module *const module,
+        struct rtc_count_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	uint32_t event_mask = 0;
-
-	/* Check if the user has requested an overflow event */
-	if (events->generate_event_on_overflow) {
-		event_mask |= RTC_MODE0_EVCTRL_OVFEO;
-	}
-
-	/* Check if the user has requested any compare events */
-	for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
-		if (events->generate_event_on_compare[i]) {
-			event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
-		}
-	}
-
-	/* Check if the user has requested any periodic events */
-	for (uint8_t i = 0; i < 8; i++) {
-		if (events->generate_event_on_periodic[i]) {
-			event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    uint32_t event_mask = 0;
+
+    /* Check if the user has requested an overflow event */
+    if (events->generate_event_on_overflow)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_OVFEO;
+    }
+
+    /* Check if the user has requested any compare events */
+    for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++)
+    {
+        if (events->generate_event_on_compare[i])
+        {
+            event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
+        }
+    }
+
+    /* Check if the user has requested any periodic events */
+    for (uint8_t i = 0; i < 8; i++)
+    {
+        if (events->generate_event_on_periodic[i])
+        {
+            event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
+        }
+    }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	/* Check if the user has requested a tamper event output. */
-	if (events->generate_event_on_tamper) {
-		event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
-	}
-
-	/* Check if the user has requested a tamper event input. */
-	if (events->on_event_to_tamper) {
-		event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
-	}
+    /* Check if the user has requested a tamper event output. */
+    if (events->generate_event_on_tamper)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_TAMPEREO;
+    }
+
+    /* Check if the user has requested a tamper event input. */
+    if (events->on_event_to_tamper)
+    {
+        event_mask |= RTC_MODE0_EVCTRL_TAMPEVEI;
+    }
 #endif
 
-	/* Disable given event(s). */
-	rtc_module->MODE0.EVCTRL.reg &= ~event_mask;
+    /* Disable given event(s). */
+    rtc_module->MODE0.EVCTRL.reg &= ~event_mask;
 }
 
 /** @} */
@@ -1111,18 +1130,18 @@ static inline void rtc_count_disable_events(
  *
  */
 static inline void rtc_write_general_purpose_reg(
-	struct rtc_module *const module,
-	const  uint8_t index,
-	uint32_t value)
+    struct rtc_module *const module,
+    const  uint8_t index,
+    uint32_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(index <= 3);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(index <= 3);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	rtc_module->MODE0.GP[index].reg = value;
+    rtc_module->MODE0.GP[index].reg = value;
 }
 
 /**
@@ -1134,17 +1153,17 @@ static inline void rtc_write_general_purpose_reg(
  * \return Value of general purpose register.
  */
 static inline uint32_t rtc_read_general_purpose_reg(
-	struct rtc_module *const module,
-	const  uint8_t index)
+    struct rtc_module *const module,
+    const  uint8_t index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(index <= 3);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(index <= 3);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	return rtc_module->MODE0.GP[index].reg;
+    return rtc_module->MODE0.GP[index].reg;
 }
 
 /** @} */
@@ -1177,22 +1196,22 @@ uint32_t rtc_tamper_get_stamp (struct rtc_module *const module);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</td>
- *		<th>Description</td>
- *	</tr>
- *	<tr>
- *		<td>RTC</td>
- *		<td>Real Time Counter</td>
- *	</tr>
- *	<tr>
- *		<td>PPM</td>
- *		<td>Part Per Million</td>
- *	</tr>
- *	<tr>
- *		<td>RC</td>
- *		<td>Resistor/Capacitor</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</td>
+ *      <th>Description</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RTC</td>
+ *      <td>Real Time Counter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PPM</td>
+ *      <td>Part Per Million</td>
+ *  </tr>
+ *  <tr>
+ *      <td>RC</td>
+ *      <td>Resistor/Capacitor</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1213,36 +1232,36 @@ uint32_t rtc_tamper_get_stamp (struct rtc_module *const module);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added support for SAM C21</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for SAM L21/L22</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for SAM R30</td>
- *	</tr>
- *	<tr>
- *		<td>Added support for RTC tamper feature</td>
- *	</tr>
- *	<tr>
- *		<td>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for SAM C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for SAM L21/L22</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for SAM R30</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added support for RTC tamper feature</td>
+ *  </tr>
+ *  <tr>
+ *      <td>
  *          Added driver instance parameter to all API function calls, except
  *          get_config_defaults
  *      </td>
- *	</tr>
- *	<tr>
- *		<td>
- *			Updated initialization function to also enable the digital interface
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *          Updated initialization function to also enable the digital interface
  *          clock to the module if it is disabled
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1264,37 +1283,37 @@ uint32_t rtc_tamper_get_stamp (struct rtc_module *const module);
  * \page asfdoc_sam0_rtc_count_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42111E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
- *	</tr>
- *	<tr>
- *		<td>42111D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42111C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42111B</td>
- *		<td>06/2013</td>
- *		<td>Added additional documentation on the event system. Corrected
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42111E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42111D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42111C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42111B</td>
+ *      <td>06/2013</td>
+ *      <td>Added additional documentation on the event system. Corrected
  *          documentation typos.</td>
- *	</tr>
- *	<tr>
- *		<td>42111A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>42111A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h
index 02fdd5d7df19..0aeab6b0d910 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_count_interrupt.h
@@ -63,21 +63,21 @@ extern "C" {
  * @{
  */
 enum status_code rtc_count_register_callback(
-		struct rtc_module *const module,
-		rtc_count_callback_t callback,
-		enum rtc_count_callback callback_type);
+        struct rtc_module *const module,
+        rtc_count_callback_t callback,
+        enum rtc_count_callback callback_type);
 
 enum status_code rtc_count_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type);
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type);
 
 void rtc_count_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type);
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type);
 
 void rtc_count_disable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type);
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c
index a53bb3a3a24e..e66192445746 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar.c
@@ -68,13 +68,14 @@ struct rtc_module *_rtc_instance[RTC_INST_NUM];
  */
 static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-        if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+        if (rtc_module->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY)
+        {
                 return true;
         }
 
@@ -91,22 +92,23 @@ static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
  */
 void rtc_calendar_enable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_CALENDAR_ASYNC == true
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Enable RTC module. */
-	rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
+    /* Enable RTC module. */
+    rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE;
 }
 
 /**
@@ -118,27 +120,28 @@ void rtc_calendar_enable(struct rtc_module *const module)
  */
 void rtc_calendar_disable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_CALENDAR_ASYNC == true
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
+    /* Disbale interrupt */
+    rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
 
-	/* Disable RTC module. */
-	rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
+    /* Disable RTC module. */
+    rtc_module->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE;
 }
 
 /**
@@ -150,26 +153,27 @@ void rtc_calendar_disable(struct rtc_module *const module)
  */
 void rtc_calendar_reset(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable module before reset. */
-	rtc_calendar_disable(module);
+    /* Disable module before reset. */
+    rtc_calendar_disable(module);
 
 #if RTC_CALENDAR_ASYNC == true
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Initiate software reset. */
-	rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST;
+    /* Initiate software reset. */
+    rtc_module->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST;
 }
 
 /**
@@ -182,38 +186,39 @@ void rtc_calendar_reset(struct rtc_module *const module)
  * \return 32-bit value.
  */
 uint32_t rtc_calendar_time_to_register_value(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time)
 {
-	/* Initialize return value. */
-	uint32_t register_value;
+    /* Initialize return value. */
+    uint32_t register_value;
 
-	/* Set year value into register_value minus initial year. */
-	register_value = (time->year - module->year_init_value) <<
-			RTC_MODE2_CLOCK_YEAR_Pos;
+    /* Set year value into register_value minus initial year. */
+    register_value = (time->year - module->year_init_value) <<
+            RTC_MODE2_CLOCK_YEAR_Pos;
 
-	/* Set month value into register_value. */
-	register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
+    /* Set month value into register_value. */
+    register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
 
-	/* Set day value into register_value. */
-	register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
+    /* Set day value into register_value. */
+    register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
 
-	/* Set 24 hour value into register_value. */
-	register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
+    /* Set 24 hour value into register_value. */
+    register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
 
-	/* Check if 24 h clock and set pm flag. */
-	if (!(module->clock_24h) && (time->pm)) {
-		/* Set pm flag. */
-		register_value |= RTC_MODE2_CLOCK_HOUR_PM;
-	}
+    /* Check if 24 h clock and set pm flag. */
+    if (!(module->clock_24h) && (time->pm))
+    {
+        /* Set pm flag. */
+        register_value |= RTC_MODE2_CLOCK_HOUR_PM;
+    }
 
-	/* Set minute value into register_value. */
-	register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
+    /* Set minute value into register_value. */
+    register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
 
-	/* Set second value into register_value. */
-	register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
+    /* Set second value into register_value. */
+    register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
 
-	return register_value;
+    return register_value;
 }
 
 /**
@@ -225,43 +230,44 @@ uint32_t rtc_calendar_time_to_register_value(
  * \param[out] time  Pointer to the time structure
  */
 void rtc_calendar_register_value_to_time(
-		struct rtc_module *const module,
-		const uint32_t register_value,
-		struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const uint32_t register_value,
+        struct rtc_calendar_time *const time)
 {
-	/* Set year plus value of initial year. */
-	time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
-			RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
-
-	/* Set month value into time struct. */
-	time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
-			RTC_MODE2_CLOCK_MONTH_Pos);
-
-	/* Set day value into time struct. */
-	time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
-			RTC_MODE2_CLOCK_DAY_Pos);
-
-	if (module->clock_24h) {
-		/* Set hour in 24h mode. */
-		time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
-				RTC_MODE2_CLOCK_HOUR_Pos);
-	} else {
-		/* Set hour in 12h mode. */
-		time->hour = ((register_value &
-				(RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >>
-				RTC_MODE2_CLOCK_HOUR_Pos);
-
-		/* Set pm flag */
-		time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0);
-	}
-
-	/* Set minute value into time struct. */
-	time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
-			RTC_MODE2_CLOCK_MINUTE_Pos);
-
-	/* Set second value into time struct. */
-	time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
-			RTC_MODE2_CLOCK_SECOND_Pos);
+    /* Set year plus value of initial year. */
+    time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
+            RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
+
+    /* Set month value into time struct. */
+    time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
+            RTC_MODE2_CLOCK_MONTH_Pos);
+
+    /* Set day value into time struct. */
+    time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
+            RTC_MODE2_CLOCK_DAY_Pos);
+
+    if (module->clock_24h)
+    {
+        /* Set hour in 24h mode. */
+        time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
+                RTC_MODE2_CLOCK_HOUR_Pos);
+    } else {
+        /* Set hour in 12h mode. */
+        time->hour = ((register_value &
+                (RTC_MODE2_CLOCK_HOUR_Msk & ~RTC_MODE2_CLOCK_HOUR_PM)) >>
+                RTC_MODE2_CLOCK_HOUR_Pos);
+
+        /* Set pm flag */
+        time->pm = ((register_value & RTC_MODE2_CLOCK_HOUR_PM) != 0);
+    }
+
+    /* Set minute value into time struct. */
+    time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
+            RTC_MODE2_CLOCK_MINUTE_Pos);
+
+    /* Set second value into time struct. */
+    time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
+            RTC_MODE2_CLOCK_SECOND_Pos);
 }
 
 /**
@@ -274,46 +280,50 @@ void rtc_calendar_register_value_to_time(
  * \param[in] config  Pointer to the configuration structure.
  */
 static void _rtc_calendar_set_config(
-		struct rtc_module *const module,
-		const struct rtc_calendar_config *const config)
+        struct rtc_module *const module,
+        const struct rtc_calendar_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Set up temporary register value. */
-	uint16_t tmp_reg;
-
-	/* Set to calendar mode and set the prescaler. */
-	tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler;
-
-	/* Check clock mode. */
-	if (!(config->clock_24h)) {
-		/* Set clock mode 12h. */
-		tmp_reg |= RTC_MODE2_CTRL_CLKREP;
-	}
-
-	/* Check for clear on compare match. */
-	if (config->clear_on_match) {
-		/* Set clear on compare match. */
-		tmp_reg |= RTC_MODE2_CTRL_MATCHCLR;
-	}
-
-	/* Set temporary value to register. */
-	rtc_module->MODE2.CTRL.reg = tmp_reg;
-
-	/* Check to set continuously clock read update mode. */
-	if (config->continuously_update) {
-		/* Set continuously mode. */
-		rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT;
-	}
-
-	/* Set alarm time registers. */
-	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-		rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Set up temporary register value. */
+    uint16_t tmp_reg;
+
+    /* Set to calendar mode and set the prescaler. */
+    tmp_reg = RTC_MODE2_CTRL_MODE(2) | config->prescaler;
+
+    /* Check clock mode. */
+    if (!(config->clock_24h))
+    {
+        /* Set clock mode 12h. */
+        tmp_reg |= RTC_MODE2_CTRL_CLKREP;
+    }
+
+    /* Check for clear on compare match. */
+    if (config->clear_on_match)
+    {
+        /* Set clear on compare match. */
+        tmp_reg |= RTC_MODE2_CTRL_MATCHCLR;
+    }
+
+    /* Set temporary value to register. */
+    rtc_module->MODE2.CTRL.reg = tmp_reg;
+
+    /* Check to set continuously clock read update mode. */
+    if (config->continuously_update)
+    {
+        /* Set continuously mode. */
+        rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT;
+    }
+
+    /* Set alarm time registers. */
+    for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+    {
+        rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
+    }
 }
 
 /**
@@ -327,45 +337,45 @@ static void _rtc_calendar_set_config(
  * \param[in]   config  Pointer to the configuration structure
  */
 void rtc_calendar_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_calendar_config *const config)
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_calendar_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
 
-	/* Set up GCLK */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
-	system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(RTC_GCLK_ID);
+    /* Set up GCLK */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+    system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(RTC_GCLK_ID);
 
-	/* Reset module to hardware defaults. */
-	rtc_calendar_reset(module);
+    /* Reset module to hardware defaults. */
+    rtc_calendar_reset(module);
 
-	/* Save conf_struct internally for continued use. */
-	module->clock_24h           = config->clock_24h;
-	module->continuously_update = config->continuously_update;
-	module->year_init_value     = config->year_init_value;
+    /* Save conf_struct internally for continued use. */
+    module->clock_24h           = config->clock_24h;
+    module->continuously_update = config->continuously_update;
+    module->year_init_value     = config->year_init_value;
 
 #if (RTC_INST_NUM == 1)
-	_rtc_instance[0] = module;
+    _rtc_instance[0] = module;
 #else
-	/* Register this instance for callbacks*/
-	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+    /* Register this instance for callbacks*/
+    _rtc_instance[_rtc_get_inst_index(hw)] = module;
 #endif
 
-	/* Set config. */
-	_rtc_calendar_set_config(module, config);
+    /* Set config. */
+    _rtc_calendar_set_config(module, config);
 }
 
 /**
@@ -381,84 +391,93 @@ void rtc_calendar_init(
  */
 void rtc_calendar_swap_time_mode(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Initialize time structure. */
-	struct rtc_calendar_time time;
-	struct rtc_calendar_alarm_time alarm;
-
-	/* Get current time. */
-	rtc_calendar_get_time(module, &time);
-
-	/* Check current mode. */
-	if (module->clock_24h) {
-		/* Set pm flag. */
-		time.pm = (uint8_t)(time.hour / 12);
-
-		/* Set 12h clock hour value. */
-		time.hour = time.hour % 12;
-		if (time.hour == 0) {
-			time.hour = 12;
-		}
-
-		/* Update alarms */
-		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
-			alarm.time.hour = alarm.time.hour % 12;
-			if (alarm.time.hour == 0) {
-				alarm.time.hour = 12;
-			}
-			module->clock_24h = false;
-			rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			module->clock_24h = true;
-		}
-
-		/* Change value in configuration structure. */
-		module->clock_24h = false;
-	} else {
-		/* Set hour value based on pm flag. */
-		if (time.pm == 1) {
-			time.hour = time.hour + 12;
-
-			time.pm = 0;
-		} else if (time.hour == 12) {
-			time.hour = 0;
-		}
-
-		/* Update alarms */
-		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			if (alarm.time.pm == 1) {
-				alarm.time.hour = alarm.time.hour + 12;
-				alarm.time.pm = 0;
-				module->clock_24h = true;
-				rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-				module->clock_24h = false;
-			} else if (alarm.time.hour == 12) {
-				alarm.time.hour = 0;
-			}
-		}
-
-		/* Change value in configuration structure. */
-		module->clock_24h = true;
-	}
-
-	/* Disable RTC so new configuration can be set. */
-	rtc_calendar_disable(module);
-
-	/* Toggle mode. */
-	rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP;
-
-	/* Enable RTC. */
-	rtc_calendar_enable(module);
-
-	/* Set new time format in CLOCK register. */
-	rtc_calendar_set_time(module, &time);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Initialize time structure. */
+    struct rtc_calendar_time time;
+    struct rtc_calendar_alarm_time alarm;
+
+    /* Get current time. */
+    rtc_calendar_get_time(module, &time);
+
+    /* Check current mode. */
+    if (module->clock_24h)
+    {
+        /* Set pm flag. */
+        time.pm = (uint8_t)(time.hour / 12);
+
+        /* Set 12h clock hour value. */
+        time.hour = time.hour % 12;
+        if (time.hour == 0)
+        {
+            time.hour = 12;
+        }
+
+        /* Update alarms */
+        for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+        {
+            rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
+            alarm.time.hour = alarm.time.hour % 12;
+            if (alarm.time.hour == 0)
+            {
+                alarm.time.hour = 12;
+            }
+            module->clock_24h = false;
+            rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            module->clock_24h = true;
+        }
+
+        /* Change value in configuration structure. */
+        module->clock_24h = false;
+    } else {
+        /* Set hour value based on pm flag. */
+        if (time.pm == 1)
+        {
+            time.hour = time.hour + 12;
+
+            time.pm = 0;
+        } else if (time.hour == 12)
+        {
+            time.hour = 0;
+        }
+
+        /* Update alarms */
+        for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+        {
+            rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            if (alarm.time.pm == 1)
+            {
+                alarm.time.hour = alarm.time.hour + 12;
+                alarm.time.pm = 0;
+                module->clock_24h = true;
+                rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+                module->clock_24h = false;
+            } else if (alarm.time.hour == 12)
+            {
+                alarm.time.hour = 0;
+            }
+        }
+
+        /* Change value in configuration structure. */
+        module->clock_24h = true;
+    }
+
+    /* Disable RTC so new configuration can be set. */
+    rtc_calendar_disable(module);
+
+    /* Toggle mode. */
+    rtc_module->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP;
+
+    /* Enable RTC. */
+    rtc_calendar_enable(module);
+
+    /* Set new time format in CLOCK register. */
+    rtc_calendar_set_time(module, &time);
 }
 
 /**
@@ -470,23 +489,24 @@ void rtc_calendar_swap_time_mode(struct rtc_module *const module)
  * \param[in] time  The time to set in the calendar
  */
 void rtc_calendar_set_time(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
+    uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Write value to register. */
-	rtc_module->MODE2.CLOCK.reg = register_value;
+    /* Write value to register. */
+    rtc_module->MODE2.CLOCK.reg = register_value;
 }
 
 /**
@@ -498,37 +518,41 @@ void rtc_calendar_set_time(
  * \param[out] time  Pointer to value that will be filled with current time
  */
 void rtc_calendar_get_time(
-		struct rtc_module *const module,
-		struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        struct rtc_calendar_time *const time)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Change of read method based on value of continuously_update value in
-	 * the configuration structure. */
-	if (!(module->continuously_update)) {
-		/* Request read on CLOCK register. */
-		rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ;
-
-		while (rtc_calendar_is_syncing(module)) {
-			/* Wait for synchronization */
-		}
-	} else if (!(rtc_module->MODE2.READREQ.reg & RTC_READREQ_RCONT)){
-		rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
-		 /* wait that the first Read request finishes */
-		while (rtc_calendar_is_syncing(module)) {
-			/* Wait for synchronization */
-		}
-	}
-
-	/* Read value. */
-	uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
-
-	/* Convert value to time structure. */
-	rtc_calendar_register_value_to_time(module, register_value, time);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Change of read method based on value of continuously_update value in
+     * the configuration structure. */
+    if (!(module->continuously_update))
+    {
+        /* Request read on CLOCK register. */
+        rtc_module->MODE2.READREQ.reg = RTC_READREQ_RREQ;
+
+        while (rtc_calendar_is_syncing(module))
+        {
+            /* Wait for synchronization */
+        }
+    } else if (!(rtc_module->MODE2.READREQ.reg & RTC_READREQ_RCONT))
+    {
+        rtc_module->MODE2.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
+         /* wait that the first Read request finishes */
+        while (rtc_calendar_is_syncing(module))
+        {
+            /* Wait for synchronization */
+        }
+    }
+
+    /* Read value. */
+    uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
+
+    /* Convert value to time structure. */
+    rtc_calendar_register_value_to_time(module, register_value, time);
 }
 
 /**
@@ -545,35 +569,37 @@ void rtc_calendar_get_time(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_set_alarm(
-		struct rtc_module *const module,
-		const struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        const struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check. */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check. */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Get register_value from time. */
-	uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
+    /* Get register_value from time. */
+    uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set alarm value. */
-	rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
+    /* Set alarm value. */
+    rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
 
-	/* Set alarm mask */
-	rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
+    /* Set alarm mask */
+    rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -591,32 +617,33 @@ enum status_code rtc_calendar_set_alarm(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_get_alarm(
-		struct rtc_module *const module,
-		struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check. */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check. */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Read alarm value. */
-	uint32_t register_value =
-			rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
+    /* Read alarm value. */
+    uint32_t register_value =
+            rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
 
-	/* Convert to time structure. */
-	rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
+    /* Convert to time structure. */
+    rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
 
-	/* Read alarm mask */
-	alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
+    /* Read alarm mask */
+    alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -640,37 +667,40 @@ enum status_code rtc_calendar_get_alarm(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value)
+        struct rtc_module *const module,
+        const int8_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check if valid argument. */
-	if (abs(value) > 0x7F) {
-		/* Value bigger than allowed, return invalid argument. */
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if valid argument. */
+    if (abs(value) > 0x7F)
+    {
+        /* Value bigger than allowed, return invalid argument. */
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	uint32_t new_correction_value;
+    uint32_t new_correction_value;
 
-	/* Load the new correction value as a positive value, sign added later */
-	new_correction_value = abs(value);
+    /* Load the new correction value as a positive value, sign added later */
+    new_correction_value = abs(value);
 
-	/* Convert to positive value and adjust register sign bit. */
-	if (value < 0) {
-		new_correction_value |= RTC_FREQCORR_SIGN;
-	}
+    /* Convert to positive value and adjust register sign bit. */
+    if (value < 0)
+    {
+        new_correction_value |= RTC_FREQCORR_SIGN;
+    }
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set value. */
-	rtc_module->MODE2.FREQCORR.reg = new_correction_value;
+    /* Set value. */
+    rtc_module->MODE2.FREQCORR.reg = new_correction_value;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c
index 9664f597732b..6c22ca804c7f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_calendar_interrupt.c
@@ -65,29 +65,32 @@ extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
  * \retval STATUS_ERR_INVALID_ARG If trying to register, a callback is not available
  */
 enum status_code rtc_calendar_register_callback(
-		struct rtc_module *const module,
-		rtc_calendar_callback_t callback,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        rtc_calendar_callback_t callback,
+        enum rtc_calendar_callback callback_type)
 {
 
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		status = STATUS_OK;
-	} else if (callback_type > RTC_NUM_OF_ALARMS) {
-		/* Make sure alarm callback can be registered */
-		status = STATUS_ERR_INVALID_ARG;
-	}
+    /* Overflow callback */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        status = STATUS_OK;
+    } else if (callback_type > RTC_NUM_OF_ALARMS)
+    {
+        /* Make sure alarm callback can be registered */
+        status = STATUS_ERR_INVALID_ARG;
+    }
 
-	if (status == STATUS_OK) {
-		/* Register callback */
-		module->callbacks[callback_type] = callback;
-		/* Set corresponding bit to set callback as registered */
-		module->registered_callback |= (1 << callback_type);
-	}
+    if (status == STATUS_OK)
+    {
+        /* Register callback */
+        module->callbacks[callback_type] = callback;
+        /* Set corresponding bit to set callback as registered */
+        module->registered_callback |= (1 << callback_type);
+    }
 
-	return status;
+    return status;
 }
 
 /**
@@ -104,27 +107,30 @@ enum status_code rtc_calendar_register_callback(
  * \retval STATUS_ERR_INVALID_ARG If trying to unregister, a callback is not available
  */
 enum status_code rtc_calendar_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		status = STATUS_OK;
-	} else if (callback_type > RTC_NUM_OF_ALARMS) {
-		/* Make sure alarm callback can be unregistered */
-		status = STATUS_ERR_INVALID_ARG;
-	}
+    /* Overflow callback */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        status = STATUS_OK;
+    } else if (callback_type > RTC_NUM_OF_ALARMS)
+    {
+        /* Make sure alarm callback can be unregistered */
+        status = STATUS_ERR_INVALID_ARG;
+    }
 
-	if (status == STATUS_OK) {
-		/* Unregister callback */
-		module->callbacks[callback_type] = NULL;
+    if (status == STATUS_OK)
+    {
+        /* Unregister callback */
+        module->callbacks[callback_type] = NULL;
 
-		/* Clear corresponding bit to set callback as unregistered */
-		module->registered_callback &= ~(1 << callback_type);
-	}
-	return status;
+        /* Clear corresponding bit to set callback as unregistered */
+        module->registered_callback &= ~(1 << callback_type);
+    }
+    return status;
 }
 
 /**
@@ -136,22 +142,23 @@ enum status_code rtc_calendar_unregister_callback(
  * \param[in]     callback_type Callback type to enable
  */
 void rtc_calendar_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
-	} else {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
-	}
-	/* Mark callback as enabled. */
-	module->enabled_callback |= (1 << callback_type);
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
+    } else {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
+    }
+    /* Mark callback as enabled. */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -163,24 +170,25 @@ void rtc_calendar_enable_callback(
  * \param[in]     callback_type Callback type to disable
  */
 void rtc_calendar_disable_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable interrupt */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
-	} else {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
-	}
+    /* Disable interrupt */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
+    } else {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << callback_type);
+    }
 
-	/* Mark callback as disabled. */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled. */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -190,65 +198,75 @@ void rtc_calendar_disable_callback(
  */
 static void _rtc_interrupt_handler(const uint32_t instance_index)
 {
-	struct rtc_module *module = _rtc_instance[instance_index];
+    struct rtc_module *module = _rtc_instance[instance_index];
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Combine callback registered and enabled masks */
-	uint16_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
+    /* Combine callback registered and enabled masks */
+    uint16_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
 
-	/* Read and mask interrupt flag register */
-	uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
-	interrupt_status &= rtc_module->MODE2.INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
+    interrupt_status &= rtc_module->MODE2.INTENSET.reg;
 
-	if (interrupt_status & RTC_MODE2_INTFLAG_OVF) {
-		/* Overflow interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
-		}
+    if (interrupt_status & RTC_MODE2_INTFLAG_OVF)
+    {
+        /* Overflow interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
+        }
 
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0)) {
-		/* Alarm 0 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0))
+    {
+        /* Alarm 0 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1)) {
-		#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
-		/* Alarm 1 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
-		#endif
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1))
+    {
+        #if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+        /* Alarm 1 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2)) {
-		#if (RTC_NUM_OF_ALARMS > 2)	|| defined(__DOXYGEN__)
-		/* Alarm 2 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
-		#endif
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2))
+    {
+        #if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+        /* Alarm 2 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3)) {
-		#if (RTC_NUM_OF_ALARMS > 3)	|| defined(__DOXYGEN__)
-		/* Alarm 3 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
-		#endif
-	}
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3))
+    {
+        #if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+        /* Alarm 3 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
+        #endif
+    }
 }
 
 /**
@@ -257,14 +275,14 @@ static void _rtc_interrupt_handler(const uint32_t instance_index)
 #if (RTC_INST_NUM == 1)
 void RTC_Handler(void)
 {
-	_rtc_interrupt_handler(0);
+    _rtc_interrupt_handler(0);
 }
 #elif (RTC_INST_NUM > 1)
 #  define _RTC_INTERRUPT_HANDLER(n, unused) \
-		void RTC##n##_Handler(void) \
-		{ \
-			_rtc_interrupt_handler(n); \
-		}
+        void RTC##n##_Handler(void) \
+        { \
+            _rtc_interrupt_handler(n); \
+        }
 
 MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
-#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
+#endif /* (RTC_INST_NUM > 1) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c
index 044fcabe7ebd..4dc122956d9a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count.c
@@ -68,13 +68,14 @@ struct rtc_module *_rtc_instance[RTC_INST_NUM];
  */
 static bool rtc_count_is_syncing(struct rtc_module *const module)
 {
- 	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-        if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+        if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY)
+        {
                 return true;
         }
 
@@ -91,22 +92,23 @@ static bool rtc_count_is_syncing(struct rtc_module *const module)
  */
 void rtc_count_enable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_COUNT_ASYNC == true
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Enable RTC module. */
-	rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
+    /* Enable RTC module. */
+    rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
 }
 
 /**
@@ -118,27 +120,28 @@ void rtc_count_enable(struct rtc_module *const module)
  */
 void rtc_count_disable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_COUNT_ASYNC == true
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
+    /* Disbale interrupt */
+    rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
 
-	/* Disable RTC module. */
-	rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
+    /* Disable RTC module. */
+    rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
 }
 
 /**
@@ -149,26 +152,27 @@ void rtc_count_disable(struct rtc_module *const module)
  */
 void rtc_count_reset(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable module before reset. */
-	rtc_count_disable(module);
+    /* Disable module before reset. */
+    rtc_count_disable(module);
 
 #if RTC_COUNT_ASYNC == true
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Initiate software reset. */
-	rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
+    /* Initiate software reset. */
+    rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
 }
 
 /**
@@ -185,72 +189,80 @@ void rtc_count_reset(struct rtc_module *const module)
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given.
  */
 static enum status_code _rtc_count_set_config(
-		struct rtc_module *const module,
-		const struct rtc_count_config *const config)
+        struct rtc_module *const module,
+        const struct rtc_count_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler;
-
-	/* Set mode and clear on match if applicable. */
-	switch (config->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Set 32bit mode and clear on match if applicable. */
-			rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0);
-
-			/* Check if clear on compare match should be set. */
-			if (config->clear_on_match) {
-				/* Set clear on match. */
-				rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
-			}
-			/* Set compare values. */
-			for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) {
-				while (rtc_count_is_syncing(module)) {
-					/* Wait for synchronization */
-				}
-
-				rtc_count_set_compare(module, config->compare_values[i],
-						(enum rtc_count_compare)i);
-			}
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Set 16bit mode. */
-			rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1);
-
-			/* Check if match on clear is set, and return invalid
-			 * argument if set. */
-			if (config->clear_on_match) {
-				Assert(false);
-				return STATUS_ERR_INVALID_ARG;
-			}
-			/* Set compare values. */
-			for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
-				while (rtc_count_is_syncing(module)) {
-					/* Wait for synchronization */
-				}
-
-				rtc_count_set_compare(module, config->compare_values[i],
-						(enum rtc_count_compare)i);
-			}
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check to set continuously clock read update mode. */
-	if (config->continuously_update) {
-		/* Set continuously mode. */
-		rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
-	}
-
-	/* Return status OK if everything was configured. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler;
+
+    /* Set mode and clear on match if applicable. */
+    switch (config->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Set 32bit mode and clear on match if applicable. */
+            rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0);
+
+            /* Check if clear on compare match should be set. */
+            if (config->clear_on_match)
+            {
+                /* Set clear on match. */
+                rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
+            }
+            /* Set compare values. */
+            for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++)
+            {
+                while (rtc_count_is_syncing(module))
+                {
+                    /* Wait for synchronization */
+                }
+
+                rtc_count_set_compare(module, config->compare_values[i],
+                        (enum rtc_count_compare)i);
+            }
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Set 16bit mode. */
+            rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1);
+
+            /* Check if match on clear is set, and return invalid
+             * argument if set. */
+            if (config->clear_on_match)
+            {
+                Assert(false);
+                return STATUS_ERR_INVALID_ARG;
+            }
+            /* Set compare values. */
+            for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++)
+            {
+                while (rtc_count_is_syncing(module))
+                {
+                    /* Wait for synchronization */
+                }
+
+                rtc_count_set_compare(module, config->compare_values[i],
+                        (enum rtc_count_compare)i);
+            }
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check to set continuously clock read update mode. */
+    if (config->continuously_update)
+    {
+        /* Set continuously mode. */
+        rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
+    }
+
+    /* Return status OK if everything was configured. */
+    return STATUS_OK;
 }
 
 /**
@@ -268,44 +280,44 @@ static enum status_code _rtc_count_set_config(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
  */
 enum status_code rtc_count_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_count_config *const config)
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_count_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
 
-	/* Set up GCLK */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
-	system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(RTC_GCLK_ID);
+    /* Set up GCLK */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
+    system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(RTC_GCLK_ID);
 
-	/* Reset module to hardware defaults. */
-	rtc_count_reset(module);
+    /* Reset module to hardware defaults. */
+    rtc_count_reset(module);
 
-	/* Save conf_struct internally for continued use. */
-	module->mode                = config->mode;
-	module->continuously_update = config->continuously_update;
+    /* Save conf_struct internally for continued use. */
+    module->mode                = config->mode;
+    module->continuously_update = config->continuously_update;
 
 #  if (RTC_INST_NUM == 1)
-	_rtc_instance[0] = module;
+    _rtc_instance[0] = module;
 #  else
-	/* Register this instance for callbacks*/
-	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+    /* Register this instance for callbacks*/
+    _rtc_instance[_rtc_get_inst_index(hw)] = module;
 #  endif
 
-	/* Set config and return status. */
-	return _rtc_count_set_config(module, config);
+    /* Set config and return status. */
+    return _rtc_count_set_config(module, config);
 }
 
 /**
@@ -321,43 +333,46 @@ enum status_code rtc_count_init(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_count_set_count(
-		struct rtc_module *const module,
-		const uint32_t count_value)
+        struct rtc_module *const module,
+        const uint32_t count_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set count according to mode */
-	switch(module->mode){
-		case RTC_COUNT_MODE_32BIT:
-			/* Write value to register. */
-			rtc_module->MODE0.COUNT.reg = count_value;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check if 16-bit value is provided. */
-			if(count_value > 0xffff){
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Write value to register. */
-			rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set count according to mode */
+    switch(module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Write value to register. */
+            rtc_module->MODE0.COUNT.reg = count_value;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check if 16-bit value is provided. */
+            if(count_value > 0xffff)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Write value to register. */
+            rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -371,54 +386,59 @@ enum status_code rtc_count_set_count(
  */
 uint32_t rtc_count_get_count(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Initialize return value. */
-	uint32_t ret_val;
-
-	/* Change of read method based on value of continuously_update value in
-	 * the configuration structure. */
-	if(!(module->continuously_update)) {
-		/* Request read on count register. */
-		rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ;
-
-		while (rtc_count_is_syncing(module)) {
-			/* Wait for synchronization */
-		}
-	} else if (!(rtc_module->MODE0.READREQ.reg & RTC_READREQ_RCONT)){
-		rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
-		 /* wait that the first Read request finishes */
-		while (rtc_count_is_syncing(module)) {
-			/* Wait for synchronization */
-		}
-	}
-
-	/* Read value based on mode. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Return count value in 32-bit mode. */
-			ret_val = rtc_module->MODE0.COUNT.reg;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Return count value in 16-bit mode. */
-			ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
-
-			break;
-
-		default:
-			Assert(false);
-			/* Counter not initialized. Assume counter value 0.*/
-			ret_val = 0;
-			break;
-	}
-
-	return ret_val;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Initialize return value. */
+    uint32_t ret_val;
+
+    /* Change of read method based on value of continuously_update value in
+     * the configuration structure. */
+    if(!(module->continuously_update))
+    {
+        /* Request read on count register. */
+        rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ;
+
+        while (rtc_count_is_syncing(module))
+        {
+            /* Wait for synchronization */
+        }
+    } else if (!(rtc_module->MODE0.READREQ.reg & RTC_READREQ_RCONT))
+    {
+        rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT | RTC_READREQ_RREQ;
+         /* wait that the first Read request finishes */
+        while (rtc_count_is_syncing(module))
+        {
+            /* Wait for synchronization */
+        }
+    }
+
+    /* Read value based on mode. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Return count value in 32-bit mode. */
+            ret_val = rtc_module->MODE0.COUNT.reg;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Return count value in 16-bit mode. */
+            ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+
+            break;
+
+        default:
+            Assert(false);
+            /* Counter not initialized. Assume counter value 0.*/
+            ret_val = 0;
+            break;
+    }
+
+    return ret_val;
 }
 
 /**
@@ -438,57 +458,62 @@ uint32_t rtc_count_get_count(struct rtc_module *const module)
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_set_compare(
-		struct rtc_module *const module,
-		const uint32_t comp_value,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const uint32_t comp_value,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set compare values based on operation mode. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Set compare value for COMP. */
-			rtc_module->MODE0.COMP[comp_index].reg = comp_value;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Check that 16-bit value is provided. */
-			if (comp_value > 0xffff) {
-				Assert(false);
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Set compare value for COMP. */
-			rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Return status if everything is OK. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set compare values based on operation mode. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP32)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Set compare value for COMP. */
+            rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Check that 16-bit value is provided. */
+            if (comp_value > 0xffff)
+            {
+                Assert(false);
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Set compare value for COMP. */
+            rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Return status if everything is OK. */
+    return STATUS_OK;
 }
 
 /**
@@ -509,45 +534,48 @@ enum status_code rtc_count_set_compare(
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_get_compare(
-		struct rtc_module *const module,
-		uint32_t *const comp_value,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        uint32_t *const comp_value,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Get compare value for COMP. */
-			*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Get compare value for COMP. */
-			*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-	/* Return status showing everything is OK. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP32)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Get compare value for COMP. */
+            *comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Get compare value for COMP. */
+            *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+    /* Return status showing everything is OK. */
+    return STATUS_OK;
 }
 
 /**
@@ -565,24 +593,25 @@ enum status_code rtc_count_get_compare(
  * \retval STATUS_ERR_UNSUPPORTED_DEV  If incorrect mode was set
  */
 enum status_code rtc_count_get_period(
-		struct rtc_module *const module,
-		uint16_t *const period_value)
+        struct rtc_module *const module,
+        uint16_t *const period_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check that correct mode is set. */
-	if (module->mode != RTC_COUNT_MODE_16BIT) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Check that correct mode is set. */
+    if (module->mode != RTC_COUNT_MODE_16BIT)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	/* Returns the value. */
-	*period_value = rtc_module->MODE1.PER.reg;
+    /* Returns the value. */
+    *period_value = rtc_module->MODE1.PER.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -600,28 +629,30 @@ enum status_code rtc_count_get_period(
  * \retval STATUS_ERR_UNSUPPORTED_DEV  If module is not operated in 16-bit mode
  */
 enum status_code rtc_count_set_period(
-		struct rtc_module *const module,
-		const uint16_t period_value)
+        struct rtc_module *const module,
+        const uint16_t period_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check that correct mode is set. */
-	if (module->mode != RTC_COUNT_MODE_16BIT) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Check that correct mode is set. */
+    if (module->mode != RTC_COUNT_MODE_16BIT)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Write value to register. */
-	rtc_module->MODE1.PER.reg = period_value;
+    /* Write value to register. */
+    rtc_module->MODE1.PER.reg = period_value;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -636,40 +667,43 @@ enum status_code rtc_count_set_period(
  * \param[in] comp_index  Index of compare to check current flag
  */
 bool rtc_count_is_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Check sanity. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP32) {
-				return false;
-			}
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP16) {
-				return false;
-			}
-
-			break;
-
-		default:
-			Assert(false);
-			return false;
-	}
-
-	/* Set status of INTFLAG as return argument. */
-	return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Check sanity. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP32)
+            {
+                return false;
+            }
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP16)
+            {
+                return false;
+            }
+
+            break;
+
+        default:
+            Assert(false);
+            return false;
+    }
+
+    /* Set status of INTFLAG as return argument. */
+    return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index)) ? true : false;
 }
 
 /**
@@ -689,42 +723,45 @@ bool rtc_count_is_compare_match(
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_clear_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Check sanity. */
-	switch (module->mode){
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP32) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Clear INTFLAG. */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Check sanity. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP32)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Clear INTFLAG. */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+    return STATUS_OK;
 }
 
 /**
@@ -747,38 +784,41 @@ enum status_code rtc_count_clear_compare_match(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_count_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value)
+        struct rtc_module *const module,
+        const int8_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check if valid argument. */
-	if (abs(value) > 0x7F) {
-		/* Value bigger than allowed, return invalid argument. */
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if valid argument. */
+    if (abs(value) > 0x7F)
+    {
+        /* Value bigger than allowed, return invalid argument. */
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	uint32_t new_correction_value;
+    uint32_t new_correction_value;
 
-	/* Load the new correction value as a positive value, sign added later */
-	new_correction_value = abs(value);
+    /* Load the new correction value as a positive value, sign added later */
+    new_correction_value = abs(value);
 
-	/* Convert to positive value and adjust register sign bit. */
-	if (value < 0) {
-		new_correction_value |= RTC_FREQCORR_SIGN;
-	}
+    /* Convert to positive value and adjust register sign bit. */
+    if (value < 0)
+    {
+        new_correction_value |= RTC_FREQCORR_SIGN;
+    }
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set value. */
-	rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+    /* Set value. */
+    rtc_module->MODE0.FREQCORR.reg = new_correction_value;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c
index 444008e1441a..0337ed11e4a2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count_interrupt.c
@@ -65,45 +65,50 @@ extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
  * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
  */
 enum status_code rtc_count_register_callback(
-		struct rtc_module *const module,
-		rtc_count_callback_t callback,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        rtc_count_callback_t callback,
+        enum rtc_count_callback callback_type)
 {
 
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		status = STATUS_OK;
-	} else {
-		/* Make sure callback type can be registered */
-		switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (callback_type > RTC_NUM_OF_COMP32) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
+    /* Overflow callback */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        status = STATUS_OK;
+    } else {
+        /* Make sure callback type can be registered */
+        switch (module->mode)
+        {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (callback_type > RTC_NUM_OF_COMP32)
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
 
-			break;
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (callback_type > RTC_NUM_OF_COMP16) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		default:
-			status = STATUS_ERR_INVALID_ARG;
-		}
-	}
+            break;
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (callback_type > RTC_NUM_OF_COMP16)
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        default:
+            status = STATUS_ERR_INVALID_ARG;
+        }
+    }
 
-	if (status == STATUS_OK) {
-		/* Register callback */
-		module->callbacks[callback_type] = callback;
-		/* Set corresponding bit to set callback as registered */
-		module->registered_callback |= (1 << callback_type);
-	}
+    if (status == STATUS_OK)
+    {
+        /* Register callback */
+        module->callbacks[callback_type] = callback;
+        /* Set corresponding bit to set callback as registered */
+        module->registered_callback |= (1 << callback_type);
+    }
 
-	return status;
+    return status;
 }
 
 /**
@@ -120,41 +125,46 @@ enum status_code rtc_count_register_callback(
  * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
  */
 enum status_code rtc_count_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		status = STATUS_OK;
-	} else {
-		/* Make sure callback type can be unregistered */
-		switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (callback_type > RTC_NUM_OF_COMP32) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (callback_type > RTC_NUM_OF_COMP16) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		default:
-			status = STATUS_ERR_INVALID_ARG;
-		}
-	}
-	if (status == STATUS_OK) {
-		/* Unregister callback */
-		module->callbacks[callback_type] = NULL;
+    /* Overflow callback */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        status = STATUS_OK;
+    } else {
+        /* Make sure callback type can be unregistered */
+        switch (module->mode)
+        {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (callback_type > RTC_NUM_OF_COMP32)
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (callback_type > RTC_NUM_OF_COMP16)
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        default:
+            status = STATUS_ERR_INVALID_ARG;
+        }
+    }
+    if (status == STATUS_OK)
+    {
+        /* Unregister callback */
+        module->callbacks[callback_type] = NULL;
 
-		/* Clear corresponding bit to set callback as unregistered */
-		module->registered_callback &= ~(1 << callback_type);
-	}
-	return status;
+        /* Clear corresponding bit to set callback as unregistered */
+        module->registered_callback &= ~(1 << callback_type);
+    }
+    return status;
 }
 
 /**
@@ -166,22 +176,23 @@ enum status_code rtc_count_unregister_callback(
  * \param[in]     callback_type Callback type to enable
  */
 void rtc_count_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
-	} else {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
-	}
-	/* Mark callback as enabled. */
-	module->enabled_callback |= (1 << callback_type);
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+    } else {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+    }
+    /* Mark callback as enabled. */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -193,24 +204,25 @@ void rtc_count_enable_callback(
  * \param[in]     callback_type Callback type to disable
  */
 void rtc_count_disable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable interrupt */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
-	} else {
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
-	}
+    /* Disable interrupt */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+    } else {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
+    }
 
-	/* Mark callback as disabled. */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled. */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -220,85 +232,99 @@ void rtc_count_disable_callback(
  */
 static void _rtc_interrupt_handler(const uint32_t instance_index)
 {
-	struct rtc_module *module = _rtc_instance[instance_index];
+    struct rtc_module *module = _rtc_instance[instance_index];
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Combine callback registered and enabled masks */
-	uint16_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
+    /* Combine callback registered and enabled masks */
+    uint16_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
 
-	/* Read and mask interrupt flag register */
-	uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
-	interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+    interrupt_status &= rtc_module->MODE0.INTENSET.reg;
 
-	if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
-		/* Overflow interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
-			module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
-		}
+    if (interrupt_status & RTC_MODE0_INTFLAG_OVF)
+    {
+        /* Overflow interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+        }
 
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
-		/* Compare 0 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0))
+    {
+        /* Compare 0 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
-		#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
-		/* Compare 1 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
-		#endif
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1))
+    {
+        #if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+        /* Compare 1 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
-		#if (RTC_NUM_OF_COMP16 > 2)	|| defined(__DOXYGEN__)
-		/* Compare 2 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
-		#endif
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2))
+    {
+        #if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+        /* Compare 2 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
-		#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
-		/* Compare 3 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
-		#endif
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3))
+    {
+        #if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+        /* Compare 3 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
-		#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
-		/* Compare 4 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
-		#endif
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4))
+    {
+        #if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+        /* Compare 4 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
-		#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
-		/* Compare 5 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
-		#endif
-	}
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5))
+    {
+        #if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+        /* Compare 5 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+        #endif
+    }
 }
 
 /**
@@ -307,14 +333,14 @@ static void _rtc_interrupt_handler(const uint32_t instance_index)
 #if (RTC_INST_NUM == 1)
 void RTC_Handler(void)
 {
-	_rtc_interrupt_handler(0);
+    _rtc_interrupt_handler(0);
 }
 #elif (RTC_INST_NUM > 1)
 #  define _RTC_INTERRUPT_HANDLER(n, unused) \
-		void RTC##n##_Handler(void) \
-		{ \
-			_rtc_interrupt_handler(n); \
-		}
+        void RTC##n##_Handler(void) \
+        { \
+            _rtc_interrupt_handler(n); \
+        }
 
 MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
-#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
+#endif /* (RTC_INST_NUM > 1) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c
index 884b24a0b70c..ee621b7b558c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar.c
@@ -74,17 +74,18 @@ struct rtc_module *_rtc_instance[RTC_INST_NUM];
  */
 static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (rtc_module->MODE2.SYNCBUSY.reg) {
-		return true;
-	}
+    if (rtc_module->MODE2.SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -97,26 +98,28 @@ static inline bool rtc_calendar_is_syncing(struct rtc_module *const module)
  */
 void rtc_calendar_enable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_CALENDAR_ASYNC == true
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Enable RTC module. */
-	rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
+    /* Enable RTC module. */
+    rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -128,31 +131,33 @@ void rtc_calendar_enable(struct rtc_module *const module)
  */
 void rtc_calendar_disable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_CALENDAR_ASYNC == true
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
+    /* Disbale interrupt */
+    rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_MASK;
 
-	/* Disable RTC module. */
-	rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
+    /* Disable RTC module. */
+    rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -164,30 +169,32 @@ void rtc_calendar_disable(struct rtc_module *const module)
  */
 void rtc_calendar_reset(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable module before reset. */
-	rtc_calendar_disable(module);
+    /* Disable module before reset. */
+    rtc_calendar_disable(module);
 
 #if RTC_CALENDAR_ASYNC == true
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
 #endif
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Initiate software reset. */
-	rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
+    /* Initiate software reset. */
+    rtc_module->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -200,38 +207,39 @@ void rtc_calendar_reset(struct rtc_module *const module)
  * \return 32-bit value.
  */
 uint32_t rtc_calendar_time_to_register_value(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time)
 {
-	/* Initialize return value. */
-	uint32_t register_value;
+    /* Initialize return value. */
+    uint32_t register_value;
 
-	/* Set year value into register_value minus initial year. */
-	register_value = (time->year - module->year_init_value) <<
-			RTC_MODE2_CLOCK_YEAR_Pos;
+    /* Set year value into register_value minus initial year. */
+    register_value = (time->year - module->year_init_value) <<
+            RTC_MODE2_CLOCK_YEAR_Pos;
 
-	/* Set month value into register_value. */
-	register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
+    /* Set month value into register_value. */
+    register_value |= (time->month << RTC_MODE2_CLOCK_MONTH_Pos);
 
-	/* Set day value into register_value. */
-	register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
+    /* Set day value into register_value. */
+    register_value |= (time->day << RTC_MODE2_CLOCK_DAY_Pos);
 
-	/* Set 24 hour value into register_value. */
-	register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
+    /* Set 24 hour value into register_value. */
+    register_value |= (time->hour << RTC_MODE2_CLOCK_HOUR_Pos);
 
-	/* Check if 24h clock and set pm flag. */
-	if (!(module->clock_24h) && (time->pm)) {
-		/* Set pm flag. */
-		register_value |= (0x10u << RTC_MODE2_CLOCK_HOUR_Pos);
-	}
+    /* Check if 24h clock and set pm flag. */
+    if (!(module->clock_24h) && (time->pm))
+    {
+        /* Set pm flag. */
+        register_value |= (0x10u << RTC_MODE2_CLOCK_HOUR_Pos);
+    }
 
-	/* Set minute value into register_value. */
-	register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
+    /* Set minute value into register_value. */
+    register_value |= (time->minute << RTC_MODE2_CLOCK_MINUTE_Pos);
 
-	/* Set second value into register_value. */
-	register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
+    /* Set second value into register_value. */
+    register_value |= (time->second << RTC_MODE2_CLOCK_SECOND_Pos);
 
-	return register_value;
+    return register_value;
 }
 
 /**
@@ -243,43 +251,44 @@ uint32_t rtc_calendar_time_to_register_value(
  * \param[out] time  Pointer to the time structure
  */
 void rtc_calendar_register_value_to_time(
-		struct rtc_module *const module,
-		const uint32_t register_value,
-		struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const uint32_t register_value,
+        struct rtc_calendar_time *const time)
 {
-	/* Set year plus value of initial year. */
-	time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
-			RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
-
-	/* Set month value into time struct. */
-	time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
-			RTC_MODE2_CLOCK_MONTH_Pos);
-
-	/* Set day value into time struct. */
-	time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
-			RTC_MODE2_CLOCK_DAY_Pos);
-
-	if (module->clock_24h) {
-		/* Set hour in 24h mode. */
-		time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
-				RTC_MODE2_CLOCK_HOUR_Pos);
-	} else {
-		/* Set hour in 12h mode. */
-		time->hour = ((register_value &
-				(RTC_MODE2_CLOCK_HOUR_Msk & ~(0x10u << RTC_MODE2_CLOCK_HOUR_Pos))) >>
-				RTC_MODE2_CLOCK_HOUR_Pos);
-
-		/* Set pm flag */
-		time->pm = ((register_value & (0x10u << RTC_MODE2_CLOCK_HOUR_Pos)) != 0);
-	}
-
-	/* Set minute value into time struct. */
-	time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
-			RTC_MODE2_CLOCK_MINUTE_Pos);
-
-	/* Set second value into time struct. */
-	time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
-			RTC_MODE2_CLOCK_SECOND_Pos);
+    /* Set year plus value of initial year. */
+    time->year = ((register_value & RTC_MODE2_CLOCK_YEAR_Msk) >>
+            RTC_MODE2_CLOCK_YEAR_Pos) + module->year_init_value;
+
+    /* Set month value into time struct. */
+    time->month = ((register_value & RTC_MODE2_CLOCK_MONTH_Msk) >>
+            RTC_MODE2_CLOCK_MONTH_Pos);
+
+    /* Set day value into time struct. */
+    time->day = ((register_value & RTC_MODE2_CLOCK_DAY_Msk) >>
+            RTC_MODE2_CLOCK_DAY_Pos);
+
+    if (module->clock_24h)
+    {
+        /* Set hour in 24h mode. */
+        time->hour = ((register_value & RTC_MODE2_CLOCK_HOUR_Msk) >>
+                RTC_MODE2_CLOCK_HOUR_Pos);
+    } else {
+        /* Set hour in 12h mode. */
+        time->hour = ((register_value &
+                (RTC_MODE2_CLOCK_HOUR_Msk & ~(0x10u << RTC_MODE2_CLOCK_HOUR_Pos))) >>
+                RTC_MODE2_CLOCK_HOUR_Pos);
+
+        /* Set pm flag */
+        time->pm = ((register_value & (0x10u << RTC_MODE2_CLOCK_HOUR_Pos)) != 0);
+    }
+
+    /* Set minute value into time struct. */
+    time->minute = ((register_value & RTC_MODE2_CLOCK_MINUTE_Msk) >>
+            RTC_MODE2_CLOCK_MINUTE_Pos);
+
+    /* Set second value into time struct. */
+    time->second = ((register_value & RTC_MODE2_CLOCK_SECOND_Msk) >>
+            RTC_MODE2_CLOCK_SECOND_Pos);
 }
 
 /**
@@ -292,46 +301,50 @@ void rtc_calendar_register_value_to_time(
  * \param[in] config  Pointer to the configuration structure
  */
 static void _rtc_calendar_set_config(
-		struct rtc_module *const module,
-		const struct rtc_calendar_config *const config)
+        struct rtc_module *const module,
+        const struct rtc_calendar_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Set up temporary register value. */
-	uint16_t tmp_reg;
+    /* Set up temporary register value. */
+    uint16_t tmp_reg;
 
-	/* Set to calendar mode and set the prescaler. */
-	tmp_reg = RTC_MODE2_CTRLA_MODE(2) | config->prescaler;
+    /* Set to calendar mode and set the prescaler. */
+    tmp_reg = RTC_MODE2_CTRLA_MODE(2) | config->prescaler;
 
 #if (SAML21XXXB) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	if(config->enable_read_sync) {
-		tmp_reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
-	}
+    if(config->enable_read_sync)
+    {
+        tmp_reg |= RTC_MODE2_CTRLA_CLOCKSYNC;
+    }
 #endif
 
-	/* Check clock mode. */
-	if (!(config->clock_24h)) {
-		/* Set clock mode 12h. */
-		tmp_reg |= RTC_MODE2_CTRLA_CLKREP;
-	}
-
-	/* Check for clear on compare match. */
-	if (config->clear_on_match) {
-		/* Set clear on compare match. */
-		tmp_reg |= RTC_MODE2_CTRLA_MATCHCLR;
-	}
-
-	/* Set temporary value to register. */
-	rtc_module->MODE2.CTRLA.reg = tmp_reg;
-
-	/* Set alarm time registers. */
-	for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-		rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
-	}
+    /* Check clock mode. */
+    if (!(config->clock_24h))
+    {
+        /* Set clock mode 12h. */
+        tmp_reg |= RTC_MODE2_CTRLA_CLKREP;
+    }
+
+    /* Check for clear on compare match. */
+    if (config->clear_on_match)
+    {
+        /* Set clear on compare match. */
+        tmp_reg |= RTC_MODE2_CTRLA_MATCHCLR;
+    }
+
+    /* Set temporary value to register. */
+    rtc_module->MODE2.CTRLA.reg = tmp_reg;
+
+    /* Set alarm time registers. */
+    for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+    {
+        rtc_calendar_set_alarm(module, &(config->alarm[i]), (enum rtc_calendar_alarm)i);
+    }
 }
 
 /**
@@ -345,40 +358,40 @@ static void _rtc_calendar_set_config(
  * \param[in]   config  Pointer to the configuration structure
  */
 void rtc_calendar_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_calendar_config *const config)
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_calendar_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
 
-	/* Select RTC clock */
-	OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
+    /* Select RTC clock */
+    OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
 
-	/* Reset module to hardware defaults. */
-	rtc_calendar_reset(module);
+    /* Reset module to hardware defaults. */
+    rtc_calendar_reset(module);
 
-	/* Save conf_struct internally for continued use. */
-	module->clock_24h           = config->clock_24h;
-	module->year_init_value     = config->year_init_value;
+    /* Save conf_struct internally for continued use. */
+    module->clock_24h           = config->clock_24h;
+    module->year_init_value     = config->year_init_value;
 
 #if (RTC_INST_NUM == 1)
-	_rtc_instance[0] = module;
+    _rtc_instance[0] = module;
 #else
-	/* Register this instance for callbacks*/
-	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+    /* Register this instance for callbacks*/
+    _rtc_instance[_rtc_get_inst_index(hw)] = module;
 #endif
 
-	/* Set config. */
-	_rtc_calendar_set_config(module, config);
+    /* Set config. */
+    _rtc_calendar_set_config(module, config);
 }
 
 /**
@@ -394,84 +407,93 @@ void rtc_calendar_init(
  */
 void rtc_calendar_swap_time_mode(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Initialize time structure. */
-	struct rtc_calendar_time time;
-	struct rtc_calendar_alarm_time alarm;
-
-	/* Get current time. */
-	rtc_calendar_get_time(module, &time);
-
-	/* Check current mode. */
-	if (module->clock_24h) {
-		/* Set pm flag. */
-		time.pm = (uint8_t)(time.hour / 12);
-
-		/* Set 12h clock hour value. */
-		time.hour = time.hour % 12;
-		if (time.hour == 0) {
-			time.hour = 12;
-		}
-
-		/* Update alarms */
-		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
-			alarm.time.hour = alarm.time.hour % 12;
-			if (alarm.time.hour == 0) {
-				alarm.time.hour = 12;
-			}
-			module->clock_24h = false;
-			rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			module->clock_24h = true;
-		}
-
-		/* Change value in configuration structure. */
-		module->clock_24h = false;
-	} else {
-		/* Set hour value based on pm flag. */
-		if (time.pm == 1) {
-			time.hour = time.hour + 12;
-
-			time.pm = 0;
-		} else if (time.hour == 12) {
-			time.hour = 0;
-		}
-
-		/* Update alarms */
-		for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++) {
-			rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-			if (alarm.time.pm == 1) {
-				alarm.time.hour = alarm.time.hour + 12;
-				alarm.time.pm = 0;
-				module->clock_24h = true;
-				rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
-				module->clock_24h = false;
-			} else if (alarm.time.hour == 12) {
-				alarm.time.hour = 0;
-			}
-		}
-
-		/* Change value in configuration structure. */
-		module->clock_24h = true;
-	}
-
-	/* Disable RTC so new configuration can be set. */
-	rtc_calendar_disable(module);
-
-	/* Toggle mode. */
-	rtc_module->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
-
-	/* Enable RTC. */
-	rtc_calendar_enable(module);
-
-	/* Set new time format in CLOCK register. */
-	rtc_calendar_set_time(module, &time);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Initialize time structure. */
+    struct rtc_calendar_time time;
+    struct rtc_calendar_alarm_time alarm;
+
+    /* Get current time. */
+    rtc_calendar_get_time(module, &time);
+
+    /* Check current mode. */
+    if (module->clock_24h)
+    {
+        /* Set pm flag. */
+        time.pm = (uint8_t)(time.hour / 12);
+
+        /* Set 12h clock hour value. */
+        time.hour = time.hour % 12;
+        if (time.hour == 0)
+        {
+            time.hour = 12;
+        }
+
+        /* Update alarms */
+        for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+        {
+            rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            alarm.time.pm = (uint8_t)(alarm.time.hour / 12);
+            alarm.time.hour = alarm.time.hour % 12;
+            if (alarm.time.hour == 0)
+            {
+                alarm.time.hour = 12;
+            }
+            module->clock_24h = false;
+            rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            module->clock_24h = true;
+        }
+
+        /* Change value in configuration structure. */
+        module->clock_24h = false;
+    } else {
+        /* Set hour value based on pm flag. */
+        if (time.pm == 1)
+        {
+            time.hour = time.hour + 12;
+
+            time.pm = 0;
+        } else if (time.hour == 12)
+        {
+            time.hour = 0;
+        }
+
+        /* Update alarms */
+        for (uint8_t i = 0; i < RTC_NUM_OF_ALARMS; i++)
+        {
+            rtc_calendar_get_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+            if (alarm.time.pm == 1)
+            {
+                alarm.time.hour = alarm.time.hour + 12;
+                alarm.time.pm = 0;
+                module->clock_24h = true;
+                rtc_calendar_set_alarm(module, &alarm, (enum rtc_calendar_alarm)i);
+                module->clock_24h = false;
+            } else if (alarm.time.hour == 12)
+            {
+                alarm.time.hour = 0;
+            }
+        }
+
+        /* Change value in configuration structure. */
+        module->clock_24h = true;
+    }
+
+    /* Disable RTC so new configuration can be set. */
+    rtc_calendar_disable(module);
+
+    /* Toggle mode. */
+    rtc_module->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP;
+
+    /* Enable RTC. */
+    rtc_calendar_enable(module);
+
+    /* Set new time format in CLOCK register. */
+    rtc_calendar_set_time(module, &time);
 }
 
 /**
@@ -483,27 +505,29 @@ void rtc_calendar_swap_time_mode(struct rtc_module *const module)
  * \param[in] time  The time to set in the calendar
  */
 void rtc_calendar_set_time(
-		struct rtc_module *const module,
-		const struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        const struct rtc_calendar_time *const time)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
+    uint32_t register_value = rtc_calendar_time_to_register_value(module, time);
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Write value to register. */
-	rtc_module->MODE2.CLOCK.reg = register_value;
+    /* Write value to register. */
+    rtc_module->MODE2.CLOCK.reg = register_value;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -515,24 +539,25 @@ void rtc_calendar_set_time(
  * \param[out] time  Pointer to value that will be filled with current time
  */
 void rtc_calendar_get_time(
-		struct rtc_module *const module,
-		struct rtc_calendar_time *const time)
+        struct rtc_module *const module,
+        struct rtc_calendar_time *const time)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Read value. */
-	uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
+    /* Read value. */
+    uint32_t register_value = rtc_module->MODE2.CLOCK.reg;
 
-	/* Convert value to time structure. */
-	rtc_calendar_register_value_to_time(module, register_value, time);
+    /* Convert value to time structure. */
+    rtc_calendar_register_value_to_time(module, register_value, time);
 }
 
 /**
@@ -549,43 +574,47 @@ void rtc_calendar_get_time(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_set_alarm(
-		struct rtc_module *const module,
-		const struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        const struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check. */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check. */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Get register_value from time. */
-	uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
+    /* Get register_value from time. */
+    uint32_t register_value = rtc_calendar_time_to_register_value(module, &(alarm->time));
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set alarm value. */
-	rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
+    /* Set alarm value. */
+    rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg = register_value;
 
-	while (rtc_calendar_is_syncing(module)) {
-			/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+            /* Wait for synchronization */
+    }
 
-	/* Set alarm mask */
-	rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
+    /* Set alarm mask */
+    rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg = alarm->mask;
 
-	while (rtc_calendar_is_syncing(module)) {
-			/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+            /* Wait for synchronization */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -603,32 +632,33 @@ enum status_code rtc_calendar_set_alarm(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_get_alarm(
-		struct rtc_module *const module,
-		struct rtc_calendar_alarm_time *const alarm,
-		const enum rtc_calendar_alarm alarm_index)
+        struct rtc_module *const module,
+        struct rtc_calendar_alarm_time *const alarm,
+        const enum rtc_calendar_alarm alarm_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Sanity check. */
-	if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check. */
+    if ((uint32_t)alarm_index > RTC_NUM_OF_ALARMS)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Read alarm value. */
-	uint32_t register_value =
-			rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
+    /* Read alarm value. */
+    uint32_t register_value =
+            rtc_module->MODE2.Mode2Alarm[alarm_index].ALARM.reg;
 
-	/* Convert to time structure. */
-	rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
+    /* Convert to time structure. */
+    rtc_calendar_register_value_to_time(module, register_value, &(alarm->time));
 
-	/* Read alarm mask */
-	alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
+    /* Read alarm mask */
+    alarm->mask = (enum rtc_calendar_alarm_mask)rtc_module->MODE2.Mode2Alarm[alarm_index].MASK.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -652,43 +682,47 @@ enum status_code rtc_calendar_get_alarm(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_calendar_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value)
+        struct rtc_module *const module,
+        const int8_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check if valid argument. */
-	if (abs(value) > 0x7F) {
-		/* Value bigger than allowed, return invalid argument. */
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if valid argument. */
+    if (abs(value) > 0x7F)
+    {
+        /* Value bigger than allowed, return invalid argument. */
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	uint32_t new_correction_value;
+    uint32_t new_correction_value;
 
-	/* Load the new correction value as a positive value, sign added later */
-	new_correction_value = abs(value);
+    /* Load the new correction value as a positive value, sign added later */
+    new_correction_value = abs(value);
 
-	/* Convert to positive value and adjust register sign bit. */
-	if (value < 0) {
-		new_correction_value |= RTC_FREQCORR_SIGN;
-	}
+    /* Convert to positive value and adjust register sign bit. */
+    if (value < 0)
+    {
+        new_correction_value |= RTC_FREQCORR_SIGN;
+    }
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set value. */
-	rtc_module->MODE2.FREQCORR.reg = new_correction_value;
+    /* Set value. */
+    rtc_module->MODE2.FREQCORR.reg = new_correction_value;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
@@ -707,92 +741,101 @@ enum status_code rtc_calendar_frequency_correction(
  * \note If tamper input configured as active layer protection, RTC prescaler
  *       output automatically enabled in the function.
  */
-enum status_code rtc_tamper_set_config ( 
-		struct rtc_module *const module,
-		struct rtc_tamper_config *const tamper_cfg)
+enum status_code rtc_tamper_set_config (
+        struct rtc_module *const module,
+        struct rtc_tamper_config *const tamper_cfg)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(tamper_cfg);
-
-	Rtc *const rtc_module = module->hw;
-	uint16_t ctrl_b = 0;
-
-	/* Configure enable backup and GP register reset on tamper or not. */
-	if(tamper_cfg->bkup_reset_on_tamper) {
-		rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
-	} else {
-		rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
-	}
-	
-	if (tamper_cfg->gp_reset_on_tamper) {
-		rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
-	} else {
-		rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
-	}
-
-	/* Configure tamper detection of frequency and debounce setting. */
-	ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
-	if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC) {
-		ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
-	} else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY) {
-		ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
-	}
-	if(tamper_cfg->dma_tamper_enable) {
-		ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
-	}
-	if (tamper_cfg->gp0_enable) {
-		ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
-	}
-
-	/* Configure tamper input. */
-	volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE2.TAMPCTRL);
-
-	struct rtc_tamper_input_config in_cfg;
-	for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++) {
-		in_cfg = tamper_cfg->in_cfg[tamper_id];
-
-		if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL) {
-			ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
-		}
-	
-		switch(tamper_id) {
-			case 0:
-				tamper_ctrl->bit.IN0ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
-				break;
-			case 1:
-				tamper_ctrl->bit.IN1ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
-				break;
-			case 2:
-				tamper_ctrl->bit.IN2ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
-				break;
-			case 3:
-				tamper_ctrl->bit.IN3ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
-				break;
-			case 4:
-				tamper_ctrl->bit.IN4ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
-				break;
-			default:
-				Assert(false);
-				break;
-		}
-	}
-
-	rtc_module->MODE2.CTRLB.reg = ctrl_b;
-
-	/* Return status OK if everything was configured. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(tamper_cfg);
+
+    Rtc *const rtc_module = module->hw;
+    uint16_t ctrl_b = 0;
+
+    /* Configure enable backup and GP register reset on tamper or not. */
+    if(tamper_cfg->bkup_reset_on_tamper)
+    {
+        rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+    } else {
+        rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+    }
+
+    if (tamper_cfg->gp_reset_on_tamper)
+    {
+        rtc_module->MODE2.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+    } else {
+        rtc_module->MODE2.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+    }
+
+    /* Configure tamper detection of frequency and debounce setting. */
+    ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
+    if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
+    } else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
+    }
+    if(tamper_cfg->dma_tamper_enable)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
+    }
+    if (tamper_cfg->gp0_enable)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
+    }
+
+    /* Configure tamper input. */
+    volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE2.TAMPCTRL);
+
+    struct rtc_tamper_input_config in_cfg;
+    for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++)
+    {
+        in_cfg = tamper_cfg->in_cfg[tamper_id];
+
+        if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL)
+        {
+            ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
+        }
+
+        switch(tamper_id)
+        {
+            case 0:
+                tamper_ctrl->bit.IN0ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
+                break;
+            case 1:
+                tamper_ctrl->bit.IN1ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
+                break;
+            case 2:
+                tamper_ctrl->bit.IN2ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
+                break;
+            case 3:
+                tamper_ctrl->bit.IN3ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
+                break;
+            case 4:
+                tamper_ctrl->bit.IN4ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
+                break;
+            default:
+                Assert(false);
+                break;
+        }
+    }
+
+    rtc_module->MODE2.CTRLB.reg = ctrl_b;
+
+    /* Return status OK if everything was configured. */
+    return STATUS_OK;
 }
 
 /**
@@ -802,23 +845,24 @@ enum status_code rtc_tamper_set_config (
  * \param[out] time  Pointer to value that filled with tamper stamp time
  */
 void rtc_tamper_get_stamp (struct rtc_module *const module,
-		struct rtc_calendar_time *const time)
+        struct rtc_calendar_time *const time)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	while (rtc_calendar_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_calendar_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Initialize return value. */
-	uint32_t tamper_stamp = rtc_module->MODE2.TIMESTAMP.reg;
+    /* Initialize return value. */
+    uint32_t tamper_stamp = rtc_module->MODE2.TIMESTAMP.reg;
 
-	/* Convert value to time structure. */
-	rtc_calendar_register_value_to_time(module, tamper_stamp, time);
+    /* Convert value to time structure. */
+    rtc_calendar_register_value_to_time(module, tamper_stamp, time);
 }
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c
index a00604ffa6ff..f42d42c5eef6 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_calendar_interrupt.c
@@ -65,34 +65,37 @@ extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
  * \retval STATUS_ERR_INVALID_ARG If trying to register, a callback is not available
  */
 enum status_code rtc_calendar_register_callback(
-		struct rtc_module *const module,
-		rtc_calendar_callback_t callback,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        rtc_calendar_callback_t callback,
+        enum rtc_calendar_callback callback_type)
 {
 
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
+    /* Overflow callback */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-		|| callback_type == RTC_CALENDAR_CALLBACK_TAMPER
+        || callback_type == RTC_CALENDAR_CALLBACK_TAMPER
 #endif
-		|| (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)) {
-		status = STATUS_OK;
-	} else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM)) {
-		/* Make sure alarm callback can be registered */
-		status = STATUS_ERR_INVALID_ARG;
-	}
+        || (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7))
+            {
+        status = STATUS_OK;
+    } else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM))
+    {
+        /* Make sure alarm callback can be registered */
+        status = STATUS_ERR_INVALID_ARG;
+    }
 
-	if (status == STATUS_OK) {
-		/* Register callback */
-		module->callbacks[callback_type] = callback;
-		/* Set corresponding bit to set callback as registered */
-		module->registered_callback |= (1 << callback_type);
-	}
+    if (status == STATUS_OK)
+    {
+        /* Register callback */
+        module->callbacks[callback_type] = callback;
+        /* Set corresponding bit to set callback as registered */
+        module->registered_callback |= (1 << callback_type);
+    }
 
-	return status;
+    return status;
 }
 
 /**
@@ -109,32 +112,35 @@ enum status_code rtc_calendar_register_callback(
  * \retval STATUS_ERR_INVALID_ARG If trying to unregister, a callback is not available
  */
 enum status_code rtc_calendar_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
+    /* Overflow callback */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-		|| callback_type == RTC_CALENDAR_CALLBACK_TAMPER
+        || callback_type == RTC_CALENDAR_CALLBACK_TAMPER
 #endif
-		|| (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)) {
-		status = STATUS_OK;
-	} else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM)) {
-		/* Make sure alarm callback can be unregistered */
-		status = STATUS_ERR_INVALID_ARG;
-	}
+        || (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7))
+            {
+        status = STATUS_OK;
+    } else if (callback_type > (RTC_NUM_OF_ALARMS + RTC_PER_NUM))
+    {
+        /* Make sure alarm callback can be unregistered */
+        status = STATUS_ERR_INVALID_ARG;
+    }
 
-	if (status == STATUS_OK) {
-		/* Unregister callback */
-		module->callbacks[callback_type] = NULL;
+    if (status == STATUS_OK)
+    {
+        /* Unregister callback */
+        module->callbacks[callback_type] = NULL;
 
-		/* Clear corresponding bit to set callback as unregistered */
-		module->registered_callback &= ~(1 << callback_type);
-	}
-	return status;
+        /* Clear corresponding bit to set callback as unregistered */
+        module->registered_callback &= ~(1 << callback_type);
+    }
+    return status;
 }
 
 /**
@@ -146,29 +152,32 @@ enum status_code rtc_calendar_unregister_callback(
  * \param[in]     callback_type Callback type to enable
  */
 void rtc_calendar_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_OVF;
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER) {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_TAMPER;
+    } else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER)
+    {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_TAMPER;
 #endif
-	} else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7) {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
-	}else {
-		rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
-	}
-	/* Mark callback as enabled. */
-	module->enabled_callback |= (1 << callback_type);
+    } else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)
+            {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
+    }else {
+        rtc_module->MODE2.INTENSET.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
+    }
+    /* Mark callback as enabled. */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -180,31 +189,34 @@ void rtc_calendar_enable_callback(
  * \param[in]     callback_type Callback type to disable
  */
 void rtc_calendar_disable_callback(
-		struct rtc_module *const module,
-		enum rtc_calendar_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_calendar_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable interrupt */
-	if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW) {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
+    /* Disable interrupt */
+    if (callback_type == RTC_CALENDAR_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_OVF;
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER) {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_TAMPER;
+    } else if (callback_type == RTC_CALENDAR_CALLBACK_TAMPER)
+    {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_TAMPER;
 #endif
-	} else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7) {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
-	}else {
-		rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
-	}
+    } else if (callback_type >= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_CALENDAR_CALLBACK_PERIODIC_INTERVAL_7)
+            {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_PER((1 << callback_type));
+    }else {
+        rtc_module->MODE2.INTENCLR.reg = RTC_MODE2_INTFLAG_ALARM(1 << (callback_type - RTC_PER_NUM));
+    }
 
-	/* Mark callback as disabled. */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled. */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -214,86 +226,101 @@ void rtc_calendar_disable_callback(
  */
 static void _rtc_interrupt_handler(const uint32_t instance_index)
 {
-	struct rtc_module *module = _rtc_instance[instance_index];
+    struct rtc_module *module = _rtc_instance[instance_index];
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Combine callback registered and enabled masks */
-	uint16_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
+    /* Combine callback registered and enabled masks */
+    uint16_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
 
-	/* Read and mask interrupt flag register */
-	uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
-	interrupt_status &= rtc_module->MODE2.INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    uint16_t interrupt_status = rtc_module->MODE2.INTFLAG.reg;
+    interrupt_status &= rtc_module->MODE2.INTENSET.reg;
 
-	if (interrupt_status & RTC_MODE2_INTFLAG_OVF) {
-		/* Overflow interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
-		}
+    if (interrupt_status & RTC_MODE2_INTFLAG_OVF)
+    {
+        /* Overflow interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_OVERFLOW))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_OVERFLOW]();
+        }
 
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF;
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_TAMPER) {
-		/* Tamper interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_TAMPER)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_TAMPER]();
-		}
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_TAMPER)
+    {
+        /* Tamper interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_TAMPER))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_TAMPER]();
+        }
 
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER;
 #endif
-	}else if (interrupt_status & RTC_MODE2_INTFLAG_PER(0xff)) {
-		uint8_t i  = 0;
-		for (i = 0;i < RTC_PER_NUM;i++) {
-			if ((interrupt_status & RTC_MODE2_INTFLAG_PER(1 << i))
-			  && (callback_mask & (1 << i))) {
-				module->callbacks[i]();
-			}
+    }else if (interrupt_status & RTC_MODE2_INTFLAG_PER(0xff))
+    {
+        uint8_t i  = 0;
+        for (i = 0;i < RTC_PER_NUM;i++)
+        {
+            if ((interrupt_status & RTC_MODE2_INTFLAG_PER(1 << i))
+              && (callback_mask & (1 << i)))
+              {
+                module->callbacks[i]();
+            }
 
-			/* Clear interrupt flag */
-			rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1<<i);
-		}
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0)) {
-		/* Alarm 0 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
+            /* Clear interrupt flag */
+            rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER(1<<i);
+        }
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 0))
+    {
+        /* Alarm 0 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_0))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_0]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 0);
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1)) {
-		#if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
-		/* Alarm 1 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
-		#endif
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 1))
+    {
+        #if (RTC_NUM_OF_ALARMS > 1) || defined(__DOXYGEN__)
+        /* Alarm 1 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_1))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_1]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 1);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2)) {
-		#if (RTC_NUM_OF_ALARMS > 2)	|| defined(__DOXYGEN__)
-		/* Alarm 2 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
-		#endif
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 2))
+    {
+        #if (RTC_NUM_OF_ALARMS > 2) || defined(__DOXYGEN__)
+        /* Alarm 2 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_2))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_2]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 2);
+        #endif
 
-	} else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3)) {
-		#if (RTC_NUM_OF_ALARMS > 3)	|| defined(__DOXYGEN__)
-		/* Alarm 3 interrupt */
-		if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3)) {
-			module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
-		#endif
-	}
+    } else if (interrupt_status & RTC_MODE2_INTFLAG_ALARM(1 << 3))
+    {
+        #if (RTC_NUM_OF_ALARMS > 3) || defined(__DOXYGEN__)
+        /* Alarm 3 interrupt */
+        if (callback_mask & (1 << RTC_CALENDAR_CALLBACK_ALARM_3))
+        {
+            module->callbacks[RTC_CALENDAR_CALLBACK_ALARM_3]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(1 << 3);
+        #endif
+    }
 }
 
 /**
@@ -302,14 +329,14 @@ static void _rtc_interrupt_handler(const uint32_t instance_index)
 #if (RTC_INST_NUM == 1)
 void RTC_Handler(void)
 {
-	_rtc_interrupt_handler(0);
+    _rtc_interrupt_handler(0);
 }
 #elif (RTC_INST_NUM > 1)
 #  define _RTC_INTERRUPT_HANDLER(n, unused) \
-		void RTC##n##_Handler(void) \
-		{ \
-			_rtc_interrupt_handler(n); \
-		}
+        void RTC##n##_Handler(void) \
+        { \
+            _rtc_interrupt_handler(n); \
+        }
 
 MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
-#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
+#endif /* (RTC_INST_NUM > 1) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c
index ae73d9399a7f..cc3c5f2370f0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count.c
@@ -75,17 +75,18 @@ struct rtc_module *_rtc_instance[RTC_INST_NUM];
  */
 static bool rtc_count_is_syncing(struct rtc_module *const module)
 {
- 	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (rtc_module->MODE0.SYNCBUSY.reg) {
-		return true;
-	}
+    if (rtc_module->MODE0.SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -98,26 +99,28 @@ static bool rtc_count_is_syncing(struct rtc_module *const module)
  */
 void rtc_count_enable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_COUNT_ASYNC == true
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Enable RTC module. */
-	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+    /* Enable RTC module. */
+    rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -129,31 +132,33 @@ void rtc_count_enable(struct rtc_module *const module)
  */
 void rtc_count_disable(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if RTC_COUNT_ASYNC == true
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
+    /* Disbale interrupt */
+    rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_MASK;
 
-	/* Disable RTC module. */
-	rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+    /* Disable RTC module. */
+    rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -164,30 +169,32 @@ void rtc_count_disable(struct rtc_module *const module)
  */
 void rtc_count_reset(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable module before reset. */
-	rtc_count_disable(module);
+    /* Disable module before reset. */
+    rtc_count_disable(module);
 
 #if RTC_COUNT_ASYNC == true
-	module->registered_callback = 0;
-	module->enabled_callback    = 0;
+    module->registered_callback = 0;
+    module->enabled_callback    = 0;
 #endif
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Initiate software reset. */
-	rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
+    /* Initiate software reset. */
+    rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -204,68 +211,73 @@ void rtc_count_reset(struct rtc_module *const module)
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
  */
 static enum status_code _rtc_count_set_config(
-		struct rtc_module *const module,
-		const struct rtc_count_config *const config)
+        struct rtc_module *const module,
+        const struct rtc_count_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
 #if SAML21 || SAMR30
-	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0)
+    rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0)
 #if (SAML21XXXB) || (SAMR30)
-				    | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
+                    | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos)
 #endif
-				    | config->prescaler;
+                    | config->prescaler;
 #endif
 #if (SAMC20) || (SAMC21) || (SAML22)
-	rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler
-			| (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos);
+    rtc_module->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE(0) | config->prescaler
+            | (config->enable_read_sync << RTC_MODE0_CTRLA_COUNTSYNC_Pos);
 #endif
 
-	/* Set mode and clear on match if applicable. */
-	switch (config->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Set 32-bit mode and clear on match if applicable. */
-			rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0);
-
-			/* Check if clear on compare match should be set. */
-			if (config->clear_on_match) {
-				/* Set clear on match. */
-				rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
-			}
-			/* Set compare values. */
-			for (uint8_t i = 0; i < RTC_COMP32_NUM; i++) {
-				rtc_count_set_compare(module, config->compare_values[i],
-						(enum rtc_count_compare)i);
-			}
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Set 16bit mode. */
-			rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1);
-
-			/* Check if match on clear is set, and return invalid
-			 * argument if set. */
-			if (config->clear_on_match) {
-				Assert(false);
-				return STATUS_ERR_INVALID_ARG;
-			}
-			/* Set compare values. */
-			for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
-				rtc_count_set_compare(module, config->compare_values[i],
-						(enum rtc_count_compare)i);
-			}
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Return status OK if everything was configured. */
-	return STATUS_OK;
+    /* Set mode and clear on match if applicable. */
+    switch (config->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Set 32-bit mode and clear on match if applicable. */
+            rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(0);
+
+            /* Check if clear on compare match should be set. */
+            if (config->clear_on_match)
+            {
+                /* Set clear on match. */
+                rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR;
+            }
+            /* Set compare values. */
+            for (uint8_t i = 0; i < RTC_COMP32_NUM; i++)
+            {
+                rtc_count_set_compare(module, config->compare_values[i],
+                        (enum rtc_count_compare)i);
+            }
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Set 16bit mode. */
+            rtc_module->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(1);
+
+            /* Check if match on clear is set, and return invalid
+             * argument if set. */
+            if (config->clear_on_match)
+            {
+                Assert(false);
+                return STATUS_ERR_INVALID_ARG;
+            }
+            /* Set compare values. */
+            for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++)
+            {
+                rtc_count_set_compare(module, config->compare_values[i],
+                        (enum rtc_count_compare)i);
+            }
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Return status OK if everything was configured. */
+    return STATUS_OK;
 }
 
 /**
@@ -283,39 +295,39 @@ static enum status_code _rtc_count_set_config(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were given
  */
 enum status_code rtc_count_init(
-		struct rtc_module *const module,
-		Rtc *const hw,
-		const struct rtc_count_config *const config)
+        struct rtc_module *const module,
+        Rtc *const hw,
+        const struct rtc_count_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_RTC);
 
-	/* Select RTC clock */
-	OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
+    /* Select RTC clock */
+    OSC32KCTRL->RTCCTRL.reg = RTC_CLOCK_SOURCE;
 
-	/* Reset module to hardware defaults. */
-	rtc_count_reset(module);
+    /* Reset module to hardware defaults. */
+    rtc_count_reset(module);
 
-	/* Save conf_struct internally for continued use. */
-	module->mode                = config->mode;
+    /* Save conf_struct internally for continued use. */
+    module->mode                = config->mode;
 
 #  if (RTC_INST_NUM == 1)
-	_rtc_instance[0] = module;
+    _rtc_instance[0] = module;
 #  else
-	/* Register this instance for callbacks*/
-	_rtc_instance[_rtc_get_inst_index(hw)] = module;
+    /* Register this instance for callbacks*/
+    _rtc_instance[_rtc_get_inst_index(hw)] = module;
 #  endif
 
-	/* Set config and return status. */
-	return _rtc_count_set_config(module, config);
+    /* Set config and return status. */
+    return _rtc_count_set_config(module, config);
 }
 
 /**
@@ -331,45 +343,49 @@ enum status_code rtc_count_init(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_count_set_count(
-		struct rtc_module *const module,
-		const uint32_t count_value)
+        struct rtc_module *const module,
+        const uint32_t count_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set count according to mode */
-	switch(module->mode){
-		case RTC_COUNT_MODE_32BIT:
-			/* Write value to register. */
-			rtc_module->MODE0.COUNT.reg = count_value;
-			break;
-		case RTC_COUNT_MODE_16BIT:
-			/* Check if 16-bit value is provided. */
-			if(count_value > 0xffff){
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Write value to register. */
-			rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set count according to mode */
+    switch(module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Write value to register. */
+            rtc_module->MODE0.COUNT.reg = count_value;
+            break;
+        case RTC_COUNT_MODE_16BIT:
+            /* Check if 16-bit value is provided. */
+            if(count_value > 0xffff)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Write value to register. */
+            rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -383,41 +399,43 @@ enum status_code rtc_count_set_count(
  */
 uint32_t rtc_count_get_count(struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Initialize return value. */
-	uint32_t ret_val;
+    /* Initialize return value. */
+    uint32_t ret_val;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Read value based on mode. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Return count value in 32-bit mode. */
-			ret_val = rtc_module->MODE0.COUNT.reg;
+    /* Read value based on mode. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Return count value in 32-bit mode. */
+            ret_val = rtc_module->MODE0.COUNT.reg;
 
-			break;
+            break;
 
-		case RTC_COUNT_MODE_16BIT:
-			/* Return count value in 16-bit mode. */
-			ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
+        case RTC_COUNT_MODE_16BIT:
+            /* Return count value in 16-bit mode. */
+            ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
 
-			break;
+            break;
 
-		default:
-			Assert(false);
-			/* Counter not initialized. Assume counter value 0.*/
-			ret_val = 0;
-			break;
-	}
+        default:
+            Assert(false);
+            /* Counter not initialized. Assume counter value 0.*/
+            ret_val = 0;
+            break;
+    }
 
-	return ret_val;
+    return ret_val;
 }
 
 /**
@@ -437,61 +455,67 @@ uint32_t rtc_count_get_count(struct rtc_module *const module)
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_set_compare(
-		struct rtc_module *const module,
-		const uint32_t comp_value,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const uint32_t comp_value,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	/* Set compare values based on operation mode. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Set compare value for COMP. */
-			rtc_module->MODE0.COMP[comp_index].reg = comp_value;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Check that 16-bit value is provided. */
-			if (comp_value > 0xffff) {
-				Assert(false);
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Set compare value for COMP. */
-			rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	/* Return status if everything is OK. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Set compare values based on operation mode. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_COMP32_NUM)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Set compare value for COMP. */
+            rtc_module->MODE0.COMP[comp_index].reg = comp_value;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Check that 16-bit value is provided. */
+            if (comp_value > 0xffff)
+            {
+                Assert(false);
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Set compare value for COMP. */
+            rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Return status if everything is OK. */
+    return STATUS_OK;
 }
 
 /**
@@ -512,49 +536,53 @@ enum status_code rtc_count_set_compare(
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_get_compare(
-		struct rtc_module *const module,
-		uint32_t *const comp_value,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        uint32_t *const comp_value,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
-
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_COMP32_NUM) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Get compare value for COMP. */
-			*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity of comp_index. */
-			if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			/* Get compare value for COMP. */
-			*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-	/* Return status showing everything is OK. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
+
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_COMP32_NUM)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Get compare value for COMP. */
+            *comp_value = rtc_module->MODE0.COMP[comp_index].reg;
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity of comp_index. */
+            if ((uint32_t)comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            /* Get compare value for COMP. */
+            *comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+    /* Return status showing everything is OK. */
+    return STATUS_OK;
 }
 
 /**
@@ -572,28 +600,30 @@ enum status_code rtc_count_get_compare(
  * \retval STATUS_ERR_UNSUPPORTED_DEV  If incorrect mode was set
  */
 enum status_code rtc_count_get_period(
-		struct rtc_module *const module,
-		uint16_t *const period_value)
+        struct rtc_module *const module,
+        uint16_t *const period_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Check that correct mode is set. */
-	if (module->mode != RTC_COUNT_MODE_16BIT) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Check that correct mode is set. */
+    if (module->mode != RTC_COUNT_MODE_16BIT)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	/* Returns the value. */
-	*period_value = rtc_module->MODE1.PER.reg;
+    /* Returns the value. */
+    *period_value = rtc_module->MODE1.PER.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -611,32 +641,35 @@ enum status_code rtc_count_get_period(
  * \retval STATUS_ERR_UNSUPPORTED_DEV  If module is not operated in 16-bit mode
  */
 enum status_code rtc_count_set_period(
-		struct rtc_module *const module,
-		const uint16_t period_value)
+        struct rtc_module *const module,
+        const uint16_t period_value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check that correct mode is set. */
-	if (module->mode != RTC_COUNT_MODE_16BIT) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Check that correct mode is set. */
+    if (module->mode != RTC_COUNT_MODE_16BIT)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Write value to register. */
-	rtc_module->MODE1.PER.reg = period_value;
+    /* Write value to register. */
+    rtc_module->MODE1.PER.reg = period_value;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -651,40 +684,43 @@ enum status_code rtc_count_set_period(
  * \param[in] comp_index  Index of compare to check current flag
  */
 bool rtc_count_is_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Check sanity. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (comp_index > RTC_COMP32_NUM) {
-				return false;
-			}
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP16) {
-				return false;
-			}
-
-			break;
-
-		default:
-			Assert(false);
-			return false;
-	}
-
-	/* Set status of INTFLAG as return argument. */
-	return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Check sanity. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (comp_index > RTC_COMP32_NUM)
+            {
+                return false;
+            }
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP16)
+            {
+                return false;
+            }
+
+            break;
+
+        default:
+            Assert(false);
+            return false;
+    }
+
+    /* Set status of INTFLAG as return argument. */
+    return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP(1 << comp_index)) ? true : false;
 }
 
 /**
@@ -704,42 +740,45 @@ bool rtc_count_is_compare_match(
  * \retval STATUS_ERR_BAD_FORMAT   If the module was not initialized in a mode
  */
 enum status_code rtc_count_clear_compare_match(
-		struct rtc_module *const module,
-		const enum rtc_count_compare comp_index)
+        struct rtc_module *const module,
+        const enum rtc_count_compare comp_index)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	Rtc *const rtc_module = module->hw;
-
-	/* Check sanity. */
-	switch (module->mode){
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (comp_index > RTC_COMP32_NUM) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			break;
-
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (comp_index > RTC_NUM_OF_COMP16) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Clear INTFLAG. */
-	rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    Rtc *const rtc_module = module->hw;
+
+    /* Check sanity. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (comp_index > RTC_COMP32_NUM)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            break;
+
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (comp_index > RTC_NUM_OF_COMP16)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Clear INTFLAG. */
+    rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
+
+    return STATUS_OK;
 }
 
 /**
@@ -762,43 +801,47 @@ enum status_code rtc_count_clear_compare_match(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code rtc_count_frequency_correction(
-		struct rtc_module *const module,
-		const int8_t value)
+        struct rtc_module *const module,
+        const int8_t value)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Check if valid argument. */
-	if (abs(value) > 0x7F) {
-		/* Value bigger than allowed, return invalid argument. */
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if valid argument. */
+    if (abs(value) > 0x7F)
+    {
+        /* Value bigger than allowed, return invalid argument. */
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	uint32_t new_correction_value;
+    uint32_t new_correction_value;
 
-	/* Load the new correction value as a positive value, sign added later */
-	new_correction_value = abs(value);
+    /* Load the new correction value as a positive value, sign added later */
+    new_correction_value = abs(value);
 
-	/* Convert to positive value and adjust register sign bit. */
-	if (value < 0) {
-		new_correction_value |= RTC_FREQCORR_SIGN;
-	}
+    /* Convert to positive value and adjust register sign bit. */
+    if (value < 0)
+    {
+        new_correction_value |= RTC_FREQCORR_SIGN;
+    }
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set value. */
-	rtc_module->MODE0.FREQCORR.reg = new_correction_value;
+    /* Set value. */
+    rtc_module->MODE0.FREQCORR.reg = new_correction_value;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 #ifdef FEATURE_RTC_TAMPER_DETECTION
@@ -806,7 +849,7 @@ enum status_code rtc_count_frequency_correction(
  * \brief Applies the given configuration.
  *
  * Sets the configurations given from the configuration structure to the
- * RTC tamper and it should be called before RTC module enable. 
+ * RTC tamper and it should be called before RTC module enable.
  *
  * \param[in,out]  module  Pointer to the software instance struct
  * \param[in] config  Pointer to the configuration structure
@@ -816,92 +859,101 @@ enum status_code rtc_count_frequency_correction(
  * \note If tamper input configured as active layer protection, RTC prescaler
  *       output automatically enabled in the function.
  */
-enum status_code rtc_tamper_set_config ( 
-		struct rtc_module *const module,
-		struct rtc_tamper_config *const tamper_cfg)
+enum status_code rtc_tamper_set_config (
+        struct rtc_module *const module,
+        struct rtc_tamper_config *const tamper_cfg)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(tamper_cfg);
-
-	Rtc *const rtc_module = module->hw;
-	uint16_t ctrl_b = 0;
-
-	/* Configure enable backup and GP register reset on tamper or not. */
-	if(tamper_cfg->bkup_reset_on_tamper) {
-		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
-	} else {
-		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
-	}
-	
-	if (tamper_cfg->gp_reset_on_tamper) {
-		rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
-	} else {
-		rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
-	}
-
-	/* Configure tamper detection of frequency and debounce setting. */
-	ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
-	if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC) {
-		ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
-	} else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY) {
-		ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
-	}
-	if(tamper_cfg->dma_tamper_enable) {
-		ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
-	}
-	if (tamper_cfg->gp0_enable) {
-		ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
-	}
-
-	/* Configure tamper input. */
-	volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE0.TAMPCTRL);
-
-	struct rtc_tamper_input_config in_cfg;
-	for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++) {
-		in_cfg = tamper_cfg->in_cfg[tamper_id];
-
-		if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL) {
-			ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
-		}
-	
-		switch(tamper_id) {
-			case 0:
-				tamper_ctrl->bit.IN0ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
-				break;
-			case 1:
-				tamper_ctrl->bit.IN1ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
-				break;
-			case 2:
-				tamper_ctrl->bit.IN2ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
-				break;
-			case 3:
-				tamper_ctrl->bit.IN3ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
-				break;
-			case 4:
-				tamper_ctrl->bit.IN4ACT = in_cfg.action;
-				tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
-				tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
-				break;
-			default:
-				Assert(false);
-				break;
-		}
-	}
-
-	rtc_module->MODE0.CTRLB.reg = ctrl_b;
-
-	/* Return status OK if everything was configured. */
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(tamper_cfg);
+
+    Rtc *const rtc_module = module->hw;
+    uint16_t ctrl_b = 0;
+
+    /* Configure enable backup and GP register reset on tamper or not. */
+    if(tamper_cfg->bkup_reset_on_tamper)
+    {
+        rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST;
+    } else {
+        rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST;
+    }
+
+    if (tamper_cfg->gp_reset_on_tamper)
+    {
+        rtc_module->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST;
+    } else {
+        rtc_module->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST;
+    }
+
+    /* Configure tamper detection of frequency and debounce setting. */
+    ctrl_b = tamper_cfg->actl_freq_div | tamper_cfg->deb_freq_div;
+    if(tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_ASYNC)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DEBASYNC;
+    } else if (tamper_cfg->deb_seq == RTC_TAMPER_DEBOUNCE_MAJORITY)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DEBMAJ;
+    }
+    if(tamper_cfg->dma_tamper_enable)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_DMAEN;
+    }
+    if (tamper_cfg->gp0_enable)
+    {
+        ctrl_b |= RTC_MODE0_CTRLB_GP0EN;
+    }
+
+    /* Configure tamper input. */
+    volatile RTC_TAMPCTRL_Type *tamper_ctrl = &(rtc_module->MODE0.TAMPCTRL);
+
+    struct rtc_tamper_input_config in_cfg;
+    for (uint8_t tamper_id = 0; tamper_id < RTC_TAMPER_NUM; tamper_id++)
+    {
+        in_cfg = tamper_cfg->in_cfg[tamper_id];
+
+        if(in_cfg.action == RTC_TAMPER_INPUT_ACTION_ACTL)
+        {
+            ctrl_b |= RTC_MODE0_CTRLB_RTCOUT;
+        }
+
+        switch(tamper_id)
+        {
+            case 0:
+                tamper_ctrl->bit.IN0ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL0 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC0 = in_cfg.debounce_enable;
+                break;
+            case 1:
+                tamper_ctrl->bit.IN1ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL1 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC1 = in_cfg.debounce_enable;
+                break;
+            case 2:
+                tamper_ctrl->bit.IN2ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL2 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC2 = in_cfg.debounce_enable;
+                break;
+            case 3:
+                tamper_ctrl->bit.IN3ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL3 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC3 = in_cfg.debounce_enable;
+                break;
+            case 4:
+                tamper_ctrl->bit.IN4ACT = in_cfg.action;
+                tamper_ctrl->bit.TAMLVL4 = in_cfg.level;
+                tamper_ctrl->bit.DEBNC4 = in_cfg.debounce_enable;
+                break;
+            default:
+                Assert(false);
+                break;
+        }
+    }
+
+    rtc_module->MODE0.CTRLB.reg = ctrl_b;
+
+    /* Return status OK if everything was configured. */
+    return STATUS_OK;
 }
 
 /**
@@ -913,39 +965,41 @@ enum status_code rtc_tamper_set_config (
  */
 uint32_t rtc_tamper_get_stamp (struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Initialize return value. */
-	uint32_t tamper_stamp = 0;
+    /* Initialize return value. */
+    uint32_t tamper_stamp = 0;
 
-	while (rtc_count_is_syncing(module)) {
-		/* Wait for synchronization */
-	}
+    while (rtc_count_is_syncing(module))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Read value based on mode. */
-	switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Return stamp value in 32-bit mode. */
-			tamper_stamp = rtc_module->MODE0.TIMESTAMP.reg;
+    /* Read value based on mode. */
+    switch (module->mode)
+    {
+        case RTC_COUNT_MODE_32BIT:
+            /* Return stamp value in 32-bit mode. */
+            tamper_stamp = rtc_module->MODE0.TIMESTAMP.reg;
 
-			break;
+            break;
 
-		case RTC_COUNT_MODE_16BIT:
-			/* Return stamp value in 16-bit mode. */
-			tamper_stamp = (uint32_t)rtc_module->MODE1.TIMESTAMP.reg;
+        case RTC_COUNT_MODE_16BIT:
+            /* Return stamp value in 16-bit mode. */
+            tamper_stamp = (uint32_t)rtc_module->MODE1.TIMESTAMP.reg;
 
-			break;
+            break;
 
-		default:
-			Assert(false);
-			break;
-	}
+        default:
+            Assert(false);
+            break;
+    }
 
-	return tamper_stamp;
+    return tamper_stamp;
 }
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c
index 2c8c95c042fc..7f74fe7dd290 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_sam_l_c/rtc_count_interrupt.c
@@ -65,50 +65,55 @@ extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
  * \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
  */
 enum status_code rtc_count_register_callback(
-		struct rtc_module *const module,
-		rtc_count_callback_t callback,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        rtc_count_callback_t callback,
+        enum rtc_count_callback callback_type)
 {
 
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+    /* Overflow callback */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+        || callback_type == RTC_COUNT_CALLBACK_TAMPER
 #endif
-		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
-		status = STATUS_OK;
-	} else {
-		/* Make sure callback type can be registered */
-		switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-
-			break;
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		default:
-			status = STATUS_ERR_INVALID_ARG;
-		}
-	}
-
-	if (status == STATUS_OK) {
-		/* Register callback */
-		module->callbacks[callback_type] = callback;
-		/* Set corresponding bit to set callback as registered */
-		module->registered_callback |= (1 << callback_type);
-	}
-
-	return status;
+        || (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7))
+            {
+        status = STATUS_OK;
+    } else {
+        /* Make sure callback type can be registered */
+        switch (module->mode)
+        {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM))
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+
+            break;
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM))
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        default:
+            status = STATUS_ERR_INVALID_ARG;
+        }
+    }
+
+    if (status == STATUS_OK)
+    {
+        /* Register callback */
+        module->callbacks[callback_type] = callback;
+        /* Set corresponding bit to set callback as registered */
+        module->registered_callback |= (1 << callback_type);
+    }
+
+    return status;
 }
 
 /**
@@ -125,46 +130,51 @@ enum status_code rtc_count_register_callback(
  * \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
  */
 enum status_code rtc_count_unregister_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	enum status_code status = STATUS_OK;
+    enum status_code status = STATUS_OK;
 
-	/* Overflow callback */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
+    /* Overflow callback */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-		|| callback_type == RTC_COUNT_CALLBACK_TAMPER
+        || callback_type == RTC_COUNT_CALLBACK_TAMPER
 #endif
-		|| (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)) {
-		status = STATUS_OK;
-	} else {
-		/* Make sure callback type can be unregistered */
-		switch (module->mode) {
-		case RTC_COUNT_MODE_32BIT:
-			/* Check sanity for 32-bit mode. */
-			if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM)) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		case RTC_COUNT_MODE_16BIT:
-			/* Check sanity for 16-bit mode. */
-			if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM)) {
-				status = STATUS_ERR_INVALID_ARG;
-			}
-			break;
-		default:
-			status = STATUS_ERR_INVALID_ARG;
-		}
-	}
-	if (status == STATUS_OK) {
-		/* Unregister callback */
-		module->callbacks[callback_type] = NULL;
-
-		/* Clear corresponding bit to set callback as unregistered */
-		module->registered_callback &= ~(1 << callback_type);
-	}
-	return status;
+        || (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7))
+            {
+        status = STATUS_OK;
+    } else {
+        /* Make sure callback type can be unregistered */
+        switch (module->mode)
+        {
+        case RTC_COUNT_MODE_32BIT:
+            /* Check sanity for 32-bit mode. */
+            if (callback_type > (RTC_COMP32_NUM + RTC_PER_NUM))
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        case RTC_COUNT_MODE_16BIT:
+            /* Check sanity for 16-bit mode. */
+            if (callback_type > (RTC_NUM_OF_COMP16 + RTC_PER_NUM))
+            {
+                status = STATUS_ERR_INVALID_ARG;
+            }
+            break;
+        default:
+            status = STATUS_ERR_INVALID_ARG;
+        }
+    }
+    if (status == STATUS_OK)
+    {
+        /* Unregister callback */
+        module->callbacks[callback_type] = NULL;
+
+        /* Clear corresponding bit to set callback as unregistered */
+        module->registered_callback &= ~(1 << callback_type);
+    }
+    return status;
 }
 
 /**
@@ -176,29 +186,32 @@ enum status_code rtc_count_unregister_callback(
  * \param[in]     callback_type Callback type to enable
  */
 void rtc_count_enable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_TAMPER;
+    } else if (callback_type == RTC_COUNT_CALLBACK_TAMPER)
+    {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_TAMPER;
 #endif
-	} else if (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7) {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);
-	}else {
-		rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
-	}
-	/* Mark callback as enabled. */
-	module->enabled_callback |= (1 << callback_type);
+    } else if (callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)
+            {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);
+    }else {
+        rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+    }
+    /* Mark callback as enabled. */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -210,31 +223,34 @@ void rtc_count_enable_callback(
  * \param[in]     callback_type Callback type to disable
  */
 void rtc_count_disable_callback(
-		struct rtc_module *const module,
-		enum rtc_count_callback callback_type)
+        struct rtc_module *const module,
+        enum rtc_count_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Disable interrupt */
-	if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
+    /* Disable interrupt */
+    if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW)
+    {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (callback_type == RTC_COUNT_CALLBACK_TAMPER) {
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_TAMPER;
+    } else if (callback_type == RTC_COUNT_CALLBACK_TAMPER)
+    {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_TAMPER;
 #endif
-	} else if(callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
-			&& callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7){
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);;
-	}else {
-		rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
-	}
-
-	/* Mark callback as disabled. */
-	module->enabled_callback &= ~(1 << callback_type);
+    } else if(callback_type >= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_0
+            && callback_type <= RTC_COUNT_CALLBACK_PERIODIC_INTERVAL_7)
+            {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_PER(1 << callback_type);;
+    }else {
+        rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << (callback_type - RTC_PER_NUM));
+    }
+
+    /* Mark callback as disabled. */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -244,106 +260,125 @@ void rtc_count_disable_callback(
  */
 static void _rtc_interrupt_handler(const uint32_t instance_index)
 {
-	struct rtc_module *module = _rtc_instance[instance_index];
+    struct rtc_module *module = _rtc_instance[instance_index];
 
-	Rtc *const rtc_module = module->hw;
+    Rtc *const rtc_module = module->hw;
 
-	/* Combine callback registered and enabled masks */
-	uint16_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
+    /* Combine callback registered and enabled masks */
+    uint16_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
 
-	/* Read and mask interrupt flag register */
-	uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
-	interrupt_status &= rtc_module->MODE0.INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
+    interrupt_status &= rtc_module->MODE0.INTENSET.reg;
 
-	if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
-		/* Overflow interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
-			module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
-		}
+    if (interrupt_status & RTC_MODE0_INTFLAG_OVF)
+    {
+        /* Overflow interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
+        }
 
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
 #ifdef FEATURE_RTC_TAMPER_DETECTION
-	} else if (interrupt_status & RTC_MODE0_INTFLAG_TAMPER) {
-		/* Tamper interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_TAMPER)) {
-			module->callbacks[RTC_COUNT_CALLBACK_TAMPER]();
-		}
-
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
+    } else if (interrupt_status & RTC_MODE0_INTFLAG_TAMPER)
+    {
+        /* Tamper interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_TAMPER))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_TAMPER]();
+        }
+
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER;
 #endif
 
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_PER(0xff)) {
-		uint8_t i  = 0;
-		for ( i = 0;i < RTC_PER_NUM;i++) {
-			if ((interrupt_status & RTC_MODE1_INTFLAG_PER(1 << i))
-			  && (callback_mask & (1 << i))) {
-				module->callbacks[i]();
-			}
-
-			/* Clear interrupt flag */
-			rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_PER(1<<i);
-		}
-	}else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
-		/* Compare 0 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
-
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
-		#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
-		/* Compare 1 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
-		#endif
-
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
-		#if (RTC_NUM_OF_COMP16 > 2)	|| defined(__DOXYGEN__)
-		/* Compare 2 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
-		#endif
-
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
-		#if (RTC_NUM_OF_COMP16 > 3)	|| defined(__DOXYGEN__)
-		/* Compare 3 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
-		#endif
-
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
-		#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
-		/* Compare 4 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
-		#endif
-
-	} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
-		#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
-		/* Compare 5 interrupt */
-		if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
-			module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
-		}
-		/* Clear interrupt flag */
-		rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
-		#endif
-	}
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_PER(0xff))
+    {
+        uint8_t i  = 0;
+        for ( i = 0;i < RTC_PER_NUM;i++)
+        {
+            if ((interrupt_status & RTC_MODE1_INTFLAG_PER(1 << i))
+              && (callback_mask & (1 << i)))
+              {
+                module->callbacks[i]();
+            }
+
+            /* Clear interrupt flag */
+            rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_PER(1<<i);
+        }
+    }else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0))
+    {
+        /* Compare 0 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
+
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1))
+    {
+        #if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
+        /* Compare 1 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
+        #endif
+
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2))
+    {
+        #if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
+        /* Compare 2 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
+        #endif
+
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3))
+    {
+        #if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
+        /* Compare 3 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
+        #endif
+
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4))
+    {
+        #if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
+        /* Compare 4 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
+        #endif
+
+    } else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5))
+    {
+        #if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
+        /* Compare 5 interrupt */
+        if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5))
+        {
+            module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
+        }
+        /* Clear interrupt flag */
+        rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
+        #endif
+    }
 }
 
 /**
@@ -352,14 +387,14 @@ static void _rtc_interrupt_handler(const uint32_t instance_index)
 #if (RTC_INST_NUM == 1)
 void RTC_Handler(void)
 {
-	_rtc_interrupt_handler(0);
+    _rtc_interrupt_handler(0);
 }
 #elif (RTC_INST_NUM > 1)
 #  define _RTC_INTERRUPT_HANDLER(n, unused) \
-		void RTC##n##_Handler(void) \
-		{ \
-			_rtc_interrupt_handler(n); \
-		}
+        void RTC##n##_Handler(void) \
+        { \
+            _rtc_interrupt_handler(n); \
+        }
 
 MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
-#endif /* (RTC_INST_NUM > 1) */
\ No newline at end of file
+#endif /* (RTC_INST_NUM > 1) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h
index 57b1dd2bc446..435b3512f5e0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/rtc/rtc_tamper.h
@@ -63,8 +63,8 @@
  * output signals are compared and a tamper condition is detected when they do not match.
  *
  *
- * Separate debouncers are embedded for each external input. The detection time 
- * depends on whether the debouncer operates synchronously or asynchronously, 
+ * Separate debouncers are embedded for each external input. The detection time
+ * depends on whether the debouncer operates synchronously or asynchronously,
  * and whether majority detection is enabled or not. For details, refer to the section
  * "Tamper Detection" of datasheet.
  * \if RTC_COUNT_CALLBACK_MODE
@@ -101,22 +101,22 @@
  * layer protection.
  */
 enum rtc_tamper_active_layer_freq_divider {
-	/** RTC active layer frequency is prescaled by a factor of 2 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_2    = RTC_MODE0_CTRLB_ACTF_DIV2,
-	/** RTC active layer frequency is prescaled by a factor of 4 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_4    = RTC_MODE0_CTRLB_ACTF_DIV4,
-	/** RTC active layer frequency is prescaled by a factor of 8 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8    = RTC_MODE0_CTRLB_ACTF_DIV8,
-	/** RTC active layer frequency is prescaled by a factor of 16 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_16   = RTC_MODE0_CTRLB_ACTF_DIV16,
-	/** RTC active layer frequency is prescaled by a factor of 32 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_32   = RTC_MODE0_CTRLB_ACTF_DIV32,
-	/** RTC active layer frequency is prescaled by a factor of 64 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_64   = RTC_MODE0_CTRLB_ACTF_DIV64,
-	/** RTC active layer frequency is prescaled by a factor of 128 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_128  = RTC_MODE0_CTRLB_ACTF_DIV128,
-	/** RTC active layer frequency is prescaled by a factor of 256 */
-	RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_256  = RTC_MODE0_CTRLB_ACTF_DIV256,
+    /** RTC active layer frequency is prescaled by a factor of 2 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_2    = RTC_MODE0_CTRLB_ACTF_DIV2,
+    /** RTC active layer frequency is prescaled by a factor of 4 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_4    = RTC_MODE0_CTRLB_ACTF_DIV4,
+    /** RTC active layer frequency is prescaled by a factor of 8 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8    = RTC_MODE0_CTRLB_ACTF_DIV8,
+    /** RTC active layer frequency is prescaled by a factor of 16 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_16   = RTC_MODE0_CTRLB_ACTF_DIV16,
+    /** RTC active layer frequency is prescaled by a factor of 32 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_32   = RTC_MODE0_CTRLB_ACTF_DIV32,
+    /** RTC active layer frequency is prescaled by a factor of 64 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_64   = RTC_MODE0_CTRLB_ACTF_DIV64,
+    /** RTC active layer frequency is prescaled by a factor of 128 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_128  = RTC_MODE0_CTRLB_ACTF_DIV128,
+    /** RTC active layer frequency is prescaled by a factor of 256 */
+    RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_256  = RTC_MODE0_CTRLB_ACTF_DIV256,
 };
 
 /**
@@ -125,22 +125,22 @@ enum rtc_tamper_active_layer_freq_divider {
  * The available prescaler factor for the input debouncers.
  */
 enum rtc_tamper_debounce_freq_divider {
-	/** RTC debounce frequency is prescaled by a factor of 2 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_2    = RTC_MODE0_CTRLB_DEBF_DIV2,
-	/** RTC debounce frequency is prescaled by a factor of 4 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_4    = RTC_MODE0_CTRLB_DEBF_DIV4,
-	/** RTC debounce frequency is prescaled by a factor of 8 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_8    = RTC_MODE0_CTRLB_DEBF_DIV8,
-	/** RTC debounce frequency is prescaled by a factor of 16 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_16   = RTC_MODE0_CTRLB_DEBF_DIV16,
-	/** RTC debounce frequency is prescaled by a factor of 32 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_32   = RTC_MODE0_CTRLB_DEBF_DIV32,
-	/** RTC debounce frequency is prescaled by a factor of 64 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_64   = RTC_MODE0_CTRLB_DEBF_DIV64,
-	/** RTC debounce frequency is prescaled by a factor of 128 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_128  = RTC_MODE0_CTRLB_DEBF_DIV128,
-	/** RTC debounce frequency is prescaled by a factor of 256 */
-	RTC_TAMPER_DEBOUNCE_FREQ_DIV_256  = RTC_MODE0_CTRLB_DEBF_DIV256,
+    /** RTC debounce frequency is prescaled by a factor of 2 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_2    = RTC_MODE0_CTRLB_DEBF_DIV2,
+    /** RTC debounce frequency is prescaled by a factor of 4 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_4    = RTC_MODE0_CTRLB_DEBF_DIV4,
+    /** RTC debounce frequency is prescaled by a factor of 8 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_8    = RTC_MODE0_CTRLB_DEBF_DIV8,
+    /** RTC debounce frequency is prescaled by a factor of 16 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_16   = RTC_MODE0_CTRLB_DEBF_DIV16,
+    /** RTC debounce frequency is prescaled by a factor of 32 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_32   = RTC_MODE0_CTRLB_DEBF_DIV32,
+    /** RTC debounce frequency is prescaled by a factor of 64 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_64   = RTC_MODE0_CTRLB_DEBF_DIV64,
+    /** RTC debounce frequency is prescaled by a factor of 128 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_128  = RTC_MODE0_CTRLB_DEBF_DIV128,
+    /** RTC debounce frequency is prescaled by a factor of 256 */
+    RTC_TAMPER_DEBOUNCE_FREQ_DIV_256  = RTC_MODE0_CTRLB_DEBF_DIV256,
 };
 
 /**
@@ -149,15 +149,15 @@ enum rtc_tamper_debounce_freq_divider {
  * The available action taken by the tamper input.
  */
 enum rtc_tamper_input_action {
-	/** RTC tamper input action is disabled */
-	RTC_TAMPER_INPUT_ACTION_OFF     = RTC_TAMPCTRL_IN0ACT_OFF,
-	/** RTC tamper input action is wake and set tamper flag */
-	RTC_TAMPER_INPUT_ACTION_WAKE    = RTC_TAMPCTRL_IN0ACT_WAKE,
-	/** RTC tamper input action is capture timestamp and set tamper flag */
-	RTC_TAMPER_INPUT_ACTION_CAPTURE = RTC_TAMPCTRL_IN0ACT_CAPTURE,
-	/** RTC tamper input action is compare IN to OUT, when a mismatch occurs,
-	 *  capture timestamp and set tamper flag */
-	RTC_TAMPER_INPUT_ACTION_ACTL    = RTC_TAMPCTRL_IN0ACT_ACTL,
+    /** RTC tamper input action is disabled */
+    RTC_TAMPER_INPUT_ACTION_OFF     = RTC_TAMPCTRL_IN0ACT_OFF,
+    /** RTC tamper input action is wake and set tamper flag */
+    RTC_TAMPER_INPUT_ACTION_WAKE    = RTC_TAMPCTRL_IN0ACT_WAKE,
+    /** RTC tamper input action is capture timestamp and set tamper flag */
+    RTC_TAMPER_INPUT_ACTION_CAPTURE = RTC_TAMPCTRL_IN0ACT_CAPTURE,
+    /** RTC tamper input action is compare IN to OUT, when a mismatch occurs,
+     *  capture timestamp and set tamper flag */
+    RTC_TAMPER_INPUT_ACTION_ACTL    = RTC_TAMPCTRL_IN0ACT_ACTL,
 };
 
 /**
@@ -166,10 +166,10 @@ enum rtc_tamper_input_action {
  * The available edge condition for tamper INn level select.
  */
 enum rtc_tamper_level_sel {
-	/** A falling edge condition will be detected on Tamper input */
-	RTC_TAMPER_LEVEL_FALLING = (0),
-	/** A rising edge condition will be detected on Tamper input */
-	RTC_TAMPER_LEVEL_RISING  = (1),
+    /** A falling edge condition will be detected on Tamper input */
+    RTC_TAMPER_LEVEL_FALLING = (0),
+    /** A rising edge condition will be detected on Tamper input */
+    RTC_TAMPER_LEVEL_RISING  = (1),
 };
 
 /**
@@ -178,12 +178,12 @@ enum rtc_tamper_level_sel {
  * The available sequential for tamper debounce.
  */
 enum rtc_tamper_debounce_seq {
-	/** Tamper input detect edge with synchronous stability debounce */
-	RTC_TAMPER_DEBOUNCE_SYNC,
-	/** Tamper input detect edge with asynchronous stability debounce */
-	RTC_TAMPER_DEBOUNCE_ASYNC,
-	/** Tamper input detect edge with majority debounce */
-	RTC_TAMPER_DEBOUNCE_MAJORITY,
+    /** Tamper input detect edge with synchronous stability debounce */
+    RTC_TAMPER_DEBOUNCE_SYNC,
+    /** Tamper input detect edge with asynchronous stability debounce */
+    RTC_TAMPER_DEBOUNCE_ASYNC,
+    /** Tamper input detect edge with majority debounce */
+    RTC_TAMPER_DEBOUNCE_MAJORITY,
 };
 
 /**
@@ -192,12 +192,12 @@ enum rtc_tamper_debounce_seq {
  * The configuration structure for tamper INn.
  */
 struct rtc_tamper_input_config {
-	/** Debounce enable */
-	bool debounce_enable;
-	/** Tamper level select */
-	enum rtc_tamper_level_sel level;
-	/** Tamper input action */
-	enum rtc_tamper_input_action action;
+    /** Debounce enable */
+    bool debounce_enable;
+    /** Tamper level select */
+    enum rtc_tamper_level_sel level;
+    /** Tamper input action */
+    enum rtc_tamper_input_action action;
 };
 
 /**
@@ -208,22 +208,22 @@ struct rtc_tamper_input_config {
  * user configurations are set.
  */
 struct rtc_tamper_config {
-	/** Backup register reset on tamper enable */
-	bool bkup_reset_on_tamper;
-	/** GP register reset on tamper enable */
-	bool gp_reset_on_tamper;
-	/** Active layer frequency */
-	enum rtc_tamper_active_layer_freq_divider actl_freq_div;
-	/** Debounce frequency */
-	enum rtc_tamper_debounce_freq_divider deb_freq_div;
-	/** Debounce sequential */
-	enum rtc_tamper_debounce_seq deb_seq;
-	/** DMA on tamper enable */
-	bool dma_tamper_enable;
-	/** General Purpose 0/1 Enable */
-	bool gp0_enable;
-	/** Tamper IN configuration */
-	struct rtc_tamper_input_config in_cfg[RTC_TAMPER_NUM];
+    /** Backup register reset on tamper enable */
+    bool bkup_reset_on_tamper;
+    /** GP register reset on tamper enable */
+    bool gp_reset_on_tamper;
+    /** Active layer frequency */
+    enum rtc_tamper_active_layer_freq_divider actl_freq_div;
+    /** Debounce frequency */
+    enum rtc_tamper_debounce_freq_divider deb_freq_div;
+    /** Debounce sequential */
+    enum rtc_tamper_debounce_seq deb_seq;
+    /** DMA on tamper enable */
+    bool dma_tamper_enable;
+    /** General Purpose 0/1 Enable */
+    bool gp0_enable;
+    /** Tamper IN configuration */
+    struct rtc_tamper_input_config in_cfg[RTC_TAMPER_NUM];
 };
 
 /**
@@ -234,7 +234,7 @@ struct rtc_tamper_config {
 /**
  *  \brief Gets the RTC tamper default configurations.
  *
- *  Initializes the configuration structure to default values. 
+ *  Initializes the configuration structure to default values.
  *
  *  The default configuration is as follows:
  *  - Disable backup register reset on tamper
@@ -249,27 +249,28 @@ struct rtc_tamper_config {
  *  \param[out] config Configuration structure to be initialized to default values.
  */
 static inline void rtc_tamper_get_config_defaults(
-		struct rtc_tamper_config *const config)
+        struct rtc_tamper_config *const config)
 {
-	/* Sanity check argument */
-	Assert(config);
-
-	config->bkup_reset_on_tamper= false;
-	config->gp_reset_on_tamper  = false;
-	config->actl_freq_div       = RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8;
-	config->deb_freq_div        = RTC_TAMPER_DEBOUNCE_FREQ_DIV_8;
-	config->deb_seq             = RTC_TAMPER_DEBOUNCE_SYNC;
-	config->dma_tamper_enable   = false;
-	config->gp0_enable          = true;
-
-	for (uint8_t id = 0; id < RTC_TAMPER_NUM; id++) {
-		config->in_cfg[id].debounce_enable = false;
-		config->in_cfg[id].level = RTC_TAMPER_LEVEL_FALLING;
-		config->in_cfg[id].action = RTC_TAMPER_INPUT_ACTION_OFF;
-	}
+    /* Sanity check argument */
+    Assert(config);
+
+    config->bkup_reset_on_tamper= false;
+    config->gp_reset_on_tamper  = false;
+    config->actl_freq_div       = RTC_TAMPER_ACTIVE_LAYER_FREQ_DIV_8;
+    config->deb_freq_div        = RTC_TAMPER_DEBOUNCE_FREQ_DIV_8;
+    config->deb_seq             = RTC_TAMPER_DEBOUNCE_SYNC;
+    config->dma_tamper_enable   = false;
+    config->gp0_enable          = true;
+
+    for (uint8_t id = 0; id < RTC_TAMPER_NUM; id++)
+    {
+        config->in_cfg[id].debounce_enable = false;
+        config->in_cfg[id].level = RTC_TAMPER_LEVEL_FALLING;
+        config->in_cfg[id].action = RTC_TAMPER_INPUT_ACTION_OFF;
+    }
 }
 enum status_code rtc_tamper_set_config (struct rtc_module *const module,
-		struct rtc_tamper_config *const tamper_cfg);
+        struct rtc_tamper_config *const tamper_cfg);
 
 /**
  * \brief Retrieves the RTC tamper detection status.
@@ -289,38 +290,44 @@ enum status_code rtc_tamper_set_config (struct rtc_module *const module,
  */
 static inline uint32_t rtc_tamper_get_detect_flag (struct rtc_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	uint32_t tamper_id = module->hw->MODE0.TAMPID.reg;
-	uint32_t detect_flags = 0;
-
-	if (tamper_id & RTC_TAMPID_TAMPID0) {
-		detect_flags |= RTC_TAMPER_DETECT_ID0;
-	}
-
-	if (tamper_id & RTC_TAMPID_TAMPID1) {
-		detect_flags |= RTC_TAMPER_DETECT_ID1;
-	}
-
-	if (tamper_id & RTC_TAMPID_TAMPID2) {
-		detect_flags |= RTC_TAMPER_DETECT_ID2;
-	}
-
-	if (tamper_id & RTC_TAMPID_TAMPID3) {
-		detect_flags |= RTC_TAMPER_DETECT_ID3;
-	}
-
-	if (tamper_id & RTC_TAMPID_TAMPID4) {
-		detect_flags |= RTC_TAMPER_DETECT_ID4;
-	}
-
-	if (tamper_id & RTC_TAMPID_TAMPEVT) {
-		detect_flags |= RTC_TAMPER_DETECT_EVT;
-	}
-
-	return detect_flags;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    uint32_t tamper_id = module->hw->MODE0.TAMPID.reg;
+    uint32_t detect_flags = 0;
+
+    if (tamper_id & RTC_TAMPID_TAMPID0)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_ID0;
+    }
+
+    if (tamper_id & RTC_TAMPID_TAMPID1)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_ID1;
+    }
+
+    if (tamper_id & RTC_TAMPID_TAMPID2)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_ID2;
+    }
+
+    if (tamper_id & RTC_TAMPID_TAMPID3)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_ID3;
+    }
+
+    if (tamper_id & RTC_TAMPID_TAMPID4)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_ID4;
+    }
+
+    if (tamper_id & RTC_TAMPID_TAMPEVT)
+    {
+        detect_flags |= RTC_TAMPER_DETECT_EVT;
+    }
+
+    return detect_flags;
 }
 
 /**
@@ -332,40 +339,46 @@ static inline uint32_t rtc_tamper_get_detect_flag (struct rtc_module *const modu
  * \param[in] detect_flags  Bitmask of detection flags
  */
 static inline void rtc_tamper_clear_detect_flag(
-		struct rtc_module *const module,
-		const uint32_t detect_flags)
+        struct rtc_module *const module,
+        const uint32_t detect_flags)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	uint32_t tamper_id = 0;
+    uint32_t tamper_id = 0;
 
-	if (detect_flags & RTC_TAMPER_DETECT_ID0) {
-		tamper_id |= RTC_TAMPID_TAMPID0;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_ID0)
+    {
+        tamper_id |= RTC_TAMPID_TAMPID0;
+    }
 
-	if (detect_flags & RTC_TAMPER_DETECT_ID1) {
-		tamper_id |= RTC_TAMPID_TAMPID1;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_ID1)
+    {
+        tamper_id |= RTC_TAMPID_TAMPID1;
+    }
 
-	if (detect_flags & RTC_TAMPER_DETECT_ID2) {
-		tamper_id |= RTC_TAMPID_TAMPID2;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_ID2)
+    {
+        tamper_id |= RTC_TAMPID_TAMPID2;
+    }
 
-	if (detect_flags & RTC_TAMPER_DETECT_ID3) {
-		tamper_id |= RTC_TAMPID_TAMPID3;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_ID3)
+    {
+        tamper_id |= RTC_TAMPID_TAMPID3;
+    }
 
-	if (detect_flags & RTC_TAMPER_DETECT_ID4) {
-		tamper_id |= RTC_TAMPID_TAMPID4;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_ID4)
+    {
+        tamper_id |= RTC_TAMPID_TAMPID4;
+    }
 
-	if (detect_flags & RTC_TAMPER_DETECT_EVT) {
-		tamper_id |= RTC_TAMPID_TAMPEVT;
-	}
+    if (detect_flags & RTC_TAMPER_DETECT_EVT)
+    {
+        tamper_id |= RTC_TAMPID_TAMPEVT;
+    }
 
-	module->hw->MODE0.TAMPID.reg = tamper_id;
+    module->hw->MODE0.TAMPID.reg = tamper_id;
 
 }
 
@@ -375,4 +388,4 @@ static inline void rtc_tamper_clear_detect_flag(
 /** @} */
 
 
-#endif /* RTC_TAMPER_H_INCLUDED */
\ No newline at end of file
+#endif /* RTC_TAMPER_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c
index ef868a51a6c5..ce48395b83f1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.c
@@ -57,35 +57,35 @@
 */
 static inline void _sdadc_configure_ain_pin(uint32_t pin)
 {
-	/* Pinmapping table for AINxx -> GPIO pin number */
-	const uint32_t pinmapping[] = {
+    /* Pinmapping table for AINxx -> GPIO pin number */
+    const uint32_t pinmapping[] = {
 #if (SAMC21E)
-			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+            PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
 #elif (SAMC21G)
-			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
-			PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
+            PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+            PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
 #elif (SAMC21J)
-			PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
-			PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
-			PIN_PB06B_SDADC_INN2, PIN_PB07B_SDADC_INP2,
+            PIN_PA06B_SDADC_INN0, PIN_PA07B_SDADC_INP0,
+            PIN_PB08B_SDADC_INN1, PIN_PB09B_SDADC_INP1,
+            PIN_PB06B_SDADC_INN2, PIN_PB07B_SDADC_INP2,
 #else
 #  error SDADC pin mappings are not defined for this device.
 #endif
-	};
+    };
 
-	uint32_t pin_map_result;
+    uint32_t pin_map_result;
 
-	struct system_pinmux_config config;
-	system_pinmux_get_config_defaults(&config);
+    struct system_pinmux_config config;
+    system_pinmux_get_config_defaults(&config);
 
-	config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
-	config.mux_position = 1;
+    config.input_pull   = SYSTEM_PINMUX_PIN_PULL_NONE;
+    config.mux_position = 1;
 
-	pin_map_result = pinmapping[pin * 2];
-	system_pinmux_pin_set_config(pin_map_result, &config);
+    pin_map_result = pinmapping[pin * 2];
+    system_pinmux_pin_set_config(pin_map_result, &config);
 
-	pin_map_result = pinmapping[pin * 2 + 1];
-	system_pinmux_pin_set_config(pin_map_result, &config);
+    pin_map_result = pinmapping[pin * 2 + 1];
+    system_pinmux_pin_set_config(pin_map_result, &config);
 }
 
 /**
@@ -101,144 +101,159 @@ static inline void _sdadc_configure_ain_pin(uint32_t pin)
  * \retval STATUS_ERR_INVALID_ARG  Invalid argument(s) were provided
  */
 static enum status_code _sdadc_set_config(
-		struct sdadc_module *const module_inst,
-		struct sdadc_config *const config)
+        struct sdadc_module *const module_inst,
+        struct sdadc_config *const config)
 {
-	/* Get the hardware module pointer */
-	Sdadc *const sdadc_module = module_inst->hw;
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(SDADC_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(SDADC_GCLK_ID);
-
-	/* Setup pinmuxing for analog inputs */
-	_sdadc_configure_ain_pin(config->mux_input);
-
-	/* Configure run in standby */
-	sdadc_module->CTRLA.reg = (config->run_in_standby << SDADC_CTRLA_RUNSTDBY_Pos)
-			| (config->on_command << SDADC_CTRLA_ONDEMAND_Pos);
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure reference */
-	sdadc_module->REFCTRL.reg = (config->reference.ref_sel) | (config->reference.ref_range) |
-						(config->reference.on_ref_buffer << SDADC_REFCTRL_ONREFBUF_Pos);
-
-	/* Configure CTRLB */
-	sdadc_module->CTRLB.reg =
-			(config->skip_count << SDADC_CTRLB_SKPCNT_Pos) |
-			(config->clock_prescaler / 2 - 1) | config->osr;
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure CTRLC */
-	sdadc_module->CTRLC.reg =
-			(config->freerunning << SDADC_CTRLC_FREERUN_Pos);
-
-	/* Configure SEQCTRL */
-	sdadc_module->SEQCTRL.reg =
-			(config->seq_enable[0]) | (config->seq_enable[1] << 1) | (config->seq_enable[2] << 2);
-
-	/* Check validity of window thresholds */
-	if (config->window.window_mode != SDADC_WINDOW_MODE_DISABLE) {
-		if (config->window.window_lower_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
-			config->window.window_lower_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1) ||
-			config->window.window_upper_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
-			config->window.window_upper_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1)) {
-			/* Invalid value */
-			return STATUS_ERR_INVALID_ARG;
-		} else if (config->window.window_lower_value > (int32_t)SDADC_RESULT_RESULT_Msk ||
-				config->window.window_upper_value > (int32_t)SDADC_RESULT_RESULT_Msk){
-			/* Invalid value */
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure window mode */
-	sdadc_module->WINCTRL.reg = config->window.window_mode;
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	sdadc_module->WINLT.reg =
-			config->window.window_lower_value << SDADC_WINLT_WINLT_Pos;
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure lower threshold */
-	sdadc_module->WINUT.reg = config->window.window_upper_value <<
-			SDADC_WINUT_WINUT_Pos;
-
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
-
-	/* Configure pin scan mode and positive and negative input pins */
-	sdadc_module->INPUTCTRL.reg = config->mux_input;
-
-	/* Configure events */
-	sdadc_module->EVCTRL.reg = config->event_action;
-
-	/* Disable all interrupts */
-	sdadc_module->INTENCLR.reg = (1 << SDADC_INTENCLR_WINMON_Pos) |
-			(1 << SDADC_INTENCLR_OVERRUN_Pos) | (1 << SDADC_INTENCLR_RESRDY_Pos);
-
-	/* Make sure offset correction value is valid */
-	if (config->correction.offset_correction > (int32_t)(SDADC_OFFSETCORR_MASK / 2) ||
-		config->correction.offset_correction < - (int32_t)(SDADC_OFFSETCORR_MASK / 2 + 1)) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		while (sdadc_is_syncing(module_inst)) {
-			/* Wait for synchronization */
-		}
-
-		/* Set offset correction value */
-		sdadc_module->OFFSETCORR.reg = config->correction.offset_correction <<
-				SDADC_OFFSETCORR_OFFSETCORR_Pos;
-	}
-
-	/* Make sure gain_correction value is valid */
-	if (config->correction.gain_correction > SDADC_GAINCORR_MASK) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		while (sdadc_is_syncing(module_inst)) {
-			/* Wait for synchronization */
-		}
-
-		/* Set gain correction value */
-		sdadc_module->GAINCORR.reg = config->correction.gain_correction <<
-				SDADC_GAINCORR_GAINCORR_Pos;
-	}
-
-	/* Make sure shift_correction value is valid */
-	if (config->correction.shift_correction > SDADC_SHIFTCORR_MASK) {
-		return STATUS_ERR_INVALID_ARG;
-	} else {
-		while (sdadc_is_syncing(module_inst)) {
-			/* Wait for synchronization */
-		}
-
-		/* Set shift correction value */
-		sdadc_module->SHIFTCORR.reg = config->correction.shift_correction <<
-				SDADC_SHIFTCORR_SHIFTCORR_Pos;
-	}
-
-	return STATUS_OK;
+    /* Get the hardware module pointer */
+    Sdadc *const sdadc_module = module_inst->hw;
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(SDADC_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(SDADC_GCLK_ID);
+
+    /* Setup pinmuxing for analog inputs */
+    _sdadc_configure_ain_pin(config->mux_input);
+
+    /* Configure run in standby */
+    sdadc_module->CTRLA.reg = (config->run_in_standby << SDADC_CTRLA_RUNSTDBY_Pos)
+            | (config->on_command << SDADC_CTRLA_ONDEMAND_Pos);
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure reference */
+    sdadc_module->REFCTRL.reg = (config->reference.ref_sel) | (config->reference.ref_range) |
+                        (config->reference.on_ref_buffer << SDADC_REFCTRL_ONREFBUF_Pos);
+
+    /* Configure CTRLB */
+    sdadc_module->CTRLB.reg =
+            (config->skip_count << SDADC_CTRLB_SKPCNT_Pos) |
+            (config->clock_prescaler / 2 - 1) | config->osr;
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure CTRLC */
+    sdadc_module->CTRLC.reg =
+            (config->freerunning << SDADC_CTRLC_FREERUN_Pos);
+
+    /* Configure SEQCTRL */
+    sdadc_module->SEQCTRL.reg =
+            (config->seq_enable[0]) | (config->seq_enable[1] << 1) | (config->seq_enable[2] << 2);
+
+    /* Check validity of window thresholds */
+    if (config->window.window_mode != SDADC_WINDOW_MODE_DISABLE)
+    {
+        if (config->window.window_lower_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
+            config->window.window_lower_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1) ||
+            config->window.window_upper_value > (int32_t)(SDADC_RESULT_RESULT_Msk / 2) ||
+            config->window.window_upper_value < -(int32_t)(SDADC_RESULT_RESULT_Msk / 2 + 1))
+            {
+            /* Invalid value */
+            return STATUS_ERR_INVALID_ARG;
+        } else if (config->window.window_lower_value > (int32_t)SDADC_RESULT_RESULT_Msk ||
+                config->window.window_upper_value > (int32_t)SDADC_RESULT_RESULT_Msk)
+                {
+            /* Invalid value */
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure window mode */
+    sdadc_module->WINCTRL.reg = config->window.window_mode;
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    sdadc_module->WINLT.reg =
+            config->window.window_lower_value << SDADC_WINLT_WINLT_Pos;
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure lower threshold */
+    sdadc_module->WINUT.reg = config->window.window_upper_value <<
+            SDADC_WINUT_WINUT_Pos;
+
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
+
+    /* Configure pin scan mode and positive and negative input pins */
+    sdadc_module->INPUTCTRL.reg = config->mux_input;
+
+    /* Configure events */
+    sdadc_module->EVCTRL.reg = config->event_action;
+
+    /* Disable all interrupts */
+    sdadc_module->INTENCLR.reg = (1 << SDADC_INTENCLR_WINMON_Pos) |
+            (1 << SDADC_INTENCLR_OVERRUN_Pos) | (1 << SDADC_INTENCLR_RESRDY_Pos);
+
+    /* Make sure offset correction value is valid */
+    if (config->correction.offset_correction > (int32_t)(SDADC_OFFSETCORR_MASK / 2) ||
+        config->correction.offset_correction < - (int32_t)(SDADC_OFFSETCORR_MASK / 2 + 1))
+        {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        while (sdadc_is_syncing(module_inst))
+        {
+            /* Wait for synchronization */
+        }
+
+        /* Set offset correction value */
+        sdadc_module->OFFSETCORR.reg = config->correction.offset_correction <<
+                SDADC_OFFSETCORR_OFFSETCORR_Pos;
+    }
+
+    /* Make sure gain_correction value is valid */
+    if (config->correction.gain_correction > SDADC_GAINCORR_MASK)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        while (sdadc_is_syncing(module_inst))
+        {
+            /* Wait for synchronization */
+        }
+
+        /* Set gain correction value */
+        sdadc_module->GAINCORR.reg = config->correction.gain_correction <<
+                SDADC_GAINCORR_GAINCORR_Pos;
+    }
+
+    /* Make sure shift_correction value is valid */
+    if (config->correction.shift_correction > SDADC_SHIFTCORR_MASK)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    } else {
+        while (sdadc_is_syncing(module_inst))
+        {
+            /* Wait for synchronization */
+        }
+
+        /* Set shift correction value */
+        sdadc_module->SHIFTCORR.reg = config->correction.shift_correction <<
+                SDADC_SHIFTCORR_SHIFTCORR_Pos;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -258,54 +273,58 @@ static enum status_code _sdadc_set_config(
  * \retval STATUS_ERR_DENIED        The module is enabled
  */
 enum status_code sdadc_init(
-		struct sdadc_module *const module_inst,
-		Sdadc *hw,
-		struct sdadc_config *config)
+        struct sdadc_module *const module_inst,
+        Sdadc *hw,
+        struct sdadc_config *config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
 
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SDADC);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SDADC);
 
-	if (hw->CTRLA.reg & SDADC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
+    if (hw->CTRLA.reg & SDADC_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
 
-	if (hw->CTRLA.reg & SDADC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
+    if (hw->CTRLA.reg & SDADC_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
 
-	/* Store the selected reference for later use */
-	module_inst->reference = config->reference;
+    /* Store the selected reference for later use */
+    module_inst->reference = config->reference;
 
 #if SDADC_CALLBACK_MODE == true
-	for (uint8_t i = 0; i < SDADC_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	};
-
-	module_inst->registered_callback_mask = 0;
-	module_inst->enabled_callback_mask = 0;
-	module_inst->remaining_conversions = 0;
-	module_inst->job_status = STATUS_OK;
-
-	_sdadc_instances[0] = module_inst;
-
-	if (config->event_action == SDADC_EVENT_ACTION_DISABLED &&
-			!config->freerunning) {
-		module_inst->software_trigger = true;
-	} else {
-		module_inst->software_trigger = false;
-	}
+    for (uint8_t i = 0; i < SDADC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    };
+
+    module_inst->registered_callback_mask = 0;
+    module_inst->enabled_callback_mask = 0;
+    module_inst->remaining_conversions = 0;
+    module_inst->job_status = STATUS_OK;
+
+    _sdadc_instances[0] = module_inst;
+
+    if (config->event_action == SDADC_EVENT_ACTION_DISABLED &&
+            !config->freerunning)
+            {
+        module_inst->software_trigger = true;
+    } else {
+        module_inst->software_trigger = false;
+    }
 #endif
 
-	/* Write configuration to module */
-	return _sdadc_set_config(module_inst, config);
+    /* Write configuration to module */
+    return _sdadc_set_config(module_inst, config);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h
index ad42c9a22e78..4c9d09bb0c70 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc.h
@@ -114,7 +114,9 @@
  * A specific offset, gain, and shift can be applied to each source of the SDADC
  * by performing the following operation:
  * \f[
- * Data = (Data_{0} + OFFSET) \times \frac {GAIN}{2^{SHIFT}}
+ * Data = (Data_{0} + OFFSET)\times \frac {GAIN}
+ {2^
+ {SHIFT}}
  * \f]
  *
  *
@@ -195,15 +197,15 @@ typedef void (*sdadc_callback_t)(const struct sdadc_module *const module);
  *
  */
 enum sdadc_callback {
-	/** Callback for buffer received */
-	SDADC_CALLBACK_READ_BUFFER,
-	/** Callback when window is hit */
-	SDADC_CALLBACK_WINDOW,
-	/** Callback for error */
-	SDADC_CALLBACK_ERROR,
+    /** Callback for buffer received */
+    SDADC_CALLBACK_READ_BUFFER,
+    /** Callback when window is hit */
+    SDADC_CALLBACK_WINDOW,
+    /** Callback for error */
+    SDADC_CALLBACK_ERROR,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	SDADC_CALLBACK_N,
+    /** Number of available callbacks */
+    SDADC_CALLBACK_N,
 #  endif
 };
 
@@ -234,14 +236,14 @@ enum sdadc_callback {
  *
  */
 enum sdadc_reference_select {
-	/** Internal Bandgap Reference */
-	SDADC_REFERENCE_INTREF = SDADC_REFCTRL_REFSEL(0),
-	/** External reference B */
-	SDADC_REFERENCE_AREFB  = SDADC_REFCTRL_REFSEL(1),
-	/** DACOUT */
-	SDADC_REFERENCE_DACOUT = SDADC_REFCTRL_REFSEL(2),
-	/** VDDANA */
-	SDADC_REFERENCE_INTVCC = SDADC_REFCTRL_REFSEL(3),
+    /** Internal Bandgap Reference */
+    SDADC_REFERENCE_INTREF = SDADC_REFCTRL_REFSEL(0),
+    /** External reference B */
+    SDADC_REFERENCE_AREFB  = SDADC_REFCTRL_REFSEL(1),
+    /** DACOUT */
+    SDADC_REFERENCE_DACOUT = SDADC_REFCTRL_REFSEL(2),
+    /** VDDANA */
+    SDADC_REFERENCE_INTVCC = SDADC_REFCTRL_REFSEL(3),
 };
 
 /**
@@ -251,14 +253,14 @@ enum sdadc_reference_select {
  *
  */
 enum sdadc_reference_range {
-	/** Vref < 1.4V */
-	SDADC_REFRANGE_0 = SDADC_REFCTRL_REFRANGE(0),
-	/** 1.4V < Vref < 2.4V */
-	SDADC_REFRANGE_1 = SDADC_REFCTRL_REFRANGE(1),
-	/** 2.4V < Vref < 3.6V */
-	SDADC_REFRANGE_2 = SDADC_REFCTRL_REFRANGE(2),
-	/** Vref > 3.6V */
-	SDADC_REFRANGE_3 = SDADC_REFCTRL_REFRANGE(3),
+    /** Vref < 1.4V */
+    SDADC_REFRANGE_0 = SDADC_REFCTRL_REFRANGE(0),
+    /** 1.4V < Vref < 2.4V */
+    SDADC_REFRANGE_1 = SDADC_REFCTRL_REFRANGE(1),
+    /** 2.4V < Vref < 3.6V */
+    SDADC_REFRANGE_2 = SDADC_REFCTRL_REFRANGE(2),
+    /** Vref > 3.6V */
+    SDADC_REFRANGE_3 = SDADC_REFCTRL_REFRANGE(3),
 };
 
 /**
@@ -268,16 +270,16 @@ enum sdadc_reference_range {
  *
  */
 enum sdadc_over_sampling_ratio {
-	/** SDADC over Sampling Ratio is 64 */
-	SDADC_OVER_SAMPLING_RATIO64    = SDADC_CTRLB_OSR(0),
-	/** SDADC over Sampling Ratio is 128 */
-	SDADC_OVER_SAMPLING_RATIO128   = SDADC_CTRLB_OSR(1),
-	/** SDADC over Sampling Ratio is 256 */
-	SDADC_OVER_SAMPLING_RATIO256   = SDADC_CTRLB_OSR(2),
-	/** SDADC over Sampling Ratio is 512 */
-	SDADC_OVER_SAMPLING_RATIO512   = SDADC_CTRLB_OSR(3),
-	/** SDADC over Sampling Ratio is 1024 */
-	SDADC_OVER_SAMPLING_RATIO1024  = SDADC_CTRLB_OSR(4),
+    /** SDADC over Sampling Ratio is 64 */
+    SDADC_OVER_SAMPLING_RATIO64    = SDADC_CTRLB_OSR(0),
+    /** SDADC over Sampling Ratio is 128 */
+    SDADC_OVER_SAMPLING_RATIO128   = SDADC_CTRLB_OSR(1),
+    /** SDADC over Sampling Ratio is 256 */
+    SDADC_OVER_SAMPLING_RATIO256   = SDADC_CTRLB_OSR(2),
+    /** SDADC over Sampling Ratio is 512 */
+    SDADC_OVER_SAMPLING_RATIO512   = SDADC_CTRLB_OSR(3),
+    /** SDADC over Sampling Ratio is 1024 */
+    SDADC_OVER_SAMPLING_RATIO1024  = SDADC_CTRLB_OSR(4),
 };
 
 /**
@@ -287,16 +289,16 @@ enum sdadc_over_sampling_ratio {
  *
  */
 enum sdadc_window_mode {
-	/** No window mode */
-	SDADC_WINDOW_MODE_DISABLE          = SDADC_WINCTRL_WINMODE(0),
-	/** RESULT > WINLT */
-	SDADC_WINDOW_MODE_ABOVE            = SDADC_WINCTRL_WINMODE(1),
-	/** RESULT < WINUT */
-	SDADC_WINDOW_MODE_BELOW            = SDADC_WINCTRL_WINMODE(2),
-	/** WINLT < RESULT < WINUT */
-	SDADC_WINDOW_MODE_INSIDE           = SDADC_WINCTRL_WINMODE(3),
-	/** !(WINLT < RESULT < WINUT) */
-	SDADC_WINDOW_MODE_OUTSIDE          = SDADC_WINCTRL_WINMODE(4),
+    /** No window mode */
+    SDADC_WINDOW_MODE_DISABLE          = SDADC_WINCTRL_WINMODE(0),
+    /** RESULT > WINLT */
+    SDADC_WINDOW_MODE_ABOVE            = SDADC_WINCTRL_WINMODE(1),
+    /** RESULT < WINUT */
+    SDADC_WINDOW_MODE_BELOW            = SDADC_WINCTRL_WINMODE(2),
+    /** WINLT < RESULT < WINUT */
+    SDADC_WINDOW_MODE_INSIDE           = SDADC_WINCTRL_WINMODE(3),
+    /** !(WINLT < RESULT < WINUT) */
+    SDADC_WINDOW_MODE_OUTSIDE          = SDADC_WINCTRL_WINMODE(4),
 };
 
 /**
@@ -306,12 +308,12 @@ enum sdadc_window_mode {
  *
  */
 enum sdadc_event_action {
-	/** Event action disabled */
-	SDADC_EVENT_ACTION_DISABLED         = 0,
-	/** Flush SDADC and start conversion */
-	SDADC_EVENT_ACTION_FLUSH_START_CONV = SDADC_EVCTRL_FLUSHEI,
-	/** Start conversion */
-	SDADC_EVENT_ACTION_START_CONV       = SDADC_EVCTRL_STARTEI,
+    /** Event action disabled */
+    SDADC_EVENT_ACTION_DISABLED         = 0,
+    /** Flush SDADC and start conversion */
+    SDADC_EVENT_ACTION_FLUSH_START_CONV = SDADC_EVCTRL_FLUSHEI,
+    /** Start conversion */
+    SDADC_EVENT_ACTION_START_CONV       = SDADC_EVCTRL_STARTEI,
 };
 
 /**
@@ -321,12 +323,12 @@ enum sdadc_event_action {
  *
  */
 enum sdadc_mux_input {
-	/** Select SDADC AINN0 and AINP0 pins */
-	SDADC_MUX_INPUT_AIN0    = SDADC_INPUTCTRL_MUXSEL_AIN0,
-	/** Select SDADC AINN1 and AINP1 pins */
-	SDADC_MUX_INPUT_AIN1    = SDADC_INPUTCTRL_MUXSEL_AIN1,
-	/** Select SDADC AINN2 and AINP2 pins */
-	SDADC_MUX_INPUT_AIN2    = SDADC_INPUTCTRL_MUXSEL_AIN2,
+    /** Select SDADC AINN0 and AINP0 pins */
+    SDADC_MUX_INPUT_AIN0    = SDADC_INPUTCTRL_MUXSEL_AIN0,
+    /** Select SDADC AINN1 and AINP1 pins */
+    SDADC_MUX_INPUT_AIN1    = SDADC_INPUTCTRL_MUXSEL_AIN1,
+    /** Select SDADC AINN2 and AINP2 pins */
+    SDADC_MUX_INPUT_AIN2    = SDADC_INPUTCTRL_MUXSEL_AIN2,
 };
 
 #if SDADC_CALLBACK_MODE == true
@@ -334,12 +336,12 @@ enum sdadc_mux_input {
  * Enum for the possible SDADC interrupt flags.
  */
 enum sdadc_interrupt_flag {
-	/** SDADC result ready */
-	SDADC_INTERRUPT_RESULT_READY = SDADC_INTFLAG_RESRDY,
-	/** SDADC result overwritten before read */
-	SDADC_INTERRUPT_OVERRUN      = SDADC_INTFLAG_OVERRUN,
-	/** Window monitor match */
-	SDADC_INTERRUPT_WINDOW       = SDADC_INTFLAG_WINMON,
+    /** SDADC result ready */
+    SDADC_INTERRUPT_RESULT_READY = SDADC_INTFLAG_RESRDY,
+    /** SDADC result overwritten before read */
+    SDADC_INTERRUPT_OVERRUN      = SDADC_INTFLAG_OVERRUN,
+    /** Window monitor match */
+    SDADC_INTERRUPT_WINDOW       = SDADC_INTFLAG_WINMON,
 };
 #endif
 
@@ -349,12 +351,12 @@ enum sdadc_interrupt_flag {
  * Reference configuration structure.
  */
 struct sdadc_reference {
-	/** Reference voltage selection */
-	enum sdadc_reference_select ref_sel;
-	/** Reference voltage range */
-	enum sdadc_reference_select ref_range;
-	/** Reference buffer turning switch */
-	bool on_ref_buffer;
+    /** Reference voltage selection */
+    enum sdadc_reference_select ref_sel;
+    /** Reference voltage range */
+    enum sdadc_reference_select ref_range;
+    /** Reference buffer turning switch */
+    bool on_ref_buffer;
 };
 
 /**
@@ -363,12 +365,12 @@ struct sdadc_reference {
  * Window monitor configuration structure.
  */
 struct sdadc_window_config {
-	/** Selected window mode */
-	enum sdadc_window_mode window_mode;
-	/** Lower window value */
-	int32_t window_lower_value;
-	/** Upper window value */
-	int32_t window_upper_value;
+    /** Selected window mode */
+    enum sdadc_window_mode window_mode;
+    /** Lower window value */
+    int32_t window_lower_value;
+    /** Upper window value */
+    int32_t window_upper_value;
 };
 
 /**
@@ -378,10 +380,10 @@ struct sdadc_window_config {
  * disable events via \ref sdadc_enable_events() and \ref sdadc_disable_events().
  */
 struct sdadc_events {
-	/** Enable event generation on conversion done */
-	bool generate_event_on_conversion_done;
-	/** Enable event generation on window monitor */
-	bool generate_event_on_window_monitor;
+    /** Enable event generation on conversion done */
+    bool generate_event_on_conversion_done;
+    /** Enable event generation on window monitor */
+    bool generate_event_on_window_monitor;
 };
 
 /**
@@ -392,12 +394,12 @@ struct sdadc_events {
  * \ref sdadc_get_config_defaults.
  */
 struct sdadc_correction_config {
-	/** Offset correction */
-	int32_t offset_correction;
-	/** Gain correction */
-	uint16_t gain_correction;
-	/** Shift correction */
-	uint8_t shift_correction;
+    /** Offset correction */
+    int32_t offset_correction;
+    /** Gain correction */
+    uint16_t gain_correction;
+    /** Shift correction */
+    uint8_t shift_correction;
 };
 
 /**
@@ -408,32 +410,32 @@ struct sdadc_correction_config {
  * function before being modified by the user application.
  */
 struct sdadc_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Voltage reference */
-	struct sdadc_reference reference;
-	/** Over sampling ratio */
-	enum sdadc_over_sampling_ratio osr;
-	/** Clock prescaler */
-	uint8_t clock_prescaler;
-	/** Skip Count */
-	uint8_t skip_count;
-	/** MUX input */
-	enum sdadc_mux_input mux_input;
-	/** Enables free running mode if true */
-	bool freerunning;
-	/** Enables SDADC in standby sleep mode if true */
-	bool run_in_standby;
-	/** Enables SDADC depend on other peripheral if true */
-	bool on_command;
-	/** Enables positive input in the sequence if true */
-	bool seq_enable[3];
-	/** Window monitor configuration structure */
-	struct sdadc_window_config window;
-	/** Gain and offset correction configuration structure */
-	struct sdadc_correction_config correction;
-	/** Event action to take on incoming event */
-	enum sdadc_event_action event_action;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** Voltage reference */
+    struct sdadc_reference reference;
+    /** Over sampling ratio */
+    enum sdadc_over_sampling_ratio osr;
+    /** Clock prescaler */
+    uint8_t clock_prescaler;
+    /** Skip Count */
+    uint8_t skip_count;
+    /** MUX input */
+    enum sdadc_mux_input mux_input;
+    /** Enables free running mode if true */
+    bool freerunning;
+    /** Enables SDADC in standby sleep mode if true */
+    bool run_in_standby;
+    /** Enables SDADC depend on other peripheral if true */
+    bool on_command;
+    /** Enables positive input in the sequence if true */
+    bool seq_enable[3];
+    /** Window monitor configuration structure */
+    struct sdadc_window_config window;
+    /** Gain and offset correction configuration structure */
+    struct sdadc_correction_config correction;
+    /** Event action to take on incoming event */
+    enum sdadc_event_action event_action;
 };
 
 /**
@@ -447,25 +449,25 @@ struct sdadc_config {
  */
 struct sdadc_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to SDADC hardware module */
-	Sdadc *hw;
-	/** Keep reference configuration so we know when enable is called */
-	struct sdadc_reference reference;
+    /** Pointer to SDADC hardware module */
+    Sdadc *hw;
+    /** Keep reference configuration so we know when enable is called */
+    struct sdadc_reference reference;
 #  if SDADC_CALLBACK_MODE == true
-	/** Array to store callback functions */
-	sdadc_callback_t callback[SDADC_CALLBACK_N];
-	/** Pointer to buffer used for SDADC results */
-	volatile int32_t *job_buffer;
-	/** Remaining number of conversions in current job */
-	volatile uint16_t remaining_conversions;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback_mask;
-	/** Holds the status of the ongoing or last conversion job */
-	volatile enum status_code job_status;
-	/** If software triggering is needed */
-	bool software_trigger;
+    /** Array to store callback functions */
+    sdadc_callback_t callback[SDADC_CALLBACK_N];
+    /** Pointer to buffer used for SDADC results */
+    volatile int32_t *job_buffer;
+    /** Remaining number of conversions in current job */
+    volatile uint16_t remaining_conversions;
+    /** Bit mask for callbacks registered */
+    uint8_t registered_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enabled_callback_mask;
+    /** Holds the status of the ongoing or last conversion job */
+    volatile enum status_code job_status;
+    /** If software triggering is needed */
+    bool software_trigger;
 #  endif
 #endif
 };
@@ -475,9 +477,9 @@ struct sdadc_module {
  * @{
  */
 enum status_code sdadc_init(
-		struct sdadc_module *const module_inst,
-		Sdadc *hw,
-		struct sdadc_config *config);
+        struct sdadc_module *const module_inst,
+        Sdadc *hw,
+        struct sdadc_config *config);
 
 /**
  * \brief Initializes an SDADC configuration structure to defaults.
@@ -506,28 +508,28 @@ enum status_code sdadc_init(
  */
 static inline void sdadc_get_config_defaults(struct sdadc_config *const config)
 {
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-	config->reference.ref_sel             = SDADC_REFERENCE_INTREF;
-	config->reference.ref_range           = SDADC_REFRANGE_0;
-	config->reference.on_ref_buffer       = false;
-	config->clock_prescaler               = 2;
-	config->osr                           = SDADC_OVER_SAMPLING_RATIO64;
-	config->skip_count                    = 2;
-	config->mux_input                     = SDADC_MUX_INPUT_AIN1;
-	config->event_action                  = SDADC_EVENT_ACTION_DISABLED;
-	config->freerunning                   = false;
-	config->run_in_standby                = false;
-	config->on_command                    = false;
-	config->seq_enable[0]                 = false;
-	config->seq_enable[1]                 = false;
-	config->seq_enable[2]                 = false;
-	config->window.window_mode            = SDADC_WINDOW_MODE_DISABLE;
-	config->window.window_upper_value     = 0;
-	config->window.window_lower_value     = 0;
-	config->correction.gain_correction    = 1;
-	config->correction.offset_correction  = SDADC_OFFSETCORR_RESETVALUE;
-	config->correction.shift_correction   = SDADC_SHIFTCORR_RESETVALUE;
+    Assert(config);
+    config->clock_source                  = GCLK_GENERATOR_0;
+    config->reference.ref_sel             = SDADC_REFERENCE_INTREF;
+    config->reference.ref_range           = SDADC_REFRANGE_0;
+    config->reference.on_ref_buffer       = false;
+    config->clock_prescaler               = 2;
+    config->osr                           = SDADC_OVER_SAMPLING_RATIO64;
+    config->skip_count                    = 2;
+    config->mux_input                     = SDADC_MUX_INPUT_AIN1;
+    config->event_action                  = SDADC_EVENT_ACTION_DISABLED;
+    config->freerunning                   = false;
+    config->run_in_standby                = false;
+    config->on_command                    = false;
+    config->seq_enable[0]                 = false;
+    config->seq_enable[1]                 = false;
+    config->seq_enable[2]                 = false;
+    config->window.window_mode            = SDADC_WINDOW_MODE_DISABLE;
+    config->window.window_upper_value     = 0;
+    config->window.window_lower_value     = 0;
+    config->correction.gain_correction    = 1;
+    config->correction.offset_correction  = SDADC_OFFSETCORR_RESETVALUE;
+    config->correction.shift_correction   = SDADC_SHIFTCORR_RESETVALUE;
 }
 
 /** @} */
@@ -552,34 +554,37 @@ static inline void sdadc_get_config_defaults(struct sdadc_config *const config)
  * \retval SDADC_STATUS_OVERRUN       SDADC result has overrun
  */
 static inline uint32_t sdadc_get_status(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	uint32_t int_flags = sdadc_module->INTFLAG.reg;
+    uint32_t int_flags = sdadc_module->INTFLAG.reg;
 
-	uint32_t status_flags = 0;
+    uint32_t status_flags = 0;
 
-	/* Check for SDADC Result Ready */
-	if (int_flags & SDADC_INTFLAG_RESRDY) {
-		status_flags |= SDADC_STATUS_RESULT_READY;
-	}
+    /* Check for SDADC Result Ready */
+    if (int_flags & SDADC_INTFLAG_RESRDY)
+    {
+        status_flags |= SDADC_STATUS_RESULT_READY;
+    }
 
-	/* Check for SDADC Window Match */
-	if (int_flags & SDADC_INTFLAG_WINMON) {
-		status_flags |= SDADC_STATUS_WINDOW;
-	}
+    /* Check for SDADC Window Match */
+    if (int_flags & SDADC_INTFLAG_WINMON)
+    {
+        status_flags |= SDADC_STATUS_WINDOW;
+    }
 
-	/* Check for SDADC Overrun */
-	if (int_flags & SDADC_INTFLAG_OVERRUN) {
-		status_flags |= SDADC_STATUS_OVERRUN;
-	}
+    /* Check for SDADC Overrun */
+    if (int_flags & SDADC_INTFLAG_OVERRUN)
+    {
+        status_flags |= SDADC_STATUS_OVERRUN;
+    }
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -591,34 +596,37 @@ static inline uint32_t sdadc_get_status(
  * \param[in] status_flags  Bitmask of \c SDADC_STATUS_* flags to clear
  */
 static inline void sdadc_clear_status(
-		struct sdadc_module *const module_inst,
-		const uint32_t status_flags)
+        struct sdadc_module *const module_inst,
+        const uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	Sdadc *const sdadc_module = module_inst->hw;
-
-	uint32_t int_flags = 0;
-
-	/* Check for SDADC Result Ready */
-	if (status_flags & SDADC_STATUS_RESULT_READY) {
-		int_flags |= SDADC_INTFLAG_RESRDY;
-	}
-
-	/* Check for SDADC Window Match */
-	if (status_flags & SDADC_STATUS_WINDOW) {
-		int_flags |= SDADC_INTFLAG_WINMON;
-	}
-
-	/* Check for SDADC Overrun */
-	if (status_flags & SDADC_STATUS_OVERRUN) {
-		int_flags |= SDADC_INTFLAG_OVERRUN;
-	}
-
-	/* Clear interrupt flag */
-	sdadc_module->INTFLAG.reg = int_flags;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    Sdadc *const sdadc_module = module_inst->hw;
+
+    uint32_t int_flags = 0;
+
+    /* Check for SDADC Result Ready */
+    if (status_flags & SDADC_STATUS_RESULT_READY)
+    {
+        int_flags |= SDADC_INTFLAG_RESRDY;
+    }
+
+    /* Check for SDADC Window Match */
+    if (status_flags & SDADC_STATUS_WINDOW)
+    {
+        int_flags |= SDADC_INTFLAG_WINMON;
+    }
+
+    /* Check for SDADC Overrun */
+    if (status_flags & SDADC_STATUS_OVERRUN)
+    {
+        int_flags |= SDADC_INTFLAG_OVERRUN;
+    }
+
+    /* Clear interrupt flag */
+    sdadc_module->INTFLAG.reg = int_flags;
 }
 
 /**
@@ -635,19 +643,19 @@ static inline void sdadc_clear_status(
  * \retval false When the last conversion in a sequence is done
  */
 static inline bool sdadc_get_sequence_status(
-		struct sdadc_module *const module_inst,
-		uint8_t* seq_state)
+        struct sdadc_module *const module_inst,
+        uint8_t* seq_state)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	/* Get SDADC result */
-	*seq_state = sdadc_module->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE_Msk;
+    /* Get SDADC result */
+    *seq_state = sdadc_module->SEQSTATUS.reg & SDADC_SEQSTATUS_SEQSTATE_Msk;
 
-	return ((sdadc_module->SEQSTATUS.bit.SEQBUSY == 1) ? true : false);
+    return ((sdadc_module->SEQSTATUS.bit.SEQBUSY == 1) ? true : false);
 }
 /** @} */
 
@@ -673,18 +681,19 @@ static inline bool sdadc_get_sequence_status(
  * \retval false If the module has completed synchronization
  */
 static inline bool sdadc_is_syncing(
-	struct sdadc_module *const module_inst)
+    struct sdadc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	if (sdadc_module->SYNCBUSY.reg) {
-		return true;
-	}
+    if (sdadc_module->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -696,23 +705,24 @@ static inline bool sdadc_is_syncing(
  * \param[in] module_inst  Pointer to the SDADC software instance struct
  */
 static inline enum status_code sdadc_enable(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
 #if SDADC_CALLBACK_MODE == true
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_SDADC);
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_SDADC);
 #endif
 
-	sdadc_module->CTRLA.reg |= SDADC_CTRLA_ENABLE;
-	return STATUS_OK;
+    sdadc_module->CTRLA.reg |= SDADC_CTRLA_ENABLE;
+    return STATUS_OK;
 }
 
 /**
@@ -723,28 +733,29 @@ static inline enum status_code sdadc_enable(
  * \param[in] module_inst Pointer to the SDADC software instance struct
  */
 static inline enum status_code sdadc_disable(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
 #if SDADC_CALLBACK_MODE == true
-	system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_SDADC);
+    system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_SDADC);
 #endif
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Disbale interrupt */
-	sdadc_module->INTENCLR.reg = SDADC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	sdadc_module->INTFLAG.reg = SDADC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    sdadc_module->INTENCLR.reg = SDADC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    sdadc_module->INTFLAG.reg = SDADC_INTFLAG_MASK;
 
-	sdadc_module->CTRLA.reg &= ~SDADC_CTRLA_ENABLE;
-	return STATUS_OK;
+    sdadc_module->CTRLA.reg &= ~SDADC_CTRLA_ENABLE;
+    return STATUS_OK;
 }
 
 /**
@@ -756,24 +767,25 @@ static inline enum status_code sdadc_disable(
  * \param[in] module_inst  Pointer to the SDADC software instance struct
  */
 static inline enum status_code sdadc_reset(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	/* Disable to make sure the pipeline is flushed before reset */
-	sdadc_disable(module_inst);
+    /* Disable to make sure the pipeline is flushed before reset */
+    sdadc_disable(module_inst);
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Software reset the module */
-	sdadc_module->CTRLA.reg |= SDADC_CTRLA_SWRST;
-	return STATUS_OK;
+    /* Software reset the module */
+    sdadc_module->CTRLA.reg |= SDADC_CTRLA_SWRST;
+    return STATUS_OK;
 }
 
 
@@ -789,29 +801,31 @@ static inline enum status_code sdadc_reset(
  *  \param[in] events       Struct containing flags of events to enable
  */
 static inline void sdadc_enable_events(
-		struct sdadc_module *const module_inst,
-		struct sdadc_events *const events)
+        struct sdadc_module *const module_inst,
+        struct sdadc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= SDADC_EVCTRL_WINMONEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= SDADC_EVCTRL_WINMONEO;
+    }
 
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= SDADC_EVCTRL_RESRDYEO;
-	}
+    /* Configure Result Ready event */
+    if (events->generate_event_on_conversion_done)
+    {
+        event_mask |= SDADC_EVCTRL_RESRDYEO;
+    }
 
-	sdadc_module->EVCTRL.reg |= event_mask;
+    sdadc_module->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -826,29 +840,31 @@ static inline void sdadc_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 static inline void sdadc_disable_events(
-		struct sdadc_module *const module_inst,
-		struct sdadc_events *const events)
+        struct sdadc_module *const module_inst,
+        struct sdadc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= SDADC_EVCTRL_WINMONEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= SDADC_EVCTRL_WINMONEO;
+    }
 
-	/* Configure Result Ready event */
-	if (events->generate_event_on_conversion_done) {
-		event_mask |= SDADC_EVCTRL_RESRDYEO;
-	}
+    /* Configure Result Ready event */
+    if (events->generate_event_on_conversion_done)
+    {
+        event_mask |= SDADC_EVCTRL_RESRDYEO;
+    }
 
-	sdadc_module->EVCTRL.reg &= ~event_mask;
+    sdadc_module->EVCTRL.reg &= ~event_mask;
 }
 
 /**
@@ -859,18 +875,19 @@ static inline void sdadc_disable_events(
  * \param[in] module_inst  Pointer to the SDADC software instance struct
  */
 static inline void sdadc_start_conversion(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_START;
+    sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_START;
 }
 
 /**
@@ -888,32 +905,34 @@ static inline void sdadc_start_conversion(
  *                             SDADC module before the result was read by the software
  */
 static inline enum status_code sdadc_read(
-		struct sdadc_module *const module_inst,
-		int32_t *result)
+        struct sdadc_module *const module_inst,
+        int32_t *result)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(result);
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(result);
 
-	if (!(sdadc_get_status(module_inst) & SDADC_STATUS_RESULT_READY)) {
-		/* Result not ready */
-		return STATUS_BUSY;
-	}
+    if (!(sdadc_get_status(module_inst) & SDADC_STATUS_RESULT_READY))
+    {
+        /* Result not ready */
+        return STATUS_BUSY;
+    }
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	/* Get SDADC result */
-	*result = ((int32_t)(sdadc_module->RESULT.reg << 8)) >> 8;
+    /* Get SDADC result */
+    *result = ((int32_t)(sdadc_module->RESULT.reg << 8)) >> 8;
 
-	/* Reset ready flag */
-	sdadc_clear_status(module_inst, SDADC_STATUS_RESULT_READY);
+    /* Reset ready flag */
+    sdadc_clear_status(module_inst, SDADC_STATUS_RESULT_READY);
 
-	if (sdadc_get_status(module_inst) & SDADC_STATUS_OVERRUN) {
-		sdadc_clear_status(module_inst, SDADC_STATUS_OVERRUN);
-		return STATUS_ERR_OVERFLOW;
-	}
+    if (sdadc_get_status(module_inst) & SDADC_STATUS_OVERRUN)
+    {
+        sdadc_clear_status(module_inst, SDADC_STATUS_OVERRUN);
+        return STATUS_ERR_OVERFLOW;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /** @} */
@@ -933,18 +952,19 @@ static inline enum status_code sdadc_read(
  * \param[in] module_inst  Pointer to the SDADC software instance struct
  */
 static inline void sdadc_flush(
-		struct sdadc_module *const module_inst)
+        struct sdadc_module *const module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_FLUSH;
+    sdadc_module->SWTRIG.reg |= SDADC_SWTRIG_FLUSH;
 }
 
 /**
@@ -958,37 +978,40 @@ static inline void sdadc_flush(
  * \param[in] window_upper_value  Upper window monitor threshold value
   */
 static inline void sdadc_set_window_mode(
-		struct sdadc_module *const module_inst,
-		const enum sdadc_window_mode window_mode,
-		const int16_t window_lower_value,
-		const int16_t window_upper_value)
+        struct sdadc_module *const module_inst,
+        const enum sdadc_window_mode window_mode,
+        const int16_t window_lower_value,
+        const int16_t window_upper_value)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set window mode */
-	sdadc_module->WINCTRL.reg = window_mode << SDADC_WINCTRL_WINMODE_Pos;
+    /* Set window mode */
+    sdadc_module->WINCTRL.reg = window_mode << SDADC_WINCTRL_WINMODE_Pos;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set lower window monitor threshold value */
-	sdadc_module->WINLT.reg = window_lower_value << SDADC_WINLT_WINLT_Pos;
+    /* Set lower window monitor threshold value */
+    sdadc_module->WINLT.reg = window_lower_value << SDADC_WINLT_WINLT_Pos;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set upper window monitor threshold value */
-	sdadc_module->WINUT.reg = window_upper_value << SDADC_WINUT_WINUT_Pos;
+    /* Set upper window monitor threshold value */
+    sdadc_module->WINUT.reg = window_upper_value << SDADC_WINUT_WINUT_Pos;
 }
 
 /**
@@ -1000,22 +1023,23 @@ static inline void sdadc_set_window_mode(
  * \param[in] mux_input       MUX input pin
  */
 static inline void sdadc_set_mux_input(
-		struct sdadc_module *const module_inst,
-		const enum sdadc_mux_input mux_input)
+        struct sdadc_module *const module_inst,
+        const enum sdadc_mux_input mux_input)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
+    Sdadc *const sdadc_module = module_inst->hw;
 
-	while (sdadc_is_syncing(module_inst)) {
-		/* Wait for synchronization */
-	}
+    while (sdadc_is_syncing(module_inst))
+    {
+        /* Wait for synchronization */
+    }
 
-	/* Set mux input pin */
-	sdadc_module->INPUTCTRL.reg =
-			(sdadc_module->INPUTCTRL.reg & ~SDADC_INPUTCTRL_MUXSEL_Msk) | mux_input;
+    /* Set mux input pin */
+    sdadc_module->INPUTCTRL.reg =
+            (sdadc_module->INPUTCTRL.reg & ~SDADC_INPUTCTRL_MUXSEL_Msk) | mux_input;
 }
 
 
@@ -1036,15 +1060,15 @@ static inline void sdadc_set_mux_input(
  * \param[in] interrupt Interrupt to enable
  */
 static inline void sdadc_enable_interrupt(struct sdadc_module *const module_inst,
-		enum sdadc_interrupt_flag interrupt)
+        enum sdadc_interrupt_flag interrupt)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
-	/* Enable interrupt */
-	sdadc_module->INTENSET.reg = interrupt;
+    Sdadc *const sdadc_module = module_inst->hw;
+    /* Enable interrupt */
+    sdadc_module->INTENSET.reg = interrupt;
 }
 
 /**
@@ -1056,15 +1080,15 @@ static inline void sdadc_enable_interrupt(struct sdadc_module *const module_inst
  * \param[in] interrupt Interrupt to disable
  */
 static inline void sdadc_disable_interrupt(struct sdadc_module *const module_inst,
-		enum sdadc_interrupt_flag interrupt)
+        enum sdadc_interrupt_flag interrupt)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Sdadc *const sdadc_module = module_inst->hw;
-	/* Enable interrupt */
-	sdadc_module->INTENCLR.reg = interrupt;
+    Sdadc *const sdadc_module = module_inst->hw;
+    /* Enable interrupt */
+    sdadc_module->INTENCLR.reg = interrupt;
 }
 
 /** @} */
@@ -1084,18 +1108,18 @@ static inline void sdadc_disable_interrupt(struct sdadc_module *const module_ins
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>SDADC</td>
- *		<td>Sigma-Delta Analog-to-Digital Converter</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SDADC</td>
+ *      <td>Sigma-Delta Analog-to-Digital Converter</td>
+ *  </tr>
  *  <tr>
- *		<td>OSR</td>
- *		<td>Over Sampling Ratio</td>
- *	</tr>
+ *      <td>OSR</td>
+ *      <td>Over Sampling Ratio</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1114,12 +1138,12 @@ static inline void sdadc_disable_interrupt(struct sdadc_module *const module_ins
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1140,16 +1164,16 @@ static inline void sdadc_disable_interrupt(struct sdadc_module *const module_ins
  * \page asfdoc_sam0_sdadc_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42496A</td>
- *		<td>09/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42496A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c
index 11543fa6203a..26a9207d7efe 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.c
@@ -50,59 +50,68 @@ struct sdadc_module *_sdadc_instances[SDADC_INST_NUM];
 
 static void _sdadc_interrupt_handler(const uint8_t instance)
 {
-	struct sdadc_module *module = _sdadc_instances[instance];
-
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->INTFLAG.reg;
-
-	if (flags & SDADC_INTFLAG_RESRDY) {
-		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER)) &&
-				(module->registered_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER))) {
-			/* clear interrupt flag */
-			module->hw->INTFLAG.reg = SDADC_INTFLAG_RESRDY;
-
-			/* store SDADC result in job buffer */
-			*(module->job_buffer++) = ((int32_t)(module->hw->RESULT.reg << 8)) >> 8;
-
-			if (--module->remaining_conversions > 0) {
-				if (module->software_trigger == true) {
-					sdadc_start_conversion(module);
-				}
-			} else {
-				if (module->job_status == STATUS_BUSY) {
-					/* job is complete. update status,disable interrupt
-					 *and call callback */
-					module->job_status = STATUS_OK;
-					sdadc_disable_interrupt(module, SDADC_INTERRUPT_RESULT_READY);
-
-					(module->callback[SDADC_CALLBACK_READ_BUFFER])(module);
-				}
-			}
-		}
-	}
-
-	if (flags & SDADC_INTFLAG_WINMON) {
-		module->hw->INTFLAG.reg = SDADC_INTFLAG_WINMON;
-		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_WINDOW)) &&
-				(module->registered_callback_mask & (1 << SDADC_CALLBACK_WINDOW))) {
-			(module->callback[SDADC_CALLBACK_WINDOW])(module);
-		}
-
-	}
-
-	if (flags & SDADC_INTFLAG_OVERRUN) {
-		module->hw->INTFLAG.reg = SDADC_INTFLAG_OVERRUN;
-		if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_ERROR)) &&
-				(module->registered_callback_mask & (1 << SDADC_CALLBACK_ERROR))) {
-			(module->callback[SDADC_CALLBACK_ERROR])(module);
-		}
-	}
+    struct sdadc_module *module = _sdadc_instances[instance];
+
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->INTFLAG.reg;
+
+    if (flags & SDADC_INTFLAG_RESRDY)
+    {
+        if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER)) &&
+                (module->registered_callback_mask & (1 << SDADC_CALLBACK_READ_BUFFER)))
+                {
+            /* clear interrupt flag */
+            module->hw->INTFLAG.reg = SDADC_INTFLAG_RESRDY;
+
+            /* store SDADC result in job buffer */
+            *(module->job_buffer++) = ((int32_t)(module->hw->RESULT.reg << 8)) >> 8;
+
+            if (--module->remaining_conversions > 0)
+            {
+                if (module->software_trigger == true)
+                {
+                    sdadc_start_conversion(module);
+                }
+            } else {
+                if (module->job_status == STATUS_BUSY)
+                {
+                    /* job is complete. update status,disable interrupt
+                     *and call callback */
+                    module->job_status = STATUS_OK;
+                    sdadc_disable_interrupt(module, SDADC_INTERRUPT_RESULT_READY);
+
+                    (module->callback[SDADC_CALLBACK_READ_BUFFER])(module);
+                }
+            }
+        }
+    }
+
+    if (flags & SDADC_INTFLAG_WINMON)
+    {
+        module->hw->INTFLAG.reg = SDADC_INTFLAG_WINMON;
+        if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_WINDOW)) &&
+                (module->registered_callback_mask & (1 << SDADC_CALLBACK_WINDOW)))
+                {
+            (module->callback[SDADC_CALLBACK_WINDOW])(module);
+        }
+
+    }
+
+    if (flags & SDADC_INTFLAG_OVERRUN)
+    {
+        module->hw->INTFLAG.reg = SDADC_INTFLAG_OVERRUN;
+        if ((module->enabled_callback_mask & (1 << SDADC_CALLBACK_ERROR)) &&
+                (module->registered_callback_mask & (1 << SDADC_CALLBACK_ERROR)))
+                {
+            (module->callback[SDADC_CALLBACK_ERROR])(module);
+        }
+    }
 }
 
 /** Interrupt handler for the SDADC module. */
 void SDADC_Handler(void)
 {
-	_sdadc_interrupt_handler(0);
+    _sdadc_interrupt_handler(0);
 }
 
 /**
@@ -119,19 +128,19 @@ void SDADC_Handler(void)
  *
  */
 void sdadc_register_callback(
-		struct sdadc_module *const module,
-		sdadc_callback_t callback_func,
-		enum sdadc_callback callback_type)
+        struct sdadc_module *const module,
+        sdadc_callback_t callback_func,
+        enum sdadc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->registered_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->registered_callback_mask |= (1 << callback_type);
 }
 
 /**
@@ -144,17 +153,17 @@ void sdadc_register_callback(
  *
  */
 void sdadc_unregister_callback(
-		struct sdadc_module *const module,
-		enum sdadc_callback callback_type)
+        struct sdadc_module *const module,
+        enum sdadc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->registered_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->registered_callback_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -176,30 +185,32 @@ void sdadc_unregister_callback(
  * \retval STATUS_BUSY      The SDADC is already busy with another job
  */
 enum status_code sdadc_read_buffer_job(
-		struct sdadc_module *const module_inst,
-		int32_t *buffer,
-		uint16_t samples)
+        struct sdadc_module *const module_inst,
+        int32_t *buffer,
+        uint16_t samples)
 {
-	Assert(module_inst);
-	Assert(samples);
-	Assert(buffer);
+    Assert(module_inst);
+    Assert(samples);
+    Assert(buffer);
 
-	if(module_inst->remaining_conversions != 0 ||
-			module_inst->job_status == STATUS_BUSY){
-		return STATUS_BUSY;
-	}
+    if(module_inst->remaining_conversions != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	module_inst->job_status = STATUS_BUSY;
-	module_inst->remaining_conversions = samples;
-	module_inst->job_buffer = buffer;
+    module_inst->job_status = STATUS_BUSY;
+    module_inst->remaining_conversions = samples;
+    module_inst->job_buffer = buffer;
 
-	sdadc_enable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
+    sdadc_enable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
 
-	if(module_inst->software_trigger == true) {
-		sdadc_start_conversion(module_inst);
-	}
+    if(module_inst->software_trigger == true)
+    {
+        sdadc_start_conversion(module_inst);
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -213,17 +224,18 @@ enum status_code sdadc_read_buffer_job(
  * \return Status of the job.
  */
 enum status_code sdadc_get_job_status(
-		struct sdadc_module *module_inst,
-		enum sdadc_job_type type)
+        struct sdadc_module *module_inst,
+        enum sdadc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == SDADC_JOB_READ_BUFFER ) {
-		return module_inst->job_status;
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == SDADC_JOB_READ_BUFFER )
+    {
+        return module_inst->job_status;
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -235,18 +247,19 @@ enum status_code sdadc_get_job_status(
  * \param [in]  type        Type of job to abort
  */
 void sdadc_abort_job(
-		struct sdadc_module *module_inst,
-		enum sdadc_job_type type)
+        struct sdadc_module *module_inst,
+        enum sdadc_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == SDADC_JOB_READ_BUFFER) {
-		/* Disable interrupt */
-		sdadc_disable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
-		/* Mark job as aborted */
-		module_inst->job_status = STATUS_ABORTED;
-		module_inst->remaining_conversions = 0;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == SDADC_JOB_READ_BUFFER)
+    {
+        /* Disable interrupt */
+        sdadc_disable_interrupt(module_inst, SDADC_INTERRUPT_RESULT_READY);
+        /* Mark job as aborted */
+        module_inst->job_status = STATUS_ABORTED;
+        module_inst->remaining_conversions = 0;
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h
index d078758ef332..9ca92b166329 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sdadc/sdadc_callback.h
@@ -64,8 +64,8 @@ extern "C" {
  * the driver.
  */
 enum sdadc_job_type {
-	/** Asynchronous SDADC read into a user provided buffer */
-	SDADC_JOB_READ_BUFFER,
+    /** Asynchronous SDADC read into a user provided buffer */
+    SDADC_JOB_READ_BUFFER,
 };
 
 /**
@@ -73,13 +73,13 @@ enum sdadc_job_type {
  * @{
  */
 void sdadc_register_callback(
-		struct sdadc_module *const module,
-		sdadc_callback_t callback_func,
-		enum sdadc_callback callback_type);
+        struct sdadc_module *const module,
+        sdadc_callback_t callback_func,
+        enum sdadc_callback callback_type);
 
 void sdadc_unregister_callback(
-		struct sdadc_module *module,
-		enum sdadc_callback callback_type);
+        struct sdadc_module *module,
+        enum sdadc_callback callback_type);
 
 /**
  * \brief Enables callback.
@@ -98,23 +98,25 @@ void sdadc_unregister_callback(
  *
  */
 static inline void sdadc_enable_callback(
-		struct sdadc_module *const module,
-		enum sdadc_callback callback_type)
+        struct sdadc_module *const module,
+        enum sdadc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Enable callback */
-	module->enabled_callback_mask |= (1 << callback_type);
-
-	/* Enable window interrupt if this is a window callback */
-	if (callback_type == SDADC_CALLBACK_WINDOW) {
-		sdadc_enable_interrupt(module, SDADC_INTERRUPT_WINDOW);
-	}
-	/* Enable overrun interrupt if error callback is registered */
-	if (callback_type == SDADC_CALLBACK_ERROR) {
-		sdadc_enable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Enable callback */
+    module->enabled_callback_mask |= (1 << callback_type);
+
+    /* Enable window interrupt if this is a window callback */
+    if (callback_type == SDADC_CALLBACK_WINDOW)
+    {
+        sdadc_enable_interrupt(module, SDADC_INTERRUPT_WINDOW);
+    }
+    /* Enable overrun interrupt if error callback is registered */
+    if (callback_type == SDADC_CALLBACK_ERROR)
+    {
+        sdadc_enable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
+    }
 }
 
 /**
@@ -133,23 +135,25 @@ static inline void sdadc_enable_callback(
  *
  */
 static inline void sdadc_disable_callback(
-		struct sdadc_module *const module,
-		enum sdadc_callback callback_type)
+        struct sdadc_module *const module,
+        enum sdadc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Disable callback */
-	module->enabled_callback_mask &= ~(1 << callback_type);
-
-	/* Disable window interrupt if this is a window callback */
-	if (callback_type == SDADC_CALLBACK_WINDOW) {
-		sdadc_disable_interrupt(module, SDADC_INTERRUPT_WINDOW);
-	}
-	/* Disable overrun interrupt if this is the error callback */
-	if (callback_type == SDADC_CALLBACK_ERROR) {
-		sdadc_disable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Disable callback */
+    module->enabled_callback_mask &= ~(1 << callback_type);
+
+    /* Disable window interrupt if this is a window callback */
+    if (callback_type == SDADC_CALLBACK_WINDOW)
+    {
+        sdadc_disable_interrupt(module, SDADC_INTERRUPT_WINDOW);
+    }
+    /* Disable overrun interrupt if this is the error callback */
+    if (callback_type == SDADC_CALLBACK_ERROR)
+    {
+        sdadc_disable_interrupt(module, SDADC_INTERRUPT_OVERRUN);
+    }
 }
 
 /** @} */
@@ -160,17 +164,17 @@ static inline void sdadc_disable_callback(
  * @{
  */
 enum status_code sdadc_read_buffer_job(
-		struct sdadc_module *const module_inst,
-		int32_t *buffer,
-		uint16_t samples);
+        struct sdadc_module *const module_inst,
+        int32_t *buffer,
+        uint16_t samples);
 
 enum status_code sdadc_get_job_status(
-		struct sdadc_module *module_inst,
-		enum sdadc_job_type type);
+        struct sdadc_module *module_inst,
+        enum sdadc_job_type type);
 
 void sdadc_abort_job(
-		struct sdadc_module *module_inst,
-		enum sdadc_job_type type);
+        struct sdadc_module *module_inst,
+        enum sdadc_job_type type);
 /** @} */
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h
index 405b5575a3a5..d2abafafcf13 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_common.h
@@ -116,32 +116,32 @@ extern "C" {
  *
  * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition
  * <table>
- *	<tr>
- *		<th>Driver Feature Macro</th>
- *		<th>Supported devices</th>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
- *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_I2C_10_BIT_ADDRESS</td>
- *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_I2C_SCL_STRETCH_MODE</td>
- *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
- *		<td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
- *	</tr>
+ *  <tr>
+ *      <th>Driver Feature Macro</th>
+ *      <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED</td>
+ *      <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_I2C_10_BIT_ADDRESS</td>
+ *      <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_I2C_SCL_STRETCH_MODE</td>
+ *      <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_I2C_SCL_EXTEND_TIMEOUT</td>
+ *      <td>SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/HA1</td>
+ *  </tr>
  * </table>
  * \note The specific features are only available in the driver when the selected
- * device supports those features. 
+ * device supports those features.
  * \note When using the I2C high-speed mode for off-board communication,
- * there are various high frequency interference, which can lead to distortion of the signals 
- * and communication failure. When using Xplained Pro boards in order to test I2C high-speed 
+ * there are various high frequency interference, which can lead to distortion of the signals
+ * and communication failure. When using Xplained Pro boards in order to test I2C high-speed
  * communication, the following recommendation should be followed:
  * - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger
  * pull-ups on both SDA and SCL.
@@ -407,7 +407,7 @@ extern "C" {
  * @{
  */
 #if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \
-	(SAMHA1) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
+    (SAMHA1) || (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
 /** Fast mode plus and high speed support. */
 #  define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
 /** 10-bit address support */
@@ -426,10 +426,10 @@ extern "C" {
  * For slave: direction of request from master.
  */
 enum i2c_transfer_direction {
-	/** Master write operation is in progress */
-	I2C_TRANSFER_WRITE = 0,
-	/** Master read operation is in progress */
-	I2C_TRANSFER_READ  = 1,
+    /** Master write operation is in progress */
+    I2C_TRANSFER_WRITE = 0,
+    /** Master read operation is in progress */
+    I2C_TRANSFER_READ  = 1,
 };
 
 /** @} */
@@ -448,26 +448,26 @@ enum i2c_transfer_direction {
  * \anchor asfdoc_sam0_sercom_i2c_acronyms_table
  * <table>
  *  <caption>Acronyms</caption>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>SDA</td>
- *		<td>Serial Data Line</td>
- *	</tr>
- *	<tr>
- *		<td>SCL</td>
- *		<td>Serial Clock Line</td>
- *	</tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>Serial Communication Interface</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SDA</td>
+ *      <td>Serial Data Line</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SCL</td>
+ *      <td>Serial Clock Line</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SERCOM</td>
+ *      <td>Serial Communication Interface</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies
@@ -488,29 +488,29 @@ enum i2c_transfer_direction {
  * \anchor asfdoc_sam0_sercom_i2c_extra_history_table
  * <table>
  *  <caption>Module History</caption>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>
- *		\li Added 10-bit addressing and high speed support in SAM D21
- *		\li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>
- *		\li Added support for SCL stretch and extended timeout hardware features in SAM D21
- *		\li Added fast mode plus support in SAM D21
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>Fixed incorrect logical mask for determining if a bus error has
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *      \li Added 10-bit addressing and high speed support in SAM D21
+ *      \li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *      \li Added support for SCL stretch and extended timeout hardware features in SAM D21
+ *      \li Added fast mode plus support in SAM D21
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Fixed incorrect logical mask for determining if a bus error has
  *          occurred in I<SUP>2</SUP>C Slave mode
  *      </td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -521,7 +521,7 @@ enum i2c_transfer_direction {
  * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with
  * step-by-step instructions to configure and use this driver in a selection of
  * use cases. Note that a QSG can be compiled as a standalone application or be
- * added to the user application.  
+ * added to the user application.
  *
  * \if I2C_MASTER_MODE
  * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case"
@@ -542,71 +542,71 @@ enum i2c_transfer_direction {
  *
  * \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE)
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42117E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
- *	</tr>
- *	<tr>
- *		<td>42117D</td>
- *		<td>12/2014</td>
- *		<td>Added support for 10-bit addressing and high speed in SAM D21.
- *		    Added support for SAM R21 and SAM D10/D11.</td>
- *	</tr>
- *	<tr>
- *		<td>42117C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42117B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
- *	</tr>
- *	<tr>
- *		<td>42117A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42117E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42117D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for 10-bit addressing and high speed in SAM D21.
+ *          Added support for SAM R21 and SAM D10/D11.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42117C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42117B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42117A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  * \else
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42116E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
- *	</tr>
- *	<tr>
- *		<td>42116D</td>
- *		<td>12/2014</td>
- *		<td>Added support for 10-bit addressing and high speed in SAM D21.
- *		    Added support for SAM R21 and SAM D10/D11.</td>
- *	</tr>
- *	<tr>
- *		<td>42116C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42116B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
- *	</tr>
- *	<tr>
- *		<td>42116A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42116E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42116D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for 10-bit addressing and high speed in SAM D21.
+ *          Added support for SAM R21 and SAM D10/D11.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42116C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42116B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos. Updated I<SUP>2</SUP>C Bus State Diagram.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42116A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  *\endif
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h
index 79c2effe8e59..d96d9001f325 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master.h
@@ -75,18 +75,18 @@ extern "C" {
  * Structure to be used when transferring I<SUP>2</SUP>C master packets.
  */
 struct i2c_master_packet {
-	/** Address to slave device  */
-	uint16_t address;
-	/** Length of data array */
-	uint16_t data_length;
-	/** Data array containing all data to be transferred */
-	uint8_t *data;
-	/** Use 10-bit addressing. Set to false if the feature is not supported by the device  */
-	bool ten_bit_address;
-	/** Use high speed transfer. Set to false if the feature is not supported by the device */
-	bool high_speed;
-	/** High speed mode master code (0000 1XXX), valid when high_speed is true */
-	uint8_t hs_master_code;
+    /** Address to slave device  */
+    uint16_t address;
+    /** Length of data array */
+    uint16_t data_length;
+    /** Data array containing all data to be transferred */
+    uint8_t *data;
+    /** Use 10-bit addressing. Set to false if the feature is not supported by the device  */
+    bool ten_bit_address;
+    /** Use high speed transfer. Set to false if the feature is not supported by the device */
+    bool high_speed;
+    /** High speed mode master code (0000 1XXX), valid when high_speed is true */
+    uint8_t hs_master_code;
 };
 
 /** \brief Interrupt flags
@@ -94,10 +94,10 @@ struct i2c_master_packet {
  * Flags used when reading or setting interrupt flags.
  */
 enum i2c_master_interrupt_flag {
-	/** Interrupt flag used for write */
-	I2C_MASTER_INTERRUPT_WRITE = 0,
-	/** Interrupt flag used for read */
-	I2C_MASTER_INTERRUPT_READ  = 1,
+    /** Interrupt flag used for write */
+    I2C_MASTER_INTERRUPT_WRITE = 0,
+    /** Interrupt flag used for read */
+    I2C_MASTER_INTERRUPT_READ  = 1,
 };
 
 /**
@@ -107,14 +107,14 @@ enum i2c_master_interrupt_flag {
  * bit has been sent.
  */
 enum i2c_master_start_hold_time {
-	/** Internal SDA hold time disabled */
-	I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
-	/** Internal SDA hold time 50ns - 100ns */
-	I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
-	/** Internal SDA hold time 300ns - 600ns */
-	I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
-	/** Internal SDA hold time 400ns - 800ns */
-	I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
+    /** Internal SDA hold time disabled */
+    I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0),
+    /** Internal SDA hold time 50ns - 100ns */
+    I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1),
+    /** Internal SDA hold time 300ns - 600ns */
+    I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2),
+    /** Internal SDA hold time 400ns - 800ns */
+    I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3),
 };
 
 /**
@@ -124,14 +124,14 @@ enum i2c_master_start_hold_time {
  * longer than the time-out setting, the bus state logic will be set to idle.
  */
 enum i2c_master_inactive_timeout {
-	/** Inactive bus time-out disabled */
-	I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
-	/** Inactive bus time-out 5-6 SCL cycle time-out */
-	I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
-	/** Inactive bus time-out 10-11 SCL cycle time-out */
-	I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
-	/** Inactive bus time-out 20-21 SCL cycle time-out */
-	I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
+    /** Inactive bus time-out disabled */
+    I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0),
+    /** Inactive bus time-out 5-6 SCL cycle time-out */
+    I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1),
+    /** Inactive bus time-out 10-11 SCL cycle time-out */
+    I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2),
+    /** Inactive bus time-out 20-21 SCL cycle time-out */
+    I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3),
 };
 
 /**
@@ -145,15 +145,15 @@ enum i2c_master_inactive_timeout {
  * structure the value 10.
  */
 enum i2c_master_baud_rate {
-	/** Baud rate at 100KHz (Standard-mode) */
-	I2C_MASTER_BAUD_RATE_100KHZ = 100,
-	/** Baud rate at 400KHz (Fast-mode) */
-	I2C_MASTER_BAUD_RATE_400KHZ = 400,
+    /** Baud rate at 100KHz (Standard-mode) */
+    I2C_MASTER_BAUD_RATE_100KHZ = 100,
+    /** Baud rate at 400KHz (Fast-mode) */
+    I2C_MASTER_BAUD_RATE_400KHZ = 400,
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
-	/** Baud rate at 1MHz (Fast-mode Plus) */
-	I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
-	/** Baud rate at 3.4MHz (High-speed mode) */
-	I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
+    /** Baud rate at 1MHz (Fast-mode Plus) */
+    I2C_MASTER_BAUD_RATE_1000KHZ = 1000,
+    /** Baud rate at 3.4MHz (High-speed mode) */
+    I2C_MASTER_BAUD_RATE_3400KHZ = 3400,
 #endif
 };
 
@@ -164,12 +164,12 @@ enum i2c_master_baud_rate {
  * Enum for the transfer speed.
  */
 enum i2c_master_transfer_speed {
-	/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
-	I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
-	/** Fast-mode Plus (Fm+) up to 1MHz */
-	I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
-	/** High-speed mode (Hs-mode) up to 3.4MHz */
-	I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
+    /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
+    I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0),
+    /** Fast-mode Plus (Fm+) up to 1MHz */
+    I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1),
+    /** High-speed mode (Hs-mode) up to 3.4MHz */
+    I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2),
 };
 #endif
 
@@ -180,15 +180,15 @@ enum i2c_master_transfer_speed {
  * The available callback types for the I<SUP>2</SUP>C master module.
  */
 enum i2c_master_callback {
-	/** Callback for packet write complete */
-	I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
-	/** Callback for packet read complete */
-	I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
-	/** Callback for error */
-	I2C_MASTER_CALLBACK_ERROR          = 2,
+    /** Callback for packet write complete */
+    I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0,
+    /** Callback for packet read complete */
+    I2C_MASTER_CALLBACK_READ_COMPLETE  = 1,
+    /** Callback for error */
+    I2C_MASTER_CALLBACK_ERROR          = 2,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_I2C_MASTER_CALLBACK_N             = 3,
+    /** Total number of callbacks */
+    _I2C_MASTER_CALLBACK_N             = 3,
 #  endif
 };
 
@@ -197,7 +197,7 @@ enum i2c_master_callback {
 struct i2c_master_module;
 
 typedef void (*i2c_master_callback_t)(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 #  endif
 #endif
 
@@ -212,38 +212,38 @@ typedef void (*i2c_master_callback_t)(
  */
 struct i2c_master_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware instance initialized for the struct */
-	Sercom *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** Unknown bus state timeout */
-	uint16_t unknown_bus_state_timeout;
-	/** Buffer write timeout value */
-	uint16_t buffer_timeout;
-	/** If true, stop condition will be sent after a read/write */
-	bool send_stop;
-	/** If true, nack signal will be sent after a read/write */
-	bool send_nack;
+    /** Hardware instance initialized for the struct */
+    Sercom *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** Unknown bus state timeout */
+    uint16_t unknown_bus_state_timeout;
+    /** Buffer write timeout value */
+    uint16_t buffer_timeout;
+    /** If true, stop condition will be sent after a read/write */
+    bool send_stop;
+    /** If true, nack signal will be sent after a read/write */
+    bool send_nack;
 #  if I2C_MASTER_CALLBACK_MODE == true
-	/** Pointers to callback functions */
-	volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint8_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint8_t enabled_callback;
-	/** The total number of bytes to transfer */
-	volatile uint16_t buffer_length;
-	/**
-	 * Counter used for bytes left to send in write and to count number of
-	 * obtained bytes in read
-	 */
-	volatile uint16_t buffer_remaining;
-	/** Data buffer for packet write and read */
-	volatile uint8_t *buffer;
-	/** Save direction of async request. 1 = read, 0 = write */
-	volatile enum i2c_transfer_direction transfer_direction;
-	/** Status for status read back in error callback */
-	volatile enum status_code status;
+    /** Pointers to callback functions */
+    volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint8_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint8_t enabled_callback;
+    /** The total number of bytes to transfer */
+    volatile uint16_t buffer_length;
+    /**
+     * Counter used for bytes left to send in write and to count number of
+     * obtained bytes in read
+     */
+    volatile uint16_t buffer_remaining;
+    /** Data buffer for packet write and read */
+    volatile uint8_t *buffer;
+    /** Save direction of async request. 1 = read, 0 = write */
+    volatile enum i2c_transfer_direction transfer_direction;
+    /** Status for status read back in error callback */
+    volatile enum status_code status;
 #  endif
 #endif
 };
@@ -257,47 +257,47 @@ struct i2c_master_module {
  * \ref i2c_master_get_config_defaults.
  */
 struct i2c_master_config {
-	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
-	 * standard-mode, Fast-mode, and Fast-mode Plus Transfers,
-	 * \ref i2c_master_baud_rate */
-	uint32_t baud_rate;
+    /** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+     * standard-mode, Fast-mode, and Fast-mode Plus Transfers,
+     * \ref i2c_master_baud_rate */
+    uint32_t baud_rate;
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
-	/** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
-	 * High-speed mode, \ref i2c_master_baud_rate */
-	uint32_t baud_rate_high_speed;
-	/** Transfer speed mode */
-	enum i2c_master_transfer_speed transfer_speed;
+    /** Baud rate (in KHz) for I<SUP>2</SUP>C operations in
+     * High-speed mode, \ref i2c_master_baud_rate */
+    uint32_t baud_rate_high_speed;
+    /** Transfer speed mode */
+    enum i2c_master_transfer_speed transfer_speed;
 #endif
-	/** GCLK generator to use as clock source */
-	enum gclk_generator generator_source;
-	/** Bus hold time after start signal on data line */
-	enum i2c_master_start_hold_time start_hold_time;
-	/** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */
-	uint16_t unknown_bus_state_timeout;
-	/** Timeout for packet write to wait for slave */
-	uint16_t buffer_timeout;
-	/** Set to keep module active in sleep modes */
-	bool run_in_standby;
-	/** PAD0 (SDA) pinmux */
-	uint32_t pinmux_pad0;
-	/** PAD1 (SCL) pinmux */
-	uint32_t pinmux_pad1;
-	/** Set to enable SCL low time-out */
-	bool scl_low_timeout;
-	/** Inactive bus time out */
-	enum i2c_master_inactive_timeout inactive_timeout;
+    /** GCLK generator to use as clock source */
+    enum gclk_generator generator_source;
+    /** Bus hold time after start signal on data line */
+    enum i2c_master_start_hold_time start_hold_time;
+    /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */
+    uint16_t unknown_bus_state_timeout;
+    /** Timeout for packet write to wait for slave */
+    uint16_t buffer_timeout;
+    /** Set to keep module active in sleep modes */
+    bool run_in_standby;
+    /** PAD0 (SDA) pinmux */
+    uint32_t pinmux_pad0;
+    /** PAD1 (SCL) pinmux */
+    uint32_t pinmux_pad1;
+    /** Set to enable SCL low time-out */
+    bool scl_low_timeout;
+    /** Inactive bus time out */
+    enum i2c_master_inactive_timeout inactive_timeout;
 #ifdef FEATURE_I2C_SCL_STRETCH_MODE
-	/** Set to enable SCL stretch only after ACK bit (required for high speed) */
-	bool scl_stretch_only_after_ack_bit;
+    /** Set to enable SCL stretch only after ACK bit (required for high speed) */
+    bool scl_stretch_only_after_ack_bit;
 #endif
 #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
-	/** Set to enable slave SCL low extend time-out */
-	bool slave_scl_low_extend_timeout;
-	/** Set to enable maser SCL low extend time-out */
-	bool master_scl_low_extend_timeout;
+    /** Set to enable slave SCL low extend time-out */
+    bool slave_scl_low_extend_timeout;
+    /** Set to enable maser SCL low extend time-out */
+    bool master_scl_low_extend_timeout;
 #endif
-	/** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */
-	uint16_t sda_scl_rise_time_ns;
+    /** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */
+    uint16_t sda_scl_rise_time_ns;
 };
 
 /**
@@ -321,22 +321,23 @@ struct i2c_master_config {
  * \retval STATUS_BUSY If the module was already locked
  */
 static inline enum status_code i2c_master_lock(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return status;
+    return status;
 }
 
 /**
@@ -352,7 +353,7 @@ static inline enum status_code i2c_master_lock(
  */
 static inline void i2c_master_unlock(struct i2c_master_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /** @} */
@@ -374,18 +375,18 @@ static inline void i2c_master_unlock(struct i2c_master_module *const module)
  * \retval false  Module is not synchronizing
  */
 static inline bool i2c_master_is_syncing (
-		const struct i2c_master_module *const module)
+        const struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_hw = &(module->hw->I2CM);
+    SercomI2cm *const i2c_hw = &(module->hw->I2CM);
 
 #if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
-	return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
+    return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY);
 #elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
-	return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
+    return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK);
 #else
 #  error Unknown SERCOM SYNCBUSY scheme!
 #endif
@@ -399,14 +400,15 @@ static inline bool i2c_master_is_syncing (
  * \param[in]  module  Pointer to software module structure
  */
 static void _i2c_master_wait_for_sync(
-		const struct i2c_master_module *const module)
+        const struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
+    /* Sanity check */
+    Assert(module);
 
-	while (i2c_master_is_syncing(module)) {
-		/* Wait for I2C module to sync. */
-	}
+    while (i2c_master_is_syncing(module))
+    {
+        /* Wait for I2C module to sync. */
+    }
 }
 #endif
 
@@ -435,39 +437,39 @@ static void _i2c_master_wait_for_sync(
  * \param[out] config  Pointer to configuration structure to be initiated
  */
 static inline void i2c_master_get_config_defaults(
-		struct i2c_master_config *const config)
+        struct i2c_master_config *const config)
 {
-	/*Sanity check argument */
-	Assert(config);
-	config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
+    /*Sanity check argument */
+    Assert(config);
+    config->baud_rate        = I2C_MASTER_BAUD_RATE_100KHZ;
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
-	config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
-	config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
+    config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ;
+    config->transfer_speed       = I2C_MASTER_SPEED_STANDARD_AND_FAST;
 #endif
-	config->generator_source = GCLK_GENERATOR_0;
-	config->run_in_standby   = false;
-	config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
-	config->buffer_timeout   = 65535;
-	config->unknown_bus_state_timeout = 65535;
-	config->pinmux_pad0      = PINMUX_DEFAULT;
-	config->pinmux_pad1      = PINMUX_DEFAULT;
-	config->scl_low_timeout  = false;
-	config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
+    config->generator_source = GCLK_GENERATOR_0;
+    config->run_in_standby   = false;
+    config->start_hold_time  = I2C_MASTER_START_HOLD_TIME_300NS_600NS;
+    config->buffer_timeout   = 65535;
+    config->unknown_bus_state_timeout = 65535;
+    config->pinmux_pad0      = PINMUX_DEFAULT;
+    config->pinmux_pad1      = PINMUX_DEFAULT;
+    config->scl_low_timeout  = false;
+    config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED;
 #ifdef FEATURE_I2C_SCL_STRETCH_MODE
-	config->scl_stretch_only_after_ack_bit = false;
+    config->scl_stretch_only_after_ack_bit = false;
 #endif
 #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
-	config->slave_scl_low_extend_timeout   = false;
-	config->master_scl_low_extend_timeout  = false;
+    config->slave_scl_low_extend_timeout   = false;
+    config->master_scl_low_extend_timeout  = false;
 #endif
-	/* The typical value is 215ns */
-	config->sda_scl_rise_time_ns = 215;
+    /* The typical value is 215ns */
+    config->sda_scl_rise_time_ns = 215;
 }
 
 enum status_code i2c_master_init(
-		struct i2c_master_module *const module,
-		Sercom *const hw,
-		const struct i2c_master_config *const config);
+        struct i2c_master_module *const module,
+        Sercom *const hw,
+        const struct i2c_master_config *const config);
 
 /**
  * \brief Enables the I<SUP>2</SUP>C module
@@ -479,37 +481,39 @@ enum status_code i2c_master_init(
  * \param[in]  module  Pointer to the software module struct
  */
 static inline void i2c_master_enable(
-		const struct i2c_master_module *const module)
+        const struct i2c_master_module *const module)
 {
-	/* Sanity check of arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check of arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Timeout counter used to force bus state */
-	uint32_t timeout_counter = 0;
+    /* Timeout counter used to force bus state */
+    uint32_t timeout_counter = 0;
 
-	/* Wait for module to sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for module to sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Enable module */
-	i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
+    /* Enable module */
+    i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE;
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Enable module interrupts */
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+    /* Enable module interrupts */
+    system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
 #endif
-	/* Start timeout if bus state is unknown */
-	while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) {
-		timeout_counter++;
-		if(timeout_counter >= (module->unknown_bus_state_timeout)) {
-			/* Timeout, force bus state to idle */
-			i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
-			/* Workaround #1 */
-			return;
-		}
-	}
+    /* Start timeout if bus state is unknown */
+    while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1)))
+    {
+        timeout_counter++;
+        if(timeout_counter >= (module->unknown_bus_state_timeout))
+        {
+            /* Timeout, force bus state to idle */
+            i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1);
+            /* Workaround #1 */
+            return;
+        }
+    }
 }
 
 /**
@@ -520,29 +524,29 @@ static inline void i2c_master_enable(
  * \param[in]  module  Pointer to the software module struct
  */
 static inline void i2c_master_disable(
-		const struct i2c_master_module *const module)
+        const struct i2c_master_module *const module)
 {
-	/* Sanity check of arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check of arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-		/* Disable module interrupts */
-		system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+        /* Disable module interrupts */
+        system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
 #endif
 
-	/* Wait for module to sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for module to sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Disbale interrupt */
-	i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
+    /* Disbale interrupt */
+    i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK;
 
-	/* Disable module */
-	i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
+    /* Disable module */
+    i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE;
 
 }
 
@@ -556,36 +560,36 @@ void i2c_master_reset(struct i2c_master_module *const module);
 */
 
 enum status_code i2c_master_read_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_read_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 void i2c_master_send_stop(struct i2c_master_module *const module);
 
 void i2c_master_send_nack(struct i2c_master_module *const module);
 
 enum status_code i2c_master_read_byte(
-		struct i2c_master_module *const module,
-		uint8_t *byte);
+        struct i2c_master_module *const module,
+        uint8_t *byte);
 
 enum status_code i2c_master_write_byte(
-		struct i2c_master_module *const module,
-		uint8_t byte);
+        struct i2c_master_module *const module,
+        uint8_t byte);
 
 enum status_code i2c_master_read_packet_wait_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 /** @} */
 
@@ -608,13 +612,13 @@ enum status_code i2c_master_read_packet_wait_no_nack(
  *
  */
 static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module,
-		uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
+        uint16_t addr, uint8_t length, enum i2c_transfer_direction direction)
 {
-	module->hw->I2CM.ADDR.reg =
-		SERCOM_I2CM_ADDR_ADDR(addr<<1) |
-		SERCOM_I2CM_ADDR_LENEN |
-		SERCOM_I2CM_ADDR_LEN(length) |
-		direction;
+    module->hw->I2CM.ADDR.reg =
+        SERCOM_I2CM_ADDR_ADDR(addr<<1) |
+        SERCOM_I2CM_ADDR_LENEN |
+        SERCOM_I2CM_ADDR_LEN(length) |
+        direction;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h
index 249525d3c14c..7f508a412287 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_master_interrupt.h
@@ -65,17 +65,17 @@ extern "C" {
  */
 #if !defined(__DOXYGEN__)
 void _i2c_master_interrupt_handler(
-		uint8_t instance);
+        uint8_t instance);
 #endif
 
 void i2c_master_register_callback(
-		struct i2c_master_module *const module,
-		i2c_master_callback_t callback,
-		enum i2c_master_callback callback_type);
+        struct i2c_master_module *const module,
+        i2c_master_callback_t callback,
+        enum i2c_master_callback callback_type);
 
 void i2c_master_unregister_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type);
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -86,15 +86,15 @@ void i2c_master_unregister_callback(
  * \param[in]     callback_type  Callback type to enable
  */
 static inline void i2c_master_enable_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as enabled */
-	module->enabled_callback |= (1 << callback_type);
+    /* Mark callback as enabled */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -106,15 +106,15 @@ static inline void i2c_master_enable_callback(
  * \param[in]     callback_type  Callback type to disable
  */
 static inline void i2c_master_disable_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Mark callback as disabled */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Mark callback as disabled */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /** @} */
@@ -125,32 +125,32 @@ static inline void i2c_master_disable_callback(
  */
 
 enum status_code i2c_master_read_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
- 
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
+
 enum status_code i2c_master_read_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_read_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_read_packet_job_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 enum status_code i2c_master_write_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet);
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet);
 
 /**
  * \brief Cancel any currently ongoing operation
@@ -160,16 +160,16 @@ enum status_code i2c_master_write_packet_job_no_stop(
  * \param[in,out] module  Pointer to software module structure
  */
 static inline void i2c_master_cancel_job(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Set buffer to 0 */
-	module->buffer_remaining = 0;
-	/* Update status */
-	module->status = STATUS_ABORTED;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Set buffer to 0 */
+    module->buffer_remaining = 0;
+    /* Update status */
+    module->status = STATUS_ABORTED;
 }
 
 /**
@@ -193,14 +193,14 @@ static inline void i2c_master_cancel_job(
  *                                      want more data and was not able to read
  */
 static inline enum status_code i2c_master_get_job_status(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Check sanity */
-	Assert(module);
-	Assert(module->hw);
+    /* Check sanity */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Return current status code */
-	return module->status;
+    /* Return current status code */
+    return module->status;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c
index 2122e8d1f340..10f99cd92c24 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c
@@ -52,14 +52,14 @@
 
 /* Forward declaration */
 enum status_code _i2c_master_wait_for_bus(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 
 enum status_code _i2c_master_address_response(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 
 enum status_code _i2c_master_send_hs_master_code(
-		struct i2c_master_module *const module,
-		uint8_t hs_master_code);
+        struct i2c_master_module *const module,
+        uint8_t hs_master_code);
 
 #if !defined(__DOXYGEN__)
 
@@ -77,132 +77,145 @@ enum status_code _i2c_master_send_hs_master_code(
  *                                          with set GCLK frequency
  */
 static enum status_code _i2c_master_set_config(
-		struct i2c_master_module *const module,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-
-	/* Temporary variables. */
-	uint32_t tmp_ctrla;
-	int32_t tmp_baud = 0;
-	int32_t tmp_baud_hs = 0;
-	int32_t tmp_baudlow_hs = 0;
-	enum status_code tmp_status_code = STATUS_OK;
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	Sercom *const sercom_hw = module->hw;
-
-	uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
-
-	/* Pin configuration */
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	uint32_t pad0 = config->pinmux_pad0;
-	uint32_t pad1 = config->pinmux_pad1;
-
-	/* SERCOM PAD0 - SDA */
-	if (pad0 == PINMUX_DEFAULT) {
-		pad0 = _sercom_get_default_pad(sercom_hw, 0);
-	}
-	pin_conf.mux_position = pad0 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
-
-	/* SERCOM PAD1 - SCL */
-	if (pad1 == PINMUX_DEFAULT) {
-		pad1 = _sercom_get_default_pad(sercom_hw, 1);
-	}
-	pin_conf.mux_position = pad1 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
-
-	/* Save timeout on unknown bus state in software module. */
-	module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
-
-	/* Save timeout on buffer write. */
-	module->buffer_timeout = config->buffer_timeout;
-
-	/* Set whether module should run in standby. */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
-	} else {
-		tmp_ctrla = 0;
-	}
-
-	/* Check and set start data hold timeout. */
-	if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
-		tmp_ctrla |= config->start_hold_time;
-	}
-
-	/* Check and set transfer speed */
-	tmp_ctrla |= config->transfer_speed;
-
-	/* Check and set SCL low timeout. */
-	if (config->scl_low_timeout) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
-	}
-
-	/* Check and set inactive bus timeout. */
-	if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
-		tmp_ctrla |= config->inactive_timeout;
-	}
-
-	/* Check and set SCL clock stretch mode. */
-	if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
-	}
-
-	/* Check and set slave SCL low extend timeout. */
-	if (config->slave_scl_low_extend_timeout) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
-	}
-
-	/* Check and set master SCL low extend timeout. */
-	if (config->master_scl_low_extend_timeout) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
-	}
-
-	/* Write config to register CTRLA. */
-	i2c_module->CTRLA.reg |= tmp_ctrla;
-
-	/* Set configurations in CTRLB. */
-	i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
-
-	/* Find and set baudrate, considering sda/scl rise time */
-	uint32_t fgclk       = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index);
-	uint32_t fscl        = 1000 * config->baud_rate;
-	uint32_t fscl_hs     = 1000 * config->baud_rate_high_speed;
-	uint32_t trise       = config->sda_scl_rise_time_ns;
-	
-	tmp_baud = (int32_t)(div_ceil(
-			fgclk - fscl * (10 + (fgclk * 0.000000001)* trise), 2 * fscl));
-	
-	/* For High speed mode, set the SCL ratio of high:low to 1:2. */
-	if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED) {
-		tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1);
-		if (tmp_baudlow_hs) {
-			tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs;
-		} else {
-			tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1;
-		}
-	}
-
-	/* Check that baudrate is supported at current speed. */
-	if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
-		/* Baud rate not supported. */
-		tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	}
-	if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) {
-		/* Baud rate acceptable. */
-		i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
-			SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs);
-	}
-
-	return tmp_status_code;
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    /* Temporary variables. */
+    uint32_t tmp_ctrla;
+    int32_t tmp_baud = 0;
+    int32_t tmp_baud_hs = 0;
+    int32_t tmp_baudlow_hs = 0;
+    enum status_code tmp_status_code = STATUS_OK;
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    Sercom *const sercom_hw = module->hw;
+
+    uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
+
+    /* Pin configuration */
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    uint32_t pad0 = config->pinmux_pad0;
+    uint32_t pad1 = config->pinmux_pad1;
+
+    /* SERCOM PAD0 - SDA */
+    if (pad0 == PINMUX_DEFAULT)
+    {
+        pad0 = _sercom_get_default_pad(sercom_hw, 0);
+    }
+    pin_conf.mux_position = pad0 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+    /* SERCOM PAD1 - SCL */
+    if (pad1 == PINMUX_DEFAULT)
+    {
+        pad1 = _sercom_get_default_pad(sercom_hw, 1);
+    }
+    pin_conf.mux_position = pad1 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+    /* Save timeout on unknown bus state in software module. */
+    module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
+
+    /* Save timeout on buffer write. */
+    module->buffer_timeout = config->buffer_timeout;
+
+    /* Set whether module should run in standby. */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
+    } else {
+        tmp_ctrla = 0;
+    }
+
+    /* Check and set start data hold timeout. */
+    if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED)
+    {
+        tmp_ctrla |= config->start_hold_time;
+    }
+
+    /* Check and set transfer speed */
+    tmp_ctrla |= config->transfer_speed;
+
+    /* Check and set SCL low timeout. */
+    if (config->scl_low_timeout)
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
+    }
+
+    /* Check and set inactive bus timeout. */
+    if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED)
+    {
+        tmp_ctrla |= config->inactive_timeout;
+    }
+
+    /* Check and set SCL clock stretch mode. */
+    if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED))
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
+    }
+
+    /* Check and set slave SCL low extend timeout. */
+    if (config->slave_scl_low_extend_timeout)
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
+    }
+
+    /* Check and set master SCL low extend timeout. */
+    if (config->master_scl_low_extend_timeout)
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
+    }
+
+    /* Write config to register CTRLA. */
+    i2c_module->CTRLA.reg |= tmp_ctrla;
+
+    /* Set configurations in CTRLB. */
+    i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
+
+    /* Find and set baudrate, considering sda/scl rise time */
+    uint32_t fgclk       = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index);
+    uint32_t fscl        = 1000 * config->baud_rate;
+    uint32_t fscl_hs     = 1000 * config->baud_rate_high_speed;
+    uint32_t trise       = config->sda_scl_rise_time_ns;
+
+    tmp_baud = (int32_t)(div_ceil(
+            fgclk - fscl * (10 + (fgclk * 0.000000001)* trise), 2 * fscl));
+
+    /* For High speed mode, set the SCL ratio of high:low to 1:2. */
+    if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)
+    {
+        tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1);
+        if (tmp_baudlow_hs)
+        {
+            tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs;
+        } else {
+            tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1;
+        }
+    }
+
+    /* Check that baudrate is supported at current speed. */
+    if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0)
+    {
+        /* Baud rate not supported. */
+        tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+    }
+    if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE)
+    {
+        /* Baud rate acceptable. */
+        i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
+            SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs);
+    }
+
+    return tmp_status_code;
 }
 #endif /* __DOXYGEN__ */
 
@@ -228,96 +241,101 @@ static enum status_code _i2c_master_set_config(
  *
  */
 enum status_code i2c_master_init(
-		struct i2c_master_module *const module,
-		Sercom *const hw,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        Sercom *const hw,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize software module */
-	module->hw = hw;
+    /* Initialize software module */
+    module->hw = hw;
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index, gclk_index;
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index, gclk_index;
 
 #if (SAML22) || (SAMC20)
-	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #elif (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
+    if (sercom_index == 5)
+    {
+        pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+        gclk_index   = SERCOM5_GCLK_ID_CORE;
+    } else {
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
 #elif (SAMC21)
-	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	if (sercom_index == 5) {
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
+    pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    if (sercom_index == 5)
+    {
+        gclk_index   = SERCOM5_GCLK_ID_CORE;
+    } else {
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
 #else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #endif
 
-	/* Turn on module in PM */
+    /* Turn on module in PM */
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
-	} else {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-	}
+    if (sercom_index == 5)
+    {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+    } else {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    }
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
 #endif
 
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
-
-	/* Check if module is enabled. */
-	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress. */
-	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
+
+    /* Check if module is enabled. */
+    if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress. */
+    if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Get sercom instance index and register callback. */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
-	_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
-	_sercom_instances[instance_index] = module;
-
-	/* Initialize values in module. */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->buffer_remaining = 0;
-
-	module->status = STATUS_OK;
-	module->buffer = NULL;
+    /* Get sercom instance index and register callback. */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    _sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
+    _sercom_instances[instance_index] = module;
+
+    /* Initialize values in module. */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->buffer_remaining = 0;
+
+    module->status = STATUS_OK;
+    module->buffer = NULL;
 #endif
 
-	/* Set sercom module to operate in I2C master mode. */
-	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
+    /* Set sercom module to operate in I2C master mode. */
+    i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
 
-	/* Set config and return status. */
-	return _i2c_master_set_config(module, config);
+    /* Set config and return status. */
+    return _i2c_master_set_config(module, config);
 }
 
 /**
@@ -329,30 +347,30 @@ enum status_code i2c_master_init(
  */
 void i2c_master_reset(struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Wait for sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Disable module */
-	i2c_master_disable(module);
+    /* Disable module */
+    i2c_master_disable(module);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Clear all pending interrupts */
-	system_interrupt_enter_critical_section();
-	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
-	system_interrupt_leave_critical_section();
+    /* Clear all pending interrupts */
+    system_interrupt_enter_critical_section();
+    system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_leave_critical_section();
 #endif
 
-	/* Wait for sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Reset module */
-	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
+    /* Reset module */
+    i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
 }
 
 #if !defined(__DOXYGEN__)
@@ -370,36 +388,39 @@ void i2c_master_reset(struct i2c_master_module *const module)
  *                                      acknowledged the address
  */
 enum status_code _i2c_master_address_response(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
-	 * BUSY */
-	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
-
-		/* Clear write interrupt flag */
-		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
-
-		/* Check arbitration. */
-		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
-			/* Return packet collision. */
-			return STATUS_ERR_PACKET_COLLISION;
-		}
-	/* Check that slave responded with ack. */
-	} else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-		/* Slave busy. Issue ack and stop command. */
-		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-
-		/* Return bad address value. */
-		return STATUS_ERR_BAD_ADDRESS;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
+     * BUSY */
+    if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)
+    {
+
+        /* Clear write interrupt flag */
+        i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+
+        /* Check arbitration. */
+        if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST)
+        {
+            /* Return packet collision. */
+            return STATUS_ERR_PACKET_COLLISION;
+        }
+    /* Check that slave responded with ack. */
+    } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+    {
+        /* Slave busy. Issue ack and stop command. */
+        i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+
+        /* Return bad address value. */
+        return STATUS_ERR_BAD_ADDRESS;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -414,25 +435,27 @@ enum status_code _i2c_master_address_response(
  *                             period
  */
 enum status_code _i2c_master_wait_for_bus(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Wait for reply. */
-	uint16_t timeout_counter = 0;
-	while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
-			!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
-
-		/* Check timeout condition. */
-		if (++timeout_counter >= module->buffer_timeout) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Wait for reply. */
+    uint16_t timeout_counter = 0;
+    while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
+            !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB))
+            {
+
+        /* Check timeout condition. */
+        if (++timeout_counter >= module->buffer_timeout)
+        {
+            return STATUS_ERR_TIMEOUT;
+        }
+    }
+    return STATUS_OK;
 }
 #endif /* __DOXYGEN__ */
 
@@ -447,23 +470,23 @@ enum status_code _i2c_master_wait_for_bus(
  * \retval STATUS_OK           No error happen
  */
 enum status_code _i2c_master_send_hs_master_code(
-		struct i2c_master_module *const module,
-		uint8_t hs_master_code)
+        struct i2c_master_module *const module,
+        uint8_t hs_master_code)
 {
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	/* Return value. */
-	enum status_code tmp_status;
-
-	/* Set NACK for high speed code */
-	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-	/* Send high speed code */
-	i2c_module->ADDR.reg = hs_master_code;
-	/* Wait for response on bus. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-	/* Clear write interrupt flag */
-	i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
-
-	return tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    /* Return value. */
+    enum status_code tmp_status;
+
+    /* Set NACK for high speed code */
+    i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    /* Send high speed code */
+    i2c_module->ADDR.reg = hs_master_code;
+    /* Wait for response on bus. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+    /* Clear write interrupt flag */
+    i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+    return tmp_status;
 }
 
 
@@ -485,126 +508,138 @@ enum status_code _i2c_master_send_hs_master_code(
  *
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Return value. */
-	enum status_code tmp_status;
-	uint16_t tmp_data_length = packet->data_length;
-
-	/* Written buffer counter. */
-	uint16_t counter = 0;
-
-	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
-
-	/* Switch to high speed mode */
-	if (packet->high_speed) {
-		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
-	}
-
-	/* Set action to ACK. */
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-	/* Set address and direction bit. Will send start command on bus. */
-	if (packet->ten_bit_address) {
-		/*
-		 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
-		 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
-		 */
-		i2c_module->ADDR.reg = (packet->address << 1) |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-			SERCOM_I2CM_ADDR_TENBITEN;
-
-		/* Wait for response on bus. */
-		tmp_status = _i2c_master_wait_for_bus(module);
-
-		/* Set action to ack. */
-		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-		/* Check for address response error unless previous error is
-		 * detected. */
-		if (tmp_status == STATUS_OK) {
-			tmp_status = _i2c_master_address_response(module);
-		}
-
-		if (tmp_status == STATUS_OK) {
-			/*
-			 * Write ADDR[7:0] register to "11110 address[9:8] 1"
-			 * ADDR.TENBITEN must be cleared
-			 */
-			i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
-				(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-				I2C_TRANSFER_READ;
-		} else {
-			return tmp_status;
-		}
-	} else {
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
-	}
-
-	/* Wait for response on bus. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-
-	/* Set action to ack or nack. */
-	if ((sclsm_flag) && (packet->data_length == 1)) {
-		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-	} else {
-		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;	
-	}
-
-	/* Check for address response error unless previous error is
-	 * detected. */
-	if (tmp_status == STATUS_OK) {
-		tmp_status = _i2c_master_address_response(module);
-	}
-
-	/* Check that no error has occurred. */
-	if (tmp_status == STATUS_OK) {
-		/* Read data buffer. */
-		while (tmp_data_length--) {
-			/* Check that bus ownership is not lost. */
-			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
-				return STATUS_ERR_PACKET_COLLISION;
-			}
-
-			if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) ||
-					((sclsm_flag) && (tmp_data_length == 1)))) {
-				/* Set action to NACK */
-				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-			} else {
-				/* Save data to buffer. */
-				_i2c_master_wait_for_sync(module);
-				packet->data[counter++] = i2c_module->DATA.reg;
-				/* Wait for response. */
-				tmp_status = _i2c_master_wait_for_bus(module);
-			}
-
-			/* Check for error. */
-			if (tmp_status != STATUS_OK) {
-				break;
-			}
-		}
-
-		if (module->send_stop) {
-			/* Send stop command unless arbitration is lost. */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		}
-
-		/* Save last data to buffer. */
-		_i2c_master_wait_for_sync(module);
-		packet->data[counter] = i2c_module->DATA.reg;
-	}
-
-	return tmp_status;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Return value. */
+    enum status_code tmp_status;
+    uint16_t tmp_data_length = packet->data_length;
+
+    /* Written buffer counter. */
+    uint16_t counter = 0;
+
+    bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+    /* Switch to high speed mode */
+    if (packet->high_speed)
+    {
+        _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+    }
+
+    /* Set action to ACK. */
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+    /* Set address and direction bit. Will send start command on bus. */
+    if (packet->ten_bit_address)
+    {
+        /*
+         * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+         * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+         */
+        i2c_module->ADDR.reg = (packet->address << 1) |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+            SERCOM_I2CM_ADDR_TENBITEN;
+
+        /* Wait for response on bus. */
+        tmp_status = _i2c_master_wait_for_bus(module);
+
+        /* Set action to ack. */
+        i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+        /* Check for address response error unless previous error is
+         * detected. */
+        if (tmp_status == STATUS_OK)
+        {
+            tmp_status = _i2c_master_address_response(module);
+        }
+
+        if (tmp_status == STATUS_OK)
+        {
+            /*
+             * Write ADDR[7:0] register to "11110 address[9:8] 1"
+             * ADDR.TENBITEN must be cleared
+             */
+            i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+                (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+                I2C_TRANSFER_READ;
+        } else {
+            return tmp_status;
+        }
+    } else {
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+    }
+
+    /* Wait for response on bus. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+
+    /* Set action to ack or nack. */
+    if ((sclsm_flag) && (packet->data_length == 1))
+    {
+        i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    } else {
+        i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+    }
+
+    /* Check for address response error unless previous error is
+     * detected. */
+    if (tmp_status == STATUS_OK)
+    {
+        tmp_status = _i2c_master_address_response(module);
+    }
+
+    /* Check that no error has occurred. */
+    if (tmp_status == STATUS_OK)
+    {
+        /* Read data buffer. */
+        while (tmp_data_length--)
+        {
+            /* Check that bus ownership is not lost. */
+            if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2)))
+            {
+                return STATUS_ERR_PACKET_COLLISION;
+            }
+
+            if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) ||
+                    ((sclsm_flag) && (tmp_data_length == 1))))
+                    {
+                /* Set action to NACK */
+                i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+            } else {
+                /* Save data to buffer. */
+                _i2c_master_wait_for_sync(module);
+                packet->data[counter++] = i2c_module->DATA.reg;
+                /* Wait for response. */
+                tmp_status = _i2c_master_wait_for_bus(module);
+            }
+
+            /* Check for error. */
+            if (tmp_status != STATUS_OK)
+            {
+                break;
+            }
+        }
+
+        if (module->send_stop)
+        {
+            /* Send stop command unless arbitration is lost. */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        }
+
+        /* Save last data to buffer. */
+        _i2c_master_wait_for_sync(module);
+        packet->data[counter] = i2c_module->DATA.reg;
+    }
+
+    return tmp_status;
 }
 
 /**
@@ -629,25 +664,26 @@ static enum status_code _i2c_master_read_packet(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = true;
-	module->send_nack = true;
+    module->send_stop = true;
+    module->send_nack = true;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -676,25 +712,26 @@ enum status_code i2c_master_read_packet_wait(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = true;
+    module->send_stop = false;
+    module->send_nack = true;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -726,25 +763,26 @@ enum status_code i2c_master_read_packet_wait_no_stop(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = false;
+    module->send_stop = false;
+    module->send_nack = false;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -764,83 +802,92 @@ enum status_code i2c_master_read_packet_wait_no_nack(
  *                                      acknowledged the address
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Return value. */
-	enum status_code tmp_status;
-	uint16_t tmp_data_length = packet->data_length;
-
-	_i2c_master_wait_for_sync(module);
-
-	/* Switch to high speed mode */
-	if (packet->high_speed) {
-		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
-	}
-
-	/* Set action to ACK. */
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-	/* Set address and direction bit. Will send start command on bus. */
-	if (packet->ten_bit_address) {
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-			SERCOM_I2CM_ADDR_TENBITEN;
-	} else {
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
-	}
-	/* Wait for response on bus. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-
-	/* Check for address response error unless previous error is
-	 * detected. */
-	if (tmp_status == STATUS_OK) {
-		tmp_status = _i2c_master_address_response(module);
-	}
-
-	/* Check that no error has occurred. */
-	if (tmp_status == STATUS_OK) {
-		/* Buffer counter. */
-		uint16_t buffer_counter = 0;
-
-		/* Write data buffer. */
-		while (tmp_data_length--) {
-			/* Check that bus ownership is not lost. */
-			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
-				return STATUS_ERR_PACKET_COLLISION;
-			}
-
-			/* Write byte to slave. */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->DATA.reg = packet->data[buffer_counter++];
-
-			/* Wait for response. */
-			tmp_status = _i2c_master_wait_for_bus(module);
-
-			/* Check for error. */
-			if (tmp_status != STATUS_OK) {
-				break;
-			}
-
-			/* Check for NACK from slave. */
-			if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-				/* Return bad data value. */
-				tmp_status = STATUS_ERR_OVERFLOW;
-				break;
-			}
-		}
-
-		if (module->send_stop) {
-			/* Stop command */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		}
-	}
-
-	return tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Return value. */
+    enum status_code tmp_status;
+    uint16_t tmp_data_length = packet->data_length;
+
+    _i2c_master_wait_for_sync(module);
+
+    /* Switch to high speed mode */
+    if (packet->high_speed)
+    {
+        _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+    }
+
+    /* Set action to ACK. */
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+    /* Set address and direction bit. Will send start command on bus. */
+    if (packet->ten_bit_address)
+    {
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+            SERCOM_I2CM_ADDR_TENBITEN;
+    } else {
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+    }
+    /* Wait for response on bus. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+
+    /* Check for address response error unless previous error is
+     * detected. */
+    if (tmp_status == STATUS_OK)
+    {
+        tmp_status = _i2c_master_address_response(module);
+    }
+
+    /* Check that no error has occurred. */
+    if (tmp_status == STATUS_OK)
+    {
+        /* Buffer counter. */
+        uint16_t buffer_counter = 0;
+
+        /* Write data buffer. */
+        while (tmp_data_length--)
+        {
+            /* Check that bus ownership is not lost. */
+            if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2)))
+            {
+                return STATUS_ERR_PACKET_COLLISION;
+            }
+
+            /* Write byte to slave. */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->DATA.reg = packet->data[buffer_counter++];
+
+            /* Wait for response. */
+            tmp_status = _i2c_master_wait_for_bus(module);
+
+            /* Check for error. */
+            if (tmp_status != STATUS_OK)
+            {
+                break;
+            }
+
+            /* Check for NACK from slave. */
+            if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+            {
+                /* Return bad data value. */
+                tmp_status = STATUS_ERR_OVERFLOW;
+                break;
+            }
+        }
+
+        if (module->send_stop)
+        {
+            /* Stop command */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        }
+    }
+
+    return tmp_status;
 }
 
 /**
@@ -869,25 +916,26 @@ static enum status_code _i2c_master_write_packet(
  *                                      last data sent
  */
 enum status_code i2c_master_write_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = true;
-	module->send_nack = true;
+    module->send_stop = true;
+    module->send_nack = true;
 
-	return _i2c_master_write_packet(module, packet);
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -918,25 +966,26 @@ enum status_code i2c_master_write_packet_wait(
  *                                      more data
  */
 enum status_code i2c_master_write_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = true;
+    module->send_stop = false;
+    module->send_nack = true;
 
-	return _i2c_master_write_packet(module, packet);
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -953,15 +1002,15 @@ enum status_code i2c_master_write_packet_wait_no_stop(
  */
 void i2c_master_send_stop(struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Send stop command */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+    /* Send stop command */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
 }
 
 /**
@@ -976,15 +1025,15 @@ void i2c_master_send_stop(struct i2c_master_module *const module)
  */
 void i2c_master_send_nack(struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Send nack signal */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    /* Send nack signal */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
 }
 
 /**
@@ -1003,20 +1052,20 @@ void i2c_master_send_nack(struct i2c_master_module *const module)
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_byte(
-		struct i2c_master_module *const module,
-		uint8_t *byte)
+        struct i2c_master_module *const module,
+        uint8_t *byte)
 {
-  	enum status_code tmp_status;
-  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    enum status_code tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-	/* Write byte to slave. */
-	_i2c_master_wait_for_sync(module);
-	*byte = i2c_module->DATA.reg;
-	/* Wait for response. */
-	tmp_status = _i2c_master_wait_for_bus(module);
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+    /* Write byte to slave. */
+    _i2c_master_wait_for_sync(module);
+    *byte = i2c_module->DATA.reg;
+    /* Wait for response. */
+    tmp_status = _i2c_master_wait_for_bus(module);
 
-	return tmp_status;
+    return tmp_status;
 }
 
 /**
@@ -1035,16 +1084,16 @@ enum status_code i2c_master_read_byte(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_write_byte(
-		struct i2c_master_module *const module,
-		uint8_t byte)
+        struct i2c_master_module *const module,
+        uint8_t byte)
 {
-  	enum status_code tmp_status;
-  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Write byte to slave. */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->DATA.reg = byte;
-	/* Wait for response. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-	return tmp_status;
+    enum status_code tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Write byte to slave. */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->DATA.reg = byte;
+    /* Wait for response. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+    return tmp_status;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c
index 7551b291256f..dceb40e4cf5d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c
@@ -47,14 +47,14 @@
 #include "i2c_master_interrupt.h"
 
 extern enum status_code _i2c_master_wait_for_bus(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 
 extern enum status_code _i2c_master_address_response(
-		struct i2c_master_module *const module);
+        struct i2c_master_module *const module);
 
 extern enum status_code _i2c_master_send_hs_master_code(
-		struct i2c_master_module *const module,
-		uint8_t hs_master_code);;
+        struct i2c_master_module *const module,
+        uint8_t hs_master_code);;
 
 /**
  * \internal
@@ -63,44 +63,49 @@ extern enum status_code _i2c_master_send_hs_master_code(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_master_read(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
-
-	/* Find index to save next value in buffer */
-	uint16_t buffer_index = module->buffer_length;
-	buffer_index -= module->buffer_remaining;
-
-	module->buffer_remaining--;
-
-	if (sclsm_flag) {
-		if (module->send_nack && module->buffer_remaining == 1) {
-			/* Set action to NACK. */
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-		}
-	} else {
-		if (module->send_nack && module->buffer_remaining == 0) {
-			/* Set action to NACK. */
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-		}
-	}
-
-	if (module->buffer_remaining == 0) {
-		if (module->send_stop) {
-			/* Send stop condition */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		}
-	}
-	
-	/* Read byte from slave and put in buffer */
-	_i2c_master_wait_for_sync(module);
-	module->buffer[buffer_index] = i2c_module->DATA.reg;
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+    /* Find index to save next value in buffer */
+    uint16_t buffer_index = module->buffer_length;
+    buffer_index -= module->buffer_remaining;
+
+    module->buffer_remaining--;
+
+    if (sclsm_flag)
+    {
+        if (module->send_nack && module->buffer_remaining == 1)
+        {
+            /* Set action to NACK. */
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+        }
+    } else {
+        if (module->send_nack && module->buffer_remaining == 0)
+        {
+            /* Set action to NACK. */
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+        }
+    }
+
+    if (module->buffer_remaining == 0)
+    {
+        if (module->send_stop)
+        {
+            /* Send stop condition */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        }
+    }
+
+    /* Read byte from slave and put in buffer */
+    _i2c_master_wait_for_sync(module);
+    module->buffer[buffer_index] = i2c_module->DATA.reg;
 }
 
 /**
@@ -112,30 +117,30 @@ static void _i2c_master_read(
  */
 static void _i2c_master_write(struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Check for ack from slave */
-	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
-	{
-		/* Set status */
-		module->status = STATUS_ERR_OVERFLOW;
-		/* Do not write more data */
-		return;
-	}
-
-	/* Find index to get next byte in buffer */
-	uint16_t buffer_index = module->buffer_length;
-	buffer_index -= module->buffer_remaining;
-
-	module->buffer_remaining--;
-
-	/* Write byte from buffer to slave */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->DATA.reg = module->buffer[buffer_index];
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Check for ack from slave */
+    if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+    {
+        /* Set status */
+        module->status = STATUS_ERR_OVERFLOW;
+        /* Do not write more data */
+        return;
+    }
+
+    /* Find index to get next byte in buffer */
+    uint16_t buffer_index = module->buffer_length;
+    buffer_index -= module->buffer_remaining;
+
+    module->buffer_remaining--;
+
+    /* Write byte from buffer to slave */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->DATA.reg = module->buffer[buffer_index];
 }
 
 /**
@@ -146,51 +151,56 @@ static void _i2c_master_write(struct i2c_master_module *const module)
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_master_async_address_response(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Check for error. Ignore bus-error; workaround for bus state stuck in
-	 * BUSY.
-	 */
-	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
-	{
-		/* Clear write interrupt flag */
-		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
-
-		/* Check arbitration */
-		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
-			/* Return busy */
-			module->status = STATUS_ERR_PACKET_COLLISION;
-		}
-		/* No slave responds */
-		else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-			module->status           = STATUS_ERR_BAD_ADDRESS;
-			module->buffer_remaining = 0;
-
-			if (module->send_stop) {
-				/* Send stop condition */
-				_i2c_master_wait_for_sync(module);
-				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-			}
-		}
-	}
-
-	module->buffer_length = module->buffer_remaining;
-
-	/* Check for status OK. */
-	if (module->status == STATUS_BUSY) {
-		/* Call function based on transfer direction. */
-		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-			_i2c_master_write(module);
-		} else {
-			_i2c_master_read(module);
-		}
-	}
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Check for error. Ignore bus-error; workaround for bus state stuck in
+     * BUSY.
+     */
+    if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
+    {
+        /* Clear write interrupt flag */
+        i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+        /* Check arbitration */
+        if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST)
+        {
+            /* Return busy */
+            module->status = STATUS_ERR_PACKET_COLLISION;
+        }
+        /* No slave responds */
+        else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+        {
+            module->status           = STATUS_ERR_BAD_ADDRESS;
+            module->buffer_remaining = 0;
+
+            if (module->send_stop)
+            {
+                /* Send stop condition */
+                _i2c_master_wait_for_sync(module);
+                i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+            }
+        }
+    }
+
+    module->buffer_length = module->buffer_remaining;
+
+    /* Check for status OK. */
+    if (module->status == STATUS_BUSY)
+    {
+        /* Call function based on transfer direction. */
+        if (module->transfer_direction == I2C_TRANSFER_WRITE)
+        {
+            _i2c_master_write(module);
+        } else {
+            _i2c_master_read(module);
+        }
+    }
 }
 
 /**
@@ -208,20 +218,20 @@ static void _i2c_master_async_address_response(
  * \param[in]      callback_type  Callback type to register
  */
 void i2c_master_register_callback(
-		struct i2c_master_module *const module,
-		const i2c_master_callback_t callback,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        const i2c_master_callback_t callback,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback */
-	module->callbacks[callback_type] = callback;
+    /* Register callback */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as registered */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as registered */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -234,18 +244,18 @@ void i2c_master_register_callback(
  * \param[in]     callback_type  Specifies the callback type to unregister
  */
 void i2c_master_unregister_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Register callback */
-	module->callbacks[callback_type] = NULL;
+    /* Register callback */
+    module->callbacks[callback_type] = NULL;
 
-	/* Clear corresponding bit to set callback as unregistered */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Clear corresponding bit to set callback as unregistered */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -260,28 +270,28 @@ void i2c_master_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_read_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_READ;
-	module->status             = STATUS_BUSY;
-	module->send_stop = false;
-	module->send_nack = false;
-	
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_READ;
+    module->status             = STATUS_BUSY;
+    module->send_stop = false;
+    module->send_nack = false;
+
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+    return STATUS_OK;
 }
 
 /**
@@ -296,83 +306,88 @@ enum status_code i2c_master_read_bytes(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	enum status_code tmp_status;
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_READ;
-	module->status             = STATUS_BUSY;
-
-	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
-
-	/* Switch to high speed mode */
-	if (packet->high_speed) {
-		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
-	}
-
-	/* Set action to ACK or NACK. */
-	if ((sclsm_flag) && (packet->data_length == 1)) {
-		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-	} else {
-		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-	}
-
-	if (packet->ten_bit_address) {
-		/*
-		 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
-		 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
-		 */
-		i2c_module->ADDR.reg = (packet->address << 1) |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-			SERCOM_I2CM_ADDR_TENBITEN;
-
-		/* Wait for response on bus. */
-		tmp_status = _i2c_master_wait_for_bus(module);
-
-		/* Set action to ack. */
-		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-		/* Check for address response error unless previous error is
-		 * detected. */
-		if (tmp_status == STATUS_OK) {
-			tmp_status = _i2c_master_address_response(module);
-		}
-
-		if (tmp_status == STATUS_OK) {
-			/* Enable interrupts */
-			i2c_module->INTENSET.reg =
-				SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-			/*
-			 * Write ADDR[7:0] register to "11110 address[9:8] 1"
-			 * ADDR.TENBITEN must be cleared
-			 */
-			i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
-				(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-				I2C_TRANSFER_READ;
-		} else {
-			return tmp_status;
-		}
-	} else {
-		/* Enable interrupts */
-		i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-		/* Set address and direction bit. Will send start command on bus */
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
-	}
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    enum status_code tmp_status;
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_READ;
+    module->status             = STATUS_BUSY;
+
+    bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+    /* Switch to high speed mode */
+    if (packet->high_speed)
+    {
+        _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+    }
+
+    /* Set action to ACK or NACK. */
+    if ((sclsm_flag) && (packet->data_length == 1))
+    {
+        i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    } else {
+        i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+    }
+
+    if (packet->ten_bit_address)
+    {
+        /*
+         * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
+         * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
+         */
+        i2c_module->ADDR.reg = (packet->address << 1) |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+            SERCOM_I2CM_ADDR_TENBITEN;
+
+        /* Wait for response on bus. */
+        tmp_status = _i2c_master_wait_for_bus(module);
+
+        /* Set action to ack. */
+        i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+        /* Check for address response error unless previous error is
+         * detected. */
+        if (tmp_status == STATUS_OK)
+        {
+            tmp_status = _i2c_master_address_response(module);
+        }
+
+        if (tmp_status == STATUS_OK)
+        {
+            /* Enable interrupts */
+            i2c_module->INTENSET.reg =
+                SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+            /*
+             * Write ADDR[7:0] register to "11110 address[9:8] 1"
+             * ADDR.TENBITEN must be cleared
+             */
+            i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
+                (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+                I2C_TRANSFER_READ;
+        } else {
+            return tmp_status;
+        }
+    } else {
+        /* Enable interrupts */
+        i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+        /* Set address and direction bit. Will send start command on bus */
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -389,24 +404,25 @@ static enum status_code _i2c_master_read_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_read_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP */
-	module->send_stop = true;
-	module->send_nack = true;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP */
+    module->send_stop = true;
+    module->send_nack = true;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -428,28 +444,29 @@ enum status_code i2c_master_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another operation
  */
 enum status_code i2c_master_read_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we don't send STOP */
-	module->send_stop = false;
-	module->send_nack = true;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we don't send STOP */
+    module->send_stop = false;
+    module->send_nack = true;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
- * \brief Initiates a read packet operation without sending a NACK signal and a 
+ * \brief Initiates a read packet operation without sending a NACK signal and a
  * STOP condition when done
  *
  * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
@@ -468,24 +485,25 @@ enum status_code i2c_master_read_packet_job_no_stop(
  * \retval STATUS_BUSY If module is currently busy with another operation
  */
 enum status_code i2c_master_read_packet_job_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we don't send STOP */
-	module->send_stop = false;
-	module->send_nack = false;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we don't send STOP */
+    module->send_stop = false;
+    module->send_nack = false;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -500,28 +518,28 @@ enum status_code i2c_master_read_packet_job_no_nack(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_write_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_WRITE;
-	module->status             = STATUS_BUSY;
-	module->send_stop = false;
-	module->send_nack = false;
-	
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_WRITE;
+    module->status             = STATUS_BUSY;
+    module->send_stop = false;
+    module->send_nack = false;
+
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+    return STATUS_OK;
 }
 
 /**
@@ -535,44 +553,46 @@ enum status_code i2c_master_write_bytes(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Switch to high speed mode */
-	if (packet->high_speed) {
-		_i2c_master_send_hs_master_code(module, packet->hs_master_code);
-	}
-
-	/* Set action to ACK. */
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_WRITE;
-	module->status             = STATUS_BUSY;
-
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-	/* Set address and direction bit, will send start command on bus */
-	if (packet->ten_bit_address) {
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
-			SERCOM_I2CM_ADDR_TENBITEN;
-	} else {
-		i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
-			(packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
-	}
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Switch to high speed mode */
+    if (packet->high_speed)
+    {
+        _i2c_master_send_hs_master_code(module, packet->hs_master_code);
+    }
+
+    /* Set action to ACK. */
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_WRITE;
+    module->status             = STATUS_BUSY;
+
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+    /* Set address and direction bit, will send start command on bus */
+    if (packet->ten_bit_address)
+    {
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
+            SERCOM_I2CM_ADDR_TENBITEN;
+    } else {
+        i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
+            (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -589,24 +609,25 @@ static enum status_code _i2c_master_write_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_write_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP at end*/
-	module->send_stop = true;
-	module->send_nack = true;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP at end*/
+    module->send_stop = true;
+    module->send_nack = true;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -628,24 +649,25 @@ enum status_code i2c_master_write_packet_job(
  * \retval STATUS_BUSY  If module is currently busy with another
  */
 enum status_code i2c_master_write_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Do not send stop condition when done */
-	module->send_stop = false;
-	module->send_nack = true;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Do not send stop condition when done */
+    module->send_stop = false;
+    module->send_nack = true;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -655,108 +677,122 @@ enum status_code i2c_master_write_packet_job_no_stop(
  * \param[in] instance  SERCOM instance that triggered the interrupt
  */
 void _i2c_master_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Get software module for callback handling */
-	struct i2c_master_module *module =
-			(struct i2c_master_module*)_sercom_instances[instance];
-
-	Assert(module);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
-
-	/* Combine callback registered and enabled masks */
-	uint8_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
-
-	/* Check if the module should respond to address ack */
-	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
-		/* Call function for address response */
-		_i2c_master_async_address_response(module);
-
-	/* Check if buffer write is done */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg =
-				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
-
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		if (module->send_stop) {
-			/* Send stop condition */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		} else {
-			/* Clear write interrupt flag */
-			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
-		}
-		
-		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
-			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
-		}
-
-	/* Continue buffer write/read */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
-		/* Check that bus ownership is not lost */
-		if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
-				(!(sclsm_flag && (module->buffer_remaining == 1))))	{
-			module->status = STATUS_ERR_PACKET_COLLISION;
-		} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-			_i2c_master_write(module);
-		} else {
-			_i2c_master_read(module);
-		}
-	}
-
-	/* Check if read buffer transfer is complete */
-	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_READ)) {
-		
-		/* Clear read interrupt flag */
-		if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
-			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
-		}
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg =
-				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		/* Call appropriate callback if enabled and registered */
-		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
-				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
-			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
-		} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
-				&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
-			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
-		}
-	}
-
-	/* Check for error */
-	if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
-				SERCOM_I2CM_INTENCLR_SB;
-
-		module->buffer_length = 0;
-		module->buffer_remaining = 0;
-
-		/* Send nack and stop command unless arbitration is lost */
-		if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
-				module->send_stop) {
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
-					SERCOM_I2CM_CTRLB_CMD(3);
-		}
-
-		/* Call error callback if enabled and registered */
-		if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
-			module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
-		}
-	}
+    /* Get software module for callback handling */
+    struct i2c_master_module *module =
+            (struct i2c_master_module*)_sercom_instances[instance];
+
+    Assert(module);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
+
+    /* Combine callback registered and enabled masks */
+    uint8_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
+
+    /* Check if the module should respond to address ack */
+    if ((module->buffer_length <= 0) && (module->buffer_remaining > 0))
+    {
+        /* Call function for address response */
+        _i2c_master_async_address_response(module);
+
+    /* Check if buffer write is done */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_WRITE))
+            {
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg =
+                SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        if (module->send_stop)
+        {
+            /* Send stop condition */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        } else {
+            /* Clear write interrupt flag */
+            i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+        }
+
+        if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+        {
+            module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+        }
+
+    /* Continue buffer write/read */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0))
+    {
+        /* Check that bus ownership is not lost */
+        if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) &&
+                (!(sclsm_flag && (module->buffer_remaining == 1))))
+                {
+            module->status = STATUS_ERR_PACKET_COLLISION;
+        } else if (module->transfer_direction == I2C_TRANSFER_WRITE)
+        {
+            _i2c_master_write(module);
+        } else {
+            _i2c_master_read(module);
+        }
+    }
+
+    /* Check if read buffer transfer is complete */
+    if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_READ))
+            {
+
+        /* Clear read interrupt flag */
+        if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)
+        {
+            i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+        }
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg =
+                SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        /* Call appropriate callback if enabled and registered */
+        if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+                && (module->transfer_direction == I2C_TRANSFER_READ))
+                {
+            module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+        } else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+                && (module->transfer_direction == I2C_TRANSFER_WRITE))
+                {
+            module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+        }
+    }
+
+    /* Check for error */
+    if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK))
+    {
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
+                SERCOM_I2CM_INTENCLR_SB;
+
+        module->buffer_length = 0;
+        module->buffer_remaining = 0;
+
+        /* Send nack and stop command unless arbitration is lost */
+        if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
+                module->send_stop)
+                {
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
+                    SERCOM_I2CM_CTRLB_CMD(3);
+        }
+
+        /* Call error callback if enabled and registered */
+        if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR))
+        {
+            module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c
index 113087794781..caa584e8ca86 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c
@@ -61,72 +61,76 @@
  *                                         previously set
  */
 static enum status_code _i2c_slave_set_config(
-		struct i2c_slave_module *const module,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        const struct i2c_slave_config *const config)
 {
-	uint32_t tmp_ctrla;
-
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	Sercom *const sercom_hw = module->hw;
-
-	module->buffer_timeout = config->buffer_timeout;
-	module->ten_bit_address = config->ten_bit_address;
-
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	uint32_t pad0 = config->pinmux_pad0;
-	uint32_t pad1 = config->pinmux_pad1;
-
-	/* SERCOM PAD0 - SDA */
-	if (pad0 == PINMUX_DEFAULT) {
-		pad0 = _sercom_get_default_pad(sercom_hw, 0);
-	}
-	pin_conf.mux_position = pad0 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
-
-	/* SERCOM PAD1 - SCL */
-	if (pad1 == PINMUX_DEFAULT) {
-		pad1 = _sercom_get_default_pad(sercom_hw, 1);
-	}
-	pin_conf.mux_position = pad1 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
-
-	/* Prepare config to write to register CTRLA */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
-	} else {
-		tmp_ctrla = 0;
-	}
-
-	/* Check and set SCL clock stretch mode. */
-	if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_SLAVE_SPEED_HIGH_SPEED)) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
-	}
-	
-	tmp_ctrla |= ((uint32_t)config->sda_hold_time |
-			config->transfer_speed |
-			(config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) |
-			(config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos));
-
-	i2c_hw->CTRLA.reg |= tmp_ctrla;
-
-	/* Set CTRLB configuration */
-	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
-
-	i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
-			config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
-			config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos |
-			config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
-
-	return STATUS_OK;
+    uint32_t tmp_ctrla;
+
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    Sercom *const sercom_hw = module->hw;
+
+    module->buffer_timeout = config->buffer_timeout;
+    module->ten_bit_address = config->ten_bit_address;
+
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    uint32_t pad0 = config->pinmux_pad0;
+    uint32_t pad1 = config->pinmux_pad1;
+
+    /* SERCOM PAD0 - SDA */
+    if (pad0 == PINMUX_DEFAULT)
+    {
+        pad0 = _sercom_get_default_pad(sercom_hw, 0);
+    }
+    pin_conf.mux_position = pad0 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+    /* SERCOM PAD1 - SCL */
+    if (pad1 == PINMUX_DEFAULT)
+    {
+        pad1 = _sercom_get_default_pad(sercom_hw, 1);
+    }
+    pin_conf.mux_position = pad1 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+    /* Prepare config to write to register CTRLA */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
+    } else {
+        tmp_ctrla = 0;
+    }
+
+    /* Check and set SCL clock stretch mode. */
+    if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_SLAVE_SPEED_HIGH_SPEED))
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
+    }
+
+    tmp_ctrla |= ((uint32_t)config->sda_hold_time |
+            config->transfer_speed |
+            (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) |
+            (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos));
+
+    i2c_hw->CTRLA.reg |= tmp_ctrla;
+
+    /* Set CTRLB configuration */
+    i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
+
+    i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
+            config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
+            config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos |
+            config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
+
+    return STATUS_OK;
 }
 
 /**
@@ -148,91 +152,95 @@ static enum status_code _i2c_slave_set_config(
  *                                         previously set
  */
 enum status_code i2c_slave_init(
-		struct i2c_slave_module *const module,
-		Sercom *const hw,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        Sercom *const hw,
+        const struct i2c_slave_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
-
-	/* Initialize software module */
-	module->hw = hw;
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Check if module is enabled */
-	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress */
-	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
-
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index, gclk_index; 
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
+
+    /* Initialize software module */
+    module->hw = hw;
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Check if module is enabled */
+    if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress */
+    if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
+
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index, gclk_index;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
+    if (sercom_index == 5)
+    {
+        pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+        gclk_index   = SERCOM5_GCLK_ID_CORE;
+    } else {
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
 #else
-	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #endif
 #else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #endif
-	
-	/* Turn on module in PM */
+
+    /* Turn on module in PM */
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
-	} else {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
-	}
+    if (sercom_index == 5)
+    {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+    } else {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    }
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
 #endif
 
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Get sercom instance index */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    /* Get sercom instance index */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
 
-	/* Save software module in interrupt handler */
-	_sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
+    /* Save software module in interrupt handler */
+    _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
 
-	/* Save software module */
-	_sercom_instances[instance_index] = module;
+    /* Save software module */
+    _sercom_instances[instance_index] = module;
 
-	/* Initialize values in module */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->nack_on_address = config->enable_nack_on_address;
+    /* Initialize values in module */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->nack_on_address = config->enable_nack_on_address;
 #endif
 
-	/* Set SERCOM module to operate in I2C slave mode */
-	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4);
+    /* Set SERCOM module to operate in I2C slave mode */
+    i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4);
 
-	/* Set config and return status */
-	return _i2c_slave_set_config(module, config);
+    /* Set config and return status */
+    return _i2c_slave_set_config(module, config);
 }
 
 /**
@@ -243,38 +251,38 @@ enum status_code i2c_slave_init(
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_reset(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Reset module instance */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->buffer_remaining = 0;
-	module->buffer = NULL;
+    /* Reset module instance */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->buffer_remaining = 0;
+    module->buffer = NULL;
 #endif
 
-	/* Disable module */
-	i2c_slave_disable(module);
+    /* Disable module */
+    i2c_slave_disable(module);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Clear all pending interrupts */
-	system_interrupt_enter_critical_section();
-	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
-	system_interrupt_leave_critical_section();
+    /* Clear all pending interrupts */
+    system_interrupt_enter_critical_section();
+    system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_leave_critical_section();
 #endif
 
-	/* Wait for sync */
-	_i2c_slave_wait_for_sync(module);
+    /* Wait for sync */
+    _i2c_slave_wait_for_sync(module);
 
-	/* Reset module */
-	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
+    /* Reset module */
+    i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
 }
 
 /**
@@ -288,26 +296,28 @@ void i2c_slave_reset(
  *                             period
  */
 static enum status_code _i2c_slave_wait_for_bus(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Wait for reply */
-	uint16_t timeout_counter = 0;
-	while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
-			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
-			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) {
-
-		/* Check timeout condition */
-		if (++timeout_counter >= module->buffer_timeout) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Wait for reply */
+    uint16_t timeout_counter = 0;
+    while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
+            (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
+            (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)))
+            {
+
+        /* Check timeout condition */
+        if (++timeout_counter >= module->buffer_timeout)
+        {
+            return STATUS_ERR_TIMEOUT;
+        }
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -333,117 +343,130 @@ static enum status_code _i2c_slave_wait_for_bus(
  *                                  period
  */
 enum status_code i2c_slave_write_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	uint16_t length = packet->data_length;
+    uint16_t length = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Check if the module is busy with a job or AMATCH is enabled */
-	if (module->buffer_remaining > 0 ||
-			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy with a job or AMATCH is enabled */
+    if (module->buffer_remaining > 0 ||
+            (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+            {
+        return STATUS_BUSY;
+    }
 #endif
 
-	enum status_code status;
-	/* Wait for master to send address packet */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-	}
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return STATUS_ERR_DENIED;
-	}
-
-	if (module->ten_bit_address) {
-		/* ACK the first address */
-		i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
-
-		/* Wait for address interrupt */
-		status = _i2c_slave_wait_for_bus(module);
-
-		if (status != STATUS_OK) {
-			/* Timeout, return */
-			return STATUS_ERR_TIMEOUT;
-		}
-
-		if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-			/* Not address interrupt, something is wrong */
-			return STATUS_ERR_DENIED;
-		}
-	}
-
-	/* Check if there was an error in last transfer */
-	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Check direction */
-	if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Write request from master, send NACK and return */
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Read request from master, ACK address */
-	i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
-	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
-
-	uint16_t i = 0;
-
-	/* Wait for data interrupt */
-	status = _i2c_slave_wait_for_bus(module);
-	if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-	}
-
-	while (length--) {
-		/* Write data */
-		_i2c_slave_wait_for_sync(module);
-		i2c_hw->DATA.reg = packet->data[i++];
-
-		/* Wait for response from master */
-		status = _i2c_slave_wait_for_bus(module);
-
-		if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-		}
-
-		if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
-				length !=0) {
-			/* NACK from master, abort */
-			/* Release line */
-			i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
-
-			return STATUS_ERR_OVERFLOW;
-		}
-		/* ACK from master, continue writing */
-	}
-
-	/* Release line */
-	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
-
-	return STATUS_OK;
+    enum status_code status;
+    /* Wait for master to send address packet */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (status != STATUS_OK)
+    {
+            /* Timeout, return */
+            return status;
+    }
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return STATUS_ERR_DENIED;
+    }
+
+    if (module->ten_bit_address)
+    {
+        /* ACK the first address */
+        i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+        /* Wait for address interrupt */
+        status = _i2c_slave_wait_for_bus(module);
+
+        if (status != STATUS_OK)
+        {
+            /* Timeout, return */
+            return STATUS_ERR_TIMEOUT;
+        }
+
+        if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+        {
+            /* Not address interrupt, something is wrong */
+            return STATUS_ERR_DENIED;
+        }
+    }
+
+    /* Check if there was an error in last transfer */
+    if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+            SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+            {
+        return STATUS_ERR_IO;
+    }
+
+    /* Check direction */
+    if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Write request from master, send NACK and return */
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Read request from master, ACK address */
+    i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+    i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+    uint16_t i = 0;
+
+    /* Wait for data interrupt */
+    status = _i2c_slave_wait_for_bus(module);
+    if (status != STATUS_OK)
+    {
+            /* Timeout, return */
+            return status;
+    }
+
+    while (length--)
+    {
+        /* Write data */
+        _i2c_slave_wait_for_sync(module);
+        i2c_hw->DATA.reg = packet->data[i++];
+
+        /* Wait for response from master */
+        status = _i2c_slave_wait_for_bus(module);
+
+        if (status != STATUS_OK)
+        {
+            /* Timeout, return */
+            return status;
+        }
+
+        if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
+                length !=0)
+                {
+            /* NACK from master, abort */
+            /* Release line */
+            i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+            return STATUS_ERR_OVERFLOW;
+        }
+        /* ACK from master, continue writing */
+    }
+
+    /* Release line */
+    i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+    return STATUS_OK;
 }
 
 /**
@@ -469,98 +492,109 @@ enum status_code i2c_slave_write_packet_wait(
  * \retval STATUS_ERR_ERR_OVERFLOW  Last byte received overflows buffer
  */
 enum status_code i2c_slave_read_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	uint16_t length = packet->data_length;
+    uint16_t length = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Check if the module is busy with a job or AMATCH is enabled */
-	if (module->buffer_remaining > 0 ||
-			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy with a job or AMATCH is enabled */
+    if (module->buffer_remaining > 0 ||
+            (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+            {
+        return STATUS_BUSY;
+    }
 #endif
 
-	enum status_code status;
-
-	/* Wait for master to send address packet */
-	status = _i2c_slave_wait_for_bus(module);
-	if (status != STATUS_OK) {
-		/* Timeout, return */
-		return status;
-	}
-
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if there was an error in the last transfer */
-	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-		return STATUS_ERR_IO;
-	}
-	/* Check direction */
-	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Read request from master, send NACK and return */
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Write request from master, ACK address */
-	i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
-	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
-
-	uint16_t i = 0;
-	while (length--) {
-
-		/* Wait for next byte or stop condition */
-		status = _i2c_slave_wait_for_bus(module);
-		if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-		}
-
-		if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
-				i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
-			/* Master sent stop condition, or repeated start, read done */
-			/* Clear stop flag */
-			i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-			return STATUS_ABORTED;
-		}
-
-		/* Read data */
-		_i2c_slave_wait_for_sync(module);
-		packet->data[i++] = i2c_hw->DATA.reg;
-
-	}
-
-	/* Packet read done, wait for packet to NACK, Stop or repeated start */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
-		/* Buffer is full, send NACK */
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-	}
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
-		/* Clear stop flag */
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-	}
-	return STATUS_OK;
+    enum status_code status;
+
+    /* Wait for master to send address packet */
+    status = _i2c_slave_wait_for_bus(module);
+    if (status != STATUS_OK)
+    {
+        /* Timeout, return */
+        return status;
+    }
+
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if there was an error in the last transfer */
+    if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+            SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+            {
+        return STATUS_ERR_IO;
+    }
+    /* Check direction */
+    if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Read request from master, send NACK and return */
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Write request from master, ACK address */
+    i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+    i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
+
+    uint16_t i = 0;
+    while (length--)
+    {
+
+        /* Wait for next byte or stop condition */
+        status = _i2c_slave_wait_for_bus(module);
+        if (status != STATUS_OK)
+        {
+            /* Timeout, return */
+            return status;
+        }
+
+        if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
+                i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)
+                {
+            /* Master sent stop condition, or repeated start, read done */
+            /* Clear stop flag */
+            i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+            return STATUS_ABORTED;
+        }
+
+        /* Read data */
+        _i2c_slave_wait_for_sync(module);
+        packet->data[i++] = i2c_hw->DATA.reg;
+
+    }
+
+    /* Packet read done, wait for packet to NACK, Stop or repeated start */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        /* Buffer is full, send NACK */
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+    }
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        /* Clear stop flag */
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -569,7 +603,7 @@ enum status_code i2c_slave_read_packet_wait(
  * \note This function is only available for 7-bit slave addressing.
  *
  * Waits for the master to issue a start condition on the bus.
- * 
+ *
  * \note This function does not check for errors in the last transfer,
  * this will be discovered when reading or writing.
  *
@@ -582,37 +616,40 @@ enum status_code i2c_slave_read_packet_wait(
  * \retval I2C_SLAVE_DIRECTION_WRITE  Read request from master
  */
 enum i2c_slave_direction i2c_slave_get_direction_wait(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	enum status_code status;
-
-	/* Wait for address interrupt */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (status != STATUS_OK) {
-		/* Timeout, return */
-		return I2C_SLAVE_DIRECTION_NONE;
-	}
-
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return I2C_SLAVE_DIRECTION_NONE;
-	}
-
-	/* Check direction */
-	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Read request from master */
-		return I2C_SLAVE_DIRECTION_WRITE;
-	} else {
-		/* Write request from master */
-		return I2C_SLAVE_DIRECTION_READ;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    enum status_code status;
+
+    /* Wait for address interrupt */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (status != STATUS_OK)
+    {
+        /* Timeout, return */
+        return I2C_SLAVE_DIRECTION_NONE;
+    }
+
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return I2C_SLAVE_DIRECTION_NONE;
+    }
+
+    /* Check direction */
+    if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Read request from master */
+        return I2C_SLAVE_DIRECTION_WRITE;
+    } else {
+        /* Write request from master */
+        return I2C_SLAVE_DIRECTION_READ;
+    }
 }
 
 /**
@@ -645,56 +682,65 @@ enum i2c_slave_direction i2c_slave_get_direction_wait(
  *                                          occurred on the bus
  */
 uint32_t i2c_slave_get_status(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	uint8_t intflags = i2c_hw->INTFLAG.reg;
-	uint8_t status = i2c_hw->STATUS.reg;
-	uint32_t status_flags = 0;
-
-	/* Check Address Match flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) {
-		status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
-	}
-	/* Check Data Ready flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_DRDY) {
-		status_flags |= I2C_SLAVE_STATUS_DATA_READY;
-	}
-	/* Check Stop flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_PREC) {
-		status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
-	}
-	/* Check Clock Hold */
-	if (status & SERCOM_I2CS_STATUS_CLKHOLD) {
-		status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
-	}
-	/* Check SCL Low Timeout */
-	if (status & SERCOM_I2CS_STATUS_LOWTOUT) {
-		status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
-	}
-	/* Check Repeated Start */
-	if (status & SERCOM_I2CS_STATUS_SR) {
-		status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
-	}
-	/* Check Received Not Acknowledge */
-	if (status & SERCOM_I2CS_STATUS_RXNACK) {
-		status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
-	}
-	/* Check Transmit Collision */
-	if (status & SERCOM_I2CS_STATUS_COLL) {
-		status_flags |= I2C_SLAVE_STATUS_COLLISION;
-	}
-	/* Check Bus Error */
-	if (status & SERCOM_I2CS_STATUS_BUSERR) {
-		status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
-	}
-
-	return status_flags;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    uint8_t intflags = i2c_hw->INTFLAG.reg;
+    uint8_t status = i2c_hw->STATUS.reg;
+    uint32_t status_flags = 0;
+
+    /* Check Address Match flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_AMATCH)
+    {
+        status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
+    }
+    /* Check Data Ready flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        status_flags |= I2C_SLAVE_STATUS_DATA_READY;
+    }
+    /* Check Stop flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
+    }
+    /* Check Clock Hold */
+    if (status & SERCOM_I2CS_STATUS_CLKHOLD)
+    {
+        status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
+    }
+    /* Check SCL Low Timeout */
+    if (status & SERCOM_I2CS_STATUS_LOWTOUT)
+    {
+        status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
+    }
+    /* Check Repeated Start */
+    if (status & SERCOM_I2CS_STATUS_SR)
+    {
+        status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
+    }
+    /* Check Received Not Acknowledge */
+    if (status & SERCOM_I2CS_STATUS_RXNACK)
+    {
+        status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
+    }
+    /* Check Transmit Collision */
+    if (status & SERCOM_I2CS_STATUS_COLL)
+    {
+        status_flags |= I2C_SLAVE_STATUS_COLLISION;
+    }
+    /* Check Bus Error */
+    if (status & SERCOM_I2CS_STATUS_BUSERR)
+    {
+        status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
+    }
+
+    return status_flags;
 }
 
 /**
@@ -709,37 +755,43 @@ uint32_t i2c_slave_get_status(
  *
  */
 void i2c_slave_clear_status(
-		struct i2c_slave_module *const module,
-		uint32_t status_flags)
+        struct i2c_slave_module *const module,
+        uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Clear Address Match flag */
-	if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-	}
-	/* Clear Data Ready flag */
-	if (status_flags & I2C_SLAVE_STATUS_DATA_READY) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
-	}
-	/* Clear Stop flag */
-	if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-	}
-	/* Clear SCL Low Timeout */
-	if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
-	}
-	/* Clear Transmit Collision */
-	if (status_flags & I2C_SLAVE_STATUS_COLLISION) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
-	}
-	/* Clear Bus Error */
-	if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Clear Address Match flag */
+    if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+    }
+    /* Clear Data Ready flag */
+    if (status_flags & I2C_SLAVE_STATUS_DATA_READY)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+    }
+    /* Clear Stop flag */
+    if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+    }
+    /* Clear SCL Low Timeout */
+    if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+    }
+    /* Clear Transmit Collision */
+    if (status_flags & I2C_SLAVE_STATUS_COLLISION)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+    }
+    /* Clear Bus Error */
+    if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c
index 0a6f234f8b83..e7fe50e9dda3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c
@@ -55,12 +55,12 @@
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_enable_nack_on_address(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
+    /* Sanity check arguments. */
+    Assert(module);
 
-	module->nack_on_address = true;
+    module->nack_on_address = true;
 }
 
 /**
@@ -72,12 +72,12 @@ void i2c_slave_enable_nack_on_address(
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_disable_nack_on_address(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
+    /* Sanity check arguments. */
+    Assert(module);
 
-	module->nack_on_address = false;
+    module->nack_on_address = false;
 }
 
 /**
@@ -87,15 +87,15 @@ void i2c_slave_disable_nack_on_address(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_read(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	/* Read byte from master and put in buffer. */
-	*(module->buffer++) = i2c_hw->DATA.reg;
+    /* Read byte from master and put in buffer. */
+    *(module->buffer++) = i2c_hw->DATA.reg;
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -105,15 +105,15 @@ static void _i2c_slave_read(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_write(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	/* Write byte from buffer to master */
-	i2c_hw->DATA.reg = *(module->buffer++);
+    /* Write byte from buffer to master */
+    i2c_hw->DATA.reg = *(module->buffer++);
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -129,20 +129,20 @@ static void _i2c_slave_write(
  * \param[in]     callback_type  Callback type to register
  */
 void i2c_slave_register_callback(
-		struct i2c_slave_module *const module,
-		i2c_slave_callback_t callback,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        i2c_slave_callback_t callback,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = callback;
+    /* Register callback. */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -155,18 +155,18 @@ void i2c_slave_register_callback(
  * \param[in]      callback_type  Callback type to unregister
  */
 void i2c_slave_unregister_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = NULL;
+    /* Register callback. */
+    module->callbacks[callback_type] = NULL;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -186,32 +186,33 @@ void i2c_slave_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_slave_read_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy doing async operation. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status           = STATUS_BUSY;
-
-	/* Enable interrupts */
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
-			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
-
-	/* Read will begin when master initiates the transfer */
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy doing async operation. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+            SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+    /* Read will begin when master initiates the transfer */
+    return STATUS_OK;
 }
 
 /**
@@ -231,31 +232,32 @@ enum status_code i2c_slave_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 enum status_code i2c_slave_write_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy doing async operation. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status           = STATUS_BUSY;
-
-	/* Enable interrupts */
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
-			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy doing async operation. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+            SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+    return STATUS_OK;
 }
 
 /**
@@ -264,171 +266,195 @@ enum status_code i2c_slave_write_packet_job(
  * \param[in] instance Sercom instance that triggered the interrupt
  */
 void _i2c_slave_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Get software module for callback handling. */
-	struct i2c_slave_module *module =
-			(struct i2c_slave_module*)_sercom_instances[instance];
-
-	Assert(module);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Combine callback registered and enabled masks. */
-	uint8_t callback_mask = module->enabled_callback;
-	callback_mask &= module->registered_callback;
-
-
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
-	/* Address match */
-		/* Check if last transfer is done - repeated start */
-		if (module->buffer_length != module->buffer_remaining &&
-				module->transfer_direction == I2C_TRANSFER_WRITE) {
-
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-			}
-		} else if (module->buffer_length != module->buffer_remaining &&
-				module->transfer_direction == I2C_TRANSFER_READ) {
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
-			}
-		}
-
-		if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-				SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-			/* An error occurred in last packet transfer */
-			module->status = STATUS_ERR_IO;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
-			}
-		}
-		if (module->nack_on_address) {
-			/* NACK address, workaround 13574 */
-			_i2c_slave_set_ctrlb_ackact(module, false);
-		} else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) {
-			/* Set transfer direction in module instance */
-			module->transfer_direction = I2C_TRANSFER_READ;
-
-			/* Read request from master */
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
-			}
-
-			if (module->buffer_length == 0) {
-				/* Data buffer not set up, NACK address, workaround 13574*/
-				_i2c_slave_set_ctrlb_ackact(module, false);
-			} else {
-				/* ACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, true);
-			}
-		} else {
-			/* Set transfer direction in dev inst */
-			module->transfer_direction = I2C_TRANSFER_WRITE;
-
-			/* Write request from master */
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
-			}
-
-			if (module->buffer_length == 0) {
-				/* Data buffer not set up, NACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-			} else {
-				/* ACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, true);
-			}
-		}
-
-		/* ACK or NACK address, Workaround 13574 */
-		_i2c_slave_set_ctrlb_cmd3(module);
-
-		/* ACK next incoming packet, workaround 13574 */
-		_i2c_slave_set_ctrlb_ackact(module, true);
-
-	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
-		/* Stop condition on bus - current transfer done */
-
-		/* Clear Stop interrupt */
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-
-		/* Disable interrupts */
-		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
-
-		if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
-				|| (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) {
-			/* Disable address match if read/write request is not enabled */
-			i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-		}
-
-		if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) {
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			/* Call appropriate callback if enabled and registered */
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
-					&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
-				/* Read from master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-			} else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
-					&& (module->transfer_direction == I2C_TRANSFER_READ)) {
-				/* Write to master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
-			}
-					}
-	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
-		/* Check if buffer is full, or NACK from master */
-		if (module->buffer_remaining <= 0 ||
-				(module->transfer_direction == I2C_TRANSFER_READ &&
-				(module->buffer_length > module->buffer_remaining) &&
-				(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) {
-
-			module->buffer_remaining = 0;
-			module->buffer_length = 0;
-
-			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-				/* Buffer is full, send NACK, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-
-				/* Set status, new character in DATA register will overflow
-				 * buffer */
-				module->status = STATUS_ERR_OVERFLOW;
-
-				if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) {
-					/* Read complete */
-					module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
-				}
-			} else {
-				/* Release SCL and wait for new start condition */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-
-				/* Transfer successful */
-				module->status = STATUS_OK;
-
-				/* Disable interrupts */
-				i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
-			}
-
-		/* Continue buffer write/read */
-		} else if (module->buffer_length > 0 && module->buffer_remaining > 0) {
-			/* Call function based on transfer direction */
-			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-				_i2c_slave_read(module);
-			} else {
-				_i2c_slave_write(module);
-			}
-		}
-	}
+    /* Get software module for callback handling. */
+    struct i2c_slave_module *module =
+            (struct i2c_slave_module*)_sercom_instances[instance];
+
+    Assert(module);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Combine callback registered and enabled masks. */
+    uint8_t callback_mask = module->enabled_callback;
+    callback_mask &= module->registered_callback;
+
+
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)
+    {
+    /* Address match */
+        /* Check if last transfer is done - repeated start */
+        if (module->buffer_length != module->buffer_remaining &&
+                module->transfer_direction == I2C_TRANSFER_WRITE)
+                {
+
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+            }
+        } else if (module->buffer_length != module->buffer_remaining &&
+                module->transfer_direction == I2C_TRANSFER_READ)
+                {
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+            }
+        }
+
+        if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+                SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+                {
+            /* An error occurred in last packet transfer */
+            module->status = STATUS_ERR_IO;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
+            }
+        }
+        if (module->nack_on_address)
+        {
+            /* NACK address, workaround 13574 */
+            _i2c_slave_set_ctrlb_ackact(module, false);
+        } else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)
+        {
+            /* Set transfer direction in module instance */
+            module->transfer_direction = I2C_TRANSFER_READ;
+
+            /* Read request from master */
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+            }
+
+            if (module->buffer_length == 0)
+            {
+                /* Data buffer not set up, NACK address, workaround 13574*/
+                _i2c_slave_set_ctrlb_ackact(module, false);
+            } else {
+                /* ACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, true);
+            }
+        } else {
+            /* Set transfer direction in dev inst */
+            module->transfer_direction = I2C_TRANSFER_WRITE;
+
+            /* Write request from master */
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+            }
+
+            if (module->buffer_length == 0)
+            {
+                /* Data buffer not set up, NACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+            } else {
+                /* ACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, true);
+            }
+        }
+
+        /* ACK or NACK address, Workaround 13574 */
+        _i2c_slave_set_ctrlb_cmd3(module);
+
+        /* ACK next incoming packet, workaround 13574 */
+        _i2c_slave_set_ctrlb_ackact(module, true);
+
+    } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        /* Stop condition on bus - current transfer done */
+
+        /* Clear Stop interrupt */
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+
+        /* Disable interrupts */
+        i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
+
+        if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+                || (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST))))
+                {
+            /* Disable address match if read/write request is not enabled */
+            i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+        }
+
+        if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO))
+        {
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            /* Call appropriate callback if enabled and registered */
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+                    && (module->transfer_direction == I2C_TRANSFER_WRITE))
+                    {
+                /* Read from master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+            } else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
+                    && (module->transfer_direction == I2C_TRANSFER_READ))
+                    {
+                /* Write to master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+            }
+                    }
+    } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        /* Check if buffer is full, or NACK from master */
+        if (module->buffer_remaining <= 0 ||
+                (module->transfer_direction == I2C_TRANSFER_READ &&
+                (module->buffer_length > module->buffer_remaining) &&
+                (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK)))
+                {
+
+            module->buffer_remaining = 0;
+            module->buffer_length = 0;
+
+            if (module->transfer_direction == I2C_TRANSFER_WRITE)
+            {
+                /* Buffer is full, send NACK, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+                i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+                /* Set status, new character in DATA register will overflow
+                 * buffer */
+                module->status = STATUS_ERR_OVERFLOW;
+
+                if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR))
+                {
+                    /* Read complete */
+                    module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
+                }
+            } else {
+                /* Release SCL and wait for new start condition */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+                i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+                /* Transfer successful */
+                module->status = STATUS_OK;
+
+                /* Disable interrupts */
+                i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
+            }
+
+        /* Continue buffer write/read */
+        } else if (module->buffer_length > 0 && module->buffer_remaining > 0)
+        {
+            /* Call function based on transfer direction */
+            if (module->transfer_direction == I2C_TRANSFER_WRITE)
+            {
+                _i2c_slave_read(module);
+            } else {
+                _i2c_slave_write(module);
+            }
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c
index ce4f58c2303c..d9f607d52f99 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c
@@ -66,96 +66,103 @@
  *                                          with set GCLK frequency
  */
 static enum status_code _i2c_master_set_config(
-		struct i2c_master_module *const module,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-
-	/* Temporary variables. */
-	uint32_t tmp_ctrla;
-	int32_t tmp_baud;
-	enum status_code tmp_status_code = STATUS_OK;
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	Sercom *const sercom_hw = module->hw;
-
-	uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
-
-	/* Pin configuration */
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	uint32_t pad0 = config->pinmux_pad0;
-	uint32_t pad1 = config->pinmux_pad1;
-
-	/* SERCOM PAD0 - SDA */
-	if (pad0 == PINMUX_DEFAULT) {
-		pad0 = _sercom_get_default_pad(sercom_hw, 0);
-	}
-	pin_conf.mux_position = pad0 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
-
-	/* SERCOM PAD1 - SCL */
-	if (pad1 == PINMUX_DEFAULT) {
-		pad1 = _sercom_get_default_pad(sercom_hw, 1);
-	}
-	pin_conf.mux_position = pad1 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
-
-	/* Save timeout on unknown bus state in software module. */
-	module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
-
-	/* Save timeout on buffer write. */
-	module->buffer_timeout = config->buffer_timeout;
-
-	/* Set whether module should run in standby. */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
-	} else {
-		tmp_ctrla = 0;
-	}
-
-	/* Check and set start data hold timeout. */
-	if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
-		tmp_ctrla |= config->start_hold_time;
-	}
-
-	/* Check and set SCL low timeout. */
-	if (config->scl_low_timeout) {
-		tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUT;
-	}
-
-	/* Check and set inactive bus timeout. */
-	if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
-		tmp_ctrla |= config->inactive_timeout;
-	}
-
-	/* Write config to register CTRLA. */
-	i2c_module->CTRLA.reg |= tmp_ctrla;
-
-	/* Set configurations in CTRLB. */
-	i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
-
-	/* Find and set baudrate. */
-	tmp_baud = (int32_t)(div_ceil(
-				system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index),
-				(2000*(config->baud_rate))) - 5);
-
-	/* Check that baud rate is supported at current speed. */
-	if (tmp_baud > 255 || tmp_baud < 0) {
-		/* Baud rate not supported. */
-		tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	} else {
-		/* Baud rate acceptable. */
-		i2c_module->BAUD.reg = (uint8_t)tmp_baud;
-	}
-
-	return tmp_status_code;
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    /* Temporary variables. */
+    uint32_t tmp_ctrla;
+    int32_t tmp_baud;
+    enum status_code tmp_status_code = STATUS_OK;
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    Sercom *const sercom_hw = module->hw;
+
+    uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
+
+    /* Pin configuration */
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    uint32_t pad0 = config->pinmux_pad0;
+    uint32_t pad1 = config->pinmux_pad1;
+
+    /* SERCOM PAD0 - SDA */
+    if (pad0 == PINMUX_DEFAULT)
+    {
+        pad0 = _sercom_get_default_pad(sercom_hw, 0);
+    }
+    pin_conf.mux_position = pad0 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+    /* SERCOM PAD1 - SCL */
+    if (pad1 == PINMUX_DEFAULT)
+    {
+        pad1 = _sercom_get_default_pad(sercom_hw, 1);
+    }
+    pin_conf.mux_position = pad1 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+    /* Save timeout on unknown bus state in software module. */
+    module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
+
+    /* Save timeout on buffer write. */
+    module->buffer_timeout = config->buffer_timeout;
+
+    /* Set whether module should run in standby. */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
+    } else {
+        tmp_ctrla = 0;
+    }
+
+    /* Check and set start data hold timeout. */
+    if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED)
+    {
+        tmp_ctrla |= config->start_hold_time;
+    }
+
+    /* Check and set SCL low timeout. */
+    if (config->scl_low_timeout)
+    {
+        tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUT;
+    }
+
+    /* Check and set inactive bus timeout. */
+    if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED)
+    {
+        tmp_ctrla |= config->inactive_timeout;
+    }
+
+    /* Write config to register CTRLA. */
+    i2c_module->CTRLA.reg |= tmp_ctrla;
+
+    /* Set configurations in CTRLB. */
+    i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
+
+    /* Find and set baudrate. */
+    tmp_baud = (int32_t)(div_ceil(
+                system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index),
+                (2000*(config->baud_rate))) - 5);
+
+    /* Check that baud rate is supported at current speed. */
+    if (tmp_baud > 255 || tmp_baud < 0)
+    {
+        /* Baud rate not supported. */
+        tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
+    } else {
+        /* Baud rate acceptable. */
+        i2c_module->BAUD.reg = (uint8_t)tmp_baud;
+    }
+
+    return tmp_status_code;
 }
 #endif /* __DOXYGEN__ */
 
@@ -181,66 +188,68 @@ static enum status_code _i2c_master_set_config(
  *
  */
 enum status_code i2c_master_init(
-		struct i2c_master_module *const module,
-		Sercom *const hw,
-		const struct i2c_master_config *const config)
+        struct i2c_master_module *const module,
+        Sercom *const hw,
+        const struct i2c_master_config *const config)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
-
-	/* Initialize software module */
-	module->hw = hw;
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-
-	/* Turn on module in PM */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
-
-	/* Check if module is enabled. */
-	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress. */
-	if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
+
+    /* Initialize software module */
+    module->hw = hw;
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+    /* Turn on module in PM */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
+
+    /* Check if module is enabled. */
+    if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress. */
+    if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Get sercom instance index and register callback. */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
-	_sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
-	_sercom_instances[instance_index] = module;
-
-	/* Initialize values in module. */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->buffer_remaining = 0;
-
-	module->status = STATUS_OK;
-	module->buffer = NULL;
+    /* Get sercom instance index and register callback. */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    _sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
+    _sercom_instances[instance_index] = module;
+
+    /* Initialize values in module. */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->buffer_remaining = 0;
+
+    module->status = STATUS_OK;
+    module->buffer = NULL;
 #endif
 
-	/* Set sercom module to operate in I2C master mode. */
-	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER;
+    /* Set sercom module to operate in I2C master mode. */
+    i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER;
 
-	/* Set config and return status. */
-	return _i2c_master_set_config(module, config);
+    /* Set config and return status. */
+    return _i2c_master_set_config(module, config);
 }
 
 /**
@@ -252,30 +261,30 @@ enum status_code i2c_master_init(
  */
 void i2c_master_reset(struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Wait for sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Disable module */
-	i2c_master_disable(module);
+    /* Disable module */
+    i2c_master_disable(module);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Clear all pending interrupts */
-	system_interrupt_enter_critical_section();
-	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
-	system_interrupt_leave_critical_section();
+    /* Clear all pending interrupts */
+    system_interrupt_enter_critical_section();
+    system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_leave_critical_section();
 #endif
 
-	/* Wait for sync */
-	_i2c_master_wait_for_sync(module);
+    /* Wait for sync */
+    _i2c_master_wait_for_sync(module);
 
-	/* Reset module */
-	i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
+    /* Reset module */
+    i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
 }
 
 #if !defined(__DOXYGEN__)
@@ -293,36 +302,39 @@ void i2c_master_reset(struct i2c_master_module *const module)
  *                                      acknowledged the address
  */
 static enum status_code _i2c_master_address_response(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
-	 * BUSY */
-	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
-
-		/* Clear write interrupt flag */
-		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
-
-		/* Check arbitration. */
-		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
-			/* Return packet collision. */
-			return STATUS_ERR_PACKET_COLLISION;
-		}
-	/* Check that slave responded with ack. */
-	} else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-		/* Slave busy. Issue ack and stop command. */
-		i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-
-		/* Return bad address value. */
-		return STATUS_ERR_BAD_ADDRESS;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
+     * BUSY */
+    if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)
+    {
+
+        /* Clear write interrupt flag */
+        i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
+
+        /* Check arbitration. */
+        if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST)
+        {
+            /* Return packet collision. */
+            return STATUS_ERR_PACKET_COLLISION;
+        }
+    /* Check that slave responded with ack. */
+    } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+    {
+        /* Slave busy. Issue ack and stop command. */
+        i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+
+        /* Return bad address value. */
+        return STATUS_ERR_BAD_ADDRESS;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -337,25 +349,27 @@ static enum status_code _i2c_master_address_response(
  *                             period
  */
 static enum status_code _i2c_master_wait_for_bus(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Wait for reply. */
-	uint16_t timeout_counter = 0;
-	while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
-			!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
-
-		/* Check timeout condition. */
-		if (++timeout_counter >= module->buffer_timeout) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Wait for reply. */
+    uint16_t timeout_counter = 0;
+    while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
+            !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB))
+            {
+
+        /* Check timeout condition. */
+        if (++timeout_counter >= module->buffer_timeout)
+        {
+            return STATUS_ERR_TIMEOUT;
+        }
+    }
+    return STATUS_OK;
 }
 #endif /* __DOXYGEN__ */
 
@@ -377,79 +391,86 @@ static enum status_code _i2c_master_wait_for_bus(
  *
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Return value. */
-	enum status_code tmp_status;
-	uint16_t tmp_data_length = packet->data_length;
-
-	/* Written buffer counter. */
-	uint16_t counter = 0;
-
-	/* Set address and direction bit. Will send start command on bus. */
-	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
-
-	/* Wait for response on bus. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-
-	/* Set action to ack. */
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-
-	/* Check for address response error unless previous error is
-	 * detected. */
-	if (tmp_status == STATUS_OK) {
-		tmp_status = _i2c_master_address_response(module);
-	}
-
-	/* Check that no error has occurred. */
-	if (tmp_status == STATUS_OK) {
-		/* Read data buffer. */
-		while (tmp_data_length--) {
-			/* Check that bus ownership is not lost. */
-			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
-				return STATUS_ERR_PACKET_COLLISION;
-			}
-
-			if (module->send_nack && tmp_data_length == 0) {
-				/* Set action to NACK */
-				i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-			} else {
-				/* Save data to buffer. */
-				_i2c_master_wait_for_sync(module);
-				packet->data[counter++] = i2c_module->DATA.reg;
-				/* Wait for response. */
-				tmp_status = _i2c_master_wait_for_bus(module);
-			}
-
-			/* Check for error. */
-			if (tmp_status != STATUS_OK) {
-				break;
-			}
-		}
-
-		if (module->send_stop) {
-			/* Send stop command unless arbitration is lost. */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		} else {
-		  	_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
-		}
-
-		/* Save last data to buffer. */
-		_i2c_master_wait_for_sync(module);
-		packet->data[counter] = i2c_module->DATA.reg;
-	}
-
-	return tmp_status;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Return value. */
+    enum status_code tmp_status;
+    uint16_t tmp_data_length = packet->data_length;
+
+    /* Written buffer counter. */
+    uint16_t counter = 0;
+
+    /* Set address and direction bit. Will send start command on bus. */
+    i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
+
+    /* Wait for response on bus. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+
+    /* Set action to ack. */
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+
+    /* Check for address response error unless previous error is
+     * detected. */
+    if (tmp_status == STATUS_OK)
+    {
+        tmp_status = _i2c_master_address_response(module);
+    }
+
+    /* Check that no error has occurred. */
+    if (tmp_status == STATUS_OK)
+    {
+        /* Read data buffer. */
+        while (tmp_data_length--)
+        {
+            /* Check that bus ownership is not lost. */
+            if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2)))
+            {
+                return STATUS_ERR_PACKET_COLLISION;
+            }
+
+            if (module->send_nack && tmp_data_length == 0)
+            {
+                /* Set action to NACK */
+                i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+            } else {
+                /* Save data to buffer. */
+                _i2c_master_wait_for_sync(module);
+                packet->data[counter++] = i2c_module->DATA.reg;
+                /* Wait for response. */
+                tmp_status = _i2c_master_wait_for_bus(module);
+            }
+
+            /* Check for error. */
+            if (tmp_status != STATUS_OK)
+            {
+                break;
+            }
+        }
+
+        if (module->send_stop)
+        {
+            /* Send stop command unless arbitration is lost. */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        } else {
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
+        }
+
+        /* Save last data to buffer. */
+        _i2c_master_wait_for_sync(module);
+        packet->data[counter] = i2c_module->DATA.reg;
+    }
+
+    return tmp_status;
 }
 
 /**
@@ -474,25 +495,26 @@ static enum status_code _i2c_master_read_packet(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = true;
-	module->send_nack = true;
-	
-	return _i2c_master_read_packet(module, packet);
+    module->send_stop = true;
+    module->send_nack = true;
+
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -521,35 +543,36 @@ enum status_code i2c_master_read_packet_wait(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = true;
-	
-	return _i2c_master_read_packet(module, packet);
+    module->send_stop = false;
+    module->send_nack = true;
+
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
  * \internal
  * Starts blocking read operation.
- * \brief Reads data packet from slave without sending a nack signal and a stop 
+ * \brief Reads data packet from slave without sending a nack signal and a stop
  * condition when done
  *
  * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
- * bus without sending a nack signal and a stop condition when done, 
+ * bus without sending a nack signal and a stop condition when done,
  * thus retaining ownership of the bus when done. To end the transaction, a
  * \ref i2c_master_read_packet_wait "read" or
  * \ref i2c_master_write_packet_wait "write" with stop condition must be
@@ -571,25 +594,26 @@ enum status_code i2c_master_read_packet_wait_no_stop(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_packet_wait_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = false;
+    module->send_stop = false;
+    module->send_nack = false;
 
-	return _i2c_master_read_packet(module, packet);
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -609,69 +633,76 @@ enum status_code i2c_master_read_packet_wait_no_nack(
  *                                      acknowledged the address
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Return value. */
-	enum status_code tmp_status;
-	uint16_t tmp_data_length = packet->data_length;
-
-	_i2c_master_wait_for_sync(module);
-
-	/* Set address and direction bit. Will send start command on bus. */
-	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
-
-	/* Wait for response on bus. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-
-	/* Check for address response error unless previous error is
-	 * detected. */
-	if (tmp_status == STATUS_OK) {
-		tmp_status = _i2c_master_address_response(module);
-	}
-
-	/* Check that no error has occurred. */
-	if (tmp_status == STATUS_OK) {
-		/* Buffer counter. */
-		uint16_t buffer_counter = 0;
-
-		/* Write data buffer. */
-		while (tmp_data_length--) {
-			/* Check that bus ownership is not lost. */
-			if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
-				return STATUS_ERR_PACKET_COLLISION;
-			}
-
-			/* Write byte to slave. */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->DATA.reg = packet->data[buffer_counter++];
-
-			/* Wait for response. */
-			tmp_status = _i2c_master_wait_for_bus(module);
-
-			/* Check for error. */
-			if (tmp_status != STATUS_OK) {
-				break;
-			}
-
-			/* Check for NACK from slave. */
-			if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-				/* Return bad data value. */
-				tmp_status = STATUS_ERR_OVERFLOW;
-				break;
-			}
-		}
-
-		if (module->send_stop) {
-			/* Stop command */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		}
-	}
-
-	return tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Return value. */
+    enum status_code tmp_status;
+    uint16_t tmp_data_length = packet->data_length;
+
+    _i2c_master_wait_for_sync(module);
+
+    /* Set address and direction bit. Will send start command on bus. */
+    i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
+
+    /* Wait for response on bus. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+
+    /* Check for address response error unless previous error is
+     * detected. */
+    if (tmp_status == STATUS_OK)
+    {
+        tmp_status = _i2c_master_address_response(module);
+    }
+
+    /* Check that no error has occurred. */
+    if (tmp_status == STATUS_OK)
+    {
+        /* Buffer counter. */
+        uint16_t buffer_counter = 0;
+
+        /* Write data buffer. */
+        while (tmp_data_length--)
+        {
+            /* Check that bus ownership is not lost. */
+            if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2)))
+            {
+                return STATUS_ERR_PACKET_COLLISION;
+            }
+
+            /* Write byte to slave. */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->DATA.reg = packet->data[buffer_counter++];
+
+            /* Wait for response. */
+            tmp_status = _i2c_master_wait_for_bus(module);
+
+            /* Check for error. */
+            if (tmp_status != STATUS_OK)
+            {
+                break;
+            }
+
+            /* Check for NACK from slave. */
+            if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+            {
+                /* Return bad data value. */
+                tmp_status = STATUS_ERR_OVERFLOW;
+                break;
+            }
+        }
+
+        if (module->send_stop)
+        {
+            /* Stop command */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        }
+    }
+
+    return tmp_status;
 }
 
 /**
@@ -700,25 +731,26 @@ static enum status_code _i2c_master_write_packet(
  *                                      last data sent
  */
 enum status_code i2c_master_write_packet_wait(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = true;
-	module->send_nack = true;
-	
-	return _i2c_master_write_packet(module, packet);
+    module->send_stop = true;
+    module->send_nack = true;
+
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -749,25 +781,26 @@ enum status_code i2c_master_write_packet_wait(
  *                                      more data
  */
 enum status_code i2c_master_write_packet_wait_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
 #if I2C_MASTER_CALLBACK_MODE == true
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	module->send_stop = false;
-	module->send_nack = true;
-	
-	return _i2c_master_write_packet(module, packet);
+    module->send_stop = false;
+    module->send_nack = true;
+
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -784,15 +817,15 @@ enum status_code i2c_master_write_packet_wait_no_stop(
  */
 void i2c_master_send_stop(struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Send stop command */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+    /* Send stop command */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
 }
 
 /**
@@ -807,15 +840,15 @@ void i2c_master_send_stop(struct i2c_master_module *const module)
  */
 void i2c_master_send_nack(struct i2c_master_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Send nack signal */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+    /* Send nack signal */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
 }
 
 /**
@@ -834,20 +867,20 @@ void i2c_master_send_nack(struct i2c_master_module *const module)
  *                                      acknowledged the address
  */
 enum status_code i2c_master_read_byte(
-		struct i2c_master_module *const module,
-		uint8_t *byte)
+        struct i2c_master_module *const module,
+        uint8_t *byte)
 {
-  	enum status_code tmp_status;
-  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-	/* Write byte to slave. */
-	_i2c_master_wait_for_sync(module);
-	*byte = i2c_module->DATA.reg;
-	/* Wait for response. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-	
-	return tmp_status;
+    enum status_code tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+    /* Write byte to slave. */
+    _i2c_master_wait_for_sync(module);
+    *byte = i2c_module->DATA.reg;
+    /* Wait for response. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+
+    return tmp_status;
 }
 
 /**
@@ -866,16 +899,16 @@ enum status_code i2c_master_read_byte(
  *                                      acknowledged the address
  */
 enum status_code i2c_master_write_byte(
-		struct i2c_master_module *const module,
-		uint8_t byte)
+        struct i2c_master_module *const module,
+        uint8_t byte)
 {
-  	enum status_code tmp_status;
-  	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-	
-	/* Write byte to slave. */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->DATA.reg = byte;
-	/* Wait for response. */
-	tmp_status = _i2c_master_wait_for_bus(module);
-	return tmp_status;
-}
\ No newline at end of file
+    enum status_code tmp_status;
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Write byte to slave. */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->DATA.reg = byte;
+    /* Wait for response. */
+    tmp_status = _i2c_master_wait_for_bus(module);
+    return tmp_status;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c
index 07c892a036b9..32210d0ce95c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c
@@ -53,38 +53,40 @@
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_master_read(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Find index to save next value in buffer */
-	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
-
-	module->buffer_remaining--;
-
-	if (!module->buffer_remaining) {
-		/* Send nack */
-	  	if (module->send_nack)
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
-		if (module->send_stop) {
-			/* Send stop condition */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		} else {
-		  	_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
-		}
-	} else {
-		i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
-	}
-
-	/* Read byte from slave and put in buffer */
-	_i2c_master_wait_for_sync(module);
-	module->buffer[buffer_index] = i2c_module->DATA.reg;
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Find index to save next value in buffer */
+    uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+
+    module->buffer_remaining--;
+
+    if (!module->buffer_remaining)
+    {
+        /* Send nack */
+        if (module->send_nack)
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
+        if (module->send_stop)
+        {
+            /* Send stop condition */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        } else {
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1);
+        }
+    } else {
+        i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
+    }
+
+    /* Read byte from slave and put in buffer */
+    _i2c_master_wait_for_sync(module);
+    module->buffer[buffer_index] = i2c_module->DATA.reg;
 }
 
 /**
@@ -96,29 +98,29 @@ static void _i2c_master_read(
  */
 static void _i2c_master_write(struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Check for ack from slave */
-	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
-	{
-		/* Set status */
-		module->status = STATUS_ERR_OVERFLOW;
-		/* Do not write more data */
-		return;
-	}
+    /* Check for ack from slave */
+    if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+    {
+        /* Set status */
+        module->status = STATUS_ERR_OVERFLOW;
+        /* Do not write more data */
+        return;
+    }
 
-	/* Find index to get next byte in buffer */
-	uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
+    /* Find index to get next byte in buffer */
+    uint16_t buffer_index = module->buffer_length - module->buffer_remaining;
 
-	module->buffer_remaining--;
+    module->buffer_remaining--;
 
-	/* Write byte from buffer to slave */
-	_i2c_master_wait_for_sync(module);
-	i2c_module->DATA.reg = module->buffer[buffer_index];
+    /* Write byte from buffer to slave */
+    _i2c_master_wait_for_sync(module);
+    i2c_module->DATA.reg = module->buffer[buffer_index];
 }
 
 /**
@@ -129,52 +131,57 @@ static void _i2c_master_write(struct i2c_master_module *const module)
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_master_async_address_response(
-		struct i2c_master_module *const module)
+        struct i2c_master_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Check for error. Ignore bus-error; workaround for bus state stuck in
-	 * BUSY.
-	 */
-	if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
-	{
-		/* Clear write interrupt flag */
-		i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
-
-		/* Check arbitration */
-		if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
-			/* Return busy */
-			module->status = STATUS_ERR_PACKET_COLLISION;
-		}
-	}
-
-	if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
-		/* Return bad address value */
-		module->status           = STATUS_ERR_BAD_ADDRESS;
-		module->buffer_remaining = 0;
-
-		if (module->send_stop) {
-			/* Send stop condition */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		}
-	}
-
-	module->buffer_length = module->buffer_remaining;
-
-	/* Check for status OK. */
-	if (module->status == STATUS_BUSY) {
-		/* Call function based on transfer direction. */
-		if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-			_i2c_master_write(module);
-		} else {
-			_i2c_master_read(module);
-		}
-	}
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Check for error. Ignore bus-error; workaround for bus state stuck in
+     * BUSY.
+     */
+    if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB)
+    {
+        /* Clear write interrupt flag */
+        i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
+
+        /* Check arbitration */
+        if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST)
+        {
+            /* Return busy */
+            module->status = STATUS_ERR_PACKET_COLLISION;
+        }
+    }
+
+    if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK)
+    {
+        /* Return bad address value */
+        module->status           = STATUS_ERR_BAD_ADDRESS;
+        module->buffer_remaining = 0;
+
+        if (module->send_stop)
+        {
+            /* Send stop condition */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        }
+    }
+
+    module->buffer_length = module->buffer_remaining;
+
+    /* Check for status OK. */
+    if (module->status == STATUS_BUSY)
+    {
+        /* Call function based on transfer direction. */
+        if (module->transfer_direction == I2C_TRANSFER_WRITE)
+        {
+            _i2c_master_write(module);
+        } else {
+            _i2c_master_read(module);
+        }
+    }
 }
 
 /**
@@ -192,20 +199,20 @@ static void _i2c_master_async_address_response(
  * \param[in]      callback_type  Callback type to register
  */
 void i2c_master_register_callback(
-		struct i2c_master_module *const module,
-		const i2c_master_callback_t callback,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        const i2c_master_callback_t callback,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback */
-	module->callbacks[callback_type] = callback;
+    /* Register callback */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as registered */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as registered */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -218,18 +225,18 @@ void i2c_master_register_callback(
  * \param[in]     callback_type  Specifies the callback type to unregister
  */
 void i2c_master_unregister_callback(
-		struct i2c_master_module *const module,
-		enum i2c_master_callback callback_type)
+        struct i2c_master_module *const module,
+        enum i2c_master_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Register callback */
-	module->callbacks[callback_type] = NULL;
+    /* Register callback */
+    module->callbacks[callback_type] = NULL;
 
-	/* Clear corresponding bit to set callback as unregistered */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Clear corresponding bit to set callback as unregistered */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -244,28 +251,28 @@ void i2c_master_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_read_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_READ;
-	module->status             = STATUS_BUSY;
-	module->send_stop = false;
-	module->send_nack = false;
-	
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_READ;
+    module->status             = STATUS_BUSY;
+    module->send_stop = false;
+    module->send_nack = false;
+
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+    return STATUS_OK;
 }
 
 /**
@@ -280,29 +287,29 @@ enum status_code i2c_master_read_bytes(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_read_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_READ;
-	module->status             = STATUS_BUSY;
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_READ;
+    module->status             = STATUS_BUSY;
 
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
 
-	/* Set address and direction bit. Will send start command on bus */
-	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
+    /* Set address and direction bit. Will send start command on bus */
+    i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -319,24 +326,25 @@ static enum status_code _i2c_master_read_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_read_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP */
-	module->send_stop = true;
-	module->send_nack = true;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP */
+    module->send_stop = true;
+    module->send_nack = true;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -358,28 +366,29 @@ enum status_code i2c_master_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another operation
  */
 enum status_code i2c_master_read_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we don't send STOP */
-	module->send_stop = false;
-	module->send_nack = true;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we don't send STOP */
+    module->send_stop = false;
+    module->send_nack = true;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
- * \brief Initiates a read packet operation without sending a NACK signal and a 
+ * \brief Initiates a read packet operation without sending a NACK signal and a
  * STOP condition when done
  *
  * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C bus without
@@ -398,24 +407,25 @@ enum status_code i2c_master_read_packet_job_no_stop(
  * \retval STATUS_BUSY If module is currently busy with another operation
  */
 enum status_code i2c_master_read_packet_job_no_nack(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with a job */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we don't send STOP */
-	module->send_stop = false;
-	module->send_nack = false;
-	/* Start reading */
-	return _i2c_master_read_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with a job */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we don't send STOP */
+    module->send_stop = false;
+    module->send_nack = false;
+    /* Start reading */
+    return _i2c_master_read_packet(module, packet);
 }
 
 /**
@@ -430,28 +440,28 @@ enum status_code i2c_master_read_packet_job_no_nack(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_write_bytes(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_WRITE;
-	module->status             = STATUS_BUSY;
-	module->send_stop = false;
-	module->send_nack = false;
-	
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_WRITE;
+    module->status             = STATUS_BUSY;
+    module->send_stop = false;
+    module->send_nack = false;
+
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+
+    return STATUS_OK;
 }
 
 /**
@@ -465,29 +475,29 @@ enum status_code i2c_master_write_bytes(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 static enum status_code _i2c_master_write_packet(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
 
-	/* Save packet to software module */
-	module->buffer             = packet->data;
-	module->buffer_remaining   = packet->data_length;
-	module->transfer_direction = I2C_TRANSFER_WRITE;
-	module->status             = STATUS_BUSY;
+    /* Save packet to software module */
+    module->buffer             = packet->data;
+    module->buffer_remaining   = packet->data_length;
+    module->transfer_direction = I2C_TRANSFER_WRITE;
+    module->status             = STATUS_BUSY;
 
-	/* Enable interrupts */
-	i2c_module->INTENSET.reg =
-			SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
+    /* Enable interrupts */
+    i2c_module->INTENSET.reg =
+            SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB;
 
-	/* Set address and direction bit, will send start command on bus */
-	i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
+    /* Set address and direction bit, will send start command on bus */
+    i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -504,24 +514,25 @@ static enum status_code _i2c_master_write_packet(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_master_write_packet_job(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Make sure we send STOP at end*/
-	module->send_stop = true;
-	module->send_nack = true;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Make sure we send STOP at end*/
+    module->send_stop = true;
+    module->send_nack = true;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -543,24 +554,25 @@ enum status_code i2c_master_write_packet_job(
  * \retval STATUS_BUSY  If module is currently busy with another
  */
 enum status_code i2c_master_write_packet_job_no_stop(
-		struct i2c_master_module *const module,
-		struct i2c_master_packet *const packet)
+        struct i2c_master_module *const module,
+        struct i2c_master_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy with another job. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Do not send stop condition when done */
-	module->send_stop = false;
-	module->send_nack = true;
-	/* Start write operation */
-	return _i2c_master_write_packet(module, packet);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy with another job. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Do not send stop condition when done */
+    module->send_stop = false;
+    module->send_nack = true;
+    /* Start write operation */
+    return _i2c_master_write_packet(module, packet);
 }
 
 /**
@@ -570,101 +582,114 @@ enum status_code i2c_master_write_packet_job_no_stop(
  * \param[in] instance  SERCOM instance that triggered the interrupt
  */
 void _i2c_master_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Get software module for callback handling */
-	struct i2c_master_module *module =
-			(struct i2c_master_module*)_sercom_instances[instance];
-
-	Assert(module);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Combine callback registered and enabled masks */
-	uint8_t callback_mask = module->enabled_callback &
-			module->registered_callback;
-
-	/* Check if the module should respond to address ack */
-	if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) {
-		/* Call function for address response */
-		_i2c_master_async_address_response(module);
-
-	/* Check if buffer write is done */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_WRITE)) {
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg =
-				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
-
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		if (module->send_stop) {
-			/* Send stop condition */
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
-		} else {
-			/* Clear write interrupt flag */
-			i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
-		}
-		if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) {
-			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
-		}
-
-	/* Continue buffer write/read */
-	} else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){
-		/* Check that bus ownership is not lost */
-		if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
-			module->status = STATUS_ERR_PACKET_COLLISION;
-		} else if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-			_i2c_master_write(module);
-		} else {
-			_i2c_master_read(module);
-		}
-	}
-
-	/* Check if read buffer transfer is complete */
-	if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
-			(module->status == STATUS_BUSY) &&
-			(module->transfer_direction == I2C_TRANSFER_READ)) {
-
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg =
-				SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
-		module->buffer_length = 0;
-		module->status        = STATUS_OK;
-
-		/* Call appropriate callback if enabled and registered */
-		if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
-				&& (module->transfer_direction == I2C_TRANSFER_READ)) {
-			module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
-		} else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
-				&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
-			module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
-		}
-	}
-
-	/* Check for error */
-	if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) {
-		/* Stop packet operation */
-		i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
-				SERCOM_I2CM_INTENCLR_SB;
-
-		module->buffer_length = 0;
-		module->buffer_remaining = 0;
-
-		/* Send nack and stop command unless arbitration is lost */
-		if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
-				module->send_stop) {
-			_i2c_master_wait_for_sync(module);
-			i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
-					SERCOM_I2CM_CTRLB_CMD(3);
-		}
-
-		/* Call error callback if enabled and registered */
-		if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) {
-			module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
-		}
-	}
+    /* Get software module for callback handling */
+    struct i2c_master_module *module =
+            (struct i2c_master_module*)_sercom_instances[instance];
+
+    Assert(module);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Combine callback registered and enabled masks */
+    uint8_t callback_mask = module->enabled_callback &
+            module->registered_callback;
+
+    /* Check if the module should respond to address ack */
+    if ((module->buffer_length <= 0) && (module->buffer_remaining > 0))
+    {
+        /* Call function for address response */
+        _i2c_master_async_address_response(module);
+
+    /* Check if buffer write is done */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_WRITE))
+            {
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg =
+                SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        if (module->send_stop)
+        {
+            /* Send stop condition */
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
+        } else {
+            /* Clear write interrupt flag */
+            i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB;
+        }
+        if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+        {
+            module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+        }
+
+    /* Continue buffer write/read */
+    } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0))
+    {
+        /* Check that bus ownership is not lost */
+        if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2)))
+        {
+            module->status = STATUS_ERR_PACKET_COLLISION;
+        } else if (module->transfer_direction == I2C_TRANSFER_WRITE)
+        {
+            _i2c_master_write(module);
+        } else {
+            _i2c_master_read(module);
+        }
+    }
+
+    /* Check if read buffer transfer is complete */
+    if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) &&
+            (module->status == STATUS_BUSY) &&
+            (module->transfer_direction == I2C_TRANSFER_READ))
+            {
+
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg =
+                SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB;
+        module->buffer_length = 0;
+        module->status        = STATUS_OK;
+
+        /* Call appropriate callback if enabled and registered */
+        if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE))
+                && (module->transfer_direction == I2C_TRANSFER_READ))
+                {
+            module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module);
+        } else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE))
+                && (module->transfer_direction == I2C_TRANSFER_WRITE))
+                {
+            module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module);
+        }
+    }
+
+    /* Check for error */
+    if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK))
+    {
+        /* Stop packet operation */
+        i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB |
+                SERCOM_I2CM_INTENCLR_SB;
+
+        module->buffer_length = 0;
+        module->buffer_remaining = 0;
+
+        /* Send nack and stop command unless arbitration is lost */
+        if ((module->status != STATUS_ERR_PACKET_COLLISION) &&
+                module->send_stop)
+                {
+            _i2c_master_wait_for_sync(module);
+            i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT |
+                    SERCOM_I2CM_CTRLB_CMD(3);
+        }
+
+        /* Call error callback if enabled and registered */
+        if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR))
+        {
+            module->callbacks[I2C_MASTER_CALLBACK_ERROR](module);
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c
index c403479a386e..0efb30ea024a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c
@@ -61,63 +61,66 @@
  *                                         previously set
  */
 static enum status_code _i2c_slave_set_config(
-		struct i2c_slave_module *const module,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        const struct i2c_slave_config *const config)
 {
-	uint32_t tmp_ctrla;
-
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(config);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	Sercom *const sercom_hw = module->hw;
-
-	module->buffer_timeout = config->buffer_timeout;
-
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-
-	uint32_t pad0 = config->pinmux_pad0;
-	uint32_t pad1 = config->pinmux_pad1;
-
-	/* SERCOM PAD0 - SDA */
-	if (pad0 == PINMUX_DEFAULT) {
-		pad0 = _sercom_get_default_pad(sercom_hw, 0);
-	}
-	pin_conf.mux_position = pad0 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
-
-	/* SERCOM PAD1 - SCL */
-	if (pad1 == PINMUX_DEFAULT) {
-		pad1 = _sercom_get_default_pad(sercom_hw, 1);
-	}
-	pin_conf.mux_position = pad1 & 0xFFFF;
-	pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
-	system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
-
-	/* Prepare config to write to register CTRLA */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
-	} else {
-		tmp_ctrla = 0;
-	}
-
-	tmp_ctrla |= config->sda_hold_time |
-			(config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUT_Pos);
-
-	i2c_hw->CTRLA.reg |= tmp_ctrla;
-
-	/* Set CTRLB configuration */
-	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
-
-	i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
-			config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
-			config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
-
-	return STATUS_OK;
+    uint32_t tmp_ctrla;
+
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(config);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    Sercom *const sercom_hw = module->hw;
+
+    module->buffer_timeout = config->buffer_timeout;
+
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+
+    uint32_t pad0 = config->pinmux_pad0;
+    uint32_t pad1 = config->pinmux_pad1;
+
+    /* SERCOM PAD0 - SDA */
+    if (pad0 == PINMUX_DEFAULT)
+    {
+        pad0 = _sercom_get_default_pad(sercom_hw, 0);
+    }
+    pin_conf.mux_position = pad0 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
+
+    /* SERCOM PAD1 - SCL */
+    if (pad1 == PINMUX_DEFAULT)
+    {
+        pad1 = _sercom_get_default_pad(sercom_hw, 1);
+    }
+    pin_conf.mux_position = pad1 & 0xFFFF;
+    pin_conf.direction    = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
+    system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
+
+    /* Prepare config to write to register CTRLA */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY;
+    } else {
+        tmp_ctrla = 0;
+    }
+
+    tmp_ctrla |= config->sda_hold_time |
+            (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUT_Pos);
+
+    i2c_hw->CTRLA.reg |= tmp_ctrla;
+
+    /* Set CTRLB configuration */
+    i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode;
+
+    i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos |
+            config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos |
+            config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos;
+
+    return STATUS_OK;
 }
 
 /**
@@ -139,67 +142,69 @@ static enum status_code _i2c_slave_set_config(
  *                                         previously set
  */
 enum status_code i2c_slave_init(
-		struct i2c_slave_module *const module,
-		Sercom *const hw,
-		const struct i2c_slave_config *const config)
+        struct i2c_slave_module *const module,
+        Sercom *const hw,
+        const struct i2c_slave_config *const config)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
-
-	/* Initialize software module */
-	module->hw = hw;
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Check if module is enabled. */
-	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if reset is in progress. */
-	if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) {
-		return STATUS_BUSY;
-	}
-
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-
-	/* Turn on module in PM */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
+
+    /* Initialize software module */
+    module->hw = hw;
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Check if module is enabled. */
+    if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if reset is in progress. */
+    if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
+
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+
+    /* Turn on module in PM */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Get sercom instance index. */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    /* Get sercom instance index. */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
 
-	/* Save software module in interrupt handler. */
-	_sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
+    /* Save software module in interrupt handler. */
+    _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler);
 
-	/* Save software module. */
-	_sercom_instances[instance_index] = module;
+    /* Save software module. */
+    _sercom_instances[instance_index] = module;
 
-	/* Initialize values in module. */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->nack_on_address = config->enable_nack_on_address;
+    /* Initialize values in module. */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->nack_on_address = config->enable_nack_on_address;
 #endif
 
-	/* Set SERCOM module to operate in I2C slave mode. */
-	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE;
+    /* Set SERCOM module to operate in I2C slave mode. */
+    i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE;
 
-	/* Set config and return status. */
-	return _i2c_slave_set_config(module, config);
+    /* Set config and return status. */
+    return _i2c_slave_set_config(module, config);
 }
 
 /**
@@ -210,38 +215,38 @@ enum status_code i2c_slave_init(
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_reset(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Reset module instance. */
-	module->registered_callback = 0;
-	module->enabled_callback = 0;
-	module->buffer_length = 0;
-	module->buffer_remaining = 0;
-	module->buffer = NULL;
+    /* Reset module instance. */
+    module->registered_callback = 0;
+    module->enabled_callback = 0;
+    module->buffer_length = 0;
+    module->buffer_remaining = 0;
+    module->buffer = NULL;
 #endif
 
-	/* Disable module */
-	i2c_slave_disable(module);
+    /* Disable module */
+    i2c_slave_disable(module);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Clear all pending interrupts. */
-	system_interrupt_enter_critical_section();
-	system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
-	system_interrupt_leave_critical_section();
+    /* Clear all pending interrupts. */
+    system_interrupt_enter_critical_section();
+    system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_leave_critical_section();
 #endif
 
-	/* Wait for sync. */
-	_i2c_slave_wait_for_sync(module);
+    /* Wait for sync. */
+    _i2c_slave_wait_for_sync(module);
 
-	/* Reset module. */
-	i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
+    /* Reset module. */
+    i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST;
 }
 
 /**
@@ -255,26 +260,28 @@ void i2c_slave_reset(
  *                             period
  */
 static enum status_code _i2c_slave_wait_for_bus(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cm *const i2c_module = &(module->hw->I2CM);
-
-	/* Wait for reply. */
-	uint16_t timeout_counter = 0;
-	while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
-			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
-			(!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) {
-
-		/* Check timeout condition. */
-		if (++timeout_counter >= module->buffer_timeout) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-	return STATUS_OK;
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cm *const i2c_module = &(module->hw->I2CM);
+
+    /* Wait for reply. */
+    uint16_t timeout_counter = 0;
+    while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) &&
+            (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) &&
+            (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)))
+            {
+
+        /* Check timeout condition. */
+        if (++timeout_counter >= module->buffer_timeout)
+        {
+            return STATUS_ERR_TIMEOUT;
+        }
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -300,99 +307,109 @@ static enum status_code _i2c_slave_wait_for_bus(
  *                                  period
  */
 enum status_code i2c_slave_write_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	uint16_t length = packet->data_length;
+    uint16_t length = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Check if the module is busy with a job or AMATCH is enabled */
-	if (module->buffer_remaining > 0 ||
-			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy with a job or AMATCH is enabled */
+    if (module->buffer_remaining > 0 ||
+            (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+            {
+        return STATUS_BUSY;
+    }
 #endif
 
-	enum status_code status;
-	/* Wait for master to send address packet */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-	}
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if there was an error in last transfer */
-	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Check direction */
-	if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Write request from master, send NACK and return, workaround 13574*/
-		_i2c_slave_set_ctrlb_ackact(module, false);
-		_i2c_slave_set_ctrlb_cmd3(module);
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Read request from master, ACK address, workaround 13574 */
-	_i2c_slave_set_ctrlb_ackact(module, true);
-	_i2c_slave_set_ctrlb_cmd3(module);
-
-	uint16_t i = 0;
-
-	/* Wait for data interrupt */
-	status = _i2c_slave_wait_for_bus(module);
-	if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-	}
-
-	while (length--) {
-		/* Write data */
-		_i2c_slave_wait_for_sync(module);
-		i2c_hw->DATA.reg = packet->data[i++];
-
-		/* Wait for response from master */
-		status = _i2c_slave_wait_for_bus(module);
-
-		if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-		}
-
-		if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
-				length !=0) {
-			/* NACK from master, abort */
-			/* Release line */
-			i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
-
-			return STATUS_ERR_OVERFLOW;
-			/* Workaround: PIF will probably not be set, ignore */
-		}
-		/* ACK from master, continue writing */
-	}
-
-	/* Release line */
-	i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
-
-	return STATUS_OK;
+    enum status_code status;
+    /* Wait for master to send address packet */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (status != STATUS_OK)
+    {
+            /* Timeout, return */
+            return status;
+    }
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if there was an error in last transfer */
+    if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+            SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+            {
+        return STATUS_ERR_IO;
+    }
+
+    /* Check direction */
+    if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Write request from master, send NACK and return, workaround 13574*/
+        _i2c_slave_set_ctrlb_ackact(module, false);
+        _i2c_slave_set_ctrlb_cmd3(module);
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Read request from master, ACK address, workaround 13574 */
+    _i2c_slave_set_ctrlb_ackact(module, true);
+    _i2c_slave_set_ctrlb_cmd3(module);
+
+    uint16_t i = 0;
+
+    /* Wait for data interrupt */
+    status = _i2c_slave_wait_for_bus(module);
+    if (status != STATUS_OK)
+    {
+            /* Timeout, return */
+            return status;
+    }
+
+    while (length--)
+    {
+        /* Write data */
+        _i2c_slave_wait_for_sync(module);
+        i2c_hw->DATA.reg = packet->data[i++];
+
+        /* Wait for response from master */
+        status = _i2c_slave_wait_for_bus(module);
+
+        if (status != STATUS_OK)
+        {
+            /* Timeout, return */
+            return status;
+        }
+
+        if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK &&
+                length !=0)
+                {
+            /* NACK from master, abort */
+            /* Release line */
+            i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+            return STATUS_ERR_OVERFLOW;
+            /* Workaround: PIF will probably not be set, ignore */
+        }
+        /* ACK from master, continue writing */
+    }
+
+    /* Release line */
+    i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02);
+
+    return STATUS_OK;
 }
 
 /**
@@ -418,98 +435,109 @@ enum status_code i2c_slave_write_packet_wait(
  * \retval STATUS_ERR_ERR_OVERFLOW  Last byte received overflows buffer
  */
 enum status_code i2c_slave_read_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	uint16_t length = packet->data_length;
+    uint16_t length = packet->data_length;
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Check if the module is busy with a job or AMATCH is enabled */
-	if (module->buffer_remaining > 0 ||
-			(i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		return STATUS_BUSY;
-	}
+    /* Check if the module is busy with a job or AMATCH is enabled */
+    if (module->buffer_remaining > 0 ||
+            (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+            {
+        return STATUS_BUSY;
+    }
 #endif
 
-	enum status_code status;
-
-	/* Wait for master to send address packet */
-	status = _i2c_slave_wait_for_bus(module);
-	if (status != STATUS_OK) {
-		/* Timeout, return */
-		return status;
-	}
-
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if there was an error in the last transfer */
-	if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-			SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-		return STATUS_ERR_IO;
-	}
-	/* Check direction */
-	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Read request from master, send NACK and return, workaround 13574 */
-		_i2c_slave_set_ctrlb_ackact(module, false);
-		_i2c_slave_set_ctrlb_cmd3(module);
-		return STATUS_ERR_BAD_FORMAT;
-	}
-
-	/* Write request from master, ACK address, workaround 13574 */
-	_i2c_slave_set_ctrlb_ackact(module, true);
-	_i2c_slave_set_ctrlb_cmd3(module);
-
-	uint16_t i = 0;
-	while (length--) {
-
-		/* Wait for next byte or stop condition */
-		status = _i2c_slave_wait_for_bus(module);
-		if (status != STATUS_OK) {
-			/* Timeout, return */
-			return status;
-		}
-
-		if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
-				i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
-			/* Master sent stop condition, or repeated start, read done */
-			/* Clear stop flag */
-			i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-			return STATUS_ABORTED;
-		}
-
-		/* Read data */
-		_i2c_slave_wait_for_sync(module);
-		packet->data[i++] = i2c_hw->DATA.reg;
-
-	}
-
-	/* Packet read done, wait for packet to NACK, Stop or repeated start */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
-		/* Buffer is full, send NACK */
-		_i2c_slave_set_ctrlb_ackact(module, false);
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-	}
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
-		/* Clear stop flag */
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-	}
-	return STATUS_OK;
+    enum status_code status;
+
+    /* Wait for master to send address packet */
+    status = _i2c_slave_wait_for_bus(module);
+    if (status != STATUS_OK)
+    {
+        /* Timeout, return */
+        return status;
+    }
+
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if there was an error in the last transfer */
+    if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+            SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+            {
+        return STATUS_ERR_IO;
+    }
+    /* Check direction */
+    if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Read request from master, send NACK and return, workaround 13574 */
+        _i2c_slave_set_ctrlb_ackact(module, false);
+        _i2c_slave_set_ctrlb_cmd3(module);
+        return STATUS_ERR_BAD_FORMAT;
+    }
+
+    /* Write request from master, ACK address, workaround 13574 */
+    _i2c_slave_set_ctrlb_ackact(module, true);
+    _i2c_slave_set_ctrlb_cmd3(module);
+
+    uint16_t i = 0;
+    while (length--)
+    {
+
+        /* Wait for next byte or stop condition */
+        status = _i2c_slave_wait_for_bus(module);
+        if (status != STATUS_OK)
+        {
+            /* Timeout, return */
+            return status;
+        }
+
+        if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) ||
+                i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)
+                {
+            /* Master sent stop condition, or repeated start, read done */
+            /* Clear stop flag */
+            i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+            return STATUS_ABORTED;
+        }
+
+        /* Read data */
+        _i2c_slave_wait_for_sync(module);
+        packet->data[i++] = i2c_hw->DATA.reg;
+
+    }
+
+    /* Packet read done, wait for packet to NACK, Stop or repeated start */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        /* Buffer is full, send NACK */
+        _i2c_slave_set_ctrlb_ackact(module, false);
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+    }
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        /* Clear stop flag */
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -530,37 +558,40 @@ enum status_code i2c_slave_read_packet_wait(
  * \retval I2C_SLAVE_DIRECTION_WRITE  Read request from master
  */
 enum i2c_slave_direction i2c_slave_get_direction_wait(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	enum status_code status;
-
-	/* Wait for address interrupt */
-	status = _i2c_slave_wait_for_bus(module);
-
-	if (status != STATUS_OK) {
-		/* Timeout, return */
-		return I2C_SLAVE_DIRECTION_NONE;
-	}
-
-	if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) {
-		/* Not address interrupt, something is wrong */
-		return I2C_SLAVE_DIRECTION_NONE;
-	}
-
-	/* Check direction */
-	if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) {
-		/* Read request from master */
-		return I2C_SLAVE_DIRECTION_WRITE;
-	} else {
-		/* Write request from master */
-		return I2C_SLAVE_DIRECTION_READ;
-	}
+    /* Sanity check arguments. */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    enum status_code status;
+
+    /* Wait for address interrupt */
+    status = _i2c_slave_wait_for_bus(module);
+
+    if (status != STATUS_OK)
+    {
+        /* Timeout, return */
+        return I2C_SLAVE_DIRECTION_NONE;
+    }
+
+    if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))
+    {
+        /* Not address interrupt, something is wrong */
+        return I2C_SLAVE_DIRECTION_NONE;
+    }
+
+    /* Check direction */
+    if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR))
+    {
+        /* Read request from master */
+        return I2C_SLAVE_DIRECTION_WRITE;
+    } else {
+        /* Write request from master */
+        return I2C_SLAVE_DIRECTION_READ;
+    }
 }
 
 /**
@@ -593,56 +624,65 @@ enum i2c_slave_direction i2c_slave_get_direction_wait(
  *                                          occurred on the bus
  */
 uint32_t i2c_slave_get_status(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	 /* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	uint8_t intflags = i2c_hw->INTFLAG.reg;
-	uint8_t status = i2c_hw->STATUS.reg;
-	uint32_t status_flags = 0;
-
-	/* Check Address Match flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) {
-		status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
-	}
-	/* Check Data Ready flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_DRDY) {
-		status_flags |= I2C_SLAVE_STATUS_DATA_READY;
-	}
-	/* Check Stop flag */
-	if (intflags & SERCOM_I2CS_INTFLAG_PREC) {
-		status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
-	}
-	/* Check Clock Hold */
-	if (status & SERCOM_I2CS_STATUS_CLKHOLD) {
-		status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
-	}
-	/* Check SCL Low Timeout */
-	if (status & SERCOM_I2CS_STATUS_LOWTOUT) {
-		status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
-	}
-	/* Check Repeated Start */
-	if (status & SERCOM_I2CS_STATUS_SR) {
-		status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
-	}
-	/* Check Received Not Acknowledge */
-	if (status & SERCOM_I2CS_STATUS_RXNACK) {
-		status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
-	}
-	/* Check Transmit Collision */
-	if (status & SERCOM_I2CS_STATUS_COLL) {
-		status_flags |= I2C_SLAVE_STATUS_COLLISION;
-	}
-	/* Check Bus Error */
-	if (status & SERCOM_I2CS_STATUS_BUSERR) {
-		status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
-	}
-
-	return status_flags;
+     /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    uint8_t intflags = i2c_hw->INTFLAG.reg;
+    uint8_t status = i2c_hw->STATUS.reg;
+    uint32_t status_flags = 0;
+
+    /* Check Address Match flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_AMATCH)
+    {
+        status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH;
+    }
+    /* Check Data Ready flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        status_flags |= I2C_SLAVE_STATUS_DATA_READY;
+    }
+    /* Check Stop flag */
+    if (intflags & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED;
+    }
+    /* Check Clock Hold */
+    if (status & SERCOM_I2CS_STATUS_CLKHOLD)
+    {
+        status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD;
+    }
+    /* Check SCL Low Timeout */
+    if (status & SERCOM_I2CS_STATUS_LOWTOUT)
+    {
+        status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT;
+    }
+    /* Check Repeated Start */
+    if (status & SERCOM_I2CS_STATUS_SR)
+    {
+        status_flags |= I2C_SLAVE_STATUS_REPEATED_START;
+    }
+    /* Check Received Not Acknowledge */
+    if (status & SERCOM_I2CS_STATUS_RXNACK)
+    {
+        status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK;
+    }
+    /* Check Transmit Collision */
+    if (status & SERCOM_I2CS_STATUS_COLL)
+    {
+        status_flags |= I2C_SLAVE_STATUS_COLLISION;
+    }
+    /* Check Bus Error */
+    if (status & SERCOM_I2CS_STATUS_BUSERR)
+    {
+        status_flags |= I2C_SLAVE_STATUS_BUS_ERROR;
+    }
+
+    return status_flags;
 }
 
 /**
@@ -657,37 +697,43 @@ uint32_t i2c_slave_get_status(
  *
  */
 void i2c_slave_clear_status(
-		struct i2c_slave_module *const module,
-		uint32_t status_flags)
+        struct i2c_slave_module *const module,
+        uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Clear Address Match flag */
-	if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-	}
-	/* Clear Data Ready flag */
-	if (status_flags & I2C_SLAVE_STATUS_DATA_READY) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
-	}
-	/* Clear Stop flag */
-	if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-	}
-	/* Clear SCL Low Timeout */
-	if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
-	}
-	/* Clear Transmit Collision */
-	if (status_flags & I2C_SLAVE_STATUS_COLLISION) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
-	}
-	/* Clear Bus Error */
-	if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) {
-		i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Clear Address Match flag */
+    if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+    }
+    /* Clear Data Ready flag */
+    if (status_flags & I2C_SLAVE_STATUS_DATA_READY)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY;
+    }
+    /* Clear Stop flag */
+    if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+    }
+    /* Clear SCL Low Timeout */
+    if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT;
+    }
+    /* Clear Transmit Collision */
+    if (status_flags & I2C_SLAVE_STATUS_COLLISION)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL;
+    }
+    /* Clear Bus Error */
+    if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR)
+    {
+        i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c
index 29d222bd2cac..495c0e0b4170 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c
@@ -55,12 +55,12 @@
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_enable_nack_on_address(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
+    /* Sanity check arguments. */
+    Assert(module);
 
-	module->nack_on_address = true;
+    module->nack_on_address = true;
 }
 
 /**
@@ -72,12 +72,12 @@ void i2c_slave_enable_nack_on_address(
  * \param[in,out] module  Pointer to software module structure
  */
 void i2c_slave_disable_nack_on_address(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check arguments. */
-	Assert(module);
+    /* Sanity check arguments. */
+    Assert(module);
 
-	module->nack_on_address = false;
+    module->nack_on_address = false;
 }
 
 /**
@@ -87,15 +87,15 @@ void i2c_slave_disable_nack_on_address(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_read(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	/* Read byte from master and put in buffer. */
-	*(module->buffer++) = i2c_hw->DATA.reg;
+    /* Read byte from master and put in buffer. */
+    *(module->buffer++) = i2c_hw->DATA.reg;
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -105,15 +105,15 @@ static void _i2c_slave_read(
  * \param[in,out] module  Pointer to software module structure
  */
 static void _i2c_slave_write(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	/* Write byte from buffer to master */
-	i2c_hw->DATA.reg = *(module->buffer++);
+    /* Write byte from buffer to master */
+    i2c_hw->DATA.reg = *(module->buffer++);
 
-	/*Decrement remaining buffer length */
-	module->buffer_remaining--;
+    /*Decrement remaining buffer length */
+    module->buffer_remaining--;
 }
 
 /**
@@ -129,20 +129,20 @@ static void _i2c_slave_write(
  * \param[in]     callback_type  Callback type to register
  */
 void i2c_slave_register_callback(
-		struct i2c_slave_module *const module,
-		i2c_slave_callback_t callback,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        i2c_slave_callback_t callback,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
-	Assert(callback);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
+    Assert(callback);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = callback;
+    /* Register callback. */
+    module->callbacks[callback_type] = callback;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback |= (1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -155,18 +155,18 @@ void i2c_slave_register_callback(
  * \param[in]      callback_type  Callback type to unregister
  */
 void i2c_slave_unregister_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Register callback. */
-	module->callbacks[callback_type] = NULL;
+    /* Register callback. */
+    module->callbacks[callback_type] = NULL;
 
-	/* Set corresponding bit to set callback as initiated. */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Set corresponding bit to set callback as initiated. */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -186,32 +186,33 @@ void i2c_slave_unregister_callback(
  * \retval STATUS_BUSY  If module is currently busy with another transfer
  */
 enum status_code i2c_slave_read_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy doing async operation. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status           = STATUS_BUSY;
-
-	/* Enable interrupts */
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
-			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
-
-	/* Read will begin when master initiates the transfer */
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy doing async operation. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+            SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+    /* Read will begin when master initiates the transfer */
+    return STATUS_OK;
 }
 
 /**
@@ -231,31 +232,32 @@ enum status_code i2c_slave_read_packet_job(
  * \retval STATUS_BUSY If module is currently busy with another transfer
  */
 enum status_code i2c_slave_write_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet)
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-	Assert(packet);
-
-	/* Check if the I2C module is busy doing async operation. */
-	if (module->buffer_remaining > 0) {
-		return STATUS_BUSY;
-	}
-
-	/* Save packet to software module. */
-	module->buffer           = packet->data;
-	module->buffer_remaining = packet->data_length;
-	module->buffer_length    = packet->data_length;
-	module->status           = STATUS_BUSY;
-
-	/* Enable interrupts */
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
-			SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
-
-	return STATUS_OK;
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+    Assert(packet);
+
+    /* Check if the I2C module is busy doing async operation. */
+    if (module->buffer_remaining > 0)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Save packet to software module. */
+    module->buffer           = packet->data;
+    module->buffer_remaining = packet->data_length;
+    module->buffer_length    = packet->data_length;
+    module->status           = STATUS_BUSY;
+
+    /* Enable interrupts */
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH |
+            SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC;
+
+    return STATUS_OK;
 }
 
 /**
@@ -264,171 +266,195 @@ enum status_code i2c_slave_write_packet_job(
  * \param[in] instance Sercom instance that triggered the interrupt
  */
 void _i2c_slave_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Get software module for callback handling. */
-	struct i2c_slave_module *module =
-			(struct i2c_slave_module*)_sercom_instances[instance];
-
-	Assert(module);
-
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-
-	/* Combine callback registered and enabled masks. */
-	uint8_t callback_mask =
-			module->enabled_callback & module->registered_callback;
-
-
-	if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) {
-	/* Address match */
-		/* Check if last transfer is done - repeated start */
-		if (module->buffer_length != module->buffer_remaining &&
-				module->transfer_direction == I2C_TRANSFER_WRITE) {
-
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-			}
-		} else if (module->buffer_length != module->buffer_remaining &&
-				module->transfer_direction == I2C_TRANSFER_READ) {
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
-			}
-		}
-
-		if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
-				SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) {
-			/* An error occurred in last packet transfer */
-			module->status = STATUS_ERR_IO;
-
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) {
-				module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
-			}
-		}
-		if (module->nack_on_address) {
-			/* NACK address, workaround 13574 */
-			_i2c_slave_set_ctrlb_ackact(module, false);
-		} else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) {
-			/* Set transfer direction in module instance */
-			module->transfer_direction = I2C_TRANSFER_READ;
-
-			/* Read request from master */
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) {
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
-			}
-
-			if (module->buffer_length == 0) {
-				/* Data buffer not set up, NACK address, workaround 13574*/
-				_i2c_slave_set_ctrlb_ackact(module, false);
-			} else {
-				/* ACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, true);
-			}
-		} else {
-			/* Set transfer direction in dev inst */
-			module->transfer_direction = I2C_TRANSFER_WRITE;
-
-			/* Write request from master */
-			if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) {
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
-			}
-
-			if (module->buffer_length == 0) {
-				/* Data buffer not set up, NACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-			} else {
-				/* ACK address, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, true);
-			}
-		}
-
-		/* ACK or NACK address, Workaround 13574 */
-		_i2c_slave_set_ctrlb_cmd3(module);
-
-		/* ACK next incoming packet, workaround 13574 */
-		_i2c_slave_set_ctrlb_ackact(module, true);
-
-	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) {
-		/* Stop condition on bus - current transfer done */
-
-		/* Clear Stop interrupt */
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-
-		/* Disable interrupts */
-		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
-
-		if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
-				|| (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) {
-			/* Disable address match if read/write request is not enabled */
-			i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-		}
-
-		if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) {
-			module->status = STATUS_OK;
-			module->buffer_length = 0;
-			module->buffer_remaining = 0;
-
-			/* Call appropriate callback if enabled and registered */
-			if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
-					&& (module->transfer_direction == I2C_TRANSFER_WRITE)) {
-				/* Read from master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
-			} else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
-					&& (module->transfer_direction == I2C_TRANSFER_READ)) {
-				/* Write to master complete */
-				module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
-			}
-					}
-	} else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) {
-		/* Check if buffer is full, or NACK from master */
-		if (module->buffer_remaining <= 0 ||
-				(module->transfer_direction == I2C_TRANSFER_READ &&
-				(module->buffer_length > module->buffer_remaining) &&
-				(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) {
-
-			module->buffer_remaining = 0;
-			module->buffer_length = 0;
-
-			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-				/* Buffer is full, send NACK, workaround 13574 */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-
-				/* Set status, new character in DATA register will overflow
-				 * buffer */
-				module->status = STATUS_ERR_OVERFLOW;
-
-				if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) {
-					/* Read complete */
-					module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
-				}
-			} else {
-				/* Release SCL and wait for new start condition */
-				_i2c_slave_set_ctrlb_ackact(module, false);
-				i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
-
-				/* Transfer successful */
-				module->status = STATUS_OK;
-
-				/* Disable interrupts */
-				i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
-			}
-
-		/* Continue buffer write/read */
-		} else if (module->buffer_length > 0 && module->buffer_remaining > 0) {
-			/* Call function based on transfer direction */
-			if (module->transfer_direction == I2C_TRANSFER_WRITE) {
-				_i2c_slave_read(module);
-			} else {
-				_i2c_slave_write(module);
-			}
-		}
-	}
+    /* Get software module for callback handling. */
+    struct i2c_slave_module *module =
+            (struct i2c_slave_module*)_sercom_instances[instance];
+
+    Assert(module);
+
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+
+    /* Combine callback registered and enabled masks. */
+    uint8_t callback_mask =
+            module->enabled_callback & module->registered_callback;
+
+
+    if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)
+    {
+    /* Address match */
+        /* Check if last transfer is done - repeated start */
+        if (module->buffer_length != module->buffer_remaining &&
+                module->transfer_direction == I2C_TRANSFER_WRITE)
+                {
+
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+            }
+        } else if (module->buffer_length != module->buffer_remaining &&
+                module->transfer_direction == I2C_TRANSFER_READ)
+                {
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+            }
+        }
+
+        if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR |
+                SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT))
+                {
+            /* An error occurred in last packet transfer */
+            module->status = STATUS_ERR_IO;
+
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER)))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module);
+            }
+        }
+        if (module->nack_on_address)
+        {
+            /* NACK address, workaround 13574 */
+            _i2c_slave_set_ctrlb_ackact(module, false);
+        } else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)
+        {
+            /* Set transfer direction in module instance */
+            module->transfer_direction = I2C_TRANSFER_READ;
+
+            /* Read request from master */
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module);
+            }
+
+            if (module->buffer_length == 0)
+            {
+                /* Data buffer not set up, NACK address, workaround 13574*/
+                _i2c_slave_set_ctrlb_ackact(module, false);
+            } else {
+                /* ACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, true);
+            }
+        } else {
+            /* Set transfer direction in dev inst */
+            module->transfer_direction = I2C_TRANSFER_WRITE;
+
+            /* Write request from master */
+            if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST))
+            {
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module);
+            }
+
+            if (module->buffer_length == 0)
+            {
+                /* Data buffer not set up, NACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+            } else {
+                /* ACK address, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, true);
+            }
+        }
+
+        /* ACK or NACK address, Workaround 13574 */
+        _i2c_slave_set_ctrlb_cmd3(module);
+
+        /* ACK next incoming packet, workaround 13574 */
+        _i2c_slave_set_ctrlb_ackact(module, true);
+
+    } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)
+    {
+        /* Stop condition on bus - current transfer done */
+
+        /* Clear Stop interrupt */
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+
+        /* Disable interrupts */
+        i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY;
+
+        if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST))
+                || (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST))))
+                {
+            /* Disable address match if read/write request is not enabled */
+            i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+        }
+
+        if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO))
+        {
+            module->status = STATUS_OK;
+            module->buffer_length = 0;
+            module->buffer_remaining = 0;
+
+            /* Call appropriate callback if enabled and registered */
+            if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))
+                    && (module->transfer_direction == I2C_TRANSFER_WRITE))
+                    {
+                /* Read from master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module);
+            } else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))
+                    && (module->transfer_direction == I2C_TRANSFER_READ))
+                    {
+                /* Write to master complete */
+                module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module);
+            }
+                    }
+    } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)
+    {
+        /* Check if buffer is full, or NACK from master */
+        if (module->buffer_remaining <= 0 ||
+                (module->transfer_direction == I2C_TRANSFER_READ &&
+                (module->buffer_length > module->buffer_remaining) &&
+                (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK)))
+                {
+
+            module->buffer_remaining = 0;
+            module->buffer_length = 0;
+
+            if (module->transfer_direction == I2C_TRANSFER_WRITE)
+            {
+                /* Buffer is full, send NACK, workaround 13574 */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+                i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+                /* Set status, new character in DATA register will overflow
+                 * buffer */
+                module->status = STATUS_ERR_OVERFLOW;
+
+                if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR))
+                {
+                    /* Read complete */
+                    module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module);
+                }
+            } else {
+                /* Release SCL and wait for new start condition */
+                _i2c_slave_set_ctrlb_ackact(module, false);
+                i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2);
+
+                /* Transfer successful */
+                module->status = STATUS_OK;
+
+                /* Disable interrupts */
+                i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY;
+            }
+
+        /* Continue buffer write/read */
+        } else if (module->buffer_length > 0 && module->buffer_remaining > 0)
+        {
+            /* Call function based on transfer direction */
+            if (module->transfer_direction == I2C_TRANSFER_WRITE)
+            {
+                _i2c_slave_read(module);
+            } else {
+                _i2c_slave_write(module);
+            }
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h
index 011104f04dc4..9b23e9164d95 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave.h
@@ -115,10 +115,10 @@ extern "C" {
  * Structure to be used when transferring I<SUP>2</SUP>C slave packets.
  */
 struct i2c_slave_packet {
-	/** Length of data array */
-	uint16_t data_length;
-	/** Data array containing all data to be transferred */
-	uint8_t *data;
+    /** Length of data array */
+    uint16_t data_length;
+    /** Data array containing all data to be transferred */
+    uint8_t *data;
 };
 
 #if I2C_SLAVE_CALLBACK_MODE == true
@@ -128,29 +128,29 @@ struct i2c_slave_packet {
  * The available callback types for the I<SUP>2</SUP>C slave.
  */
 enum i2c_slave_callback {
-	/** Callback for packet write complete */
-	I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
-	/** Callback for packet read complete */
-	I2C_SLAVE_CALLBACK_READ_COMPLETE,
-	/**
-	 * Callback for read request from master - can be used to
-	 * issue a write
-	 */
-	I2C_SLAVE_CALLBACK_READ_REQUEST,
-	/**
-	 * Callback for write request from master - can be used to issue a read
-	 */
-	I2C_SLAVE_CALLBACK_WRITE_REQUEST,
-	/** Callback for error */
-	I2C_SLAVE_CALLBACK_ERROR,
-	/**
-	 * Callback for error in last transfer. Discovered on a new address
-	 * interrupt.
-	 */
-	I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER,
+    /** Callback for packet write complete */
+    I2C_SLAVE_CALLBACK_WRITE_COMPLETE,
+    /** Callback for packet read complete */
+    I2C_SLAVE_CALLBACK_READ_COMPLETE,
+    /**
+     * Callback for read request from master - can be used to
+     * issue a write
+     */
+    I2C_SLAVE_CALLBACK_READ_REQUEST,
+    /**
+     * Callback for write request from master - can be used to issue a read
+     */
+    I2C_SLAVE_CALLBACK_WRITE_REQUEST,
+    /** Callback for error */
+    I2C_SLAVE_CALLBACK_ERROR,
+    /**
+     * Callback for error in last transfer. Discovered on a new address
+     * interrupt.
+     */
+    I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER,
 #  if !defined(__DOXYGEN__)
-	/** Total number of callbacks */
-	_I2C_SLAVE_CALLBACK_N,
+    /** Total number of callbacks */
+    _I2C_SLAVE_CALLBACK_N,
 #  endif
 };
 
@@ -160,7 +160,7 @@ struct i2c_slave_module;
 
 /** Callback type */
 typedef void (*i2c_slave_callback_t)(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 #  endif
 #endif
 
@@ -172,18 +172,18 @@ typedef void (*i2c_slave_callback_t)(
  * of SCL.
  */
 enum i2c_slave_sda_hold_time {
-	/** SDA hold time disabled */
-	I2C_SLAVE_SDA_HOLD_TIME_DISABLED =
-			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
-	/** SDA hold time 50ns - 100ns */
-	I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS =
-			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
-	/** SDA hold time 300ns - 600ns */
-	I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS =
-			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
-	/** SDA hold time 400ns - 800ns */
-	I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS =
-			((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+    /** SDA hold time disabled */
+    I2C_SLAVE_SDA_HOLD_TIME_DISABLED =
+            ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+    /** SDA hold time 50ns - 100ns */
+    I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS =
+            ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+    /** SDA hold time 300ns - 600ns */
+    I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS =
+            ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
+    /** SDA hold time 400ns - 800ns */
+    I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS =
+            ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))),
 };
 
 /**
@@ -192,15 +192,15 @@ enum i2c_slave_sda_hold_time {
  * Enum for the possible address modes.
  */
 enum i2c_slave_address_mode {
-	/** Address match on address_mask used as a mask to address */
-	I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0),
-	/** Address math on both address and address_mask */
-	I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1),
-	/**
-	 * Address match on range of addresses between and including address and
-	 * address_mask
-	 */
-	I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2),
+    /** Address match on address_mask used as a mask to address */
+    I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0),
+    /** Address math on both address and address_mask */
+    I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1),
+    /**
+     * Address match on range of addresses between and including address and
+     * address_mask
+     */
+    I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2),
 };
 
 /**
@@ -209,12 +209,12 @@ enum i2c_slave_address_mode {
  * Enum for the direction of a request.
  */
 enum i2c_slave_direction {
-	/** Read */
-	I2C_SLAVE_DIRECTION_READ,
-	/** Write */
-	I2C_SLAVE_DIRECTION_WRITE,
-	/** No direction */
-	I2C_SLAVE_DIRECTION_NONE,
+    /** Read */
+    I2C_SLAVE_DIRECTION_READ,
+    /** Write */
+    I2C_SLAVE_DIRECTION_WRITE,
+    /** No direction */
+    I2C_SLAVE_DIRECTION_NONE,
 };
 
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
@@ -224,12 +224,12 @@ enum i2c_slave_direction {
  * Enum for the transfer speed.
  */
 enum i2c_slave_transfer_speed {
-	/** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
-	I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0),
-	/** Fast-mode Plus (Fm+) up to 1MHz */
-	I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1),
-	/** High-speed mode (Hs-mode) up to 3.4MHz */
-	I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2),
+    /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */
+    I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0),
+    /** Fast-mode Plus (Fm+) up to 1MHz */
+    I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1),
+    /** High-speed mode (Hs-mode) up to 3.4MHz */
+    I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2),
 };
 #endif
 
@@ -244,38 +244,38 @@ enum i2c_slave_transfer_speed {
  */
 struct i2c_slave_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware instance initialized for the struct */
-	Sercom *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** Timeout value for polled functions */
-	uint16_t buffer_timeout;
+    /** Hardware instance initialized for the struct */
+    Sercom *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** Timeout value for polled functions */
+    uint16_t buffer_timeout;
 #  ifdef FEATURE_I2C_10_BIT_ADDRESS
-	/** Using 10-bit addressing for the slave */
-	bool ten_bit_address;
+    /** Using 10-bit addressing for the slave */
+    bool ten_bit_address;
 #  endif
 #  if I2C_SLAVE_CALLBACK_MODE == true
-	/** Nack on address match */
-	bool nack_on_address;
-	/** Pointers to callback functions */
-	volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
-	/** Mask for registered callbacks */
-	volatile uint8_t registered_callback;
-	/** Mask for enabled callbacks */
-	volatile uint8_t enabled_callback;
-	/** The total number of bytes to transfer */
-	volatile uint16_t buffer_length;
-	/**
-	 * Counter used for bytes left to send in write and to count number of
-	 * obtained bytes in read
-	 */
-	uint16_t buffer_remaining;
-	/** Data buffer for packet write and read */
-	volatile uint8_t *buffer;
-	/** Save direction of request from master. 1 = read, 0 = write. */
-	volatile enum i2c_transfer_direction transfer_direction;
-	/** Status for status read back in error callback */
-	volatile enum status_code status;
+    /** Nack on address match */
+    bool nack_on_address;
+    /** Pointers to callback functions */
+    volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N];
+    /** Mask for registered callbacks */
+    volatile uint8_t registered_callback;
+    /** Mask for enabled callbacks */
+    volatile uint8_t enabled_callback;
+    /** The total number of bytes to transfer */
+    volatile uint16_t buffer_length;
+    /**
+     * Counter used for bytes left to send in write and to count number of
+     * obtained bytes in read
+     */
+    uint16_t buffer_remaining;
+    /** Data buffer for packet write and read */
+    volatile uint8_t *buffer;
+    /** Save direction of request from master. 1 = read, 0 = write. */
+    volatile enum i2c_transfer_direction transfer_direction;
+    /** Status for status read back in error callback */
+    volatile enum status_code status;
 #  endif
 #endif
 };
@@ -289,58 +289,58 @@ struct i2c_slave_module {
  * \ref i2c_slave_get_config_defaults.
  */
 struct i2c_slave_config {
-	/** Set to enable the SCL low timeout */
-	bool enable_scl_low_timeout;
-	/** SDA hold time with respect to the negative edge of SCL */
-	enum i2c_slave_sda_hold_time sda_hold_time;
-	/** Timeout to wait for master in polled functions */
-	uint16_t buffer_timeout;
-	/** Addressing mode */
-	enum i2c_slave_address_mode address_mode;
-	/** Address or upper limit of address range */
-	uint16_t address;
-	/** Address mask, second address, or lower limit of address range */
-	uint16_t address_mask;
+    /** Set to enable the SCL low timeout */
+    bool enable_scl_low_timeout;
+    /** SDA hold time with respect to the negative edge of SCL */
+    enum i2c_slave_sda_hold_time sda_hold_time;
+    /** Timeout to wait for master in polled functions */
+    uint16_t buffer_timeout;
+    /** Addressing mode */
+    enum i2c_slave_address_mode address_mode;
+    /** Address or upper limit of address range */
+    uint16_t address;
+    /** Address mask, second address, or lower limit of address range */
+    uint16_t address_mask;
 #ifdef FEATURE_I2C_10_BIT_ADDRESS
-	/** Enable 10-bit addressing */
-	bool ten_bit_address;
+    /** Enable 10-bit addressing */
+    bool ten_bit_address;
 #endif
-	/**
-	 * Enable general call address recognition (general call address
-	 * is defined as 0000000 with direction bit 0).
-	 */
-	bool enable_general_call_address;
+    /**
+     * Enable general call address recognition (general call address
+     * is defined as 0000000 with direction bit 0).
+     */
+    bool enable_general_call_address;
 
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
-	/** Transfer speed mode */
-	enum i2c_slave_transfer_speed transfer_speed;
+    /** Transfer speed mode */
+    enum i2c_slave_transfer_speed transfer_speed;
 #endif
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/**
-	 * Enable NACK on address match (this can be changed after initialization
-	 * via the \ref i2c_slave_enable_nack_on_address and
-	 * \ref i2c_slave_disable_nack_on_address functions).
-	 */
-	bool enable_nack_on_address;
+    /**
+     * Enable NACK on address match (this can be changed after initialization
+     * via the \ref i2c_slave_enable_nack_on_address and
+     * \ref i2c_slave_disable_nack_on_address functions).
+     */
+    bool enable_nack_on_address;
 #endif
-	/** GCLK generator to use as clock source */
-	enum gclk_generator generator_source;
-	/** Set to keep module active in sleep modes */
-	bool run_in_standby;
-	/** PAD0 (SDA) pinmux */
-	uint32_t pinmux_pad0;
-	/** PAD1 (SCL) pinmux */
-	uint32_t pinmux_pad1;
-	/** Set to enable SCL low time-out */
-	bool scl_low_timeout;
+    /** GCLK generator to use as clock source */
+    enum gclk_generator generator_source;
+    /** Set to keep module active in sleep modes */
+    bool run_in_standby;
+    /** PAD0 (SDA) pinmux */
+    uint32_t pinmux_pad0;
+    /** PAD1 (SCL) pinmux */
+    uint32_t pinmux_pad1;
+    /** Set to enable SCL low time-out */
+    bool scl_low_timeout;
 #ifdef FEATURE_I2C_SCL_STRETCH_MODE
-	/** Set to enable SCL stretch only after ACK bit (required for high speed) */
-	bool scl_stretch_only_after_ack_bit;
+    /** Set to enable SCL stretch only after ACK bit (required for high speed) */
+    bool scl_stretch_only_after_ack_bit;
 #endif
 #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
-	/** Set to enable slave SCL low extend time-out */
-	bool slave_scl_low_extend_timeout;
+    /** Set to enable slave SCL low extend time-out */
+    bool slave_scl_low_extend_timeout;
 #endif
 };
 
@@ -366,22 +366,23 @@ struct i2c_slave_config {
  * \retval STATUS_BUSY If the module was already locked
  */
 static inline enum status_code i2c_slave_lock(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return status;
+    return status;
 }
 
 /**
@@ -397,7 +398,7 @@ static inline enum status_code i2c_slave_lock(
  */
 static inline void i2c_slave_unlock(struct i2c_slave_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /** @} */
@@ -419,19 +420,19 @@ static inline void i2c_slave_unlock(struct i2c_slave_module *const module)
  * \retval false  Module is not synchronizing
  */
 static inline bool i2c_slave_is_syncing(
-		const struct i2c_slave_module *const module)
+        const struct i2c_slave_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
-	/* Return sync status */
+    /* Return sync status */
 #if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
-	return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY);
+    return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY);
 #elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
-	return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK);
+    return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK);
 #else
 #  error Unknown SERCOM SYNCBUSY scheme!
 #endif
@@ -444,18 +445,19 @@ static inline bool i2c_slave_is_syncing(
  * \param[in]  module  Pointer to software module structure
  */
 static void _i2c_slave_wait_for_sync(
-		const struct i2c_slave_module *const module)
+        const struct i2c_slave_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
+    /* Sanity check */
+    Assert(module);
 
-	while (i2c_slave_is_syncing(module)) {
-		/* Wait for I<SUP>2</SUP>C module to sync */
-	}
+    while (i2c_slave_is_syncing(module))
+    {
+        /* Wait for I<SUP>2</SUP>C module to sync */
+    }
 }
 #endif
 
-///@cond INTERNAL
+/*/@cond INTERNAL*/
 /**
  * \internal Workaround for errata 13574
  * Instead set ACK/NACK of CTRLB
@@ -471,37 +473,39 @@ static void _i2c_slave_wait_for_sync(
  * \param[in] send_ack true send ACK, false send NACK
  */
 static inline void _i2c_slave_set_ctrlb_ackact(
-		struct i2c_slave_module *const module,
-		bool send_ack)
+        struct i2c_slave_module *const module,
+        bool send_ack)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAMDA1 ||  \
-		SAML22 || SAMC20 || SAMC21 || SAMHA1 || SAMR30)
-	/* Workaround, Following two write are atomic */
-	system_interrupt_enter_critical_section();
-	i2c_hw->STATUS.reg = 0;
-
-	if (send_ack == true) {
-		i2c_hw->CTRLB.reg = 0;
-	}
-	else {
-		i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
-	}
-	system_interrupt_leave_critical_section();
+        SAML22 || SAMC20 || SAMC21 || SAMHA1 || SAMR30)
+    /* Workaround, Following two write are atomic */
+    system_interrupt_enter_critical_section();
+    i2c_hw->STATUS.reg = 0;
+
+    if (send_ack == true)
+    {
+        i2c_hw->CTRLB.reg = 0;
+    }
+    else {
+        i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
+    }
+    system_interrupt_leave_critical_section();
 #else
-	/* Normal operation */
-	if (send_ack == true) {
-		i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
-	}
-	else {
-		i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
-	}
+    /* Normal operation */
+    if (send_ack == true)
+    {
+        i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
+    }
+    else {
+        i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
+    }
 #endif
-	return;
+    return;
 }
 
 /**
@@ -518,32 +522,33 @@ static inline void _i2c_slave_set_ctrlb_ackact(
  * \param[in,out] module  Pointer to software module structure
  */
 static inline void _i2c_slave_set_ctrlb_cmd3(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	Assert(module);
-	Assert(module->hw);
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAML22 || \
-		SAMDA1 || SAMC20 || SAMC21 || SAMR30 || SAMHA1)
-	/* Workaround */
-	/*
-	 * Below code instead i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
-	 * CMD=0x3 clears all interrupts, so to keep the result similar
-	 * PREC is cleared if it was set
-	 */
-	if (i2c_hw->INTFLAG.bit.PREC) {
-		i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
-	}
-	i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+        SAMDA1 || SAMC20 || SAMC21 || SAMR30 || SAMHA1)
+    /* Workaround */
+    /*
+     * Below code instead i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
+     * CMD=0x3 clears all interrupts, so to keep the result similar
+     * PREC is cleared if it was set
+     */
+    if (i2c_hw->INTFLAG.bit.PREC)
+    {
+        i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC;
+    }
+    i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
 #else
-	/* Normal operation */
-	i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
+    /* Normal operation */
+    i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3);
 #endif
-	return;
+    return;
 }
-///@endcond
+/*/@endcond*/
 
 /**
  * \brief Gets the I<SUP>2</SUP>C slave default configurations
@@ -572,42 +577,42 @@ static inline void _i2c_slave_set_ctrlb_cmd3(
  * \param[out] config  Pointer to configuration structure to be initialized
  */
 static inline void i2c_slave_get_config_defaults(
-		struct i2c_slave_config *const config)
+        struct i2c_slave_config *const config)
 {
-	/*Sanity check argument */
-	Assert(config);
-	config->enable_scl_low_timeout = false;
-	config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS;
-	config->buffer_timeout = 65535;
-	config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK;
-	config->address = 0;
-	config->address_mask = 0;
+    /*Sanity check argument */
+    Assert(config);
+    config->enable_scl_low_timeout = false;
+    config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS;
+    config->buffer_timeout = 65535;
+    config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK;
+    config->address = 0;
+    config->address_mask = 0;
 #ifdef FEATURE_I2C_10_BIT_ADDRESS
-	config->ten_bit_address = false;
+    config->ten_bit_address = false;
 #endif
-	config->enable_general_call_address = false;
+    config->enable_general_call_address = false;
 #ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED
-	config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST;
+    config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST;
 #endif
 #if I2C_SLAVE_CALLBACK_MODE == true
-	config->enable_nack_on_address = false;
+    config->enable_nack_on_address = false;
 #endif
-	config->generator_source = GCLK_GENERATOR_0;
-	config->run_in_standby = false;
-	config->pinmux_pad0 = PINMUX_DEFAULT;
-	config->pinmux_pad1 = PINMUX_DEFAULT;
-	config->scl_low_timeout  = false;
+    config->generator_source = GCLK_GENERATOR_0;
+    config->run_in_standby = false;
+    config->pinmux_pad0 = PINMUX_DEFAULT;
+    config->pinmux_pad1 = PINMUX_DEFAULT;
+    config->scl_low_timeout  = false;
 #ifdef FEATURE_I2C_SCL_STRETCH_MODE
-	config->scl_stretch_only_after_ack_bit = false;
+    config->scl_stretch_only_after_ack_bit = false;
 #endif
 #ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT
-	config->slave_scl_low_extend_timeout   = false;
+    config->slave_scl_low_extend_timeout   = false;
 #endif
 }
 
 enum status_code i2c_slave_init(struct i2c_slave_module *const module,
-		Sercom *const hw,
-		const struct i2c_slave_config *const config);
+        Sercom *const hw,
+        const struct i2c_slave_config *const config);
 
 /**
  * \brief Enables the I<SUP>2</SUP>C module
@@ -617,24 +622,24 @@ enum status_code i2c_slave_init(struct i2c_slave_module *const module,
  * \param[in]  module Pointer to the software module struct
  */
 static inline void i2c_slave_enable(
-		const struct i2c_slave_module *const module)
+        const struct i2c_slave_module *const module)
 {
-	/* Sanity check of arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check of arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Enable global interrupt for module */
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+    /* Enable global interrupt for module */
+    system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
 #endif
 
-	/* Wait for module to sync */
-	_i2c_slave_wait_for_sync(module);
+    /* Wait for module to sync */
+    _i2c_slave_wait_for_sync(module);
 
-	/* Enable module */
-	i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
+    /* Enable module */
+    i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE;
 }
 
 
@@ -647,36 +652,36 @@ static inline void i2c_slave_enable(
  * \param[in]  module  Pointer to the software module struct
  */
 static inline void i2c_slave_disable(
-		const struct i2c_slave_module *const module)
+        const struct i2c_slave_module *const module)
 {
-	/* Sanity check of arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check of arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
 
 #if I2C_SLAVE_CALLBACK_MODE == true
-	/* Disable interrupts */
-	i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC |
-			SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY;
+    /* Disable interrupts */
+    i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC |
+            SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY;
 
-	/* Clear interrupt flags */
-	i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH |
-			SERCOM_I2CS_INTFLAG_DRDY;
+    /* Clear interrupt flags */
+    i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH |
+            SERCOM_I2CS_INTFLAG_DRDY;
 
-	/* Disable global interrupt for module */
-	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+    /* Disable global interrupt for module */
+    system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
 #endif
 
-	/* Wait for module to sync */
-	_i2c_slave_wait_for_sync(module);
+    /* Wait for module to sync */
+    _i2c_slave_wait_for_sync(module);
 
-	/* Disable module */
-	i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
+    /* Disable module */
+    i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE;
 }
 
 void i2c_slave_reset(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 
 /** @} */
 
@@ -686,13 +691,13 @@ void i2c_slave_reset(
  */
 
 enum status_code i2c_slave_write_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 enum status_code i2c_slave_read_packet_wait(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 enum i2c_slave_direction i2c_slave_get_direction_wait(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 
 /** @} */
 
@@ -701,10 +706,10 @@ enum i2c_slave_direction i2c_slave_get_direction_wait(
  * @{
  */
 uint32_t i2c_slave_get_status(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 void i2c_slave_clear_status(
-		struct i2c_slave_module *const module,
-		uint32_t status_flags);
+        struct i2c_slave_module *const module,
+        uint32_t status_flags);
 /** @} */
 
 #ifdef FEATURE_I2C_DMA_SUPPORT
@@ -723,7 +728,7 @@ void i2c_slave_clear_status(
  */
 static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module)
 {
-	return (uint8_t)module->hw->I2CS.INTFLAG.reg;
+    return (uint8_t)module->hw->I2CS.INTFLAG.reg;
 }
 
 /**
@@ -736,9 +741,9 @@ static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_modul
  *
  */
 static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module,
-		uint8_t flag)
+        uint8_t flag)
 {
-	module->hw->I2CS.INTFLAG.reg = flag;
+    module->hw->I2CS.INTFLAG.reg = flag;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h
index cf1c4362c798..3374a66a63d8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h
@@ -65,9 +65,9 @@ extern "C" {
  */
 
 void i2c_slave_enable_nack_on_address(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 void i2c_slave_disable_nack_on_address(
-		struct i2c_slave_module *const module);
+        struct i2c_slave_module *const module);
 
 /** @} */
 
@@ -80,13 +80,13 @@ void _i2c_slave_interrupt_handler(uint8_t instance);
 #endif
 
 void i2c_slave_register_callback(
-		struct i2c_slave_module *const module,
-		i2c_slave_callback_t callback,
-		enum i2c_slave_callback callback_type);
+        struct i2c_slave_module *const module,
+        i2c_slave_callback_t callback,
+        enum i2c_slave_callback callback_type);
 
 void i2c_slave_unregister_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type);
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -97,22 +97,23 @@ void i2c_slave_unregister_callback(
  * \param[in]      callback_type  Callback type to enable
  */
 static inline void i2c_slave_enable_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Mark callback as enabled */
-	module->enabled_callback |= (1 << callback_type);
-
-	/* Enable address callback */
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
-			callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST) {
-		i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-	}
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Mark callback as enabled */
+    module->enabled_callback |= (1 << callback_type);
+
+    /* Enable address callback */
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
+            callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST)
+            {
+        i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+    }
 }
 
 /**
@@ -124,21 +125,22 @@ static inline void i2c_slave_enable_callback(
  * \param[in]      callback_type  Callback type to disable
  */
 static inline void i2c_slave_disable_callback(
-		struct i2c_slave_module *const module,
-		enum i2c_slave_callback callback_type)
+        struct i2c_slave_module *const module,
+        enum i2c_slave_callback callback_type)
 {
-	/* Sanity check */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Mark callback as disabled */
-	module->enabled_callback &= ~(1 << callback_type);
-	SercomI2cs *const i2c_hw = &(module->hw->I2CS);
-	if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
-			callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST ||
-			module->status != STATUS_BUSY) {
-		i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
-	}
+    /* Sanity check */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Mark callback as disabled */
+    module->enabled_callback &= ~(1 << callback_type);
+    SercomI2cs *const i2c_hw = &(module->hw->I2CS);
+    if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST ||
+            callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST ||
+            module->status != STATUS_BUSY)
+            {
+        i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH;
+    }
 }
 
 /** @} */
@@ -150,12 +152,12 @@ static inline void i2c_slave_disable_callback(
 
 
 enum status_code i2c_slave_read_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 
 enum status_code i2c_slave_write_packet_job(
-		struct i2c_slave_module *const module,
-		struct i2c_slave_packet *const packet);
+        struct i2c_slave_module *const module,
+        struct i2c_slave_packet *const packet);
 
 /**
  * \brief Cancels any currently ongoing operation
@@ -165,15 +167,15 @@ enum status_code i2c_slave_write_packet_job(
  * \param[in,out] module  Pointer to software module structure
  */
 static inline void i2c_slave_cancel_job(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Sanity check. */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Set buffer to 0. */
-	module->buffer_remaining = 0;
-	module->buffer_length = 0;
+    /* Set buffer to 0. */
+    module->buffer_remaining = 0;
+    module->buffer_length = 0;
 }
 
 /**
@@ -194,14 +196,14 @@ static inline void i2c_slave_cancel_job(
  * \retval STATUS_ERR_OVERFLOW  Data from master overflows receive buffer
  */
 static inline enum status_code i2c_slave_get_job_status(
-		struct i2c_slave_module *const module)
+        struct i2c_slave_module *const module)
 {
-	/* Check sanity. */
-	Assert(module);
-	Assert(module->hw);
+    /* Check sanity. */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Return current status code. */
-	return module->status;
+    /* Return current status code. */
+    return module->status;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c
index 270973a7db6f..1535e1853d4e 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.c
@@ -54,10 +54,10 @@
  * \internal Configuration structure to save current gclk status.
  */
 struct _sercom_conf {
-	/* Status of gclk generator initialization */
-	bool generator_is_set;
-	/* Sercom gclk generator used */
-	enum gclk_generator generator_source;
+    /* Status of gclk generator initialization */
+    bool generator_is_set;
+    /* Sercom gclk generator used */
+    enum gclk_generator generator_source;
 };
 
 static struct _sercom_conf _sercom_config;
@@ -69,107 +69,117 @@ static struct _sercom_conf _sercom_config;
  */
 static uint64_t long_division(uint64_t n, uint64_t d)
 {
-	int32_t i;
-	uint64_t q = 0, r = 0, bit_shift;
-	for (i = 63; i >= 0; i--) {
-		bit_shift = (uint64_t)1 << i;
+    int32_t i;
+    uint64_t q = 0, r = 0, bit_shift;
+    for (i = 63; i >= 0; i--)
+    {
+        bit_shift = (uint64_t)1 << i;
 
-		r = r << 1;
+        r = r << 1;
 
-		if (n & bit_shift) {
-			r |= 0x01;
-		}
+        if (n & bit_shift)
+        {
+            r |= 0x01;
+        }
 
-		if (r >= d) {
-			r = r - d;
-			q |= bit_shift;
-		}
-	}
+        if (r >= d)
+        {
+            r = r - d;
+            q |= bit_shift;
+        }
+    }
 
-	return q;
+    return q;
 }
 
 /**
  * \internal Calculate synchronous baudrate value (SPI/UART)
  */
 enum status_code _sercom_get_sync_baud_val(
-		const uint32_t baudrate,
-		const uint32_t external_clock,
-		uint16_t *const baudvalue)
+        const uint32_t baudrate,
+        const uint32_t external_clock,
+        uint16_t *const baudvalue)
 {
-	/* Baud value variable */
-	uint16_t baud_calculated = 0;
-	uint32_t clock_value = external_clock;
+    /* Baud value variable */
+    uint16_t baud_calculated = 0;
+    uint32_t clock_value = external_clock;
 
 
-	/* Check if baudrate is outside of valid range */
-	if (baudrate > (external_clock / 2)) {
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	}
+    /* Check if baudrate is outside of valid range */
+    if (baudrate > (external_clock / 2))
+    {
+        /* Return with error code */
+        return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+    }
 
-	/* Calculate BAUD value from clock frequency and baudrate */
-	clock_value = external_clock / 2;
-	while (clock_value >= baudrate) {
-		clock_value = clock_value - baudrate;
-		baud_calculated++;
-	}
-	baud_calculated = baud_calculated - 1;
+    /* Calculate BAUD value from clock frequency and baudrate */
+    clock_value = external_clock / 2;
+    while (clock_value >= baudrate)
+    {
+        clock_value = clock_value - baudrate;
+        baud_calculated++;
+    }
+    baud_calculated = baud_calculated - 1;
 
-	/* Check if BAUD value is more than 255, which is maximum
-	 * for synchronous mode */
-	if (baud_calculated > 0xFF) {
-		/* Return with an error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	} else {
-		*baudvalue = baud_calculated;
-		return STATUS_OK;
-	}
+    /* Check if BAUD value is more than 255, which is maximum
+     * for synchronous mode */
+    if (baud_calculated > 0xFF)
+    {
+        /* Return with an error code */
+        return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+    } else {
+        *baudvalue = baud_calculated;
+        return STATUS_OK;
+    }
 }
 
 /**
  * \internal Calculate asynchronous baudrate value (UART)
 */
 enum status_code _sercom_get_async_baud_val(
-		const uint32_t baudrate,
-		const uint32_t peripheral_clock,
-		uint16_t *const baudval,
-		enum sercom_asynchronous_operation_mode mode,
-		enum sercom_asynchronous_sample_num sample_num)
+        const uint32_t baudrate,
+        const uint32_t peripheral_clock,
+        uint16_t *const baudval,
+        enum sercom_asynchronous_operation_mode mode,
+        enum sercom_asynchronous_sample_num sample_num)
 {
-	/* Temporary variables  */
-	uint64_t ratio = 0;
-	uint64_t scale = 0;
-	uint64_t baud_calculated = 0;
-	uint8_t baud_fp;
-	uint32_t baud_int = 0;
-	uint64_t temp1;
+    /* Temporary variables  */
+    uint64_t ratio = 0;
+    uint64_t scale = 0;
+    uint64_t baud_calculated = 0;
+    uint8_t baud_fp;
+    uint32_t baud_int = 0;
+    uint64_t temp1;
 
-	/* Check if the baudrate is outside of valid range */
-	if ((baudrate * sample_num) > peripheral_clock) {
-		/* Return with error code */
-		return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-	}
+    /* Check if the baudrate is outside of valid range */
+    if ((baudrate * sample_num) > peripheral_clock)
+    {
+        /* Return with error code */
+        return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+    }
 
-	if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) {
-		/* Calculate the BAUD value */
-		temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
-		ratio = long_division(temp1, peripheral_clock);
-		scale = ((uint64_t)1 << SHIFT) - ratio;
-		baud_calculated = (65536 * scale) >> SHIFT;
-	} else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) {
-		temp1 = ((uint64_t)baudrate * sample_num);
-		baud_int = long_division( peripheral_clock, temp1);
-		if(baud_int > BAUD_INT_MAX) {
-				return STATUS_ERR_BAUDRATE_UNAVAILABLE;
-		}
-		temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
-		baud_fp = temp1 - 8 * baud_int;
-		baud_calculated = baud_int | (baud_fp << 13);
-	}
+    if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC)
+    {
+        /* Calculate the BAUD value */
+        temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT);
+        ratio = long_division(temp1, peripheral_clock);
+        scale = ((uint64_t)1 << SHIFT) - ratio;
+        baud_calculated = (65536 * scale) >> SHIFT;
+    } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL)
+    {
+        temp1 = ((uint64_t)baudrate * sample_num);
+        baud_int = long_division( peripheral_clock, temp1);
+        if(baud_int > BAUD_INT_MAX)
+        {
+                return STATUS_ERR_BAUDRATE_UNAVAILABLE;
+        }
+        temp1 = long_division( 8 * (uint64_t)peripheral_clock, temp1);
+        baud_fp = temp1 - 8 * baud_int;
+        baud_calculated = baud_int | (baud_fp << 13);
+    }
 
-	*baudval = baud_calculated;
-	return STATUS_OK;
+    *baudval = baud_calculated;
+    return STATUS_OK;
 }
 #endif
 
@@ -194,30 +204,32 @@ enum status_code _sercom_get_async_baud_val(
  *                                         forced.
  */
 enum status_code sercom_set_gclk_generator(
-		const enum gclk_generator generator_source,
-		const bool force_change)
+        const enum gclk_generator generator_source,
+        const bool force_change)
 {
-	/* Check if valid option */
-	if (!_sercom_config.generator_is_set || force_change) {
-		/* Create and fill a GCLK configuration structure for the new config */
-		struct system_gclk_chan_config gclk_chan_conf;
-		system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-		gclk_chan_conf.source_generator = generator_source;
-		system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
-		system_gclk_chan_enable(SERCOM_GCLK_ID);
+    /* Check if valid option */
+    if (!_sercom_config.generator_is_set || force_change)
+    {
+        /* Create and fill a GCLK configuration structure for the new config */
+        struct system_gclk_chan_config gclk_chan_conf;
+        system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+        gclk_chan_conf.source_generator = generator_source;
+        system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf);
+        system_gclk_chan_enable(SERCOM_GCLK_ID);
 
-		/* Save config */
-		_sercom_config.generator_source = generator_source;
-		_sercom_config.generator_is_set = true;
+        /* Save config */
+        _sercom_config.generator_source = generator_source;
+        _sercom_config.generator_is_set = true;
 
-		return STATUS_OK;
-	} else if (generator_source == _sercom_config.generator_source) {
-		/* Return status OK if same config */
-		return STATUS_OK;
-	}
+        return STATUS_OK;
+    } else if (generator_source == _sercom_config.generator_source)
+    {
+        /* Return status OK if same config */
+        return STATUS_OK;
+    }
 
-	/* Return invalid config to already initialized GCLK */
-	return STATUS_ERR_ALREADY_INITIALIZED;
+    /* Return invalid config to already initialized GCLK */
+    return STATUS_ERR_ALREADY_INITIALIZED;
 }
 
 /** \internal
@@ -225,18 +237,19 @@ enum status_code sercom_set_gclk_generator(
  * index to the default SERCOM pad MUX setting.
  */
 #define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \
-		case (uintptr_t)SERCOM##n: \
-			switch (pad) { \
-				case 0: \
-					return SERCOM##n##_PAD0_DEFAULT; \
-				case 1: \
-					return SERCOM##n##_PAD1_DEFAULT; \
-				case 2: \
-					return SERCOM##n##_PAD2_DEFAULT; \
-				case 3: \
-					return SERCOM##n##_PAD3_DEFAULT; \
-			} \
-			break;
+        case (uintptr_t)SERCOM##n: \
+            switch (pad)
+            { \
+                case 0: \
+                    return SERCOM##n##_PAD0_DEFAULT; \
+                case 1: \
+                    return SERCOM##n##_PAD1_DEFAULT; \
+                case 2: \
+                    return SERCOM##n##_PAD2_DEFAULT; \
+                case 3: \
+                    return SERCOM##n##_PAD3_DEFAULT; \
+            } \
+            break;
 
 /**
  * \internal Gets the default PAD pinout for a given SERCOM.
@@ -251,16 +264,17 @@ enum status_code sercom_set_gclk_generator(
  *
  */
 uint32_t _sercom_get_default_pad(
-		Sercom *const sercom_module,
-		const uint8_t pad)
+        Sercom *const sercom_module,
+        const uint8_t pad)
 {
-	switch ((uintptr_t)sercom_module) {
-		/* Auto-generate a lookup table for the default SERCOM pad defaults */
-		MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
-	}
+    switch ((uintptr_t)sercom_module)
+    {
+        /* Auto-generate a lookup table for the default SERCOM pad defaults */
+        MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad)
+    }
 
-	Assert(false);
-	return 0;
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -272,19 +286,21 @@ uint32_t _sercom_get_default_pad(
  * \return Index of given instance.
  */
 uint8_t _sercom_get_sercom_inst_index(
-		Sercom *const sercom_instance)
+        Sercom *const sercom_instance)
 {
-	/* Save all available SERCOM instances for compare */
-	Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
+    /* Save all available SERCOM instances for compare */
+    Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS;
 
-	/* Find index for sercom instance */
-	for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-		if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) {
-			return i;
-		}
-	}
+    /* Find index for sercom instance */
+    for (uint32_t i = 0; i < SERCOM_INST_NUM; i++)
+    {
+        if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i])
+        {
+            return i;
+        }
+    }
 
-	/* Invalid data given */
-	Assert(false);
-	return 0;
+    /* Invalid data given */
+    Assert(false);
+    return 0;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h
index 60ce6f8ad103..637d378d506d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom.h
@@ -74,8 +74,8 @@ extern "C" {
  * Select sercom asynchronous operation mode
  */
 enum sercom_asynchronous_operation_mode {
-	SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
-	SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
+    SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0,
+    SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL,
 };
 
 /**
@@ -84,35 +84,35 @@ enum sercom_asynchronous_operation_mode {
  * Select number of samples per bit
  */
 enum sercom_asynchronous_sample_num {
-	SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
-	SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
-	SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
+    SERCOM_ASYNC_SAMPLE_NUM_3 = 3,
+    SERCOM_ASYNC_SAMPLE_NUM_8 = 8,
+    SERCOM_ASYNC_SAMPLE_NUM_16 = 16,
 };
 
 enum status_code sercom_set_gclk_generator(
-		const enum gclk_generator generator_source,
-		const bool force_change);
+        const enum gclk_generator generator_source,
+        const bool force_change);
 
 enum status_code _sercom_get_sync_baud_val(
-		const uint32_t baudrate,
-		const uint32_t external_clock,
-		uint16_t *const baudval);
+        const uint32_t baudrate,
+        const uint32_t external_clock,
+        uint16_t *const baudval);
 
 enum status_code _sercom_get_async_baud_val(
-		const uint32_t baudrate,
-		const uint32_t peripheral_clock,
-		uint16_t *const baudval,
-		enum sercom_asynchronous_operation_mode mode,
-		enum sercom_asynchronous_sample_num sample_num);
+        const uint32_t baudrate,
+        const uint32_t peripheral_clock,
+        uint16_t *const baudval,
+        enum sercom_asynchronous_operation_mode mode,
+        enum sercom_asynchronous_sample_num sample_num);
 
 uint32_t _sercom_get_default_pad(
-		Sercom *const sercom_module,
-		const uint8_t pad);
+        Sercom *const sercom_module,
+        const uint8_t pad);
 
 uint8_t _sercom_get_sercom_inst_index(
-		Sercom *const sercom_instance);
+        Sercom *const sercom_instance);
 #ifdef __cplusplus
 }
 #endif
 
-#endif //__SERCOM_H_INCLUDED
+#endif /*__SERCOM_H_INCLUDED*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c
index b26d05b6e74a..2b145aa6f5d0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.c
@@ -60,9 +60,9 @@ static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instanc
  * \param[in] instance SERCOM instance used.
  */
 static void _sercom_default_handler(
-		const uint8_t instance)
+        const uint8_t instance)
 {
-	Assert(false);
+    Assert(false);
 }
 
 /**
@@ -73,21 +73,23 @@ static void _sercom_default_handler(
  * \param[in]  interrupt_handler  Pointer to instance callback handler.
  */
 void _sercom_set_handler(
-		const uint8_t instance,
-		const sercom_handler_t interrupt_handler)
+        const uint8_t instance,
+        const sercom_handler_t interrupt_handler)
 {
-	/* Initialize handlers with default handler and device instances with 0 */
-	if (_handler_table_initialized == false) {
-		for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) {
-			_sercom_interrupt_handlers[i] = &_sercom_default_handler;
-			_sercom_instances[i] = NULL;
-		}
+    /* Initialize handlers with default handler and device instances with 0 */
+    if (_handler_table_initialized == false)
+    {
+        for (uint32_t i = 0; i < SERCOM_INST_NUM; i++)
+        {
+            _sercom_interrupt_handlers[i] = &_sercom_default_handler;
+            _sercom_instances[i] = NULL;
+        }
 
-		_handler_table_initialized = true;
-	}
+        _handler_table_initialized = true;
+    }
 
-	/* Save interrupt handler */
-	_sercom_interrupt_handlers[instance] = interrupt_handler;
+    /* Save interrupt handler */
+    _sercom_interrupt_handlers[instance] = interrupt_handler;
 }
 
 
@@ -95,16 +97,16 @@ void _sercom_set_handler(
  * Converts a given SERCOM index to its interrupt vector index.
  */
 #define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \
-		SYSTEM_INTERRUPT_MODULE_SERCOM##n,
+        SYSTEM_INTERRUPT_MODULE_SERCOM##n,
 
 /** \internal
  * Generates a SERCOM interrupt handler function for a given SERCOM index.
  */
 #define _SERCOM_INTERRUPT_HANDLER(n, unused) \
-		void SERCOM##n##_Handler(void) \
-		{ \
-			_sercom_interrupt_handlers[n](n); \
-		}
+        void SERCOM##n##_Handler(void) \
+        { \
+            _sercom_interrupt_handlers[n](n); \
+        }
 
 /**
  * \internal
@@ -123,18 +125,18 @@ void _sercom_set_handler(
  * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7
  */
 enum system_interrupt_vector _sercom_get_interrupt_vector(
-		Sercom *const sercom_instance)
+        Sercom *const sercom_instance)
 {
-	const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
-		{
-			MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
-		};
+    const uint8_t sercom_int_vectors[SERCOM_INST_NUM] =
+        {
+            MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~)
+        };
 
-	/* Retrieve the index of the SERCOM being requested */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
+    /* Retrieve the index of the SERCOM being requested */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance);
 
-	/* Get the vector number from the lookup table for the requested SERCOM */
-	return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
+    /* Get the vector number from the lookup table for the requested SERCOM */
+    return (enum system_interrupt_vector)sercom_int_vectors[instance_index];
 }
 
 /** Auto-generate a set of interrupt handlers for each SERCOM in the device */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h
index 18945f5186cc..531d6ebee772 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_interrupt.h
@@ -59,11 +59,11 @@ extern void *_sercom_instances[SERCOM_INST_NUM];
 typedef void (*sercom_handler_t)(uint8_t instance);
 
 enum system_interrupt_vector _sercom_get_interrupt_vector(
-		Sercom *const sercom_instance);
+        Sercom *const sercom_instance);
 
 void _sercom_set_handler(
-		const uint8_t instance,
-		const sercom_handler_t interrupt_handler);
+        const uint8_t instance,
+        const sercom_handler_t interrupt_handler);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h
index fdbc5405e22a..e1f401ab2581 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/sercom_pinout.h
@@ -49,497 +49,497 @@
 #include <compiler.h>
 
 #if SAMR21E
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+    /* SERCOM3 */
 # if SAM_PART_IS_DEFINED(SAMR21E19A)
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
 # else
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA27F_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA28F_SERCOM3_PAD1
 #endif
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
 
-	/* SERCOM4 */
+    /* SERCOM4 */
 # if SAM_PART_IS_DEFINED(SAMR21E19A)
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
 # else
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
 # endif
 
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
 
 #elif SAMR21G
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PC19F_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PB31F_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PB30F_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PC18F_SERCOM4_PAD3
+
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
 
 #elif (SAMD09)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
-
-#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) 
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+
+#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU)
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA22C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA23C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA16D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA25D_SERCOM2_PAD3
 
 #elif (SAMD10C) || (SAMD11C)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA08D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA09D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA30C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA31C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA24C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA25C_SERCOM1_PAD3
 
 #elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L)
 
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
 
 #elif (SAML22N)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PB02C_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PB21C_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PB00C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PB01C_SERCOM3_PAD3
+
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PA12C_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PA13C_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14C_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15C_SERCOM4_PAD3
+
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PB30D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PB31D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
 #elif (SAML22J) || (SAML22G)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA08C_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA09C_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA22D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA23D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA20D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA21D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA12D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA13D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA14D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA15D_SERCOM3_PAD3
 #elif (SAMC20E) || (SAMC21E)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
 
 #elif (SAMC20G) || (SAMC21G)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
 
   #ifdef ID_SERCOM4
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
   #endif
 
   #ifdef ID_SERCOM5
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PB22D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PB23D_SERCOM5_PAD3
   #endif
 
 #elif (SAMC20J) || (SAMC21J)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA12C_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA13C_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA22C_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA23C_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA24C_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA25C_SERCOM3_PAD3
 
   #ifdef ID_SERCOM4
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PB08D_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PB09D_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
   #endif
 
   #ifdef ID_SERCOM5
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PB02D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PB03D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PB00D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PB01D_SERCOM5_PAD3
   #endif
 
 #elif (SAMDA1)
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
 
   #if (SAMDA1E)
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
   #else
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
   #endif
 
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
 
 #elif   SAM_PART_IS_DEFINED(SAMHA1G14A) || SAM_PART_IS_DEFINED(SAMHA1G15A) || \
-	SAM_PART_IS_DEFINED(SAMHA1G16A)
-	
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
-
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
+    SAM_PART_IS_DEFINED(SAMHA1G16A)
+
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA10C_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA11C_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA14C_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA15C_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PB10D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PB11D_SERCOM4_PAD3
+
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PB16C_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PB17C_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA20C_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA21C_SERCOM5_PAD3
 
 #elif (SAML21E) || (SAMR30E)
 
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
-
-	/* SERCOM1 */
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
-
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
-
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+
+    /* SERCOM1 */
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
 
   #if !SAM_PART_IS_DEFINED(SAML21E18A) && !SAM_PART_IS_DEFINED(SAMR30E18A)
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD1_DEFAULT      0 /* No available pin */
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
   #endif
 
 #else
-	/* SERCOM0 */
-	#define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
-	#define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
-	#define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
-	#define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
+    /* SERCOM0 */
+    #define SERCOM0_PAD0_DEFAULT      PINMUX_PA04D_SERCOM0_PAD0
+    #define SERCOM0_PAD1_DEFAULT      PINMUX_PA05D_SERCOM0_PAD1
+    #define SERCOM0_PAD2_DEFAULT      PINMUX_PA06D_SERCOM0_PAD2
+    #define SERCOM0_PAD3_DEFAULT      PINMUX_PA07D_SERCOM0_PAD3
 
-	/* SERCOM1 */
+    /* SERCOM1 */
 #if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L)
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA16C_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA17C_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA18C_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA19C_SERCOM1_PAD3
 #else
-	#define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
-	#define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
-	#define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
-	#define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
+    #define SERCOM1_PAD0_DEFAULT      PINMUX_PA00D_SERCOM1_PAD0
+    #define SERCOM1_PAD1_DEFAULT      PINMUX_PA01D_SERCOM1_PAD1
+    #define SERCOM1_PAD2_DEFAULT      PINMUX_PA30D_SERCOM1_PAD2
+    #define SERCOM1_PAD3_DEFAULT      PINMUX_PA31D_SERCOM1_PAD3
 #endif
 
-	/* SERCOM2 */
-	#define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
-	#define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
-	#define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
-	#define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
+    /* SERCOM2 */
+    #define SERCOM2_PAD0_DEFAULT      PINMUX_PA08D_SERCOM2_PAD0
+    #define SERCOM2_PAD1_DEFAULT      PINMUX_PA09D_SERCOM2_PAD1
+    #define SERCOM2_PAD2_DEFAULT      PINMUX_PA10D_SERCOM2_PAD2
+    #define SERCOM2_PAD3_DEFAULT      PINMUX_PA11D_SERCOM2_PAD3
 
-	/* SERCOM3 */
-	#define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
-	#define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
-	#define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
-	#define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
+    /* SERCOM3 */
+    #define SERCOM3_PAD0_DEFAULT      PINMUX_PA16D_SERCOM3_PAD0
+    #define SERCOM3_PAD1_DEFAULT      PINMUX_PA17D_SERCOM3_PAD1
+    #define SERCOM3_PAD2_DEFAULT      PINMUX_PA18D_SERCOM3_PAD2
+    #define SERCOM3_PAD3_DEFAULT      PINMUX_PA19D_SERCOM3_PAD3
 
   #if !(SAMD20E || SAMD21E)
-	/* SERCOM4 */
-	#define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
-	#define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
-	#define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
-	#define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
-
-	/* SERCOM5 */
-	#define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
-	#define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
-	#define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
-	#define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
+    /* SERCOM4 */
+    #define SERCOM4_PAD0_DEFAULT      PINMUX_PA12D_SERCOM4_PAD0
+    #define SERCOM4_PAD1_DEFAULT      PINMUX_PA13D_SERCOM4_PAD1
+    #define SERCOM4_PAD2_DEFAULT      PINMUX_PA14D_SERCOM4_PAD2
+    #define SERCOM4_PAD3_DEFAULT      PINMUX_PA15D_SERCOM4_PAD3
+
+    /* SERCOM5 */
+    #define SERCOM5_PAD0_DEFAULT      PINMUX_PA22D_SERCOM5_PAD0
+    #define SERCOM5_PAD1_DEFAULT      PINMUX_PA23D_SERCOM5_PAD1
+    #define SERCOM5_PAD2_DEFAULT      PINMUX_PA24D_SERCOM5_PAD2
+    #define SERCOM5_PAD3_DEFAULT      PINMUX_PA25D_SERCOM5_PAD3
   #endif
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c
index c0b4acb4a0f5..9f6ae56fcd90 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.c
@@ -54,23 +54,24 @@
  * \param[in,out] module Pointer to the software instance struct
  */
 void spi_reset(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Disable the module */
-	spi_disable(module);
+    /* Disable the module */
+    spi_disable(module);
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Software reset the module */
-	spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+    /* Software reset the module */
+    spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
 }
 
 /**
@@ -86,54 +87,58 @@ void spi_reset(
  * \retval STATUS_OK               If the configuration was written
  */
 enum status_code spi_set_baudrate(
-		struct spi_module *const module,
-		uint32_t baudrate)
+        struct spi_module *const module,
+        uint32_t baudrate)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(baudrate);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(baudrate);
+    Assert(module->hw);
 
-	/* Value to write to BAUD register */
-	uint16_t baud = 0;
+    /* Value to write to BAUD register */
+    uint16_t baud = 0;
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Disable the module */
-	spi_disable(module);
+    /* Disable the module */
+    spi_disable(module);
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+    /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
 
-	/* Get baud value, based on baudrate and the internal clock frequency */
-	enum status_code error_code = _sercom_get_sync_baud_val(
-			baudrate, internal_clock, &baud);
+    /* Get baud value, based on baudrate and the internal clock frequency */
+    enum status_code error_code = _sercom_get_sync_baud_val(
+            baudrate, internal_clock, &baud);
 
-	if (error_code != STATUS_OK) {
-		/* Baud rate calculation error, return status code */
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (error_code != STATUS_OK)
+    {
+        /* Baud rate calculation error, return status code */
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	spi_module->BAUD.reg = (uint8_t)baud;
+    spi_module->BAUD.reg = (uint8_t)baud;
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Enable the module */
-	spi_enable(module);
+    /* Enable the module */
+    spi_enable(module);
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 #  if CONF_SPI_SLAVE_ENABLE == true
@@ -143,16 +148,16 @@ enum status_code spi_set_baudrate(
  * \param[in]  module  Pointer to the software instance struct
  */
 static void _spi_clear_tx_complete_flag(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Clear interrupt flag */
-	spi_module->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+    /* Clear interrupt flag */
+    spi_module->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
 }
 #  endif
 
@@ -170,139 +175,151 @@ static void _spi_clear_tx_complete_flag(
  * \retval STATUS_OK               If the configuration was written
  */
 static enum status_code _spi_set_config(
-		struct spi_module *const module,
-		const struct spi_config *const config)
+        struct spi_module *const module,
+        const struct spi_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(config);
-	Assert(module->hw);
-
-	SercomSpi *const spi_module = &(module->hw->SPI);
-	Sercom *const hw = module->hw;
-
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	if(config->mode == SPI_MODE_SLAVE) {
-		pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
-	}
-
-	uint32_t pad_pinmuxes[] = {
-			config->pinmux_pad0, config->pinmux_pad1,
-			config->pinmux_pad2, config->pinmux_pad3
-		};
-
-	/* Configure the SERCOM pins according to the user configuration */
-	for (uint8_t pad = 0; pad < 4; pad++) {
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-
-		if (current_pinmux == PINMUX_DEFAULT) {
-			current_pinmux = _sercom_get_default_pad(hw, pad);
-		}
-
-		if (current_pinmux != PINMUX_UNUSED) {
-			pin_conf.mux_position = current_pinmux & 0xFFFF;
-			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
-		}
-	}
-
-	module->mode             = config->mode;
-	module->character_size   = config->character_size;
-	module->receiver_enabled = config->receiver_enable;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(config);
+    Assert(module->hw);
+
+    SercomSpi *const spi_module = &(module->hw->SPI);
+    Sercom *const hw = module->hw;
+
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+    pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    if(config->mode == SPI_MODE_SLAVE)
+    {
+        pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+    }
+
+    uint32_t pad_pinmuxes[] = {
+            config->pinmux_pad0, config->pinmux_pad1,
+            config->pinmux_pad2, config->pinmux_pad3
+        };
+
+    /* Configure the SERCOM pins according to the user configuration */
+    for (uint8_t pad = 0; pad < 4; pad++)
+    {
+        uint32_t current_pinmux = pad_pinmuxes[pad];
+
+        if (current_pinmux == PINMUX_DEFAULT)
+        {
+            current_pinmux = _sercom_get_default_pad(hw, pad);
+        }
+
+        if (current_pinmux != PINMUX_UNUSED)
+        {
+            pin_conf.mux_position = current_pinmux & 0xFFFF;
+            system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+        }
+    }
+
+    module->mode             = config->mode;
+    module->character_size   = config->character_size;
+    module->receiver_enabled = config->receiver_enable;
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	module->master_slave_select_enable = config->master_slave_select_enable;
+    module->master_slave_select_enable = config->master_slave_select_enable;
 #  endif
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	/* Value to write to BAUD register */
-	uint16_t baud = 0;
+    /* Value to write to BAUD register */
+    uint16_t baud = 0;
 #  endif
-	/* Value to write to CTRLA register */
-	uint32_t ctrla = 0;
-	/* Value to write to CTRLB register */
-	uint32_t ctrlb = 0;
+    /* Value to write to CTRLA register */
+    uint32_t ctrla = 0;
+    /* Value to write to CTRLB register */
+    uint32_t ctrlb = 0;
 
 # if CONF_SPI_MASTER_ENABLE == true
-	/* Find baud value and write it */
-	if (config->mode == SPI_MODE_MASTER) {
-		/* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
-		uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-		uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-		uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
-
-		/* Get baud value, based on baudrate and the internal clock frequency */
-		enum status_code error_code = _sercom_get_sync_baud_val(
-				config->mode_specific.master.baudrate,
-				internal_clock, &baud);
-
-		if (error_code != STATUS_OK) {
-			/* Baud rate calculation error, return status code */
-			return STATUS_ERR_INVALID_ARG;
-		}
-
-		spi_module->BAUD.reg = (uint8_t)baud;
-	}
+    /* Find baud value and write it */
+    if (config->mode == SPI_MODE_MASTER)
+    {
+        /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */
+        uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+        uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+        uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index);
+
+        /* Get baud value, based on baudrate and the internal clock frequency */
+        enum status_code error_code = _sercom_get_sync_baud_val(
+                config->mode_specific.master.baudrate,
+                internal_clock, &baud);
+
+        if (error_code != STATUS_OK)
+        {
+            /* Baud rate calculation error, return status code */
+            return STATUS_ERR_INVALID_ARG;
+        }
+
+        spi_module->BAUD.reg = (uint8_t)baud;
+    }
 # endif
 # if CONF_SPI_SLAVE_ENABLE == true
-	if (config->mode == SPI_MODE_SLAVE) {
-		/* Set frame format */
-		ctrla = config->mode_specific.slave.frame_format;
-
-		/* Set address mode */
-		ctrlb = config->mode_specific.slave.address_mode;
-
-		/* Set address and address mask*/
-		spi_module->ADDR.reg |=
-				(config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
-				(config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
-
-		if (config->mode_specific.slave.preload_enable) {
-			/* Enable pre-loading of shift register */
-			ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
-		}
-	}
+    if (config->mode == SPI_MODE_SLAVE)
+    {
+        /* Set frame format */
+        ctrla = config->mode_specific.slave.frame_format;
+
+        /* Set address mode */
+        ctrlb = config->mode_specific.slave.address_mode;
+
+        /* Set address and address mask*/
+        spi_module->ADDR.reg |=
+                (config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
+                (config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
+
+        if (config->mode_specific.slave.preload_enable)
+        {
+            /* Enable pre-loading of shift register */
+            ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
+        }
+    }
 # endif
-	/* Set data order */
-	ctrla |= config->data_order;
+    /* Set data order */
+    ctrla |= config->data_order;
 
-	/* Set clock polarity and clock phase */
-	ctrla |= config->transfer_mode;
+    /* Set clock polarity and clock phase */
+    ctrla |= config->transfer_mode;
 
-	/* Set MUX setting */
-	ctrla |= config->mux_setting;
+    /* Set MUX setting */
+    ctrla |= config->mux_setting;
 
-	/* Set SPI character size */
-	ctrlb |= config->character_size;
+    /* Set SPI character size */
+    ctrlb |= config->character_size;
 
-	/* Set whether module should run in standby. */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
-	}
+    /* Set whether module should run in standby. */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
+    }
 
-	if (config->receiver_enable) {
-		/* Enable receiver */
-		ctrlb |= SERCOM_SPI_CTRLB_RXEN;
-	}
+    if (config->receiver_enable)
+    {
+        /* Enable receiver */
+        ctrlb |= SERCOM_SPI_CTRLB_RXEN;
+    }
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	if (config->select_slave_low_detect_enable) {
-		/* Enable Slave Select Low Detect */
-		ctrlb |= SERCOM_SPI_CTRLB_SSDE;
-	}
+    if (config->select_slave_low_detect_enable)
+    {
+        /* Enable Slave Select Low Detect */
+        ctrlb |= SERCOM_SPI_CTRLB_SSDE;
+    }
 #  endif
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	if (config->master_slave_select_enable) {
-		/* Enable Master Slave Select */
-		ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
-	}
+    if (config->master_slave_select_enable)
+    {
+        /* Enable Master Slave Select */
+        ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
+    }
 #  endif
-	/* Write CTRLA register */
-	spi_module->CTRLA.reg |= ctrla;
+    /* Write CTRLA register */
+    spi_module->CTRLA.reg |= ctrla;
 
-	/* Write CTRLB register */
-	spi_module->CTRLB.reg |= ctrlb;
+    /* Write CTRLB register */
+    spi_module->CTRLB.reg |= ctrlb;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 #if SPI_CALLBACK_MODE == false
@@ -322,145 +339,160 @@ static enum status_code _spi_set_config(
  * \retval STATUS_OK               If the configuration was written
  */
 static enum status_code _spi_check_config(
-		struct spi_module *const module,
-		const struct spi_config *const config)
+        struct spi_module *const module,
+        const struct spi_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(config);
-	Assert(module->hw);
-
-	SercomSpi *const spi_module = &(module->hw->SPI);
-	Sercom *const hw = module->hw;
-
-	uint32_t pad_pinmuxes[] = {
-		config->pinmux_pad0, config->pinmux_pad1,
-		config->pinmux_pad2, config->pinmux_pad3
-	};
-
-	/* Compare the current SERCOM pins against the user configuration */
-	for (uint8_t pad = 0; pad < 4; pad++) {
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-
-		if (current_pinmux == PINMUX_DEFAULT) {
-			current_pinmux = _sercom_get_default_pad(hw, pad);
-		}
-
-		if (current_pinmux == PINMUX_UNUSED) {
-			continue;
-		}
-
-		if ((current_pinmux & 0xFFFF) !=
-				system_pinmux_pin_get_mux_position(current_pinmux >> 16)) {
-			module->hw = NULL;
-			return STATUS_ERR_DENIED;
-		}
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(config);
+    Assert(module->hw);
+
+    SercomSpi *const spi_module = &(module->hw->SPI);
+    Sercom *const hw = module->hw;
+
+    uint32_t pad_pinmuxes[] = {
+        config->pinmux_pad0, config->pinmux_pad1,
+        config->pinmux_pad2, config->pinmux_pad3
+    };
+
+    /* Compare the current SERCOM pins against the user configuration */
+    for (uint8_t pad = 0; pad < 4; pad++)
+    {
+        uint32_t current_pinmux = pad_pinmuxes[pad];
+
+        if (current_pinmux == PINMUX_DEFAULT)
+        {
+            current_pinmux = _sercom_get_default_pad(hw, pad);
+        }
+
+        if (current_pinmux == PINMUX_UNUSED)
+        {
+            continue;
+        }
+
+        if ((current_pinmux & 0xFFFF) !=
+                system_pinmux_pin_get_mux_position(current_pinmux >> 16))
+                {
+            module->hw = NULL;
+            return STATUS_ERR_DENIED;
+        }
+    }
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	/* Value to read BAUD register */
-	uint16_t baud;
-	uint32_t external_clock = system_gclk_chan_get_hz(SERCOM_GCLK_ID);
+    /* Value to read BAUD register */
+    uint16_t baud;
+    uint32_t external_clock = system_gclk_chan_get_hz(SERCOM_GCLK_ID);
 #  endif
-	/* Value to read CTRLA, CTRLB and ADDR register */
-	uint32_t ctrla = 0;
-	uint32_t ctrlb = 0;
+    /* Value to read CTRLA, CTRLB and ADDR register */
+    uint32_t ctrla = 0;
+    uint32_t ctrlb = 0;
 #  if CONF_SPI_SLAVE_ENABLE == true
-	uint32_t addr = 0;
+    uint32_t addr = 0;
 #  endif
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	/* Find baud value and compare it */
-	if (config->mode == SPI_MODE_MASTER) {
-		enum status_code error_code = _sercom_get_sync_baud_val(
-				config->mode_specific.master.baudrate,
-				external_clock, &baud);
-
-		if (error_code != STATUS_OK) {
-			/* Baud rate calculation error, return status code */
-			return STATUS_ERR_INVALID_ARG;
-		}
-
-		if (spi_module->BAUD.reg !=  (uint8_t)baud) {
-			return STATUS_ERR_DENIED;
-		}
-
-		ctrla |= SERCOM_SPI_CTRLA_MODE(0x3);
-	}
+    /* Find baud value and compare it */
+    if (config->mode == SPI_MODE_MASTER)
+    {
+        enum status_code error_code = _sercom_get_sync_baud_val(
+                config->mode_specific.master.baudrate,
+                external_clock, &baud);
+
+        if (error_code != STATUS_OK)
+        {
+            /* Baud rate calculation error, return status code */
+            return STATUS_ERR_INVALID_ARG;
+        }
+
+        if (spi_module->BAUD.reg !=  (uint8_t)baud)
+        {
+            return STATUS_ERR_DENIED;
+        }
+
+        ctrla |= SERCOM_SPI_CTRLA_MODE(0x3);
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (config->mode == SPI_MODE_SLAVE) {
-
-		/* Set frame format */
-		ctrla |= config->mode_specific.slave.frame_format;
-
-		/* Set address mode */
-		ctrlb |= config->mode_specific.slave.address_mode;
-
-		/* Set address and address mask*/
-		addr |= (config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
-				(config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
-		if (spi_module->CTRLA.reg != addr) {
-			return STATUS_ERR_DENIED;
-		}
-
-		if (config->mode_specific.slave.preload_enable) {
-			/* Enable pre-loading of shift register */
-			ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
-		}
-		ctrla |= SERCOM_SPI_CTRLA_MODE(0x2);
-	}
+    if (config->mode == SPI_MODE_SLAVE)
+    {
+
+        /* Set frame format */
+        ctrla |= config->mode_specific.slave.frame_format;
+
+        /* Set address mode */
+        ctrlb |= config->mode_specific.slave.address_mode;
+
+        /* Set address and address mask*/
+        addr |= (config->mode_specific.slave.address      << SERCOM_SPI_ADDR_ADDR_Pos) |
+                (config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos);
+        if (spi_module->CTRLA.reg != addr)
+        {
+            return STATUS_ERR_DENIED;
+        }
+
+        if (config->mode_specific.slave.preload_enable)
+        {
+            /* Enable pre-loading of shift register */
+            ctrlb |= SERCOM_SPI_CTRLB_PLOADEN;
+        }
+        ctrla |= SERCOM_SPI_CTRLA_MODE(0x2);
+    }
 #  endif
-	/* Set data order */
-	ctrla |= config->data_order;
+    /* Set data order */
+    ctrla |= config->data_order;
 
-	/* Set clock polarity and clock phase */
-	ctrla |= config->transfer_mode;
+    /* Set clock polarity and clock phase */
+    ctrla |= config->transfer_mode;
 
-	/* Set MUX setting */
-	ctrla |= config->mux_setting;
+    /* Set MUX setting */
+    ctrla |= config->mux_setting;
 
-	/* Set SPI character size */
-	ctrlb |= config->character_size;
+    /* Set SPI character size */
+    ctrlb |= config->character_size;
 
-	if (config->run_in_standby) {
-		/* Enable in sleep mode */
-		ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
-	}
+    if (config->run_in_standby)
+    {
+        /* Enable in sleep mode */
+        ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY;
+    }
 
-	if (config->receiver_enable) {
-		/* Enable receiver */
-		ctrlb |= SERCOM_SPI_CTRLB_RXEN;
-	}
+    if (config->receiver_enable)
+    {
+        /* Enable receiver */
+        ctrlb |= SERCOM_SPI_CTRLB_RXEN;
+    }
 
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	if (config->select_slave_low_detect_enable) {
-		/* Enable Slave Select Low Detect */
-		ctrlb |= SERCOM_SPI_CTRLB_SSDE;
-	}
+    if (config->select_slave_low_detect_enable)
+    {
+        /* Enable Slave Select Low Detect */
+        ctrlb |= SERCOM_SPI_CTRLB_SSDE;
+    }
 #  endif
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	if (config->master_slave_select_enable) {
-		/* Enable Master Slave Select */
-		ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
-	}
+    if (config->master_slave_select_enable)
+    {
+        /* Enable Master Slave Select */
+        ctrlb |= SERCOM_SPI_CTRLB_MSSEN;
+    }
 #  endif
 
-	ctrla |= SERCOM_SPI_CTRLA_ENABLE;
+    ctrla |= SERCOM_SPI_CTRLA_ENABLE;
 
-	/* Check that same config is set */
-	if (spi_module->CTRLA.reg == ctrla &&
-			spi_module->CTRLB.reg == ctrlb) {
-		module->mode           = config->mode;
-		module->character_size = config->character_size;
-		return STATUS_OK;
-	}
+    /* Check that same config is set */
+    if (spi_module->CTRLA.reg == ctrla &&
+            spi_module->CTRLB.reg == ctrlb)
+            {
+        module->mode           = config->mode;
+        module->character_size = config->character_size;
+        return STATUS_OK;
+    }
 
-	/* Not same config, wipe module pointer and return */
-	module->hw = NULL;
+    /* Not same config, wipe module pointer and return */
+    module->hw = NULL;
 
-	return STATUS_ERR_DENIED;
+    return STATUS_ERR_DENIED;
 }
 #endif
 
@@ -481,136 +513,144 @@ static enum status_code _spi_check_config(
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code spi_init(
-		struct spi_module *const module,
-		Sercom *const hw,
-		const struct spi_config *const config)
+        struct spi_module *const module,
+        Sercom *const hw,
+        const struct spi_config *const config)
 {
 
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Check if module is enabled. */
-	if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_ENABLE) {
+    /* Check if module is enabled. */
+    if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_ENABLE)
+    {
 #  if SPI_CALLBACK_MODE == false
-		/* Check if config is valid */
-		return _spi_check_config(module, config);
+        /* Check if config is valid */
+        return _spi_check_config(module, config);
 #  else
-		return STATUS_ERR_DENIED;
+        return STATUS_ERR_DENIED;
 #  endif
-	}
+    }
 
-	/* Check if reset is in progress. */
-	if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST){
-		return STATUS_BUSY;
-	}
+    /* Check if reset is in progress. */
+    if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST)
+    {
+        return STATUS_BUSY;
+    }
 
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index, gclk_index;
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index, gclk_index;
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
+    if (sercom_index == 5)
+    {
 #  ifdef ID_SERCOM5
-		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
-		gclk_index   =  SERCOM5_GCLK_ID_CORE;
+        pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+        gclk_index   =  SERCOM5_GCLK_ID_CORE;
 #  else
-		return STATUS_ERR_INVALID_ARG;
+        return STATUS_ERR_INVALID_ARG;
 #  endif
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
-#elif (SAMC21) 
-	if (sercom_index == 5) {
+    } else {
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
+#elif (SAMC21)
+    if (sercom_index == 5)
+    {
 #  ifdef ID_SERCOM5
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   =  SERCOM5_GCLK_ID_CORE;
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   =  SERCOM5_GCLK_ID_CORE;
 #  else
-		return STATUS_ERR_INVALID_ARG;
+        return STATUS_ERR_INVALID_ARG;
 #  endif
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
+    } else {
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
 #elif (SAMC20) || (SAML22)
-	pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #endif
 
-	/* Turn on module in PM */
+    /* Turn on module in PM */
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
+    if (sercom_index == 5)
+    {
 #  ifdef ID_SERCOM5
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
 #  else
-		return STATUS_ERR_INVALID_ARG;
+        return STATUS_ERR_INVALID_ARG;
 #  endif
-	} else {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-	}
+    } else {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    }
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
 #endif
 
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	if (config->mode == SPI_MODE_MASTER) {
-		/* Set the SERCOM in SPI master mode */
-		spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3);
-	}
+    if (config->mode == SPI_MODE_MASTER)
+    {
+        /* Set the SERCOM in SPI master mode */
+        spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3);
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (config->mode == SPI_MODE_SLAVE) {
-		/* Set the SERCOM in SPI slave mode */
-		spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x2);
-	}
+    if (config->mode == SPI_MODE_SLAVE)
+    {
+        /* Set the SERCOM in SPI slave mode */
+        spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x2);
+    }
 #  endif
 
 #if SPI_CALLBACK_MODE == true
-	/* Temporary variables */
-	uint8_t i;
-	uint8_t instance_index;
-
-	/* Initialize parameters */
-	for (i = 0; i < SPI_CALLBACK_N; i++) {
-		module->callback[i]        = NULL;
-	}
-	module->tx_buffer_ptr              = NULL;
-	module->rx_buffer_ptr              = NULL;
-	module->remaining_tx_buffer_length = 0x0000;
-	module->remaining_rx_buffer_length = 0x0000;
-	module->registered_callback        = 0x00;
-	module->enabled_callback           = 0x00;
-	module->status                     = STATUS_OK;
-	module->dir                        = SPI_DIRECTION_IDLE;
-	module->locked                     = false;
-	/*
-	 * Set interrupt handler and register SPI software module struct in
-	 * look-up table
-	 */
-	instance_index = _sercom_get_sercom_inst_index(module->hw);
-	_sercom_set_handler(instance_index, _spi_interrupt_handler);
-	_sercom_instances[instance_index] = module;
+    /* Temporary variables */
+    uint8_t i;
+    uint8_t instance_index;
+
+    /* Initialize parameters */
+    for (i = 0; i < SPI_CALLBACK_N; i++)
+    {
+        module->callback[i]        = NULL;
+    }
+    module->tx_buffer_ptr              = NULL;
+    module->rx_buffer_ptr              = NULL;
+    module->remaining_tx_buffer_length = 0x0000;
+    module->remaining_rx_buffer_length = 0x0000;
+    module->registered_callback        = 0x00;
+    module->enabled_callback           = 0x00;
+    module->status                     = STATUS_OK;
+    module->dir                        = SPI_DIRECTION_IDLE;
+    module->locked                     = false;
+    /*
+     * Set interrupt handler and register SPI software module struct in
+     * look-up table
+     */
+    instance_index = _sercom_get_sercom_inst_index(module->hw);
+    _sercom_set_handler(instance_index, _spi_interrupt_handler);
+    _sercom_instances[instance_index] = module;
 #endif
 
-	/* Write configuration to module and return status code */
-	return _spi_set_config(module, config);
+    /* Write configuration to module and return status code */
+    return _spi_set_config(module, config);
 }
 
 /**
@@ -638,93 +678,108 @@ enum status_code spi_init(
  * \retval STATUS_ERR_OVERFLOW    If the data is overflown
  */
 enum status_code spi_read_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
 #  if SPI_CALLBACK_MODE == true
-	if (module->status == STATUS_BUSY) {
-		/* Check if the SPI module is busy with a job */
-		return STATUS_BUSY;
-	}
+    if (module->status == STATUS_BUSY)
+    {
+        /* Check if the SPI module is busy with a job */
+        return STATUS_BUSY;
+    }
 #  endif
 
-	/* Sanity check arguments */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
-		/* Clear TX complete flag */
-		_spi_clear_tx_complete_flag(module);
-	}
+    if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module)))
+    {
+        /* Clear TX complete flag */
+        _spi_clear_tx_complete_flag(module);
+    }
 #  endif
-	uint16_t rx_pos = 0;
+    uint16_t rx_pos = 0;
 
-	while (length--) {
+    while (length--)
+    {
 #  if CONF_SPI_MASTER_ENABLE == true
-		if (module->mode == SPI_MODE_MASTER) {
-			/* Wait until the module is ready to write a character */
-			while (!spi_is_ready_to_write(module)) {
-			}
-
-			/* Send dummy SPI character to read in master mode */
-			spi_write(module, dummy);
-		}
+        if (module->mode == SPI_MODE_MASTER)
+        {
+            /* Wait until the module is ready to write a character */
+            while (!spi_is_ready_to_write(module))
+            {
+            }
+
+            /* Send dummy SPI character to read in master mode */
+            spi_write(module, dummy);
+        }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-		/* Start timeout period for slave */
-		if (module->mode == SPI_MODE_SLAVE) {
-			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-				if (spi_is_ready_to_read(module)) {
-					break;
-				}
-			}
-			/* Check if master has ended the transaction */
-			if (spi_is_write_complete(module)) {
-				_spi_clear_tx_complete_flag(module);
-				return STATUS_ABORTED;
-			}
-
-			if (!spi_is_ready_to_read(module)) {
-				/* Not ready to read data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
+        /* Start timeout period for slave */
+        if (module->mode == SPI_MODE_SLAVE)
+        {
+            for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+            {
+                if (spi_is_ready_to_read(module))
+                {
+                    break;
+                }
+            }
+            /* Check if master has ended the transaction */
+            if (spi_is_write_complete(module))
+            {
+                _spi_clear_tx_complete_flag(module);
+                return STATUS_ABORTED;
+            }
+
+            if (!spi_is_ready_to_read(module))
+            {
+                /* Not ready to read data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
 #  endif
 
-		/* Wait until the module is ready to read a character */
-		while (!spi_is_ready_to_read(module)) {
-		}
+        /* Wait until the module is ready to read a character */
+        while (!spi_is_ready_to_read(module))
+        {
+        }
 
-		uint16_t received_data = 0;
-		enum status_code retval = spi_read(module, &received_data);
+        uint16_t received_data = 0;
+        enum status_code retval = spi_read(module, &received_data);
 
-		if (retval != STATUS_OK) {
-			/* Overflow, abort */
-			return retval;
-		}
+        if (retval != STATUS_OK)
+        {
+            /* Overflow, abort */
+            return retval;
+        }
 
-		/* Read value will be at least 8-bits long */
-		rx_data[rx_pos++] = received_data;
+        /* Read value will be at least 8-bits long */
+        rx_data[rx_pos++] = received_data;
 
-		/* If 9-bit data, write next received byte to the buffer */
-		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-			rx_data[rx_pos++] = (received_data >> 8);
-		}
-	}
+        /* If 9-bit data, write next received byte to the buffer */
+        if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+        {
+            rx_data[rx_pos++] = (received_data >> 8);
+        }
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -758,71 +813,83 @@ enum status_code spi_read_buffer_wait(
  * \retval STATUS_ERR_OVERFLOW  If the incoming data is overflown
  */
 enum status_code spi_transceive_wait(
-		struct spi_module *const module,
-		uint16_t tx_data,
-		uint16_t *rx_data)
+        struct spi_module *const module,
+        uint16_t tx_data,
+        uint16_t *rx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 
 #  if SPI_CALLBACK_MODE == true
-	if (module->status == STATUS_BUSY) {
-		/* Check if the SPI module is busy with a job */
-		return STATUS_BUSY;
-	}
+    if (module->status == STATUS_BUSY)
+    {
+        /* Check if the SPI module is busy with a job */
+        return STATUS_BUSY;
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	uint16_t j;
+    uint16_t j;
 #  endif
-	enum status_code retval = STATUS_OK;
+    enum status_code retval = STATUS_OK;
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	/* Start timeout period for slave */
-	if (module->mode == SPI_MODE_SLAVE) {
-		for (j = 0; j <= SPI_TIMEOUT; j++) {
-			if (spi_is_ready_to_write(module)) {
-				break;
-			} else if (j == SPI_TIMEOUT) {
-				/* Not ready to write data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-	}
+    /* Start timeout period for slave */
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        for (j = 0; j <= SPI_TIMEOUT; j++)
+        {
+            if (spi_is_ready_to_write(module))
+            {
+                break;
+            } else if (j == SPI_TIMEOUT)
+            {
+                /* Not ready to write data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
+    }
 #  endif
-	/* Wait until the module is ready to write the character */
-	while (!spi_is_ready_to_write(module)) {
-	}
+    /* Wait until the module is ready to write the character */
+    while (!spi_is_ready_to_write(module))
+    {
+    }
 
-	/* Write data */
-	spi_write(module, tx_data);
+    /* Write data */
+    spi_write(module, tx_data);
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	/* Start timeout period for slave */
-	if (module->mode == SPI_MODE_SLAVE) {
-		for (j = 0; j <= SPI_TIMEOUT; j++) {
-			if (spi_is_ready_to_read(module)) {
-				break;
-			} else if (j == SPI_TIMEOUT) {
-				/* Not ready to read data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-	}
+    /* Start timeout period for slave */
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        for (j = 0; j <= SPI_TIMEOUT; j++)
+        {
+            if (spi_is_ready_to_read(module))
+            {
+                break;
+            } else if (j == SPI_TIMEOUT)
+            {
+                /* Not ready to read data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
+    }
 #  endif
 
-	/* Wait until the module is ready to read the character */
-	while (!spi_is_ready_to_read(module)) {
-	}
+    /* Wait until the module is ready to read the character */
+    while (!spi_is_ready_to_read(module))
+    {
+    }
 
-	/* Read data */
-	retval = spi_read(module, rx_data);
+    /* Read data */
+    retval = spi_read(module, rx_data);
 
-	return retval;
+    return retval;
 }
 
  /**
@@ -846,56 +913,62 @@ enum status_code spi_transceive_wait(
  *                                     the slave address
  */
 enum status_code spi_select_slave(
-		struct spi_module *const module,
-		struct spi_slave_inst *const slave,
-		const bool select)
+        struct spi_module *const module,
+        struct spi_slave_inst *const slave,
+        const bool select)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(slave);
-
-	/* Check that the SPI module is operating in master mode */
-	if (module->mode != SPI_MODE_MASTER) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(slave);
+
+    /* Check that the SPI module is operating in master mode */
+    if (module->mode != SPI_MODE_MASTER)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	if(!(module->master_slave_select_enable))
+    if(!(module->master_slave_select_enable))
 #  endif
-	{
-		if (select) {
-			/* Check if address recognition is enabled */
-			if (slave->address_enabled) {
-				/* Check if the module is ready to write the address */
-				if (!spi_is_ready_to_write(module)) {
-					/* Not ready, do not select slave and return */
-					port_pin_set_output_level(slave->ss_pin, true);
-					return STATUS_BUSY;
-				}
-
-				/* Drive Slave Select low */
-				port_pin_set_output_level(slave->ss_pin, false);
-
-				/* Write address to slave */
-				spi_write(module, slave->address);
-
-				if (!(module->receiver_enabled)) {
-					/* Flush contents of shift register shifted back from slave */
-					while (!spi_is_ready_to_read(module)) {
-					}
-					uint16_t flush = 0;
-					spi_read(module, &flush);
-				}
-			} else {
-				/* Drive Slave Select low */
-				port_pin_set_output_level(slave->ss_pin, false);
-			}
-		} else {
-			/* Drive Slave Select high */
-			port_pin_set_output_level(slave->ss_pin, true);
-		}
-	}
-	return STATUS_OK;
+    {
+        if (select)
+        {
+            /* Check if address recognition is enabled */
+            if (slave->address_enabled)
+            {
+                /* Check if the module is ready to write the address */
+                if (!spi_is_ready_to_write(module))
+                {
+                    /* Not ready, do not select slave and return */
+                    port_pin_set_output_level(slave->ss_pin, true);
+                    return STATUS_BUSY;
+                }
+
+                /* Drive Slave Select low */
+                port_pin_set_output_level(slave->ss_pin, false);
+
+                /* Write address to slave */
+                spi_write(module, slave->address);
+
+                if (!(module->receiver_enabled))
+                {
+                    /* Flush contents of shift register shifted back from slave */
+                    while (!spi_is_ready_to_read(module))
+                    {
+                    }
+                    uint16_t flush = 0;
+                    spi_read(module, &flush);
+                }
+            } else {
+                /* Drive Slave Select low */
+                port_pin_set_output_level(slave->ss_pin, false);
+            }
+        } else {
+            /* Drive Slave Select high */
+            port_pin_set_output_level(slave->ss_pin, true);
+        }
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -921,147 +994,175 @@ enum status_code spi_select_slave(
  *                                 timeout in slave mode
  */
 enum status_code spi_write_buffer_wait(
-		struct spi_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        const uint8_t *tx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
 #  if SPI_CALLBACK_MODE == true
-	if (module->status == STATUS_BUSY) {
-		/* Check if the SPI module is busy with a job */
-		return STATUS_BUSY;
-	}
+    if (module->status == STATUS_BUSY)
+    {
+        /* Check if the SPI module is busy with a job */
+        return STATUS_BUSY;
+    }
 #  endif
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
-		/* Clear TX complete flag */
-		_spi_clear_tx_complete_flag(module);
-	}
+    if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module)))
+    {
+        /* Clear TX complete flag */
+        _spi_clear_tx_complete_flag(module);
+    }
 #  endif
 
-	uint16_t tx_pos = 0;
-	uint16_t flush_length = length;
+    uint16_t tx_pos = 0;
+    uint16_t flush_length = length;
 
-	/* Write block */
-	while (length--) {
+    /* Write block */
+    while (length--)
+    {
 #  if CONF_SPI_SLAVE_ENABLE == true
-		/* Start timeout period for slave */
-		if (module->mode == SPI_MODE_SLAVE) {
-			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-				if (spi_is_ready_to_write(module)) {
-					break;
-				}
-			}
-			/* Check if master has ended the transaction */
-			if (spi_is_write_complete(module)) {
-				_spi_clear_tx_complete_flag(module);
-				return STATUS_ABORTED;
-			}
-
-			if (!spi_is_ready_to_write(module)) {
-				/* Not ready to write data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
+        /* Start timeout period for slave */
+        if (module->mode == SPI_MODE_SLAVE)
+        {
+            for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+            {
+                if (spi_is_ready_to_write(module))
+                {
+                    break;
+                }
+            }
+            /* Check if master has ended the transaction */
+            if (spi_is_write_complete(module))
+            {
+                _spi_clear_tx_complete_flag(module);
+                return STATUS_ABORTED;
+            }
+
+            if (!spi_is_ready_to_write(module))
+            {
+                /* Not ready to write data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
 #  endif
 
-		/* Wait until the module is ready to write a character */
-		while (!spi_is_ready_to_write(module)) {
-		}
+        /* Wait until the module is ready to write a character */
+        while (!spi_is_ready_to_write(module))
+        {
+        }
 
-		/* Write value will be at least 8-bits long */
-		uint16_t data_to_send = tx_data[tx_pos++];
+        /* Write value will be at least 8-bits long */
+        uint16_t data_to_send = tx_data[tx_pos++];
 
-		/* If 9-bit data, get next byte to send from the buffer */
-		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-			data_to_send |= (tx_data[tx_pos++] << 8);
-		}
+        /* If 9-bit data, get next byte to send from the buffer */
+        if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+        {
+            data_to_send |= (tx_data[tx_pos++] << 8);
+        }
 
-		/* Write the data to send */
-		spi_write(module, data_to_send);
+        /* Write the data to send */
+        spi_write(module, data_to_send);
 
-		if (module->receiver_enabled) {
+        if (module->receiver_enabled)
+        {
 #  if CONF_SPI_SLAVE_ENABLE == true
-			/* Start timeout period for slave */
-			if (module->mode == SPI_MODE_SLAVE) {
-				for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-					if (length && spi_is_ready_to_write(module)) {
-						data_to_send = tx_data[tx_pos++];
-						/* If 9-bit data, get next byte to send from the buffer */
-						if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-							data_to_send |= (tx_data[tx_pos++] << 8);
-						}
-
-						/* Write the data to send */
-						spi_write(module, data_to_send);
-						length--;
-					}
-					if (spi_is_ready_to_read(module)) {
-						break;
-					}
-				}
-
-				/* Check if master has ended the transaction */
-				if (spi_is_write_complete(module)) {
-					_spi_clear_tx_complete_flag(module);
-					return STATUS_ABORTED;
-				}
-
-				if (!spi_is_ready_to_read(module)) {
-					/* Not ready to read data within timeout period */
-					return STATUS_ERR_TIMEOUT;
-				}
-			}
+            /* Start timeout period for slave */
+            if (module->mode == SPI_MODE_SLAVE)
+            {
+                for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+                {
+                    if (length && spi_is_ready_to_write(module))
+                    {
+                        data_to_send = tx_data[tx_pos++];
+                        /* If 9-bit data, get next byte to send from the buffer */
+                        if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+                        {
+                            data_to_send |= (tx_data[tx_pos++] << 8);
+                        }
+
+                        /* Write the data to send */
+                        spi_write(module, data_to_send);
+                        length--;
+                    }
+                    if (spi_is_ready_to_read(module))
+                    {
+                        break;
+                    }
+                }
+
+                /* Check if master has ended the transaction */
+                if (spi_is_write_complete(module))
+                {
+                    _spi_clear_tx_complete_flag(module);
+                    return STATUS_ABORTED;
+                }
+
+                if (!spi_is_ready_to_read(module))
+                {
+                    /* Not ready to read data within timeout period */
+                    return STATUS_ERR_TIMEOUT;
+                }
+            }
 #  endif
 
-			while (!spi_is_ready_to_read(module)) {
-			}
+            while (!spi_is_ready_to_read(module))
+            {
+            }
 
-			/* Flush read buffer */
-			uint16_t flush;
-			spi_read(module, &flush);
-			flush_length--;
-		}
-	}
+            /* Flush read buffer */
+            uint16_t flush;
+            spi_read(module, &flush);
+            flush_length--;
+        }
+    }
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	if (module->mode == SPI_MODE_MASTER) {
-		/* Wait for last byte to be transferred */
-		while (!spi_is_write_complete(module)) {
-		}
-	}
+    if (module->mode == SPI_MODE_MASTER)
+    {
+        /* Wait for last byte to be transferred */
+        while (!spi_is_write_complete(module))
+        {
+        }
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (module->mode == SPI_MODE_SLAVE) {
-		if (module->receiver_enabled) {
-			while (flush_length) {
-				/* Start timeout period for slave */
-				for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-					if (spi_is_ready_to_read(module)) {
-						break;
-					}
-				}
-				if (!spi_is_ready_to_read(module)) {
-					/* Not ready to read data within timeout period */
-					return STATUS_ERR_TIMEOUT;
-				}
-				/* Flush read buffer */
-				uint16_t flush;
-				spi_read(module, &flush);
-				flush_length--;
-			}
-		}
-	}
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        if (module->receiver_enabled)
+        {
+            while (flush_length)
+            {
+                /* Start timeout period for slave */
+                for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+                {
+                    if (spi_is_ready_to_read(module))
+                    {
+                        break;
+                    }
+                }
+                if (!spi_is_ready_to_read(module))
+                {
+                    /* Not ready to read data within timeout period */
+                    return STATUS_ERR_TIMEOUT;
+                }
+                /* Flush read buffer */
+                uint16_t flush;
+                spi_read(module, &flush);
+                flush_length--;
+            }
+        }
+    }
 #  endif
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1091,175 +1192,206 @@ enum status_code spi_write_buffer_wait(
  * \retval STATUS_ERR_OVERFLOW     If the data is overflown
  */
 enum status_code spi_transceive_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
 #  if SPI_CALLBACK_MODE == true
-	if (module->status == STATUS_BUSY) {
-		/* Check if the SPI module is busy with a job */
-		return STATUS_BUSY;
-	}
+    if (module->status == STATUS_BUSY)
+    {
+        /* Check if the SPI module is busy with a job */
+        return STATUS_BUSY;
+    }
 #  endif
 
-	/* Sanity check arguments */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) {
-		/* Clear TX complete flag */
-		_spi_clear_tx_complete_flag(module);
-	}
+    if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module)))
+    {
+        /* Clear TX complete flag */
+        _spi_clear_tx_complete_flag(module);
+    }
 #  endif
 
-	uint16_t tx_pos = 0;
-	uint16_t rx_pos = 0;
-	uint16_t rx_length = length;
+    uint16_t tx_pos = 0;
+    uint16_t rx_pos = 0;
+    uint16_t rx_length = length;
 
-	/* Send and receive buffer */
-	while (length--) {
+    /* Send and receive buffer */
+    while (length--)
+    {
 #  if CONF_SPI_SLAVE_ENABLE == true
-		/* Start timeout period for slave */
-		if (module->mode == SPI_MODE_SLAVE) {
-			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-				if (spi_is_ready_to_write(module)) {
-					break;
-				}
-			}
-			/* Check if master has ended the transaction */
-			if (spi_is_write_complete(module)) {
-				_spi_clear_tx_complete_flag(module);
-				return STATUS_ABORTED;
-			}
-
-			if (!spi_is_ready_to_write(module)) {
-				/* Not ready to write data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
+        /* Start timeout period for slave */
+        if (module->mode == SPI_MODE_SLAVE)
+        {
+            for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+            {
+                if (spi_is_ready_to_write(module))
+                {
+                    break;
+                }
+            }
+            /* Check if master has ended the transaction */
+            if (spi_is_write_complete(module))
+            {
+                _spi_clear_tx_complete_flag(module);
+                return STATUS_ABORTED;
+            }
+
+            if (!spi_is_ready_to_write(module))
+            {
+                /* Not ready to write data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
 #  endif
 
-		/* Wait until the module is ready to write a character */
-		while (!spi_is_ready_to_write(module)) {
-		}
+        /* Wait until the module is ready to write a character */
+        while (!spi_is_ready_to_write(module))
+        {
+        }
 
-		/* Write value will be at least 8-bits long */
-		uint16_t data_to_send = tx_data[tx_pos++];
+        /* Write value will be at least 8-bits long */
+        uint16_t data_to_send = tx_data[tx_pos++];
 
-		/* If 9-bit data, get next byte to send from the buffer */
-		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-			data_to_send |= (tx_data[tx_pos++] << 8);
-		}
+        /* If 9-bit data, get next byte to send from the buffer */
+        if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+        {
+            data_to_send |= (tx_data[tx_pos++] << 8);
+        }
 
-		/* Write the data to send */
-		spi_write(module, data_to_send);
+        /* Write the data to send */
+        spi_write(module, data_to_send);
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-		/* Start timeout period for slave */
-		if (module->mode == SPI_MODE_SLAVE) {
-			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-				if (spi_is_ready_to_write(module)) {
-					data_to_send = tx_data[tx_pos++];
-					/* If 9-bit data, get next byte to send from the buffer */
-					if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-						data_to_send |= (tx_data[tx_pos++] << 8);
-					}
-
-					/* Write the data to send */
-					spi_write(module, data_to_send);
-					length--;
-				}
-				if (spi_is_ready_to_read(module)) {
-					break;
-				}
-			}
-			/* Check if master has ended the transaction */
-			if (spi_is_write_complete(module)) {
-				_spi_clear_tx_complete_flag(module);
-				return STATUS_ABORTED;
-			}
-
-			if (!spi_is_ready_to_read(module)) {
-				/* Not ready to read data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
+        /* Start timeout period for slave */
+        if (module->mode == SPI_MODE_SLAVE)
+        {
+            for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+            {
+                if (spi_is_ready_to_write(module))
+                {
+                    data_to_send = tx_data[tx_pos++];
+                    /* If 9-bit data, get next byte to send from the buffer */
+                    if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+                    {
+                        data_to_send |= (tx_data[tx_pos++] << 8);
+                    }
+
+                    /* Write the data to send */
+                    spi_write(module, data_to_send);
+                    length--;
+                }
+                if (spi_is_ready_to_read(module))
+                {
+                    break;
+                }
+            }
+            /* Check if master has ended the transaction */
+            if (spi_is_write_complete(module))
+            {
+                _spi_clear_tx_complete_flag(module);
+                return STATUS_ABORTED;
+            }
+
+            if (!spi_is_ready_to_read(module))
+            {
+                /* Not ready to read data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
 #  endif
 
-		/* Wait until the module is ready to read a character */
-		while (!spi_is_ready_to_read(module)) {
-		}
+        /* Wait until the module is ready to read a character */
+        while (!spi_is_ready_to_read(module))
+        {
+        }
 
-		enum status_code retval;
-		uint16_t received_data = 0;
-		rx_length--;
+        enum status_code retval;
+        uint16_t received_data = 0;
+        rx_length--;
 
-		retval = spi_read(module, &received_data);
+        retval = spi_read(module, &received_data);
 
-		if (retval != STATUS_OK) {
-			/* Overflow, abort */
-			return retval;
-		}
+        if (retval != STATUS_OK)
+        {
+            /* Overflow, abort */
+            return retval;
+        }
 
-		/* Read value will be at least 8-bits long */
-		rx_data[rx_pos++] = received_data;
+        /* Read value will be at least 8-bits long */
+        rx_data[rx_pos++] = received_data;
 
-		/* If 9-bit data, write next received byte to the buffer */
-		if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-			rx_data[rx_pos++] = (received_data >> 8);
-		}
-	}
+        /* If 9-bit data, write next received byte to the buffer */
+        if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+        {
+            rx_data[rx_pos++] = (received_data >> 8);
+        }
+    }
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	if (module->mode == SPI_MODE_MASTER) {
-		/* Wait for last byte to be transferred */
-		while (!spi_is_write_complete(module)) {
-		}
-	}
+    if (module->mode == SPI_MODE_MASTER)
+    {
+        /* Wait for last byte to be transferred */
+        while (!spi_is_write_complete(module))
+        {
+        }
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (module->mode == SPI_MODE_SLAVE) {
-		while (rx_length) {
-			/* Start timeout period for slave */
-			for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) {
-				if (spi_is_ready_to_read(module)) {
-					break;
-				}
-			}
-			if (!spi_is_ready_to_read(module)) {
-				/* Not ready to read data within timeout period */
-				return STATUS_ERR_TIMEOUT;
-			}
-			enum status_code retval;
-			uint16_t received_data = 0;
-			rx_length--;
-
-			retval = spi_read(module, &received_data);
-
-			if (retval != STATUS_OK) {
-				/* Overflow, abort */
-				return retval;
-			}
-			/* Read value will be at least 8-bits long */
-			rx_data[rx_pos++] = received_data;
-
-			/* If 9-bit data, write next received byte to the buffer */
-			if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-				rx_data[rx_pos++] = (received_data >> 8);
-			}
-		}
-	}
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        while (rx_length)
+        {
+            /* Start timeout period for slave */
+            for (uint32_t i = 0; i <= SPI_TIMEOUT; i++)
+            {
+                if (spi_is_ready_to_read(module))
+                {
+                    break;
+                }
+            }
+            if (!spi_is_ready_to_read(module))
+            {
+                /* Not ready to read data within timeout period */
+                return STATUS_ERR_TIMEOUT;
+            }
+            enum status_code retval;
+            uint16_t received_data = 0;
+            rx_length--;
+
+            retval = spi_read(module, &received_data);
+
+            if (retval != STATUS_OK)
+            {
+                /* Overflow, abort */
+                return retval;
+            }
+            /* Read value will be at least 8-bits long */
+            rx_data[rx_pos++] = received_data;
+
+            /* If 9-bit data, write next received byte to the buffer */
+            if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+            {
+                rx_data[rx_pos++] = (received_data >> 8);
+            }
+        }
+    }
 #  endif
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h
index 81a55ec9e229..c367383a8ecd 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi.h
@@ -390,7 +390,7 @@ extern "C" {
  * @{
  */
 #  if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAML21) || (SAMDA1) || (SAMHA1) ||\
-	  (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
+      (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__)
 /** SPI slave select low detection. */
 #  define FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
 /** Slave select can be controlled by hardware. */
@@ -428,30 +428,30 @@ extern "C" {
  *
  */
 enum spi_callback {
-	/** Callback for buffer transmitted */
-	SPI_CALLBACK_BUFFER_TRANSMITTED,
-	/** Callback for buffer received */
-	SPI_CALLBACK_BUFFER_RECEIVED,
-	/** Callback for buffers transceived */
-	SPI_CALLBACK_BUFFER_TRANSCEIVED,
-	/** Callback for error */
-	SPI_CALLBACK_ERROR,
-	/**
-	* Callback for transmission ended by master before the entire buffer was
-	* read or written from slave
-	*/
-	SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE,
+    /** Callback for buffer transmitted */
+    SPI_CALLBACK_BUFFER_TRANSMITTED,
+    /** Callback for buffer received */
+    SPI_CALLBACK_BUFFER_RECEIVED,
+    /** Callback for buffers transceived */
+    SPI_CALLBACK_BUFFER_TRANSCEIVED,
+    /** Callback for error */
+    SPI_CALLBACK_ERROR,
+    /**
+    * Callback for transmission ended by master before the entire buffer was
+    * read or written from slave
+    */
+    SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE,
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	/** Callback for  slave select low */
-	SPI_CALLBACK_SLAVE_SELECT_LOW,
+    /** Callback for  slave select low */
+    SPI_CALLBACK_SLAVE_SELECT_LOW,
 #  endif
 #  ifdef FEATURE_SPI_ERROR_INTERRUPT
-	/** Callback for combined error happen */
-	SPI_CALLBACK_COMBINED_ERROR,
+    /** Callback for combined error happen */
+    SPI_CALLBACK_COMBINED_ERROR,
 #  endif
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	SPI_CALLBACK_N,
+    /** Number of available callbacks */
+    SPI_CALLBACK_N,
 #  endif
 };
 #  endif
@@ -462,14 +462,14 @@ enum spi_callback {
  * \internal SPI transfer directions
  */
 enum _spi_direction {
-	/** Transfer direction is read */
-	SPI_DIRECTION_READ,
-	/** Transfer direction is write */
-	SPI_DIRECTION_WRITE,
-	/** Transfer direction is read and write */
-	SPI_DIRECTION_BOTH,
-	/** No transfer */
-	SPI_DIRECTION_IDLE,
+    /** Transfer direction is read */
+    SPI_DIRECTION_READ,
+    /** Transfer direction is write */
+    SPI_DIRECTION_WRITE,
+    /** Transfer direction is read and write */
+    SPI_DIRECTION_BOTH,
+    /** No transfer */
+    SPI_DIRECTION_IDLE,
 };
 #  endif
 #endif
@@ -481,25 +481,25 @@ enum _spi_direction {
  *
  */
 enum spi_interrupt_flag {
-	/**
-	 * This flag is set when the contents of the data register has been moved
-	 * to the shift register and the data register is ready for new data
-	 */
-	SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY = SERCOM_SPI_INTFLAG_DRE,
-	/**
-	 * This flag is set when the contents of the shift register has been
-	 * shifted out
-	 */
-	SPI_INTERRUPT_FLAG_TX_COMPLETE         = SERCOM_SPI_INTFLAG_TXC,
-	/** This flag is set when data has been shifted into the data register */
-	SPI_INTERRUPT_FLAG_RX_COMPLETE         = SERCOM_SPI_INTFLAG_RXC,
+    /**
+     * This flag is set when the contents of the data register has been moved
+     * to the shift register and the data register is ready for new data
+     */
+    SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY = SERCOM_SPI_INTFLAG_DRE,
+    /**
+     * This flag is set when the contents of the shift register has been
+     * shifted out
+     */
+    SPI_INTERRUPT_FLAG_TX_COMPLETE         = SERCOM_SPI_INTFLAG_TXC,
+    /** This flag is set when data has been shifted into the data register */
+    SPI_INTERRUPT_FLAG_RX_COMPLETE         = SERCOM_SPI_INTFLAG_RXC,
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	/** This flag is set when slave select low  */
-	SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW         = SERCOM_SPI_INTFLAG_SSL,
+    /** This flag is set when slave select low  */
+    SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW         = SERCOM_SPI_INTFLAG_SSL,
 #  endif
 #  ifdef FEATURE_SPI_ERROR_INTERRUPT
-	/** This flag is set when combined error happen */
-	SPI_INTERRUPT_FLAG_COMBINED_ERROR         = SERCOM_SPI_INTFLAG_ERROR,
+    /** This flag is set when combined error happen */
+    SPI_INTERRUPT_FLAG_COMBINED_ERROR         = SERCOM_SPI_INTFLAG_ERROR,
 #  endif
 };
 
@@ -509,14 +509,14 @@ enum spi_interrupt_flag {
  * SPI transfer mode.
  */
 enum spi_transfer_mode {
-	/** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
-	SPI_TRANSFER_MODE_0 = 0,
-	/** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
-	SPI_TRANSFER_MODE_1 = SERCOM_SPI_CTRLA_CPHA,
-	/** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
-	SPI_TRANSFER_MODE_2 = SERCOM_SPI_CTRLA_CPOL,
-	/** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
-	SPI_TRANSFER_MODE_3 = SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL,
+    /** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
+    SPI_TRANSFER_MODE_0 = 0,
+    /** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
+    SPI_TRANSFER_MODE_1 = SERCOM_SPI_CTRLA_CPHA,
+    /** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
+    SPI_TRANSFER_MODE_2 = SERCOM_SPI_CTRLA_CPOL,
+    /** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
+    SPI_TRANSFER_MODE_3 = SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL,
 };
 
 /**
@@ -525,10 +525,10 @@ enum spi_transfer_mode {
  * Frame format for slave mode.
  */
 enum spi_frame_format {
-	/** SPI frame */
-	SPI_FRAME_FORMAT_SPI_FRAME      = SERCOM_SPI_CTRLA_FORM(0),
-	/** SPI frame with address */
-	SPI_FRAME_FORMAT_SPI_FRAME_ADDR = SERCOM_SPI_CTRLA_FORM(2),
+    /** SPI frame */
+    SPI_FRAME_FORMAT_SPI_FRAME      = SERCOM_SPI_CTRLA_FORM(0),
+    /** SPI frame with address */
+    SPI_FRAME_FORMAT_SPI_FRAME_ADDR = SERCOM_SPI_CTRLA_FORM(2),
 };
 
 /**
@@ -545,70 +545,70 @@ enum spi_frame_format {
  * various MUX setting options.
  */
 enum spi_signal_mux_setting {
-	/** SPI MUX combination A. DOPO: 0x0, DIPO: 0x0 */
-	SPI_SIGNAL_MUX_SETTING_A =
-			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination B. DOPO: 0x0, DIPO: 0x1 */
-	SPI_SIGNAL_MUX_SETTING_B =
-			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination C. DOPO: 0x0, DIPO: 0x2 */
-	SPI_SIGNAL_MUX_SETTING_C =
-			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination D. DOPO: 0x0, DIPO: 0x3 */
-	SPI_SIGNAL_MUX_SETTING_D =
-			(0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination E. DOPO: 0x1, DIPO: 0x0 */
-	SPI_SIGNAL_MUX_SETTING_E =
-			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination F. DOPO: 0x1, DIPO: 0x1 */
-	SPI_SIGNAL_MUX_SETTING_F =
-			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination G. DOPO: 0x1, DIPO: 0x2 */
-	SPI_SIGNAL_MUX_SETTING_G =
-			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination H. DOPO: 0x1, DIPO: 0x3 */
-	SPI_SIGNAL_MUX_SETTING_H =
-			(0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination I. DOPO: 0x2, DIPO: 0x0 */
-	SPI_SIGNAL_MUX_SETTING_I =
-			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination J. DOPO: 0x2, DIPO: 0x1 */
-	SPI_SIGNAL_MUX_SETTING_J =
-			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination K. DOPO: 0x2, DIPO: 0x2 */
-	SPI_SIGNAL_MUX_SETTING_K =
-			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination L. DOPO: 0x2, DIPO: 0x3 */
-	SPI_SIGNAL_MUX_SETTING_L =
-			(0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination M. DOPO: 0x3, DIPO: 0x0 */
-	SPI_SIGNAL_MUX_SETTING_M =
-			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination N. DOPO: 0x3, DIPO: 0x1 */
-	SPI_SIGNAL_MUX_SETTING_N =
-			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination O. DOPO: 0x3, DIPO: 0x2 */
-	SPI_SIGNAL_MUX_SETTING_O =
-			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
-	/** SPI MUX combination P. DOPO: 0x3, DIPO: 0x3 */
-	SPI_SIGNAL_MUX_SETTING_P =
-			(0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
-			(0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination A. DOPO: 0x0, DIPO: 0x0 */
+    SPI_SIGNAL_MUX_SETTING_A =
+            (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination B. DOPO: 0x0, DIPO: 0x1 */
+    SPI_SIGNAL_MUX_SETTING_B =
+            (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination C. DOPO: 0x0, DIPO: 0x2 */
+    SPI_SIGNAL_MUX_SETTING_C =
+            (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination D. DOPO: 0x0, DIPO: 0x3 */
+    SPI_SIGNAL_MUX_SETTING_D =
+            (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination E. DOPO: 0x1, DIPO: 0x0 */
+    SPI_SIGNAL_MUX_SETTING_E =
+            (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination F. DOPO: 0x1, DIPO: 0x1 */
+    SPI_SIGNAL_MUX_SETTING_F =
+            (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination G. DOPO: 0x1, DIPO: 0x2 */
+    SPI_SIGNAL_MUX_SETTING_G =
+            (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination H. DOPO: 0x1, DIPO: 0x3 */
+    SPI_SIGNAL_MUX_SETTING_H =
+            (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination I. DOPO: 0x2, DIPO: 0x0 */
+    SPI_SIGNAL_MUX_SETTING_I =
+            (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination J. DOPO: 0x2, DIPO: 0x1 */
+    SPI_SIGNAL_MUX_SETTING_J =
+            (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination K. DOPO: 0x2, DIPO: 0x2 */
+    SPI_SIGNAL_MUX_SETTING_K =
+            (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination L. DOPO: 0x2, DIPO: 0x3 */
+    SPI_SIGNAL_MUX_SETTING_L =
+            (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination M. DOPO: 0x3, DIPO: 0x0 */
+    SPI_SIGNAL_MUX_SETTING_M =
+            (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination N. DOPO: 0x3, DIPO: 0x1 */
+    SPI_SIGNAL_MUX_SETTING_N =
+            (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination O. DOPO: 0x3, DIPO: 0x2 */
+    SPI_SIGNAL_MUX_SETTING_O =
+            (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos),
+    /** SPI MUX combination P. DOPO: 0x3, DIPO: 0x3 */
+    SPI_SIGNAL_MUX_SETTING_P =
+            (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) |
+            (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos),
 };
 
 /**
@@ -618,20 +618,20 @@ enum spi_signal_mux_setting {
  *
  */
 enum spi_addr_mode {
-	/**
-	 * \c address_mask in the \ref spi_config struct is used as a mask to the register
-	 */
-	SPI_ADDR_MODE_MASK      = SERCOM_SPI_CTRLB_AMODE(0),
-	/**
-	 * The slave responds to the two unique addresses in \c address and
-	 * \c address_mask in the \ref spi_config struct
-	 */
-	SPI_ADDR_MODE_UNIQUE    = SERCOM_SPI_CTRLB_AMODE(1),
-	/**
-	 * The slave responds to the range of addresses between and including \c address
-	 * and \c address_mask in the \ref spi_config struct
-	 */
-	SPI_ADDR_MODE_RANGE     = SERCOM_SPI_CTRLB_AMODE(2),
+    /**
+     * \c address_mask in the \ref spi_config struct is used as a mask to the register
+     */
+    SPI_ADDR_MODE_MASK      = SERCOM_SPI_CTRLB_AMODE(0),
+    /**
+     * The slave responds to the two unique addresses in \c address and
+     * \c address_mask in the \ref spi_config struct
+     */
+    SPI_ADDR_MODE_UNIQUE    = SERCOM_SPI_CTRLB_AMODE(1),
+    /**
+     * The slave responds to the range of addresses between and including \c address
+     * and \c address_mask in the \ref spi_config struct
+     */
+    SPI_ADDR_MODE_RANGE     = SERCOM_SPI_CTRLB_AMODE(2),
 };
 
 /**
@@ -640,10 +640,10 @@ enum spi_addr_mode {
  * SPI mode selection.
  */
 enum spi_mode {
-	/** Master mode */
-	SPI_MODE_MASTER         = 1,
-	/** Slave mode */
-	SPI_MODE_SLAVE          = 0,
+    /** Master mode */
+    SPI_MODE_MASTER         = 1,
+    /** Slave mode */
+    SPI_MODE_SLAVE          = 0,
 };
 
 /**
@@ -653,10 +653,10 @@ enum spi_mode {
  *
  */
 enum spi_data_order {
-	/** The LSB of the data is transmitted first */
-	SPI_DATA_ORDER_LSB      = SERCOM_SPI_CTRLA_DORD,
-	/** The MSB of the data is transmitted first */
-	SPI_DATA_ORDER_MSB      = 0,
+    /** The LSB of the data is transmitted first */
+    SPI_DATA_ORDER_LSB      = SERCOM_SPI_CTRLA_DORD,
+    /** The MSB of the data is transmitted first */
+    SPI_DATA_ORDER_MSB      = 0,
 };
 
 /**
@@ -666,10 +666,10 @@ enum spi_data_order {
  *
  */
 enum spi_character_size {
-	/** 8-bit character */
-	SPI_CHARACTER_SIZE_8BIT = SERCOM_SPI_CTRLB_CHSIZE(0),
-	/** 9-bit character */
-	SPI_CHARACTER_SIZE_9BIT = SERCOM_SPI_CTRLB_CHSIZE(1),
+    /** 8-bit character */
+    SPI_CHARACTER_SIZE_8BIT = SERCOM_SPI_CTRLB_CHSIZE(0),
+    /** 9-bit character */
+    SPI_CHARACTER_SIZE_9BIT = SERCOM_SPI_CTRLB_CHSIZE(1),
 };
 
 #  if SPI_CALLBACK_MODE == true
@@ -696,42 +696,42 @@ extern void _spi_interrupt_handler(uint8_t instance);
  */
 struct spi_module {
 #  if !defined(__DOXYGEN__)
-	/** SERCOM hardware module */
-	Sercom *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** SPI mode */
-	enum spi_mode mode;
-	/** SPI character size */
-	enum spi_character_size character_size;
-	/** Receiver enabled */
-	bool receiver_enabled;
+    /** SERCOM hardware module */
+    Sercom *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** SPI mode */
+    enum spi_mode mode;
+    /** SPI character size */
+    enum spi_character_size character_size;
+    /** Receiver enabled */
+    bool receiver_enabled;
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	/** Enable Hardware Slave Select */
-	bool master_slave_select_enable;
+    /** Enable Hardware Slave Select */
+    bool master_slave_select_enable;
 #  endif
 #  if SPI_CALLBACK_MODE == true
-	/** Direction of transaction */
-	volatile enum _spi_direction dir;
-	/** Array to store callback function pointers in */
-	spi_callback_t callback[SPI_CALLBACK_N];
-	/** Buffer pointer to where the next received character will be put */
-	volatile uint8_t *rx_buffer_ptr;
-	/** Buffer pointer to where the next character will be transmitted from
-	**/
-	volatile uint8_t *tx_buffer_ptr;
-	/** Remaining characters to receive */
-	volatile uint16_t remaining_rx_buffer_length;
-	/** Remaining dummy characters to send when reading */
-	volatile uint16_t remaining_dummy_buffer_length;
-	/** Remaining characters to transmit */
-	volatile uint16_t remaining_tx_buffer_length;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback;
-	/** Holds the status of the ongoing or last operation */
-	volatile enum status_code status;
+    /** Direction of transaction */
+    volatile enum _spi_direction dir;
+    /** Array to store callback function pointers in */
+    spi_callback_t callback[SPI_CALLBACK_N];
+    /** Buffer pointer to where the next received character will be put */
+    volatile uint8_t *rx_buffer_ptr;
+    /** Buffer pointer to where the next character will be transmitted from
+    **/
+    volatile uint8_t *tx_buffer_ptr;
+    /** Remaining characters to receive */
+    volatile uint16_t remaining_rx_buffer_length;
+    /** Remaining dummy characters to send when reading */
+    volatile uint16_t remaining_dummy_buffer_length;
+    /** Remaining characters to transmit */
+    volatile uint16_t remaining_tx_buffer_length;
+    /** Bit mask for callbacks registered */
+    uint8_t registered_callback;
+    /** Bit mask for callbacks enabled */
+    uint8_t enabled_callback;
+    /** Holds the status of the ongoing or last operation */
+    volatile enum status_code status;
 #  endif
 #  endif
 };
@@ -744,12 +744,12 @@ struct spi_module {
  * \ref spi_select_slave.
  */
 struct spi_slave_inst {
-	/** Pin to use as slave select */
-	uint8_t ss_pin;
-	/** Address recognition enabled in slave device */
-	bool address_enabled;
-	/** Address of slave device */
-	uint8_t address;
+    /** Pin to use as slave select */
+    uint8_t ss_pin;
+    /** Address recognition enabled in slave device */
+    bool address_enabled;
+    /** Address of slave device */
+    uint8_t address;
 };
 
 /**
@@ -758,12 +758,12 @@ struct spi_slave_inst {
  * SPI Peripheral slave configuration structure.
  */
 struct spi_slave_inst_config {
-	/** Pin to use as slave select */
-	uint8_t ss_pin;
-	/** Enable address */
-	bool address_enabled;
-	/** Address of slave */
-	uint8_t address;
+    /** Pin to use as slave select */
+    uint8_t ss_pin;
+    /** Enable address */
+    bool address_enabled;
+    /** Address of slave */
+    uint8_t address;
 };
 
 /**
@@ -772,8 +772,8 @@ struct spi_slave_inst_config {
  * SPI Master configuration structure.
  */
 struct spi_master_config {
-	/** Baud rate */
-	uint32_t baudrate;
+    /** Baud rate */
+    uint32_t baudrate;
 };
 
 /**
@@ -782,16 +782,16 @@ struct spi_master_config {
  * SPI slave configuration structure.
  */
 struct spi_slave_config {
-	/** Frame format */
-	enum spi_frame_format frame_format;
-	/** Address mode */
-	enum spi_addr_mode address_mode;
-	/** Address */
-	uint8_t address;
-	/** Address mask */
-	uint8_t address_mask;
-	/** Preload data to the shift register while SS is high */
-	bool preload_enable;
+    /** Frame format */
+    enum spi_frame_format frame_format;
+    /** Address mode */
+    enum spi_addr_mode address_mode;
+    /** Address */
+    uint8_t address;
+    /** Address mask */
+    uint8_t address_mask;
+    /** Preload data to the shift register while SS is high */
+    bool preload_enable;
 };
 
 /**
@@ -802,45 +802,45 @@ struct spi_slave_config {
  * modified by the user application.
  */
 struct spi_config {
-	/** SPI mode */
-	enum spi_mode mode;
-	/** Data order */
-	enum spi_data_order data_order;
-	/** Transfer mode */
-	enum spi_transfer_mode transfer_mode;
-	/** MUX setting */
-	enum spi_signal_mux_setting mux_setting;
-	/** SPI character size */
-	enum spi_character_size character_size;
-	/** Enabled in sleep modes */
-	bool run_in_standby;
-	/** Enable receiver */
-	bool receiver_enable;
+    /** SPI mode */
+    enum spi_mode mode;
+    /** Data order */
+    enum spi_data_order data_order;
+    /** Transfer mode */
+    enum spi_transfer_mode transfer_mode;
+    /** MUX setting */
+    enum spi_signal_mux_setting mux_setting;
+    /** SPI character size */
+    enum spi_character_size character_size;
+    /** Enabled in sleep modes */
+    bool run_in_standby;
+    /** Enable receiver */
+    bool receiver_enable;
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	/** Enable Slave Select Low Detect */
-	bool select_slave_low_detect_enable;
+    /** Enable Slave Select Low Detect */
+    bool select_slave_low_detect_enable;
 #  endif
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	/** Enable Master Slave Select */
-	bool master_slave_select_enable;
+    /** Enable Master Slave Select */
+    bool master_slave_select_enable;
 #  endif
-	/** Union for slave or master specific configuration */
-	union {
-		/** Slave specific configuration */
-		struct spi_slave_config slave;
-		/** Master specific configuration */
-		struct spi_master_config master;
-	} mode_specific;
-	/** GCLK generator to use as clock source */
-	enum gclk_generator generator_source;
-	/** PAD0 pinmux */
-	uint32_t pinmux_pad0;
-	/** PAD1 pinmux */
-	uint32_t pinmux_pad1;
-	/** PAD2 pinmux */
-	uint32_t pinmux_pad2;
-	/** PAD3 pinmux */
-	uint32_t pinmux_pad3;
+    /** Union for slave or master specific configuration */
+    union {
+        /** Slave specific configuration */
+        struct spi_slave_config slave;
+        /** Master specific configuration */
+        struct spi_master_config master;
+    } mode_specific;
+    /** GCLK generator to use as clock source */
+    enum gclk_generator generator_source;
+    /** PAD0 pinmux */
+    uint32_t pinmux_pad0;
+    /** PAD1 pinmux */
+    uint32_t pinmux_pad1;
+    /** PAD2 pinmux */
+    uint32_t pinmux_pad2;
+    /** PAD3 pinmux */
+    uint32_t pinmux_pad3;
 };
 
 /**
@@ -859,20 +859,20 @@ struct spi_config {
  *
  */
 static inline bool spi_is_syncing(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
 #  ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2
-	/* Return synchronization status */
-	return (spi_module->SYNCBUSY.reg);
+    /* Return synchronization status */
+    return (spi_module->SYNCBUSY.reg);
 #  else
-	/* Return synchronization status */
-	return (spi_module->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY);
+    /* Return synchronization status */
+    return (spi_module->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY);
 #  endif
 }
 
@@ -904,38 +904,38 @@ static inline bool spi_is_syncing(
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void spi_get_config_defaults(
-		struct spi_config *const config)
+        struct spi_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->mode             = SPI_MODE_MASTER;
-	config->data_order       = SPI_DATA_ORDER_MSB;
-	config->transfer_mode    = SPI_TRANSFER_MODE_0;
-	config->mux_setting      = SPI_SIGNAL_MUX_SETTING_D;
-	config->character_size   = SPI_CHARACTER_SIZE_8BIT;
-	config->run_in_standby   = false;
-	config->receiver_enable  = true;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->mode             = SPI_MODE_MASTER;
+    config->data_order       = SPI_DATA_ORDER_MSB;
+    config->transfer_mode    = SPI_TRANSFER_MODE_0;
+    config->mux_setting      = SPI_SIGNAL_MUX_SETTING_D;
+    config->character_size   = SPI_CHARACTER_SIZE_8BIT;
+    config->run_in_standby   = false;
+    config->receiver_enable  = true;
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-	config->select_slave_low_detect_enable= true;
+    config->select_slave_low_detect_enable= true;
 #  endif
 #  ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT
-	config->master_slave_select_enable= false;
+    config->master_slave_select_enable= false;
 #  endif
-	config->generator_source = GCLK_GENERATOR_0;
+    config->generator_source = GCLK_GENERATOR_0;
 
-	/* Clear mode specific config */
-	memset(&(config->mode_specific), 0, sizeof(config->mode_specific));
+    /* Clear mode specific config */
+    memset(&(config->mode_specific), 0, sizeof(config->mode_specific));
 
-	/* Master config defaults */
-	config->mode_specific.master.baudrate = 100000;
+    /* Master config defaults */
+    config->mode_specific.master.baudrate = 100000;
 
-	/* pinmux config defaults */
-	config->pinmux_pad0 = PINMUX_DEFAULT;
-	config->pinmux_pad1 = PINMUX_DEFAULT;
-	config->pinmux_pad2 = PINMUX_DEFAULT;
-	config->pinmux_pad3 = PINMUX_DEFAULT;
+    /* pinmux config defaults */
+    config->pinmux_pad0 = PINMUX_DEFAULT;
+    config->pinmux_pad1 = PINMUX_DEFAULT;
+    config->pinmux_pad2 = PINMUX_DEFAULT;
+    config->pinmux_pad3 = PINMUX_DEFAULT;
 
 };
 
@@ -954,13 +954,13 @@ static inline void spi_get_config_defaults(
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void spi_slave_inst_get_config_defaults(
-		struct spi_slave_inst_config *const config)
+        struct spi_slave_inst_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->ss_pin          = 10;
-	config->address_enabled = false;
-	config->address         = 0;
+    config->ss_pin          = 10;
+    config->address_enabled = false;
+    config->address         = 0;
 }
 
 /**
@@ -975,32 +975,32 @@ static inline void spi_slave_inst_get_config_defaults(
  *
  */
 static inline void spi_attach_slave(
-		struct spi_slave_inst *const slave,
-		const struct spi_slave_inst_config *const config)
+        struct spi_slave_inst *const slave,
+        const struct spi_slave_inst_config *const config)
 {
-	Assert(slave);
-	Assert(config);
+    Assert(slave);
+    Assert(config);
 
-	slave->ss_pin          = config->ss_pin;
-	slave->address_enabled = config->address_enabled;
-	slave->address         = config->address;
+    slave->ss_pin          = config->ss_pin;
+    slave->address_enabled = config->address_enabled;
+    slave->address         = config->address;
 
-	/* Get default config for pin */
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
+    /* Get default config for pin */
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
 
-	/* Edit config to set the pin as output */
-	pin_conf.direction = PORT_PIN_DIR_OUTPUT;
+    /* Edit config to set the pin as output */
+    pin_conf.direction = PORT_PIN_DIR_OUTPUT;
 
-	/* Set config on Slave Select pin */
-	port_pin_set_config(slave->ss_pin, &pin_conf);
-	port_pin_set_output_level(slave->ss_pin, true);
+    /* Set config on Slave Select pin */
+    port_pin_set_config(slave->ss_pin, &pin_conf);
+    port_pin_set_output_level(slave->ss_pin, true);
 }
 
 enum status_code spi_init(
-		struct spi_module *const module,
-		Sercom *const hw,
-		const struct spi_config *const config);
+        struct spi_module *const module,
+        Sercom *const hw,
+        const struct spi_config *const config);
 
 /** @} */
 
@@ -1017,24 +1017,25 @@ enum status_code spi_init(
  * \param[in,out] module  Pointer to the software instance struct
  */
 static inline void spi_enable(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
 #  if SPI_CALLBACK_MODE == true
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
 #  endif
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Enable SPI */
-	spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+    /* Enable SPI */
+    spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
 }
 
 /**
@@ -1045,39 +1046,40 @@ static inline void spi_enable(
  * \param[in,out] module  Pointer to the software instance struct
  */
 static inline void spi_disable(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
 #  if SPI_CALLBACK_MODE == true
-	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+    system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
 #  endif
 
-	while (spi_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (spi_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 
-	/* Disbale interrupt */
-	spi_module->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	spi_module->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
+    /* Disbale interrupt */
+    spi_module->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    spi_module->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
 
-	/* Disable SPI */
-	spi_module->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+    /* Disable SPI */
+    spi_module->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
 }
 
 void spi_reset(
-		struct spi_module *const module);
+        struct spi_module *const module);
 
 /** @} */
 
 enum status_code spi_set_baudrate(
-		struct spi_module *const module,
-		uint32_t baudrate);
+        struct spi_module *const module,
+        uint32_t baudrate);
 
 /**
  * \name Lock/Unlock
@@ -1101,20 +1103,21 @@ enum status_code spi_set_baudrate(
  */
 static inline enum status_code spi_lock(struct spi_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return status;
+    return status;
 }
 
 /**
@@ -1130,7 +1133,7 @@ static inline enum status_code spi_lock(struct spi_module *const module)
  */
 static inline void spi_unlock(struct spi_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /** @} */
@@ -1155,16 +1158,16 @@ static inline void spi_unlock(struct spi_module *const module)
  * \retval false  If the SPI master module has not shifted out data
  */
 static inline bool spi_is_write_complete(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Check interrupt flag */
-	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
+    /* Check interrupt flag */
+    return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC);
 }
 
  /**
@@ -1179,16 +1182,16 @@ static inline bool spi_is_write_complete(
  * \retval false  If the SPI module is not ready to write data
  */
 static inline bool spi_is_ready_to_write(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Check interrupt flag */
-	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
+    /* Check interrupt flag */
+    return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE);
 }
 
 /**
@@ -1203,16 +1206,16 @@ static inline bool spi_is_ready_to_write(
  * \retval false  If the SPI module is not ready to read data
  */
 static inline bool spi_is_ready_to_read(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Check interrupt flag */
-	return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
+    /* Check interrupt flag */
+    return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC);
 }
 /** @} */
 
@@ -1244,31 +1247,32 @@ static inline bool spi_is_ready_to_read(
  * \retval STATUS_BUSY  If the last write was not completed
  */
 static inline enum status_code spi_write(
-		struct spi_module *module,
-		uint16_t tx_data)
+        struct spi_module *module,
+        uint16_t tx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomSpi *const spi_module = &(module->hw->SPI);
+    SercomSpi *const spi_module = &(module->hw->SPI);
 
-	/* Check if the data register has been copied to the shift register */
-	if (!spi_is_ready_to_write(module)) {
-		/* Data register has not been copied to the shift register, return */
-		return STATUS_BUSY;
-	}
+    /* Check if the data register has been copied to the shift register */
+    if (!spi_is_ready_to_write(module))
+    {
+        /* Data register has not been copied to the shift register, return */
+        return STATUS_BUSY;
+    }
 
-	/* Write the character to the DATA register */
-	spi_module->DATA.reg = tx_data & SERCOM_SPI_DATA_MASK;
+    /* Write the character to the DATA register */
+    spi_module->DATA.reg = tx_data & SERCOM_SPI_DATA_MASK;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 enum status_code spi_write_buffer_wait(
-		struct spi_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        const uint8_t *tx_data,
+        uint16_t length);
 
 /**
  * \brief Reads last received SPI character
@@ -1290,62 +1294,65 @@ enum status_code spi_write_buffer_wait(
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 static inline enum status_code spi_read(
-		struct spi_module *const module,
-		uint16_t *rx_data)
+        struct spi_module *const module,
+        uint16_t *rx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	SercomSpi *const spi_module = &(module->hw->SPI);
-
-	/* Check if data is ready to be read */
-	if (!spi_is_ready_to_read(module)) {
-		/* No data has been received, return */
-		return STATUS_ERR_IO;
-	}
-
-	/* Return value */
-	enum status_code retval = STATUS_OK;
-
-	/* Check if data is overflown */
-	if (spi_module->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
-		retval = STATUS_ERR_OVERFLOW;
-		/* Clear overflow flag */
-		spi_module->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
-	}
-
-	/* Read the character from the DATA register */
-	if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-		*rx_data = (spi_module->DATA.reg & SERCOM_SPI_DATA_MASK);
-	} else {
-		*rx_data = (uint8_t)spi_module->DATA.reg;
-	}
-
-	return retval;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    SercomSpi *const spi_module = &(module->hw->SPI);
+
+    /* Check if data is ready to be read */
+    if (!spi_is_ready_to_read(module))
+    {
+        /* No data has been received, return */
+        return STATUS_ERR_IO;
+    }
+
+    /* Return value */
+    enum status_code retval = STATUS_OK;
+
+    /* Check if data is overflown */
+    if (spi_module->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF)
+    {
+        retval = STATUS_ERR_OVERFLOW;
+        /* Clear overflow flag */
+        spi_module->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+    }
+
+    /* Read the character from the DATA register */
+    if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+    {
+        *rx_data = (spi_module->DATA.reg & SERCOM_SPI_DATA_MASK);
+    } else {
+        *rx_data = (uint8_t)spi_module->DATA.reg;
+    }
+
+    return retval;
 }
 
 enum status_code spi_read_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy);
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy);
 
 enum status_code spi_transceive_wait(
-		struct spi_module *const module,
-		uint16_t tx_data,
-		uint16_t *rx_data);
+        struct spi_module *const module,
+        uint16_t tx_data,
+        uint16_t *rx_data);
 
 enum status_code spi_transceive_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length);
 
 enum status_code spi_select_slave(
-		struct spi_module *const module,
-		struct spi_slave_inst *const slave,
-		bool select);
+        struct spi_module *const module,
+        struct spi_slave_inst *const slave,
+        bool select);
 
 /** @} */
 
@@ -1364,50 +1371,50 @@ enum status_code spi_select_slave(
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>Serial Communication Interface</td>
- *	</tr>
- *	<tr>
- *		<td>SPI</td>
- *		<td>Serial Peripheral Interface</td>
- *	</tr>
- *	<tr>
- *		<td>SCK</td>
- *		<td>Serial Clock</td>
- *	</tr>
- *	<tr>
- *		<td>MOSI</td>
- *		<td>Master Output Slave Input</td>
- *	</tr>
- *	<tr>
- *		<td>MISO</td>
- *		<td>Master Input Slave Output</td>
- *	</tr>
- *	<tr>
- *		<td>SS</td>
- *		<td>Slave Select</td>
- *	</tr>
- *	<tr>
- *		<td>DIO</td>
- *		<td>Data Input Output</td>
- *	</tr>
- *	<tr>
- *		<td>DO</td>
- *		<td>Data Output</td>
- *	</tr>
- *	<tr>
- *		<td>DI</td>
- *		<td>Data Input</td>
- *	</tr>
- *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SERCOM</td>
+ *      <td>Serial Communication Interface</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SPI</td>
+ *      <td>Serial Peripheral Interface</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SCK</td>
+ *      <td>Serial Clock</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MOSI</td>
+ *      <td>Master Output Slave Input</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MISO</td>
+ *      <td>Master Input Slave Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SS</td>
+ *      <td>Slave Select</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DIO</td>
+ *      <td>Data Input Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DO</td>
+ *      <td>Data Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DI</td>
+ *      <td>Data Input</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_sam0_sercom_spi_extra_dependencies Dependencies
@@ -1424,26 +1431,26 @@ enum status_code spi_select_slave(
  * release. The current version of this corresponds to the newest version in the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added new features as below:
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new features as below:
  *             \li Slave select low detect
  *             \li Hardware slave select
  *             \li DMA support </td>
- *	</tr>
- *	<tr>
- *		<td>Edited slave part of write and transceive buffer functions to ensure
- *		that second character is sent at the right time</td>
- *	</tr>
- *	<tr>
- *		<td>Renamed the anonymous union in \c struct spi_config to
+ *  </tr>
+ *  <tr>
+ *      <td>Edited slave part of write and transceive buffer functions to ensure
+ *      that second character is sent at the right time</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Renamed the anonymous union in \c struct spi_config to
  *          \c mode_specific</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1482,142 +1489,142 @@ enum status_code spi_select_slave(
   *       given MUX setting.
   *
   * <table>
-  *		<tr>
-  *			<th>Combination</th>
-  *			<th>DOPO / DIPO</th>
-  *			<th>SERCOM PAD[0]</th>
-  *			<th>SERCOM PAD[1]</th>
-  *			<th>SERCOM PAD[2]</th>
-  *			<th>SERCOM PAD[3]</th>
-  *		</tr>
-  *		<tr>
-  *			<td>A</td>
-  *			<td>0x0 / 0x0</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>B</td>
-  *			<td>0x0 / 0x1</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>C</td>
-  *			<td>0x0 / 0x2</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *			<td>MISO</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>D</td>
-  *			<td>0x0 / 0x3</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>MISO</td>
-  *		</tr>
-  *		<tr>
-  *			<td>E</td>
-  *			<td>0x1 / 0x0</td>
-  *			<td>MISO</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>F</td>
-  *			<td>0x1 / 0x1</td>
-  *			<td>-</td>
-  *			<td>MISO</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>G</td>
-  *			<td>0x1 / 0x2</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>H</td>
-  *			<td>0x1 / 0x3</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>I</td>
-  *			<td>0x2 / 0x0</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *		</tr>
-  *		<tr>
-  *			<td>J</td>
-  *			<td>0x2 / 0x1</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *		</tr>
-  *		<tr>
-  *			<td>K</td>
-  *			<td>0x2 / 0x2</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>MISO</td>
-  *			<td>MOSI</td>
-  *		</tr>
-  *		<tr>
-  *			<td>L</td>
-  *			<td>0x2 / 0x3</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>-</td>
-  *			<td>MOSI</td>
-  *		</tr>
-  *		<tr>
-  *			<td>M</td>
-  *			<td>0x3 / 0x0</td>
-  *			<td>MOSI</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>N</td>
-  *			<td>0x3 / 0x1</td>
-  *			<td>MOSI</td>
-  *			<td>MISO</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>O</td>
-  *			<td>0x3 / 0x2</td>
-  *			<td>MOSI</td>
-  *			<td>-</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>P</td>
-  *			<td>0x3 / 0x3</td>
-  *			<td>MOSI</td>
-  *			<td>-</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
+  *     <tr>
+  *         <th>Combination</th>
+  *         <th>DOPO / DIPO</th>
+  *         <th>SERCOM PAD[0]</th>
+  *         <th>SERCOM PAD[1]</th>
+  *         <th>SERCOM PAD[2]</th>
+  *         <th>SERCOM PAD[3]</th>
+  *     </tr>
+  *     <tr>
+  *         <td>A</td>
+  *         <td>0x0 / 0x0</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>B</td>
+  *         <td>0x0 / 0x1</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>C</td>
+  *         <td>0x0 / 0x2</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *         <td>MISO</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>D</td>
+  *         <td>0x0 / 0x3</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>MISO</td>
+  *     </tr>
+  *     <tr>
+  *         <td>E</td>
+  *         <td>0x1 / 0x0</td>
+  *         <td>MISO</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>F</td>
+  *         <td>0x1 / 0x1</td>
+  *         <td>-</td>
+  *         <td>MISO</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>G</td>
+  *         <td>0x1 / 0x2</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>H</td>
+  *         <td>0x1 / 0x3</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>I</td>
+  *         <td>0x2 / 0x0</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *     </tr>
+  *     <tr>
+  *         <td>J</td>
+  *         <td>0x2 / 0x1</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *     </tr>
+  *     <tr>
+  *         <td>K</td>
+  *         <td>0x2 / 0x2</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>MISO</td>
+  *         <td>MOSI</td>
+  *     </tr>
+  *     <tr>
+  *         <td>L</td>
+  *         <td>0x2 / 0x3</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>-</td>
+  *         <td>MOSI</td>
+  *     </tr>
+  *     <tr>
+  *         <td>M</td>
+  *         <td>0x3 / 0x0</td>
+  *         <td>MOSI</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>N</td>
+  *         <td>0x3 / 0x1</td>
+  *         <td>MOSI</td>
+  *         <td>MISO</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>O</td>
+  *         <td>0x3 / 0x2</td>
+  *         <td>MOSI</td>
+  *         <td>-</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>P</td>
+  *         <td>0x3 / 0x3</td>
+  *         <td>MOSI</td>
+  *         <td>-</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
   * </table>
   *
   *
@@ -1629,142 +1636,142 @@ enum status_code spi_select_slave(
   *       given MUX setting.
   *
   * <table>
-  *		<tr>
-  *			<th>Combination</th>
-  *			<th>DOPO / DIPO</th>
-  *			<th>SERCOM PAD[0]</th>
-  *			<th>SERCOM PAD[1]</th>
-  *			<th>SERCOM PAD[2]</th>
-  *			<th>SERCOM PAD[3]</th>
-  *		</tr>
-  *		<tr>
-  *			<td>A</td>
-  *			<td>0x0 / 0x0</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>B</td>
-  *			<td>0x0 / 0x1</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>C</td>
-  *			<td>0x0 / 0x2</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *		</tr>
-  *		<tr>
-  *			<td>D</td>
-  *			<td>0x0 / 0x3</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>MOSI</td>
-  *		</tr>
-  *		<tr>
-  *			<td>E</td>
-  *			<td>0x1 / 0x0</td>
-  *			<td>MOSI</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>F</td>
-  *			<td>0x1 / 0x1</td>
-  *			<td>-</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>G</td>
-  *			<td>0x1 / 0x2</td>
-  *			<td>-</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>H</td>
-  *			<td>0x1 / 0x3</td>
-  *			<td>-</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>I</td>
-  *			<td>0x2 / 0x0</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *		</tr>
-  *		<tr>
-  *			<td>J</td>
-  *			<td>0x2 / 0x1</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *		</tr>
-  *		<tr>
-  *			<td>K</td>
-  *			<td>0x2 / 0x2</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *		</tr>
-  *		<tr>
-  *			<td>L</td>
-  *			<td>0x2 / 0x3</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *			<td>/SS</td>
-  *			<td>MISO</td>
-  *		</tr>
-  *		<tr>
-  *			<td>M</td>
-  *			<td>0x3 / 0x0</td>
-  *			<td>MISO</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>N</td>
-  *			<td>0x3 / 0x1</td>
-  *			<td>MISO</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>O</td>
-  *			<td>0x3 / 0x2</td>
-  *			<td>MISO</td>
-  *			<td>/SS</td>
-  *			<td>MOSI</td>
-  *			<td>SCK</td>
-  *		</tr>
-  *		<tr>
-  *			<td>P</td>
-  *			<td>0x3 / 0x3</td>
-  *			<td>MISO</td>
-  *			<td>/SS</td>
-  *			<td>-</td>
-  *			<td>SCK</td>
-  *		</tr>
+  *     <tr>
+  *         <th>Combination</th>
+  *         <th>DOPO / DIPO</th>
+  *         <th>SERCOM PAD[0]</th>
+  *         <th>SERCOM PAD[1]</th>
+  *         <th>SERCOM PAD[2]</th>
+  *         <th>SERCOM PAD[3]</th>
+  *     </tr>
+  *     <tr>
+  *         <td>A</td>
+  *         <td>0x0 / 0x0</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>B</td>
+  *         <td>0x0 / 0x1</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>C</td>
+  *         <td>0x0 / 0x2</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *     </tr>
+  *     <tr>
+  *         <td>D</td>
+  *         <td>0x0 / 0x3</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>MOSI</td>
+  *     </tr>
+  *     <tr>
+  *         <td>E</td>
+  *         <td>0x1 / 0x0</td>
+  *         <td>MOSI</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>F</td>
+  *         <td>0x1 / 0x1</td>
+  *         <td>-</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>G</td>
+  *         <td>0x1 / 0x2</td>
+  *         <td>-</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>H</td>
+  *         <td>0x1 / 0x3</td>
+  *         <td>-</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>I</td>
+  *         <td>0x2 / 0x0</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *     </tr>
+  *     <tr>
+  *         <td>J</td>
+  *         <td>0x2 / 0x1</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *     </tr>
+  *     <tr>
+  *         <td>K</td>
+  *         <td>0x2 / 0x2</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *     </tr>
+  *     <tr>
+  *         <td>L</td>
+  *         <td>0x2 / 0x3</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *         <td>/SS</td>
+  *         <td>MISO</td>
+  *     </tr>
+  *     <tr>
+  *         <td>M</td>
+  *         <td>0x3 / 0x0</td>
+  *         <td>MISO</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>N</td>
+  *         <td>0x3 / 0x1</td>
+  *         <td>MISO</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>O</td>
+  *         <td>0x3 / 0x2</td>
+  *         <td>MISO</td>
+  *         <td>/SS</td>
+  *         <td>MOSI</td>
+  *         <td>SCK</td>
+  *     </tr>
+  *     <tr>
+  *         <td>P</td>
+  *         <td>0x3 / 0x3</td>
+  *         <td>MISO</td>
+  *         <td>/SS</td>
+  *         <td>-</td>
+  *         <td>SCK</td>
+  *     </tr>
   * </table>
   *
   *
@@ -1772,36 +1779,36 @@ enum status_code spi_select_slave(
   * \page asfdoc_sam0_sercom_spi_document_revision_history Document Revision History
   *
   * <table>
-  *	<tr>
-  *		<th>Doc. Rev.</th>
-  *		<th>Date</th>
-  *		<th>Comments</th>
-  *	</tr>
-  *	<tr>
-  *		<td>42115E</td>
-  *		<td>12/2015</td>
-  *		<td>Add SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C21 support</td>
-  *	</tr>
-  *	<tr>
-  *		<td>42115D</td>
-  *		<td>12/2014</td>
-  *		<td>Add SAM R21/D10/D11 support</td>
-  *	</tr>
-  *	<tr>
-  *		<td>42115C</td>
-  *		<td>01/2014</td>
-  *		<td>Add SAM D21 support</td>
-  *	</tr>
-  *	<tr>
-  *		<td>42115B</td>
-  *		<td>11/2013</td>
-  *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
-  *	</tr>
-  *	<tr>
-  *		<td>42115A</td>
-  *		<td>06/2013</td>
-  *		<td>Initial release</td>
-  *	</tr>
+  * <tr>
+  *     <th>Doc. Rev.</th>
+  *     <th>Date</th>
+  *     <th>Comments</th>
+  * </tr>
+  * <tr>
+  *     <td>42115E</td>
+  *     <td>12/2015</td>
+  *     <td>Add SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C21 support</td>
+  * </tr>
+  * <tr>
+  *     <td>42115D</td>
+  *     <td>12/2014</td>
+  *     <td>Add SAM R21/D10/D11 support</td>
+  * </tr>
+  * <tr>
+  *     <td>42115C</td>
+  *     <td>01/2014</td>
+  *     <td>Add SAM D21 support</td>
+  * </tr>
+  * <tr>
+  *     <td>42115B</td>
+  *     <td>11/2013</td>
+  *     <td>Replaced the pad multiplexing documentation with a condensed table</td>
+  * </tr>
+  * <tr>
+  *     <td>42115A</td>
+  *     <td>06/2013</td>
+  *     <td>Initial release</td>
+  * </tr>
   * </table>
   */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c
index 5909843b2d44..ffe3205c6933 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.c
@@ -63,37 +63,38 @@ uint16_t dummy_write;
  *
  */
 static void _spi_transceive_buffer(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-	module->remaining_rx_buffer_length = length;
-	module->rx_buffer_ptr = rx_data;
-	module->tx_buffer_ptr = tx_data;
-	module->status = STATUS_BUSY;
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
+    module->remaining_rx_buffer_length = length;
+    module->rx_buffer_ptr = rx_data;
+    module->tx_buffer_ptr = tx_data;
+    module->status = STATUS_BUSY;
 
-	module->dir = SPI_DIRECTION_BOTH;
+    module->dir = SPI_DIRECTION_BOTH;
 
-	/* Get a pointer to the hardware module instance */
-	SercomSpi *const hw = &(module->hw->SPI);
+    /* Get a pointer to the hardware module instance */
+    SercomSpi *const hw = &(module->hw->SPI);
 
-	/* Enable the Data Register Empty and RX Complete Interrupt */
-	hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
-			SPI_INTERRUPT_FLAG_RX_COMPLETE);
+    /* Enable the Data Register Empty and RX Complete Interrupt */
+    hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+            SPI_INTERRUPT_FLAG_RX_COMPLETE);
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (module->mode == SPI_MODE_SLAVE) {
-		/* Clear TXC flag if set */
-		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-		/* Enable transmit complete interrupt for slave */
-		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-	}
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        /* Clear TXC flag if set */
+        hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+        /* Enable transmit complete interrupt for slave */
+        hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+    }
 #  endif
 }
 
@@ -107,41 +108,43 @@ static void _spi_transceive_buffer(
  *
  */
 static void _spi_write_buffer(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-	module->remaining_dummy_buffer_length = length;
-	module->tx_buffer_ptr = tx_data;
-	module->status = STATUS_BUSY;
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
+    module->remaining_dummy_buffer_length = length;
+    module->tx_buffer_ptr = tx_data;
+    module->status = STATUS_BUSY;
 
-	module->dir = SPI_DIRECTION_WRITE;
+    module->dir = SPI_DIRECTION_WRITE;
 
-	/* Get a pointer to the hardware module instance */
-	SercomSpi *const hw = &(module->hw->SPI);
+    /* Get a pointer to the hardware module instance */
+    SercomSpi *const hw = &(module->hw->SPI);
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (module->mode == SPI_MODE_SLAVE) {
-		/* Clear TXC flag if set */
-		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-		/* Enable transmit complete interrupt for slave */
-		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-	}
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        /* Clear TXC flag if set */
+        hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+        /* Enable transmit complete interrupt for slave */
+        hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+    }
 #  endif
 
-	if (module->receiver_enabled) {
-		/* Enable the Data Register Empty and RX Complete interrupt */
-		hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
-				SPI_INTERRUPT_FLAG_RX_COMPLETE);
-	} else {
-		/* Enable the Data Register Empty interrupt */
-		hw->INTENSET.reg = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-	}
+    if (module->receiver_enabled)
+    {
+        /* Enable the Data Register Empty and RX Complete interrupt */
+        hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+                SPI_INTERRUPT_FLAG_RX_COMPLETE);
+    } else {
+        /* Enable the Data Register Empty interrupt */
+        hw->INTENSET.reg = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+    }
 }
 
 /**
@@ -154,55 +157,57 @@ static void _spi_write_buffer(
  *
  */
 static void _spi_read_buffer(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(rx_data);
+    Assert(module);
+    Assert(rx_data);
 
-	uint8_t tmp_intenset = 0;
+    uint8_t tmp_intenset = 0;
 
-	/* Set length for the buffer and the pointer, and let
-	 * the interrupt handler do the rest */
-	module->remaining_rx_buffer_length = length;
-	module->remaining_dummy_buffer_length = length;
-	module->rx_buffer_ptr = rx_data;
-	module->status = STATUS_BUSY;
+    /* Set length for the buffer and the pointer, and let
+     * the interrupt handler do the rest */
+    module->remaining_rx_buffer_length = length;
+    module->remaining_dummy_buffer_length = length;
+    module->rx_buffer_ptr = rx_data;
+    module->status = STATUS_BUSY;
 
-	module->dir = SPI_DIRECTION_READ;
+    module->dir = SPI_DIRECTION_READ;
 
-	/* Get a pointer to the hardware module instance */
-	SercomSpi *const hw = &(module->hw->SPI);
+    /* Get a pointer to the hardware module instance */
+    SercomSpi *const hw = &(module->hw->SPI);
 
-	/* Enable the RX Complete Interrupt */
-	tmp_intenset = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+    /* Enable the RX Complete Interrupt */
+    tmp_intenset = SPI_INTERRUPT_FLAG_RX_COMPLETE;
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	if (module->mode == SPI_MODE_MASTER && module->dir == SPI_DIRECTION_READ) {
-		/* Enable Data Register Empty interrupt for master */
-		tmp_intenset |= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-	}
+    if (module->mode == SPI_MODE_MASTER && module->dir == SPI_DIRECTION_READ)
+    {
+        /* Enable Data Register Empty interrupt for master */
+        tmp_intenset |= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+    }
 #  endif
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (module->mode == SPI_MODE_SLAVE) {
-		/* Clear TXC flag if set */
-		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-		/* Enable transmit complete interrupt for slave */
-		tmp_intenset |= SPI_INTERRUPT_FLAG_TX_COMPLETE;
-
-		/* Workaround for SSL flag enable */
+    if (module->mode == SPI_MODE_SLAVE)
+    {
+        /* Clear TXC flag if set */
+        hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+        /* Enable transmit complete interrupt for slave */
+        tmp_intenset |= SPI_INTERRUPT_FLAG_TX_COMPLETE;
+
+        /* Workaround for SSL flag enable */
 #ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
-		/* Clear SSL flag if set */
-		hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
-		/* Enable Slave Select Low Interrupt for slave */
-		tmp_intenset |= SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+        /* Clear SSL flag if set */
+        hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+        /* Enable Slave Select Low Interrupt for slave */
+        tmp_intenset |= SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
 #endif
-	}
+    }
 #  endif
 
-	/* Enable all interrupts simultaneously */
-	hw->INTENSET.reg = tmp_intenset;
+    /* Enable all interrupts simultaneously */
+    hw->INTENSET.reg = tmp_intenset;
 }
 
 /**
@@ -220,19 +225,19 @@ static void _spi_read_buffer(
  *
  */
 void spi_register_callback(
-		struct spi_module *const module,
-		spi_callback_t callback_func,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        spi_callback_t callback_func,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->registered_callback |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -245,17 +250,17 @@ void spi_register_callback(
  *
  */
 void spi_unregister_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -275,26 +280,28 @@ void spi_unregister_callback(
  * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
  */
 enum status_code spi_write_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Issue internal write */
-	_spi_write_buffer(module, tx_data, length);
+    /* Issue internal write */
+    _spi_write_buffer(module, tx_data, length);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -319,32 +326,35 @@ enum status_code spi_write_buffer_job(
  * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
  */
 enum status_code spi_read_buffer_job(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	dummy_write = dummy;
-	/* Issue internal read */
-	_spi_read_buffer(module, rx_data, length);
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    dummy_write = dummy;
+    /* Issue internal read */
+    _spi_read_buffer(module, rx_data, length);
+    return STATUS_OK;
 }
 
 /**
@@ -369,32 +379,35 @@ enum status_code spi_read_buffer_job(
  * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
  */
 enum status_code spi_transceive_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Issue internal transceive */
-	_spi_transceive_buffer(module, tx_data, rx_data, length);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Issue internal transceive */
+    _spi_transceive_buffer(module, tx_data, rx_data, length);
+
+    return STATUS_OK;
 }
 /**
  * \brief Aborts an ongoing job
@@ -404,25 +417,25 @@ enum status_code spi_transceive_buffer_job(
  * \param[in]  module    Pointer to SPI software instance struct
  */
 void spi_abort_job(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw
-		= &(module->hw->SPI);
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw
+        = &(module->hw->SPI);
 
-	/* Abort ongoing job */
+    /* Abort ongoing job */
 
-	/* Disable interrupts */
-	spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
-			SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
-			SPI_INTERRUPT_FLAG_TX_COMPLETE;
+    /* Disable interrupts */
+    spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
+            SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY |
+            SPI_INTERRUPT_FLAG_TX_COMPLETE;
 
-	module->status = STATUS_ABORTED;
-	module->remaining_rx_buffer_length = 0;
-	module->remaining_dummy_buffer_length = 0;
-	module->remaining_tx_buffer_length = 0;
+    module->status = STATUS_ABORTED;
+    module->remaining_rx_buffer_length = 0;
+    module->remaining_dummy_buffer_length = 0;
+    module->remaining_tx_buffer_length = 0;
 
-	module->dir = SPI_DIRECTION_IDLE;
+    module->dir = SPI_DIRECTION_IDLE;
 }
 
 #  if CONF_SPI_SLAVE_ENABLE == true || CONF_SPI_MASTER_ENABLE == true
@@ -433,27 +446,28 @@ void spi_abort_job(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_write(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw = &(module->hw->SPI);
-
-	/* Write value will be at least 8-bits long */
-	uint16_t data_to_send = *(module->tx_buffer_ptr);
-	/* Increment 8-bit pointer */
-	(module->tx_buffer_ptr)++;
-
-	if (module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-		data_to_send |= ((*(module->tx_buffer_ptr)) << 8);
-		/* Increment 8-bit pointer */
-		(module->tx_buffer_ptr)++;
-	}
-
-	/* Write the data to send*/
-	spi_hw->DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK;
-
-	/* Decrement remaining buffer length */
-	(module->remaining_tx_buffer_length)--;
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw = &(module->hw->SPI);
+
+    /* Write value will be at least 8-bits long */
+    uint16_t data_to_send = *(module->tx_buffer_ptr);
+    /* Increment 8-bit pointer */
+    (module->tx_buffer_ptr)++;
+
+    if (module->character_size == SPI_CHARACTER_SIZE_9BIT)
+    {
+        data_to_send |= ((*(module->tx_buffer_ptr)) << 8);
+        /* Increment 8-bit pointer */
+        (module->tx_buffer_ptr)++;
+    }
+
+    /* Write the data to send*/
+    spi_hw->DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK;
+
+    /* Decrement remaining buffer length */
+    (module->remaining_tx_buffer_length)--;
 }
 #  endif
 
@@ -465,16 +479,16 @@ static void _spi_write(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_write_dummy(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw = &(module->hw->SPI);
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw = &(module->hw->SPI);
 
-	/* Write dummy byte */
-	spi_hw->DATA.reg = dummy_write;
+    /* Write dummy byte */
+    spi_hw->DATA.reg = dummy_write;
 
-	/* Decrement remaining dummy buffer length */
-	module->remaining_dummy_buffer_length--;
+    /* Decrement remaining dummy buffer length */
+    module->remaining_dummy_buffer_length--;
 }
 #  endif
 
@@ -485,18 +499,18 @@ static void _spi_write_dummy(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_read_dummy(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw = &(module->hw->SPI);
-	uint16_t flush = 0;
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw = &(module->hw->SPI);
+    uint16_t flush = 0;
 
-	/* Read dummy byte */
-	flush = spi_hw->DATA.reg;
-	UNUSED(flush);
+    /* Read dummy byte */
+    flush = spi_hw->DATA.reg;
+    UNUSED(flush);
 
-	/* Decrement remaining dummy buffer length */
-	module->remaining_dummy_buffer_length--;
+    /* Decrement remaining dummy buffer length */
+    module->remaining_dummy_buffer_length--;
 }
 
 /**
@@ -506,27 +520,28 @@ static void _spi_read_dummy(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_read(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw = &(module->hw->SPI);
-
-	uint16_t received_data = (spi_hw->DATA.reg & SERCOM_SPI_DATA_MASK);
-
-	/* Read value will be at least 8-bits long */
-	*(module->rx_buffer_ptr) = received_data;
-	/* Increment 8-bit pointer */
-	module->rx_buffer_ptr += 1;
-
-	if(module->character_size == SPI_CHARACTER_SIZE_9BIT) {
-		/* 9-bit data, write next received byte to the buffer */
-		*(module->rx_buffer_ptr) = (received_data >> 8);
-		/* Increment 8-bit pointer */
-		module->rx_buffer_ptr += 1;
-	}
-
-	/* Decrement length of the remaining buffer */
-	module->remaining_rx_buffer_length--;
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw = &(module->hw->SPI);
+
+    uint16_t received_data = (spi_hw->DATA.reg & SERCOM_SPI_DATA_MASK);
+
+    /* Read value will be at least 8-bits long */
+    *(module->rx_buffer_ptr) = received_data;
+    /* Increment 8-bit pointer */
+    module->rx_buffer_ptr += 1;
+
+    if(module->character_size == SPI_CHARACTER_SIZE_9BIT)
+    {
+        /* 9-bit data, write next received byte to the buffer */
+        *(module->rx_buffer_ptr) = (received_data >> 8);
+        /* Increment 8-bit pointer */
+        module->rx_buffer_ptr += 1;
+    }
+
+    /* Decrement length of the remaining buffer */
+    module->remaining_rx_buffer_length--;
 }
 
 /**
@@ -542,200 +557,228 @@ static void _spi_read(
  *                       handler.
  */
 void _spi_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Get device instance from the look-up table */
-	struct spi_module *module
-		= (struct spi_module *)_sercom_instances[instance];
+    /* Get device instance from the look-up table */
+    struct spi_module *module
+        = (struct spi_module *)_sercom_instances[instance];
 
-	/* Pointer to the hardware module instance */
-	SercomSpi *const spi_hw = &(module->hw->SPI);
+    /* Pointer to the hardware module instance */
+    SercomSpi *const spi_hw = &(module->hw->SPI);
 
-	/* Combine callback registered and enabled masks. */
-	uint8_t callback_mask =
-			module->enabled_callback & module->registered_callback;
+    /* Combine callback registered and enabled masks. */
+    uint8_t callback_mask =
+            module->enabled_callback & module->registered_callback;
 
-	/* Read and mask interrupt flag register */
-	uint16_t interrupt_status = spi_hw->INTFLAG.reg;
-	interrupt_status &= spi_hw->INTENSET.reg;
+    /* Read and mask interrupt flag register */
+    uint16_t interrupt_status = spi_hw->INTFLAG.reg;
+    interrupt_status &= spi_hw->INTENSET.reg;
 
-	/* Data register empty interrupt */
-	if (interrupt_status & SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY) {
+    /* Data register empty interrupt */
+    if (interrupt_status & SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY)
+    {
 #  if CONF_SPI_MASTER_ENABLE == true
-		if ((module->mode == SPI_MODE_MASTER) &&
-			(module->dir == SPI_DIRECTION_READ)) {
-			/* Send dummy byte when reading in master mode */
-			_spi_write_dummy(module);
-			if (module->remaining_dummy_buffer_length == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				spi_hw->INTENCLR.reg
-						= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-			}
-		}
+        if ((module->mode == SPI_MODE_MASTER) &&
+            (module->dir == SPI_DIRECTION_READ))
+            {
+            /* Send dummy byte when reading in master mode */
+            _spi_write_dummy(module);
+            if (module->remaining_dummy_buffer_length == 0)
+            {
+                /* Disable the Data Register Empty Interrupt */
+                spi_hw->INTENCLR.reg
+                        = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+            }
+        }
 #  endif
 
-		if (0
+        if (0
 #  if CONF_SPI_MASTER_ENABLE == true
-		|| ((module->mode == SPI_MODE_MASTER) &&
-			(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_MASTER) &&
+            (module->dir != SPI_DIRECTION_READ))
 #  endif
 #  if CONF_SPI_SLAVE_ENABLE == true
-		|| ((module->mode == SPI_MODE_SLAVE) &&
-			(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_SLAVE) &&
+            (module->dir != SPI_DIRECTION_READ))
 #  endif
-		) {
-			/* Write next byte from buffer */
-			_spi_write(module);
-			if (module->remaining_tx_buffer_length == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				spi_hw->INTENCLR.reg
-						= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-
-				if (module->dir == SPI_DIRECTION_WRITE &&
-						!(module->receiver_enabled)) {
-					/* Enable the Data Register transmit complete Interrupt */
-					spi_hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-				}
-			}
-		}
-	}
-
-	/* Receive complete interrupt*/
-	if (interrupt_status & SPI_INTERRUPT_FLAG_RX_COMPLETE) {
-		/* Check for overflow */
-		if (spi_hw->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) {
-			if (module->dir != SPI_DIRECTION_WRITE) {
-				/* Store the error code */
-				module->status = STATUS_ERR_OVERFLOW;
-
-				/* End transaction */
-				module->dir = SPI_DIRECTION_IDLE;
-
-				spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
-						SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-				/* Run callback if registered and enabled */
-				if (callback_mask & (1 << SPI_CALLBACK_ERROR)) {
-					(module->callback[SPI_CALLBACK_ERROR])(module);
-				}
-			}
-			/* Flush */
-			uint16_t flush = spi_hw->DATA.reg;
-			UNUSED(flush);
-			/* Clear overflow flag */
-			spi_hw->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
-		} else {
-			if (module->dir == SPI_DIRECTION_WRITE) {
-				/* Flush receive buffer when writing */
-				_spi_read_dummy(module);
-				if (module->remaining_dummy_buffer_length == 0) {
-					spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
-					module->status = STATUS_OK;
-					module->dir = SPI_DIRECTION_IDLE;
-					/* Run callback if registered and enabled */
-					if (callback_mask &
-							(1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){
-						(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
-					}
-				}
-			} else {
-				/* Read data register */
-				_spi_read(module);
-
-				/* Check if the last character have been received */
-				if (module->remaining_rx_buffer_length == 0) {
-					module->status = STATUS_OK;
-					/* Disable RX Complete Interrupt and set status */
-					spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
-					if(module->dir == SPI_DIRECTION_BOTH) {
-						if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) {
-							(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
-						}
-					} else if (module->dir == SPI_DIRECTION_READ) {
-						if (callback_mask & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) {
-							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
-						}
-					}
-				}
-			}
-		}
-	}
-
-	/* Transmit complete */
-	if (interrupt_status & SPI_INTERRUPT_FLAG_TX_COMPLETE) {
+        )
+        {
+            /* Write next byte from buffer */
+            _spi_write(module);
+            if (module->remaining_tx_buffer_length == 0)
+            {
+                /* Disable the Data Register Empty Interrupt */
+                spi_hw->INTENCLR.reg
+                        = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+
+                if (module->dir == SPI_DIRECTION_WRITE &&
+                        !(module->receiver_enabled))
+                        {
+                    /* Enable the Data Register transmit complete Interrupt */
+                    spi_hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+                }
+            }
+        }
+    }
+
+    /* Receive complete interrupt*/
+    if (interrupt_status & SPI_INTERRUPT_FLAG_RX_COMPLETE)
+    {
+        /* Check for overflow */
+        if (spi_hw->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF)
+        {
+            if (module->dir != SPI_DIRECTION_WRITE)
+            {
+                /* Store the error code */
+                module->status = STATUS_ERR_OVERFLOW;
+
+                /* End transaction */
+                module->dir = SPI_DIRECTION_IDLE;
+
+                spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE |
+                        SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+                /* Run callback if registered and enabled */
+                if (callback_mask & (1 << SPI_CALLBACK_ERROR))
+                {
+                    (module->callback[SPI_CALLBACK_ERROR])(module);
+                }
+            }
+            /* Flush */
+            uint16_t flush = spi_hw->DATA.reg;
+            UNUSED(flush);
+            /* Clear overflow flag */
+            spi_hw->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF;
+        } else {
+            if (module->dir == SPI_DIRECTION_WRITE)
+            {
+                /* Flush receive buffer when writing */
+                _spi_read_dummy(module);
+                if (module->remaining_dummy_buffer_length == 0)
+                {
+                    spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+                    module->status = STATUS_OK;
+                    module->dir = SPI_DIRECTION_IDLE;
+                    /* Run callback if registered and enabled */
+                    if (callback_mask &
+                            (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))
+                            {
+                        (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+                    }
+                }
+            } else {
+                /* Read data register */
+                _spi_read(module);
+
+                /* Check if the last character have been received */
+                if (module->remaining_rx_buffer_length == 0)
+                {
+                    module->status = STATUS_OK;
+                    /* Disable RX Complete Interrupt and set status */
+                    spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE;
+                    if(module->dir == SPI_DIRECTION_BOTH)
+                    {
+                        if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))
+                        {
+                            (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+                        }
+                    } else if (module->dir == SPI_DIRECTION_READ)
+                    {
+                        if (callback_mask & (1 << SPI_CALLBACK_BUFFER_RECEIVED))
+                        {
+                            (module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    /* Transmit complete */
+    if (interrupt_status & SPI_INTERRUPT_FLAG_TX_COMPLETE)
+    {
 #  if CONF_SPI_SLAVE_ENABLE == true
-		if (module->mode == SPI_MODE_SLAVE) {
-			/* Transaction ended by master */
-
-			/* Disable interrupts */
-			spi_hw->INTENCLR.reg =
-					SPI_INTERRUPT_FLAG_TX_COMPLETE |
-					SPI_INTERRUPT_FLAG_RX_COMPLETE |
-					SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
-			/* Clear interrupt flag */
-			spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
-
-
-			/* Reset all status information */
-			module->dir = SPI_DIRECTION_IDLE;
-			module->remaining_tx_buffer_length = 0;
-			module->remaining_rx_buffer_length = 0;
-			module->status = STATUS_OK;
-
-			if (callback_mask &
-					(1 << SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE)) {
-			(module->callback[SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE])
-					(module);
-			}
-
-		}
+        if (module->mode == SPI_MODE_SLAVE)
+        {
+            /* Transaction ended by master */
+
+            /* Disable interrupts */
+            spi_hw->INTENCLR.reg =
+                    SPI_INTERRUPT_FLAG_TX_COMPLETE |
+                    SPI_INTERRUPT_FLAG_RX_COMPLETE |
+                    SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY;
+            /* Clear interrupt flag */
+            spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+
+
+            /* Reset all status information */
+            module->dir = SPI_DIRECTION_IDLE;
+            module->remaining_tx_buffer_length = 0;
+            module->remaining_rx_buffer_length = 0;
+            module->status = STATUS_OK;
+
+            if (callback_mask &
+                    (1 << SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE))
+                    {
+            (module->callback[SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE])
+                    (module);
+            }
+
+        }
 #  endif
 #  if CONF_SPI_MASTER_ENABLE == true
-		if ((module->mode == SPI_MODE_MASTER) &&
-			(module->dir == SPI_DIRECTION_WRITE) && !(module->receiver_enabled)) {
-		  	/* Clear interrupt flag */
-		 	spi_hw->INTENCLR.reg
-					= SPI_INTERRUPT_FLAG_TX_COMPLETE;
-			/* Buffer sent with receiver disabled */
-			module->dir = SPI_DIRECTION_IDLE;
-			module->status = STATUS_OK;
-			/* Run callback if registered and enabled */
-			if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){
-				(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])
-						(module);
-			}
-		}
+        if ((module->mode == SPI_MODE_MASTER) &&
+            (module->dir == SPI_DIRECTION_WRITE) && !(module->receiver_enabled))
+            {
+            /* Clear interrupt flag */
+            spi_hw->INTENCLR.reg
+                    = SPI_INTERRUPT_FLAG_TX_COMPLETE;
+            /* Buffer sent with receiver disabled */
+            module->dir = SPI_DIRECTION_IDLE;
+            module->status = STATUS_OK;
+            /* Run callback if registered and enabled */
+            if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))
+            {
+                (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])
+                        (module);
+            }
+        }
 #endif
-	}
+    }
 
 #  ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT
 #  if CONF_SPI_SLAVE_ENABLE == true
-		/* When a high to low transition is detected on the _SS pin in slave mode */
-		if (interrupt_status & SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW) {
-			if (module->mode == SPI_MODE_SLAVE) {
-				/* Disable interrupts */
-				spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
-				/* Clear interrupt flag */
-				spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
-
-				if (callback_mask & (1 << SPI_CALLBACK_SLAVE_SELECT_LOW)) {
-					(module->callback[SPI_CALLBACK_SLAVE_SELECT_LOW])(module);
-				}
-			}
-		}
+        /* When a high to low transition is detected on the _SS pin in slave mode */
+        if (interrupt_status & SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW)
+        {
+            if (module->mode == SPI_MODE_SLAVE)
+            {
+                /* Disable interrupts */
+                spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+                /* Clear interrupt flag */
+                spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW;
+
+                if (callback_mask & (1 << SPI_CALLBACK_SLAVE_SELECT_LOW))
+                {
+                    (module->callback[SPI_CALLBACK_SLAVE_SELECT_LOW])(module);
+                }
+            }
+        }
 #  endif
 #  endif
 
 #  ifdef FEATURE_SPI_ERROR_INTERRUPT
-	/* When combined error happen */
-	if (interrupt_status & SPI_INTERRUPT_FLAG_COMBINED_ERROR) {
-		/* Disable interrupts */
-		spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
-		/* Clear interrupt flag */
-		spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
-
-		if (callback_mask & (1 << SPI_CALLBACK_COMBINED_ERROR)) {
-			(module->callback[SPI_CALLBACK_COMBINED_ERROR])(module);
-		}
-	}
+    /* When combined error happen */
+    if (interrupt_status & SPI_INTERRUPT_FLAG_COMBINED_ERROR)
+    {
+        /* Disable interrupts */
+        spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
+        /* Clear interrupt flag */
+        spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR;
+
+        if (callback_mask & (1 << SPI_CALLBACK_COMBINED_ERROR))
+        {
+            (module->callback[SPI_CALLBACK_COMBINED_ERROR])(module);
+        }
+    }
 #  endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h
index bb7168250124..c02a107decc0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi/spi_interrupt.h
@@ -65,13 +65,13 @@ extern "C" {
  */
 
 void spi_register_callback(
-		struct spi_module *const module,
-		spi_callback_t callback_func,
-		enum spi_callback callback_type);
+        struct spi_module *const module,
+        spi_callback_t callback_func,
+        enum spi_callback callback_type);
 
 void spi_unregister_callback(
-		struct spi_module *module,
-		enum spi_callback callback_type);
+        struct spi_module *module,
+        enum spi_callback callback_type);
 
 /**
  * \brief Enables an SPI callback of a given type
@@ -84,14 +84,14 @@ void spi_unregister_callback(
  * \param[in] callback_type  Callback type given by an enum
  */
 static inline void spi_enable_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->enabled_callback |= (1 << callback_type);
+    /* Enable callback */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -104,14 +104,14 @@ static inline void spi_enable_callback(
  * \param[in] callback_type  Callback type given by an enum
  */
 static inline void spi_disable_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Disable callback */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Disable callback */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /** @} */
@@ -122,24 +122,24 @@ static inline void spi_disable_callback(
  * @{
  */
 enum status_code spi_write_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length);
 
 enum status_code spi_read_buffer_job(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy);
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy);
 
 enum status_code spi_transceive_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length);
 
 void spi_abort_job(
-		struct spi_module *const module);
+        struct spi_module *const module);
 
 /**
  * \brief Retrieves the current status of a job.
@@ -151,9 +151,9 @@ void spi_abort_job(
  * \return Current job status.
  */
 static inline enum status_code spi_get_job_status(
-		const struct spi_module *const module)
+        const struct spi_module *const module)
 {
-	return module->status;
+    return module->status;
 }
 
 /**
@@ -166,15 +166,15 @@ static inline enum status_code spi_get_job_status(
  * \return Current non-busy job status.
  */
 static inline enum status_code spi_get_job_status_wait(
-		const struct spi_module *const module)
+        const struct spi_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	do {
-		status = spi_get_job_status(module);
-	} while (status == STATUS_BUSY);
+    do {
+        status = spi_get_job_status(module);
+    } while (status == STATUS_BUSY);
 
-	return status;
+    return status;
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h
index 394b1fa6173c..a28b8e8c26e2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h
@@ -54,15 +54,15 @@
 #  define CONF_SPI_MASTER_VEC_OS_SUPPORT
 #  define CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE                   xSemaphoreHandle
 #  define CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(semaphore)  \
-		vSemaphoreCreateBinary(semaphore)
+        vSemaphoreCreateBinary(semaphore)
 #  define CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(semaphore)  \
-		vSemaphoreDelete(semaphore)
+        vSemaphoreDelete(semaphore)
 #  define CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(semaphore)  \
-		xSemaphoreTake((semaphore), portMAX_DELAY)
+        xSemaphoreTake((semaphore), portMAX_DELAY)
 #  define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(semaphore)  \
-		xSemaphoreGive((semaphore))
+        xSemaphoreGive((semaphore))
 #  define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(semaphore)  \
-		xSemaphoreGiveFromISR((semaphore), NULL)
+        xSemaphoreGiveFromISR((semaphore), NULL)
 #endif
 
-#endif // CONF_SPI_MASTER_VEC_H
\ No newline at end of file
+#endif /* CONF_SPI_MASTER_VEC_H*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c
index 89de7dd0d71b..33e33890db2a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c
@@ -74,13 +74,15 @@ static void _spi_master_vec_int_handler(uint8_t sercom_index);
 static inline void _spi_master_vec_wait_for_sync(SercomSpi *const sercom_spi)
 {
 #if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1)
-	while (sercom_spi->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) {
-		/* Intentionally left empty */
-	}
+    while (sercom_spi->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY)
+    {
+        /* Intentionally left empty */
+    }
 #elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2)
-	while (sercom_spi->SYNCBUSY.reg) {
-		/* Intentionally left empty */
-	}
+    while (sercom_spi->SYNCBUSY.reg)
+    {
+        /* Intentionally left empty */
+    }
 #else
 #  error Unknown SERCOM SYNCBUSY scheme!
 #endif
@@ -95,21 +97,23 @@ static inline void _spi_master_vec_wait_for_sync(SercomSpi *const sercom_spi)
  * \param[in] sercom,padnum SERCOM pad specification, for \ref PINMUX_DEFAULT.
  */
 static inline void _spi_master_vec_pinmux_helper(uint32_t pinmux,
-		Sercom *const sercom, uint8_t padnum)
+        Sercom *const sercom, uint8_t padnum)
 {
-	struct system_pinmux_config pin_conf;
+    struct system_pinmux_config pin_conf;
 
-	if (pinmux == PINMUX_DEFAULT) {
-		pinmux = _sercom_get_default_pad(sercom, padnum);
-	}
+    if (pinmux == PINMUX_DEFAULT)
+    {
+        pinmux = _sercom_get_default_pad(sercom, padnum);
+    }
 
-	if (pinmux == PINMUX_UNUSED) {
-		return;
-	}
+    if (pinmux == PINMUX_UNUSED)
+    {
+        return;
+    }
 
-	system_pinmux_get_config_defaults(&pin_conf);
-	pin_conf.mux_position = pinmux & 0xFFFF;
-	system_pinmux_pin_set_config(pinmux >> 16, &pin_conf);
+    system_pinmux_get_config_defaults(&pin_conf);
+    pin_conf.mux_position = pinmux & 0xFFFF;
+    system_pinmux_pin_set_config(pinmux >> 16, &pin_conf);
 };
 
 /** \endcond */
@@ -138,88 +142,90 @@ static inline void _spi_master_vec_pinmux_helper(uint32_t pinmux,
  * \retval STATUS_ERR_INVALID_ARG if driver has been misconfigured.
  */
 enum status_code spi_master_vec_init(struct spi_master_vec_module *const module,
-		Sercom *const sercom, const struct spi_master_vec_config *const config)
+        Sercom *const sercom, const struct spi_master_vec_config *const config)
 {
-	Assert(module);
-	Assert(sercom);
-	Assert(config);
-
-	enum status_code status;
-	SercomSpi *const spi_hw = &(sercom->SPI);
-	struct system_gclk_chan_config gclk_chan_conf;
-	uint16_t tmp_baud;
-	uint32_t sercom_index = _sercom_get_sercom_inst_index((Sercom *)spi_hw);
+    Assert(module);
+    Assert(sercom);
+    Assert(config);
+
+    enum status_code status;
+    SercomSpi *const spi_hw = &(sercom->SPI);
+    struct system_gclk_chan_config gclk_chan_conf;
+    uint16_t tmp_baud;
+    uint32_t sercom_index = _sercom_get_sercom_inst_index((Sercom *)spi_hw);
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
 #else
-	uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
 #endif
-	uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
-	uint32_t gclk_hz;
-
-	module->sercom = sercom;
-
-	/* Enable clock for the module interface */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
-
-	/* Set up the GCLK for the module */
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->gclk_generator;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->gclk_generator, false);
-
-	_spi_master_vec_wait_for_sync(spi_hw);
-
-	/* Set up the SERCOM SPI module as master */
-	spi_hw->CTRLA.reg = SERCOM_SPI_CTRLA_MODE(0x3);
-	spi_hw->CTRLA.reg |= (uint32_t)config->mux_setting
-			| config->transfer_mode
-			| config->data_order
-			| ((config->run_in_standby || system_is_debugger_present()) ?
-					SERCOM_SPI_CTRLA_RUNSTDBY : 0);
-
-	/* Get baud value from configured baudrate and internal clock rate */
-	gclk_hz = system_gclk_chan_get_hz(gclk_index);
-	status = _sercom_get_sync_baud_val(config->baudrate, gclk_hz, &tmp_baud);
-
-	if (status != STATUS_OK) {
-		/* Baud rate calculation error! */
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	spi_hw->BAUD.reg = (uint8_t)tmp_baud;
-
-	/* Configure the pin multiplexers */
-	_spi_master_vec_pinmux_helper(config->pinmux_pad0, sercom, 0);
-	_spi_master_vec_pinmux_helper(config->pinmux_pad3, sercom, 3);
-
-	/* SERCOM PAD1 and PAD2 are used for slave SS.
-	 * This is a SPI master driver, so control of slave SS must be left to
-	 * the PORT module, i.e., peripheral MUX should not be set for that pin.
-	 * DOPO controls which PAD is used for slave SS:
-	 * If DOPO is odd, SERCOM_PAD1 is SS: SERCOM_PAD2 can be MUXed.
-	 * If DOPO is even, SERCOM_PAD2 is SS: SERCOM_PAD1 can be MUXed.
-	 */
-	if (config->mux_setting & (1 << SERCOM_SPI_CTRLA_DOPO_Pos)) {
-		_spi_master_vec_pinmux_helper(config->pinmux_pad2, sercom, 2);
-	} else {
-		_spi_master_vec_pinmux_helper(config->pinmux_pad1, sercom, 1);
-	}
-
-	/* Initialize our instance and register interrupt handler + data */
-	module->rx_bufdesc_ptr = NULL;
-	module->tx_bufdesc_ptr = NULL;
-	module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
-	module->status = STATUS_OK;
+    uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
+    uint32_t gclk_hz;
+
+    module->sercom = sercom;
+
+    /* Enable clock for the module interface */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+
+    /* Set up the GCLK for the module */
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->gclk_generator;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->gclk_generator, false);
+
+    _spi_master_vec_wait_for_sync(spi_hw);
+
+    /* Set up the SERCOM SPI module as master */
+    spi_hw->CTRLA.reg = SERCOM_SPI_CTRLA_MODE(0x3);
+    spi_hw->CTRLA.reg |= (uint32_t)config->mux_setting
+            | config->transfer_mode
+            | config->data_order
+            | ((config->run_in_standby || system_is_debugger_present()) ?
+                    SERCOM_SPI_CTRLA_RUNSTDBY : 0);
+
+    /* Get baud value from configured baudrate and internal clock rate */
+    gclk_hz = system_gclk_chan_get_hz(gclk_index);
+    status = _sercom_get_sync_baud_val(config->baudrate, gclk_hz, &tmp_baud);
+
+    if (status != STATUS_OK)
+    {
+        /* Baud rate calculation error! */
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    spi_hw->BAUD.reg = (uint8_t)tmp_baud;
+
+    /* Configure the pin multiplexers */
+    _spi_master_vec_pinmux_helper(config->pinmux_pad0, sercom, 0);
+    _spi_master_vec_pinmux_helper(config->pinmux_pad3, sercom, 3);
+
+    /* SERCOM PAD1 and PAD2 are used for slave SS.
+     * This is a SPI master driver, so control of slave SS must be left to
+     * the PORT module, i.e., peripheral MUX should not be set for that pin.
+     * DOPO controls which PAD is used for slave SS:
+     * If DOPO is odd, SERCOM_PAD1 is SS: SERCOM_PAD2 can be MUXed.
+     * If DOPO is even, SERCOM_PAD2 is SS: SERCOM_PAD1 can be MUXed.
+     */
+    if (config->mux_setting & (1 << SERCOM_SPI_CTRLA_DOPO_Pos))
+    {
+        _spi_master_vec_pinmux_helper(config->pinmux_pad2, sercom, 2);
+    } else {
+        _spi_master_vec_pinmux_helper(config->pinmux_pad1, sercom, 1);
+    }
+
+    /* Initialize our instance and register interrupt handler + data */
+    module->rx_bufdesc_ptr = NULL;
+    module->tx_bufdesc_ptr = NULL;
+    module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
+    module->status = STATUS_OK;
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-	CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(module->busy_semaphore);
+    CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(module->busy_semaphore);
 #endif
 
-	_sercom_set_handler(sercom_index, _spi_master_vec_int_handler);
-	_sercom_instances[sercom_index] = module;
+    _sercom_set_handler(sercom_index, _spi_master_vec_int_handler);
+    _sercom_instances[sercom_index] = module;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -232,19 +238,19 @@ enum status_code spi_master_vec_init(struct spi_master_vec_module *const module,
  */
 void spi_master_vec_enable(const struct spi_master_vec_module *const module)
 {
-	Assert(module);
-	Assert(module->sercom);
+    Assert(module);
+    Assert(module->sercom);
 
-	SercomSpi *const spi_hw = &(module->sercom->SPI);
+    SercomSpi *const spi_hw = &(module->sercom->SPI);
 
-	spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC
-			| SERCOM_SPI_INTFLAG_TXC;
+    spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC
+            | SERCOM_SPI_INTFLAG_TXC;
 
-	_spi_master_vec_wait_for_sync(spi_hw);
+    _spi_master_vec_wait_for_sync(spi_hw);
 
-	spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
+    spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE;
 
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->sercom));
+    system_interrupt_enable(_sercom_get_interrupt_vector(module->sercom));
 }
 
 /**
@@ -254,23 +260,23 @@ void spi_master_vec_enable(const struct spi_master_vec_module *const module)
  */
 void spi_master_vec_disable(struct spi_master_vec_module *const module)
 {
-	Assert(module);
-	Assert(module->sercom);
+    Assert(module);
+    Assert(module->sercom);
 
-	SercomSpi *const spi_hw = &(module->sercom->SPI);
+    SercomSpi *const spi_hw = &(module->sercom->SPI);
 
-	system_interrupt_disable(_sercom_get_interrupt_vector(module->sercom));
+    system_interrupt_disable(_sercom_get_interrupt_vector(module->sercom));
 
-	_spi_master_vec_wait_for_sync(spi_hw);
+    _spi_master_vec_wait_for_sync(spi_hw);
 
-	spi_hw->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
-	spi_hw->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
-	spi_hw->CTRLB.reg = 0;
-	spi_hw->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
-	module->rx_bufdesc_ptr = NULL;
-	module->tx_bufdesc_ptr = NULL;
-	module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
-	module->status = STATUS_OK;
+    spi_hw->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK;
+    spi_hw->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK;
+    spi_hw->CTRLB.reg = 0;
+    spi_hw->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE;
+    module->rx_bufdesc_ptr = NULL;
+    module->tx_bufdesc_ptr = NULL;
+    module->direction = SPI_MASTER_VEC_DIRECTION_IDLE;
+    module->status = STATUS_OK;
 }
 
 /**
@@ -283,22 +289,22 @@ void spi_master_vec_disable(struct spi_master_vec_module *const module)
  */
 void spi_master_vec_reset(struct spi_master_vec_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->sercom);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->sercom);
 
-	SercomSpi *const spi_hw = &(module->sercom->SPI);
+    SercomSpi *const spi_hw = &(module->sercom->SPI);
 
-	/* Disable the module */
-	spi_master_vec_disable(module);
+    /* Disable the module */
+    spi_master_vec_disable(module);
 
-	_spi_master_vec_wait_for_sync(spi_hw);
+    _spi_master_vec_wait_for_sync(spi_hw);
 
-	/* Software reset the module */
-	spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
+    /* Software reset the module */
+    spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST;
 
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-	CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(module->busy_semaphore);
+    CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(module->busy_semaphore);
 #endif
 }
 
@@ -321,24 +327,24 @@ void spi_master_vec_reset(struct spi_master_vec_module *const module)
  * available buffer to receive them into. As an example, to receive the two
  * first bytes and discard the 128 following, the buffer descriptors could be:
 \code
-	struct spi_master_vec_bufdesc rx_buffers[3] = {
-		// Read two status bytes
-		{.data = status_buffer, .length = 2},
-		// Discard 128 data bytes
-		{.data = NULL, .length = 128},
-		// End of reception
-		{.length = 0},
-	};
+    struct spi_master_vec_bufdesc rx_buffers[3] = {
+        // Read two status bytes
+        {.data = status_buffer, .length = 2},
+        // Discard 128 data bytes
+        {.data = NULL, .length = 128},
+        // End of reception
+        {.length = 0},
+    };
 \endcode
  *
  * To initiate a unidirectional transfer, pass \c NULL as the address of either
  * buffer descriptor array, like this:
 \code
-	// Transmit some buffers
-	spi_master_vec_transceive_buffer_job(&module, tx_buffers, NULL);
+    // Transmit some buffers
+    spi_master_vec_transceive_buffer_job(&module, tx_buffers, NULL);
 
-	// Receive some buffers
-	spi_master_vec_transceive_buffer_job(&module, NULL, rx_buffers);
+    // Receive some buffers
+    spi_master_vec_transceive_buffer_job(&module, NULL, rx_buffers);
 \endcode
  *
  * \pre \ref spi_master_vec_init() and \ref spi_master_vec_enable() must have
@@ -357,74 +363,77 @@ void spi_master_vec_reset(struct spi_master_vec_module *const module)
  * \retval STATUS_BUSY if a transfer is already on-going.
  */
 enum status_code spi_master_vec_transceive_buffer_job(
-		struct spi_master_vec_module *const module,
-		struct spi_master_vec_bufdesc tx_bufdescs[],
-		struct spi_master_vec_bufdesc rx_bufdescs[])
+        struct spi_master_vec_module *const module,
+        struct spi_master_vec_bufdesc tx_bufdescs[],
+        struct spi_master_vec_bufdesc rx_bufdescs[])
 {
-	Assert(module);
-	Assert(module->sercom);
-	Assert(tx_bufdescs || rx_bufdescs);
-
-	SercomSpi *const spi_hw = &(module->sercom->SPI);
-	uint32_t tmp_ctrlb;
-	uint8_t tmp_intenset;
-
-	system_interrupt_enter_critical_section();
-	if (module->status == STATUS_BUSY) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	} else {
-		module->status = STATUS_BUSY;
-		system_interrupt_leave_critical_section();
-	}
+    Assert(module);
+    Assert(module->sercom);
+    Assert(tx_bufdescs || rx_bufdescs);
+
+    SercomSpi *const spi_hw = &(module->sercom->SPI);
+    uint32_t tmp_ctrlb;
+    uint8_t tmp_intenset;
+
+    system_interrupt_enter_critical_section();
+    if (module->status == STATUS_BUSY)
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_BUSY;
+    } else {
+        module->status = STATUS_BUSY;
+        system_interrupt_leave_critical_section();
+    }
 
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-	CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
+    CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
 #endif
 
-	module->tx_bufdesc_ptr = tx_bufdescs;
-	module->rx_bufdesc_ptr = rx_bufdescs;
-
-	if (tx_bufdescs && rx_bufdescs) {
-		Assert(tx_bufdescs[0].length);
-		Assert(rx_bufdescs[0].length);
-
-		module->direction = SPI_MASTER_VEC_DIRECTION_BOTH;
-		module->tx_length = tx_bufdescs[0].length;
-		module->tx_head_ptr = tx_bufdescs[0].data;
-		module->rx_length = rx_bufdescs[0].length;
-		module->rx_head_ptr = rx_bufdescs[0].data;
-		module->tx_lead_on_rx = 0;
-		tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
-		tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
-	} else {
-		if (tx_bufdescs) {
-			Assert(tx_bufdescs[0].length);
-
-			module->direction = SPI_MASTER_VEC_DIRECTION_WRITE;
-			module->tx_length = tx_bufdescs[0].length;
-			module->tx_head_ptr = tx_bufdescs[0].data;
-			tmp_ctrlb = 0;
-			tmp_intenset = SERCOM_SPI_INTFLAG_DRE;
-		} else {
-			Assert(rx_bufdescs[0].length);
-
-			module->direction = SPI_MASTER_VEC_DIRECTION_READ;
-			module->rx_length = rx_bufdescs[0].length;
-			module->rx_head_ptr = rx_bufdescs[0].data;
-			module->tx_lead_on_rx = 0;
-			tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
-			tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
-		}
-	}
-
-	/* Ensure the SERCOM is sync'ed before writing these registers */
-	_spi_master_vec_wait_for_sync(spi_hw);
-
-	spi_hw->CTRLB.reg = tmp_ctrlb;
-	spi_hw->INTENSET.reg = tmp_intenset;
-
-	return STATUS_OK;
+    module->tx_bufdesc_ptr = tx_bufdescs;
+    module->rx_bufdesc_ptr = rx_bufdescs;
+
+    if (tx_bufdescs && rx_bufdescs)
+    {
+        Assert(tx_bufdescs[0].length);
+        Assert(rx_bufdescs[0].length);
+
+        module->direction = SPI_MASTER_VEC_DIRECTION_BOTH;
+        module->tx_length = tx_bufdescs[0].length;
+        module->tx_head_ptr = tx_bufdescs[0].data;
+        module->rx_length = rx_bufdescs[0].length;
+        module->rx_head_ptr = rx_bufdescs[0].data;
+        module->tx_lead_on_rx = 0;
+        tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
+        tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
+    } else {
+        if (tx_bufdescs)
+        {
+            Assert(tx_bufdescs[0].length);
+
+            module->direction = SPI_MASTER_VEC_DIRECTION_WRITE;
+            module->tx_length = tx_bufdescs[0].length;
+            module->tx_head_ptr = tx_bufdescs[0].data;
+            tmp_ctrlb = 0;
+            tmp_intenset = SERCOM_SPI_INTFLAG_DRE;
+        } else {
+            Assert(rx_bufdescs[0].length);
+
+            module->direction = SPI_MASTER_VEC_DIRECTION_READ;
+            module->rx_length = rx_bufdescs[0].length;
+            module->rx_head_ptr = rx_bufdescs[0].data;
+            module->tx_lead_on_rx = 0;
+            tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN;
+            tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC;
+        }
+    }
+
+    /* Ensure the SERCOM is sync'ed before writing these registers */
+    _spi_master_vec_wait_for_sync(spi_hw);
+
+    spi_hw->CTRLB.reg = tmp_ctrlb;
+    spi_hw->INTENSET.reg = tmp_intenset;
+
+    return STATUS_OK;
 }
 
 /**
@@ -435,154 +444,168 @@ enum status_code spi_master_vec_transceive_buffer_job(
  */
 static void _spi_master_vec_int_handler(uint8_t sercom_index)
 {
-	struct spi_master_vec_module *const module =
-			_sercom_instances[sercom_index];
-	enum _spi_master_vec_direction dir = module->direction;
-	SercomSpi *const spi_hw = &(module->sercom->SPI);
-	uint8_t int_status;
+    struct spi_master_vec_module *const module =
+            _sercom_instances[sercom_index];
+    enum _spi_master_vec_direction dir = module->direction;
+    SercomSpi *const spi_hw = &(module->sercom->SPI);
+    uint8_t int_status;
 
-	int_status = spi_hw->INTFLAG.reg ;
+    int_status = spi_hw->INTFLAG.reg ;
     int_status &= spi_hw->INTENSET.reg;
 
-	if (int_status & SERCOM_SPI_INTFLAG_DRE) {
-		uint_fast8_t tx_lead_on_rx = module->tx_lead_on_rx;
-
-		/* If TX is ahead of RX by 2+ bytes, allow RX to catch up.
-		 * Note: will only happen _once_ per READ or BOTH.
-		 */
-		if ((tx_lead_on_rx >= 2) && (dir != SPI_MASTER_VEC_DIRECTION_WRITE)) {
-			Assert((dir == SPI_MASTER_VEC_DIRECTION_READ)
-					|| (dir == SPI_MASTER_VEC_DIRECTION_BOTH));
-			Assert(int_status & SERCOM_SPI_INTFLAG_RXC);
-		/* Otherwise, we can send more bytes */
-		} else {
-			module->tx_lead_on_rx = ++tx_lead_on_rx;
-
-			/* If doing a READ, just send 0 to trigger the transfer */
-			if (dir == SPI_MASTER_VEC_DIRECTION_READ) {
-				uint32_t tx_lead_limit;
-
-				spi_hw->DATA.reg = 0;
+    if (int_status & SERCOM_SPI_INTFLAG_DRE)
+    {
+        uint_fast8_t tx_lead_on_rx = module->tx_lead_on_rx;
+
+        /* If TX is ahead of RX by 2+ bytes, allow RX to catch up.
+         * Note: will only happen _once_ per READ or BOTH.
+         */
+        if ((tx_lead_on_rx >= 2) && (dir != SPI_MASTER_VEC_DIRECTION_WRITE))
+        {
+            Assert((dir == SPI_MASTER_VEC_DIRECTION_READ)
+                    || (dir == SPI_MASTER_VEC_DIRECTION_BOTH));
+            Assert(int_status & SERCOM_SPI_INTFLAG_RXC);
+        /* Otherwise, we can send more bytes */
+        } else {
+            module->tx_lead_on_rx = ++tx_lead_on_rx;
+
+            /* If doing a READ, just send 0 to trigger the transfer */
+            if (dir == SPI_MASTER_VEC_DIRECTION_READ)
+            {
+                uint32_t tx_lead_limit;
+
+                spi_hw->DATA.reg = 0;
 
 check_for_read_end:
-				/* With current TX'ed bytes, will we get the last RX byte?
-				 * If so, we can disable the DRE interrupt to stop transmitting.
-				 *
-				 * Since a buffer can have minimum 1 byte length, this check is
-				 * simplified by first checking if the RX end is so close that
-				 * the max. 2 byte lead of TX may actually fill the buffers.
-				 */
-				tx_lead_limit = (module->rx_bufdesc_ptr + 1)->length;
-
-				if (!tx_lead_limit || !(module->rx_bufdesc_ptr + 2)->length) {
-					tx_lead_limit += module->rx_length;
-
-					if (tx_lead_on_rx >= tx_lead_limit) {
-						spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
-					}
-				}
-			/* For WRITE and BOTH, output current byte */
-			} else {
-				spi_master_vec_buflen_t tx_length;
-				uint8_t *tx_head_ptr;
-
-				tx_head_ptr = module->tx_head_ptr;
-				spi_hw->DATA.reg = *(tx_head_ptr++);
-
-				/* Check if this was the last byte to send */
-				tx_length = module->tx_length - 1;
-
-				if (tx_length) {
-					module->tx_head_ptr = tx_head_ptr;
-					module->tx_length = tx_length;
-				} else {
-				/* Any more buffers left to send, perhaps? */
-					tx_length = (++module->tx_bufdesc_ptr)->length;
-
-					if (tx_length) {
-						module->tx_head_ptr = module->tx_bufdesc_ptr->data;
-						module->tx_length = tx_length;
-					} else {
-						if (dir == SPI_MASTER_VEC_DIRECTION_WRITE) {
-						/* Disable DRE and enable TXC to end WRITE */
-							spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
-							spi_hw->INTENSET.reg = SERCOM_SPI_INTFLAG_TXC;
-						} else {
-						/* For BOTH, check if we still have bytes to read */
-							dir = SPI_MASTER_VEC_DIRECTION_READ;
-							module->direction = dir;
-							goto check_for_read_end;
-						}
-					}
-				}
-			}
-		}
-	}
-
-	/* For READ and BOTH, store the received byte */
-	if (int_status & SERCOM_SPI_INTFLAG_RXC) {
-		spi_master_vec_buflen_t rx_length;
-		uint8_t *rx_head_ptr;
-
-		rx_head_ptr = module->rx_head_ptr;
-		if (rx_head_ptr != NULL) {
-			*(rx_head_ptr++) = spi_hw->DATA.reg;
-		} else {
-			uint8_t dummy;
-			dummy = spi_hw->DATA.reg;
-			UNUSED(dummy);
-		}
-		module->tx_lead_on_rx--;
-
-		/* Check if this was the last byte to receive */
-		rx_length = module->rx_length - 1;
-
-		if (rx_length) {
-			module->rx_head_ptr = rx_head_ptr;
-			module->rx_length = rx_length;
-		} else {
-			/* Any more buffers left to receive into? */
-			rx_length = (++module->rx_bufdesc_ptr)->length;
-
-			if (rx_length) {
-				module->rx_head_ptr = module->rx_bufdesc_ptr->data;
-				module->rx_length = rx_length;
-			} else {
-				/* Disable the SPI receiver (instant effect) and RX interrupt */
-				spi_hw->CTRLB.reg = 0;
-				spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_RXC;
-
-				if (dir == SPI_MASTER_VEC_DIRECTION_READ) {
-					/* If doing READ, end the transaction here */
-					dir = SPI_MASTER_VEC_DIRECTION_IDLE;
-					module->direction = dir;
-					module->status = STATUS_OK;
+                /* With current TX'ed bytes, will we get the last RX byte?
+                 * If so, we can disable the DRE interrupt to stop transmitting.
+                 *
+                 * Since a buffer can have minimum 1 byte length, this check is
+                 * simplified by first checking if the RX end is so close that
+                 * the max. 2 byte lead of TX may actually fill the buffers.
+                 */
+                tx_lead_limit = (module->rx_bufdesc_ptr + 1)->length;
+
+                if (!tx_lead_limit || !(module->rx_bufdesc_ptr + 2)->length)
+                {
+                    tx_lead_limit += module->rx_length;
+
+                    if (tx_lead_on_rx >= tx_lead_limit)
+                    {
+                        spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
+                    }
+                }
+            /* For WRITE and BOTH, output current byte */
+            } else {
+                spi_master_vec_buflen_t tx_length;
+                uint8_t *tx_head_ptr;
+
+                tx_head_ptr = module->tx_head_ptr;
+                spi_hw->DATA.reg = *(tx_head_ptr++);
+
+                /* Check if this was the last byte to send */
+                tx_length = module->tx_length - 1;
+
+                if (tx_length)
+                {
+                    module->tx_head_ptr = tx_head_ptr;
+                    module->tx_length = tx_length;
+                } else {
+                /* Any more buffers left to send, perhaps? */
+                    tx_length = (++module->tx_bufdesc_ptr)->length;
+
+                    if (tx_length)
+                    {
+                        module->tx_head_ptr = module->tx_bufdesc_ptr->data;
+                        module->tx_length = tx_length;
+                    } else {
+                        if (dir == SPI_MASTER_VEC_DIRECTION_WRITE)
+                        {
+                        /* Disable DRE and enable TXC to end WRITE */
+                            spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE;
+                            spi_hw->INTENSET.reg = SERCOM_SPI_INTFLAG_TXC;
+                        } else {
+                        /* For BOTH, check if we still have bytes to read */
+                            dir = SPI_MASTER_VEC_DIRECTION_READ;
+                            module->direction = dir;
+                            goto check_for_read_end;
+                        }
+                    }
+                }
+            }
+        }
+    }
+
+    /* For READ and BOTH, store the received byte */
+    if (int_status & SERCOM_SPI_INTFLAG_RXC)
+    {
+        spi_master_vec_buflen_t rx_length;
+        uint8_t *rx_head_ptr;
+
+        rx_head_ptr = module->rx_head_ptr;
+        if (rx_head_ptr != NULL)
+        {
+            *(rx_head_ptr++) = spi_hw->DATA.reg;
+        } else {
+            uint8_t dummy;
+            dummy = spi_hw->DATA.reg;
+            UNUSED(dummy);
+        }
+        module->tx_lead_on_rx--;
+
+        /* Check if this was the last byte to receive */
+        rx_length = module->rx_length - 1;
+
+        if (rx_length)
+        {
+            module->rx_head_ptr = rx_head_ptr;
+            module->rx_length = rx_length;
+        } else {
+            /* Any more buffers left to receive into? */
+            rx_length = (++module->rx_bufdesc_ptr)->length;
+
+            if (rx_length)
+            {
+                module->rx_head_ptr = module->rx_bufdesc_ptr->data;
+                module->rx_length = rx_length;
+            } else {
+                /* Disable the SPI receiver (instant effect) and RX interrupt */
+                spi_hw->CTRLB.reg = 0;
+                spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_RXC;
+
+                if (dir == SPI_MASTER_VEC_DIRECTION_READ)
+                {
+                    /* If doing READ, end the transaction here */
+                    dir = SPI_MASTER_VEC_DIRECTION_IDLE;
+                    module->direction = dir;
+                    module->status = STATUS_OK;
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-					CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
+                    CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
 #endif
-				} else {
-					/* If doing BOTH, change direction to WRITE */
-					dir = SPI_MASTER_VEC_DIRECTION_WRITE;
-					module->direction = dir;
-				}
-			}
-		}
-	}
-
-	/* For WRITE */
-	if (int_status & SERCOM_SPI_INTFLAG_TXC) {
-		/* End transaction here, since last byte has been sent */
-		spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC;
-
-		dir = SPI_MASTER_VEC_DIRECTION_IDLE;
-		module->direction = dir;
-		module->status = STATUS_OK;
+                } else {
+                    /* If doing BOTH, change direction to WRITE */
+                    dir = SPI_MASTER_VEC_DIRECTION_WRITE;
+                    module->direction = dir;
+                }
+            }
+        }
+    }
+
+    /* For WRITE */
+    if (int_status & SERCOM_SPI_INTFLAG_TXC)
+    {
+        /* End transaction here, since last byte has been sent */
+        spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC;
+
+        dir = SPI_MASTER_VEC_DIRECTION_IDLE;
+        module->direction = dir;
+        module->status = STATUS_OK;
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-		CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
+        CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore);
 #endif
-	}
+    }
 }
 
 /**
  * @}
- */
\ No newline at end of file
+ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h
index a10ae22f14c0..7038048a823d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h
@@ -126,26 +126,26 @@
  * \anchor asfdoc_sam0_vectored_io_example
  * \dot
 digraph bufptr_to_spiord {
-	rankdir=LR;
-	subgraph cluster_bufptr {
-		style=invis;
-		bufptr_label [shape=none, label="Buffer descriptors"];
-		bufptrs [shape=record, label="<bf1> [0]|<bf2> [1]|<bf3> [2]|<bf4> [3]"];
-	}
-	subgraph cluster_buf {
-		style=invis;
-		buf_label [shape=none, label="Memory layout"];
-		bufs [shape=record, label="...|<b1>&quot;yy&quot;|...|<b3>&quot;z&quot;|<b2>&quot;xxx&quot;|..."];
-	}
-	subgraph cluster_spiord {
-		style=invis;
-		spiord_label [shape=none, label="SPI transmission"];
-		spiord [shape=record, label="<s1>&quot;yy&quot;|<s2>&quot;xxx&quot;|<s3>&quot;z&quot;"];
-	}
-	bufptrs:bf1 -> bufs:b1 -> spiord:s1;
-	bufptrs:bf2 -> bufs:b2 -> spiord:s2;
-	bufptrs:bf3 -> bufs:b3 -> spiord:s3;
-	bufptrs:bf4 -> "none";
+    rankdir=LR;
+    subgraph cluster_bufptr {
+        style=invis;
+        bufptr_label [shape=none, label="Buffer descriptors"];
+        bufptrs [shape=record, label="<bf1> [0]|<bf2> [1]|<bf3> [2]|<bf4> [3]"];
+    }
+    subgraph cluster_buf {
+        style=invis;
+        buf_label [shape=none, label="Memory layout"];
+        bufs [shape=record, label="...|<b1>&quot;yy&quot;|...|<b3>&quot;z&quot;|<b2>&quot;xxx&quot;|..."];
+    }
+    subgraph cluster_spiord {
+        style=invis;
+        spiord_label [shape=none, label="SPI transmission"];
+        spiord [shape=record, label="<s1>&quot;yy&quot;|<s2>&quot;xxx&quot;|<s3>&quot;z&quot;"];
+    }
+    bufptrs:bf1 -> bufs:b1 -> spiord:s1;
+    bufptrs:bf2 -> bufs:b2 -> spiord:s2;
+    bufptrs:bf3 -> bufs:b3 -> spiord:s3;
+    bufptrs:bf4 -> "none";
 }
  * \enddot
  *
@@ -247,26 +247,26 @@ digraph bufptr_to_spiord {
  * information regarding SERCOM pad and pin MUX.
  */
 struct spi_master_vec_config {
-	/** Baud rate in Hertz. */
-	uint32_t baudrate;
-	/** GCLK generator to use for the SERCOM. */
-	enum gclk_generator gclk_generator;
-	/** Enabled in sleep modes. */
-	bool run_in_standby;
-	/** SERCOM pad MUX setting. */
-	enum spi_signal_mux_setting mux_setting;
-	/** Transfer mode. */
-	enum spi_transfer_mode transfer_mode;
-	/** Data order. */
-	enum spi_data_order data_order;
-	/** Pin MUX setting for SERCOM pad 0. */
-	uint32_t pinmux_pad0;
-	/** Pin MUX setting for SERCOM pad 1. */
-	uint32_t pinmux_pad1;
-	/** Pin MUX setting for SERCOM pad 2. */
-	uint32_t pinmux_pad2;
-	/** Pin MUX setting for SERCOM pad 4. */
-	uint32_t pinmux_pad3;
+    /** Baud rate in Hertz. */
+    uint32_t baudrate;
+    /** GCLK generator to use for the SERCOM. */
+    enum gclk_generator gclk_generator;
+    /** Enabled in sleep modes. */
+    bool run_in_standby;
+    /** SERCOM pad MUX setting. */
+    enum spi_signal_mux_setting mux_setting;
+    /** Transfer mode. */
+    enum spi_transfer_mode transfer_mode;
+    /** Data order. */
+    enum spi_data_order data_order;
+    /** Pin MUX setting for SERCOM pad 0. */
+    uint32_t pinmux_pad0;
+    /** Pin MUX setting for SERCOM pad 1. */
+    uint32_t pinmux_pad1;
+    /** Pin MUX setting for SERCOM pad 2. */
+    uint32_t pinmux_pad2;
+    /** Pin MUX setting for SERCOM pad 4. */
+    uint32_t pinmux_pad3;
 };
 
 /** Buffer length container. */
@@ -274,36 +274,36 @@ typedef uint16_t spi_master_vec_buflen_t;
 
 /** Buffer descriptor structure. */
 struct spi_master_vec_bufdesc {
-	/** Pointer to buffer start. */
-	void *data;
-	/** Length of buffer. */
-	spi_master_vec_buflen_t length;
+    /** Pointer to buffer start. */
+    void *data;
+    /** Length of buffer. */
+    spi_master_vec_buflen_t length;
 };
 
 /** Transfer direction */
 enum _spi_master_vec_direction {
-	SPI_MASTER_VEC_DIRECTION_READ,
-	SPI_MASTER_VEC_DIRECTION_WRITE,
-	SPI_MASTER_VEC_DIRECTION_BOTH,
-	SPI_MASTER_VEC_DIRECTION_IDLE,
+    SPI_MASTER_VEC_DIRECTION_READ,
+    SPI_MASTER_VEC_DIRECTION_WRITE,
+    SPI_MASTER_VEC_DIRECTION_BOTH,
+    SPI_MASTER_VEC_DIRECTION_IDLE,
 };
 
 /** Driver instance. */
 struct spi_master_vec_module {
 #if !defined(__DOXYGEN__)
-	Sercom *volatile sercom;
-	volatile bool locked;
-	volatile enum _spi_master_vec_direction direction;
-	volatile enum status_code status;
-	volatile spi_master_vec_buflen_t rx_length;
-	volatile spi_master_vec_buflen_t tx_length;
-	uint8_t *volatile rx_head_ptr;
-	uint8_t *volatile tx_head_ptr;
-	volatile uint_fast8_t tx_lead_on_rx;
-	struct spi_master_vec_bufdesc *volatile rx_bufdesc_ptr;
-	struct spi_master_vec_bufdesc *volatile tx_bufdesc_ptr;
+    Sercom *volatile sercom;
+    volatile bool locked;
+    volatile enum _spi_master_vec_direction direction;
+    volatile enum status_code status;
+    volatile spi_master_vec_buflen_t rx_length;
+    volatile spi_master_vec_buflen_t tx_length;
+    uint8_t *volatile rx_head_ptr;
+    uint8_t *volatile tx_head_ptr;
+    volatile uint_fast8_t tx_lead_on_rx;
+    struct spi_master_vec_bufdesc *volatile rx_bufdesc_ptr;
+    struct spi_master_vec_bufdesc *volatile tx_bufdesc_ptr;
 #  ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-	CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE busy_semaphore;
+    CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE busy_semaphore;
 #  endif
 #endif
 };
@@ -319,18 +319,18 @@ struct spi_master_vec_module {
  * \param[out] config Configuration struct to initialize.
  */
 static inline void spi_master_vec_get_config_defaults(
-		struct spi_master_vec_config *const config)
+        struct spi_master_vec_config *const config)
 {
-	config->baudrate = 100000;
-	config->gclk_generator = GCLK_GENERATOR_0;
-	config->run_in_standby = false;
-	config->mux_setting = SPI_SIGNAL_MUX_SETTING_D;
-	config->transfer_mode = SPI_TRANSFER_MODE_0;
-	config->data_order = SPI_DATA_ORDER_MSB;
-	config->pinmux_pad0 = PINMUX_DEFAULT;
-	config->pinmux_pad1 = PINMUX_DEFAULT;
-	config->pinmux_pad2 = PINMUX_DEFAULT;
-	config->pinmux_pad3 = PINMUX_DEFAULT;
+    config->baudrate = 100000;
+    config->gclk_generator = GCLK_GENERATOR_0;
+    config->run_in_standby = false;
+    config->mux_setting = SPI_SIGNAL_MUX_SETTING_D;
+    config->transfer_mode = SPI_TRANSFER_MODE_0;
+    config->data_order = SPI_DATA_ORDER_MSB;
+    config->pinmux_pad0 = PINMUX_DEFAULT;
+    config->pinmux_pad1 = PINMUX_DEFAULT;
+    config->pinmux_pad2 = PINMUX_DEFAULT;
+    config->pinmux_pad3 = PINMUX_DEFAULT;
 }
 
 #ifdef __cplusplus
@@ -338,7 +338,7 @@ extern "C" {
 #endif
 
 enum status_code spi_master_vec_init(struct spi_master_vec_module *const module,
-		Sercom *const sercom, const struct spi_master_vec_config *const config);
+        Sercom *const sercom, const struct spi_master_vec_config *const config);
 
 /** @} */
 
@@ -374,22 +374,23 @@ void spi_master_vec_reset(struct spi_master_vec_module *const module);
  * \retval STATUS_BUSY if the module was already locked.
  */
 static inline enum status_code spi_master_vec_lock(
-		struct spi_master_vec_module *const module)
+        struct spi_master_vec_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return status;
+    return status;
 }
 
 /**
@@ -401,9 +402,9 @@ static inline enum status_code spi_master_vec_lock(
  * \param[in,out] module Pointer to the driver instance to lock.
  */
 static inline void spi_master_vec_unlock(
-		struct spi_master_vec_module *const module)
+        struct spi_master_vec_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /** @} */
@@ -414,9 +415,9 @@ static inline void spi_master_vec_unlock(
  */
 
 enum status_code spi_master_vec_transceive_buffer_job(
-		struct spi_master_vec_module *const module,
-		struct spi_master_vec_bufdesc tx_bufdescs[],
-		struct spi_master_vec_bufdesc rx_bufdescs[]);
+        struct spi_master_vec_module *const module,
+        struct spi_master_vec_bufdesc tx_bufdescs[],
+        struct spi_master_vec_bufdesc rx_bufdescs[]);
 
 /**
  * \brief Get current status of transfer.
@@ -429,9 +430,9 @@ enum status_code spi_master_vec_transceive_buffer_job(
  * \retval <other> if previous transfer failed.
  */
 static inline enum status_code spi_master_vec_get_job_status(
-		const struct spi_master_vec_module *const module)
+        const struct spi_master_vec_module *const module)
 {
-	return module->status;
+    return module->status;
 }
 
 /**
@@ -444,21 +445,21 @@ static inline enum status_code spi_master_vec_get_job_status(
  * \retval <other> if previous transfer failed.
  */
 static inline enum status_code spi_master_vec_get_job_status_wait(
-		const struct spi_master_vec_module *const module)
+        const struct spi_master_vec_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
 #ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT
-	CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
-	status = spi_master_vec_get_job_status(module);
-	CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(module->busy_semaphore);
+    CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore);
+    status = spi_master_vec_get_job_status(module);
+    CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(module->busy_semaphore);
 #else
-	do {
-		status = spi_master_vec_get_job_status(module);
-	} while (status == STATUS_BUSY);
+    do {
+        status = spi_master_vec_get_job_status(module);
+    } while (status == STATUS_BUSY);
 #endif
 
-	return status;
+    return status;
 }
 
 
@@ -479,20 +480,21 @@ static inline enum status_code spi_master_vec_get_job_status_wait(
  * \retval <other> if transfer failed.
  */
 static inline enum status_code spi_master_vec_transceive_buffer_wait(
-		struct spi_master_vec_module *const module,
-		struct spi_master_vec_bufdesc tx_bufdescs[],
-		struct spi_master_vec_bufdesc rx_bufdescs[])
+        struct spi_master_vec_module *const module,
+        struct spi_master_vec_bufdesc tx_bufdescs[],
+        struct spi_master_vec_bufdesc rx_bufdescs[])
 {
-	enum status_code status;
+    enum status_code status;
 
-	status = spi_master_vec_transceive_buffer_job(module, tx_bufdescs,
-			rx_bufdescs);
+    status = spi_master_vec_transceive_buffer_job(module, tx_bufdescs,
+            rx_bufdescs);
 
-	if (status == STATUS_BUSY) {
-		return status;
-	}
+    if (status == STATUS_BUSY)
+    {
+        return status;
+    }
 
-	return spi_master_vec_get_job_status_wait(module);
+    return spi_master_vec_get_job_status_wait(module);
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c
index e916cf5bd44e..d4c576847033 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.c
@@ -54,239 +54,256 @@
  * Set Configuration of the USART module
  */
 static enum status_code _usart_set_config(
-		struct usart_module *const module,
-		const struct usart_config *const config)
+        struct usart_module *const module,
+        const struct usart_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	/* Index for generic clock */
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    /* Index for generic clock */
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 
-	/* Cache new register values to minimize the number of register writes */
-	uint32_t ctrla = 0;
-	uint32_t ctrlb = 0;
+    /* Cache new register values to minimize the number of register writes */
+    uint32_t ctrla = 0;
+    uint32_t ctrlb = 0;
 #ifdef FEATURE_USART_ISO7816
-	uint32_t ctrlc = 0;
+    uint32_t ctrlc = 0;
 #endif
-	uint16_t baud  = 0;
-	uint32_t transfer_mode;
+    uint16_t baud  = 0;
+    uint32_t transfer_mode;
 
-	enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-	enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+    enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+    enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
 
 #ifdef FEATURE_USART_OVER_SAMPLE
-	switch (config->sample_rate) {
-		case USART_SAMPLE_RATE_16X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-			break;
-		case USART_SAMPLE_RATE_8X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-			break;
-		case USART_SAMPLE_RATE_3X_ARITHMETIC:
-			mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
-			break;
-		case USART_SAMPLE_RATE_16X_FRACTIONAL:
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
-			break;
-		case USART_SAMPLE_RATE_8X_FRACTIONAL:
-			mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
-			sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
-			break;
-	}
+    switch (config->sample_rate)
+    {
+        case USART_SAMPLE_RATE_16X_ARITHMETIC:
+            mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+            sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+            break;
+        case USART_SAMPLE_RATE_8X_ARITHMETIC:
+            mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+            sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+            break;
+        case USART_SAMPLE_RATE_3X_ARITHMETIC:
+            mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC;
+            sample_num = SERCOM_ASYNC_SAMPLE_NUM_3;
+            break;
+        case USART_SAMPLE_RATE_16X_FRACTIONAL:
+            mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+            sample_num = SERCOM_ASYNC_SAMPLE_NUM_16;
+            break;
+        case USART_SAMPLE_RATE_8X_FRACTIONAL:
+            mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL;
+            sample_num = SERCOM_ASYNC_SAMPLE_NUM_8;
+            break;
+    }
 #endif
 
-	/* Set data order, internal muxing, and clock polarity */
-	ctrla = (uint32_t)config->data_order |
-		(uint32_t)config->mux_setting |
-	#ifdef FEATURE_USART_OVER_SAMPLE
-		config->sample_adjustment |
-		config->sample_rate |
-	#endif
-	#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-		(config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
-	#endif
-		(config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
-
-	enum status_code status_code = STATUS_OK;
-
-	transfer_mode = (uint32_t)config->transfer_mode;
+    /* Set data order, internal muxing, and clock polarity */
+    ctrla = (uint32_t)config->data_order |
+        (uint32_t)config->mux_setting |
+    #ifdef FEATURE_USART_OVER_SAMPLE
+        config->sample_adjustment |
+        config->sample_rate |
+    #endif
+    #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
+        (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) |
+    #endif
+        (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos);
+
+    enum status_code status_code = STATUS_OK;
+
+    transfer_mode = (uint32_t)config->transfer_mode;
 #ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		transfer_mode = config->iso7816_config.protocol_t;
-	}
+    if(config->iso7816_config.enabled)
+    {
+        transfer_mode = config->iso7816_config.protocol_t;
+    }
 #endif
-	/* Get baud value from mode and clock */
+    /* Get baud value from mode and clock */
 #ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		baud = config->baudrate;
-	} else {
+    if(config->iso7816_config.enabled)
+    {
+        baud = config->baudrate;
+    } else {
 #endif
-	switch (transfer_mode)
-	{
-		case USART_TRANSFER_SYNCHRONOUSLY:
-			if (!config->use_external_clock) {
-				status_code = _sercom_get_sync_baud_val(config->baudrate,
-						system_gclk_chan_get_hz(gclk_index), &baud);
-			}
-
-			break;
-
-		case USART_TRANSFER_ASYNCHRONOUSLY:
-			if (config->use_external_clock) {
-				status_code =
-						_sercom_get_async_baud_val(config->baudrate,
-							config->ext_clock_freq, &baud, mode, sample_num);
-			} else {
-				status_code =
-						_sercom_get_async_baud_val(config->baudrate,
-							system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
-			}
-
-			break;
-	}
-
-	/* Check if calculating the baudrate failed */
-	if (status_code != STATUS_OK) {
-		/* Abort */
-		return status_code;
-	}
+    switch (transfer_mode)
+    {
+        case USART_TRANSFER_SYNCHRONOUSLY:
+            if (!config->use_external_clock)
+            {
+                status_code = _sercom_get_sync_baud_val(config->baudrate,
+                        system_gclk_chan_get_hz(gclk_index), &baud);
+            }
+
+            break;
+
+        case USART_TRANSFER_ASYNCHRONOUSLY:
+            if (config->use_external_clock)
+            {
+                status_code =
+                        _sercom_get_async_baud_val(config->baudrate,
+                            config->ext_clock_freq, &baud, mode, sample_num);
+            } else {
+                status_code =
+                        _sercom_get_async_baud_val(config->baudrate,
+                            system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num);
+            }
+
+            break;
+    }
+
+    /* Check if calculating the baudrate failed */
+    if (status_code != STATUS_OK)
+    {
+        /* Abort */
+        return status_code;
+    }
 #ifdef FEATURE_USART_ISO7816
-	}
+    }
 #endif
 
 #ifdef FEATURE_USART_IRDA
-	if(config->encoding_format_enable) {
-		usart_hw->RXPL.reg = config->receive_pulse_length;
-	}
+    if(config->encoding_format_enable)
+    {
+        usart_hw->RXPL.reg = config->receive_pulse_length;
+    }
 #endif
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/*Set baud val */
-	usart_hw->BAUD.reg = baud;
-
-	/* Set sample mode */
-	ctrla |= transfer_mode;
-
-	if (config->use_external_clock == false) {
-		ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
-	}
-	else {
-		ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
-	}
-
-	/* Set stopbits and enable transceivers */
-	ctrlb =  
-		#ifdef FEATURE_USART_IRDA
-			(config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
-		#endif
-		#ifdef FEATURE_USART_START_FRAME_DECTION
-			(config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
-		#endif
-		#ifdef FEATURE_USART_COLLISION_DECTION
-			(config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
-		#endif
-			(config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
-			(config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
+
+    /*Set baud val */
+    usart_hw->BAUD.reg = baud;
+
+    /* Set sample mode */
+    ctrla |= transfer_mode;
+
+    if (config->use_external_clock == false)
+    {
+        ctrla |= SERCOM_USART_CTRLA_MODE(0x1);
+    }
+    else {
+        ctrla |= SERCOM_USART_CTRLA_MODE(0x0);
+    }
+
+    /* Set stopbits and enable transceivers */
+    ctrlb =
+        #ifdef FEATURE_USART_IRDA
+            (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) |
+        #endif
+        #ifdef FEATURE_USART_START_FRAME_DECTION
+            (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) |
+        #endif
+        #ifdef FEATURE_USART_COLLISION_DECTION
+            (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) |
+        #endif
+            (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) |
+            (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos);
 
 #ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
-		if (config->iso7816_config.enable_inverse) {
-			ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
-		}
-		ctrlb |=  USART_CHARACTER_SIZE_8BIT;
-		
-		switch(config->iso7816_config.protocol_t) {
-			case ISO7816_PROTOCOL_T_0:
-				ctrlb |= (uint32_t)config->stopbits;	
-				ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
-						(config->iso7816_config.inhibit_nack) | \
-						(config->iso7816_config.successive_recv_nack) | \
-						SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
-				break;	
-			case ISO7816_PROTOCOL_T_1:
-				ctrlb |= USART_STOPBITS_1;
-				break;		
-		}
-	} else {
+    if(config->iso7816_config.enabled)
+    {
+        ctrla |= SERCOM_USART_CTRLA_FORM(0x07);
+        if (config->iso7816_config.enable_inverse)
+        {
+            ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV;
+        }
+        ctrlb |=  USART_CHARACTER_SIZE_8BIT;
+
+        switch(config->iso7816_config.protocol_t)
+        {
+            case ISO7816_PROTOCOL_T_0:
+                ctrlb |= (uint32_t)config->stopbits;
+                ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \
+                        (config->iso7816_config.inhibit_nack) | \
+                        (config->iso7816_config.successive_recv_nack) | \
+                        SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations);
+                break;
+            case ISO7816_PROTOCOL_T_1:
+                ctrlb |= USART_STOPBITS_1;
+                break;
+        }
+    } else {
 #endif
-	ctrlb |= (uint32_t)config->stopbits;
-	ctrlb |= (uint32_t)config->character_size;
-	/* Check parity mode bits */
-	if (config->parity != USART_PARITY_NONE) {
-		ctrla |= SERCOM_USART_CTRLA_FORM(1);
-		ctrlb |= config->parity;
-	} else {
+    ctrlb |= (uint32_t)config->stopbits;
+    ctrlb |= (uint32_t)config->character_size;
+    /* Check parity mode bits */
+    if (config->parity != USART_PARITY_NONE)
+    {
+        ctrla |= SERCOM_USART_CTRLA_FORM(1);
+        ctrlb |= config->parity;
+    } else {
 #ifdef FEATURE_USART_LIN_SLAVE
-		if(config->lin_slave_enable) {
-			ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
-		} else {
-			ctrla |= SERCOM_USART_CTRLA_FORM(0);
-		}
+        if(config->lin_slave_enable)
+        {
+            ctrla |= SERCOM_USART_CTRLA_FORM(0x4);
+        } else {
+            ctrla |= SERCOM_USART_CTRLA_FORM(0);
+        }
 #else
-		ctrla |= SERCOM_USART_CTRLA_FORM(0);
+        ctrla |= SERCOM_USART_CTRLA_FORM(0);
 #endif
-	}
+    }
 #ifdef FEATURE_USART_ISO7816
-	}
+    }
 #endif
 
 #ifdef FEATURE_USART_LIN_MASTER
-	usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
-						| config->lin_header_delay
-						| config->lin_break_length;
-
-	if (config->lin_node != LIN_INVALID_MODE) {
-		ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
-		ctrla |= config->lin_node;
-	}
+    usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk)
+                        | config->lin_header_delay
+                        | config->lin_break_length;
+
+    if (config->lin_node != LIN_INVALID_MODE)
+    {
+        ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf));
+        ctrla |= config->lin_node;
+    }
 #endif
 
-	/* Set whether module should run in standby. */
-	if (config->run_in_standby || system_is_debugger_present()) {
-		ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
-	}
+    /* Set whether module should run in standby. */
+    if (config->run_in_standby || system_is_debugger_present())
+    {
+        ctrla |= SERCOM_USART_CTRLA_RUNSTDBY;
+    }
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Write configuration to CTRLB */
-	usart_hw->CTRLB.reg = ctrlb;
+    /* Write configuration to CTRLB */
+    usart_hw->CTRLB.reg = ctrlb;
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Write configuration to CTRLA */
-	usart_hw->CTRLA.reg = ctrla;
+    /* Write configuration to CTRLA */
+    usart_hw->CTRLA.reg = ctrla;
 
 #ifdef FEATURE_USART_RS485
-	if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
-		SERCOM_USART_CTRLA_FORM(0x07)) {
-		usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
-		usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
-	}
+    if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \
+        SERCOM_USART_CTRLA_FORM(0x07))
+        {
+        usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7));
+        usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time);
+    }
 #endif
 
 #ifdef FEATURE_USART_ISO7816
-	if(config->iso7816_config.enabled) {
-		_usart_wait_for_sync(module);
-		usart_hw->CTRLC.reg = ctrlc;
-	}
+    if(config->iso7816_config.enabled)
+    {
+        _usart_wait_for_sync(module);
+        usart_hw->CTRLC.reg = ctrlc;
+    }
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -317,147 +334,157 @@ static enum status_code _usart_set_config(
  *                                         the current clock configuration
  */
 enum status_code usart_init(
-		struct usart_module *const module,
-		Sercom *const hw,
-		const struct usart_config *const config)
+        struct usart_module *const module,
+        Sercom *const hw,
+        const struct usart_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	enum status_code status_code = STATUS_OK;
+    enum status_code status_code = STATUS_OK;
 
-	/* Assign module pointer to software instance struct */
-	module->hw = hw;
+    /* Assign module pointer to software instance struct */
+    module->hw = hw;
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
-	uint32_t pm_index, gclk_index; 
-#if (SAML22) || (SAMC20) 
-	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+    uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
+    uint32_t pm_index, gclk_index;
+#if (SAML22) || (SAMC20)
+    pm_index    = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+    gclk_index  = sercom_index + SERCOM0_GCLK_ID_CORE;
 #elif (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
-		gclk_index   = SERCOM5_GCLK_ID_CORE;
-	} else {
-		pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-		gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
-	}
+    if (sercom_index == 5)
+    {
+        pm_index     = MCLK_APBDMASK_SERCOM5_Pos;
+        gclk_index   = SERCOM5_GCLK_ID_CORE;
+    } else {
+        pm_index     = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+        gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    }
 #elif (SAMC21)
-	pm_index	= sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
-	
-	if (sercom_index == 5){
-		gclk_index	= SERCOM5_GCLK_ID_CORE;
+    pm_index    = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
+
+    if (sercom_index == 5)
+    {
+        gclk_index  = SERCOM5_GCLK_ID_CORE;
     } else {
-    	gclk_index	= sercom_index + SERCOM0_GCLK_ID_CORE;
+        gclk_index  = sercom_index + SERCOM0_GCLK_ID_CORE;
     }
 #else
-	pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
-	gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
+    pm_index     = sercom_index + PM_APBCMASK_SERCOM0_Pos;
+    gclk_index   = sercom_index + SERCOM0_GCLK_ID_CORE;
 #endif
 
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) {
-		/* The module is busy resetting itself */
-		return STATUS_BUSY;
-	}
+    if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST)
+    {
+        /* The module is busy resetting itself */
+        return STATUS_BUSY;
+    }
 
-	if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) {
-		/* Check the module is enabled */
-		return STATUS_ERR_DENIED;
-	}
+    if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE)
+    {
+        /* Check the module is enabled */
+        return STATUS_ERR_DENIED;
+    }
 
-	/* Turn on module in PM */
+    /* Turn on module in PM */
 #if (SAML21) || (SAMR30)
-	if (sercom_index == 5) {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
-	} else {
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);	
-	}
+    if (sercom_index == 5)
+    {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
+    } else {
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    }
 #else
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
 #endif
 
-	/* Set up the GCLK for the module */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->generator_source;
-	system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
-	system_gclk_chan_enable(gclk_index);
-	sercom_set_gclk_generator(config->generator_source, false);
+    /* Set up the GCLK for the module */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->generator_source;
+    system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
+    system_gclk_chan_enable(gclk_index);
+    sercom_set_gclk_generator(config->generator_source, false);
 
-	/* Set character size */
-	module->character_size = config->character_size;
+    /* Set character size */
+    module->character_size = config->character_size;
 
-	/* Set transmitter and receiver status */
-	module->receiver_enabled = config->receiver_enable;
-	module->transmitter_enabled = config->transmitter_enable;
+    /* Set transmitter and receiver status */
+    module->receiver_enabled = config->receiver_enable;
+    module->transmitter_enabled = config->transmitter_enable;
 
 #ifdef FEATURE_USART_LIN_SLAVE
-	module->lin_slave_enabled = config->lin_slave_enable;
+    module->lin_slave_enabled = config->lin_slave_enable;
 #endif
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	module->start_frame_detection_enabled = config->start_frame_detection_enable;
+    module->start_frame_detection_enabled = config->start_frame_detection_enable;
 #endif
 #ifdef FEATURE_USART_ISO7816
-	module->iso7816_mode_enabled = config->iso7816_config.enabled;
+    module->iso7816_mode_enabled = config->iso7816_config.enabled;
 #endif
-	/* Set configuration according to the config struct */
-	status_code = _usart_set_config(module, config);
-	if(status_code != STATUS_OK) {
-		return status_code;
-	}
-
-	struct system_pinmux_config pin_conf;
-	system_pinmux_get_config_defaults(&pin_conf);
-	pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
-
-	uint32_t pad_pinmuxes[] = {
-			config->pinmux_pad0, config->pinmux_pad1,
-			config->pinmux_pad2, config->pinmux_pad3
-		};
-
-	/* Configure the SERCOM pins according to the user configuration */
-	for (uint8_t pad = 0; pad < 4; pad++) {
-		uint32_t current_pinmux = pad_pinmuxes[pad];
-
-		if (current_pinmux == PINMUX_DEFAULT) {
-			current_pinmux = _sercom_get_default_pad(hw, pad);
-		}
-
-		if (current_pinmux != PINMUX_UNUSED) {
-			pin_conf.mux_position = current_pinmux & 0xFFFF;
-			system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
-		}
-	}
+    /* Set configuration according to the config struct */
+    status_code = _usart_set_config(module, config);
+    if(status_code != STATUS_OK)
+    {
+        return status_code;
+    }
+
+    struct system_pinmux_config pin_conf;
+    system_pinmux_get_config_defaults(&pin_conf);
+    pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
+
+    uint32_t pad_pinmuxes[] = {
+            config->pinmux_pad0, config->pinmux_pad1,
+            config->pinmux_pad2, config->pinmux_pad3
+        };
+
+    /* Configure the SERCOM pins according to the user configuration */
+    for (uint8_t pad = 0; pad < 4; pad++)
+    {
+        uint32_t current_pinmux = pad_pinmuxes[pad];
+
+        if (current_pinmux == PINMUX_DEFAULT)
+        {
+            current_pinmux = _sercom_get_default_pad(hw, pad);
+        }
+
+        if (current_pinmux != PINMUX_UNUSED)
+        {
+            pin_conf.mux_position = current_pinmux & 0xFFFF;
+            system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf);
+        }
+    }
 
 #if USART_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint32_t i = 0; i < USART_CALLBACK_N; i++) {
-		module->callback[i]            = NULL;
-	}
-
-	module->tx_buffer_ptr              = NULL;
-	module->rx_buffer_ptr              = NULL;
-	module->remaining_tx_buffer_length = 0x0000;
-	module->remaining_rx_buffer_length = 0x0000;
-	module->callback_reg_mask          = 0x00;
-	module->callback_enable_mask       = 0x00;
-	module->rx_status                  = STATUS_OK;
-	module->tx_status                  = STATUS_OK;
-
-	/* Set interrupt handler and register USART software module struct in
-	 * look-up table */
-	uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
-	_sercom_set_handler(instance_index, _usart_interrupt_handler);
-	_sercom_instances[instance_index] = module;
+    /* Initialize parameters */
+    for (uint32_t i = 0; i < USART_CALLBACK_N; i++)
+    {
+        module->callback[i]            = NULL;
+    }
+
+    module->tx_buffer_ptr              = NULL;
+    module->rx_buffer_ptr              = NULL;
+    module->remaining_tx_buffer_length = 0x0000;
+    module->remaining_rx_buffer_length = 0x0000;
+    module->callback_reg_mask          = 0x00;
+    module->callback_enable_mask       = 0x00;
+    module->rx_status                  = STATUS_OK;
+    module->tx_status                  = STATUS_OK;
+
+    /* Set interrupt handler and register USART software module struct in
+     * look-up table */
+    uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
+    _sercom_set_handler(instance_index, _usart_interrupt_handler);
+    _sercom_instances[instance_index] = module;
 #endif
 
-	return status_code;
+    return status_code;
 }
 
 /**
@@ -476,46 +503,50 @@ enum status_code usart_init(
  * \retval STATUS_ERR_DENIED If the transmitter is not enabled
  */
 enum status_code usart_write_wait(
-		struct usart_module *const module,
-		const uint16_t tx_data)
+        struct usart_module *const module,
+        const uint16_t tx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    /* Check that the transmitter is enabled */
+    if (!(module->transmitter_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 
 #if USART_CALLBACK_MODE == true
-	/* Check if the USART is busy doing asynchronous operation. */
-	if (module->remaining_tx_buffer_length > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the USART is busy doing asynchronous operation. */
+    if (module->remaining_tx_buffer_length > 0)
+    {
+        return STATUS_BUSY;
+    }
 
 #else
-	/* Check if USART is ready for new data */
-	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
-		/* Return error code */
-		return STATUS_BUSY;
-	}
+    /* Check if USART is ready for new data */
+    if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE))
+    {
+        /* Return error code */
+        return STATUS_BUSY;
+    }
 #endif
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Write data to USART module */
-	usart_hw->DATA.reg = tx_data;
+    /* Write data to USART module */
+    usart_hw->DATA.reg = tx_data;
 
-	while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
-		/* Wait until data is sent */
-	}
+    while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC))
+    {
+        /* Wait until data is sent */
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -541,89 +572,98 @@ enum status_code usart_write_wait(
  * \retval STATUS_ERR_DENIED        If the receiver is not enabled
  */
 enum status_code usart_read_wait(
-		struct usart_module *const module,
-		uint16_t *const rx_data)
+        struct usart_module *const module,
+        uint16_t *const rx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Error variable */
-	uint8_t error_code;
+    /* Error variable */
+    uint8_t error_code;
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    /* Check that the receiver is enabled */
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 
 #if USART_CALLBACK_MODE == true
-	/* Check if the USART is busy doing asynchronous operation. */
-	if (module->remaining_rx_buffer_length > 0) {
-		return STATUS_BUSY;
-	}
+    /* Check if the USART is busy doing asynchronous operation. */
+    if (module->remaining_rx_buffer_length > 0)
+    {
+        return STATUS_BUSY;
+    }
 #endif
 
-	/* Check if USART has new data */
-	if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
-		/* Return error code */
-		return STATUS_BUSY;
-	}
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	/* Read out the status code and mask away all but the 3 LSBs*/
-	error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
-
-	/* Check if an error has occurred during the receiving */
-	if (error_code) {
-		/* Check which error occurred */
-		if (error_code & SERCOM_USART_STATUS_FERR) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-
-			return STATUS_ERR_BAD_FORMAT;
-		} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-
-			return STATUS_ERR_OVERFLOW;
-		} else if (error_code & SERCOM_USART_STATUS_PERR) {
-			/* Clear flag by writing a 1 to it and
-			 * return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-
-			return STATUS_ERR_BAD_DATA;
-		}
-#ifdef FEATURE_USART_LIN_SLAVE
-		else if (error_code & SERCOM_USART_STATUS_ISF) {
-			/* Clear flag by writing 1 to it  and
-			 *  return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+    /* Check if USART has new data */
+    if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC))
+    {
+        /* Return error code */
+        return STATUS_BUSY;
+    }
 
-			return STATUS_ERR_PROTOCOL;
-		}
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
+
+    /* Read out the status code and mask away all but the 3 LSBs*/
+    error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+
+    /* Check if an error has occurred during the receiving */
+    if (error_code)
+    {
+        /* Check which error occurred */
+        if (error_code & SERCOM_USART_STATUS_FERR)
+        {
+            /* Clear flag by writing a 1 to it and
+             * return with an error code */
+            usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+
+            return STATUS_ERR_BAD_FORMAT;
+        } else if (error_code & SERCOM_USART_STATUS_BUFOVF)
+        {
+            /* Clear flag by writing a 1 to it and
+             * return with an error code */
+            usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+
+            return STATUS_ERR_OVERFLOW;
+        } else if (error_code & SERCOM_USART_STATUS_PERR)
+        {
+            /* Clear flag by writing a 1 to it and
+             * return with an error code */
+            usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+
+            return STATUS_ERR_BAD_DATA;
+        }
+#ifdef FEATURE_USART_LIN_SLAVE
+        else if (error_code & SERCOM_USART_STATUS_ISF)
+        {
+            /* Clear flag by writing 1 to it  and
+             *  return with an error code */
+            usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+
+            return STATUS_ERR_PROTOCOL;
+        }
 #endif
 #ifdef FEATURE_USART_COLLISION_DECTION
-		else if (error_code & SERCOM_USART_STATUS_COLL) {
-			/* Clear flag by writing 1 to it
-			 *  return with an error code */
-			usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-
-			return STATUS_ERR_PACKET_COLLISION;
-		}
+        else if (error_code & SERCOM_USART_STATUS_COLL)
+        {
+            /* Clear flag by writing 1 to it
+             *  return with an error code */
+            usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+
+            return STATUS_ERR_PACKET_COLLISION;
+        }
 #endif
-	}
+    }
 
-	/* Read data from USART module */
-	*rx_data = usart_hw->DATA.reg;
+    /* Read data from USART module */
+    *rx_data = usart_hw->DATA.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -640,8 +680,8 @@ enum status_code usart_read_wait(
  * \param[in]  tx_data  Pointer to data to transmit
  * \param[in]  length   Number of characters to transmit
  *
- * \note If using 9-bit data, the array that *tx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ * \note If using 9-bit data, the array that *tx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it
  *       is an address pointer, the highest byte is not discarded. For example:
  *   \code
           #define TX_LEN 3
@@ -658,66 +698,76 @@ enum status_code usart_read_wait(
  * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
  */
 enum status_code usart_write_buffer_wait(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        const uint8_t *tx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Check if the buffer length is valid */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	uint16_t tx_pos = 0;
-
-	/* Blocks while buffer is being transferred */
-	while (length--) {
-		/* Wait for the USART to be ready for new data and abort
-		* operation if it doesn't get ready within the timeout*/
-		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) {
-				break;
-			} else if (i == USART_TIMEOUT) {
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-
-		/* Data to send is at least 8 bits long */
-		uint16_t data_to_send = tx_data[tx_pos++];
-
-		/* Check if the character size exceeds 8 bit */
-		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-			data_to_send |= (tx_data[tx_pos++] << 8);
-		}
-
-		/* Send the data through the USART module */
-		usart_write_wait(module, data_to_send);
-	}
-
-	/* Wait until Transmit is complete or timeout */
-	for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-		if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) {
-			break;
-		} else if (i == USART_TIMEOUT) {
-			return STATUS_ERR_TIMEOUT;
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Check if the buffer length is valid */
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check that the transmitter is enabled */
+    if (!(module->transmitter_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
+
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
+
+    uint16_t tx_pos = 0;
+
+    /* Blocks while buffer is being transferred */
+    while (length--)
+    {
+        /* Wait for the USART to be ready for new data and abort
+        * operation if it doesn't get ready within the timeout*/
+        for (uint32_t i = 0; i <= USART_TIMEOUT; i++)
+        {
+            if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)
+            {
+                break;
+            } else if (i == USART_TIMEOUT)
+            {
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
+
+        /* Data to send is at least 8 bits long */
+        uint16_t data_to_send = tx_data[tx_pos++];
+
+        /* Check if the character size exceeds 8 bit */
+        if (module->character_size == USART_CHARACTER_SIZE_9BIT)
+        {
+            data_to_send |= (tx_data[tx_pos++] << 8);
+        }
+
+        /* Send the data through the USART module */
+        usart_write_wait(module, data_to_send);
+    }
+
+    /* Wait until Transmit is complete or timeout */
+    for (uint32_t i = 0; i <= USART_TIMEOUT; i++)
+    {
+        if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)
+        {
+            break;
+        } else if (i == USART_TIMEOUT)
+        {
+            return STATUS_ERR_TIMEOUT;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -734,8 +784,8 @@ enum status_code usart_write_buffer_wait(
  * \param[out] rx_data  Pointer to receive buffer
  * \param[in]  length   Number of characters to receive
  *
- * \note If using 9-bit data, the array that *rx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ * \note If using 9-bit data, the array that *rx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it
  *       is an address pointer, the highest byte is not discarded. For example:
  *   \code
           #define RX_LEN 3
@@ -760,59 +810,67 @@ enum status_code usart_write_buffer_wait(
  * \retval STATUS_ERR_DENIED        If the receiver is not enabled
  */
 enum status_code usart_read_buffer_wait(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Check if the buffer length is valid */
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	uint16_t rx_pos = 0;
-
-	/* Blocks while buffer is being received */
-	while (length--) {
-		/* Wait for the USART to have new data and abort operation if it
-		 * doesn't get ready within the timeout*/
-		for (uint32_t i = 0; i <= USART_TIMEOUT; i++) {
-			if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) {
-				break;
-			} else if (i == USART_TIMEOUT) {
-				return STATUS_ERR_TIMEOUT;
-			}
-		}
-
-		enum status_code retval;
-		uint16_t received_data = 0;
-
-		retval = usart_read_wait(module, &received_data);
-
-		if (retval != STATUS_OK) {
-			/* Overflow, abort */
-			return retval;
-		}
-
-		/* Read value will be at least 8-bits long */
-		rx_data[rx_pos++] = received_data;
-
-		/* If 9-bit data, write next received byte to the buffer */
-		if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-			rx_data[rx_pos++] = (received_data >> 8);
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Check if the buffer length is valid */
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check that the receiver is enabled */
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
+
+    uint16_t rx_pos = 0;
+
+    /* Blocks while buffer is being received */
+    while (length--)
+    {
+        /* Wait for the USART to have new data and abort operation if it
+         * doesn't get ready within the timeout*/
+        for (uint32_t i = 0; i <= USART_TIMEOUT; i++)
+        {
+            if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)
+            {
+                break;
+            } else if (i == USART_TIMEOUT)
+            {
+                return STATUS_ERR_TIMEOUT;
+            }
+        }
+
+        enum status_code retval;
+        uint16_t received_data = 0;
+
+        retval = usart_read_wait(module, &received_data);
+
+        if (retval != STATUS_OK)
+        {
+            /* Overflow, abort */
+            return retval;
+        }
+
+        /* Read value will be at least 8-bits long */
+        rx_data[rx_pos++] = received_data;
+
+        /* If 9-bit data, write next received byte to the buffer */
+        if (module->character_size == USART_CHARACTER_SIZE_9BIT)
+        {
+            rx_data[rx_pos++] = (received_data >> 8);
+        }
+    }
+
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h
index f1bb0d4fcd54..44991c4ee5e7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart.h
@@ -283,8 +283,8 @@ extern "C" {
  */
 
 #if (SAMD21) || (SAMR21) || (SAMD09) || (SAMD10) || (SAMD11) || \
-	(SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || \
-	(SAMR30) || (SAMHA1) || defined(__DOXYGEN__)
+    (SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || \
+    (SAMR30) || (SAMHA1) || defined(__DOXYGEN__)
 /** USART sync scheme version 2. */
 #  define FEATURE_USART_SYNC_SCHEME_V2
 /** USART oversampling. */
@@ -324,12 +324,12 @@ extern "C" {
  * LIN node type.
  */
 enum lin_node_type {
-	/** LIN master mode */
-	LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02),
-	/** LIN slave mode */
-	LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04),
-	/** Neither LIN master nor LIN slave mode */
-	LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00),
+    /** LIN master mode */
+    LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02),
+    /** LIN slave mode */
+    LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04),
+    /** Neither LIN master nor LIN slave mode */
+    LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00),
 };
 
 /**
@@ -338,10 +338,10 @@ enum lin_node_type {
  * LIN master command enum.
  */
 enum lin_master_cmd {
-	/** LIN master software control transmission command */
-	LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01),
-	/** LIN master automatically transmission command */
-	LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02),
+    /** LIN master software control transmission command */
+    LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01),
+    /** LIN master automatically transmission command */
+    LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02),
 };
 
 /**
@@ -352,18 +352,18 @@ enum lin_master_cmd {
  * This field is only valid when using automatically transmission command
  */
 enum lin_master_header_delay {
-	/** Delay between break and sync transmission is 1 bit time.
-		Delay between sync and ID transmission is 1 bit time. */
-	LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0),
-	/** Delay between break and sync transmission is 4 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01),
-	/** Delay between break and sync transmission is 8 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02),
-	/** Delay between break and sync transmission is 14 bit time.
-		Delay between sync and ID transmission is 4 bit time. */
-	LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03),
+    /** Delay between break and sync transmission is 1 bit time.
+        Delay between sync and ID transmission is 1 bit time. */
+    LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0),
+    /** Delay between break and sync transmission is 4 bit time.
+        Delay between sync and ID transmission is 4 bit time. */
+    LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01),
+    /** Delay between break and sync transmission is 8 bit time.
+        Delay between sync and ID transmission is 4 bit time. */
+    LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02),
+    /** Delay between break and sync transmission is 14 bit time.
+        Delay between sync and ID transmission is 4 bit time. */
+    LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03),
 };
 
 /**
@@ -372,14 +372,14 @@ enum lin_master_header_delay {
  * Length of the break field transmitted when in LIN master mode
  */
 enum lin_master_break_length {
-	/** Break field transmission is 13 bit times */
-	LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0),
-	/** Break field transmission is 17 bit times */
-	LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1),
-	/** Break field transmission is 21 bit times */
-	LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2),
-	/** Break field transmission is 26 bit times */
-	LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3),
+    /** Break field transmission is 13 bit times */
+    LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0),
+    /** Break field transmission is 17 bit times */
+    LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1),
+    /** Break field transmission is 21 bit times */
+    LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2),
+    /** Break field transmission is 26 bit times */
+    LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3),
 };
 #endif
 #ifdef FEATURE_USART_ISO7816
@@ -389,10 +389,10 @@ enum lin_master_break_length {
  * ISO7816 protocol type.
  */
 enum iso7816_protocol_type {
-	/** ISO7816 protocol type 0 */
-	ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE,
-	/** ISO7816 protocol type 1 */
-	ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+    /** ISO7816 protocol type 0 */
+    ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE,
+    /** ISO7816 protocol type 1 */
+    ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
 };
 
 /**
@@ -401,18 +401,18 @@ enum iso7816_protocol_type {
  * The value of ISO7816 guard time.
  */
 enum iso7816_guard_time {
-	/** The guard time is 2-bit times */
-	ISO7816_GUARD_TIME_2_BIT = 2,
-	/** The guard time is 3-bit times */
-	ISO7816_GUARD_TIME_3_BIT,
-	/** The guard time is 4-bit times */
-	ISO7816_GUARD_TIME_4_BIT,
-	/** The guard time is 5-bit times */
-	ISO7816_GUARD_TIME_5_BIT,
-	/** The guard time is 6-bit times */
-	ISO7816_GUARD_TIME_6_BIT,
-	/** The guard time is 7-bit times */
-	ISO7816_GUARD_TIME_7_BIT,
+    /** The guard time is 2-bit times */
+    ISO7816_GUARD_TIME_2_BIT = 2,
+    /** The guard time is 3-bit times */
+    ISO7816_GUARD_TIME_3_BIT,
+    /** The guard time is 4-bit times */
+    ISO7816_GUARD_TIME_4_BIT,
+    /** The guard time is 5-bit times */
+    ISO7816_GUARD_TIME_5_BIT,
+    /** The guard time is 6-bit times */
+    ISO7816_GUARD_TIME_6_BIT,
+    /** The guard time is 7-bit times */
+    ISO7816_GUARD_TIME_7_BIT,
 };
 
 /**
@@ -421,10 +421,10 @@ enum iso7816_guard_time {
  * The value of ISO7816 receive NACK inhibit.
  */
 enum iso7816_inhibit_nack {
-	/** The NACK is generated */
-	ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
-	/** The NACK is not generated */
-	ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK,
+    /** The NACK is generated */
+    ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+    /** The NACK is not generated */
+    ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK,
 };
 
 /**
@@ -433,10 +433,10 @@ enum iso7816_inhibit_nack {
  * The value of ISO7816 disable successive receive NACK.
  */
 enum iso7816_successive_recv_nack {
-	/** The successive receive NACK is enable. */
-	ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
-	/** The successive receive NACK is disable. */
-	ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK,
+    /** The successive receive NACK is enable. */
+    ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos),
+    /** The successive receive NACK is disable. */
+    ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK,
 };
 
 /**
@@ -445,31 +445,31 @@ enum iso7816_successive_recv_nack {
  * ISO7816 configuration structure.
  */
 struct iso7816_config_t {
-	/* ISO7816 mode enable */
-	bool enabled;
-	/** ISO7816 protocol type */
-	enum iso7816_protocol_type protocol_t;
-	/** Enable inverse transmission and reception */
-	bool enable_inverse;
-	/** Guard time, which lasts two bit times */
-	enum iso7816_guard_time guard_time;
-	/**
-	 * Inhibit Non Acknowledge:
-	 *   - 0: the NACK is generated;
-	 *   - 1: the NACK is not generated.
-	 */
-	enum iso7816_inhibit_nack inhibit_nack;
-	/**
-	 * Disable successive NACKs.
-	 *  - 0: NACK is sent on the ISO line as soon as a parity error occurs
-	 * in the received character. Successive parity errors are counted up to
-	 * the value in the max_iterations field. These parity errors generate
-	 * a NACK on the ISO line. As soon as this value is reached, no additional
-	 * NACK is sent on the ISO line. The ITERATION flag is asserted.
-	 */
-	enum iso7816_successive_recv_nack successive_recv_nack;
-	/* Max number of repetitions */
-	uint32_t max_iterations;
+    /* ISO7816 mode enable */
+    bool enabled;
+    /** ISO7816 protocol type */
+    enum iso7816_protocol_type protocol_t;
+    /** Enable inverse transmission and reception */
+    bool enable_inverse;
+    /** Guard time, which lasts two bit times */
+    enum iso7816_guard_time guard_time;
+    /**
+     * Inhibit Non Acknowledge:
+     *   - 0: the NACK is generated;
+     *   - 1: the NACK is not generated.
+     */
+    enum iso7816_inhibit_nack inhibit_nack;
+    /**
+     * Disable successive NACKs.
+     *  - 0: NACK is sent on the ISO line as soon as a parity error occurs
+     * in the received character. Successive parity errors are counted up to
+     * the value in the max_iterations field. These parity errors generate
+     * a NACK on the ISO line. As soon as this value is reached, no additional
+     * NACK is sent on the ISO line. The ITERATION flag is asserted.
+     */
+    enum iso7816_successive_recv_nack successive_recv_nack;
+    /* Max number of repetitions */
+    uint32_t max_iterations;
 };
 #endif
 
@@ -495,27 +495,27 @@ struct iso7816_config_t {
  * Callbacks for the Asynchronous USART driver.
  */
 enum usart_callback {
-	/** Callback for buffer transmitted */
-	USART_CALLBACK_BUFFER_TRANSMITTED,
-	/** Callback for buffer received */
-	USART_CALLBACK_BUFFER_RECEIVED,
-	/** Callback for error */
-	USART_CALLBACK_ERROR,
+    /** Callback for buffer transmitted */
+    USART_CALLBACK_BUFFER_TRANSMITTED,
+    /** Callback for buffer received */
+    USART_CALLBACK_BUFFER_RECEIVED,
+    /** Callback for error */
+    USART_CALLBACK_ERROR,
 #ifdef FEATURE_USART_LIN_SLAVE
-	/** Callback for break character is received */
-	USART_CALLBACK_BREAK_RECEIVED,
+    /** Callback for break character is received */
+    USART_CALLBACK_BREAK_RECEIVED,
 #endif
 #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	/** Callback for a change is detected on the CTS pin */
-	USART_CALLBACK_CTS_INPUT_CHANGE,
+    /** Callback for a change is detected on the CTS pin */
+    USART_CALLBACK_CTS_INPUT_CHANGE,
 #endif
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Callback for a start condition is detected on the RxD line */
-	USART_CALLBACK_START_RECEIVED,
+    /** Callback for a start condition is detected on the RxD line */
+    USART_CALLBACK_START_RECEIVED,
 #endif
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	USART_CALLBACK_N,
+    /** Number of available callbacks */
+    USART_CALLBACK_N,
 #  endif
 };
 #endif
@@ -527,12 +527,12 @@ enum usart_callback {
  * transferred.
  */
 enum usart_dataorder {
-	/** The MSB will be shifted out first during transmission,
-	 *  and shifted in first during reception */
-	USART_DATAORDER_MSB = 0,
-	/** The LSB will be shifted out first during transmission,
-	 *  and shifted in first during reception */
-	USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
+    /** The MSB will be shifted out first during transmission,
+     *  and shifted in first during reception */
+    USART_DATAORDER_MSB = 0,
+    /** The LSB will be shifted out first during transmission,
+     *  and shifted in first during reception */
+    USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD,
 };
 
 /**
@@ -541,10 +541,10 @@ enum usart_dataorder {
  * Select USART transfer mode.
  */
 enum usart_transfer_mode {
-	/** Transfer of data is done synchronously */
-	USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
-	/** Transfer of data is done asynchronously */
-	USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
+    /** Transfer of data is done synchronously */
+    USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE),
+    /** Transfer of data is done asynchronously */
+    USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos),
 };
 
 /**
@@ -553,17 +553,17 @@ enum usart_transfer_mode {
  * Select parity USART parity mode.
  */
 enum usart_parity {
-	/** For odd parity checking, the parity bit will be set if number of
-	 *  ones being transferred is even */
-	USART_PARITY_ODD  = SERCOM_USART_CTRLB_PMODE,
+    /** For odd parity checking, the parity bit will be set if number of
+     *  ones being transferred is even */
+    USART_PARITY_ODD  = SERCOM_USART_CTRLB_PMODE,
 
-	/** For even parity checking, the parity bit will be set if number of
-	 *  ones being received is odd */
-	USART_PARITY_EVEN = 0,
+    /** For even parity checking, the parity bit will be set if number of
+     *  ones being received is odd */
+    USART_PARITY_EVEN = 0,
 
-	/** No parity checking will be executed, and there will be no parity bit
-	 *  in the received frame */
-	USART_PARITY_NONE = 0xFF,
+    /** No parity checking will be executed, and there will be no parity bit
+     *  in the received frame */
+    USART_PARITY_NONE = 0xFF,
 };
 
 /**
@@ -576,57 +576,57 @@ enum usart_parity {
  */
 enum usart_signal_mux_settings {
 #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	/** MUX setting RX_0_TX_0_XCK_1 */
-	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_0_TX_2_XCK_3 */
-	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
-	USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_1_TX_0_XCK_1 */
-	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_1_TX_2_XCK_3 */
-	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
-	USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_2_TX_0_XCK_1 */
-	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_2_TX_2_XCK_3 */
-	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
-	USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
-	/** MUX setting RX_3_TX_0_XCK_1 */
-	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
-	/** MUX setting RX_3_TX_2_XCK_3 */
-	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
-	/** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
-	USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
+    /** MUX setting RX_0_TX_0_XCK_1 */
+    USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)),
+    /** MUX setting RX_0_TX_2_XCK_3 */
+    USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)),
+    /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */
+    USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)),
+    /** MUX setting RX_1_TX_0_XCK_1 */
+    USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)),
+    /** MUX setting RX_1_TX_2_XCK_3 */
+    USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)),
+    /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */
+    USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)),
+    /** MUX setting RX_2_TX_0_XCK_1 */
+    USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)),
+    /** MUX setting RX_2_TX_2_XCK_3 */
+    USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)),
+    /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */
+    USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)),
+    /** MUX setting RX_3_TX_0_XCK_1 */
+    USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)),
+    /** MUX setting RX_3_TX_2_XCK_3 */
+    USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)),
+    /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */
+    USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)),
 #ifdef FEATURE_USART_RS485
-	/** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */
-	USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */
-	USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */
-	USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)),
-	/** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */
-	USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)),
+    /** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */
+    USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)),
+    /** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */
+    USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)),
+    /** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */
+    USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)),
+    /** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */
+    USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)),
 #endif
 #else
-	/** MUX setting RX_0_TX_0_XCK_1 */
-	USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
-	/** MUX setting RX_0_TX_2_XCK_3 */
-	USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_1_TX_0_XCK_1 */
-	USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
-	/** MUX setting RX_1_TX_2_XCK_3 */
-	USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_2_TX_0_XCK_1 */
-	USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
-	/** MUX setting RX_2_TX_2_XCK_3 */
-	USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
-	/** MUX setting RX_3_TX_0_XCK_1 */
-	USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
-	/** MUX setting RX_3_TX_2_XCK_3 */
-	USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
+    /** MUX setting RX_0_TX_0_XCK_1 */
+    USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)),
+    /** MUX setting RX_0_TX_2_XCK_3 */
+    USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO),
+    /** MUX setting RX_1_TX_0_XCK_1 */
+    USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)),
+    /** MUX setting RX_1_TX_2_XCK_3 */
+    USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO),
+    /** MUX setting RX_2_TX_0_XCK_1 */
+    USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)),
+    /** MUX setting RX_2_TX_2_XCK_3 */
+    USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO),
+    /** MUX setting RX_3_TX_0_XCK_1 */
+    USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)),
+    /** MUX setting RX_3_TX_2_XCK_3 */
+    USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO),
 #endif
 };
 
@@ -636,10 +636,10 @@ enum usart_signal_mux_settings {
  * Number of stop bits for a frame.
  */
 enum usart_stopbits {
-	/** Each transferred frame contains one stop bit */
-	USART_STOPBITS_1 = 0,
-	/** Each transferred frame contains two stop bits */
-	USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
+    /** Each transferred frame contains one stop bit */
+    USART_STOPBITS_1 = 0,
+    /** Each transferred frame contains two stop bits */
+    USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE,
 };
 
 /**
@@ -648,16 +648,16 @@ enum usart_stopbits {
  * Number of bits for the character sent in a frame.
  */
 enum usart_character_size {
-	/** The char being sent in a frame is five bits long */
-	USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
-	/** The char being sent in a frame is six bits long */
-	USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
-	/** The char being sent in a frame is seven bits long */
-	USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
-	/** The char being sent in a frame is eight bits long */
-	USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
-	/** The char being sent in a frame is nine bits long */
-	USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
+    /** The char being sent in a frame is five bits long */
+    USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5),
+    /** The char being sent in a frame is six bits long */
+    USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6),
+    /** The char being sent in a frame is seven bits long */
+    USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7),
+    /** The char being sent in a frame is eight bits long */
+    USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0),
+    /** The char being sent in a frame is nine bits long */
+    USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1),
 };
 
 #ifdef FEATURE_USART_OVER_SAMPLE
@@ -667,16 +667,16 @@ enum usart_character_size {
  * The value of sample rate and baudrate generation mode.
  */
 enum usart_sample_rate {
-	/** 16x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
-	/** 16x over-sampling using fractional baudrate generation */
-	USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
-	/** 8x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
-	/** 8x over-sampling using fractional baudrate generation */
-	USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
-	/** 3x over-sampling using arithmetic baudrate generation */
-	USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
+    /** 16x over-sampling using arithmetic baudrate generation */
+    USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0),
+    /** 16x over-sampling using fractional baudrate generation */
+    USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1),
+    /** 8x over-sampling using arithmetic baudrate generation */
+    USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2),
+    /** 8x over-sampling using fractional baudrate generation */
+    USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3),
+    /** 3x over-sampling using arithmetic baudrate generation */
+    USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4),
 };
 
 /**
@@ -685,14 +685,14 @@ enum usart_sample_rate {
  * The value of sample number used for majority voting.
  */
 enum usart_sample_adjustment {
-	/** The first, middle and last sample number used for majority voting is 7-8-9 */
-	USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
-	/** The first, middle and last sample number used for majority voting is 9-10-11 */
-	USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
-	/** The first, middle and last sample number used for majority voting is 11-12-13 */
-	USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
-	/** The first, middle and last sample number used for majority voting is 13-14-15 */
-	USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
+    /** The first, middle and last sample number used for majority voting is 7-8-9 */
+    USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0),
+    /** The first, middle and last sample number used for majority voting is 9-10-11 */
+    USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1),
+    /** The first, middle and last sample number used for majority voting is 11-12-13 */
+    USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2),
+    /** The first, middle and last sample number used for majority voting is 13-14-15 */
+    USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3),
 };
 #endif
 
@@ -703,22 +703,22 @@ enum usart_sample_adjustment {
  * The value of RS485 guard time.
  */
 enum rs485_guard_time {
-	/** The guard time is 0-bit time */
-	RS485_GUARD_TIME_0_BIT = 0,
-	/** The guard time is 1-bit time */
-	RS485_GUARD_TIME_1_BIT,
-	/** The guard time is 2-bit times */
-	RS485_GUARD_TIME_2_BIT,
-	/** The guard time is 3-bit times */
-	RS485_GUARD_TIME_3_BIT,
-	/** The guard time is 4-bit times */
-	RS485_GUARD_TIME_4_BIT,
-	/** The guard time is 5-bit times */
-	RS485_GUARD_TIME_5_BIT,
-	/** The guard time is 6-bit times */
-	RS485_GUARD_TIME_6_BIT,
-	/** The guard time is 7-bit times */
-	RS485_GUARD_TIME_7_BIT,
+    /** The guard time is 0-bit time */
+    RS485_GUARD_TIME_0_BIT = 0,
+    /** The guard time is 1-bit time */
+    RS485_GUARD_TIME_1_BIT,
+    /** The guard time is 2-bit times */
+    RS485_GUARD_TIME_2_BIT,
+    /** The guard time is 3-bit times */
+    RS485_GUARD_TIME_3_BIT,
+    /** The guard time is 4-bit times */
+    RS485_GUARD_TIME_4_BIT,
+    /** The guard time is 5-bit times */
+    RS485_GUARD_TIME_5_BIT,
+    /** The guard time is 6-bit times */
+    RS485_GUARD_TIME_6_BIT,
+    /** The guard time is 7-bit times */
+    RS485_GUARD_TIME_7_BIT,
 };
 #endif
 
@@ -728,10 +728,10 @@ enum rs485_guard_time {
  * Select Receiver or Transmitter.
  */
 enum usart_transceiver_type {
-	/** The parameter is for the Receiver */
-	USART_TRANSCEIVER_RX,
-	/** The parameter is for the Transmitter */
-	USART_TRANSCEIVER_TX,
+    /** The parameter is for the Receiver */
+    USART_TRANSCEIVER_RX,
+    /** The parameter is for the Transmitter */
+    USART_TRANSCEIVER_TX,
 };
 
 /**
@@ -740,123 +740,123 @@ enum usart_transceiver_type {
  * Configuration options for USART.
  */
 struct usart_config {
-	/** USART bit order (MSB or LSB first) */
-	enum usart_dataorder data_order;
-	/** USART in asynchronous or synchronous mode */
-	enum usart_transfer_mode transfer_mode;
-	/** USART parity */
-	enum usart_parity parity;
-	/** Number of stop bits */
-	enum usart_stopbits stopbits;
-	/** USART character size */
-	enum usart_character_size character_size;
-	/** USART pin out */
-	enum usart_signal_mux_settings mux_setting;
+    /** USART bit order (MSB or LSB first) */
+    enum usart_dataorder data_order;
+    /** USART in asynchronous or synchronous mode */
+    enum usart_transfer_mode transfer_mode;
+    /** USART parity */
+    enum usart_parity parity;
+    /** Number of stop bits */
+    enum usart_stopbits stopbits;
+    /** USART character size */
+    enum usart_character_size character_size;
+    /** USART pin out */
+    enum usart_signal_mux_settings mux_setting;
 #ifdef FEATURE_USART_OVER_SAMPLE
-	/** USART sample rate */
-	enum usart_sample_rate sample_rate;
-	/** USART sample adjustment */
-	enum usart_sample_adjustment sample_adjustment;
+    /** USART sample rate */
+    enum usart_sample_rate sample_rate;
+    /** USART sample adjustment */
+    enum usart_sample_adjustment sample_adjustment;
 #endif
 #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-	/** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */
-	bool immediate_buffer_overflow_notification;
+    /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */
+    bool immediate_buffer_overflow_notification;
 #endif
 #ifdef FEATURE_USART_IRDA
-	/** Enable IrDA encoding format */
-	bool encoding_format_enable;
-	/** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */
-	uint8_t receive_pulse_length;
+    /** Enable IrDA encoding format */
+    bool encoding_format_enable;
+    /** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */
+    uint8_t receive_pulse_length;
 #endif
 #ifdef FEATURE_USART_LIN_SLAVE
-	/** Enable LIN Slave Support */
-	bool lin_slave_enable;
+    /** Enable LIN Slave Support */
+    bool lin_slave_enable;
 #endif
 
 #ifdef FEATURE_USART_LIN_MASTER
-	/** LIN node type */
-	enum lin_node_type lin_node;
-	/** LIN master header delay */
-	enum lin_master_header_delay lin_header_delay;
-	/** LIN Master Break Length */
-	enum lin_master_break_length lin_break_length;
+    /** LIN node type */
+    enum lin_node_type lin_node;
+    /** LIN master header delay */
+    enum lin_master_header_delay lin_header_delay;
+    /** LIN Master Break Length */
+    enum lin_master_break_length lin_break_length;
 #endif
 
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Enable start of frame dection */
-	bool start_frame_detection_enable;
+    /** Enable start of frame dection */
+    bool start_frame_detection_enable;
 #endif
 #ifdef FEATURE_USART_ISO7816
-	/** Enable ISO7816 for smart card interfacing */
-	struct iso7816_config_t iso7816_config;
+    /** Enable ISO7816 for smart card interfacing */
+    struct iso7816_config_t iso7816_config;
 #endif
 #ifdef FEATURE_USART_RS485
-	/** RS485 guard time */
-	enum rs485_guard_time rs485_guard_time;
+    /** RS485 guard time */
+    enum rs485_guard_time rs485_guard_time;
 #endif
 #ifdef FEATURE_USART_COLLISION_DECTION
-	/** Enable collision dection */
-	bool collision_detection_enable;
+    /** Enable collision dection */
+    bool collision_detection_enable;
 #endif
-	/** USART baudrate */
-	uint32_t baudrate;
-	/** Enable receiver */
-	bool receiver_enable;
-	/** Enable transmitter */
-	bool transmitter_enable;
-
-	/** USART Clock Polarity.
-	 * If true, data changes on falling XCK edge and
-	 * is sampled at rising edge.
-	 * If false, data changes on rising XCK edge and
-	 * is sampled at falling edge.
-	 * */
-	bool clock_polarity_inverted;
-
-	/** States whether to use the external clock applied to the XCK pin.
-	 * In synchronous mode the shift register will act directly on the XCK clock.
-	 * In asynchronous mode the XCK will be the input to the USART hardware module.
-	 */
-	bool use_external_clock;
-	/** External clock frequency in synchronous mode.
-	 * This must be set if \c use_external_clock is true. */
-	uint32_t ext_clock_freq;
-	/** If true the USART will be kept running in Standby sleep mode */
-	bool run_in_standby;
-	/** GCLK generator source */
-	enum gclk_generator generator_source;
-	/** PAD0 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD0, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD0.
-	 */
-	uint32_t pinmux_pad0;
-	/** PAD1 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD1, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD1.
-	 */
-	uint32_t pinmux_pad1;
-	/** PAD2 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD2, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD2.
-	 */
-	uint32_t pinmux_pad2;
-	/** PAD3 pinmux.
-	 *
-	 * If current USARTx has several alternative multiplexing I/O pins for PAD3, then
-	 * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3
-	 * function. Make sure that no other alternative multiplexing I/O is associated
-	 * with the same USARTx PAD3.
-	 */
-	uint32_t pinmux_pad3;
+    /** USART baudrate */
+    uint32_t baudrate;
+    /** Enable receiver */
+    bool receiver_enable;
+    /** Enable transmitter */
+    bool transmitter_enable;
+
+    /** USART Clock Polarity.
+     * If true, data changes on falling XCK edge and
+     * is sampled at rising edge.
+     * If false, data changes on rising XCK edge and
+     * is sampled at falling edge.
+     * */
+    bool clock_polarity_inverted;
+
+    /** States whether to use the external clock applied to the XCK pin.
+     * In synchronous mode the shift register will act directly on the XCK clock.
+     * In asynchronous mode the XCK will be the input to the USART hardware module.
+     */
+    bool use_external_clock;
+    /** External clock frequency in synchronous mode.
+     * This must be set if \c use_external_clock is true. */
+    uint32_t ext_clock_freq;
+    /** If true the USART will be kept running in Standby sleep mode */
+    bool run_in_standby;
+    /** GCLK generator source */
+    enum gclk_generator generator_source;
+    /** PAD0 pinmux.
+     *
+     * If current USARTx has several alternative multiplexing I/O pins for PAD0, then
+     * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0
+     * function. Make sure that no other alternative multiplexing I/O is associated
+     * with the same USARTx PAD0.
+     */
+    uint32_t pinmux_pad0;
+    /** PAD1 pinmux.
+     *
+     * If current USARTx has several alternative multiplexing I/O pins for PAD1, then
+     * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1
+     * function. Make sure that no other alternative multiplexing I/O is associated
+     * with the same USARTx PAD1.
+     */
+    uint32_t pinmux_pad1;
+    /** PAD2 pinmux.
+     *
+     * If current USARTx has several alternative multiplexing I/O pins for PAD2, then
+     * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2
+     * function. Make sure that no other alternative multiplexing I/O is associated
+     * with the same USARTx PAD2.
+     */
+    uint32_t pinmux_pad2;
+    /** PAD3 pinmux.
+     *
+     * If current USARTx has several alternative multiplexing I/O pins for PAD3, then
+     * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3
+     * function. Make sure that no other alternative multiplexing I/O is associated
+     * with the same USARTx PAD3.
+     */
+    uint32_t pinmux_pad3;
 };
 
 #if USART_CALLBACK_MODE == true
@@ -886,49 +886,49 @@ typedef void (*usart_callback_t)(struct usart_module *const module);
  */
 struct usart_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to the hardware instance */
-	Sercom *hw;
-	/** Module lock */
-	volatile bool locked;
-	/** Character size of the data being transferred */
-	enum usart_character_size character_size;
-	/** Receiver enabled */
-	bool receiver_enabled;
-	/** Transmitter enabled */
-	bool transmitter_enabled;
+    /** Pointer to the hardware instance */
+    Sercom *hw;
+    /** Module lock */
+    volatile bool locked;
+    /** Character size of the data being transferred */
+    enum usart_character_size character_size;
+    /** Receiver enabled */
+    bool receiver_enabled;
+    /** Transmitter enabled */
+    bool transmitter_enabled;
 #ifdef FEATURE_USART_LIN_SLAVE
-	/** LIN Slave Support enabled */
-	bool lin_slave_enabled;
+    /** LIN Slave Support enabled */
+    bool lin_slave_enabled;
 #endif
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	/** Start of frame dection enabled */
-	bool start_frame_detection_enabled;
+    /** Start of frame dection enabled */
+    bool start_frame_detection_enabled;
 #endif
 #ifdef FEATURE_USART_ISO7816
-	/** ISO7816 mode enable */
-	bool iso7816_mode_enabled;
+    /** ISO7816 mode enable */
+    bool iso7816_mode_enabled;
 #endif
 #  if USART_CALLBACK_MODE == true
-	/** Array to store callback function pointers in */
-	usart_callback_t callback[USART_CALLBACK_N];
-	/** Buffer pointer to where the next received character will be put */
-	volatile uint8_t *rx_buffer_ptr;
-
-	/** Buffer pointer to where the next character will be transmitted from
-	**/
-	volatile uint8_t *tx_buffer_ptr;
-	/** Remaining characters to receive */
-	volatile uint16_t remaining_rx_buffer_length;
-	/** Remaining characters to transmit */
-	volatile uint16_t remaining_tx_buffer_length;
-	/** Bit mask for callbacks registered */
-	uint8_t callback_reg_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t callback_enable_mask;
-	/** Holds the status of the ongoing or last read operation */
-	volatile enum status_code rx_status;
-	/** Holds the status of the ongoing or last write operation */
-	volatile enum status_code tx_status;
+    /** Array to store callback function pointers in */
+    usart_callback_t callback[USART_CALLBACK_N];
+    /** Buffer pointer to where the next received character will be put */
+    volatile uint8_t *rx_buffer_ptr;
+
+    /** Buffer pointer to where the next character will be transmitted from
+    **/
+    volatile uint8_t *tx_buffer_ptr;
+    /** Remaining characters to receive */
+    volatile uint16_t remaining_rx_buffer_length;
+    /** Remaining characters to transmit */
+    volatile uint16_t remaining_tx_buffer_length;
+    /** Bit mask for callbacks registered */
+    uint8_t callback_reg_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t callback_enable_mask;
+    /** Holds the status of the ongoing or last read operation */
+    volatile enum status_code rx_status;
+    /** Holds the status of the ongoing or last write operation */
+    volatile enum status_code tx_status;
 #  endif
 #endif
 };
@@ -954,22 +954,23 @@ struct usart_module {
  * \retval STATUS_BUSY If the module was already locked
  */
 static inline enum status_code usart_lock(
-		struct usart_module *const module)
+        struct usart_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return status;
+    return status;
 }
 
 /**
@@ -983,7 +984,7 @@ static inline enum status_code usart_lock(
  */
 static inline void usart_unlock(struct usart_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /** @} */
@@ -1005,18 +1006,18 @@ static inline void usart_unlock(struct usart_module *const module)
  *                stalling the bus
  */
 static inline bool usart_is_syncing(
-		const struct usart_module *const module)
+        const struct usart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
 #ifdef FEATURE_USART_SYNC_SCHEME_V2
-	return (usart_hw->SYNCBUSY.reg);
+    return (usart_hw->SYNCBUSY.reg);
 #else
-	return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
+    return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY);
 #endif
 }
 
@@ -1026,14 +1027,15 @@ static inline bool usart_is_syncing(
  * Waits until synchronization is complete
  */
 static inline void _usart_wait_for_sync(
-		const struct usart_module *const module)
+        const struct usart_module *const module)
 {
-	/* Sanity check */
-	Assert(module);
+    /* Sanity check */
+    Assert(module);
 
-	while (usart_is_syncing(module)) {
-		/* Wait until the synchronization is complete */
-	}
+    while (usart_is_syncing(module))
+    {
+        /* Wait until the synchronization is complete */
+    }
 }
 #endif
 
@@ -1056,75 +1058,75 @@ static inline void _usart_wait_for_sync(
  * \param[in,out] config  Pointer to configuration struct
  */
 static inline void usart_get_config_defaults(
-		struct usart_config *const config)
+        struct usart_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Set default config in the config struct */
-	config->data_order       = USART_DATAORDER_LSB;
-	config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
-	config->parity           = USART_PARITY_NONE;
-	config->stopbits         = USART_STOPBITS_1;
-	config->character_size   = USART_CHARACTER_SIZE_8BIT;
-	config->baudrate         = 9600;
-	config->receiver_enable  = true;
-	config->transmitter_enable = true;
-	config->clock_polarity_inverted = false;
-	config->use_external_clock = false;
-	config->ext_clock_freq   = 0;
-	config->mux_setting      = USART_RX_1_TX_2_XCK_3;
-	config->run_in_standby   = false;
-	config->generator_source = GCLK_GENERATOR_0;
-	config->pinmux_pad0      = PINMUX_DEFAULT;
-	config->pinmux_pad1      = PINMUX_DEFAULT;
-	config->pinmux_pad2      = PINMUX_DEFAULT;
-	config->pinmux_pad3      = PINMUX_DEFAULT;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Set default config in the config struct */
+    config->data_order       = USART_DATAORDER_LSB;
+    config->transfer_mode    = USART_TRANSFER_ASYNCHRONOUSLY;
+    config->parity           = USART_PARITY_NONE;
+    config->stopbits         = USART_STOPBITS_1;
+    config->character_size   = USART_CHARACTER_SIZE_8BIT;
+    config->baudrate         = 9600;
+    config->receiver_enable  = true;
+    config->transmitter_enable = true;
+    config->clock_polarity_inverted = false;
+    config->use_external_clock = false;
+    config->ext_clock_freq   = 0;
+    config->mux_setting      = USART_RX_1_TX_2_XCK_3;
+    config->run_in_standby   = false;
+    config->generator_source = GCLK_GENERATOR_0;
+    config->pinmux_pad0      = PINMUX_DEFAULT;
+    config->pinmux_pad1      = PINMUX_DEFAULT;
+    config->pinmux_pad2      = PINMUX_DEFAULT;
+    config->pinmux_pad3      = PINMUX_DEFAULT;
 #ifdef FEATURE_USART_OVER_SAMPLE
-	config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
-	config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
+    config->sample_adjustment     = USART_SAMPLE_ADJUSTMENT_7_8_9;
+    config->sample_rate           = USART_SAMPLE_RATE_16X_ARITHMETIC;
 #endif
 #ifdef FEATURE_USART_LIN_SLAVE
-	config->lin_slave_enable      = false;
+    config->lin_slave_enable      = false;
 #endif
 
 #ifdef FEATURE_USART_LIN_MASTER
-	config->lin_node = LIN_INVALID_MODE;
-	config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
-	config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
+    config->lin_node = LIN_INVALID_MODE;
+    config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0;
+    config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT;
 #endif
 
 #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION
-	config->immediate_buffer_overflow_notification  = false;
+    config->immediate_buffer_overflow_notification  = false;
 #endif
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	config->start_frame_detection_enable            = false;
+    config->start_frame_detection_enable            = false;
 #endif
 #ifdef FEATURE_USART_IRDA
-	config->encoding_format_enable                  = false;
-	config->receive_pulse_length                    = 19;
+    config->encoding_format_enable                  = false;
+    config->receive_pulse_length                    = 19;
 #endif
 #ifdef FEATURE_USART_ISO7816
-	config->iso7816_config.enabled                  = false;
-	config->iso7816_config.guard_time               = ISO7816_GUARD_TIME_2_BIT;
-	config->iso7816_config.protocol_t               = ISO7816_PROTOCOL_T_0;
-	config->iso7816_config.enable_inverse           = false;
-	config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
-	config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
-	config->iso7816_config.max_iterations           = 7;
+    config->iso7816_config.enabled                  = false;
+    config->iso7816_config.guard_time               = ISO7816_GUARD_TIME_2_BIT;
+    config->iso7816_config.protocol_t               = ISO7816_PROTOCOL_T_0;
+    config->iso7816_config.enable_inverse           = false;
+    config->iso7816_config.inhibit_nack             = ISO7816_INHIBIT_NACK_DISABLE;
+    config->iso7816_config.successive_recv_nack     = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE;
+    config->iso7816_config.max_iterations           = 7;
 #endif
 #ifdef FEATURE_USART_COLLISION_DECTION
-	config->collision_detection_enable              = false;
+    config->collision_detection_enable              = false;
 #endif
 #ifdef FEATURE_USART_RS485
-	config->rs485_guard_time = RS485_GUARD_TIME_0_BIT;
+    config->rs485_guard_time = RS485_GUARD_TIME_0_BIT;
 #endif
 }
 
 enum status_code usart_init(
-		struct usart_module *const module,
-		Sercom *const hw,
-		const struct usart_config *const config);
+        struct usart_module *const module,
+        Sercom *const hw,
+        const struct usart_config *const config);
 
 /**
  * \brief Enable the module
@@ -1134,25 +1136,25 @@ enum status_code usart_init(
  * \param[in]  module  Pointer to USART software instance struct
  */
 static inline void usart_enable(
-		const struct usart_module *const module)
+        const struct usart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
 #if USART_CALLBACK_MODE == true
-	/* Enable Global interrupt for module */
-	system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
+    /* Enable Global interrupt for module */
+    system_interrupt_enable(_sercom_get_interrupt_vector(module->hw));
 #endif
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Enable USART module */
-	usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
+    /* Enable USART module */
+    usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
 }
 
 /**
@@ -1163,25 +1165,25 @@ static inline void usart_enable(
  * \param[in]  module  Pointer to USART software instance struct
  */
 static inline void usart_disable(
-		const struct usart_module *const module)
+        const struct usart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
 #if USART_CALLBACK_MODE == true
-	/* Disable Global interrupt for module */
-	system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
+    /* Disable Global interrupt for module */
+    system_interrupt_disable(_sercom_get_interrupt_vector(module->hw));
 #endif
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Disable USART module */
-	usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
+    /* Disable USART module */
+    usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE;
 }
 
 /**
@@ -1192,22 +1194,22 @@ static inline void usart_disable(
  * \param[in]  module  Pointer to the USART software instance struct
  */
 static inline void usart_reset(
-		const struct usart_module *const module)
+        const struct usart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	usart_disable(module);
+    usart_disable(module);
 
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
 
-	/* Reset module */
-	usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
+    /* Reset module */
+    usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
 }
 
 /**
@@ -1215,22 +1217,22 @@ static inline void usart_reset(
  * @{
  */
 enum status_code usart_write_wait(
-		struct usart_module *const module,
-		const uint16_t tx_data);
+        struct usart_module *const module,
+        const uint16_t tx_data);
 
 enum status_code usart_read_wait(
-		struct usart_module *const module,
-		uint16_t *const rx_data);
+        struct usart_module *const module,
+        uint16_t *const rx_data);
 
 enum status_code usart_write_buffer_wait(
-		struct usart_module *const module,
-		const uint8_t *tx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        const uint8_t *tx_data,
+        uint16_t length);
 
 enum status_code usart_read_buffer_wait(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length);
 /** @} */
 
 /**
@@ -1247,33 +1249,34 @@ enum status_code usart_read_buffer_wait(
  * \param[in]  transceiver_type  Transceiver type
  */
 static inline void usart_enable_transceiver(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	switch (transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Enable RX */
-			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
-			module->receiver_enabled = true;
-			break;
-
-		case USART_TRANSCEIVER_TX:
-			/* Enable TX */
-			usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
-			module->transmitter_enabled = true;
-			break;
-	}
-	_usart_wait_for_sync(module);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
+
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
+
+    switch (transceiver_type)
+    {
+        case USART_TRANSCEIVER_RX:
+            /* Enable RX */
+            usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN;
+            module->receiver_enabled = true;
+            break;
+
+        case USART_TRANSCEIVER_TX:
+            /* Enable TX */
+            usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN;
+            module->transmitter_enabled = true;
+            break;
+    }
+    _usart_wait_for_sync(module);
 }
 
 /**
@@ -1285,32 +1288,33 @@ static inline void usart_enable_transceiver(
  * \param[in]  transceiver_type  Transceiver type
  */
 static inline void usart_disable_transceiver(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
-
-	/* Wait until synchronization is complete */
-	_usart_wait_for_sync(module);
-
-	switch (transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Disable RX */
-			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
-			module->receiver_enabled = false;
-			break;
-
-		case USART_TRANSCEIVER_TX:
-			/* Disable TX */
-			usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
-			module->transmitter_enabled = false;
-			break;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
+
+    /* Wait until synchronization is complete */
+    _usart_wait_for_sync(module);
+
+    switch (transceiver_type)
+    {
+        case USART_TRANSCEIVER_RX:
+            /* Disable RX */
+            usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN;
+            module->receiver_enabled = false;
+            break;
+
+        case USART_TRANSCEIVER_TX:
+            /* Disable TX */
+            usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN;
+            module->transmitter_enabled = false;
+            break;
+    }
 }
 
 /** @} */
@@ -1330,12 +1334,12 @@ static inline void usart_disable_transceiver(
  * \param[in]  cmd  Cammand type
  */
 static inline void lin_master_send_cmd(
-		struct usart_module *const module,
-		enum lin_master_cmd cmd)
+        struct usart_module *const module,
+        enum lin_master_cmd cmd)
 {
-	SercomUsart *const usart_hw = &(module->hw->USART);
-	_usart_wait_for_sync(module);
-	usart_hw->CTRLB.reg |= cmd;
+    SercomUsart *const usart_hw = &(module->hw->USART);
+    _usart_wait_for_sync(module);
+    usart_hw->CTRLB.reg |= cmd;
 }
 
 /**
@@ -1351,8 +1355,8 @@ static inline void lin_master_send_cmd(
  */
 static inline bool lin_master_transmission_status(struct usart_module *const module)
 {
-	SercomUsart *const usart_hw = &(module->hw->USART);
-	return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false);
+    SercomUsart *const usart_hw = &(module->hw->USART);
+    return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false);
 }
 
 /** @} */
@@ -1418,20 +1422,20 @@ static inline bool lin_master_transmission_status(struct usart_module *const mod
 * the table.
 *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Added new feature as below:
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Added new feature as below:
  *          \li ISO7816
- *	</tr>
- *	<tr>
- *		<td>Added new features as below:
+ *  </tr>
+ *  <tr>
+ *      <td>Added new features as below:
  *          \li LIN master
  *          \li RS485
- *	</tr>
- *	<tr>
- *		<td>Added new features as below:
+ *  </tr>
+ *  <tr>
+ *      <td>Added new features as below:
  *          \li Oversample
  *          \li Buffer overflow notification
  *          \li Irda
@@ -1440,18 +1444,18 @@ static inline bool lin_master_transmission_status(struct usart_module *const mod
  *          \li Hardware flow control
  *          \li Collision detection
  *          \li DMA support </td>
- *	</tr>
- *	<tr>
- *		<td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
+ *  </tr>
+ *  <tr>
+ *      <td>\li Added new \c transmitter_enable and \c receiver_enable Boolean
  *              values to \c struct usart_config
  *          \li Altered \c usart_write_* and usart_read_* functions to abort with
  *              an error code if the relevant transceiver is not enabled
  *          \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait()
  *              not aborting correctly when a timeout condition occurs</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
 */
 
@@ -1488,109 +1492,109 @@ static inline bool lin_master_transmission_status(struct usart_module *const mod
  *
  *
  * <table>
- *		<tr>
- *			<th>MUX/Pad</th>
- *			<th>PAD 0</th>
- *			<th>PAD 1</th>
- *			<th>PAD 2</th>
- *			<th>PAD 3</th>
- *		</tr>
- *		<tr>
- *			<td>RX_0_TX_0_XCK_1</td>
- *			<td>TX / RX</td>
- *			<td>XCK</td>
- *			<td>-</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_0_TX_2_XCK_3</td>
- *			<td>RX</td>
- *			<td>-</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_1_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>RX / XCK</td>
- *			<td>-</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_1_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>RX</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_2_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *			<td>RX</td>
- *			<td>-</td>
- *		</tr>
- *		<tr>
- *			<td>RX_2_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>-</td>
- *			<td>TX / RX</td>
- *			<td>XCK</td>
- *		</tr>
- *		<tr>
- *			<td>RX_3_TX_0_XCK_1</td>
- *			<td>TX</td>
- *			<td>XCK</td>
- *			<td>-</td>
- *			<td>RX</td>
- *		</tr>
- *		<tr>
- *			<td>RX_3_TX_2_XCK_3</td>
- *			<td>-</td>
- *			<td>-</td>
- *			<td>TX</td>
- *			<td>RX / XCK</td>
- *		</tr>
+ *      <tr>
+ *          <th>MUX/Pad</th>
+ *          <th>PAD 0</th>
+ *          <th>PAD 1</th>
+ *          <th>PAD 2</th>
+ *          <th>PAD 3</th>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_0_TX_0_XCK_1</td>
+ *          <td>TX / RX</td>
+ *          <td>XCK</td>
+ *          <td>-</td>
+ *          <td>-</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_0_TX_2_XCK_3</td>
+ *          <td>RX</td>
+ *          <td>-</td>
+ *          <td>TX</td>
+ *          <td>XCK</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_1_TX_0_XCK_1</td>
+ *          <td>TX</td>
+ *          <td>RX / XCK</td>
+ *          <td>-</td>
+ *          <td>-</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_1_TX_2_XCK_3</td>
+ *          <td>-</td>
+ *          <td>RX</td>
+ *          <td>TX</td>
+ *          <td>XCK</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_2_TX_0_XCK_1</td>
+ *          <td>TX</td>
+ *          <td>XCK</td>
+ *          <td>RX</td>
+ *          <td>-</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_2_TX_2_XCK_3</td>
+ *          <td>-</td>
+ *          <td>-</td>
+ *          <td>TX / RX</td>
+ *          <td>XCK</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_3_TX_0_XCK_1</td>
+ *          <td>TX</td>
+ *          <td>XCK</td>
+ *          <td>-</td>
+ *          <td>RX</td>
+ *      </tr>
+ *      <tr>
+ *          <td>RX_3_TX_2_XCK_3</td>
+ *          <td>-</td>
+ *          <td>-</td>
+ *          <td>TX</td>
+ *          <td>RX / XCK</td>
+ *      </tr>
  * </table>
  *
  * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42118F</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42118E</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42118D</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42118C</td>
- *		<td>10/2013</td>
- *		<td>Replaced the pad multiplexing documentation with a condensed table</td>
- *	</tr>
- *	<tr>
- *		<td>42118B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42118A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118F</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118E</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118D</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118C</td>
+ *      <td>10/2013</td>
+ *      <td>Replaced the pad multiplexing documentation with a condensed table</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42118A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 #endif /* USART_H_INCLUDED */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c
index cc042894c8e5..520d9a3f01be 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.c
@@ -56,38 +56,39 @@
  *
  */
 enum status_code _usart_write_buffer(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(tx_data);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(tx_data);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Check if the USART transmitter is busy */
-	if (module->remaining_tx_buffer_length > 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
+    /* Check if the USART transmitter is busy */
+    if (module->remaining_tx_buffer_length > 0)
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_BUSY;
+    }
 
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	module->tx_buffer_ptr              = tx_data;
-	module->tx_status                  = STATUS_BUSY;
+    module->tx_buffer_ptr              = tx_data;
+    module->tx_status                  = STATUS_BUSY;
 
-	/* Enable the Data Register Empty Interrupt */
-	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
+    /* Enable the Data Register Empty Interrupt */
+    usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -100,53 +101,56 @@ enum status_code _usart_write_buffer(
  *
  */
 enum status_code _usart_read_buffer(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
-	Assert(rx_data);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
+    Assert(rx_data);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Check if the USART receiver is busy */
-	if (module->remaining_rx_buffer_length > 0) {
-		system_interrupt_leave_critical_section();
-		return STATUS_BUSY;
-	}
+    /* Check if the USART receiver is busy */
+    if (module->remaining_rx_buffer_length > 0)
+    {
+        system_interrupt_leave_critical_section();
+        return STATUS_BUSY;
+    }
 
-	/* Set length for the buffer and the pointer, and let
-	 * the interrupt handler do the rest */
-	module->remaining_rx_buffer_length = length;
+    /* Set length for the buffer and the pointer, and let
+     * the interrupt handler do the rest */
+    module->remaining_rx_buffer_length = length;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	module->rx_buffer_ptr              = rx_data;
-	module->rx_status                  = STATUS_BUSY;
+    module->rx_buffer_ptr              = rx_data;
+    module->rx_status                  = STATUS_BUSY;
 
-	/* Enable the RX Complete Interrupt */
-	usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+    /* Enable the RX Complete Interrupt */
+    usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
 
 #ifdef FEATURE_USART_LIN_SLAVE
-	/* Enable the break character is received Interrupt */
-	if(module->lin_slave_enabled) {
-		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
-	}
+    /* Enable the break character is received Interrupt */
+    if(module->lin_slave_enabled)
+    {
+        usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK;
+    }
 #endif
 
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	/* Enable a start condition is detected Interrupt */
-	if(module->start_frame_detection_enabled) {
-		usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
-	}
+    /* Enable a start condition is detected Interrupt */
+    if(module->start_frame_detection_enabled)
+    {
+        usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS;
+    }
 #endif
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -164,19 +168,19 @@ enum status_code _usart_read_buffer(
  *
  */
 void usart_register_callback(
-		struct usart_module *const module,
-		usart_callback_t callback_func,
-		enum usart_callback callback_type)
+        struct usart_module *const module,
+        usart_callback_t callback_func,
+        enum usart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->callback_reg_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->callback_reg_mask |= (1 << callback_type);
 }
 
 /**
@@ -189,17 +193,17 @@ void usart_register_callback(
  *
  */
 void usart_unregister_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
+        struct usart_module *const module,
+        enum usart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->callback_reg_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->callback_reg_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -218,21 +222,22 @@ void usart_unregister_callback(
  * \retval STATUS_ERR_DENIED If the transmitter is not enabled
  */
 enum status_code usart_write_job(
-		struct usart_module *const module,
-		const uint16_t *tx_data)
+        struct usart_module *const module,
+        const uint16_t *tx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(tx_data);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(tx_data);
 
 
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
+    /* Check that the transmitter is enabled */
+    if (!(module->transmitter_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
 
-	/* Call internal write buffer function with length 1 */
-	return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
+    /* Call internal write buffer function with length 1 */
+    return _usart_write_buffer(module, (uint8_t *)tx_data, 1);
 }
 
 /**
@@ -250,15 +255,15 @@ enum status_code usart_write_job(
  * \retval  STATUS_BUSY  If operation was not completed
  */
 enum status_code usart_read_job(
-		struct usart_module *const module,
-		uint16_t *const rx_data)
+        struct usart_module *const module,
+        uint16_t *const rx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
 
-	/* Call internal read buffer function with length 1 */
-	return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
+    /* Call internal read buffer function with length 1 */
+    return _usart_read_buffer(module, (uint8_t *)rx_data, 1);
 }
 
 /**
@@ -271,8 +276,8 @@ enum status_code usart_read_job(
  * \param[in]  tx_data  Pointer do data buffer to transmit
  * \param[in]  length   Length of the data to transmit
  *
- * \note If using 9-bit data, the array that *tx_data point to should be defined 
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ * \note If using 9-bit data, the array that *tx_data point to should be defined
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it
  *       is an address pointer, the highest byte is not discarded. For example:
  *   \code
           #define TX_LEN 3
@@ -289,25 +294,27 @@ enum status_code usart_read_job(
  * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
  */
 enum status_code usart_write_buffer_job(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(tx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the transmitter is enabled */
-	if (!(module->transmitter_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Issue internal asynchronous write */
-	return _usart_write_buffer(module, tx_data, length);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(tx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check that the transmitter is enabled */
+    if (!(module->transmitter_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Issue internal asynchronous write */
+    return _usart_write_buffer(module, tx_data, length);
 }
 
 /**
@@ -321,7 +328,7 @@ enum status_code usart_write_buffer_job(
  * \param[in]  length   Data buffer length
  *
  * \note If using 9-bit data, the array that *rx_data point to should be defined
- *       as uint16_t array and should be casted to uint8_t* pointer. Because it 
+ *       as uint16_t array and should be casted to uint8_t* pointer. Because it
  *       is an address pointer, the highest byte is not discarded. For example:
  *   \code
            #define RX_LEN 3
@@ -338,25 +345,27 @@ enum status_code usart_write_buffer_job(
  * \retval STATUS_ERR_DENIED      If the transmitter is not enabled
  */
 enum status_code usart_read_buffer_job(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check that the receiver is enabled */
-	if (!(module->receiver_enabled)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Issue internal asynchronous read */
-	return _usart_read_buffer(module, rx_data, length);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check that the receiver is enabled */
+    if (!(module->receiver_enabled))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Issue internal asynchronous read */
+    return _usart_read_buffer(module, rx_data, length);
 }
 
 /**
@@ -369,37 +378,38 @@ enum status_code usart_read_buffer_job(
  * \param[in]  transceiver_type  Transfer type to cancel
  */
 void usart_abort_job(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Get a pointer to the hardware module instance */
-	SercomUsart *const usart_hw = &(module->hw->USART);
+    /* Get a pointer to the hardware module instance */
+    SercomUsart *const usart_hw = &(module->hw->USART);
 
-	switch(transceiver_type) {
-		case USART_TRANSCEIVER_RX:
-			/* Clear the interrupt flag in order to prevent the receive
-			 * complete callback to fire */
-			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
+    switch(transceiver_type)
+    {
+        case USART_TRANSCEIVER_RX:
+            /* Clear the interrupt flag in order to prevent the receive
+             * complete callback to fire */
+            usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC;
 
-			/* Clear the software reception buffer */
-			module->remaining_rx_buffer_length = 0;
+            /* Clear the software reception buffer */
+            module->remaining_rx_buffer_length = 0;
 
-			break;
+            break;
 
-		case USART_TRANSCEIVER_TX:
-			/* Clear the interrupt flag in order to prevent the receive
-			 * complete callback to fire */
-			usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
+        case USART_TRANSCEIVER_TX:
+            /* Clear the interrupt flag in order to prevent the receive
+             * complete callback to fire */
+            usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC;
 
-			/* Clear the software reception buffer */
-			module->remaining_tx_buffer_length = 0;
+            /* Clear the software reception buffer */
+            module->remaining_tx_buffer_length = 0;
 
-			break;
-	}
+            break;
+    }
 }
 
 /**
@@ -424,30 +434,31 @@ void usart_abort_job(
  * \retval STATUS_ERR_INVALID_ARG  An invalid transceiver enum given
  */
 enum status_code usart_get_job_status(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type)
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Variable for status code */
-	enum status_code status_code;
+    /* Variable for status code */
+    enum status_code status_code;
 
-	switch(transceiver_type) {
-	case USART_TRANSCEIVER_RX:
-			status_code = module->rx_status;
-			break;
+    switch(transceiver_type)
+    {
+    case USART_TRANSCEIVER_RX:
+            status_code = module->rx_status;
+            break;
 
-	case USART_TRANSCEIVER_TX:
-			status_code = module->tx_status;
-			break;
+    case USART_TRANSCEIVER_TX:
+            status_code = module->tx_status;
+            break;
 
-	default:
-			status_code = STATUS_ERR_INVALID_ARG;
-			break;
-	}
+    default:
+            status_code = STATUS_ERR_INVALID_ARG;
+            break;
+    }
 
-	return status_code;
+    return status_code;
 }
 
 /**
@@ -459,208 +470,234 @@ enum status_code usart_get_job_status(
  *                       handler.
  */
 void _usart_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Temporary variables */
-	uint16_t interrupt_status;
-	uint16_t callback_status;
-	uint8_t error_code;
-
-
-	/* Get device instance from the look-up table */
-	struct usart_module *module
-		= (struct usart_module *)_sercom_instances[instance];
-
-	/* Pointer to the hardware module instance */
-	SercomUsart *const usart_hw
-		= &(module->hw->USART);
-
-	/* Wait for the synchronization to complete */
-	_usart_wait_for_sync(module);
-
-	/* Read and mask interrupt flag register */
-	interrupt_status = usart_hw->INTFLAG.reg;
-	interrupt_status &= usart_hw->INTENSET.reg;
-	callback_status = module->callback_reg_mask &
-			module->callback_enable_mask;
-
-	/* Check if a DATA READY interrupt has occurred,
-	 * and if there is more to transfer */
-	if (interrupt_status & SERCOM_USART_INTFLAG_DRE) {
-		if (module->remaining_tx_buffer_length) {
-			/* Write value will be at least 8-bits long */
-			uint16_t data_to_send = *(module->tx_buffer_ptr);
-			/* Increment 8-bit pointer */
-			(module->tx_buffer_ptr)++;
-
-			if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-				data_to_send |= (*(module->tx_buffer_ptr) << 8);
-				/* Increment 8-bit pointer */
-				(module->tx_buffer_ptr)++;
-			}
-			/* Write the data to send */
-			usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
-
-			if (--(module->remaining_tx_buffer_length) == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-				/* Enable Transmission Complete interrupt */
-				usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
-
-			}
-		} else {
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
-		}
-	}
-
-	/* Check if the Transmission Complete interrupt has occurred and
-	 * that the transmit buffer is empty */
-	if (interrupt_status & SERCOM_USART_INTFLAG_TXC) {
-
-		/* Disable TX Complete Interrupt, and set STATUS_OK */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
-		module->tx_status = STATUS_OK;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) {
-			(*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
-		}
-	}
-
-	/* Check if the Receive Complete interrupt has occurred, and that
-	 * there's more data to receive */
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
-
-		if (module->remaining_rx_buffer_length) {
-			/* Read out the status code and mask away all but the 4 LSBs*/
-			error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+    /* Temporary variables */
+    uint16_t interrupt_status;
+    uint16_t callback_status;
+    uint8_t error_code;
+
+
+    /* Get device instance from the look-up table */
+    struct usart_module *module
+        = (struct usart_module *)_sercom_instances[instance];
+
+    /* Pointer to the hardware module instance */
+    SercomUsart *const usart_hw
+        = &(module->hw->USART);
+
+    /* Wait for the synchronization to complete */
+    _usart_wait_for_sync(module);
+
+    /* Read and mask interrupt flag register */
+    interrupt_status = usart_hw->INTFLAG.reg;
+    interrupt_status &= usart_hw->INTENSET.reg;
+    callback_status = module->callback_reg_mask &
+            module->callback_enable_mask;
+
+    /* Check if a DATA READY interrupt has occurred,
+     * and if there is more to transfer */
+    if (interrupt_status & SERCOM_USART_INTFLAG_DRE)
+    {
+        if (module->remaining_tx_buffer_length)
+        {
+            /* Write value will be at least 8-bits long */
+            uint16_t data_to_send = *(module->tx_buffer_ptr);
+            /* Increment 8-bit pointer */
+            (module->tx_buffer_ptr)++;
+
+            if (module->character_size == USART_CHARACTER_SIZE_9BIT)
+            {
+                data_to_send |= (*(module->tx_buffer_ptr) << 8);
+                /* Increment 8-bit pointer */
+                (module->tx_buffer_ptr)++;
+            }
+            /* Write the data to send */
+            usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK);
+
+            if (--(module->remaining_tx_buffer_length) == 0)
+            {
+                /* Disable the Data Register Empty Interrupt */
+                usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+                /* Enable Transmission Complete interrupt */
+                usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC;
+
+            }
+        } else {
+            usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE;
+        }
+    }
+
+    /* Check if the Transmission Complete interrupt has occurred and
+     * that the transmit buffer is empty */
+    if (interrupt_status & SERCOM_USART_INTFLAG_TXC)
+    {
+
+        /* Disable TX Complete Interrupt, and set STATUS_OK */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC;
+        module->tx_status = STATUS_OK;
+
+        /* Run callback if registered and enabled */
+        if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED))
+        {
+            (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module);
+        }
+    }
+
+    /* Check if the Receive Complete interrupt has occurred, and that
+     * there's more data to receive */
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXC)
+    {
+
+        if (module->remaining_rx_buffer_length)
+        {
+            /* Read out the status code and mask away all but the 4 LSBs*/
+            error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
 #if !SAMD20
-			/* CTS status should not be considered as an error */
-			if(error_code & SERCOM_USART_STATUS_CTS) {
-				error_code &= ~SERCOM_USART_STATUS_CTS;
-			}
+            /* CTS status should not be considered as an error */
+            if(error_code & SERCOM_USART_STATUS_CTS)
+            {
+                error_code &= ~SERCOM_USART_STATUS_CTS;
+            }
 #endif
 #ifdef FEATURE_USART_LIN_MASTER
-			/* TXE status should not be considered as an error */
-			if(error_code & SERCOM_USART_STATUS_TXE) {
-				error_code &= ~SERCOM_USART_STATUS_TXE;
-			}
+            /* TXE status should not be considered as an error */
+            if(error_code & SERCOM_USART_STATUS_TXE)
+            {
+                error_code &= ~SERCOM_USART_STATUS_TXE;
+            }
 #endif
-			/* Check if an error has occurred during the receiving */
-			if (error_code) {
-				/* Check which error occurred */
-				if (error_code & SERCOM_USART_STATUS_FERR) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_BAD_FORMAT;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
-				} else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_OVERFLOW;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
-				} else if (error_code & SERCOM_USART_STATUS_PERR) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_BAD_DATA;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
-				}
+            /* Check if an error has occurred during the receiving */
+            if (error_code)
+            {
+                /* Check which error occurred */
+                if (error_code & SERCOM_USART_STATUS_FERR)
+                {
+                    /* Store the error code and clear flag by writing 1 to it */
+                    module->rx_status = STATUS_ERR_BAD_FORMAT;
+                    usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+                } else if (error_code & SERCOM_USART_STATUS_BUFOVF)
+                {
+                    /* Store the error code and clear flag by writing 1 to it */
+                    module->rx_status = STATUS_ERR_OVERFLOW;
+                    usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+                } else if (error_code & SERCOM_USART_STATUS_PERR)
+                {
+                    /* Store the error code and clear flag by writing 1 to it */
+                    module->rx_status = STATUS_ERR_BAD_DATA;
+                    usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+                }
 #ifdef FEATURE_USART_LIN_SLAVE
-				else if (error_code & SERCOM_USART_STATUS_ISF) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_PROTOCOL;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
-				}
+                else if (error_code & SERCOM_USART_STATUS_ISF)
+                {
+                    /* Store the error code and clear flag by writing 1 to it */
+                    module->rx_status = STATUS_ERR_PROTOCOL;
+                    usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+                }
 #endif
 #ifdef FEATURE_USART_COLLISION_DECTION
-				else if (error_code & SERCOM_USART_STATUS_COLL) {
-					/* Store the error code and clear flag by writing 1 to it */
-					module->rx_status = STATUS_ERR_PACKET_COLLISION;
-					usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
-				}
+                else if (error_code & SERCOM_USART_STATUS_COLL)
+                {
+                    /* Store the error code and clear flag by writing 1 to it */
+                    module->rx_status = STATUS_ERR_PACKET_COLLISION;
+                    usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+                }
 #endif
 
-				/* Run callback if registered and enabled */
-				if (callback_status
-						& (1 << USART_CALLBACK_ERROR)) {
-					(*(module->callback[USART_CALLBACK_ERROR]))(module);
-				}
-
-			} else {
-
-				/* Read current packet from DATA register,
-				 * increment buffer pointer and decrement buffer length */
-				uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
-
-				/* Read value will be at least 8-bits long */
-				*(module->rx_buffer_ptr) = received_data;
-				/* Increment 8-bit pointer */
-				module->rx_buffer_ptr += 1;
-
-				if (module->character_size == USART_CHARACTER_SIZE_9BIT) {
-					/* 9-bit data, write next received byte to the buffer */
-					*(module->rx_buffer_ptr) = (received_data >> 8);
-					/* Increment 8-bit pointer */
-					module->rx_buffer_ptr += 1;
-				}
-
-				/* Check if the last character have been received */
-				if(--(module->remaining_rx_buffer_length) == 0) {
-					/* Disable RX Complete Interrupt,
-					 * and set STATUS_OK */
-					usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-					module->rx_status = STATUS_OK;
-
-					/* Run callback if registered and enabled */
-					if (callback_status
-							& (1 << USART_CALLBACK_BUFFER_RECEIVED)) {
-						(*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
-					}
-				}
-			}
-		} else {
-			/* This should not happen. Disable Receive Complete interrupt. */
-			usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
-		}
-	}
+                /* Run callback if registered and enabled */
+                if (callback_status
+                        & (1 << USART_CALLBACK_ERROR))
+                        {
+                    (*(module->callback[USART_CALLBACK_ERROR]))(module);
+                }
+
+            } else {
+
+                /* Read current packet from DATA register,
+                 * increment buffer pointer and decrement buffer length */
+                uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK);
+
+                /* Read value will be at least 8-bits long */
+                *(module->rx_buffer_ptr) = received_data;
+                /* Increment 8-bit pointer */
+                module->rx_buffer_ptr += 1;
+
+                if (module->character_size == USART_CHARACTER_SIZE_9BIT)
+                {
+                    /* 9-bit data, write next received byte to the buffer */
+                    *(module->rx_buffer_ptr) = (received_data >> 8);
+                    /* Increment 8-bit pointer */
+                    module->rx_buffer_ptr += 1;
+                }
+
+                /* Check if the last character have been received */
+                if(--(module->remaining_rx_buffer_length) == 0)
+                {
+                    /* Disable RX Complete Interrupt,
+                     * and set STATUS_OK */
+                    usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+                    module->rx_status = STATUS_OK;
+
+                    /* Run callback if registered and enabled */
+                    if (callback_status
+                            & (1 << USART_CALLBACK_BUFFER_RECEIVED))
+                            {
+                        (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module);
+                    }
+                }
+            }
+        } else {
+            /* This should not happen. Disable Receive Complete interrupt. */
+            usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+        }
+    }
 
 #ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
-	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) {
-			(*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
-		}
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+
+        /* Run callback if registered and enabled */
+        if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE))
+        {
+            (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module);
+        }
+    }
 #endif
 
 #ifdef FEATURE_USART_LIN_SLAVE
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) {
-			(*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
-		}
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+
+        /* Run callback if registered and enabled */
+        if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED))
+        {
+            (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module);
+        }
+    }
 #endif
 
 #ifdef FEATURE_USART_START_FRAME_DECTION
-	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
-		/* Disable interrupts */
-		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
-		/* Clear interrupt flag */
-		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
-
-		/* Run callback if registered and enabled */
-		if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) {
-			(*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
-		}
-	}
+    if (interrupt_status & SERCOM_USART_INTFLAG_RXS)
+    {
+        /* Disable interrupts */
+        usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+        /* Clear interrupt flag */
+        usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+
+        /* Run callback if registered and enabled */
+        if (callback_status & (1 << USART_CALLBACK_START_RECEIVED))
+        {
+            (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module);
+        }
+    }
 #endif
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h
index 26595d0a0962..6183d63c24f1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/sercom/usart/usart_interrupt.h
@@ -54,17 +54,17 @@ extern "C" {
 
 #if !defined(__DOXYGEN__)
 enum status_code _usart_write_buffer(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        uint8_t *tx_data,
+        uint16_t length);
 
 enum status_code _usart_read_buffer(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length);
 
 void _usart_interrupt_handler(
-		uint8_t instance);
+        uint8_t instance);
 #endif
 
 /**
@@ -78,13 +78,13 @@ void _usart_interrupt_handler(
  * @{
  */
 void usart_register_callback(
-		struct usart_module *const module,
-		usart_callback_t callback_func,
-		enum usart_callback callback_type);
+        struct usart_module *const module,
+        usart_callback_t callback_func,
+        enum usart_callback callback_type);
 
 void usart_unregister_callback(
-		struct usart_module *module,
-		enum usart_callback callback_type);
+        struct usart_module *module,
+        enum usart_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -97,14 +97,14 @@ void usart_unregister_callback(
  * \param[in]  callback_type  Callback type given by an enum
  */
 static inline void usart_enable_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
+        struct usart_module *const module,
+        enum usart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->callback_enable_mask |= (1 << callback_type);
+    /* Enable callback */
+    module->callback_enable_mask |= (1 << callback_type);
 
 }
 
@@ -118,14 +118,14 @@ static inline void usart_enable_callback(
  * \param[in]  callback_type  Callback type given by an enum
  */
 static inline void usart_disable_callback(
-		struct usart_module *const module,
-		enum usart_callback callback_type)
+        struct usart_module *const module,
+        enum usart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Disable callback */
-	module->callback_enable_mask &= ~(1 << callback_type);
+    /* Disable callback */
+    module->callback_enable_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -137,30 +137,30 @@ static inline void usart_disable_callback(
  * @{
  */
 enum status_code usart_write_job(
-		struct usart_module *const module,
-		const uint16_t *tx_data);
+        struct usart_module *const module,
+        const uint16_t *tx_data);
 
 enum status_code usart_read_job(
-		struct usart_module *const module,
-		uint16_t *const rx_data);
+        struct usart_module *const module,
+        uint16_t *const rx_data);
 
 enum status_code usart_write_buffer_job(
-		struct usart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        uint8_t *tx_data,
+        uint16_t length);
 
 enum status_code usart_read_buffer_job(
-		struct usart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct usart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length);
 
 void usart_abort_job(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type);
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type);
 
 enum status_code usart_get_job_status(
-		struct usart_module *const module,
-		enum usart_transceiver_type transceiver_type);
+        struct usart_module *const module,
+        enum usart_transceiver_type transceiver_type);
 /**
  * @}
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c
index 01b0a4bb2ba6..44f525f21d89 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.c
@@ -117,14 +117,14 @@
  */
 void slcd_get_config_defaults(struct slcd_config *config)
 {
-	Assert(config);
-
-	config->run_in_standby = false;
-	config->waveform_mode = SLCD_LOW_POWER_WAVEFORM_MODE;
-	config->low_resistance_duration = 0;
-	config->enable_low_resistance = false;
-	config->bias_buffer_duration = 0;
-	config->enable_bias_buffer = false;
+    Assert(config);
+
+    config->run_in_standby = false;
+    config->waveform_mode = SLCD_LOW_POWER_WAVEFORM_MODE;
+    config->low_resistance_duration = 0;
+    config->enable_low_resistance = false;
+    config->bias_buffer_duration = 0;
+    config->enable_bias_buffer = false;
 }
 
 /**
@@ -140,34 +140,35 @@ void slcd_get_config_defaults(struct slcd_config *config)
  */
 enum status_code slcd_init(struct slcd_config *const config)
 {
-	if (!config) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SLCD);
-
-	/* Select SLCD clock */
-	OSC32KCTRL->SLCDCTRL.reg = CONF_SLCD_CLOCK_SOURCE & OSC32KCTRL_SLCDCTRL_MASK;
-
-	slcd_disable();
-	slcd_reset();
-
-	SLCD->CTRLA.reg = SLCD_CTRLA_DUTY(CONF_SLCD_DUTY) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
-					 | SLCD_CTRLA_PRESC(CONF_SLCD_PVAL) | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV)
-					 | (CONF_SLCD_VLCD_SEL << SLCD_CTRLA_XVLCD_Pos)
-					 | (config->run_in_standby << SLCD_CTRLA_RUNSTDBY_Pos)
-					 | SLCD_CTRLA_RRF(CONF_SLCD_REF_REFRESH_FREQ)
-					 | SLCD_CTRLA_PRF(CONF_SLCD_POWER_REFRESH_FREQ)
-					 | (config->waveform_mode << SLCD_CTRLA_WMOD_Pos);
-	SLCD->CTRLB.reg = SLCD_CTRLB_BBD(config->bias_buffer_duration)
-  					| (config->enable_bias_buffer << SLCD_CTRLB_BBEN_Pos)
-  					| SLCD_CTRLB_LRD(config->low_resistance_duration)
-  					| (config->enable_low_resistance << SLCD_CTRLB_LREN_Pos);
+    if (!config)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_SLCD);
+
+    /* Select SLCD clock */
+    OSC32KCTRL->SLCDCTRL.reg = CONF_SLCD_CLOCK_SOURCE & OSC32KCTRL_SLCDCTRL_MASK;
+
+    slcd_disable();
+    slcd_reset();
+
+    SLCD->CTRLA.reg = SLCD_CTRLA_DUTY(CONF_SLCD_DUTY) | SLCD_CTRLA_BIAS(CONF_SLCD_BIAS)
+                     | SLCD_CTRLA_PRESC(CONF_SLCD_PVAL) | SLCD_CTRLA_CKDIV(CONF_SLCD_CKDIV)
+                     | (CONF_SLCD_VLCD_SEL << SLCD_CTRLA_XVLCD_Pos)
+                     | (config->run_in_standby << SLCD_CTRLA_RUNSTDBY_Pos)
+                     | SLCD_CTRLA_RRF(CONF_SLCD_REF_REFRESH_FREQ)
+                     | SLCD_CTRLA_PRF(CONF_SLCD_POWER_REFRESH_FREQ)
+                     | (config->waveform_mode << SLCD_CTRLA_WMOD_Pos);
+    SLCD->CTRLB.reg = SLCD_CTRLB_BBD(config->bias_buffer_duration)
+                    | (config->enable_bias_buffer << SLCD_CTRLB_BBEN_Pos)
+                    | SLCD_CTRLB_LRD(config->low_resistance_duration)
+                    | (config->enable_low_resistance << SLCD_CTRLB_LREN_Pos);
 
 
     SLCD->CTRLC.reg |= SLCD_CTRLC_LPPM(CONF_SLCD_POWER_MODE) | SLCD_CTRLC_CTST(0x0F);
 
-	SLCD->LPENL.reg = CONF_SLCD_PIN_L_MASK & SLCD_LPENL_MASK;
-	SLCD->LPENH.reg = CONF_SLCD_PIN_H_MASK & SLCD_LPENH_MASK;
+    SLCD->LPENL.reg = CONF_SLCD_PIN_L_MASK & SLCD_LPENL_MASK;
+    SLCD->LPENH.reg = CONF_SLCD_PIN_H_MASK & SLCD_LPENH_MASK;
 
    return STATUS_OK;
 }
@@ -181,14 +182,16 @@ enum status_code slcd_init(struct slcd_config *const config)
 
 void slcd_enable(void)
 {
-	SLCD->CTRLA.reg |= SLCD_CTRLA_ENABLE;
+    SLCD->CTRLA.reg |= SLCD_CTRLA_ENABLE;
 
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 
-	while (!slcd_get_vlcd_ready_status()) {
-   	}
+    while (!slcd_get_vlcd_ready_status())
+    {
+    }
 }
 
 /**
@@ -198,12 +201,13 @@ void slcd_enable(void)
  */
 void slcd_disable(void)
 {
-	SLCD->INTENCLR.reg = SLCD_INTENCLR_MASK;
-	SLCD->INTFLAG.reg = SLCD_INTFLAG_MASK;
-	SLCD->CTRLA.reg &= ~(SLCD_CTRLA_ENABLE);
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->INTENCLR.reg = SLCD_INTENCLR_MASK;
+    SLCD->INTFLAG.reg = SLCD_INTFLAG_MASK;
+    SLCD->CTRLA.reg &= ~(SLCD_CTRLA_ENABLE);
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -218,7 +222,7 @@ void slcd_disable(void)
 
 bool slcd_is_enabled(void)
 {
-	return ((SLCD->CTRLA.reg & SLCD_CTRLA_ENABLE) == SLCD_CTRLA_ENABLE);
+    return ((SLCD->CTRLA.reg & SLCD_CTRLA_ENABLE) == SLCD_CTRLA_ENABLE);
 }
 
 /**
@@ -228,11 +232,12 @@ bool slcd_is_enabled(void)
  */
 void slcd_reset(void)
 {
-	slcd_disable();
-	SLCD->CTRLA.reg |= SLCD_CTRLA_SWRST;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    slcd_disable();
+    SLCD->CTRLA.reg |= SLCD_CTRLA_SWRST;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -254,16 +259,17 @@ void slcd_reset(void)
 enum status_code slcd_set_contrast(uint8_t contrast)
 {
 
-	if (SLCD->CTRLA.bit.XVLCD) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	uint16_t temp = SLCD->CTRLC.reg;
+    if (SLCD->CTRLA.bit.XVLCD)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    uint16_t temp = SLCD->CTRLC.reg;
 
-	temp &= ~ SLCD_CTRLC_CTST(0xf);
-	temp |= SLCD_CTRLC_CTST(contrast);
+    temp &= ~ SLCD_CTRLC_CTST(0xf);
+    temp |= SLCD_CTRLC_CTST(contrast);
 
-	SLCD->CTRLC.reg = temp;
-	return STATUS_OK;
+    SLCD->CTRLC.reg = temp;
+    return STATUS_OK;
 }
 
 /**
@@ -276,10 +282,10 @@ enum status_code slcd_set_contrast(uint8_t contrast)
  */
 void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config)
 {
-	Assert(blink_config);
+    Assert(blink_config);
 
-	blink_config->fc = SLCD_FRAME_COUNTER_0;
-	blink_config->blink_all_seg = true;
+    blink_config->fc = SLCD_FRAME_COUNTER_0;
+    blink_config->blink_all_seg = true;
 }
 
 /**
@@ -298,13 +304,14 @@ void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config)
 
 enum status_code  slcd_blink_set_config(struct slcd_blink_config *const blink_config)
 {
-	if (!blink_config) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	SLCD->BCFG.bit.MODE = (!(blink_config->blink_all_seg) << SLCD_BCFG_MODE_Pos);
-	SLCD->BCFG.bit.FCS	= SLCD_BCFG_FCS(blink_config->fc);
-	return STATUS_OK;
+    if (!blink_config)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    SLCD->BCFG.bit.MODE = (!(blink_config->blink_all_seg) << SLCD_BCFG_MODE_Pos);
+    SLCD->BCFG.bit.FCS  = SLCD_BCFG_FCS(blink_config->fc);
+    return STATUS_OK;
 }
 
 /**
@@ -314,19 +321,21 @@ enum status_code  slcd_blink_set_config(struct slcd_blink_config *const blink_co
  * \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
  */
 void slcd_set_blink_pixel(
-		uint8_t pix_com,
-		uint8_t pix_seg)
+        uint8_t pix_com,
+        uint8_t pix_seg)
 {
-	/* Validate parameters. */
-	Assert(pix_seg<=1);
-	
-	if (pix_seg == 0) {
-		SLCD->BCFG.reg |= SLCD_BCFG_BSS0(1 << pix_com);
-	}
-
-	if (pix_seg == 1) {
-		SLCD->BCFG.reg |= SLCD_BCFG_BSS1(1 << pix_com);
-	}
+    /* Validate parameters. */
+    Assert(pix_seg<=1);
+
+    if (pix_seg == 0)
+    {
+        SLCD->BCFG.reg |= SLCD_BCFG_BSS0(1 << pix_com);
+    }
+
+    if (pix_seg == 1)
+    {
+        SLCD->BCFG.reg |= SLCD_BCFG_BSS1(1 << pix_com);
+    }
 }
 
 /**
@@ -336,19 +345,21 @@ void slcd_set_blink_pixel(
  * \param[in] pix_seg Pixel/segment SEG coordinate (range 0 to 1 inclusive)
  */
 void slcd_clear_blink_pixel(
-		uint8_t pix_com,
-		uint8_t pix_seg)
+        uint8_t pix_com,
+        uint8_t pix_seg)
 {
-	/* Validate parameters. */
-	Assert(pix_seg<=1);
-	
-	if (pix_seg == 0) {
-		SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS0(1 << pix_com);
-	}
-
-	if (pix_seg == 1) {
-		SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS1(1 << pix_com);
-	}
+    /* Validate parameters. */
+    Assert(pix_seg<=1);
+
+    if (pix_seg == 0)
+    {
+        SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS0(1 << pix_com);
+    }
+
+    if (pix_seg == 1)
+    {
+        SLCD->BCFG.reg &= ~ SLCD_BCFG_BSS1(1 << pix_com);
+    }
 }
 
 /**
@@ -356,8 +367,8 @@ void slcd_clear_blink_pixel(
  */
 void slcd_clear_blink_all_pixel(void)
 {
-	SLCD->BCFG.bit.BSS0 = 0;
-	SLCD->BCFG.bit.BSS1 = 0;
+    SLCD->BCFG.bit.BSS0 = 0;
+    SLCD->BCFG.bit.BSS1 = 0;
 }
 
 
@@ -366,22 +377,22 @@ void slcd_clear_blink_all_pixel(void)
  */
 void slcd_set_display_memory(void)
 {
-	SLCD->SDATAH0.reg = SLCD_SDATAH0_MASK;
-	SLCD->SDATAL0.reg = SLCD_SDATAL0_MASK;
-	SLCD->SDATAH1.reg = SLCD_SDATAH1_MASK;
-	SLCD->SDATAL1.reg = SLCD_SDATAL1_MASK;
-	SLCD->SDATAH2.reg = SLCD_SDATAH2_MASK;
-	SLCD->SDATAL2.reg = SLCD_SDATAL2_MASK;
-	SLCD->SDATAH3.reg = SLCD_SDATAH3_MASK;
-	SLCD->SDATAL3.reg = SLCD_SDATAL3_MASK;
-	SLCD->SDATAH4.reg = SLCD_SDATAH4_MASK;
-	SLCD->SDATAL4.reg = SLCD_SDATAL4_MASK;
-	SLCD->SDATAH5.reg = SLCD_SDATAH5_MASK;
-	SLCD->SDATAL5.reg = SLCD_SDATAL5_MASK;
-	SLCD->SDATAH6.reg = SLCD_SDATAH6_MASK;
-	SLCD->SDATAL6.reg = SLCD_SDATAL6_MASK;
-	SLCD->SDATAH7.reg = SLCD_SDATAH7_MASK;
-	SLCD->SDATAL7.reg = SLCD_SDATAL7_MASK;
+    SLCD->SDATAH0.reg = SLCD_SDATAH0_MASK;
+    SLCD->SDATAL0.reg = SLCD_SDATAL0_MASK;
+    SLCD->SDATAH1.reg = SLCD_SDATAH1_MASK;
+    SLCD->SDATAL1.reg = SLCD_SDATAL1_MASK;
+    SLCD->SDATAH2.reg = SLCD_SDATAH2_MASK;
+    SLCD->SDATAL2.reg = SLCD_SDATAL2_MASK;
+    SLCD->SDATAH3.reg = SLCD_SDATAH3_MASK;
+    SLCD->SDATAL3.reg = SLCD_SDATAL3_MASK;
+    SLCD->SDATAH4.reg = SLCD_SDATAH4_MASK;
+    SLCD->SDATAL4.reg = SLCD_SDATAL4_MASK;
+    SLCD->SDATAH5.reg = SLCD_SDATAH5_MASK;
+    SLCD->SDATAL5.reg = SLCD_SDATAL5_MASK;
+    SLCD->SDATAH6.reg = SLCD_SDATAH6_MASK;
+    SLCD->SDATAL6.reg = SLCD_SDATAL6_MASK;
+    SLCD->SDATAH7.reg = SLCD_SDATAH7_MASK;
+    SLCD->SDATAL7.reg = SLCD_SDATAL7_MASK;
 }
 
 
@@ -392,72 +403,83 @@ void slcd_set_display_memory(void)
  * \param[in] pix_seg Pixel/segment SEG coordinate within [0-43]
  */
  void slcd_set_pixel(
-		uint8_t pix_com,
-		uint8_t pix_seg)
+        uint8_t pix_com,
+        uint8_t pix_seg)
 {
-	if ((pix_com < SLCD_MAX_COM) &&
-			(pix_seg < SLCD_MAX_SEG)) {
-		switch(pix_com){
-			case 0:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH0.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL0.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 1:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH1.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL1.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 2:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH2.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL2.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 3:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH3.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL3.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 4:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH4.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL4.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 5:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH5.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL5.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 6:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH6.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL6.reg |= 1 <<pix_seg;
-				}
-				break;
-			case 7:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH7.reg |= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL7.reg |= 1 <<pix_seg;
-				}
-				break;
-		}
-		while (slcd_get_char_writing_status()) {
-		}
-	}
+    if ((pix_com < SLCD_MAX_COM) &&
+            (pix_seg < SLCD_MAX_SEG))
+            {
+        switch(pix_com)
+        {
+            case 0:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH0.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL0.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 1:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH1.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL1.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 2:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH2.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL2.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 3:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH3.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL3.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 4:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH4.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL4.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 5:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH5.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL5.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 6:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH6.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL6.reg |= 1 <<pix_seg;
+                }
+                break;
+            case 7:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH7.reg |= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL7.reg |= 1 <<pix_seg;
+                }
+                break;
+        }
+        while (slcd_get_char_writing_status())
+        {
+        }
+    }
 }
 
 /**
@@ -468,69 +490,80 @@ void slcd_set_display_memory(void)
  */
  void slcd_clear_pixel(uint8_t pix_com, uint8_t pix_seg)
 {
-	if ((pix_com < SLCD_MAX_COM) &&
-			(pix_seg < SLCD_MAX_SEG)) {
-		switch(pix_com){
-			case 0:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH0.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL0.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 1:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH1.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL1.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 2:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH2.reg &= (1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL2.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 3:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH3.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL3.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 4:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH4.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL4.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 5:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH5.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL5.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 6:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH6.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL6.reg &= ~(1 <<pix_seg);
-				}
-				break;
-			case 7:
-				if (pix_seg >= 32) {
-					SLCD->SDATAH7.reg &= ~(1 <<(pix_seg-32));
-				} else {
-					SLCD->SDATAL7.reg &= ~(1 <<pix_seg);
-				}
-				break;
-		}
-		while (slcd_get_char_writing_status()) {
-		}
-	}
+    if ((pix_com < SLCD_MAX_COM) &&
+            (pix_seg < SLCD_MAX_SEG))
+            {
+        switch(pix_com)
+        {
+            case 0:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH0.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL0.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 1:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH1.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL1.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 2:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH2.reg &= (1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL2.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 3:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH3.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL3.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 4:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH4.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL4.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 5:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH5.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL5.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 6:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH6.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL6.reg &= ~(1 <<pix_seg);
+                }
+                break;
+            case 7:
+                if (pix_seg >= 32)
+                {
+                    SLCD->SDATAH7.reg &= ~(1 <<(pix_seg-32));
+                } else {
+                    SLCD->SDATAL7.reg &= ~(1 <<pix_seg);
+                }
+                break;
+        }
+        while (slcd_get_char_writing_status())
+        {
+        }
+    }
 }
 
 /**
@@ -542,12 +575,13 @@ void slcd_set_display_memory(void)
  */
 void slcd_set_seg_data(uint8_t seg_data,uint8_t byte_offset,uint8_t seg_mask)
 {
-	SLCD->ISDATA.reg = SLCD_ISDATA_SDATA(seg_data)
-					 | SLCD_ISDATA_OFF(byte_offset)
-					 | SLCD_ISDATA_SDMASK(seg_mask);
+    SLCD->ISDATA.reg = SLCD_ISDATA_SDATA(seg_data)
+                     | SLCD_ISDATA_OFF(byte_offset)
+                     | SLCD_ISDATA_SDMASK(seg_mask);
 
-	while (slcd_get_char_writing_status()) {
-	}
+    while (slcd_get_char_writing_status())
+    {
+    }
 }
 
 /**
@@ -559,20 +593,20 @@ void slcd_set_seg_data(uint8_t seg_data,uint8_t byte_offset,uint8_t seg_mask)
  *
  */
 void slcd_automated_char_get_config_default(
-		struct slcd_automated_char_config *config)
+        struct slcd_automated_char_config *config)
 {
-	Assert(config);
-
-	config->order = SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT;
-	config->fc = SLCD_FRAME_COUNTER_0;
-	config->mode = SLCD_AUTOMATED_CHAR_SEQ;
-	config->seg_line_num = 0;
-	config->start_seg_line = 0;
-	config->row_digit_num = 1;
-	config->digit_num = 0;
-	config->scrolling_step = 1;
-	config->com_line_num = 1;
-	config->data_mask = 0;
+    Assert(config);
+
+    config->order = SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT;
+    config->fc = SLCD_FRAME_COUNTER_0;
+    config->mode = SLCD_AUTOMATED_CHAR_SEQ;
+    config->seg_line_num = 0;
+    config->start_seg_line = 0;
+    config->row_digit_num = 1;
+    config->digit_num = 0;
+    config->scrolling_step = 1;
+    config->com_line_num = 1;
+    config->data_mask = 0;
 
 }
 
@@ -591,24 +625,25 @@ void slcd_automated_char_get_config_default(
  * \retval STATUS_ERR_INVALID_ARG  If automated character  configuration failed
  */
 enum status_code slcd_automated_char_set_config(
-		struct slcd_automated_char_config *const config)
+        struct slcd_automated_char_config *const config)
 {
-	if (!config) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(config->seg_line_num)
-					 | (config->order  << SLCD_CMCFG_DEC_Pos);
-	SLCD->ACMCFG.reg = SLCD_ACMCFG_FCS(config->fc)
-					 | (config->mode << SLCD_ACMCFG_MODE_Pos)
-					 | SLCD_ACMCFG_STSEG(config->start_seg_line)
-					 | SLCD_ACMCFG_NDROW(config->row_digit_num)
-					 | SLCD_ACMCFG_NDIG(config->digit_num)
-					 | SLCD_ACMCFG_STEPS(config->scrolling_step)
-					 | SLCD_ACMCFG_NCOM(config->com_line_num);
-
-	SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(config->data_mask);
-
-	return STATUS_OK;
+    if (!config)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(config->seg_line_num)
+                     | (config->order  << SLCD_CMCFG_DEC_Pos);
+    SLCD->ACMCFG.reg = SLCD_ACMCFG_FCS(config->fc)
+                     | (config->mode << SLCD_ACMCFG_MODE_Pos)
+                     | SLCD_ACMCFG_STSEG(config->start_seg_line)
+                     | SLCD_ACMCFG_NDROW(config->row_digit_num)
+                     | SLCD_ACMCFG_NDIG(config->digit_num)
+                     | SLCD_ACMCFG_STEPS(config->scrolling_step)
+                     | SLCD_ACMCFG_NCOM(config->com_line_num);
+
+    SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(config->data_mask);
+
+    return STATUS_OK;
 }
 
 /**
@@ -621,11 +656,11 @@ enum status_code slcd_automated_char_set_config(
  *                          it equal to number of SEG line - 1
  */
 void slcd_character_map_set(
-		enum slcd_automated_char_order order,
-		uint8_t seg_line_num)
+        enum slcd_automated_char_order order,
+        uint8_t seg_line_num)
 {
-	SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(seg_line_num)
-					 | (order  << SLCD_CMCFG_DEC_Pos);
+    SLCD->CMCFG.reg = SLCD_CMCFG_NSEG(seg_line_num)
+                     | (order  << SLCD_CMCFG_DEC_Pos);
 }
 
 /**
@@ -637,16 +672,17 @@ void slcd_character_map_set(
  * \param[in] seg_line_index Segments line index
  */
 void slcd_character_write_data(uint8_t com_line_index,
-									uint8_t seg_line_index,
-									uint32_t seg_data,uint32_t data_mask)
+                                    uint8_t seg_line_index,
+                                    uint32_t seg_data,uint32_t data_mask)
 {
 
-	SLCD->CMINDEX.reg = SLCD_CMINDEX_SINDEX(seg_line_index)
-						| SLCD_CMINDEX_CINDEX(com_line_index);
-	SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(data_mask);
-	SLCD->CMDATA.reg = SLCD_CMDATA_SDATA(seg_data);
-	while (slcd_get_char_writing_status()) {
-	}
+    SLCD->CMINDEX.reg = SLCD_CMINDEX_SINDEX(seg_line_index)
+                        | SLCD_CMINDEX_CINDEX(com_line_index);
+    SLCD->CMDMASK.reg = SLCD_CMDMASK_SDMASK(data_mask);
+    SLCD->CMDATA.reg = SLCD_CMDATA_SDATA(seg_data);
+    while (slcd_get_char_writing_status())
+    {
+    }
 }
 
 /**
@@ -658,14 +694,14 @@ void slcd_character_write_data(uint8_t com_line_index,
  *
  */
 void slcd_circular_shift_get_config_defaults(
-		struct slcd_circular_shift_config *const config)
+        struct slcd_circular_shift_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->fc = SLCD_FRAME_COUNTER_0;
-	config->dir = SLCD_CIRCULAR_SHIFT_LEFT;
-	config->size = 0;
-	config->data = 0;
+    config->fc = SLCD_FRAME_COUNTER_0;
+    config->dir = SLCD_CIRCULAR_SHIFT_LEFT;
+    config->size = 0;
+    config->data = 0;
 }
 
 /**
@@ -683,16 +719,17 @@ void slcd_circular_shift_get_config_defaults(
  */
 
 enum status_code slcd_circular_shift_set_config(
-		struct slcd_circular_shift_config *const config)
+        struct slcd_circular_shift_config *const config)
 {
-	if (!config) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	SLCD->CSRCFG.reg = SLCD_CSRCFG_FCS(config->fc)
-					 | (config->dir << SLCD_CSRCFG_DIR_Pos)
-					 | SLCD_CSRCFG_SIZE(config->size)
-					 | SLCD_CSRCFG_DATA(config->data);
-
-	return STATUS_OK;
+    if (!config)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    SLCD->CSRCFG.reg = SLCD_CSRCFG_FCS(config->fc)
+                     | (config->dir << SLCD_CSRCFG_DIR_Pos)
+                     | SLCD_CSRCFG_SIZE(config->size)
+                     | SLCD_CSRCFG_DATA(config->data);
+
+    return STATUS_OK;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h
index 3b909a9cc057..4cfd5ad8ae8b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd.h
@@ -150,12 +150,12 @@ extern "C" {
  * Enum SLCD frame counter definition.
  */
 enum slcd_frame_counter {
-	/** SLCD frame counter 0 */
-	SLCD_FRAME_COUNTER_0,
-	/** SLCD frame counter 1 */
-	SLCD_FRAME_COUNTER_1,
-	/** SLCD frame counter 2 */
-	SLCD_FRAME_COUNTER_2,
+    /** SLCD frame counter 0 */
+    SLCD_FRAME_COUNTER_0,
+    /** SLCD frame counter 1 */
+    SLCD_FRAME_COUNTER_1,
+    /** SLCD frame counter 2 */
+    SLCD_FRAME_COUNTER_2,
 };
 
 /**
@@ -164,10 +164,10 @@ enum slcd_frame_counter {
  * Enum waveform mode.
  */
 enum slcd_waveform_mode {
-	/** Low power waveform mode */
-	SLCD_LOW_POWER_WAVEFORM_MODE = 0,
-	/** Standard waveform mode */
-	SLCD_STANDARD_WAVEFORM_MODE,
+    /** Low power waveform mode */
+    SLCD_LOW_POWER_WAVEFORM_MODE = 0,
+    /** Standard waveform mode */
+    SLCD_STANDARD_WAVEFORM_MODE,
 };
 
 /**
@@ -176,19 +176,19 @@ enum slcd_waveform_mode {
  * Basic configuration for SLCDC.
  */
 struct slcd_config {
-	/** Keep SLCD enabled in standby sleep mode if true */
-	bool run_in_standby;
-	/** waveform mode selection */
-	enum slcd_waveform_mode waveform_mode;
-
-	/** Low resistance network duration */
-	uint8_t low_resistance_duration;
-	/** Enable Low resistance if true */
-	bool enable_low_resistance;
-	/** Bias buffer duration */
-	uint8_t bias_buffer_duration;
-	/** Enable bias buffer if true */
-	bool enable_bias_buffer;
+    /** Keep SLCD enabled in standby sleep mode if true */
+    bool run_in_standby;
+    /** waveform mode selection */
+    enum slcd_waveform_mode waveform_mode;
+
+    /** Low resistance network duration */
+    uint8_t low_resistance_duration;
+    /** Enable Low resistance if true */
+    bool enable_low_resistance;
+    /** Bias buffer duration */
+    uint8_t bias_buffer_duration;
+    /** Enable bias buffer if true */
+    bool enable_bias_buffer;
 };
 /**
  * \brief SLCD event enable/disable structure
@@ -197,12 +197,12 @@ struct slcd_config {
  * disable events via \ref slcd_enable_events() and \ref slcd_disable_events().
  */
 struct slcd_events {
-	/** Enable event generation on frame counter 0 overflow */
-	bool generate_event_on_fc0_overflow;
-	/** Enable event generation on frame counter 1 overflow */
-	bool generate_event_on_fc1_overflow;
-	/** Enable event generation on frame counter 2 overflow */
-	bool generate_event_on_fc2_overflow;
+    /** Enable event generation on frame counter 0 overflow */
+    bool generate_event_on_fc0_overflow;
+    /** Enable event generation on frame counter 1 overflow */
+    bool generate_event_on_fc1_overflow;
+    /** Enable event generation on frame counter 2 overflow */
+    bool generate_event_on_fc2_overflow;
 };
 
 /**
@@ -211,11 +211,11 @@ struct slcd_events {
  * SLCD blink configuration.
  */
 struct slcd_blink_config {
-	/** Frame counter selection for blinking */
-	enum slcd_frame_counter fc;
-	/** All segments are allowed to blink if true, else only
-	  Selected segments are allowed to blink */
-	bool blink_all_seg;
+    /** Frame counter selection for blinking */
+    enum slcd_frame_counter fc;
+    /** All segments are allowed to blink if true, else only
+      Selected segments are allowed to blink */
+    bool blink_all_seg;
 };
 
 /**
@@ -224,10 +224,10 @@ struct slcd_blink_config {
  * Enum SLCD circular shift direction.
  */
 enum slcd_circular_shift_dir {
-	/** Circular shift direction is left */
-	SLCD_CIRCULAR_SHIFT_LEFT = 0,
-	/** Circular shift direction is right */
-	SLCD_CIRCULAR_SHIFT_RIGHT,
+    /** Circular shift direction is left */
+    SLCD_CIRCULAR_SHIFT_LEFT = 0,
+    /** Circular shift direction is right */
+    SLCD_CIRCULAR_SHIFT_RIGHT,
 };
 
 /**
@@ -236,14 +236,14 @@ enum slcd_circular_shift_dir {
  * SLCD circular shift configuration.
  */
 struct slcd_circular_shift_config {
-	/** Frame counter selection for circular shift */
-	enum slcd_frame_counter fc;
-	/** Shift direction */
-	enum slcd_circular_shift_dir dir;
-	/** Size of the circular shift register, MAX. size is 16 */
-	uint8_t size;
-	/** Circular shift register value */
-	uint16_t data;
+    /** Frame counter selection for circular shift */
+    enum slcd_frame_counter fc;
+    /** Shift direction */
+    enum slcd_circular_shift_dir dir;
+    /** Size of the circular shift register, MAX. size is 16 */
+    uint8_t size;
+    /** Circular shift register value */
+    uint16_t data;
 };
 
 /**
@@ -252,10 +252,10 @@ struct slcd_circular_shift_config {
  * Enum automated char order.
  */
 enum slcd_automated_char_order {
-	/** Segment is starting from bottom right */
-	SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT = 0,
-	/** Segment is starting from bottom left */
-	SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_LEFT,
+    /** Segment is starting from bottom right */
+    SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_RIGHT = 0,
+    /** Segment is starting from bottom left */
+    SLCD_AUTOMATED_CHAR_START_FROM_BOTTOM_LEFT,
 };
 
 /**
@@ -264,10 +264,10 @@ enum slcd_automated_char_order {
  * Enum automated char display mode.
  */
 enum slcd_automated_char_mode {
-	/** Sequential Display Mode */
-	SLCD_AUTOMATED_CHAR_SEQ = 0,
-	/** Scrolling Display Mode */
-	SLCD_AUTOMATED_CHAR_SCROLL,
+    /** Sequential Display Mode */
+    SLCD_AUTOMATED_CHAR_SEQ = 0,
+    /** Scrolling Display Mode */
+    SLCD_AUTOMATED_CHAR_SCROLL,
 };
 
 /**
@@ -276,29 +276,29 @@ enum slcd_automated_char_mode {
  * SLCD automated char configuration.
  */
 struct slcd_automated_char_config {
-	/** Mapping order in automated char mode */
-	enum slcd_automated_char_order order;
-	/** Frame counter selection for automated character mapping */
-	enum slcd_frame_counter fc;
-	/** Display mode */
-	enum slcd_automated_char_mode mode;
-	/** Define the number of SEG line per digit,
-		it equal to number of SEG line - 1 */
-	uint8_t seg_line_num;
-	/** Define the index of the first segment terminal of the digit to display */
-	uint8_t start_seg_line;
-	/** Define the number of digit per row */
-	uint8_t row_digit_num;
-	/** Define the number of digit, it must be greater than 1 */
-	uint8_t digit_num;
-	/** Define the number of steps in scrolling mode.
-		scrolling_step = character string length - digit_num + 1 */
-	uint8_t scrolling_step;
-	/** Define the number of COM line per row,
-		it equal to number of COM line - 1 */
-	uint8_t com_line_num;
-	/** Segments data mask */
-	uint32_t data_mask;
+    /** Mapping order in automated char mode */
+    enum slcd_automated_char_order order;
+    /** Frame counter selection for automated character mapping */
+    enum slcd_frame_counter fc;
+    /** Display mode */
+    enum slcd_automated_char_mode mode;
+    /** Define the number of SEG line per digit,
+        it equal to number of SEG line - 1 */
+    uint8_t seg_line_num;
+    /** Define the index of the first segment terminal of the digit to display */
+    uint8_t start_seg_line;
+    /** Define the number of digit per row */
+    uint8_t row_digit_num;
+    /** Define the number of digit, it must be greater than 1 */
+    uint8_t digit_num;
+    /** Define the number of steps in scrolling mode.
+        scrolling_step = character string length - digit_num + 1 */
+    uint8_t scrolling_step;
+    /** Define the number of COM line per row,
+        it equal to number of COM line - 1 */
+    uint8_t com_line_num;
+    /** Segments data mask */
+    uint32_t data_mask;
 
 };
 
@@ -332,11 +332,12 @@ enum status_code slcd_set_contrast(uint8_t contrast);
 static inline bool slcd_is_syncing(void)
 {
 
-	if (SLCD->SYNCBUSY.reg) {
-		return true;
-	}
+    if (SLCD->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -347,7 +348,7 @@ static inline bool slcd_is_syncing(void)
  */
 static inline void slcd_lock_shadow_memory(void)
 {
-	SLCD->CTRLC.reg |= SLCD_CTRLC_LOCK;
+    SLCD->CTRLC.reg |= SLCD_CTRLC_LOCK;
 }
 
 /**
@@ -357,7 +358,7 @@ static inline void slcd_lock_shadow_memory(void)
  */
 static inline void slcd_unlock_shadow_memory(void)
 {
-	SLCD->CTRLC.reg &= (SLCD_CTRLC_MASK & ( ~SLCD_CTRLC_LOCK));
+    SLCD->CTRLC.reg &= (SLCD_CTRLC_MASK & ( ~SLCD_CTRLC_LOCK));
 }
 
 /**
@@ -367,7 +368,7 @@ static inline void slcd_unlock_shadow_memory(void)
  */
 static inline void slcd_clear_display_memory(void)
 {
-	SLCD->CTRLC.reg |= SLCD_CTRLC_CLEAR;
+    SLCD->CTRLC.reg |= SLCD_CTRLC_CLEAR;
 }
 
 /**
@@ -377,10 +378,11 @@ static inline void slcd_clear_display_memory(void)
  */
 static inline void slcd_enable_display(void)
 {
-	SLCD->CTRLD.reg |= SLCD_CTRLD_DISPEN;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg |= SLCD_CTRLD_DISPEN;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -390,10 +392,11 @@ static inline void slcd_enable_display(void)
  */
 static inline void slcd_disable_display(void)
 {
-	SLCD->CTRLD.reg &= (SLCD_CTRLD_MASK & ( ~SLCD_CTRLD_DISPEN));
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg &= (SLCD_CTRLD_MASK & ( ~SLCD_CTRLD_DISPEN));
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 /**
  * \brief  DMA display memory update frame counter selection
@@ -406,7 +409,7 @@ static inline void slcd_disable_display(void)
  */
 static inline void slcd_dma_display_memory_update_fc_sel(enum slcd_frame_counter fc)
 {
-	SLCD->CTRLA.bit.DMFCS = fc;
+    SLCD->CTRLA.bit.DMFCS = fc;
 }
 
 /** @} */
@@ -423,10 +426,11 @@ static inline void slcd_dma_display_memory_update_fc_sel(enum slcd_frame_counter
  */
 static inline void slcd_enable_blink(void)
 {
-	SLCD->CTRLD.reg |= SLCD_CTRLD_BLINK;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg |= SLCD_CTRLD_BLINK;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -436,10 +440,11 @@ static inline void slcd_enable_blink(void)
  */
 static inline void slcd_disable_blink(void)
 {
-	SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLINK;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLINK;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 void slcd_blink_get_config_defaults(struct slcd_blink_config *blink_config);
@@ -463,10 +468,11 @@ void slcd_set_blink_pixel(uint8_t pix_com,uint8_t pix_seg);
  */
 static inline void slcd_enable_blank(void)
 {
-	SLCD->CTRLD.reg |= SLCD_CTRLD_BLANK;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg |= SLCD_CTRLD_BLANK;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 /**
  * \brief Blank mode disable
@@ -475,10 +481,11 @@ static inline void slcd_enable_blank(void)
  */
 static inline void slcd_disable_blank(void)
 {
-	SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLANK;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg &= ~SLCD_CTRLD_BLANK;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 /** @} */
 
@@ -499,24 +506,27 @@ static inline void slcd_disable_blank(void)
 static inline void slcd_enable_events(struct slcd_events *const events)
 {
 
-	Assert(hw);
-	Assert(events);
+    Assert(hw);
+    Assert(events);
 
-	uint8_t event_mask = 0;
+    uint8_t event_mask = 0;
 
-	if (events->generate_event_on_fc0_overflow) {
-		event_mask |= SLCD_EVCTRL_FC0OEO;
-	}
+    if (events->generate_event_on_fc0_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC0OEO;
+    }
 
-	if (events->generate_event_on_fc1_overflow) {
-		event_mask |= SLCD_EVCTRL_FC1OEO;
-	}
+    if (events->generate_event_on_fc1_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC1OEO;
+    }
 
-	if (events->generate_event_on_fc2_overflow) {
-		event_mask |= SLCD_EVCTRL_FC2OEO;
-	}
+    if (events->generate_event_on_fc2_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC2OEO;
+    }
 
-	SLCD->EVCTRL.reg |= event_mask;
+    SLCD->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -529,23 +539,26 @@ static inline void slcd_enable_events(struct slcd_events *const events)
 static inline void slcd_disable_events(struct slcd_events *const events)
 {
 
-	Assert(events);
+    Assert(events);
 
-	uint8_t event_mask = 0;
+    uint8_t event_mask = 0;
 
-	if (events->generate_event_on_fc0_overflow) {
-		event_mask |= SLCD_EVCTRL_FC0OEO;
-	}
+    if (events->generate_event_on_fc0_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC0OEO;
+    }
 
-	if (events->generate_event_on_fc1_overflow) {
-		event_mask |= SLCD_EVCTRL_FC1OEO;
-	}
+    if (events->generate_event_on_fc1_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC1OEO;
+    }
 
-	if (events->generate_event_on_fc2_overflow) {
-		event_mask |= SLCD_EVCTRL_FC2OEO;
-	}
+    if (events->generate_event_on_fc2_overflow)
+    {
+        event_mask |= SLCD_EVCTRL_FC2OEO;
+    }
 
-	SLCD->EVCTRL.reg &= ~event_mask;
+    SLCD->EVCTRL.reg &= ~event_mask;
 }
 
 /** @} */
@@ -565,15 +578,15 @@ static inline void slcd_disable_events(struct slcd_events *const events)
  *  \param[in] fc Frame counter index
  *  \param[in] presc_bypass_enable Bypass of the frame counter prescaler
  *  \param[in] overflow_value  Frame counter overflow value. The number of frame
- *		before overflow is ((overflow_value+1)*8) when presc_bypass_enable=0
- 		else (overflow_value+1). The MAX. overflow value is 0x1FFFF.
+ *      before overflow is ((overflow_value+1)*8) when presc_bypass_enable=0
+        else (overflow_value+1). The MAX. overflow value is 0x1FFFF.
  */
 static inline void slcd_set_frame_counter(enum slcd_frame_counter fc,
-										   bool  presc_bypass_enable,
-										   uint16_t overflow_value)
+                                           bool  presc_bypass_enable,
+                                           uint16_t overflow_value)
 {
-	*(&(SLCD->FC0.reg) + fc) =  (presc_bypass_enable << SLCD_FC0_PB_Pos)
-							 | SLCD_FC0_OVF(overflow_value);
+    *(&(SLCD->FC0.reg) + fc) =  (presc_bypass_enable << SLCD_FC0_PB_Pos)
+                             | SLCD_FC0_OVF(overflow_value);
 }
 
 /**
@@ -581,27 +594,29 @@ static inline void slcd_set_frame_counter(enum slcd_frame_counter fc,
  *
  *  Enables one frame counter.
  *
- *	\param[in] fc Frame counter index
+ *  \param[in] fc Frame counter index
  */
 static inline void slcd_enable_frame_counter(enum slcd_frame_counter fc)
 {
 
-	switch(fc) {
-		case SLCD_FRAME_COUNTER_0:
-			SLCD->CTRLD.reg |= SLCD_CTRLD_FC0EN;
-			break;
-		case SLCD_FRAME_COUNTER_1:
-			SLCD->CTRLD.reg |= SLCD_CTRLD_FC1EN;
-			break;
-		case SLCD_FRAME_COUNTER_2:
-			SLCD->CTRLD.reg |= SLCD_CTRLD_FC2EN;
-			break;
-		default :
-			break;
-	}
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    switch(fc)
+    {
+        case SLCD_FRAME_COUNTER_0:
+            SLCD->CTRLD.reg |= SLCD_CTRLD_FC0EN;
+            break;
+        case SLCD_FRAME_COUNTER_1:
+            SLCD->CTRLD.reg |= SLCD_CTRLD_FC1EN;
+            break;
+        case SLCD_FRAME_COUNTER_2:
+            SLCD->CTRLD.reg |= SLCD_CTRLD_FC2EN;
+            break;
+        default :
+            break;
+    }
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -609,26 +624,28 @@ static inline void slcd_enable_frame_counter(enum slcd_frame_counter fc)
  *
  *  Disable one frame counter.
  *
- *	\param[in] fc Frame counter index
+ *  \param[in] fc Frame counter index
  */
 static inline void slcd_disable_frame_counter(enum slcd_frame_counter fc)
 {
-	switch(fc) {
-		case SLCD_FRAME_COUNTER_0:
-			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC0EN;
-			break;
-		case SLCD_FRAME_COUNTER_1:
-			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC1EN;
-			break;
-		case SLCD_FRAME_COUNTER_2:
-			SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC2EN;
-			break;
-		default :
-			break;
-	}
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    switch(fc)
+    {
+        case SLCD_FRAME_COUNTER_0:
+            SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC0EN;
+            break;
+        case SLCD_FRAME_COUNTER_1:
+            SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC1EN;
+            break;
+        case SLCD_FRAME_COUNTER_2:
+            SLCD->CTRLD.reg &= ~SLCD_CTRLD_FC2EN;
+            break;
+        default :
+            break;
+    }
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 /** @} */
 
@@ -650,12 +667,12 @@ void slcd_set_seg_data(uint8_t seg_data, uint8_t byte_offset, uint8_t seg_mask);
  */
 
 void slcd_character_map_set(
-		enum slcd_automated_char_order order,
-		uint8_t seg_line_num);
+        enum slcd_automated_char_order order,
+        uint8_t seg_line_num);
 void slcd_character_write_data(uint8_t com_line_index,
-							uint8_t seg_line_index,
-							uint32_t seg_data,
-							uint32_t data_mask);
+                            uint8_t seg_line_index,
+                            uint32_t seg_data,
+                            uint32_t data_mask);
 
 /**
  * \brief Enables automated character display
@@ -664,7 +681,7 @@ void slcd_character_write_data(uint8_t com_line_index,
  */
 static inline void slcd_enable_automated_character(void)
 {
-	SLCD->CTRLC.reg |= SLCD_CTRLC_ACMEN;
+    SLCD->CTRLC.reg |= SLCD_CTRLC_ACMEN;
 }
 
 /**
@@ -674,12 +691,12 @@ static inline void slcd_enable_automated_character(void)
  */
 static inline void slcd_disable_automated_character(void)
 {
-	SLCD->CTRLC.reg &= ~SLCD_CTRLC_ACMEN;
+    SLCD->CTRLC.reg &= ~SLCD_CTRLC_ACMEN;
 }
 void slcd_automated_char_get_config_default(
-		struct slcd_automated_char_config *config);
+        struct slcd_automated_char_config *config);
 enum status_code slcd_automated_char_set_config(
-		struct slcd_automated_char_config *const config);
+        struct slcd_automated_char_config *const config);
 /** @} */
 
 /**
@@ -694,7 +711,7 @@ enum status_code slcd_automated_char_set_config(
  */
 static inline void slcd_enable_automated_bit(void)
 {
-	SLCD->CTRLC.reg |= SLCD_CTRLC_ABMEN;
+    SLCD->CTRLC.reg |= SLCD_CTRLC_ABMEN;
 }
 
 /**
@@ -704,7 +721,7 @@ static inline void slcd_enable_automated_bit(void)
  */
 static inline void slcd_disable_automated_bit(void)
 {
-	SLCD->CTRLC.reg &= ~SLCD_CTRLC_ABMEN;
+    SLCD->CTRLC.reg &= ~SLCD_CTRLC_ABMEN;
 }
 
 /**
@@ -716,9 +733,10 @@ static inline void slcd_disable_automated_bit(void)
  */
 static inline void slcd_set_automated_bit(uint8_t size,enum slcd_frame_counter fc)
 {
-	if(size > 0 && size < 0x3f) {
-		SLCD->ABMCFG.reg = SLCD_ABMCFG_SIZE(size) | SLCD_ABMCFG_FCS(fc);
-	}
+    if(size > 0 && size < 0x3f)
+    {
+        SLCD->ABMCFG.reg = SLCD_ABMCFG_SIZE(size) | SLCD_ABMCFG_FCS(fc);
+    }
 }
 
 /** @} */
@@ -733,26 +751,28 @@ static inline void slcd_set_automated_bit(uint8_t size,enum slcd_frame_counter f
  */
 static inline void slcd_enable_circular_shift(void)
 {
-	SLCD->CTRLD.reg |= SLCD_CTRLD_CSREN;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg |= SLCD_CTRLD_CSREN;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 /**
  * \brief Disable SLCD circular shift mode
  */
 static inline void slcd_disable_circular_shift(void)
 {
-	SLCD->CTRLD.reg &= ~SLCD_CTRLD_CSREN;
-	while (slcd_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    SLCD->CTRLD.reg &= ~SLCD_CTRLD_CSREN;
+    while (slcd_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 void slcd_circular_shift_get_config_defaults(
-		struct slcd_circular_shift_config *const config);
+        struct slcd_circular_shift_config *const config);
 
 enum status_code slcd_circular_shift_set_config(
-		struct slcd_circular_shift_config *const config);
+        struct slcd_circular_shift_config *const config);
 
 /** @} */
 
@@ -772,7 +792,7 @@ enum status_code slcd_circular_shift_set_config(
 
 static inline bool slcd_get_auto_bit_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_ABMBUSY) == SLCD_STATUS_ABMBUSY);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_ABMBUSY) == SLCD_STATUS_ABMBUSY);
 }
 
 /**
@@ -786,7 +806,7 @@ static inline bool slcd_get_auto_bit_status(void)
 
 static inline bool slcd_get_auto_char_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_ACMBUSY) == SLCD_STATUS_ACMBUSY);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_ACMBUSY) == SLCD_STATUS_ACMBUSY);
 }
 
 /**
@@ -800,7 +820,7 @@ static inline bool slcd_get_auto_char_status(void)
 
 static inline bool slcd_get_char_writing_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_CMWRBUSY) == SLCD_STATUS_CMWRBUSY);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_CMWRBUSY) == SLCD_STATUS_CMWRBUSY);
 }
 
 /**
@@ -814,7 +834,7 @@ static inline bool slcd_get_char_writing_status(void)
 
 static inline bool slcd_get_vlcd_vdd33_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDS) == SLCD_STATUS_VLCDS);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDS) == SLCD_STATUS_VLCDS);
 }
 
 /**
@@ -828,7 +848,7 @@ static inline bool slcd_get_vlcd_vdd33_status(void)
 
 static inline bool slcd_get_charge_pump_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_PRUN) == SLCD_STATUS_PRUN);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_PRUN) == SLCD_STATUS_PRUN);
 }
 
 /**
@@ -842,7 +862,7 @@ static inline bool slcd_get_charge_pump_status(void)
 
 static inline bool slcd_get_vlcd_ready_status(void)
 {
-	return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDR) == SLCD_STATUS_VLCDR);
+    return ((SLCD->STATUS.reg & SLCD_STATUS_VLCDR) == SLCD_STATUS_VLCDR);
 }
 
 /** @} */
@@ -909,12 +929,12 @@ static inline bool slcd_get_vlcd_ready_status(void)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -932,16 +952,16 @@ static inline bool slcd_get_vlcd_ready_status(void)
  * \page asfdoc_sam0_drivers_slcd_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
+ *  <tr>
+ *      <th>Doc. rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
  *      <td>42605A</td>
- *		<td>12/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *      <td>12/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  *
  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c
index 9b300aded11f..3125188e942f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.c
@@ -72,15 +72,16 @@ slcd_callback_t slcd_callback_pointer[SLCD_CALLBACK_TYPE_NUM];
  */
 
 enum status_code slcd_register_callback(
-	const slcd_callback_t callback,
-	const enum slcd_callback_type type)
+    const slcd_callback_t callback,
+    const enum slcd_callback_type type)
 {
-	if (type >= SLCD_CALLBACK_TYPE_NUM){
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (type >= SLCD_CALLBACK_TYPE_NUM)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	slcd_callback_pointer[type] = callback;
-	return STATUS_OK;
+    slcd_callback_pointer[type] = callback;
+    return STATUS_OK;
 }
 
 /**
@@ -95,15 +96,16 @@ enum status_code slcd_register_callback(
  */
 
 enum status_code slcd_unregister_callback(
-	const slcd_callback_t callback,
-	const enum slcd_callback_type type)
+    const slcd_callback_t callback,
+    const enum slcd_callback_type type)
 {
-	if (type >= SLCD_CALLBACK_TYPE_NUM){
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (type >= SLCD_CALLBACK_TYPE_NUM)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	slcd_callback_pointer[type] = NULL;
-	return STATUS_OK;
+    slcd_callback_pointer[type] = NULL;
+    return STATUS_OK;
 }
 
 /**
@@ -111,15 +113,18 @@ enum status_code slcd_unregister_callback(
 */
 void SLCD_Handler(void)
 {
-	uint32_t status = SLCD->INTFLAG.reg;
-	for (uint8_t i = 0; i < SLCD_CALLBACK_TYPE_NUM; i++) {
-		if (status & (1 << i)) {
-			/* Clear the INTFLAG anyway */
-			SLCD->INTFLAG.reg = 1 << i;
+    uint32_t status = SLCD->INTFLAG.reg;
+    for (uint8_t i = 0; i < SLCD_CALLBACK_TYPE_NUM; i++)
+    {
+        if (status & (1 << i))
+        {
+            /* Clear the INTFLAG anyway */
+            SLCD->INTFLAG.reg = 1 << i;
 
-			if (slcd_callback_pointer[i]) {
-				slcd_callback_pointer[i]((enum slcd_callback_type)i);
-			}
-		}
-	}
+            if (slcd_callback_pointer[i])
+            {
+                slcd_callback_pointer[i]((enum slcd_callback_type)i);
+            }
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h
index d6d9723840ec..c6049df34e7a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/slcd/slcd_callback.h
@@ -63,21 +63,21 @@ extern "C" {
 /**
  * \brief SLCD callback type
  *
- * Enum SLCD callback type. 
+ * Enum SLCD callback type.
  */
 enum slcd_callback_type {
-	/** Frame Counter 0 Overflow callback */
-	SLCD_CALLBACK_FC0_OVERFLOW = 0,
-	/** Frame Counter 1 Overflow callback */
-	SLCD_CALLBACK_FC1_OVERFLOW,
-	/** Frame Counter 2 Overflow callback */
-	SLCD_CALLBACK_FC2_OVERFLOW,
-	/** VLCD Ready Toggle callback */
-	SLCD_CALLBACK_VLCD_READY,
-	/** VLCD Status Toggle callback */
-	SLCD_CALLBACK_VLCD_TOGGLE,
-	/** Pump Run Status Toggle callback */
-	SLCD_CALLBACK_PUMP_TOGGLE,
+    /** Frame Counter 0 Overflow callback */
+    SLCD_CALLBACK_FC0_OVERFLOW = 0,
+    /** Frame Counter 1 Overflow callback */
+    SLCD_CALLBACK_FC1_OVERFLOW,
+    /** Frame Counter 2 Overflow callback */
+    SLCD_CALLBACK_FC2_OVERFLOW,
+    /** VLCD Ready Toggle callback */
+    SLCD_CALLBACK_VLCD_READY,
+    /** VLCD Status Toggle callback */
+    SLCD_CALLBACK_VLCD_TOGGLE,
+    /** Pump Run Status Toggle callback */
+    SLCD_CALLBACK_PUMP_TOGGLE,
 };
 
 /** SLCD interrupt callback function type. */
@@ -91,12 +91,12 @@ typedef void (*slcd_callback_t)(enum slcd_callback_type type);
  */
 
 enum status_code slcd_register_callback(
-	const slcd_callback_t callback,
-	const enum slcd_callback_type type);
+    const slcd_callback_t callback,
+    const enum slcd_callback_type type);
 
 enum status_code slcd_unregister_callback(
-	const slcd_callback_t callback,
-	const enum slcd_callback_type type);
+    const slcd_callback_t callback,
+    const enum slcd_callback_type type);
 
 /**
  * \brief Enable an SLCD callback
@@ -108,9 +108,10 @@ enum status_code slcd_unregister_callback(
  */
 static inline void slcd_enable_callback(const enum slcd_callback_type type)
 {
-	if (type < SLCD_CALLBACK_TYPE_NUM){
-		SLCD->INTENSET.reg = 1 << type;
-	}
+    if (type < SLCD_CALLBACK_TYPE_NUM)
+    {
+        SLCD->INTENSET.reg = 1 << type;
+    }
 }
 
 /**
@@ -123,9 +124,10 @@ static inline void slcd_enable_callback(const enum slcd_callback_type type)
  */
 static inline void slcd_disable_callback(const enum slcd_callback_type type)
 {
-	if (type < SLCD_CALLBACK_TYPE_NUM){
-		SLCD->INTENCLR.reg = 1 << type;
-	}
+    if (type < SLCD_CALLBACK_TYPE_NUM)
+    {
+        SLCD->INTENCLR.reg = 1 << type;
+    }
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c
index 32bd8530350f..c4328588dfca 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.c
@@ -62,9 +62,9 @@
  */
 static bool _spi_is_active(Spi *const spi_module)
 {
-	Assert(spi_module);
+    Assert(spi_module);
 
-	return spi_module->SPI_BUS_STATUS.bit.SPI_ACTIVE;
+    return spi_module->SPI_BUS_STATUS.bit.SPI_ACTIVE;
 }
 
 /**
@@ -76,21 +76,23 @@ static bool _spi_is_active(Spi *const spi_module)
  */
 static void _spi_clock_enable(struct spi_module *const module)
 {
-	Assert(module);
-
-	Spi *const spi_module = (module->hw);
-
-	if (spi_module == (void *)SPI0) {
-		system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_CLK);
-		system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_PHASE);
-		system_clock_peripheral_enable(PERIPHERAL_SPI0_IF);
-		system_clock_peripheral_enable(PERIPHERAL_SPI0_CORE);
-	} else if (spi_module == (void *)SPI1) {
-		system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_CLK);
-		system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_PHASE);
-		system_clock_peripheral_enable(PERIPHERAL_SPI1_IF);
-		system_clock_peripheral_enable(PERIPHERAL_SPI1_CORE);
-	}
+    Assert(module);
+
+    Spi *const spi_module = (module->hw);
+
+    if (spi_module == (void *)SPI0)
+    {
+        system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_CLK);
+        system_clock_peripheral_enable(PERIPHERAL_SPI0_SCK_PHASE);
+        system_clock_peripheral_enable(PERIPHERAL_SPI0_IF);
+        system_clock_peripheral_enable(PERIPHERAL_SPI0_CORE);
+    } else if (spi_module == (void *)SPI1)
+    {
+        system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_CLK);
+        system_clock_peripheral_enable(PERIPHERAL_SPI1_SCK_PHASE);
+        system_clock_peripheral_enable(PERIPHERAL_SPI1_IF);
+        system_clock_peripheral_enable(PERIPHERAL_SPI1_CORE);
+    }
 }
 
 /**
@@ -102,21 +104,23 @@ static void _spi_clock_enable(struct spi_module *const module)
  */
 static void _spi_clock_disable(struct spi_module *const module)
 {
-	Assert(module);
-
-	Spi *const spi_module = (module->hw);
-
-	if (spi_module == (void *)SPI0) {
-		system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_CLK);
-		system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_PHASE);
-		system_clock_peripheral_disable(PERIPHERAL_SPI0_IF);
-		system_clock_peripheral_disable(PERIPHERAL_SPI0_CORE);
-	} else if (spi_module == (void *)SPI1) {
-		system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_CLK);
-		system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_PHASE);
-		system_clock_peripheral_disable(PERIPHERAL_SPI1_IF);
-		system_clock_peripheral_disable(PERIPHERAL_SPI1_CORE);
-	}
+    Assert(module);
+
+    Spi *const spi_module = (module->hw);
+
+    if (spi_module == (void *)SPI0)
+    {
+        system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_CLK);
+        system_clock_peripheral_disable(PERIPHERAL_SPI0_SCK_PHASE);
+        system_clock_peripheral_disable(PERIPHERAL_SPI0_IF);
+        system_clock_peripheral_disable(PERIPHERAL_SPI0_CORE);
+    } else if (spi_module == (void *)SPI1)
+    {
+        system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_CLK);
+        system_clock_peripheral_disable(PERIPHERAL_SPI1_SCK_PHASE);
+        system_clock_peripheral_disable(PERIPHERAL_SPI1_IF);
+        system_clock_peripheral_disable(PERIPHERAL_SPI1_CORE);
+    }
 }
 
 /**
@@ -133,54 +137,56 @@ static void _spi_clock_disable(struct spi_module *const module)
  * \retval STATUS_OK               If the configuration was written
  */
 static enum status_code _spi_set_config(
-		struct spi_module *const module,
-		const struct spi_config *const config)
+        struct spi_module *const module,
+        const struct spi_config *const config)
 {
-	Assert(module);
-	Assert(config);
+    Assert(module);
+    Assert(config);
 
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
-	module->mode  = config->mode;
+    module->mode  = config->mode;
 
 #if CONF_SPI_MASTER_ENABLE == true
-	/* Find baud value and write it */
-	if (config->mode == SPI_MODE_MASTER) {
-		spi_module->SPI_CLK_DIVIDER.reg = config->clock_divider;
-	}
+    /* Find baud value and write it */
+    if (config->mode == SPI_MODE_MASTER)
+    {
+        spi_module->SPI_CLK_DIVIDER.reg = config->clock_divider;
+    }
 #endif
 
-	/* Set data order */
-	if (config->data_order == SPI_DATA_ORDER_LSB) {
-		spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x1;
-	} else {
-		spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x0;
-	}
-
-	/* Set clock polarity and clock phase */
-	switch(config->transfer_mode)
-	{
-		case SPI_TRANSFER_MODE_0:
-			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
-			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
-			break;
-		case SPI_TRANSFER_MODE_1:
-			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
-			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
-			break;
-		case SPI_TRANSFER_MODE_2:
-			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
-			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
-			break;
-		case SPI_TRANSFER_MODE_3:
-			spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
-			spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
-			break;
-		default:
-			break;
-	}
-
-	return STATUS_OK;
+    /* Set data order */
+    if (config->data_order == SPI_DATA_ORDER_LSB)
+    {
+        spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x1;
+    } else {
+        spi_module->SPI_CONFIGURATION.bit.LSB_FIRST_ENABLE = 0x0;
+    }
+
+    /* Set clock polarity and clock phase */
+    switch(config->transfer_mode)
+    {
+        case SPI_TRANSFER_MODE_0:
+            spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
+            spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
+            break;
+        case SPI_TRANSFER_MODE_1:
+            spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
+            spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x0;
+            break;
+        case SPI_TRANSFER_MODE_2:
+            spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x0;
+            spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
+            break;
+        case SPI_TRANSFER_MODE_3:
+            spi_module->SPI_CONFIGURATION.bit.SCK_PHASE = 0x1;
+            spi_module->SPI_CONFIGURATION.bit.SCK_POLARITY = 0x1;
+            break;
+        default:
+            break;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -199,12 +205,12 @@ static enum status_code _spi_set_config(
  * \retval false  If the SPI master module has not shifted out data
  */
 static inline bool _spi_is_write_complete(
-		Spi *const spi_module)
+        Spi *const spi_module)
 {
-	Assert(spi_module);
+    Assert(spi_module);
 
-	/* Check interrupt flag */
-	return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_EMPTY);
+    /* Check interrupt flag */
+    return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_EMPTY);
 }
 
 
@@ -220,12 +226,12 @@ static inline bool _spi_is_write_complete(
  * \retval false  If the SPI module is not ready to write data
  */
 static inline bool _spi_is_ready_to_write(
-		Spi *const spi_module)
+        Spi *const spi_module)
 {
-	Assert(spi_module);
+    Assert(spi_module);
 
-	/* Check interrupt flag */
-	return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_NOT_FULL);
+    /* Check interrupt flag */
+    return (spi_module->TRANSMIT_STATUS.bit.TX_FIFO_NOT_FULL);
 }
 
 /**
@@ -240,12 +246,12 @@ static inline bool _spi_is_ready_to_write(
  * \retval false  If the SPI module is not ready to read data
  */
 static inline bool _spi_is_ready_to_read(
-		Spi *const spi_module)
+        Spi *const spi_module)
 {
-	Assert(spi_module);
+    Assert(spi_module);
 
-	/* Check interrupt flag */
-	return (spi_module->RECEIVE_STATUS.bit.RX_FIFO_NOT_EMPTY);
+    /* Check interrupt flag */
+    return (spi_module->RECEIVE_STATUS.bit.RX_FIFO_NOT_EMPTY);
 }
 
 /**
@@ -263,13 +269,13 @@ static inline bool _spi_is_ready_to_read(
  * \param[out] config  Configuration structure to initialize to default values
  */
 void spi_slave_inst_get_config_defaults(
-		struct spi_slave_inst_config *const config)
+        struct spi_slave_inst_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->ss_pin          = PIN_LP_GPIO_12;
-	config->address_enabled = false;
-	config->address         = 0;
+    config->ss_pin          = PIN_LP_GPIO_12;
+    config->address_enabled = false;
+    config->address         = 0;
 }
 
 /**
@@ -291,32 +297,32 @@ void spi_slave_inst_get_config_defaults(
  *  \li Baudrate 50000
  *  \li Default pinmux settings for all pads
  *  \li Clock source 0 (26MHz)
- *  \li	Clock divider  (Formula: baud_rate = ((clock input freq/clock_divider+1)/2))
+ *  \li Clock divider  (Formula: baud_rate = ((clock input freq/clock_divider+1)/2))
  *                                  (For Example: if clock source is CLOCK_INPUT_0 then
  *                                  ((26000000/(129+1))/2) = 100000 bps)
  *
  * \param[in,out] config  Configuration structure to initialize to default values
  */
 void spi_get_config_defaults(
-		struct spi_config *const config)
+        struct spi_config *const config)
 {
-	Assert(config);
-
-	config->mode             = SPI_MODE_MASTER;
-	config->data_order       = SPI_DATA_ORDER_MSB;
-	config->transfer_mode    = SPI_TRANSFER_MODE_0;
-	config->clock_source     = SPI_CLK_INPUT_0;
-	config->clock_divider    = 129;
-
-	config->pin_number_pad[0] = PIN_LP_GPIO_10;
-	config->pin_number_pad[1] = PIN_LP_GPIO_11;
-	config->pin_number_pad[2] = PIN_LP_GPIO_12;
-	config->pin_number_pad[3] = PIN_LP_GPIO_13;
-
-	config->pinmux_sel_pad[0] = MUX_LP_GPIO_10_SPI0_SCK;
-	config->pinmux_sel_pad[1] = MUX_LP_GPIO_11_SPI0_MOSI;
-	config->pinmux_sel_pad[2] = MUX_LP_GPIO_12_SPI0_SSN;
-	config->pinmux_sel_pad[3] = MUX_LP_GPIO_13_SPI0_MISO;
+    Assert(config);
+
+    config->mode             = SPI_MODE_MASTER;
+    config->data_order       = SPI_DATA_ORDER_MSB;
+    config->transfer_mode    = SPI_TRANSFER_MODE_0;
+    config->clock_source     = SPI_CLK_INPUT_0;
+    config->clock_divider    = 129;
+
+    config->pin_number_pad[0] = PIN_LP_GPIO_10;
+    config->pin_number_pad[1] = PIN_LP_GPIO_11;
+    config->pin_number_pad[2] = PIN_LP_GPIO_12;
+    config->pin_number_pad[3] = PIN_LP_GPIO_13;
+
+    config->pinmux_sel_pad[0] = MUX_LP_GPIO_10_SPI0_SCK;
+    config->pinmux_sel_pad[1] = MUX_LP_GPIO_11_SPI0_MOSI;
+    config->pinmux_sel_pad[2] = MUX_LP_GPIO_12_SPI0_SSN;
+    config->pinmux_sel_pad[3] = MUX_LP_GPIO_13_SPI0_MISO;
 };
 
 /**
@@ -331,22 +337,22 @@ void spi_get_config_defaults(
  *
  */
 void spi_attach_slave(
-		struct spi_slave_inst *const slave,
-		struct spi_slave_inst_config *const config)
+        struct spi_slave_inst *const slave,
+        struct spi_slave_inst_config *const config)
 {
-	Assert(slave);
-	Assert(config);
+    Assert(slave);
+    Assert(config);
 
-	slave->ss_pin          = config->ss_pin;
-	slave->address_enabled = config->address_enabled;
-	slave->address         = config->address;
+    slave->ss_pin          = config->ss_pin;
+    slave->address_enabled = config->address_enabled;
+    slave->address         = config->address;
 
-	struct gpio_config config_gpio;
-	gpio_get_config_defaults(&config_gpio);
-	config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
-	gpio_pin_set_config(slave->ss_pin, &config_gpio);
+    struct gpio_config config_gpio;
+    gpio_get_config_defaults(&config_gpio);
+    config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+    gpio_pin_set_config(slave->ss_pin, &config_gpio);
 
-	gpio_pin_set_output_level(slave->ss_pin, true);
+    gpio_pin_set_output_level(slave->ss_pin, true);
 }
 
 /**
@@ -359,20 +365,22 @@ void spi_attach_slave(
  */
 void spi_reset(struct spi_module *const module)
 {
-	/* Sanity check arguments */
-	Spi *const spi_module = (module->hw);
-
-	/* Disable the module */
-	spi_disable(module);
-
-	/* Software reset the module */
-	if(spi_module == (void *)SPI0) {
-		system_peripheral_reset(PERIPHERAL_SPI0_CORE);
-		system_peripheral_reset(PERIPHERAL_SPI0_IF);
-	} else if (spi_module == (void *)SPI1) {
-		system_peripheral_reset(PERIPHERAL_SPI1_CORE);
-		system_peripheral_reset(PERIPHERAL_SPI1_IF);
-	}
+    /* Sanity check arguments */
+    Spi *const spi_module = (module->hw);
+
+    /* Disable the module */
+    spi_disable(module);
+
+    /* Software reset the module */
+    if(spi_module == (void *)SPI0)
+    {
+        system_peripheral_reset(PERIPHERAL_SPI0_CORE);
+        system_peripheral_reset(PERIPHERAL_SPI0_IF);
+    } else if (spi_module == (void *)SPI1)
+    {
+        system_peripheral_reset(PERIPHERAL_SPI1_CORE);
+        system_peripheral_reset(PERIPHERAL_SPI1_IF);
+    }
 }
 
 /**
@@ -392,98 +400,108 @@ void spi_reset(struct spi_module *const module)
  * \retval STATUS_ERR_INVALID_ARG  If invalid argument(s) were provided
  */
 enum status_code spi_init(
-		struct spi_module *const module,
-		Spi *const hw,
-		const struct spi_config *const config)
+        struct spi_module *const module,
+        Spi *const hw,
+        const struct spi_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
 
-	uint8_t idx;
+    uint8_t idx;
 
-	/* Initialize device instance */
-	module->hw = hw;
+    /* Initialize device instance */
+    module->hw = hw;
 
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
-	/* Check if module is enabled. */
-	if (spi_module->SPI_MODULE_ENABLE.reg & SPI_MODULE_ENABLE_MASK) {
-		spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
-	}
+    /* Check if module is enabled. */
+    if (spi_module->SPI_MODULE_ENABLE.reg & SPI_MODULE_ENABLE_MASK)
+    {
+        spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
+    }
 
-	spi_reset(module);
-	_spi_clock_enable(module);
+    spi_reset(module);
+    _spi_clock_enable(module);
 
 #if SPI_CALLBACK_MODE == true
-	if (module->hw == SPI0) {
-		_spi_instances[0] = module;
-		system_register_isr(RAM_ISR_TABLE_SPIRX0_INDEX, (uint32_t)spi_rx0_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_SPITX0_INDEX, (uint32_t)spi_tx0_isr_handler);
-	} else if (module->hw == SPI1) {
-		_spi_instances[1] = module;
-		system_register_isr(RAM_ISR_TABLE_SPIRX1_INDEX, (uint32_t)spi_rx1_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_SPITX1_INDEX, (uint32_t)spi_tx1_isr_handler);
-	}
+    if (module->hw == SPI0)
+    {
+        _spi_instances[0] = module;
+        system_register_isr(RAM_ISR_TABLE_SPIRX0_INDEX, (uint32_t)spi_rx0_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_SPITX0_INDEX, (uint32_t)spi_tx0_isr_handler);
+    } else if (module->hw == SPI1)
+    {
+        _spi_instances[1] = module;
+        system_register_isr(RAM_ISR_TABLE_SPIRX1_INDEX, (uint32_t)spi_rx1_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_SPITX1_INDEX, (uint32_t)spi_tx1_isr_handler);
+    }
 #endif
 
-	//Program the pinmux.
-	struct gpio_config config_gpio;
-	gpio_get_config_defaults(&config_gpio);
-
-	/* Set the pinmux for this spi module. */
-	for(idx = 0; idx < 4; idx++) {
-		if (config->pin_number_pad[idx] != PINMUX_UNUSED) {
-			if (config->mode == SPI_MODE_MASTER) {
-				config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
-			} else if (config->mode == SPI_MODE_SLAVE) {
-				config_gpio.direction = GPIO_PIN_DIR_INPUT;
-			}
-			gpio_pin_set_config(config->pin_number_pad[idx], &config_gpio);
-			gpio_pinmux_cofiguration(config->pin_number_pad[idx], \
-						(uint16_t)(config->pinmux_sel_pad[idx]));
-		}
-	}
-
-	/* Set up the input clock for the module */
-	spi_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
+    /*Program the pinmux.*/
+    struct gpio_config config_gpio;
+    gpio_get_config_defaults(&config_gpio);
+
+    /* Set the pinmux for this spi module. */
+    for(idx = 0; idx < 4; idx++)
+    {
+        if (config->pin_number_pad[idx] != PINMUX_UNUSED)
+        {
+            if (config->mode == SPI_MODE_MASTER)
+            {
+                config_gpio.direction = GPIO_PIN_DIR_OUTPUT;
+            } else if (config->mode == SPI_MODE_SLAVE)
+            {
+                config_gpio.direction = GPIO_PIN_DIR_INPUT;
+            }
+            gpio_pin_set_config(config->pin_number_pad[idx], &config_gpio);
+            gpio_pinmux_cofiguration(config->pin_number_pad[idx], \
+                        (uint16_t)(config->pinmux_sel_pad[idx]));
+        }
+    }
+
+    /* Set up the input clock for the module */
+    spi_module->CLOCK_SOURCE_SELECT.reg = config->clock_source;
 
 #  if CONF_SPI_MASTER_ENABLE == true
-	if (config->mode == SPI_MODE_MASTER) {
-		/* Set the mode in SPI master mode */
-		spi_module->SPI_MASTER_MODE.reg = SPI_MODE_MASTER;
-	}
+    if (config->mode == SPI_MODE_MASTER)
+    {
+        /* Set the mode in SPI master mode */
+        spi_module->SPI_MASTER_MODE.reg = SPI_MODE_MASTER;
+    }
 #  endif
 
 #  if CONF_SPI_SLAVE_ENABLE == true
-	if (config->mode == SPI_MODE_SLAVE) {
-		/* Set the mode in SPI slave mode */
-		spi_module->SPI_MASTER_MODE.reg = SPI_MODE_SLAVE;
-	}
+    if (config->mode == SPI_MODE_SLAVE)
+    {
+        /* Set the mode in SPI slave mode */
+        spi_module->SPI_MASTER_MODE.reg = SPI_MODE_SLAVE;
+    }
 #  endif
 
 #if SPI_CALLBACK_MODE == true
-	/* Temporary variables */
-	uint8_t i;
-
-	/* Initialize parameters */
-	for (i = 0; i < SPI_CALLBACK_N; i++) {
-		module->callback[i]        = NULL;
-	}
-	module->tx_buffer_ptr              = NULL;
-	module->rx_buffer_ptr              = NULL;
-	module->remaining_tx_buffer_length = 0x0000;
-	module->remaining_rx_buffer_length = 0x0000;
-	module->registered_callback        = 0x00;
-	module->enabled_callback           = 0x00;
-	module->status                     = STATUS_OK;
-	module->dir                        = SPI_DIRECTION_IDLE;
-	module->locked                     = 0;
+    /* Temporary variables */
+    uint8_t i;
+
+    /* Initialize parameters */
+    for (i = 0; i < SPI_CALLBACK_N; i++)
+    {
+        module->callback[i]        = NULL;
+    }
+    module->tx_buffer_ptr              = NULL;
+    module->rx_buffer_ptr              = NULL;
+    module->remaining_tx_buffer_length = 0x0000;
+    module->remaining_rx_buffer_length = 0x0000;
+    module->registered_callback        = 0x00;
+    module->enabled_callback           = 0x00;
+    module->status                     = STATUS_OK;
+    module->dir                        = SPI_DIRECTION_IDLE;
+    module->locked                     = 0;
 #endif
 
-	/* Write configuration to module and return status code */
-	return _spi_set_config(module, config);
+    /* Write configuration to module and return status code */
+    return _spi_set_config(module, config);
 }
 
 /**
@@ -500,20 +518,22 @@ enum status_code spi_init(
  */
 void spi_enable(struct spi_module *const module)
 {
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
 #if SPI_CALLBACK_MODE == true
-	if(spi_module == SPI0) {
-		NVIC_EnableIRQ(SPI0_RX_IRQn);
-		NVIC_EnableIRQ(SPI0_TX_IRQn);
-	} else if(spi_module == SPI1) {
-		NVIC_EnableIRQ(SPI1_RX_IRQn);
-		NVIC_EnableIRQ(SPI1_TX_IRQn);
-	}
+    if(spi_module == SPI0)
+    {
+        NVIC_EnableIRQ(SPI0_RX_IRQn);
+        NVIC_EnableIRQ(SPI0_TX_IRQn);
+    } else if(spi_module == SPI1)
+    {
+        NVIC_EnableIRQ(SPI1_RX_IRQn);
+        NVIC_EnableIRQ(SPI1_TX_IRQn);
+    }
 #endif
 
-	/* Enable SPI */
-	spi_module->SPI_MODULE_ENABLE.reg = SPI_MODULE_ENABLE_ENABLE;
+    /* Enable SPI */
+    spi_module->SPI_MODULE_ENABLE.reg = SPI_MODULE_ENABLE_ENABLE;
 }
 
 /**
@@ -525,21 +545,23 @@ void spi_enable(struct spi_module *const module)
  */
 void spi_disable(struct spi_module *const module)
 {
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
 #  if SPI_CALLBACK_MODE == true
-	if(spi_module == SPI0) {
-		NVIC_DisableIRQ(SPI0_RX_IRQn);
-		NVIC_DisableIRQ(SPI0_TX_IRQn);
-	} else if(spi_module == SPI1) {
-		NVIC_DisableIRQ(SPI1_RX_IRQn);
-		NVIC_DisableIRQ(SPI1_TX_IRQn);
-	}
+    if(spi_module == SPI0)
+    {
+        NVIC_DisableIRQ(SPI0_RX_IRQn);
+        NVIC_DisableIRQ(SPI0_TX_IRQn);
+    } else if(spi_module == SPI1)
+    {
+        NVIC_DisableIRQ(SPI1_RX_IRQn);
+        NVIC_DisableIRQ(SPI1_TX_IRQn);
+    }
 #  endif
 
-	/* Disable SPI */
-	spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
-	_spi_clock_disable(module);
+    /* Disable SPI */
+    spi_module->SPI_MODULE_ENABLE.reg = (0x0ul << SPI_MODULE_ENABLE_ENABLE_Pos);
+    _spi_clock_disable(module);
 }
 
 /**
@@ -559,16 +581,17 @@ void spi_disable(struct spi_module *const module)
  */
 enum status_code spi_lock(struct spi_module *const module)
 {
-	enum status_code status;
+    enum status_code status;
 
-	if (module->locked) {
-		status = STATUS_BUSY;
-	} else {
-		module->locked = true;
-		status = STATUS_OK;
-	}
+    if (module->locked)
+    {
+        status = STATUS_BUSY;
+    } else {
+        module->locked = true;
+        status = STATUS_OK;
+    }
 
-	return status;
+    return status;
 }
 
 /**
@@ -584,7 +607,7 @@ enum status_code spi_lock(struct spi_module *const module)
  */
 void spi_unlock(struct spi_module *const module)
 {
-	module->locked = false;
+    module->locked = false;
 }
 
 /**
@@ -610,22 +633,23 @@ void spi_unlock(struct spi_module *const module)
  */
 enum status_code spi_write(struct spi_module *module, uint8_t tx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
-	/* Check if the data register has been copied to the shift register */
-	if (!_spi_is_ready_to_write(spi_module)) {
-		/* Data register has not been copied to the shift register, return */
-		return STATUS_BUSY;
-	}
+    /* Check if the data register has been copied to the shift register */
+    if (!_spi_is_ready_to_write(spi_module))
+    {
+        /* Data register has not been copied to the shift register, return */
+        return STATUS_BUSY;
+    }
 
-	/* Write the character to the DATA register */
-	spi_module->TRANSMIT_DATA.reg = tx_data & SPI_TRANSMIT_DATA_MASK;
+    /* Write the character to the DATA register */
+    spi_module->TRANSMIT_DATA.reg = tx_data & SPI_TRANSMIT_DATA_MASK;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -645,33 +669,35 @@ enum status_code spi_write(struct spi_module *module, uint8_t tx_data)
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 enum status_code spi_read(
-		struct spi_module *const module,
-		uint8_t *rx_data)
+        struct spi_module *const module,
+        uint8_t *rx_data)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	Spi *const spi_module = (module->hw);
+    Spi *const spi_module = (module->hw);
 
-	/* Check if data is ready to be read */
-	if (!_spi_is_ready_to_read(spi_module)) {
-		/* No data has been received, return */
-		return STATUS_ERR_IO;
-	}
+    /* Check if data is ready to be read */
+    if (!_spi_is_ready_to_read(spi_module))
+    {
+        /* No data has been received, return */
+        return STATUS_ERR_IO;
+    }
 
-	/* Return value */
-	enum status_code retval = STATUS_OK;
+    /* Return value */
+    enum status_code retval = STATUS_OK;
 
-	/* Check if data is overflown */
-	if (spi_module->RECEIVE_STATUS.bit.FIFO_OVERRUN) {
-		retval = STATUS_ERR_OVERFLOW;
-	}
+    /* Check if data is overflown */
+    if (spi_module->RECEIVE_STATUS.bit.FIFO_OVERRUN)
+    {
+        retval = STATUS_ERR_OVERFLOW;
+    }
 
-	/* Read the character from the DATA register */
-	*rx_data = ((uint8_t)spi_module->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
+    /* Read the character from the DATA register */
+    *rx_data = ((uint8_t)spi_module->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
 
-	return retval;
+    return retval;
 }
 
 /**
@@ -694,63 +720,70 @@ enum status_code spi_read(
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 enum status_code spi_transceive_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Spi *spi_module = module->hw;
-	uint8_t dummy = 0;
-	uint8_t skip_mosi = 0;
-	uint8_t skip_miso = 0;
-	uint8_t status;
-	uint16_t transfer_len = 0;
-
-	if(spi_module == 0) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-	if(!tx_data) {
-		tx_data = &dummy;
-		*tx_data = module->tx_dummy_byte;
-		skip_mosi = 1;
-	} else if(!rx_data) {
-		rx_data = &dummy;
-		skip_miso = 1;
-	} else if(length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check for Idle */
-	do {
-		status = _spi_is_active(spi_module);
-	}while(status);
-
-	/* Clear all status registers */
-	spi_module->RECEIVE_STATUS.reg;
-	spi_module->TRANSMIT_STATUS.reg;
-
-	/* Start transfer */
-	while(transfer_len < length) {
-		/* Write data to MOSI */
-		while(!_spi_is_ready_to_write(spi_module));
-		spi_module->TRANSMIT_DATA.reg = *tx_data;
-		/* Read data shifted from MISO */
-		while(!_spi_is_ready_to_read(spi_module));
-		*rx_data = spi_module->RECEIVE_DATA.reg;
-		transfer_len++;
-		if (!skip_mosi) {
-			tx_data++;
-		}
-		if (!skip_miso) {
-			rx_data++;
-		}
-	}
-	/* check TXFIFO is empty */
-	do {
-		status = _spi_is_write_complete(spi_module);
-	}while(!status);
-
-	return STATUS_OK;
+    Spi *spi_module = module->hw;
+    uint8_t dummy = 0;
+    uint8_t skip_mosi = 0;
+    uint8_t skip_miso = 0;
+    uint8_t status;
+    uint16_t transfer_len = 0;
+
+    if(spi_module == 0)
+    {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+    if(!tx_data)
+    {
+        tx_data = &dummy;
+        *tx_data = module->tx_dummy_byte;
+        skip_mosi = 1;
+    } else if(!rx_data)
+    {
+        rx_data = &dummy;
+        skip_miso = 1;
+    } else if(length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check for Idle */
+    do {
+        status = _spi_is_active(spi_module);
+    }while(status);
+
+    /* Clear all status registers */
+    spi_module->RECEIVE_STATUS.reg;
+    spi_module->TRANSMIT_STATUS.reg;
+
+    /* Start transfer */
+    while(transfer_len < length)
+    {
+        /* Write data to MOSI */
+        while(!_spi_is_ready_to_write(spi_module));
+        spi_module->TRANSMIT_DATA.reg = *tx_data;
+        /* Read data shifted from MISO */
+        while(!_spi_is_ready_to_read(spi_module));
+        *rx_data = spi_module->RECEIVE_DATA.reg;
+        transfer_len++;
+        if (!skip_mosi)
+        {
+            tx_data++;
+        }
+        if (!skip_miso)
+        {
+            rx_data++;
+        }
+    }
+    /* check TXFIFO is empty */
+    do {
+        status = _spi_is_write_complete(spi_module);
+    }while(!status);
+
+    return STATUS_OK;
 
 }
 
@@ -773,11 +806,11 @@ enum status_code spi_transceive_buffer_wait(
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 enum status_code spi_transceive_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data)
 {
-	return spi_transceive_buffer_wait(module, tx_data, rx_data, 1);
+    return spi_transceive_buffer_wait(module, tx_data, rx_data, 1);
 }
 
 /**
@@ -800,13 +833,13 @@ enum status_code spi_transceive_wait(
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 enum status_code spi_read_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint8_t dummy)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint8_t dummy)
 {
-	module->tx_dummy_byte = dummy;
-	return spi_transceive_buffer_wait(module, NULL, rx_data, length);
+    module->tx_dummy_byte = dummy;
+    return spi_transceive_buffer_wait(module, NULL, rx_data, length);
 }
 
 /**
@@ -827,11 +860,11 @@ enum status_code spi_read_buffer_wait(
  * \retval STATUS_ERR_OVERFLOW  If the data is overflown
  */
 enum status_code spi_write_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	return spi_transceive_buffer_wait(module, tx_data, NULL, length);
+    return spi_transceive_buffer_wait(module, tx_data, NULL, length);
 }
 
 /**
@@ -849,18 +882,19 @@ enum status_code spi_write_buffer_wait(
  * \retval STATUS_ERR_INVALID_ARG   Invalid SS pin
  */
 enum status_code spi_select_slave(
-		struct spi_module *const module,
-		struct spi_slave_inst *const slave,
-		bool select)
+        struct spi_module *const module,
+        struct spi_slave_inst *const slave,
+        bool select)
 {
-	uint8_t gpio_num = slave->ss_pin;
-	if(select) {
-		/* ASSERT Slave select pin */
-		gpio_pin_set_output_level(gpio_num, false);
-	} else {
-		/* DEASSERT Slave select pin */
-		gpio_pin_set_output_level(gpio_num, true);
-	}
-
-	return STATUS_OK;
+    uint8_t gpio_num = slave->ss_pin;
+    if(select)
+    {
+        /* ASSERT Slave select pin */
+        gpio_pin_set_output_level(gpio_num, false);
+    } else {
+        /* DEASSERT Slave select pin */
+        gpio_pin_set_output_level(gpio_num, true);
+    }
+
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h
index 943a4a8f845f..a1bdd7b36bb0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi.h
@@ -50,9 +50,9 @@
 /**
  * \defgroup asfdoc_samb_drivers_spi_group SAM Serial Peripheral Interface (SPI) Driver
  *
- * This driver for Atmel&reg; | SMART ARM-based microcontrollers provides 
- * an interface for the configuration and management of the module in 
- * its SPI mode to transfer SPI data frames. The following driver API modes 
+ * This driver for Atmel&reg; | SMART ARM-based microcontrollers provides
+ * an interface for the configuration and management of the module in
+ * its SPI mode to transfer SPI data frames. The following driver API modes
  * are covered by this manual:
  *
  * - Polled APIs
@@ -243,17 +243,17 @@ typedef void (*spi_callback_t)(struct spi_module *const module);
  *
  */
 enum spi_callback {
-	/** Callback for buffer transmitted */
-	SPI_CALLBACK_BUFFER_TRANSMITTED,
-	/** Callback for buffer received */
-	SPI_CALLBACK_BUFFER_RECEIVED,
-	/** Callback for buffers transceived */
-	SPI_CALLBACK_BUFFER_TRANSCEIVED,
-	/** Callback for error */
-	SPI_CALLBACK_ERROR,
+    /** Callback for buffer transmitted */
+    SPI_CALLBACK_BUFFER_TRANSMITTED,
+    /** Callback for buffer received */
+    SPI_CALLBACK_BUFFER_RECEIVED,
+    /** Callback for buffers transceived */
+    SPI_CALLBACK_BUFFER_TRANSCEIVED,
+    /** Callback for error */
+    SPI_CALLBACK_ERROR,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	SPI_CALLBACK_N,
+    /** Number of available callbacks */
+    SPI_CALLBACK_N,
 #  endif
 };
 
@@ -268,14 +268,14 @@ extern void spi_tx1_isr_handler(void);
  * \brief SPI transfer directions
  */
 enum _spi_direction {
-	/** Transfer direction is read. */
-	SPI_DIRECTION_READ,
-	/** Transfer direction is write. */
-	SPI_DIRECTION_WRITE,
-	/** Transfer direction is read and write. */
-	SPI_DIRECTION_BOTH,
-	/** No transfer. */
-	SPI_DIRECTION_IDLE,
+    /** Transfer direction is read. */
+    SPI_DIRECTION_READ,
+    /** Transfer direction is write. */
+    SPI_DIRECTION_WRITE,
+    /** Transfer direction is read and write. */
+    SPI_DIRECTION_BOTH,
+    /** No transfer. */
+    SPI_DIRECTION_IDLE,
 };
 #  endif
 #  endif
@@ -286,15 +286,15 @@ enum _spi_direction {
  * SPI transfer mode.
  */
 enum spi_transfer_mode {
-	/** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
-	SPI_TRANSFER_MODE_0 = 0,
-	/** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
-	SPI_TRANSFER_MODE_1 = SPI_CONFIGURATION_SCK_PHASE_1,
-	/** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
-	SPI_TRANSFER_MODE_2 = SPI_CONFIGURATION_SCK_POLARITY_1,
-	/** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
-	SPI_TRANSFER_MODE_3 = SPI_CONFIGURATION_SCK_PHASE_1 | \
-						SPI_CONFIGURATION_SCK_POLARITY_1,
+    /** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */
+    SPI_TRANSFER_MODE_0 = 0,
+    /** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */
+    SPI_TRANSFER_MODE_1 = SPI_CONFIGURATION_SCK_PHASE_1,
+    /** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */
+    SPI_TRANSFER_MODE_2 = SPI_CONFIGURATION_SCK_POLARITY_1,
+    /** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */
+    SPI_TRANSFER_MODE_3 = SPI_CONFIGURATION_SCK_PHASE_1 | \
+                        SPI_CONFIGURATION_SCK_POLARITY_1,
 };
 
 /**
@@ -303,10 +303,10 @@ enum spi_transfer_mode {
  * SPI mode selection.
  */
 enum spi_mode {
-	/** Master mode */
-	SPI_MODE_MASTER         = 1,
-	/** Slave mode */
-	SPI_MODE_SLAVE          = 0,
+    /** Master mode */
+    SPI_MODE_MASTER         = 1,
+    /** Slave mode */
+    SPI_MODE_SLAVE          = 0,
 };
 
 /**
@@ -316,10 +316,10 @@ enum spi_mode {
  *
  */
 enum spi_data_order {
-	/** The MSB of the data is transmitted first */
-	SPI_DATA_ORDER_MSB      = 0,
-	/** The LSB of the data is transmitted first */
-	SPI_DATA_ORDER_LSB      = SPI_CONFIGURATION_LSB_FIRST_ENABLE_1,
+    /** The MSB of the data is transmitted first */
+    SPI_DATA_ORDER_MSB      = 0,
+    /** The LSB of the data is transmitted first */
+    SPI_DATA_ORDER_LSB      = SPI_CONFIGURATION_LSB_FIRST_ENABLE_1,
 };
 
 /**
@@ -329,14 +329,14 @@ enum spi_data_order {
  *
  */
 enum spi_clock_input {
-	/** source from clock input 0 26MHz*/
-	SPI_CLK_INPUT_0 = 0,
-	/** source from clock input 1 13MHz */
-	SPI_CLK_INPUT_1,
-	/** source from clock input 2 6.5MHz*/
-	SPI_CLK_INPUT_2,
-	/** source from clock input 3 3MHz*/
-	SPI_CLK_INPUT_3,
+    /** source from clock input 0 26MHz*/
+    SPI_CLK_INPUT_0 = 0,
+    /** source from clock input 1 13MHz */
+    SPI_CLK_INPUT_1,
+    /** source from clock input 2 6.5MHz*/
+    SPI_CLK_INPUT_2,
+    /** source from clock input 3 3MHz*/
+    SPI_CLK_INPUT_3,
 };
 
 /**
@@ -350,36 +350,36 @@ enum spi_clock_input {
  */
 struct spi_module {
 #  if !defined(__DOXYGEN__)
-	/** Hardware module */
-	Spi *hw;
-	/** Module lock */
-	volatile uint8_t locked;
-	/** SPI mode */
-	enum spi_mode mode;
-	/** Transmit dummy data when receiving*/
-	uint8_t tx_dummy_byte;
+    /** Hardware module */
+    Spi *hw;
+    /** Module lock */
+    volatile uint8_t locked;
+    /** SPI mode */
+    enum spi_mode mode;
+    /** Transmit dummy data when receiving*/
+    uint8_t tx_dummy_byte;
 #if SPI_CALLBACK_MODE == true
-	/** Direction of transaction */
-	volatile enum _spi_direction dir;
-	/** Array to store callback function pointers in */
-	spi_callback_t callback[SPI_CALLBACK_N];
-	/** Buffer pointer to where the next received character will be put */
-	volatile uint8_t *rx_buffer_ptr;
-	/** Buffer pointer to where the next character will be transmitted from
-	**/
-	volatile uint8_t *tx_buffer_ptr;
-	/** Remaining characters to receive */
-	volatile uint16_t remaining_rx_buffer_length;
-	/** Remaining dummy characters to send when reading */
-	volatile uint16_t remaining_dummy_buffer_length;
-	/** Remaining characters to transmit */
-	volatile uint16_t remaining_tx_buffer_length;
-	/** Bit mask for callbacks registered */
-	uint8_t registered_callback;
-	/** Bit mask for callbacks enabled */
-	uint8_t enabled_callback;
-	/** Holds the status of the ongoing or last operation */
-	volatile enum status_code status;
+    /** Direction of transaction */
+    volatile enum _spi_direction dir;
+    /** Array to store callback function pointers in */
+    spi_callback_t callback[SPI_CALLBACK_N];
+    /** Buffer pointer to where the next received character will be put */
+    volatile uint8_t *rx_buffer_ptr;
+    /** Buffer pointer to where the next character will be transmitted from
+    **/
+    volatile uint8_t *tx_buffer_ptr;
+    /** Remaining characters to receive */
+    volatile uint16_t remaining_rx_buffer_length;
+    /** Remaining dummy characters to send when reading */
+    volatile uint16_t remaining_dummy_buffer_length;
+    /** Remaining characters to transmit */
+    volatile uint16_t remaining_tx_buffer_length;
+    /** Bit mask for callbacks registered */
+    uint8_t registered_callback;
+    /** Bit mask for callbacks enabled */
+    uint8_t enabled_callback;
+    /** Holds the status of the ongoing or last operation */
+    volatile enum status_code status;
 #  endif
 #  endif
 };
@@ -392,12 +392,12 @@ struct spi_module {
  * \ref spi_select_slave.
  */
 struct spi_slave_inst {
-	/** Pin to use as Slave Select */
-	uint8_t ss_pin;
-	/** Address recognition enabled in slave device */
-	uint8_t address_enabled;
-	/** Address of slave device */
-	uint8_t address;
+    /** Pin to use as Slave Select */
+    uint8_t ss_pin;
+    /** Address recognition enabled in slave device */
+    uint8_t address_enabled;
+    /** Address of slave device */
+    uint8_t address;
 };
 
 /**
@@ -406,12 +406,12 @@ struct spi_slave_inst {
  * SPI Peripheral slave configuration structure
  */
 struct spi_slave_inst_config {
-	/** Pin to use as Slave Select */
-	uint8_t ss_pin;
-	/** Enable address */
-	bool address_enabled;
-	/** Address of slave */
-	uint8_t address;
+    /** Pin to use as Slave Select */
+    uint8_t ss_pin;
+    /** Enable address */
+    bool address_enabled;
+    /** Address of slave */
+    uint8_t address;
 };
 
 /**
@@ -422,20 +422,20 @@ struct spi_slave_inst_config {
  * modified by the user application.
  */
 struct spi_config {
-	/** SPI mode */
-	enum spi_mode mode;
-	/** Data order */
-	enum spi_data_order data_order;
-	/** Transfer mode */
-	enum spi_transfer_mode transfer_mode;
-	/** clock source to use */
-	enum spi_clock_input clock_source;
-	/** clock divider value to use*/
-	uint8_t clock_divider;
-	/** SPI PAD pin number */
-	uint32_t pin_number_pad[4];
-	/** SPI PAD pinmux selection */
-	uint32_t pinmux_sel_pad[4];
+    /** SPI mode */
+    enum spi_mode mode;
+    /** Data order */
+    enum spi_data_order data_order;
+    /** Transfer mode */
+    enum spi_transfer_mode transfer_mode;
+    /** clock source to use */
+    enum spi_clock_input clock_source;
+    /** clock divider value to use*/
+    uint8_t clock_divider;
+    /** SPI PAD pin number */
+    uint32_t pin_number_pad[4];
+    /** SPI PAD pinmux selection */
+    uint32_t pinmux_sel_pad[4];
 };
 
 /**
@@ -444,20 +444,20 @@ struct spi_config {
  */
 
 enum status_code spi_init(
-		struct spi_module *const module,
-		Spi *const hw,
-		const struct spi_config *const config);
+        struct spi_module *const module,
+        Spi *const hw,
+        const struct spi_config *const config);
 
 void spi_reset(struct spi_module *const module);
 
 void spi_slave_inst_get_config_defaults(
-		struct spi_slave_inst_config *const config);
+        struct spi_slave_inst_config *const config);
 
 void spi_get_config_defaults(struct spi_config *const config);
 
 void spi_attach_slave(
-		struct spi_slave_inst *const slave,
-		struct spi_slave_inst_config *const config);
+        struct spi_slave_inst *const slave,
+        struct spi_slave_inst_config *const config);
 
 /** @} */
 
@@ -488,39 +488,39 @@ void spi_unlock(struct spi_module *const module);
  */
 
 enum status_code spi_write(
-		struct spi_module *module,
-		uint8_t tx_data);
+        struct spi_module *module,
+        uint8_t tx_data);
 
 enum status_code spi_write_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length);
 
 enum status_code spi_read(
-		struct spi_module *const module,
-		uint8_t *rx_data);
+        struct spi_module *const module,
+        uint8_t *rx_data);
 
 enum status_code spi_read_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint8_t dummy);
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint8_t dummy);
 
 enum status_code spi_transceive_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data);
 
 enum status_code spi_transceive_buffer_wait(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length);
 
 enum status_code spi_select_slave(
-		struct spi_module *const module,
-		struct spi_slave_inst *const slave,
-		bool select);
+        struct spi_module *const module,
+        struct spi_slave_inst *const slave,
+        bool select);
 
 /** @} */
 
@@ -537,30 +537,30 @@ enum status_code spi_select_slave(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>SPI</td>
- *		<td>Serial Peripheral Interface</td>
- *	</tr>
- *	<tr>
- *		<td>SCK</td>
- *		<td>Serial Clock</td>
- *	</tr>
- *	<tr>
- *		<td>MOSI</td>
- *		<td>Master Output Slave Input</td>
- *	</tr>
- *	<tr>
- *		<td>MISO</td>
- *		<td>Master Input Slave Output</td>
- *	</tr>
- *	<tr>
- *		<td>SS</td>
- *		<td>Slave Select</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SPI</td>
+ *      <td>Serial Peripheral Interface</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SCK</td>
+ *      <td>Serial Clock</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MOSI</td>
+ *      <td>Master Output Slave Input</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MISO</td>
+ *      <td>Master Input Slave Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SS</td>
+ *      <td>Slave Select</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_drivers_spi_extra_dependencies Dependencies
@@ -577,12 +577,12 @@ enum status_code spi_select_slave(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -602,24 +602,24 @@ enum status_code spi_select_slave(
  * - \subpage asfdoc_samb_spi_slave_callback_use
  * \endif
  */
- 
+
  /**
  *
  * \page asfdoc_samb_drivers_spi_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
-#endif //SPI_H_INCLUDED
+#endif /*SPI_H_INCLUDED*/
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c
index 238980d333fd..e311feb36290 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.c
@@ -62,21 +62,21 @@ static bool flag_direction_both[SPI_INST_NUM];
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_write(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Spi *const spi_hw = module->hw;
+    /* Pointer to the hardware module instance */
+    Spi *const spi_hw = module->hw;
 
-	/* Write value will be at least 8-bits long */
-	uint16_t data_to_send = *(module->tx_buffer_ptr);
-	/* Increment 8-bit pointer */
-	(module->tx_buffer_ptr)++;
+    /* Write value will be at least 8-bits long */
+    uint16_t data_to_send = *(module->tx_buffer_ptr);
+    /* Increment 8-bit pointer */
+    (module->tx_buffer_ptr)++;
 
-	/* Write the data to send*/
-	spi_hw->TRANSMIT_DATA.reg = data_to_send & SPI_TRANSMIT_DATA_MASK;
+    /* Write the data to send*/
+    spi_hw->TRANSMIT_DATA.reg = data_to_send & SPI_TRANSMIT_DATA_MASK;
 
-	/* Decrement remaining buffer length */
-	(module->remaining_tx_buffer_length)--;
+    /* Decrement remaining buffer length */
+    (module->remaining_tx_buffer_length)--;
 }
 
 /**
@@ -86,20 +86,20 @@ static void _spi_write(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_read(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Spi *const spi_hw = module->hw;
+    /* Pointer to the hardware module instance */
+    Spi *const spi_hw = module->hw;
 
-	uint16_t received_data = (spi_hw->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
+    uint16_t received_data = (spi_hw->RECEIVE_DATA.reg & SPI_RECEIVE_DATA_MASK);
 
-	/* Read value will be at least 8-bits long */
-	*(module->rx_buffer_ptr) = received_data;
-	/* Increment 8-bit pointer */
-	module->rx_buffer_ptr += 1;
+    /* Read value will be at least 8-bits long */
+    *(module->rx_buffer_ptr) = received_data;
+    /* Increment 8-bit pointer */
+    module->rx_buffer_ptr += 1;
 
-	/* Decrement length of the remaining buffer */
-	module->remaining_rx_buffer_length--;
+    /* Decrement length of the remaining buffer */
+    module->remaining_rx_buffer_length--;
 }
 
 #if CONF_SPI_MASTER_ENABLE == true
@@ -110,16 +110,16 @@ static void _spi_read(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_write_dummy(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Spi *const spi_hw = module->hw;
+    /* Pointer to the hardware module instance */
+    Spi *const spi_hw = module->hw;
 
-	/* Write dummy byte */
-	spi_hw->TRANSMIT_DATA.reg = dummy_write;
+    /* Write dummy byte */
+    spi_hw->TRANSMIT_DATA.reg = dummy_write;
 
-	/* Decrement remaining dummy buffer length */
-	module->remaining_dummy_buffer_length--;
+    /* Decrement remaining dummy buffer length */
+    module->remaining_dummy_buffer_length--;
 }
 #endif
 
@@ -130,305 +130,352 @@ static void _spi_write_dummy(
  * \param[in,out]  module  Pointer to SPI software instance struct
  */
 static void _spi_read_dummy(
-		struct spi_module *const module)
+        struct spi_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Spi *const spi_hw = module->hw;
-	uint16_t flush = 0;
+    /* Pointer to the hardware module instance */
+    Spi *const spi_hw = module->hw;
+    uint16_t flush = 0;
 
-	/* Read dummy byte */
-	flush = spi_hw->RECEIVE_DATA.reg;
-	UNUSED(flush);
+    /* Read dummy byte */
+    flush = spi_hw->RECEIVE_DATA.reg;
+    UNUSED(flush);
 
-	/* Decrement remaining dummy buffer length */
-	module->remaining_dummy_buffer_length--;
+    /* Decrement remaining dummy buffer length */
+    module->remaining_dummy_buffer_length--;
 }
 
 void spi_rx0_isr_handler(void)
 {
-	struct spi_module *module = _spi_instances[0];
-
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
-	flags &= module->hw->RX_INTERRUPT_MASK.reg;
-
-	if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN) {
-			if (module->dir != SPI_DIRECTION_WRITE) {
-				/* Store the error code */
-				module->status = STATUS_ERR_OVERFLOW;
-
-				/* End transaction */
-				module->dir = SPI_DIRECTION_IDLE;
-
-				module->hw->RX_INTERRUPT_MASK.reg &=
-					~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
-					SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-				/* Run callback if registered and enabled */
-				if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
-					(module->registered_callback & (1 << SPI_CALLBACK_ERROR))) {
-					module->status = STATUS_ERR_OVERFLOW;
-					module->hw->RX_INTERRUPT_MASK.reg &=
-							~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
-					(module->callback[SPI_CALLBACK_ERROR])(module);
-				}
-			}
-			/* Flush */
-			uint16_t flush = module->hw->RECEIVE_DATA.reg;
-			UNUSED(flush);
-		} else {
-			if (module->dir == SPI_DIRECTION_WRITE) {
-				/* Flush receive buffer when writing */
-				_spi_read_dummy(module);
-				if (module->remaining_dummy_buffer_length == 0) {
-					module->hw->RX_INTERRUPT_MASK.reg &=
-						~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
-					module->status = STATUS_OK;
-					module->dir = SPI_DIRECTION_IDLE;
-					///* Run callback if registered and enabled */
-					//if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
-						//(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
-						//(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
-					//}
-				}
-			} else {
-				_spi_read(module);
-				if (module->remaining_rx_buffer_length == 0) {
-					if(module->dir == SPI_DIRECTION_READ) {
-						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
-							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED))) {
-							module->status = STATUS_OK;
-							module->hw->RX_INTERRUPT_MASK.reg &=
-									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
-						}
-					} else if (module->dir == SPI_DIRECTION_BOTH) {
-						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
-							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
-								module->hw->RX_INTERRUPT_MASK.reg &=
-										~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-								if (flag_direction_both[0]) {
-									module->status = STATUS_OK;
-									flag_direction_both[0] = false;
-									(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
-								} else {
-									flag_direction_both[0] = true;
-								}
-						}
-					}
-				}
-			}
-		}
-	}
+    struct spi_module *module = _spi_instances[0];
+
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+    flags &= module->hw->RX_INTERRUPT_MASK.reg;
+
+    if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN)
+        {
+            if (module->dir != SPI_DIRECTION_WRITE)
+            {
+                /* Store the error code */
+                module->status = STATUS_ERR_OVERFLOW;
+
+                /* End transaction */
+                module->dir = SPI_DIRECTION_IDLE;
+
+                module->hw->RX_INTERRUPT_MASK.reg &=
+                    ~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+                    SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                /* Run callback if registered and enabled */
+                if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
+                    (module->registered_callback & (1 << SPI_CALLBACK_ERROR)))
+                    {
+                    module->status = STATUS_ERR_OVERFLOW;
+                    module->hw->RX_INTERRUPT_MASK.reg &=
+                            ~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
+                    (module->callback[SPI_CALLBACK_ERROR])(module);
+                }
+            }
+            /* Flush */
+            uint16_t flush = module->hw->RECEIVE_DATA.reg;
+            UNUSED(flush);
+        } else {
+            if (module->dir == SPI_DIRECTION_WRITE)
+            {
+                /* Flush receive buffer when writing */
+                _spi_read_dummy(module);
+                if (module->remaining_dummy_buffer_length == 0)
+                {
+                    module->hw->RX_INTERRUPT_MASK.reg &=
+                        ~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
+                    module->status = STATUS_OK;
+                    module->dir = SPI_DIRECTION_IDLE;
+                    /*/* Run callback if registered and enabled */
+                    /*if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&*/
+                        /*(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)))*/
+                        {
+                        /*(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);*/
+                    /*}*/
+                }
+            } else {
+                _spi_read(module);
+                if (module->remaining_rx_buffer_length == 0)
+                {
+                    if(module->dir == SPI_DIRECTION_READ)
+                    {
+                        if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
+                            (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)))
+                            {
+                            module->status = STATUS_OK;
+                            module->hw->RX_INTERRUPT_MASK.reg &=
+                                    ~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                            (module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+                        }
+                    } else if (module->dir == SPI_DIRECTION_BOTH)
+                    {
+                        if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+                            (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)))
+                            {
+                                module->hw->RX_INTERRUPT_MASK.reg &=
+                                        ~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                                if (flag_direction_both[0])
+                                {
+                                    module->status = STATUS_OK;
+                                    flag_direction_both[0] = false;
+                                    (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+                                } else {
+                                    flag_direction_both[0] = true;
+                                }
+                        }
+                    }
+                }
+            }
+        }
+    }
 }
 
 void spi_tx0_isr_handler(void)
 {
-	struct spi_module *module = _spi_instances[0];
+    struct spi_module *module = _spi_instances[0];
 
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
-	flags &= module->hw->TX_INTERRUPT_MASK.reg;
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+    flags &= module->hw->TX_INTERRUPT_MASK.reg;
 
-	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1) {
+    if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1)
+    {
 #  if CONF_SPI_MASTER_ENABLE == true
-		if ((module->mode == SPI_MODE_MASTER) &&
-			(module->dir == SPI_DIRECTION_READ)) {
-			/* Send dummy byte when reading in master mode */
-			_spi_write_dummy(module);
-			if (module->remaining_dummy_buffer_length == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				module->hw->TX_INTERRUPT_MASK.reg &=
-					~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-			}
-		}
+        if ((module->mode == SPI_MODE_MASTER) &&
+            (module->dir == SPI_DIRECTION_READ))
+            {
+            /* Send dummy byte when reading in master mode */
+            _spi_write_dummy(module);
+            if (module->remaining_dummy_buffer_length == 0)
+            {
+                /* Disable the Data Register Empty Interrupt */
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                    ~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+            }
+        }
 #  endif
-		if (0
+        if (0
 #  if CONF_SPI_MASTER_ENABLE == true
-		|| ((module->mode == SPI_MODE_MASTER) &&
-		(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_MASTER) &&
+        (module->dir != SPI_DIRECTION_READ))
 #  endif
 #  if CONF_SPI_SLAVE_ENABLE == true
-		|| ((module->mode == SPI_MODE_SLAVE) &&
-		(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_SLAVE) &&
+        (module->dir != SPI_DIRECTION_READ))
 #  endif
-		) {
-			_spi_write(module);
-			if (module->remaining_tx_buffer_length == 0) {
-				module->hw->TX_INTERRUPT_MASK.reg &=
-						~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-				module->hw->TX_INTERRUPT_MASK.reg |=
-						SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-			}
-		}
-	}
-	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
-		if (module->dir == SPI_DIRECTION_WRITE) {
-			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
-				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
-					module->status = STATUS_OK;
-					/* Disable interrupt */
-					module->hw->TX_INTERRUPT_MASK.reg &=
-							~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-					(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
-				}
-		} else if (module->dir == SPI_DIRECTION_BOTH) {
-			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
-				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
-					/* Disable interrupt */
-					module->hw->TX_INTERRUPT_MASK.reg &=
-							~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-					if (flag_direction_both[0]) {
-						module->status = STATUS_OK;
-						flag_direction_both[0] = false;
-						(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
-					} else {
-						flag_direction_both[0] = true;
-					}
-			}
-		}
-	}
+        )
+        {
+            _spi_write(module);
+            if (module->remaining_tx_buffer_length == 0)
+            {
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                        ~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+                module->hw->TX_INTERRUPT_MASK.reg |=
+                        SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+            }
+        }
+    }
+    if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY)
+    {
+        if (module->dir == SPI_DIRECTION_WRITE)
+        {
+            if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
+                (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)))
+                {
+                    module->status = STATUS_OK;
+                    /* Disable interrupt */
+                    module->hw->TX_INTERRUPT_MASK.reg &=
+                            ~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+                    (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+                }
+        } else if (module->dir == SPI_DIRECTION_BOTH)
+        {
+            if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+                (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)))
+                {
+                    /* Disable interrupt */
+                    module->hw->TX_INTERRUPT_MASK.reg &=
+                            ~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+                    if (flag_direction_both[0])
+                    {
+                        module->status = STATUS_OK;
+                        flag_direction_both[0] = false;
+                        (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+                    } else {
+                        flag_direction_both[0] = true;
+                    }
+            }
+        }
+    }
 }
 
 void spi_rx1_isr_handler(void)
 {
-	struct spi_module *module = _spi_instances[1];
-
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
-	flags &= module->hw->RX_INTERRUPT_MASK.reg;
-
-	if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN) {
-			if (module->dir != SPI_DIRECTION_WRITE) {
-				/* Store the error code */
-				module->status = STATUS_ERR_OVERFLOW;
-
-				/* End transaction */
-				module->dir = SPI_DIRECTION_IDLE;
-
-				module->hw->RX_INTERRUPT_MASK.reg &=
-						~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
-						SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-				/* Run callback if registered and enabled */
-				if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
-					(module->registered_callback & (1 << SPI_CALLBACK_ERROR))) {
-					module->status = STATUS_ERR_OVERFLOW;
-					module->hw->RX_INTERRUPT_MASK.reg &=
-							~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
-					(module->callback[SPI_CALLBACK_ERROR])(module);
-				}
-			}
-			/* Flush */
-			uint16_t flush = module->hw->RECEIVE_DATA.reg;
-			UNUSED(flush);
-		} else {
-			if (module->dir == SPI_DIRECTION_WRITE) {
-				/* Flush receive buffer when writing */
-				_spi_read_dummy(module);
-				if (module->remaining_dummy_buffer_length == 0) {
-					module->hw->RX_INTERRUPT_MASK.reg &=
-							~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
-					module->status = STATUS_OK;
-					module->dir = SPI_DIRECTION_IDLE;
-				}
-			} else {
-				_spi_read(module);
-				if (module->remaining_rx_buffer_length == 0) {
-					if(module->dir == SPI_DIRECTION_READ) {
-						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
-							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED))) {
-							module->status = STATUS_OK;
-							module->hw->RX_INTERRUPT_MASK.reg &=
-									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-							(module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
-						}
-					} else if (module->dir == SPI_DIRECTION_BOTH) {
-						if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
-							(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
-							module->hw->RX_INTERRUPT_MASK.reg &=
-									~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-							if (flag_direction_both[1]) {
-								module->status = STATUS_OK;
-								flag_direction_both[1] = false;
-								(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
-							} else {
-								flag_direction_both[1] = true;
-							}
-						}
-					}
-				}
-			}
-		}
-	}
+    struct spi_module *module = _spi_instances[1];
+
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+    flags &= module->hw->RX_INTERRUPT_MASK.reg;
+
+    if (flags & SPI_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        if (module->hw->RECEIVE_STATUS.reg & SPI_RECEIVE_STATUS_FIFO_OVERRUN)
+        {
+            if (module->dir != SPI_DIRECTION_WRITE)
+            {
+                /* Store the error code */
+                module->status = STATUS_ERR_OVERFLOW;
+
+                /* End transaction */
+                module->dir = SPI_DIRECTION_IDLE;
+
+                module->hw->RX_INTERRUPT_MASK.reg &=
+                        ~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+                        SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                /* Run callback if registered and enabled */
+                if ((module->enabled_callback & (1 << SPI_CALLBACK_ERROR)) &&
+                    (module->registered_callback & (1 << SPI_CALLBACK_ERROR)))
+                    {
+                    module->status = STATUS_ERR_OVERFLOW;
+                    module->hw->RX_INTERRUPT_MASK.reg &=
+                            ~(SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK);
+                    (module->callback[SPI_CALLBACK_ERROR])(module);
+                }
+            }
+            /* Flush */
+            uint16_t flush = module->hw->RECEIVE_DATA.reg;
+            UNUSED(flush);
+        } else {
+            if (module->dir == SPI_DIRECTION_WRITE)
+            {
+                /* Flush receive buffer when writing */
+                _spi_read_dummy(module);
+                if (module->remaining_dummy_buffer_length == 0)
+                {
+                    module->hw->RX_INTERRUPT_MASK.reg &=
+                            ~SPI_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK;
+                    module->status = STATUS_OK;
+                    module->dir = SPI_DIRECTION_IDLE;
+                }
+            } else {
+                _spi_read(module);
+                if (module->remaining_rx_buffer_length == 0)
+                {
+                    if(module->dir == SPI_DIRECTION_READ)
+                    {
+                        if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) &&
+                            (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_RECEIVED)))
+                            {
+                            module->status = STATUS_OK;
+                            module->hw->RX_INTERRUPT_MASK.reg &=
+                                    ~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                            (module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module);
+                        }
+                    } else if (module->dir == SPI_DIRECTION_BOTH)
+                    {
+                        if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+                            (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)))
+                            {
+                            module->hw->RX_INTERRUPT_MASK.reg &=
+                                    ~(SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                            if (flag_direction_both[1])
+                            {
+                                module->status = STATUS_OK;
+                                flag_direction_both[1] = false;
+                                (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+                            } else {
+                                flag_direction_both[1] = true;
+                            }
+                        }
+                    }
+                }
+            }
+        }
+    }
 }
 
 void spi_tx1_isr_handler(void)
 {
-	struct spi_module *module = _spi_instances[1];
+    struct spi_module *module = _spi_instances[1];
 
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
-	flags &= module->hw->TX_INTERRUPT_MASK.reg;
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+    flags &= module->hw->TX_INTERRUPT_MASK.reg;
 
-	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1) {
+    if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_NOT_FULL_1)
+    {
 #  if CONF_SPI_MASTER_ENABLE == true
-		if ((module->mode == SPI_MODE_MASTER) &&
-		(module->dir == SPI_DIRECTION_READ)) {
-			/* Send dummy byte when reading in master mode */
-			_spi_write_dummy(module);
-			if (module->remaining_dummy_buffer_length == 0) {
-				/* Disable the Data Register Empty Interrupt */
-				module->hw->TX_INTERRUPT_MASK.reg &=
-				~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-			}
-		}
+        if ((module->mode == SPI_MODE_MASTER) &&
+        (module->dir == SPI_DIRECTION_READ))
+        {
+            /* Send dummy byte when reading in master mode */
+            _spi_write_dummy(module);
+            if (module->remaining_dummy_buffer_length == 0)
+            {
+                /* Disable the Data Register Empty Interrupt */
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                ~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+            }
+        }
 #  endif
-		if (0
+        if (0
 #  if CONF_SPI_MASTER_ENABLE == true
-		|| ((module->mode == SPI_MODE_MASTER) &&
-		(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_MASTER) &&
+        (module->dir != SPI_DIRECTION_READ))
 #  endif
 #  if CONF_SPI_SLAVE_ENABLE == true
-		|| ((module->mode == SPI_MODE_SLAVE) &&
-		(module->dir != SPI_DIRECTION_READ))
+        || ((module->mode == SPI_MODE_SLAVE) &&
+        (module->dir != SPI_DIRECTION_READ))
 #  endif
-		) {
-			_spi_write(module);
-			if (module->remaining_tx_buffer_length == 0) {
-				module->hw->TX_INTERRUPT_MASK.reg &=
-						~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-				module->hw->TX_INTERRUPT_MASK.reg |=
-				SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-			}
-		}
-	}
-	if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
-		if (module->dir == SPI_DIRECTION_WRITE) {
-			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
-			(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED))) {
-				module->status = STATUS_OK;
-				/* Disable interrupt */
-				module->hw->TX_INTERRUPT_MASK.reg &=
-						~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-				(module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
-			}
-		} else if (module->dir == SPI_DIRECTION_BOTH) {
-			if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
-				(module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED))) {
-				/* Disable interrupt */
-				module->hw->TX_INTERRUPT_MASK.reg &=
-						~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-				if (flag_direction_both[1]) {
-					module->status = STATUS_OK;
-					flag_direction_both[1] = false;
-					(module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
-				} else {
-					flag_direction_both[1] = true;
-				}
-			}
-		}
-	}
+        )
+        {
+            _spi_write(module);
+            if (module->remaining_tx_buffer_length == 0)
+            {
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                        ~SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+                module->hw->TX_INTERRUPT_MASK.reg |=
+                SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+            }
+        }
+    }
+    if (flags & SPI_TRANSMIT_STATUS_TX_FIFO_EMPTY)
+    {
+        if (module->dir == SPI_DIRECTION_WRITE)
+        {
+            if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)) &&
+            (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)))
+            {
+                module->status = STATUS_OK;
+                /* Disable interrupt */
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                        ~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+                (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module);
+            }
+        } else if (module->dir == SPI_DIRECTION_BOTH)
+        {
+            if ((module->enabled_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) &&
+                (module->registered_callback & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)))
+                {
+                /* Disable interrupt */
+                module->hw->TX_INTERRUPT_MASK.reg &=
+                        ~SPI_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+                if (flag_direction_both[1])
+                {
+                    module->status = STATUS_OK;
+                    flag_direction_both[1] = false;
+                    (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module);
+                } else {
+                    flag_direction_both[1] = true;
+                }
+            }
+        }
+    }
 }
 
 /**
@@ -446,19 +493,19 @@ void spi_tx1_isr_handler(void)
  *
  */
 void spi_register_callback(
-		struct spi_module *const module,
-		spi_callback_t callback_func,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        spi_callback_t callback_func,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->registered_callback |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->registered_callback |= (1 << callback_type);
 }
 
 /**
@@ -471,17 +518,17 @@ void spi_register_callback(
  *
  */
 void spi_unregister_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type)
+        struct spi_module *const module,
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->registered_callback &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->registered_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -495,13 +542,13 @@ void spi_unregister_callback(
  * \param[in]  callback_type  Callback type given by an enum
  */
 void spi_enable_callback(struct spi_module *const module,
-		enum spi_callback callback_type)
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->enabled_callback |= (1 << callback_type);
+    /* Enable callback */
+    module->enabled_callback |= (1 << callback_type);
 }
 
 /**
@@ -514,13 +561,13 @@ void spi_enable_callback(struct spi_module *const module,
  * \param[in]  callback_type  Callback type given by an enum
  */
 void spi_disable_callback(struct spi_module *const module,
-		enum spi_callback callback_type)
+        enum spi_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->enabled_callback &= ~(1 << callback_type);
+    /* Enable callback */
+    module->enabled_callback &= ~(1 << callback_type);
 }
 
 /**
@@ -533,25 +580,25 @@ void spi_disable_callback(struct spi_module *const module,
  *
  */
 static void _spi_write_buffer(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-	module->remaining_dummy_buffer_length = length;
-	module->tx_buffer_ptr = tx_data;
-	module->status = STATUS_BUSY;
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
+    module->remaining_dummy_buffer_length = length;
+    module->tx_buffer_ptr = tx_data;
+    module->status = STATUS_BUSY;
 
-	module->dir = SPI_DIRECTION_WRITE;
+    module->dir = SPI_DIRECTION_WRITE;
 
-	/* Get a pointer to the hardware module instance */
-	Spi *const hw = module->hw;
+    /* Get a pointer to the hardware module instance */
+    Spi *const hw = module->hw;
 
-	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+    hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
 }
 
 /**
@@ -564,29 +611,29 @@ static void _spi_write_buffer(
  *
  */
 static void _spi_read_buffer(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(rx_data);
+    Assert(module);
+    Assert(rx_data);
 
-	/* Set length for the buffer and the pointer, and let
-	 * the interrupt handler do the rest */
-	module->remaining_rx_buffer_length = length;
-	module->remaining_dummy_buffer_length = length;
-	module->rx_buffer_ptr = rx_data;
-	module->status = STATUS_BUSY;
+    /* Set length for the buffer and the pointer, and let
+     * the interrupt handler do the rest */
+    module->remaining_rx_buffer_length = length;
+    module->remaining_dummy_buffer_length = length;
+    module->rx_buffer_ptr = rx_data;
+    module->status = STATUS_BUSY;
 
-	module->dir = SPI_DIRECTION_READ;
+    module->dir = SPI_DIRECTION_READ;
 
-	/* Get a pointer to the hardware module instance */
-	Spi *const hw = module->hw;
+    /* Get a pointer to the hardware module instance */
+    Spi *const hw = module->hw;
 
-	hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+    hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
 
 #if CONF_SPI_MASTER_ENABLE == true
-	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+    hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
 #endif
 }
 
@@ -601,35 +648,37 @@ static void _spi_read_buffer(
  *
  */
 static void _spi_transceive_buffer(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
-
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-	module->remaining_rx_buffer_length = length;
-	module->rx_buffer_ptr = rx_data;
-	module->tx_buffer_ptr = tx_data;
-	module->status = STATUS_BUSY;
-
-	module->dir = SPI_DIRECTION_BOTH;
-
-	if (module->hw == SPI0) {
-		flag_direction_both[0] = false;
-	} else if (module->hw == SPI1) {
-		flag_direction_both[1] = false;
-	}
-
-	/* Get a pointer to the hardware module instance */
-	Spi *const hw = module->hw;
-
-	/* Enable the Data Register Empty and RX Complete Interrupt */
-	hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-	hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+    Assert(module);
+    Assert(tx_data);
+
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
+    module->remaining_rx_buffer_length = length;
+    module->rx_buffer_ptr = rx_data;
+    module->tx_buffer_ptr = tx_data;
+    module->status = STATUS_BUSY;
+
+    module->dir = SPI_DIRECTION_BOTH;
+
+    if (module->hw == SPI0)
+    {
+        flag_direction_both[0] = false;
+    } else if (module->hw == SPI1)
+    {
+        flag_direction_both[1] = false;
+    }
+
+    /* Get a pointer to the hardware module instance */
+    Spi *const hw = module->hw;
+
+    /* Enable the Data Register Empty and RX Complete Interrupt */
+    hw->TX_INTERRUPT_MASK.reg = SPI_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+    hw->RX_INTERRUPT_MASK.reg = SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
 }
 
 /**
@@ -649,26 +698,28 @@ static void _spi_transceive_buffer(
  * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
  */
 enum status_code spi_write_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Issue internal write */
-	_spi_write_buffer(module, tx_data, length);
+    /* Issue internal write */
+    _spi_write_buffer(module, tx_data, length);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -693,28 +744,30 @@ enum status_code spi_write_buffer_job(
  * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
  */
 enum status_code spi_read_buffer_job(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy)
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	dummy_write = dummy;
-	/* Issue internal read */
-	_spi_read_buffer(module, rx_data, length);
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    dummy_write = dummy;
+    /* Issue internal read */
+    _spi_read_buffer(module, rx_data, length);
+    return STATUS_OK;
 }
 
 /**
@@ -739,26 +792,28 @@ enum status_code spi_read_buffer_job(
  * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
  */
 enum status_code spi_transceive_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Check if the SPI is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if the SPI is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Issue internal transceive */
-	_spi_transceive_buffer(module, tx_data, rx_data, length);
+    /* Issue internal transceive */
+    _spi_transceive_buffer(module, tx_data, rx_data, length);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h
index 82dbb339fcb7..4db45194fda8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi/spi_callback.h
@@ -64,21 +64,21 @@ extern "C" {
  * @{
  */
 void spi_register_callback(
-		struct spi_module *const module,
-		spi_callback_t callback_func,
-		enum spi_callback callback_type);
+        struct spi_module *const module,
+        spi_callback_t callback_func,
+        enum spi_callback callback_type);
 
 void spi_unregister_callback(
-		struct spi_module *module,
-		enum spi_callback callback_type);
+        struct spi_module *module,
+        enum spi_callback callback_type);
 
 void spi_enable_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type);
+        struct spi_module *const module,
+        enum spi_callback callback_type);
 
 void spi_disable_callback(
-		struct spi_module *const module,
-		enum spi_callback callback_type);
+        struct spi_module *const module,
+        enum spi_callback callback_type);
 /** @} */
 
 /**
@@ -86,19 +86,19 @@ void spi_disable_callback(
  * @{
  */
 enum status_code spi_write_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint16_t length);
 enum status_code spi_read_buffer_job(
-		struct spi_module *const module,
-		uint8_t *rx_data,
-		uint16_t length,
-		uint16_t dummy);
+        struct spi_module *const module,
+        uint8_t *rx_data,
+        uint16_t length,
+        uint16_t dummy);
 enum status_code spi_transceive_buffer_job(
-		struct spi_module *const module,
-		uint8_t *tx_data,
-		uint8_t *rx_data,
-		uint16_t length);
+        struct spi_module *const module,
+        uint8_t *tx_data,
+        uint8_t *rx_data,
+        uint16_t length);
 /** @} */
 
 /** @} */
@@ -106,5 +106,5 @@ enum status_code spi_transceive_buffer_job(
 }
 #endif
 
-#endif	//SPI_H_INCLUDED
+#endif  /*SPI_H_INCLUDED*/
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c
index 0524e2e1ae6b..3faf95b2533c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.c
@@ -52,19 +52,20 @@
  */
 static void spi_flash_write_enable(void)
 {
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_ENABLE;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_RESETVALUE;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
-
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_ENABLE;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_RESETVALUE;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
@@ -74,19 +75,20 @@ static void spi_flash_write_enable(void)
  */
 static void spi_flash_write_disable(void)
 {
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_DISABLE;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_MASK;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
-
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_WRITE_DISABLE;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = SPI_FLASH_DMA_START_ADDRESS_MASK;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
@@ -98,23 +100,24 @@ static void spi_flash_write_disable(void)
  */
 static uint8_t spi_flash_read_status_reg(void)
 {
-	volatile uint32_t status_value;
+    volatile uint32_t status_value;
 
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x01);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_STATUS;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&status_value;
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x01);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_STATUS;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&status_value;
 
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
 
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 
-	return (status_value & 0xFF);
+    return (status_value & 0xFF);
 }
 
 /**
@@ -128,39 +131,41 @@ static uint8_t spi_flash_read_status_reg(void)
  */
 static void spi_flash_page_program(uint32_t flash_addr, uint32_t memory_addr, uint16_t size)
 {
-	unsigned char cmd[8];
-
-	spi_flash_write_enable();
-
-	cmd[0] = SPI_FLASH_CMD_PAGE_PROGRAM;
-	cmd[1] = (unsigned char) (flash_addr >> 16);
-	cmd[2] = (unsigned char) (flash_addr >> 8);
-	cmd[3] = (unsigned char) (flash_addr);
-
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
-	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04) | \
-			SPI_FLASH_TRANSACTION_CTRL_WDATA_COUNT(size);
-
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
-
-	/* add additional read_status_reg before the while this gives the flash
-	 * memory time to update the registers.
-	 */
-	for(uint16_t i = 0; i < 0xFFFF; i++) {
-		/* Waiting... */
-	}
-	//spi_flash_read_status_reg();
-	while(spi_flash_read_status_reg() & 0x01);
-	spi_flash_write_disable();
+    unsigned char cmd[8];
+
+    spi_flash_write_enable();
+
+    cmd[0] = SPI_FLASH_CMD_PAGE_PROGRAM;
+    cmd[1] = (unsigned char) (flash_addr >> 16);
+    cmd[2] = (unsigned char) (flash_addr >> 8);
+    cmd[3] = (unsigned char) (flash_addr);
+
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+    SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04) | \
+            SPI_FLASH_TRANSACTION_CTRL_WDATA_COUNT(size);
+
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
+
+    /* add additional read_status_reg before the while this gives the flash
+     * memory time to update the registers.
+     */
+    for(uint16_t i = 0; i < 0xFFFF; i++)
+    {
+        /* Waiting... */
+    }
+    /*spi_flash_read_status_reg();*/
+    while(spi_flash_read_status_reg() & 0x01);
+    spi_flash_write_disable();
 }
 
 /**
@@ -170,15 +175,15 @@ static void spi_flash_page_program(uint32_t flash_addr, uint32_t memory_addr, ui
  */
 void spi_flash_init(void)
 {
-	/* PINMUX init */
-	LPMCU_MISC_REGS0->PINMUX_SEL_3.reg = \
-							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_0_SEL_SPI_FLASH0_SCK | \ 
-							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_1_SEL_SPI_FLASH0_TXD | \
-							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_2_SEL_SPI_FLASH0_SSN | \
-							LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_3_SEL_SPI_FLASH0_RXD;
-
-	SPI_FLASH0->MODE_CTRL.reg = SPI_FLASH_MODE_CTRL_RESETVALUE;
-	spi_flash_leave_low_power_mode();
+    /* PINMUX init */
+    LPMCU_MISC_REGS0->PINMUX_SEL_3.reg = \
+                            LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_0_SEL_SPI_FLASH0_SCK | \
+                            LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_1_SEL_SPI_FLASH0_TXD | \
+                            LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_2_SEL_SPI_FLASH0_SSN | \
+                            LPMCU_MISC_REGS_PINMUX_SEL_3_LP_SIP_3_SEL_SPI_FLASH0_RXD;
+
+    SPI_FLASH0->MODE_CTRL.reg = SPI_FLASH_MODE_CTRL_RESETVALUE;
+    spi_flash_leave_low_power_mode();
 }
 
 /**
@@ -188,23 +193,24 @@ void spi_flash_init(void)
  */
 uint32_t spi_flash_rdid(void)
 {
-	volatile uint32_t register_value;
+    volatile uint32_t register_value;
 
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x04);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_ID;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&register_value;
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x04);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_READ_ID;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = (uint32_t)&register_value;
 
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
 
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 
-	return (register_value);
+    return (register_value);
 }
 
 /**
@@ -217,45 +223,49 @@ uint32_t spi_flash_rdid(void)
  */
 void spi_flash_read(uint8_t *read_buf, uint32_t flash_addr, uint32_t size)
 {
-	uint8_t   cmd[8] = {0, };
-	uint32_t  memory_addr;
-	uint32_t  i=0;
-	uint8_t   *data = read_buf;
-
-	/* Get the destination buffer Address. */
-	if((flash_addr + size) > FLASH_MEMORY_SIZE) {
-		for(i=0; i < size; i++) {
-			data[i] = 0;
-		}
-	}
-
-	memory_addr = (unsigned long)read_buf;
-
-	/* Perform read operation. */
-	cmd[0] = SPI_FLASH_CMD_READ_HIGH_SPEED;
-	cmd[1] = (unsigned char) (flash_addr >> 16);
-	cmd[2] = (unsigned char) (flash_addr >> 8);
-	cmd[3] = (unsigned char) (flash_addr);
-	cmd[4] = 0xA5;
-
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(size);
-	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
-	SPI_FLASH0->CMD_BUFFER1.reg = cmd[4];
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_READ;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x05);
-
-	for (i = 0; i < 0xFF; i++) {
-		/* Waiting...*/
-	}
-	while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
-			(spi_flash_read_status_reg() & 0x01)){
-		/* Wait for current flash transaction done. */
-	}
+    uint8_t   cmd[8] = {0, };
+    uint32_t  memory_addr;
+    uint32_t  i=0;
+    uint8_t   *data = read_buf;
+
+    /* Get the destination buffer Address. */
+    if((flash_addr + size) > FLASH_MEMORY_SIZE)
+    {
+        for(i=0; i < size; i++)
+        {
+            data[i] = 0;
+        }
+    }
+
+    memory_addr = (unsigned long)read_buf;
+
+    /* Perform read operation. */
+    cmd[0] = SPI_FLASH_CMD_READ_HIGH_SPEED;
+    cmd[1] = (unsigned char) (flash_addr >> 16);
+    cmd[2] = (unsigned char) (flash_addr >> 8);
+    cmd[3] = (unsigned char) (flash_addr);
+    cmd[4] = 0xA5;
+
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(size);
+    SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+    SPI_FLASH0->CMD_BUFFER1.reg = cmd[4];
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_READ;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = memory_addr;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x05);
+
+    for (i = 0; i < 0xFF; i++)
+    {
+        /* Waiting...*/
+    }
+    while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
+            (spi_flash_read_status_reg() & 0x01))
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
@@ -269,48 +279,53 @@ void spi_flash_read(uint8_t *read_buf, uint32_t flash_addr, uint32_t size)
  */
 int8_t spi_flash_write(void *write_buf, uint32_t flash_addr, uint32_t size)
 {
-	int8_t      ret = -1;
-	uint32_t    write_size;
-	uint32_t    offset;
-	uint32_t    memory_addr;
-
-	for (uint32_t i = 0; i < 0x1FFFF; i++) {
-		/* Waiting...*/
-	}
-	if((write_buf != NULL) && (size != 0)) {
-		/* Ensure the write size does not exceed the flash limit. */
-		if((flash_addr + size) <= FLASH_MEMORY_SIZE) {
-			/* Get the destination buffer Address. */
-			memory_addr = (unsigned long)write_buf;
-			/* Perform read operation. */
-			offset = flash_addr % FLASH_PAGE_SIZE;
-
-			/* First part of data in the address page. */
-			if (offset) {
-				write_size = FLASH_PAGE_SIZE - offset;
-				spi_flash_page_program(flash_addr, memory_addr, min(size, write_size));
-				if (size < write_size) {
-					ret = 0;
-					goto EXIT;
-				}
-				memory_addr += write_size;
-				flash_addr += write_size;
-				size -= write_size;
-			}
-			do {
-				write_size = min(size, FLASH_PAGE_SIZE);
-
-				/* Write complete page or the remaining data. */
-				spi_flash_page_program(flash_addr, memory_addr, write_size);
-				memory_addr += write_size;
-				flash_addr += write_size;
-				size -= write_size;
-			} while (size > 0);
-			ret = 0;
-		}
-	}
-	EXIT:
-	return ret;
+    int8_t      ret = -1;
+    uint32_t    write_size;
+    uint32_t    offset;
+    uint32_t    memory_addr;
+
+    for (uint32_t i = 0; i < 0x1FFFF; i++)
+    {
+        /* Waiting...*/
+    }
+    if((write_buf != NULL) && (size != 0))
+    {
+        /* Ensure the write size does not exceed the flash limit. */
+        if((flash_addr + size) <= FLASH_MEMORY_SIZE)
+        {
+            /* Get the destination buffer Address. */
+            memory_addr = (unsigned long)write_buf;
+            /* Perform read operation. */
+            offset = flash_addr % FLASH_PAGE_SIZE;
+
+            /* First part of data in the address page. */
+            if (offset)
+            {
+                write_size = FLASH_PAGE_SIZE - offset;
+                spi_flash_page_program(flash_addr, memory_addr, min(size, write_size));
+                if (size < write_size)
+                {
+                    ret = 0;
+                    goto EXIT;
+                }
+                memory_addr += write_size;
+                flash_addr += write_size;
+                size -= write_size;
+            }
+            do {
+                write_size = min(size, FLASH_PAGE_SIZE);
+
+                /* Write complete page or the remaining data. */
+                spi_flash_page_program(flash_addr, memory_addr, write_size);
+                memory_addr += write_size;
+                flash_addr += write_size;
+                size -= write_size;
+            } while (size > 0);
+            ret = 0;
+        }
+    }
+    EXIT:
+    return ret;
 }
 
 /**
@@ -321,35 +336,37 @@ int8_t spi_flash_write(void *write_buf, uint32_t flash_addr, uint32_t size)
  */
 void spi_flash_sector_erase(uint32_t flash_addr)
 {
-	uint8_t cmd[8] = {0,};
-	uint32_t  i=0;
-
-	cmd[0] = SPI_FLASH_CMD_SECTOR_ERASE;
-	cmd[1] = (char)(flash_addr >> 16);
-	cmd[2] = (char)(flash_addr >> 8);
-	cmd[3] = (char)(flash_addr);
-
-	spi_flash_write_enable();
-	spi_flash_read_status_reg();
-
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
-	SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04);
-
-	for (i = 0; i < 0xFF; i++) {
-		/* Waiting...*/
-	}
-
-	while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
-			(spi_flash_read_status_reg() & 0x01)){
-		/* Wait for current flash transaction done. */
-	}
+    uint8_t cmd[8] = {0,};
+    uint32_t  i=0;
+
+    cmd[0] = SPI_FLASH_CMD_SECTOR_ERASE;
+    cmd[1] = (char)(flash_addr >> 16);
+    cmd[2] = (char)(flash_addr >> 8);
+    cmd[3] = (char)(flash_addr);
+
+    spi_flash_write_enable();
+    spi_flash_read_status_reg();
+
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+    SPI_FLASH0->CMD_BUFFER0.reg = cmd[0] | (cmd[1] << 8) | (cmd[2] << 16) | (cmd[3] << 24);
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_PRO;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x04);
+
+    for (i = 0; i < 0xFF; i++)
+    {
+        /* Waiting...*/
+    }
+
+    while ((SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) && \
+            (spi_flash_read_status_reg() & 0x01))
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
@@ -368,7 +385,8 @@ unsigned char spi_flash_erase(uint32_t start_offset, uint32_t size)
 
 
     /* Check address overflow */
-    if (end_offset > FLASH_MEMORY_SIZE) {
+    if (end_offset > FLASH_MEMORY_SIZE)
+    {
         return 1;
     }
 
@@ -377,15 +395,17 @@ unsigned char spi_flash_erase(uint32_t start_offset, uint32_t size)
 
     /* Erase next sectors */
     spi_flash_write_enable();
-    while(start_offset < end_offset) {
-			spi_flash_sector_erase(start_offset);
-			while(spi_flash_read_status_reg() & 0x01) {
-				/* Waiting. */
-			}
-			start_offset += FLASH_SECTOR_SIZE;
+    while(start_offset < end_offset)
+    {
+            spi_flash_sector_erase(start_offset);
+            while(spi_flash_read_status_reg() & 0x01)
+            {
+                /* Waiting. */
+            }
+            start_offset += FLASH_SECTOR_SIZE;
     }
 
-	spi_flash_write_disable();
+    spi_flash_write_disable();
 
     return 0;
 }
@@ -397,19 +417,20 @@ unsigned char spi_flash_erase(uint32_t start_offset, uint32_t size)
  */
 void spi_flash_enter_low_power_mode(void)
 {
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_ENTER_LOW_POWER;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
-
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_ENTER_LOW_POWER;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
@@ -419,33 +440,34 @@ void spi_flash_enter_low_power_mode(void)
  */
 void spi_flash_leave_low_power_mode(void)
 {
-	SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
-	SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_LEAVE_LOW_POWER;
-	SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
-	SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
-
-	SPI_FLASH0->TRANSACTION_CTRL.reg = \
-			SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
-			SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
-
-	while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
-			SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE) {
-		/* Wait for current flash transaction done. */
-	}
+    SPI_FLASH0->READ_CTRL.reg = SPI_FLASH_READ_CTRL_RDATA_COUNT(0x0);
+    SPI_FLASH0->CMD_BUFFER0.reg = SPI_FLASH_CMD_LEAVE_LOW_POWER;
+    SPI_FLASH0->DIRECTION.reg = SPI_FLASH_DIRECTION_CMD;
+    SPI_FLASH0->DMA_START_ADDRESS.reg = 0x0;
+
+    SPI_FLASH0->TRANSACTION_CTRL.reg = \
+            SPI_FLASH_TRANSACTION_CTRL_FLASH_TRANS_START | \
+            SPI_FLASH_TRANSACTION_CTRL_CMD_COUNT(0x01);
+
+    while (SPI_FLASH0->IRQ_STATUS.bit.FLASH_TRANS_DONE != \
+            SPI_FLASH_IRQ_STATUS_FLASH_TRANS_DONE)
+            {
+        /* Wait for current flash transaction done. */
+    }
 }
 
 /**
  * \brief Initializes the SPI Flash module
  */
 void spi_flash_clock_init(void)
-{	
-	/* Reset SPI_Flash */
-	system_peripheral_reset(PERIPHERAL_SPI_FLASH);
-	system_peripheral_reset(PERIPHERAL_SPI_FLASH_IF);
-	/* SPI_Flash core clock enable */
-	system_clock_peripheral_enable(PERIPHERAL_SPI_FLASH);
-	/* change clock speed */
-	system_clock_peripheral_freq_config(PERIPHERAL_SPI_FLASH, CLOCK_FREQ_13_MHZ);
+{
+    /* Reset SPI_Flash */
+    system_peripheral_reset(PERIPHERAL_SPI_FLASH);
+    system_peripheral_reset(PERIPHERAL_SPI_FLASH_IF);
+    /* SPI_Flash core clock enable */
+    system_clock_peripheral_enable(PERIPHERAL_SPI_FLASH);
+    /* change clock speed */
+    system_clock_peripheral_freq_config(PERIPHERAL_SPI_FLASH, CLOCK_FREQ_13_MHZ);
 }
 
 /**
@@ -458,9 +480,9 @@ void spi_flash_clock_init(void)
  */
 void spi_flash_turn_off(void)
 {
-	LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
-	
-	LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = 0x0;
+    LPMCU_MISC_REGS0->PULL_ENABLE.reg &= ~LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
+
+    LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = 0x0;
 }
 
 /**
@@ -471,7 +493,7 @@ void spi_flash_turn_off(void)
  */
 void spi_flash_turn_on(void)
 {
-	LPMCU_MISC_REGS0->PULL_ENABLE.reg |= LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
-	
-	LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = LPMCU_MISC_REGS_SPIFLASH_VDDIO_CTRL_ENABLE;
-}
\ No newline at end of file
+    LPMCU_MISC_REGS0->PULL_ENABLE.reg |= LPMCU_MISC_REGS_PULL_ENABLE_LP_SIP__Msk;
+
+    LPMCU_MISC_REGS0->SPIFLASH_VDDIO_CTRL.reg = LPMCU_MISC_REGS_SPIFLASH_VDDIO_CTRL_ENABLE;
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h
index 7b2258583e34..a29318cb0f08 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/spi_flash/spi_flash.h
@@ -228,14 +228,14 @@ void spi_flash_turn_on(void);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>SPI Flash</td>
- *		<td>Serial Peripheral Interface Flash</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>SPI Flash</td>
+ *      <td>Serial Peripheral Interface Flash</td>
+ *  </tr>
  * </table>
  *
  *
@@ -254,12 +254,12 @@ void spi_flash_turn_on(void);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -277,16 +277,16 @@ void spi_flash_turn_on(void);
  * \page asfdoc_samb_spi_flash_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c
index fdb392ef1626..a1a3226d2374 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock.c
@@ -52,9 +52,9 @@
  * \brief DFLL-specific data container.
  */
 struct _system_clock_dfll_config {
-	uint32_t control;
-	uint32_t val;
-	uint32_t mul;
+    uint32_t control;
+    uint32_t val;
+    uint32_t mul;
 };
 
 /**
@@ -62,7 +62,7 @@ struct _system_clock_dfll_config {
  * \brief XOSC-specific data container.
  */
 struct _system_clock_xosc_config {
-	uint32_t frequency;
+    uint32_t frequency;
 };
 
 /**
@@ -70,9 +70,9 @@ struct _system_clock_xosc_config {
  * \brief System clock module data container.
  */
 struct _system_clock_module {
-	volatile struct _system_clock_dfll_config dfll;
-	volatile struct _system_clock_xosc_config xosc;
-	volatile struct _system_clock_xosc_config xosc32k;
+    volatile struct _system_clock_dfll_config dfll;
+    volatile struct _system_clock_xosc_config xosc;
+    volatile struct _system_clock_xosc_config xosc32k;
 };
 
 /**
@@ -80,18 +80,18 @@ struct _system_clock_module {
  * \brief Internal module instance to cache configuration values.
  */
 static struct _system_clock_module _system_clock_inst = {
-		.dfll = {
-			.control     = 0,
-			.val     = 0,
-			.mul     = 0,
-		},
-		.xosc = {
-			.frequency   = 0,
-		},
-		.xosc32k = {
-			.frequency   = 0,
-		},
-	};
+        .dfll = {
+            .control     = 0,
+            .val     = 0,
+            .mul     = 0,
+        },
+        .xosc = {
+            .frequency   = 0,
+        },
+        .xosc32k = {
+            .frequency   = 0,
+        },
+    };
 
 /**
  * \internal
@@ -99,9 +99,10 @@ static struct _system_clock_module _system_clock_inst = {
  */
 static inline void _system_dfll_wait_for_sync(void)
 {
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-		/* Wait for DFLL sync */
-	}
+    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY))
+    {
+        /* Wait for DFLL sync */
+    }
 }
 
 /**
@@ -110,23 +111,24 @@ static inline void _system_dfll_wait_for_sync(void)
  */
 static inline void _system_osc32k_wait_for_sync(void)
 {
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
-		/* Wait for OSC32K sync */
-	}
+    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY))
+    {
+        /* Wait for OSC32K sync */
+    }
 }
 
 static inline void _system_clock_source_dfll_set_config_errata_9905(void)
 {
 
-	/* Disable ONDEMAND mode while writing configurations */
-	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
-	_system_dfll_wait_for_sync();
+    /* Disable ONDEMAND mode while writing configurations */
+    SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
+    _system_dfll_wait_for_sync();
 
-	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
-	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+    SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+    SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
 
-	/* Write full configuration to DFLL control register */
-	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+    /* Write full configuration to DFLL control register */
+    SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
 }
 
 /**
@@ -139,44 +141,46 @@ static inline void _system_clock_source_dfll_set_config_errata_9905(void)
  * \returns Frequency of the given clock source, in Hz.
  */
 uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		return _system_clock_inst.xosc.frequency;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        return _system_clock_inst.xosc.frequency;
 
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		return 32768UL;
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        return 32768UL;
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		return 32768UL;
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        return 32768UL;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		return _system_clock_inst.xosc32k.frequency;
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        return _system_clock_inst.xosc32k.frequency;
 
-	case SYSTEM_CLOCK_SOURCE_DFLL:
+    case SYSTEM_CLOCK_SOURCE_DFLL:
 
-		/* Check if the DFLL has been configured */
-		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
-			return 0;
+        /* Check if the DFLL has been configured */
+        if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+            return 0;
 
-		/* Make sure that the DFLL module is ready */
-		_system_dfll_wait_for_sync();
+        /* Make sure that the DFLL module is ready */
+        _system_dfll_wait_for_sync();
 
-		/* Check if operating in closed loop mode */
-		if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
-			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
-					(_system_clock_inst.dfll.mul & 0xffff);
-		}
+        /* Check if operating in closed loop mode */
+        if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE)
+        {
+            return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+                    (_system_clock_inst.dfll.mul & 0xffff);
+        }
 
-		return 48000000UL;
+        return 48000000UL;
 
-	default:
-		return 0;
-	}
+    default:
+        return 0;
+    }
 }
 
 /**
@@ -188,16 +192,16 @@ uint32_t system_clock_source_get_hz(
  * \param[in] config  OSC8M configuration structure containing the new config
  */
 void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config)
+        struct system_clock_source_osc8m_config *const config)
 {
-	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+    SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
 
-	/* Use temporary struct to reduce register access */
-	temp.bit.PRESC    = config->prescaler;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
+    /* Use temporary struct to reduce register access */
+    temp.bit.PRESC    = config->prescaler;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
 
-	SYSCTRL->OSC8M = temp;
+    SYSCTRL->OSC8M = temp;
 }
 
 /**
@@ -209,19 +213,19 @@ void system_clock_source_osc8m_set_config(
  * \param[in] config  OSC32K configuration structure containing the new config
  */
 void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config)
+        struct system_clock_source_osc32k_config *const config)
 {
-	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+    SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
 
-	/* Update settings via a temporary struct to reduce register access */
-	temp.bit.EN1K     = config->enable_1khz_output;
-	temp.bit.EN32K    = config->enable_32khz_output;
-	temp.bit.STARTUP  = config->startup_time;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
+    /* Update settings via a temporary struct to reduce register access */
+    temp.bit.EN1K     = config->enable_1khz_output;
+    temp.bit.EN32K    = config->enable_32khz_output;
+    temp.bit.STARTUP  = config->startup_time;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+    temp.bit.WRTLOCK  = config->write_once;
 
-	SYSCTRL->OSC32K  = temp;
+    SYSCTRL->OSC32K  = temp;
 }
 
 /**
@@ -234,43 +238,50 @@ void system_clock_source_osc32k_set_config(
  *                    the new config
  */
 void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config)
+        struct system_clock_source_xosc_config *const config)
 {
-	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
-
-	temp.bit.STARTUP = config->startup_time;
-
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
-
-	temp.bit.AMPGC = config->auto_gain_control;
-
-	/* Set gain if automatic gain control is not selected */
-	if (!config->auto_gain_control) {
-		if (config->frequency <= 2000000) {
-			temp.bit.GAIN = 0;
-		} else if (config->frequency <= 4000000) {
-			temp.bit.GAIN = 1;
-		} else if (config->frequency <= 8000000) {
-			temp.bit.GAIN = 2;
-		} else if (config->frequency <= 16000000) {
-			temp.bit.GAIN = 3;
-		} else if (config->frequency <= 32000000) {
-			temp.bit.GAIN = 4;
-		}
-
-	}
-
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-
-	/* Store XOSC frequency for internal use */
-	_system_clock_inst.xosc.frequency = config->frequency;
-
-	SYSCTRL->XOSC = temp;
+    SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+    temp.bit.STARTUP = config->startup_time;
+
+    if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL)
+    {
+        temp.bit.XTALEN = 1;
+    } else {
+        temp.bit.XTALEN = 0;
+    }
+
+    temp.bit.AMPGC = config->auto_gain_control;
+
+    /* Set gain if automatic gain control is not selected */
+    if (!config->auto_gain_control)
+    {
+        if (config->frequency <= 2000000)
+        {
+            temp.bit.GAIN = 0;
+        } else if (config->frequency <= 4000000)
+        {
+            temp.bit.GAIN = 1;
+        } else if (config->frequency <= 8000000)
+        {
+            temp.bit.GAIN = 2;
+        } else if (config->frequency <= 16000000)
+        {
+            temp.bit.GAIN = 3;
+        } else if (config->frequency <= 32000000)
+        {
+            temp.bit.GAIN = 4;
+        }
+
+    }
+
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+
+    /* Store XOSC frequency for internal use */
+    _system_clock_inst.xosc.frequency = config->frequency;
+
+    SYSCTRL->XOSC = temp;
 }
 
 /**
@@ -282,33 +293,34 @@ void system_clock_source_xosc_set_config(
  * \param[in] config  XOSC32K configuration structure containing the new config
  */
 void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config)
+        struct system_clock_source_xosc32k_config *const config)
 {
-	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+    SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
 
-	temp.bit.STARTUP = config->startup_time;
+    temp.bit.STARTUP = config->startup_time;
 
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
+    if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL)
+    {
+        temp.bit.XTALEN = 1;
+    } else {
+        temp.bit.XTALEN = 0;
+    }
 
-	temp.bit.AAMPEN = config->auto_gain_control;
-	temp.bit.EN1K = config->enable_1khz_output;
-	temp.bit.EN32K = config->enable_32khz_output;
+    temp.bit.AAMPEN = config->auto_gain_control;
+    temp.bit.EN1K = config->enable_1khz_output;
+    temp.bit.EN32K = config->enable_32khz_output;
 
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+    temp.bit.WRTLOCK  = config->write_once;
 
-	/* Cache the new frequency in case the user needs to check the current
-	 * operating frequency later */
-	_system_clock_inst.xosc32k.frequency = config->frequency;
+    /* Cache the new frequency in case the user needs to check the current
+     * operating frequency later */
+    _system_clock_inst.xosc32k.frequency = config->frequency;
 
-	SYSCTRL->XOSC32K = temp;
+    SYSCTRL->XOSC32K = temp;
 }
-///@cond INTERNAL
+/*/@cond INTERNAL*/
 
 /**
  * \internal
@@ -352,7 +364,7 @@ void system_clock_source_xosc32k_set_config(
 
 #define _SYSTEM_MCU_REVISION_D 3
 
-///@endcond
+/*/@endcond*/
 
 
 /**
@@ -367,49 +379,52 @@ void system_clock_source_xosc32k_set_config(
  * \param[in] config  DFLL configuration structure containing the new config
  */
 void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config)
+        struct system_clock_source_dfll_config *const config)
 {
 
-	/* Get MCU revision */
-	uint32_t rev = system_get_device_id();
-
-	rev &= DSU_DID_REVISION_Msk;
-	rev = rev >> DSU_DID_REVISION_Pos;
-
-	if (rev < _SYSTEM_MCU_REVISION_D) {
-		_system_clock_inst.dfll.val =
-				_SYSTEM_OLD_DFLLVAL_COARSE(config->coarse_value) |
-				_SYSTEM_OLD_DFLLVAL_FINE(config->fine_value);
-	} else {
-		_system_clock_inst.dfll.val =
-				_SYSTEM_NEW_DFLLVAL_COARSE(config->coarse_value) |
-				_SYSTEM_NEW_DFLLVAL_FINE(config->fine_value);
-	}
-
-	_system_clock_inst.dfll.control =
-			(uint32_t)config->wakeup_lock     |
-			(uint32_t)config->stable_tracking |
-			(uint32_t)config->quick_lock      |
-			(uint32_t)config->chill_cycle     |
-			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
-
-	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-
-		if(rev < _SYSTEM_MCU_REVISION_D) {
-			_system_clock_inst.dfll.mul =
-					_SYSTEM_OLD_DFLLMUL_CSTEP(config->coarse_max_step) |
-					_SYSTEM_OLD_DFLLMUL_FSTEP(config->fine_max_step)   |
-					SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-		} else {
-			_system_clock_inst.dfll.mul =
-					_SYSTEM_NEW_DFLLMUL_CSTEP(config->coarse_max_step) |
-					_SYSTEM_NEW_DFLLMUL_FSTEP(config->fine_max_step)   |
-					SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-		}
-
-		/* Enable the closed loop mode */
-		_system_clock_inst.dfll.control |= config->loop_mode;
-	}
+    /* Get MCU revision */
+    uint32_t rev = system_get_device_id();
+
+    rev &= DSU_DID_REVISION_Msk;
+    rev = rev >> DSU_DID_REVISION_Pos;
+
+    if (rev < _SYSTEM_MCU_REVISION_D)
+    {
+        _system_clock_inst.dfll.val =
+                _SYSTEM_OLD_DFLLVAL_COARSE(config->coarse_value) |
+                _SYSTEM_OLD_DFLLVAL_FINE(config->fine_value);
+    } else {
+        _system_clock_inst.dfll.val =
+                _SYSTEM_NEW_DFLLVAL_COARSE(config->coarse_value) |
+                _SYSTEM_NEW_DFLLVAL_FINE(config->fine_value);
+    }
+
+    _system_clock_inst.dfll.control =
+            (uint32_t)config->wakeup_lock     |
+            (uint32_t)config->stable_tracking |
+            (uint32_t)config->quick_lock      |
+            (uint32_t)config->chill_cycle     |
+            ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+    if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+
+        if(rev < _SYSTEM_MCU_REVISION_D)
+        {
+            _system_clock_inst.dfll.mul =
+                    _SYSTEM_OLD_DFLLMUL_CSTEP(config->coarse_max_step) |
+                    _SYSTEM_OLD_DFLLMUL_FSTEP(config->fine_max_step)   |
+                    SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+        } else {
+            _system_clock_inst.dfll.mul =
+                    _SYSTEM_NEW_DFLLMUL_CSTEP(config->coarse_max_step) |
+                    _SYSTEM_NEW_DFLLMUL_FSTEP(config->fine_max_step)   |
+                    SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+        }
+
+        /* Enable the closed loop mode */
+        _system_clock_inst.dfll.control |= config->loop_mode;
+    }
 }
 
 /**
@@ -438,47 +453,51 @@ void system_clock_source_dfll_set_config(
  *                                 source.
  */
 enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range)
+        const enum system_clock_source clock_source,
+        const uint16_t calibration_value,
+        const uint8_t freq_range)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
 
-		if (calibration_value > 0xfff || freq_range > 4) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 0xfff || freq_range > 4)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
-		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
-		break;
+        SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
+        SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
 
-		if (calibration_value > 128) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 128)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		_system_osc32k_wait_for_sync();
-		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
-		break;
+        _system_osc32k_wait_for_sync();
+        SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
 
-		if (calibration_value > 32) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 32)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
-		break;
+        SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+        break;
 
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-		break;
-	}
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+        break;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -494,40 +513,41 @@ enum status_code system_clock_source_write_calibration(
  *                                 device
  */
 enum status_code system_clock_source_enable(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
-		return STATUS_OK;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
-		_system_clock_source_dfll_set_config_errata_9905();
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Always enabled */
-		return STATUS_OK;
-
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+        return STATUS_OK;
+
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+        _system_clock_source_dfll_set_config_errata_9905();
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Always enabled */
+        return STATUS_OK;
+
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -542,40 +562,41 @@ enum status_code system_clock_source_enable(
  *                                 given
  */
 enum status_code system_clock_source_disable(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
-		break;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
-		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
-		break;
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+        SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Not possible to disable */
 
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
 
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -591,45 +612,47 @@ enum status_code system_clock_source_disable(
  * \retval false  Clock source is disabled or not yet ready
  */
 bool system_clock_source_is_ready(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	uint32_t mask = 0;
-
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		mask = SYSCTRL_PCLKSR_OSC8MRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		mask = SYSCTRL_PCLKSR_OSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		mask = SYSCTRL_PCLKSR_XOSCRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-			mask = (SYSCTRL_PCLKSR_DFLLRDY |
-			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
-		} else {
-			mask = SYSCTRL_PCLKSR_DFLLRDY;
-		}
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
-		return true;
-
-	default:
-		return false;
-	}
-
-	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+    uint32_t mask = 0;
+
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        mask = SYSCTRL_PCLKSR_OSC8MRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        mask = SYSCTRL_PCLKSR_OSC32KRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        mask = SYSCTRL_PCLKSR_XOSCRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+        {
+            mask = (SYSCTRL_PCLKSR_DFLLRDY |
+                    SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+        } else {
+            mask = SYSCTRL_PCLKSR_DFLLRDY;
+        }
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Not possible to disable */
+        return true;
+
+    default:
+        return false;
+    }
+
+    return ((SYSCTRL->PCLKSR.reg & mask) == mask);
 }
 
 /* Include some checks for conf_clocks.h validation */
@@ -641,16 +664,17 @@ bool system_clock_source_is_ready(
  * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
  */
 #  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
-	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
-		struct system_gclk_gen_config gclk_conf;                          \
-		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
-		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
-		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
-		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
-		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
-		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
-		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
-	}
+    if (CONF_CLOCK_GCLK_##n##_ENABLE == true)
+    { \
+        struct system_gclk_gen_config gclk_conf;                          \
+        system_gclk_gen_get_config_defaults(&gclk_conf);                  \
+        gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
+        gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
+        gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+        gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
+        system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
+        system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
+    }
 
 /** \internal
  *
@@ -658,7 +682,7 @@ bool system_clock_source_is_ready(
  * provided that it is not the main Generic Clock Generator channel.
  */
 #  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
-		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+        if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
 #endif
 
 /** \internal
@@ -668,30 +692,31 @@ bool system_clock_source_is_ready(
  */
 static void _switch_peripheral_gclk(void)
 {
-	uint32_t gclk_id;
-	struct system_gclk_chan_config gclk_conf;
+    uint32_t gclk_id;
+    struct system_gclk_chan_config gclk_conf;
 
 #if CONF_CLOCK_GCLK_1_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_1;
+    gclk_conf.source_generator = GCLK_GENERATOR_1;
 #elif CONF_CLOCK_GCLK_2_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_2;
+    gclk_conf.source_generator = GCLK_GENERATOR_2;
 #elif CONF_CLOCK_GCLK_3_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_3;
+    gclk_conf.source_generator = GCLK_GENERATOR_3;
 #elif CONF_CLOCK_GCLK_4_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_4;
+    gclk_conf.source_generator = GCLK_GENERATOR_4;
 #elif CONF_CLOCK_GCLK_5_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_5;
+    gclk_conf.source_generator = GCLK_GENERATOR_5;
 #elif CONF_CLOCK_GCLK_6_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_6;
+    gclk_conf.source_generator = GCLK_GENERATOR_6;
 #elif CONF_CLOCK_GCLK_7_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
+    gclk_conf.source_generator = GCLK_GENERATOR_7;
 #else
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
+    gclk_conf.source_generator = GCLK_GENERATOR_7;
 #endif
 
-	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
-		system_gclk_chan_set_config(gclk_id, &gclk_conf);
-	}
+    for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++)
+    {
+        system_gclk_chan_set_config(gclk_id, &gclk_conf);
+    }
 }
 
 /**
@@ -707,200 +732,207 @@ static void _switch_peripheral_gclk(void)
  */
 void system_clock_init(void)
 {
-	/* Various bits in the INTFLAG register can be set to one at startup.
-	   This will ensure that these bits are cleared */
-	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
-			SYSCTRL_INTFLAG_DFLLRDY;
+    /* Various bits in the INTFLAG register can be set to one at startup.
+       This will ensure that these bits are cleared */
+    SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+            SYSCTRL_INTFLAG_DFLLRDY;
 
-	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+    system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
 
-	/* Switch all peripheral clock to a not enabled general clock to save power. */
-	_switch_peripheral_gclk();
+    /* Switch all peripheral clock to a not enabled general clock to save power. */
+    _switch_peripheral_gclk();
 
-	/* XOSC */
+    /* XOSC */
 #if CONF_CLOCK_XOSC_ENABLE == true
-	struct system_clock_source_xosc_config xosc_conf;
-	system_clock_source_xosc_get_config_defaults(&xosc_conf);
-
-	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
-	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
-	xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
-	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
-	xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
-	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
-
-	system_clock_source_xosc_set_config(&xosc_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+    struct system_clock_source_xosc_config xosc_conf;
+    system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+    xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+    xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
+    xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+    xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+    xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
+    xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+    system_clock_source_xosc_set_config(&xosc_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
 #endif
 
 
-	/* XOSC32K */
+    /* XOSC32K */
 #if CONF_CLOCK_XOSC32K_ENABLE == true
-	struct system_clock_source_xosc32k_config xosc32k_conf;
-	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
-
-	xosc32k_conf.frequency           = 32768UL;
-	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
-	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
-	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
-	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
-	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
-	xosc32k_conf.on_demand           = false;
-	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
-
-	system_clock_source_xosc32k_set_config(&xosc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
-	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
-		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
-	}
+    struct system_clock_source_xosc32k_config xosc32k_conf;
+    system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+    xosc32k_conf.frequency           = 32768UL;
+    xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+    xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+    xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+    xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+    xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+    xosc32k_conf.on_demand           = false;
+    xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+    system_clock_source_xosc32k_set_config(&xosc32k_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+    if (CONF_CLOCK_XOSC32K_ON_DEMAND)
+    {
+        SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+    }
 #endif
 
 
-	/* OSCK32K */
+    /* OSCK32K */
 #if CONF_CLOCK_OSC32K_ENABLE == true
-	SYSCTRL->OSC32K.bit.CALIB =
-			(*(uint32_t *)FUSES_OSC32KCAL_ADDR >> FUSES_OSC32KCAL_Pos);
+    SYSCTRL->OSC32K.bit.CALIB =
+            (*(uint32_t *)FUSES_OSC32KCAL_ADDR >> FUSES_OSC32KCAL_Pos);
 
-	struct system_clock_source_osc32k_config osc32k_conf;
-	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+    struct system_clock_source_osc32k_config osc32k_conf;
+    system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
 
-	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
-	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
-	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
-	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
-	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+    osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
+    osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+    osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+    osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
+    osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
 
-	system_clock_source_osc32k_set_config(&osc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+    system_clock_source_osc32k_set_config(&osc32k_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
 #endif
 
 
-	/* DFLL Config (Open and Closed Loop) */
+    /* DFLL Config (Open and Closed Loop) */
 #if CONF_CLOCK_DFLL_ENABLE == true
-	struct system_clock_source_dfll_config dfll_conf;
-	system_clock_source_dfll_get_config_defaults(&dfll_conf);
+    struct system_clock_source_dfll_config dfll_conf;
+    system_clock_source_dfll_get_config_defaults(&dfll_conf);
 
-	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
-	dfll_conf.on_demand      = false;
+    dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
+    dfll_conf.on_demand      = false;
 
-	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
+    /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
      in DFLL.COARSE helps to output a frequency close to 48 MHz.
-	   Not applicable for silicon rev C and previous*/
+       Not applicable for silicon rev C and previous*/
 
-	/* Get MCU revision */
-	uint32_t rev = system_get_device_id();
+    /* Get MCU revision */
+    uint32_t rev = system_get_device_id();
 
-	rev &= DSU_DID_REVISION_Msk;
-	rev = rev >> DSU_DID_REVISION_Pos;
+    rev &= DSU_DID_REVISION_Msk;
+    rev = rev >> DSU_DID_REVISION_Pos;
 
-	if (rev >= _SYSTEM_MCU_REVISION_D) {
+    if (rev >= _SYSTEM_MCU_REVISION_D)
+    {
 #define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
 #define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
 
-		uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
-				+ (NVM_DFLL_COARSE_POS / 32))
-			>> (NVM_DFLL_COARSE_POS % 32))
-			& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
-		/* In some revision chip, the coarse calibration value is not correct. */
-		if (coarse == 0x3f) {
-			coarse = 0x1f;
-		}
-		dfll_conf.coarse_value = coarse;
-	}
-
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
-		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
-	}
+        uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+                + (NVM_DFLL_COARSE_POS / 32))
+            >> (NVM_DFLL_COARSE_POS % 32))
+            & ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+        /* In some revision chip, the coarse calibration value is not correct. */
+        if (coarse == 0x3f)
+        {
+            coarse = 0x1f;
+        }
+        dfll_conf.coarse_value = coarse;
+    }
+
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN)
+    {
+        dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
+    }
 
 #  if CONF_CLOCK_DFLL_QUICK_LOCK == true
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+    dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
 #  else
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+    dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
 #  endif
 
 #  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+    dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
 #  else
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+    dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
 #  endif
 
 #  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+    dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
 #  else
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+    dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
 #  endif
 
 #  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+    dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
 #  else
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+    dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
 #  endif
 
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
-	}
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+        dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+    }
 
-	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
-	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+    dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+    dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
 
-	system_clock_source_dfll_set_config(&dfll_conf);
+    system_clock_source_dfll_set_config(&dfll_conf);
 #endif
 
 
-	/* OSC8M */
-	struct system_clock_source_osc8m_config osc8m_conf;
-	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+    /* OSC8M */
+    struct system_clock_source_osc8m_config osc8m_conf;
+    system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
 
-	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
-	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
-	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+    osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+    osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+    osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
 
-	system_clock_source_osc8m_set_config(&osc8m_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+    system_clock_source_osc8m_set_config(&osc8m_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
 
 
-	/* GCLK */
+    /* GCLK */
 #if CONF_CLOCK_CONFIGURE_GCLK == true
-	system_gclk_init();
+    system_gclk_init();
 
-	/* Configure all GCLK generators except for the main generator, which
-	 * is configured later after all other clock systems are set up */
-	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+    /* Configure all GCLK generators except for the main generator, which
+     * is configured later after all other clock systems are set up */
+    MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
 
 #  if CONF_CLOCK_DFLL_ENABLE == true
-	/* Enable DFLL reference clock if in closed loop mode */
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		struct system_gclk_chan_config dfll_gclk_chan_conf;
-
-		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
-		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
-	}
+    /* Enable DFLL reference clock if in closed loop mode */
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+        struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+        system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+        dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+        system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+        system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+    }
 #  endif
 #endif
 
 
-	/* DFLL Enable (Open and Closed Loop) */
+    /* DFLL Enable (Open and Closed Loop) */
 #if CONF_CLOCK_DFLL_ENABLE == true
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
-	if (CONF_CLOCK_DFLL_ON_DEMAND) {
-		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
-	}
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+    if (CONF_CLOCK_DFLL_ON_DEMAND)
+    {
+        SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+    }
 #endif
 
-	/* CPU and BUS clocks */
-	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+    /* CPU and BUS clocks */
+    system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
 
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
 
-	/* GCLK 0 */
+    /* GCLK 0 */
 #if CONF_CLOCK_CONFIGURE_GCLK == true
-	/* Configure the main GCLK last as it might depend on other generators */
-	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+    /* Configure the main GCLK last as it might depend on other generators */
+    _CONF_CLOCK_GCLK_CONFIG(0, ~);
 #endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h
index 2c1e343704ba..6044cbe63bc7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/clock_feature.h
@@ -96,14 +96,14 @@ extern "C" {
  *
  * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
  * <table>
- *	<tr>
- *		<th>Driver Feature Macro</th>
- *		<th>Supported devices</th>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
- *		<td>SAM D21, SAM R21, SAM D10, SAM D11</td>
- *	</tr>
+ *  <tr>
+ *      <th>Driver Feature Macro</th>
+ *      <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ *      <td>SAM D21, SAM R21, SAM D10, SAM D11</td>
+ *  </tr>
  * </table>
  * \note The specific features are only available in the driver when the
  * selected device supports those features.
@@ -284,22 +284,22 @@ extern "C" {
  * clock cycles.
  */
 enum system_xosc32k_startup {
-	/** Wait zero clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_0,
-	/** Wait 32 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_32,
-	/** Wait 2048 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_4096,
-	/** Wait 16384 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_32768,
-	/** Wait 65536 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_65536,
-	/** Wait 131072 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC32K_STARTUP_131072,
+    /** Wait zero clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_0,
+    /** Wait 32 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_32,
+    /** Wait 2048 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_2048,
+    /** Wait 4096 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_4096,
+    /** Wait 16384 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_16384,
+    /** Wait 32768 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_32768,
+    /** Wait 65536 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_65536,
+    /** Wait 131072 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC32K_STARTUP_131072,
 };
 
 /**
@@ -309,38 +309,38 @@ enum system_xosc32k_startup {
  * cycles.
  */
 enum system_xosc_startup {
-	/** Wait one clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_1,
-	/** Wait two clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_2,
-	/** Wait four clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_4,
-	/** Wait eight clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_8,
-	/** Wait 16 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_16,
-	/** Wait 32 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_32,
-	/** Wait 64 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_64,
-	/** Wait 128 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_128,
-	/** Wait 256 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_256,
-	/** Wait 512 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_512,
-	/** Wait 1024 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_1024,
-	/** Wait 2048 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_4096,
-	/** Wait 8192 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_8192,
-	/** Wait 16384 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable. */
-	SYSTEM_XOSC_STARTUP_32768,
+    /** Wait one clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_1,
+    /** Wait two clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_2,
+    /** Wait four clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_4,
+    /** Wait eight clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_8,
+    /** Wait 16 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_16,
+    /** Wait 32 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_32,
+    /** Wait 64 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_64,
+    /** Wait 128 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_128,
+    /** Wait 256 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_256,
+    /** Wait 512 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_512,
+    /** Wait 1024 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_1024,
+    /** Wait 2048 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_2048,
+    /** Wait 4096 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_4096,
+    /** Wait 8192 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_8192,
+    /** Wait 16384 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_16384,
+    /** Wait 32768 clock cycles until the clock source is considered stable. */
+    SYSTEM_XOSC_STARTUP_32768,
 };
 
 /**
@@ -350,22 +350,22 @@ enum system_xosc_startup {
  * OSC32K clock cycles.
  */
 enum system_osc32k_startup {
-	/** Wait three clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_3,
-	/** Wait four clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_4,
-	/** Wait six clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_6,
-	/** Wait ten clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_10,
-	/** Wait 18 clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_18,
-	/** Wait 34 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_34,
-	/** Wait 66 clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_66,
-	/** Wait 130 clock cycles until the clock source is considered stable. */
-	SYSTEM_OSC32K_STARTUP_130,
+    /** Wait three clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_3,
+    /** Wait four clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_4,
+    /** Wait six clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_6,
+    /** Wait ten clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_10,
+    /** Wait 18 clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_18,
+    /** Wait 34 clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_34,
+    /** Wait 66 clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_66,
+    /** Wait 130 clock cycles until the clock source is considered stable. */
+    SYSTEM_OSC32K_STARTUP_130,
 };
 
 /**
@@ -374,14 +374,14 @@ enum system_osc32k_startup {
  * Available prescalers for the internal 8MHz (nominal) system clock.
  */
 enum system_osc8m_div {
-	/** Do not divide the 8MHz RC oscillator output. */
-	SYSTEM_OSC8M_DIV_1,
-	/** Divide the 8MHz RC oscillator output by two. */
-	SYSTEM_OSC8M_DIV_2,
-	/** Divide the 8MHz RC oscillator output by four. */
-	SYSTEM_OSC8M_DIV_4,
-	/** Divide the 8MHz RC oscillator output by eight. */
-	SYSTEM_OSC8M_DIV_8,
+    /** Do not divide the 8MHz RC oscillator output. */
+    SYSTEM_OSC8M_DIV_1,
+    /** Divide the 8MHz RC oscillator output by two. */
+    SYSTEM_OSC8M_DIV_2,
+    /** Divide the 8MHz RC oscillator output by four. */
+    SYSTEM_OSC8M_DIV_4,
+    /** Divide the 8MHz RC oscillator output by eight. */
+    SYSTEM_OSC8M_DIV_8,
 };
 
 /**
@@ -390,14 +390,14 @@ enum system_osc8m_div {
  * Internal 8MHz RC oscillator frequency range setting.
  */
 enum system_osc8m_frequency_range {
-	/** Frequency range 4MHz to 6MHz. */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
-	/** Frequency range 6MHz to 8MHz. */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
-	/** Frequency range 8MHz to 11MHz. */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
-	/** Frequency range 11MHz to 15MHz. */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+    /** Frequency range 4MHz to 6MHz. */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+    /** Frequency range 6MHz to 8MHz. */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+    /** Frequency range 8MHz to 11MHz. */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+    /** Frequency range 11MHz to 15MHz. */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
 };
 
 /**
@@ -406,22 +406,22 @@ enum system_osc8m_frequency_range {
  * Available division ratios for the CPU and APB/AHB bus clocks.
  */
 enum system_main_clock_div {
-	/** Divide Main clock by one. */
-	SYSTEM_MAIN_CLOCK_DIV_1,
-	/** Divide Main clock by two. */
-	SYSTEM_MAIN_CLOCK_DIV_2,
-	/** Divide Main clock by four. */
-	SYSTEM_MAIN_CLOCK_DIV_4,
-	/** Divide Main clock by eight. */
-	SYSTEM_MAIN_CLOCK_DIV_8,
-	/** Divide Main clock by 16. */
-	SYSTEM_MAIN_CLOCK_DIV_16,
-	/** Divide Main clock by 32. */
-	SYSTEM_MAIN_CLOCK_DIV_32,
-	/** Divide Main clock by 64. */
-	SYSTEM_MAIN_CLOCK_DIV_64,
-	/** Divide Main clock by 128. */
-	SYSTEM_MAIN_CLOCK_DIV_128,
+    /** Divide Main clock by one. */
+    SYSTEM_MAIN_CLOCK_DIV_1,
+    /** Divide Main clock by two. */
+    SYSTEM_MAIN_CLOCK_DIV_2,
+    /** Divide Main clock by four. */
+    SYSTEM_MAIN_CLOCK_DIV_4,
+    /** Divide Main clock by eight. */
+    SYSTEM_MAIN_CLOCK_DIV_8,
+    /** Divide Main clock by 16. */
+    SYSTEM_MAIN_CLOCK_DIV_16,
+    /** Divide Main clock by 32. */
+    SYSTEM_MAIN_CLOCK_DIV_32,
+    /** Divide Main clock by 64. */
+    SYSTEM_MAIN_CLOCK_DIV_64,
+    /** Divide Main clock by 128. */
+    SYSTEM_MAIN_CLOCK_DIV_128,
 };
 
 /**
@@ -430,10 +430,10 @@ enum system_main_clock_div {
  * Available external clock source types.
  */
 enum system_clock_external {
-	/** The external clock source is a crystal oscillator. */
-	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
-	/** The connected clock source is an external logic level clock signal. */
-	SYSTEM_CLOCK_EXTERNAL_CLOCK,
+    /** The external clock source is a crystal oscillator. */
+    SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+    /** The connected clock source is an external logic level clock signal. */
+    SYSTEM_CLOCK_EXTERNAL_CLOCK,
 };
 
 /**
@@ -442,18 +442,18 @@ enum system_clock_external {
  * Available operating modes of the DFLL clock source module.
  */
 enum system_clock_dfll_loop_mode {
-	/** The DFLL is operating in open loop mode with no feedback. */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
-	/** The DFLL is operating in closed loop mode with frequency feedback from
-	 *  a low frequency reference clock.
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+    /** The DFLL is operating in open loop mode with no feedback. */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+    /** The DFLL is operating in closed loop mode with frequency feedback from
+     *  a low frequency reference clock.
+     */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
 
 #ifdef SYSCTRL_DFLLCTRL_USBCRM
-	/** The DFLL is operating in USB recovery mode with frequency feedback
-	 *  from USB SOF.
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+    /** The DFLL is operating in USB recovery mode with frequency feedback
+     *  from USB SOF.
+     */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
 #endif
 };
 
@@ -463,10 +463,10 @@ enum system_clock_dfll_loop_mode {
  * DFLL lock behavior modes on device wake-up from sleep.
  */
 enum system_clock_dfll_wakeup_lock {
-	/** Keep DFLL lock when the device wakes from sleep. */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
-	/** Lose DFLL lock when the devices wakes from sleep. */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+    /** Keep DFLL lock when the device wakes from sleep. */
+    SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+    /** Lose DFLL lock when the devices wakes from sleep. */
+    SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
 };
 
 /**
@@ -475,10 +475,10 @@ enum system_clock_dfll_wakeup_lock {
  * DFLL fine tracking behavior modes after a lock has been acquired.
  */
 enum system_clock_dfll_stable_tracking {
-	/** Keep tracking after the DFLL has gotten a fine lock. */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
-	/** Stop tracking after the DFLL has gotten a fine lock. */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+    /** Keep tracking after the DFLL has gotten a fine lock. */
+    SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+    /** Stop tracking after the DFLL has gotten a fine lock. */
+    SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
 };
 
 /**
@@ -489,10 +489,10 @@ enum system_clock_dfll_stable_tracking {
  * the output to stabilize after a change in the input clock source.
  */
 enum system_clock_dfll_chill_cycle {
-	/** Enable a chill cycle, where the DFLL output frequency is not measured. */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
-	/** Disable a chill cycle, where the DFLL output frequency is not measured. */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+    /** Enable a chill cycle, where the DFLL output frequency is not measured. */
+    SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+    /** Disable a chill cycle, where the DFLL output frequency is not measured. */
+    SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
 };
 
 /**
@@ -502,10 +502,10 @@ enum system_clock_dfll_chill_cycle {
  * the DFLL output frequency at the expense of accuracy.
  */
 enum system_clock_dfll_quick_lock {
-	/** Enable the QuickLock feature for looser lock requirements on the DFLL. */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
-	/** Disable the QuickLock feature for strict lock requirements on the DFLL. */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+    /** Enable the QuickLock feature for looser lock requirements on the DFLL. */
+    SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+    /** Disable the QuickLock feature for strict lock requirements on the DFLL. */
+    SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
 };
 
 /**
@@ -514,27 +514,27 @@ enum system_clock_dfll_quick_lock {
  * Clock sources available to the GCLK generators.
  */
 enum system_clock_source {
-	/** Internal 8MHz RC oscillator. */
-	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
-	/** Internal 32KHz RC oscillator. */
-	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
-	/** External oscillator. */
-	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
-	/** External 32KHz oscillator. */
-	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
-	/** Digital Frequency Locked Loop (DFLL). */
-	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
-	/** Internal Ultra Low Power 32KHz oscillator. */
-	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
-	/** Generator input pad. */
-	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
-	/** Generic clock generator one output. */
-	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
+    /** Internal 8MHz RC oscillator. */
+    SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
+    /** Internal 32KHz RC oscillator. */
+    SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
+    /** External oscillator. */
+    SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
+    /** External 32KHz oscillator. */
+    SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
+    /** Digital Frequency Locked Loop (DFLL). */
+    SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
+    /** Internal Ultra Low Power 32KHz oscillator. */
+    SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
+    /** Generator input pad. */
+    SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
+    /** Generic clock generator one output. */
+    SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	/** Digital Phase Locked Loop (DPLL).
-	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
-	 */
-	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
+    /** Digital Phase Locked Loop (DPLL).
+     * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+     */
+    SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
 #endif
 };
 
@@ -544,12 +544,12 @@ enum system_clock_source {
  * Available bus clock domains on the APB bus.
  */
 enum system_clock_apb_bus {
-	/** Peripheral bus A on the APB bus. */
-	SYSTEM_CLOCK_APB_APBA,
-	/** Peripheral bus B on the APB bus. */
-	SYSTEM_CLOCK_APB_APBB,
-	/** Peripheral bus C on the APB bus. */
-	SYSTEM_CLOCK_APB_APBC,
+    /** Peripheral bus A on the APB bus. */
+    SYSTEM_CLOCK_APB_APBA,
+    /** Peripheral bus B on the APB bus. */
+    SYSTEM_CLOCK_APB_APBB,
+    /** Peripheral bus C on the APB bus. */
+    SYSTEM_CLOCK_APB_APBC,
 };
 
 /**
@@ -558,19 +558,19 @@ enum system_clock_apb_bus {
  * External oscillator clock configuration structure.
  */
 struct system_clock_source_xosc_config {
-	/** External clock type. */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time. */
-	enum system_xosc_startup startup_time;
-	/** Enable automatic amplitude gain control. */
-	bool auto_gain_control;
-	/** External clock/crystal frequency. */
-	uint32_t frequency;
-	/** Keep the XOSC enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
+    /** External clock type. */
+    enum system_clock_external external_clock;
+    /** Crystal oscillator start-up time. */
+    enum system_xosc_startup startup_time;
+    /** Enable automatic amplitude gain control. */
+    bool auto_gain_control;
+    /** External clock/crystal frequency. */
+    uint32_t frequency;
+    /** Keep the XOSC enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the XOSC won't run
+     * until requested by a peripheral. */
+    bool on_demand;
 };
 
 /**
@@ -579,26 +579,26 @@ struct system_clock_source_xosc_config {
  * External 32KHz oscillator clock configuration structure.
  */
 struct system_clock_source_xosc32k_config {
-	/** External clock type. */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time. */
-	enum system_xosc32k_startup startup_time;
-	/** Enable automatic amplitude control. */
-	bool auto_gain_control;
-	/** Enable 1KHz output. */
-	bool enable_1khz_output;
-	/** Enable 32KHz output. */
-	bool enable_32khz_output;
-	/** External clock/crystal frequency. */
-	uint32_t frequency;
-	/** Keep the XOSC32K enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC32K won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock. */
-	bool write_once;
+    /** External clock type. */
+    enum system_clock_external external_clock;
+    /** Crystal oscillator start-up time. */
+    enum system_xosc32k_startup startup_time;
+    /** Enable automatic amplitude control. */
+    bool auto_gain_control;
+    /** Enable 1KHz output. */
+    bool enable_1khz_output;
+    /** Enable 32KHz output. */
+    bool enable_32khz_output;
+    /** External clock/crystal frequency. */
+    uint32_t frequency;
+    /** Keep the XOSC32K enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the XOSC32K won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Lock configuration after it has been written,
+     *  a device reset will release the lock. */
+    bool write_once;
 };
 
 /**
@@ -607,13 +607,13 @@ struct system_clock_source_xosc32k_config {
  * Internal 8MHz (nominal) oscillator configuration structure.
  */
 struct system_clock_source_osc8m_config {
-	/** Internal 8MHz RC oscillator prescaler. */
-	enum system_osc8m_div prescaler;
-	/** Keep the OSC8M enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC8M won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
+    /** Internal 8MHz RC oscillator prescaler. */
+    enum system_osc8m_div prescaler;
+    /** Keep the OSC8M enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the OSC8M won't run
+     * until requested by a peripheral. */
+    bool on_demand;
 };
 
 /**
@@ -622,20 +622,20 @@ struct system_clock_source_osc8m_config {
  * Internal 32KHz (nominal) oscillator configuration structure.
  */
 struct system_clock_source_osc32k_config {
-	/** Startup time. */
-	enum system_osc32k_startup startup_time;
-	/** Enable 1KHz output. */
-	bool enable_1khz_output;
-	/** Enable 32KHz output. */
-	bool enable_32khz_output;
-	/** Keep the OSC32K enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC32K won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock. */
-	bool write_once;
+    /** Startup time. */
+    enum system_osc32k_startup startup_time;
+    /** Enable 1KHz output. */
+    bool enable_1khz_output;
+    /** Enable 32KHz output. */
+    bool enable_32khz_output;
+    /** Keep the OSC32K enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the OSC32K won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Lock configuration after it has been written,
+     *  a device reset will release the lock. */
+    bool write_once;
 };
 
 /**
@@ -644,29 +644,29 @@ struct system_clock_source_osc32k_config {
  * DFLL oscillator configuration structure.
  */
 struct system_clock_source_dfll_config {
-	/** Loop mode. */
-	enum system_clock_dfll_loop_mode loop_mode;
-	/** Run On Demand. If this is set the DFLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Enable Quick Lock. */
-	enum system_clock_dfll_quick_lock quick_lock;
-	/** Enable Chill Cycle. */
-	enum system_clock_dfll_chill_cycle chill_cycle;
-	/** DFLL lock state on wakeup. */
-	enum system_clock_dfll_wakeup_lock wakeup_lock;
-	/** DFLL tracking after fine lock. */
-	enum system_clock_dfll_stable_tracking stable_tracking;
-	/** Coarse calibration value (Open loop mode). */
-	uint8_t coarse_value;
-	/** Fine calibration value (Open loop mode). */
-	uint16_t fine_value;
-	/** Coarse adjustment maximum step size (Closed loop mode). */
-	uint8_t coarse_max_step;
-	/** Fine adjustment maximum step size (Closed loop mode). */
-	uint16_t fine_max_step;
-	/** DFLL multiply factor (Closed loop mode. */
-	uint16_t multiply_factor;
+    /** Loop mode. */
+    enum system_clock_dfll_loop_mode loop_mode;
+    /** Run On Demand. If this is set the DFLL won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Enable Quick Lock. */
+    enum system_clock_dfll_quick_lock quick_lock;
+    /** Enable Chill Cycle. */
+    enum system_clock_dfll_chill_cycle chill_cycle;
+    /** DFLL lock state on wakeup. */
+    enum system_clock_dfll_wakeup_lock wakeup_lock;
+    /** DFLL tracking after fine lock. */
+    enum system_clock_dfll_stable_tracking stable_tracking;
+    /** Coarse calibration value (Open loop mode). */
+    uint8_t coarse_value;
+    /** Fine calibration value (Open loop mode). */
+    uint16_t fine_value;
+    /** Coarse adjustment maximum step size (Closed loop mode). */
+    uint8_t coarse_max_step;
+    /** Fine adjustment maximum step size (Closed loop mode). */
+    uint16_t fine_max_step;
+    /** DFLL multiply factor (Closed loop mode. */
+    uint16_t multiply_factor;
 };
 
 /**
@@ -689,20 +689,20 @@ struct system_clock_source_dfll_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_xosc_get_config_defaults(
-		struct system_clock_source_xosc_config *const config)
+        struct system_clock_source_xosc_config *const config)
 {
-	Assert(config);
-
-	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
-	config->auto_gain_control = true;
-	config->frequency         = 12000000UL;
-	config->run_in_standby    = false;
-	config->on_demand         = true;
+    Assert(config);
+
+    config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+    config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
+    config->auto_gain_control = true;
+    config->frequency         = 12000000UL;
+    config->run_in_standby    = false;
+    config->on_demand         = true;
 }
 
 void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config);
+        struct system_clock_source_xosc_config *const config);
 
 /**
  * @}
@@ -732,23 +732,23 @@ void system_clock_source_xosc_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_xosc32k_get_config_defaults(
-		struct system_clock_source_xosc32k_config *const config)
+        struct system_clock_source_xosc32k_config *const config)
 {
-	Assert(config);
-
-	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
-	config->auto_gain_control   = false;
-	config->frequency           = 32768UL;
-	config->enable_1khz_output  = false;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->write_once          = false;
+    Assert(config);
+
+    config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+    config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
+    config->auto_gain_control   = false;
+    config->frequency           = 32768UL;
+    config->enable_1khz_output  = false;
+    config->enable_32khz_output = true;
+    config->run_in_standby      = false;
+    config->on_demand           = true;
+    config->write_once          = false;
 }
 
 void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config);
+        struct system_clock_source_xosc32k_config *const config);
 /**
  * @}
  */
@@ -774,20 +774,20 @@ void system_clock_source_xosc32k_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_osc32k_get_config_defaults(
-		struct system_clock_source_osc32k_config *const config)
+        struct system_clock_source_osc32k_config *const config)
 {
-	Assert(config);
-
-	config->enable_1khz_output  = true;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
-	config->write_once          = false;
+    Assert(config);
+
+    config->enable_1khz_output  = true;
+    config->enable_32khz_output = true;
+    config->run_in_standby      = false;
+    config->on_demand           = true;
+    config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
+    config->write_once          = false;
 }
 
 void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config);
+        struct system_clock_source_osc32k_config *const config);
 
 /**
  * @}
@@ -811,17 +811,17 @@ void system_clock_source_osc32k_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_osc8m_get_config_defaults(
-		struct system_clock_source_osc8m_config *const config)
+        struct system_clock_source_osc8m_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->prescaler       = SYSTEM_OSC8M_DIV_8;
-	config->run_in_standby  = false;
-	config->on_demand       = true;
+    config->prescaler       = SYSTEM_OSC8M_DIV_8;
+    config->run_in_standby  = false;
+    config->on_demand       = true;
 }
 
 void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config);
+        struct system_clock_source_osc8m_config *const config);
 
 /**
  * @}
@@ -851,29 +851,29 @@ void system_clock_source_osc8m_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_dfll_get_config_defaults(
-		struct system_clock_source_dfll_config *const config)
+        struct system_clock_source_dfll_config *const config)
 {
-	Assert(config);
-
-	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
-	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
-	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-	config->on_demand       = true;
-
-	/* Open loop mode calibration value */
-	config->coarse_value    = 0x1f / 4; /* Midpoint */
-	config->fine_value      = 0xff / 4; /* Midpoint */
-
-	/* Closed loop mode */
-	config->coarse_max_step = 1;
-	config->fine_max_step   = 1;
-	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+    Assert(config);
+
+    config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+    config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+    config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+    config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+    config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+    config->on_demand       = true;
+
+    /* Open loop mode calibration value */
+    config->coarse_value    = 0x1f / 4; /* Midpoint */
+    config->fine_value      = 0xff / 4; /* Midpoint */
+
+    /* Closed loop mode */
+    config->coarse_max_step = 1;
+    config->fine_max_step   = 1;
+    config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
 }
 
 void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config);
+        struct system_clock_source_dfll_config *const config);
 
 /**
  * @}
@@ -884,21 +884,21 @@ void system_clock_source_dfll_set_config(
  * @{
  */
 enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source system_clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range);
+        const enum system_clock_source system_clock_source,
+        const uint16_t calibration_value,
+        const uint8_t freq_range);
 
 enum status_code system_clock_source_enable(
-		const enum system_clock_source system_clock_source);
+        const enum system_clock_source system_clock_source);
 
 enum status_code system_clock_source_disable(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 bool system_clock_source_is_ready(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 /**
  * @}
@@ -917,10 +917,10 @@ uint32_t system_clock_source_get_hz(
  * \param[in] divider  CPU clock divider to set
  */
 static inline void system_cpu_clock_set_divider(
-		const enum system_main_clock_div divider)
+        const enum system_main_clock_div divider)
 {
-	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
-	PM->CPUSEL.reg = (uint32_t)divider;
+    Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+    PM->CPUSEL.reg = (uint32_t)divider;
 }
 
 /**
@@ -933,7 +933,7 @@ static inline void system_cpu_clock_set_divider(
  */
 static inline uint32_t system_cpu_clock_get_hz(void)
 {
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+    return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
 }
 
 /**
@@ -951,25 +951,26 @@ static inline uint32_t system_cpu_clock_get_hz(void)
  * \retval STATUS_OK               The APBx clock was set successfully
  */
 static inline enum status_code system_apb_clock_set_divider(
-		const enum system_clock_apb_bus bus,
-		const enum system_main_clock_div divider)
+        const enum system_clock_apb_bus bus,
+        const enum system_main_clock_div divider)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBASEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBSEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCSEL.reg = (uint32_t)divider;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBASEL.reg = (uint32_t)divider;
+            break;
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBSEL.reg = (uint32_t)divider;
+            break;
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCSEL.reg = (uint32_t)divider;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -981,26 +982,27 @@ static inline enum status_code system_apb_clock_set_divider(
  * \return Current APBx bus frequency in Hz.
  */
 static inline uint32_t system_apb_clock_get_hz(
-		const enum system_clock_apb_bus bus)
+        const enum system_clock_apb_bus bus)
 {
-	uint16_t bus_divider = 0;
-
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			bus_divider = PM->APBASEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			bus_divider = PM->APBBSEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			bus_divider = PM->APBCSEL.reg;
-			break;
-		default:
-			Assert(false);
-			return 0;
-	}
-
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+    uint16_t bus_divider = 0;
+
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            bus_divider = PM->APBASEL.reg;
+            break;
+        case SYSTEM_CLOCK_APB_APBB:
+            bus_divider = PM->APBBSEL.reg;
+            break;
+        case SYSTEM_CLOCK_APB_APBC:
+            bus_divider = PM->APBCSEL.reg;
+            break;
+        default:
+            Assert(false);
+            return 0;
+    }
+
+    return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
 }
 
 
@@ -1023,9 +1025,9 @@ static inline uint32_t system_apb_clock_get_hz(
  * \param[in] ahb_mask  AHB clock mask to enable
  */
 static inline void system_ahb_clock_set_mask(
-		const uint32_t ahb_mask)
+        const uint32_t ahb_mask)
 {
-	PM->AHBMASK.reg |= ahb_mask;
+    PM->AHBMASK.reg |= ahb_mask;
 }
 
 /**
@@ -1038,9 +1040,9 @@ static inline void system_ahb_clock_set_mask(
  * \param[in] ahb_mask  AHB clock mask to disable
  */
 static inline void system_ahb_clock_clear_mask(
-		const uint32_t ahb_mask)
+        const uint32_t ahb_mask)
 {
-	PM->AHBMASK.reg &= ~ahb_mask;
+    PM->AHBMASK.reg &= ~ahb_mask;
 }
 
 /**
@@ -1061,29 +1063,30 @@ static inline void system_ahb_clock_clear_mask(
  * \retval STATUS_OK               The clock mask was set successfully
  */
 static inline enum status_code system_apb_clock_set_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
+        const enum system_clock_apb_bus bus,
+        const uint32_t mask)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg |= mask;
-			break;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBAMASK.reg |= mask;
+            break;
 
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg |= mask;
-			break;
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBMASK.reg |= mask;
+            break;
 
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg |= mask;
-			break;
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCMASK.reg |= mask;
+            break;
 
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
 
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1103,28 +1106,29 @@ static inline enum status_code system_apb_clock_set_mask(
  * \retval STATUS_OK               The clock mask was changed successfully
  */
 static inline enum status_code system_apb_clock_clear_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
+        const enum system_clock_apb_bus bus,
+        const uint32_t mask)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg &= ~mask;
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBAMASK.reg &= ~mask;
+            break;
+
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBMASK.reg &= ~mask;
+            break;
+
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCMASK.reg &= ~mask;
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1136,42 +1140,42 @@ static inline enum status_code system_apb_clock_clear_mask(
  * \brief Reference clock source of the DPLL module.
  */
 enum system_clock_source_dpll_reference_clock {
-	/** Select CLK_DPLL_REF0 as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
-	/** Select CLK_DPLL_REF1 as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
-	/** Select GCLK_DPLL as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+    /** Select CLK_DPLL_REF0 as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
+    /** Select CLK_DPLL_REF1 as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
+    /** Select GCLK_DPLL as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
 };
 
 /**
  * \brief Lock time-out value of the DPLL module.
  */
 enum system_clock_source_dpll_lock_time {
-	/** Set no time-out as default. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
-	/** Set time-out if no lock within 8ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
-	/** Set time-out if no lock within 9ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
-	/** Set time-out if no lock within 10ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
-	/** Set time-out if no lock within 11ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+    /** Set no time-out as default. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+    /** Set time-out if no lock within 8ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+    /** Set time-out if no lock within 9ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+    /** Set time-out if no lock within 10ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+    /** Set time-out if no lock within 11ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
 };
 
 /**
  * \brief Filter type of the DPLL module.
  */
 enum system_clock_source_dpll_filter {
-	/** Default filter mode. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
-	/** Low bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
-	/** High bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
-	/** High damping filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+    /** Default filter mode. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+    /** Low bandwidth filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+    /** High bandwidth filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+    /** High damping filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
 };
 
 /**
@@ -1180,32 +1184,32 @@ enum system_clock_source_dpll_filter {
  * DPLL oscillator configuration structure.
  */
 struct system_clock_source_dpll_config {
-	/** Run On Demand. If this is set the DPLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Keep the DPLL enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Bypass lock signal. */
-	bool lock_bypass;
-	/** Wake up fast. If this is set DPLL output clock is enabled after
-	 * the startup time. */
-	bool wake_up_fast;
-	/** Enable low power mode.  */
-	bool low_power_enable;
-
-	/** Output frequency of the clock. */
-	uint32_t output_frequency;
-	/** Reference frequency of the clock. */
-	uint32_t reference_frequency;
-	/** Devider of reference clock. */
-	uint16_t reference_divider;
-
-	/** Filter type of the DPLL module. */
-	enum system_clock_source_dpll_filter          filter;
-	/** Lock time-out value of the DPLL module. */
-	enum system_clock_source_dpll_lock_time       lock_time;
-	/** Reference clock source of the DPLL module. */
-	enum system_clock_source_dpll_reference_clock reference_clock;
+    /** Run On Demand. If this is set the DPLL won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Keep the DPLL enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Bypass lock signal. */
+    bool lock_bypass;
+    /** Wake up fast. If this is set DPLL output clock is enabled after
+     * the startup time. */
+    bool wake_up_fast;
+    /** Enable low power mode.  */
+    bool low_power_enable;
+
+    /** Output frequency of the clock. */
+    uint32_t output_frequency;
+    /** Reference frequency of the clock. */
+    uint32_t reference_frequency;
+    /** Devider of reference clock. */
+    uint16_t reference_divider;
+
+    /** Filter type of the DPLL module. */
+    enum system_clock_source_dpll_filter          filter;
+    /** Lock time-out value of the DPLL module. */
+    enum system_clock_source_dpll_lock_time       lock_time;
+    /** Reference clock source of the DPLL module. */
+    enum system_clock_source_dpll_reference_clock reference_clock;
 };
 
 /**
@@ -1233,25 +1237,25 @@ struct system_clock_source_dpll_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_dpll_get_config_defaults(
-		struct system_clock_source_dpll_config *const config)
+        struct system_clock_source_dpll_config *const config)
 {
-	config->on_demand           = true;
-	config->run_in_standby      = false;
-	config->lock_bypass         = false;
-	config->wake_up_fast        = false;
-	config->low_power_enable    = false;
-
-	config->output_frequency    = 48000000;
-	config->reference_frequency = 32768;
-	config->reference_divider   = 1;
-	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
-
-	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
-	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+    config->on_demand           = true;
+    config->run_in_standby      = false;
+    config->lock_bypass         = false;
+    config->wake_up_fast        = false;
+    config->low_power_enable    = false;
+
+    config->output_frequency    = 48000000;
+    config->reference_frequency = 32768;
+    config->reference_divider   = 1;
+    config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
+
+    config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+    config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
 };
 
 void system_clock_source_dpll_set_config(
-		struct system_clock_source_dpll_config *const config);
+        struct system_clock_source_dpll_config *const config);
 
 /* @} */
 #endif
@@ -1284,10 +1288,10 @@ void system_clock_init(void);
  */
 static inline void system_flash_set_waitstates(uint8_t wait_states)
 {
-	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
-			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+    Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+            ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
 
-	NVMCTRL->CTRLB.bit.RWS = wait_states;
+    NVMCTRL->CTRLB.bit.RWS = wait_states;
 }
 /**
  * @}
@@ -1305,54 +1309,54 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>DFLL</td>
- *		<td>Digital Frequency Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
- *	<tr>
- *		<td>OSC32K</td>
- *		<td>Internal 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>OSC8M</td>
- *		<td>Internal 8MHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>PLL</td>
- *		<td>Phase Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>OSC</td>
- *		<td>Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC</td>
- *		<td>External Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC32K</td>
- *		<td>External 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>AHB</td>
- *		<td>Advanced High-performance Bus</td>
- *	</tr>
- *	<tr>
- *		<td>APB</td>
- *		<td>Advanced Peripheral Bus</td>
- *	</tr>
- *	<tr>
- *		<td>DPLL</td>
- *		<td>Digital Phase Locked Loop</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>DFLL</td>
+ *      <td>Digital Frequency Locked Loop</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC32K</td>
+ *      <td>Internal 32KHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC8M</td>
+ *      <td>Internal 8MHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PLL</td>
+ *      <td>Phase Locked Loop</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC</td>
+ *      <td>Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>XOSC</td>
+ *      <td>External Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>XOSC32K</td>
+ *      <td>External 32KHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>AHB</td>
+ *      <td>Advanced High-performance Bus</td>
+ *  </tr>
+ *  <tr>
+ *      <td>APB</td>
+ *      <td>Advanced Peripheral Bus</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DPLL</td>
+ *      <td>Digital Phase Locked Loop</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1364,11 +1368,11 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  *
  * \section asfdoc_sam0_system_clock_extra_errata Errata
  *
- *	- This driver implements experimental workaround for errata 9905
+ *  - This driver implements experimental workaround for errata 9905
  *
- *	  "The DFLL clock must be requested before being configured otherwise a
- *	  write access to a DFLL register can freeze the device."
- *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *    "The DFLL clock must be requested before being configured otherwise a
+ *    write access to a DFLL register can freeze the device."
+ *    This driver will enable and configure the DFLL before the ONDEMAND bit is set.
  *
  *
  * \section asfdoc_sam0_system_clock_extra_history Module History
@@ -1378,47 +1382,47 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Corrected OSC32K startup time definitions
- *			\li Support locking of OSC32K and XOSC32K config register (default: false)
- *			\li Added DPLL support, functions added:
- *			    \c system_clock_source_dpll_get_config_defaults() and
- *		        \c system_clock_source_dpll_set_config()
- *			\li Moved gclk channel locking feature out of the config struct
- *			    functions added:
- *			    \c system_gclk_chan_lock(),
- *			    \c system_gclk_chan_is_locked()
- *			    \c system_gclk_chan_is_enabled() and
- *			    \c system_gclk_gen_is_enabled()
- *		</td>
- *	</tr>
  *  <tr>
- *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
- *		    and configured to a failed/not running clock generator</td>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *          \li Corrected OSC32K startup time definitions
+ *          \li Support locking of OSC32K and XOSC32K config register (default: false)
+ *          \li Added DPLL support, functions added:
+ *              \c system_clock_source_dpll_get_config_defaults() and
+ *              \c system_clock_source_dpll_set_config()
+ *          \li Moved gclk channel locking feature out of the config struct
+ *              functions added:
+ *              \c system_gclk_chan_lock(),
+ *              \c system_gclk_chan_is_locked()
+ *              \c system_gclk_chan_is_enabled() and
+ *              \c system_gclk_gen_is_enabled()
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ *          and configured to a failed/not running clock generator</td>
  *  </tr>
- *	<tr>
- *		<td>
- *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
- *			\li Fixed system_flash_set_waitstates() failing with an assertion
- *			    if an odd number of wait states provided
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Updated DFLL configuration function to implement workaround for
- *			    errata 9905 in the DFLL module
- *			\li Updated \c system_clock_init() to reset interrupt flags before
- *			    they are used
- *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
- *			    frequency number
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ *  <tr>
+ *      <td>
+ *          \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ *          \li Fixed system_flash_set_waitstates() failing with an assertion
+ *              if an odd number of wait states provided
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *          \li Updated DFLL configuration function to implement workaround for
+ *              errata 9905 in the DFLL module
+ *          \li Updated \c system_clock_init() to reset interrupt flags before
+ *              they are used
+ *          \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ *              frequency number
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>\li Fixed \c system_clock_source_is_ready not returning the correct
  *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
  *          \li Renamed the various \c system_clock_source_*_get_default_config()
  *              functions to \c system_clock_source_*_get_config_defaults() to
@@ -1428,10 +1432,10 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  *          \li Updated default configuration of the XOSC32 to disable Automatic
  *              Gain Control due to silicon errata
  *      </td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1450,37 +1454,37 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>E</td>
- *		<td>04/2015</td>
- *		<td>Added support for SAMDA1.</td>
- *	</tr>
- *	<tr>
- *		<td>D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAMR21 and SAMD10/D11.</td>
- *	</tr>
- *	<tr>
- *		<td>C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAMD21.</td>
- *	</tr>
- *	<tr>
- *		<td>B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos. Fixed missing steps in the Basic
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>E</td>
+ *      <td>04/2015</td>
+ *      <td>Added support for SAMDA1.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAMR21 and SAMD10/D11.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAMD21.</td>
+ *  </tr>
+ *  <tr>
+ *      <td>B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos. Fixed missing steps in the Basic
  *          Use Case Quick Start Guide.</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c
index 36579ad9ae39..8ff53e8aff7b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/gclk.c
@@ -64,11 +64,12 @@
  */
 static inline bool system_gclk_is_syncing(void)
 {
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-		return true;
-	}
+    if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -79,14 +80,15 @@ static inline bool system_gclk_is_syncing(void)
  */
 void system_gclk_init(void)
 {
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
-
-	/* Software reset the module to ensure it is re-initialized correctly */
-	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
-	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
-		/* Wait for reset to complete */
-	}
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+    /* Software reset the module to ensure it is re-initialized correctly */
+    GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+    while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
+    {
+        /* Wait for reset to complete */
+    }
 }
 
 /**
@@ -110,86 +112,95 @@ void system_gclk_init(void)
  * \param[in] config     Configuration settings for the generator
  */
 void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config)
+        const uint8_t generator,
+        struct system_gclk_gen_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Cache new register configurations to minimize sync requirements. */
-	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
-	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
-
-	/* Select the requested source clock for the generator */
-	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
-
-	/* Configure the clock to be either high or low when disabled */
-	if (config->high_when_disabled) {
-		new_genctrl_config |= GCLK_GENCTRL_OOV;
-	}
-
-	/* Configure if the clock output to I/O pin should be enabled. */
-	if (config->output_enable) {
-		new_genctrl_config |= GCLK_GENCTRL_OE;
-	}
-
-	/* Set division factor */
-	if (config->division_factor > 1) {
-		/* Check if division is a power of two */
-		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
-			/* Determine the index of the highest bit set to get the
-			 * division factor that must be loaded into the division
-			 * register */
-
-			uint32_t div2_count = 0;
-
-			uint32_t mask;
-			for (mask = (1UL << 1); mask < config->division_factor;
-						mask <<= 1) {
-				div2_count++;
-			}
-
-			/* Set binary divider power of 2 division factor */
-			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
-			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
-		} else {
-			/* Set integer division factor */
-
-			new_gendiv_config  |=
-					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
-
-			/* Enable non-binary division with increased duty cycle accuracy */
-			new_genctrl_config |= GCLK_GENCTRL_IDC;
-		}
-
-	}
-
-	/* Enable or disable the clock in standby mode */
-	if (config->run_in_standby) {
-		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
-	}
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the correct generator */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-
-	/* Write the new generator configuration */
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENDIV.reg  = new_gendiv_config;
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
-
-	system_interrupt_leave_critical_section();
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Cache new register configurations to minimize sync requirements. */
+    uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+    uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+    /* Select the requested source clock for the generator */
+    new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+    /* Configure the clock to be either high or low when disabled */
+    if (config->high_when_disabled)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_OOV;
+    }
+
+    /* Configure if the clock output to I/O pin should be enabled. */
+    if (config->output_enable)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_OE;
+    }
+
+    /* Set division factor */
+    if (config->division_factor > 1)
+    {
+        /* Check if division is a power of two */
+        if (((config->division_factor & (config->division_factor - 1)) == 0))
+        {
+            /* Determine the index of the highest bit set to get the
+             * division factor that must be loaded into the division
+             * register */
+
+            uint32_t div2_count = 0;
+
+            uint32_t mask;
+            for (mask = (1UL << 1); mask < config->division_factor;
+                        mask <<= 1)
+                        {
+                div2_count++;
+            }
+
+            /* Set binary divider power of 2 division factor */
+            new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+            new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+        } else {
+            /* Set integer division factor */
+
+            new_gendiv_config  |=
+                    (config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+            /* Enable non-binary division with increased duty cycle accuracy */
+            new_genctrl_config |= GCLK_GENCTRL_IDC;
+        }
+
+    }
+
+    /* Enable or disable the clock in standby mode */
+    if (config->run_in_standby)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+    }
+
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    system_interrupt_enter_critical_section();
+
+    /* Select the correct generator */
+    *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+    /* Write the new generator configuration */
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+    GCLK->GENDIV.reg  = new_gendiv_config;
+
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+    GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -201,24 +212,26 @@ void system_gclk_gen_set_config(
  * \param[in] generator  Generic Clock Generator index to enable
  */
 void system_gclk_gen_enable(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	/* Enable generator */
-	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+    /* Enable generator */
+    GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -230,27 +243,30 @@ void system_gclk_gen_enable(
  * \param[in] generator  Generic Clock Generator index to disable
  */
 void system_gclk_gen_disable(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	/* Disable generator */
-	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
-	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
-		/* Wait for clock to become disabled */
-	}
-
-	system_interrupt_leave_critical_section();
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    system_interrupt_enter_critical_section();
+
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    /* Disable generator */
+    GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+    while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN)
+    {
+        /* Wait for clock to become disabled */
+    }
+
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -263,20 +279,20 @@ void system_gclk_gen_disable(
  * \retval false The Generic Clock Generator is disabled
  */
 bool system_gclk_gen_is_enabled(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	bool enabled;
+    bool enabled;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	/* Obtain the enabled status */
-	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    /* Obtain the enabled status */
+    enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return enabled;
+    return enabled;
 }
 
 /**
@@ -290,46 +306,51 @@ bool system_gclk_gen_is_enabled(
  * \return The frequency of the generic clock generator, in Hz.
  */
 uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the appropriate generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the appropriate generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	/* Get the frequency of the source connected to the GCLK generator */
-	uint32_t gen_input_hz = system_clock_source_get_hz(
-			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+    /* Get the frequency of the source connected to the GCLK generator */
+    uint32_t gen_input_hz = system_clock_source_get_hz(
+            (enum system_clock_source)GCLK->GENCTRL.bit.SRC);
 
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
 
-	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+    uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
 
-	/* Select the appropriate generator division register */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the appropriate generator division register */
+    *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	uint32_t divider = GCLK->GENDIV.bit.DIV;
+    uint32_t divider = GCLK->GENDIV.bit.DIV;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	/* Check if the generator is using fractional or binary division */
-	if (!divsel && divider > 1) {
-		gen_input_hz /= divider;
-	} else if (divsel) {
-		gen_input_hz >>= (divider+1);
-	}
+    /* Check if the generator is using fractional or binary division */
+    if (!divsel && divider > 1)
+    {
+        gen_input_hz /= divider;
+    } else if (divsel)
+    {
+        gen_input_hz >>= (divider+1);
+    }
 
-	return gen_input_hz;
+    return gen_input_hz;
 }
 
 /**
@@ -346,23 +367,23 @@ uint32_t system_gclk_gen_get_hz(
  *
  */
 void system_gclk_chan_set_config(
-		const uint8_t channel,
-		struct system_gclk_chan_config *const config)
+        const uint8_t channel,
+        struct system_gclk_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Cache the new config to reduce sync requirements */
-	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+    /* Cache the new config to reduce sync requirements */
+    uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
 
-	/* Select the desired generic clock generator */
-	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+    /* Select the desired generic clock generator */
+    new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
 
-	/* Disable generic clock channel */
-	system_gclk_chan_disable(channel);
+    /* Disable generic clock channel */
+    system_gclk_chan_disable(channel);
 
-	/* Write the new configuration */
-	GCLK->CLKCTRL.reg = new_clkctrl_config;
+    /* Write the new configuration */
+    GCLK->CLKCTRL.reg = new_clkctrl_config;
 }
 
 /**
@@ -374,17 +395,17 @@ void system_gclk_chan_set_config(
  * \param[in] channel   Generic Clock channel to enable
  */
 void system_gclk_chan_enable(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Enable the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+    /* Enable the generic clock */
+    GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -396,30 +417,31 @@ void system_gclk_chan_enable(
  * \param[in] channel  Generic Clock channel to disable
  */
 void system_gclk_chan_disable(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Sanity check WRTLOCK */
-	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+    /* Sanity check WRTLOCK */
+    Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
 
-	/* Switch to known-working source so that the channel can be disabled */
-	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
-	GCLK->CLKCTRL.bit.GEN = 0;
+    /* Switch to known-working source so that the channel can be disabled */
+    uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+    GCLK->CLKCTRL.bit.GEN = 0;
 
-	/* Disable the generic clock */
-	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
-	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
-		/* Wait for clock to become disabled */
-	}
+    /* Disable the generic clock */
+    GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+    while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN)
+    {
+        /* Wait for clock to become disabled */
+    }
 
-	/* Restore previous configured clock generator */
-	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+    /* Restore previous configured clock generator */
+    GCLK->CLKCTRL.bit.GEN = prev_gen_id;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -432,19 +454,19 @@ void system_gclk_chan_disable(
  * \retval false The Generic Clock channel is disabled
  */
 bool system_gclk_chan_is_enabled(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	bool enabled;
+    bool enabled;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	enabled = GCLK->CLKCTRL.bit.CLKEN;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    enabled = GCLK->CLKCTRL.bit.CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return enabled;
+    return enabled;
 }
 
 /**
@@ -456,17 +478,17 @@ bool system_gclk_chan_is_enabled(
  * \param[in] channel   Generic Clock channel to enable
  */
 void system_gclk_chan_lock(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Lock the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+    /* Lock the generic clock */
+    GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -479,19 +501,19 @@ void system_gclk_chan_lock(
  * \retval false The Generic Clock channel is not locked
  */
 bool system_gclk_chan_is_locked(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	bool locked;
+    bool locked;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    locked = GCLK->CLKCTRL.bit.WRTLOCK;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return locked;
+    return locked;
 }
 
 /**
@@ -505,18 +527,18 @@ bool system_gclk_chan_is_locked(
  * \return The frequency of the generic clock channel, in Hz.
  */
 uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	uint8_t gen_id;
+    uint8_t gen_id;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	gen_id = GCLK->CLKCTRL.bit.GEN;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    gen_id = GCLK->CLKCTRL.bit.GEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	/* Return the clock speed of the associated GCLK generator */
-	return system_gclk_gen_get_hz(gen_id);
+    /* Return the clock speed of the associated GCLK generator */
+    return system_gclk_gen_get_hz(gen_id);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
index 115149730f08..9ca5107c2f2d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock.c
@@ -66,9 +66,9 @@
  * \brief DFLL-specific data container.
  */
 struct _system_clock_dfll_config {
-	uint32_t control;
-	uint32_t val;
-	uint32_t mul;
+    uint32_t control;
+    uint32_t val;
+    uint32_t mul;
 };
 
 /**
@@ -76,7 +76,7 @@ struct _system_clock_dfll_config {
  * \brief DPLL-specific data container.
  */
 struct _system_clock_dpll_config {
-	uint32_t frequency;
+    uint32_t frequency;
 };
 
 
@@ -85,7 +85,7 @@ struct _system_clock_dpll_config {
  * \brief XOSC-specific data container.
  */
 struct _system_clock_xosc_config {
-	uint32_t frequency;
+    uint32_t frequency;
 };
 
 /**
@@ -93,14 +93,14 @@ struct _system_clock_xosc_config {
  * \brief System clock module data container.
  */
 struct _system_clock_module {
-	volatile struct _system_clock_dfll_config dfll;
+    volatile struct _system_clock_dfll_config dfll;
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	volatile struct _system_clock_dpll_config dpll;
+    volatile struct _system_clock_dpll_config dpll;
 #endif
 
-	volatile struct _system_clock_xosc_config xosc;
-	volatile struct _system_clock_xosc_config xosc32k;
+    volatile struct _system_clock_xosc_config xosc;
+    volatile struct _system_clock_xosc_config xosc32k;
 };
 
 /**
@@ -108,24 +108,24 @@ struct _system_clock_module {
  * \brief Internal module instance to cache configuration values.
  */
 static struct _system_clock_module _system_clock_inst = {
-		.dfll = {
-			.control     = 0,
-			.val     = 0,
-			.mul     = 0,
-		},
+        .dfll = {
+            .control     = 0,
+            .val     = 0,
+            .mul     = 0,
+        },
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-		.dpll = {
-			.frequency   = 0,
-		},
+        .dpll = {
+            .frequency   = 0,
+        },
 #endif
-		.xosc = {
-			.frequency   = 0,
-		},
-		.xosc32k = {
-			.frequency   = 0,
-		},
-	};
+        .xosc = {
+            .frequency   = 0,
+        },
+        .xosc32k = {
+            .frequency   = 0,
+        },
+    };
 
 /**
  * \internal
@@ -133,9 +133,10 @@ static struct _system_clock_module _system_clock_inst = {
  */
 static inline void _system_dfll_wait_for_sync(void)
 {
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
-		/* Wait for DFLL sync */
-	}
+    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY))
+    {
+        /* Wait for DFLL sync */
+    }
 }
 
 /**
@@ -144,25 +145,26 @@ static inline void _system_dfll_wait_for_sync(void)
  */
 static inline void _system_osc32k_wait_for_sync(void)
 {
-	while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
-		/* Wait for OSC32K sync */
-	}
+    while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY))
+    {
+        /* Wait for OSC32K sync */
+    }
 }
 
 static inline void _system_clock_source_dfll_set_config_errata_9905(void)
 {
 
-	/* Disable ONDEMAND mode while writing configurations */
-	SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
-	_system_dfll_wait_for_sync();
+    /* Disable ONDEMAND mode while writing configurations */
+    SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE;
+    _system_dfll_wait_for_sync();
 
-	SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
-	SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
+    SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
+    SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
 
-	/* Write full configuration to DFLL control register */
-	SYSCTRL->DFLLCTRL.reg = 0;
-	_system_dfll_wait_for_sync();
-	SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+    /* Write full configuration to DFLL control register */
+    SYSCTRL->DFLLCTRL.reg = 0;
+    _system_dfll_wait_for_sync();
+    SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
 }
 
 /**
@@ -175,53 +177,56 @@ static inline void _system_clock_source_dfll_set_config_errata_9905(void)
  * \returns Frequency of the given clock source, in Hz.
  */
 uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		return _system_clock_inst.xosc.frequency;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        return _system_clock_inst.xosc.frequency;
 
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		return 32768UL;
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        return 32768UL;
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		return 32768UL;
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        return 32768UL;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		return _system_clock_inst.xosc32k.frequency;
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        return _system_clock_inst.xosc32k.frequency;
 
-	case SYSTEM_CLOCK_SOURCE_DFLL:
+    case SYSTEM_CLOCK_SOURCE_DFLL:
 
-		/* Check if the DFLL has been configured */
-		if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
-			return 0;
+        /* Check if the DFLL has been configured */
+        if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
+            return 0;
 
-		/* Make sure that the DFLL module is ready */
-		_system_dfll_wait_for_sync();
+        /* Make sure that the DFLL module is ready */
+        _system_dfll_wait_for_sync();
 
-		/* Check if operating in closed loop mode */
-		if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
-			return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
-					(_system_clock_inst.dfll.mul & 0xffff);
-		}
+        /* Check if operating in closed loop mode */
+        if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE)
+        {
+            return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
+                    (_system_clock_inst.dfll.mul & 0xffff);
+        }
 
-		return 48000000UL;
+        return 48000000UL;
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
-			return 0;
-		}
+    case SYSTEM_CLOCK_SOURCE_DPLL:
+        if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE))
+        {
+            return 0;
+        }
 
-		return _system_clock_inst.dpll.frequency;
+        return _system_clock_inst.dpll.frequency;
 #endif
 
-	default:
-		return 0;
-	}
+    default:
+        return 0;
+    }
 }
 
 /**
@@ -233,16 +238,16 @@ uint32_t system_clock_source_get_hz(
  * \param[in] config  OSC8M configuration structure containing the new config
  */
 void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config)
+        struct system_clock_source_osc8m_config *const config)
 {
-	SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
+    SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
 
-	/* Use temporary struct to reduce register access */
-	temp.bit.PRESC    = config->prescaler;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
+    /* Use temporary struct to reduce register access */
+    temp.bit.PRESC    = config->prescaler;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
 
-	SYSCTRL->OSC8M = temp;
+    SYSCTRL->OSC8M = temp;
 }
 
 /**
@@ -254,19 +259,19 @@ void system_clock_source_osc8m_set_config(
  * \param[in] config  OSC32K configuration structure containing the new config
  */
 void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config)
+        struct system_clock_source_osc32k_config *const config)
 {
-	SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
+    SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
 
-	/* Update settings via a temporary struct to reduce register access */
-	temp.bit.EN1K     = config->enable_1khz_output;
-	temp.bit.EN32K    = config->enable_32khz_output;
-	temp.bit.STARTUP  = config->startup_time;
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
+    /* Update settings via a temporary struct to reduce register access */
+    temp.bit.EN1K     = config->enable_1khz_output;
+    temp.bit.EN32K    = config->enable_32khz_output;
+    temp.bit.STARTUP  = config->startup_time;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+    temp.bit.WRTLOCK  = config->write_once;
 
-	SYSCTRL->OSC32K  = temp;
+    SYSCTRL->OSC32K  = temp;
 }
 
 /**
@@ -279,43 +284,50 @@ void system_clock_source_osc32k_set_config(
  *                    the new config
  */
 void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config)
+        struct system_clock_source_xosc_config *const config)
 {
-	SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
-
-	temp.bit.STARTUP = config->startup_time;
-
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
-
-	temp.bit.AMPGC = config->auto_gain_control;
-
-	/* Set gain if automatic gain control is not selected */
-	if (!config->auto_gain_control) {
-		if (config->frequency <= 2000000) {
-			temp.bit.GAIN = 0;
-		} else if (config->frequency <= 4000000) {
-			temp.bit.GAIN = 1;
-		} else if (config->frequency <= 8000000) {
-			temp.bit.GAIN = 2;
-		} else if (config->frequency <= 16000000) {
-			temp.bit.GAIN = 3;
-		} else if (config->frequency <= 32000000) {
-			temp.bit.GAIN = 4;
-		}
-
-	}
-
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-
-	/* Store XOSC frequency for internal use */
-	_system_clock_inst.xosc.frequency = config->frequency;
-
-	SYSCTRL->XOSC = temp;
+    SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
+
+    temp.bit.STARTUP = config->startup_time;
+
+    if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL)
+    {
+        temp.bit.XTALEN = 1;
+    } else {
+        temp.bit.XTALEN = 0;
+    }
+
+    temp.bit.AMPGC = config->auto_gain_control;
+
+    /* Set gain if automatic gain control is not selected */
+    if (!config->auto_gain_control)
+    {
+        if (config->frequency <= 2000000)
+        {
+            temp.bit.GAIN = 0;
+        } else if (config->frequency <= 4000000)
+        {
+            temp.bit.GAIN = 1;
+        } else if (config->frequency <= 8000000)
+        {
+            temp.bit.GAIN = 2;
+        } else if (config->frequency <= 16000000)
+        {
+            temp.bit.GAIN = 3;
+        } else if (config->frequency <= 32000000)
+        {
+            temp.bit.GAIN = 4;
+        }
+
+    }
+
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+
+    /* Store XOSC frequency for internal use */
+    _system_clock_inst.xosc.frequency = config->frequency;
+
+    SYSCTRL->XOSC = temp;
 }
 
 /**
@@ -327,31 +339,32 @@ void system_clock_source_xosc_set_config(
  * \param[in] config  XOSC32K configuration structure containing the new config
  */
 void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config)
+        struct system_clock_source_xosc32k_config *const config)
 {
-	SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
+    SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
 
-	temp.bit.STARTUP = config->startup_time;
+    temp.bit.STARTUP = config->startup_time;
 
-	if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
-		temp.bit.XTALEN = 1;
-	} else {
-		temp.bit.XTALEN = 0;
-	}
+    if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL)
+    {
+        temp.bit.XTALEN = 1;
+    } else {
+        temp.bit.XTALEN = 0;
+    }
 
-	temp.bit.AAMPEN = config->auto_gain_control;
-	temp.bit.EN1K = config->enable_1khz_output;
-	temp.bit.EN32K = config->enable_32khz_output;
+    temp.bit.AAMPEN = config->auto_gain_control;
+    temp.bit.EN1K = config->enable_1khz_output;
+    temp.bit.EN32K = config->enable_32khz_output;
 
-	temp.bit.ONDEMAND = config->on_demand;
-	temp.bit.RUNSTDBY = config->run_in_standby;
-	temp.bit.WRTLOCK  = config->write_once;
+    temp.bit.ONDEMAND = config->on_demand;
+    temp.bit.RUNSTDBY = config->run_in_standby;
+    temp.bit.WRTLOCK  = config->write_once;
 
-	/* Cache the new frequency in case the user needs to check the current
-	 * operating frequency later */
-	_system_clock_inst.xosc32k.frequency = config->frequency;
+    /* Cache the new frequency in case the user needs to check the current
+     * operating frequency later */
+    _system_clock_inst.xosc32k.frequency = config->frequency;
 
-	SYSCTRL->XOSC32K = temp;
+    SYSCTRL->XOSC32K = temp;
 }
 
 /**
@@ -366,40 +379,42 @@ void system_clock_source_xosc32k_set_config(
  * \param[in] config  DFLL configuration structure containing the new config
  */
 void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config)
+        struct system_clock_source_dfll_config *const config)
 {
-	_system_clock_inst.dfll.val =
-			SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
-			SYSCTRL_DFLLVAL_FINE(config->fine_value);
-
-	_system_clock_inst.dfll.control =
-			(uint32_t)config->wakeup_lock     |
-			(uint32_t)config->stable_tracking |
-			(uint32_t)config->quick_lock      |
-			(uint32_t)config->chill_cycle     |
-			((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
-
-	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-
-		_system_clock_inst.dfll.mul =
-				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
-				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
-				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-
-		/* Enable the closed loop mode */
-		_system_clock_inst.dfll.control |= config->loop_mode;
-	}
-	if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
-
-		_system_clock_inst.dfll.mul =
-				SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
-				SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
-				SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
-
-		/* Enable the USB recovery mode */
-		_system_clock_inst.dfll.control |= config->loop_mode |
-				SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC;
-	}
+    _system_clock_inst.dfll.val =
+            SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
+            SYSCTRL_DFLLVAL_FINE(config->fine_value);
+
+    _system_clock_inst.dfll.control =
+            (uint32_t)config->wakeup_lock     |
+            (uint32_t)config->stable_tracking |
+            (uint32_t)config->quick_lock      |
+            (uint32_t)config->chill_cycle     |
+            ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
+
+    if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+
+        _system_clock_inst.dfll.mul =
+                SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+                SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+                SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+        /* Enable the closed loop mode */
+        _system_clock_inst.dfll.control |= config->loop_mode;
+    }
+    if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY)
+    {
+
+        _system_clock_inst.dfll.mul =
+                SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
+                SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step)   |
+                SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
+
+        /* Enable the USB recovery mode */
+        _system_clock_inst.dfll.control |= config->loop_mode |
+                SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC;
+    }
 }
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
@@ -415,47 +430,48 @@ void system_clock_source_dfll_set_config(
  * \param[in] config  DPLL configuration structure containing the new config
  */
 void system_clock_source_dpll_set_config(
-		struct system_clock_source_dpll_config *const config)
+        struct system_clock_source_dpll_config *const config)
 {
 
-	uint32_t tmpldr;
-	uint8_t  tmpldrfrac;
-	uint32_t refclk;
-
-	refclk = config->reference_frequency;
-
-	/* Only reference clock REF1 can be divided */
-	if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
-		refclk = refclk / (2 * (config->reference_divider + 1));
-	}
-
-	/* Calculate LDRFRAC and LDR */
-	tmpldr = (config->output_frequency << 4) / refclk;
-	tmpldrfrac = tmpldr & 0x0f;
-	tmpldr = (tmpldr >> 4) - 1;
-
-	SYSCTRL->DPLLCTRLA.reg =
-			((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
-			((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
-
-	SYSCTRL->DPLLRATIO.reg =
-			SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
-			SYSCTRL_DPLLRATIO_LDR(tmpldr);
-
-	SYSCTRL->DPLLCTRLB.reg =
-			SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
-			((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
-			SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
-			SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
-			((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
-			((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
-			SYSCTRL_DPLLCTRLB_FILTER(config->filter);
-
-	/*
-	 * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
-	 */
-	_system_clock_inst.dpll.frequency =
-			(refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4;
+    uint32_t tmpldr;
+    uint8_t  tmpldrfrac;
+    uint32_t refclk;
+
+    refclk = config->reference_frequency;
+
+    /* Only reference clock REF1 can be divided */
+    if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC)
+    {
+        refclk = refclk / (2 * (config->reference_divider + 1));
+    }
+
+    /* Calculate LDRFRAC and LDR */
+    tmpldr = (config->output_frequency << 4) / refclk;
+    tmpldrfrac = tmpldr & 0x0f;
+    tmpldr = (tmpldr >> 4) - 1;
+
+    SYSCTRL->DPLLCTRLA.reg =
+            ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
+            ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
+
+    SYSCTRL->DPLLRATIO.reg =
+            SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
+            SYSCTRL_DPLLRATIO_LDR(tmpldr);
+
+    SYSCTRL->DPLLCTRLB.reg =
+            SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
+            ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
+            SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
+            SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
+            ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
+            ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
+            SYSCTRL_DPLLCTRLB_FILTER(config->filter);
+
+    /*
+     * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
+     */
+    _system_clock_inst.dpll.frequency =
+            (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4;
 }
 #endif
 
@@ -485,47 +501,51 @@ void system_clock_source_dpll_set_config(
  *                                 source.
  */
 enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range)
+        const enum system_clock_source clock_source,
+        const uint16_t calibration_value,
+        const uint8_t freq_range)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
 
-		if (calibration_value > 0xfff || freq_range > 4) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 0xfff || freq_range > 4)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
-		SYSCTRL->OSC8M.bit.FRANGE = freq_range;
-		break;
+        SYSCTRL->OSC8M.bit.CALIB  = calibration_value;
+        SYSCTRL->OSC8M.bit.FRANGE = freq_range;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
 
-		if (calibration_value > 128) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 128)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		_system_osc32k_wait_for_sync();
-		SYSCTRL->OSC32K.bit.CALIB = calibration_value;
-		break;
+        _system_osc32k_wait_for_sync();
+        SYSCTRL->OSC32K.bit.CALIB = calibration_value;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
 
-		if (calibration_value > 32) {
-			return STATUS_ERR_INVALID_ARG;
-		}
+        if (calibration_value > 32)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
 
-		SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
-		break;
+        SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
+        break;
 
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-		break;
-	}
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+        break;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -541,46 +561,47 @@ enum status_code system_clock_source_write_calibration(
  *                                 device
  */
 enum status_code system_clock_source_enable(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
-		return STATUS_OK;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
+        return STATUS_OK;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
-		_system_clock_source_dfll_set_config_errata_9905();
-		break;
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
+        _system_clock_source_dfll_set_config_errata_9905();
+        break;
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_DPLL:
+        SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
+        break;
 #endif
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Always enabled */
-		return STATUS_OK;
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Always enabled */
+        return STATUS_OK;
 
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -595,46 +616,47 @@ enum status_code system_clock_source_enable(
  *                                 given
  */
 enum status_code system_clock_source_disable(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
-		break;
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
+        break;
 
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
-		SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
-		break;
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
+        SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
+        break;
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
-		break;
+    case SYSTEM_CLOCK_SOURCE_DPLL:
+        SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
+        break;
 #endif
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Not possible to disable */
 
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
 
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -650,52 +672,54 @@ enum status_code system_clock_source_disable(
  * \retval false  Clock source is disabled or not yet ready
  */
 bool system_clock_source_is_ready(
-		const enum system_clock_source clock_source)
+        const enum system_clock_source clock_source)
 {
-	uint32_t mask = 0;
-
-	switch (clock_source) {
-	case SYSTEM_CLOCK_SOURCE_OSC8M:
-		mask = SYSCTRL_PCLKSR_OSC8MRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_OSC32K:
-		mask = SYSCTRL_PCLKSR_OSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC:
-		mask = SYSCTRL_PCLKSR_XOSCRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_XOSC32K:
-		mask = SYSCTRL_PCLKSR_XOSC32KRDY;
-		break;
-
-	case SYSTEM_CLOCK_SOURCE_DFLL:
-		if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-			mask = (SYSCTRL_PCLKSR_DFLLRDY |
-			        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
-		} else {
-			mask = SYSCTRL_PCLKSR_DFLLRDY;
-		}
-		break;
+    uint32_t mask = 0;
+
+    switch (clock_source)
+    {
+    case SYSTEM_CLOCK_SOURCE_OSC8M:
+        mask = SYSCTRL_PCLKSR_OSC8MRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_OSC32K:
+        mask = SYSCTRL_PCLKSR_OSC32KRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC:
+        mask = SYSCTRL_PCLKSR_XOSCRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_XOSC32K:
+        mask = SYSCTRL_PCLKSR_XOSC32KRDY;
+        break;
+
+    case SYSTEM_CLOCK_SOURCE_DFLL:
+        if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+        {
+            mask = (SYSCTRL_PCLKSR_DFLLRDY |
+                    SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
+        } else {
+            mask = SYSCTRL_PCLKSR_DFLLRDY;
+        }
+        break;
 
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	case SYSTEM_CLOCK_SOURCE_DPLL:
-		return ((SYSCTRL->DPLLSTATUS.reg &
-				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
-				(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
+    case SYSTEM_CLOCK_SOURCE_DPLL:
+        return ((SYSCTRL->DPLLSTATUS.reg &
+                (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
+                (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
 #endif
 
-	case SYSTEM_CLOCK_SOURCE_ULP32K:
-		/* Not possible to disable */
-		return true;
+    case SYSTEM_CLOCK_SOURCE_ULP32K:
+        /* Not possible to disable */
+        return true;
 
-	default:
-		return false;
-	}
+    default:
+        return false;
+    }
 
-	return ((SYSCTRL->PCLKSR.reg & mask) == mask);
+    return ((SYSCTRL->PCLKSR.reg & mask) == mask);
 }
 
 /* Include some checks for conf_clocks.h validation */
@@ -707,16 +731,17 @@ bool system_clock_source_is_ready(
  * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
  */
 #  define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
-	if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
-		struct system_gclk_gen_config gclk_conf;                          \
-		system_gclk_gen_get_config_defaults(&gclk_conf);                  \
-		gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
-		gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
-		gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
-		gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
-		system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
-		system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
-	}
+    if (CONF_CLOCK_GCLK_##n##_ENABLE == true)
+    { \
+        struct system_gclk_gen_config gclk_conf;                          \
+        system_gclk_gen_get_config_defaults(&gclk_conf);                  \
+        gclk_conf.source_clock    = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE;   \
+        gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER;      \
+        gclk_conf.run_in_standby  = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
+        gclk_conf.output_enable   = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE;  \
+        system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf);       \
+        system_gclk_gen_enable(GCLK_GENERATOR_##n);                       \
+    }
 
 /** \internal
  *
@@ -724,7 +749,7 @@ bool system_clock_source_is_ready(
  * provided that it is not the main Generic Clock Generator channel.
  */
 #  define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
-		if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
+        if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
 #endif
 
 /** \internal
@@ -734,30 +759,31 @@ bool system_clock_source_is_ready(
  */
 static void _switch_peripheral_gclk(void)
 {
-	uint32_t gclk_id;
-	struct system_gclk_chan_config gclk_conf;
+    uint32_t gclk_id;
+    struct system_gclk_chan_config gclk_conf;
 
 #if CONF_CLOCK_GCLK_1_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_1;
+    gclk_conf.source_generator = GCLK_GENERATOR_1;
 #elif CONF_CLOCK_GCLK_2_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_2;
+    gclk_conf.source_generator = GCLK_GENERATOR_2;
 #elif CONF_CLOCK_GCLK_3_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_3;
+    gclk_conf.source_generator = GCLK_GENERATOR_3;
 #elif CONF_CLOCK_GCLK_4_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_4;
+    gclk_conf.source_generator = GCLK_GENERATOR_4;
 #elif CONF_CLOCK_GCLK_5_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_5;
+    gclk_conf.source_generator = GCLK_GENERATOR_5;
 #elif CONF_CLOCK_GCLK_6_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_6;
+    gclk_conf.source_generator = GCLK_GENERATOR_6;
 #elif CONF_CLOCK_GCLK_7_ENABLE == false
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
+    gclk_conf.source_generator = GCLK_GENERATOR_7;
 #else
-	gclk_conf.source_generator = GCLK_GENERATOR_7;
+    gclk_conf.source_generator = GCLK_GENERATOR_7;
 #endif
 
-	for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) {
-		system_gclk_chan_set_config(gclk_id, &gclk_conf);
-	}
+    for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++)
+    {
+        system_gclk_chan_set_config(gclk_id, &gclk_conf);
+    }
 }
 
 /**
@@ -773,266 +799,279 @@ static void _switch_peripheral_gclk(void)
  */
 void system_clock_init(void)
 {
-	/* Various bits in the INTFLAG register can be set to one at startup.
-	   This will ensure that these bits are cleared */
-	SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
-			SYSCTRL_INTFLAG_DFLLRDY;
+    /* Various bits in the INTFLAG register can be set to one at startup.
+       This will ensure that these bits are cleared */
+    SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
+            SYSCTRL_INTFLAG_DFLLRDY;
 
-	system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
+    system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
 
-	/* Switch all peripheral clock to a not enabled general clock to save power. */
-	_switch_peripheral_gclk();
+    /* Switch all peripheral clock to a not enabled general clock to save power. */
+    _switch_peripheral_gclk();
 
-	/* XOSC */
+    /* XOSC */
 #if CONF_CLOCK_XOSC_ENABLE == true
-	struct system_clock_source_xosc_config xosc_conf;
-	system_clock_source_xosc_get_config_defaults(&xosc_conf);
-
-	xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
-	xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
-	xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
-	xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
-	xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
-	xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
-
-	system_clock_source_xosc_set_config(&xosc_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
+    struct system_clock_source_xosc_config xosc_conf;
+    system_clock_source_xosc_get_config_defaults(&xosc_conf);
+
+    xosc_conf.external_clock    = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
+    xosc_conf.startup_time      = CONF_CLOCK_XOSC_STARTUP_TIME;
+    xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
+    xosc_conf.frequency         = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
+    xosc_conf.on_demand         = CONF_CLOCK_XOSC_ON_DEMAND;
+    xosc_conf.run_in_standby    = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
+
+    system_clock_source_xosc_set_config(&xosc_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
 #endif
 
 
-	/* XOSC32K */
+    /* XOSC32K */
 #if CONF_CLOCK_XOSC32K_ENABLE == true
-	struct system_clock_source_xosc32k_config xosc32k_conf;
-	system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
-
-	xosc32k_conf.frequency           = 32768UL;
-	xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
-	xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
-	xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
-	xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
-	xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
-	xosc32k_conf.on_demand           = false;
-	xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
-
-	system_clock_source_xosc32k_set_config(&xosc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
-	if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
-		SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
-	}
+    struct system_clock_source_xosc32k_config xosc32k_conf;
+    system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
+
+    xosc32k_conf.frequency           = 32768UL;
+    xosc32k_conf.external_clock      = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
+    xosc32k_conf.startup_time        = CONF_CLOCK_XOSC32K_STARTUP_TIME;
+    xosc32k_conf.auto_gain_control   = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
+    xosc32k_conf.enable_1khz_output  = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
+    xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
+    xosc32k_conf.on_demand           = false;
+    xosc32k_conf.run_in_standby      = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
+
+    system_clock_source_xosc32k_set_config(&xosc32k_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+    if (CONF_CLOCK_XOSC32K_ON_DEMAND)
+    {
+        SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
+    }
 #endif
 
 
-	/* OSCK32K */
+    /* OSCK32K */
 #if CONF_CLOCK_OSC32K_ENABLE == true
-	SYSCTRL->OSC32K.bit.CALIB =
-			((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> 
-			SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful);
+    SYSCTRL->OSC32K.bit.CALIB =
+            ((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >>
+            SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful);
 
-	struct system_clock_source_osc32k_config osc32k_conf;
-	system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
+    struct system_clock_source_osc32k_config osc32k_conf;
+    system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
 
-	osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
-	osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
-	osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
-	osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
-	osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
+    osc32k_conf.startup_time        = CONF_CLOCK_OSC32K_STARTUP_TIME;
+    osc32k_conf.enable_1khz_output  = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
+    osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
+    osc32k_conf.on_demand           = CONF_CLOCK_OSC32K_ON_DEMAND;
+    osc32k_conf.run_in_standby      = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
 
-	system_clock_source_osc32k_set_config(&osc32k_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
+    system_clock_source_osc32k_set_config(&osc32k_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
 #endif
 
 
-	/* DFLL Config (Open and Closed Loop) */
+    /* DFLL Config (Open and Closed Loop) */
 #if CONF_CLOCK_DFLL_ENABLE == true
-	struct system_clock_source_dfll_config dfll_conf;
-	system_clock_source_dfll_get_config_defaults(&dfll_conf);
+    struct system_clock_source_dfll_config dfll_conf;
+    system_clock_source_dfll_get_config_defaults(&dfll_conf);
 
-	dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
-	dfll_conf.on_demand      = false;
+    dfll_conf.loop_mode      = CONF_CLOCK_DFLL_LOOP_MODE;
+    dfll_conf.on_demand      = false;
 
-	/* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping 
-	   in DFLL.COARSE helps to output a frequency close to 48 MHz.*/
+    /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping
+       in DFLL.COARSE helps to output a frequency close to 48 MHz.*/
 #define NVM_DFLL_COARSE_POS    58 /* DFLL48M Coarse calibration value bit position.*/
 #define NVM_DFLL_COARSE_SIZE   6  /* DFLL48M Coarse calibration value bit size.*/
 
-	uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_DFLL_COARSE_POS / 32))
-		>> (NVM_DFLL_COARSE_POS % 32))
-		& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
-	/* In some revision chip, the coarse calibration value is not correct. */
-	if (coarse == 0x3f) {
-		coarse = 0x1f;
-	}
-	dfll_conf.coarse_value = coarse;
-
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
-		dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
-	}
+    uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_DFLL_COARSE_POS / 32))
+        >> (NVM_DFLL_COARSE_POS % 32))
+        & ((1 << NVM_DFLL_COARSE_SIZE) - 1);
+    /* In some revision chip, the coarse calibration value is not correct. */
+    if (coarse == 0x3f)
+    {
+        coarse = 0x1f;
+    }
+    dfll_conf.coarse_value = coarse;
+
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN)
+    {
+        dfll_conf.fine_value   = CONF_CLOCK_DFLL_FINE_VALUE;
+    }
 
 #  if CONF_CLOCK_DFLL_QUICK_LOCK == true
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+    dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
 #  else
-	dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
+    dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
 #  endif
 
 #  if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+    dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
 #  else
-	dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
+    dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
 #  endif
 
 #  if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+    dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
 #  else
-	dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
+    dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
 #  endif
 
 #  if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+    dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
 #  else
-	dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+    dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
 #  endif
 
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
-	}
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+        dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
+    }
 
-	dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
-	dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
+    dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
+    dfll_conf.fine_max_step   = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
 
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
-		dfll_conf.fine_max_step   = 10; 
-		dfll_conf.fine_value   = 0x1ff;
-		dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-		dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-		dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-		dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY)
+    {
+        dfll_conf.fine_max_step   = 10;
+        dfll_conf.fine_value   = 0x1ff;
+        dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+        dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+        dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+        dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
 
-		dfll_conf.multiply_factor = 48000;
-	}
+        dfll_conf.multiply_factor = 48000;
+    }
 
-	system_clock_source_dfll_set_config(&dfll_conf);
+    system_clock_source_dfll_set_config(&dfll_conf);
 #endif
 
 
-	/* OSC8M */
-	struct system_clock_source_osc8m_config osc8m_conf;
-	system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
+    /* OSC8M */
+    struct system_clock_source_osc8m_config osc8m_conf;
+    system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
 
-	osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
-	osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
-	osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
+    osc8m_conf.prescaler       = CONF_CLOCK_OSC8M_PRESCALER;
+    osc8m_conf.on_demand       = CONF_CLOCK_OSC8M_ON_DEMAND;
+    osc8m_conf.run_in_standby  = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
 
-	system_clock_source_osc8m_set_config(&osc8m_conf);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
+    system_clock_source_osc8m_set_config(&osc8m_conf);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
 
 
-	/* GCLK */
+    /* GCLK */
 #if CONF_CLOCK_CONFIGURE_GCLK == true
-	system_gclk_init();
+    system_gclk_init();
 
-	/* Configure all GCLK generators except for the main generator, which
-	 * is configured later after all other clock systems are set up */
-	MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
+    /* Configure all GCLK generators except for the main generator, which
+     * is configured later after all other clock systems are set up */
+    MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
 
 #  if CONF_CLOCK_DFLL_ENABLE == true
-	/* Enable DFLL reference clock if in closed loop mode */
-	if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
-		struct system_gclk_chan_config dfll_gclk_chan_conf;
-
-		system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
-		dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
-	}
+    /* Enable DFLL reference clock if in closed loop mode */
+    if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED)
+    {
+        struct system_gclk_chan_config dfll_gclk_chan_conf;
+
+        system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
+        dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
+        system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
+        system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
+    }
 #  endif
 
 #  if CONF_CLOCK_DPLL_ENABLE == true
-	/* Enable DPLL internal lock timer and reference clock */
-	struct system_gclk_chan_config dpll_gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf);
-	if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) {
-		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K);
-	}
-
-	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
-		dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR;
-		system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf);
-		system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
-	}
+    /* Enable DPLL internal lock timer and reference clock */
+    struct system_gclk_chan_config dpll_gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf);
+    if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT)
+    {
+        dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR;
+        system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf);
+        system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K);
+    }
+
+    if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK)
+    {
+        dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR;
+        system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf);
+        system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL);
+    }
 #  endif
 #endif
 
 
-	/* DFLL Enable (Open and Closed Loop) */
+    /* DFLL Enable (Open and Closed Loop) */
 #if CONF_CLOCK_DFLL_ENABLE == true
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
-	if (CONF_CLOCK_DFLL_ON_DEMAND) {
-		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
-	}
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+    if (CONF_CLOCK_DFLL_ON_DEMAND)
+    {
+        SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+    }
 #endif
 
-	/* DPLL */
+    /* DPLL */
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
 #  if (CONF_CLOCK_DPLL_ENABLE == true)
 
-	/* Enable DPLL reference clock */
-	if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) {
-		/* XOSC32K should have been enabled for DPLL_REF0 */
-		Assert(CONF_CLOCK_XOSC32K_ENABLE);
-	} else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) {
-		/* XOSC should have been enabled for DPLL_REF1 */
-		Assert(CONF_CLOCK_XOSC_ENABLE);
-	}
-	else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) {
-		/* GCLK should have been enabled */
-		Assert(CONF_CLOCK_CONFIGURE_GCLK);
-	}
-	else {
-		Assert(false);
-	}
-
-	struct system_clock_source_dpll_config dpll_config;
-	system_clock_source_dpll_get_config_defaults(&dpll_config);
-
-	dpll_config.on_demand        = false;
-	dpll_config.run_in_standby   = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
-	dpll_config.lock_bypass      = CONF_CLOCK_DPLL_LOCK_BYPASS;
-	dpll_config.wake_up_fast     = CONF_CLOCK_DPLL_WAKE_UP_FAST;
-	dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
-
-	dpll_config.filter           = CONF_CLOCK_DPLL_FILTER;
-	dpll_config.lock_time        = CONF_CLOCK_DPLL_LOCK_TIME;
-
-	dpll_config.reference_clock     = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
-	dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
-	dpll_config.reference_divider   = CONF_CLOCK_DPLL_REFERENCE_DIVIDER;
-	dpll_config.output_frequency    = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
-
-	system_clock_source_dpll_set_config(&dpll_config);
-	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
-	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
-	if (CONF_CLOCK_DPLL_ON_DEMAND) {
-		SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
-	}
+    /* Enable DPLL reference clock */
+    if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K)
+    {
+        /* XOSC32K should have been enabled for DPLL_REF0 */
+        Assert(CONF_CLOCK_XOSC32K_ENABLE);
+    } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC)
+    {
+        /* XOSC should have been enabled for DPLL_REF1 */
+        Assert(CONF_CLOCK_XOSC_ENABLE);
+    }
+    else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK)
+    {
+        /* GCLK should have been enabled */
+        Assert(CONF_CLOCK_CONFIGURE_GCLK);
+    }
+    else {
+        Assert(false);
+    }
+
+    struct system_clock_source_dpll_config dpll_config;
+    system_clock_source_dpll_get_config_defaults(&dpll_config);
+
+    dpll_config.on_demand        = false;
+    dpll_config.run_in_standby   = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
+    dpll_config.lock_bypass      = CONF_CLOCK_DPLL_LOCK_BYPASS;
+    dpll_config.wake_up_fast     = CONF_CLOCK_DPLL_WAKE_UP_FAST;
+    dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
+
+    dpll_config.filter           = CONF_CLOCK_DPLL_FILTER;
+    dpll_config.lock_time        = CONF_CLOCK_DPLL_LOCK_TIME;
+
+    dpll_config.reference_clock     = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
+    dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
+    dpll_config.reference_divider   = CONF_CLOCK_DPLL_REFERENCE_DIVIDER;
+    dpll_config.output_frequency    = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
+
+    system_clock_source_dpll_set_config(&dpll_config);
+    system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
+    while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
+    if (CONF_CLOCK_DPLL_ON_DEMAND)
+    {
+        SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
+    }
 
 #  endif
 #endif
 
-	/* CPU and BUS clocks */
-	system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
+    /* CPU and BUS clocks */
+    system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
 
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
-	system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
+    system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER);
 
-	/* GCLK 0 */
+    /* GCLK 0 */
 #if CONF_CLOCK_CONFIGURE_GCLK == true
-	/* Configure the main GCLK last as it might depend on other generators */
-	_CONF_CLOCK_GCLK_CONFIG(0, ~);
+    /* Configure the main GCLK last as it might depend on other generators */
+    _CONF_CLOCK_GCLK_CONFIG(0, ~);
 #endif
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
index db993049a600..ce2bfe0ac259 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/clock_feature.h
@@ -98,14 +98,14 @@ extern "C" {
  *
  * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition
  * <table>
- *	<tr>
- *		<th>Driver Feature Macro</th>
- *		<th>Supported devices</th>
- *	</tr>
- *	<tr>
- *		<td>FEATURE_SYSTEM_CLOCK_DPLL</td>
- *		<td>SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1</td>
- *	</tr>
+ *  <tr>
+ *      <th>Driver Feature Macro</th>
+ *      <th>Supported devices</th>
+ *  </tr>
+ *  <tr>
+ *      <td>FEATURE_SYSTEM_CLOCK_DPLL</td>
+ *      <td>SAM D21, SAM R21, SAM D10, SAM D11, SAM DA1</td>
+ *  </tr>
  * </table>
  * \note The specific features are only available in the driver when the
  * selected device supports those features.
@@ -286,22 +286,22 @@ extern "C" {
  * clock cycles.
  */
 enum system_xosc32k_startup {
-	/** Wait zero clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_0,
-	/** Wait 32 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_32,
-	/** Wait 2048 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_4096,
-	/** Wait 16384 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_32768,
-	/** Wait 65536 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_65536,
-	/** Wait 131072 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC32K_STARTUP_131072,
+    /** Wait zero clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_0,
+    /** Wait 32 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_32,
+    /** Wait 2048 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_2048,
+    /** Wait 4096 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_4096,
+    /** Wait 16384 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_16384,
+    /** Wait 32768 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_32768,
+    /** Wait 65536 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_65536,
+    /** Wait 131072 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC32K_STARTUP_131072,
 };
 
 /**
@@ -311,38 +311,38 @@ enum system_xosc32k_startup {
  * cycles.
  */
 enum system_xosc_startup {
-	/** Wait one clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_1,
-	/** Wait two clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_2,
-	/** Wait four clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_4,
-	/** Wait eight clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_8,
-	/** Wait 16 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_16,
-	/** Wait 32 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_32,
-	/** Wait 64 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_64,
-	/** Wait 128 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_128,
-	/** Wait 256 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_256,
-	/** Wait 512 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_512,
-	/** Wait 1024 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_1024,
-	/** Wait 2048 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_2048,
-	/** Wait 4096 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_4096,
-	/** Wait 8192 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_8192,
-	/** Wait 16384 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_16384,
-	/** Wait 32768 clock cycles until the clock source is considered stable */
-	SYSTEM_XOSC_STARTUP_32768,
+    /** Wait one clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_1,
+    /** Wait two clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_2,
+    /** Wait four clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_4,
+    /** Wait eight clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_8,
+    /** Wait 16 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_16,
+    /** Wait 32 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_32,
+    /** Wait 64 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_64,
+    /** Wait 128 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_128,
+    /** Wait 256 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_256,
+    /** Wait 512 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_512,
+    /** Wait 1024 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_1024,
+    /** Wait 2048 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_2048,
+    /** Wait 4096 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_4096,
+    /** Wait 8192 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_8192,
+    /** Wait 16384 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_16384,
+    /** Wait 32768 clock cycles until the clock source is considered stable */
+    SYSTEM_XOSC_STARTUP_32768,
 };
 
 /**
@@ -352,22 +352,22 @@ enum system_xosc_startup {
  * OSC32K clock cycles.
  */
 enum system_osc32k_startup {
-	/** Wait three clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_3,
-	/** Wait four clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_4,
-	/** Wait six clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_6,
-	/** Wait ten clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_10,
-	/** Wait 18 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_18,
-	/** Wait 34 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_34,
-	/** Wait 66 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_66,
-	/** Wait 130 clock cycles until the clock source is considered stable */
-	SYSTEM_OSC32K_STARTUP_130,
+    /** Wait three clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_3,
+    /** Wait four clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_4,
+    /** Wait six clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_6,
+    /** Wait ten clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_10,
+    /** Wait 18 clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_18,
+    /** Wait 34 clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_34,
+    /** Wait 66 clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_66,
+    /** Wait 130 clock cycles until the clock source is considered stable */
+    SYSTEM_OSC32K_STARTUP_130,
 };
 
 /**
@@ -376,14 +376,14 @@ enum system_osc32k_startup {
  * Available prescalers for the internal 8MHz (nominal) system clock.
  */
 enum system_osc8m_div {
-	/** Do not divide the 8MHz RC oscillator output */
-	SYSTEM_OSC8M_DIV_1,
-	/** Divide the 8MHz RC oscillator output by two */
-	SYSTEM_OSC8M_DIV_2,
-	/** Divide the 8MHz RC oscillator output by four */
-	SYSTEM_OSC8M_DIV_4,
-	/** Divide the 8MHz RC oscillator output by eight */
-	SYSTEM_OSC8M_DIV_8,
+    /** Do not divide the 8MHz RC oscillator output */
+    SYSTEM_OSC8M_DIV_1,
+    /** Divide the 8MHz RC oscillator output by two */
+    SYSTEM_OSC8M_DIV_2,
+    /** Divide the 8MHz RC oscillator output by four */
+    SYSTEM_OSC8M_DIV_4,
+    /** Divide the 8MHz RC oscillator output by eight */
+    SYSTEM_OSC8M_DIV_8,
 };
 
 /**
@@ -392,14 +392,14 @@ enum system_osc8m_div {
  * Internal 8MHz RC oscillator frequency range setting.
  */
 enum system_osc8m_frequency_range {
-	/** Frequency range 4MHz to 6MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
-	/** Frequency range 6MHz to 8MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
-	/** Frequency range 8MHz to 11MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
-	/** Frequency range 11MHz to 15MHz */
-	SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
+    /** Frequency range 4MHz to 6MHz */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6,
+    /** Frequency range 6MHz to 8MHz */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8,
+    /** Frequency range 8MHz to 11MHz */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11,
+    /** Frequency range 11MHz to 15MHz */
+    SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15,
 };
 
 /**
@@ -408,22 +408,22 @@ enum system_osc8m_frequency_range {
  * Available division ratios for the CPU and APB/AHB bus clocks.
  */
 enum system_main_clock_div {
-	/** Divide Main clock by one */
-	SYSTEM_MAIN_CLOCK_DIV_1,
-	/** Divide Main clock by two */
-	SYSTEM_MAIN_CLOCK_DIV_2,
-	/** Divide Main clock by four */
-	SYSTEM_MAIN_CLOCK_DIV_4,
-	/** Divide Main clock by eight */
-	SYSTEM_MAIN_CLOCK_DIV_8,
-	/** Divide Main clock by 16 */
-	SYSTEM_MAIN_CLOCK_DIV_16,
-	/** Divide Main clock by 32 */
-	SYSTEM_MAIN_CLOCK_DIV_32,
-	/** Divide Main clock by 64 */
-	SYSTEM_MAIN_CLOCK_DIV_64,
-	/** Divide Main clock by 128 */
-	SYSTEM_MAIN_CLOCK_DIV_128,
+    /** Divide Main clock by one */
+    SYSTEM_MAIN_CLOCK_DIV_1,
+    /** Divide Main clock by two */
+    SYSTEM_MAIN_CLOCK_DIV_2,
+    /** Divide Main clock by four */
+    SYSTEM_MAIN_CLOCK_DIV_4,
+    /** Divide Main clock by eight */
+    SYSTEM_MAIN_CLOCK_DIV_8,
+    /** Divide Main clock by 16 */
+    SYSTEM_MAIN_CLOCK_DIV_16,
+    /** Divide Main clock by 32 */
+    SYSTEM_MAIN_CLOCK_DIV_32,
+    /** Divide Main clock by 64 */
+    SYSTEM_MAIN_CLOCK_DIV_64,
+    /** Divide Main clock by 128 */
+    SYSTEM_MAIN_CLOCK_DIV_128,
 };
 
 /**
@@ -432,10 +432,10 @@ enum system_main_clock_div {
  * Available external clock source types.
  */
 enum system_clock_external {
-	/** The external clock source is a crystal oscillator */
-	SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
-	/** The connected clock source is an external logic level clock signal */
-	SYSTEM_CLOCK_EXTERNAL_CLOCK,
+    /** The external clock source is a crystal oscillator */
+    SYSTEM_CLOCK_EXTERNAL_CRYSTAL,
+    /** The connected clock source is an external logic level clock signal */
+    SYSTEM_CLOCK_EXTERNAL_CLOCK,
 };
 
 /**
@@ -444,18 +444,18 @@ enum system_clock_external {
  * Available operating modes of the DFLL clock source module.
  */
 enum system_clock_dfll_loop_mode {
-	/** The DFLL is operating in open loop mode with no feedback */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
-	/** The DFLL is operating in closed loop mode with frequency feedback from
-	 *  a low frequency reference clock
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
+    /** The DFLL is operating in open loop mode with no feedback */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN,
+    /** The DFLL is operating in closed loop mode with frequency feedback from
+     *  a low frequency reference clock
+     */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE,
 
 #ifdef SYSCTRL_DFLLCTRL_USBCRM
-	/** The DFLL is operating in USB recovery mode with frequency feedback
-	 *  from USB SOF.
-	 */
-	SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
+    /** The DFLL is operating in USB recovery mode with frequency feedback
+     *  from USB SOF.
+     */
+    SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM,
 #endif
 };
 
@@ -465,10 +465,10 @@ enum system_clock_dfll_loop_mode {
  * DFLL lock behavior modes on device wake-up from sleep.
  */
 enum system_clock_dfll_wakeup_lock {
-	/** Keep DFLL lock when the device wakes from sleep */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
-	/** Lose DFLL lock when the devices wakes from sleep */
-	SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
+    /** Keep DFLL lock when the device wakes from sleep */
+    SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP,
+    /** Lose DFLL lock when the devices wakes from sleep */
+    SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW,
 };
 
 /**
@@ -477,10 +477,10 @@ enum system_clock_dfll_wakeup_lock {
  * DFLL fine tracking behavior modes after a lock has been acquired.
  */
 enum system_clock_dfll_stable_tracking {
-	/** Keep tracking after the DFLL has gotten a fine lock */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
-	/** Stop tracking after the DFLL has gotten a fine lock */
-	SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
+    /** Keep tracking after the DFLL has gotten a fine lock */
+    SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK,
+    /** Stop tracking after the DFLL has gotten a fine lock */
+    SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE,
 };
 
 /**
@@ -491,10 +491,10 @@ enum system_clock_dfll_stable_tracking {
  * the output to stabilize after a change in the input clock source.
  */
 enum system_clock_dfll_chill_cycle {
-	/** Enable a chill cycle, where the DFLL output frequency is not measured */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
-	/** Disable a chill cycle, where the DFLL output frequency is not measured */
-	SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
+    /** Enable a chill cycle, where the DFLL output frequency is not measured */
+    SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE,
+    /** Disable a chill cycle, where the DFLL output frequency is not measured */
+    SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS,
 };
 
 /**
@@ -504,10 +504,10 @@ enum system_clock_dfll_chill_cycle {
  * the DFLL output frequency at the expense of accuracy.
  */
 enum system_clock_dfll_quick_lock {
-	/** Enable the QuickLock feature for looser lock requirements on the DFLL */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
-	/** Disable the QuickLock feature for strict lock requirements on the DFLL */
-	SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
+    /** Enable the QuickLock feature for looser lock requirements on the DFLL */
+    SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE,
+    /** Disable the QuickLock feature for strict lock requirements on the DFLL */
+    SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS,
 };
 
 /**
@@ -516,27 +516,27 @@ enum system_clock_dfll_quick_lock {
  * Clock sources available to the GCLK generators.
  */
 enum system_clock_source {
-	/** Internal 8MHz RC oscillator */
-	SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
-	/** Internal 32KHz RC oscillator */
-	SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
-	/** External oscillator */
-	SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
-	/** External 32KHz oscillator */
-	SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
-	/** Digital Frequency Locked Loop (DFLL) */
-	SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
-	/** Internal Ultra Low Power 32KHz oscillator */
-	SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
-	/** Generator input pad */
-	SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
-	/** Generic clock generator one output */
-	SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
+    /** Internal 8MHz RC oscillator */
+    SYSTEM_CLOCK_SOURCE_OSC8M    = GCLK_SOURCE_OSC8M,
+    /** Internal 32KHz RC oscillator */
+    SYSTEM_CLOCK_SOURCE_OSC32K   = GCLK_SOURCE_OSC32K,
+    /** External oscillator */
+    SYSTEM_CLOCK_SOURCE_XOSC     = GCLK_SOURCE_XOSC ,
+    /** External 32KHz oscillator */
+    SYSTEM_CLOCK_SOURCE_XOSC32K  = GCLK_SOURCE_XOSC32K,
+    /** Digital Frequency Locked Loop (DFLL) */
+    SYSTEM_CLOCK_SOURCE_DFLL     = GCLK_SOURCE_DFLL48M,
+    /** Internal Ultra Low Power 32KHz oscillator */
+    SYSTEM_CLOCK_SOURCE_ULP32K   = GCLK_SOURCE_OSCULP32K,
+    /** Generator input pad */
+    SYSTEM_CLOCK_SOURCE_GCLKIN     = GCLK_SOURCE_GCLKIN,
+    /** Generic clock generator one output */
+    SYSTEM_CLOCK_SOURCE_GCLKGEN1   = GCLK_SOURCE_GCLKGEN1,
 #ifdef FEATURE_SYSTEM_CLOCK_DPLL
-	/** Digital Phase Locked Loop (DPLL).
-	 * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
-	 */
-	SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
+    /** Digital Phase Locked Loop (DPLL).
+     * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it.
+     */
+    SYSTEM_CLOCK_SOURCE_DPLL     = GCLK_SOURCE_FDPLL,
 #endif
 };
 
@@ -546,12 +546,12 @@ enum system_clock_source {
  * Available bus clock domains on the APB bus.
  */
 enum system_clock_apb_bus {
-	/** Peripheral bus A on the APB bus */
-	SYSTEM_CLOCK_APB_APBA,
-	/** Peripheral bus B on the APB bus */
-	SYSTEM_CLOCK_APB_APBB,
-	/** Peripheral bus C on the APB bus */
-	SYSTEM_CLOCK_APB_APBC,
+    /** Peripheral bus A on the APB bus */
+    SYSTEM_CLOCK_APB_APBA,
+    /** Peripheral bus B on the APB bus */
+    SYSTEM_CLOCK_APB_APBB,
+    /** Peripheral bus C on the APB bus */
+    SYSTEM_CLOCK_APB_APBC,
 };
 
 /**
@@ -560,19 +560,19 @@ enum system_clock_apb_bus {
  * External oscillator clock configuration structure.
  */
 struct system_clock_source_xosc_config {
-	/** External clock type */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time */
-	enum system_xosc_startup startup_time;
-	/** Enable automatic amplitude gain control */
-	bool auto_gain_control;
-	/** External clock/crystal frequency */
-	uint32_t frequency;
-	/** Keep the XOSC enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
+    /** External clock type */
+    enum system_clock_external external_clock;
+    /** Crystal oscillator start-up time */
+    enum system_xosc_startup startup_time;
+    /** Enable automatic amplitude gain control */
+    bool auto_gain_control;
+    /** External clock/crystal frequency */
+    uint32_t frequency;
+    /** Keep the XOSC enabled in standby sleep mode */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the XOSC won't run
+     * until requested by a peripheral. */
+    bool on_demand;
 };
 
 /**
@@ -581,26 +581,26 @@ struct system_clock_source_xosc_config {
  * External 32KHz oscillator clock configuration structure.
  */
 struct system_clock_source_xosc32k_config {
-	/** External clock type */
-	enum system_clock_external external_clock;
-	/** Crystal oscillator start-up time */
-	enum system_xosc32k_startup startup_time;
-	/** Enable automatic amplitude control */
-	bool auto_gain_control;
-	/** Enable 1KHz output */
-	bool enable_1khz_output;
-	/** Enable 32KHz output */
-	bool enable_32khz_output;
-	/** External clock/crystal frequency */
-	uint32_t frequency;
-	/** Keep the XOSC32K enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the XOSC32K won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock */
-	bool write_once;
+    /** External clock type */
+    enum system_clock_external external_clock;
+    /** Crystal oscillator start-up time */
+    enum system_xosc32k_startup startup_time;
+    /** Enable automatic amplitude control */
+    bool auto_gain_control;
+    /** Enable 1KHz output */
+    bool enable_1khz_output;
+    /** Enable 32KHz output */
+    bool enable_32khz_output;
+    /** External clock/crystal frequency */
+    uint32_t frequency;
+    /** Keep the XOSC32K enabled in standby sleep mode */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the XOSC32K won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Lock configuration after it has been written,
+     *  a device reset will release the lock */
+    bool write_once;
 };
 
 /**
@@ -609,13 +609,13 @@ struct system_clock_source_xosc32k_config {
  * Internal 8MHz (nominal) oscillator configuration structure.
  */
 struct system_clock_source_osc8m_config {
-	/** Internal 8MHz RC oscillator prescaler */
-	enum system_osc8m_div prescaler;
-	/** Keep the OSC8M enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC8M won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
+    /** Internal 8MHz RC oscillator prescaler */
+    enum system_osc8m_div prescaler;
+    /** Keep the OSC8M enabled in standby sleep mode */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the OSC8M won't run
+     * until requested by a peripheral. */
+    bool on_demand;
 };
 
 /**
@@ -624,20 +624,20 @@ struct system_clock_source_osc8m_config {
  * Internal 32KHz (nominal) oscillator configuration structure.
  */
 struct system_clock_source_osc32k_config {
-	/** Startup time */
-	enum system_osc32k_startup startup_time;
-	/** Enable 1KHz output */
-	bool enable_1khz_output;
-	/** Enable 32KHz output */
-	bool enable_32khz_output;
-	/** Keep the OSC32K enabled in standby sleep mode */
-	bool run_in_standby;
-	/** Run On Demand. If this is set the OSC32K won't run
-	 * until requested by a peripheral */
-	bool on_demand;
-	/** Lock configuration after it has been written,
-	 *  a device reset will release the lock */
-	bool write_once;
+    /** Startup time */
+    enum system_osc32k_startup startup_time;
+    /** Enable 1KHz output */
+    bool enable_1khz_output;
+    /** Enable 32KHz output */
+    bool enable_32khz_output;
+    /** Keep the OSC32K enabled in standby sleep mode */
+    bool run_in_standby;
+    /** Run On Demand. If this is set the OSC32K won't run
+     * until requested by a peripheral */
+    bool on_demand;
+    /** Lock configuration after it has been written,
+     *  a device reset will release the lock */
+    bool write_once;
 };
 
 /**
@@ -646,29 +646,29 @@ struct system_clock_source_osc32k_config {
  * DFLL oscillator configuration structure.
  */
 struct system_clock_source_dfll_config {
-	/** Loop mode */
-	enum system_clock_dfll_loop_mode loop_mode;
-	/** Run On Demand. If this is set the DFLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Enable Quick Lock */
-	enum system_clock_dfll_quick_lock quick_lock;
-	/** Enable Chill Cycle */
-	enum system_clock_dfll_chill_cycle chill_cycle;
-	/** DFLL lock state on wakeup */
-	enum system_clock_dfll_wakeup_lock wakeup_lock;
-	/** DFLL tracking after fine lock */
-	enum system_clock_dfll_stable_tracking stable_tracking;
-	/** Coarse calibration value (Open loop mode) */
-	uint8_t coarse_value;
-	/** Fine calibration value (Open loop mode) */
-	uint16_t fine_value;
-	/** Coarse adjustment maximum step size (Closed loop mode) */
-	uint8_t coarse_max_step;
-	/** Fine adjustment maximum step size (Closed loop mode) */
-	uint16_t fine_max_step;
-	/** DFLL multiply factor (Closed loop mode */
-	uint16_t multiply_factor;
+    /** Loop mode */
+    enum system_clock_dfll_loop_mode loop_mode;
+    /** Run On Demand. If this is set the DFLL won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Enable Quick Lock */
+    enum system_clock_dfll_quick_lock quick_lock;
+    /** Enable Chill Cycle */
+    enum system_clock_dfll_chill_cycle chill_cycle;
+    /** DFLL lock state on wakeup */
+    enum system_clock_dfll_wakeup_lock wakeup_lock;
+    /** DFLL tracking after fine lock */
+    enum system_clock_dfll_stable_tracking stable_tracking;
+    /** Coarse calibration value (Open loop mode) */
+    uint8_t coarse_value;
+    /** Fine calibration value (Open loop mode) */
+    uint16_t fine_value;
+    /** Coarse adjustment maximum step size (Closed loop mode) */
+    uint8_t coarse_max_step;
+    /** Fine adjustment maximum step size (Closed loop mode) */
+    uint16_t fine_max_step;
+    /** DFLL multiply factor (Closed loop mode */
+    uint16_t multiply_factor;
 };
 
 /**
@@ -691,20 +691,20 @@ struct system_clock_source_dfll_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_xosc_get_config_defaults(
-		struct system_clock_source_xosc_config *const config)
+        struct system_clock_source_xosc_config *const config)
 {
-	Assert(config);
-
-	config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
-	config->auto_gain_control = true;
-	config->frequency         = 12000000UL;
-	config->run_in_standby    = false;
-	config->on_demand         = true;
+    Assert(config);
+
+    config->external_clock    = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+    config->startup_time      = SYSTEM_XOSC_STARTUP_16384;
+    config->auto_gain_control = true;
+    config->frequency         = 12000000UL;
+    config->run_in_standby    = false;
+    config->on_demand         = true;
 }
 
 void system_clock_source_xosc_set_config(
-		struct system_clock_source_xosc_config *const config);
+        struct system_clock_source_xosc_config *const config);
 
 /**
  * @}
@@ -734,23 +734,23 @@ void system_clock_source_xosc_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_xosc32k_get_config_defaults(
-		struct system_clock_source_xosc32k_config *const config)
+        struct system_clock_source_xosc32k_config *const config)
 {
-	Assert(config);
-
-	config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
-	config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
-	config->auto_gain_control   = false;
-	config->frequency           = 32768UL;
-	config->enable_1khz_output  = false;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->write_once          = false;
+    Assert(config);
+
+    config->external_clock      = SYSTEM_CLOCK_EXTERNAL_CRYSTAL;
+    config->startup_time        = SYSTEM_XOSC32K_STARTUP_16384;
+    config->auto_gain_control   = false;
+    config->frequency           = 32768UL;
+    config->enable_1khz_output  = false;
+    config->enable_32khz_output = true;
+    config->run_in_standby      = false;
+    config->on_demand           = true;
+    config->write_once          = false;
 }
 
 void system_clock_source_xosc32k_set_config(
-		struct system_clock_source_xosc32k_config *const config);
+        struct system_clock_source_xosc32k_config *const config);
 /**
  * @}
  */
@@ -776,20 +776,20 @@ void system_clock_source_xosc32k_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_osc32k_get_config_defaults(
-		struct system_clock_source_osc32k_config *const config)
+        struct system_clock_source_osc32k_config *const config)
 {
-	Assert(config);
-
-	config->enable_1khz_output  = true;
-	config->enable_32khz_output = true;
-	config->run_in_standby      = false;
-	config->on_demand           = true;
-	config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
-	config->write_once          = false;
+    Assert(config);
+
+    config->enable_1khz_output  = true;
+    config->enable_32khz_output = true;
+    config->run_in_standby      = false;
+    config->on_demand           = true;
+    config->startup_time        = SYSTEM_OSC32K_STARTUP_130;
+    config->write_once          = false;
 }
 
 void system_clock_source_osc32k_set_config(
-		struct system_clock_source_osc32k_config *const config);
+        struct system_clock_source_osc32k_config *const config);
 
 /**
  * @}
@@ -813,17 +813,17 @@ void system_clock_source_osc32k_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_osc8m_get_config_defaults(
-		struct system_clock_source_osc8m_config *const config)
+        struct system_clock_source_osc8m_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->prescaler       = SYSTEM_OSC8M_DIV_8;
-	config->run_in_standby  = false;
-	config->on_demand       = true;
+    config->prescaler       = SYSTEM_OSC8M_DIV_8;
+    config->run_in_standby  = false;
+    config->on_demand       = true;
 }
 
 void system_clock_source_osc8m_set_config(
-		struct system_clock_source_osc8m_config *const config);
+        struct system_clock_source_osc8m_config *const config);
 
 /**
  * @}
@@ -853,29 +853,29 @@ void system_clock_source_osc8m_set_config(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_dfll_get_config_defaults(
-		struct system_clock_source_dfll_config *const config)
+        struct system_clock_source_dfll_config *const config)
 {
-	Assert(config);
-
-	config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
-	config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
-	config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
-	config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
-	config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
-	config->on_demand       = true;
-
-	/* Open loop mode calibration value */
-	config->coarse_value    = 0x1f / 4; /* Midpoint */
-	config->fine_value      = 0xff / 4; /* Midpoint */
-
-	/* Closed loop mode */
-	config->coarse_max_step = 1;
-	config->fine_max_step   = 1;
-	config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
+    Assert(config);
+
+    config->loop_mode       = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN;
+    config->quick_lock      = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
+    config->chill_cycle     = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
+    config->wakeup_lock     = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
+    config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
+    config->on_demand       = true;
+
+    /* Open loop mode calibration value */
+    config->coarse_value    = 0x1f / 4; /* Midpoint */
+    config->fine_value      = 0xff / 4; /* Midpoint */
+
+    /* Closed loop mode */
+    config->coarse_max_step = 1;
+    config->fine_max_step   = 1;
+    config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */
 }
 
 void system_clock_source_dfll_set_config(
-		struct system_clock_source_dfll_config *const config);
+        struct system_clock_source_dfll_config *const config);
 
 /**
  * @}
@@ -886,21 +886,21 @@ void system_clock_source_dfll_set_config(
  * @{
  */
 enum status_code system_clock_source_write_calibration(
-		const enum system_clock_source system_clock_source,
-		const uint16_t calibration_value,
-		const uint8_t freq_range);
+        const enum system_clock_source system_clock_source,
+        const uint16_t calibration_value,
+        const uint8_t freq_range);
 
 enum status_code system_clock_source_enable(
-		const enum system_clock_source system_clock_source);
+        const enum system_clock_source system_clock_source);
 
 enum status_code system_clock_source_disable(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 bool system_clock_source_is_ready(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 uint32_t system_clock_source_get_hz(
-		const enum system_clock_source clk_source);
+        const enum system_clock_source clk_source);
 
 /**
  * @}
@@ -919,10 +919,10 @@ uint32_t system_clock_source_get_hz(
  * \param[in] divider  CPU clock divider to set
  */
 static inline void system_cpu_clock_set_divider(
-		const enum system_main_clock_div divider)
+        const enum system_main_clock_div divider)
 {
-	Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
-	PM->CPUSEL.reg = (uint32_t)divider;
+    Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider);
+    PM->CPUSEL.reg = (uint32_t)divider;
 }
 
 /**
@@ -935,7 +935,7 @@ static inline void system_cpu_clock_set_divider(
  */
 static inline uint32_t system_cpu_clock_get_hz(void)
 {
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
+    return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg);
 }
 
 /**
@@ -953,25 +953,26 @@ static inline uint32_t system_cpu_clock_get_hz(void)
  * \retval STATUS_OK               The APBx clock was set successfully
  */
 static inline enum status_code system_apb_clock_set_divider(
-		const enum system_clock_apb_bus bus,
-		const enum system_main_clock_div divider)
+        const enum system_clock_apb_bus bus,
+        const enum system_main_clock_div divider)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBASEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBSEL.reg = (uint32_t)divider;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCSEL.reg = (uint32_t)divider;
-			break;
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBASEL.reg = (uint32_t)divider;
+            break;
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBSEL.reg = (uint32_t)divider;
+            break;
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCSEL.reg = (uint32_t)divider;
+            break;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -983,26 +984,27 @@ static inline enum status_code system_apb_clock_set_divider(
  * \return Current APBx bus frequency in Hz.
  */
 static inline uint32_t system_apb_clock_get_hz(
-		const enum system_clock_apb_bus bus)
+        const enum system_clock_apb_bus bus)
 {
-	uint16_t bus_divider = 0;
-
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			bus_divider = PM->APBASEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBB:
-			bus_divider = PM->APBBSEL.reg;
-			break;
-		case SYSTEM_CLOCK_APB_APBC:
-			bus_divider = PM->APBCSEL.reg;
-			break;
-		default:
-			Assert(false);
-			return 0;
-	}
-
-	return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
+    uint16_t bus_divider = 0;
+
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            bus_divider = PM->APBASEL.reg;
+            break;
+        case SYSTEM_CLOCK_APB_APBB:
+            bus_divider = PM->APBBSEL.reg;
+            break;
+        case SYSTEM_CLOCK_APB_APBC:
+            bus_divider = PM->APBCSEL.reg;
+            break;
+        default:
+            Assert(false);
+            return 0;
+    }
+
+    return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider);
 }
 
 
@@ -1025,9 +1027,9 @@ static inline uint32_t system_apb_clock_get_hz(
  * \param[in] ahb_mask  AHB clock mask to enable
  */
 static inline void system_ahb_clock_set_mask(
-		const uint32_t ahb_mask)
+        const uint32_t ahb_mask)
 {
-	PM->AHBMASK.reg |= ahb_mask;
+    PM->AHBMASK.reg |= ahb_mask;
 }
 
 /**
@@ -1040,9 +1042,9 @@ static inline void system_ahb_clock_set_mask(
  * \param[in] ahb_mask  AHB clock mask to disable
  */
 static inline void system_ahb_clock_clear_mask(
-		const uint32_t ahb_mask)
+        const uint32_t ahb_mask)
 {
-	PM->AHBMASK.reg &= ~ahb_mask;
+    PM->AHBMASK.reg &= ~ahb_mask;
 }
 
 /**
@@ -1063,29 +1065,30 @@ static inline void system_ahb_clock_clear_mask(
  * \retval STATUS_OK               The clock mask was set successfully
  */
 static inline enum status_code system_apb_clock_set_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
+        const enum system_clock_apb_bus bus,
+        const uint32_t mask)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg |= mask;
-			break;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBAMASK.reg |= mask;
+            break;
 
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg |= mask;
-			break;
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBMASK.reg |= mask;
+            break;
 
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg |= mask;
-			break;
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCMASK.reg |= mask;
+            break;
 
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
 
-	}
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1105,28 +1108,29 @@ static inline enum status_code system_apb_clock_set_mask(
  * \retval STATUS_OK               The clock mask was changed successfully
  */
 static inline enum status_code system_apb_clock_clear_mask(
-		const enum system_clock_apb_bus bus,
-		const uint32_t mask)
+        const enum system_clock_apb_bus bus,
+        const uint32_t mask)
 {
-	switch (bus) {
-		case SYSTEM_CLOCK_APB_APBA:
-			PM->APBAMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBB:
-			PM->APBBMASK.reg &= ~mask;
-			break;
-
-		case SYSTEM_CLOCK_APB_APBC:
-			PM->APBCMASK.reg &= ~mask;
-			break;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (bus)
+    {
+        case SYSTEM_CLOCK_APB_APBA:
+            PM->APBAMASK.reg &= ~mask;
+            break;
+
+        case SYSTEM_CLOCK_APB_APBB:
+            PM->APBBMASK.reg &= ~mask;
+            break;
+
+        case SYSTEM_CLOCK_APB_APBC:
+            PM->APBCMASK.reg &= ~mask;
+            break;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1138,42 +1142,42 @@ static inline enum status_code system_apb_clock_clear_mask(
  * \brief Reference clock source of the DPLL module.
  */
 enum system_clock_source_dpll_reference_clock {
-	/** Select XOSC32K as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
-	/** Select XOSC as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
-	/** Select GCLK as clock reference. */
-	SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
+    /** Select XOSC32K as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K,
+    /** Select XOSC as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC,
+    /** Select GCLK as clock reference. */
+    SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK,
 };
 
 /**
  * \brief Lock time-out value of the DPLL module.
  */
 enum system_clock_source_dpll_lock_time {
-	/** Set no time-out as default. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
-	/** Set time-out if no lock within 8ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
-	/** Set time-out if no lock within 9ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
-	/** Set time-out if no lock within 10ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
-	/** Set time-out if no lock within 11ms. */
-	SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
+    /** Set no time-out as default. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT,
+    /** Set time-out if no lock within 8ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04,
+    /** Set time-out if no lock within 9ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS,
+    /** Set time-out if no lock within 10ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS,
+    /** Set time-out if no lock within 11ms. */
+    SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS,
 };
 
 /**
  * \brief Filter type of the DPLL module.
  */
 enum system_clock_source_dpll_filter {
-	/** Default filter mode. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
-	/** Low bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
-	/** High bandwidth filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
-	/** High damping filter. */
-	SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
+    /** Default filter mode. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT,
+    /** Low bandwidth filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER,
+    /** High bandwidth filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER,
+    /** High damping filter. */
+    SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER,
 };
 
 /**
@@ -1182,32 +1186,32 @@ enum system_clock_source_dpll_filter {
  * DPLL oscillator configuration structure.
  */
 struct system_clock_source_dpll_config {
-	/** Run On Demand. If this is set the DPLL won't run
-	 * until requested by a peripheral. */
-	bool on_demand;
-	/** Keep the DPLL enabled in standby sleep mode. */
-	bool run_in_standby;
-	/** Bypass lock signal. */
-	bool lock_bypass;
-	/** Wake up fast. If this is set DPLL output clock is enabled after
-	 * the startup time. */
-	bool wake_up_fast;
-	/** Enable low power mode.  */
-	bool low_power_enable;
-
-	/** Output frequency of the clock. */
-	uint32_t output_frequency;
-	/** Reference frequency of the clock. */
-	uint32_t reference_frequency;
-	/** Devider of reference clock. */
-	uint16_t reference_divider;
-
-	/** Filter type of the DPLL module. */
-	enum system_clock_source_dpll_filter          filter;
-	/** Lock time-out value of the DPLL module. */
-	enum system_clock_source_dpll_lock_time       lock_time;
-	/** Reference clock source of the DPLL module. */
-	enum system_clock_source_dpll_reference_clock reference_clock;
+    /** Run On Demand. If this is set the DPLL won't run
+     * until requested by a peripheral. */
+    bool on_demand;
+    /** Keep the DPLL enabled in standby sleep mode. */
+    bool run_in_standby;
+    /** Bypass lock signal. */
+    bool lock_bypass;
+    /** Wake up fast. If this is set DPLL output clock is enabled after
+     * the startup time. */
+    bool wake_up_fast;
+    /** Enable low power mode.  */
+    bool low_power_enable;
+
+    /** Output frequency of the clock. */
+    uint32_t output_frequency;
+    /** Reference frequency of the clock. */
+    uint32_t reference_frequency;
+    /** Devider of reference clock. */
+    uint16_t reference_divider;
+
+    /** Filter type of the DPLL module. */
+    enum system_clock_source_dpll_filter          filter;
+    /** Lock time-out value of the DPLL module. */
+    enum system_clock_source_dpll_lock_time       lock_time;
+    /** Reference clock source of the DPLL module. */
+    enum system_clock_source_dpll_reference_clock reference_clock;
 };
 
 /**
@@ -1235,25 +1239,25 @@ struct system_clock_source_dpll_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_clock_source_dpll_get_config_defaults(
-		struct system_clock_source_dpll_config *const config)
+        struct system_clock_source_dpll_config *const config)
 {
-	config->on_demand           = true;
-	config->run_in_standby      = false;
-	config->lock_bypass         = false;
-	config->wake_up_fast        = false;
-	config->low_power_enable    = false;
-
-	config->output_frequency    = 48000000;
-	config->reference_frequency = 32768;
-	config->reference_divider   = 1;
-	config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
-
-	config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
-	config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
+    config->on_demand           = true;
+    config->run_in_standby      = false;
+    config->lock_bypass         = false;
+    config->wake_up_fast        = false;
+    config->low_power_enable    = false;
+
+    config->output_frequency    = 48000000;
+    config->reference_frequency = 32768;
+    config->reference_divider   = 1;
+    config->reference_clock     = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K;
+
+    config->lock_time           = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT;
+    config->filter              = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT;
 };
 
 void system_clock_source_dpll_set_config(
-		struct system_clock_source_dpll_config *const config);
+        struct system_clock_source_dpll_config *const config);
 
 /* @} */
 #endif
@@ -1286,10 +1290,10 @@ void system_clock_init(void);
  */
 static inline void system_flash_set_waitstates(uint8_t wait_states)
 {
-	Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
-			((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
+    Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) ==
+            ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos));
 
-	NVMCTRL->CTRLB.bit.RWS = wait_states;
+    NVMCTRL->CTRLB.bit.RWS = wait_states;
 }
 /**
  * @}
@@ -1307,54 +1311,54 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>DFLL</td>
- *		<td>Digital Frequency Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
- *	<tr>
- *		<td>OSC32K</td>
- *		<td>Internal 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>OSC8M</td>
- *		<td>Internal 8MHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>PLL</td>
- *		<td>Phase Locked Loop</td>
- *	</tr>
- *	<tr>
- *		<td>OSC</td>
- *		<td>Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC</td>
- *		<td>External Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>XOSC32K</td>
- *		<td>External 32KHz Oscillator</td>
- *	</tr>
- *	<tr>
- *		<td>AHB</td>
- *		<td>Advanced High-performance Bus</td>
- *	</tr>
- *	<tr>
- *		<td>APB</td>
- *		<td>Advanced Peripheral Bus</td>
- *	</tr>
- *	<tr>
- *		<td>DPLL</td>
- *		<td>Digital Phase Locked Loop</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>DFLL</td>
+ *      <td>Digital Frequency Locked Loop</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC32K</td>
+ *      <td>Internal 32KHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC8M</td>
+ *      <td>Internal 8MHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PLL</td>
+ *      <td>Phase Locked Loop</td>
+ *  </tr>
+ *  <tr>
+ *      <td>OSC</td>
+ *      <td>Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>XOSC</td>
+ *      <td>External Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>XOSC32K</td>
+ *      <td>External 32KHz Oscillator</td>
+ *  </tr>
+ *  <tr>
+ *      <td>AHB</td>
+ *      <td>Advanced High-performance Bus</td>
+ *  </tr>
+ *  <tr>
+ *      <td>APB</td>
+ *      <td>Advanced Peripheral Bus</td>
+ *  </tr>
+ *  <tr>
+ *      <td>DPLL</td>
+ *      <td>Digital Phase Locked Loop</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1366,11 +1370,11 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  *
  * \section asfdoc_sam0_system_clock_extra_errata Errata
  *
- *	- This driver implements experimental workaround for errata 9905
+ *  - This driver implements experimental workaround for errata 9905
  *
- *	  "The DFLL clock must be requested before being configured otherwise a
- *	  write access to a DFLL register can freeze the device."
- *	  This driver will enable and configure the DFLL before the ONDEMAND bit is set.
+ *    "The DFLL clock must be requested before being configured otherwise a
+ *    write access to a DFLL register can freeze the device."
+ *    This driver will enable and configure the DFLL before the ONDEMAND bit is set.
  *
  *
  * \section asfdoc_sam0_system_clock_extra_history Module History
@@ -1380,47 +1384,47 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Corrected OSC32K startup time definitions
- *			\li Support locking of OSC32K and XOSC32K config register (default: false)
- *			\li Added DPLL support, functions added:
- *			    \c system_clock_source_dpll_get_config_defaults() and
- *		        \c system_clock_source_dpll_set_config()
- *			\li Moved gclk channel locking feature out of the config struct
- *			    functions added:
- *			    \c system_gclk_chan_lock(),
- *			    \c system_gclk_chan_is_locked()
- *			    \c system_gclk_chan_is_enabled() and
- *			    \c system_gclk_gen_is_enabled()
- *		</td>
- *	</tr>
  *  <tr>
- *		<td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
- *		    and configured to a failed/not running clock generator</td>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *          \li Corrected OSC32K startup time definitions
+ *          \li Support locking of OSC32K and XOSC32K config register (default: false)
+ *          \li Added DPLL support, functions added:
+ *              \c system_clock_source_dpll_get_config_defaults() and
+ *              \c system_clock_source_dpll_set_config()
+ *          \li Moved gclk channel locking feature out of the config struct
+ *              functions added:
+ *              \c system_gclk_chan_lock(),
+ *              \c system_gclk_chan_is_locked()
+ *              \c system_gclk_chan_is_enabled() and
+ *              \c system_gclk_gen_is_enabled()
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled
+ *          and configured to a failed/not running clock generator</td>
  *  </tr>
- *	<tr>
- *		<td>
- *			\li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
- *			\li Fixed system_flash_set_waitstates() failing with an assertion
- *			    if an odd number of wait states provided
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>
- *			\li Updated DFLL configuration function to implement workaround for
- *			    errata 9905 in the DFLL module
- *			\li Updated \c system_clock_init() to reset interrupt flags before
- *			    they are used
- *			\li Fixed \c system_clock_source_get_hz() to return correcy DFLL
- *			    frequency number
- *		</td>
- *	</tr>
- *	<tr>
- *		<td>\li Fixed \c system_clock_source_is_ready not returning the correct
+ *  <tr>
+ *      <td>
+ *          \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false
+ *          \li Fixed system_flash_set_waitstates() failing with an assertion
+ *              if an odd number of wait states provided
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>
+ *          \li Updated DFLL configuration function to implement workaround for
+ *              errata 9905 in the DFLL module
+ *          \li Updated \c system_clock_init() to reset interrupt flags before
+ *              they are used
+ *          \li Fixed \c system_clock_source_get_hz() to return correcy DFLL
+ *              frequency number
+ *      </td>
+ *  </tr>
+ *  <tr>
+ *      <td>\li Fixed \c system_clock_source_is_ready not returning the correct
  *              state for \c SYSTEM_CLOCK_SOURCE_OSC8M
  *          \li Renamed the various \c system_clock_source_*_get_default_config()
  *              functions to \c system_clock_source_*_get_config_defaults() to
@@ -1430,10 +1434,10 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  *          \li Updated default configuration of the XOSC32 to disable Automatic
  *              Gain Control due to silicon errata
  *      </td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1452,37 +1456,37 @@ static inline void system_flash_set_waitstates(uint8_t wait_states)
  * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42119E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM DA1 and SAM D09</td>
- *	</tr>
- *	<tr>
- *		<td>42119D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42119C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42119B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos. Fixed missing steps in the Basic
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42119E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM DA1 and SAM D09</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42119D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42119C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42119B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos. Fixed missing steps in the Basic
  *          Use Case Quick Start Guide</td>
- *	</tr>
- *	<tr>
- *		<td>42119A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>42119A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
index e1c186cf677b..442e16bcf292 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/gclk.c
@@ -64,11 +64,12 @@
  */
 static inline bool system_gclk_is_syncing(void)
 {
-	if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){
-		return true;
-	}
+    if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -79,14 +80,15 @@ static inline bool system_gclk_is_syncing(void)
  */
 void system_gclk_init(void)
 {
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
-
-	/* Software reset the module to ensure it is re-initialized correctly */
-	GCLK->CTRL.reg = GCLK_CTRL_SWRST;
-	while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
-		/* Wait for reset to complete */
-	}
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
+
+    /* Software reset the module to ensure it is re-initialized correctly */
+    GCLK->CTRL.reg = GCLK_CTRL_SWRST;
+    while (GCLK->CTRL.reg & GCLK_CTRL_SWRST)
+    {
+        /* Wait for reset to complete */
+    }
 }
 
 /**
@@ -110,86 +112,95 @@ void system_gclk_init(void)
  * \param[in] config     Configuration settings for the generator
  */
 void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config)
+        const uint8_t generator,
+        struct system_gclk_gen_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Cache new register configurations to minimize sync requirements. */
-	uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
-	uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
-
-	/* Select the requested source clock for the generator */
-	new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
-
-	/* Configure the clock to be either high or low when disabled */
-	if (config->high_when_disabled) {
-		new_genctrl_config |= GCLK_GENCTRL_OOV;
-	}
-
-	/* Configure if the clock output to I/O pin should be enabled. */
-	if (config->output_enable) {
-		new_genctrl_config |= GCLK_GENCTRL_OE;
-	}
-
-	/* Set division factor */
-	if (config->division_factor > 1) {
-		/* Check if division is a power of two */
-		if (((config->division_factor & (config->division_factor - 1)) == 0)) {
-			/* Determine the index of the highest bit set to get the
-			 * division factor that must be loaded into the division
-			 * register */
-
-			uint32_t div2_count = 0;
-
-			uint32_t mask;
-			for (mask = (1UL << 1); mask < config->division_factor;
-						mask <<= 1) {
-				div2_count++;
-			}
-
-			/* Set binary divider power of 2 division factor */
-			new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
-			new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
-		} else {
-			/* Set integer division factor */
-
-			new_gendiv_config  |=
-					(config->division_factor) << GCLK_GENDIV_DIV_Pos;
-
-			/* Enable non-binary division with increased duty cycle accuracy */
-			new_genctrl_config |= GCLK_GENCTRL_IDC;
-		}
-
-	}
-
-	/* Enable or disable the clock in standby mode */
-	if (config->run_in_standby) {
-		new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
-	}
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the correct generator */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-
-	/* Write the new generator configuration */
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENDIV.reg  = new_gendiv_config;
-
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-	GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
-
-	system_interrupt_leave_critical_section();
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Cache new register configurations to minimize sync requirements. */
+    uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
+    uint32_t new_gendiv_config  = (generator << GCLK_GENDIV_ID_Pos);
+
+    /* Select the requested source clock for the generator */
+    new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
+
+    /* Configure the clock to be either high or low when disabled */
+    if (config->high_when_disabled)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_OOV;
+    }
+
+    /* Configure if the clock output to I/O pin should be enabled. */
+    if (config->output_enable)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_OE;
+    }
+
+    /* Set division factor */
+    if (config->division_factor > 1)
+    {
+        /* Check if division is a power of two */
+        if (((config->division_factor & (config->division_factor - 1)) == 0))
+        {
+            /* Determine the index of the highest bit set to get the
+             * division factor that must be loaded into the division
+             * register */
+
+            uint32_t div2_count = 0;
+
+            uint32_t mask;
+            for (mask = (1UL << 1); mask < config->division_factor;
+                        mask <<= 1)
+                        {
+                div2_count++;
+            }
+
+            /* Set binary divider power of 2 division factor */
+            new_gendiv_config  |= div2_count << GCLK_GENDIV_DIV_Pos;
+            new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
+        } else {
+            /* Set integer division factor */
+
+            new_gendiv_config  |=
+                    (config->division_factor) << GCLK_GENDIV_DIV_Pos;
+
+            /* Enable non-binary division with increased duty cycle accuracy */
+            new_genctrl_config |= GCLK_GENCTRL_IDC;
+        }
+
+    }
+
+    /* Enable or disable the clock in standby mode */
+    if (config->run_in_standby)
+    {
+        new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
+    }
+
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    system_interrupt_enter_critical_section();
+
+    /* Select the correct generator */
+    *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+
+    /* Write the new generator configuration */
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+    GCLK->GENDIV.reg  = new_gendiv_config;
+
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+    GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -201,24 +212,26 @@ void system_gclk_gen_set_config(
  * \param[in] generator  Generic Clock Generator index to enable
  */
 void system_gclk_gen_enable(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	/* Enable generator */
-	GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
+    /* Enable generator */
+    GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -230,27 +243,30 @@ void system_gclk_gen_enable(
  * \param[in] generator  Generic Clock Generator index to disable
  */
 void system_gclk_gen_disable(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	system_interrupt_enter_critical_section();
-
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
-
-	/* Disable generator */
-	GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
-	while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
-		/* Wait for clock to become disabled */
-	}
-
-	system_interrupt_leave_critical_section();
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    system_interrupt_enter_critical_section();
+
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
+
+    /* Disable generator */
+    GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
+    while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN)
+    {
+        /* Wait for clock to become disabled */
+    }
+
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -263,20 +279,20 @@ void system_gclk_gen_disable(
  * \retval false The Generic Clock Generator is disabled
  */
 bool system_gclk_gen_is_enabled(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	bool enabled;
+    bool enabled;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	/* Obtain the enabled status */
-	enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
+    /* Select the requested generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    /* Obtain the enabled status */
+    enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return enabled;
+    return enabled;
 }
 
 /**
@@ -290,46 +306,51 @@ bool system_gclk_gen_is_enabled(
  * \return The frequency of the generic clock generator, in Hz.
  */
 uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator)
+        const uint8_t generator)
 {
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the appropriate generator */
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the appropriate generator */
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	/* Get the frequency of the source connected to the GCLK generator */
-	uint32_t gen_input_hz = system_clock_source_get_hz(
-			(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
+    /* Get the frequency of the source connected to the GCLK generator */
+    uint32_t gen_input_hz = system_clock_source_get_hz(
+            (enum system_clock_source)GCLK->GENCTRL.bit.SRC);
 
-	*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
+    *((uint8_t*)&GCLK->GENCTRL.reg) = generator;
 
-	uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
+    uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
 
-	/* Select the appropriate generator division register */
-	*((uint8_t*)&GCLK->GENDIV.reg) = generator;
-	while (system_gclk_is_syncing()) {
-		/* Wait for synchronization */
-	};
+    /* Select the appropriate generator division register */
+    *((uint8_t*)&GCLK->GENDIV.reg) = generator;
+    while (system_gclk_is_syncing())
+    {
+        /* Wait for synchronization */
+    };
 
-	uint32_t divider = GCLK->GENDIV.bit.DIV;
+    uint32_t divider = GCLK->GENDIV.bit.DIV;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	/* Check if the generator is using fractional or binary division */
-	if (!divsel && divider > 1) {
-		gen_input_hz /= divider;
-	} else if (divsel) {
-		gen_input_hz >>= (divider+1);
-	}
+    /* Check if the generator is using fractional or binary division */
+    if (!divsel && divider > 1)
+    {
+        gen_input_hz /= divider;
+    } else if (divsel)
+    {
+        gen_input_hz >>= (divider+1);
+    }
 
-	return gen_input_hz;
+    return gen_input_hz;
 }
 
 /**
@@ -346,23 +367,23 @@ uint32_t system_gclk_gen_get_hz(
  *
  */
 void system_gclk_chan_set_config(
-		const uint8_t channel,
-		struct system_gclk_chan_config *const config)
+        const uint8_t channel,
+        struct system_gclk_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Cache the new config to reduce sync requirements */
-	uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
+    /* Cache the new config to reduce sync requirements */
+    uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
 
-	/* Select the desired generic clock generator */
-	new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
+    /* Select the desired generic clock generator */
+    new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
 
-	/* Disable generic clock channel */
-	system_gclk_chan_disable(channel);
+    /* Disable generic clock channel */
+    system_gclk_chan_disable(channel);
 
-	/* Write the new configuration */
-	GCLK->CLKCTRL.reg = new_clkctrl_config;
+    /* Write the new configuration */
+    GCLK->CLKCTRL.reg = new_clkctrl_config;
 }
 
 /**
@@ -374,17 +395,17 @@ void system_gclk_chan_set_config(
  * \param[in] channel   Generic Clock channel to enable
  */
 void system_gclk_chan_enable(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Enable the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
+    /* Enable the generic clock */
+    GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -396,30 +417,31 @@ void system_gclk_chan_enable(
  * \param[in] channel  Generic Clock channel to disable
  */
 void system_gclk_chan_disable(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Sanity check WRTLOCK */
-	Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
+    /* Sanity check WRTLOCK */
+    Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
 
-	/* Switch to known-working source so that the channel can be disabled */
-	uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
-	GCLK->CLKCTRL.bit.GEN = 0;
+    /* Switch to known-working source so that the channel can be disabled */
+    uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
+    GCLK->CLKCTRL.bit.GEN = 0;
 
-	/* Disable the generic clock */
-	GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
-	while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
-		/* Wait for clock to become disabled */
-	}
+    /* Disable the generic clock */
+    GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
+    while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN)
+    {
+        /* Wait for clock to become disabled */
+    }
 
-	/* Restore previous configured clock generator */
-	GCLK->CLKCTRL.bit.GEN = prev_gen_id;
+    /* Restore previous configured clock generator */
+    GCLK->CLKCTRL.bit.GEN = prev_gen_id;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -432,19 +454,19 @@ void system_gclk_chan_disable(
  * \retval false The Generic Clock channel is disabled
  */
 bool system_gclk_chan_is_enabled(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	bool enabled;
+    bool enabled;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	enabled = GCLK->CLKCTRL.bit.CLKEN;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    enabled = GCLK->CLKCTRL.bit.CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return enabled;
+    return enabled;
 }
 
 /**
@@ -456,17 +478,17 @@ bool system_gclk_chan_is_enabled(
  * \param[in] channel   Generic Clock channel to enable
  */
 void system_gclk_chan_lock(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generator channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    /* Select the requested generator channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
 
-	/* Lock the generic clock */
-	GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
+    /* Lock the generic clock */
+    GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 }
 
 /**
@@ -479,19 +501,19 @@ void system_gclk_chan_lock(
  * \retval false The Generic Clock channel is not locked
  */
 bool system_gclk_chan_is_locked(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	bool locked;
+    bool locked;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	locked = GCLK->CLKCTRL.bit.WRTLOCK;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    locked = GCLK->CLKCTRL.bit.WRTLOCK;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	return locked;
+    return locked;
 }
 
 /**
@@ -505,18 +527,18 @@ bool system_gclk_chan_is_locked(
  * \return The frequency of the generic clock channel, in Hz.
  */
 uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel)
+        const uint8_t channel)
 {
-	uint8_t gen_id;
+    uint8_t gen_id;
 
-	system_interrupt_enter_critical_section();
+    system_interrupt_enter_critical_section();
 
-	/* Select the requested generic clock channel */
-	*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
-	gen_id = GCLK->CLKCTRL.bit.GEN;
+    /* Select the requested generic clock channel */
+    *((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
+    gen_id = GCLK->CLKCTRL.bit.GEN;
 
-	system_interrupt_leave_critical_section();
+    system_interrupt_leave_critical_section();
 
-	/* Return the clock speed of the associated GCLK generator */
-	return system_gclk_gen_get_hz(gen_id);
+    /* Return the clock speed of the associated GCLK generator */
+    return system_gclk_gen_get_hz(gen_id);
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h
index ff26eac9ebad..cd4e4a5665d7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/gclk.h
@@ -67,71 +67,71 @@ extern "C" {
  * The number of GCLK generators available is device dependent.
  */
 enum gclk_generator {
-	/** GCLK generator channel 0 */
-	GCLK_GENERATOR_0,
+    /** GCLK generator channel 0 */
+    GCLK_GENERATOR_0,
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
-	/** GCLK generator channel 1 */
-	GCLK_GENERATOR_1,
+    /** GCLK generator channel 1 */
+    GCLK_GENERATOR_1,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
-	/** GCLK generator channel 2 */
-	GCLK_GENERATOR_2,
+    /** GCLK generator channel 2 */
+    GCLK_GENERATOR_2,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
-	/** GCLK generator channel 3 */
-	GCLK_GENERATOR_3,
+    /** GCLK generator channel 3 */
+    GCLK_GENERATOR_3,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
-	/** GCLK generator channel 4 */
-	GCLK_GENERATOR_4,
+    /** GCLK generator channel 4 */
+    GCLK_GENERATOR_4,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
-	/** GCLK generator channel 5 */
-	GCLK_GENERATOR_5,
+    /** GCLK generator channel 5 */
+    GCLK_GENERATOR_5,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
-	/** GCLK generator channel 6 */
-	GCLK_GENERATOR_6,
+    /** GCLK generator channel 6 */
+    GCLK_GENERATOR_6,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
-	/** GCLK generator channel 7 */
-	GCLK_GENERATOR_7,
+    /** GCLK generator channel 7 */
+    GCLK_GENERATOR_7,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
-	/** GCLK generator channel 8 */
-	GCLK_GENERATOR_8,
+    /** GCLK generator channel 8 */
+    GCLK_GENERATOR_8,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
-	/** GCLK generator channel 9 */
-	GCLK_GENERATOR_9,
+    /** GCLK generator channel 9 */
+    GCLK_GENERATOR_9,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
-	/** GCLK generator channel 10 */
-	GCLK_GENERATOR_10,
+    /** GCLK generator channel 10 */
+    GCLK_GENERATOR_10,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
-	/** GCLK generator channel 11 */
-	GCLK_GENERATOR_11,
+    /** GCLK generator channel 11 */
+    GCLK_GENERATOR_11,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
-	/** GCLK generator channel 12 */
-	GCLK_GENERATOR_12,
+    /** GCLK generator channel 12 */
+    GCLK_GENERATOR_12,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
-	/** GCLK generator channel 13 */
-	GCLK_GENERATOR_13,
+    /** GCLK generator channel 13 */
+    GCLK_GENERATOR_13,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
-	/** GCLK generator channel 14 */
-	GCLK_GENERATOR_14,
+    /** GCLK generator channel 14 */
+    GCLK_GENERATOR_14,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
-	/** GCLK generator channel 15 */
-	GCLK_GENERATOR_15,
+    /** GCLK generator channel 15 */
+    GCLK_GENERATOR_15,
 #endif
 #if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
-	/** GCLK generator channel 16 */
-	GCLK_GENERATOR_16,
+    /** GCLK generator channel 16 */
+    GCLK_GENERATOR_16,
 #endif
 };
 
@@ -144,16 +144,16 @@ enum gclk_generator {
  * the user application.
  */
 struct system_gclk_gen_config {
-	/** Source clock input channel index, see the \ref system_clock_source */
-	uint8_t source_clock;
-	/** If \c true, the generator output level is high when disabled */
-	bool high_when_disabled;
-	/** Integer division factor of the clock output compared to the input */
-	uint32_t division_factor;
-	/** If \c true, the clock is kept enabled during device standby mode */
-	bool run_in_standby;
-	/** If \c true, enables GCLK generator clock output to a GPIO pin */
-	bool output_enable;
+    /** Source clock input channel index, see the \ref system_clock_source */
+    uint8_t source_clock;
+    /** If \c true, the generator output level is high when disabled */
+    bool high_when_disabled;
+    /** Integer division factor of the clock output compared to the input */
+    uint32_t division_factor;
+    /** If \c true, the clock is kept enabled during device standby mode */
+    bool run_in_standby;
+    /** If \c true, enables GCLK generator clock output to a GPIO pin */
+    bool output_enable;
 };
 
 /**
@@ -164,8 +164,8 @@ struct system_gclk_gen_config {
  * function before being modified by the user application.
  */
 struct system_gclk_chan_config {
-	/** Generic Clock Generator source channel */
-	enum gclk_generator source_generator;
+    /** Generic Clock Generator source channel */
+    enum gclk_generator source_generator;
 };
 
 /** \name Generic Clock Management
@@ -199,37 +199,37 @@ void system_gclk_init(void);
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void system_gclk_gen_get_config_defaults(
-		struct system_gclk_gen_config *const config)
+        struct system_gclk_gen_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->division_factor    = 1;
-	config->high_when_disabled = false;
+    /* Default configuration values */
+    config->division_factor    = 1;
+    config->high_when_disabled = false;
 #if SAML21 || SAML22  || SAMR30
-	config->source_clock       = GCLK_SOURCE_OSC16M;
+    config->source_clock       = GCLK_SOURCE_OSC16M;
 #elif (SAMC20) || (SAMC21)
-	config->source_clock       = GCLK_SOURCE_OSC48M;
+    config->source_clock       = GCLK_SOURCE_OSC48M;
 #else
-	config->source_clock       = GCLK_SOURCE_OSC8M;
+    config->source_clock       = GCLK_SOURCE_OSC8M;
 #endif
-	config->run_in_standby     = false;
-	config->output_enable      = false;
+    config->run_in_standby     = false;
+    config->output_enable      = false;
 }
 
 void system_gclk_gen_set_config(
-		const uint8_t generator,
-		struct system_gclk_gen_config *const config);
+        const uint8_t generator,
+        struct system_gclk_gen_config *const config);
 
 void system_gclk_gen_enable(
-		const uint8_t generator);
+        const uint8_t generator);
 
 void system_gclk_gen_disable(
-		const uint8_t generator);
+        const uint8_t generator);
 
 bool system_gclk_gen_is_enabled(
-		const uint8_t generator);
+        const uint8_t generator);
 
 /** @} */
 
@@ -254,33 +254,33 @@ bool system_gclk_gen_is_enabled(
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void system_gclk_chan_get_config_defaults(
-		struct system_gclk_chan_config *const config)
+        struct system_gclk_chan_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->source_generator = GCLK_GENERATOR_0;
+    /* Default configuration values */
+    config->source_generator = GCLK_GENERATOR_0;
 }
 
 void system_gclk_chan_set_config(
-		const uint8_t channel,
-		struct system_gclk_chan_config *const config);
+        const uint8_t channel,
+        struct system_gclk_chan_config *const config);
 
 void system_gclk_chan_enable(
-		const uint8_t channel);
+        const uint8_t channel);
 
 void system_gclk_chan_disable(
-		const uint8_t channel);
+        const uint8_t channel);
 
 bool system_gclk_chan_is_enabled(
-		const uint8_t channel);
+        const uint8_t channel);
 
 void system_gclk_chan_lock(
-		const uint8_t channel);
+        const uint8_t channel);
 
 bool system_gclk_chan_is_locked(
-		const uint8_t channel);
+        const uint8_t channel);
 
 /** @} */
 
@@ -291,10 +291,10 @@ bool system_gclk_chan_is_locked(
  */
 
 uint32_t system_gclk_gen_get_hz(
-		const uint8_t generator);
+        const uint8_t generator);
 
 uint32_t system_gclk_chan_get_hz(
-		const uint8_t channel);
+        const uint8_t channel);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c
index 24ee27ffa28c..961760b5d3fb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.c
@@ -59,20 +59,22 @@
  *
  */
 bool system_interrupt_is_pending(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	bool result;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
-	} else {
-		Assert(false);
-		result = false;
-	}
-
-	return result;
+    bool result;
+
+    if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START)
+    {
+        result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
+    } else if (vector == SYSTEM_INTERRUPT_SYSTICK)
+    {
+        result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
+    } else {
+        Assert(false);
+        result = false;
+    }
+
+    return result;
 }
 
 /**
@@ -92,25 +94,28 @@ bool system_interrupt_is_pending(
  * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
  */
 enum status_code system_interrupt_set_pending(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		NVIC->ISPR[0] = (1 << vector);
-	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
-		/* Note: Because NMI has highest priority it will be executed
-		 * immediately after it has been set pending */
-		SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
-	} else {
-		/* The user want to set something unsupported as pending */
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
+    enum status_code status = STATUS_OK;
+
+    if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START)
+    {
+        NVIC->ISPR[0] = (1 << vector);
+    } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE)
+    {
+        /* Note: Because NMI has highest priority it will be executed
+         * immediately after it has been set pending */
+        SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
+    } else if (vector == SYSTEM_INTERRUPT_SYSTICK)
+    {
+        SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
+    } else {
+        /* The user want to set something unsupported as pending */
+        Assert(false);
+        status = STATUS_ERR_INVALID_ARG;
+    }
+
+    return status;
 }
 
 /**
@@ -127,25 +132,28 @@ enum status_code system_interrupt_set_pending(
  * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
  */
 enum status_code system_interrupt_clear_pending(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		NVIC->ICPR[0] = (1 << vector);
-	} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
-		/* Note: Clearing of NMI pending interrupts does not make sense and is
-		 * not supported by the device, as it has the highest priority and will
-		 * always be executed at the moment it is set */
-		return STATUS_ERR_INVALID_ARG;
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
-	} else {
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
+    enum status_code status = STATUS_OK;
+
+    if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START)
+    {
+        NVIC->ICPR[0] = (1 << vector);
+    } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE)
+    {
+        /* Note: Clearing of NMI pending interrupts does not make sense and is
+         * not supported by the device, as it has the highest priority and will
+         * always be executed at the moment it is set */
+        return STATUS_ERR_INVALID_ARG;
+    } else if (vector == SYSTEM_INTERRUPT_SYSTICK)
+    {
+        SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
+    } else {
+        Assert(false);
+        status = STATUS_ERR_INVALID_ARG;
+    }
+
+    return status;
 }
 
 /**
@@ -163,27 +171,29 @@ enum status_code system_interrupt_clear_pending(
  * \retval STATUS_INVALID_ARG  If an unsupported interrupt vector number was given
  */
 enum status_code system_interrupt_set_priority(
-		const enum system_interrupt_vector vector,
-		const enum system_interrupt_priority_level priority_level)
+        const enum system_interrupt_vector vector,
+        const enum system_interrupt_priority_level priority_level)
 {
-	enum status_code status = STATUS_OK;
-
-	if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
-		uint8_t register_num = vector / 4;
-		uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
-
-		NVIC->IP[register_num] =
-				(NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
-				(priority_level << priority_pos);
-
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
-	} else {
-		Assert(false);
-		status = STATUS_ERR_INVALID_ARG;
-	}
-
-	return status;
+    enum status_code status = STATUS_OK;
+
+    if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START)
+    {
+        uint8_t register_num = vector / 4;
+        uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+        NVIC->IP[register_num] =
+                (NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) |
+                (priority_level << priority_pos);
+
+    } else if (vector == SYSTEM_INTERRUPT_SYSTICK)
+    {
+        SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
+    } else {
+        Assert(false);
+        status = STATUS_ERR_INVALID_ARG;
+    }
+
+    return status;
 }
 
 /**
@@ -197,21 +207,23 @@ enum status_code system_interrupt_set_priority(
  *         vector.
  */
 enum system_interrupt_priority_level system_interrupt_get_priority(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	uint8_t register_num = vector / 4;
-	uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
-
-	enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
-
-	if (vector >= 0) {
-		priority = (enum system_interrupt_priority_level)
-				((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
-	} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
-		priority = (enum system_interrupt_priority_level)
-				((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
-	}
-
-	return priority;
+    uint8_t register_num = vector / 4;
+    uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
+
+    enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
+
+    if (vector >= 0)
+    {
+        priority = (enum system_interrupt_priority_level)
+                ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+    } else if (vector == SYSTEM_INTERRUPT_SYSTICK)
+    {
+        priority = (enum system_interrupt_priority_level)
+                ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
+    }
+
+    return priority;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h
index 940170e7c2da..8e40f7a580c5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt.h
@@ -145,14 +145,14 @@ extern "C" {
  * device.
  */
 enum system_interrupt_priority_level {
-	/** Priority level 0, the highest possible interrupt priority */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
-	/** Priority level 1 */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
-	/** Priority level 2 */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
-	/** Priority level 3, the lowest possible interrupt priority */
-	SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
+    /** Priority level 0, the highest possible interrupt priority */
+    SYSTEM_INTERRUPT_PRIORITY_LEVEL_0  = 0,
+    /** Priority level 1 */
+    SYSTEM_INTERRUPT_PRIORITY_LEVEL_1  = 1,
+    /** Priority level 2 */
+    SYSTEM_INTERRUPT_PRIORITY_LEVEL_2  = 2,
+    /** Priority level 3, the lowest possible interrupt priority */
+    SYSTEM_INTERRUPT_PRIORITY_LEVEL_3  = 3,
 };
 
 /**
@@ -170,7 +170,7 @@ enum system_interrupt_priority_level {
  */
 static inline void system_interrupt_enter_critical_section(void)
 {
-	cpu_irq_enter_critical();
+    cpu_irq_enter_critical();
 }
 
 /**
@@ -183,7 +183,7 @@ static inline void system_interrupt_enter_critical_section(void)
  */
 static inline void system_interrupt_leave_critical_section(void)
 {
-	cpu_irq_leave_critical();
+    cpu_irq_leave_critical();
 }
 
 /** @} */
@@ -206,7 +206,7 @@ static inline void system_interrupt_leave_critical_section(void)
  */
 static inline bool system_interrupt_is_global_enabled(void)
 {
-	return cpu_irq_is_enabled();
+    return cpu_irq_is_enabled();
 }
 
 /**
@@ -216,7 +216,7 @@ static inline bool system_interrupt_is_global_enabled(void)
  */
 static inline void system_interrupt_enable_global(void)
 {
-	cpu_irq_enable();
+    cpu_irq_enable();
 }
 
 /**
@@ -227,7 +227,7 @@ static inline void system_interrupt_enable_global(void)
  */
 static inline void system_interrupt_disable_global(void)
 {
-	cpu_irq_disable();
+    cpu_irq_disable();
 }
 
 /**
@@ -244,9 +244,9 @@ static inline void system_interrupt_disable_global(void)
  *
  */
 static inline bool system_interrupt_is_enabled(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
+    return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
 }
 
 /**
@@ -257,9 +257,9 @@ static inline bool system_interrupt_is_enabled(
  * \param[in] vector Interrupt vector to enable
  */
 static inline void system_interrupt_enable(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+    NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
 }
 
 /**
@@ -270,9 +270,9 @@ static inline void system_interrupt_enable(
  * \param[in] vector  Interrupt vector to disable
  */
 static inline void system_interrupt_disable(
-		const enum system_interrupt_vector vector)
+        const enum system_interrupt_vector vector)
 {
-	NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
+    NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
 }
 
 /** @} */
@@ -291,19 +291,19 @@ static inline void system_interrupt_disable(
  */
 static inline enum system_interrupt_vector system_interrupt_get_active(void)
 {
-	uint32_t IPSR = __get_IPSR();
-	/* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
-	return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
+    uint32_t IPSR = __get_IPSR();
+    /* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */
+    return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16);
 }
 
 bool system_interrupt_is_pending(
-		const enum system_interrupt_vector vector);
+        const enum system_interrupt_vector vector);
 
 enum status_code system_interrupt_set_pending(
-		const enum system_interrupt_vector vector);
+        const enum system_interrupt_vector vector);
 
 enum status_code system_interrupt_clear_pending(
-		const enum system_interrupt_vector vector);
+        const enum system_interrupt_vector vector);
 
 /** @} */
 
@@ -313,11 +313,11 @@ enum status_code system_interrupt_clear_pending(
  */
 
 enum status_code system_interrupt_set_priority(
-		const enum system_interrupt_vector vector,
-		const enum system_interrupt_priority_level priority_level);
+        const enum system_interrupt_vector vector,
+        const enum system_interrupt_priority_level priority_level);
 
 enum system_interrupt_priority_level system_interrupt_get_priority(
-		const enum system_interrupt_vector vector);
+        const enum system_interrupt_vector vector);
 
 /** @} */
 
@@ -330,22 +330,22 @@ enum system_interrupt_priority_level system_interrupt_get_priority(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>ISR</td>
- *		<td>Interrupt Service Routine</td>
- *	</tr>
- *	<tr>
- *		<td>NMI</td>
- *		<td>Non-maskable Interrupt</td>
- *	</tr>
- *	<tr>
- *		<td>SERCOM</td>
- *		<td>Serial Communication Interface</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>ISR</td>
+ *      <td>Interrupt Service Routine</td>
+ *  </tr>
+ *  <tr>
+ *      <td>NMI</td>
+ *      <td>Non-maskable Interrupt</td>
+ *  </tr>
+ *  <tr>
+ *      <td>SERCOM</td>
+ *      <td>Serial Communication Interface</td>
+ *  </tr>
  * </table>
  *
  *
@@ -366,12 +366,12 @@ enum system_interrupt_priority_level system_interrupt_get_priority(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -390,36 +390,36 @@ enum system_interrupt_priority_level system_interrupt_get_priority(
  * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42122E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42122D</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42122C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42122B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42122A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42122E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42122D</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42122C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42122B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42122A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -427,4 +427,4 @@ enum system_interrupt_priority_level system_interrupt_get_priority(
 }
 #endif
 
-#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED
+#endif /* #ifndef SYSTEM_INTERRUPT_H_INCLUDED*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h
index 3bfebfe7f541..88f16149e9b7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd20/system_interrupt_features.h
@@ -52,12 +52,12 @@
 /* Generates a interrupt vector table enum list entry for a given module type
    and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
 #  define _MODULE_IRQn(n, module) \
-		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+        SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
 
 /* Generates interrupt vector table enum list entries for all instances of a
    given module type on the selected device. */
 #  define _SYSTEM_INTERRUPT_MODULES(name) \
-		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+        MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
 
 #  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
 #  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
@@ -84,58 +84,58 @@ enum system_interrupt_vector_samd20 {
 #else
 enum system_interrupt_vector {
 #endif
-	/** Interrupt vector index for a NMI interrupt */
-	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
-	/** Interrupt vector index for a Hard Fault memory access exception */
-	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
-	/** Interrupt vector index for a Supervisor Call exception */
-	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
-	/** Interrupt vector index for a Pending Supervisor interrupt */
-	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
-	/** Interrupt vector index for a System Tick interrupt */
-	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+    /** Interrupt vector index for a NMI interrupt */
+    SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+    /** Interrupt vector index for a Hard Fault memory access exception */
+    SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+    /** Interrupt vector index for a Supervisor Call exception */
+    SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+    /** Interrupt vector index for a Pending Supervisor interrupt */
+    SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+    /** Interrupt vector index for a System Tick interrupt */
+    SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
 
-	/** Interrupt vector index for a Power Manager peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
-	/** Interrupt vector index for a System Control peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
-	/** Interrupt vector index for a Watch Dog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
-	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
-	/** Interrupt vector index for an External Interrupt peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
-	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
-	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
-	/** Interrupt vector index for an Event System interrupt */
-	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+    /** Interrupt vector index for a Power Manager peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+    /** Interrupt vector index for a System Control peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+    /** Interrupt vector index for a Watch Dog peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+    /** Interrupt vector index for a Real Time Clock peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+    /** Interrupt vector index for an External Interrupt peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+    /** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+    SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+    /** Interrupt vector index for an Event System interrupt */
+    SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
 #if defined(__DOXYGEN__)
-	/** Interrupt vector index for a SERCOM peripheral interrupt.
-	 *
-	 *  Each specific device may contain several SERCOM peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
-	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
-	 *
-	 *  Each specific device may contain several TC peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_TC0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+    /** Interrupt vector index for a SERCOM peripheral interrupt.
+     *
+     *  Each specific device may contain several SERCOM peripherals; each module
+     *  instance will have its own entry in the table, with the instance number
+     *  substituted for "n" in the entry name (e.g.
+     *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+     */
+    SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+    /** Interrupt vector index for a Timer/Counter peripheral interrupt.
+     *
+     *  Each specific device may contain several TC peripherals; each module
+     *  instance will have its own entry in the table, with the instance number
+     *  substituted for "n" in the entry name (e.g.
+     *  \c SYSTEM_INTERRUPT_MODULE_TC0).
+     */
+    SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
 #else
-	_SYSTEM_INTERRUPT_MODULES(SERCOM)
-	_SYSTEM_INTERRUPT_MODULES(TC)
+    _SYSTEM_INTERRUPT_MODULES(SERCOM)
+    _SYSTEM_INTERRUPT_MODULES(TC)
 #endif
-	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
-	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
-	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+    /** Interrupt vector index for an Analog Comparator peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+    /** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+    /** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
 };
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
index 25dfa838db74..fd161517af21 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h
@@ -52,12 +52,12 @@
 /* Generates a interrupt vector table enum list entry for a given module type
    and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
 #  define _MODULE_IRQn(n, module) \
-		SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
+        SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
 
 /* Generates interrupt vector table enum list entries for all instances of a
    given module type on the selected device. */
 #  define _SYSTEM_INTERRUPT_MODULES(name) \
-		MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
+        MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
 
 #  define _SYSTEM_INTERRUPT_IPSR_MASK              0x0000003f
 #  define _SYSTEM_INTERRUPT_PRIORITY_MASK          0x00000003
@@ -86,107 +86,107 @@ enum system_interrupt_vector_samd21 {
 #else
 enum system_interrupt_vector {
 #endif
-	/** Interrupt vector index for a NMI interrupt */
-	SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
-	/** Interrupt vector index for a Hard Fault memory access exception */
-	SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
-	/** Interrupt vector index for a Supervisor Call exception */
-	SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
-	/** Interrupt vector index for a Pending Supervisor interrupt */
-	SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
-	/** Interrupt vector index for a System Tick interrupt */
-	SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
-
-	/** Interrupt vector index for a Power Manager peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
-	/** Interrupt vector index for a System Control peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
-	/** Interrupt vector index for a Watch Dog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
-	/** Interrupt vector index for a Real Time Clock peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
-	/** Interrupt vector index for an External Interrupt peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
-	/** Interrupt vector index for a Non Volatile Memory Controller interrupt */
-	SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
-	/** Interrupt vector index for a Direct Memory Access interrupt */
-	SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
+    /** Interrupt vector index for a NMI interrupt */
+    SYSTEM_INTERRUPT_NON_MASKABLE      = NonMaskableInt_IRQn,
+    /** Interrupt vector index for a Hard Fault memory access exception */
+    SYSTEM_INTERRUPT_HARD_FAULT        = HardFault_IRQn,
+    /** Interrupt vector index for a Supervisor Call exception */
+    SYSTEM_INTERRUPT_SV_CALL           = SVCall_IRQn,
+    /** Interrupt vector index for a Pending Supervisor interrupt */
+    SYSTEM_INTERRUPT_PENDING_SV        = PendSV_IRQn,
+    /** Interrupt vector index for a System Tick interrupt */
+    SYSTEM_INTERRUPT_SYSTICK           = SysTick_IRQn,
+
+    /** Interrupt vector index for a Power Manager peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_PM         = PM_IRQn,
+    /** Interrupt vector index for a System Control peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_SYSCTRL    = SYSCTRL_IRQn,
+    /** Interrupt vector index for a Watch Dog peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_WDT        = WDT_IRQn,
+    /** Interrupt vector index for a Real Time Clock peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_RTC        = RTC_IRQn,
+    /** Interrupt vector index for an External Interrupt peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_EIC        = EIC_IRQn,
+    /** Interrupt vector index for a Non Volatile Memory Controller interrupt */
+    SYSTEM_INTERRUPT_MODULE_NVMCTRL    = NVMCTRL_IRQn,
+    /** Interrupt vector index for a Direct Memory Access interrupt */
+    SYSTEM_INTERRUPT_MODULE_DMA        = DMAC_IRQn,
 #if defined(__DOXYGEN__) || defined(ID_USB)
-	/** Interrupt vector index for a Universal Serial Bus interrupt */
-	SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
+    /** Interrupt vector index for a Universal Serial Bus interrupt */
+    SYSTEM_INTERRUPT_MODULE_USB        = USB_IRQn,
 #endif
-	/** Interrupt vector index for an Event System interrupt */
-	SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
+    /** Interrupt vector index for an Event System interrupt */
+    SYSTEM_INTERRUPT_MODULE_EVSYS      = EVSYS_IRQn,
 #if defined(__DOXYGEN__)
-	/** Interrupt vector index for a SERCOM peripheral interrupt.
-	 *
-	 *  Each specific device may contain several SERCOM peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
-
-	/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
-	 *
-	 *  Each specific device may contain several TCC peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
-	 */
-	SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
-
-	/** Interrupt vector index for a Timer/Counter peripheral interrupt.
-	 *
-	 *  Each specific device may contain several TC peripherals; each module
-	 *  instance will have its own entry in the table, with the instance number
-	 *  substituted for "n" in the entry name (e.g.
-	 *  \c SYSTEM_INTERRUPT_MODULE_TC3).
-	 */
-	SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
+    /** Interrupt vector index for a SERCOM peripheral interrupt.
+     *
+     *  Each specific device may contain several SERCOM peripherals; each module
+     *  instance will have its own entry in the table, with the instance number
+     *  substituted for "n" in the entry name (e.g.
+     *  \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
+     */
+    SYSTEM_INTERRUPT_MODULE_SERCOMn    = SERCOMn_IRQn,
+
+    /** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
+     *
+     *  Each specific device may contain several TCC peripherals; each module
+     *  instance will have its own entry in the table, with the instance number
+     *  substituted for "n" in the entry name (e.g.
+     *  \c SYSTEM_INTERRUPT_MODULE_TCC0).
+     */
+    SYSTEM_INTERRUPT_MODULE_TCCn        = TCCn_IRQn,
+
+    /** Interrupt vector index for a Timer/Counter peripheral interrupt.
+     *
+     *  Each specific device may contain several TC peripherals; each module
+     *  instance will have its own entry in the table, with the instance number
+     *  substituted for "n" in the entry name (e.g.
+     *  \c SYSTEM_INTERRUPT_MODULE_TC3).
+     */
+    SYSTEM_INTERRUPT_MODULE_TCn        = TCn_IRQn,
 #else
-	_SYSTEM_INTERRUPT_MODULES(SERCOM)
+    _SYSTEM_INTERRUPT_MODULES(SERCOM)
 
-	_SYSTEM_INTERRUPT_MODULES(TCC)
+    _SYSTEM_INTERRUPT_MODULES(TCC)
 
-	SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
-	SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
-	SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
+    SYSTEM_INTERRUPT_MODULE_TC3        = TC3_IRQn,
+    SYSTEM_INTERRUPT_MODULE_TC4        = TC4_IRQn,
+    SYSTEM_INTERRUPT_MODULE_TC5        = TC5_IRQn,
 #  if defined(ID_TC6)
-	SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
+    SYSTEM_INTERRUPT_MODULE_TC6        = TC6_IRQn,
 #  endif
 #  if defined(ID_TC7)
-	SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
+    SYSTEM_INTERRUPT_MODULE_TC7        = TC7_IRQn,
 #  endif
 #endif
 
 #if defined(__DOXYGEN__) || defined(ID_ADC)
-	/** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
+    /** Interrupt vector index for an Analog-to-Digital peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_ADC        = ADC_IRQn,
 #endif
 
 #if defined(__DOXYGEN__) || defined(ID_AC)
-	/** Interrupt vector index for an Analog Comparator peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
+    /** Interrupt vector index for an Analog Comparator peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_AC         = AC_IRQn,
 #endif
 
 #if defined(__DOXYGEN__) || defined(ID_DAC)
-	/** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
+    /** Interrupt vector index for a Digital-to-Analog peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_DAC        = DAC_IRQn,
 #endif
 #if defined(__DOXYGEN__) || defined(ID_PTC)
-	/** Interrupt vector index for a Peripheral Touch Controller peripheral
-	 *  interrupt */
-	SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
+    /** Interrupt vector index for a Peripheral Touch Controller peripheral
+     *  interrupt */
+    SYSTEM_INTERRUPT_MODULE_PTC        = PTC_IRQn,
 #endif
 #if defined(__DOXYGEN__) || defined(ID_I2S)
-	/** Interrupt vector index for a Inter-IC Sound Interface peripheral
-	 *  interrupt */
-	SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
+    /** Interrupt vector index for a Inter-IC Sound Interface peripheral
+     *  interrupt */
+    SYSTEM_INTERRUPT_MODULE_I2S        = I2S_IRQn,
 #endif
 #if defined(__DOXYGEN__) || defined(ID_AC1)
-	/** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
-	SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
+    /** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */
+    SYSTEM_INTERRUPT_MODULE_AC1        = AC1_IRQn,
 #endif
 };
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c
index a2c9c7cdcc75..44b39eca5405 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.c
@@ -58,91 +58,100 @@
  * \param[in] config    Configuration settings for the pin
  */
 static void _system_pinmux_config(
-		PortGroup *const port,
-		const uint32_t pin_mask,
-		const struct system_pinmux_config *const config)
+        PortGroup *const port,
+        const uint32_t pin_mask,
+        const struct system_pinmux_config *const config)
 {
-	Assert(port);
-	Assert(config);
+    Assert(port);
+    Assert(config);
 
-	/* Track the configuration bits into a temporary variable before writing */
-	uint32_t pin_cfg = 0;
+    /* Track the configuration bits into a temporary variable before writing */
+    uint32_t pin_cfg = 0;
 
-	/* Enabled powersave mode, don't create configuration */
-	if (!config->powersave) {
-		/* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
-		 * be written later) and store the new MUX mask */
-		if (config->mux_position != SYSTEM_PINMUX_GPIO) {
-			pin_cfg |= PORT_WRCONFIG_PMUXEN;
-			pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
-		}
+    /* Enabled powersave mode, don't create configuration */
+    if (!config->powersave)
+    {
+        /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will
+         * be written later) and store the new MUX mask */
+        if (config->mux_position != SYSTEM_PINMUX_GPIO)
+        {
+            pin_cfg |= PORT_WRCONFIG_PMUXEN;
+            pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
+        }
 
-		/* Check if the user has requested that the input buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Enable input buffer flag */
-			pin_cfg |= PORT_WRCONFIG_INEN;
+        /* Check if the user has requested that the input buffer be enabled */
+        if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
+                (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK))
+                {
+            /* Enable input buffer flag */
+            pin_cfg |= PORT_WRCONFIG_INEN;
 
-			/* Enable pull-up/pull-down control flag if requested */
-			if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
-				pin_cfg |= PORT_WRCONFIG_PULLEN;
-			}
+            /* Enable pull-up/pull-down control flag if requested */
+            if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE)
+            {
+                pin_cfg |= PORT_WRCONFIG_PULLEN;
+            }
 
-			/* Clear the port DIR bits to disable the output buffer */
-			port->DIRCLR.reg = pin_mask;
-		}
+            /* Clear the port DIR bits to disable the output buffer */
+            port->DIRCLR.reg = pin_mask;
+        }
 
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Cannot use a pull-up if the output driver is enabled,
-			 * if requested the input buffer can only sample the current
-			 * output state */
-			pin_cfg &= ~PORT_WRCONFIG_PULLEN;
-		}
-	} else {
-		port->DIRCLR.reg = pin_mask;
-	}
+        /* Check if the user has requested that the output buffer be enabled */
+        if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+                (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK))
+                {
+            /* Cannot use a pull-up if the output driver is enabled,
+             * if requested the input buffer can only sample the current
+             * output state */
+            pin_cfg &= ~PORT_WRCONFIG_PULLEN;
+        }
+    } else {
+        port->DIRCLR.reg = pin_mask;
+    }
 
-	/* The Write Configuration register (WRCONFIG) requires the
-	 * pins to to grouped into two 16-bit half-words - split them out here */
-	uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
-	uint32_t upper_pin_mask = (pin_mask >> 16);
+    /* The Write Configuration register (WRCONFIG) requires the
+     * pins to to grouped into two 16-bit half-words - split them out here */
+    uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
+    uint32_t upper_pin_mask = (pin_mask >> 16);
 
-	/* Configure the lower 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
+    /* Configure the lower 16-bits of the port to the desired configuration,
+     * including the pin peripheral multiplexer just in case it is enabled */
+    port->WRCONFIG.reg
+        = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+            pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
 
-	/* Configure the upper 16-bits of the port to the desired configuration,
-	 * including the pin peripheral multiplexer just in case it is enabled */
-	port->WRCONFIG.reg
-		= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
-			pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
-			PORT_WRCONFIG_HWSEL;
+    /* Configure the upper 16-bits of the port to the desired configuration,
+     * including the pin peripheral multiplexer just in case it is enabled */
+    port->WRCONFIG.reg
+        = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
+            pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
+            PORT_WRCONFIG_HWSEL;
 
-	if(!config->powersave) {
-		/* Set the pull-up state once the port pins are configured if one was
-		 * requested and it does not violate the valid set of port
-		 * configurations */
-		if (pin_cfg & PORT_WRCONFIG_PULLEN) {
-			/* Set the OUT register bits to enable the pull-up if requested,
-			 * clear to enable pull-down */
-			if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
-				port->OUTSET.reg = pin_mask;
-			} else {
-				port->OUTCLR.reg = pin_mask;
-			}
-		}
+    if(!config->powersave)
+    {
+        /* Set the pull-up state once the port pins are configured if one was
+         * requested and it does not violate the valid set of port
+         * configurations */
+        if (pin_cfg & PORT_WRCONFIG_PULLEN)
+        {
+            /* Set the OUT register bits to enable the pull-up if requested,
+             * clear to enable pull-down */
+            if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP)
+            {
+                port->OUTSET.reg = pin_mask;
+            } else {
+                port->OUTCLR.reg = pin_mask;
+            }
+        }
 
-		/* Check if the user has requested that the output buffer be enabled */
-		if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
-				(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
-			/* Set the port DIR bits to enable the output buffer */
-			port->DIRSET.reg = pin_mask;
-		}
-	}
+        /* Check if the user has requested that the output buffer be enabled */
+        if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
+                (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK))
+                {
+            /* Set the port DIR bits to enable the output buffer */
+            port->DIRSET.reg = pin_mask;
+        }
+    }
 }
 
 /**
@@ -158,13 +167,13 @@ static void _system_pinmux_config(
  * \param[in] config    Configuration settings for the pin
  */
 void system_pinmux_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct system_pinmux_config *const config)
+        const uint8_t gpio_pin,
+        const struct system_pinmux_config *const config)
 {
-	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_mask = (1UL << (gpio_pin % 32));
+    PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_mask = (1UL << (gpio_pin % 32));
 
-	_system_pinmux_config(port, pin_mask, config);
+    _system_pinmux_config(port, pin_mask, config);
 }
 
 /**
@@ -181,17 +190,19 @@ void system_pinmux_pin_set_config(
  * \param[in] config    Configuration settings for the pin
  */
 void system_pinmux_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct system_pinmux_config *const config)
+        PortGroup *const port,
+        const uint32_t mask,
+        const struct system_pinmux_config *const config)
 {
-	Assert(port);
+    Assert(port);
 
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			_system_pinmux_config(port, (1UL << i), config);
-		}
-	}
+    for (int i = 0; i < 32; i++)
+    {
+        if (mask & (1UL << i))
+        {
+            _system_pinmux_config(port, (1UL << i), config);
+        }
+    }
 }
 
 /**
@@ -206,17 +217,18 @@ void system_pinmux_group_set_config(
  * \param[in] mode     New pin sampling mode to configure
  */
 void system_pinmux_group_set_input_sample_mode(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_sample mode)
+        PortGroup *const port,
+        const uint32_t mask,
+        const enum system_pinmux_pin_sample mode)
 {
-	Assert(port);
+    Assert(port);
 
-	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
-		port->CTRL.reg |= mask;
-	} else {
-		port->CTRL.reg &= ~mask;
-	}
+    if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND)
+    {
+        port->CTRL.reg |= mask;
+    } else {
+        port->CTRL.reg &= ~mask;
+    }
 }
 
 #ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER
@@ -232,21 +244,24 @@ void system_pinmux_group_set_input_sample_mode(
  * \param[in] mode     New pin slew rate mode to configure
  */
 void system_pinmux_group_set_output_slew_rate(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_slew_rate mode)
+        PortGroup *const port,
+        const uint32_t mask,
+        const enum system_pinmux_pin_slew_rate mode)
 {
-	Assert(port);
+    Assert(port);
 
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
-				port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
-			}
-		}
-	}
+    for (int i = 0; i < 32; i++)
+    {
+        if (mask & (1UL << i))
+        {
+            if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED)
+            {
+                port->PINCFG[i].reg |=  PORT_PINCFG_SLEWLIM;
+            } else {
+                port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM;
+            }
+        }
+    }
 }
 #endif
 
@@ -262,21 +277,24 @@ void system_pinmux_group_set_output_slew_rate(
  * \param[in] mode     New output driver strength mode to configure
  */
 void system_pinmux_group_set_output_strength(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_strength mode)
+        PortGroup *const port,
+        const uint32_t mask,
+        const enum system_pinmux_pin_strength mode)
 {
-	Assert(port);
+    Assert(port);
 
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
-				port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
-			}
-		}
-	}
+    for (int i = 0; i < 32; i++)
+    {
+        if (mask & (1UL << i))
+        {
+            if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH)
+            {
+                port->PINCFG[i].reg |=  PORT_PINCFG_DRVSTR;
+            } else {
+                port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR;
+            }
+        }
+    }
 }
 #endif
 
@@ -292,20 +310,23 @@ void system_pinmux_group_set_output_strength(
  * \param[in] mode New pad output driver mode to configure
  */
 void system_pinmux_group_set_output_drive(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_drive mode)
+        PortGroup *const port,
+        const uint32_t mask,
+        const enum system_pinmux_pin_drive mode)
 {
-	Assert(port);
+    Assert(port);
 
-	for (int i = 0; i < 32; i++) {
-		if (mask & (1UL << i)) {
-			if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
-				port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
-			} else {
-				port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
-			}
-		}
-	}
+    for (int i = 0; i < 32; i++)
+    {
+        if (mask & (1UL << i))
+        {
+            if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN)
+            {
+                port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN;
+            } else {
+                port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN;
+            }
+        }
+    }
 }
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h
index e057ad60ba6e..07e8e3af5ba4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/pinmux/pinmux.h
@@ -217,15 +217,15 @@ extern "C" {
  * structure, to indicate the direction the pin should use.
  */
 enum system_pinmux_pin_dir {
-	/** The pin's input buffer should be enabled, so that the pin state can
-	 *  be read */
-	SYSTEM_PINMUX_PIN_DIR_INPUT,
-	/** The pin's output buffer should be enabled, so that the pin state can
-	 *  be set (but not read back) */
-	SYSTEM_PINMUX_PIN_DIR_OUTPUT,
-	/** The pin's output and input buffers should both be enabled, so that the
-	 *  pin state can be set and read back */
-	SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
+    /** The pin's input buffer should be enabled, so that the pin state can
+     *  be read */
+    SYSTEM_PINMUX_PIN_DIR_INPUT,
+    /** The pin's output buffer should be enabled, so that the pin state can
+     *  be set (but not read back) */
+    SYSTEM_PINMUX_PIN_DIR_OUTPUT,
+    /** The pin's output and input buffers should both be enabled, so that the
+     *  pin state can be set and read back */
+    SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
 };
 
 /**
@@ -235,12 +235,12 @@ enum system_pinmux_pin_dir {
  * structure, to indicate the type of logic level pull the pin should use.
  */
 enum system_pinmux_pin_pull {
-	/** No logical pull should be applied to the pin */
-	SYSTEM_PINMUX_PIN_PULL_NONE,
-	/** Pin should be pulled up when idle */
-	SYSTEM_PINMUX_PIN_PULL_UP,
-	/** Pin should be pulled down when idle */
-	SYSTEM_PINMUX_PIN_PULL_DOWN,
+    /** No logical pull should be applied to the pin */
+    SYSTEM_PINMUX_PIN_PULL_NONE,
+    /** Pin should be pulled up when idle */
+    SYSTEM_PINMUX_PIN_PULL_UP,
+    /** Pin should be pulled down when idle */
+    SYSTEM_PINMUX_PIN_PULL_DOWN,
 };
 
 /**
@@ -250,10 +250,10 @@ enum system_pinmux_pin_pull {
  * structure, to indicate the type of sampling a port pin should use.
  */
 enum system_pinmux_pin_sample {
-	/** Pin input buffer should continuously sample the pin state */
-	SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
-	/** Pin input buffer should be enabled when the IN register is read */
-	SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
+    /** Pin input buffer should continuously sample the pin state */
+    SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
+    /** Pin input buffer should be enabled when the IN register is read */
+    SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
 };
 
 /**
@@ -264,22 +264,22 @@ enum system_pinmux_pin_sample {
  * before being modified by the user application.
  */
 struct system_pinmux_config {
-	/** MUX index of the peripheral that should control the pin, if peripheral
-	 *  control is desired. For GPIO use, this should be set to
-	 *  \ref SYSTEM_PINMUX_GPIO. */
-	uint8_t mux_position;
-
-	/** Port buffer input/output direction */
-	enum system_pinmux_pin_dir direction;
-
-	/** Logic level pull of the input buffer */
-	enum system_pinmux_pin_pull input_pull;
-
-	/** Enable lowest possible powerstate on the pin
-	 *
-	 *  \note All other configurations will be ignored, the pin will be disabled.
-	 */
-	bool powersave;
+    /** MUX index of the peripheral that should control the pin, if peripheral
+     *  control is desired. For GPIO use, this should be set to
+     *  \ref SYSTEM_PINMUX_GPIO. */
+    uint8_t mux_position;
+
+    /** Port buffer input/output direction */
+    enum system_pinmux_pin_dir direction;
+
+    /** Logic level pull of the input buffer */
+    enum system_pinmux_pin_pull input_pull;
+
+    /** Enable lowest possible powerstate on the pin
+     *
+     *  \note All other configurations will be ignored, the pin will be disabled.
+     */
+    bool powersave;
 };
 
 /** \name Configuration and Initialization
@@ -301,26 +301,26 @@ struct system_pinmux_config {
  * \param[out] config  Configuration structure to initialize to default values
  */
 static inline void system_pinmux_get_config_defaults(
-		struct system_pinmux_config *const config)
+        struct system_pinmux_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Default configuration values */
-	config->mux_position = SYSTEM_PINMUX_GPIO;
-	config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
-	config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
-	config->powersave    = false;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Default configuration values */
+    config->mux_position = SYSTEM_PINMUX_GPIO;
+    config->direction    = SYSTEM_PINMUX_PIN_DIR_INPUT;
+    config->input_pull   = SYSTEM_PINMUX_PIN_PULL_UP;
+    config->powersave    = false;
 }
 
 void system_pinmux_pin_set_config(
-		const uint8_t gpio_pin,
-		const struct system_pinmux_config *const config);
+        const uint8_t gpio_pin,
+        const struct system_pinmux_config *const config);
 
 void system_pinmux_group_set_config(
-		PortGroup *const port,
-		const uint32_t mask,
-		const struct system_pinmux_config *const config);
+        PortGroup *const port,
+        const uint32_t mask,
+        const struct system_pinmux_config *const config);
 
 /** @} */
 
@@ -339,26 +339,27 @@ void system_pinmux_group_set_config(
  * \return Base address of the associated PORT module.
  */
 static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	uint8_t port_index  = (gpio_pin / 128);
-	uint8_t group_index = (gpio_pin / 32);
-
-	/* Array of available ports */
-	Port *const ports[PORT_INST_NUM] = PORT_INSTS;
-
-	if (port_index < PORT_INST_NUM) {
-		return &(ports[port_index]->Group[group_index]);
-	} else {
-		Assert(false);
-		return NULL;
-	}
+    uint8_t port_index  = (gpio_pin / 128);
+    uint8_t group_index = (gpio_pin / 32);
+
+    /* Array of available ports */
+    Port *const ports[PORT_INST_NUM] = PORT_INSTS;
+
+    if (port_index < PORT_INST_NUM)
+    {
+        return &(ports[port_index]->Group[group_index]);
+    } else {
+        Assert(false);
+        return NULL;
+    }
 }
 
 void system_pinmux_group_set_input_sample_mode(
-		PortGroup *const port,
-		const uint32_t mask,
-		const enum system_pinmux_pin_sample mode);
+        PortGroup *const port,
+        const uint32_t mask,
+        const enum system_pinmux_pin_sample mode);
 
 /** @} */
 
@@ -376,23 +377,25 @@ void system_pinmux_group_set_input_sample_mode(
  * \return Currently selected peripheral index on the specified pin.
  */
 static inline uint8_t system_pinmux_pin_get_mux_position(
-		const uint8_t gpio_pin)
+        const uint8_t gpio_pin)
 {
-	PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_index = (gpio_pin % 32);
-
-	if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
-		return SYSTEM_PINMUX_GPIO;
-	}
-
-	uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
-
-	if (pin_index & 1) {
-		return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
-	}
-	else {
-		return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
-	}
+    PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_index = (gpio_pin % 32);
+
+    if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN))
+    {
+        return SYSTEM_PINMUX_GPIO;
+    }
+
+    uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
+
+    if (pin_index & 1)
+    {
+        return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
+    }
+    else {
+        return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
+    }
 }
 
 /**
@@ -406,17 +409,18 @@ static inline uint8_t system_pinmux_pin_get_mux_position(
  * \param[in] mode     New pin sampling mode to configure
  */
 static inline void system_pinmux_pin_set_input_sample_mode(
-		const uint8_t gpio_pin,
-		const enum system_pinmux_pin_sample mode)
+        const uint8_t gpio_pin,
+        const enum system_pinmux_pin_sample mode)
 {
-	PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
-	uint32_t pin_index = (gpio_pin % 32);
-
-	if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
-		port->CTRL.reg |= (1 << pin_index);
-	} else {
-		port->CTRL.reg &= ~(1 << pin_index);
-	}
+    PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
+    uint32_t pin_index = (gpio_pin % 32);
+
+    if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND)
+    {
+        port->CTRL.reg |= (1 << pin_index);
+    } else {
+        port->CTRL.reg &= ~(1 << pin_index);
+    }
 }
 
 /** @} */
@@ -452,7 +456,8 @@ static inline void system_pinmux_pin_set_output_strength(
   PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
   uint32_t pin_index = (gpio_pin % 32);
 
-  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) {
+  if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH)
+  {
     port->PINCFG[pin_index].reg |=  PORT_PINCFG_DRVSTR;
   }
  else {
@@ -498,7 +503,8 @@ static inline void system_pinmux_pin_set_output_slew_rate(
   PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
   uint32_t pin_index = (gpio_pin % 32);
 
-  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) {
+  if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED)
+  {
     port->PINCFG[pin_index].reg |=  PORT_PINCFG_SLEWLIM;
   }
   else {
@@ -542,7 +548,8 @@ static inline void system_pinmux_pin_set_output_drive(
   PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
   uint32_t pin_index = (gpio_pin % 32);
 
-  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) {
+  if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN)
+  {
     port->PINCFG[pin_index].reg |=  PORT_PINCFG_ODRAIN;
   }
   else {
@@ -569,18 +576,18 @@ void system_pinmux_group_set_output_drive(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>GPIO</td>
- *		<td>General Purpose Input/Output</td>
- *	</tr>
- *	<tr>
- *		<td>MUX</td>
- *		<td>Multiplexer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>GPIO</td>
+ *      <td>General Purpose Input/Output</td>
+ *  </tr>
+ *  <tr>
+ *      <td>MUX</td>
+ *      <td>Multiplexer</td>
+ *  </tr>
  * </table>
  *
  *
@@ -601,23 +608,23 @@ void system_pinmux_group_set_output_drive(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Removed code of open drain, slew limit and drive strength
- *		features</td>
- *	</tr>
- *	<tr>
- *		<td>Fixed broken sampling mode function implementations, which wrote
- *		    corrupt configuration values to the device registers</td>
- *	</tr>
- *	<tr>
- *		<td>Added missing NULL pointer asserts to the PORT driver functions</td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Removed code of open drain, slew limit and drive strength
+ *      features</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Fixed broken sampling mode function implementations, which wrote
+ *          corrupt configuration values to the device registers</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Added missing NULL pointer asserts to the PORT driver functions</td>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -635,41 +642,41 @@ void system_pinmux_group_set_output_drive(
  * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42121F</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42121E</td>
- *		<td>12/2014</td>
- *		<td>Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42121D</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42121C</td>
- *		<td>09/2013</td>
- *		<td>Fixed incorrect documentation for the device pin sampling mode</td>
- *	</tr>
- *	<tr>
- *		<td>42121B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42121A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121F</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121E</td>
+ *      <td>12/2014</td>
+ *      <td>Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121D</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121C</td>
+ *      <td>09/2013</td>
+ *      <td>Fixed incorrect documentation for the device pin sampling mode</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42121A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h
index 53c02e906380..939547d5ac1b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_c/power.h
@@ -61,14 +61,14 @@ extern "C" {
  * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
  */
 enum system_sleepmode {
-	/** IDLE 0 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_0 = PM_SLEEPCFG_SLEEPMODE(0),
-	/** IDLE 1 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_1 = PM_SLEEPCFG_SLEEPMODE(0x1),
-	/** IDLE 2 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_2 = PM_SLEEPCFG_SLEEPMODE(0x2),
-	/** Standby sleep mode */
-	SYSTEM_SLEEPMODE_STANDBY = PM_SLEEPCFG_SLEEPMODE(0x4),
+    /** IDLE 0 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_0 = PM_SLEEPCFG_SLEEPMODE(0),
+    /** IDLE 1 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_1 = PM_SLEEPCFG_SLEEPMODE(0x1),
+    /** IDLE 2 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_2 = PM_SLEEPCFG_SLEEPMODE(0x2),
+    /** Standby sleep mode */
+    SYSTEM_SLEEPMODE_STANDBY = PM_SLEEPCFG_SLEEPMODE(0x4),
 };
 
 /**
@@ -77,12 +77,12 @@ enum system_sleepmode {
  * Voltage references selection for ADC/DAC.
  */
 enum system_voltage_references_sel {
-	/** 1.024V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_1V024  = SUPC_VREF_SEL_1V024_Val,
-	/** 2.048V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_2V048  = SUPC_VREF_SEL_2V048_Val,
-	/** 4.096V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_4V096    = SUPC_VREF_SEL_4V096_Val,
+    /** 1.024V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_1V024  = SUPC_VREF_SEL_1V024_Val,
+    /** 2.048V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_2V048  = SUPC_VREF_SEL_2V048_Val,
+    /** 4.096V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_4V096    = SUPC_VREF_SEL_4V096_Val,
 };
 
 
@@ -93,10 +93,10 @@ enum system_voltage_references_sel {
  * device.
  */
 enum system_voltage_reference {
-	/** Temperature sensor voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
-	/** Voltage reference output for ADC/DAC */
-	SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
+    /** Temperature sensor voltage reference */
+    SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+    /** Voltage reference output for ADC/DAC */
+    SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
 };
 
 /**
@@ -105,8 +105,8 @@ enum system_voltage_reference {
  * Configuration structure for VREG.
  */
 struct system_voltage_regulator_config {
-	/** Run in standby in standby sleep mode */
-	bool run_in_standby;
+    /** Run in standby in standby sleep mode */
+    bool run_in_standby;
 };
 
 /**
@@ -115,12 +115,12 @@ struct system_voltage_regulator_config {
  * Configuration structure for VREF.
  */
 struct system_voltage_references_config {
-	/** Voltage references selection */
-	enum system_voltage_references_sel  sel;
-	/** On demand control */
-	bool on_demand;
-	/** Run in standby */
-	bool run_in_standby;
+    /** Voltage references selection */
+    enum system_voltage_references_sel  sel;
+    /** On demand control */
+    bool on_demand;
+    /** Run in standby */
+    bool run_in_standby;
 };
 
 /**
@@ -128,12 +128,12 @@ struct system_voltage_references_config {
  *
  */
 enum system_vreg_switch_mode {
-	/** Automatic mode */
-	SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
-	/** Performance oriented */
-	SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
-	/** Low Power consumption oriented */
-	SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
+    /** Automatic mode */
+    SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
+    /** Performance oriented */
+    SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
+    /** Low Power consumption oriented */
+    SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
 };
 
 /**
@@ -142,10 +142,10 @@ enum system_vreg_switch_mode {
  * Configuration structure for standby mode.
  */
 struct system_standby_config {
-	/** Regulator switch mode in standby */
-	enum system_vreg_switch_mode vreg_switch_mode;
-	/** Back bias for HMCRAMCHS (false: no, true: standby) */
-	bool hmcramchs_back_bias;
+    /** Regulator switch mode in standby */
+    enum system_vreg_switch_mode vreg_switch_mode;
+    /** Back bias for HMCRAMCHS (false: no, true: standby) */
+    bool hmcramchs_back_bias;
 };
 
 /**
@@ -162,10 +162,10 @@ struct system_standby_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_voltage_regulator_get_config_defaults(
-		struct system_voltage_regulator_config *const config)
+        struct system_voltage_regulator_config *const config)
 {
-	Assert(config);
-	config->run_in_standby       = false;
+    Assert(config);
+    config->run_in_standby       = false;
 }
 
 /**
@@ -177,9 +177,9 @@ static inline void system_voltage_regulator_get_config_defaults(
  *                    the new config
  */
 static inline void system_voltage_regulator_set_config(
-		struct system_voltage_regulator_config *const config)
+        struct system_voltage_regulator_config *const config)
 {
-	SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
+    SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
 }
 
 /**
@@ -189,7 +189,7 @@ static inline void system_voltage_regulator_set_config(
  */
 static inline void system_voltage_regulator_enable(void)
 {
-	SUPC->VREG.reg |= SUPC_VREG_ENABLE;
+    SUPC->VREG.reg |= SUPC_VREG_ENABLE;
 }
 
 /**
@@ -199,7 +199,7 @@ static inline void system_voltage_regulator_enable(void)
  */
 static inline void system_voltage_regulator_disable(void)
 {
-	SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
+    SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
 }
 
 /**
@@ -222,12 +222,12 @@ static inline void system_voltage_regulator_disable(void)
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_voltage_reference_get_config_defaults(
-		struct system_voltage_references_config *const config)
+        struct system_voltage_references_config *const config)
 {
-	Assert(config);
-	config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V024;
-	config->on_demand      = false;
-	config->run_in_standby = false;
+    Assert(config);
+    config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V024;
+    config->on_demand      = false;
+    config->run_in_standby = false;
 }
 
 /**
@@ -239,12 +239,12 @@ static inline void system_voltage_reference_get_config_defaults(
  *                    the new config
  */
 static inline void system_voltage_reference_set_config(
-		struct system_voltage_references_config *const config)
+        struct system_voltage_references_config *const config)
 {
-	Assert(config);
-	SUPC->VREF.bit.SEL      = config->sel;
-	SUPC->VREF.bit.ONDEMAND = config->on_demand;
-	SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
+    Assert(config);
+    SUPC->VREF.bit.SEL      = config->sel;
+    SUPC->VREF.bit.ONDEMAND = config->on_demand;
+    SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
 }
 
 /**
@@ -256,19 +256,20 @@ static inline void system_voltage_reference_set_config(
  * \param[in] vref  Voltage reference to enable
  */
 static inline void system_voltage_reference_enable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SUPC->VREF.reg |= SUPC_VREF_TSEN;
-			break;
-		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
-			SUPC->VREF.reg |= SUPC_VREF_VREFOE;
-			break;
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SUPC->VREF.reg |= SUPC_VREF_TSEN;
+            break;
+        case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+            SUPC->VREF.reg |= SUPC_VREF_VREFOE;
+            break;
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -279,19 +280,20 @@ static inline void system_voltage_reference_enable(
  * \param[in] vref  Voltage reference to disable
  */
 static inline void system_voltage_reference_disable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
-			break;
-		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
-			SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
-			break;
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
+            break;
+        case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+            SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
+            break;
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -315,9 +317,9 @@ static inline void system_voltage_reference_disable(
  * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
  */
 static inline void system_set_sleepmode(
-	const enum system_sleepmode sleep_mode)
+    const enum system_sleepmode sleep_mode)
 {
-	PM->SLEEPCFG.reg = sleep_mode;
+    PM->SLEEPCFG.reg = sleep_mode;
 }
 
 
@@ -331,8 +333,8 @@ static inline void system_set_sleepmode(
  */
 static inline void system_sleep(void)
 {
-	__DSB();
-	__WFI();
+    __DSB();
+    __WFI();
 }
 
 /**
@@ -354,12 +356,12 @@ static inline void system_sleep(void)
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_standby_get_config_defaults(
-		struct system_standby_config *const config)
+        struct system_standby_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
-	config->hmcramchs_back_bias = false;
+    config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
+    config->hmcramchs_back_bias = false;
 }
 
 /**
@@ -371,12 +373,12 @@ static inline void system_standby_get_config_defaults(
  *                    the new config
  */
 static inline void system_standby_set_config(
-		struct system_standby_config *const config)
+        struct system_standby_config *const config)
 {
-	Assert(config);
+    Assert(config);
 
-	PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
-					 PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
+    PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
+                     PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h
index e63f1cdb62f2..9896b7a3ef21 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_d_r_h/power.h
@@ -68,10 +68,10 @@ extern "C" {
  * device.
  */
 enum system_voltage_reference {
-	/** Temperature sensor voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
-	/** Bandgap voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
+    /** Temperature sensor voltage reference */
+    SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+    /** Bandgap voltage reference */
+    SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
 };
 
 /**
@@ -81,14 +81,14 @@ enum system_voltage_reference {
  * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
  */
 enum system_sleepmode {
-	/** IDLE 0 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_0,
-	/** IDLE 1 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_1,
-	/** IDLE 2 sleep mode */
-	SYSTEM_SLEEPMODE_IDLE_2,
-	/** Standby sleep mode */
-	SYSTEM_SLEEPMODE_STANDBY,
+    /** IDLE 0 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_0,
+    /** IDLE 1 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_1,
+    /** IDLE 2 sleep mode */
+    SYSTEM_SLEEPMODE_IDLE_2,
+    /** Standby sleep mode */
+    SYSTEM_SLEEPMODE_STANDBY,
 };
 
 
@@ -107,21 +107,22 @@ enum system_sleepmode {
  * \param[in] vref  Voltage reference to enable
  */
 static inline void system_voltage_reference_enable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
-			break;
-
-		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
-			SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
-			break;
-
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
+            break;
+
+        case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+            SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
+            break;
+
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -132,21 +133,22 @@ static inline void system_voltage_reference_enable(
  * \param[in] vref  Voltage reference to disable
  */
 static inline void system_voltage_reference_disable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
-			break;
-
-		case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
-			SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
-			break;
-
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
+            break;
+
+        case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
+            SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
+            break;
+
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -175,52 +177,55 @@ static inline void system_voltage_reference_disable(
  *                                 available
  */
 static inline enum status_code system_set_sleepmode(
-	const enum system_sleepmode sleep_mode)
+    const enum system_sleepmode sleep_mode)
 {
 
 #if (SAMD20 || SAMD21 || SAMR21)
 
-	/* Get MCU revision */
-	uint32_t rev = DSU->DID.reg;
+    /* Get MCU revision */
+    uint32_t rev = DSU->DID.reg;
 
-	rev &= DSU_DID_REVISION_Msk;
-	rev = rev >> DSU_DID_REVISION_Pos;
+    rev &= DSU_DID_REVISION_Msk;
+    rev = rev >> DSU_DID_REVISION_Pos;
 
 #if (SAMD20)
-	if (rev < _SYSTEM_MCU_REVISION_E) {
-		/* Errata 13140: Make sure that the Flash does not power all the way down
-		 * when in sleep mode. */
-		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
-	}
+    if (rev < _SYSTEM_MCU_REVISION_E)
+    {
+        /* Errata 13140: Make sure that the Flash does not power all the way down
+         * when in sleep mode. */
+        NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+    }
 #endif
 
 #if (SAMD21 || SAMR21)
-	if (rev < _SYSTEM_MCU_REVISION_D) {
-		/* Errata 13140: Make sure that the Flash does not power all the way down
-		 * when in sleep mode. */
-		NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
-	}
+    if (rev < _SYSTEM_MCU_REVISION_D)
+    {
+        /* Errata 13140: Make sure that the Flash does not power all the way down
+         * when in sleep mode. */
+        NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val;
+    }
 #endif
 
 #endif
 
-	switch (sleep_mode) {
-		case SYSTEM_SLEEPMODE_IDLE_0:
-		case SYSTEM_SLEEPMODE_IDLE_1:
-		case SYSTEM_SLEEPMODE_IDLE_2:
-			SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
-			PM->SLEEP.reg = sleep_mode;
-			break;
+    switch (sleep_mode)
+    {
+        case SYSTEM_SLEEPMODE_IDLE_0:
+        case SYSTEM_SLEEPMODE_IDLE_1:
+        case SYSTEM_SLEEPMODE_IDLE_2:
+            SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+            PM->SLEEP.reg = sleep_mode;
+            break;
 
-		case SYSTEM_SLEEPMODE_STANDBY:
-			SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
-			break;
+        case SYSTEM_SLEEPMODE_STANDBY:
+            SCB->SCR |=  SCB_SCR_SLEEPDEEP_Msk;
+            break;
 
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -233,8 +238,8 @@ static inline enum status_code system_set_sleepmode(
  */
 static inline void system_sleep(void)
 {
-	__DSB();
-	__WFI();
+    __DSB();
+    __WFI();
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h
index eddf533f56cf..413a1b6d202a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/power/power_sam_l/power.h
@@ -65,14 +65,14 @@ extern "C" {
  * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
  */
 enum system_sleepmode {
-	/** IDLE sleep mode */
-	SYSTEM_SLEEPMODE_IDLE       = PM_SLEEPCFG_SLEEPMODE(0x2),
-	/** STANDBY sleep mode */
-	SYSTEM_SLEEPMODE_STANDBY    = PM_SLEEPCFG_SLEEPMODE_STANDBY,
-	/** BACKUP sleep mode */
-	SYSTEM_SLEEPMODE_BACKUP     = PM_SLEEPCFG_SLEEPMODE_BACKUP,
-	/** OFF sleep mode */
-	SYSTEM_SLEEPMODE_OFF        = PM_SLEEPCFG_SLEEPMODE_OFF,
+    /** IDLE sleep mode */
+    SYSTEM_SLEEPMODE_IDLE       = PM_SLEEPCFG_SLEEPMODE(0x2),
+    /** STANDBY sleep mode */
+    SYSTEM_SLEEPMODE_STANDBY    = PM_SLEEPCFG_SLEEPMODE_STANDBY,
+    /** BACKUP sleep mode */
+    SYSTEM_SLEEPMODE_BACKUP     = PM_SLEEPCFG_SLEEPMODE_BACKUP,
+    /** OFF sleep mode */
+    SYSTEM_SLEEPMODE_OFF        = PM_SLEEPCFG_SLEEPMODE_OFF,
 };
 
 /**
@@ -82,10 +82,10 @@ enum system_sleepmode {
  * adjusting the regulator output voltage to reduce power consumption.
  */
 enum system_performance_level {
-	/** Performance level 0 */
-	SYSTEM_PERFORMANCE_LEVEL_0  = PM_PLCFG_PLSEL_PL0,
-	/** Performance level 2 */
-	SYSTEM_PERFORMANCE_LEVEL_2  = PM_PLCFG_PLSEL_PL2,
+    /** Performance level 0 */
+    SYSTEM_PERFORMANCE_LEVEL_0  = PM_PLCFG_PLSEL_PL0,
+    /** Performance level 2 */
+    SYSTEM_PERFORMANCE_LEVEL_2  = PM_PLCFG_PLSEL_PL2,
 };
 
 /**
@@ -97,14 +97,14 @@ enum system_performance_level {
  * bit groups in STDBYCFG(STDBYCFG.BBIASxx).
  */
 enum system_ram_back_bias_mode {
-	/** Retention Back biasing mode */
-	SYSTEM_RAM_BACK_BIAS_RETENTION = 0,
-	/** Standby Back Biasing mode */
-	SYSTEM_RAM_BACK_BIAS_STANDBY,
-	/** Standby OFF mode */
-	SYSTEM_RAM_BACK_BIAS_STANDBY_OFF,
-	/** Always OFF mode */
-	SYSTEM_RAM_BACK_BIAS_OFF,
+    /** Retention Back biasing mode */
+    SYSTEM_RAM_BACK_BIAS_RETENTION = 0,
+    /** Standby Back Biasing mode */
+    SYSTEM_RAM_BACK_BIAS_STANDBY,
+    /** Standby OFF mode */
+    SYSTEM_RAM_BACK_BIAS_STANDBY_OFF,
+    /** Always OFF mode */
+    SYSTEM_RAM_BACK_BIAS_OFF,
 };
 
 #if SAML21 || SAMR30
@@ -116,14 +116,14 @@ enum system_ram_back_bias_mode {
  * power domain (PDn-1) is in active state too.
  */
 enum system_linked_power_domain {
-	/** Power domains PD0/PD1/PD2 are not linked */
-	SYSTEM_LINKED_POWER_DOMAIN_DEFAULT   = PM_STDBYCFG_LINKPD_DEFAULT_Val,
-	/** Power domains PD0 and PD1 are linked */
-	SYSTEM_LINKED_POWER_DOMAIN_PD01      = PM_STDBYCFG_LINKPD_PD01_Val,
-	/** Power domains PD1 and PD2 are linked */
-	SYSTEM_LINKED_POWER_DOMAIN_PD12      = PM_STDBYCFG_LINKPD_PD12_Val,
-	/** All Power domains are linked */
-	SYSTEM_LINKED_POWER_DOMAIN_PD012     = PM_STDBYCFG_LINKPD_PD012_Val,
+    /** Power domains PD0/PD1/PD2 are not linked */
+    SYSTEM_LINKED_POWER_DOMAIN_DEFAULT   = PM_STDBYCFG_LINKPD_DEFAULT_Val,
+    /** Power domains PD0 and PD1 are linked */
+    SYSTEM_LINKED_POWER_DOMAIN_PD01      = PM_STDBYCFG_LINKPD_PD01_Val,
+    /** Power domains PD1 and PD2 are linked */
+    SYSTEM_LINKED_POWER_DOMAIN_PD12      = PM_STDBYCFG_LINKPD_PD12_Val,
+    /** All Power domains are linked */
+    SYSTEM_LINKED_POWER_DOMAIN_PD012     = PM_STDBYCFG_LINKPD_PD012_Val,
 };
 
 #if (SAML21XXXB) || (SAMR30)
@@ -133,12 +133,12 @@ enum system_linked_power_domain {
  * List of VREG switching modes.
  */
 enum system_vreg_switch_mode {
-	/** Automatic mode. */
-	SYSTEM_SYSTEM_VREG_SWITCH_AUTO = 0,
-	/** Performance oriented. */
-	SYSTEM_SYSTEM_VREG_SWITCH_PERFORMANCE,
-	/** Low Power consumption oriented. */
-	SYSTEM_SYSTEM_VREG_SWITCH_LP,
+    /** Automatic mode. */
+    SYSTEM_SYSTEM_VREG_SWITCH_AUTO = 0,
+    /** Performance oriented. */
+    SYSTEM_SYSTEM_VREG_SWITCH_PERFORMANCE,
+    /** Low Power consumption oriented. */
+    SYSTEM_SYSTEM_VREG_SWITCH_LP,
 };
 #endif
 
@@ -150,14 +150,14 @@ enum system_vreg_switch_mode {
  * powered up.
  */
 enum system_power_domain {
-	/** All power domains switching are handled by hardware */
-	SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val,
-	/** Power domain 0 (PD0) is forced ACTIVE */
-	SYSTEM_POWER_DOMAIN_PD0     = PM_STDBYCFG_PDCFG_PD0_Val,
-	/** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */
-	SYSTEM_POWER_DOMAIN_PD01    = PM_STDBYCFG_PDCFG_PD01_Val,
-	/** All power domains are forced ACTIVE */
-	SYSTEM_POWER_DOMAIN_PD012   = PM_STDBYCFG_PDCFG_PD012_Val,
+    /** All power domains switching are handled by hardware */
+    SYSTEM_POWER_DOMAIN_DEFAULT = PM_STDBYCFG_PDCFG_DEFAULT_Val,
+    /** Power domain 0 (PD0) is forced ACTIVE */
+    SYSTEM_POWER_DOMAIN_PD0     = PM_STDBYCFG_PDCFG_PD0_Val,
+    /** Power domain 0 and 1 (PD0 and PD1) are forced ACTIVE */
+    SYSTEM_POWER_DOMAIN_PD01    = PM_STDBYCFG_PDCFG_PD01_Val,
+    /** All power domains are forced ACTIVE */
+    SYSTEM_POWER_DOMAIN_PD012   = PM_STDBYCFG_PDCFG_PD012_Val,
 };
 #endif
 
@@ -167,12 +167,12 @@ enum system_power_domain {
  *
  */
 enum system_vreg_switch_mode {
-	/** Automatic mode. */
-	SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
-	/** Performance oriented. */
-	SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
-	/** Low Power consumption oriented. */
-	SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
+    /** Automatic mode. */
+    SYSTEM_VREG_SWITCH_AUTO        = PM_STDBYCFG_VREGSMOD_AUTO_Val,
+    /** Performance oriented. */
+    SYSTEM_VREG_SWITCH_PERFORMANCE = PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val,
+    /** Low Power consumption oriented. */
+    SYSTEM_VREG_SWITCH_LP          = PM_STDBYCFG_VREGSMOD_LP_Val,
 };
 
 #endif
@@ -184,10 +184,10 @@ enum system_vreg_switch_mode {
  * can be chosen on the fly between a LDO or a Buck converter.
  */
 enum system_voltage_regulator_sel {
-	/** The voltage regulator in active mode is a LDO voltage regulator */
-	SYSTEM_VOLTAGE_REGULATOR_LDO    = SUPC_VREG_SEL_LDO_Val,
-	/** The voltage regulator in active mode is a buck converter */
-	SYSTEM_VOLTAGE_REGULATOR_BUCK   = SUPC_VREG_SEL_BUCK_Val,
+    /** The voltage regulator in active mode is a LDO voltage regulator */
+    SYSTEM_VOLTAGE_REGULATOR_LDO    = SUPC_VREG_SEL_LDO_Val,
+    /** The voltage regulator in active mode is a buck converter */
+    SYSTEM_VOLTAGE_REGULATOR_BUCK   = SUPC_VREG_SEL_BUCK_Val,
 };
 
 /**
@@ -196,12 +196,12 @@ enum system_voltage_regulator_sel {
  * Low power mode efficiency.
  */
 enum system_voltage_regulator_low_power_efficiency {
-	/** The voltage regulator in Low power mode has the default efficiency and
-		support the whole VDD range (1.62V to 3.6V) */
-	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT,
-	/** The voltage regulator in Low power mode has the highest efficiency and
-		support the limited VDD range (2.5V to 3.6V) */
-	SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST,
+    /** The voltage regulator in Low power mode has the default efficiency and
+        support the whole VDD range (1.62V to 3.6V) */
+    SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT,
+    /** The voltage regulator in Low power mode has the highest efficiency and
+        support the limited VDD range (2.5V to 3.6V) */
+    SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_HIGHTEST,
 };
 
 /**
@@ -210,22 +210,22 @@ enum system_voltage_regulator_low_power_efficiency {
  * Voltage references selection.
  */
 enum system_voltage_references_sel {
-	/** 1.0V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_1V0    = SUPC_VREF_SEL_1V0_Val,
-	/** 1.1V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_1V1    = SUPC_VREF_SEL_1V1_Val,
-	/** 1.2V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_1V2    = SUPC_VREF_SEL_1V2_Val,
-	/** 1.25V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_1V25   = SUPC_VREF_SEL_1V25_Val,
-	/** 2.0V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_2V0    = SUPC_VREF_SEL_2V0_Val,
-	/** 2.2V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_2V2    = SUPC_VREF_SEL_2V2_Val,
-	/** 2.4V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_2V4    = SUPC_VREF_SEL_2V4_Val,
-	/** 2.5V voltage reference typical value */
-	SYSTEM_VOLTAGE_REFERENCE_2V5    = SUPC_VREF_SEL_2V5_Val,
+    /** 1.0V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_1V0    = SUPC_VREF_SEL_1V0_Val,
+    /** 1.1V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_1V1    = SUPC_VREF_SEL_1V1_Val,
+    /** 1.2V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_1V2    = SUPC_VREF_SEL_1V2_Val,
+    /** 1.25V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_1V25   = SUPC_VREF_SEL_1V25_Val,
+    /** 2.0V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_2V0    = SUPC_VREF_SEL_2V0_Val,
+    /** 2.2V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_2V2    = SUPC_VREF_SEL_2V2_Val,
+    /** 2.4V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_2V4    = SUPC_VREF_SEL_2V4_Val,
+    /** 2.5V voltage reference typical value */
+    SYSTEM_VOLTAGE_REFERENCE_2V5    = SUPC_VREF_SEL_2V5_Val,
 };
 
 /**
@@ -234,14 +234,14 @@ enum system_voltage_references_sel {
  * Enum for Battery power switch modes.
  */
 enum system_battery_power_switch {
-	/** The backup domain is always supplied by main power */
-	SYSTEM_BATTERY_POWER_SWITCH_NONE      = SUPC_BBPS_CONF_NONE_Val,
-	/** The power switch is handled by the automatic power switch */
-	SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val,
-	/** The backup domain is always supplied by battery backup power */
-	SYSTEM_BATTERY_POWER_SWITCH_FORCED    = SUPC_BBPS_CONF_FORCED_Val,
-	/** The power switch is handled by the BOD33 */
-	SYSTEM_BATTERY_POWER_SWITCH_BOD33     = SUPC_BBPS_CONF_BOD33_Val,
+    /** The backup domain is always supplied by main power */
+    SYSTEM_BATTERY_POWER_SWITCH_NONE      = SUPC_BBPS_CONF_NONE_Val,
+    /** The power switch is handled by the automatic power switch */
+    SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC = SUPC_BBPS_CONF_APWS_Val,
+    /** The backup domain is always supplied by battery backup power */
+    SYSTEM_BATTERY_POWER_SWITCH_FORCED    = SUPC_BBPS_CONF_FORCED_Val,
+    /** The power switch is handled by the BOD33 */
+    SYSTEM_BATTERY_POWER_SWITCH_BOD33     = SUPC_BBPS_CONF_BOD33_Val,
 };
 
 /**
@@ -251,10 +251,10 @@ enum system_battery_power_switch {
  * device.
  */
 enum system_voltage_reference {
-	/** Temperature sensor voltage reference */
-	SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
-	/** Voltage reference output */
-	SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
+    /** Temperature sensor voltage reference */
+    SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
+    /** Voltage reference output */
+    SYSTEM_VOLTAGE_REFERENCE_OUTPUT,
 };
 
 /**
@@ -265,12 +265,12 @@ enum system_voltage_reference {
  * by the SUPC.
  */
 enum system_backup_pin {
-	/** Power Supply OK status pin */
-	SYSTEM_BACKUP_PIN_PSOK  = (0x1 << 0),
-	/** Backup output pin 0  */
-	SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1),
-	/** Backup output pin 1  */
-	SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2)
+    /** Power Supply OK status pin */
+    SYSTEM_BACKUP_PIN_PSOK  = (0x1 << 0),
+    /** Backup output pin 0  */
+    SYSTEM_BACKUP_PIN_OUT_0 = (0x1 << 1),
+    /** Backup output pin 1  */
+    SYSTEM_BACKUP_PIN_OUT_1 = (0x1 << 2)
 };
 
 /**
@@ -280,29 +280,29 @@ enum system_backup_pin {
  */
 struct system_standby_config {
 #if SAML21 || SAMR30
-	/** Power domain. */
-	enum system_power_domain  power_domain;
-	/** Enable dynamic power gating for power domain 0 */
-	bool enable_dpgpd0;
-	/** Enable dynamic power gating for power domain 1 */
-	bool enable_dpgpd1;
+    /** Power domain. */
+    enum system_power_domain  power_domain;
+    /** Enable dynamic power gating for power domain 0 */
+    bool enable_dpgpd0;
+    /** Enable dynamic power gating for power domain 1 */
+    bool enable_dpgpd1;
 #if (SAML21XXXA)
-	/** Automatic VREG switching disable. */
-	bool disable_avregsd;
+    /** Automatic VREG switching disable. */
+    bool disable_avregsd;
 #else
-	/** VREG switching mode */
-	enum system_vreg_switch_mode vregs_mode;
+    /** VREG switching mode */
+    enum system_vreg_switch_mode vregs_mode;
 #endif
-	/** Linked power domain */
-	enum system_linked_power_domain linked_power_domain;
+    /** Linked power domain */
+    enum system_linked_power_domain linked_power_domain;
 #elif SAML22
-	/** Regulator switch mode in standby. */
-	enum system_vreg_switch_mode vreg_switch_mode;
+    /** Regulator switch mode in standby. */
+    enum system_vreg_switch_mode vreg_switch_mode;
 #endif
-	/** Back bias for HMCRAMCHS. */
-	enum system_ram_back_bias_mode hmcramchs_back_bias;
-	/** Back bias for HMCRAMCLP */
-	enum system_ram_back_bias_mode hmcramclp_back_bias;
+    /** Back bias for HMCRAMCHS. */
+    enum system_ram_back_bias_mode hmcramchs_back_bias;
+    /** Back bias for HMCRAMCLP */
+    enum system_ram_back_bias_mode hmcramclp_back_bias;
 };
 
 /**
@@ -311,19 +311,19 @@ struct system_standby_config {
  * Configuration structure for VREG.
  */
 struct system_voltage_regulator_config {
-	/** Voltage scaling period */
-	uint8_t  voltage_scale_period;
-	/** Voltage scaling voltage step */
-	uint8_t voltage_scale_step;
-	/** Run in standby in standby sleep mode */
-	bool run_in_standby;
-	/** Voltage Regulator Selection */
-	enum system_voltage_regulator_sel  regulator_sel;
-	/** Low power efficiency */
-	enum system_voltage_regulator_low_power_efficiency low_power_efficiency;
+    /** Voltage scaling period */
+    uint8_t  voltage_scale_period;
+    /** Voltage scaling voltage step */
+    uint8_t voltage_scale_step;
+    /** Run in standby in standby sleep mode */
+    bool run_in_standby;
+    /** Voltage Regulator Selection */
+    enum system_voltage_regulator_sel  regulator_sel;
+    /** Low power efficiency */
+    enum system_voltage_regulator_low_power_efficiency low_power_efficiency;
 #if SAML22 || SAML21XXXB
-	/** Run in standby in performance level 0. */
-	bool run_in_standby_pl0;
+    /** Run in standby in performance level 0. */
+    bool run_in_standby_pl0;
 #endif
 };
 
@@ -333,15 +333,15 @@ struct system_voltage_regulator_config {
  * Configuration structure for VREF.
  */
 struct system_voltage_references_config {
-	/** Voltage References Selection */
-	enum system_voltage_references_sel  sel;
-	/** On Demand Control */
-	bool on_demand;
-	/** Run in standby */
-	bool run_in_standby;
+    /** Voltage References Selection */
+    enum system_voltage_references_sel  sel;
+    /** On Demand Control */
+    bool on_demand;
+    /** Run in standby */
+    bool run_in_standby;
 #if SAML22
-	/** Temperature Sensor Selection. */
-	bool temperature_sensor_sel;
+    /** Temperature Sensor Selection. */
+    bool temperature_sensor_sel;
 #endif
 };
 
@@ -351,11 +351,11 @@ struct system_voltage_references_config {
  * Configuration structure for Battery Backup Power Switch (BBPS).
  */
 struct system_battery_backup_power_switch_config {
-	/** Enable device wake up when BBPS switches from
-		battery backup power to main power */
-	bool wake_enabled;
-	/** Battery backup power switch configuration */
-	enum system_battery_power_switch battery_power_switch;
+    /** Enable device wake up when BBPS switches from
+        battery backup power to main power */
+    bool wake_enabled;
+    /** Battery backup power switch configuration */
+    enum system_battery_power_switch battery_power_switch;
 };
 
 /**
@@ -376,16 +376,16 @@ struct system_battery_backup_power_switch_config {
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_voltage_regulator_get_config_defaults(
-		struct system_voltage_regulator_config *const config)
+        struct system_voltage_regulator_config *const config)
 {
-	Assert(config);
-	config->voltage_scale_period = 0;
-	config->voltage_scale_step   = 0;
-	config->run_in_standby       = false;
-	config->regulator_sel        = SYSTEM_VOLTAGE_REGULATOR_LDO;
-	config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT;
+    Assert(config);
+    config->voltage_scale_period = 0;
+    config->voltage_scale_step   = 0;
+    config->run_in_standby       = false;
+    config->regulator_sel        = SYSTEM_VOLTAGE_REGULATOR_LDO;
+    config->low_power_efficiency = SYSTEM_VOLTAGE_REGULATOR_LOW_POWER_EFFICIENCY_DEFAULT;
 #if SAML22 || SAML21XXXB
-	config->run_in_standby_pl0   = false;
+    config->run_in_standby_pl0   = false;
 #endif
 }
 
@@ -398,22 +398,23 @@ static inline void system_voltage_regulator_get_config_defaults(
  *                    the new config
  */
 static inline void system_voltage_regulator_set_config(
-		struct system_voltage_regulator_config *const config)
+        struct system_voltage_regulator_config *const config)
 {
-	Assert(config);
-	SUPC->VREG.bit.VSPER    = config->voltage_scale_period;
-	SUPC->VREG.bit.VSVSTEP  = config->voltage_scale_step;
-	SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
-	SUPC->VREG.bit.SEL      = config->regulator_sel;
+    Assert(config);
+    SUPC->VREG.bit.VSPER    = config->voltage_scale_period;
+    SUPC->VREG.bit.VSVSTEP  = config->voltage_scale_step;
+    SUPC->VREG.bit.RUNSTDBY = config->run_in_standby;
+    SUPC->VREG.bit.SEL      = config->regulator_sel;
 #if (SAML21XXXB) || (SAMR30)
-	SUPC->VREG.bit.LPEFF    = config->low_power_efficiency;
+    SUPC->VREG.bit.LPEFF    = config->low_power_efficiency;
 #endif
 #if SAML22 || SAML21XXXB
-	SUPC->VREG.bit.STDBYPL0 = config->run_in_standby_pl0;
+    SUPC->VREG.bit.STDBYPL0 = config->run_in_standby_pl0;
 #endif
-	while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY)) {
-		;
-	}
+    while(!(SUPC->STATUS.reg & SUPC_STATUS_VREGRDY))
+    {
+        ;
+    }
 }
 
 /**
@@ -423,7 +424,7 @@ static inline void system_voltage_regulator_set_config(
  */
 static inline void system_voltage_regulator_enable(void)
 {
-	SUPC->VREG.reg |= SUPC_VREG_ENABLE;
+    SUPC->VREG.reg |= SUPC_VREG_ENABLE;
 }
 
 /**
@@ -433,7 +434,7 @@ static inline void system_voltage_regulator_enable(void)
  */
 static inline void system_voltage_regulator_disable(void)
 {
-	SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
+    SUPC->VREG.reg &= ~SUPC_VREG_ENABLE;
 }
 
 /**
@@ -456,14 +457,14 @@ static inline void system_voltage_regulator_disable(void)
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_voltage_reference_get_config_defaults(
-		struct system_voltage_references_config *const config)
+        struct system_voltage_references_config *const config)
 {
-	Assert(config);
-	config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V0;
-	config->on_demand      = false;
-	config->run_in_standby = false;
+    Assert(config);
+    config->sel            = SYSTEM_VOLTAGE_REFERENCE_1V0;
+    config->on_demand      = false;
+    config->run_in_standby = false;
 #if SAML22
-	config->temperature_sensor_sel = false;
+    config->temperature_sensor_sel = false;
 #endif
 }
 
@@ -476,14 +477,14 @@ static inline void system_voltage_reference_get_config_defaults(
  *                    the new config
  */
 static inline void system_voltage_reference_set_config(
-		struct system_voltage_references_config *const config)
+        struct system_voltage_references_config *const config)
 {
-	Assert(config);
-	SUPC->VREF.bit.SEL      = config->sel;
-	SUPC->VREF.bit.ONDEMAND = config->on_demand;
-	SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
+    Assert(config);
+    SUPC->VREF.bit.SEL      = config->sel;
+    SUPC->VREF.bit.ONDEMAND = config->on_demand;
+    SUPC->VREF.bit.RUNSTDBY = config->run_in_standby;
 #if SAML22
-	SUPC->VREF.bit.TSSEL    = config->temperature_sensor_sel;
+    SUPC->VREF.bit.TSSEL    = config->temperature_sensor_sel;
 #endif
 }
 
@@ -496,19 +497,20 @@ static inline void system_voltage_reference_set_config(
  * \param[in] vref  Voltage reference to enable
  */
 static inline void system_voltage_reference_enable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SUPC->VREF.reg |= SUPC_VREF_TSEN;
-			break;
-		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
-			SUPC->VREF.reg |= SUPC_VREF_VREFOE;
-			break;
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SUPC->VREF.reg |= SUPC_VREF_TSEN;
+            break;
+        case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+            SUPC->VREF.reg |= SUPC_VREF_VREFOE;
+            break;
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -519,19 +521,20 @@ static inline void system_voltage_reference_enable(
  * \param[in] vref  Voltage reference to disable
  */
 static inline void system_voltage_reference_disable(
-		const enum system_voltage_reference vref)
+        const enum system_voltage_reference vref)
 {
-	switch (vref) {
-		case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
-			SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
-			break;
-		case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
-			SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
-			break;
-		default:
-			Assert(false);
-			return;
-	}
+    switch (vref)
+    {
+        case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
+            SUPC->VREF.reg &= ~SUPC_VREF_TSEN;
+            break;
+        case SYSTEM_VOLTAGE_REFERENCE_OUTPUT:
+            SUPC->VREF.reg &= ~SUPC_VREF_VREFOE;
+            break;
+        default:
+            Assert(false);
+            return;
+    }
 }
 
 /**
@@ -554,11 +557,11 @@ static inline void system_voltage_reference_disable(
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_battery_backup_power_switch_get_config_defaults(
-		struct system_battery_backup_power_switch_config *const config)
+        struct system_battery_backup_power_switch_config *const config)
 {
-	Assert(config);
-	config->wake_enabled         = false;
-	config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE;
+    Assert(config);
+    config->wake_enabled         = false;
+    config->battery_power_switch = SYSTEM_BATTERY_POWER_SWITCH_NONE;
 }
 
 /**
@@ -570,24 +573,27 @@ static inline void system_battery_backup_power_switch_get_config_defaults(
  *                    the new config
  */
 static inline void system_battery_backup_power_switch_set_config(
-		struct system_battery_backup_power_switch_config *const config)
+        struct system_battery_backup_power_switch_config *const config)
 {
-	Assert(config);
-	uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN;
+    Assert(config);
+    uint32_t new_config = SUPC->BBPS.reg & SUPC_BBPS_PSOKEN;
 
-	if(config->wake_enabled) {
-		new_config |= SUPC_BBPS_WAKEEN;
-	}
+    if(config->wake_enabled)
+    {
+        new_config |= SUPC_BBPS_WAKEEN;
+    }
 
-	new_config |= SUPC_BBPS_CONF(config->battery_power_switch);
+    new_config |= SUPC_BBPS_CONF(config->battery_power_switch);
 
-	SUPC->BBPS.reg = new_config;
+    SUPC->BBPS.reg = new_config;
 
-	if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC) {
-		while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY)) {
-			;
-		}
-	}
+    if (config->battery_power_switch == SYSTEM_BATTERY_POWER_SWITCH_AUTOMATIC)
+    {
+        while (!(SUPC->STATUS.reg & SUPC_STATUS_APWSRDY))
+        {
+            ;
+        }
+    }
 }
 
 /**
@@ -607,13 +613,14 @@ static inline void system_battery_backup_power_switch_set_config(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_enable(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
-		SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN;
-	} else {
-		SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1);
-	}
+    if (pin == SYSTEM_BACKUP_PIN_PSOK)
+    {
+        SUPC->BBPS.reg |= SUPC_BBPS_PSOKEN;
+    } else {
+        SUPC->BKOUT.reg |= SUPC_BKOUT_EN(pin >> 1);
+    }
 }
 
 /**
@@ -624,13 +631,14 @@ static inline void system_backup_pin_output_enable(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_disable(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
-		SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
-	} else {
-		SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1);
-	}
+    if (pin == SYSTEM_BACKUP_PIN_PSOK)
+    {
+        SUPC->BBPS.reg &= ~SUPC_BBPS_PSOKEN;
+    } else {
+        SUPC->BKOUT.reg &= ~SUPC_BKOUT_EN(pin >> 1);
+    }
 }
 
 /**
@@ -643,20 +651,23 @@ static inline void system_backup_pin_output_disable(
  * \retval false The output is not enabled
  */
 static inline bool system_backup_pin_output_is_enabled(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	bool enabled = false;
-
-	if (pin == SYSTEM_BACKUP_PIN_PSOK) {
-		if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN) {
-			enabled = true;
-		}
-	} else {
-		if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1)) {
-			enabled = true;
-		}
-	}
-	return enabled;
+    bool enabled = false;
+
+    if (pin == SYSTEM_BACKUP_PIN_PSOK)
+    {
+        if (SUPC->BBPS.reg & SUPC_BBPS_PSOKEN)
+        {
+            enabled = true;
+        }
+    } else {
+        if (SUPC->BKOUT.reg & SUPC_BKOUT_EN(pin >> 1))
+        {
+            enabled = true;
+        }
+    }
+    return enabled;
 }
 
 /**
@@ -667,11 +678,11 @@ static inline bool system_backup_pin_output_is_enabled(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_enable_rtc_toggle(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+    Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
 
-	SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1);
+    SUPC->BKOUT.reg |= SUPC_BKOUT_RTCTGL(pin >> 1);
 }
 
 /**
@@ -682,11 +693,11 @@ static inline void system_backup_pin_output_enable_rtc_toggle(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_disable_rtc_toggle(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+    Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
 
-	SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1);
+    SUPC->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(pin >> 1);
 }
 
 /**
@@ -697,11 +708,11 @@ static inline void system_backup_pin_output_disable_rtc_toggle(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_set(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+    Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
 
-	SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1);
+    SUPC->BKOUT.reg |= SUPC_BKOUT_SET(pin >> 1);
 }
 
 /**
@@ -712,11 +723,11 @@ static inline void system_backup_pin_output_set(
  *  \param[in] pin Backup pin index
  */
 static inline void system_backup_pin_output_clear(
-		enum system_backup_pin pin)
+        enum system_backup_pin pin)
 {
-	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+    Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
 
-	SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1);
+    SUPC->BKOUT.reg |= SUPC_BKOUT_CLR(pin >> 1);
 }
 
 /**
@@ -731,9 +742,9 @@ static inline void system_backup_pin_output_clear(
  */
 static inline bool system_backup_pin_output_get(enum system_backup_pin pin)
 {
-	Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
+    Assert(pin != SYSTEM_BACKUP_PIN_PSOK);
 
-	return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1));
+    return (SUPC->BKIN.reg & SUPC_BKIN_BKIN(pin >> 1));
 }
 
 /**
@@ -757,10 +768,10 @@ static inline bool system_backup_pin_output_get(enum system_backup_pin pin)
  * \param[in] sleep_mode  Sleep mode to configure for the next sleep operation
  */
 static inline void system_set_sleepmode(
-	const enum system_sleepmode sleep_mode)
+    const enum system_sleepmode sleep_mode)
 {
-	PM->SLEEPCFG.reg = sleep_mode;
-	while(PM->SLEEPCFG.reg != sleep_mode) ;
+    PM->SLEEPCFG.reg = sleep_mode;
+    while(PM->SLEEPCFG.reg != sleep_mode) ;
 }
 
 /**
@@ -773,8 +784,8 @@ static inline void system_set_sleepmode(
  */
 static inline void system_sleep(void)
 {
-	__DSB();
-	__WFI();
+    __DSB();
+    __WFI();
 }
 
 /**
@@ -802,30 +813,33 @@ static inline void system_sleep(void)
  * \retval STATUS_OK               Successfully
  */
 static inline enum status_code system_switch_performance_level(
-					const enum system_performance_level performance_level)
+                    const enum system_performance_level performance_level)
 {
 
-	if (performance_level == (enum system_performance_level)PM->PLCFG.reg) {
-		return STATUS_OK;
-	}
+    if (performance_level == (enum system_performance_level)PM->PLCFG.reg)
+    {
+        return STATUS_OK;
+    }
 
 #if SAML22 || SAML21XXXB
-	if (PM->PLCFG.reg & PM_PLCFG_PLDIS) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (PM->PLCFG.reg & PM_PLCFG_PLDIS)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 #endif
 
-	/* Clear performance level status */
-	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+    /* Clear performance level status */
+    PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
 
-	/* Switch performance level */
-	PM->PLCFG.reg = performance_level;
+    /* Switch performance level */
+    PM->PLCFG.reg = performance_level;
 
-	/* Waiting performance level ready */
-	while (!PM->INTFLAG.reg) {
-		;
-	}
-	return STATUS_OK;
+    /* Waiting performance level ready */
+    while (!PM->INTFLAG.reg)
+    {
+        ;
+    }
+    return STATUS_OK;
 }
 
 #if SAML22 || SAML21XXXB
@@ -836,7 +850,7 @@ static inline enum status_code system_switch_performance_level(
  */
 static inline void system_performance_level_enable(void)
 {
-	PM->PLCFG.reg &= ~PM_PLCFG_PLDIS;
+    PM->PLCFG.reg &= ~PM_PLCFG_PLDIS;
 }
 
 /**
@@ -846,7 +860,7 @@ static inline void system_performance_level_enable(void)
  */
 static inline void system_performance_level_disable(void)
 {
-	PM->PLCFG.reg |= PM_PLCFG_PLDIS;
+    PM->PLCFG.reg |= PM_PLCFG_PLDIS;
 }
 #endif
 
@@ -859,7 +873,7 @@ static inline void system_performance_level_disable(void)
  */
 static inline enum system_performance_level system_get_performance_level(void)
 {
-	return (enum system_performance_level)PM->PLCFG.reg;
+    return (enum system_performance_level)PM->PLCFG.reg;
 }
 
 /**
@@ -870,7 +884,7 @@ static inline enum system_performance_level system_get_performance_level(void)
  */
 static inline uint8_t system_get_performance_level_status(void)
 {
-	return PM->INTFLAG.reg;
+    return PM->INTFLAG.reg;
 }
 
 /**
@@ -880,7 +894,7 @@ static inline uint8_t system_get_performance_level_status(void)
  */
 static inline void system_clear_performance_level_status(void)
 {
-	PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
+    PM->INTFLAG.reg = PM_INTFLAG_PLRDY;
 }
 
 /**
@@ -907,24 +921,24 @@ static inline void system_clear_performance_level_status(void)
  * \param[out] config  Configuration structure to fill with default values
  */
 static inline void system_standby_get_config_defaults(
-		struct system_standby_config *const config)
+        struct system_standby_config *const config)
 {
-	Assert(config);
+    Assert(config);
 #if SAML21 || SAMR30
-	config->power_domain        = SYSTEM_POWER_DOMAIN_DEFAULT;
-	config->enable_dpgpd0       = false;
-	config->enable_dpgpd1       = false;
+    config->power_domain        = SYSTEM_POWER_DOMAIN_DEFAULT;
+    config->enable_dpgpd0       = false;
+    config->enable_dpgpd1       = false;
 #if (SAML21XXXB) || (SAMR30)
-	config->vregs_mode          = SYSTEM_SYSTEM_VREG_SWITCH_AUTO;
+    config->vregs_mode          = SYSTEM_SYSTEM_VREG_SWITCH_AUTO;
 #else
-	config->disable_avregsd     = false;
+    config->disable_avregsd     = false;
 #endif
-	config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT;
+    config->linked_power_domain = SYSTEM_LINKED_POWER_DOMAIN_DEFAULT;
 #elif SAML22
-	config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
+    config->vreg_switch_mode    = SYSTEM_VREG_SWITCH_AUTO;
 #endif
-	config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
-	config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+    config->hmcramchs_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
+    config->hmcramclp_back_bias = SYSTEM_RAM_BACK_BIAS_RETENTION;
 }
 
 /**
@@ -936,24 +950,24 @@ static inline void system_standby_get_config_defaults(
  *                    the new config
  */
 static inline void system_standby_set_config(
-		struct system_standby_config *const config)
+        struct system_standby_config *const config)
 {
-	Assert(config);
+    Assert(config);
 #if SAML21 || SAMR30
-	PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain)
-					 | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos)
-					 | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos)
+    PM->STDBYCFG.reg = PM_STDBYCFG_PDCFG(config->power_domain)
+                     | (config->enable_dpgpd0 << PM_STDBYCFG_DPGPD0_Pos)
+                     | (config->enable_dpgpd1 << PM_STDBYCFG_DPGPD1_Pos)
 #if (SAML21XXXB) || (SAMR30)
-					 | PM_STDBYCFG_VREGSMOD(config->vregs_mode)
+                     | PM_STDBYCFG_VREGSMOD(config->vregs_mode)
 #else
-					 | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos)
+                     | (config->disable_avregsd << PM_STDBYCFG_AVREGSD_Pos)
 #endif
-					 | PM_STDBYCFG_LINKPD(config->linked_power_domain)
-					 | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias)
-					 | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias);
+                     | PM_STDBYCFG_LINKPD(config->linked_power_domain)
+                     | PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias)
+                     | PM_STDBYCFG_BBIASLP(config->hmcramclp_back_bias);
 #elif SAML22
-	PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
-					 PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
+    PM->STDBYCFG.reg = PM_STDBYCFG_VREGSMOD(config->vreg_switch_mode) |
+                     PM_STDBYCFG_BBIASHS(config->hmcramchs_back_bias);
 #endif
 }
 
@@ -974,7 +988,7 @@ static inline void system_standby_set_config(
  */
 static inline void system_io_retension_enable(void)
 {
-	PM->CTRLA.reg = PM_CTRLA_IORET;
+    PM->CTRLA.reg = PM_CTRLA_IORET;
 }
 
 /**
@@ -984,7 +998,7 @@ static inline void system_io_retension_enable(void)
  */
 static inline void system_io_retension_disable(void)
 {
-	PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
+    PM->CTRLA.reg = PM_CTRLA_MASK & (~PM_CTRLA_IORET);
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h
index 647296be247f..088ad9cc3d27 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_c/reset.h
@@ -60,19 +60,19 @@ extern "C" {
  * List of possible reset causes of the system.
  */
 enum system_reset_cause {
-	/** The system was last reset by a software reset */
-	SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
-	/** The system was last reset by the watchdog timer */
-	SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
-	/** The system was last reset because the external reset 
-		line was pulled low */
-	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
-	/** The system was last reset by VDD brown out detector */
-	SYSTEM_RESET_CAUSE_BODVDD         = RSTC_RCAUSE_BODVDD,
-	/** The system was last reset by VDDCORE brown out detector */
-	SYSTEM_RESET_CAUSE_BODCORE        = RSTC_RCAUSE_BODCORE,
-	/** The system was last reset by the POR (Power on reset) */
-	SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
+    /** The system was last reset by a software reset */
+    SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
+    /** The system was last reset by the watchdog timer */
+    SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
+    /** The system was last reset because the external reset
+        line was pulled low */
+    SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
+    /** The system was last reset by VDD brown out detector */
+    SYSTEM_RESET_CAUSE_BODVDD         = RSTC_RCAUSE_BODVDD,
+    /** The system was last reset by VDDCORE brown out detector */
+    SYSTEM_RESET_CAUSE_BODCORE        = RSTC_RCAUSE_BODCORE,
+    /** The system was last reset by the POR (Power on reset) */
+    SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
 };
 
 /**
@@ -89,7 +89,7 @@ enum system_reset_cause {
  */
 static inline void system_reset(void)
 {
-	NVIC_SystemReset();
+    NVIC_SystemReset();
 }
 
 /**
@@ -101,7 +101,7 @@ static inline void system_reset(void)
  */
 static inline enum system_reset_cause system_get_reset_cause(void)
 {
-	return (enum system_reset_cause)RSTC->RCAUSE.reg;
+    return (enum system_reset_cause)RSTC->RCAUSE.reg;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
index 33ccd5030ef8..f9ce4e32ac48 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_d_r_h/reset.h
@@ -63,18 +63,18 @@ extern "C" {
  * List of possible reset causes of the system.
  */
 enum system_reset_cause {
-	/** The system was last reset by a software reset */
-	SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
-	/** The system was last reset by the watchdog timer */
-	SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
-	/** The system was last reset because the external reset line was pulled low */
-	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
-	/** The system was last reset by the BOD33 */
-	SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
-	/** The system was last reset by the BOD12 */
-	SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
-	/** The system was last reset by the POR (Power on reset) */
-	SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
+    /** The system was last reset by a software reset */
+    SYSTEM_RESET_CAUSE_SOFTWARE       = PM_RCAUSE_SYST,
+    /** The system was last reset by the watchdog timer */
+    SYSTEM_RESET_CAUSE_WDT            = PM_RCAUSE_WDT,
+    /** The system was last reset because the external reset line was pulled low */
+    SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
+    /** The system was last reset by the BOD33 */
+    SYSTEM_RESET_CAUSE_BOD33          = PM_RCAUSE_BOD33,
+    /** The system was last reset by the BOD12 */
+    SYSTEM_RESET_CAUSE_BOD12          = PM_RCAUSE_BOD12,
+    /** The system was last reset by the POR (Power on reset) */
+    SYSTEM_RESET_CAUSE_POR            = PM_RCAUSE_POR,
 };
 
 
@@ -92,7 +92,7 @@ enum system_reset_cause {
  */
 static inline void system_reset(void)
 {
-	NVIC_SystemReset();
+    NVIC_SystemReset();
 }
 
 /**
@@ -104,7 +104,7 @@ static inline void system_reset(void)
  */
 static inline enum system_reset_cause system_get_reset_cause(void)
 {
-	return (enum system_reset_cause)PM->RCAUSE.reg;
+    return (enum system_reset_cause)PM->RCAUSE.reg;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h
index 7b5cd29611d1..8396387fe8b5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/reset/reset_sam_l/reset.h
@@ -64,27 +64,27 @@ extern "C" {
  * List of possible reset causes of the system.
  */
 enum system_reset_cause {
-	/** The system was last reset by a backup reset */
-	SYSTEM_RESET_CAUSE_BACKUP         = RSTC_RCAUSE_BACKUP,
-	/** The system was last reset by a software reset */
-	SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
-	/** The system was last reset by the watchdog timer */
-	SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
-	/** The system was last reset because the external reset line was pulled low */
-	SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
+    /** The system was last reset by a backup reset */
+    SYSTEM_RESET_CAUSE_BACKUP         = RSTC_RCAUSE_BACKUP,
+    /** The system was last reset by a software reset */
+    SYSTEM_RESET_CAUSE_SOFTWARE       = RSTC_RCAUSE_SYST,
+    /** The system was last reset by the watchdog timer */
+    SYSTEM_RESET_CAUSE_WDT            = RSTC_RCAUSE_WDT,
+    /** The system was last reset because the external reset line was pulled low */
+    SYSTEM_RESET_CAUSE_EXTERNAL_RESET = RSTC_RCAUSE_EXT,
 #if SAML21 || SAMR30
-	/** The system was last reset by the BOD33. */
-	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BOD33,
-	/** The system was last reset by the BOD12 */
-	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BOD12,
+    /** The system was last reset by the BOD33. */
+    SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BOD33,
+    /** The system was last reset by the BOD12 */
+    SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BOD12,
 #else
-	/** The system was last reset by the BOD VDD. */
-	SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BODVDD,
-	/** The system was last reset by the BOD CORE. */
-	SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BODCORE,
+    /** The system was last reset by the BOD VDD. */
+    SYSTEM_RESET_CAUSE_BOD33          = RSTC_RCAUSE_BODVDD,
+    /** The system was last reset by the BOD CORE. */
+    SYSTEM_RESET_CAUSE_BOD12          = RSTC_RCAUSE_BODCORE,
 #endif
-	/** The system was last reset by the POR (Power on reset). */
-	SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
+    /** The system was last reset by the POR (Power on reset). */
+    SYSTEM_RESET_CAUSE_POR            = RSTC_RCAUSE_POR,
 };
 
 /**
@@ -94,13 +94,13 @@ enum system_reset_cause {
  */
 enum system_reset_backup_exit_source {
 #if SAML21 || SAMR30
-	/** The backup exit source was external wakeup. */
-	SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE    = RSTC_BKUPEXIT_EXTWAKE,
+    /** The backup exit source was external wakeup. */
+    SYSTEM_RESET_BACKKUP_EXIT_EXTWAKE    = RSTC_BKUPEXIT_EXTWAKE,
 #endif
-	/** The backup exit source was RTC interrupt. */
-	SYSTEM_RESET_BACKKUP_EXIT_RTC        = RSTC_BKUPEXIT_RTC,
-	/** The backup exit source was battery backup power switch */
-	SYSTEM_RESET_BACKKUP_EXIT_BBPS       = RSTC_BKUPEXIT_BBPS,
+    /** The backup exit source was RTC interrupt. */
+    SYSTEM_RESET_BACKKUP_EXIT_RTC        = RSTC_BKUPEXIT_RTC,
+    /** The backup exit source was battery backup power switch */
+    SYSTEM_RESET_BACKKUP_EXIT_BBPS       = RSTC_BKUPEXIT_BBPS,
 };
 
 #if SAML21 || SAMR30
@@ -110,20 +110,20 @@ enum system_reset_backup_exit_source {
  * Wakeup debounce counter value when waking up by external wakeup pin from backup mode.
  */
 enum system_wakeup_debounce_count {
-	/** No debouncing */
-	SYSTEM_WAKEUP_DEBOUNCE_OFF         = RSTC_WKDBCONF_WKDBCNT_OFF,
-	/** Input pin shall be active for at least two 32KHz clock period. */
-	SYSTEM_WAKEUP_DEBOUNCE_2CK32       = RSTC_WKDBCONF_WKDBCNT_2CK32,
-	/** Input pin shall be active for at least three 32KHz clock period. */
-	SYSTEM_WAKEUP_DEBOUNCE_3CK32       = RSTC_WKDBCONF_WKDBCNT_3CK32,
-	/** Input pin shall be active for at least 32 32KHz clock periods */
-	SYSTEM_WAKEUP_DEBOUNCE_32CK32      = RSTC_WKDBCONF_WKDBCNT_32CK32,
-	/** Input pin shall be active for at least 512 32KHz clock periods */
-	SYSTEM_WAKEUP_DEBOUNCE_512CK32     = RSTC_WKDBCONF_WKDBCNT_512CK32,
-	/** Input pin shall be active for at least 4096 32KHz clock periods */
-	SYSTEM_WAKEUP_DEBOUNCE_4096CK32    = RSTC_WKDBCONF_WKDBCNT_4096CK32,
-	/** Input pin shall be active for at least 32768 32KHz clock periods */
-	SYSTEM_WAKEUP_DEBOUNCE_32768CK32   = RSTC_WKDBCONF_WKDBCNT_32768CK32,
+    /** No debouncing */
+    SYSTEM_WAKEUP_DEBOUNCE_OFF         = RSTC_WKDBCONF_WKDBCNT_OFF,
+    /** Input pin shall be active for at least two 32KHz clock period. */
+    SYSTEM_WAKEUP_DEBOUNCE_2CK32       = RSTC_WKDBCONF_WKDBCNT_2CK32,
+    /** Input pin shall be active for at least three 32KHz clock period. */
+    SYSTEM_WAKEUP_DEBOUNCE_3CK32       = RSTC_WKDBCONF_WKDBCNT_3CK32,
+    /** Input pin shall be active for at least 32 32KHz clock periods */
+    SYSTEM_WAKEUP_DEBOUNCE_32CK32      = RSTC_WKDBCONF_WKDBCNT_32CK32,
+    /** Input pin shall be active for at least 512 32KHz clock periods */
+    SYSTEM_WAKEUP_DEBOUNCE_512CK32     = RSTC_WKDBCONF_WKDBCNT_512CK32,
+    /** Input pin shall be active for at least 4096 32KHz clock periods */
+    SYSTEM_WAKEUP_DEBOUNCE_4096CK32    = RSTC_WKDBCONF_WKDBCNT_4096CK32,
+    /** Input pin shall be active for at least 32768 32KHz clock periods */
+    SYSTEM_WAKEUP_DEBOUNCE_32768CK32   = RSTC_WKDBCONF_WKDBCNT_32768CK32,
 };
 #endif
 
@@ -141,7 +141,7 @@ enum system_wakeup_debounce_count {
  */
 static inline void system_reset(void)
 {
-	NVIC_SystemReset();
+    NVIC_SystemReset();
 }
 
 /**
@@ -153,7 +153,7 @@ static inline void system_reset(void)
  */
 static inline enum system_reset_cause system_get_reset_cause(void)
 {
-	return (enum system_reset_cause)RSTC->RCAUSE.reg;
+    return (enum system_reset_cause)RSTC->RCAUSE.reg;
 }
 
 /**
@@ -174,7 +174,7 @@ static inline enum system_reset_cause system_get_reset_cause(void)
  */
 static inline enum system_reset_backup_exit_source system_get_backup_exit_source(void)
 {
-	return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg;
+    return (enum system_reset_backup_exit_source)RSTC->BKUPEXIT.reg;
 }
 
 #if SAML21 || SAMR30
@@ -186,9 +186,9 @@ static inline enum system_reset_backup_exit_source system_get_backup_exit_source
  * \param[in] wakeup_debounce_count Wakeup debounce counter value
  */
 static inline void system_set_pin_wakeup_debounce_counter(
-					const enum system_wakeup_debounce_count wakeup_debounce_count)
+                    const enum system_wakeup_debounce_count wakeup_debounce_count)
 {
-	RSTC->WKDBCONF.reg = wakeup_debounce_count;
+    RSTC->WKDBCONF.reg = wakeup_debounce_count;
 }
 
 /**
@@ -200,7 +200,7 @@ static inline void system_set_pin_wakeup_debounce_counter(
  */
 static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask)
 {
-	RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask));
+    RSTC->WKPOL.reg &= ~(RSTC_WKPOL_WKPOL(pin_mask));
 }
 
 /**
@@ -212,7 +212,7 @@ static inline void system_set_pin_wakeup_polarity_low(const uint16_t pin_mask)
  */
 static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask)
 {
-	RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask);
+    RSTC->WKPOL.reg |= RSTC_WKPOL_WKPOL(pin_mask);
 }
 
 /**
@@ -224,7 +224,7 @@ static inline void system_set_pin_wakeup_polarity_high(const uint16_t pin_mask)
  */
 static inline void system_enable_pin_wakeup(const uint16_t pin_mask)
 {
-	RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask);
+    RSTC->WKEN.reg |= RSTC_WKEN_WKEN(pin_mask);
 }
 
 /**
@@ -236,7 +236,7 @@ static inline void system_enable_pin_wakeup(const uint16_t pin_mask)
  */
 static inline void system_disable_pin_wakeup(const uint16_t pin_mask)
 {
-	RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask));
+    RSTC->WKEN.reg &= ~(RSTC_WKEN_WKEN(pin_mask));
 }
 
 /**
@@ -249,7 +249,7 @@ static inline void system_disable_pin_wakeup(const uint16_t pin_mask)
  */
 static inline uint16_t system_get_pin_wakeup_cause(void)
 {
-	return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos));
+    return (RSTC_WKCAUSE_MASK & (RSTC->WKCAUSE.reg >> RSTC_WKCAUSE_WKCAUSE_Pos));
 }
 #endif
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c
index feab5f340282..462821418131 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.c
@@ -54,7 +54,7 @@
 void _system_dummy_init(void);
 void _system_dummy_init(void)
 {
-	return;
+    return;
 }
 
 #if !defined(__DOXYGEN__)
@@ -93,19 +93,19 @@ void _system_divas_init(void);
  */
 void system_init(void)
 {
-	/* Configure GCLK and clock sources according to conf_clocks.h */
-	system_clock_init();
+    /* Configure GCLK and clock sources according to conf_clocks.h */
+    system_clock_init();
 
-	/* Initialize board hardware */
-	system_board_init();
+    /* Initialize board hardware */
+    system_board_init();
 
-	/* Initialize EVSYS hardware */
-	_system_events_init();
+    /* Initialize EVSYS hardware */
+    _system_events_init();
 
-	/* Initialize External hardware */
-	_system_extint_init();
+    /* Initialize External hardware */
+    _system_extint_init();
 
-	/* Initialize DIVAS hardware */
-	_system_divas_init();
+    /* Initialize DIVAS hardware */
+    _system_divas_init();
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h
index c6dd6e856218..96ee50af77e4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system.h
@@ -522,7 +522,7 @@ extern "C" {
  */
 static inline bool system_is_debugger_present(void)
 {
-	return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
+    return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
 }
 
 /**
@@ -543,7 +543,7 @@ static inline bool system_is_debugger_present(void)
  */
 static inline uint32_t system_get_device_id(void)
 {
-	return DSU->DID.reg;
+    return DSU->DID.reg;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c
index ea609da2c06a..caf9b13b9054 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.c
@@ -61,43 +61,44 @@ uint32_t system_clock_value;
  * \retval STATUS_ERR_INVALID_ARG  If data is invalid
  */
 enum status_code system_clock_config(enum system_clock_resource resoure, \
-				enum system_clock_freq freq)
+                enum system_clock_freq freq)
 {
-	switch (resoure) {
-		case CLOCK_RESOURCE_XO_26_MHZ:
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-					LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
-					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
-			system_clock_value = 26000000;
-			break;
-
-		case CLOCK_RESOURCE_LP_2_MHZ:
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
-					~LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK;
-			AON_GP_REGS0->AON_PMU_CTRL.reg |= \
-					AON_GP_REGS_AON_PMU_CTRL_PMU_2MHZ_CLK_EN;
-			system_clock_value = 2000000;
-			break;
-
-		case CLOCK_RESOURCE_RC_26_MHZ:
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
-					~(LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
-					LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK);
-			system_clock_value = 26000000;
-			break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
-		~LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL_Msk;
-	LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-		LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL(freq);
-
-	return STATUS_OK;
+    switch (resoure)
+    {
+        case CLOCK_RESOURCE_XO_26_MHZ:
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                    LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
+                    LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
+            system_clock_value = 26000000;
+            break;
+
+        case CLOCK_RESOURCE_LP_2_MHZ:
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                    LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK;
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+                    ~LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK;
+            AON_GP_REGS0->AON_PMU_CTRL.reg |= \
+                    AON_GP_REGS_AON_PMU_CTRL_PMU_2MHZ_CLK_EN;
+            system_clock_value = 2000000;
+            break;
+
+        case CLOCK_RESOURCE_RC_26_MHZ:
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+                    ~(LPMCU_MISC_REGS_LPMCU_CTRL_USE_BT26M_CLK | \
+                    LPMCU_MISC_REGS_LPMCU_CTRL_USE_ARM_LP_CLK);
+            system_clock_value = 26000000;
+            break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+        ~LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL_Msk;
+    LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+        LPMCU_MISC_REGS_LPMCU_CTRL_LPMCU_CLK_SEL(freq);
+
+    return STATUS_OK;
 }
 
 /**
@@ -109,7 +110,7 @@ enum status_code system_clock_config(enum system_clock_resource resoure, \
  */
 uint32_t system_clock_get_value(void)
 {
-	return system_clock_value;
+    return system_clock_value;
 }
 
 /**
@@ -125,282 +126,283 @@ uint32_t system_clock_get_value(void)
  */
 enum status_code system_clock_peripheral_enable(enum system_peripheral peripheral)
 {
-	switch (peripheral) {
-		case PERIPHERAL_SPI_FLASH:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_I2C0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_DUALT_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
-		break;
-
-		case PERIPHERAL_GPIO_CLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
-		break;
-
-		case PERIPHERAL_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
-		break;
-
-		case PERIPHERAL_WDT0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
-		break;
-
-		case PERIPHERAL_WDT1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART0_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART1_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_NVIC:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_ROM:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_AON_WRAPPER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
-		break;
-
-		case PERIPHERAL_ARM_PCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
-		break;
-
-		case PERIPHERAL_ARM_GATED_PCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
-		break;
-
-		case PERIPHERAL_ARM_BLE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
-		break;
-
-		case PERIPHERAL_I2C1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE3:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE4:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE5:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE6:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM3:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
-		break;
-
-		case PERIPHERAL_ADC:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI0_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI1_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
-		break;
-
-		case PERIPHERAL_GPIO_GCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
-		break;
-
-		case PERIPHERAL_TIMER0_GATE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
-		break;
-
-		case PERIPHERAL_SHA_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_SHA_AHB:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_AES_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_AES_AHB:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2_0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2_1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_RXTX:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
-				LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_AHB:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
-				LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_PERIPH_REGS:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
-				LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
-		break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (peripheral)
+    {
+        case PERIPHERAL_SPI_FLASH:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_I2C0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_DUALT_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+        break;
+
+        case PERIPHERAL_GPIO_CLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
+        break;
+
+        case PERIPHERAL_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
+        break;
+
+        case PERIPHERAL_WDT0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
+        break;
+
+        case PERIPHERAL_WDT1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART0_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART1_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_NVIC:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_ROM:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_AON_WRAPPER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
+        break;
+
+        case PERIPHERAL_ARM_PCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
+        break;
+
+        case PERIPHERAL_ARM_GATED_PCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
+        break;
+
+        case PERIPHERAL_ARM_BLE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+        break;
+
+        case PERIPHERAL_I2C1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE3:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE4:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE5:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE6:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM3:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
+        break;
+
+        case PERIPHERAL_ADC:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI0_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI1_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
+        break;
+
+        case PERIPHERAL_GPIO_GCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
+        break;
+
+        case PERIPHERAL_TIMER0_GATE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
+        break;
+
+        case PERIPHERAL_SHA_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_SHA_AHB:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_AES_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_AES_AHB:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2_0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2_1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_RXTX:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+                LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_AHB:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+                LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_PERIPH_REGS:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg |= \
+                LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
+        break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -416,282 +418,283 @@ enum status_code system_clock_peripheral_enable(enum system_peripheral periphera
  */
 enum status_code system_clock_peripheral_disable(enum system_peripheral peripheral)
 {
-	switch (peripheral) {
-		case PERIPHERAL_SPI_FLASH:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_I2C0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_DUALT_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
-		break;
-
-		case PERIPHERAL_GPIO_CLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
-		break;
-
-		case PERIPHERAL_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
-		break;
-
-		case PERIPHERAL_WDT0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
-		break;
-
-		case PERIPHERAL_WDT1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART0_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_UART1_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_NVIC:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_ROM:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_IF:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
-		break;
-
-		case PERIPHERAL_AON_WRAPPER:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
-		break;
-
-		case PERIPHERAL_ARM_PCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
-		break;
-
-		case PERIPHERAL_ARM_GATED_PCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
-		break;
-
-		case PERIPHERAL_ARM_BLE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
-		break;
-
-		case PERIPHERAL_QDEC2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
-		break;
-
-		case PERIPHERAL_I2C1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE3:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE4:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE5:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
-		break;
-
-		case PERIPHERAL_EFUSE6:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
-		break;
-
-		case PERIPHERAL_PWM3:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
-		break;
-
-		case PERIPHERAL_ADC:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI0_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
-		break;
-
-		case PERIPHERAL_SPI1_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
-		break;
-
-		case PERIPHERAL_GPIO_GCLK:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
-		break;
-
-		case PERIPHERAL_TIMER0_GATE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
-		break;
-
-		case PERIPHERAL_SHA_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_SHA_AHB:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_AES_CORE:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
-		break;
-
-		case PERIPHERAL_AES_AHB:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM1_2:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2_0:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_IDRAM2_1:
-			LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_RXTX:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
-				~LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_AHB:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
-				~LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
-		break;
-
-		case PERIPHERAL_BLE_PERIPH_REGS:
-			LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
-				~LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
-		break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (peripheral)
+    {
+        case PERIPHERAL_SPI_FLASH:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI_FLASH0_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_SPI1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_I2C0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_DUALT_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_DUALTIMER0_CLK_EN;
+        break;
+
+        case PERIPHERAL_GPIO_CLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_GPIO_CLK_EN;
+        break;
+
+        case PERIPHERAL_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_TIMER0_CLK_EN;
+        break;
+
+        case PERIPHERAL_WDT0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT0_CLK_EN;
+        break;
+
+        case PERIPHERAL_WDT1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_WDT1_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART0_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART0_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_UART1_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_UART1_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_NVIC:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IRQ_CTRLR_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_1_GL_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_IDRAM_2_GL_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_ROM:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ROM_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_IF:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_XBAR_IF_CLK_EN;
+        break;
+
+        case PERIPHERAL_AON_WRAPPER:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_AON_WRAPPER_CLK_EN;
+        break;
+
+        case PERIPHERAL_ARM_PCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLK_EN;
+        break;
+
+        case PERIPHERAL_ARM_GATED_PCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_ARM_PCLKG_EN;
+        break;
+
+        case PERIPHERAL_ARM_BLE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_BLE_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC0_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC1_CLK_EN;
+        break;
+
+        case PERIPHERAL_QDEC2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_QUAD_DEC2_CLK_EN;
+        break;
+
+        case PERIPHERAL_I2C1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_I2C1_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_0_CALIB_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE0_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE1_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE3:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE2_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE4:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE3_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE5:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE4_CLK_EN;
+        break;
+
+        case PERIPHERAL_EFUSE6:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_EFUSE5_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM0_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM1_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM2_CLK_EN;
+        break;
+
+        case PERIPHERAL_PWM3:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_PWM3_CLK_EN;
+        break;
+
+        case PERIPHERAL_ADC:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SENS_ADC_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI0_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI0_SCK_PHASE_INT_CLK_EN;
+        break;
+
+        case PERIPHERAL_SPI1_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SPI1_SCK_PHASE_INT_CLK_EN;
+        break;
+
+        case PERIPHERAL_GPIO_GCLK:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_GPIO_GCLK_EN;
+        break;
+
+        case PERIPHERAL_TIMER0_GATE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_TIMER0_PGCLK_EN;
+        break;
+
+        case PERIPHERAL_SHA_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_SHA_AHB:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_SHA_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_AES_CORE:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_CORE_CLK_EN;
+        break;
+
+        case PERIPHERAL_AES_AHB:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_AES_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_0_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_1_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM1_2:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_1_2_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2_0:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_0_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_IDRAM2_1:
+            LPMCU_MISC_REGS0->LPMCU_CLOCK_ENABLES_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1_IDRAM_2_1_MEM_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_RXTX:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_BTMCU_CTRL_RXTX_SEQ_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_AHB:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_BTMCU_CTRL_AHB_CLK_EN;
+        break;
+
+        case PERIPHERAL_BLE_PERIPH_REGS:
+            LPMCU_MISC_REGS0->BTMCU_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_BTMCU_CTRL_PERIPH_REGS_CLK_EN;
+        break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -707,94 +710,96 @@ enum status_code system_clock_peripheral_disable(enum system_peripheral peripher
  * \retval STATUS_ERR_INVALID_ARG  If data is invalid
  */
 enum status_code system_clock_peripheral_freq_config( \
-		enum system_peripheral peripheral, \
-		enum system_clock_freq freq)
+        enum system_peripheral peripheral, \
+        enum system_clock_freq freq)
 {
-	switch (peripheral) {
-		case PERIPHERAL_SPI_FLASH:
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
-					~LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_Msk;
-			switch (freq) {
-				case CLOCK_FREQ_26_MHZ:
-					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_3;
-					break;
-				case CLOCK_FREQ_13_MHZ:
-					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_2;
-					break;
-				case CLOCK_FREQ_6_5_MHZ:
-					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_1;
-				break;
-				case CLOCK_FREQ_3_25_MHZ:
-					LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-						LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_0;
-				break;
-			}
-			break;
-
-		case PERIPHERAL_DUALT_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL_Msk;
-			LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
-				LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL(freq);
-			break;
-
-		case PERIPHERAL_PWM0:
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg &= \
-				~LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->PWM0_CTRL.reg |= \
-				LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_PWM1:
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg &= \
-				~LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->PWM1_CTRL.reg |= \
-				LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_PWM2:
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg &= \
-				~LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->PWM2_CTRL.reg |= \
-				LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_PWM3:
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg &= \
-				~LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->PWM3_CTRL.reg |= \
-				LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_QDEC0:
-			LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &= \
-				~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |= \
-				LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_QDEC1:
-			LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &= \
-				~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |= \
-				LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL(freq);
-			break;
-
-		case PERIPHERAL_QDEC2:
-			LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &= \
-				~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL_Msk;
-			LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |= \
-				LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL(freq);
-			break;
-
-		default:
-			return 	STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (peripheral)
+    {
+        case PERIPHERAL_SPI_FLASH:
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+                    ~LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_Msk;
+            switch (freq)
+            {
+                case CLOCK_FREQ_26_MHZ:
+                    LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                        LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_3;
+                    break;
+                case CLOCK_FREQ_13_MHZ:
+                    LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                        LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_2;
+                    break;
+                case CLOCK_FREQ_6_5_MHZ:
+                    LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                        LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_1;
+                break;
+                case CLOCK_FREQ_3_25_MHZ:
+                    LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                        LPMCU_MISC_REGS_LPMCU_CTRL_SPI_FLASH0_CLKSEL_0;
+                break;
+            }
+            break;
+
+        case PERIPHERAL_DUALT_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL_Msk;
+            LPMCU_MISC_REGS0->LPMCU_CTRL.reg |= \
+                LPMCU_MISC_REGS_LPMCU_CTRL_DUALTIMER0_CLK_SEL(freq);
+            break;
+
+        case PERIPHERAL_PWM0:
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->PWM0_CTRL.reg |= \
+                LPMCU_MISC_REGS_PWM0_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_PWM1:
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->PWM1_CTRL.reg |= \
+                LPMCU_MISC_REGS_PWM1_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_PWM2:
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->PWM2_CTRL.reg |= \
+                LPMCU_MISC_REGS_PWM2_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_PWM3:
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->PWM3_CTRL.reg |= \
+                LPMCU_MISC_REGS_PWM3_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_QDEC0:
+            LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->QUAD_DEC0_CTRL.reg |= \
+                LPMCU_MISC_REGS_QUAD_DEC0_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_QDEC1:
+            LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->QUAD_DEC1_CTRL.reg |= \
+                LPMCU_MISC_REGS_QUAD_DEC1_CTRL_CLOCK_SEL(freq);
+            break;
+
+        case PERIPHERAL_QDEC2:
+            LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg &= \
+                ~LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL_Msk;
+            LPMCU_MISC_REGS0->QUAD_DEC2_CTRL.reg |= \
+                LPMCU_MISC_REGS_QUAD_DEC2_CTRL_CLOCK_SEL(freq);
+            break;
+
+        default:
+            return  STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -805,10 +810,10 @@ enum status_code system_clock_peripheral_freq_config( \
  */
 void system_global_reset(void)
 {
-	LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-		~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
-	LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-		LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
+    LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+        ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
+    LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+        LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GLOBAL_RSTN;
 };
 
 /**
@@ -824,313 +829,314 @@ void system_global_reset(void)
  */
 enum status_code system_peripheral_reset(enum system_peripheral peripheral)
 {
-	switch (peripheral) {
-		case PERIPHERAL_LPMCU_CPU:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
-		break;
-
-		case PERIPHERAL_SPI_FLASH:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
-		break;
-
-		case PERIPHERAL_SPI_FLASH_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
-		break;
-
-		case PERIPHERAL_SPI0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_SPI0_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
-		break;
-
-		case PERIPHERAL_SPI1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
-		break;
-
-		case PERIPHERAL_SPI1_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
-		break;
-
-		case PERIPHERAL_I2C0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_I2C0_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
-		break;
-
-		case PERIPHERAL_GPIO_CLK:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
-		break;
-
-		case PERIPHERAL_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
-		break;
-
-		case PERIPHERAL_UART0_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_UART0_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
-		break;
-
-		case PERIPHERAL_UART1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_UART1_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
-		break;
-
-		case PERIPHERAL_WDT0:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
-		break;
-
-		case PERIPHERAL_WDT1:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
-		break;
-
-		case PERIPHERAL_NVIC:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_MBIST:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
-		break;
-
-		case PERIPHERAL_LOW_POWER_APB:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
-		break;
-
-		case PERIPHERAL_LPMCU_DEBUG:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
-		break;
-
-		case PERIPHERAL_ARM_FREE_CLK:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
-		break;
-
-		case PERIPHERAL_ARM_APB:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
-		break;
-
-		case PERIPHERAL_QDEC0:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
-		break;
-
-		case PERIPHERAL_QDEC1:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
-		break;
-
-		case PERIPHERAL_QDEC2:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
-		break;
-
-		case PERIPHERAL_PWM0:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
-		break;
-
-		case PERIPHERAL_PWM1:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
-		break;
-
-		case PERIPHERAL_PWM2:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
-		break;
-
-		case PERIPHERAL_PWM3:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
-		break;
-
-		case PERIPHERAL_DUALT_TIMER:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
-		break;
-
-		case PERIPHERAL_I2C1_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_I2C1_IF:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
-		break;
-
-		case PERIPHERAL_SHA_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_SHA_AHB:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
-		break;
-
-		case PERIPHERAL_AES_CORE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
-		break;
-
-		case PERIPHERAL_AES_AHB:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
-		break;
-
-		case PERIPHERAL_SPI0_SCK_CLK:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
-		break;
-
-		case PERIPHERAL_SPI1_SCK_CLK:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
-		break;
-
-		case PERIPHERAL_SPI0_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
-		break;
-
-		case PERIPHERAL_SPI1_SCK_PHASE:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
-		break;
-
-		case PERIPHERAL_DMA:
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
-				~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
-			LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
-				LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
-		break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-
-	return STATUS_OK;
+    switch (peripheral)
+    {
+        case PERIPHERAL_LPMCU_CPU:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CPU_RSTN;
+        break;
+
+        case PERIPHERAL_SPI_FLASH:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_SYS_RSTN;
+        break;
+
+        case PERIPHERAL_SPI_FLASH_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI_FLASH0_RSTN;
+        break;
+
+        case PERIPHERAL_SPI0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_SPI0_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI0_IF_RSTN;
+        break;
+
+        case PERIPHERAL_SPI1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_CORE_RESETN;
+        break;
+
+        case PERIPHERAL_SPI1_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_SPI1_IF_RSTN;
+        break;
+
+        case PERIPHERAL_I2C0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_I2C0_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_I2C0_IF_RSTN;
+        break;
+
+        case PERIPHERAL_GPIO_CLK:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_GPIO_RSTN;
+        break;
+
+        case PERIPHERAL_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_TIMER0_RSTN;
+        break;
+
+        case PERIPHERAL_UART0_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_UART0_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART0_IF_RSTN;
+        break;
+
+        case PERIPHERAL_UART1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_UART1_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_UART1_IF_RSTN;
+        break;
+
+        case PERIPHERAL_WDT0:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT0_RSTN;
+        break;
+
+        case PERIPHERAL_WDT1:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_WDT1_RSTN;
+        break;
+
+        case PERIPHERAL_NVIC:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_IRQ_CTRLR_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_MBIST:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_MBIST_RSTN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_RSTN;
+        break;
+
+        case PERIPHERAL_LOW_POWER_APB:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_CALIB_XBAR_IF_RSTN;
+        break;
+
+        case PERIPHERAL_LPMCU_DEBUG:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_DBUG_RSTN;
+        break;
+
+        case PERIPHERAL_ARM_FREE_CLK:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_FREE_CLK_RSTN;
+        break;
+
+        case PERIPHERAL_ARM_APB:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_ARM_PRESETN_RSTN;
+        break;
+
+        case PERIPHERAL_QDEC0:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC0_RSTN;
+        break;
+
+        case PERIPHERAL_QDEC1:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC1_RSTN;
+        break;
+
+        case PERIPHERAL_QDEC2:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_QUAD_DEC2_RSTN;
+        break;
+
+        case PERIPHERAL_PWM0:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM0_RSTN;
+        break;
+
+        case PERIPHERAL_PWM1:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM1_RSTN;
+        break;
+
+        case PERIPHERAL_PWM2:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM2_RSTN;
+        break;
+
+        case PERIPHERAL_PWM3:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_0.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_0_PWM3_RSTN;
+        break;
+
+        case PERIPHERAL_DUALT_TIMER:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_DUALTIMER0_RSTN;
+        break;
+
+        case PERIPHERAL_I2C1_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_I2C1_IF:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_I2C1_IF_RSTN;
+        break;
+
+        case PERIPHERAL_SHA_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_SHA_AHB:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_SHA_AHB_RSTN;
+        break;
+
+        case PERIPHERAL_AES_CORE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_CORE_RSTN;
+        break;
+
+        case PERIPHERAL_AES_AHB:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SECURITY_AES_AHB_RSTN;
+        break;
+
+        case PERIPHERAL_SPI0_SCK_CLK:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_CLK_RSTN;
+        break;
+
+        case PERIPHERAL_SPI1_SCK_CLK:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_CLK_RSTN;
+        break;
+
+        case PERIPHERAL_SPI0_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI0_SCK_PHASE_INT_CLK_RSTN;
+        break;
+
+        case PERIPHERAL_SPI1_SCK_PHASE:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_SPI1_SCK_PHASE_INT_CLK_RSTN;
+        break;
+
+        case PERIPHERAL_DMA:
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg &= \
+                ~LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
+            LPMCU_MISC_REGS0->LPMCU_GLOBAL_RESET_1.reg |= \
+                LPMCU_MISC_REGS_LPMCU_GLOBAL_RESET_1_PROV_DMA_CTRL0_RSTN;
+        break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1143,11 +1149,11 @@ enum status_code system_peripheral_reset(enum system_peripheral peripheral)
  *
  */
 void system_register_isr(enum ram_isr_table_index isr_index,
-		uint32_t isr_address)
+        uint32_t isr_address)
 {
-	uint32_t *temp;
-	temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
-	*temp = isr_address;
+    uint32_t *temp;
+    temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
+    *temp = isr_address;
 }
 
 /**
@@ -1160,9 +1166,9 @@ void system_register_isr(enum ram_isr_table_index isr_index,
  */
 void system_unregister_isr(enum ram_isr_table_index isr_index)
 {
-	uint32_t *temp;
-	temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
-	*temp = 0;
+    uint32_t *temp;
+    temp = (uint32_t *)(isr_index * 4 + ISR_RAM_MAP_START_ADDRESS);
+    *temp = 0;
 }
 
 /**
@@ -1177,12 +1183,12 @@ void system_unregister_isr(enum ram_isr_table_index isr_index)
  */
 void system_calibration_get_config_defaults(struct system_calibration_config *config)
 {
-	config->clk_num             = CALIBRATION_CLK_NUM_1024;
-	config->interrupt_control   = CALIBRATION_INTERRUPT_OSC_DONE;
-	config->osc_fractional_part = 0;
-	config->osc_integer_part    = 0;
-	config->rtc_fractional_part = 0;
-	config->rtc_integer_part    = 0;
+    config->clk_num             = CALIBRATION_CLK_NUM_1024;
+    config->interrupt_control   = CALIBRATION_INTERRUPT_OSC_DONE;
+    config->osc_fractional_part = 0;
+    config->osc_integer_part    = 0;
+    config->rtc_fractional_part = 0;
+    config->rtc_integer_part    = 0;
 }
 
 /**
@@ -1195,14 +1201,14 @@ void system_calibration_get_config_defaults(struct system_calibration_config *co
  */
 void system_calibration_set_config(struct system_calibration_config *config)
 {
-	Assert(config);
-
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
-		~(LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS_Msk | \
-		LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL_Msk);
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
-		LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS(config->clk_num) | \
-		LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL(config->interrupt_control);
+    Assert(config);
+
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+        ~(LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS_Msk | \
+        LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL_Msk);
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+        LP_CLK_CAL_REGS_CONFIG_REG_NUMBER_CALIB_CLKS(config->clk_num) | \
+        LP_CLK_CAL_REGS_CONFIG_REG_IRQ_CONTROL(config->interrupt_control);
 }
 
 /**
@@ -1218,47 +1224,56 @@ void system_calibration_set_config(struct system_calibration_config *config)
  * \retval CALBRATION_DONE               Calibration done
  */
 enum system_calibration_status system_calibration_get_interrupt_status( \
-				struct system_calibration_config *config)
+                struct system_calibration_config *config)
 {
-	switch (config->interrupt_control) {
-		case CALIBRATION_INTERRUPT_OSC_DONE:
-			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING) {
-				return CALBRATION_IN_PROGRESS;
-			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE) {
-				return CALBRATION_DONE;
-			}
-			break;
-		case CALIBRATION_INTERRUPT_RTC_DONE:
-			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING) {
-				return CALBRATION_IN_PROGRESS;
-			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
-				return CALBRATION_DONE;
-			}
-			break;
-		case CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE:
-			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE || \
-				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
-				return CALBRATION_DONE;
-			} else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
-				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
-				return CALBRATION_IN_PROGRESS;
-			}
-			break;
-		case CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE:
-			if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE && \
-				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE) {
-				return CALBRATION_DONE;
-			} else if  (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
-				LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING){
-				return CALBRATION_IN_PROGRESS;
-			}
-			break;
-
-		default:
-			return CALBRATION_NO_IN_PROGRESS;
-	}
-
-	return CALBRATION_NO_IN_PROGRESS;
+    switch (config->interrupt_control)
+    {
+        case CALIBRATION_INTERRUPT_OSC_DONE:
+            if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING)
+            {
+                return CALBRATION_IN_PROGRESS;
+            } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE)
+            {
+                return CALBRATION_DONE;
+            }
+            break;
+        case CALIBRATION_INTERRUPT_RTC_DONE:
+            if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING)
+            {
+                return CALBRATION_IN_PROGRESS;
+            } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE)
+            {
+                return CALBRATION_DONE;
+            }
+            break;
+        case CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE:
+            if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE || \
+                LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE)
+                {
+                return CALBRATION_DONE;
+            } else if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
+                LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING)
+                {
+                return CALBRATION_IN_PROGRESS;
+            }
+            break;
+        case CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE:
+            if (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_OSC_DONE && \
+                LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.CALIBRATION_RTC_DONE)
+                {
+                return CALBRATION_DONE;
+            } else if  (LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.OSC_CAL_RUNNING || \
+                LP_CLK_CAL_REGS0->CALIB_STATUS_REG.bit.RTC_CAL_RUNNING)
+                {
+                return CALBRATION_IN_PROGRESS;
+            }
+            break;
+
+        default:
+            return CALBRATION_NO_IN_PROGRESS;
+    }
+
+    return CALBRATION_NO_IN_PROGRESS;
 }
 
 /**
@@ -1268,8 +1283,8 @@ enum system_calibration_status system_calibration_get_interrupt_status( \
  */
 void system_osc_calibration_enable(void)
 {
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
-		LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+        LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
 }
 
 /**
@@ -1279,8 +1294,8 @@ void system_osc_calibration_enable(void)
  */
 void system_osc_calibration_disable(void)
 {
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
-		~LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+        ~LP_CLK_CAL_REGS_CONFIG_REG_START_OSC_CALIB;
 }
 
 /**
@@ -1297,13 +1312,15 @@ void system_osc_calibration_disable(void)
  */
 enum system_calibration_status system_osc_calibration_get_status(void)
 {
-	if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
-		return CALBRATION_NO_IN_PROGRESS;
-	} else if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_DONE) {
-		return CALBRATION_DONE;
-	} else {
-		return CALBRATION_IN_PROGRESS;
-	}
+    if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.NO_CAL_IN_PROGRESS)
+    {
+        return CALBRATION_NO_IN_PROGRESS;
+    } else if (LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_DONE)
+    {
+        return CALBRATION_DONE;
+    } else {
+        return CALBRATION_IN_PROGRESS;
+    }
 }
 
 /**
@@ -1313,7 +1330,7 @@ enum system_calibration_status system_osc_calibration_get_status(void)
  */
 void system_osc_calibration_clear_status(void)
 {
-	//LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.reg = 0x01;
+    /*LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.reg = 0x01;*/
 }
 
 /**
@@ -1325,8 +1342,8 @@ void system_osc_calibration_clear_status(void)
  */
 void system_osc_calibration_result(struct system_calibration_config *config)
 {
-	config->osc_fractional_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_FRAC_COUNT;
-	config->osc_integer_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_INT_COUNT;
+    config->osc_fractional_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_FRAC_COUNT;
+    config->osc_integer_part = LP_CLK_CAL_REGS0->CALIB_OSC_COUNT_REG.bit.CAL_INT_COUNT;
 }
 
 /**
@@ -1336,8 +1353,8 @@ void system_osc_calibration_result(struct system_calibration_config *config)
  */
 void system_rtc_calibration_enable(void)
 {
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
-		LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg |= \
+        LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
 }
 
 /**
@@ -1347,8 +1364,8 @@ void system_rtc_calibration_enable(void)
  */
 void system_rtc_calibration_disable(void)
 {
-	LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
-		~LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
+    LP_CLK_CAL_REGS0->CONFIG_REG.reg &= \
+        ~LP_CLK_CAL_REGS_CONFIG_REG_START_RTC_CALIB;
 }
 
 /**
@@ -1365,13 +1382,15 @@ void system_rtc_calibration_disable(void)
  */
 enum system_calibration_status system_rtc_calibration_get_status(void)
 {
-	if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.NO_CAL_IN_PROGRESS) {
-		return CALBRATION_NO_IN_PROGRESS;
-	} else if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_DONE) {
-		return CALBRATION_DONE;
-	} else {
-		return CALBRATION_IN_PROGRESS;
-	}
+    if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.NO_CAL_IN_PROGRESS)
+    {
+        return CALBRATION_NO_IN_PROGRESS;
+    } else if (LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_DONE)
+    {
+        return CALBRATION_DONE;
+    } else {
+        return CALBRATION_IN_PROGRESS;
+    }
 }
 
 /**
@@ -1381,7 +1400,7 @@ enum system_calibration_status system_rtc_calibration_get_status(void)
  */
 void system_rtc_calibration_clear_status(void)
 {
-	//LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.reg = 0x01;
+    /*LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.reg = 0x01;*/
 }
 
 /**
@@ -1393,8 +1412,8 @@ void system_rtc_calibration_clear_status(void)
  */
 void system_rtc_calibration_result(struct system_calibration_config *config)
 {
-	config->rtc_fractional_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_FRAC_COUNT;
-	config->rtc_integer_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_INT_COUNT;
+    config->rtc_fractional_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_FRAC_COUNT;
+    config->rtc_integer_part = LP_CLK_CAL_REGS0->CALIB_RTC_COUNT_REG.bit.CAL_INT_COUNT;
 }
 
 /**
@@ -1410,56 +1429,64 @@ void system_rtc_calibration_result(struct system_calibration_config *config)
  * \retval STATUS_ERR_INVALID_ARG  If data is invalid
  */
 enum status_code system_clock_aon_config( \
-		enum system_peripheral_aon peripheral_aon, \
-		enum system_clock_aon_resource aon_resource)
+        enum system_peripheral_aon peripheral_aon, \
+        enum system_clock_aon_resource aon_resource)
 {
-	switch (peripheral_aon) {
-		case PERIPHERAL_AON_SLEEP_TIMER:
-			if (aon_resource == CLOCK_AON_RESOURCE_31_25_KHZ) {
-					AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-						AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
-					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-						~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
-			} else if (aon_resource == CLOCK_AON_RESOURCE_32_768_KHZ) {
-					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-						~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
-					AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-						AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
-			} else if (aon_resource == CLOCK_AON_DEFAULT) {
-					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-						~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
-					AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-						~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
-			}
-		break;
-
-		case PERIPHERAL_AON_POWER_SEQUENCER:
-			if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
-				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-					AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
-				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-					AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
-			} else if (aon_resource == CLOCK_AON_DEFAULT) {
-				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-					~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
-				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-					~AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
-			}
-		break;
-
-		case PERIPHERAL_AON_PD:
-			if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ) {
-				AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-					AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
-			} else if (aon_resource == CLOCK_AON_DEFAULT) {
-				AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-					~AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
-			}
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    switch (peripheral_aon)
+    {
+        case PERIPHERAL_AON_SLEEP_TIMER:
+            if (aon_resource == CLOCK_AON_RESOURCE_31_25_KHZ)
+            {
+                    AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                        AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+                    AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                        ~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+            } else if (aon_resource == CLOCK_AON_RESOURCE_32_768_KHZ)
+            {
+                    AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                        ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+                    AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                        AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+            } else if (aon_resource == CLOCK_AON_DEFAULT)
+            {
+                    AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                        ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_32KHZ_CLK_SLEEP_TIMER;
+                    AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                        ~AON_GP_REGS_AON_MISC_CTRL_USE_EXT_32KHZ_CLK_SLEEP_TIMER;
+            }
+        break;
+
+        case PERIPHERAL_AON_POWER_SEQUENCER:
+            if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ)
+            {
+                AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                    AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
+                AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                    AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
+            } else if (aon_resource == CLOCK_AON_DEFAULT)
+            {
+                AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                    ~AON_GP_REGS_AON_MISC_CTRL_USE_RTC_AON_PWR_SEQ_CLK;
+                AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                    ~AON_GP_REGS_AON_MISC_CTRL_USE_2M_AON_PWR_SEQ_CLK;
+            }
+        break;
+
+        case PERIPHERAL_AON_PD:
+            if (aon_resource == CLOCK_AON_RESOURCE_2_MHZ)
+            {
+                AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                    AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
+            } else if (aon_resource == CLOCK_AON_DEFAULT)
+            {
+                AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                    ~AON_GP_REGS_AON_MISC_CTRL_USE_OSC2M_AS_TB_CLK;
+            }
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -1475,21 +1502,22 @@ enum status_code system_clock_aon_config( \
  */
 enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon)
 {
-	switch (peripheral_aon) {
-		case PERIPHERAL_AON_SLEEP_TIMER:
-			AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-				AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
-		break;
-
-		case PERIPHERAL_AON_PD:
-			AON_GP_REGS0->AON_MISC_CTRL.reg |= \
-				AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
-		break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    switch (peripheral_aon)
+    {
+        case PERIPHERAL_AON_SLEEP_TIMER:
+            AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
+        break;
+
+        case PERIPHERAL_AON_PD:
+            AON_GP_REGS0->AON_MISC_CTRL.reg |= \
+                AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
+        break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -1505,19 +1533,20 @@ enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon p
  */
 enum status_code system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon)
 {
-	switch (peripheral_aon) {
-		case PERIPHERAL_AON_SLEEP_TIMER:
-			AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-				~AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
-		break;
-
-		case PERIPHERAL_AON_PD:
-			AON_GP_REGS0->AON_MISC_CTRL.reg &= \
-				~AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
-		break;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
-	return STATUS_OK;
+    switch (peripheral_aon)
+    {
+        case PERIPHERAL_AON_SLEEP_TIMER:
+            AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                ~AON_GP_REGS_AON_MISC_CTRL_AON_SLEEP_TIMER_CLK_EN;
+        break;
+
+        case PERIPHERAL_AON_PD:
+            AON_GP_REGS0->AON_MISC_CTRL.reg &= \
+                ~AON_GP_REGS_AON_MISC_CTRL_AON_EXT_32KHZ_OUT_EN;
+        break;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h
index 7bfca03b8b67..b84194f30958 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/system_sam_b.h
@@ -118,7 +118,7 @@ extern "C" {
 
 
 /* ISR RAM table address, definition from rom code, */
-#define ISR_RAM_MAP_START_ADDRESS	(0x10000000)
+#define ISR_RAM_MAP_START_ADDRESS   (0x10000000)
 /* ISR initialization status located in offset 0, definition from rom code*/
 #define ISR_RAM_MAP_INITIALIZED (0x20101985)
 
@@ -129,44 +129,44 @@ extern "C" {
  *
  */
 enum ram_isr_table_index {
-	RAM_ISR_TABLE_RESET_INDEX              = 1,
-	RAM_ISR_TABLE_NMI_INDEX                = 2,
-	RAM_ISR_TABLE_HARDFAULT_INDEX          = 3,
-	RAM_ISR_TABLE_SVC_INDEX                = 11,
-	RAM_ISR_TABLE_PENDSV_INDEX             = 14,
-	RAM_ISR_TABLE_SYSTICK_INDEX            = 15,
-	RAM_ISR_TABLE_UARTRX0_INDEX            = 16,
-	RAM_ISR_TABLE_UARTTX0_INDEX            = 17,
-	RAM_ISR_TABLE_UARTRX1_INDEX            = 18,
-	RAM_ISR_TABLE_UARTTX1_INDEX            = 19,
-	RAM_ISR_TABLE_SPIRX0_INDEX             = 20,
-	RAM_ISR_TABLE_SPITX0_INDEX             = 21,
-	RAM_ISR_TABLE_SPIRX1_INDEX             = 22,
-	RAM_ISR_TABLE_SPITX1_INDEX             = 23,
-	RAM_ISR_TABLE_I2CRX0_INDEX             = 24,
-	RAM_ISR_TABLE_I2CTX0_INDEX             = 25,
-	RAM_ISR_TABLE_I2CRX1_INDEX             = 26,
-	RAM_ISR_TABLE_I2CTX1_INDEX             = 27,
-	RAM_ISR_TABLE_WDT0_INDEX               = 28,
-	RAM_ISR_TABLE_WDT1_INDEX               = 29,
-	RAM_ISR_TABLE_DUALTIMER_INDEX          = 30,
-	RAM_ISR_TABLE_BLE_PERIPH_REGS_INDEX    = 31,
-	RAM_ISR_TABLE_SECURITY_INDEX           = 32,
-	RAM_ISR_TABLE_EFUSE_OUT_OF_RESET_INDEX = 33,
-	RAM_ISR_TABLE_SPI_FLASH_INDEX          = 34,
-	RAM_ISR_TABLE_LP_CLK_CAL_DONE_INDEX    = 35,	
-	RAM_ISR_TABLE_BROWNOUT_DETECTED_INDEX  = 36,	
-	RAM_ISR_TABLE_BLE_CORE_RESET_INDEX     = 37,
-	RAM_ISR_TABLE_BLE_LP_CORE_RESET_INDEX  = 38,
-	RAM_ISR_TABLE_PORT0_COMB_INDEX         = 39,
-	RAM_ISR_TABLE_PORT1_COMB_INDEX         = 40,
-	RAM_ISR_TABLE_PORT2_COMB_INDEX         = 41,
-	RAM_ISR_TABLE_TIMER0_INDEX             = 42,
-	RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX    = 43,
-	RAM_ISR_TABLE_BLE_OSC_EN_INDEX         = 44,
-	RAM_ISR_TABLE_BLE_WAKEUP_LP_INDEX      = 45,
-	RAM_ISR_TABLE_RXTX_SEQ_SLEEP_INDEX     = 46,
-	RAM_ISR_TABLE_BLE_CORE_INDEX           = 47,
+    RAM_ISR_TABLE_RESET_INDEX              = 1,
+    RAM_ISR_TABLE_NMI_INDEX                = 2,
+    RAM_ISR_TABLE_HARDFAULT_INDEX          = 3,
+    RAM_ISR_TABLE_SVC_INDEX                = 11,
+    RAM_ISR_TABLE_PENDSV_INDEX             = 14,
+    RAM_ISR_TABLE_SYSTICK_INDEX            = 15,
+    RAM_ISR_TABLE_UARTRX0_INDEX            = 16,
+    RAM_ISR_TABLE_UARTTX0_INDEX            = 17,
+    RAM_ISR_TABLE_UARTRX1_INDEX            = 18,
+    RAM_ISR_TABLE_UARTTX1_INDEX            = 19,
+    RAM_ISR_TABLE_SPIRX0_INDEX             = 20,
+    RAM_ISR_TABLE_SPITX0_INDEX             = 21,
+    RAM_ISR_TABLE_SPIRX1_INDEX             = 22,
+    RAM_ISR_TABLE_SPITX1_INDEX             = 23,
+    RAM_ISR_TABLE_I2CRX0_INDEX             = 24,
+    RAM_ISR_TABLE_I2CTX0_INDEX             = 25,
+    RAM_ISR_TABLE_I2CRX1_INDEX             = 26,
+    RAM_ISR_TABLE_I2CTX1_INDEX             = 27,
+    RAM_ISR_TABLE_WDT0_INDEX               = 28,
+    RAM_ISR_TABLE_WDT1_INDEX               = 29,
+    RAM_ISR_TABLE_DUALTIMER_INDEX          = 30,
+    RAM_ISR_TABLE_BLE_PERIPH_REGS_INDEX    = 31,
+    RAM_ISR_TABLE_SECURITY_INDEX           = 32,
+    RAM_ISR_TABLE_EFUSE_OUT_OF_RESET_INDEX = 33,
+    RAM_ISR_TABLE_SPI_FLASH_INDEX          = 34,
+    RAM_ISR_TABLE_LP_CLK_CAL_DONE_INDEX    = 35,
+    RAM_ISR_TABLE_BROWNOUT_DETECTED_INDEX  = 36,
+    RAM_ISR_TABLE_BLE_CORE_RESET_INDEX     = 37,
+    RAM_ISR_TABLE_BLE_LP_CORE_RESET_INDEX  = 38,
+    RAM_ISR_TABLE_PORT0_COMB_INDEX         = 39,
+    RAM_ISR_TABLE_PORT1_COMB_INDEX         = 40,
+    RAM_ISR_TABLE_PORT2_COMB_INDEX         = 41,
+    RAM_ISR_TABLE_TIMER0_INDEX             = 42,
+    RAM_ISR_TABLE_AON_SLEEP_TIMER_INDEX    = 43,
+    RAM_ISR_TABLE_BLE_OSC_EN_INDEX         = 44,
+    RAM_ISR_TABLE_BLE_WAKEUP_LP_INDEX      = 45,
+    RAM_ISR_TABLE_RXTX_SEQ_SLEEP_INDEX     = 46,
+    RAM_ISR_TABLE_BLE_CORE_INDEX           = 47,
 };
 
 /**
@@ -176,148 +176,148 @@ enum ram_isr_table_index {
  *
  */
 enum system_peripheral {
-	/** SPI Flash */
-	PERIPHERAL_SPI_FLASH,
-	/** SPI0 Core */
-	PERIPHERAL_SPI0_CORE,
-	/** SPI1 Core */
-	PERIPHERAL_SPI1_CORE,
-	/** I2C0 Core */
-	PERIPHERAL_I2C0_CORE,
-	/** ARM Dual Timer */
-	PERIPHERAL_DUALT_TIMER,
-	/** GPIO Controller */
-	PERIPHERAL_GPIO_CLK,
-	/** ARM Timer */
-	PERIPHERAL_TIMER,
-	/** WDT0 */
-	PERIPHERAL_WDT0,
-	/** WDT1 */
-	PERIPHERAL_WDT1,
-	/** UART0 Core */
-	PERIPHERAL_UART0_CORE,
-	/** UART0 Interface */
-	PERIPHERAL_UART0_IF,
-	/** UART1 Core */
-	PERIPHERAL_UART1_CORE,
-	/** UART1 Interface */
-	PERIPHERAL_UART1_IF,
-	/** NVIC */
-	PERIPHERAL_NVIC,
-	/** IDRAM1 Glue Logic */
-	PERIPHERAL_IDRAM1,
-	/** IDRAM2 Glue Logic */
-	PERIPHERAL_IDRAM2,
-	/** ROM */
-	PERIPHERAL_ROM,
-	/** Low Power Clock Calibration Interface */
-	PERIPHERAL_LOW_POWER_IF,
-	/** AON Wrapper */
-	PERIPHERAL_AON_WRAPPER,
-	/** ARM PCLK */
-	PERIPHERAL_ARM_PCLK,
-	/** ARM Gated PCLK */
-	PERIPHERAL_ARM_GATED_PCLK,
-	/** ARM BLE 8K Retention Memory */
-	PERIPHERAL_ARM_BLE,
-	/** Quad Decoder 0 */
-	PERIPHERAL_QDEC0,
-	/** Quad Decoder 1 */
-	PERIPHERAL_QDEC1,
-	/** Quad Decoder 2 */
-	PERIPHERAL_QDEC2,
-	/** I2C1 Core */
-	PERIPHERAL_I2C1_CORE,
-	/** Low Power Clock Calibration Core */
-	PERIPHERAL_LOW_POWER_CORE,
-
-	/* LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1 */
-	/** EFUSE1 */
-	PERIPHERAL_EFUSE1,
-	/** EFUSE2 */
-	PERIPHERAL_EFUSE2,
-	/** EFUSE3 */
-	PERIPHERAL_EFUSE3,
-	/** EFUSE4 */
-	PERIPHERAL_EFUSE4,
-	/** EFUSE5 */
-	PERIPHERAL_EFUSE5,
-	/** EFUSE6 */
-	PERIPHERAL_EFUSE6,
-	/** PWM0 */
-	PERIPHERAL_PWM0,
-	/** PWM1 */
-	PERIPHERAL_PWM1,
-	/** PWM2 */
-	PERIPHERAL_PWM2,
-	/** PWM3 */
-	PERIPHERAL_PWM3,
-	/** PMU Sensor ADC */
-	PERIPHERAL_ADC,
-	/** SPI0 SCK Phase Internal */
-	PERIPHERAL_SPI0_SCK_PHASE,
-	/** SPI1 SCK Phase Internal */
-	PERIPHERAL_SPI1_SCK_PHASE,
-	/** GPIO Controller */
-	PERIPHERAL_GPIO_GCLK,
-	/** ARM Timer 0 Gated APB */
-	PERIPHERAL_TIMER0_GATE,
-	/** SHA Core */
-	PERIPHERAL_SHA_CORE,
-	/** SHA AHB */
-	PERIPHERAL_SHA_AHB,
-	/** AES Core */
-	PERIPHERAL_AES_CORE,
-	/** AES AHB */
-	PERIPHERAL_AES_AHB,
-	/** IDRAM1_0 Memory */
-	PERIPHERAL_IDRAM1_0,
-	/** IDRAM1_1 Memory */
-	PERIPHERAL_IDRAM1_1,
-	/** IDRAM1_2 Memory */
-	PERIPHERAL_IDRAM1_2,
-	/** IDRAM2_0 Memory */
-	PERIPHERAL_IDRAM2_0,
-	/** IDRAM2_1 Memory */
-	PERIPHERAL_IDRAM2_1,
-
-	/** BLE RXTX Sequencer */
-	PERIPHERAL_BLE_RXTX,
-	/** BLE HAB */
-	PERIPHERAL_BLE_AHB,
-	/** BLE Periph Regs */
-	PERIPHERAL_BLE_PERIPH_REGS,
-
-	/** LPMCU CPU */
-	PERIPHERAL_LPMCU_CPU,
-	/** SPI Flash Interface */
-	PERIPHERAL_SPI_FLASH_IF,
-	/** SPI0 Interface */
-	PERIPHERAL_SPI0_IF,
-	/** SPI1 Interface */
-	PERIPHERAL_SPI1_IF,
-	/** I2C0 Interface */
-	PERIPHERAL_I2C0_IF,
-	/** MBIST Logic */
-	PERIPHERAL_MBIST,
-	/** Low Power Clock Calibration APB */
-	PERIPHERAL_LOW_POWER_APB,
-	/** LPMCU Debug */
-	PERIPHERAL_LPMCU_DEBUG,
-	/** Free Running ARM Clock */
-	PERIPHERAL_ARM_FREE_CLK,
-	/** ARM APB */
-	PERIPHERAL_ARM_APB,
-	/** I2C1 Interface */
-	PERIPHERAL_I2C1_IF,
-	/** SPI0 SCK Clock */
-	PERIPHERAL_SPI0_SCK_CLK,
-	/** SPI1 SCK Clock */
-	PERIPHERAL_SPI1_SCK_CLK,
-	/** DMA Controller */
-	PERIPHERAL_DMA,
-
-	PERIPHERAL_SLEEP_TIMER,
+    /** SPI Flash */
+    PERIPHERAL_SPI_FLASH,
+    /** SPI0 Core */
+    PERIPHERAL_SPI0_CORE,
+    /** SPI1 Core */
+    PERIPHERAL_SPI1_CORE,
+    /** I2C0 Core */
+    PERIPHERAL_I2C0_CORE,
+    /** ARM Dual Timer */
+    PERIPHERAL_DUALT_TIMER,
+    /** GPIO Controller */
+    PERIPHERAL_GPIO_CLK,
+    /** ARM Timer */
+    PERIPHERAL_TIMER,
+    /** WDT0 */
+    PERIPHERAL_WDT0,
+    /** WDT1 */
+    PERIPHERAL_WDT1,
+    /** UART0 Core */
+    PERIPHERAL_UART0_CORE,
+    /** UART0 Interface */
+    PERIPHERAL_UART0_IF,
+    /** UART1 Core */
+    PERIPHERAL_UART1_CORE,
+    /** UART1 Interface */
+    PERIPHERAL_UART1_IF,
+    /** NVIC */
+    PERIPHERAL_NVIC,
+    /** IDRAM1 Glue Logic */
+    PERIPHERAL_IDRAM1,
+    /** IDRAM2 Glue Logic */
+    PERIPHERAL_IDRAM2,
+    /** ROM */
+    PERIPHERAL_ROM,
+    /** Low Power Clock Calibration Interface */
+    PERIPHERAL_LOW_POWER_IF,
+    /** AON Wrapper */
+    PERIPHERAL_AON_WRAPPER,
+    /** ARM PCLK */
+    PERIPHERAL_ARM_PCLK,
+    /** ARM Gated PCLK */
+    PERIPHERAL_ARM_GATED_PCLK,
+    /** ARM BLE 8K Retention Memory */
+    PERIPHERAL_ARM_BLE,
+    /** Quad Decoder 0 */
+    PERIPHERAL_QDEC0,
+    /** Quad Decoder 1 */
+    PERIPHERAL_QDEC1,
+    /** Quad Decoder 2 */
+    PERIPHERAL_QDEC2,
+    /** I2C1 Core */
+    PERIPHERAL_I2C1_CORE,
+    /** Low Power Clock Calibration Core */
+    PERIPHERAL_LOW_POWER_CORE,
+
+    /* LPMCU_MISC_REGS_LPMCU_CLOCK_ENABLES_1 */
+    /** EFUSE1 */
+    PERIPHERAL_EFUSE1,
+    /** EFUSE2 */
+    PERIPHERAL_EFUSE2,
+    /** EFUSE3 */
+    PERIPHERAL_EFUSE3,
+    /** EFUSE4 */
+    PERIPHERAL_EFUSE4,
+    /** EFUSE5 */
+    PERIPHERAL_EFUSE5,
+    /** EFUSE6 */
+    PERIPHERAL_EFUSE6,
+    /** PWM0 */
+    PERIPHERAL_PWM0,
+    /** PWM1 */
+    PERIPHERAL_PWM1,
+    /** PWM2 */
+    PERIPHERAL_PWM2,
+    /** PWM3 */
+    PERIPHERAL_PWM3,
+    /** PMU Sensor ADC */
+    PERIPHERAL_ADC,
+    /** SPI0 SCK Phase Internal */
+    PERIPHERAL_SPI0_SCK_PHASE,
+    /** SPI1 SCK Phase Internal */
+    PERIPHERAL_SPI1_SCK_PHASE,
+    /** GPIO Controller */
+    PERIPHERAL_GPIO_GCLK,
+    /** ARM Timer 0 Gated APB */
+    PERIPHERAL_TIMER0_GATE,
+    /** SHA Core */
+    PERIPHERAL_SHA_CORE,
+    /** SHA AHB */
+    PERIPHERAL_SHA_AHB,
+    /** AES Core */
+    PERIPHERAL_AES_CORE,
+    /** AES AHB */
+    PERIPHERAL_AES_AHB,
+    /** IDRAM1_0 Memory */
+    PERIPHERAL_IDRAM1_0,
+    /** IDRAM1_1 Memory */
+    PERIPHERAL_IDRAM1_1,
+    /** IDRAM1_2 Memory */
+    PERIPHERAL_IDRAM1_2,
+    /** IDRAM2_0 Memory */
+    PERIPHERAL_IDRAM2_0,
+    /** IDRAM2_1 Memory */
+    PERIPHERAL_IDRAM2_1,
+
+    /** BLE RXTX Sequencer */
+    PERIPHERAL_BLE_RXTX,
+    /** BLE HAB */
+    PERIPHERAL_BLE_AHB,
+    /** BLE Periph Regs */
+    PERIPHERAL_BLE_PERIPH_REGS,
+
+    /** LPMCU CPU */
+    PERIPHERAL_LPMCU_CPU,
+    /** SPI Flash Interface */
+    PERIPHERAL_SPI_FLASH_IF,
+    /** SPI0 Interface */
+    PERIPHERAL_SPI0_IF,
+    /** SPI1 Interface */
+    PERIPHERAL_SPI1_IF,
+    /** I2C0 Interface */
+    PERIPHERAL_I2C0_IF,
+    /** MBIST Logic */
+    PERIPHERAL_MBIST,
+    /** Low Power Clock Calibration APB */
+    PERIPHERAL_LOW_POWER_APB,
+    /** LPMCU Debug */
+    PERIPHERAL_LPMCU_DEBUG,
+    /** Free Running ARM Clock */
+    PERIPHERAL_ARM_FREE_CLK,
+    /** ARM APB */
+    PERIPHERAL_ARM_APB,
+    /** I2C1 Interface */
+    PERIPHERAL_I2C1_IF,
+    /** SPI0 SCK Clock */
+    PERIPHERAL_SPI0_SCK_CLK,
+    /** SPI1 SCK Clock */
+    PERIPHERAL_SPI1_SCK_CLK,
+    /** DMA Controller */
+    PERIPHERAL_DMA,
+
+    PERIPHERAL_SLEEP_TIMER,
 };
 
 /**
@@ -327,12 +327,12 @@ enum system_peripheral {
  *
  */
 enum system_peripheral_aon {
-	/** Sleep timer */
-	PERIPHERAL_AON_SLEEP_TIMER,
-	/** Power sequencer */
-	PERIPHERAL_AON_POWER_SEQUENCER,
-	/** PD0 */
-	PERIPHERAL_AON_PD,
+    /** Sleep timer */
+    PERIPHERAL_AON_SLEEP_TIMER,
+    /** Power sequencer */
+    PERIPHERAL_AON_POWER_SEQUENCER,
+    /** PD0 */
+    PERIPHERAL_AON_PD,
 };
 
 /**
@@ -342,14 +342,14 @@ enum system_peripheral_aon {
  *
  */
 enum system_clock_freq {
-	/** 26MHz */
-	CLOCK_FREQ_26_MHZ,
-	/** 13MHz */
-	CLOCK_FREQ_13_MHZ,
-	/** 6.5MHz */
-	CLOCK_FREQ_6_5_MHZ,
-	/** 3.25MHz */
-	CLOCK_FREQ_3_25_MHZ,
+    /** 26MHz */
+    CLOCK_FREQ_26_MHZ,
+    /** 13MHz */
+    CLOCK_FREQ_13_MHZ,
+    /** 6.5MHz */
+    CLOCK_FREQ_6_5_MHZ,
+    /** 3.25MHz */
+    CLOCK_FREQ_3_25_MHZ,
 };
 
 /**
@@ -359,12 +359,12 @@ enum system_clock_freq {
  *
  */
 enum system_clock_resource {
-	/** Use 26MHz Crystal Oscillator XO as ARM clock */
-	CLOCK_RESOURCE_XO_26_MHZ,
-	/** Use either LP 2MHz clock */
-	CLOCK_RESOURCE_LP_2_MHZ,
-	/** 26MHz integrated RC Oscillator */
-	CLOCK_RESOURCE_RC_26_MHZ,
+    /** Use 26MHz Crystal Oscillator XO as ARM clock */
+    CLOCK_RESOURCE_XO_26_MHZ,
+    /** Use either LP 2MHz clock */
+    CLOCK_RESOURCE_LP_2_MHZ,
+    /** 26MHz integrated RC Oscillator */
+    CLOCK_RESOURCE_RC_26_MHZ,
 };
 
 /**
@@ -374,14 +374,14 @@ enum system_clock_resource {
  *
  */
 enum system_clock_aon_resource {
-	/** OSC 2MHz */
-	CLOCK_AON_RESOURCE_2_MHZ,
-	/** OSC 2MHz/64 = 31.25KHz */
-	CLOCK_AON_RESOURCE_31_25_KHZ,
-	/** RTC XO 32.768KHz */
-	CLOCK_AON_RESOURCE_32_768_KHZ,
-	/** Use default clock */
-	CLOCK_AON_DEFAULT,
+    /** OSC 2MHz */
+    CLOCK_AON_RESOURCE_2_MHZ,
+    /** OSC 2MHz/64 = 31.25KHz */
+    CLOCK_AON_RESOURCE_31_25_KHZ,
+    /** RTC XO 32.768KHz */
+    CLOCK_AON_RESOURCE_32_768_KHZ,
+    /** Use default clock */
+    CLOCK_AON_DEFAULT,
 };
 
 /**
@@ -391,38 +391,38 @@ enum system_clock_aon_resource {
  *
  */
 enum system_calibration_clk_num {
-	/** 1 clock */
-	CALIBRATION_CLK_NUM_1,
-	/** 2 clocks */
-	CALIBRATION_CLK_NUM_2,
-	/** 4 clocks */
-	CALIBRATION_CLK_NUM_4,
-	/** 8 clocks */
-	CALIBRATION_CLK_NUM_8,
-	/** 16 clocks */
-	CALIBRATION_CLK_NUM_16,
-	/** 32 clocks */
-	CALIBRATION_CLK_NUM_32,
-	/** 64 clocks */
-	CALIBRATION_CLK_NUM_64,
-	/** 128 clocks */
-	CALIBRATION_CLK_NUM_128,
-	/** 256 clocks */
-	CALIBRATION_CLK_NUM_256,
-	/** 512 clocks */
-	CALIBRATION_CLK_NUM_512,
-	/** 1024 clocks */
-	CALIBRATION_CLK_NUM_1024,
-	/** 2048 clocks */
-	CALIBRATION_CLK_NUM_2048,
-	/** 4096 clocks */
-	CALIBRATION_CLK_NUM_4096,
-	/** 8192 clocks */
-	CALIBRATION_CLK_NUM_8192,
-	/** 16384 clocks */
-	CALIBRATION_CLK_NUM_16384,
-	/** 32768 clocks */
-	CALIBRATION_CLK_NUM_32768,
+    /** 1 clock */
+    CALIBRATION_CLK_NUM_1,
+    /** 2 clocks */
+    CALIBRATION_CLK_NUM_2,
+    /** 4 clocks */
+    CALIBRATION_CLK_NUM_4,
+    /** 8 clocks */
+    CALIBRATION_CLK_NUM_8,
+    /** 16 clocks */
+    CALIBRATION_CLK_NUM_16,
+    /** 32 clocks */
+    CALIBRATION_CLK_NUM_32,
+    /** 64 clocks */
+    CALIBRATION_CLK_NUM_64,
+    /** 128 clocks */
+    CALIBRATION_CLK_NUM_128,
+    /** 256 clocks */
+    CALIBRATION_CLK_NUM_256,
+    /** 512 clocks */
+    CALIBRATION_CLK_NUM_512,
+    /** 1024 clocks */
+    CALIBRATION_CLK_NUM_1024,
+    /** 2048 clocks */
+    CALIBRATION_CLK_NUM_2048,
+    /** 4096 clocks */
+    CALIBRATION_CLK_NUM_4096,
+    /** 8192 clocks */
+    CALIBRATION_CLK_NUM_8192,
+    /** 16384 clocks */
+    CALIBRATION_CLK_NUM_16384,
+    /** 32768 clocks */
+    CALIBRATION_CLK_NUM_32768,
 };
 
 /**
@@ -432,32 +432,32 @@ enum system_calibration_clk_num {
  *
  */
 enum system_calibration_interrput_control {
-	/** IRQ when OSC calibration done */
-	CALIBRATION_INTERRUPT_OSC_DONE,
-	/** IRQ when RTC calibration done */
-	CALIBRATION_INTERRUPT_RTC_DONE,
-	/** IRQ when OSC or RTC calibration done */
-	CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE,
-	/** IRQ when OSC and RTC calibration done */
-	CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE,
+    /** IRQ when OSC calibration done */
+    CALIBRATION_INTERRUPT_OSC_DONE,
+    /** IRQ when RTC calibration done */
+    CALIBRATION_INTERRUPT_RTC_DONE,
+    /** IRQ when OSC or RTC calibration done */
+    CALIBRATION_INTERRUPT_OSC_OR_RTC_DONE,
+    /** IRQ when OSC and RTC calibration done */
+    CALIBRATION_INTERRUPT_OSC_AND_RTC_DONE,
 };
 
 enum system_calibration_status {
-	/** No calibration in progress */
-	CALBRATION_NO_IN_PROGRESS,
-	/** Calibration in progress */
-	CALBRATION_IN_PROGRESS,
-	/** Calibration done */
-	CALBRATION_DONE,
+    /** No calibration in progress */
+    CALBRATION_NO_IN_PROGRESS,
+    /** Calibration in progress */
+    CALBRATION_IN_PROGRESS,
+    /** Calibration done */
+    CALBRATION_DONE,
 };
 
 struct system_calibration_config {
-	enum system_calibration_clk_num clk_num;
-	enum system_calibration_interrput_control interrupt_control;
-	uint16_t osc_fractional_part;
-	uint16_t osc_integer_part;
-	uint16_t rtc_fractional_part;
-	uint16_t rtc_integer_part;
+    enum system_calibration_clk_num clk_num;
+    enum system_calibration_interrput_control interrupt_control;
+    uint16_t osc_fractional_part;
+    uint16_t osc_integer_part;
+    uint16_t rtc_fractional_part;
+    uint16_t rtc_integer_part;
 };
 
 /**
@@ -465,15 +465,15 @@ struct system_calibration_config {
  * @{
  */
 enum status_code system_clock_config( \
-				enum system_clock_resource resoure, \
-				enum system_clock_freq freq);
+                enum system_clock_resource resoure, \
+                enum system_clock_freq freq);
 uint32_t system_clock_get_value(void);
 enum status_code system_clock_peripheral_enable(enum system_peripheral peripheral);
 enum status_code system_clock_peripheral_disable(enum system_peripheral peripheral);
 enum status_code system_clock_peripheral_freq_config( \
-				enum system_peripheral peripheral, \
-				enum system_clock_freq freq);
-//void system_init(void);
+                enum system_peripheral peripheral, \
+                enum system_clock_freq freq);
+/*void system_init(void);*/
 /** @} */
 
 /**
@@ -489,7 +489,7 @@ enum status_code system_peripheral_reset(enum system_peripheral peripheral);
  * @{
  */
 void system_register_isr(enum ram_isr_table_index isr_index,
-		uint32_t isr_address);
+        uint32_t isr_address);
 void system_unregister_isr(enum ram_isr_table_index isr_index);
 /** @} */
 
@@ -500,7 +500,7 @@ void system_unregister_isr(enum ram_isr_table_index isr_index);
 void system_calibration_get_config_defaults(struct system_calibration_config *config);
 void system_calibration_set_config(struct system_calibration_config *config);
 enum system_calibration_status system_calibration_get_interrupt_status( \
-				struct system_calibration_config *config);
+                struct system_calibration_config *config);
 
 void system_osc_calibration_enable(void);
 void system_osc_calibration_disable(void);
@@ -520,8 +520,8 @@ void system_rtc_calibration_result(struct system_calibration_config *config);
  * @{
  */
 enum status_code system_clock_aon_config( \
-				enum system_peripheral_aon peripheral_aon, \
-				enum system_clock_aon_resource aon_resource);
+                enum system_peripheral_aon peripheral_aon, \
+                enum system_clock_aon_resource aon_resource);
 enum status_code system_clock_peripheral_aon_enable(enum system_peripheral_aon peripheral_aon);
 enum status_code system_clock_peripheral_aon_disable(enum system_peripheral_aon peripheral_aon);
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h
index f34e82660968..468db8146898 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc.h
@@ -48,7 +48,7 @@
 #define TC_H_INCLUDED
 
 /**
- * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter (TC) Driver 
+ * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter (TC) Driver
  *
  * This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the configuration
  * and management of the timer modules within the device, for waveform
@@ -536,17 +536,17 @@ extern "C" {
 #if TC_ASYNC == true
 /** Enum for the possible callback types for the TC module. */
 enum tc_callback {
-	/** Callback for TC overflow */
-	TC_CALLBACK_OVERFLOW,
-	/** Callback for capture overflow error */
-	TC_CALLBACK_ERROR,
-	/** Callback for capture compare channel 0 */
-	TC_CALLBACK_CC_CHANNEL0,
-	/** Callback for capture compare channel 1 */
-	TC_CALLBACK_CC_CHANNEL1,
+    /** Callback for TC overflow */
+    TC_CALLBACK_OVERFLOW,
+    /** Callback for capture overflow error */
+    TC_CALLBACK_ERROR,
+    /** Callback for capture compare channel 0 */
+    TC_CALLBACK_CC_CHANNEL0,
+    /** Callback for capture compare channel 1 */
+    TC_CALLBACK_CC_CHANNEL1,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	TC_CALLBACK_N,
+    /** Number of available callbacks */
+    TC_CALLBACK_N,
 #  endif
 };
 #endif
@@ -603,10 +603,10 @@ enum tc_callback {
  * operations on.
  */
 enum tc_compare_capture_channel {
-	/** Index of compare capture channel 0 */
-	TC_COMPARE_CAPTURE_CHANNEL_0,
-	/** Index of compare capture channel 1 */
-	TC_COMPARE_CAPTURE_CHANNEL_1,
+    /** Index of compare capture channel 0 */
+    TC_COMPARE_CAPTURE_CHANNEL_0,
+    /** Index of compare capture channel 1 */
+    TC_COMPARE_CAPTURE_CHANNEL_1,
 };
 
 /**
@@ -643,25 +643,25 @@ enum tc_compare_capture_channel {
  *
  */
 enum tc_wave_generation {
-	/** Top is maximum, except in 8-bit counter size where it is the PER
-	 * register
-	 */
-	TC_WAVE_GENERATION_NORMAL_FREQ      = TC_WAVE_GENERATION_NORMAL_FREQ_MODE,
-
-	/** Top is CC0, except in 8-bit counter size where it is the PER
-	 * register
-	 */
-	TC_WAVE_GENERATION_MATCH_FREQ       = TC_WAVE_GENERATION_MATCH_FREQ_MODE,
-
-	/** Top is maximum, except in 8-bit counter size where it is the PER
-	 * register
-	 */
-	TC_WAVE_GENERATION_NORMAL_PWM       = TC_WAVE_GENERATION_NORMAL_PWM_MODE,
-
-	/** Top is CC0, except in 8-bit counter size where it is the PER
-	 * register
-	 */
-	TC_WAVE_GENERATION_MATCH_PWM        = TC_WAVE_GENERATION_MATCH_PWM_MODE,
+    /** Top is maximum, except in 8-bit counter size where it is the PER
+     * register
+     */
+    TC_WAVE_GENERATION_NORMAL_FREQ      = TC_WAVE_GENERATION_NORMAL_FREQ_MODE,
+
+    /** Top is CC0, except in 8-bit counter size where it is the PER
+     * register
+     */
+    TC_WAVE_GENERATION_MATCH_FREQ       = TC_WAVE_GENERATION_MATCH_FREQ_MODE,
+
+    /** Top is maximum, except in 8-bit counter size where it is the PER
+     * register
+     */
+    TC_WAVE_GENERATION_NORMAL_PWM       = TC_WAVE_GENERATION_NORMAL_PWM_MODE,
+
+    /** Top is CC0, except in 8-bit counter size where it is the PER
+     * register
+     */
+    TC_WAVE_GENERATION_MATCH_PWM        = TC_WAVE_GENERATION_MATCH_PWM_MODE,
 };
 
 /**
@@ -670,24 +670,24 @@ enum tc_wave_generation {
  * This enum specifies the maximum value it is possible to count to.
  */
 enum tc_counter_size {
-	/** The counter's maximum value is 0xFF, the period register is
-	 * available to be used as top value
-	 */
-	TC_COUNTER_SIZE_8BIT                = TC_CTRLA_MODE_COUNT8,
-
-	/** The counter's maximum value is 0xFFFF. There is no separate
-	 * period register, to modify top one of the capture compare
-	 * registers has to be used. This limits the amount of
-	 * available channels.
-	 */
-	TC_COUNTER_SIZE_16BIT               = TC_CTRLA_MODE_COUNT16,
-
-	/** The counter's maximum value is 0xFFFFFFFF. There is no separate
-	 * period register, to modify top one of the capture compare
-	 * registers has to be used. This limits the amount of
-	 * available channels.
-	 */
-	TC_COUNTER_SIZE_32BIT               = TC_CTRLA_MODE_COUNT32,
+    /** The counter's maximum value is 0xFF, the period register is
+     * available to be used as top value
+     */
+    TC_COUNTER_SIZE_8BIT                = TC_CTRLA_MODE_COUNT8,
+
+    /** The counter's maximum value is 0xFFFF. There is no separate
+     * period register, to modify top one of the capture compare
+     * registers has to be used. This limits the amount of
+     * available channels.
+     */
+    TC_COUNTER_SIZE_16BIT               = TC_CTRLA_MODE_COUNT16,
+
+    /** The counter's maximum value is 0xFFFFFFFF. There is no separate
+     * period register, to modify top one of the capture compare
+     * registers has to be used. This limits the amount of
+     * available channels.
+     */
+    TC_COUNTER_SIZE_32BIT               = TC_CTRLA_MODE_COUNT32,
 };
 
 /**
@@ -696,19 +696,19 @@ enum tc_counter_size {
  * This enum specify how the counter and prescaler should reload.
  */
 enum tc_reload_action {
-	/** The counter is reloaded/reset on the next GCLK and starts
-	 * counting on the prescaler clock
-	 */
-	TC_RELOAD_ACTION_GCLK               = TC_CTRLA_PRESCSYNC_GCLK,
-
-	/** The counter is reloaded/reset on the next prescaler clock
-	 */
-	TC_RELOAD_ACTION_PRESC              = TC_CTRLA_PRESCSYNC_PRESC,
-
-	/** The counter is reloaded/reset on the next GCLK, and the
-	 * prescaler is restarted as well
-	 */
-	TC_RELOAD_ACTION_RESYNC             = TC_CTRLA_PRESCSYNC_RESYNC,
+    /** The counter is reloaded/reset on the next GCLK and starts
+     * counting on the prescaler clock
+     */
+    TC_RELOAD_ACTION_GCLK               = TC_CTRLA_PRESCSYNC_GCLK,
+
+    /** The counter is reloaded/reset on the next prescaler clock
+     */
+    TC_RELOAD_ACTION_PRESC              = TC_CTRLA_PRESCSYNC_PRESC,
+
+    /** The counter is reloaded/reset on the next GCLK, and the
+     * prescaler is restarted as well
+     */
+    TC_RELOAD_ACTION_RESYNC             = TC_CTRLA_PRESCSYNC_RESYNC,
 };
 
 /**
@@ -719,22 +719,22 @@ enum tc_reload_action {
  * module to make the counter count slower.
  */
 enum tc_clock_prescaler {
-	/** Divide clock by 1 */
-	TC_CLOCK_PRESCALER_DIV1             = TC_CTRLA_PRESCALER(0),
-	/** Divide clock by 2 */
-	TC_CLOCK_PRESCALER_DIV2             = TC_CTRLA_PRESCALER(1),
-	/** Divide clock by 4 */
-	TC_CLOCK_PRESCALER_DIV4             = TC_CTRLA_PRESCALER(2),
-	/** Divide clock by 8 */
-	TC_CLOCK_PRESCALER_DIV8             = TC_CTRLA_PRESCALER(3),
-	/** Divide clock by 16 */
-	TC_CLOCK_PRESCALER_DIV16            = TC_CTRLA_PRESCALER(4),
-	/** Divide clock by 64 */
-	TC_CLOCK_PRESCALER_DIV64            = TC_CTRLA_PRESCALER(5),
-	/** Divide clock by 256 */
-	TC_CLOCK_PRESCALER_DIV256           = TC_CTRLA_PRESCALER(6),
-	/** Divide clock by 1024 */
-	TC_CLOCK_PRESCALER_DIV1024          = TC_CTRLA_PRESCALER(7),
+    /** Divide clock by 1 */
+    TC_CLOCK_PRESCALER_DIV1             = TC_CTRLA_PRESCALER(0),
+    /** Divide clock by 2 */
+    TC_CLOCK_PRESCALER_DIV2             = TC_CTRLA_PRESCALER(1),
+    /** Divide clock by 4 */
+    TC_CLOCK_PRESCALER_DIV4             = TC_CTRLA_PRESCALER(2),
+    /** Divide clock by 8 */
+    TC_CLOCK_PRESCALER_DIV8             = TC_CTRLA_PRESCALER(3),
+    /** Divide clock by 16 */
+    TC_CLOCK_PRESCALER_DIV16            = TC_CTRLA_PRESCALER(4),
+    /** Divide clock by 64 */
+    TC_CLOCK_PRESCALER_DIV64            = TC_CTRLA_PRESCALER(5),
+    /** Divide clock by 256 */
+    TC_CLOCK_PRESCALER_DIV256           = TC_CTRLA_PRESCALER(6),
+    /** Divide clock by 1024 */
+    TC_CLOCK_PRESCALER_DIV1024          = TC_CTRLA_PRESCALER(7),
 };
 
 /**
@@ -743,11 +743,11 @@ enum tc_clock_prescaler {
  * Timer/Counter count direction.
  */
 enum tc_count_direction {
-	/** Timer should count upward from zero to MAX */
-	TC_COUNT_DIRECTION_UP,
+    /** Timer should count upward from zero to MAX */
+    TC_COUNT_DIRECTION_UP,
 
-	/** Timer should count downward to zero from MAX */
-	TC_COUNT_DIRECTION_DOWN,
+    /** Timer should count downward to zero from MAX */
+    TC_COUNT_DIRECTION_DOWN,
 };
 
 /**
@@ -773,12 +773,12 @@ enum tc_count_direction {
  * Output waveform inversion mode.
  */
 enum tc_waveform_invert_output {
-	/** No inversion of the waveform output */
-	TC_WAVEFORM_INVERT_OUTPUT_NONE      = 0,
-	/** Invert output from compare channel 0 */
-	TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE,
-	/** Invert output from compare channel 1 */
-	TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE,
+    /** No inversion of the waveform output */
+    TC_WAVEFORM_INVERT_OUTPUT_NONE      = 0,
+    /** Invert output from compare channel 0 */
+    TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE,
+    /** Invert output from compare channel 1 */
+    TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE,
 };
 
 /**
@@ -787,29 +787,29 @@ enum tc_waveform_invert_output {
  * Event action to perform when the module is triggered by an event.
  */
 enum tc_event_action {
-	/** No event action */
-	TC_EVENT_ACTION_OFF                 = TC_EVCTRL_EVACT_OFF,
-	/** Re-trigger on event */
-	TC_EVENT_ACTION_RETRIGGER           = TC_EVCTRL_EVACT_RETRIGGER,
-	/** Increment counter on event */
-	TC_EVENT_ACTION_INCREMENT_COUNTER   = TC_EVCTRL_EVACT_COUNT,
-	/** Start counter on event */
-	TC_EVENT_ACTION_START               = TC_EVCTRL_EVACT_START,
-
-	/** Store period in capture register 0, pulse width in capture
-	 *  register 1
-	 */
-	TC_EVENT_ACTION_PPW                 = TC_EVCTRL_EVACT_PPW,
-
-	/** Store pulse width in capture register 0, period in capture
-	 *  register 1
-	 */
-	TC_EVENT_ACTION_PWP                 = TC_EVCTRL_EVACT_PWP,
+    /** No event action */
+    TC_EVENT_ACTION_OFF                 = TC_EVCTRL_EVACT_OFF,
+    /** Re-trigger on event */
+    TC_EVENT_ACTION_RETRIGGER           = TC_EVCTRL_EVACT_RETRIGGER,
+    /** Increment counter on event */
+    TC_EVENT_ACTION_INCREMENT_COUNTER   = TC_EVCTRL_EVACT_COUNT,
+    /** Start counter on event */
+    TC_EVENT_ACTION_START               = TC_EVCTRL_EVACT_START,
+
+    /** Store period in capture register 0, pulse width in capture
+     *  register 1
+     */
+    TC_EVENT_ACTION_PPW                 = TC_EVCTRL_EVACT_PPW,
+
+    /** Store pulse width in capture register 0, period in capture
+     *  register 1
+     */
+    TC_EVENT_ACTION_PWP                 = TC_EVCTRL_EVACT_PWP,
 #ifdef FEATURE_TC_STAMP_PW_CAPTURE
-	/** Time stamp capture */
-	TC_EVENT_ACTION_STAMP               = TC_EVCTRL_EVACT_STAMP,
-	/** Pulse width capture */
-	TC_EVENT_ACTION_PW                  = TC_EVCTRL_EVACT_PW,
+    /** Time stamp capture */
+    TC_EVENT_ACTION_STAMP               = TC_EVCTRL_EVACT_STAMP,
+    /** Pulse width capture */
+    TC_EVENT_ACTION_PW                  = TC_EVCTRL_EVACT_PW,
 #endif
 };
 
@@ -819,63 +819,63 @@ enum tc_event_action {
  * Event flags for the \ref tc_enable_events() and \ref tc_disable_events().
  */
 struct tc_events {
-	/** Generate an output event on a compare channel match */
-	bool generate_event_on_compare_channel
-			[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
-	/** Generate an output event on counter overflow */
-	bool generate_event_on_overflow;
-	/** Perform the configured event action when an incoming event is signalled */
-	bool on_event_perform_action;
-	/** Specifies if the input event source is inverted, when used in PWP or
-	 *  PPW event action modes
-	 */
-	bool invert_event_input;
-	/** Specifies which event to trigger if an event is triggered */
-	enum tc_event_action event_action;
+    /** Generate an output event on a compare channel match */
+    bool generate_event_on_compare_channel
+            [NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Generate an output event on counter overflow */
+    bool generate_event_on_overflow;
+    /** Perform the configured event action when an incoming event is signalled */
+    bool on_event_perform_action;
+    /** Specifies if the input event source is inverted, when used in PWP or
+     *  PPW event action modes
+     */
+    bool invert_event_input;
+    /** Specifies which event to trigger if an event is triggered */
+    enum tc_event_action event_action;
 };
 
 /**
  * \brief Configuration struct for TC module in 8-bit size counter mode.
  */
 struct tc_8bit_config {
-	/** Initial timer count value */
-	uint8_t value;
-	/** Where to count to or from depending on the direction on the counter */
-	uint8_t period;
-	/** Value to be used for compare match on each channel */
-	uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Initial timer count value */
+    uint8_t value;
+    /** Where to count to or from depending on the direction on the counter */
+    uint8_t period;
+    /** Value to be used for compare match on each channel */
+    uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
 };
 
 /**
  * \brief Configuration struct for TC module in 16-bit size counter mode.
  */
 struct tc_16bit_config {
-	/** Initial timer count value */
-	uint16_t value;
-	/** Value to be used for compare match on each channel */
-	uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Initial timer count value */
+    uint16_t value;
+    /** Value to be used for compare match on each channel */
+    uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
 };
 
 /**
  * \brief Configuration struct for TC module in 32-bit size counter mode.
  */
 struct tc_32bit_config {
-	/** Initial timer count value */
-	uint32_t value;
-	/** Value to be used for compare match on each channel */
-	uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Initial timer count value */
+    uint32_t value;
+    /** Value to be used for compare match on each channel */
+    uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
 };
 
 /**
  * \brief Configuration struct for TC module in 32-bit size counter mode.
  */
 struct tc_pwm_channel {
-	/** When \c true, PWM output for the given channel is enabled */
-	bool enabled;
-	/** Specifies pin output for each channel */
-	uint32_t pin_out;
-	/** Specifies Multiplexer (MUX) setting for each output channel pin */
-	uint32_t pin_mux;
+    /** When \c true, PWM output for the given channel is enabled */
+    bool enabled;
+    /** Specifies pin output for each channel */
+    uint32_t pin_out;
+    /** Specifies Multiplexer (MUX) setting for each output channel pin */
+    uint32_t pin_mux;
 };
 
 /**
@@ -886,71 +886,71 @@ struct tc_pwm_channel {
  * modified by the user application.
  */
 struct tc_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
 
-	/** When \c true the module is enabled during standby */
-	bool run_in_standby;
+    /** When \c true the module is enabled during standby */
+    bool run_in_standby;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	/** Run on demand */
-	bool on_demand;
+    /** Run on demand */
+    bool on_demand;
 #endif
-	/** Specifies either 8-, 16-, or 32-bit counter size */
-	enum tc_counter_size counter_size;
-	/** Specifies the prescaler value for GCLK_TC */
-	enum tc_clock_prescaler clock_prescaler;
-	/** Specifies which waveform generation mode to use */
-	enum tc_wave_generation wave_generation;
-
-	/** Specifies the reload or reset time of the counter and prescaler
-	 *  resynchronization on a re-trigger event for the TC
-	 */
-	enum tc_reload_action reload_action;
-
-	/** Specifies which channel(s) to invert the waveform on.
-		For SAM L21/L22/C20/C21, it's also used to invert I/O input pin. */
-	uint8_t waveform_invert_output;
-
-	/** Specifies which channel(s) to enable channel capture
-	 *  operation on
-	 */
-	bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
-#ifdef 	FEATURE_TC_IO_CAPTURE
-	/** Specifies which channel(s) to enable I/O capture
-	 *  operation on
-	 */
-	bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Specifies either 8-, 16-, or 32-bit counter size */
+    enum tc_counter_size counter_size;
+    /** Specifies the prescaler value for GCLK_TC */
+    enum tc_clock_prescaler clock_prescaler;
+    /** Specifies which waveform generation mode to use */
+    enum tc_wave_generation wave_generation;
+
+    /** Specifies the reload or reset time of the counter and prescaler
+     *  resynchronization on a re-trigger event for the TC
+     */
+    enum tc_reload_action reload_action;
+
+    /** Specifies which channel(s) to invert the waveform on.
+        For SAM L21/L22/C20/C21, it's also used to invert I/O input pin. */
+    uint8_t waveform_invert_output;
+
+    /** Specifies which channel(s) to enable channel capture
+     *  operation on
+     */
+    bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+#ifdef  FEATURE_TC_IO_CAPTURE
+    /** Specifies which channel(s) to enable I/O capture
+     *  operation on
+     */
+    bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
 #endif
 
-	/** When \c true, one-shot will stop the TC on next hardware or software
-	 *  re-trigger event or overflow/underflow
-	 */
-	bool oneshot;
+    /** When \c true, one-shot will stop the TC on next hardware or software
+     *  re-trigger event or overflow/underflow
+     */
+    bool oneshot;
 
-	/** Specifies the direction for the TC to count */
-	enum tc_count_direction count_direction;
+    /** Specifies the direction for the TC to count */
+    enum tc_count_direction count_direction;
 
-	/** Specifies the PWM channel for TC */
-	struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
+    /** Specifies the PWM channel for TC */
+    struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS];
 
-	/** Access the different counter size settings through this configuration member. */
-	union {
-		/** Struct for 8-bit specific timer configuration */
-		struct tc_8bit_config counter_8_bit;
-		/** Struct for 16-bit specific timer configuration */
-		struct tc_16bit_config counter_16_bit;
-		/** Struct for 32-bit specific timer configuration */
-		struct tc_32bit_config counter_32_bit;
-	};
+    /** Access the different counter size settings through this configuration member. */
+    union {
+        /** Struct for 8-bit specific timer configuration */
+        struct tc_8bit_config counter_8_bit;
+        /** Struct for 16-bit specific timer configuration */
+        struct tc_16bit_config counter_16_bit;
+        /** Struct for 32-bit specific timer configuration */
+        struct tc_32bit_config counter_32_bit;
+    };
 
 #ifdef FEATURE_TC_DOUBLE_BUFFERED
-	/** Set to \c true to enable double buffering write. When enabled any write
-	 *  through \ref tc_set_top_value(), \ref tc_set_compare_value() and
-	 *  will direct to the buffer register as buffered
-	 *  value, and the buffered value will be committed to effective register
-	 *  on UPDATE condition, if update is not locked.
-	 */
-	bool double_buffering_enabled;
+    /** Set to \c true to enable double buffering write. When enabled any write
+     *  through \ref tc_set_top_value(), \ref tc_set_compare_value() and
+     *  will direct to the buffer register as buffered
+     *  value, and the buffered value will be committed to effective register
+     *  on UPDATE condition, if update is not locked.
+     */
+    bool double_buffering_enabled;
 #endif
 };
 
@@ -973,29 +973,29 @@ typedef void (*tc_callback_t)(struct tc_module *const module);
  */
 struct tc_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware module pointer of the associated Timer/Counter peripheral */
-	Tc *hw;
+    /** Hardware module pointer of the associated Timer/Counter peripheral */
+    Tc *hw;
 
-	/** Size of the initialized Timer/Counter module configuration */
-	enum tc_counter_size counter_size;
+    /** Size of the initialized Timer/Counter module configuration */
+    enum tc_counter_size counter_size;
 #  if TC_ASYNC == true
-	/** Array of callbacks */
-	tc_callback_t callback[TC_CALLBACK_N];
-	/** Bit mask for callbacks registered */
-	uint8_t register_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enable_callback_mask;
+    /** Array of callbacks */
+    tc_callback_t callback[TC_CALLBACK_N];
+    /** Bit mask for callbacks registered */
+    uint8_t register_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enable_callback_mask;
 #  endif
 #ifdef FEATURE_TC_DOUBLE_BUFFERED
-	/** Set to \c true to enable double buffering write */
-	bool double_buffering_enabled;
+    /** Set to \c true to enable double buffering write */
+    bool double_buffering_enabled;
 #endif
 #endif
 };
 
 #if !defined(__DOXYGEN__)
 uint8_t _tc_get_inst_index(
-		Tc *const hw);
+        Tc *const hw);
 #endif
 
 /**
@@ -1021,19 +1021,19 @@ uint8_t _tc_get_inst_index(
  * \retval true  If the module synchronization is ongoing
  */
 static inline bool tc_is_syncing(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	return (tc_module->SYNCBUSY.reg);
+    return (tc_module->SYNCBUSY.reg);
 #else
-	return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY);
+    return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY);
 #endif
 }
 
@@ -1072,55 +1072,55 @@ static inline bool tc_is_syncing(
  * \param[out]  config  Pointer to a TC module configuration structure to set
  */
 static inline void tc_get_config_defaults(
-		struct tc_config *const config)
+        struct tc_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	/* Write default config to config struct */
-	config->clock_source               = GCLK_GENERATOR_0;
-	config->counter_size               = TC_COUNTER_SIZE_16BIT;
-	config->clock_prescaler            = TC_CLOCK_PRESCALER_DIV1;
-	config->wave_generation            = TC_WAVE_GENERATION_NORMAL_FREQ;
-	config->reload_action              = TC_RELOAD_ACTION_GCLK;
-	config->run_in_standby             = false;
+    /* Sanity check arguments */
+    Assert(config);
+
+    /* Write default config to config struct */
+    config->clock_source               = GCLK_GENERATOR_0;
+    config->counter_size               = TC_COUNTER_SIZE_16BIT;
+    config->clock_prescaler            = TC_CLOCK_PRESCALER_DIV1;
+    config->wave_generation            = TC_WAVE_GENERATION_NORMAL_FREQ;
+    config->reload_action              = TC_RELOAD_ACTION_GCLK;
+    config->run_in_standby             = false;
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	config->on_demand                  = false;
+    config->on_demand                  = false;
 #endif
-	config->waveform_invert_output     = TC_WAVEFORM_INVERT_OUTPUT_NONE;
-	config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
-	config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
-#ifdef 	FEATURE_TC_IO_CAPTURE
-	config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
-	config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+    config->waveform_invert_output     = TC_WAVEFORM_INVERT_OUTPUT_NONE;
+    config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+    config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
+#ifdef  FEATURE_TC_IO_CAPTURE
+    config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false;
+    config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false;
 #endif
 
-	config->count_direction            = TC_COUNT_DIRECTION_UP;
-	config->oneshot                    = false;
+    config->count_direction            = TC_COUNT_DIRECTION_UP;
+    config->oneshot                    = false;
 
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false;
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0;
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0;
 
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false;
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0;
-	config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0;
+    config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0;
 
-	config->counter_16_bit.value                   = 0x0000;
-	config->counter_16_bit.compare_capture_channel\
-		[TC_COMPARE_CAPTURE_CHANNEL_0]                        = 0x0000;
-	config->counter_16_bit.compare_capture_channel\
-		[TC_COMPARE_CAPTURE_CHANNEL_1]                        = 0x0000;
+    config->counter_16_bit.value                   = 0x0000;
+    config->counter_16_bit.compare_capture_channel\
+        [TC_COMPARE_CAPTURE_CHANNEL_0]                        = 0x0000;
+    config->counter_16_bit.compare_capture_channel\
+        [TC_COMPARE_CAPTURE_CHANNEL_1]                        = 0x0000;
 #ifdef FEATURE_TC_DOUBLE_BUFFERED
-	config->double_buffering_enabled = false;
+    config->double_buffering_enabled = false;
 #endif
 
 }
 
 enum status_code tc_init(
-		struct tc_module *const module_inst,
-		Tc *const hw,
-		const struct tc_config *const config);
+        struct tc_module *const module_inst,
+        Tc *const hw,
+        const struct tc_config *const config);
 
 /** @} */
 
@@ -1141,37 +1141,42 @@ enum status_code tc_init(
  * \param[in]  events       Struct containing flags of events to enable
  */
 static inline void tc_enable_events(
-		struct tc_module *const module_inst,
-		struct tc_events *const events)
+        struct tc_module *const module_inst,
+        struct tc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Tc *const tc_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	if (events->invert_event_input == true) {
-		event_mask |= TC_EVCTRL_TCINV;
-	}
-
-	if (events->on_event_perform_action == true) {
-		event_mask |= TC_EVCTRL_TCEI;
-	}
-
-	if (events->generate_event_on_overflow == true) {
-		event_mask |= TC_EVCTRL_OVFEO;
-	}
-
-	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
-		if (events->generate_event_on_compare_channel[i] == true) {
-			event_mask |= (TC_EVCTRL_MCEO(1) << i);
-		}
-	}
-
-	tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Tc *const tc_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    if (events->invert_event_input == true)
+    {
+        event_mask |= TC_EVCTRL_TCINV;
+    }
+
+    if (events->on_event_perform_action == true)
+    {
+        event_mask |= TC_EVCTRL_TCEI;
+    }
+
+    if (events->generate_event_on_overflow == true)
+    {
+        event_mask |= TC_EVCTRL_OVFEO;
+    }
+
+    for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++)
+    {
+        if (events->generate_event_on_compare_channel[i] == true)
+        {
+            event_mask |= (TC_EVCTRL_MCEO(1) << i);
+        }
+    }
+
+    tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action;
 }
 
 /**
@@ -1186,37 +1191,42 @@ static inline void tc_enable_events(
  * \param[in]  events       Struct containing flags of events to disable
  */
 static inline void tc_disable_events(
-		struct tc_module *const module_inst,
-		struct tc_events *const events)
+        struct tc_module *const module_inst,
+        struct tc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Tc *const tc_module = module_inst->hw;
-
-	uint32_t event_mask = 0;
-
-	if (events->invert_event_input == true) {
-		event_mask |= TC_EVCTRL_TCINV;
-	}
-
-	if (events->on_event_perform_action == true) {
-		event_mask |= TC_EVCTRL_TCEI;
-	}
-
-	if (events->generate_event_on_overflow == true) {
-		event_mask |= TC_EVCTRL_OVFEO;
-	}
-
-	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
-		if (events->generate_event_on_compare_channel[i] == true) {
-			event_mask |= (TC_EVCTRL_MCEO(1) << i);
-		}
-	}
-
-	tc_module->COUNT8.EVCTRL.reg &= ~event_mask;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Tc *const tc_module = module_inst->hw;
+
+    uint32_t event_mask = 0;
+
+    if (events->invert_event_input == true)
+    {
+        event_mask |= TC_EVCTRL_TCINV;
+    }
+
+    if (events->on_event_perform_action == true)
+    {
+        event_mask |= TC_EVCTRL_TCEI;
+    }
+
+    if (events->generate_event_on_overflow == true)
+    {
+        event_mask |= TC_EVCTRL_OVFEO;
+    }
+
+    for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++)
+    {
+        if (events->generate_event_on_compare_channel[i] == true)
+        {
+            event_mask |= (TC_EVCTRL_MCEO(1) << i);
+        }
+    }
+
+    tc_module->COUNT8.EVCTRL.reg &= ~event_mask;
 }
 
 /** @} */
@@ -1227,7 +1237,7 @@ static inline void tc_disable_events(
  */
 
 enum status_code tc_reset(
-		const struct tc_module *const module_inst);
+        const struct tc_module *const module_inst);
 
 /**
  * \brief Enable the TC module.
@@ -1241,21 +1251,22 @@ enum status_code tc_reset(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_enable(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Enable TC module */
-	tc_module->CTRLA.reg |= TC_CTRLA_ENABLE;
+    /* Enable TC module */
+    tc_module->CTRLA.reg |= TC_CTRLA_ENABLE;
 }
 
 /**
@@ -1266,26 +1277,27 @@ static inline void tc_enable(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_disable(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Disbale interrupt */
-	tc_module->INTENCLR.reg = TC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	tc_module->INTFLAG.reg = TC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    tc_module->INTENCLR.reg = TC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    tc_module->INTFLAG.reg = TC_INTFLAG_MASK;
 
-	/* Disable TC module */
-	tc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
+    /* Disable TC module */
+    tc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
 }
 
 /** @} */
@@ -1296,11 +1308,11 @@ static inline void tc_disable(
  */
 
 uint32_t tc_get_count_value(
-		const struct tc_module *const module_inst);
+        const struct tc_module *const module_inst);
 
 enum status_code tc_set_count_value(
-		const struct tc_module *const module_inst,
-		const uint32_t count);
+        const struct tc_module *const module_inst,
+        const uint32_t count);
 
 /** @} */
 
@@ -1320,21 +1332,22 @@ enum status_code tc_set_count_value(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_stop_counter(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Write command to execute */
-	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val);
+    /* Write command to execute */
+    tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val);
 }
 
 /**
@@ -1345,28 +1358,30 @@ static inline void tc_stop_counter(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_start_counter(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Make certain that there are no conflicting commands in the register */
-	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+    /* Make certain that there are no conflicting commands in the register */
+    tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Write command to execute */
-	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val);
+    /* Write command to execute */
+    tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val);
 }
 
 /** @} */
@@ -1385,28 +1400,30 @@ static inline void tc_start_counter(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_update_double_buffer(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Make certain that there are no conflicting commands in the register */
-	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+    /* Make certain that there are no conflicting commands in the register */
+    tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Write command to execute */
-	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val);
+    /* Write command to execute */
+    tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val);
 }
 /** @} */
 #endif
@@ -1425,28 +1442,30 @@ static inline void tc_update_double_buffer(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_sync_read_count(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Make certain that there are no conflicting commands in the register */
-	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+    /* Make certain that there are no conflicting commands in the register */
+    tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Write command to execute */
-	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val);
+    /* Write command to execute */
+    tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val);
 }
 /** @} */
 #endif
@@ -1465,29 +1484,31 @@ static inline void tc_sync_read_count(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tc_dma_trigger_command(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Make certain that there are no conflicting commands in the register */
-	tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
+    /* Make certain that there are no conflicting commands in the register */
+    tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE;
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
 #if (SAMC20) || (SAMC21) || (SAML22) || (SAML21XXXB) || (SAMR30)
-	/* Write command to execute */
-	tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val);
+    /* Write command to execute */
+    tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val);
 #endif
 }
 /** @} */
@@ -1499,13 +1520,13 @@ static inline void tc_dma_trigger_command(
  */
 
 uint32_t tc_get_capture_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index);
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index);
 
 enum status_code tc_set_compare_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index,
-		const uint32_t compare_value);
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index,
+        const uint32_t compare_value);
 
 /** @} */
 
@@ -1515,8 +1536,8 @@ enum status_code tc_set_compare_value(
  */
 
 enum status_code tc_set_top_value(
-		const struct tc_module *const module_inst,
-		const uint32_t top_value);
+        const struct tc_module *const module_inst,
+        const uint32_t top_value);
 
 /** @} */
 
@@ -1544,63 +1565,71 @@ enum status_code tc_set_top_value(
  * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid
  */
 static inline uint32_t tc_get_status(
-		struct tc_module *const module_inst)
+        struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	uint32_t int_flags = tc_module->INTFLAG.reg;
+    uint32_t int_flags = tc_module->INTFLAG.reg;
 
-	uint32_t status_flags = 0;
+    uint32_t status_flags = 0;
 
-	/* Check for TC channel 0 match */
-	if (int_flags & TC_INTFLAG_MC(1)) {
-		status_flags |= TC_STATUS_CHANNEL_0_MATCH;
-	}
+    /* Check for TC channel 0 match */
+    if (int_flags & TC_INTFLAG_MC(1))
+    {
+        status_flags |= TC_STATUS_CHANNEL_0_MATCH;
+    }
 
-	/* Check for TC channel 1 match */
-	if (int_flags & TC_INTFLAG_MC(2)) {
-		status_flags |= TC_STATUS_CHANNEL_1_MATCH;
-	}
+    /* Check for TC channel 1 match */
+    if (int_flags & TC_INTFLAG_MC(2))
+    {
+        status_flags |= TC_STATUS_CHANNEL_1_MATCH;
+    }
 
 #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
-	/* Check for TC read synchronization ready */
-	if (int_flags & TC_INTFLAG_SYNCRDY) {
-		status_flags |= TC_STATUS_SYNC_READY;
-	}
+    /* Check for TC read synchronization ready */
+    if (int_flags & TC_INTFLAG_SYNCRDY)
+    {
+        status_flags |= TC_STATUS_SYNC_READY;
+    }
 #endif
 
-	/* Check for TC capture overflow */
-	if (int_flags & TC_INTFLAG_ERR) {
-		status_flags |= TC_STATUS_CAPTURE_OVERFLOW;
-	}
-
-	/* Check for TC count overflow */
-	if (int_flags & TC_INTFLAG_OVF) {
-		status_flags |= TC_STATUS_COUNT_OVERFLOW;
-	}
+    /* Check for TC capture overflow */
+    if (int_flags & TC_INTFLAG_ERR)
+    {
+        status_flags |= TC_STATUS_CAPTURE_OVERFLOW;
+    }
+
+    /* Check for TC count overflow */
+    if (int_flags & TC_INTFLAG_OVF)
+    {
+        status_flags |= TC_STATUS_COUNT_OVERFLOW;
+    }
 #ifdef FEATURE_TC_DOUBLE_BUFFERED
-	uint8_t double_buffer_valid_status = tc_module->STATUS.reg;
-
-	/* Check channel 0 compare or capture buffer valid */
-	if (double_buffer_valid_status & TC_STATUS_CCBUFV0) {
-		status_flags |= TC_STATUS_CHN0_BUFFER_VALID;
-	}
-	/* Check channel 0 compare or capture buffer valid */
-	if (double_buffer_valid_status & TC_STATUS_CCBUFV1) {
-		status_flags |= TC_STATUS_CHN1_BUFFER_VALID;
-	}
-	/* Check period buffer valid */
-	if (double_buffer_valid_status & TC_STATUS_PERBUFV) {
-		status_flags |= TC_STATUS_PERIOD_BUFFER_VALID;
-	}
+    uint8_t double_buffer_valid_status = tc_module->STATUS.reg;
+
+    /* Check channel 0 compare or capture buffer valid */
+    if (double_buffer_valid_status & TC_STATUS_CCBUFV0)
+    {
+        status_flags |= TC_STATUS_CHN0_BUFFER_VALID;
+    }
+    /* Check channel 0 compare or capture buffer valid */
+    if (double_buffer_valid_status & TC_STATUS_CCBUFV1)
+    {
+        status_flags |= TC_STATUS_CHN1_BUFFER_VALID;
+    }
+    /* Check period buffer valid */
+    if (double_buffer_valid_status & TC_STATUS_PERBUFV)
+    {
+        status_flags |= TC_STATUS_PERIOD_BUFFER_VALID;
+    }
 #endif
 
-	return status_flags;
+    return status_flags;
 }
 
 /**
@@ -1612,47 +1641,52 @@ static inline uint32_t tc_get_status(
  * \param[in] status_flags  Bitmask of \c TC_STATUS_* flags to clear
  */
 static inline void tc_clear_status(
-		struct tc_module *const module_inst,
-		const uint32_t status_flags)
+        struct tc_module *const module_inst,
+        const uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+    /* Get a pointer to the module's hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
 
-	uint32_t int_flags = 0;
+    uint32_t int_flags = 0;
 
-	/* Check for TC channel 0 match */
-	if (status_flags & TC_STATUS_CHANNEL_0_MATCH) {
-		int_flags |= TC_INTFLAG_MC(1);
-	}
+    /* Check for TC channel 0 match */
+    if (status_flags & TC_STATUS_CHANNEL_0_MATCH)
+    {
+        int_flags |= TC_INTFLAG_MC(1);
+    }
 
-	/* Check for TC channel 1 match */
-	if (status_flags & TC_STATUS_CHANNEL_1_MATCH) {
-		int_flags |= TC_INTFLAG_MC(2);
-	}
+    /* Check for TC channel 1 match */
+    if (status_flags & TC_STATUS_CHANNEL_1_MATCH)
+    {
+        int_flags |= TC_INTFLAG_MC(2);
+    }
 
 #if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2)
-	/* Check for TC read synchronization ready */
-	if (status_flags & TC_STATUS_SYNC_READY) {
-		int_flags |= TC_INTFLAG_SYNCRDY;
-	}
+    /* Check for TC read synchronization ready */
+    if (status_flags & TC_STATUS_SYNC_READY)
+    {
+        int_flags |= TC_INTFLAG_SYNCRDY;
+    }
 #endif
 
-	/* Check for TC capture overflow */
-	if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) {
-		int_flags |= TC_INTFLAG_ERR;
-	}
+    /* Check for TC capture overflow */
+    if (status_flags & TC_STATUS_CAPTURE_OVERFLOW)
+    {
+        int_flags |= TC_INTFLAG_ERR;
+    }
 
-	/* Check for TC count overflow */
-	if (status_flags & TC_STATUS_COUNT_OVERFLOW) {
-		int_flags |= TC_INTFLAG_OVF;
-	}
+    /* Check for TC count overflow */
+    if (status_flags & TC_STATUS_COUNT_OVERFLOW)
+    {
+        int_flags |= TC_INTFLAG_OVF;
+    }
 
-	/* Clear interrupt flag */
-	tc_module->INTFLAG.reg = int_flags;
+    /* Clear interrupt flag */
+    tc_module->INTFLAG.reg = int_flags;
 }
 
 /** @} */
@@ -1670,30 +1704,30 @@ static inline void tc_clear_status(
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
-  *	<tr>
- *		<td>DMA</td>
- *		<td>Direct Memory Access</td>
- *	</tr>
- *	<tr>
- *		<td>TC</td>
- *		<td>Timer Counter</td>
- *	</tr>
- *	<tr>
- *		<td>PWM</td>
- *		<td>Pulse Width Modulation</td>
- *	</tr>
- *	<tr>
- *		<td>PWP</td>
- *		<td>Pulse Width Period</td>
- *	</tr>
- *	<tr>
- *		<td>PPW</td>
- *		<td>Period Pulse Width</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+  * <tr>
+ *      <td>DMA</td>
+ *      <td>Direct Memory Access</td>
+ *  </tr>
+ *  <tr>
+ *      <td>TC</td>
+ *      <td>Timer Counter</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PWM</td>
+ *      <td>Pulse Width Modulation</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PWP</td>
+ *      <td>Pulse Width Period</td>
+ *  </tr>
+ *  <tr>
+ *      <td>PPW</td>
+ *      <td>Period Pulse Width</td>
+ *  </tr>
  * </table>
  *
  *
@@ -1714,23 +1748,23 @@ static inline void tc_clear_status(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
  *    <td>Added support for SAM D21 and do some modifications as below:
  *          \li Clean up in the configuration structure, the counter size
  *              setting specific registers is accessed through the counter_8_bit,
  *              counter_16_bit, and counter_32_bit structures
  *          \li All event related settings moved into the tc_event structure </td>
- *	</tr>
- *	<tr>
- *		<td>Added automatic digital clock interface enable for the slave TC
+ *  </tr>
+ *  <tr>
+ *      <td>Added automatic digital clock interface enable for the slave TC
  *          module when a timer is initialized in 32-bit mode</td>
- *	</tr>
- *	<tr>
- *		<td>Initial release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
@@ -1754,37 +1788,37 @@ static inline void tc_clear_status(
  * \page asfdoc_sam0_tc_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42123E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
- *	</tr>
- *	<tr>
- *		<td>42123D</td>
- *		<td>12/2014</td>
- *		<td>Added timer use case.
- *		    Added support for SAM R21 and SAM D10/D11</td>
- *	</tr>
- *	<tr>
- *		<td>42123C</td>
- *		<td>01/2014</td>
- *		<td>Added support for SAM D21</td>
- *	</tr>
- *	<tr>
- *		<td>42123B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42123A</td>
- *		<td>06/2013</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42123E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42123D</td>
+ *      <td>12/2014</td>
+ *      <td>Added timer use case.
+ *          Added support for SAM R21 and SAM D10/D11</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42123C</td>
+ *      <td>01/2014</td>
+ *      <td>Added support for SAM D21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42123B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42123A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c
index 3a5cf7e45ab7..8b8507d98d6f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.c
@@ -65,28 +65,30 @@ void _tc_interrupt_handler(uint8_t instance);
  * \param[in]     callback_type Callback type given by an enum
  */
 enum status_code tc_register_callback(
-		struct tc_module *const module,
-		tc_callback_t callback_func,
-		const enum tc_callback callback_type)
+        struct tc_module *const module,
+        tc_callback_t callback_func,
+        const enum tc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
-
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-
-	/* Set the bit corresponding to the callback_type */
-	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
-		module->register_callback_mask |= TC_INTFLAG_MC(1);
-	}
-	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
-		module->register_callback_mask |= TC_INTFLAG_MC(2);
-	}
-	else {
-		module->register_callback_mask |= (1 << callback_type);
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
+
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
+
+    /* Set the bit corresponding to the callback_type */
+    if (callback_type == TC_CALLBACK_CC_CHANNEL0)
+    {
+        module->register_callback_mask |= TC_INTFLAG_MC(1);
+    }
+    else if (callback_type == TC_CALLBACK_CC_CHANNEL1)
+    {
+        module->register_callback_mask |= TC_INTFLAG_MC(2);
+    }
+    else {
+        module->register_callback_mask |= (1 << callback_type);
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -99,26 +101,28 @@ enum status_code tc_register_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 enum status_code tc_unregister_callback(
-		struct tc_module *const module,
-		const enum tc_callback callback_type)
+        struct tc_module *const module,
+        const enum tc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
-
-	/* Clear the bit corresponding to the callback_type */
-	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
-		module->register_callback_mask &= ~TC_INTFLAG_MC(1);
-	}
-	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
-		module->register_callback_mask &= ~TC_INTFLAG_MC(2);
-	}
-	else {
-		module->register_callback_mask &= ~(1 << callback_type);
-	}
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
+
+    /* Clear the bit corresponding to the callback_type */
+    if (callback_type == TC_CALLBACK_CC_CHANNEL0)
+    {
+        module->register_callback_mask &= ~TC_INTFLAG_MC(1);
+    }
+    else if (callback_type == TC_CALLBACK_CC_CHANNEL1)
+    {
+        module->register_callback_mask &= ~TC_INTFLAG_MC(2);
+    }
+    else {
+        module->register_callback_mask &= ~(1 << callback_type);
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -127,17 +131,17 @@ enum status_code tc_unregister_callback(
  * Auto-generate a set of interrupt handlers for each TC in the device.
  */
 #define _TC_INTERRUPT_HANDLER(n, m) \
-		void TC##n##_Handler(void) \
-		{ \
-			_tc_interrupt_handler(m); \
-		}
+        void TC##n##_Handler(void) \
+        { \
+            _tc_interrupt_handler(m); \
+        }
 
 #if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
-	_TC_INTERRUPT_HANDLER(0,0)
-	_TC_INTERRUPT_HANDLER(1,1)
-	_TC_INTERRUPT_HANDLER(4,2)
+    _TC_INTERRUPT_HANDLER(0,0)
+    _TC_INTERRUPT_HANDLER(1,1)
+    _TC_INTERRUPT_HANDLER(4,2)
 #else
-	MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID)
+    MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID)
 #endif
 
 
@@ -151,49 +155,53 @@ enum status_code tc_unregister_callback(
  *                       handler
  */
 void _tc_interrupt_handler(
-		uint8_t instance)
+        uint8_t instance)
 {
-	/* Temporary variable */
-	uint8_t interrupt_and_callback_status_mask;
-
-	/* Get device instance from the look-up table */
-	struct tc_module *module
-			= (struct tc_module *)_tc_instances[instance];
-
-	/* Read and mask interrupt flag register */
-	interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg &
-			module->register_callback_mask &
-			module->enable_callback_mask;
-
-	/* Check if an Overflow interrupt has occurred */
-	if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[TC_CALLBACK_OVERFLOW])(module);
-		/* Clear interrupt flag */
-		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
-	}
-
-	/* Check if an Error interrupt has occurred */
-	if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[TC_CALLBACK_ERROR])(module);
-		/* Clear interrupt flag */
-		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
-	}
-
-	/* Check if an Match/Capture Channel 0 interrupt has occurred */
-	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[TC_CALLBACK_CC_CHANNEL0])(module);
-		/* Clear interrupt flag */
-		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1);
-	}
-
-	/* Check if an Match/Capture Channel 1 interrupt has occurred */
-	if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) {
-		/* Invoke registered and enabled callback function */
-		(module->callback[TC_CALLBACK_CC_CHANNEL1])(module);
-		/* Clear interrupt flag */
-		module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2);
-	}
+    /* Temporary variable */
+    uint8_t interrupt_and_callback_status_mask;
+
+    /* Get device instance from the look-up table */
+    struct tc_module *module
+            = (struct tc_module *)_tc_instances[instance];
+
+    /* Read and mask interrupt flag register */
+    interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg &
+            module->register_callback_mask &
+            module->enable_callback_mask;
+
+    /* Check if an Overflow interrupt has occurred */
+    if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[TC_CALLBACK_OVERFLOW])(module);
+        /* Clear interrupt flag */
+        module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF;
+    }
+
+    /* Check if an Error interrupt has occurred */
+    if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR)
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[TC_CALLBACK_ERROR])(module);
+        /* Clear interrupt flag */
+        module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR;
+    }
+
+    /* Check if an Match/Capture Channel 0 interrupt has occurred */
+    if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1))
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[TC_CALLBACK_CC_CHANNEL0])(module);
+        /* Clear interrupt flag */
+        module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1);
+    }
+
+    /* Check if an Match/Capture Channel 1 interrupt has occurred */
+    if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2))
+    {
+        /* Invoke registered and enabled callback function */
+        (module->callback[TC_CALLBACK_CC_CHANNEL1])(module);
+        /* Clear interrupt flag */
+        module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2);
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h
index 56c7264ad785..3959dc9c18a9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_interrupt.h
@@ -59,7 +59,7 @@ extern "C" {
 extern void *_tc_instances[TC_INST_NUM];
 
 #  define _TC_INTERRUPT_VECT_NUM(n, unused) \
-		  SYSTEM_INTERRUPT_MODULE_TC##n,
+          SYSTEM_INTERRUPT_MODULE_TC##n,
 /**
  * \internal Get the interrupt vector for the given device instance
  *
@@ -68,20 +68,20 @@ extern void *_tc_instances[TC_INST_NUM];
  * \return Interrupt vector for of the given TC module instance.
  */
 static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector(
-		uint32_t inst_num)
+        uint32_t inst_num)
 {
-	static uint8_t tc_interrupt_vectors[TC_INST_NUM] =
-		{
+    static uint8_t tc_interrupt_vectors[TC_INST_NUM] =
+        {
 #if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G)
-			SYSTEM_INTERRUPT_MODULE_TC0,
-			SYSTEM_INTERRUPT_MODULE_TC1,
-			SYSTEM_INTERRUPT_MODULE_TC4
+            SYSTEM_INTERRUPT_MODULE_TC0,
+            SYSTEM_INTERRUPT_MODULE_TC1,
+            SYSTEM_INTERRUPT_MODULE_TC4
 #else
-			MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID)
+            MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID)
 #endif
-		};
+        };
 
-	return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num];
+    return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num];
 }
 #endif /* !defined(__DOXYGEN__) */
 
@@ -91,13 +91,13 @@ static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector(
  */
 
 enum status_code tc_register_callback(
-		struct tc_module *const module,
-		tc_callback_t callback_func,
-		const enum tc_callback callback_type);
+        struct tc_module *const module,
+        tc_callback_t callback_func,
+        const enum tc_callback callback_type);
 
 enum status_code tc_unregister_callback(
-		struct tc_module *const module,
-		const enum tc_callback callback_type);
+        struct tc_module *const module,
+        const enum tc_callback callback_type);
 
 /**
  * \brief Enables callback.
@@ -111,29 +111,31 @@ enum status_code tc_unregister_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void tc_enable_callback(
-		struct tc_module *const module,
-		const enum tc_callback callback_type)
+        struct tc_module *const module,
+        const enum tc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-
-	/* Enable interrupts for this TC module */
-	system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw)));
-
-	/* Enable callback */
-	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
-		module->enable_callback_mask |= TC_INTFLAG_MC(1);
-		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1);
-	}
-	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
-		module->enable_callback_mask |= TC_INTFLAG_MC(2);
-		module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2);
-	}
-	else {
-		module->enable_callback_mask |= (1 << callback_type);
-		module->hw->COUNT8.INTENSET.reg = (1 << callback_type);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+
+    /* Enable interrupts for this TC module */
+    system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw)));
+
+    /* Enable callback */
+    if (callback_type == TC_CALLBACK_CC_CHANNEL0)
+    {
+        module->enable_callback_mask |= TC_INTFLAG_MC(1);
+        module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1);
+    }
+    else if (callback_type == TC_CALLBACK_CC_CHANNEL1)
+    {
+        module->enable_callback_mask |= TC_INTFLAG_MC(2);
+        module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2);
+    }
+    else {
+        module->enable_callback_mask |= (1 << callback_type);
+        module->hw->COUNT8.INTENSET.reg = (1 << callback_type);
+    }
 }
 
 /**
@@ -148,24 +150,27 @@ static inline void tc_enable_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void tc_disable_callback(
-		struct tc_module *const module,
-		const enum tc_callback callback_type){
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* Disable callback */
-	if (callback_type == TC_CALLBACK_CC_CHANNEL0) {
-		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
-		module->enable_callback_mask &= ~TC_INTFLAG_MC(1);
-	}
-	else if (callback_type == TC_CALLBACK_CC_CHANNEL1) {
-		module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
-		module->enable_callback_mask &= ~TC_INTFLAG_MC(2);
-	}
-	else {
-		module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
-		module->enable_callback_mask &= ~(1 << callback_type);
-	}
+        struct tc_module *const module,
+        const enum tc_callback callback_type)
+        {
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* Disable callback */
+    if (callback_type == TC_CALLBACK_CC_CHANNEL0)
+    {
+        module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1);
+        module->enable_callback_mask &= ~TC_INTFLAG_MC(1);
+    }
+    else if (callback_type == TC_CALLBACK_CC_CHANNEL1)
+    {
+        module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2);
+        module->enable_callback_mask &= ~TC_INTFLAG_MC(2);
+    }
+    else {
+        module->hw->COUNT8.INTENCLR.reg = (1 << callback_type);
+        module->enable_callback_mask &= ~(1 << callback_type);
+    }
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c
index 19e721574ac5..0d497e50316a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_d_r_h/tc.c
@@ -54,7 +54,7 @@
  * Converts a given TC index to its interrupt vector index.
  */
 #  define _TC_INTERRUPT_VECT_NUM(n, unused) \
-		SYSTEM_INTERRUPT_MODULE_TC##n,
+        SYSTEM_INTERRUPT_MODULE_TC##n,
 #endif
 
 #if !defined(__DOXYGEN__)
@@ -74,21 +74,23 @@
  * \return Index of the given TC module instance.
  */
 uint8_t _tc_get_inst_index(
-		Tc *const hw)
+        Tc *const hw)
 {
-	/* List of available TC modules. */
-	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
-
-	/* Find index for TC instance. */
-	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
-		if (hw == tc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given. */
-	Assert(false);
-	return 0;
+    /* List of available TC modules. */
+    Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+    /* Find index for TC instance. */
+    for (uint32_t i = 0; i < TC_INST_NUM; i++)
+    {
+        if (hw == tc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given. */
+    Assert(false);
+    return 0;
 }
 
 
@@ -114,273 +116,303 @@ uint8_t _tc_get_inst_index(
  *                             slave mode
  */
 enum status_code tc_init(
-		struct tc_module *const module_inst,
-		Tc *const hw,
-		const struct tc_config *const config)
+        struct tc_module *const module_inst,
+        Tc *const hw,
+        const struct tc_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(module_inst);
-	Assert(config);
-
-	/* Temporary variable to hold all updates to the CTRLA
-	 * register before they are written to it */
-	uint16_t ctrla_tmp = 0;
-	/* Temporary variable to hold all updates to the CTRLBSET
-	 * register before they are written to it */
-	uint8_t ctrlbset_tmp = 0;
-	/* Temporary variable to hold all updates to the CTRLC
-	 * register before they are written to it */
-	uint8_t ctrlc_tmp = 0;
-	/* Temporary variable to hold TC instance number */
-	uint8_t instance = _tc_get_inst_index(hw);
-
-	/* Array of GLCK ID for different TC instances */
-	uint8_t inst_gclk_id[] = TC_INST_GCLK_ID;
-	/* Array of PM APBC mask bit position for different TC instances */
-	uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK;
-
-	struct system_pinmux_config pin_config;
-	struct system_gclk_chan_config gclk_chan_config;
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(module_inst);
+    Assert(config);
+
+    /* Temporary variable to hold all updates to the CTRLA
+     * register before they are written to it */
+    uint16_t ctrla_tmp = 0;
+    /* Temporary variable to hold all updates to the CTRLBSET
+     * register before they are written to it */
+    uint8_t ctrlbset_tmp = 0;
+    /* Temporary variable to hold all updates to the CTRLC
+     * register before they are written to it */
+    uint8_t ctrlc_tmp = 0;
+    /* Temporary variable to hold TC instance number */
+    uint8_t instance = _tc_get_inst_index(hw);
+
+    /* Array of GLCK ID for different TC instances */
+    uint8_t inst_gclk_id[] = TC_INST_GCLK_ID;
+    /* Array of PM APBC mask bit position for different TC instances */
+    uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK;
+
+    struct system_pinmux_config pin_config;
+    struct system_gclk_chan_config gclk_chan_config;
 
 #if TC_ASYNC == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
-		module_inst->callback[i]        = NULL;
-	}
-	module_inst->register_callback_mask     = 0x00;
-	module_inst->enable_callback_mask       = 0x00;
-
-	/* Register this instance for callbacks*/
-	_tc_instances[instance] = module_inst;
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < TC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i]        = NULL;
+    }
+    module_inst->register_callback_mask     = 0x00;
+    module_inst->enable_callback_mask       = 0x00;
+
+    /* Register this instance for callbacks*/
+    _tc_instances[instance] = module_inst;
 #endif
 
-	/* Associate the given device instance with the hardware module */
-	module_inst->hw = hw;
+    /* Associate the given device instance with the hardware module */
+    module_inst->hw = hw;
 
 #if SAMD09 || SAMD10 || SAMD11 || SAMHA1
-	/* Check if even numbered TC modules are being configured in 32-bit
-	 * counter size. Only odd numbered counters are allowed to be
-	 * configured in 32-bit counter size.
-	 */
-	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
-			!((instance + TC_INSTANCE_OFFSET) & 0x01)) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if even numbered TC modules are being configured in 32-bit
+     * counter size. Only odd numbered counters are allowed to be
+     * configured in 32-bit counter size.
+     */
+    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+            !((instance + TC_INSTANCE_OFFSET) & 0x01))
+            {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 #else
-	/* Check if odd numbered TC modules are being configured in 32-bit
-	 * counter size. Only even numbered counters are allowed to be
-	 * configured in 32-bit counter size.
-	 */
-	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
-			((instance + TC_INSTANCE_OFFSET) & 0x01)) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check if odd numbered TC modules are being configured in 32-bit
+     * counter size. Only even numbered counters are allowed to be
+     * configured in 32-bit counter size.
+     */
+    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+            ((instance + TC_INSTANCE_OFFSET) & 0x01))
+            {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 #endif
 
-	/* Make the counter size variable in the module_inst struct reflect
-	 * the counter size in the module
-	 */
-	module_inst->counter_size = config->counter_size;
-
-	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
-
-	if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
-		/* Module is used as a slave */
-		return STATUS_ERR_DENIED;
-	}
-
-	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Set up the TC PWM out pin for channel 0 */
-	if (config->pwm_channel[0].enabled) {
-		system_pinmux_get_config_defaults(&pin_config);
-		pin_config.mux_position = config->pwm_channel[0].pin_mux;
-		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
-		system_pinmux_pin_set_config(
-				config->pwm_channel[0].pin_out, &pin_config);
-	}
-
-	/* Set up the TC PWM out pin for channel 1 */
-	if (config->pwm_channel[1].enabled) {
-		system_pinmux_get_config_defaults(&pin_config);
-		pin_config.mux_position = config->pwm_channel[1].pin_mux;
-		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
-		system_pinmux_pin_set_config(
-				config->pwm_channel[1].pin_out, &pin_config);
-	}
-
-	/* Enable the user interface clock in the PM */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
-			inst_pm_apbmask[instance]);
-
-	/* Enable the slave counter if counter_size is 32-bit */
-	if ((config->counter_size == TC_COUNTER_SIZE_32BIT))
-	{
-		/* Enable the user interface clock in the PM */
-		system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
-				inst_pm_apbmask[instance + 1]);
-	}
-
-	/* Setup clock for module */
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = config->clock_source;
-	system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
-	system_gclk_chan_enable(inst_gclk_id[instance]);
-
-	/* Set ctrla register */
-	ctrla_tmp =
-			(uint32_t)config->counter_size |
-			(uint32_t)config->wave_generation |
-			(uint32_t)config->reload_action |
-			(uint32_t)config->clock_prescaler;
-
-	if (config->run_in_standby) {
-		ctrla_tmp |= TC_CTRLA_RUNSTDBY;
-	}
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.CTRLA.reg = ctrla_tmp;
-
-	/* Set ctrlb register */
-	if (config->oneshot) {
-		ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
-	}
-
-	if (config->count_direction) {
-		ctrlbset_tmp |= TC_CTRLBSET_DIR;
-	}
-
-	/* Clear old ctrlb configuration */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.CTRLBCLR.reg = 0xFF;
-
-	/* Check if we actually need to go into a wait state. */
-	if (ctrlbset_tmp) {
-		while (tc_is_syncing(module_inst)) {
-			/* Wait for sync */
-		}
-		/* Write configuration to register */
-		hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
-	}
-
-	/* Set ctrlc register*/
-	ctrlc_tmp = config->waveform_invert_output;
-	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
-		if (config->enable_capture_on_channel[i] == true) {
-			ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i);
-		}
-	}
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.CTRLC.reg = ctrlc_tmp;
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Switch for TC counter size  */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.COUNT.reg =
-					config->counter_8_bit.value;
-
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.PER.reg =
-					config->counter_8_bit.period;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.CC[0].reg =
-					config->counter_8_bit.compare_capture_channel[0];
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.CC[1].reg =
-					config->counter_8_bit.compare_capture_channel[1];
-
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT16.COUNT.reg
-				= config->counter_16_bit.value;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT16.CC[0].reg =
-					config->counter_16_bit.compare_capture_channel[0];
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT16.CC[1].reg =
-					config->counter_16_bit.compare_capture_channel[1];
+    /* Make the counter size variable in the module_inst struct reflect
+     * the counter size in the module
+     */
+    module_inst->counter_size = config->counter_size;
+
+    if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
+
+    if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE)
+    {
+        /* Module is used as a slave */
+        return STATUS_ERR_DENIED;
+    }
+
+    if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Set up the TC PWM out pin for channel 0 */
+    if (config->pwm_channel[0].enabled)
+    {
+        system_pinmux_get_config_defaults(&pin_config);
+        pin_config.mux_position = config->pwm_channel[0].pin_mux;
+        pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+        system_pinmux_pin_set_config(
+                config->pwm_channel[0].pin_out, &pin_config);
+    }
+
+    /* Set up the TC PWM out pin for channel 1 */
+    if (config->pwm_channel[1].enabled)
+    {
+        system_pinmux_get_config_defaults(&pin_config);
+        pin_config.mux_position = config->pwm_channel[1].pin_mux;
+        pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+        system_pinmux_pin_set_config(
+                config->pwm_channel[1].pin_out, &pin_config);
+    }
+
+    /* Enable the user interface clock in the PM */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+            inst_pm_apbmask[instance]);
+
+    /* Enable the slave counter if counter_size is 32-bit */
+    if ((config->counter_size == TC_COUNTER_SIZE_32BIT))
+    {
+        /* Enable the user interface clock in the PM */
+        system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+                inst_pm_apbmask[instance + 1]);
+    }
+
+    /* Setup clock for module */
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = config->clock_source;
+    system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+    system_gclk_chan_enable(inst_gclk_id[instance]);
+
+    /* Set ctrla register */
+    ctrla_tmp =
+            (uint32_t)config->counter_size |
+            (uint32_t)config->wave_generation |
+            (uint32_t)config->reload_action |
+            (uint32_t)config->clock_prescaler;
+
+    if (config->run_in_standby)
+    {
+        ctrla_tmp |= TC_CTRLA_RUNSTDBY;
+    }
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+    /* Set ctrlb register */
+    if (config->oneshot)
+    {
+        ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+    }
+
+    if (config->count_direction)
+    {
+        ctrlbset_tmp |= TC_CTRLBSET_DIR;
+    }
+
+    /* Clear old ctrlb configuration */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+    /* Check if we actually need to go into a wait state. */
+    if (ctrlbset_tmp)
+    {
+        while (tc_is_syncing(module_inst))
+        {
+            /* Wait for sync */
+        }
+        /* Write configuration to register */
+        hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+    }
+
+    /* Set ctrlc register*/
+    ctrlc_tmp = config->waveform_invert_output;
+    for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++)
+    {
+        if (config->enable_capture_on_channel[i] == true)
+        {
+            ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i);
+        }
+    }
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.CTRLC.reg = ctrlc_tmp;
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Switch for TC counter size  */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.COUNT.reg =
+                    config->counter_8_bit.value;
+
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.PER.reg =
+                    config->counter_8_bit.period;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.CC[0].reg =
+                    config->counter_8_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.CC[1].reg =
+                    config->counter_8_bit.compare_capture_channel[1];
+
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.COUNT.reg
+                = config->counter_16_bit.value;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.CC[0].reg =
+                    config->counter_16_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.CC[1].reg =
+                    config->counter_16_bit.compare_capture_channel[1];
+
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT32.COUNT.reg
+                = config->counter_32_bit.value;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT32.CC[0].reg =
+                    config->counter_32_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT32.CC[1].reg =
+                    config->counter_32_bit.compare_capture_channel[1];
 
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
+            return STATUS_OK;
+    }
 
-			hw->COUNT32.COUNT.reg
-				= config->counter_32_bit.value;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT32.CC[0].reg =
-					config->counter_32_bit.compare_capture_channel[0];
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT32.CC[1].reg =
-					config->counter_32_bit.compare_capture_channel[1];
-
-			return STATUS_OK;
-	}
-
-	Assert(false);
-	return STATUS_ERR_INVALID_ARG;
+    Assert(false);
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -398,37 +430,39 @@ enum status_code tc_init(
  * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
  */
 enum status_code tc_set_count_value(
-		const struct tc_module *const module_inst,
-		const uint32_t count)
+        const struct tc_module *const module_inst,
+        const uint32_t count)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance*/
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Write to based on the TC counter_size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			tc_module->COUNT16.COUNT.reg = (uint16_t)count;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			tc_module->COUNT32.COUNT.reg = (uint32_t)count;
-			return STATUS_OK;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance*/
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Write to based on the TC counter_size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+            return STATUS_OK;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -442,33 +476,35 @@ enum status_code tc_set_count_value(
  * \return Count value of the specified TC module.
  */
 uint32_t tc_get_count_value(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
 
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
 
-	/* Read from based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			return (uint32_t)tc_module->COUNT8.COUNT.reg;
+    /* Read from based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            return (uint32_t)tc_module->COUNT8.COUNT.reg;
 
-		case TC_COUNTER_SIZE_16BIT:
-			return (uint32_t)tc_module->COUNT16.COUNT.reg;
+        case TC_COUNTER_SIZE_16BIT:
+            return (uint32_t)tc_module->COUNT16.COUNT.reg;
 
-		case TC_COUNTER_SIZE_32BIT:
-			return tc_module->COUNT32.COUNT.reg;
-	}
+        case TC_COUNTER_SIZE_32BIT:
+            return tc_module->COUNT32.COUNT.reg;
+    }
 
-	Assert(false);
-	return 0;
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -482,43 +518,48 @@ uint32_t tc_get_count_value(
  * \return Capture value stored in the specified timer channel.
  */
 uint32_t tc_get_capture_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index)
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Read out based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT8.CC[channel_index].reg;
-			}
-
-		case TC_COUNTER_SIZE_16BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT16.CC[channel_index].reg;
-			}
-
-		case TC_COUNTER_SIZE_32BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT32.CC[channel_index].reg;
-			}
-	}
-
-	Assert(false);
-	return 0;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Read out based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT8.CC[channel_index].reg;
+            }
+
+        case TC_COUNTER_SIZE_16BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT16.CC[channel_index].reg;
+            }
+
+        case TC_COUNTER_SIZE_32BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT32.CC[channel_index].reg;
+            }
+    }
+
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -536,49 +577,54 @@ uint32_t tc_get_capture_value(
  * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied
  */
 enum status_code tc_set_compare_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index,
-		const uint32_t compare)
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index,
+        const uint32_t compare)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Read out based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				tc_module->COUNT8.CC[channel_index].reg  =
-						(uint8_t)compare;
-				return STATUS_OK;
-			}
-
-		case TC_COUNTER_SIZE_16BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				tc_module->COUNT16.CC[channel_index].reg =
-						(uint16_t)compare;
-				return STATUS_OK;
-			}
-
-		case TC_COUNTER_SIZE_32BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				tc_module->COUNT32.CC[channel_index].reg =
-						(uint32_t)compare;
-				return STATUS_OK;
-			}
-	}
-
-	return STATUS_ERR_INVALID_ARG;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Read out based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                tc_module->COUNT8.CC[channel_index].reg  =
+                        (uint8_t)compare;
+                return STATUS_OK;
+            }
+
+        case TC_COUNTER_SIZE_16BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                tc_module->COUNT16.CC[channel_index].reg =
+                        (uint16_t)compare;
+                return STATUS_OK;
+            }
+
+        case TC_COUNTER_SIZE_32BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                tc_module->COUNT32.CC[channel_index].reg =
+                        (uint32_t)compare;
+                return STATUS_OK;
+            }
+    }
+
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -600,31 +646,34 @@ enum status_code tc_set_compare_value(
  *                                     TC
  */
 enum status_code tc_reset(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments  */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
-
-	if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	/* Disable this module if it is running */
-	if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
-		tc_disable(module_inst);
-		while (tc_is_syncing(module_inst)) {
-			/* wait while module is disabling */
-		}
-	}
-
-	/* Reset this TC module */
-	tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
-
-	return STATUS_OK;
+    /* Sanity check arguments  */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+    if (tc_module->STATUS.reg & TC_STATUS_SLAVE)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    /* Disable this module if it is running */
+    if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE)
+    {
+        tc_disable(module_inst);
+        while (tc_is_syncing(module_inst))
+        {
+            /* wait while module is disabling */
+        }
+    }
+
+    /* Reset this TC module */
+    tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
+
+    return STATUS_OK;
 }
 
 /**
@@ -652,34 +701,36 @@ enum status_code tc_reset(
  *                                module instance is invalid
  */
 enum status_code tc_set_top_value (
-		const struct tc_module *const module_inst,
-		const uint32_t top_value)
+        const struct tc_module *const module_inst,
+        const uint32_t top_value)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(top_value);
-
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			tc_module->COUNT8.PER.reg    = (uint8_t)top_value;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
-			return STATUS_OK;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(top_value);
+
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            tc_module->COUNT8.PER.reg    = (uint8_t)top_value;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+            return STATUS_OK;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c
index 82daf22724e3..49b5d93b7138 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tc/tc_sam_l_c/tc.c
@@ -59,21 +59,23 @@
  * \return Index of the given TC module instance.
  */
 uint8_t _tc_get_inst_index(
-		Tc *const hw)
+        Tc *const hw)
 {
-	/* List of available TC modules. */
-	Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
-
-	/* Find index for TC instance. */
-	for (uint32_t i = 0; i < TC_INST_NUM; i++) {
-		if (hw == tc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given. */
-	Assert(false);
-	return 0;
+    /* List of available TC modules. */
+    Tc *const tc_modules[TC_INST_NUM] = TC_INSTS;
+
+    /* Find index for TC instance. */
+    for (uint32_t i = 0; i < TC_INST_NUM; i++)
+    {
+        if (hw == tc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given. */
+    Assert(false);
+    return 0;
 }
 
 
@@ -99,296 +101,326 @@ uint8_t _tc_get_inst_index(
  *                             slave mode
  */
 enum status_code tc_init(
-		struct tc_module *const module_inst,
-		Tc *const hw,
-		const struct tc_config *const config)
+        struct tc_module *const module_inst,
+        Tc *const hw,
+        const struct tc_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(module_inst);
-	Assert(config);
-
-	/* Temporary variable to hold all updates to the CTRLA
-	 * register before they are written to it */
-	uint32_t ctrla_tmp = 0;
-	/* Temporary variable to hold all updates to the CTRLBSET
-	 * register before they are written to it */
-	uint8_t ctrlbset_tmp = 0;
-	/* Temporary variable to hold TC instance number */
-	uint8_t instance = _tc_get_inst_index(hw);
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(module_inst);
+    Assert(config);
+
+    /* Temporary variable to hold all updates to the CTRLA
+     * register before they are written to it */
+    uint32_t ctrla_tmp = 0;
+    /* Temporary variable to hold all updates to the CTRLBSET
+     * register before they are written to it */
+    uint8_t ctrlbset_tmp = 0;
+    /* Temporary variable to hold TC instance number */
+    uint8_t instance = _tc_get_inst_index(hw);
 
 #if (SAMC20) || (SAMC21)
-	/* Array of GLCK ID for different TC instances */
-	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
-	/* Array of MCLK APB mask bit position for different TC instances */
-	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4};
+    /* Array of GLCK ID for different TC instances */
+    uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+    /* Array of MCLK APB mask bit position for different TC instances */
+    uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC4};
 #elif (SAML21J)
-	/* Array of GLCK ID for different TC instances */
-	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
-	/* Array of MCLK APB mask bit position for different TC instances */
-	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
-									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+    /* Array of GLCK ID for different TC instances */
+    uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID, TC4_GCLK_ID};
+    /* Array of MCLK APB mask bit position for different TC instances */
+    uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3,
+                                    SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
 #elif (SAML22)
-	/* Array of GLCK ID for different TC instances */
-	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID};
-	/* Array of MCLK APB mask bit position for different TC instances */
-	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3};
+    /* Array of GLCK ID for different TC instances */
+    uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC2_GCLK_ID, TC3_GCLK_ID};
+    /* Array of MCLK APB mask bit position for different TC instances */
+    uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC2,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC3};
 #else
-	/* Array of GLCK ID for different TC instances */
-	uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID};
-	/* Array of PM APB mask bit position for different TC instances */
-	uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
-									SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
-									SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
+    /* Array of GLCK ID for different TC instances */
+    uint8_t inst_gclk_id[] = {TC0_GCLK_ID, TC1_GCLK_ID, TC4_GCLK_ID};
+    /* Array of PM APB mask bit position for different TC instances */
+    uint32_t inst_mclk_apbmask[] = {SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC0,
+                                    SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TC1,
+                                    SYSTEM_CLOCK_APB_APBD, MCLK_APBDMASK_TC4};
 #endif
 
-	struct system_pinmux_config pin_config;
-	struct system_gclk_chan_config gclk_chan_config;
+    struct system_pinmux_config pin_config;
+    struct system_gclk_chan_config gclk_chan_config;
 
 #if TC_ASYNC == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < TC_CALLBACK_N; i++) {
-		module_inst->callback[i]        = NULL;
-	}
-	module_inst->register_callback_mask     = 0x00;
-	module_inst->enable_callback_mask       = 0x00;
-
-	/* Register this instance for callbacks*/
-	_tc_instances[instance] = module_inst;
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < TC_CALLBACK_N; i++)
+    {
+        module_inst->callback[i]        = NULL;
+    }
+    module_inst->register_callback_mask     = 0x00;
+    module_inst->enable_callback_mask       = 0x00;
+
+    /* Register this instance for callbacks*/
+    _tc_instances[instance] = module_inst;
 #endif
 
-	/* Associate the given device instance with the hardware module */
-	module_inst->hw = hw;
-
-	module_inst->double_buffering_enabled = config->double_buffering_enabled;
-
-	/* Check if odd numbered TC modules are being configured in 32-bit
-	 * counter size. Only even numbered counters are allowed to be
-	 * configured in 32-bit counter size.
-	 */
-	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
-			((instance + TC_INSTANCE_OFFSET) & 0x01)) {
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Make the counter size variable in the module_inst struct reflect
-	 * the counter size in the module
-	 */
-	module_inst->counter_size = config->counter_size;
-
-	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
-
-	if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) {
-		/* Module is used as a slave */
-		return STATUS_ERR_DENIED;
-	}
-
-	if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
-
-	/* Set up the TC PWM out pin for channel 0 */
-	if (config->pwm_channel[0].enabled) {
-		system_pinmux_get_config_defaults(&pin_config);
-		pin_config.mux_position = config->pwm_channel[0].pin_mux;
-		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
-		system_pinmux_pin_set_config(
-				config->pwm_channel[0].pin_out, &pin_config);
-	}
-
-	/* Set up the TC PWM out pin for channel 1 */
-	if (config->pwm_channel[1].enabled) {
-		system_pinmux_get_config_defaults(&pin_config);
-		pin_config.mux_position = config->pwm_channel[1].pin_mux;
-		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
-		system_pinmux_pin_set_config(
-				config->pwm_channel[1].pin_out, &pin_config);
-	}
-
-	/* Enable the user interface clock in the MCLK */
-	system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2],
-			inst_mclk_apbmask[2*instance+1]);
-
-	/* Enable the slave counter if counter_size is 32-bit */
-	if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM))
-	{
-		/* Enable the user interface clock in the MCLK */
-		system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[(instance+1)*2],
-				inst_mclk_apbmask[(instance+1)*2+1]);
-	}
-
-
-	/* Setup clock for module */
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = config->clock_source;
-	system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
-	system_gclk_chan_enable(inst_gclk_id[instance]);
-
-	/* Set ctrla register */
-	ctrla_tmp =
-			(uint32_t)config->counter_size |
-			(uint32_t)config->reload_action |
-			(uint32_t)config->clock_prescaler;
-
-	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
-		if (config->enable_capture_on_channel[i] == true) {
-			ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i);
-		}
-	}
-
-	for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) {
-		if (config->enable_capture_on_IO[i] == true) {
-			ctrla_tmp |= (TC_CTRLA_COPEN(1) << i);
-		}
-	}
-
-	ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos)
-				|(config->on_demand << TC_CTRLA_ONDEMAND_Pos);
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.CTRLA.reg = ctrla_tmp;
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.WAVE.reg = config->wave_generation;
-
-	/* Set ctrlb register */
-	if (config->oneshot) {
-		ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
-	}
-
-	if (config->count_direction) {
-		ctrlbset_tmp |= TC_CTRLBSET_DIR;
-	}
-
-	/* Clear old ctrlb configuration */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-	hw->COUNT8.CTRLBCLR.reg = 0xFF;
-
-	/* Check if we actually need to go into a wait state. */
-	if (ctrlbset_tmp) {
-		while (tc_is_syncing(module_inst)) {
-			/* Wait for sync */
-		}
-		/* Write configuration to register */
-		hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
-	}
-
-	/* Set drvvtrl register*/
-	hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output;
-
-	/* Write configuration to register */
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Switch for TC counter size  */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.COUNT.reg =
-					config->counter_8_bit.value;
-
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.PER.reg =
-					config->counter_8_bit.period;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.CC[0].reg =
-					config->counter_8_bit.compare_capture_channel[0];
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT8.CC[1].reg =
-					config->counter_8_bit.compare_capture_channel[1];
-
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
+    /* Associate the given device instance with the hardware module */
+    module_inst->hw = hw;
+
+    module_inst->double_buffering_enabled = config->double_buffering_enabled;
+
+    /* Check if odd numbered TC modules are being configured in 32-bit
+     * counter size. Only even numbered counters are allowed to be
+     * configured in 32-bit counter size.
+     */
+    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) &&
+            ((instance + TC_INSTANCE_OFFSET) & 0x01))
+            {
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Make the counter size variable in the module_inst struct reflect
+     * the counter size in the module
+     */
+    module_inst->counter_size = config->counter_size;
+
+    if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
+
+    if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE)
+    {
+        /* Module is used as a slave */
+        return STATUS_ERR_DENIED;
+    }
+
+    if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
+
+    /* Set up the TC PWM out pin for channel 0 */
+    if (config->pwm_channel[0].enabled)
+    {
+        system_pinmux_get_config_defaults(&pin_config);
+        pin_config.mux_position = config->pwm_channel[0].pin_mux;
+        pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+        system_pinmux_pin_set_config(
+                config->pwm_channel[0].pin_out, &pin_config);
+    }
+
+    /* Set up the TC PWM out pin for channel 1 */
+    if (config->pwm_channel[1].enabled)
+    {
+        system_pinmux_get_config_defaults(&pin_config);
+        pin_config.mux_position = config->pwm_channel[1].pin_mux;
+        pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+        system_pinmux_pin_set_config(
+                config->pwm_channel[1].pin_out, &pin_config);
+    }
+
+    /* Enable the user interface clock in the MCLK */
+    system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[instance*2],
+            inst_mclk_apbmask[2*instance+1]);
+
+    /* Enable the slave counter if counter_size is 32-bit */
+    if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && (instance+1 < TC_INST_NUM))
+    {
+        /* Enable the user interface clock in the MCLK */
+        system_apb_clock_set_mask((enum system_clock_apb_bus)inst_mclk_apbmask[(instance+1)*2],
+                inst_mclk_apbmask[(instance+1)*2+1]);
+    }
+
+
+    /* Setup clock for module */
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = config->clock_source;
+    system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config);
+    system_gclk_chan_enable(inst_gclk_id[instance]);
+
+    /* Set ctrla register */
+    ctrla_tmp =
+            (uint32_t)config->counter_size |
+            (uint32_t)config->reload_action |
+            (uint32_t)config->clock_prescaler;
+
+    for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++)
+    {
+        if (config->enable_capture_on_channel[i] == true)
+        {
+            ctrla_tmp |= (TC_CTRLA_CAPTEN(1) << i);
+        }
+    }
+
+    for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++)
+    {
+        if (config->enable_capture_on_IO[i] == true)
+        {
+            ctrla_tmp |= (TC_CTRLA_COPEN(1) << i);
+        }
+    }
+
+    ctrla_tmp |= (config->run_in_standby << TC_CTRLA_RUNSTDBY_Pos)
+                |(config->on_demand << TC_CTRLA_ONDEMAND_Pos);
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.CTRLA.reg = ctrla_tmp;
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.WAVE.reg = config->wave_generation;
+
+    /* Set ctrlb register */
+    if (config->oneshot)
+    {
+        ctrlbset_tmp = TC_CTRLBSET_ONESHOT;
+    }
+
+    if (config->count_direction)
+    {
+        ctrlbset_tmp |= TC_CTRLBSET_DIR;
+    }
+
+    /* Clear old ctrlb configuration */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT8.CTRLBCLR.reg = 0xFF;
+
+    /* Check if we actually need to go into a wait state. */
+    if (ctrlbset_tmp)
+    {
+        while (tc_is_syncing(module_inst))
+        {
+            /* Wait for sync */
+        }
+        /* Write configuration to register */
+        hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp;
+    }
+
+    /* Set drvvtrl register*/
+    hw->COUNT8.DRVCTRL.reg = config->waveform_invert_output;
+
+    /* Write configuration to register */
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Switch for TC counter size  */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.COUNT.reg =
+                    config->counter_8_bit.value;
+
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.PER.reg =
+                    config->counter_8_bit.period;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.CC[0].reg =
+                    config->counter_8_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT8.CC[1].reg =
+                    config->counter_8_bit.compare_capture_channel[1];
+
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.COUNT.reg
+                = config->counter_16_bit.value;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.CC[0].reg =
+                    config->counter_16_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT16.CC[1].reg =
+                    config->counter_16_bit.compare_capture_channel[1];
+
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT32.COUNT.reg
+                = config->counter_32_bit.value;
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
+
+            hw->COUNT32.CC[0].reg =
+                    config->counter_32_bit.compare_capture_channel[0];
+
+            while (tc_is_syncing(module_inst))
+            {
+                /* Wait for sync */
+            }
 
-			hw->COUNT16.COUNT.reg
-				= config->counter_16_bit.value;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
+            hw->COUNT32.CC[1].reg =
+                    config->counter_32_bit.compare_capture_channel[1];
 
-			hw->COUNT16.CC[0].reg =
-					config->counter_16_bit.compare_capture_channel[0];
+            return STATUS_OK;
+    }
 
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT16.CC[1].reg =
-					config->counter_16_bit.compare_capture_channel[1];
-
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT32.COUNT.reg
-				= config->counter_32_bit.value;
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT32.CC[0].reg =
-					config->counter_32_bit.compare_capture_channel[0];
-
-			while (tc_is_syncing(module_inst)) {
-				/* Wait for sync */
-			}
-
-			hw->COUNT32.CC[1].reg =
-					config->counter_32_bit.compare_capture_channel[1];
-
-			return STATUS_OK;
-	}
-
-	Assert(false);
-	return STATUS_ERR_INVALID_ARG;
+    Assert(false);
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -406,37 +438,39 @@ enum status_code tc_init(
  * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
  */
 enum status_code tc_set_count_value(
-		const struct tc_module *const module_inst,
-		const uint32_t count)
+        const struct tc_module *const module_inst,
+        const uint32_t count)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance*/
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Write to based on the TC counter_size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			tc_module->COUNT16.COUNT.reg = (uint16_t)count;
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			tc_module->COUNT32.COUNT.reg = (uint32_t)count;
-			return STATUS_OK;
-
-		default:
-			return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance*/
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Write to based on the TC counter_size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            tc_module->COUNT8.COUNT.reg  = (uint8_t)count;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            tc_module->COUNT16.COUNT.reg = (uint16_t)count;
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            tc_module->COUNT32.COUNT.reg = (uint32_t)count;
+            return STATUS_OK;
+
+        default:
+            return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -450,36 +484,38 @@ enum status_code tc_set_count_value(
  * \return Count value of the specified TC module.
  */
 uint32_t tc_get_count_value(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Read synchronization */
-	tc_sync_read_count(module_inst);
-	
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Read from based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			return (uint32_t)tc_module->COUNT8.COUNT.reg;
-
-		case TC_COUNTER_SIZE_16BIT:
-			return (uint32_t)tc_module->COUNT16.COUNT.reg;
-
-		case TC_COUNTER_SIZE_32BIT:
-			return tc_module->COUNT32.COUNT.reg;
-	}
-
-	Assert(false);
-	return 0;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Read synchronization */
+    tc_sync_read_count(module_inst);
+
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Read from based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            return (uint32_t)tc_module->COUNT8.COUNT.reg;
+
+        case TC_COUNTER_SIZE_16BIT:
+            return (uint32_t)tc_module->COUNT16.COUNT.reg;
+
+        case TC_COUNTER_SIZE_32BIT:
+            return tc_module->COUNT32.COUNT.reg;
+    }
+
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -493,43 +529,48 @@ uint32_t tc_get_count_value(
  * \return Capture value stored in the specified timer channel.
  */
 uint32_t tc_get_capture_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index)
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Read out based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT8.CC[channel_index].reg;
-			}
-
-		case TC_COUNTER_SIZE_16BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT16.CC[channel_index].reg;
-			}
-
-		case TC_COUNTER_SIZE_32BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				return tc_module->COUNT32.CC[channel_index].reg;
-			}
-	}
-
-	Assert(false);
-	return 0;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Read out based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT8.CC[channel_index].reg;
+            }
+
+        case TC_COUNTER_SIZE_16BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT16.CC[channel_index].reg;
+            }
+
+        case TC_COUNTER_SIZE_32BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                return tc_module->COUNT32.CC[channel_index].reg;
+            }
+    }
+
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -547,64 +588,72 @@ uint32_t tc_get_capture_value(
  * \retval  STATUS_ERR_INVALID_ARG  An invalid channel index was supplied
  */
 enum status_code tc_set_compare_value(
-		const struct tc_module *const module_inst,
-		const enum tc_compare_capture_channel channel_index,
-		const uint32_t compare)
+        const struct tc_module *const module_inst,
+        const enum tc_compare_capture_channel channel_index,
+        const uint32_t compare)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(compare);
-
-	/* Get a pointer to the module's hardware instance */
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	/* Read out based on the TC counter size */
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				if (module_inst->double_buffering_enabled){
-					tc_module->COUNT8.CCBUF[channel_index].reg =
-							(uint8_t)compare;
-				} else {
-					tc_module->COUNT8.CC[channel_index].reg  =
-							(uint8_t)compare;
-				}
-				return STATUS_OK;
-			}
-		case TC_COUNTER_SIZE_16BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				if (module_inst->double_buffering_enabled){
-					tc_module->COUNT16.CCBUF[channel_index].reg =
-							(uint16_t)compare;
-				} else {
-					tc_module->COUNT16.CC[channel_index].reg =
-							(uint16_t)compare;
-				}
-				return STATUS_OK;
-			}
-
-		case TC_COUNTER_SIZE_32BIT:
-			if (channel_index <
-					NUMBER_OF_COMPARE_CAPTURE_CHANNELS) {
-				if (module_inst->double_buffering_enabled){
-					tc_module->COUNT32.CCBUF[channel_index].reg =
-							(uint32_t)compare;
-				} else {
-					tc_module->COUNT32.CC[channel_index].reg =
-						(uint32_t)compare;
-				}
-				return STATUS_OK;
-			}
-	}
-
-	return STATUS_ERR_INVALID_ARG;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(compare);
+
+    /* Get a pointer to the module's hardware instance */
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    /* Read out based on the TC counter size */
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                if (module_inst->double_buffering_enabled)
+                {
+                    tc_module->COUNT8.CCBUF[channel_index].reg =
+                            (uint8_t)compare;
+                } else {
+                    tc_module->COUNT8.CC[channel_index].reg  =
+                            (uint8_t)compare;
+                }
+                return STATUS_OK;
+            }
+        case TC_COUNTER_SIZE_16BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                if (module_inst->double_buffering_enabled)
+                {
+                    tc_module->COUNT16.CCBUF[channel_index].reg =
+                            (uint16_t)compare;
+                } else {
+                    tc_module->COUNT16.CC[channel_index].reg =
+                            (uint16_t)compare;
+                }
+                return STATUS_OK;
+            }
+
+        case TC_COUNTER_SIZE_32BIT:
+            if (channel_index <
+                    NUMBER_OF_COMPARE_CAPTURE_CHANNELS)
+                    {
+                if (module_inst->double_buffering_enabled)
+                {
+                    tc_module->COUNT32.CCBUF[channel_index].reg =
+                            (uint32_t)compare;
+                } else {
+                    tc_module->COUNT32.CC[channel_index].reg =
+                        (uint32_t)compare;
+                }
+                return STATUS_OK;
+            }
+    }
+
+    return STATUS_ERR_INVALID_ARG;
 }
 
 /**
@@ -626,31 +675,34 @@ enum status_code tc_set_compare_value(
  *                                     TC
  */
 enum status_code tc_reset(
-		const struct tc_module *const module_inst)
+        const struct tc_module *const module_inst)
 {
-	/* Sanity check arguments  */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module hardware instance */
-	TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
-
-	if (tc_module->STATUS.reg & TC_STATUS_SLAVE) {
-		return STATUS_ERR_UNSUPPORTED_DEV;
-	}
-
-	/* Disable this module if it is running */
-	if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) {
-		tc_disable(module_inst);
-		while (tc_is_syncing(module_inst)) {
-			/* wait while module is disabling */
-		}
-	}
-
-	/* Reset this TC module */
-	tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
-
-	return STATUS_OK;
+    /* Sanity check arguments  */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module hardware instance */
+    TcCount8 *const tc_module = &(module_inst->hw->COUNT8);
+
+    if (tc_module->STATUS.reg & TC_STATUS_SLAVE)
+    {
+        return STATUS_ERR_UNSUPPORTED_DEV;
+    }
+
+    /* Disable this module if it is running */
+    if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE)
+    {
+        tc_disable(module_inst);
+        while (tc_is_syncing(module_inst))
+        {
+            /* wait while module is disabling */
+        }
+    }
+
+    /* Reset this TC module */
+    tc_module->CTRLA.reg  |= TC_CTRLA_SWRST;
+
+    return STATUS_OK;
 }
 
 /**
@@ -678,46 +730,51 @@ enum status_code tc_reset(
  *                                module instance is invalid
  */
 enum status_code tc_set_top_value (
-		const struct tc_module *const module_inst,
-		const uint32_t top_value)
+        const struct tc_module *const module_inst,
+        const uint32_t top_value)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(top_value);
-
-	Tc *const tc_module = module_inst->hw;
-
-	while (tc_is_syncing(module_inst)) {
-		/* Wait for sync */
-	}
-
-	switch (module_inst->counter_size) {
-		case TC_COUNTER_SIZE_8BIT:
-			if (module_inst->double_buffering_enabled){
-				tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value;
-			} else {
-				tc_module->COUNT8.PER.reg = (uint8_t)top_value;
-			}
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_16BIT:
-			if (module_inst->double_buffering_enabled){
-				tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value;
-			} else {
-				tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
-			}
-			return STATUS_OK;
-
-		case TC_COUNTER_SIZE_32BIT:
-			if (module_inst->double_buffering_enabled){
-				tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value;
-			} else {
-				tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
-			}
-			return STATUS_OK;
-
-		default:
-			Assert(false);
-			return STATUS_ERR_INVALID_ARG;
-	}
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(top_value);
+
+    Tc *const tc_module = module_inst->hw;
+
+    while (tc_is_syncing(module_inst))
+    {
+        /* Wait for sync */
+    }
+
+    switch (module_inst->counter_size)
+    {
+        case TC_COUNTER_SIZE_8BIT:
+            if (module_inst->double_buffering_enabled)
+            {
+                tc_module->COUNT8.PERBUF.reg = (uint8_t)top_value;
+            } else {
+                tc_module->COUNT8.PER.reg = (uint8_t)top_value;
+            }
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_16BIT:
+            if (module_inst->double_buffering_enabled)
+            {
+                tc_module->COUNT16.CCBUF[0].reg = (uint16_t)top_value;
+            } else {
+                tc_module->COUNT16.CC[0].reg = (uint16_t)top_value;
+            }
+            return STATUS_OK;
+
+        case TC_COUNTER_SIZE_32BIT:
+            if (module_inst->double_buffering_enabled)
+            {
+                tc_module->COUNT32.CCBUF[0].reg = (uint32_t)top_value;
+            } else {
+                tc_module->COUNT32.CC[0].reg = (uint32_t)top_value;
+            }
+            return STATUS_OK;
+
+        default:
+            Assert(false);
+            return STATUS_ERR_INVALID_ARG;
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c
index 64cffc461d21..c46e08f8c796 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.c
@@ -54,11 +54,11 @@
  * Converts a given TCC index to its interrupt vector index.
  */
 #  define _TCC_INTERRUPT_VECT_NUM(n, unused) \
-		SYSTEM_INTERRUPT_MODULE_TCC##n,
+        SYSTEM_INTERRUPT_MODULE_TCC##n,
 #endif
 
 #define _SIZE_MAX(size) ((size==32u) ? 0xFFFFFFFF : ( \
-		(1u << size) - 1))
+        (1u << size) - 1))
 
 #define _SIZE_MAX_WITH_DITHER 0x03FFFFFF
 
@@ -127,18 +127,20 @@ const uint8_t _tcc_ow_nums[TCC_INST_NUM] = TCC_OW_NUMS;
  * \return Index of the given TCC module instance.
  */
 uint8_t _tcc_get_inst_index(
-		Tcc *const hw)
+        Tcc *const hw)
 {
-	/* Find index for TCC instance. */
-	for (uint32_t i = 0; i < TCC_INST_NUM; i++) {
-		if (hw == tcc_modules[i]) {
-			return i;
-		}
-	}
-
-	/* Invalid data given. */
-	Assert(false);
-	return 0;
+    /* Find index for TCC instance. */
+    for (uint32_t i = 0; i < TCC_INST_NUM; i++)
+    {
+        if (hw == tcc_modules[i])
+        {
+            return i;
+        }
+    }
+
+    /* Invalid data given. */
+    Assert(false);
+    return 0;
 }
 
 /**
@@ -180,88 +182,88 @@ uint8_t _tcc_get_inst_index(
  *
  */
 void tcc_get_config_defaults(
-		struct tcc_config *const config,
-		Tcc *const hw)
+        struct tcc_config *const config,
+        Tcc *const hw)
 {
-	/* TCC instance index */
-	uint8_t module_index = _tcc_get_inst_index(hw);
+    /* TCC instance index */
+    uint8_t module_index = _tcc_get_inst_index(hw);
 
-	/* Base counter defaults */
-	config->counter.count                  = 0;
+    /* Base counter defaults */
+    config->counter.count                  = 0;
 
-	config->counter.period                 = _tcc_maxs[module_index];
+    config->counter.period                 = _tcc_maxs[module_index];
 
-	config->counter.clock_source           = GCLK_GENERATOR_0;
-	config->counter.clock_prescaler        = TCC_CLOCK_PRESCALER_DIV1;
-	config->counter.reload_action          = TCC_RELOAD_ACTION_GCLK;
+    config->counter.clock_source           = GCLK_GENERATOR_0;
+    config->counter.clock_prescaler        = TCC_CLOCK_PRESCALER_DIV1;
+    config->counter.reload_action          = TCC_RELOAD_ACTION_GCLK;
 
-	config->counter.direction              = TCC_COUNT_DIRECTION_UP;
-	config->counter.oneshot                = false;
+    config->counter.direction              = TCC_COUNT_DIRECTION_UP;
+    config->counter.oneshot                = false;
 
 #ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
-	config->counter.dma_trigger_mode       = TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE;
+    config->counter.dma_trigger_mode       = TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE;
 #endif
 
-	/* Match/Capture defaults */
+    /* Match/Capture defaults */
 #  define _TCC_CHANNEL_MATCH_VALUE_INIT(n, value) \
-		config->compare.match[n] = value;
-	MREPEAT(TCC_NUM_CHANNELS,
-		_TCC_CHANNEL_MATCH_VALUE_INIT, 0)
+        config->compare.match[n] = value;
+    MREPEAT(TCC_NUM_CHANNELS,
+        _TCC_CHANNEL_MATCH_VALUE_INIT, 0)
 #  undef _TCC_CHANNEL_MATCH_VALUE_INIT
 
-	/* Wave polarity defaults */
+    /* Wave polarity defaults */
 #  define _TCC_CHANNEL_WAVE_POLARITY_INIT(n, value) \
-		config->compare.wave_polarity[n] = value;
-	MREPEAT(TCC_NUM_CHANNELS,
-		_TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0)
+        config->compare.wave_polarity[n] = value;
+    MREPEAT(TCC_NUM_CHANNELS,
+        _TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0)
 #  undef _TCC_CHANNEL_WAVE_POLARITY_INIT
 
-	config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ;
-	config->compare.wave_ramp       = TCC_RAMP_RAMP1;
+    config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ;
+    config->compare.wave_ramp       = TCC_RAMP_RAMP1;
 
 #  define _TCC_CHANNEL_FUNCTION_INIT(n, value) \
-		config->compare.channel_function[n] = value;
-	MREPEAT(TCC_NUM_CHANNELS,
-			_TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE)
+        config->compare.channel_function[n] = value;
+    MREPEAT(TCC_NUM_CHANNELS,
+            _TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE)
 #  undef _TCC_CHANNEL_FUNCTION_INIT
 
-	/* Recoverable fault defaults */
+    /* Recoverable fault defaults */
 #  define _TCC_FAULT_FUNCTION_INIT(n, dummy) \
-		config->wave_ext.recoverable_fault[n].filter_value = 0;      \
-		config->wave_ext.recoverable_fault[n].blanking_cycles = 0;   \
-		config->wave_ext.recoverable_fault[n].restart = false;       \
-		config->wave_ext.recoverable_fault[n].keep = false;          \
-		config->wave_ext.recoverable_fault[n].qualification = false; \
-		config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE;           \
-		config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE;       \
-		config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \
-		config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE;  \
-		config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0;
-	MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0)
+        config->wave_ext.recoverable_fault[n].filter_value = 0;      \
+        config->wave_ext.recoverable_fault[n].blanking_cycles = 0;   \
+        config->wave_ext.recoverable_fault[n].restart = false;       \
+        config->wave_ext.recoverable_fault[n].keep = false;          \
+        config->wave_ext.recoverable_fault[n].qualification = false; \
+        config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE;           \
+        config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE;       \
+        config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \
+        config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE;  \
+        config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0;
+    MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0)
 #  undef _TCC_FAULT_FUNCTION_INIT
 
-	/* Non-recoverable fault defaults */
+    /* Non-recoverable fault defaults */
 #  define _TCC_NRF_FUNCTION_INIT(n, dummy) \
-		config->wave_ext.non_recoverable_fault[n].filter_value = 0; \
-		config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF;
-	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0)
+        config->wave_ext.non_recoverable_fault[n].filter_value = 0; \
+        config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF;
+    MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0)
 #  undef _TCC_NRF_FUNCTION_INIT
 
-	/* Output inversion defaults */
+    /* Output inversion defaults */
 #  define _TCC_OUT_INVERT_INIT(n, value) \
-		config->wave_ext.invert[n] = value;
-	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false)
+        config->wave_ext.invert[n] = value;
+    MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false)
 #  undef _TCC_OUT_INVERT_INIT
 
 #  define _TCC_CHANNEL_OUT_PIN_INIT(n, dummy) \
-		config->pins.enable_wave_out_pin[n]                = false;\
-		config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n]     = 0;    \
-		config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0;
-	MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0)
+        config->pins.enable_wave_out_pin[n]                = false;\
+        config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n]     = 0;    \
+        config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0;
+    MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0)
 #  undef _TCC_CHANNEL_OUT_PIN_INIT
 
-	config->double_buffering_enabled  = true;
-	config->run_in_standby            = false;
+    config->double_buffering_enabled  = true;
+    config->run_in_standby            = false;
 }
 
 
@@ -281,33 +283,37 @@ void tcc_get_config_defaults(
  *                                used capture channel is invalid for module
  */
 static inline enum status_code _tcc_build_ctrla(
-		const uint8_t module_index,
-		const struct tcc_config *const config,
-		uint32_t *value_buffer)
+        const uint8_t module_index,
+        const struct tcc_config *const config,
+        uint32_t *value_buffer)
 {
-	uint32_t ctrla = 0;
-
-	int i;
-	for (i = 0; i < TCC_NUM_CHANNELS; i ++) {
-		if (config->capture.channel_function[i] ==
-			TCC_CHANNEL_FUNCTION_CAPTURE) {
-
-			if (i > _tcc_cc_nums[module_index]) {
-				/* Channel not supported */
-				return STATUS_ERR_INVALID_ARG;
-			}
-			ctrla |= (TCC_CTRLA_CPTEN0 << i);
-		}
-	}
-
-	if (config->run_in_standby) {
-		ctrla |= TCC_CTRLA_RUNSTDBY;
-	}
-	ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos;
-	ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos;
-
-	*value_buffer = ctrla;
-	return STATUS_OK;
+    uint32_t ctrla = 0;
+
+    int i;
+    for (i = 0; i < TCC_NUM_CHANNELS; i ++)
+    {
+        if (config->capture.channel_function[i] ==
+            TCC_CHANNEL_FUNCTION_CAPTURE)
+            {
+
+            if (i > _tcc_cc_nums[module_index])
+            {
+                /* Channel not supported */
+                return STATUS_ERR_INVALID_ARG;
+            }
+            ctrla |= (TCC_CTRLA_CPTEN0 << i);
+        }
+    }
+
+    if (config->run_in_standby)
+    {
+        ctrla |= TCC_CTRLA_RUNSTDBY;
+    }
+    ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos;
+    ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos;
+
+    *value_buffer = ctrla;
+    return STATUS_OK;
 }
 
 /**
@@ -318,20 +324,22 @@ static inline enum status_code _tcc_build_ctrla(
  * \param[out] value_buffer Pointer to the buffer to fill with built value
  */
 static inline void _tcc_build_ctrlb(
-		const uint8_t module_index,
-		const struct tcc_config *const config,
-		uint8_t *value_buffer)
+        const uint8_t module_index,
+        const struct tcc_config *const config,
+        uint8_t *value_buffer)
 {
-	uint8_t ctrlb = 0;
-
-	if (config->counter.oneshot) {
-		ctrlb |= TCC_CTRLBSET_ONESHOT;
-	}
-	if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN) {
-		ctrlb |= TCC_CTRLBSET_DIR;
-	}
-
-	*value_buffer = ctrlb;
+    uint8_t ctrlb = 0;
+
+    if (config->counter.oneshot)
+    {
+        ctrlb |= TCC_CTRLBSET_ONESHOT;
+    }
+    if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN)
+    {
+        ctrlb |= TCC_CTRLBSET_DIR;
+    }
+
+    *value_buffer = ctrlb;
 }
 
 /**
@@ -348,36 +356,39 @@ static inline void _tcc_build_ctrlb(
  *                                value is invalid
  */
 static inline enum status_code _tcc_build_faults(
-		const uint8_t module_index,
-		const struct tcc_config *const config,
-		uint32_t *value_buffer)
+        const uint8_t module_index,
+        const struct tcc_config *const config,
+        uint32_t *value_buffer)
 {
-	struct tcc_recoverable_fault_config *cfg;
-	uint8_t cc_num = _tcc_cc_nums[module_index];
-	uint32_t fault;
-	int i;
-	for (i = 0; i < TCC_NUM_FAULTS; i ++) {
-		cfg = (struct tcc_recoverable_fault_config *)
-				&config->wave_ext.recoverable_fault[i];
-		if (cfg->capture_channel >= cc_num) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		if (cfg->filter_value > 0xF) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-		fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value)
-				| TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles)
-				| (cfg->restart ? TCC_FCTRLA_RESTART : 0)
-				| (cfg->keep ? TCC_FCTRLA_KEEP : 0)
-				| (cfg->qualification ? TCC_FCTRLA_QUAL : 0)
-				| TCC_FCTRLA_SRC(cfg->source)
-				| TCC_FCTRLA_BLANK(cfg->blanking)
-				| TCC_FCTRLA_HALT(cfg->halt_action)
-				| TCC_FCTRLA_CAPTURE(cfg->capture_action)
-				| TCC_FCTRLA_CHSEL(cfg->capture_channel);
-		value_buffer[i] = fault;
-	}
-	return STATUS_OK;
+    struct tcc_recoverable_fault_config *cfg;
+    uint8_t cc_num = _tcc_cc_nums[module_index];
+    uint32_t fault;
+    int i;
+    for (i = 0; i < TCC_NUM_FAULTS; i ++)
+    {
+        cfg = (struct tcc_recoverable_fault_config *)
+                &config->wave_ext.recoverable_fault[i];
+        if (cfg->capture_channel >= cc_num)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        if (cfg->filter_value > 0xF)
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+        fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value)
+                | TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles)
+                | (cfg->restart ? TCC_FCTRLA_RESTART : 0)
+                | (cfg->keep ? TCC_FCTRLA_KEEP : 0)
+                | (cfg->qualification ? TCC_FCTRLA_QUAL : 0)
+                | TCC_FCTRLA_SRC(cfg->source)
+                | TCC_FCTRLA_BLANK(cfg->blanking)
+                | TCC_FCTRLA_HALT(cfg->halt_action)
+                | TCC_FCTRLA_CAPTURE(cfg->capture_action)
+                | TCC_FCTRLA_CHSEL(cfg->capture_channel);
+        value_buffer[i] = fault;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -393,38 +404,44 @@ static inline enum status_code _tcc_build_faults(
  *                                is invalid; filter value is invalid
  */
 static inline enum status_code _tcc_build_drvctrl(
-		const uint8_t module_index,
-		const struct tcc_config *const config,
-		uint32_t *value_buffer)
+        const uint8_t module_index,
+        const struct tcc_config *const config,
+        uint32_t *value_buffer)
 {
-	uint32_t i;
-	uint8_t ow_num = _tcc_ow_nums[module_index];
-	uint32_t drvctrl;
-
-	drvctrl = 0;
-
-	for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) {
-		if (config->wave_ext.invert[i]) {
-			if (i >= ow_num) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-			drvctrl |= (TCC_DRVCTRL_INVEN0 << i);
-		}
-		if (config->wave_ext.non_recoverable_fault[i].output !=
-			TCC_FAULT_STATE_OUTPUT_OFF) {
-			if (i >= ow_num) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-			if (config->wave_ext.non_recoverable_fault[i].output ==
-				TCC_FAULT_STATE_OUTPUT_1) {
-				drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i;
-			} else {
-				drvctrl |= (TCC_DRVCTRL_NRE0) << i;
-			}
-		}
-	}
-	*value_buffer = drvctrl;
-	return STATUS_OK;
+    uint32_t i;
+    uint8_t ow_num = _tcc_ow_nums[module_index];
+    uint32_t drvctrl;
+
+    drvctrl = 0;
+
+    for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++)
+    {
+        if (config->wave_ext.invert[i])
+        {
+            if (i >= ow_num)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+            drvctrl |= (TCC_DRVCTRL_INVEN0 << i);
+        }
+        if (config->wave_ext.non_recoverable_fault[i].output !=
+            TCC_FAULT_STATE_OUTPUT_OFF)
+            {
+            if (i >= ow_num)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+            if (config->wave_ext.non_recoverable_fault[i].output ==
+                TCC_FAULT_STATE_OUTPUT_1)
+                {
+                drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i;
+            } else {
+                drvctrl |= (TCC_DRVCTRL_NRE0) << i;
+            }
+        }
+    }
+    *value_buffer = drvctrl;
+    return STATUS_OK;
 }
 
 /**
@@ -442,32 +459,35 @@ static inline enum status_code _tcc_build_drvctrl(
  *                                module
  */
 static inline enum status_code _tcc_build_waves(
-		const uint8_t module_index,
-		const struct tcc_config *const config,
-		uint32_t *value_buffer)
+        const uint8_t module_index,
+        const struct tcc_config *const config,
+        uint32_t *value_buffer)
 {
-	int n;
+    int n;
 
-	uint8_t cc_num = _tcc_cc_nums[module_index];
-	struct tcc_match_wave_config const *wav_cfg = &config->compare;
+    uint8_t cc_num = _tcc_cc_nums[module_index];
+    struct tcc_match_wave_config const *wav_cfg = &config->compare;
 
-	uint32_t wave;
+    uint32_t wave;
 
-	wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) |
-			TCC_WAVE_WAVEGEN(wav_cfg->wave_generation);
+    wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) |
+            TCC_WAVE_WAVEGEN(wav_cfg->wave_generation);
 
-	for (n = 0; n < TCC_NUM_CHANNELS; n++) {
-		if (wav_cfg->wave_polarity[n]) {
-			if (n >= cc_num) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-			wave |= (TCC_WAVE_POL0 << n);
-		}
-	}
+    for (n = 0; n < TCC_NUM_CHANNELS; n++)
+    {
+        if (wav_cfg->wave_polarity[n])
+        {
+            if (n >= cc_num)
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+            wave |= (TCC_WAVE_POL0 << n);
+        }
+    }
 
-	value_buffer[0] = wave;
+    value_buffer[0] = wave;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -490,183 +510,205 @@ static inline enum status_code _tcc_build_waves(
  * \retval STATUS_ERR_DENIED   The hardware module was already enabled
  */
 enum status_code tcc_init(
-		struct tcc_module *const module_inst,
-		Tcc *const hw,
-		const struct tcc_config *const config)
+        struct tcc_module *const module_inst,
+        Tcc *const hw,
+        const struct tcc_config *const config)
 {
-	int i;
-
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(module_inst);
-	Assert(config);
-
-	/* TCC instance index */
-	uint8_t module_index = _tcc_get_inst_index(hw);
-
-	/* Enable the user interface clock for TCC */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
-			_tcc_apbcmasks[module_index]);
-
-	/* Check if it's enabled. */
-	if (hw->CTRLA.reg & TCC_CTRLA_ENABLE) {
-		return STATUS_ERR_DENIED;
-	}
-	/* Check if it's resetting */
-	if (hw->CTRLA.reg & TCC_CTRLA_SWRST) {
-		return STATUS_ERR_DENIED;
-	}
-
-	enum status_code status;
-
-	/* Check COUNT, PER, CCx */
-	uint32_t count_max  = _tcc_maxs[module_index];
-
-	/* Check all counter values */
-	if ((config->counter.count > count_max)
-		|| (config->counter.period > count_max)
-		) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check all channel values */
-	for (i = 0; i < TCC_NUM_CHANNELS; i ++) {
-		if ((config->compare.match[i] > count_max)
-			) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-
-	/* Check all outputs */
-	for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) {
-		if (!config->pins.enable_wave_out_pin[i]) {
-			continue;
-		}
-		/* Output line is not supported */
-		if (i >= _tcc_ow_nums[module_index]) {
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-
-	/* CTRLA settings */
-	uint32_t ctrla = 0;
-	status = _tcc_build_ctrla(module_index, config, &ctrla);
-	if (STATUS_OK != status) {
-		return status;
-	}
-
-	/* CTRLB settings */
-	uint8_t ctrlb;
-	_tcc_build_ctrlb(module_index, config, &ctrlb);
-
-	/* FAULTs settings */
-	uint32_t faults[TCC_NUM_FAULTS];
-
-	status = _tcc_build_faults(module_index, config, faults);
-	if (STATUS_OK != status) {
-		return status;
-	}
-
-	/* DRVCTRL */
-	uint32_t drvctrl = 0;
-
-	status = _tcc_build_drvctrl(module_index, config, &drvctrl);
-	if (STATUS_OK != status) {
-		return status;
-	}
-
-	/* WAVE */
-	uint32_t waves[1];
-
-	status = _tcc_build_waves(module_index, config, waves);
-	if (STATUS_OK != status) {
-		return status;
-	}
-
-	/* Initialize module */
+    int i;
+
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(module_inst);
+    Assert(config);
+
+    /* TCC instance index */
+    uint8_t module_index = _tcc_get_inst_index(hw);
+
+    /* Enable the user interface clock for TCC */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC,
+            _tcc_apbcmasks[module_index]);
+
+    /* Check if it's enabled. */
+    if (hw->CTRLA.reg & TCC_CTRLA_ENABLE)
+    {
+        return STATUS_ERR_DENIED;
+    }
+    /* Check if it's resetting */
+    if (hw->CTRLA.reg & TCC_CTRLA_SWRST)
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    enum status_code status;
+
+    /* Check COUNT, PER, CCx */
+    uint32_t count_max  = _tcc_maxs[module_index];
+
+    /* Check all counter values */
+    if ((config->counter.count > count_max)
+        || (config->counter.period > count_max)
+        )
+        {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check all channel values */
+    for (i = 0; i < TCC_NUM_CHANNELS; i ++)
+    {
+        if ((config->compare.match[i] > count_max)
+            )
+            {
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+
+    /* Check all outputs */
+    for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++)
+    {
+        if (!config->pins.enable_wave_out_pin[i])
+        {
+            continue;
+        }
+        /* Output line is not supported */
+        if (i >= _tcc_ow_nums[module_index])
+        {
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+
+    /* CTRLA settings */
+    uint32_t ctrla = 0;
+    status = _tcc_build_ctrla(module_index, config, &ctrla);
+    if (STATUS_OK != status)
+    {
+        return status;
+    }
+
+    /* CTRLB settings */
+    uint8_t ctrlb;
+    _tcc_build_ctrlb(module_index, config, &ctrlb);
+
+    /* FAULTs settings */
+    uint32_t faults[TCC_NUM_FAULTS];
+
+    status = _tcc_build_faults(module_index, config, faults);
+    if (STATUS_OK != status)
+    {
+        return status;
+    }
+
+    /* DRVCTRL */
+    uint32_t drvctrl = 0;
+
+    status = _tcc_build_drvctrl(module_index, config, &drvctrl);
+    if (STATUS_OK != status)
+    {
+        return status;
+    }
+
+    /* WAVE */
+    uint32_t waves[1];
+
+    status = _tcc_build_waves(module_index, config, waves);
+    if (STATUS_OK != status)
+    {
+        return status;
+    }
+
+    /* Initialize module */
 #if TCC_ASYNC
-	/* Initialize parameters */
-	for (i = 0; i < TCC_CALLBACK_N; i ++) {
-		module_inst->callback[i] = NULL;
-	}
-	module_inst->register_callback_mask = 0;
-	module_inst->enable_callback_mask = 0;
-	_tcc_instances[module_index] = module_inst;
+    /* Initialize parameters */
+    for (i = 0; i < TCC_CALLBACK_N; i ++)
+    {
+        module_inst->callback[i] = NULL;
+    }
+    module_inst->register_callback_mask = 0;
+    module_inst->enable_callback_mask = 0;
+    _tcc_instances[module_index] = module_inst;
 #endif
 
-	module_inst->hw = hw;
-
-	module_inst->double_buffering_enabled = config->double_buffering_enabled;
-
-	/* Setup clock for module */
-	struct system_gclk_chan_config gclk_chan_config;
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = config->counter.clock_source;
-	system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config);
-	system_gclk_chan_enable(_tcc_gclk_ids[module_index]);
-
-	/* Initialize pins */
-	struct system_pinmux_config pin_config;
-	for (i = 0; i <  _tcc_ow_nums[module_index]; i ++) {
-		if (!config->pins.enable_wave_out_pin[i]) {
-			continue;
-		}
-
-		system_pinmux_get_config_defaults(&pin_config);
-		pin_config.mux_position = config->pins.wave_out_pin_mux[i];
-		pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
-		system_pinmux_pin_set_config(
-				config->pins.wave_out_pin[i], &pin_config);
-	}
-
-	/* Write to registers */
-
-	hw->CTRLA.reg = ctrla;
-	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-
-	hw->CTRLBCLR.reg = 0xFF;
-	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-	hw->CTRLBSET.reg = ctrlb;
-
-	hw->FCTRLA.reg = faults[0];
-	hw->FCTRLB.reg = faults[1];
-
-	hw->DRVCTRL.reg = drvctrl;
+    module_inst->hw = hw;
+
+    module_inst->double_buffering_enabled = config->double_buffering_enabled;
+
+    /* Setup clock for module */
+    struct system_gclk_chan_config gclk_chan_config;
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = config->counter.clock_source;
+    system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config);
+    system_gclk_chan_enable(_tcc_gclk_ids[module_index]);
+
+    /* Initialize pins */
+    struct system_pinmux_config pin_config;
+    for (i = 0; i <  _tcc_ow_nums[module_index]; i ++)
+    {
+        if (!config->pins.enable_wave_out_pin[i])
+        {
+            continue;
+        }
+
+        system_pinmux_get_config_defaults(&pin_config);
+        pin_config.mux_position = config->pins.wave_out_pin_mux[i];
+        pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
+        system_pinmux_pin_set_config(
+                config->pins.wave_out_pin[i], &pin_config);
+    }
+
+    /* Write to registers */
+
+    hw->CTRLA.reg = ctrla;
+    while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+
+    hw->CTRLBCLR.reg = 0xFF;
+    while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+    hw->CTRLBSET.reg = ctrlb;
+
+    hw->FCTRLA.reg = faults[0];
+    hw->FCTRLB.reg = faults[1];
+
+    hw->DRVCTRL.reg = drvctrl;
 
 #if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
-	while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB)) {
-		/* Wait for sync */
-	}
+    while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB))
+    {
+        /* Wait for sync */
+    }
 #endif
-	hw->WAVE.reg = waves[0];
+    hw->WAVE.reg = waves[0];
 
-	while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
-		/* Wait for sync */
-	}
-	hw->COUNT.reg = config->counter.count;
+    while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT)
+    {
+        /* Wait for sync */
+    }
+    hw->COUNT.reg = config->counter.count;
 
 #if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
-	while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB)) {
-		/* Wait for sync */
-	}
+    while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB))
+    {
+        /* Wait for sync */
+    }
 #endif
-	hw->PER.reg = (config->counter.period);
+    hw->PER.reg = (config->counter.period);
 
-	for (i = 0; i <  _tcc_cc_nums[module_index]; i ++) {
+    for (i = 0; i <  _tcc_cc_nums[module_index]; i ++)
+    {
 #if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30)
-		while (hw->SYNCBUSY.reg & (
-			(TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i)) {
-			/* Wait for sync */
-		}
+        while (hw->SYNCBUSY.reg & (
+            (TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i))
+            {
+            /* Wait for sync */
+        }
 #endif
-		hw->CC[i].reg = (config->compare.match[i]);
-	}
+        hw->CC[i].reg = (config->compare.match[i]);
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 
@@ -689,146 +731,163 @@ enum status_code tcc_init(
  *                             was supplied
  */
 enum status_code tcc_enable_events(
-		struct tcc_module *const module_inst,
-		struct tcc_events *const events)
+        struct tcc_module *const module_inst,
+        struct tcc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Tcc *const tcc_module = module_inst->hw;
-
-	/* Check if it's enabled or resetting. */
-	if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) {
-		return STATUS_ERR_DENIED;
-	}
-
-	uint32_t evctrl = tcc_module->EVCTRL.reg;
-
-	/* Setup event output action */
-	if (events->output_config.modify_generation_selection) {
-		evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk;
-		switch(events->output_config.generation_selection) {
-		case TCC_EVENT_GENERATION_SELECTION_START:
-			evctrl |= TCC_EVCTRL_CNTSEL_START;
-			break;
-		case TCC_EVENT_GENERATION_SELECTION_END:
-			evctrl |= TCC_EVCTRL_CNTSEL_END;
-			break;
-		case TCC_EVENT_GENERATION_SELECTION_BETWEEN:
-			evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN;
-			break;
-		case TCC_EVENT_GENERATION_SELECTION_BOUNDARY:
-			evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY;
-			break;
-		default:
-			Assert(false);
-			/* Wrong configuration */
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-	/* Setup input event0 */
-	if (events->on_input_event_perform_action[0]) {
-		evctrl |= TCC_EVCTRL_TCEI0;
-	}
-	if (events->input_config[0].invert) {
-		evctrl |= TCC_EVCTRL_TCINV0;
-	}
-	if (events->input_config[0].modify_action) {
-		evctrl &= ~ TCC_EVCTRL_EVACT0_Msk;
-		switch(events->input_config[0].action) {
-		case TCC_EVENT0_ACTION_OFF:
-			evctrl |= TCC_EVCTRL_EVACT0_OFF;
-			break;
-		case TCC_EVENT0_ACTION_RETRIGGER:
-			evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER;
-			break;
-		case TCC_EVENT0_ACTION_COUNT_EVENT:
-			evctrl |= TCC_EVCTRL_EVACT0_COUNTEV;
-			break;
-		case TCC_EVENT0_ACTION_START:
-			evctrl |= TCC_EVCTRL_EVACT0_START;
-			break;
-		case TCC_EVENT0_ACTION_INCREMENT:
-			evctrl |= TCC_EVCTRL_EVACT0_INC;
-			break;
-		case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE:
-			evctrl |= TCC_EVCTRL_EVACT0_COUNT;
-			break;
-		case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT:
-			evctrl |= TCC_EVCTRL_EVACT0_FAULT;
-			break;
-		default:
-			Assert(false);
-			/* Wrong configuration */
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-	/* Setup input event1 */
-	if (events->on_input_event_perform_action[1]) {
-		evctrl |= TCC_EVCTRL_TCEI1;
-	}
-	if (events->input_config[1].invert) {
-		evctrl |= TCC_EVCTRL_TCINV1;
-	}
-	if (events->input_config[1].modify_action) {
-		evctrl &= ~ TCC_EVCTRL_EVACT1_Msk;
-		switch(events->input_config[1].action) {
-		case TCC_EVENT1_ACTION_OFF:
-			evctrl |= TCC_EVCTRL_EVACT1_OFF;
-			break;
-		case TCC_EVENT1_ACTION_RETRIGGER:
-			evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER;
-			break;
-		case TCC_EVENT1_ACTION_DIR_CONTROL:
-			evctrl |= TCC_EVCTRL_EVACT1_DIR;
-			break;
-		case TCC_EVENT1_ACTION_STOP:
-			evctrl |= TCC_EVCTRL_EVACT1_STOP;
-			break;
-		case TCC_EVENT1_ACTION_DECREMENT:
-			evctrl |= TCC_EVCTRL_EVACT1_DEC;
-			break;
-		case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE:
-			evctrl |= TCC_EVCTRL_EVACT1_PPW |
-					TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
-			break;
-		case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE:
-			evctrl |= TCC_EVCTRL_EVACT1_PWP |
-					TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
-			break;
-		case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT:
-			evctrl |= TCC_EVCTRL_EVACT1_FAULT;
-			break;
-		default:
-			Assert(false);
-			/* Wrong configuration */
-			return STATUS_ERR_INVALID_ARG;
-		}
-	}
-	uint32_t ch;
-	for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) {
-		if (events->generate_event_on_channel[ch]) {
-			evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
-		}
-		if (events->on_event_perform_channel_action[ch]) {
-			evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
-		}
-	}
-	if (events->generate_event_on_counter_overflow) {
-		evctrl |= TCC_EVCTRL_OVFEO;
-	}
-	if (events->generate_event_on_counter_retrigger) {
-		evctrl |= TCC_EVCTRL_TRGEO;
-	}
-	if (events->generate_event_on_counter_event) {
-		evctrl |= TCC_EVCTRL_CNTEO;
-	}
-
-	tcc_module->EVCTRL.reg = evctrl;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Tcc *const tcc_module = module_inst->hw;
+
+    /* Check if it's enabled or resetting. */
+    if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST))
+    {
+        return STATUS_ERR_DENIED;
+    }
+
+    uint32_t evctrl = tcc_module->EVCTRL.reg;
+
+    /* Setup event output action */
+    if (events->output_config.modify_generation_selection)
+    {
+        evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk;
+        switch(events->output_config.generation_selection)
+        {
+        case TCC_EVENT_GENERATION_SELECTION_START:
+            evctrl |= TCC_EVCTRL_CNTSEL_START;
+            break;
+        case TCC_EVENT_GENERATION_SELECTION_END:
+            evctrl |= TCC_EVCTRL_CNTSEL_END;
+            break;
+        case TCC_EVENT_GENERATION_SELECTION_BETWEEN:
+            evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN;
+            break;
+        case TCC_EVENT_GENERATION_SELECTION_BOUNDARY:
+            evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY;
+            break;
+        default:
+            Assert(false);
+            /* Wrong configuration */
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+    /* Setup input event0 */
+    if (events->on_input_event_perform_action[0])
+    {
+        evctrl |= TCC_EVCTRL_TCEI0;
+    }
+    if (events->input_config[0].invert)
+    {
+        evctrl |= TCC_EVCTRL_TCINV0;
+    }
+    if (events->input_config[0].modify_action)
+    {
+        evctrl &= ~ TCC_EVCTRL_EVACT0_Msk;
+        switch(events->input_config[0].action)
+        {
+        case TCC_EVENT0_ACTION_OFF:
+            evctrl |= TCC_EVCTRL_EVACT0_OFF;
+            break;
+        case TCC_EVENT0_ACTION_RETRIGGER:
+            evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER;
+            break;
+        case TCC_EVENT0_ACTION_COUNT_EVENT:
+            evctrl |= TCC_EVCTRL_EVACT0_COUNTEV;
+            break;
+        case TCC_EVENT0_ACTION_START:
+            evctrl |= TCC_EVCTRL_EVACT0_START;
+            break;
+        case TCC_EVENT0_ACTION_INCREMENT:
+            evctrl |= TCC_EVCTRL_EVACT0_INC;
+            break;
+        case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE:
+            evctrl |= TCC_EVCTRL_EVACT0_COUNT;
+            break;
+        case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT:
+            evctrl |= TCC_EVCTRL_EVACT0_FAULT;
+            break;
+        default:
+            Assert(false);
+            /* Wrong configuration */
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+    /* Setup input event1 */
+    if (events->on_input_event_perform_action[1])
+    {
+        evctrl |= TCC_EVCTRL_TCEI1;
+    }
+    if (events->input_config[1].invert)
+    {
+        evctrl |= TCC_EVCTRL_TCINV1;
+    }
+    if (events->input_config[1].modify_action)
+    {
+        evctrl &= ~ TCC_EVCTRL_EVACT1_Msk;
+        switch(events->input_config[1].action)
+        {
+        case TCC_EVENT1_ACTION_OFF:
+            evctrl |= TCC_EVCTRL_EVACT1_OFF;
+            break;
+        case TCC_EVENT1_ACTION_RETRIGGER:
+            evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER;
+            break;
+        case TCC_EVENT1_ACTION_DIR_CONTROL:
+            evctrl |= TCC_EVCTRL_EVACT1_DIR;
+            break;
+        case TCC_EVENT1_ACTION_STOP:
+            evctrl |= TCC_EVCTRL_EVACT1_STOP;
+            break;
+        case TCC_EVENT1_ACTION_DECREMENT:
+            evctrl |= TCC_EVCTRL_EVACT1_DEC;
+            break;
+        case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE:
+            evctrl |= TCC_EVCTRL_EVACT1_PPW |
+                    TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
+            break;
+        case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE:
+            evctrl |= TCC_EVCTRL_EVACT1_PWP |
+                    TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1;
+            break;
+        case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT:
+            evctrl |= TCC_EVCTRL_EVACT1_FAULT;
+            break;
+        default:
+            Assert(false);
+            /* Wrong configuration */
+            return STATUS_ERR_INVALID_ARG;
+        }
+    }
+    uint32_t ch;
+    for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++)
+    {
+        if (events->generate_event_on_channel[ch])
+        {
+            evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
+        }
+        if (events->on_event_perform_channel_action[ch])
+        {
+            evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
+        }
+    }
+    if (events->generate_event_on_counter_overflow)
+    {
+        evctrl |= TCC_EVCTRL_OVFEO;
+    }
+    if (events->generate_event_on_counter_retrigger)
+    {
+        evctrl |= TCC_EVCTRL_TRGEO;
+    }
+    if (events->generate_event_on_counter_event)
+    {
+        evctrl |= TCC_EVCTRL_CNTEO;
+    }
+
+    tcc_module->EVCTRL.reg = evctrl;
+
+    return STATUS_OK;
 }
 
 /**
@@ -843,55 +902,66 @@ enum status_code tcc_enable_events(
  * \param[in]  events       Struct containing flags of events to disable
  */
 void tcc_disable_events(
-		struct tcc_module *const module_inst,
-		struct tcc_events *const events)
+        struct tcc_module *const module_inst,
+        struct tcc_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(events);
-
-	Tcc *const tcc_module = module_inst->hw;
-
-	/* Check if it's enabled or resetting. */
-	if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) {
-		return;
-	}
-
-
-	uint32_t evctrl = 0;
-	uint32_t ch;
-	for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) {
-		if (events->generate_event_on_channel[ch]) {
-			evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
-		}
-		if (events->on_event_perform_channel_action[ch]) {
-			evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
-		}
-	}
-	if (events->generate_event_on_counter_overflow) {
-		evctrl |= TCC_EVCTRL_OVFEO;
-	}
-	if (events->generate_event_on_counter_retrigger) {
-		evctrl |= TCC_EVCTRL_TRGEO;
-	}
-	if (events->generate_event_on_counter_event) {
-		evctrl |= TCC_EVCTRL_CNTEO;
-	}
-	if (events->on_input_event_perform_action[0]) {
-		evctrl |= TCC_EVCTRL_TCEI0;
-	}
-	if (events->on_input_event_perform_action[1]) {
-		evctrl |= TCC_EVCTRL_TCEI1;
-	}
-	if (events->input_config[0].invert) {
-		evctrl |= TCC_EVCTRL_TCINV0;
-	}
-	if (events->input_config[1].invert) {
-		evctrl |= TCC_EVCTRL_TCINV1;
-	}
-
-	tcc_module->EVCTRL.reg &= ~evctrl;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(events);
+
+    Tcc *const tcc_module = module_inst->hw;
+
+    /* Check if it's enabled or resetting. */
+    if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST))
+    {
+        return;
+    }
+
+
+    uint32_t evctrl = 0;
+    uint32_t ch;
+    for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++)
+    {
+        if (events->generate_event_on_channel[ch])
+        {
+            evctrl |= (TCC_EVCTRL_MCEO(1) << ch);
+        }
+        if (events->on_event_perform_channel_action[ch])
+        {
+            evctrl |= (TCC_EVCTRL_MCEI(1) << ch);
+        }
+    }
+    if (events->generate_event_on_counter_overflow)
+    {
+        evctrl |= TCC_EVCTRL_OVFEO;
+    }
+    if (events->generate_event_on_counter_retrigger)
+    {
+        evctrl |= TCC_EVCTRL_TRGEO;
+    }
+    if (events->generate_event_on_counter_event)
+    {
+        evctrl |= TCC_EVCTRL_CNTEO;
+    }
+    if (events->on_input_event_perform_action[0])
+    {
+        evctrl |= TCC_EVCTRL_TCEI0;
+    }
+    if (events->on_input_event_perform_action[1])
+    {
+        evctrl |= TCC_EVCTRL_TCEI1;
+    }
+    if (events->input_config[0].invert)
+    {
+        evctrl |= TCC_EVCTRL_TCINV0;
+    }
+    if (events->input_config[1].invert)
+    {
+        evctrl |= TCC_EVCTRL_TCINV1;
+    }
+
+    tcc_module->EVCTRL.reg &= ~evctrl;
 }
 
 
@@ -911,32 +981,34 @@ void tcc_disable_events(
  * \retval STATUS_ERR_INVALID_ARG  An invalid timer counter size was specified
  */
 enum status_code tcc_set_count_value(
-		const struct tcc_module *const module_inst,
-		const uint32_t count)
+        const struct tcc_module *const module_inst,
+        const uint32_t count)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance*/
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+    /* Get a pointer to the module's hardware instance*/
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
 
-	uint32_t max_count = _tcc_maxs[module_index];
+    uint32_t max_count = _tcc_maxs[module_index];
 
-	if (count > max_count) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (count > max_count)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
-		/* Wait for sync */
-	}
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT)
+    {
+        /* Wait for sync */
+    }
 
-	/* Write to based on the TCC dithering */
-	tcc_module->COUNT.reg = (count);
+    /* Write to based on the TCC dithering */
+    tcc_module->COUNT.reg = (count);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -950,39 +1022,44 @@ enum status_code tcc_set_count_value(
  * \return Count value of the specified TCC module.
  */
 uint32_t tcc_get_count_value(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance*/
-	Tcc *const tcc_module = module_inst->hw;
-	uint32_t last_cmd;
-
-	/* Wait last command done */
-	do {
-		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-		}
-		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
-		if (TCC_CTRLBSET_CMD_NONE == last_cmd) {
-			/* Issue read command and break */
-			tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val;
-			while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-				/* Wait for sync */
-			}
-			break;
-		} else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd) {
-			/* Command have been issued */
-			break;
-		}
-	} while (1);
-
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) {
-		/* Wait for sync */
-	}
-	return (tcc_module->COUNT.reg);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance*/
+    Tcc *const tcc_module = module_inst->hw;
+    uint32_t last_cmd;
+
+    /* Wait last command done */
+    do {
+        while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+        {
+            /* Wait for sync */
+        }
+        last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+        if (TCC_CTRLBSET_CMD_NONE == last_cmd)
+        {
+            /* Issue read command and break */
+            tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val;
+            while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+            {
+                /* Wait for sync */
+            }
+            break;
+        } else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd)
+        {
+            /* Command have been issued */
+            break;
+        }
+    } while (1);
+
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT)
+    {
+        /* Wait for sync */
+    }
+    return (tcc_module->COUNT.reg);
 }
 
 
@@ -998,23 +1075,24 @@ uint32_t tcc_get_count_value(
  * \return Capture value stored in the specified timer channel.
  */
 uint32_t tcc_get_capture_value(
-		const struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index)
+        const struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]);
+    Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]);
 
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
 
-	while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index)) {
-		/* Sync wait */
-	}
+    while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index))
+    {
+        /* Sync wait */
+    }
 
-	return tcc_module->CC[channel_index].reg;
+    return tcc_module->CC[channel_index].reg;
 }
 
 /**
@@ -1036,53 +1114,59 @@ uint32_t tcc_get_capture_value(
  *                                  compare value exceed resolution
  */
 static enum status_code _tcc_set_compare_value(
-		const struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index,
-		const uint32_t compare,
-		const bool double_buffering_enabled)
+        const struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index,
+        const uint32_t compare,
+        const bool double_buffering_enabled)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
-
-	/* Check index */
-	if (channel_index >= _tcc_cc_nums[module_index]) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	uint32_t max_count = _tcc_maxs[module_index];
-
-	/* Check compare value */
-	if (compare > max_count) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	if (double_buffering_enabled) {
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+    /* Check index */
+    if (channel_index >= _tcc_cc_nums[module_index])
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    uint32_t max_count = _tcc_maxs[module_index];
+
+    /* Check compare value */
+    if (compare > max_count)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    if (double_buffering_enabled)
+    {
 #if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
-		tcc_module->CCBUF[channel_index].reg = compare;
+        tcc_module->CCBUF[channel_index].reg = compare;
 #else
-		while(tcc_module->STATUS.reg  &
-				(TCC_STATUS_CCBV0 << channel_index)) {
-			/* Valid check */
-		}
-		while(tcc_module->SYNCBUSY.reg  &
-				(TCC_SYNCBUSY_CCB0 << channel_index)) {
-			/* Sync wait */
-		}
-		tcc_module->CCB[channel_index].reg = compare;
+        while(tcc_module->STATUS.reg  &
+                (TCC_STATUS_CCBV0 << channel_index))
+                {
+            /* Valid check */
+        }
+        while(tcc_module->SYNCBUSY.reg  &
+                (TCC_SYNCBUSY_CCB0 << channel_index))
+                {
+            /* Sync wait */
+        }
+        tcc_module->CCB[channel_index].reg = compare;
 #endif
-	} else {
-		while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index)) {
-			/* Sync wait */
-		}
-		tcc_module->CC[channel_index].reg = compare;
-	}
-	return STATUS_OK;
+    } else {
+        while(tcc_module->SYNCBUSY.reg  & (TCC_SYNCBUSY_CC0 << channel_index))
+        {
+            /* Sync wait */
+        }
+        tcc_module->CC[channel_index].reg = compare;
+    }
+    return STATUS_OK;
 }
 
 
@@ -1107,15 +1191,15 @@ static enum status_code _tcc_set_compare_value(
  *                                  compare value exceed resolution
  */
 enum status_code tcc_set_compare_value(
-		const struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index,
-		const uint32_t compare)
+        const struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index,
+        const uint32_t compare)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	return _tcc_set_compare_value(module_inst, channel_index, compare,
-			module_inst->double_buffering_enabled);
+    return _tcc_set_compare_value(module_inst, channel_index, compare,
+            module_inst->double_buffering_enabled);
 }
 
 /**
@@ -1137,20 +1221,21 @@ enum status_code tcc_set_compare_value(
  *                                  compare value exceed resolution
  */
 enum status_code tcc_set_double_buffer_compare_values(
-		struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index,
-		const uint32_t compare, const uint32_t compare_buffer)
+        struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index,
+        const uint32_t compare, const uint32_t compare_buffer)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	enum status_code status;
-	status = _tcc_set_compare_value(module_inst, channel_index, compare, false);
-	if (status != STATUS_OK) {
-		return status;
-	}
-	return _tcc_set_compare_value(module_inst, channel_index, compare_buffer,
-			true);
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    enum status_code status;
+    status = _tcc_set_compare_value(module_inst, channel_index, compare, false);
+    if (status != STATUS_OK)
+    {
+        return status;
+    }
+    return _tcc_set_compare_value(module_inst, channel_index, compare_buffer,
+            true);
 }
 
 
@@ -1171,42 +1256,46 @@ enum status_code tcc_set_double_buffer_compare_values(
  *                                top/period value exceed resolution
  */
 static enum status_code _tcc_set_top_value(
-		const struct tcc_module *const module_inst,
-		const uint32_t top_value,
-		const bool double_buffering_enabled)
+        const struct tcc_module *const module_inst,
+        const uint32_t top_value,
+        const bool double_buffering_enabled)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
 
-	uint32_t max_count = _tcc_maxs[module_index];
+    uint32_t max_count = _tcc_maxs[module_index];
 
-	/* Check compare value */
-	if (top_value > max_count) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Check compare value */
+    if (top_value > max_count)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	if (double_buffering_enabled) {
+    if (double_buffering_enabled)
+    {
 #if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
-		tcc_module->PERBUF.reg = top_value;
+        tcc_module->PERBUF.reg = top_value;
 #else
-		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PERB) {
-			/* Sync wait */
-		}
-		tcc_module->PERB.reg = top_value;
+        while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PERB)
+        {
+            /* Sync wait */
+        }
+        tcc_module->PERB.reg = top_value;
 #endif
-	} else {
-		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PER) {
-			/* Sync wait */
-		}
-		tcc_module->PER.reg = top_value;
-	}
-	return STATUS_OK;
+    } else {
+        while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PER)
+        {
+            /* Sync wait */
+        }
+        tcc_module->PER.reg = top_value;
+    }
+    return STATUS_OK;
 }
 
 
@@ -1237,14 +1326,14 @@ static enum status_code _tcc_set_top_value(
  *                                top/period value exceed resolution
  */
 enum status_code tcc_set_top_value(
-		const struct tcc_module *const module_inst,
-		const uint32_t top_value)
+        const struct tcc_module *const module_inst,
+        const uint32_t top_value)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	return _tcc_set_top_value(module_inst, top_value,
-			module_inst->double_buffering_enabled);
+    return _tcc_set_top_value(module_inst, top_value,
+            module_inst->double_buffering_enabled);
 }
 
 /**
@@ -1271,18 +1360,19 @@ enum status_code tcc_set_top_value(
  *                                top/period value exceed resolution
  */
 enum status_code tcc_set_double_buffer_top_values(
-		const struct tcc_module *const module_inst,
-		const uint32_t top_value, const uint32_t top_buffer_value)
+        const struct tcc_module *const module_inst,
+        const uint32_t top_value, const uint32_t top_buffer_value)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	enum status_code status;
-	status = _tcc_set_top_value(module_inst, top_value, false);
-	if (status != STATUS_OK) {
-		return status;
-	}
-	return _tcc_set_top_value(module_inst, top_buffer_value, true);
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    enum status_code status;
+    status = _tcc_set_top_value(module_inst, top_value, false);
+    if (status != STATUS_OK)
+    {
+        return status;
+    }
+    return _tcc_set_top_value(module_inst, top_buffer_value, true);
 }
 
 
@@ -1306,54 +1396,60 @@ enum status_code tcc_set_double_buffer_top_values(
  * \retval  STATUS_ERR_INVALID_ARG  An invalid line index was supplied
  */
 enum status_code tcc_set_pattern(
-		const struct tcc_module *const module_inst,
-		const uint32_t line_index,
-		const enum tcc_output_pattern pattern)
+        const struct tcc_module *const module_inst,
+        const uint32_t line_index,
+        const enum tcc_output_pattern pattern)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
-	/* Get number of output lines */
-	uint8_t ow_num = _tcc_ow_nums[module_index];
-
-	/* Check if line number is OK */
-	if (line_index >= ow_num) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	uint32_t patt_value;
-
-	while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATT) {
-		/* Sync wait */
-	}
-	patt_value = tcc_module->PATT.reg;
-	if (TCC_OUTPUT_PATTERN_DISABLE == pattern) {
-		patt_value &= ~(TCC_PATT_PGE0 << line_index);
-	} else if (TCC_OUTPUT_PATTERN_0 == pattern) {
-		patt_value &= ~(TCC_PATT_PGV0 << line_index);
-		patt_value |=  (TCC_PATT_PGE0 << line_index);
-	} else {
-		patt_value |=  ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index);
-	}
-
-	if (module_inst->double_buffering_enabled) {
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
+    /* Get number of output lines */
+    uint8_t ow_num = _tcc_ow_nums[module_index];
+
+    /* Check if line number is OK */
+    if (line_index >= ow_num)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    uint32_t patt_value;
+
+    while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATT)
+    {
+        /* Sync wait */
+    }
+    patt_value = tcc_module->PATT.reg;
+    if (TCC_OUTPUT_PATTERN_DISABLE == pattern)
+    {
+        patt_value &= ~(TCC_PATT_PGE0 << line_index);
+    } else if (TCC_OUTPUT_PATTERN_0 == pattern)
+    {
+        patt_value &= ~(TCC_PATT_PGV0 << line_index);
+        patt_value |=  (TCC_PATT_PGE0 << line_index);
+    } else {
+        patt_value |=  ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index);
+    }
+
+    if (module_inst->double_buffering_enabled)
+    {
 #if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30)
-		tcc_module->PATTBUF.reg = patt_value;
+        tcc_module->PATTBUF.reg = patt_value;
 #else
-		while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATTB) {
-			/* Sync wait */
-		}
-		tcc_module->PATTB.reg = patt_value;
+        while(tcc_module->SYNCBUSY.reg  & TCC_SYNCBUSY_PATTB)
+        {
+            /* Sync wait */
+        }
+        tcc_module->PATTB.reg = patt_value;
 #endif
-	} else {
-		tcc_module->PATT.reg = patt_value;
-	}
-	return STATUS_OK;
+    } else {
+        tcc_module->PATT.reg = patt_value;
+    }
+    return STATUS_OK;
 }
 
 /**
@@ -1380,89 +1476,107 @@ enum status_code tcc_set_pattern(
  * \retval TCC_STATUS_RAMP_CYCLE_INDEX    Wave ramp index for cycle
  */
 uint32_t tcc_get_status(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint32_t int_flags = module_inst->hw->INTFLAG.reg;
-	uint32_t status_flags = module_inst->hw->STATUS.reg;
-	uint32_t status = 0;
-	int i;
-
-	/* SYNC */
-	if (module_inst->hw->SYNCBUSY.reg == 0) {
-		status |= TCC_STATUS_SYNC_READY;
-	}
-
-	/* Channels */
-	for (i = 0; i < TCC_NUM_CHANNELS; i++) {
-		if (int_flags & TCC_INTFLAG_MC(i)) {
-			status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i);
-		}
-		if (status_flags & TCC_STATUS_CMP(i)) {
-			status |= TCC_STATUS_CHANNEL_OUTPUT(i);
-		}
-	}
-	/* Non-recoverable fault state */
-	if ((int_flags & TCC_INTFLAG_FAULT1) ||
-		(status_flags & TCC_STATUS_FAULT1)) {
-		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1);
-	}
-	if ((int_flags & TCC_INTFLAG_FAULT0) ||
-		(status_flags & TCC_STATUS_FAULT0)) {
-		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0);
-	}
-	/* Non-recoverable fault inputs */
-	if (status_flags & TCC_STATUS_FAULT0IN) {
-		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0);
-	}
-	if (status_flags & TCC_STATUS_FAULT1IN) {
-		status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1);
-	}
-	/* Recoverable fault state */
-	if ((int_flags & TCC_INTFLAG_FAULTB) ||
-		(status_flags & TCC_STATUS_FAULTB)) {
-		status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1);
-	}
-	if ((int_flags & TCC_INTFLAG_FAULTA) ||
-		(status_flags & TCC_STATUS_FAULTA)) {
-		status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0);
-	}
-	/* Recoverable fault inputs */
-	if (status_flags & TCC_STATUS_FAULTAIN) {
-		status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(0);
-	}
-	if (status_flags & TCC_STATUS_FAULTBIN) {
-		status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(1);
-	}
-
-	/* Check for TCC capture overflow */
-	if (int_flags & TCC_INTFLAG_ERR) {
-		status |= TCC_STATUS_CAPTURE_OVERFLOW;
-	}
-	/* Check for TCC count counter */
-	if (int_flags & TCC_INTFLAG_CNT) {
-		status |= TCC_STATUS_COUNTER_EVENT;
-	}
-	/* Check for TCC count retrigger */
-	if (int_flags & TCC_INTFLAG_TRG) {
-		status |= TCC_STATUS_COUNTER_RETRIGGERED;
-	}
-	/* Check for TCC count overflow */
-	if (int_flags & TCC_INTFLAG_OVF) {
-		status |= TCC_STATUS_COUNT_OVERFLOW;
-	}
-	/* Check for TCC count stop */
-	if (status_flags & TCC_STATUS_STOP) {
-		status |= TCC_STATUS_STOPPED;
-	}
-	/* Check for TCC RAMP index */
-	if (status_flags & TCC_STATUS_IDX) {
-		status |= TCC_STATUS_RAMP_CYCLE_INDEX;
-	}
-	return status;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint32_t int_flags = module_inst->hw->INTFLAG.reg;
+    uint32_t status_flags = module_inst->hw->STATUS.reg;
+    uint32_t status = 0;
+    int i;
+
+    /* SYNC */
+    if (module_inst->hw->SYNCBUSY.reg == 0)
+    {
+        status |= TCC_STATUS_SYNC_READY;
+    }
+
+    /* Channels */
+    for (i = 0; i < TCC_NUM_CHANNELS; i++)
+    {
+        if (int_flags & TCC_INTFLAG_MC(i))
+        {
+            status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i);
+        }
+        if (status_flags & TCC_STATUS_CMP(i))
+        {
+            status |= TCC_STATUS_CHANNEL_OUTPUT(i);
+        }
+    }
+    /* Non-recoverable fault state */
+    if ((int_flags & TCC_INTFLAG_FAULT1) ||
+        (status_flags & TCC_STATUS_FAULT1))
+        {
+        status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1);
+    }
+    if ((int_flags & TCC_INTFLAG_FAULT0) ||
+        (status_flags & TCC_STATUS_FAULT0))
+        {
+        status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0);
+    }
+    /* Non-recoverable fault inputs */
+    if (status_flags & TCC_STATUS_FAULT0IN)
+    {
+        status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0);
+    }
+    if (status_flags & TCC_STATUS_FAULT1IN)
+    {
+        status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1);
+    }
+    /* Recoverable fault state */
+    if ((int_flags & TCC_INTFLAG_FAULTB) ||
+        (status_flags & TCC_STATUS_FAULTB))
+        {
+        status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1);
+    }
+    if ((int_flags & TCC_INTFLAG_FAULTA) ||
+        (status_flags & TCC_STATUS_FAULTA))
+        {
+        status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0);
+    }
+    /* Recoverable fault inputs */
+    if (status_flags & TCC_STATUS_FAULTAIN)
+    {
+        status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(0);
+    }
+    if (status_flags & TCC_STATUS_FAULTBIN)
+    {
+        status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(1);
+    }
+
+    /* Check for TCC capture overflow */
+    if (int_flags & TCC_INTFLAG_ERR)
+    {
+        status |= TCC_STATUS_CAPTURE_OVERFLOW;
+    }
+    /* Check for TCC count counter */
+    if (int_flags & TCC_INTFLAG_CNT)
+    {
+        status |= TCC_STATUS_COUNTER_EVENT;
+    }
+    /* Check for TCC count retrigger */
+    if (int_flags & TCC_INTFLAG_TRG)
+    {
+        status |= TCC_STATUS_COUNTER_RETRIGGERED;
+    }
+    /* Check for TCC count overflow */
+    if (int_flags & TCC_INTFLAG_OVF)
+    {
+        status |= TCC_STATUS_COUNT_OVERFLOW;
+    }
+    /* Check for TCC count stop */
+    if (status_flags & TCC_STATUS_STOP)
+    {
+        status |= TCC_STATUS_STOPPED;
+    }
+    /* Check for TCC RAMP index */
+    if (status_flags & TCC_STATUS_IDX)
+    {
+        status |= TCC_STATUS_RAMP_CYCLE_INDEX;
+    }
+    return status;
 }
 
 /**
@@ -1474,60 +1588,70 @@ uint32_t tcc_get_status(
  * \param[in] status_flags  Bitmask of \c TCC_STATUS_* flags to clear
  */
 void tcc_clear_status(
-		struct tcc_module *const module_inst,
-		const uint32_t status_flags)
+        struct tcc_module *const module_inst,
+        const uint32_t status_flags)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint32_t int_clr = 0;
-	uint32_t status_clr = 0;
-	int i;
-
-	/* Channels */
-	for (i = 0; i < TCC_NUM_CHANNELS; i++) {
-		if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i)) {
-			int_clr |= TCC_INTFLAG_MC(i);
-		}
-	}
-	/* Faults */
-	if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1)) {
-		int_clr |= TCC_INTFLAG_FAULT1;
-		status_clr |= TCC_STATUS_FAULT1;
-	}
-	if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0)) {
-		int_clr |= TCC_INTFLAG_FAULT0;
-		status_clr |= TCC_STATUS_FAULT0;
-	}
-	if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1)) {
-		int_clr |= TCC_INTFLAG_FAULTB;
-		status_clr |= TCC_STATUS_FAULTB;
-	}
-	if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0)) {
-		int_clr |= TCC_INTFLAG_FAULTA;
-		status_clr |= TCC_STATUS_FAULTA;
-	}
-	/* Check for TCC capture overflow */
-	if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW) {
-		int_clr |= TCC_INTFLAG_ERR;
-	}
-	/* Check for TCC count counter */
-	if (status_flags & TCC_STATUS_COUNTER_EVENT) {
-		int_clr |= TCC_INTFLAG_CNT;
-	}
-	/* Check for TCC count retrigger */
-	if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED) {
-		int_clr = TCC_INTFLAG_TRG;
-	}
-	/* Check for TCC count overflow */
-	if (status_flags & TCC_STATUS_COUNT_OVERFLOW) {
-		int_clr |= TCC_INTFLAG_OVF;
-	}
-	/* Clear status flag */
-	module_inst->hw->STATUS.reg = status_clr;
-	/* Clear interrupt flag */
-	module_inst->hw->INTFLAG.reg = int_clr;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint32_t int_clr = 0;
+    uint32_t status_clr = 0;
+    int i;
+
+    /* Channels */
+    for (i = 0; i < TCC_NUM_CHANNELS; i++)
+    {
+        if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i))
+        {
+            int_clr |= TCC_INTFLAG_MC(i);
+        }
+    }
+    /* Faults */
+    if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1))
+    {
+        int_clr |= TCC_INTFLAG_FAULT1;
+        status_clr |= TCC_STATUS_FAULT1;
+    }
+    if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0))
+    {
+        int_clr |= TCC_INTFLAG_FAULT0;
+        status_clr |= TCC_STATUS_FAULT0;
+    }
+    if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1))
+    {
+        int_clr |= TCC_INTFLAG_FAULTB;
+        status_clr |= TCC_STATUS_FAULTB;
+    }
+    if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0))
+    {
+        int_clr |= TCC_INTFLAG_FAULTA;
+        status_clr |= TCC_STATUS_FAULTA;
+    }
+    /* Check for TCC capture overflow */
+    if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW)
+    {
+        int_clr |= TCC_INTFLAG_ERR;
+    }
+    /* Check for TCC count counter */
+    if (status_flags & TCC_STATUS_COUNTER_EVENT)
+    {
+        int_clr |= TCC_INTFLAG_CNT;
+    }
+    /* Check for TCC count retrigger */
+    if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED)
+    {
+        int_clr = TCC_INTFLAG_TRG;
+    }
+    /* Check for TCC count overflow */
+    if (status_flags & TCC_STATUS_COUNT_OVERFLOW)
+    {
+        int_clr |= TCC_INTFLAG_OVF;
+    }
+    /* Clear status flag */
+    module_inst->hw->STATUS.reg = status_clr;
+    /* Clear interrupt flag */
+    module_inst->hw->INTFLAG.reg = int_clr;
 }
 
 /**
@@ -1545,29 +1669,31 @@ void tcc_clear_status(
  * \retval STATUS_INVALID_ARG  An invalid channel index is supplied
  */
 enum status_code tcc_enable_circular_buffer_compare(
-		struct tcc_module *const module_inst,
-		enum tcc_match_capture_channel channel_index)
+        struct tcc_module *const module_inst,
+        enum tcc_match_capture_channel channel_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
-
-	/* Check index */
-	if (channel_index > 3) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	if (channel_index >= _tcc_cc_nums[module_index]) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	tcc_module->WAVE.reg |=  (TCC_WAVE_CICCEN0 << channel_index);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+    /* Check index */
+    if (channel_index > 3)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    if (channel_index >= _tcc_cc_nums[module_index])
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    tcc_module->WAVE.reg |=  (TCC_WAVE_CICCEN0 << channel_index);
+
+    return STATUS_OK;
 }
 
 /**
@@ -1582,27 +1708,29 @@ enum status_code tcc_enable_circular_buffer_compare(
  * \retval STATUS_INVALID_ARG  An invalid channel index is supplied
  */
 enum status_code tcc_disable_circular_buffer_compare(
-		struct tcc_module *const module_inst,
-		enum tcc_match_capture_channel channel_index)
+        struct tcc_module *const module_inst,
+        enum tcc_match_capture_channel channel_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	/* Get a index of the module */
-	uint8_t module_index = _tcc_get_inst_index(tcc_module);
-
-	/* Check index */
-	if (channel_index > 3) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-	if (channel_index >= _tcc_cc_nums[module_index]) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    /* Get a index of the module */
+    uint8_t module_index = _tcc_get_inst_index(tcc_module);
+
+    /* Check index */
+    if (channel_index > 3)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+    if (channel_index >= _tcc_cc_nums[module_index])
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index);
+
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h
index 4c2daa6ac5b5..e10bf186c9f7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc.h
@@ -790,50 +790,50 @@ extern "C" {
 /** Generates table enum list entries for all channels of a
    given type and channel number on TCC module. */
 #define _TCC_CHANNEL_ENUM_LIST(type) \
-		MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL)
+        MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL)
 /** Generates table enum list entries for all output of a
    given type and waveform output number on TCC module. */
 #define _TCC_WO_ENUM_LIST(type) \
-		MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type)
+        MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type)
 
 
 #if TCC_ASYNC == true
 /** Enum for the possible callback types for the TCC module. */
 enum tcc_callback {
-	/** Callback for TCC overflow */
-	TCC_CALLBACK_OVERFLOW,
-	/** Callback for TCC Retrigger */
-	TCC_CALLBACK_RETRIGGER,
-	/** Callback for TCC counter event */
-	TCC_CALLBACK_COUNTER_EVENT,
-	/** Callback for capture overflow error */
-	TCC_CALLBACK_ERROR,
-	/** Callback for Recoverable Fault A */
-	TCC_CALLBACK_FAULTA,
-	/** Callback for Recoverable Fault B */
-	TCC_CALLBACK_FAULTB,
-	/** Callback for Non-Recoverable Fault 0 */
-	TCC_CALLBACK_FAULT0,
-	/** Callback for Non-Recoverable Fault 1 */
-	TCC_CALLBACK_FAULT1,
+    /** Callback for TCC overflow */
+    TCC_CALLBACK_OVERFLOW,
+    /** Callback for TCC Retrigger */
+    TCC_CALLBACK_RETRIGGER,
+    /** Callback for TCC counter event */
+    TCC_CALLBACK_COUNTER_EVENT,
+    /** Callback for capture overflow error */
+    TCC_CALLBACK_ERROR,
+    /** Callback for Recoverable Fault A */
+    TCC_CALLBACK_FAULTA,
+    /** Callback for Recoverable Fault B */
+    TCC_CALLBACK_FAULTB,
+    /** Callback for Non-Recoverable Fault 0 */
+    TCC_CALLBACK_FAULT0,
+    /** Callback for Non-Recoverable Fault 1 */
+    TCC_CALLBACK_FAULT1,
 
 #  if defined(__DOXYGEN__)
-	/** Channel callback type table for TCC
-	 *
-	 *  Each TCC module may contain several callback types for channels; each
-	 *  channel will have its own callback type in the table, with the channel
-	 *  index number substituted for "n" in the channel callback type
-	 *  (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
-	 */
-	TCC_CALLBACK_CHANNEL_n = n,
+    /** Channel callback type table for TCC
+     *
+     *  Each TCC module may contain several callback types for channels; each
+     *  channel will have its own callback type in the table, with the channel
+     *  index number substituted for "n" in the channel callback type
+     *  (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
+     */
+    TCC_CALLBACK_CHANNEL_n = n,
 #  else
-	/** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0 */
-	_TCC_CHANNEL_ENUM_LIST(CALLBACK)
+    /** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0 */
+    _TCC_CHANNEL_ENUM_LIST(CALLBACK)
 #  endif
 
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	TCC_CALLBACK_N
+    /** Number of available callbacks */
+    TCC_CALLBACK_N
 #  endif
 };
 #endif /* #if TCC_ASYNC == true */
@@ -895,20 +895,20 @@ enum tcc_callback {
  */
 enum tcc_match_capture_channel {
 #  if defined(__DOXYGEN__)
-	/** Match capture channel index table for TCC
-	 *
-	 *  Each TCC module may contain several match capture channels; each channel
-	 *  will have its own index in the table, with the index number substituted
-	 *  for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
-	 */
-	TCC_MATCH_CAPTURE_CHANNEL_n = n,
+    /** Match capture channel index table for TCC
+     *
+     *  Each TCC module may contain several match capture channels; each channel
+     *  will have its own index in the table, with the index number substituted
+     *  for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0).
+     */
+    TCC_MATCH_CAPTURE_CHANNEL_n = n,
 #  else
-	/** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0 */
-	_TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE)
+    /** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0 */
+    _TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE)
 #  endif
 #  if !defined(__DOXYGEN__)
-	/** Number of supported channels */
-	TCC_MATCH_CAPTURE_CHANNEL_N
+    /** Number of supported channels */
+    TCC_MATCH_CAPTURE_CHANNEL_N
 #  endif
 };
 
@@ -920,20 +920,20 @@ enum tcc_match_capture_channel {
  */
 enum tcc_wave_output {
 #  if defined(__DOXYGEN__)
-	/** Waveform output index table for TCC
-	 *
-	 *  Each TCC module may contain several wave outputs; each output
-	 *  will have its own index in the table, with the index number substituted
-	 *  for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0).
-	 */
-	TCC_WAVE_OUTPUT_n = n,
+    /** Waveform output index table for TCC
+     *
+     *  Each TCC module may contain several wave outputs; each output
+     *  will have its own index in the table, with the index number substituted
+     *  for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0).
+     */
+    TCC_WAVE_OUTPUT_n = n,
 #  else
-	/** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0 */
-	_TCC_WO_ENUM_LIST(WAVE_OUTPUT)
+    /** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0 */
+    _TCC_WO_ENUM_LIST(WAVE_OUTPUT)
 #  endif
 #  if !defined(__DOXYGEN__)
-	/** Number of supported channels */
-	TCC_WAVE_OUTPUT_N
+    /** Number of supported channels */
+    TCC_WAVE_OUTPUT_N
 #  endif
 };
 
@@ -944,29 +944,29 @@ enum tcc_wave_output {
  *
  */
 enum tcc_wave_generation {
-	/** Normal Frequency: Top is the PER register, output toggled on each
-	 *  compare match */
-	TCC_WAVE_GENERATION_NORMAL_FREQ = 0,
-	/** Match Frequency: Top is CC0 register, output toggles on each update
-	 *  condition */
-	TCC_WAVE_GENERATION_MATCH_FREQ = 1,
-	/** Single-Slope PWM: Top is the PER register, CCx controls duty cycle
-	 *  (output active when count is greater than CCx) */
-	TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2,
-
-	/** Double-slope (count up and down), non centre-aligned: Top is the PER
-	 *  register, CC[x] controls duty cycle while counting up and CC[x+N/2]
-	 *  controls it while counting down */
-	TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4,
-	/** Double-slope (count up and down), interrupt/event at Bottom (Top is the
-	 *  PER register, output active when count is greater than CCx) */
-	TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5,
-	/** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the
-	 *  PER register, output active when count is lower than CCx) */
-	TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6,
-	/** Double-slope (count up and down), interrupt/event at Top (Top is the
-	 *  PER register, output active when count is greater than CCx) */
-	TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7,
+    /** Normal Frequency: Top is the PER register, output toggled on each
+     *  compare match */
+    TCC_WAVE_GENERATION_NORMAL_FREQ = 0,
+    /** Match Frequency: Top is CC0 register, output toggles on each update
+     *  condition */
+    TCC_WAVE_GENERATION_MATCH_FREQ = 1,
+    /** Single-Slope PWM: Top is the PER register, CCx controls duty cycle
+     *  (output active when count is greater than CCx) */
+    TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2,
+
+    /** Double-slope (count up and down), non centre-aligned: Top is the PER
+     *  register, CC[x] controls duty cycle while counting up and CC[x+N/2]
+     *  controls it while counting down */
+    TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4,
+    /** Double-slope (count up and down), interrupt/event at Bottom (Top is the
+     *  PER register, output active when count is greater than CCx) */
+    TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5,
+    /** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the
+     *  PER register, output active when count is lower than CCx) */
+    TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6,
+    /** Double-slope (count up and down), interrupt/event at Top (Top is the
+     *  PER register, output active when count is greater than CCx) */
+    TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7,
 };
 
 /**
@@ -975,10 +975,10 @@ enum tcc_wave_generation {
  * Specifies whether the wave output needs to be inverted or not.
  */
 enum tcc_wave_polarity {
-	/** Wave output is not inverted */
-	TCC_WAVE_POLARITY_0,
-	/** Wave output is inverted */
-	TCC_WAVE_POLARITY_1
+    /** Wave output is not inverted */
+    TCC_WAVE_POLARITY_0,
+    /** Wave output is inverted */
+    TCC_WAVE_POLARITY_1
 };
 
 /**
@@ -987,12 +987,12 @@ enum tcc_wave_polarity {
  * Used when disabling output pattern or when selecting a specific pattern.
  */
 enum tcc_output_pattern {
-	/** SWAP output pattern is not used */
-	TCC_OUTPUT_PATTERN_DISABLE,
-	/** Pattern 0 is applied to SWAP output */
-	TCC_OUTPUT_PATTERN_0,
-	/** Pattern 1 is applied to SWAP output */
-	TCC_OUTPUT_PATTERN_1
+    /** SWAP output pattern is not used */
+    TCC_OUTPUT_PATTERN_DISABLE,
+    /** Pattern 0 is applied to SWAP output */
+    TCC_OUTPUT_PATTERN_0,
+    /** Pattern 1 is applied to SWAP output */
+    TCC_OUTPUT_PATTERN_1
 };
 
 /**
@@ -1001,18 +1001,18 @@ enum tcc_output_pattern {
  * Ramp operations which are supported in single-slope PWM generation.
  */
 enum tcc_ramp {
-	/** Default timer/counter PWM operation */
-	TCC_RAMP_RAMP1 = 0,
-
-	/** Uses a single channel (CC0) to control both CC0/CC1 compare outputs.
-	 *  In cycle A, the channel 0 output is disabled, and
-	 *  in cycle B, the channel 1 output is disabled. */
-	TCC_RAMP_RAMP2A,
-
-	/** Uses channels CC0 and CC1 to control compare outputs.
-	 *  In cycle A, the channel 0 output is disabled, and
-	 *  in cycle B, the channel 1 output is disabled.*/
-	TCC_RAMP_RAMP2
+    /** Default timer/counter PWM operation */
+    TCC_RAMP_RAMP1 = 0,
+
+    /** Uses a single channel (CC0) to control both CC0/CC1 compare outputs.
+     *  In cycle A, the channel 0 output is disabled, and
+     *  in cycle B, the channel 1 output is disabled. */
+    TCC_RAMP_RAMP2A,
+
+    /** Uses channels CC0 and CC1 to control compare outputs.
+     *  In cycle A, the channel 0 output is disabled, and
+     *  in cycle B, the channel 1 output is disabled.*/
+    TCC_RAMP_RAMP2
 };
 
 /**
@@ -1022,14 +1022,14 @@ enum tcc_ramp {
  *  the index 0 represents cycle A and 1 represents cycle B.
  */
 enum tcc_ramp_index {
-	/** Default, cycle index toggles. */
-	TCC_RAMP_INDEX_DEFAULT,
-	/** Force next cycle to be cycle B (set to 1) */
-	TCC_RAMP_INDEX_FORCE_B,
-	/** Force next cycle to be cycle A (clear to 0) */
-	TCC_RAMP_INDEX_FORCE_A,
-	/** Force next cycle keeping the same as current */
-	TCC_RAMP_INDEX_FORCE_KEEP
+    /** Default, cycle index toggles. */
+    TCC_RAMP_INDEX_DEFAULT,
+    /** Force next cycle to be cycle B (set to 1) */
+    TCC_RAMP_INDEX_FORCE_B,
+    /** Force next cycle to be cycle A (clear to 0) */
+    TCC_RAMP_INDEX_FORCE_A,
+    /** Force next cycle keeping the same as current */
+    TCC_RAMP_INDEX_FORCE_KEEP
 };
 
 /**
@@ -1038,10 +1038,10 @@ enum tcc_ramp_index {
  * Used when enabling or disabling output inversion.
  */
 enum tcc_output_invertion {
-	/** Output inversion not to be enabled */
-	TCC_OUTPUT_INVERTION_DISABLE,
-	/** Invert the output from WO[x] */
-	TCC_OUTPUT_INVERTION_ENABLE
+    /** Output inversion not to be enabled */
+    TCC_OUTPUT_INVERTION_DISABLE,
+    /** Invert the output from WO[x] */
+    TCC_OUTPUT_INVERTION_ENABLE
 };
 
 /**
@@ -1051,17 +1051,17 @@ enum tcc_output_invertion {
  * should be restarted.
  */
 enum tcc_reload_action {
-	/** The counter is reloaded/reset on the next GCLK and starts
-	 * counting on the prescaler clock
-	 */
-	TCC_RELOAD_ACTION_GCLK,
-	/** The counter is reloaded/reset on the next prescaler clock
-	 */
-	TCC_RELOAD_ACTION_PRESC,
-	/** The counter is reloaded/reset on the next GCLK, and the
-	 * prescaler is restarted as well
-	 */
-	TCC_RELOAD_ACTION_RESYNC
+    /** The counter is reloaded/reset on the next GCLK and starts
+     * counting on the prescaler clock
+     */
+    TCC_RELOAD_ACTION_GCLK,
+    /** The counter is reloaded/reset on the next prescaler clock
+     */
+    TCC_RELOAD_ACTION_PRESC,
+    /** The counter is reloaded/reset on the next GCLK, and the
+     * prescaler is restarted as well
+     */
+    TCC_RELOAD_ACTION_RESYNC
 };
 
 
@@ -1073,22 +1073,22 @@ enum tcc_reload_action {
  * module to operate TCC at a slower clock rate.
  */
 enum tcc_clock_prescaler {
-	/** Divide clock by 1 */
-	TCC_CLOCK_PRESCALER_DIV1,
-	/** Divide clock by 2 */
-	TCC_CLOCK_PRESCALER_DIV2,
-	/** Divide clock by 4 */
-	TCC_CLOCK_PRESCALER_DIV4,
-	/** Divide clock by 8 */
-	TCC_CLOCK_PRESCALER_DIV8,
-	/** Divide clock by 16 */
-	TCC_CLOCK_PRESCALER_DIV16,
-	/** Divide clock by 64 */
-	TCC_CLOCK_PRESCALER_DIV64,
-	/** Divide clock by 256 */
-	TCC_CLOCK_PRESCALER_DIV256,
-	/** Divide clock by 1024 */
-	TCC_CLOCK_PRESCALER_DIV1024
+    /** Divide clock by 1 */
+    TCC_CLOCK_PRESCALER_DIV1,
+    /** Divide clock by 2 */
+    TCC_CLOCK_PRESCALER_DIV2,
+    /** Divide clock by 4 */
+    TCC_CLOCK_PRESCALER_DIV4,
+    /** Divide clock by 8 */
+    TCC_CLOCK_PRESCALER_DIV8,
+    /** Divide clock by 16 */
+    TCC_CLOCK_PRESCALER_DIV16,
+    /** Divide clock by 64 */
+    TCC_CLOCK_PRESCALER_DIV64,
+    /** Divide clock by 256 */
+    TCC_CLOCK_PRESCALER_DIV256,
+    /** Divide clock by 1024 */
+    TCC_CLOCK_PRESCALER_DIV1024
 };
 
 /**
@@ -1097,10 +1097,10 @@ enum tcc_clock_prescaler {
  * Used when selecting the Timer/Counter count direction.
  */
 enum tcc_count_direction {
-	/** Timer should count upward */
-	TCC_COUNT_DIRECTION_UP,
-	/** Timer should count downward */
-	TCC_COUNT_DIRECTION_DOWN,
+    /** Timer should count upward */
+    TCC_COUNT_DIRECTION_UP,
+    /** Timer should count downward */
+    TCC_COUNT_DIRECTION_DOWN,
 };
 
 #ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
@@ -1110,15 +1110,15 @@ enum tcc_count_direction {
  * Used when selecting the Timer/Counter overflow DMA request mode.
  */
 enum tcc_count_overflow_dma_trigger_mode {
-	/** TCC generates a DMA request on each cycle when an update condition 
-	 * is detected
-	 */
-	TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE,
-	/** When an update condition is detected, the TCC generates a DMA trigger 
-	 * on the cycle following the DMA One-Shot Command written to the Control 
-	 * B register
-	 */
-	TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_ONE_SHOT,
+    /** TCC generates a DMA request on each cycle when an update condition
+     * is detected
+     */
+    TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE,
+    /** When an update condition is detected, the TCC generates a DMA trigger
+     * on the cycle following the DMA One-Shot Command written to the Control
+     * B register
+     */
+    TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_ONE_SHOT,
 };
 #endif
 
@@ -1128,53 +1128,53 @@ enum tcc_count_overflow_dma_trigger_mode {
  * Event action to perform when the module is triggered by events.
  */
 enum tcc_event_action {
-	/** No event action */
-	TCC_EVENT_ACTION_OFF,
-	/** Stop counting, the counter will maintain its current value, waveforms
-	 *  are set to a defined Non-Recoverable State output
-	 *  (\ref tcc_non_recoverable_state_output). */
-	TCC_EVENT_ACTION_STOP,
-	/** Re-trigger counter on event, may generate an event if the re-trigger
-	 *  event output is enabled.
-	 *  \note When re-trigger event action is enabled, enabling the counter
-	 *        will not start until the next incoming event appears. */
-	TCC_EVENT_ACTION_RETRIGGER,
-
-	/** Start counter when previously stopped.
-	 * Start counting on the event rising edge. Further events will not
-	 * restart the counter;
-	 * the counter keeps on counting using prescaled GCLK_TCCx, until it
-	 * reaches TOP or Zero
-	 * depending on the direction. */
-	TCC_EVENT_ACTION_START,
-	/** Count events; i.e. Increment or decrement depending on count
-	 * direction. */
-	TCC_EVENT_ACTION_COUNT_EVENT,
-	/** The event source must be an asynchronous event, input value will
-	 *  overrides the direction settings (input low: counting up, input high:
-	 *  counting down). */
-	TCC_EVENT_ACTION_DIR_CONTROL,
-	/** Increment the counter on event, irrespective of count direction */
-	TCC_EVENT_ACTION_INCREMENT,
-	/** Decrement the counter on event, irrespective of count direction */
-	TCC_EVENT_ACTION_DECREMENT,
-	/** Count during active state of asynchronous event. In this case,
-	* depending	on the count direction, the  count will be incremented 
-	* or decremented on each prescaled GCLK_TCCx, as long as the input
-	* event remains active. */
-	TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
-
-	/** Store period in capture register 0, pulse width in capture
-	 *  register 1
-	 */
-	TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
-	/** Store pulse width in capture register 0, period in capture
-	 *  register 1
-	 */
-	TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
-
-	/** Generate Non-Recoverable Fault on event */
-	TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT,
+    /** No event action */
+    TCC_EVENT_ACTION_OFF,
+    /** Stop counting, the counter will maintain its current value, waveforms
+     *  are set to a defined Non-Recoverable State output
+     *  (\ref tcc_non_recoverable_state_output). */
+    TCC_EVENT_ACTION_STOP,
+    /** Re-trigger counter on event, may generate an event if the re-trigger
+     *  event output is enabled.
+     *  \note When re-trigger event action is enabled, enabling the counter
+     *        will not start until the next incoming event appears. */
+    TCC_EVENT_ACTION_RETRIGGER,
+
+    /** Start counter when previously stopped.
+     * Start counting on the event rising edge. Further events will not
+     * restart the counter;
+     * the counter keeps on counting using prescaled GCLK_TCCx, until it
+     * reaches TOP or Zero
+     * depending on the direction. */
+    TCC_EVENT_ACTION_START,
+    /** Count events; i.e. Increment or decrement depending on count
+     * direction. */
+    TCC_EVENT_ACTION_COUNT_EVENT,
+    /** The event source must be an asynchronous event, input value will
+     *  overrides the direction settings (input low: counting up, input high:
+     *  counting down). */
+    TCC_EVENT_ACTION_DIR_CONTROL,
+    /** Increment the counter on event, irrespective of count direction */
+    TCC_EVENT_ACTION_INCREMENT,
+    /** Decrement the counter on event, irrespective of count direction */
+    TCC_EVENT_ACTION_DECREMENT,
+    /** Count during active state of asynchronous event. In this case,
+    * depending on the count direction, the  count will be incremented
+    * or decremented on each prescaled GCLK_TCCx, as long as the input
+    * event remains active. */
+    TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
+
+    /** Store period in capture register 0, pulse width in capture
+     *  register 1
+     */
+    TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
+    /** Store pulse width in capture register 0, period in capture
+     *  register 1
+     */
+    TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
+
+    /** Generate Non-Recoverable Fault on event */
+    TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT,
 };
 
 
@@ -1184,22 +1184,22 @@ enum tcc_event_action {
  * Event action to perform when the module is triggered by event0.
  */
 enum tcc_event0_action {
-	/** No event action */
-	TCC_EVENT0_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
-	/** Re-trigger Counter on event */
-	TCC_EVENT0_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
-	/** Count events (increment or decrement, depending on count direction)
-	 */
-	TCC_EVENT0_ACTION_COUNT_EVENT           = TCC_EVENT_ACTION_COUNT_EVENT,
-	/** Start counter on event */
-	TCC_EVENT0_ACTION_START                 = TCC_EVENT_ACTION_START,
-	/** Increment counter on event */
-	TCC_EVENT0_ACTION_INCREMENT             = TCC_EVENT_ACTION_INCREMENT,
-	/** Count during active state of asynchronous event */
-	TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE   = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
-
-	/** Generate Non-Recoverable Fault on event */
-	TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
+    /** No event action */
+    TCC_EVENT0_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
+    /** Re-trigger Counter on event */
+    TCC_EVENT0_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
+    /** Count events (increment or decrement, depending on count direction)
+     */
+    TCC_EVENT0_ACTION_COUNT_EVENT           = TCC_EVENT_ACTION_COUNT_EVENT,
+    /** Start counter on event */
+    TCC_EVENT0_ACTION_START                 = TCC_EVENT_ACTION_START,
+    /** Increment counter on event */
+    TCC_EVENT0_ACTION_INCREMENT             = TCC_EVENT_ACTION_INCREMENT,
+    /** Count during active state of asynchronous event */
+    TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE   = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE,
+
+    /** Generate Non-Recoverable Fault on event */
+    TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
 };
 
 /**
@@ -1208,32 +1208,32 @@ enum tcc_event0_action {
  * Event action to perform when the module is triggered by event1.
  */
 enum tcc_event1_action {
-	/** No event action */
-	TCC_EVENT1_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
-	/** Re-trigger Counter on event */
-	TCC_EVENT1_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
-	/** The event source must be an asynchronous event, and the input value
-	 *  will override the direction settings.
-	 *  If TCEINVx is 0 and input event is LOW: counter will count up.
-	 *  If TCEINVx is 0 and input event is HIGH: counter will count down.
-	 */
-	TCC_EVENT1_ACTION_DIR_CONTROL           = TCC_EVENT_ACTION_DIR_CONTROL,
-	/** Stop counter on event */
-	TCC_EVENT1_ACTION_STOP                  = TCC_EVENT_ACTION_STOP,
-	/** Decrement on event */
-	TCC_EVENT1_ACTION_DECREMENT             = TCC_EVENT_ACTION_DECREMENT,
-
-	/** Store period in capture register 0, pulse width in capture
-	 *  register 1
-	 */
-	TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE  = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
-	/** Store pulse width in capture register 0, period in capture
-	 *  register 1
-	 */
-	TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE  = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
-
-	/** Generate Non-Recoverable Fault on event */
-	TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
+    /** No event action */
+    TCC_EVENT1_ACTION_OFF                   = TCC_EVENT_ACTION_OFF,
+    /** Re-trigger Counter on event */
+    TCC_EVENT1_ACTION_RETRIGGER             = TCC_EVENT_ACTION_RETRIGGER,
+    /** The event source must be an asynchronous event, and the input value
+     *  will override the direction settings.
+     *  If TCEINVx is 0 and input event is LOW: counter will count up.
+     *  If TCEINVx is 0 and input event is HIGH: counter will count down.
+     */
+    TCC_EVENT1_ACTION_DIR_CONTROL           = TCC_EVENT_ACTION_DIR_CONTROL,
+    /** Stop counter on event */
+    TCC_EVENT1_ACTION_STOP                  = TCC_EVENT_ACTION_STOP,
+    /** Decrement on event */
+    TCC_EVENT1_ACTION_DECREMENT             = TCC_EVENT_ACTION_DECREMENT,
+
+    /** Store period in capture register 0, pulse width in capture
+     *  register 1
+     */
+    TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE  = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE,
+    /** Store pulse width in capture register 0, period in capture
+     *  register 1
+     */
+    TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE  = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE,
+
+    /** Generate Non-Recoverable Fault on event */
+    TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT
 };
 
 /**
@@ -1242,15 +1242,15 @@ enum tcc_event1_action {
  * This enum is used to define the point at which the counter event is generated.
  */
 enum tcc_event_generation_selection {
-	/** Counter Event is generated when a new counter cycle starts */
-	TCC_EVENT_GENERATION_SELECTION_START,
-	/** Counter Event is generated when a counter cycle ends */
-	TCC_EVENT_GENERATION_SELECTION_END,
-	/** Counter Event is generated when a counter cycle ends, except for the
-	 *  first and last cycles */
-	TCC_EVENT_GENERATION_SELECTION_BETWEEN,
-	/** Counter Event is generated when a new counter cycle starts or ends */
-	TCC_EVENT_GENERATION_SELECTION_BOUNDARY
+    /** Counter Event is generated when a new counter cycle starts */
+    TCC_EVENT_GENERATION_SELECTION_START,
+    /** Counter Event is generated when a counter cycle ends */
+    TCC_EVENT_GENERATION_SELECTION_END,
+    /** Counter Event is generated when a counter cycle ends, except for the
+     *  first and last cycles */
+    TCC_EVENT_GENERATION_SELECTION_BETWEEN,
+    /** Counter Event is generated when a new counter cycle starts or ends */
+    TCC_EVENT_GENERATION_SELECTION_BOUNDARY
 };
 
 /**
@@ -1259,180 +1259,180 @@ enum tcc_event_generation_selection {
  * To set a timer channel either in compare or in capture mode.
  */
 enum tcc_channel_function {
-	/** TCC channel performs compare operation */
-	TCC_CHANNEL_FUNCTION_COMPARE,
-	/** TCC channel performs capture operation */
-	TCC_CHANNEL_FUNCTION_CAPTURE
+    /** TCC channel performs compare operation */
+    TCC_CHANNEL_FUNCTION_COMPARE,
+    /** TCC channel performs capture operation */
+    TCC_CHANNEL_FUNCTION_CAPTURE
 };
 
 /**
  * \brief TCC (recoverable) fault Halt action
  */
 enum tcc_fault_halt_action {
-	/** Halt action disabled. */
-	TCC_FAULT_HALT_ACTION_DISABLE,
-	/** Hardware halt action, counter is halted until restart */
-	TCC_FAULT_HALT_ACTION_HW_HALT,
-	/** Software halt action, counter is halted until fault bit cleared */
-	TCC_FAULT_HALT_ACTION_SW_HALT,
-	/** Non-Recoverable fault, force output to pre-defined level */
-	TCC_FAULT_HALT_ACTION_NON_RECOVERABLE
+    /** Halt action disabled. */
+    TCC_FAULT_HALT_ACTION_DISABLE,
+    /** Hardware halt action, counter is halted until restart */
+    TCC_FAULT_HALT_ACTION_HW_HALT,
+    /** Software halt action, counter is halted until fault bit cleared */
+    TCC_FAULT_HALT_ACTION_SW_HALT,
+    /** Non-Recoverable fault, force output to pre-defined level */
+    TCC_FAULT_HALT_ACTION_NON_RECOVERABLE
 };
 
 /**
  * \brief TCC (recoverable) fault Capture action
  */
 enum tcc_fault_capture_action {
-	/** Capture disabled */
-	TCC_FAULT_CAPTURE_DISABLE,
-	/** Capture on Fault, each value is captured */
-	TCC_FAULT_CAPTURE_EACH,
-	/** Capture the minimum detection, but notify on smaller ones */
-	TCC_FAULT_CAPTURE_MINIMUM,
-	/** Capture the maximum detection, but notify on bigger ones */
-	TCC_FAULT_CAPTURE_MAXIMUM,
-	/** Capture if the value is smaller than last, notify event or interrupt
-	 *  if previous stamp is confirmed to be "local minimum" (not bigger than
-	 *  current stamp). */
-	TCC_FAULT_CAPTURE_SMALLER,
-	/** Capture if the value is bigger than last, notify event or interrupt
-	 *  if previous stamp is confirmed to be "local maximum" (not smaller than
-	 *  current stamp). */
-	TCC_FAULT_CAPTURE_BIGGER,
-	/** Capture if the time stamps changes its increment direction */
-	TCC_FAULT_CAPTURE_CHANGE
+    /** Capture disabled */
+    TCC_FAULT_CAPTURE_DISABLE,
+    /** Capture on Fault, each value is captured */
+    TCC_FAULT_CAPTURE_EACH,
+    /** Capture the minimum detection, but notify on smaller ones */
+    TCC_FAULT_CAPTURE_MINIMUM,
+    /** Capture the maximum detection, but notify on bigger ones */
+    TCC_FAULT_CAPTURE_MAXIMUM,
+    /** Capture if the value is smaller than last, notify event or interrupt
+     *  if previous stamp is confirmed to be "local minimum" (not bigger than
+     *  current stamp). */
+    TCC_FAULT_CAPTURE_SMALLER,
+    /** Capture if the value is bigger than last, notify event or interrupt
+     *  if previous stamp is confirmed to be "local maximum" (not smaller than
+     *  current stamp). */
+    TCC_FAULT_CAPTURE_BIGGER,
+    /** Capture if the time stamps changes its increment direction */
+    TCC_FAULT_CAPTURE_CHANGE
 };
 
 /**
  * \brief Capture Channel triggered by TCC (recoverable) fault
  */
 enum tcc_fault_capture_channel {
-	/** Recoverable fault triggers channel 0 capture operation */
-	TCC_FAULT_CAPTURE_CHANNEL_0,
-	/** Recoverable fault triggers channel 1 capture operation */
-	TCC_FAULT_CAPTURE_CHANNEL_1,
-	/** Recoverable fault triggers channel 2 capture operation */
-	TCC_FAULT_CAPTURE_CHANNEL_2,
-	/** Recoverable fault triggers channel 3 capture operation */
-	TCC_FAULT_CAPTURE_CHANNEL_3
+    /** Recoverable fault triggers channel 0 capture operation */
+    TCC_FAULT_CAPTURE_CHANNEL_0,
+    /** Recoverable fault triggers channel 1 capture operation */
+    TCC_FAULT_CAPTURE_CHANNEL_1,
+    /** Recoverable fault triggers channel 2 capture operation */
+    TCC_FAULT_CAPTURE_CHANNEL_2,
+    /** Recoverable fault triggers channel 3 capture operation */
+    TCC_FAULT_CAPTURE_CHANNEL_3
 };
 
 /**
  * \brief TCC (recoverable) fault Input Source
  */
 enum tcc_fault_source {
-	/** Fault input is disabled */
-	TCC_FAULT_SOURCE_DISABLE,
-	/** Match Capture Event x (x=0,1) input */
-	TCC_FAULT_SOURCE_ENABLE,
-	/** Inverted MCEx (x=0,1) event input */
-	TCC_FAULT_SOURCE_INVERT,
-	/** Alternate fault (A or B) state at the end of the previous period */
-	TCC_FAULT_SOURCE_ALTFAULT
+    /** Fault input is disabled */
+    TCC_FAULT_SOURCE_DISABLE,
+    /** Match Capture Event x (x=0,1) input */
+    TCC_FAULT_SOURCE_ENABLE,
+    /** Inverted MCEx (x=0,1) event input */
+    TCC_FAULT_SOURCE_INVERT,
+    /** Alternate fault (A or B) state at the end of the previous period */
+    TCC_FAULT_SOURCE_ALTFAULT
 };
 
 /**
  * \brief TCC (recoverable) fault Input Blanking Start Point
  */
 enum tcc_fault_blanking {
-	/** No blanking */
-	TCC_FAULT_BLANKING_DISABLE,
-	/** Blanking applied from rising edge of the output waveform */
-	TCC_FAULT_BLANKING_RISING_EDGE,
-	/** Blanking applied from falling edge of the output waveform */
-	TCC_FAULT_BLANKING_FALLING_EDGE,
-	/** Blanking applied from each toggle of the output waveform */
-	TCC_FAULT_BLANKING_BOTH_EDGE
+    /** No blanking */
+    TCC_FAULT_BLANKING_DISABLE,
+    /** Blanking applied from rising edge of the output waveform */
+    TCC_FAULT_BLANKING_RISING_EDGE,
+    /** Blanking applied from falling edge of the output waveform */
+    TCC_FAULT_BLANKING_FALLING_EDGE,
+    /** Blanking applied from each toggle of the output waveform */
+    TCC_FAULT_BLANKING_BOTH_EDGE
 };
 
 /**
  * \brief TCC (recoverable) fault Input Qualification Action
  */
 enum tcc_fault_qualification {
-	/** The input is not disabled on compare condition */
-	TCC_FAULT_QUALIFICATION_DISABLE,
-	/** The input is disabled when match output signal is at inactive level */
-	TCC_FAULT_QUALIFICATION_BY_OUTPUT
+    /** The input is not disabled on compare condition */
+    TCC_FAULT_QUALIFICATION_DISABLE,
+    /** The input is disabled when match output signal is at inactive level */
+    TCC_FAULT_QUALIFICATION_BY_OUTPUT
 };
 
 /**
  * \brief TCC (recoverable) fault Output Keep Action
  */
 enum tcc_fault_keep {
-	/** Disable keeping, wave output released as soon as fault is released */
-	TCC_FAULT_KEEP_DISABLE,
-	/** Keep wave output until end of TCC cycle */
-	TCC_FAULT_KEEP_TILL_END
+    /** Disable keeping, wave output released as soon as fault is released */
+    TCC_FAULT_KEEP_DISABLE,
+    /** Keep wave output until end of TCC cycle */
+    TCC_FAULT_KEEP_TILL_END
 };
 
 /**
  * \brief TCC Non-recoverable State Outupt
  */
 enum tcc_fault_state_output {
-	/** Non-recoverable fault output is tri-stated */
-	TCC_FAULT_STATE_OUTPUT_OFF,
-	/** Non-recoverable fault force output 0 */
-	TCC_FAULT_STATE_OUTPUT_0,
-	/** Non-recoverable fault force output 1 */
-	TCC_FAULT_STATE_OUTPUT_1
+    /** Non-recoverable fault output is tri-stated */
+    TCC_FAULT_STATE_OUTPUT_OFF,
+    /** Non-recoverable fault force output 0 */
+    TCC_FAULT_STATE_OUTPUT_0,
+    /** Non-recoverable fault force output 1 */
+    TCC_FAULT_STATE_OUTPUT_1
 };
 
 /**
  * \brief TCC (recoverable) fault Restart Action
  */
 enum tcc_fault_restart {
-	/** Restart Action disabled */
-	TCC_FAULT_RESTART_DISABLE,
-	/** Restart Action enabled */
-	TCC_FAULT_RESTART_ENABLE
+    /** Restart Action disabled */
+    TCC_FAULT_RESTART_DISABLE,
+    /** Restart Action enabled */
+    TCC_FAULT_RESTART_ENABLE
 };
 
 /**
  * \brief Configuration struct for TCC module recoverable fault
  */
 struct tcc_recoverable_fault_config {
-	/** Fault filter value applied on MCEx event input line (0x0 ~ 0xF).
-	 *  Must be 0 when MCEx event is used as synchronous event.
-	 *  Apply to both recoverable and non-recoverable fault. */
-	uint8_t filter_value;
-	/** Fault blanking value (0 ~ 255), disable input source for several TCC
-	 * clocks after the detection of the waveform edge */
-	uint8_t blanking_cycles;
-
-	/** Set to \c true to enable restart action */
-	bool restart;
-	/** Set to \c true to enable keep action (keep until end of TCC cycle) */
-	bool keep;
-
-	/** Set to \c true to enable input qualification
-	 *  (disable input when output is inactive) */
-	bool qualification;
-
-	/** Specifies if the event input generates recoverable Fault.
-	 *  The event system channel connected to MCEx event input must be
-	 *  configured as asynchronous.
-	 */
-	enum tcc_fault_source source;
-	/** Fault Blanking Start Point for recoverable Fault */
-	enum tcc_fault_blanking blanking;
-
-	/** Halt action for recoverable Fault */
-	enum tcc_fault_halt_action halt_action;
-	/** Capture action for recoverable Fault */
-	enum tcc_fault_capture_action capture_action;
-	/** Channel triggered by recoverable Fault */
-	enum tcc_fault_capture_channel capture_channel;
+    /** Fault filter value applied on MCEx event input line (0x0 ~ 0xF).
+     *  Must be 0 when MCEx event is used as synchronous event.
+     *  Apply to both recoverable and non-recoverable fault. */
+    uint8_t filter_value;
+    /** Fault blanking value (0 ~ 255), disable input source for several TCC
+     * clocks after the detection of the waveform edge */
+    uint8_t blanking_cycles;
+
+    /** Set to \c true to enable restart action */
+    bool restart;
+    /** Set to \c true to enable keep action (keep until end of TCC cycle) */
+    bool keep;
+
+    /** Set to \c true to enable input qualification
+     *  (disable input when output is inactive) */
+    bool qualification;
+
+    /** Specifies if the event input generates recoverable Fault.
+     *  The event system channel connected to MCEx event input must be
+     *  configured as asynchronous.
+     */
+    enum tcc_fault_source source;
+    /** Fault Blanking Start Point for recoverable Fault */
+    enum tcc_fault_blanking blanking;
+
+    /** Halt action for recoverable Fault */
+    enum tcc_fault_halt_action halt_action;
+    /** Capture action for recoverable Fault */
+    enum tcc_fault_capture_action capture_action;
+    /** Channel triggered by recoverable Fault */
+    enum tcc_fault_capture_channel capture_channel;
 };
 
 /**
  * \brief Configuration struct for TCC module non-recoverable fault
  */
 struct tcc_non_recoverable_fault_config {
-	/** Fault filter value applied on TCEx event input line (0x0 ~ 0xF).
-	 *  Must be 0 when TCEx event is used as synchronous event. */
-	uint8_t filter_value;
-	/** Output */
-	enum tcc_fault_state_output output;
+    /** Fault filter value applied on TCEx event input line (0x0 ~ 0xF).
+     *  Must be 0 when TCEx event is used as synchronous event. */
+    uint8_t filter_value;
+    /** Output */
+    enum tcc_fault_state_output output;
 };
 
 /**
@@ -1441,12 +1441,12 @@ struct tcc_non_recoverable_fault_config {
  * For configuring an input event.
  */
 struct tcc_input_event_config {
-	/** Event action on incoming event */
-	enum tcc_event_action action;
-	/** Modify event action */
-	bool modify_action;
-	/** Invert incoming event input line */
-	bool invert;
+    /** Event action on incoming event */
+    enum tcc_event_action action;
+    /** Modify event action */
+    bool modify_action;
+    /** Invert incoming event input line */
+    bool invert;
 };
 
 /**
@@ -1455,13 +1455,13 @@ struct tcc_input_event_config {
  * Structure used for configuring an output event.
  */
 struct tcc_output_event_config {
-	/** It decides which part of the counter cycle the counter event output
-	 * is generated */
-	enum tcc_event_generation_selection generation_selection;
-	/** A switch to allow enable/disable of events, without modifying the
-	 *  event output configuration
-	 */
-	bool modify_generation_selection;
+    /** It decides which part of the counter cycle the counter event output
+     * is generated */
+    enum tcc_event_generation_selection generation_selection;
+    /** A switch to allow enable/disable of events, without modifying the
+     *  event output configuration
+     */
+    bool modify_generation_selection;
 };
 
 /**
@@ -1470,29 +1470,29 @@ struct tcc_output_event_config {
  * Event flags for the \ref tcc_enable_events() and \ref tcc_disable_events().
  */
 struct tcc_events {
-	/** Input events configuration */
-	struct tcc_input_event_config input_config[2];
-	/** Output event configuration */
-	struct tcc_output_event_config output_config;
-
-	/** Perform the configured event action when an incoming event is
-	 *  signalled */
-	bool on_input_event_perform_action[2];
-
-	/** Perform the configured event action when an incoming channel event is
-	 *  signalled */
-	bool on_event_perform_channel_action[TCC_NUM_CHANNELS];
-	/** Generate an output event on a channel capture/match.
-	 *  Specify which channels will generate events */
-	bool generate_event_on_channel[TCC_NUM_CHANNELS];
-
-	/** Generate an output event on counter overflow/underflow */
-	bool generate_event_on_counter_overflow;
-	/** Generate an output event on counter retrigger */
-	bool generate_event_on_counter_retrigger;
-	/** Generate an output event on counter boundary.
-	 *  See \ref tcc_event_output_action. */
-	bool generate_event_on_counter_event;
+    /** Input events configuration */
+    struct tcc_input_event_config input_config[2];
+    /** Output event configuration */
+    struct tcc_output_event_config output_config;
+
+    /** Perform the configured event action when an incoming event is
+     *  signalled */
+    bool on_input_event_perform_action[2];
+
+    /** Perform the configured event action when an incoming channel event is
+     *  signalled */
+    bool on_event_perform_channel_action[TCC_NUM_CHANNELS];
+    /** Generate an output event on a channel capture/match.
+     *  Specify which channels will generate events */
+    bool generate_event_on_channel[TCC_NUM_CHANNELS];
+
+    /** Generate an output event on counter overflow/underflow */
+    bool generate_event_on_counter_overflow;
+    /** Generate an output event on counter retrigger */
+    bool generate_event_on_counter_retrigger;
+    /** Generate an output event on counter boundary.
+     *  See \ref tcc_event_output_action. */
+    bool generate_event_on_counter_event;
 };
 
 /**
@@ -1501,32 +1501,32 @@ struct tcc_events {
  * Structure for configuring a TCC as a counter.
  */
 struct tcc_counter_config {
-	/** Value to initialize the count register */
-	uint32_t count;
-	/** Period/top and period/top buffer values for counter */
-	uint32_t period;
-
-	/** When \c true, the counter will be stopped on the next hardware or
-	 * software re-trigger event or overflow/underflow
-	 */
-	bool oneshot;
-
-#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER	
-	/** Counter overflow trigger a DMA request mode */
-	enum tcc_count_overflow_dma_trigger_mode dma_trigger_mode;
+    /** Value to initialize the count register */
+    uint32_t count;
+    /** Period/top and period/top buffer values for counter */
+    uint32_t period;
+
+    /** When \c true, the counter will be stopped on the next hardware or
+     * software re-trigger event or overflow/underflow
+     */
+    bool oneshot;
+
+#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER
+    /** Counter overflow trigger a DMA request mode */
+    enum tcc_count_overflow_dma_trigger_mode dma_trigger_mode;
 #endif
 
-	/** Specifies the direction for the TCC to count */
-	enum tcc_count_direction direction;
-
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Specifies the prescaler value for GCLK_TCC */
-	enum tcc_clock_prescaler clock_prescaler;
-	/** Specifies the reload or reset time of the counter and prescaler
-	 *  resynchronization on a re-trigger event for the TCC
-	 */
-	enum tcc_reload_action reload_action;
+    /** Specifies the direction for the TCC to count */
+    enum tcc_count_direction direction;
+
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** Specifies the prescaler value for GCLK_TCC */
+    enum tcc_clock_prescaler clock_prescaler;
+    /** Specifies the reload or reset time of the counter and prescaler
+     *  resynchronization on a re-trigger event for the TCC
+     */
+    enum tcc_reload_action reload_action;
 };
 
 /**
@@ -1535,8 +1535,8 @@ struct tcc_counter_config {
  * Structure used when configuring TCC channels in capture mode.
  */
 struct tcc_capture_config {
-	/** Channel functions selection (capture/match) */
-	enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
+    /** Channel functions selection (capture/match) */
+    enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
 };
 
 /**
@@ -1546,18 +1546,18 @@ struct tcc_capture_config {
  * operation and wave generation.
  */
 struct tcc_match_wave_config {
-	/** Channel functions selection (capture/match) */
-	enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
-
-	/** Specifies polarity for match output waveform generation */
-	enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS];
-	/** Specifies which waveform generation mode to use */
-	enum tcc_wave_generation wave_generation;
-	/** Specifies Ramp mode for waveform generation */
-	enum tcc_ramp wave_ramp;
-
-	/** Value to be used for compare match on each channel */
-	uint32_t match[TCC_NUM_CHANNELS];
+    /** Channel functions selection (capture/match) */
+    enum tcc_channel_function channel_function[TCC_NUM_CHANNELS];
+
+    /** Specifies polarity for match output waveform generation */
+    enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS];
+    /** Specifies which waveform generation mode to use */
+    enum tcc_wave_generation wave_generation;
+    /** Specifies Ramp mode for waveform generation */
+    enum tcc_ramp wave_ramp;
+
+    /** Value to be used for compare match on each channel */
+    uint32_t match[TCC_NUM_CHANNELS];
 };
 
 /**
@@ -1566,15 +1566,15 @@ struct tcc_match_wave_config {
  * This structure is used to specify the waveform extension features for TCC.
  */
 struct tcc_wave_extension_config {
-	/** Configuration for recoverable faults */
-	struct tcc_recoverable_fault_config
-			recoverable_fault[TCC_NUM_FAULTS];
-	/** Configuration for non-recoverable faults */
-	struct tcc_non_recoverable_fault_config
-			non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS];
-
-	/** Invert waveform final outputs lines */
-	bool invert[TCC_NUM_WAVE_OUTPUTS];
+    /** Configuration for recoverable faults */
+    struct tcc_recoverable_fault_config
+            recoverable_fault[TCC_NUM_FAULTS];
+    /** Configuration for non-recoverable faults */
+    struct tcc_non_recoverable_fault_config
+            non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS];
+
+    /** Invert waveform final outputs lines */
+    bool invert[TCC_NUM_WAVE_OUTPUTS];
 };
 
 /**
@@ -1583,12 +1583,12 @@ struct tcc_wave_extension_config {
  * Structure which is used when taking wave output from TCC.
  */
 struct tcc_pins_config {
-	/** Specifies pin output for each channel */
-	uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
-	/** Specifies MUX setting for each output channel pin */
-	uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS];
-	/** When \c true, PWM output pin for the given channel is enabled */
-	bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
+    /** Specifies pin output for each channel */
+    uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
+    /** Specifies MUX setting for each output channel pin */
+    uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS];
+    /** When \c true, PWM output pin for the given channel is enabled */
+    bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS];
 };
 
 /**
@@ -1599,40 +1599,40 @@ struct tcc_pins_config {
  * modified by the user application.
  */
 struct tcc_config {
-	/** Structure for configuring TCC base timer/counter */
-	struct tcc_counter_config counter;
-	/** TCC match/capture configurations */
-	union {
-		/** Helps to configure a TCC channel in capture mode */
-		struct tcc_capture_config capture;
-		/** For configuring a TCC channel in compare mode */
-		struct tcc_match_wave_config compare;
-		/** Serves the same purpose as compare. Used as an alias for
-		 * compare,
-		 *  when a TCC channel is configured for wave generation */
-		struct tcc_match_wave_config wave;
-	};
-
-	/** Structure for configuring TCC waveform extension */
-	struct tcc_wave_extension_config wave_ext;
-
-	/** Structure for configuring TCC output pins */
-	struct tcc_pins_config pins;
-
-	/** Set to \c true to enable double buffering write. When enabled any write
-	 *  through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and
-	 *  \ref tcc_set_pattern() will direct to the buffer register as buffered
-	 *  value, and the buffered value will be committed to effective register
-	 *  on UPDATE condition, if update is not locked.
-	 *
-	 *  \note The init values in \ref tcc_config for \ref tcc_init are always
-	 *        filled to effective registers, no matter if double buffering is
-	 *        enabled or not.
-	 */
-	bool double_buffering_enabled;
-
-	/** When \c true the module is enabled during standby */
-	bool run_in_standby;
+    /** Structure for configuring TCC base timer/counter */
+    struct tcc_counter_config counter;
+    /** TCC match/capture configurations */
+    union {
+        /** Helps to configure a TCC channel in capture mode */
+        struct tcc_capture_config capture;
+        /** For configuring a TCC channel in compare mode */
+        struct tcc_match_wave_config compare;
+        /** Serves the same purpose as compare. Used as an alias for
+         * compare,
+         *  when a TCC channel is configured for wave generation */
+        struct tcc_match_wave_config wave;
+    };
+
+    /** Structure for configuring TCC waveform extension */
+    struct tcc_wave_extension_config wave_ext;
+
+    /** Structure for configuring TCC output pins */
+    struct tcc_pins_config pins;
+
+    /** Set to \c true to enable double buffering write. When enabled any write
+     *  through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and
+     *  \ref tcc_set_pattern() will direct to the buffer register as buffered
+     *  value, and the buffered value will be committed to effective register
+     *  on UPDATE condition, if update is not locked.
+     *
+     *  \note The init values in \ref tcc_config for \ref tcc_init are always
+     *        filled to effective registers, no matter if double buffering is
+     *        enabled or not.
+     */
+    bool double_buffering_enabled;
+
+    /** When \c true the module is enabled during standby */
+    bool run_in_standby;
 };
 
 #if TCC_ASYNC == true
@@ -1653,25 +1653,25 @@ typedef void (*tcc_callback_t)(struct tcc_module *const module);
  *       application; they are reserved only for module-internal use.
  */
 struct tcc_module {
-	/** Hardware module pointer of the associated Timer/Counter peripheral. */
-	Tcc *hw;
+    /** Hardware module pointer of the associated Timer/Counter peripheral. */
+    Tcc *hw;
 
 #  if TCC_ASYNC == true
-	/** Array of callbacks */
-	tcc_callback_t callback[TCC_CALLBACK_N];
-	/** Bit mask for callbacks registered */
-	uint32_t register_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint32_t enable_callback_mask;
+    /** Array of callbacks */
+    tcc_callback_t callback[TCC_CALLBACK_N];
+    /** Bit mask for callbacks registered */
+    uint32_t register_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint32_t enable_callback_mask;
 #  endif
 
-	/** Set to \c true to write to buffered registers */
-	bool double_buffering_enabled;
+    /** Set to \c true to write to buffered registers */
+    bool double_buffering_enabled;
 };
 
 #if !defined(__DOXYGEN__)
 uint8_t _tcc_get_inst_index(
-		Tcc *const hw);
+        Tcc *const hw);
 #endif
 
 /**
@@ -1696,24 +1696,24 @@ uint8_t _tcc_get_inst_index(
  * \retval true  If the module synchronization is ongoing
  */
 static inline bool tcc_is_syncing(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return (module_inst->hw->SYNCBUSY.reg > 0);
+    return (module_inst->hw->SYNCBUSY.reg > 0);
 }
 
 
 void tcc_get_config_defaults(
-		struct tcc_config *const config,
-		Tcc *const hw);
+        struct tcc_config *const config,
+        Tcc *const hw);
 
 enum status_code tcc_init(
-		struct tcc_module *const module_inst,
-		Tcc *const hw,
-		const struct tcc_config *const config);
+        struct tcc_module *const module_inst,
+        Tcc *const hw,
+        const struct tcc_config *const config);
 
 /** @} */
 
@@ -1723,12 +1723,12 @@ enum status_code tcc_init(
  */
 
 enum status_code tcc_enable_events(
-		struct tcc_module *const module_inst,
-		struct tcc_events *const events);
+        struct tcc_module *const module_inst,
+        struct tcc_events *const events);
 
 void tcc_disable_events(
-		struct tcc_module *const module_inst,
-		struct tcc_events *const events);
+        struct tcc_module *const module_inst,
+        struct tcc_events *const events);
 
 /** @} */
 
@@ -1750,21 +1750,22 @@ void tcc_disable_events(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tcc_enable(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
 
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) {
-		/* Wait for sync */
-	}
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE)
+    {
+        /* Wait for sync */
+    }
 
-	/* Enable the TCC module */
-	tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE;
+    /* Enable the TCC module */
+    tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE;
 }
 
 /**
@@ -1775,26 +1776,27 @@ static inline void tcc_enable(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tcc_disable(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
 
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) {
-		/* Wait for sync */
-	}
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE)
+    {
+        /* Wait for sync */
+    }
 
-	/* Disbale interrupt */
-	tcc_module->INTENCLR.reg = TCC_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	tcc_module->INTFLAG.reg = TCC_INTFLAG_MASK;
+    /* Disbale interrupt */
+    tcc_module->INTENCLR.reg = TCC_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    tcc_module->INTFLAG.reg = TCC_INTFLAG_MASK;
 
-	/* Disable the TCC module */
-	tcc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
+    /* Disable the TCC module */
+    tcc_module->CTRLA.reg  &= ~TC_CTRLA_ENABLE;
 }
 
 /**
@@ -1811,25 +1813,27 @@ static inline void tcc_disable(
  *
  */
 static inline void tcc_reset(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments  */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-
-	/* Disable this module if it is running */
-	if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE) {
-		tcc_disable(module_inst);
-		while (tcc_is_syncing(module_inst)) {
-			/* wait while module is disabling */
-		}
-	}
-
-	/* Reset this TC module */
-	tcc_module->CTRLA.reg  |= TCC_CTRLA_SWRST;
+    /* Sanity check arguments  */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+
+    /* Disable this module if it is running */
+    if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE)
+    {
+        tcc_disable(module_inst);
+        while (tcc_is_syncing(module_inst))
+        {
+            /* wait while module is disabling */
+        }
+    }
+
+    /* Reset this TC module */
+    tcc_module->CTRLA.reg  |= TCC_CTRLA_SWRST;
 }
 
 /** @} */
@@ -1850,26 +1854,28 @@ static inline void tcc_reset(
  * \param[in] dir          New timer count direction to set
  */
 static inline void tcc_set_count_direction(
-		const struct tcc_module *const module_inst,
-		enum tcc_count_direction dir)
+        const struct tcc_module *const module_inst,
+        enum tcc_count_direction dir)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-
-	/* Set count direction */
-	if (TCC_COUNT_DIRECTION_DOWN == dir) {
-		tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
-		return;
-	}
-	tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+
+    /* Set count direction */
+    if (TCC_COUNT_DIRECTION_DOWN == dir)
+    {
+        tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+        return;
+    }
+    tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
 }
 
 /**
@@ -1881,24 +1887,26 @@ static inline void tcc_set_count_direction(
  * \param[in] module_inst  Pointer to the software module instance struct
  */
 static inline void tcc_toggle_count_direction(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-	bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR;
-	if (dir_value_1) {
-		tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
-	} else {
-		tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+    bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR;
+    if (dir_value_1)
+    {
+        tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR;
+    } else {
+        tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR;
+    }
 }
 
 /** @} */
@@ -1909,11 +1917,11 @@ static inline void tcc_toggle_count_direction(
  */
 
 uint32_t tcc_get_count_value(
-		const struct tcc_module *const module_inst);
+        const struct tcc_module *const module_inst);
 
 enum status_code tcc_set_count_value(
-		const struct tcc_module *const module_inst,
-		const uint32_t count);
+        const struct tcc_module *const module_inst,
+        const uint32_t count);
 
 /** @} */
 
@@ -1933,35 +1941,39 @@ enum status_code tcc_set_count_value(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tcc_stop_counter(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	uint32_t last_cmd;
-
-	/* Wait until last command is done */
-	do {
-		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-		}
-		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
-		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
-			break;
-		} else if (last_cmd == TCC_CTRLBSET_CMD_STOP) {
-			/* Command have been issued */
-			return;
-		} else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) {
-			/* Cancel RETRIGGER command and issue STOP */
-			tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
-		}
-	} while (1);
-
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    uint32_t last_cmd;
+
+    /* Wait until last command is done */
+    do {
+        while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+        {
+            /* Wait for sync */
+        }
+        last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+        if (last_cmd == TCC_CTRLBSET_CMD_NONE)
+        {
+            break;
+        } else if (last_cmd == TCC_CTRLBSET_CMD_STOP)
+        {
+            /* Command have been issued */
+            return;
+        } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER)
+        {
+            /* Cancel RETRIGGER command and issue STOP */
+            tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
+        }
+    } while (1);
+
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP;
 }
 
 /**
@@ -1972,35 +1984,39 @@ static inline void tcc_stop_counter(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tcc_restart_counter(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	uint32_t last_cmd;
-
-	/* Wait until last command is done */
-	do {
-		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-		}
-		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
-		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
-			break;
-		} else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) {
-			/* Command have been issued */
-			return;
-		} else if (last_cmd == TCC_CTRLBSET_CMD_STOP) {
-			/* Cancel STOP command and issue RETRIGGER */
-			tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
-		}
-	} while (1);
-
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    uint32_t last_cmd;
+
+    /* Wait until last command is done */
+    do {
+        while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+        {
+            /* Wait for sync */
+        }
+        last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+        if (last_cmd == TCC_CTRLBSET_CMD_NONE)
+        {
+            break;
+        } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER)
+        {
+            /* Command have been issued */
+            return;
+        } else if (last_cmd == TCC_CTRLBSET_CMD_STOP)
+        {
+            /* Cancel STOP command and issue RETRIGGER */
+            tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk;
+        }
+    } while (1);
+
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER;
 }
 
 /** @} */
@@ -2019,34 +2035,36 @@ static inline void tcc_restart_counter(
  * \param[in]  module_inst   Pointer to the software module instance struct
  */
 static inline void tcc_dma_trigger_command(
-		const struct tcc_module *const module_inst)
+        const struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
 
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+            /* Wait for sync */
+    }
 
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-	}
+    /* Make certain that there are no conflicting commands in the register */
+    tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_NONE;
 
-	/* Make certain that there are no conflicting commands in the register */
-	tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_NONE;
+    while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+            /* Wait for sync */
+    }
 
-	while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-	}
-	
 #if !(SAML21 || SAML22 || SAMR30)
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMATRG;
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMATRG;
 #endif
 
 #if (SAML21XXXB) || (SAML22) || (SAMR30)
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMAOS;
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMAOS;
 #endif
 }
 /** @} */
@@ -2058,13 +2076,13 @@ static inline void tcc_dma_trigger_command(
  */
 
 uint32_t tcc_get_capture_value(
-		const struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index);
+        const struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index);
 
 enum status_code tcc_set_compare_value(
-		const struct tcc_module *const module_inst,
-		const enum tcc_match_capture_channel channel_index,
-		const uint32_t compare);
+        const struct tcc_module *const module_inst,
+        const enum tcc_match_capture_channel channel_index,
+        const uint32_t compare);
 
 /** @} */
 
@@ -2074,8 +2092,8 @@ enum status_code tcc_set_compare_value(
  */
 
 enum status_code tcc_set_top_value(
-		const struct tcc_module *const module_inst,
-		const uint32_t top_value);
+        const struct tcc_module *const module_inst,
+        const uint32_t top_value);
 
 /** @} */
 
@@ -2086,9 +2104,9 @@ enum status_code tcc_set_top_value(
  */
 
 enum status_code tcc_set_pattern(
-		const struct tcc_module *const module_inst,
-		const uint32_t line_index,
-		const enum tcc_output_pattern pattern);
+        const struct tcc_module *const module_inst,
+        const uint32_t line_index,
+        const enum tcc_output_pattern pattern);
 
 /** @} */
 
@@ -2111,38 +2129,42 @@ enum status_code tcc_set_pattern(
  * \param[in]  ramp_index  Ramp index (\ref tcc_ramp_index) of the next cycle
  */
 static inline void tcc_set_ramp_index(
-		const struct tcc_module *const module_inst,
-		const enum tcc_ramp_index ramp_index)
+        const struct tcc_module *const module_inst,
+        const enum tcc_ramp_index ramp_index)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	uint32_t last_cmd;
-
-	/* Wait until last command is done */
-	do {
-		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-		}
-		if (TCC_RAMP_INDEX_DEFAULT == ramp_index) {
-			/* Cancel pending command */
-			tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_HOLD;
-			return;
-		}
-		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk;
-		if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE) {
-			break;
-		} else if (last_cmd == TCC_CTRLBSET_IDXCMD(ramp_index)) {
-			/* Command have been issued */
-			return;
-		}
-	} while (1);
-
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(ramp_index);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    uint32_t last_cmd;
+
+    /* Wait until last command is done */
+    do {
+        while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+        {
+            /* Wait for sync */
+        }
+        if (TCC_RAMP_INDEX_DEFAULT == ramp_index)
+        {
+            /* Cancel pending command */
+            tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_HOLD;
+            return;
+        }
+        last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk;
+        if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE)
+        {
+            break;
+        } else if (last_cmd == TCC_CTRLBSET_IDXCMD(ramp_index))
+        {
+            /* Command have been issued */
+            return;
+        }
+    } while (1);
+
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(ramp_index);
 }
 
 /** @} */
@@ -2163,21 +2185,21 @@ static inline void tcc_set_ramp_index(
  * \retval false The timer/counter is stopped
  */
 static inline bool tcc_is_running(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return !module_inst->hw->STATUS.bit.STOP;
+    return !module_inst->hw->STATUS.bit.STOP;
 }
 
 uint32_t tcc_get_status(
-		struct tcc_module *const module_inst);
+        struct tcc_module *const module_inst);
 
 void tcc_clear_status(
-		struct tcc_module *const module_inst,
-		const uint32_t status_flags);
+        struct tcc_module *const module_inst,
+        const uint32_t status_flags);
 
 /** @} */
 
@@ -2201,12 +2223,12 @@ void tcc_clear_status(
  * \param[in] module_inst  Pointer to the TCC software instance struct
  */
 static inline void tcc_enable_double_buffering(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	module_inst->double_buffering_enabled = true;
+    module_inst->double_buffering_enabled = true;
 }
 
 /**
@@ -2227,13 +2249,13 @@ static inline void tcc_enable_double_buffering(
  * \param[in] module_inst  Pointer to the TCC software instance struct
  */
 static inline void tcc_disable_double_buffering(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->double_buffering_enabled = false;
+    module_inst->double_buffering_enabled = false;
 }
 
 /**
@@ -2246,16 +2268,17 @@ static inline void tcc_disable_double_buffering(
  *
  */
 static inline void tcc_lock_double_buffer_update(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-	module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+    module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
 }
 
 /**
@@ -2268,16 +2291,17 @@ static inline void tcc_lock_double_buffer_update(
  *
  */
 static inline void tcc_unlock_double_buffer_update(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-		/* Wait for sync */
-	}
-	module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+    {
+        /* Wait for sync */
+    }
+    module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD;
 }
 
 /**
@@ -2287,32 +2311,35 @@ static inline void tcc_unlock_double_buffer_update(
  *
  */
 static inline void tcc_force_double_buffer_update(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Get a pointer to the module's hardware instance */
-	Tcc *const tcc_module = module_inst->hw;
-	uint32_t last_cmd;
-
-	/* Wait until last command is done */
-	do {
-		while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) {
-			/* Wait for sync */
-		}
-		last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
-		if (last_cmd == TCC_CTRLBSET_CMD_NONE) {
-			break;
-		} else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE) {
-			/* Command have been issued */
-			return;
-		}
-	} while (1);
-
-	/* Write command to execute */
-	tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Get a pointer to the module's hardware instance */
+    Tcc *const tcc_module = module_inst->hw;
+    uint32_t last_cmd;
+
+    /* Wait until last command is done */
+    do {
+        while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB)
+        {
+            /* Wait for sync */
+        }
+        last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk;
+        if (last_cmd == TCC_CTRLBSET_CMD_NONE)
+        {
+            break;
+        } else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE)
+        {
+            /* Command have been issued */
+            return;
+        }
+    } while (1);
+
+    /* Write command to execute */
+    tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE;
 }
 
 /**
@@ -2326,13 +2353,13 @@ static inline void tcc_force_double_buffer_update(
  * \param[in] module_inst     Pointer to the TCC software instance struct
  */
 static inline void tcc_enable_circular_buffer_top(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->WAVE.reg |=  TCC_WAVE_CIPEREN;
+    module_inst->hw->WAVE.reg |=  TCC_WAVE_CIPEREN;
 }
 
 /**
@@ -2343,31 +2370,31 @@ static inline void tcc_enable_circular_buffer_top(
  * \param[in] module_inst     Pointer to the TCC software instance struct
  */
 static inline void tcc_disable_circular_buffer_top(
-		struct tcc_module *const module_inst)
+        struct tcc_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN;
+    module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN;
 }
 
 enum status_code tcc_set_double_buffer_top_values(
-		const struct tcc_module *const module_inst,
-		const uint32_t top_value, const uint32_t top_buffer_value);
+        const struct tcc_module *const module_inst,
+        const uint32_t top_value, const uint32_t top_buffer_value);
 
 
 enum status_code tcc_enable_circular_buffer_compare(
-		struct tcc_module *const module_inst,
-		enum tcc_match_capture_channel channel_index);
+        struct tcc_module *const module_inst,
+        enum tcc_match_capture_channel channel_index);
 enum status_code tcc_disable_circular_buffer_compare(
-		struct tcc_module *const module_inst,
-		enum tcc_match_capture_channel channel_index);
+        struct tcc_module *const module_inst,
+        enum tcc_match_capture_channel channel_index);
 enum status_code tcc_set_double_buffer_compare_values(
-		struct tcc_module *const module_inst,
-		enum tcc_match_capture_channel channel_index,
-		const uint32_t compare,
-		const uint32_t compare_buffer);
+        struct tcc_module *const module_inst,
+        enum tcc_match_capture_channel channel_index,
+        const uint32_t compare,
+        const uint32_t compare_buffer);
 
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c
index aa1d5e3e9477..de2165670a3c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.c
@@ -51,22 +51,22 @@ void *_tcc_instances[TCC_INST_NUM];
 void _tcc_interrupt_handler(uint8_t module_index);
 
 const uint32_t _tcc_intflag[TCC_CALLBACK_N] = {
-	TCC_INTFLAG_OVF,
-	TCC_INTFLAG_TRG,
-	TCC_INTFLAG_CNT,
-	TCC_INTFLAG_ERR,
-	TCC_INTFLAG_FAULTA,
-	TCC_INTFLAG_FAULTB,
-	TCC_INTFLAG_FAULT0,
-	TCC_INTFLAG_FAULT1,
+    TCC_INTFLAG_OVF,
+    TCC_INTFLAG_TRG,
+    TCC_INTFLAG_CNT,
+    TCC_INTFLAG_ERR,
+    TCC_INTFLAG_FAULTA,
+    TCC_INTFLAG_FAULTB,
+    TCC_INTFLAG_FAULT0,
+    TCC_INTFLAG_FAULT1,
 #define _TCC_INTFLAG_MC(n,dummy) TCC_INTFLAG_MC##n,
-	/* TCC_INTFLAG_MC0 ~ ... */
-	MREPEAT(TCC_NUM_CHANNELS, _TCC_INTFLAG_MC, 0)
+    /* TCC_INTFLAG_MC0 ~ ... */
+    MREPEAT(TCC_NUM_CHANNELS, _TCC_INTFLAG_MC, 0)
 #undef _TCC_INTFLAG_MC
 };
 
 #  define _TCC_INTERRUPT_VECT_NUM(n, unused) \
-		  SYSTEM_INTERRUPT_MODULE_TCC##n,
+          SYSTEM_INTERRUPT_MODULE_TCC##n,
 /**
  * \internal Get the interrupt vector for the given device instance
  *
@@ -75,13 +75,13 @@ const uint32_t _tcc_intflag[TCC_CALLBACK_N] = {
  * \return Interrupt vector for of the given TCC module instance.
  */
 static enum system_interrupt_vector _tcc_interrupt_get_interrupt_vector(
-		uint32_t inst_num)
+        uint32_t inst_num)
 {
-	static uint8_t tcc_interrupt_vectors[TCC_INST_NUM] = {
-		MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_VECT_NUM, 0)
-	};
+    static uint8_t tcc_interrupt_vectors[TCC_INST_NUM] = {
+        MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_VECT_NUM, 0)
+    };
 
-	return (enum system_interrupt_vector)tcc_interrupt_vectors[inst_num];
+    return (enum system_interrupt_vector)tcc_interrupt_vectors[inst_num];
 }
 
 /**
@@ -98,21 +98,21 @@ static enum system_interrupt_vector _tcc_interrupt_get_interrupt_vector(
  * \param[in]     callback_type Callback type given by an enum
  */
 enum status_code tcc_register_callback(
-		struct tcc_module *const module,
-		tcc_callback_t callback_func,
-		const enum tcc_callback callback_type)
+        struct tcc_module *const module,
+        tcc_callback_t callback_func,
+        const enum tcc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->register_callback_mask |= _tcc_intflag[callback_type];
+    /* Set the bit corresponding to the callback_type */
+    module->register_callback_mask |= _tcc_intflag[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -125,19 +125,19 @@ enum status_code tcc_register_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 enum status_code tcc_unregister_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type)
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->register_callback_mask &= ~_tcc_intflag[callback_type];
+    /* Clear the bit corresponding to the callback_type */
+    module->register_callback_mask &= ~_tcc_intflag[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -152,20 +152,20 @@ enum status_code tcc_unregister_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 void tcc_enable_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type)
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Enable interrupts for this TCC module */
-	system_interrupt_enable(_tcc_interrupt_get_interrupt_vector(
-			_tcc_get_inst_index(module->hw)));
+    /* Enable interrupts for this TCC module */
+    system_interrupt_enable(_tcc_interrupt_get_interrupt_vector(
+            _tcc_get_inst_index(module->hw)));
 
-	/* Enable channel or other callbacks */
-	module->enable_callback_mask |= _tcc_intflag[callback_type];
-	module->hw->INTENSET.reg = _tcc_intflag[callback_type];
+    /* Enable channel or other callbacks */
+    module->enable_callback_mask |= _tcc_intflag[callback_type];
+    module->hw->INTENSET.reg = _tcc_intflag[callback_type];
 }
 
 /**
@@ -180,20 +180,20 @@ void tcc_enable_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 void tcc_disable_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type)
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(module->hw);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(module->hw);
 
-	/* Disable interrupts for this TCC module */
-	system_interrupt_disable(_tcc_interrupt_get_interrupt_vector(
-			_tcc_get_inst_index(module->hw)));
+    /* Disable interrupts for this TCC module */
+    system_interrupt_disable(_tcc_interrupt_get_interrupt_vector(
+            _tcc_get_inst_index(module->hw)));
 
-	/* Disable channel or other callbacks */
-	module->enable_callback_mask &= ~_tcc_intflag[callback_type];
-	module->hw->INTENCLR.reg = _tcc_intflag[callback_type];
+    /* Disable channel or other callbacks */
+    module->enable_callback_mask &= ~_tcc_intflag[callback_type];
+    module->hw->INTENCLR.reg = _tcc_intflag[callback_type];
 }
 
 
@@ -203,10 +203,10 @@ void tcc_disable_callback(
  * Auto-generate a set of interrupt handlers for each TCC in the device.
  */
 #define _TCC_INTERRUPT_HANDLER(n, m) \
-		void TCC##n##_Handler(void) \
-		{ \
-			_tcc_interrupt_handler(n); \
-		}
+        void TCC##n##_Handler(void) \
+        { \
+            _tcc_interrupt_handler(n); \
+        }
 
 MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_HANDLER, 0)
 
@@ -220,26 +220,28 @@ MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_HANDLER, 0)
  *                           handler
  */
 void _tcc_interrupt_handler(
-		uint8_t module_index)
+        uint8_t module_index)
 {
-	int i;
-
-	uint32_t interrupt_and_callback_status_mask;
-
-	struct tcc_module *module =
-			(struct tcc_module *)_tcc_instances[module_index];
-
-	interrupt_and_callback_status_mask = (module->hw->INTFLAG.reg &
-			module->register_callback_mask &
-			module->enable_callback_mask);
-
-	/* Check if callback interrupt has occured */
-	for (i = 0; i < TCC_CALLBACK_N; i ++) {
-		if (interrupt_and_callback_status_mask & _tcc_intflag[i]) {
-			/* Invoke the registered and enabled callback function */
-			(module->callback[i])(module);
-			/* Clear interrupt flag */
-			module->hw->INTFLAG.reg = _tcc_intflag[i];
-		}
-	}
+    int i;
+
+    uint32_t interrupt_and_callback_status_mask;
+
+    struct tcc_module *module =
+            (struct tcc_module *)_tcc_instances[module_index];
+
+    interrupt_and_callback_status_mask = (module->hw->INTFLAG.reg &
+            module->register_callback_mask &
+            module->enable_callback_mask);
+
+    /* Check if callback interrupt has occured */
+    for (i = 0; i < TCC_CALLBACK_N; i ++)
+    {
+        if (interrupt_and_callback_status_mask & _tcc_intflag[i])
+        {
+            /* Invoke the registered and enabled callback function */
+            (module->callback[i])(module);
+            /* Clear interrupt flag */
+            module->hw->INTFLAG.reg = _tcc_intflag[i];
+        }
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h
index 37b0bbb72797..e76534585db8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tcc/tcc_callback.h
@@ -66,21 +66,21 @@ extern void *_tcc_instances[TCC_INST_NUM];
  */
 
 enum status_code tcc_register_callback(
-		struct tcc_module *const module,
-		tcc_callback_t callback_func,
-		const enum tcc_callback callback_type);
+        struct tcc_module *const module,
+        tcc_callback_t callback_func,
+        const enum tcc_callback callback_type);
 
 enum status_code tcc_unregister_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type);
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type);
 
 void tcc_enable_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type);
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type);
 
 void tcc_disable_callback(
-		struct tcc_module *const module,
-		const enum tcc_callback callback_type);
+        struct tcc_module *const module,
+        const enum tcc_callback callback_type);
 
 /**
  * @}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c
index 707371de5934..a03f662cab5a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.c
@@ -62,8 +62,8 @@ static timer_callback_t timer_callback;
  */
 void timer_get_config_defaults(struct timer_config *config)
 {
-	config->reload_value = 0;
-	config->interrupt_enable = true;
+    config->reload_value = 0;
+    config->interrupt_enable = true;
 }
 
 
@@ -74,7 +74,7 @@ void timer_get_config_defaults(struct timer_config *config)
  */
 uint32_t timer_get_value(void)
 {
-	return TIMER0->VALUE.reg;
+    return TIMER0->VALUE.reg;
 }
 
 /**
@@ -84,7 +84,7 @@ uint32_t timer_get_value(void)
  */
 void timer_set_value(uint32_t value)
 {
-	TIMER0->RELOAD.reg = value;
+    TIMER0->RELOAD.reg = value;
 }
 
 /**
@@ -94,7 +94,7 @@ void timer_set_value(uint32_t value)
  */
 uint32_t timer_get_interrupt_status(void)
 {
-	return TIMER0->INTSTATUSCLEAR.reg;
+    return TIMER0->INTSTATUSCLEAR.reg;
 }
 
 /**
@@ -104,9 +104,9 @@ uint32_t timer_get_interrupt_status(void)
  */
 void timer_clear_interrupt_status(void)
 {
-	TIMER0->INTSTATUSCLEAR.reg = 1;
-	/* Wait for operation finish */
-	while (TIMER0->INTSTATUSCLEAR.reg);
+    TIMER0->INTSTATUSCLEAR.reg = 1;
+    /* Wait for operation finish */
+    while (TIMER0->INTSTATUSCLEAR.reg);
 }
 
 /**
@@ -116,7 +116,7 @@ void timer_clear_interrupt_status(void)
  */
 void timer_enable(void)
 {
-	TIMER0->CTRL.reg |= TIMER_CTRL_ENABLE;
+    TIMER0->CTRL.reg |= TIMER_CTRL_ENABLE;
 }
 
 /**
@@ -126,7 +126,7 @@ void timer_enable(void)
  */
 void timer_disable(void)
 {
-	TIMER0->CTRL.reg &= (~TIMER_CTRL_ENABLE);
+    TIMER0->CTRL.reg &= (~TIMER_CTRL_ENABLE);
 }
 
 /**
@@ -138,7 +138,7 @@ void timer_disable(void)
  */
 void timer_register_callback(timer_callback_t fun)
 {
-	timer_callback = fun; 
+    timer_callback = fun;
 }
 
 /**
@@ -149,7 +149,7 @@ void timer_register_callback(timer_callback_t fun)
  */
 void timer_unregister_callback(void)
 {
-	timer_callback = NULL; 
+    timer_callback = NULL;
 }
 
 /**
@@ -160,13 +160,15 @@ void timer_unregister_callback(void)
  */
 static void timer_isr_handler(void)
 {
-	if (timer_get_interrupt_status()) {
-		timer_clear_interrupt_status();
-		
-		if (timer_callback) {
-			timer_callback();
-		}
-	}
+    if (timer_get_interrupt_status())
+    {
+        timer_clear_interrupt_status();
+
+        if (timer_callback)
+        {
+            timer_callback();
+        }
+    }
 }
 
 /**
@@ -181,12 +183,12 @@ static void timer_isr_handler(void)
  */
 void timer_init(const struct timer_config *config)
 {
-	/* Global reset */
-	system_peripheral_reset(PERIPHERAL_TIMER);
+    /* Global reset */
+    system_peripheral_reset(PERIPHERAL_TIMER);
+
+    TIMER0->CTRL.reg = config->interrupt_enable << TIMER_CTRL_INTERRUPT_ENABLE_Pos;
+    TIMER0->RELOAD.reg = config->reload_value;
 
-	TIMER0->CTRL.reg = config->interrupt_enable << TIMER_CTRL_INTERRUPT_ENABLE_Pos;
-	TIMER0->RELOAD.reg = config->reload_value;
-	
-	timer_callback = NULL;
-	system_register_isr(RAM_ISR_TABLE_TIMER0_INDEX, (uint32_t)timer_isr_handler);
-}
\ No newline at end of file
+    timer_callback = NULL;
+    system_register_isr(RAM_ISR_TABLE_TIMER0_INDEX, (uint32_t)timer_isr_handler);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h
index d21f5f35ea44..b60f8b08a0cd 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/timer/timer.h
@@ -78,7 +78,7 @@
  *
  * - You can generate an interrupt request signal, TIMERINT,
  * when the counter reaches 0.
- 
+
  * - The interrupt request is held until it is cleared by writing to the INTCLEAR Register.
  *
  * - You can use the zero to one transition of the external input signal, EXTIN, as a timer enable.
@@ -88,7 +88,7 @@
  *
  * - The external clock, EXTIN, must be slower than half of the peripheral clock because it is
  * sampled by a double flip-flop and then goes through edge-detection logic when the
- * external inputs act as a clock. 
+ * external inputs act as a clock.
  *
  * - A separate clock pin, PCLKG, for the APB register read or write logic that permits the
  * clock to peripheral register logic to stop when there is no APB activity.
@@ -134,10 +134,10 @@ typedef void (*timer_callback_t)(void);
  * modified by the user application.
  */
 struct timer_config {
-	/** Reload value */
-	uint32_t reload_value;
-	/** Enable timer interrupt */
-	bool interrupt_enable;
+    /** Reload value */
+    uint32_t reload_value;
+    /** Enable timer interrupt */
+    bool interrupt_enable;
 };
 
 /**
@@ -193,14 +193,14 @@ void timer_unregister_callback(void);
  * Below is a table listing the acronyms used in this module, along with their
  * intended meanings.
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>TIMER</td>
- *		<td>Timer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>TIMER</td>
+ *      <td>Timer</td>
+ *  </tr>
  * </table>
  *
  * \section asfdoc_samb_timer_extra_dependencies Dependencies
@@ -254,4 +254,4 @@ void timer_unregister_callback(void);
  * </table>
  */
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c
index b5ce6b39f871..f2593679b8c7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.c
@@ -61,41 +61,42 @@
  * \retval STATUS_OK           The module was initialized successfully
  */
 enum status_code trng_init(
-		struct trng_module *const module_inst,
-		Trng *const hw,
-		struct trng_config *const config)
+        struct trng_module *const module_inst,
+        Trng *const hw,
+        struct trng_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(hw);
+    Assert(config);
 
-	/* Initialize device instance */
-	module_inst->hw = hw;
+    /* Initialize device instance */
+    module_inst->hw = hw;
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TRNG);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_TRNG);
 
 #if TRNG_CALLBACK_MODE == true
-	/* Initialize parameters */
-	for (uint8_t i = 0; i < TRNG_CALLBACK_N; i++) {
-		module_inst->callback[i] = NULL;
-	}
+    /* Initialize parameters */
+    for (uint8_t i = 0; i < TRNG_CALLBACK_N; i++)
+    {
+        module_inst->callback[i] = NULL;
+    }
 
-	/* Initialize software flags*/
-	module_inst->register_callback_mask = 0x00;
-	module_inst->enable_callback_mask   = 0x00;
-	module_inst->job_buffer             = NULL;
-	module_inst->remaining_number       = 0;
-	module_inst->job_status             = STATUS_OK;
+    /* Initialize software flags*/
+    module_inst->register_callback_mask = 0x00;
+    module_inst->enable_callback_mask   = 0x00;
+    module_inst->job_buffer             = NULL;
+    module_inst->remaining_number       = 0;
+    module_inst->job_status             = STATUS_OK;
 
-	/* Register this instance for callbacks*/
-	_trng_instance = module_inst;
+    /* Register this instance for callbacks*/
+    _trng_instance = module_inst;
 #endif
 
-	/* Write configuration to module */
-	hw->CTRLA.reg = ((uint32_t)config->run_in_standby << TRNG_CTRLA_RUNSTDBY_Pos);
+    /* Write configuration to module */
+    hw->CTRLA.reg = ((uint32_t)config->run_in_standby << TRNG_CTRLA_RUNSTDBY_Pos);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h
index 8fec9b98e991..430b75d8cbcf 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng.h
@@ -129,11 +129,11 @@ typedef void (*trng_callback_t)(struct trng_module *const module_inst);
 
 /** Enum for possible callback types for the TRNG module. */
 enum trng_callback {
-	/** Callback for specific number of random data ready */
-	TRNG_CALLBACK_READ_BUFFER = 0,
-	/** Number of available callbacks */
+    /** Callback for specific number of random data ready */
+    TRNG_CALLBACK_READ_BUFFER = 0,
+    /** Number of available callbacks */
 #if !defined(__DOXYGEN__)
-	TRNG_CALLBACK_N,
+    TRNG_CALLBACK_N,
 #endif
 };
 #endif
@@ -149,21 +149,21 @@ enum trng_callback {
  */
 struct trng_module {
 #if !defined(__DOXYGEN__)
-	/** Hardware module pointer of the associated TRNG peripheral */
-	Trng *hw;
+    /** Hardware module pointer of the associated TRNG peripheral */
+    Trng *hw;
 #  if TRNG_CALLBACK_MODE == true
-	/** Array of callbacks */
-	trng_callback_t callback[TRNG_CALLBACK_N];
-	/** Bit mask for callbacks registered */
-	uint8_t register_callback_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t enable_callback_mask;
-	/** Holds the status of the ongoing or last read job */
-	volatile enum status_code job_status;
-	/** Pointer to buffer used for TRNG results */
-	volatile uint32_t *job_buffer;
-	/** Remaining number of TRNG results in current job */
-	volatile uint32_t remaining_number;
+    /** Array of callbacks */
+    trng_callback_t callback[TRNG_CALLBACK_N];
+    /** Bit mask for callbacks registered */
+    uint8_t register_callback_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t enable_callback_mask;
+    /** Holds the status of the ongoing or last read job */
+    volatile enum status_code job_status;
+    /** Pointer to buffer used for TRNG results */
+    volatile uint32_t *job_buffer;
+    /** Remaining number of TRNG results in current job */
+    volatile uint32_t remaining_number;
 #  endif
 #endif
 };
@@ -174,9 +174,9 @@ struct trng_module {
  *  Configuration structure for a True Random Number Generator.
  */
 struct trng_config {
-	/** If \c true, the True Random Number Generator will not be stopped in
-	 *  standby sleep mode */
-	bool run_in_standby;
+    /** If \c true, the True Random Number Generator will not be stopped in
+     *  standby sleep mode */
+    bool run_in_standby;
 };
 
 /**
@@ -186,8 +186,8 @@ struct trng_config {
  * disable events via \ref trng_enable_events() and \ref trng_disable_events().
  */
 struct trng_events {
-	/** Enable event generation on random data ready */
-	bool generate_event_on_data_ready;
+    /** Enable event generation on random data ready */
+    bool generate_event_on_data_ready;
 };
 
 
@@ -196,9 +196,9 @@ struct trng_events {
  * @{
  */
 enum status_code trng_init(
-		struct trng_module *const module_inst,
-		Trng *const hw,
-		struct trng_config *const config);
+        struct trng_module *const module_inst,
+        Trng *const hw,
+        struct trng_config *const config);
 
 /**
  * \brief Initializes all members of a TRNG configuration structure
@@ -215,13 +215,13 @@ enum status_code trng_init(
  *  \param[out] config  Configuration structure to initialize to default values
  */
 static inline void trng_get_config_defaults(
-		struct trng_config *const config)
+        struct trng_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->run_in_standby = false;
+    /* Default configuration values */
+    config->run_in_standby = false;
 }
 
 /**
@@ -234,16 +234,16 @@ static inline void trng_get_config_defaults(
  *                         Generator peripheral
  */
 static inline void trng_enable(
-		struct trng_module *const module_inst)
+        struct trng_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Trng *const trng_module = module_inst->hw;
+    Trng *const trng_module = module_inst->hw;
 
-	/* Enable TRNG */
-	trng_module->CTRLA.reg |= TRNG_CTRLA_ENABLE;
+    /* Enable TRNG */
+    trng_module->CTRLA.reg |= TRNG_CTRLA_ENABLE;
 }
 
 /**
@@ -256,21 +256,21 @@ static inline void trng_enable(
  *                         Generator peripheral
  */
 static inline void trng_disable(
-		struct trng_module *const module_inst)
+        struct trng_module *const module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Trng *const trng_module = module_inst->hw;
+    Trng *const trng_module = module_inst->hw;
 
-	/* Disbale interrupt */
-	trng_module->INTENCLR.reg = TRNG_INTENCLR_MASK;
-	/* Clear interrupt flag */
-	trng_module->INTFLAG.reg = TRNG_INTFLAG_MASK;
+    /* Disbale interrupt */
+    trng_module->INTENCLR.reg = TRNG_INTENCLR_MASK;
+    /* Clear interrupt flag */
+    trng_module->INTFLAG.reg = TRNG_INTFLAG_MASK;
 
-	/* Disable TRNG */
-	trng_module->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
+    /* Disable TRNG */
+    trng_module->CTRLA.reg &= ~TRNG_CTRLA_ENABLE;
 }
 
 /**
@@ -286,19 +286,20 @@ static inline void trng_disable(
  *  \param[in] events       Struct containing flags of events to enable
  */
 static inline void trng_enable_events(
-		struct trng_module *const module_inst,
-		struct trng_events *const events)
+        struct trng_module *const module_inst,
+        struct trng_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Trng *const trng_module = module_inst->hw;
+    Trng *const trng_module = module_inst->hw;
 
-	if (events->generate_event_on_data_ready) {
-		/* Enable data ready event output */
-		trng_module->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
-	}
+    if (events->generate_event_on_data_ready)
+    {
+        /* Enable data ready event output */
+        trng_module->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO;
+    }
 }
 
 /**
@@ -314,19 +315,20 @@ static inline void trng_enable_events(
  *  \param[in] events       Struct containing flags of events to disable
  */
 static inline void trng_disable_events(
-		struct trng_module *const module_inst,
-		struct trng_events *const events)
+        struct trng_module *const module_inst,
+        struct trng_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	Trng *const trng_module = module_inst->hw;
+    Trng *const trng_module = module_inst->hw;
 
-	if (events->generate_event_on_data_ready) {
-		/* Disable data ready event output */
-		trng_module->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
-	}
+    if (events->generate_event_on_data_ready)
+    {
+        /* Disable data ready event output */
+        trng_module->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO;
+    }
 }
 /** @} */
 
@@ -348,25 +350,26 @@ static inline void trng_disable_events(
  * \retval STATUS_BUSY         A random result was not ready
  */
 static inline enum status_code trng_read(
-		struct trng_module *const module_inst,
-		uint32_t *result)
+        struct trng_module *const module_inst,
+        uint32_t *result)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(result);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(result);
 
-	Trng *const trng_hw = module_inst->hw;
+    Trng *const trng_hw = module_inst->hw;
 
-	if (!(trng_hw->INTFLAG.reg & TRNG_INTFLAG_DATARDY)) {
-		/* Result not ready */
-		return STATUS_BUSY;
-	}
+    if (!(trng_hw->INTFLAG.reg & TRNG_INTFLAG_DATARDY))
+    {
+        /* Result not ready */
+        return STATUS_BUSY;
+    }
 
-	/* Get randomly generated output data (it will clear data ready flag) */
-	*result = trng_hw->DATA.reg;
+    /* Get randomly generated output data (it will clear data ready flag) */
+    *result = trng_hw->DATA.reg;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 /** @} */
 
@@ -382,14 +385,14 @@ static inline enum status_code trng_read(
  * \section asfdoc_sam0_trng_extra_acronyms Acronyms
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>TRNG</td>
- *		<td>True Random Number Generator</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>TRNG</td>
+ *      <td>True Random Number Generator</td>
+ *  </tr>
  * </table>
  *
  *
@@ -408,12 +411,12 @@ static inline enum status_code trng_read(
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -434,21 +437,21 @@ static inline enum status_code trng_read(
  * \page asfdoc_sam0_trng_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>42444B</td>
- *		<td>01/2016</td>
- *		<td>Added support for SAM L22</td>
- *	</tr>
- *	<tr>
- *		<td>42444A</td>
- *		<td>06/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42444B</td>
+ *      <td>01/2016</td>
+ *      <td>Added support for SAM L22</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42444A</td>
+ *      <td>06/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c
index a3a7ea56728f..e8455fbfd3f6 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.c
@@ -65,24 +65,24 @@ struct trng_module *_trng_instance;
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code trng_register_callback(
-		struct trng_module *const module,
-		trng_callback_t callback_func,
-		const enum trng_callback callback_type)
+        struct trng_module *const module,
+        trng_callback_t callback_func,
+        const enum trng_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module->register_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module->register_callback_mask |= (1 << callback_type);
 
-	/* Enable interrupt for this TRNG module */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_TRNG);
+    /* Enable interrupt for this TRNG module */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_TRNG);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -97,24 +97,25 @@ enum status_code trng_register_callback(
  * \retval STATUS_OK  The function exited successfully
  */
 enum status_code trng_unregister_callback(
-		struct trng_module *const module,
-		const enum trng_callback callback_type)
+        struct trng_module *const module,
+        const enum trng_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module->register_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module->register_callback_mask &= ~(1 << callback_type);
 
-	/* Disable interrupt for this TRNG module */
-	if (module->register_callback_mask == 0) {
-		system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_TRNG);
-	}
+    /* Disable interrupt for this TRNG module */
+    if (module->register_callback_mask == 0)
+    {
+        system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_TRNG);
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -124,35 +125,38 @@ enum status_code trng_unregister_callback(
  */
 void TRNG_Handler(void)
 {
-	/* Temporary variable */
-	uint8_t interrupt_and_callback_status_mask;
-
-	/* Get device instance from the look-up table */
-	struct trng_module *module = _trng_instance;
-
-	/* Read and mask interrupt flag register */
-	interrupt_and_callback_status_mask = module->hw->INTFLAG.reg &
-			(module->register_callback_mask & module->enable_callback_mask);
-
-	/* Check if data ready needs to be serviced */
-	if (interrupt_and_callback_status_mask & TRNG_INTFLAG_DATARDY) {
-		/* Store random result in job buffer (it will clear data ready flag) */
-		*(module->job_buffer++) = module->hw->DATA.reg;
-
-		module->remaining_number -= 1;
-		if (module->remaining_number == 0) {
-			if (module->job_status == STATUS_BUSY) {
-				/* Job is complete. Update status, disable interrupt
-				 * and call callback */
-				module->job_status = STATUS_OK;
-				module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
-				(module->callback[TRNG_CALLBACK_READ_BUFFER])(module);
-			}
-		}
-	}
-
-	/* Clear interrupt flag */
-	module->hw->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
+    /* Temporary variable */
+    uint8_t interrupt_and_callback_status_mask;
+
+    /* Get device instance from the look-up table */
+    struct trng_module *module = _trng_instance;
+
+    /* Read and mask interrupt flag register */
+    interrupt_and_callback_status_mask = module->hw->INTFLAG.reg &
+            (module->register_callback_mask & module->enable_callback_mask);
+
+    /* Check if data ready needs to be serviced */
+    if (interrupt_and_callback_status_mask & TRNG_INTFLAG_DATARDY)
+    {
+        /* Store random result in job buffer (it will clear data ready flag) */
+        *(module->job_buffer++) = module->hw->DATA.reg;
+
+        module->remaining_number -= 1;
+        if (module->remaining_number == 0)
+        {
+            if (module->job_status == STATUS_BUSY)
+            {
+                /* Job is complete. Update status, disable interrupt
+                 * and call callback */
+                module->job_status = STATUS_OK;
+                module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+                (module->callback[TRNG_CALLBACK_READ_BUFFER])(module);
+            }
+        }
+    }
+
+    /* Clear interrupt flag */
+    module->hw->INTFLAG.reg = TRNG_INTFLAG_DATARDY;
 }
 
 /**
@@ -171,27 +175,28 @@ void TRNG_Handler(void)
  * \retval STATUS_BUSY      The TRNG is already busy with another job
  */
 enum status_code trng_read_buffer_job(
-		struct trng_module *const module_inst,
-		uint32_t *buffer,
-		uint32_t number)
+        struct trng_module *const module_inst,
+        uint32_t *buffer,
+        uint32_t number)
 {
-	Assert(module_inst);
-	Assert(number);
-	Assert(buffer);
+    Assert(module_inst);
+    Assert(number);
+    Assert(buffer);
 
-	if (module_inst->remaining_number != 0 ||
-			module_inst->job_status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    if (module_inst->remaining_number != 0 ||
+            module_inst->job_status == STATUS_BUSY)
+            {
+        return STATUS_BUSY;
+    }
 
-	module_inst->job_status = STATUS_BUSY;
-	module_inst->remaining_number = number;
-	module_inst->job_buffer = buffer;
+    module_inst->job_status = STATUS_BUSY;
+    module_inst->remaining_number = number;
+    module_inst->job_buffer = buffer;
 
-	/* Enable data ready interrupt */
-	module_inst->hw->INTENSET.reg = TRNG_INTENSET_DATARDY;
+    /* Enable data ready interrupt */
+    module_inst->hw->INTENSET.reg = TRNG_INTENSET_DATARDY;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -205,17 +210,18 @@ enum status_code trng_read_buffer_job(
  * \return Status of the job.
  */
 enum status_code trng_get_job_status(
-		struct trng_module *module_inst,
-		enum trng_job_type type)
+        struct trng_module *module_inst,
+        enum trng_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == TRNG_JOB_READ_BUFFER) {
-		return module_inst->job_status;
-	} else {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == TRNG_JOB_READ_BUFFER)
+    {
+        return module_inst->job_status;
+    } else {
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -225,18 +231,19 @@ enum status_code trng_get_job_status(
  * \param [in]  type        Type of job to abort
  */
 void trng_abort_job(
-		struct trng_module *module_inst,
-		enum trng_job_type type)
+        struct trng_module *module_inst,
+        enum trng_job_type type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-
-	if (type == TRNG_JOB_READ_BUFFER) {
-		/* Disable interrupt */
-		module_inst->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
-		/* Mark job as aborted */
-		module_inst->job_status = STATUS_ABORTED;
-		module_inst->remaining_number = 0;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+
+    if (type == TRNG_JOB_READ_BUFFER)
+    {
+        /* Disable interrupt */
+        module_inst->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+        /* Mark job as aborted */
+        module_inst->job_status = STATUS_ABORTED;
+        module_inst->remaining_number = 0;
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h
index ee2e53f42a66..2e37f8d6554c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/trng/trng_callback.h
@@ -64,8 +64,8 @@ extern "C" {
  * the driver.
  */
 enum trng_job_type {
-	/** Asynchronous TRNG read into a user provided buffer */
-	TRNG_JOB_READ_BUFFER,
+    /** Asynchronous TRNG read into a user provided buffer */
+    TRNG_JOB_READ_BUFFER,
 };
 
 /**
@@ -73,13 +73,13 @@ enum trng_job_type {
  * @{
  */
 enum status_code trng_register_callback(
-		struct trng_module *const module,
-		trng_callback_t callback_func,
-		enum trng_callback callback_type);
+        struct trng_module *const module,
+        trng_callback_t callback_func,
+        enum trng_callback callback_type);
 
 enum status_code trng_unregister_callback(
-		struct trng_module *module,
-		enum trng_callback callback_type);
+        struct trng_module *module,
+        enum trng_callback callback_type);
 
 /**
  * \brief Enables callback
@@ -92,14 +92,14 @@ enum status_code trng_unregister_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void trng_enable_callback(
-		struct trng_module *const module,
-		enum trng_callback callback_type)
+        struct trng_module *const module,
+        enum trng_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->enable_callback_mask |= (1 << callback_type);
+    /* Enable callback */
+    module->enable_callback_mask |= (1 << callback_type);
 }
 
 /**
@@ -112,19 +112,20 @@ static inline void trng_enable_callback(
  * \param[in]     callback_type Callback type given by an enum
  */
 static inline void trng_disable_callback(
-		struct trng_module *const module,
-		enum trng_callback callback_type)
+        struct trng_module *const module,
+        enum trng_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Disable callback */
-	module->enable_callback_mask &= ~(1UL << callback_type);
+    /* Disable callback */
+    module->enable_callback_mask &= ~(1UL << callback_type);
 
-	/* Disable data ready interrupt */
-	if (callback_type == TRNG_CALLBACK_READ_BUFFER) {
-		module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
-	}
+    /* Disable data ready interrupt */
+    if (callback_type == TRNG_CALLBACK_READ_BUFFER)
+    {
+        module->hw->INTENCLR.reg = TRNG_INTENCLR_DATARDY;
+    }
 }
 
 /** @} */
@@ -134,17 +135,17 @@ static inline void trng_disable_callback(
  * @{
  */
 enum status_code trng_read_buffer_job(
-		struct trng_module *const module_inst,
-		uint32_t *buffer,
-		uint32_t number);
+        struct trng_module *const module_inst,
+        uint32_t *buffer,
+        uint32_t number);
 
 enum status_code trng_get_job_status(
-		struct trng_module *module_inst,
-		enum trng_job_type type);
+        struct trng_module *module_inst,
+        enum trng_job_type type);
 
 void trng_abort_job(
-		struct trng_module *module_inst,
-		enum trng_job_type type);
+        struct trng_module *module_inst,
+        enum trng_job_type type);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c
index 0a5f1acbfe3d..dae11208b305 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.c
@@ -62,63 +62,65 @@
  */
 static enum status_code _tsens_set_config(struct tsens_config *const config)
 {
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	system_gclk_chan_get_config_defaults(&gclk_chan_conf);
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(TSENS_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(TSENS_GCLK_ID);
-
-	/* Configure run in standby */
-	TSENS->CTRLA.reg = (config->run_in_standby << TSENS_CTRLA_RUNSTDBY_Pos);
-
-	/* Check validity of window thresholds */
-	if (config->window.window_mode != TSENS_WINDOW_MODE_DISABLE) {
-		if((config->window.window_lower_value < WINDOW_MIN_VALUE) || \
-			(config->window.window_upper_value > WINDOW_MAX_VALUE)) {
-				return STATUS_ERR_INVALID_ARG;
-			}
-	}
-
-	/* Configure CTRLC */
-	TSENS->CTRLC.reg =
-			(config->free_running << TSENS_CTRLC_FREERUN_Pos) | \
-			(config->window.window_mode);
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    system_gclk_chan_get_config_defaults(&gclk_chan_conf);
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(TSENS_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(TSENS_GCLK_ID);
+
+    /* Configure run in standby */
+    TSENS->CTRLA.reg = (config->run_in_standby << TSENS_CTRLA_RUNSTDBY_Pos);
+
+    /* Check validity of window thresholds */
+    if (config->window.window_mode != TSENS_WINDOW_MODE_DISABLE)
+    {
+        if((config->window.window_lower_value < WINDOW_MIN_VALUE) || \
+            (config->window.window_upper_value > WINDOW_MAX_VALUE))
+            {
+                return STATUS_ERR_INVALID_ARG;
+            }
+    }
+
+    /* Configure CTRLC */
+    TSENS->CTRLC.reg =
+            (config->free_running << TSENS_CTRLC_FREERUN_Pos) | \
+            (config->window.window_mode);
 
 #if ERRATA_14476
-	/* Configure lower threshold */
-	TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
+    /* Configure lower threshold */
+    TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
 
-	/* Configure upper threshold */
-	TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
+    /* Configure upper threshold */
+    TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
 #else
-	/* Configure lower threshold */
-	TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
+    /* Configure lower threshold */
+    TSENS->WINLT.reg = TSENS_WINLT_WINLT(config->window.window_lower_value);
 
-	/* Configure upper threshold */
-	TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
+    /* Configure upper threshold */
+    TSENS->WINUT.reg = TSENS_WINLT_WINLT(config->window.window_upper_value);
 #endif
 
-	/* Configure events */
-	TSENS->EVCTRL.reg = config->event_action;
+    /* Configure events */
+    TSENS->EVCTRL.reg = config->event_action;
 
-	/* Disable all interrupts */
-	TSENS->INTENCLR.reg =
-			(1 << TSENS_INTENCLR_OVF_Pos) | (1 << TSENS_INTENCLR_WINMON_Pos) | \
-			(1 << TSENS_INTENCLR_OVERRUN_Pos) | (1 << TSENS_INTENCLR_RESRDY_Pos);
+    /* Disable all interrupts */
+    TSENS->INTENCLR.reg =
+            (1 << TSENS_INTENCLR_OVF_Pos) | (1 << TSENS_INTENCLR_WINMON_Pos) | \
+            (1 << TSENS_INTENCLR_OVERRUN_Pos) | (1 << TSENS_INTENCLR_RESRDY_Pos);
 
-	/* Read calibration from NVM */
-	uint32_t tsens_bits = *((uint32_t *)NVMCTRL_TEMP_LOG);
-	uint32_t tsens_tcal = \
-				((tsens_bits & TSENS_FUSES_TCAL_Msk) >> TSENS_FUSES_TCAL_Pos);
-	uint32_t tsens_fcal = \
-				((tsens_bits & TSENS_FUSES_FCAL_Msk) >> TSENS_FUSES_FCAL_Pos);
+    /* Read calibration from NVM */
+    uint32_t tsens_bits = *((uint32_t *)NVMCTRL_TEMP_LOG);
+    uint32_t tsens_tcal = \
+                ((tsens_bits & TSENS_FUSES_TCAL_Msk) >> TSENS_FUSES_TCAL_Pos);
+    uint32_t tsens_fcal = \
+                ((tsens_bits & TSENS_FUSES_FCAL_Msk) >> TSENS_FUSES_FCAL_Pos);
 
-	TSENS->CAL.reg = TSENS_CAL_TCAL(tsens_tcal) | TSENS_CAL_FCAL(tsens_fcal);
-	TSENS->GAIN.reg = TSENS_GAIN_GAIN(config->calibration.gain);
-	TSENS->OFFSET.reg = TSENS_OFFSET_OFFSETC(config->calibration.offset);
+    TSENS->CAL.reg = TSENS_CAL_TCAL(tsens_tcal) | TSENS_CAL_FCAL(tsens_fcal);
+    TSENS->GAIN.reg = TSENS_GAIN_GAIN(config->calibration.gain);
+    TSENS->OFFSET.reg = TSENS_OFFSET_OFFSETC(config->calibration.offset);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -137,24 +139,26 @@ static enum status_code _tsens_set_config(struct tsens_config *const config)
  */
 enum status_code tsens_init(struct tsens_config *config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_TSENS);
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_TSENS);
 
-	if (TSENS->CTRLA.reg & TSENS_CTRLA_SWRST) {
-		/* We are in the middle of a reset. Abort. */
-		return STATUS_BUSY;
-	}
+    if (TSENS->CTRLA.reg & TSENS_CTRLA_SWRST)
+    {
+        /* We are in the middle of a reset. Abort. */
+        return STATUS_BUSY;
+    }
 
-	if (TSENS->CTRLA.reg & TSENS_CTRLA_ENABLE) {
-		/* Module must be disabled before initialization. Abort. */
-		return STATUS_ERR_DENIED;
-	}
+    if (TSENS->CTRLA.reg & TSENS_CTRLA_ENABLE)
+    {
+        /* Module must be disabled before initialization. Abort. */
+        return STATUS_ERR_DENIED;
+    }
 
-	/* Write configuration to module */
-	return _tsens_set_config(config);
+    /* Write configuration to module */
+    return _tsens_set_config(config);
 }
 
 /**
@@ -183,23 +187,23 @@ enum status_code tsens_init(struct tsens_config *config)
  */
 void tsens_get_config_defaults(struct tsens_config *const config)
 {
-	Assert(config);
-	config->clock_source                  = GCLK_GENERATOR_0;
-	config->free_running                  = false;
-	config->run_in_standby                = false;
-	config->window.window_mode            = TSENS_WINDOW_MODE_DISABLE;
-	config->window.window_upper_value     = 0;
-	config->window.window_lower_value     = 0;
-	config->event_action                  = TSENS_EVENT_ACTION_DISABLED;
-
-	uint32_t tsens_bits[2];
-	tsens_bits[0] = *((uint32_t *)NVMCTRL_TEMP_LOG);
-	tsens_bits[1] = *(((uint32_t *)NVMCTRL_TEMP_LOG) + 1);
-	config->calibration.offset   = \
-		((tsens_bits[0] & TSENS_FUSES_OFFSET_Msk) >> TSENS_FUSES_OFFSET_Pos);
-	config->calibration.gain     = \
-		((tsens_bits[0] & TSENS_FUSES_GAIN_0_Msk) >> TSENS_FUSES_GAIN_0_Pos) | \
-		((tsens_bits[1] & TSENS_FUSES_GAIN_1_Msk) >> TSENS_FUSES_GAIN_1_Pos);
+    Assert(config);
+    config->clock_source                  = GCLK_GENERATOR_0;
+    config->free_running                  = false;
+    config->run_in_standby                = false;
+    config->window.window_mode            = TSENS_WINDOW_MODE_DISABLE;
+    config->window.window_upper_value     = 0;
+    config->window.window_lower_value     = 0;
+    config->event_action                  = TSENS_EVENT_ACTION_DISABLED;
+
+    uint32_t tsens_bits[2];
+    tsens_bits[0] = *((uint32_t *)NVMCTRL_TEMP_LOG);
+    tsens_bits[1] = *(((uint32_t *)NVMCTRL_TEMP_LOG) + 1);
+    config->calibration.offset   = \
+        ((tsens_bits[0] & TSENS_FUSES_OFFSET_Msk) >> TSENS_FUSES_OFFSET_Pos);
+    config->calibration.gain     = \
+        ((tsens_bits[0] & TSENS_FUSES_GAIN_0_Msk) >> TSENS_FUSES_GAIN_0_Pos) | \
+        ((tsens_bits[1] & TSENS_FUSES_GAIN_1_Msk) >> TSENS_FUSES_GAIN_1_Pos);
 }
 
 /**
@@ -217,34 +221,38 @@ void tsens_get_config_defaults(struct tsens_config *const config)
  */
 enum status_code tsens_read(int32_t *result)
 {
-	Assert(result);
-
-	if (!(tsens_get_status() & TSENS_STATUS_RESULT_READY)) {
-		/* Result not ready */
-		return STATUS_BUSY;
-	}
-
-	if (TSENS->STATUS.reg & TSENS_STATUS_OVF) {
-		/* The result is not valid */
-		return STATUS_ERR_BAD_DATA;
-	}
-
-	/* Get TSENS result */
-	uint32_t temp = TSENS->VALUE.reg;
-	if(temp & 0x00800000) {
-		temp |= ~TSENS_VALUE_MASK;
-	}
+    Assert(result);
+
+    if (!(tsens_get_status() & TSENS_STATUS_RESULT_READY))
+    {
+        /* Result not ready */
+        return STATUS_BUSY;
+    }
+
+    if (TSENS->STATUS.reg & TSENS_STATUS_OVF)
+    {
+        /* The result is not valid */
+        return STATUS_ERR_BAD_DATA;
+    }
+
+    /* Get TSENS result */
+    uint32_t temp = TSENS->VALUE.reg;
+    if(temp & 0x00800000)
+    {
+        temp |= ~TSENS_VALUE_MASK;
+    }
 #if (ERRATA_14476)
-	*result = temp * (-1);
+    *result = temp * (-1);
 #endif
 
-	/* Reset ready flag */
-	tsens_clear_status(TSENS_STATUS_RESULT_READY);
+    /* Reset ready flag */
+    tsens_clear_status(TSENS_STATUS_RESULT_READY);
 
-	if (tsens_get_status() & TSENS_STATUS_OVERRUN) {
-		tsens_clear_status(TSENS_STATUS_OVERRUN);
-		return STATUS_ERR_OVERFLOW;
-	}
+    if (tsens_get_status() & TSENS_STATUS_OVERRUN)
+    {
+        tsens_clear_status(TSENS_STATUS_OVERRUN);
+        return STATUS_ERR_OVERFLOW;
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h
index 2131eb2fde6e..1e9dfac89c41 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens.h
@@ -103,22 +103,22 @@
  * and resolution as below:
  * <table>
  *  <tr>
- *	  <th>Resolution (#/°C)</th>
- *	  <th>GAIN@48MHz</th>
- *	  <th>GAIN@40MHz</th>
- *	</tr>
- *	<tr>
- *	  <td>&times;1 (1°C)</td>
+ *    <th>Resolution (#/°C)</th>
+ *    <th>GAIN@48MHz</th>
+ *    <th>GAIN@40MHz</th>
+ *  </tr>
+ *  <tr>
+ *    <td>&times;1 (1°C)</td>
  *    <td>960</td>
  *    <td>800</td>
  *  </tr>
- *	<tr>
- *	  <td>&times;10 (0.1°C)</td>
+ *  <tr>
+ *    <td>&times;10 (0.1°C)</td>
  *    <td>9600</td>
  *    <td>8000</td>
  *  </tr>
- *	<tr>
- *	  <td>&times;100 (0.01°C)</td>
+ *  <tr>
+ *    <td>&times;100 (0.01°C)</td>
  *    <td>96000</td>
  *    <td>80000</td>
  *  </tr>
@@ -209,20 +209,20 @@ extern "C" {
  *
  */
 enum tsens_window_mode {
-	/** No window mode */
-	TSENS_WINDOW_MODE_DISABLE          = TSENS_CTRLC_WINMODE_DISABLE,
-	/** RESULT > WINLT */
-	TSENS_WINDOW_MODE_ABOVE            = TSENS_CTRLC_WINMODE_ABOVE,
-	/** RESULT < WINUT */
-	TSENS_WINDOW_MODE_BELOW            = TSENS_CTRLC_WINMODE_BELOW,
-	/** WINLT < RESULT < WINUT */
-	TSENS_WINDOW_MODE_INSIDE           = TSENS_CTRLC_WINMODE_INSIDE,
-	/** !(WINLT < RESULT < WINUT) */
-	TSENS_WINDOW_MODE_OUTSIDE          = TSENS_CTRLC_WINMODE_OUTSIDE,
-	/** VALUE > WINUT with hysteresis to WINLT */
-	TSENS_WINDOW_MODE_HYST_ABOVE       = TSENS_CTRLC_WINMODE_HYST_ABOVE,
-	/** VALUE < WINLT with hysteresis to WINUT */
-	TSENS_WINDOW_MODE_HYST_BELOW       = TSENS_CTRLC_WINMODE_HYST_BELOW,
+    /** No window mode */
+    TSENS_WINDOW_MODE_DISABLE          = TSENS_CTRLC_WINMODE_DISABLE,
+    /** RESULT > WINLT */
+    TSENS_WINDOW_MODE_ABOVE            = TSENS_CTRLC_WINMODE_ABOVE,
+    /** RESULT < WINUT */
+    TSENS_WINDOW_MODE_BELOW            = TSENS_CTRLC_WINMODE_BELOW,
+    /** WINLT < RESULT < WINUT */
+    TSENS_WINDOW_MODE_INSIDE           = TSENS_CTRLC_WINMODE_INSIDE,
+    /** !(WINLT < RESULT < WINUT) */
+    TSENS_WINDOW_MODE_OUTSIDE          = TSENS_CTRLC_WINMODE_OUTSIDE,
+    /** VALUE > WINUT with hysteresis to WINLT */
+    TSENS_WINDOW_MODE_HYST_ABOVE       = TSENS_CTRLC_WINMODE_HYST_ABOVE,
+    /** VALUE < WINLT with hysteresis to WINUT */
+    TSENS_WINDOW_MODE_HYST_BELOW       = TSENS_CTRLC_WINMODE_HYST_BELOW,
 };
 
 /**
@@ -232,10 +232,10 @@ enum tsens_window_mode {
  *
  */
 enum tsens_event_action {
-	/** Event action disabled */
-	TSENS_EVENT_ACTION_DISABLED         = 0,
-	/** Start conversion */
-	TSENS_EVENT_ACTION_START_CONV       = TSENS_EVCTRL_STARTEI,
+    /** Event action disabled */
+    TSENS_EVENT_ACTION_DISABLED         = 0,
+    /** Start conversion */
+    TSENS_EVENT_ACTION_START_CONV       = TSENS_EVCTRL_STARTEI,
 };
 
 /**
@@ -244,12 +244,12 @@ enum tsens_event_action {
  * Window monitor configuration structure.
  */
 struct tsens_window_config {
-	/** Selected window mode */
-	enum tsens_window_mode window_mode;
-	/** Lower window value */
-	int32_t window_lower_value;
-	/** Upper window value */
-	int32_t window_upper_value;
+    /** Selected window mode */
+    enum tsens_window_mode window_mode;
+    /** Lower window value */
+    int32_t window_lower_value;
+    /** Upper window value */
+    int32_t window_upper_value;
 };
 
 /**
@@ -259,8 +259,8 @@ struct tsens_window_config {
  * disable events via \ref tsens_enable_events() and \ref tsens_disable_events().
  */
 struct tsens_events {
-	/** Enable event generation on window monitor */
-	bool generate_event_on_window_monitor;
+    /** Enable event generation on window monitor */
+    bool generate_event_on_window_monitor;
 };
 
 /**
@@ -269,10 +269,10 @@ struct tsens_events {
  * Calibration configuration structure.
  */
 struct tsens_calibration {
-	/** Time amplifier gain */
-	uint32_t gain;
-	/** Offset correction */
-	int32_t offset;
+    /** Time amplifier gain */
+    uint32_t gain;
+    /** Offset correction */
+    int32_t offset;
 };
 
 /**
@@ -283,18 +283,18 @@ struct tsens_calibration {
  * modified by the user application.
  */
 struct tsens_config {
-	/** GCLK generator used to clock the peripheral */
-	enum gclk_generator clock_source;
-	/** Enables free running mode if true */
-	bool free_running;
-	/** Enables TSENS in standby sleep mode if true */
-	bool run_in_standby;
-	/** Window monitor configuration structure */
-	struct tsens_window_config window;
-	/** Event action to take on incoming event */
-	enum tsens_event_action event_action;
-	/** Calibration value */
-	struct tsens_calibration calibration;
+    /** GCLK generator used to clock the peripheral */
+    enum gclk_generator clock_source;
+    /** Enables free running mode if true */
+    bool free_running;
+    /** Enables TSENS in standby sleep mode if true */
+    bool run_in_standby;
+    /** Window monitor configuration structure */
+    struct tsens_window_config window;
+    /** Event action to take on incoming event */
+    enum tsens_event_action event_action;
+    /** Calibration value */
+    struct tsens_calibration calibration;
 };
 
 
@@ -327,31 +327,35 @@ void tsens_get_config_defaults(struct tsens_config *const config);
  */
 static inline uint32_t tsens_get_status(void)
 {
-	uint32_t int_flags = TSENS->INTFLAG.reg;
-
-	uint32_t status_flags = 0;
-
-	/* Check for TSENS Result Ready */
-	if (int_flags & TSENS_INTFLAG_RESRDY) {
-		status_flags |= TSENS_STATUS_RESULT_READY;
-	}
-
-	/* Check for TSENS Overrun */
-	if (int_flags & TSENS_INTFLAG_OVERRUN) {
-		status_flags |= TSENS_STATUS_OVERRUN;
-	}
-
-	/* Check for TSENS Window Match */
-	if (int_flags & TSENS_INTFLAG_WINMON) {
-		status_flags |= TSENS_STATUS_WINDOW;
-	}
-
-	/* Check for TSENS overflow */
-	if (int_flags & TSENS_INTFLAG_OVF) {
-		status_flags |= TSENS_STATUS_OVERFLOW;
-	}
-
-	return status_flags;
+    uint32_t int_flags = TSENS->INTFLAG.reg;
+
+    uint32_t status_flags = 0;
+
+    /* Check for TSENS Result Ready */
+    if (int_flags & TSENS_INTFLAG_RESRDY)
+    {
+        status_flags |= TSENS_STATUS_RESULT_READY;
+    }
+
+    /* Check for TSENS Overrun */
+    if (int_flags & TSENS_INTFLAG_OVERRUN)
+    {
+        status_flags |= TSENS_STATUS_OVERRUN;
+    }
+
+    /* Check for TSENS Window Match */
+    if (int_flags & TSENS_INTFLAG_WINMON)
+    {
+        status_flags |= TSENS_STATUS_WINDOW;
+    }
+
+    /* Check for TSENS overflow */
+    if (int_flags & TSENS_INTFLAG_OVF)
+    {
+        status_flags |= TSENS_STATUS_OVERFLOW;
+    }
+
+    return status_flags;
 }
 
 /**
@@ -364,30 +368,34 @@ static inline uint32_t tsens_get_status(void)
  */
 static inline void tsens_clear_status(const uint32_t status_flags)
 {
-	uint32_t int_flags = 0;
-
-	/* Check for TSENS Result Ready */
-	if (status_flags & TSENS_INTFLAG_RESRDY) {
-		 int_flags |= TSENS_STATUS_RESULT_READY;
-	}
-
-	/* Check for TSENS Overrun */
-	if (status_flags & TSENS_INTFLAG_OVERRUN) {
-		int_flags |= TSENS_STATUS_OVERRUN;
-	}
-
-	/* Check for TSENS Window Match */
-	if (status_flags & TSENS_INTFLAG_WINMON) {
-		int_flags |= TSENS_STATUS_WINDOW;
-	}
-
-	/* Check for TSENS overflow */
-	if (status_flags & TSENS_INTFLAG_OVF) {
-		int_flags |= TSENS_STATUS_OVERFLOW;
-	}
-
-	/* Clear interrupt flag */
-	TSENS->INTFLAG.reg = int_flags;
+    uint32_t int_flags = 0;
+
+    /* Check for TSENS Result Ready */
+    if (status_flags & TSENS_INTFLAG_RESRDY)
+    {
+         int_flags |= TSENS_STATUS_RESULT_READY;
+    }
+
+    /* Check for TSENS Overrun */
+    if (status_flags & TSENS_INTFLAG_OVERRUN)
+    {
+        int_flags |= TSENS_STATUS_OVERRUN;
+    }
+
+    /* Check for TSENS Window Match */
+    if (status_flags & TSENS_INTFLAG_WINMON)
+    {
+        int_flags |= TSENS_STATUS_WINDOW;
+    }
+
+    /* Check for TSENS overflow */
+    if (status_flags & TSENS_INTFLAG_OVF)
+    {
+        int_flags |= TSENS_STATUS_OVERFLOW;
+    }
+
+    /* Clear interrupt flag */
+    TSENS->INTFLAG.reg = int_flags;
 }
 
 /** @} */
@@ -413,11 +421,12 @@ static inline void tsens_clear_status(const uint32_t status_flags)
  */
 static inline bool tsens_is_syncing(void)
 {
-	if (TSENS->SYNCBUSY.reg) {
-		return true;
-	}
+    if (TSENS->SYNCBUSY.reg)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -428,11 +437,12 @@ static inline bool tsens_is_syncing(void)
  */
 static inline void tsens_enable(void)
 {
-	TSENS->CTRLA.reg |= TSENS_CTRLA_ENABLE;
+    TSENS->CTRLA.reg |= TSENS_CTRLA_ENABLE;
 
-	while (tsens_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    while (tsens_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -443,13 +453,14 @@ static inline void tsens_enable(void)
  */
 static inline void tsens_disable(void)
 {
-	TSENS->INTENCLR.reg = TSENS_INTENCLR_MASK;
-	TSENS->INTFLAG.reg = TSENS_INTFLAG_MASK;
-	TSENS->CTRLA.reg &= ~TSENS_CTRLA_ENABLE;
-
-	while (tsens_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    TSENS->INTENCLR.reg = TSENS_INTENCLR_MASK;
+    TSENS->INTFLAG.reg = TSENS_INTFLAG_MASK;
+    TSENS->CTRLA.reg &= ~TSENS_CTRLA_ENABLE;
+
+    while (tsens_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 /**
@@ -461,15 +472,16 @@ static inline void tsens_disable(void)
  */
 static inline void tsens_reset(void)
 {
-	/* Disable to make sure the pipeline is flushed before reset */
-	tsens_disable();
+    /* Disable to make sure the pipeline is flushed before reset */
+    tsens_disable();
 
-	/* Software reset the module */
-	TSENS->CTRLA.reg |= TSENS_CTRLA_SWRST;
+    /* Software reset the module */
+    TSENS->CTRLA.reg |= TSENS_CTRLA_SWRST;
 
-	while (tsens_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    while (tsens_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 
@@ -485,17 +497,18 @@ static inline void tsens_reset(void)
  */
 static inline void tsens_enable_events(struct tsens_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(events);
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= TSENS_EVCTRL_WINEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= TSENS_EVCTRL_WINEO;
+    }
 
-	TSENS->EVCTRL.reg |= event_mask;
+    TSENS->EVCTRL.reg |= event_mask;
 }
 
 /**
@@ -510,17 +523,18 @@ static inline void tsens_enable_events(struct tsens_events *const events)
  */
 static inline void tsens_disable_events(struct tsens_events *const events)
 {
-	/* Sanity check arguments */
-	Assert(events);
+    /* Sanity check arguments */
+    Assert(events);
 
-	uint32_t event_mask = 0;
+    uint32_t event_mask = 0;
 
-	/* Configure Window Monitor event */
-	if (events->generate_event_on_window_monitor) {
-		event_mask |= TSENS_EVCTRL_WINEO;
-	}
+    /* Configure Window Monitor event */
+    if (events->generate_event_on_window_monitor)
+    {
+        event_mask |= TSENS_EVCTRL_WINEO;
+    }
 
-	TSENS->EVCTRL.reg &= ~event_mask;
+    TSENS->EVCTRL.reg &= ~event_mask;
 }
 
 /**
@@ -531,11 +545,12 @@ static inline void tsens_disable_events(struct tsens_events *const events)
  */
 static inline void tsens_start_conversion(void)
 {
-	TSENS->CTRLB.reg |= TSENS_CTRLB_START;
+    TSENS->CTRLB.reg |= TSENS_CTRLB_START;
 
-	while (tsens_is_syncing()) {
-		/* Wait for synchronization */
-	}
+    while (tsens_is_syncing())
+    {
+        /* Wait for synchronization */
+    }
 }
 
 enum status_code tsens_read(int32_t *result);
@@ -551,14 +566,14 @@ enum status_code tsens_read(int32_t *result);
  * intended meaning.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
  *  <tr>
- *		<td>TSENS</td>
- *		<td>Temperature Sensor</td>
- *	</tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>TSENS</td>
+ *      <td>Temperature Sensor</td>
+ *  </tr>
  * </table>
  *
  *
@@ -580,12 +595,12 @@ enum status_code tsens_read(int32_t *result);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
-  *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+  * <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -604,16 +619,16 @@ enum status_code tsens_read(int32_t *result);
  * \page asfdoc_sam0_tsens_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42542A</td>
- *		<td>12/2015</td>
- *		<td>Initial document release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42542A</td>
+ *      <td>12/2015</td>
+ *      <td>Initial document release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c
index ef7fd46ca697..dbce0fbf506a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.c
@@ -51,32 +51,35 @@ struct tsens_module *_tsens_instances;
 /** Interrupt handler for the TSENS module. */
 void TSENS_Handler(void)
 {
-	struct tsens_module *module = _tsens_instances;
-	Assert(module);
-
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = TSENS->INTFLAG.reg;
-
-	/* store TSENS result in job buffer */
-	uint32_t temp = TSENS->VALUE.reg;
-	if(temp & 0x00800000) {
-		temp |= ~TSENS_VALUE_MASK;
-	}
+    struct tsens_module *module = _tsens_instances;
+    Assert(module);
+
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = TSENS->INTFLAG.reg;
+
+    /* store TSENS result in job buffer */
+    uint32_t temp = TSENS->VALUE.reg;
+    if(temp & 0x00800000)
+    {
+        temp |= ~TSENS_VALUE_MASK;
+    }
 #if (ERRATA_14476)
-	*(module->value) = temp * (-1);
+    *(module->value) = temp * (-1);
 #endif
 
-	for(uint8_t i = 0; i < TSENS_CALLBACK_NUM; i++)
-	{
-		if (flags & ((uint32_t)0x01 << i)) {
-			/* Clear the INTFLAG anyway */
-			TSENS->INTFLAG.reg = (uint32_t)0x01 << i;
-
-			if(module->callback[i] != NULL) {
-				module->callback[i]((enum tsens_callback)i);
-			}
-		}
-	}
+    for(uint8_t i = 0; i < TSENS_CALLBACK_NUM; i++)
+    {
+        if (flags & ((uint32_t)0x01 << i))
+        {
+            /* Clear the INTFLAG anyway */
+            TSENS->INTFLAG.reg = (uint32_t)0x01 << i;
+
+            if(module->callback[i] != NULL)
+            {
+                module->callback[i]((enum tsens_callback)i);
+            }
+        }
+    }
 }
 
 /**
@@ -93,23 +96,24 @@ void TSENS_Handler(void)
  *
  */
 enum status_code tsens_register_callback(
-		struct tsens_module *const module,
-		tsens_callback_t callback_func,
-		enum tsens_callback callback_type)
+        struct tsens_module *const module,
+        tsens_callback_t callback_func,
+        enum tsens_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	if(callback_type > TSENS_CALLBACK_NUM) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if(callback_type > TSENS_CALLBACK_NUM)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-	_tsens_instances = module;
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
+    _tsens_instances = module;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -122,20 +126,21 @@ enum status_code tsens_register_callback(
  *
  */
 enum status_code tsens_unregister_callback(
-		struct tsens_module *const module,
-		enum tsens_callback callback_type)
+        struct tsens_module *const module,
+        enum tsens_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	if(callback_type > TSENS_CALLBACK_NUM) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if(callback_type > TSENS_CALLBACK_NUM)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Register callback function */
-	module->callback[callback_type] = NULL;
+    /* Register callback function */
+    module->callback[callback_type] = NULL;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -146,15 +151,16 @@ enum status_code tsens_unregister_callback(
  *
  */
 void tsens_read_job(
-		struct tsens_module *const module_inst,
-		int32_t *result)
+        struct tsens_module *const module_inst,
+        int32_t *result)
 {
-	Assert(module_inst);
-	Assert(result);
+    Assert(module_inst);
+    Assert(result);
 
-	module_inst->value = result;
+    module_inst->value = result;
 
-	if(!(TSENS->CTRLC.reg & TSENS_CTRLC_FREERUN)) {
-		tsens_start_conversion();
-	}
+    if(!(TSENS->CTRLC.reg & TSENS_CTRLC_FREERUN))
+    {
+        tsens_start_conversion();
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h
index 9ce663570707..fb0faae9f693 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/tsens/tsens_callback.h
@@ -68,17 +68,17 @@ extern "C" {
  *
  */
 enum tsens_callback {
-	/** Callback for result ready */
-	TSENS_CALLBACK_RESULT_READY,
-	/** Callback when result overwritten before read */
-	TSENS_CALLBACK_OVERRUN,
-	/** Callback when window is hit */
-	TSENS_CALLBACK_WINDOW,
-	/** Callback when the result overflows */
-	TSENS_CALLBACK_OVF,
+    /** Callback for result ready */
+    TSENS_CALLBACK_RESULT_READY,
+    /** Callback when result overwritten before read */
+    TSENS_CALLBACK_OVERRUN,
+    /** Callback when window is hit */
+    TSENS_CALLBACK_WINDOW,
+    /** Callback when the result overflows */
+    TSENS_CALLBACK_OVF,
 #  if !defined(__DOXYGEN__)
-	/** Number of available callbacks */
-	TSENS_CALLBACK_NUM,
+    /** Number of available callbacks */
+    TSENS_CALLBACK_NUM,
 #  endif
 };
 
@@ -96,10 +96,10 @@ typedef void (*tsens_callback_t)(enum tsens_callback);
  */
 struct tsens_module {
 #if !defined(__DOXYGEN__)
-	/** Array to store callback functions. */
-	tsens_callback_t callback[TSENS_CALLBACK_NUM];
-	/** Pointer to used for TSENS results. */
-	volatile int32_t *value;
+    /** Array to store callback functions. */
+    tsens_callback_t callback[TSENS_CALLBACK_NUM];
+    /** Pointer to used for TSENS results. */
+    volatile int32_t *value;
 #endif
 };
 
@@ -108,13 +108,13 @@ struct tsens_module {
  * @{
  */
 enum status_code tsens_register_callback(
-			struct tsens_module *const module,
-			tsens_callback_t callback_func,
-			enum tsens_callback callback_type);
+            struct tsens_module *const module,
+            tsens_callback_t callback_func,
+            enum tsens_callback callback_type);
 
 enum status_code tsens_unregister_callback(
-			struct tsens_module *const module,
-			enum tsens_callback callback_type);
+            struct tsens_module *const module,
+            enum tsens_callback callback_type);
 
 /**
  * \brief Enables callback.
@@ -128,28 +128,29 @@ enum status_code tsens_unregister_callback(
  */
 static inline void tsens_enable_callback(enum tsens_callback callback_type)
 {
-	uint32_t inenset_temp = 0;
-
-	switch (callback_type) {
-		case TSENS_CALLBACK_RESULT_READY:
-			inenset_temp |= TSENS_INTFLAG_RESRDY;
-			break;
-		case TSENS_CALLBACK_OVERRUN:
-			inenset_temp |= TSENS_INTENSET_OVERRUN;
-			break;
-		case TSENS_CALLBACK_WINDOW:
-			inenset_temp |= TSENS_INTENSET_WINMON;
-			break;
-		case TSENS_CALLBACK_OVF:
-			inenset_temp |= TSENS_INTENSET_OVF;
-			break;
-
-		default:
-			break;
-	}
-
-	/* Enable the interrupt for the callback */
-	TSENS->INTENSET.reg = inenset_temp;
+    uint32_t inenset_temp = 0;
+
+    switch (callback_type)
+    {
+        case TSENS_CALLBACK_RESULT_READY:
+            inenset_temp |= TSENS_INTFLAG_RESRDY;
+            break;
+        case TSENS_CALLBACK_OVERRUN:
+            inenset_temp |= TSENS_INTENSET_OVERRUN;
+            break;
+        case TSENS_CALLBACK_WINDOW:
+            inenset_temp |= TSENS_INTENSET_WINMON;
+            break;
+        case TSENS_CALLBACK_OVF:
+            inenset_temp |= TSENS_INTENSET_OVF;
+            break;
+
+        default:
+            break;
+    }
+
+    /* Enable the interrupt for the callback */
+    TSENS->INTENSET.reg = inenset_temp;
 }
 
 /**
@@ -163,28 +164,29 @@ static inline void tsens_enable_callback(enum tsens_callback callback_type)
  */
 static inline void tsens_disable_callback(enum tsens_callback callback_type)
 {
-	uint32_t inenclr_temp = 0;
-
-	switch (callback_type) {
-		case TSENS_CALLBACK_RESULT_READY:
-			inenclr_temp |= TSENS_INTENCLR_OVERRUN;
-			break;
-		case TSENS_CALLBACK_OVERRUN:
-			inenclr_temp |= TSENS_INTENSET_OVERRUN;
-			break;
-		case TSENS_CALLBACK_WINDOW:
-			inenclr_temp |= TSENS_INTENSET_WINMON;
-			break;
-		case TSENS_CALLBACK_OVF:
-			inenclr_temp |= TSENS_INTENSET_OVF;
-			break;
-
-		default:
-			break;
-	}
-
-	/* Disable the interrupt for the callback */
-	TSENS->INTENCLR.reg = inenclr_temp;
+    uint32_t inenclr_temp = 0;
+
+    switch (callback_type)
+    {
+        case TSENS_CALLBACK_RESULT_READY:
+            inenclr_temp |= TSENS_INTENCLR_OVERRUN;
+            break;
+        case TSENS_CALLBACK_OVERRUN:
+            inenclr_temp |= TSENS_INTENSET_OVERRUN;
+            break;
+        case TSENS_CALLBACK_WINDOW:
+            inenclr_temp |= TSENS_INTENSET_WINMON;
+            break;
+        case TSENS_CALLBACK_OVF:
+            inenclr_temp |= TSENS_INTENSET_OVF;
+            break;
+
+        default:
+            break;
+    }
+
+    /* Disable the interrupt for the callback */
+    TSENS->INTENCLR.reg = inenclr_temp;
 }
 
 void tsens_read_job(struct tsens_module *const module_inst, int32_t *result);
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c
index 057fd1cfb67e..185f6f496a5a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.c
@@ -59,19 +59,19 @@ struct uart_module *_uart_instances[UART_INST_NUM];
  */
 static void _uart_write(struct uart_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Uart *const uart_hw = module->hw;
+    /* Pointer to the hardware module instance */
+    Uart *const uart_hw = module->hw;
 
-	/* Write value will be at least 8-bits long */
-	uint8_t data_to_send = *(module->tx_buffer_ptr);
-	/* Increment 8-bit pointer */
-	(module->tx_buffer_ptr)++;
+    /* Write value will be at least 8-bits long */
+    uint8_t data_to_send = *(module->tx_buffer_ptr);
+    /* Increment 8-bit pointer */
+    (module->tx_buffer_ptr)++;
 
-	/* Write the data to send*/
-	uart_hw->TRANSMIT_DATA.reg = data_to_send & UART_TRANSMIT_DATA_MASK;
+    /* Write the data to send*/
+    uart_hw->TRANSMIT_DATA.reg = data_to_send & UART_TRANSMIT_DATA_MASK;
 
-	/* Decrement remaining buffer length */
-	(module->remaining_tx_buffer_length)--;
+    /* Decrement remaining buffer length */
+    (module->remaining_tx_buffer_length)--;
 }
 
 /**
@@ -81,181 +81,204 @@ static void _uart_write(struct uart_module *const module)
  * \param[in,out]  module  Pointer to UART software instance struct
  */
 static void _uart_read(
-		struct uart_module *const module)
+        struct uart_module *const module)
 {
-	/* Pointer to the hardware module instance */
-	Uart *const uart_hw = module->hw;
+    /* Pointer to the hardware module instance */
+    Uart *const uart_hw = module->hw;
 
-	uint16_t received_data = (uart_hw->RECEIVE_DATA.reg & UART_RECEIVE_DATA_MASK);
+    uint16_t received_data = (uart_hw->RECEIVE_DATA.reg & UART_RECEIVE_DATA_MASK);
 
-	/* Read value will be at least 8-bits long */
-	*(module->rx_buffer_ptr) = received_data;
-	/* Increment 8-bit pointer */
-	module->rx_buffer_ptr += 1;
+    /* Read value will be at least 8-bits long */
+    *(module->rx_buffer_ptr) = received_data;
+    /* Increment 8-bit pointer */
+    module->rx_buffer_ptr += 1;
 
-	/* Decrement length of the remaining buffer */
-	module->remaining_rx_buffer_length--;
+    /* Decrement length of the remaining buffer */
+    module->remaining_rx_buffer_length--;
 }
 
 static void uart_rx0_isr_handler(void)
 {
-	struct uart_module *module = _uart_instances[0];
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
-	if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
-		/* Store the error code */
-		module->status = STATUS_ERR_OVERFLOW;
-		/* Disable interrupt */
-		module->hw->RX_INTERRUPT_MASK.reg &=
-			~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
-			SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-		if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
-			(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
-			(module->callback[UART_RX_FIFO_OVERRUN])(module);
-		}
-		/* Flush */
-		uint8_t flush = module->hw->RECEIVE_DATA.reg;
-		UNUSED(flush);
-	}
-	if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		_uart_read(module);
-		if (module->remaining_rx_buffer_length == 0) {
-			if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
-				(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
-				module->status = STATUS_OK;
-				module->hw->RX_INTERRUPT_MASK.reg &=
-					~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-				(module->callback[UART_RX_COMPLETE])(module);
-			}
-		}
-	}
+    struct uart_module *module = _uart_instances[0];
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+    if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN)
+    {
+        /* Store the error code */
+        module->status = STATUS_ERR_OVERFLOW;
+        /* Disable interrupt */
+        module->hw->RX_INTERRUPT_MASK.reg &=
+            ~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+            SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+        if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
+            (module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN)))
+            {
+            (module->callback[UART_RX_FIFO_OVERRUN])(module);
+        }
+        /* Flush */
+        uint8_t flush = module->hw->RECEIVE_DATA.reg;
+        UNUSED(flush);
+    }
+    if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        _uart_read(module);
+        if (module->remaining_rx_buffer_length == 0)
+        {
+            if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
+                (module->callback_reg_mask & (1 << UART_RX_COMPLETE)))
+                {
+                module->status = STATUS_OK;
+                module->hw->RX_INTERRUPT_MASK.reg &=
+                    ~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                (module->callback[UART_RX_COMPLETE])(module);
+            }
+        }
+    }
 }
 
 static void uart_tx0_isr_handler(void)
 {
-	struct uart_module *module = _uart_instances[0];
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
-	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
-		_uart_write(module);
-		if (module->remaining_tx_buffer_length == 0) {
-			module->hw->TX_INTERRUPT_MASK.reg &=
-					~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-			module->hw->TX_INTERRUPT_MASK.reg |=
-					UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-		}
-	}
-	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
-		if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
-			(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
-			module->status = STATUS_OK;
-			/* Disable interrupt */
-			module->hw->TX_INTERRUPT_MASK.reg &=
-				~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-			(module->callback[UART_TX_COMPLETE])(module);
-		}
-
-	}
-	if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
-		if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
-			(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
-			(module->callback[UART_CTS_ACTIVE])(module);
-		}
-
-	}
+    struct uart_module *module = _uart_instances[0];
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+    if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL)
+    {
+        _uart_write(module);
+        if (module->remaining_tx_buffer_length == 0)
+        {
+            module->hw->TX_INTERRUPT_MASK.reg &=
+                    ~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+            module->hw->TX_INTERRUPT_MASK.reg |=
+                    UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+        }
+    }
+    if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY)
+    {
+        if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
+            (module->callback_reg_mask & (1 << UART_TX_COMPLETE)))
+            {
+            module->status = STATUS_OK;
+            /* Disable interrupt */
+            module->hw->TX_INTERRUPT_MASK.reg &=
+                ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+            (module->callback[UART_TX_COMPLETE])(module);
+        }
+
+    }
+    if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE)
+    {
+        if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
+            (module->callback_reg_mask & (1 << UART_CTS_ACTIVE)))
+            {
+            (module->callback[UART_CTS_ACTIVE])(module);
+        }
+
+    }
 }
 
 static void uart_rx1_isr_handler(void)
 {
-	struct uart_module *module = _uart_instances[1];
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->RECEIVE_STATUS.reg;
-	if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN) {
-		/* Store the error code */
-		module->status = STATUS_ERR_OVERFLOW;
-		/* Disable interrupt */
-		module->hw->RX_INTERRUPT_MASK.reg &=
-			~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
-			SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-		if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
-			(module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN))) {
-			(module->callback[UART_RX_FIFO_OVERRUN])(module);
-		}
-		/* Flush */
-		uint8_t flush = module->hw->RECEIVE_DATA.reg;
-		UNUSED(flush);
-	}
-	if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		_uart_read(module);
-		if (module->remaining_rx_buffer_length == 0) {
-			if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
-				(module->callback_reg_mask & (1 << UART_RX_COMPLETE))) {
-				module->status = STATUS_OK;
-				module->hw->RX_INTERRUPT_MASK.reg &=
-					~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
-				(module->callback[UART_RX_COMPLETE])(module);
-			}
-		}
-	}
+    struct uart_module *module = _uart_instances[1];
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->RECEIVE_STATUS.reg;
+    if (flags & UART_RECEIVE_STATUS_FIFO_OVERRUN)
+    {
+        /* Store the error code */
+        module->status = STATUS_ERR_OVERFLOW;
+        /* Disable interrupt */
+        module->hw->RX_INTERRUPT_MASK.reg &=
+            ~(UART_RX_INTERRUPT_MASK_FIFO_OVERRUN_MASK |
+            SPI_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+        if ((module->callback_enable_mask & (1 << UART_RX_FIFO_OVERRUN)) &&
+            (module->callback_reg_mask & (1 << UART_RX_FIFO_OVERRUN)))
+            {
+            (module->callback[UART_RX_FIFO_OVERRUN])(module);
+        }
+        /* Flush */
+        uint8_t flush = module->hw->RECEIVE_DATA.reg;
+        UNUSED(flush);
+    }
+    if (flags & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        _uart_read(module);
+        if (module->remaining_rx_buffer_length == 0)
+        {
+            if ((module->callback_enable_mask & (1 << UART_RX_COMPLETE)) &&
+                (module->callback_reg_mask & (1 << UART_RX_COMPLETE)))
+                {
+                module->status = STATUS_OK;
+                module->hw->RX_INTERRUPT_MASK.reg &=
+                    ~(UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK);
+                (module->callback[UART_RX_COMPLETE])(module);
+            }
+        }
+    }
 }
 
 static void uart_tx1_isr_handler(void)
 {
-	struct uart_module *module = _uart_instances[1];
-	/* get interrupt flags and mask out enabled callbacks */
-	uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
-	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL) {
-		_uart_write(module);
-		if (module->remaining_tx_buffer_length == 0) {
-			module->hw->TX_INTERRUPT_MASK.reg &=
-					~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
-			module->hw->TX_INTERRUPT_MASK.reg |=
-					UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-		}
-	}
-	if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY) {
-		if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
-			(module->callback_reg_mask & (1 << UART_TX_COMPLETE))) {
-			module->status = STATUS_OK;
-			/* Disable interrupt */
-			module->hw->TX_INTERRUPT_MASK.reg &=
-				~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-			(module->callback[UART_TX_COMPLETE])(module);
-		}
-
-	}
-	if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE) {
-		if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
-			(module->callback_reg_mask & (1 << UART_CTS_ACTIVE))) {
-			(module->callback[UART_CTS_ACTIVE])(module);
-		}
-
-	}
+    struct uart_module *module = _uart_instances[1];
+    /* get interrupt flags and mask out enabled callbacks */
+    uint32_t flags = module->hw->TRANSMIT_STATUS.reg;
+    if (flags & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL)
+    {
+        _uart_write(module);
+        if (module->remaining_tx_buffer_length == 0)
+        {
+            module->hw->TX_INTERRUPT_MASK.reg &=
+                    ~UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+            module->hw->TX_INTERRUPT_MASK.reg |=
+                    UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+        }
+    }
+    if (flags & UART_TRANSMIT_STATUS_TX_FIFO_EMPTY)
+    {
+        if ((module->callback_enable_mask & (1 << UART_TX_COMPLETE)) &&
+            (module->callback_reg_mask & (1 << UART_TX_COMPLETE)))
+            {
+            module->status = STATUS_OK;
+            /* Disable interrupt */
+            module->hw->TX_INTERRUPT_MASK.reg &=
+                ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+            (module->callback[UART_TX_COMPLETE])(module);
+        }
+
+    }
+    if (flags & UART_TRANSMIT_STATUS_CTS_ACTIVE)
+    {
+        if ((module->callback_enable_mask & (1 << UART_CTS_ACTIVE)) &&
+            (module->callback_reg_mask & (1 << UART_CTS_ACTIVE)))
+            {
+            (module->callback[UART_CTS_ACTIVE])(module);
+        }
+
+    }
 }
 
 static void uart_set_baudrate(struct uart_module *const module,
-		const uint32_t baud_rate)
+        const uint32_t baud_rate)
 {
-	uint32_t clock;
-	uint16_t integerpart = 0;
-	uint8_t fractionalpart = 0;
-	uint32_t diff;
-	uint8_t i = 0;
-
-	clock = system_clock_get_value();
-	integerpart = clock / baud_rate;
-	diff = clock - (baud_rate * integerpart);
-	i = 0;
-	while(diff > (baud_rate / 16)) {
-		i++;
-		diff -= (baud_rate / 16);
-	}
-	fractionalpart = (i + 1) / 2;
-
-	module->hw->UART_CLOCK_SOURCE.reg = UART_CLOCK_SOURCE_CLOCK_SELECT_0;
-	module->hw->UART_BAUD_RATE.reg =
-		UART_BAUD_RATE_INTEGER_DIVISION(integerpart) |
-		UART_BAUD_RATE_FRACTIONAL_DIVISION(fractionalpart);
+    uint32_t clock;
+    uint16_t integerpart = 0;
+    uint8_t fractionalpart = 0;
+    uint32_t diff;
+    uint8_t i = 0;
+
+    clock = system_clock_get_value();
+    integerpart = clock / baud_rate;
+    diff = clock - (baud_rate * integerpart);
+    i = 0;
+    while(diff > (baud_rate / 16))
+    {
+        i++;
+        diff -= (baud_rate / 16);
+    }
+    fractionalpart = (i + 1) / 2;
+
+    module->hw->UART_CLOCK_SOURCE.reg = UART_CLOCK_SOURCE_CLOCK_SELECT_0;
+    module->hw->UART_BAUD_RATE.reg =
+        UART_BAUD_RATE_INTEGER_DIVISION(integerpart) |
+        UART_BAUD_RATE_FRACTIONAL_DIVISION(fractionalpart);
 }
 
 /**
@@ -273,23 +296,23 @@ static void uart_set_baudrate(struct uart_module *const module,
  * \param[out] config  Pointer to configuration structure to be initiated
  */
 void uart_get_config_defaults(
-		struct uart_config *const config)
+        struct uart_config *const config)
 {
-	config->baud_rate = 115200;
-	config->data_bits = UART_8_BITS;
-	config->stop_bits = UART_1_STOP_BIT;
-	config->parity = UART_NO_PARITY;
-	config->flow_control = false;
-
-	config->pin_number_pad[0] = PIN_LP_GPIO_2;
-	config->pin_number_pad[1] = PIN_LP_GPIO_3;
-	config->pin_number_pad[2] = PIN_LP_GPIO_4;
-	config->pin_number_pad[3] = PIN_LP_GPIO_5;
-
-	config->pinmux_sel_pad[0] = MUX_LP_GPIO_2_UART0_RXD;
-	config->pinmux_sel_pad[1] = MUX_LP_GPIO_3_UART0_TXD;
-	config->pinmux_sel_pad[2] = MUX_LP_GPIO_4_UART0_CTS;
-	config->pinmux_sel_pad[3] = MUX_LP_GPIO_5_UART0_RTS;
+    config->baud_rate = 115200;
+    config->data_bits = UART_8_BITS;
+    config->stop_bits = UART_1_STOP_BIT;
+    config->parity = UART_NO_PARITY;
+    config->flow_control = false;
+
+    config->pin_number_pad[0] = PIN_LP_GPIO_2;
+    config->pin_number_pad[1] = PIN_LP_GPIO_3;
+    config->pin_number_pad[2] = PIN_LP_GPIO_4;
+    config->pin_number_pad[3] = PIN_LP_GPIO_5;
+
+    config->pinmux_sel_pad[0] = MUX_LP_GPIO_2_UART0_RXD;
+    config->pinmux_sel_pad[1] = MUX_LP_GPIO_3_UART0_TXD;
+    config->pinmux_sel_pad[2] = MUX_LP_GPIO_4_UART0_CTS;
+    config->pinmux_sel_pad[3] = MUX_LP_GPIO_5_UART0_RTS;
 }
 
 /**
@@ -307,119 +330,127 @@ void uart_get_config_defaults(
  * \retval STATUS_OK                       The initialization was successful
  */
 enum status_code uart_init(struct uart_module *const module, Uart * const hw,
-		const struct uart_config *const config)
+        const struct uart_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
-
-	uint8_t config_temp = 0;
-	uint8_t i,index;
-
-	/* Assign module pointer to software instance struct */
-	module->hw = hw;
-
-	for (i = 0; i < UART_CALLBACK_N; i++) {
-		module->callback[i] = NULL;
-	}
-	module->rx_buffer_ptr = NULL;
-	module->tx_buffer_ptr = NULL;
-	module->remaining_rx_buffer_length = 0;
-	module->remaining_tx_buffer_length = 0;
-	module->callback_reg_mask = 0;
-	module->callback_enable_mask = 0;
-	module->status = STATUS_OK;
-
-	if (hw == UART0) {
-		system_peripheral_reset(PERIPHERAL_UART0_CORE);
-		system_peripheral_reset(PERIPHERAL_UART0_IF);
-		system_clock_peripheral_enable(PERIPHERAL_UART0_CORE);
-		system_clock_peripheral_enable(PERIPHERAL_UART0_IF);
-		_uart_instances[0] = module;
-		system_register_isr(RAM_ISR_TABLE_UARTRX0_INDEX, (uint32_t)uart_rx0_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_UARTTX0_INDEX, (uint32_t)uart_tx0_isr_handler);
-		NVIC_EnableIRQ(UART0_RX_IRQn);
-		NVIC_EnableIRQ(UART0_TX_IRQn);
-	} else if (hw == UART1) {
-		system_peripheral_reset(PERIPHERAL_UART1_CORE);
-		system_peripheral_reset(PERIPHERAL_UART1_IF);
-		system_clock_peripheral_enable(PERIPHERAL_UART1_CORE);
-		system_clock_peripheral_enable(PERIPHERAL_UART1_IF);
-		_uart_instances[1] = module;
-		system_register_isr(RAM_ISR_TABLE_UARTRX1_INDEX, (uint32_t)uart_rx1_isr_handler);
-		system_register_isr(RAM_ISR_TABLE_UARTTX1_INDEX, (uint32_t)uart_tx1_isr_handler);
-		NVIC_EnableIRQ(UART1_RX_IRQn);
-		NVIC_EnableIRQ(UART1_TX_IRQn);
-	}
-
-	/* Set the pinmux for this UART module. */
-	if(config->flow_control) {
-		index = 4;
-	} else {
-		index = 2;
-	}
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
+
+    uint8_t config_temp = 0;
+    uint8_t i,index;
+
+    /* Assign module pointer to software instance struct */
+    module->hw = hw;
+
+    for (i = 0; i < UART_CALLBACK_N; i++)
+    {
+        module->callback[i] = NULL;
+    }
+    module->rx_buffer_ptr = NULL;
+    module->tx_buffer_ptr = NULL;
+    module->remaining_rx_buffer_length = 0;
+    module->remaining_tx_buffer_length = 0;
+    module->callback_reg_mask = 0;
+    module->callback_enable_mask = 0;
+    module->status = STATUS_OK;
+
+    if (hw == UART0)
+    {
+        system_peripheral_reset(PERIPHERAL_UART0_CORE);
+        system_peripheral_reset(PERIPHERAL_UART0_IF);
+        system_clock_peripheral_enable(PERIPHERAL_UART0_CORE);
+        system_clock_peripheral_enable(PERIPHERAL_UART0_IF);
+        _uart_instances[0] = module;
+        system_register_isr(RAM_ISR_TABLE_UARTRX0_INDEX, (uint32_t)uart_rx0_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_UARTTX0_INDEX, (uint32_t)uart_tx0_isr_handler);
+        NVIC_EnableIRQ(UART0_RX_IRQn);
+        NVIC_EnableIRQ(UART0_TX_IRQn);
+    } else if (hw == UART1)
+    {
+        system_peripheral_reset(PERIPHERAL_UART1_CORE);
+        system_peripheral_reset(PERIPHERAL_UART1_IF);
+        system_clock_peripheral_enable(PERIPHERAL_UART1_CORE);
+        system_clock_peripheral_enable(PERIPHERAL_UART1_IF);
+        _uart_instances[1] = module;
+        system_register_isr(RAM_ISR_TABLE_UARTRX1_INDEX, (uint32_t)uart_rx1_isr_handler);
+        system_register_isr(RAM_ISR_TABLE_UARTTX1_INDEX, (uint32_t)uart_tx1_isr_handler);
+        NVIC_EnableIRQ(UART1_RX_IRQn);
+        NVIC_EnableIRQ(UART1_TX_IRQn);
+    }
+
+    /* Set the pinmux for this UART module. */
+    if(config->flow_control)
+    {
+        index = 4;
+    } else {
+        index = 2;
+    }
 
 #if (BTLC1000)
     index = 2;  /* BTLC1000 has no flow control function. */
 #endif
 
-	for(i = 0; i < index; i++) {
-		gpio_pinmux_cofiguration(config->pin_number_pad[i], \
-								(uint16_t)(config->pinmux_sel_pad[i]));
-	}
-
-	/* empty UART FIFO */
-	while (module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY) {
-		i = module->hw->RECEIVE_DATA.reg;
-	}
-	
-	/* reset configuration register */
-	module->hw->UART_CONFIGURATION.reg = 0;
-
-	/* program the uart configuration. */
-	if(config->flow_control) {
-		config_temp |= UART_CONFIGURATION_CTS_ENABLE_1;
-	}
-	config_temp |= config->data_bits;
-	config_temp |= config->stop_bits;
-	switch(config->parity) {
-		case UART_NO_PARITY:
-			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_0;
-			break;
-
-		case UART_EVEN_PARITY:
-			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
-			config_temp |= UART_CONFIGURATION_PARITY_MODE_0;
-			break;
-
-		case UART_ODD_PARITY:
-			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
-			config_temp |= UART_CONFIGURATION_PARITY_MODE_1;
-			break;
-
-		case UART_SPACE_PARITY:
-			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
-			config_temp |= UART_CONFIGURATION_PARITY_MODE_2;
-			break;
-
-		case UART_MARK_PARITY:
-			config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
-			config_temp |= UART_CONFIGURATION_PARITY_MODE_3;
-			break;
-
-		default:
-			break;
-	}	
-	module->hw->UART_CONFIGURATION.reg = config_temp;
-
-	/* Calculate the baud rate. */
-	uart_set_baudrate(module, config->baud_rate);
-
-	module->hw->RX_INTERRUPT_MASK.reg = 0;	// disable int at initialization, enable it at read time
-	module->hw->TX_INTERRUPT_MASK.reg = 0;	// disable int at initialization, enable it at write time
-	
-	return STATUS_OK;
+    for(i = 0; i < index; i++)
+    {
+        gpio_pinmux_cofiguration(config->pin_number_pad[i], \
+                                (uint16_t)(config->pinmux_sel_pad[i]));
+    }
+
+    /* empty UART FIFO */
+    while (module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY)
+    {
+        i = module->hw->RECEIVE_DATA.reg;
+    }
+
+    /* reset configuration register */
+    module->hw->UART_CONFIGURATION.reg = 0;
+
+    /* program the uart configuration. */
+    if(config->flow_control)
+    {
+        config_temp |= UART_CONFIGURATION_CTS_ENABLE_1;
+    }
+    config_temp |= config->data_bits;
+    config_temp |= config->stop_bits;
+    switch(config->parity)
+    {
+        case UART_NO_PARITY:
+            config_temp |= UART_CONFIGURATION_PARITY_ENABLE_0;
+            break;
+
+        case UART_EVEN_PARITY:
+            config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+            config_temp |= UART_CONFIGURATION_PARITY_MODE_0;
+            break;
+
+        case UART_ODD_PARITY:
+            config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+            config_temp |= UART_CONFIGURATION_PARITY_MODE_1;
+            break;
+
+        case UART_SPACE_PARITY:
+            config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+            config_temp |= UART_CONFIGURATION_PARITY_MODE_2;
+            break;
+
+        case UART_MARK_PARITY:
+            config_temp |= UART_CONFIGURATION_PARITY_ENABLE_1;
+            config_temp |= UART_CONFIGURATION_PARITY_MODE_3;
+            break;
+
+        default:
+            break;
+    }
+    module->hw->UART_CONFIGURATION.reg = config_temp;
+
+    /* Calculate the baud rate. */
+    uart_set_baudrate(module, config->baud_rate);
+
+    module->hw->RX_INTERRUPT_MASK.reg = 0;  /* disable int at initialization, enable it at read time*/
+    module->hw->TX_INTERRUPT_MASK.reg = 0;  /* disable int at initialization, enable it at write time*/
+
+    return STATUS_OK;
 }
 
 /**
@@ -435,13 +466,13 @@ enum status_code uart_init(struct uart_module *const module, Uart * const hw,
 * \retval STATUS_OK         If the operation was completed
 */
 enum status_code uart_write_wait(struct uart_module *const module,
-		const uint8_t tx_data)
+        const uint8_t tx_data)
 {
-	while (!(module->hw->TRANSMIT_STATUS.reg & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL));
+    while (!(module->hw->TRANSMIT_STATUS.reg & UART_TRANSMIT_STATUS_TX_FIFO_NOT_FULL));
 
-	module->hw->TRANSMIT_DATA.reg = tx_data;
-	
-	return STATUS_OK;
+    module->hw->TRANSMIT_DATA.reg = tx_data;
+
+    return STATUS_OK;
 }
 
 /**
@@ -456,13 +487,13 @@ enum status_code uart_write_wait(struct uart_module *const module,
 * \retval STATUS_OK                If the operation was completed
 */
 enum status_code uart_read_wait(struct uart_module *const module,
-		uint8_t *const rx_data)
+        uint8_t *const rx_data)
 {
-	while (!(module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY));
+    while (!(module->hw->RECEIVE_STATUS.reg & UART_RECEIVE_STATUS_RX_FIFO_NOT_EMPTY));
+
+    *rx_data = module->hw->RECEIVE_DATA.reg;
 
-	*rx_data = module->hw->RECEIVE_DATA.reg;
-	
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -478,17 +509,17 @@ enum status_code uart_read_wait(struct uart_module *const module,
 * \param[in]  module  enumeration UART hw module
 * \param[in]  tx_data  Pointer to data to transmit
 * \param[in]  length   Number of characters to transmit
-* 
+*
 * \return Status of the operation.
 * \retval STATUS_OK              If operation was completed
 */
-enum status_code uart_write_buffer_wait(struct uart_module *const module, 
-		const uint8_t *tx_data, uint32_t length)
+enum status_code uart_write_buffer_wait(struct uart_module *const module,
+        const uint8_t *tx_data, uint32_t length)
 {
-	while(length--)
-		uart_write_wait(module, *tx_data++);
-	
-	return STATUS_OK;
+    while(length--)
+        uart_write_wait(module, *tx_data++);
+
+    return STATUS_OK;
 }
 
 /**
@@ -509,12 +540,12 @@ enum status_code uart_write_buffer_wait(struct uart_module *const module,
  * \retval STATUS_OK                If operation was completed
  */
 enum status_code uart_read_buffer_wait(struct uart_module *const module,
-		uint8_t *rx_data, uint16_t length)
+        uint8_t *rx_data, uint16_t length)
 {
-	while(length--)
-		uart_read_wait(module, rx_data++);
-	
-	return STATUS_OK;
+    while(length--)
+        uart_read_wait(module, rx_data++);
+
+    return STATUS_OK;
 }
 
 /**
@@ -527,19 +558,19 @@ enum status_code uart_read_buffer_wait(struct uart_module *const module,
  *
  */
 static void _uart_write_buffer(
-		struct uart_module *const module,
-		uint8_t *tx_data,
-		uint16_t length)
+        struct uart_module *const module,
+        uint8_t *tx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	/* Write parameters to the device instance */
-	module->remaining_tx_buffer_length = length;
-	module->tx_buffer_ptr = tx_data;
-	module->status = STATUS_BUSY;
+    /* Write parameters to the device instance */
+    module->remaining_tx_buffer_length = length;
+    module->tx_buffer_ptr = tx_data;
+    module->status = STATUS_BUSY;
 
-	module->hw->TX_INTERRUPT_MASK.reg = UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
+    module->hw->TX_INTERRUPT_MASK.reg = UART_TX_INTERRUPT_MASK_TX_FIFO_NOT_FULL_MASK;
 }
 
 /**
@@ -552,20 +583,20 @@ static void _uart_write_buffer(
  *
  */
 static void _uart_read_buffer(
-		struct uart_module *const module,
-		uint8_t *rx_data,
-		uint16_t length)
+        struct uart_module *const module,
+        uint8_t *rx_data,
+        uint16_t length)
 {
-	Assert(module);
-	Assert(rx_data);
+    Assert(module);
+    Assert(rx_data);
 
-	/* Set length for the buffer and the pointer, and let
-	 * the interrupt handler do the rest */
-	module->remaining_rx_buffer_length = length;
-	module->rx_buffer_ptr = rx_data;
-	module->status = STATUS_BUSY;
+    /* Set length for the buffer and the pointer, and let
+     * the interrupt handler do the rest */
+    module->remaining_rx_buffer_length = length;
+    module->rx_buffer_ptr = rx_data;
+    module->status = STATUS_BUSY;
 
-	module->hw->RX_INTERRUPT_MASK.reg = UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+    module->hw->RX_INTERRUPT_MASK.reg = UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
 }
 
 /**
@@ -585,24 +616,26 @@ static void _uart_read_buffer(
  * \retval STATUS_ERR_INVALID_ARG  If requested write length was zero
  */
 enum status_code uart_write_buffer_job(struct uart_module *const module,
-		uint8_t *tx_data, uint32_t length)
+        uint8_t *tx_data, uint32_t length)
 {
-	Assert(module);
-	Assert(tx_data);
+    Assert(module);
+    Assert(tx_data);
 
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
 
-	/* Check if the UART is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
+    /* Check if the UART is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
 
-	/* Issue internal write */
-	_uart_write_buffer(module, tx_data, length);
+    /* Issue internal write */
+    _uart_write_buffer(module, tx_data, length);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -627,24 +660,26 @@ enum status_code uart_write_buffer_job(struct uart_module *const module,
  * \retval  STATUS_ERR_INVALID_ARG  If requested read length was zero
  */
 enum status_code uart_read_buffer_job(struct uart_module *const module,
-		uint8_t *rx_data, uint16_t length)
+        uint8_t *rx_data, uint16_t length)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(rx_data);
-
-	if (length == 0) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Check if the UART is busy transmitting or slave waiting for TXC*/
-	if (module->status == STATUS_BUSY) {
-		return STATUS_BUSY;
-	}
-
-	/* Issue internal read */
-	_uart_read_buffer(module, rx_data, length);
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(rx_data);
+
+    if (length == 0)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Check if the UART is busy transmitting or slave waiting for TXC*/
+    if (module->status == STATUS_BUSY)
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Issue internal read */
+    _uart_read_buffer(module, rx_data, length);
+    return STATUS_OK;
 }
 
 /**
@@ -662,17 +697,17 @@ enum status_code uart_read_buffer_job(struct uart_module *const module,
  *
  */
 void uart_register_callback(struct uart_module *const module,
-		uart_callback_t callback_func,
-		enum uart_callback callback_type)
+        uart_callback_t callback_func,
+        enum uart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
-
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-	/* Set the bit corresponding to the callback_type */
-	module->callback_reg_mask |= (1 << callback_type);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
+
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
+    /* Set the bit corresponding to the callback_type */
+    module->callback_reg_mask |= (1 << callback_type);
 }
 
 /**
@@ -685,15 +720,15 @@ void uart_register_callback(struct uart_module *const module,
  *
  */
 void uart_unregister_callback(struct uart_module *module,
-		enum uart_callback callback_type)
+        enum uart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
-	/* Clear the bit corresponding to the callback_type */
-	module->callback_reg_mask &= ~(1 << callback_type);
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
+    /* Clear the bit corresponding to the callback_type */
+    module->callback_reg_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -707,17 +742,18 @@ void uart_unregister_callback(struct uart_module *module,
  * \param[in]  callback_type  Callback type given by an enum
  */
 void uart_enable_callback(struct uart_module *const module,
-		enum uart_callback callback_type)
+        enum uart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->callback_enable_mask |= (1 << callback_type);
+    /* Enable callback */
+    module->callback_enable_mask |= (1 << callback_type);
 
-	if (callback_type == UART_CTS_ACTIVE) {
-		module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
-	}
+    if (callback_type == UART_CTS_ACTIVE)
+    {
+        module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
+    }
 }
 
 /**
@@ -730,17 +766,18 @@ void uart_enable_callback(struct uart_module *const module,
  * \param[in]  callback_type  Callback type given by an enum
  */
 void uart_disable_callback(struct uart_module *const module,
-		enum uart_callback callback_type)
+        enum uart_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Disable callback */
-	module->callback_enable_mask &= ~(1 << callback_type);
+    /* Disable callback */
+    module->callback_enable_mask &= ~(1 << callback_type);
 
-	if (callback_type == UART_CTS_ACTIVE) {
-		module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
-	}
+    if (callback_type == UART_CTS_ACTIVE)
+    {
+        module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_CTS_ACTIVE_MASK;
+    }
 
 }
 
@@ -751,18 +788,20 @@ void uart_disable_callback(struct uart_module *const module,
  */
 void uart_enable_transmit_dma(struct uart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* DMA need the interrupt signal to trigger */
-	module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-
-	/* Disable NVIC to avoid trigger the CPU interrupt */
-	if (module->hw == UART0) {
-		NVIC_DisableIRQ(UART0_TX_IRQn);
-	} else if (module->hw == UART1) {
-		NVIC_DisableIRQ(UART1_TX_IRQn);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* DMA need the interrupt signal to trigger */
+    module->hw->TX_INTERRUPT_MASK.reg |= UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+    /* Disable NVIC to avoid trigger the CPU interrupt */
+    if (module->hw == UART0)
+    {
+        NVIC_DisableIRQ(UART0_TX_IRQn);
+    } else if (module->hw == UART1)
+    {
+        NVIC_DisableIRQ(UART1_TX_IRQn);
+    }
 }
 
 /**
@@ -772,17 +811,19 @@ void uart_enable_transmit_dma(struct uart_module *const module)
  */
 void uart_disable_transmit_dma(struct uart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
-
-	/* Enable NVIC to restore the callback functions */
-	if (module->hw == UART0) {
-		NVIC_EnableIRQ(UART0_TX_IRQn);
-	} else if (module->hw == UART1) {
-		NVIC_EnableIRQ(UART1_TX_IRQn);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    module->hw->TX_INTERRUPT_MASK.reg &= ~UART_TX_INTERRUPT_MASK_TX_FIFO_EMPTY_MASK;
+
+    /* Enable NVIC to restore the callback functions */
+    if (module->hw == UART0)
+    {
+        NVIC_EnableIRQ(UART0_TX_IRQn);
+    } else if (module->hw == UART1)
+    {
+        NVIC_EnableIRQ(UART1_TX_IRQn);
+    }
 }
 
 /**
@@ -792,18 +833,20 @@ void uart_disable_transmit_dma(struct uart_module *const module)
  */
 void uart_enable_receive_dma(struct uart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	/* DMA need the interrupt signal to trigger */
-	module->hw->RX_INTERRUPT_MASK.reg |= UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
-
-	/* Disable NVIC to avoid trigger the CPU interrupt */
-	if (module->hw == UART0) {
-		NVIC_DisableIRQ(UART0_TX_IRQn);
-	} else if (module->hw == UART1) {
-		NVIC_DisableIRQ(UART1_TX_IRQn);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    /* DMA need the interrupt signal to trigger */
+    module->hw->RX_INTERRUPT_MASK.reg |= UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+    /* Disable NVIC to avoid trigger the CPU interrupt */
+    if (module->hw == UART0)
+    {
+        NVIC_DisableIRQ(UART0_TX_IRQn);
+    } else if (module->hw == UART1)
+    {
+        NVIC_DisableIRQ(UART1_TX_IRQn);
+    }
 }
 
 /**
@@ -813,16 +856,18 @@ void uart_enable_receive_dma(struct uart_module *const module)
  */
 void uart_disable_receive_dma(struct uart_module *const module)
 {
-	/* Sanity check arguments */
-	Assert(module);
-
-	module->hw->RX_INTERRUPT_MASK.reg &= ~UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
-
-	/* Enable NVIC to restore the callback functions */
-	if (module->hw == UART0) {
-		NVIC_EnableIRQ(UART0_TX_IRQn);
-	} else if (module->hw == UART1) {
-		NVIC_EnableIRQ(UART1_TX_IRQn);
-	}
+    /* Sanity check arguments */
+    Assert(module);
+
+    module->hw->RX_INTERRUPT_MASK.reg &= ~UART_RX_INTERRUPT_MASK_RX_FIFO_NOT_EMPTY_MASK;
+
+    /* Enable NVIC to restore the callback functions */
+    if (module->hw == UART0)
+    {
+        NVIC_EnableIRQ(UART0_TX_IRQn);
+    } else if (module->hw == UART1)
+    {
+        NVIC_EnableIRQ(UART1_TX_IRQn);
+    }
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h
index 6f17ab4a1ba7..f2e81ff32a0e 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/uart/uart.h
@@ -117,10 +117,10 @@ extern "C" {
  * Number of bit per byte selection for UART communication.
  */
 enum uart_number_of_bit_selection{
-	/** 8 bit per byte*/
-	UART_8_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_0,
-	/** 7 bit per byte*/
-	UART_7_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_1,
+    /** 8 bit per byte*/
+    UART_8_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_0,
+    /** 7 bit per byte*/
+    UART_7_BITS = UART_CONFIGURATION_NUMBER_OF_BITS_1,
 };
 
 /** \brief UART stop bit selection
@@ -128,10 +128,10 @@ enum uart_number_of_bit_selection{
  * Number of stop bit selection for UART communication.
  */
 enum uart_stop_bit_selection{
-	/** 1 stop bit per byte*/
-	UART_1_STOP_BIT = UART_CONFIGURATION_STOP_BITS_0,
-	/** 2 stop bit per byte*/
-	UART_2_STOP_BITS = UART_CONFIGURATION_STOP_BITS_1,
+    /** 1 stop bit per byte*/
+    UART_1_STOP_BIT = UART_CONFIGURATION_STOP_BITS_0,
+    /** 2 stop bit per byte*/
+    UART_2_STOP_BITS = UART_CONFIGURATION_STOP_BITS_1,
 };
 
 
@@ -140,16 +140,16 @@ enum uart_stop_bit_selection{
  * Parity type selection for UART communication.
  */
 enum uart_parity_selection{
-	/** No parity bit */
-	UART_NO_PARITY = 0,
-	/** Even parity */
-	UART_EVEN_PARITY,
-	/** Odd parity */
-	UART_ODD_PARITY,
-	/** Space parity */
-	UART_SPACE_PARITY,
-	/** Mark parity */
-	UART_MARK_PARITY
+    /** No parity bit */
+    UART_NO_PARITY = 0,
+    /** Even parity */
+    UART_EVEN_PARITY,
+    /** Odd parity */
+    UART_ODD_PARITY,
+    /** Space parity */
+    UART_SPACE_PARITY,
+    /** Mark parity */
+    UART_MARK_PARITY
 };
 
 /**
@@ -172,16 +172,16 @@ typedef void (*uart_callback_t)(struct uart_module *const module);
  * Callbacks for the UART driver.
  */
 enum uart_callback {
-	/** Callback for TX FIFO not full. */
-	UART_TX_COMPLETE,
-	/** Callback for CTS active. */
-	UART_CTS_ACTIVE,
-	/** Callback for RX FIFO overrun. */
-	UART_RX_COMPLETE,
-	/** Callback for RX FIFO overrun. */
-	UART_RX_FIFO_OVERRUN,
-	/** Number of available callbacks. */
-	UART_CALLBACK_N,
+    /** Callback for TX FIFO not full. */
+    UART_TX_COMPLETE,
+    /** Callback for CTS active. */
+    UART_CTS_ACTIVE,
+    /** Callback for RX FIFO overrun. */
+    UART_RX_COMPLETE,
+    /** Callback for RX FIFO overrun. */
+    UART_RX_FIFO_OVERRUN,
+    /** Number of available callbacks. */
+    UART_CALLBACK_N,
 };
 
 
@@ -194,20 +194,20 @@ enum uart_callback {
  * \ref uart_get_config_defaults .
  */
 struct uart_config{
-	/** Baud rate */
-	uint32_t baud_rate;
-	/** Number of data bits */
-	enum uart_number_of_bit_selection data_bits;
-	/** Number of stop bits */
-	enum uart_stop_bit_selection stop_bits;
-	/** Parity type */
-	enum uart_parity_selection parity;
-	/** flow control type */
-	bool flow_control;
-	/** UART PAD pin number */
-	uint32_t pin_number_pad[4];
-	/** UART PAD pinmux selection */
-	uint32_t pinmux_sel_pad[4];
+    /** Baud rate */
+    uint32_t baud_rate;
+    /** Number of data bits */
+    enum uart_number_of_bit_selection data_bits;
+    /** Number of stop bits */
+    enum uart_stop_bit_selection stop_bits;
+    /** Parity type */
+    enum uart_parity_selection parity;
+    /** flow control type */
+    bool flow_control;
+    /** UART PAD pin number */
+    uint32_t pin_number_pad[4];
+    /** UART PAD pinmux selection */
+    uint32_t pinmux_sel_pad[4];
 };
 
 /**
@@ -220,25 +220,25 @@ struct uart_config{
  *       application; they are reserved for module-internal use only.
  */
 struct uart_module {
-	/** Pointer to the hardware instance. */
-	Uart *hw;
-	/** Array to store callback function pointers in. */
-	uart_callback_t callback[UART_CALLBACK_N];
-	/** Buffer pointer to where the next received character will be put */
-	volatile uint8_t *rx_buffer_ptr;
-	/** Buffer pointer to where the next character will be transmitted from
-	**/
-	volatile uint8_t *tx_buffer_ptr;
-	/** Remaining characters to receive */
-	volatile uint16_t remaining_rx_buffer_length;
-	/** Remaining characters to transmit */
-	volatile uint16_t remaining_tx_buffer_length;
-	/** Bit mask for callbacks registered. */
-	uint8_t callback_reg_mask;
-	/** Bit mask for callbacks enabled. */
-	uint8_t callback_enable_mask;
-	/** Holds the status of the ongoing or last operation */
-	volatile enum status_code status;
+    /** Pointer to the hardware instance. */
+    Uart *hw;
+    /** Array to store callback function pointers in. */
+    uart_callback_t callback[UART_CALLBACK_N];
+    /** Buffer pointer to where the next received character will be put */
+    volatile uint8_t *rx_buffer_ptr;
+    /** Buffer pointer to where the next character will be transmitted from
+    **/
+    volatile uint8_t *tx_buffer_ptr;
+    /** Remaining characters to receive */
+    volatile uint16_t remaining_rx_buffer_length;
+    /** Remaining characters to transmit */
+    volatile uint16_t remaining_tx_buffer_length;
+    /** Bit mask for callbacks registered. */
+    uint8_t callback_reg_mask;
+    /** Bit mask for callbacks enabled. */
+    uint8_t callback_enable_mask;
+    /** Holds the status of the ongoing or last operation */
+    volatile enum status_code status;
 };
 
 /** \name UART Configuration and initialization
@@ -246,38 +246,38 @@ struct uart_module {
  */
 void uart_get_config_defaults(struct uart_config *const config);
 enum status_code uart_init(struct uart_module *const module, Uart * const hw,
-		const struct uart_config *const config);
+        const struct uart_config *const config);
 /** @} */
 
 /** \name UART read and write functions
  * @{
  */
 enum status_code uart_write_wait(struct uart_module *const module,
-		const uint8_t tx_data);
+        const uint8_t tx_data);
 enum status_code uart_read_wait(struct uart_module *const module,
-		uint8_t *const rx_data);
+        uint8_t *const rx_data);
 enum status_code uart_write_buffer_wait(struct uart_module *const module,
-		const uint8_t *tx_data, uint32_t length);
+        const uint8_t *tx_data, uint32_t length);
 enum status_code uart_read_buffer_wait(struct uart_module *const module,
-		uint8_t *rx_data, uint16_t length);
+        uint8_t *rx_data, uint16_t length);
 enum status_code uart_write_buffer_job(struct uart_module *const module,
-		uint8_t *tx_data, uint32_t length);
+        uint8_t *tx_data, uint32_t length);
 enum status_code uart_read_buffer_job(struct uart_module *const module,
-		uint8_t *rx_data, uint16_t length);
+        uint8_t *rx_data, uint16_t length);
 /** @} */
 
 /** \name UART callback config
  * @{
  */
 void uart_register_callback(struct uart_module *const module,
-		uart_callback_t callback_func,
-		enum uart_callback callback_type);
+        uart_callback_t callback_func,
+        enum uart_callback callback_type);
 void uart_unregister_callback(struct uart_module *module,
-		enum uart_callback callback_type);
+        enum uart_callback callback_type);
 void uart_enable_callback(struct uart_module *const module,
-		enum uart_callback callback_type);
+        enum uart_callback callback_type);
 void uart_disable_callback(struct uart_module *const module,
-		enum uart_callback callback_type);
+        enum uart_callback callback_type);
 /** @}*/
 
 /** \name UART DAM enable/disable functions
@@ -304,14 +304,14 @@ void uart_disable_receive_dma(struct uart_module *const module);
  * intended meanings.
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>UART</td>
- *		<td>Universal Asynchronous Receiver/Transmitter</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>UART</td>
+ *      <td>Universal Asynchronous Receiver/Transmitter</td>
+ *  </tr>
  * </table>
  *
  *
@@ -330,12 +330,12 @@ void uart_disable_receive_dma(struct uart_module *const module);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -354,16 +354,16 @@ void uart_disable_receive_dma(struct uart_module *const module);
  * \page asfdoc_samb_uart_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c
index 7d3eaee1924d..be98dbe14662 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_device_udd.c
@@ -46,7 +46,7 @@
 #include <string.h>
 #include <stdlib.h>
 
-// Get USB device configuration
+/* Get USB device configuration*/
 #include "conf_usb.h"
 #include "udd.h"
 #include "usb.h"
@@ -59,7 +59,7 @@
  * USB low-level driver for USB device mode
  * @{
  */
-// Check USB device configuration
+/* Check USB device configuration*/
 #ifdef USB_DEVICE_HS_SUPPORT
 #  error The High speed mode is not supported on this part, please remove USB_DEVICE_HS_SUPPORT in conf_usb.h
 #endif
@@ -111,43 +111,47 @@ struct usb_module usb_device;
 static inline void udd_wait_clock_ready(void)
 {
 
-	if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DPLL) {
+    if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DPLL)
+    {
 #if (SAML21) || (SAML22) || (SAMR30)
-	#define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)
+    #define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK)
 
-		while((OSCCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
-	}
+        while((OSCCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
+    }
 #else
 #define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | \
-		SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)
+        SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)
 
-		while((SYSCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
-	}
+        while((SYSCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG);
+    }
 #endif
 
-	if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DFLL) {
+    if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DFLL)
+    {
 #if (SAML21) || (SAML22) || (SAMR30)
 #define DFLL_READY_FLAG (OSCCTRL_STATUS_DFLLRDY | \
-		OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC)
-
-		/* In USB recovery mode the status is not checked */
-		if (!(OSCCTRL->DFLLCTRL.reg & OSCCTRL_DFLLCTRL_USBCRM)) {
-			while((OSCCTRL->STATUS.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
-		} else {
-			while((OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY);
-		}
-	}
+        OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC)
+
+        /* In USB recovery mode the status is not checked */
+        if (!(OSCCTRL->DFLLCTRL.reg & OSCCTRL_DFLLCTRL_USBCRM))
+        {
+            while((OSCCTRL->STATUS.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
+        } else {
+            while((OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY);
+        }
+    }
 #else
 #define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | \
-		SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC)
-
-		/* In USB recovery mode the status is not checked */
-		if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) {
-			while((SYSCTRL->PCLKSR.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
-		} else {
-			while((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY);
-		}
-	}
+        SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC)
+
+        /* In USB recovery mode the status is not checked */
+        if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM))
+        {
+            while((SYSCTRL->PCLKSR.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG);
+        } else {
+            while((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY);
+        }
+    }
 #endif
 }
 /** @} */
@@ -162,10 +166,10 @@ static inline void udd_wait_clock_ready(void)
 #include "sleepmgr.h"
 /** States of USB interface */
 enum udd_usb_state_enum {
-	UDD_STATE_OFF,
-	UDD_STATE_SUSPEND,
-	UDD_STATE_SUSPEND_LPM,
-	UDD_STATE_IDLE,
+    UDD_STATE_OFF,
+    UDD_STATE_SUSPEND,
+    UDD_STATE_SUSPEND_LPM,
+    UDD_STATE_IDLE,
 };
 
 /** \brief Manages the sleep mode following the USB state
@@ -174,33 +178,36 @@ enum udd_usb_state_enum {
  */
 static void udd_sleep_mode(enum udd_usb_state_enum new_state)
 {
-	enum sleepmgr_mode sleep_mode[] = {
-		SLEEPMGR_ACTIVE,  /* UDD_STATE_OFF (not used) */
-	#if (SAML21) || (SAML22) || (SAMR30)
-		SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND */
-		SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND_LPM */
-		SLEEPMGR_IDLE,  /* UDD_STATE_IDLE */
-	#else
-		SLEEPMGR_IDLE_2,  /* UDD_STATE_SUSPEND */
-		SLEEPMGR_IDLE_1,  /* UDD_STATE_SUSPEND_LPM */
-		SLEEPMGR_IDLE_0,  /* UDD_STATE_IDLE */
-	#endif	
-	};
-
-	static enum udd_usb_state_enum udd_state = UDD_STATE_OFF;
-
-	if (udd_state == new_state) {
-		return; // No change
-	}
-	if (new_state != UDD_STATE_OFF) {
-		/* Lock new limit */
-		sleepmgr_lock_mode(sleep_mode[new_state]);
-	}
-	if (udd_state != UDD_STATE_OFF) {
-		/* Unlock old limit */
-		sleepmgr_unlock_mode(sleep_mode[udd_state]);
-	}
-	udd_state = new_state;
+    enum sleepmgr_mode sleep_mode[] = {
+        SLEEPMGR_ACTIVE,  /* UDD_STATE_OFF (not used) */
+    #if (SAML21) || (SAML22) || (SAMR30)
+        SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND */
+        SLEEPMGR_IDLE,  /* UDD_STATE_SUSPEND_LPM */
+        SLEEPMGR_IDLE,  /* UDD_STATE_IDLE */
+    #else
+        SLEEPMGR_IDLE_2,  /* UDD_STATE_SUSPEND */
+        SLEEPMGR_IDLE_1,  /* UDD_STATE_SUSPEND_LPM */
+        SLEEPMGR_IDLE_0,  /* UDD_STATE_IDLE */
+    #endif
+    };
+
+    static enum udd_usb_state_enum udd_state = UDD_STATE_OFF;
+
+    if (udd_state == new_state)
+    {
+        return; /* No change*/
+    }
+    if (new_state != UDD_STATE_OFF)
+    {
+        /* Lock new limit */
+        sleepmgr_lock_mode(sleep_mode[new_state]);
+    }
+    if (udd_state != UDD_STATE_OFF)
+    {
+        /* Unlock old limit */
+        sleepmgr_unlock_mode(sleep_mode[udd_state]);
+    }
+    udd_state = new_state;
 }
 
 #else
@@ -228,12 +235,12 @@ uint8_t udd_ctrl_buffer[USB_DEVICE_EP_CTRL_SIZE];
 
 /** Bit definitions about endpoint control state machine for udd_ep_control_state */
 typedef enum {
-	UDD_EPCTRL_SETUP                  = 0, //!< Wait a SETUP packet
-	UDD_EPCTRL_DATA_OUT               = 1, //!< Wait a OUT data packet
-	UDD_EPCTRL_DATA_IN                = 2, //!< Wait a IN data packet
-	UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP  = 3, //!< Wait a IN ZLP packet
-	UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet
-	UDD_EPCTRL_STALL_REQ              = 5, //!< STALL enabled on IN & OUT packet
+    UDD_EPCTRL_SETUP                  = 0, /*!< Wait a SETUP packet*/
+    UDD_EPCTRL_DATA_OUT               = 1, /*!< Wait a OUT data packet*/
+    UDD_EPCTRL_DATA_IN                = 2, /*!< Wait a IN data packet*/
+    UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP  = 3, /*!< Wait a IN ZLP packet*/
+    UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, /*!< Wait a OUT ZLP packet*/
+    UDD_EPCTRL_STALL_REQ              = 5, /*!< STALL enabled on IN & OUT packet*/
 } udd_ctrl_ep_state_t;
 
 /** Global variable to give and record information of the set up request management */
@@ -282,26 +289,26 @@ UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][64];
 
 /** Structure definition about job registered on an endpoint */
 typedef struct {
-	union {
-		//! Callback to call at the end of transfer
-		udd_callback_trans_t call_trans;
-		//! Callback to call when the endpoint halt is cleared
-		udd_callback_halt_cleared_t call_nohalt;
-	};
-	//! Buffer located in internal RAM to send or fill during job
-	uint8_t *buf;
-	//! Size of buffer to send or fill
-	iram_size_t buf_size;
-	//! Total number of data transferred on endpoint
-	iram_size_t nb_trans;
-	//! Endpoint size
-	uint16_t ep_size;
-	//! A job is registered on this endpoint
-	uint8_t busy:1;
-	//! A short packet is requested for this job on endpoint IN
-	uint8_t b_shortpacket:1;
-	//! The cache buffer is currently used on endpoint OUT
-	uint8_t b_use_out_cache_buffer:1;
+    union {
+        /*! Callback to call at the end of transfer*/
+        udd_callback_trans_t call_trans;
+        /*! Callback to call when the endpoint halt is cleared*/
+        udd_callback_halt_cleared_t call_nohalt;
+    };
+    /*! Buffer located in internal RAM to send or fill during job*/
+    uint8_t *buf;
+    /*! Size of buffer to send or fill*/
+    iram_size_t buf_size;
+    /*! Total number of data transferred on endpoint*/
+    iram_size_t nb_trans;
+    /*! Endpoint size*/
+    uint16_t ep_size;
+    /*! A job is registered on this endpoint*/
+    uint8_t busy:1;
+    /*! A short packet is requested for this job on endpoint IN*/
+    uint8_t b_shortpacket:1;
+    /*! The cache buffer is currently used on endpoint OUT*/
+    uint8_t b_use_out_cache_buffer:1;
 } udd_ep_job_t;
 
 /** Array to register a job on bulk/interrupt/isochronous endpoint */
@@ -316,11 +323,12 @@ static udd_ep_job_t udd_ep_job[2 * USB_DEVICE_MAX_EP];
  */
 static udd_ep_job_t* udd_ep_get_job(udd_ep_id_t ep)
 {
-	if ((ep == 0) || (ep == 0x80)) {
-		return NULL;
-	} else {
-		return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2];
-	}
+    if ((ep == 0) || (ep == 0x80))
+    {
+        return NULL;
+    } else {
+        return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2];
+    }
 }
 
 /**
@@ -329,48 +337,52 @@ static udd_ep_job_t* udd_ep_get_job(udd_ep_id_t ep)
  */
 static void udd_ep_trans_in_next(void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-	udd_ep_id_t ep = ep_callback_para->endpoint_address;
-	uint16_t ep_size, nb_trans;
-	uint16_t next_trans;
-	udd_ep_id_t ep_num;
-	udd_ep_job_t *ptr_job;
-
-	ptr_job = udd_ep_get_job(ep);
-	ep_num = ep & USB_EP_ADDR_MASK;
-
-	ep_size = ptr_job->ep_size;
-	/* Update number of data transferred */
-	nb_trans = ep_callback_para->sent_bytes;
-	ptr_job->nb_trans += nb_trans;
-
-	/* Need to send other data */
-	if (ptr_job->nb_trans != ptr_job->buf_size) {
-		next_trans = ptr_job->buf_size - ptr_job->nb_trans;
-		if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
-		/* The USB hardware support a maximum
-		 * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */
-			next_trans = UDD_ENDPOINT_MAX_TRANS -(UDD_ENDPOINT_MAX_TRANS % ep_size);
-		}
-		/* Need ZLP, if requested and last packet is not a short packet */
-		ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size));
-		usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
-		return;
-	}
-
-	/* Need to send a ZLP after all data transfer */
-	if (ptr_job->b_shortpacket) {
-		ptr_job->b_shortpacket = false;
-		/* Start new transfer */
-		usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],0);
-		return;
-	}
-
-	/* Job complete then call callback */
-	ptr_job->busy = false;
-	if (NULL != ptr_job->call_trans) {
-		ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+    udd_ep_id_t ep = ep_callback_para->endpoint_address;
+    uint16_t ep_size, nb_trans;
+    uint16_t next_trans;
+    udd_ep_id_t ep_num;
+    udd_ep_job_t *ptr_job;
+
+    ptr_job = udd_ep_get_job(ep);
+    ep_num = ep & USB_EP_ADDR_MASK;
+
+    ep_size = ptr_job->ep_size;
+    /* Update number of data transferred */
+    nb_trans = ep_callback_para->sent_bytes;
+    ptr_job->nb_trans += nb_trans;
+
+    /* Need to send other data */
+    if (ptr_job->nb_trans != ptr_job->buf_size)
+    {
+        next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+        if (UDD_ENDPOINT_MAX_TRANS < next_trans)
+        {
+        /* The USB hardware support a maximum
+         * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */
+            next_trans = UDD_ENDPOINT_MAX_TRANS -(UDD_ENDPOINT_MAX_TRANS % ep_size);
+        }
+        /* Need ZLP, if requested and last packet is not a short packet */
+        ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size));
+        usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+        return;
+    }
+
+    /* Need to send a ZLP after all data transfer */
+    if (ptr_job->b_shortpacket)
+    {
+        ptr_job->b_shortpacket = false;
+        /* Start new transfer */
+        usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],0);
+        return;
+    }
+
+    /* Job complete then call callback */
+    ptr_job->busy = false;
+    if (NULL != ptr_job->call_trans)
+    {
+        ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+    }
 }
 
 /**
@@ -379,58 +391,64 @@ static void udd_ep_trans_in_next(void* pointer)
  */
 static void udd_ep_trans_out_next(void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-	udd_ep_id_t ep = ep_callback_para->endpoint_address;
-	uint16_t ep_size, nb_trans;
-	uint16_t next_trans;
-	udd_ep_id_t ep_num;
-	udd_ep_job_t *ptr_job;
-
-	ptr_job = udd_ep_get_job(ep);
-	ep_num = ep & USB_EP_ADDR_MASK;
-
-	ep_size = ptr_job->ep_size;
-	/* Update number of data transferred */
-	nb_trans = ep_callback_para->received_bytes;
-
-	/* Can be necessary to copy data receive from cache buffer to user buffer */
-	if (ptr_job->b_use_out_cache_buffer) {
-		memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size);
-	}
-
-	/* Update number of data transferred */
-	ptr_job->nb_trans += nb_trans;
-	if (ptr_job->nb_trans > ptr_job->buf_size) {
-		ptr_job->nb_trans = ptr_job->buf_size;
-	}
-
-	/* If all previous data requested are received and user buffer not full
-	 * then need to receive other data */
-	if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size)) {
-		next_trans = ptr_job->buf_size - ptr_job->nb_trans;
-		if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
-		/* The USB hardware support a maximum transfer size
-		 * of UDD_ENDPOINT_MAX_TRANS Bytes */
-		next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
-		} else {
-			next_trans -= next_trans % ep_size;
-		}
-
-		if (next_trans < ep_size) {
-			/* Use the cache buffer for Bulk or Interrupt size endpoint */
-			ptr_job->b_use_out_cache_buffer = true;
-			usb_device_endpoint_read_buffer_job(&usb_device,ep_num,udd_ep_out_cache_buffer[ep_num - 1],ep_size);
-		} else {
-			usb_device_endpoint_read_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
-		}
-		return;
-	}
-
-	/* Job complete then call callback */
-	ptr_job->busy = false;
-	if (NULL != ptr_job->call_trans) {
-		ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+    udd_ep_id_t ep = ep_callback_para->endpoint_address;
+    uint16_t ep_size, nb_trans;
+    uint16_t next_trans;
+    udd_ep_id_t ep_num;
+    udd_ep_job_t *ptr_job;
+
+    ptr_job = udd_ep_get_job(ep);
+    ep_num = ep & USB_EP_ADDR_MASK;
+
+    ep_size = ptr_job->ep_size;
+    /* Update number of data transferred */
+    nb_trans = ep_callback_para->received_bytes;
+
+    /* Can be necessary to copy data receive from cache buffer to user buffer */
+    if (ptr_job->b_use_out_cache_buffer)
+    {
+        memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size);
+    }
+
+    /* Update number of data transferred */
+    ptr_job->nb_trans += nb_trans;
+    if (ptr_job->nb_trans > ptr_job->buf_size)
+    {
+        ptr_job->nb_trans = ptr_job->buf_size;
+    }
+
+    /* If all previous data requested are received and user buffer not full
+     * then need to receive other data */
+    if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size))
+    {
+        next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+        if (UDD_ENDPOINT_MAX_TRANS < next_trans)
+        {
+        /* The USB hardware support a maximum transfer size
+         * of UDD_ENDPOINT_MAX_TRANS Bytes */
+        next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size);
+        } else {
+            next_trans -= next_trans % ep_size;
+        }
+
+        if (next_trans < ep_size)
+        {
+            /* Use the cache buffer for Bulk or Interrupt size endpoint */
+            ptr_job->b_use_out_cache_buffer = true;
+            usb_device_endpoint_read_buffer_job(&usb_device,ep_num,udd_ep_out_cache_buffer[ep_num - 1],ep_size);
+        } else {
+            usb_device_endpoint_read_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans);
+        }
+        return;
+    }
+
+    /* Job complete then call callback */
+    ptr_job->busy = false;
+    if (NULL != ptr_job->call_trans)
+    {
+        ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep);
+    }
 }
 
 /**
@@ -440,187 +458,209 @@ static void udd_ep_trans_out_next(void* pointer)
  */
 static void udd_ep_transfer_process(struct usb_module *module_inst, void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-	udd_ep_id_t ep = ep_callback_para->endpoint_address;
-
-	if (ep & USB_EP_DIR_IN) {
-		udd_ep_trans_in_next(pointer);
-	} else {
-		udd_ep_trans_out_next(pointer);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+    udd_ep_id_t ep = ep_callback_para->endpoint_address;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        udd_ep_trans_in_next(pointer);
+    } else {
+        udd_ep_trans_out_next(pointer);
+    }
 }
 
 void udd_ep_abort(udd_ep_id_t ep)
 {
-	udd_ep_job_t *ptr_job;
-
-	usb_device_endpoint_abort_job(&usb_device, ep);
-
-	/* Job complete then call callback */
-	ptr_job = udd_ep_get_job(ep);
-	if (!ptr_job->busy) {
-		return;
-	}
-	ptr_job->busy = false;
-	if (NULL != ptr_job->call_trans) {
-		/* It can be a Transfer or stall callback */
-		ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep);
-	}
+    udd_ep_job_t *ptr_job;
+
+    usb_device_endpoint_abort_job(&usb_device, ep);
+
+    /* Job complete then call callback */
+    ptr_job = udd_ep_get_job(ep);
+    if (!ptr_job->busy)
+    {
+        return;
+    }
+    ptr_job->busy = false;
+    if (NULL != ptr_job->call_trans)
+    {
+        /* It can be a Transfer or stall callback */
+        ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep);
+    }
 }
 
 bool udd_is_high_speed(void)
 {
 #if SAMD21 || SAMR21 || SAMD11 || SAML21  || SAML22 || SAMDA1 || SAMR30
-	return false;
+    return false;
 #endif
 }
 
 uint16_t udd_get_frame_number(void)
 {
-	return usb_device_get_frame_number(&usb_device);
+    return usb_device_get_frame_number(&usb_device);
 }
 
 uint16_t udd_get_micro_frame_number(void)
 {
-	return usb_device_get_micro_frame_number(&usb_device);
+    return usb_device_get_micro_frame_number(&usb_device);
 }
 
 void udd_ep_free(udd_ep_id_t ep)
 {
-	struct usb_device_endpoint_config config_ep;
-	usb_device_endpoint_get_config_defaults(&config_ep);
+    struct usb_device_endpoint_config config_ep;
+    usb_device_endpoint_get_config_defaults(&config_ep);
 
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	udd_ep_abort(ep);
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    udd_ep_abort(ep);
 
-	config_ep.ep_address = ep;
-	config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE;
-	usb_device_endpoint_set_config(&usb_device, &config_ep);
-	usb_device_endpoint_unregister_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
-	usb_device_endpoint_disable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+    config_ep.ep_address = ep;
+    config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE;
+    usb_device_endpoint_set_config(&usb_device, &config_ep);
+    usb_device_endpoint_unregister_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+    usb_device_endpoint_disable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
 }
 
 bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize)
 {
-	struct usb_device_endpoint_config config_ep;
-	usb_device_endpoint_get_config_defaults(&config_ep);
-
-	config_ep.ep_address = ep;
-
-	if(MaxEndpointSize <= 8) {
-		config_ep.ep_size = USB_ENDPOINT_8_BYTE;
-	} else if(MaxEndpointSize <= 16) {
-		config_ep.ep_size = USB_ENDPOINT_16_BYTE;
-	} else if(MaxEndpointSize <= 32) {
-		config_ep.ep_size = USB_ENDPOINT_32_BYTE;
-	} else if(MaxEndpointSize <= 64) {
-		config_ep.ep_size = USB_ENDPOINT_64_BYTE;
-	} else if(MaxEndpointSize <= 128) {
-		config_ep.ep_size = USB_ENDPOINT_128_BYTE;
-	} else if(MaxEndpointSize <= 256) {
-		config_ep.ep_size = USB_ENDPOINT_256_BYTE;
-	} else if(MaxEndpointSize <= 512) {
-		config_ep.ep_size = USB_ENDPOINT_512_BYTE;
-	} else if(MaxEndpointSize <= 1023) {
-		config_ep.ep_size = USB_ENDPOINT_1023_BYTE;
-	} else {
-		return false;
-	}
-	udd_ep_job_t *ptr_job = udd_ep_get_job(ep);
-	ptr_job->ep_size = MaxEndpointSize;
-
-	bmAttributes = bmAttributes & USB_EP_TYPE_MASK;
-
-	/* Check endpoint type */
-	if(USB_EP_TYPE_ISOCHRONOUS == bmAttributes) {
-		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS;
-	} else if (USB_EP_TYPE_BULK == bmAttributes) {
-		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK;
-	} else if (USB_EP_TYPE_INTERRUPT == bmAttributes) {
-		config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT;
-	} else {
-		return false;
-	}
-
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep)) {
-		return false;
-	}
-	usb_device_endpoint_register_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,udd_ep_transfer_process);
-	usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
-	usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
-
-	return true;
+    struct usb_device_endpoint_config config_ep;
+    usb_device_endpoint_get_config_defaults(&config_ep);
+
+    config_ep.ep_address = ep;
+
+    if(MaxEndpointSize <= 8)
+    {
+        config_ep.ep_size = USB_ENDPOINT_8_BYTE;
+    } else if(MaxEndpointSize <= 16)
+    {
+        config_ep.ep_size = USB_ENDPOINT_16_BYTE;
+    } else if(MaxEndpointSize <= 32)
+    {
+        config_ep.ep_size = USB_ENDPOINT_32_BYTE;
+    } else if(MaxEndpointSize <= 64)
+    {
+        config_ep.ep_size = USB_ENDPOINT_64_BYTE;
+    } else if(MaxEndpointSize <= 128)
+    {
+        config_ep.ep_size = USB_ENDPOINT_128_BYTE;
+    } else if(MaxEndpointSize <= 256)
+    {
+        config_ep.ep_size = USB_ENDPOINT_256_BYTE;
+    } else if(MaxEndpointSize <= 512)
+    {
+        config_ep.ep_size = USB_ENDPOINT_512_BYTE;
+    } else if(MaxEndpointSize <= 1023)
+    {
+        config_ep.ep_size = USB_ENDPOINT_1023_BYTE;
+    } else {
+        return false;
+    }
+    udd_ep_job_t *ptr_job = udd_ep_get_job(ep);
+    ptr_job->ep_size = MaxEndpointSize;
+
+    bmAttributes = bmAttributes & USB_EP_TYPE_MASK;
+
+    /* Check endpoint type */
+    if(USB_EP_TYPE_ISOCHRONOUS == bmAttributes)
+    {
+        config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS;
+    } else if (USB_EP_TYPE_BULK == bmAttributes)
+    {
+        config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK;
+    } else if (USB_EP_TYPE_INTERRUPT == bmAttributes)
+    {
+        config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT;
+    } else {
+        return false;
+    }
+
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep))
+    {
+        return false;
+    }
+    usb_device_endpoint_register_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,udd_ep_transfer_process);
+    usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+    usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+
+    return true;
 }
 
 bool udd_ep_is_halted(udd_ep_id_t ep)
 {
-	return usb_device_endpoint_is_halted(&usb_device, ep);
+    return usb_device_endpoint_is_halted(&usb_device, ep);
 }
 
 bool udd_ep_set_halt(udd_ep_id_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
 
-	if (USB_DEVICE_MAX_EP < ep_num) {
-		return false;
-	}
+    if (USB_DEVICE_MAX_EP < ep_num)
+    {
+        return false;
+    }
 
-	usb_device_endpoint_set_halt(&usb_device, ep);
+    usb_device_endpoint_set_halt(&usb_device, ep);
 
-	udd_ep_abort(ep);
-	return true;
+    udd_ep_abort(ep);
+    return true;
 }
 
 bool udd_ep_clear_halt(udd_ep_id_t ep)
 {
-	udd_ep_job_t *ptr_job;
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    udd_ep_job_t *ptr_job;
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
 
-	if (USB_DEVICE_MAX_EP < ep_num) {
-		return false;
-	}
-	ptr_job = udd_ep_get_job(ep);
+    if (USB_DEVICE_MAX_EP < ep_num)
+    {
+        return false;
+    }
+    ptr_job = udd_ep_get_job(ep);
 
-	usb_device_endpoint_clear_halt(&usb_device, ep);
+    usb_device_endpoint_clear_halt(&usb_device, ep);
 
-	/* If a job is register on clear halt action then execute callback */
-	if (ptr_job->busy == true) {
-		ptr_job->busy = false;
-		ptr_job->call_nohalt();
-	}
+    /* If a job is register on clear halt action then execute callback */
+    if (ptr_job->busy == true)
+    {
+        ptr_job->busy = false;
+        ptr_job->call_nohalt();
+    }
 
-	return true;
+    return true;
 }
 
 bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback)
 {
-	udd_ep_id_t ep_num;
-	udd_ep_job_t *ptr_job;
-
-	ep_num = ep & USB_EP_ADDR_MASK;
-	if (USB_DEVICE_MAX_EP < ep_num) {
-		return false;
-	}
-
-	ptr_job = udd_ep_get_job(ep);
-	if (ptr_job->busy == true) {
-		return false; /* Job already on going */
-	}
-
-	/* Wait clear halt endpoint */
-	if (usb_device_endpoint_is_halted(&usb_device, ep)) {
-		/* Endpoint halted then registers the callback */
-		ptr_job->busy = true;
-		ptr_job->call_nohalt = callback;
-		return true;
-	} else if (usb_device_endpoint_is_configured(&usb_device, ep)) {
-		callback(); /* Endpoint not halted then call directly callback */
-		return true;
-	} else {
-		return false;
-	}
+    udd_ep_id_t ep_num;
+    udd_ep_job_t *ptr_job;
+
+    ep_num = ep & USB_EP_ADDR_MASK;
+    if (USB_DEVICE_MAX_EP < ep_num)
+    {
+        return false;
+    }
+
+    ptr_job = udd_ep_get_job(ep);
+    if (ptr_job->busy == true)
+    {
+        return false; /* Job already on going */
+    }
+
+    /* Wait clear halt endpoint */
+    if (usb_device_endpoint_is_halted(&usb_device, ep))
+    {
+        /* Endpoint halted then registers the callback */
+        ptr_job->busy = true;
+        ptr_job->call_nohalt = callback;
+        return true;
+    } else if (usb_device_endpoint_is_configured(&usb_device, ep))
+    {
+        callback(); /* Endpoint not halted then call directly callback */
+        return true;
+    } else {
+        return false;
+    }
 }
 
 /**
@@ -628,123 +668,135 @@ bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callbac
  */
 static void udd_ctrl_stall_data(void)
 {
-	udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+    udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
 
-	usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN);
-	usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT);
+    usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN);
+    usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT);
 }
 
 bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback)
 {
-	udd_ep_id_t ep_num;
-	udd_ep_job_t *ptr_job;
-	irqflags_t flags;
-
-	ep_num = ep & USB_EP_ADDR_MASK;
-
-	if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep))) {
-		return false;
-	}
-
-	ptr_job = udd_ep_get_job(ep);
-
-	flags = cpu_irq_save();
-	if (ptr_job->busy == true) {
-		cpu_irq_restore(flags);
-		return false; /* Job already on going */
-	}
-	ptr_job->busy = true;
-	cpu_irq_restore(flags);
-
-	/* No job running, set up a new one */
-	ptr_job->buf = buf;
-	ptr_job->buf_size = buf_size;
-	ptr_job->nb_trans = 0;
-	ptr_job->call_trans = callback;
-	ptr_job->b_shortpacket = b_shortpacket;
-	ptr_job->b_use_out_cache_buffer = false;
-
-	/* Initialize value to simulate a empty transfer */
-	uint16_t next_trans;
-
-	if (ep & USB_EP_DIR_IN) {
-		if (0 != ptr_job->buf_size) {
-			next_trans = ptr_job->buf_size;
-			if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
-				next_trans = UDD_ENDPOINT_MAX_TRANS -
-						(UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
-			}
-			ptr_job->b_shortpacket = ptr_job->b_shortpacket &&
-					(0 == (next_trans % ptr_job->ep_size));
-		} else if (true == ptr_job->b_shortpacket) {
-			ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */
-			next_trans = 0;
-		} else {
-			ptr_job->busy = false;
-			if (NULL != ptr_job->call_trans) {
-				ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
-			}
-			return true;
-		}
-		return (STATUS_OK ==
-				usb_device_endpoint_write_buffer_job(&usb_device,
-						ep_num,&ptr_job->buf[0],next_trans));
-	} else {
-		if (0 != ptr_job->buf_size) {
-			next_trans = ptr_job->buf_size;
-			if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
-				/* The USB hardware support a maximum transfer size
-				 * of UDD_ENDPOINT_MAX_TRANS Bytes */
-				next_trans = UDD_ENDPOINT_MAX_TRANS -
-						(UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
-			} else {
-				next_trans -= next_trans % ptr_job->ep_size;
-			}
-			if (next_trans < ptr_job->ep_size) {
-				ptr_job->b_use_out_cache_buffer = true;
-				return (STATUS_OK ==
-						usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
-								udd_ep_out_cache_buffer[ep_num - 1],
-								ptr_job->ep_size));
-			} else {
-				return (STATUS_OK ==
-						usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
-								&ptr_job->buf[0],next_trans));
-			}
-		} else {
-			ptr_job->busy = false;
-			if (NULL != ptr_job->call_trans) {
-				ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
-			}
-			return true;
-		}
-	}
+    udd_ep_id_t ep_num;
+    udd_ep_job_t *ptr_job;
+    irqflags_t flags;
+
+    ep_num = ep & USB_EP_ADDR_MASK;
+
+    if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep)))
+    {
+        return false;
+    }
+
+    ptr_job = udd_ep_get_job(ep);
+
+    flags = cpu_irq_save();
+    if (ptr_job->busy == true)
+    {
+        cpu_irq_restore(flags);
+        return false; /* Job already on going */
+    }
+    ptr_job->busy = true;
+    cpu_irq_restore(flags);
+
+    /* No job running, set up a new one */
+    ptr_job->buf = buf;
+    ptr_job->buf_size = buf_size;
+    ptr_job->nb_trans = 0;
+    ptr_job->call_trans = callback;
+    ptr_job->b_shortpacket = b_shortpacket;
+    ptr_job->b_use_out_cache_buffer = false;
+
+    /* Initialize value to simulate a empty transfer */
+    uint16_t next_trans;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        if (0 != ptr_job->buf_size)
+        {
+            next_trans = ptr_job->buf_size;
+            if (UDD_ENDPOINT_MAX_TRANS < next_trans)
+            {
+                next_trans = UDD_ENDPOINT_MAX_TRANS -
+                        (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+            }
+            ptr_job->b_shortpacket = ptr_job->b_shortpacket &&
+                    (0 == (next_trans % ptr_job->ep_size));
+        } else if (true == ptr_job->b_shortpacket)
+        {
+            ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */
+            next_trans = 0;
+        } else {
+            ptr_job->busy = false;
+            if (NULL != ptr_job->call_trans)
+            {
+                ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+            }
+            return true;
+        }
+        return (STATUS_OK ==
+                usb_device_endpoint_write_buffer_job(&usb_device,
+                        ep_num,&ptr_job->buf[0],next_trans));
+    } else {
+        if (0 != ptr_job->buf_size)
+        {
+            next_trans = ptr_job->buf_size;
+            if (UDD_ENDPOINT_MAX_TRANS < next_trans)
+            {
+                /* The USB hardware support a maximum transfer size
+                 * of UDD_ENDPOINT_MAX_TRANS Bytes */
+                next_trans = UDD_ENDPOINT_MAX_TRANS -
+                        (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size);
+            } else {
+                next_trans -= next_trans % ptr_job->ep_size;
+            }
+            if (next_trans < ptr_job->ep_size)
+            {
+                ptr_job->b_use_out_cache_buffer = true;
+                return (STATUS_OK ==
+                        usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+                                udd_ep_out_cache_buffer[ep_num - 1],
+                                ptr_job->ep_size));
+            } else {
+                return (STATUS_OK ==
+                        usb_device_endpoint_read_buffer_job(&usb_device, ep_num,
+                                &ptr_job->buf[0],next_trans));
+            }
+        } else {
+            ptr_job->busy = false;
+            if (NULL != ptr_job->call_trans)
+            {
+                ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep);
+            }
+            return true;
+        }
+    }
 }
 
 void udd_set_address(uint8_t address)
 {
-	usb_device_set_address(&usb_device,address);
+    usb_device_set_address(&usb_device,address);
 }
 
 uint8_t udd_getaddress(void)
 {
-	return usb_device_get_address(&usb_device);
+    return usb_device_get_address(&usb_device);
 }
 
 void udd_send_remotewakeup(void)
 {
-	uint32_t try = 5;
-	udd_wait_clock_ready();
-	udd_sleep_mode(UDD_STATE_IDLE);
-	while(2 != usb_get_state_machine_status(&usb_device) && try --) {
-		usb_device_send_remote_wake_up(&usb_device);
-	}
+    uint32_t try = 5;
+    udd_wait_clock_ready();
+    udd_sleep_mode(UDD_STATE_IDLE);
+    while(2 != usb_get_state_machine_status(&usb_device) && try --)
+    {
+        usb_device_send_remote_wake_up(&usb_device);
+    }
 }
 
 void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size )
 {
-	udd_g_ctrlreq.payload = payload;
-	udd_g_ctrlreq.payload_size = payload_size;
+    udd_g_ctrlreq.payload = payload;
+    udd_g_ctrlreq.payload_size = payload_size;
 }
 
 /**
@@ -752,11 +804,11 @@ void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size )
  */
 static void udd_ctrl_fetch_ram(void)
 {
-	udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0];
-	udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1];
-	udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2];
-	udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4];
-	udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6];
+    udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0];
+    udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1];
+    udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2];
+    udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4];
+    udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6];
 }
 
 /**
@@ -764,9 +816,9 @@ static void udd_ctrl_fetch_ram(void)
  */
 static void udd_ctrl_send_zlp_in(void)
 {
-	udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP;
-	usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
-	usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload,0);
+    udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP;
+    usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+    usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload,0);
 }
 
 /**
@@ -774,44 +826,48 @@ static void udd_ctrl_send_zlp_in(void)
  */
 static void udd_ctrl_in_sent(void)
 {
-	static bool b_shortpacket = false;
-	uint16_t nb_remain;
-
-	nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
-
-	if (0 == nb_remain) {
-		/* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */
-		udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
-		if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket) {
-			/* All data requested are transferred or a short packet has been sent, then it is the end of data phase.
-			 * Generate an OUT ZLP for handshake phase */
-			udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
-			usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
-			return;
-		}
-		/* Need of new buffer because the data phase is not complete */
-		if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run())) {
-			/* Under run then send zlp on IN
-			 * Here nb_remain=0, this allows to send a IN ZLP */
-		} else {
-			/* A new payload buffer is given */
-			udd_ctrl_payload_nb_trans = 0;
-			nb_remain = udd_g_ctrlreq.payload_size;
-		}
-	}
-
-	/* Continue transfer and send next data */
-	if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) {
-		nb_remain = USB_DEVICE_EP_CTRL_SIZE;
-		b_shortpacket = false;
-	} else {
-		b_shortpacket = true;
-	}
-
-	/* Link payload buffer directly on USB hardware */
-	usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans,nb_remain);
-
-	udd_ctrl_payload_nb_trans += nb_remain;
+    static bool b_shortpacket = false;
+    uint16_t nb_remain;
+
+    nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+
+    if (0 == nb_remain)
+    {
+        /* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */
+        udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+        if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket)
+        {
+            /* All data requested are transferred or a short packet has been sent, then it is the end of data phase.
+             * Generate an OUT ZLP for handshake phase */
+            udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+            usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer);
+            return;
+        }
+        /* Need of new buffer because the data phase is not complete */
+        if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run()))
+        {
+            /* Under run then send zlp on IN
+             * Here nb_remain=0, this allows to send a IN ZLP */
+        } else {
+            /* A new payload buffer is given */
+            udd_ctrl_payload_nb_trans = 0;
+            nb_remain = udd_g_ctrlreq.payload_size;
+        }
+    }
+
+    /* Continue transfer and send next data */
+    if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE)
+    {
+        nb_remain = USB_DEVICE_EP_CTRL_SIZE;
+        b_shortpacket = false;
+    } else {
+        b_shortpacket = true;
+    }
+
+    /* Link payload buffer directly on USB hardware */
+    usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans,nb_remain);
+
+    udd_ctrl_payload_nb_trans += nb_remain;
 }
 
 /**
@@ -820,68 +876,75 @@ static void udd_ctrl_in_sent(void)
  */
 static void udd_ctrl_out_received(void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-
-	uint16_t nb_data;
-	nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */
-
-	if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data)) {
-		/* Payload buffer too small */
-		nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
-	}
-
-	memcpy((uint8_t *) (udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data);
-	udd_ctrl_payload_nb_trans += nb_data;
-
-	if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || \
-	(udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans))) {
-		/* End of reception because it is a short packet
-		 * or all data are transferred */
-
-		/* Before send ZLP, call intermediate callback
-		 * in case of data receive generate a stall */
-		udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans;
-		if (NULL != udd_g_ctrlreq.over_under_run) {
-			if (!udd_g_ctrlreq.over_under_run()) {
-				/* Stall ZLP */
-				udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
-				/* Stall all packets on IN & OUT control endpoint */
-				udd_ep_set_halt(0);
-				/* Ack reception of OUT to replace NAK by a STALL */
-				return;
-			}
-		}
-		/* Send IN ZLP to ACK setup request */
-		udd_ctrl_send_zlp_in();
-		return;
-	}
-
-	if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans) {
-		/* Overrun then request a new payload buffer */
-		if (!udd_g_ctrlreq.over_under_run) {
-			/* No callback available to request a new payload buffer
-			 * Stall ZLP */
-			udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
-			/* Stall all packets on IN & OUT control endpoint */
-			udd_ep_set_halt(0);
-			return;
-		}
-		if (!udd_g_ctrlreq.over_under_run()) {
-			/* No new payload buffer delivered
-			 * Stall ZLP */
-			udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
-			/* Stall all packets on IN & OUT control endpoint */
-			udd_ep_set_halt(0);
-			return;
-		}
-		/* New payload buffer available
-		 * Update number of total data received */
-		udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
-
-		/* Reinitialize reception on payload buffer */
-		udd_ctrl_payload_nb_trans = 0;
-	}
-	usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+    uint16_t nb_data;
+    nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */
+
+    if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data))
+    {
+        /* Payload buffer too small */
+        nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans;
+    }
+
+    memcpy((uint8_t *) (udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data);
+    udd_ctrl_payload_nb_trans += nb_data;
+
+    if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || \
+    (udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans)))
+    {
+        /* End of reception because it is a short packet
+         * or all data are transferred */
+
+        /* Before send ZLP, call intermediate callback
+         * in case of data receive generate a stall */
+        udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans;
+        if (NULL != udd_g_ctrlreq.over_under_run)
+        {
+            if (!udd_g_ctrlreq.over_under_run())
+            {
+                /* Stall ZLP */
+                udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+                /* Stall all packets on IN & OUT control endpoint */
+                udd_ep_set_halt(0);
+                /* Ack reception of OUT to replace NAK by a STALL */
+                return;
+            }
+        }
+        /* Send IN ZLP to ACK setup request */
+        udd_ctrl_send_zlp_in();
+        return;
+    }
+
+    if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans)
+    {
+        /* Overrun then request a new payload buffer */
+        if (!udd_g_ctrlreq.over_under_run)
+        {
+            /* No callback available to request a new payload buffer
+             * Stall ZLP */
+            udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+            /* Stall all packets on IN & OUT control endpoint */
+            udd_ep_set_halt(0);
+            return;
+        }
+        if (!udd_g_ctrlreq.over_under_run())
+        {
+            /* No new payload buffer delivered
+             * Stall ZLP */
+            udd_ep_control_state = UDD_EPCTRL_STALL_REQ;
+            /* Stall all packets on IN & OUT control endpoint */
+            udd_ep_set_halt(0);
+            return;
+        }
+        /* New payload buffer available
+         * Update number of total data received */
+        udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans;
+
+        /* Reinitialize reception on payload buffer */
+        udd_ctrl_payload_nb_trans = 0;
+    }
+    usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
 }
 
 /**
@@ -892,41 +955,47 @@ static void udd_ctrl_out_received(void* pointer)
  */
 static void _usb_ep0_on_setup(struct usb_module *module_inst, void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-
-	if (UDD_EPCTRL_SETUP != udd_ep_control_state) {
-		if (NULL != udd_g_ctrlreq.callback) {
-			udd_g_ctrlreq.callback();
-		}
-		udd_ep_control_state = UDD_EPCTRL_SETUP;
-	}
-	if ( 8 != ep_callback_para->received_bytes) {
-		udd_ctrl_stall_data();
-		return;
-	} else {
-		udd_ctrl_fetch_ram();
-		if (false == udc_process_setup()) {
-			udd_ctrl_stall_data();
-			return;
-		} else if (Udd_setup_is_in()) {
-			udd_ctrl_prev_payload_nb_trans = 0;
-			udd_ctrl_payload_nb_trans = 0;
-			udd_ep_control_state = UDD_EPCTRL_DATA_IN;
-			usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
-			udd_ctrl_in_sent();
-		} else {
-			if(0 == udd_g_ctrlreq.req.wLength) {
-				udd_ctrl_send_zlp_in();
-				return;
-			} else {
-				udd_ctrl_prev_payload_nb_trans = 0;
-				udd_ctrl_payload_nb_trans = 0;
-				udd_ep_control_state = UDD_EPCTRL_DATA_OUT;
-				/* Initialize buffer size and enable OUT bank */
-				usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
-			}
-		}
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+    if (UDD_EPCTRL_SETUP != udd_ep_control_state)
+    {
+        if (NULL != udd_g_ctrlreq.callback)
+        {
+            udd_g_ctrlreq.callback();
+        }
+        udd_ep_control_state = UDD_EPCTRL_SETUP;
+    }
+    if ( 8 != ep_callback_para->received_bytes)
+    {
+        udd_ctrl_stall_data();
+        return;
+    } else {
+        udd_ctrl_fetch_ram();
+        if (false == udc_process_setup())
+        {
+            udd_ctrl_stall_data();
+            return;
+        } else if (Udd_setup_is_in())
+        {
+            udd_ctrl_prev_payload_nb_trans = 0;
+            udd_ctrl_payload_nb_trans = 0;
+            udd_ep_control_state = UDD_EPCTRL_DATA_IN;
+            usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+            udd_ctrl_in_sent();
+        } else {
+            if(0 == udd_g_ctrlreq.req.wLength)
+            {
+                udd_ctrl_send_zlp_in();
+                return;
+            } else {
+                udd_ctrl_prev_payload_nb_trans = 0;
+                udd_ctrl_payload_nb_trans = 0;
+                udd_ep_control_state = UDD_EPCTRL_DATA_OUT;
+                /* Initialize buffer size and enable OUT bank */
+                usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE);
+            }
+        }
+    }
 }
 
 /**
@@ -935,17 +1004,19 @@ static void _usb_ep0_on_setup(struct usb_module *module_inst, void* pointer)
  */
 static void udd_ctrl_underflow(void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-
-	if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) {
-		/* Host want to stop OUT transaction
-		 * then stop to wait OUT data phase and wait IN ZLP handshake */
-		udd_ctrl_send_zlp_in();
-	} else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) {
-		/* A OUT handshake is waiting by device,
-		 * but host want extra IN data then stall extra IN data */
-		usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+    if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state)
+    {
+        /* Host want to stop OUT transaction
+         * then stop to wait OUT data phase and wait IN ZLP handshake */
+        udd_ctrl_send_zlp_in();
+    } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state)
+    {
+        /* A OUT handshake is waiting by device,
+         * but host want extra IN data then stall extra IN data */
+        usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+    }
 }
 
 /**
@@ -954,17 +1025,19 @@ static void udd_ctrl_underflow(void* pointer)
  */
 static void udd_ctrl_overflow(void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-
-	if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) {
-		/* Host want to stop IN transaction
-		 * then stop to wait IN data phase and wait OUT ZLP handshake */
-		udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
-	} else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) {
-		/* A IN handshake is waiting by device,
-		 * but host want extra OUT data then stall extra OUT data and following status stage */
-		usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+    if (UDD_EPCTRL_DATA_IN == udd_ep_control_state)
+    {
+        /* Host want to stop IN transaction
+         * then stop to wait IN data phase and wait OUT ZLP handshake */
+        udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP;
+    } else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state)
+    {
+        /* A IN handshake is waiting by device,
+         * but host want extra OUT data then stall extra OUT data and following status stage */
+        usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address);
+    }
 }
 
 /**
@@ -975,13 +1048,14 @@ static void udd_ctrl_overflow(void* pointer)
  */
 static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void* pointer)
 {
-	struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
-
-	if(ep_callback_para->endpoint_address & USB_EP_DIR_IN) {
-		udd_ctrl_underflow(pointer);
-	} else {
-		udd_ctrl_overflow(pointer);
-	}
+    struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer;
+
+    if(ep_callback_para->endpoint_address & USB_EP_DIR_IN)
+    {
+        udd_ctrl_underflow(pointer);
+    } else {
+        udd_ctrl_overflow(pointer);
+    }
 }
 
 /**
@@ -992,16 +1066,19 @@ static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void* point
  */
 static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void * pointer)
 {
-		if (UDD_EPCTRL_DATA_OUT  == udd_ep_control_state) { /* handshake Out for status stage */
-			udd_ctrl_out_received(pointer);
-		} else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { /* handshake In for status stage */
-			udd_ctrl_in_sent();
-		} else {
-			if (NULL != udd_g_ctrlreq.callback) {
-				udd_g_ctrlreq.callback();
-			}
-			udd_ep_control_state = UDD_EPCTRL_SETUP;
-		}
+        if (UDD_EPCTRL_DATA_OUT  == udd_ep_control_state)
+        { /* handshake Out for status stage */
+            udd_ctrl_out_received(pointer);
+        } else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state)
+        { /* handshake In for status stage */
+            udd_ctrl_in_sent();
+        } else {
+            if (NULL != udd_g_ctrlreq.callback)
+            {
+                udd_g_ctrlreq.callback();
+            }
+            udd_ep_control_state = UDD_EPCTRL_SETUP;
+        }
 }
 
 /**
@@ -1010,28 +1087,28 @@ static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void * pointe
  */
 static void udd_ctrl_ep_enable(struct usb_module *module_inst)
 {
-	/* USB Device Endpoint0 Configuration */
-	 struct usb_device_endpoint_config config_ep0;
+    /* USB Device Endpoint0 Configuration */
+     struct usb_device_endpoint_config config_ep0;
 
-	 usb_device_endpoint_get_config_defaults(&config_ep0);
-	 config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3);
-	 usb_device_endpoint_set_config(module_inst,&config_ep0);
+     usb_device_endpoint_get_config_defaults(&config_ep0);
+     config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3);
+     usb_device_endpoint_set_config(module_inst,&config_ep0);
 
-	 usb_device_endpoint_setup_buffer_job(module_inst,udd_ctrl_buffer);
+     usb_device_endpoint_setup_buffer_job(module_inst,udd_ctrl_buffer);
 
-	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup );
-	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,_usb_ep0_on_tansfer_ok );
-	 usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,_usb_ep0_on_tansfer_fail );
-	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP);
-	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
-	 usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
+     usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup );
+     usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,_usb_ep0_on_tansfer_ok );
+     usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,_usb_ep0_on_tansfer_fail );
+     usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP);
+     usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT);
+     usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL);
 
 #ifdef  USB_DEVICE_LPM_SUPPORT
-	 // Enable LPM feature
-	 usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK);
+     /* Enable LPM feature*/
+     usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK);
 #endif
 
-	 udd_ep_control_state = UDD_EPCTRL_SETUP;
+     udd_ep_control_state = UDD_EPCTRL_SETUP;
 }
 
 /**
@@ -1042,35 +1119,37 @@ static void udd_ctrl_ep_enable(struct usb_module *module_inst)
  */
 static void _usb_on_suspend(struct usb_module *module_inst, void *pointer)
 {
-	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
-	udd_sleep_mode(UDD_STATE_SUSPEND);
+    usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+    udd_sleep_mode(UDD_STATE_SUSPEND);
 #ifdef UDC_SUSPEND_EVENT
-	UDC_SUSPEND_EVENT();
+    UDC_SUSPEND_EVENT();
 #endif
 }
 
 #ifdef  USB_DEVICE_LPM_SUPPORT
 static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointer)
 {
-	dbg_print("LPM_SUSP\n");
-
-	uint32_t *lpm_wakeup_enable;
-	lpm_wakeup_enable = (uint32_t *)pointer;
-
-	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
-	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
-
-//#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.HIRD
-	udd_sleep_mode(UDD_STATE_SUSPEND_LPM);  // Enter in LPM SUSPEND mode
-	if ((*lpm_wakeup_enable)) {
-		UDC_REMOTEWAKEUP_LPM_ENABLE();
-	}
-	if (!(*lpm_wakeup_enable)) {
-		UDC_REMOTEWAKEUP_LPM_DISABLE();
-	}
-	UDC_SUSPEND_LPM_EVENT();
+    dbg_print("LPM_SUSP\n");
+
+    uint32_t *lpm_wakeup_enable;
+    lpm_wakeup_enable = (uint32_t *)pointer;
+
+    usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+    usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+
+/*#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.HIRD*/
+    udd_sleep_mode(UDD_STATE_SUSPEND_LPM);  /* Enter in LPM SUSPEND mode*/
+    if ((*lpm_wakeup_enable))
+    {
+        UDC_REMOTEWAKEUP_LPM_ENABLE();
+    }
+    if (!(*lpm_wakeup_enable))
+    {
+        UDC_REMOTEWAKEUP_LPM_DISABLE();
+    }
+    UDC_SUSPEND_LPM_EVENT();
 }
 #endif
 
@@ -1082,9 +1161,9 @@ static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointe
  */
 static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer)
 {
-	udc_sof_notify();
+    udc_sof_notify();
 #ifdef UDC_SOF_EVENT
-	UDC_SOF_EVENT();
+    UDC_SOF_EVENT();
 #endif
 }
 
@@ -1096,10 +1175,10 @@ static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer)
  */
 static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer)
 {
-	// Reset USB Device Stack Core
-	udc_reset();
-	usb_device_set_address(module_inst,0);
-	udd_ctrl_ep_enable(module_inst);
+    /* Reset USB Device Stack Core*/
+    udc_reset();
+    usb_device_set_address(module_inst,0);
+    udd_ctrl_ep_enable(module_inst);
 }
 
 /**
@@ -1110,43 +1189,43 @@ static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer)
  */
 static void _usb_on_wakeup(struct usb_module *module_inst, void *pointer)
 {
-	udd_wait_clock_ready();
+    udd_wait_clock_ready();
 
-	usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+    usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
 #ifdef  USB_DEVICE_LPM_SUPPORT
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
 #endif
-	udd_sleep_mode(UDD_STATE_IDLE);
+    udd_sleep_mode(UDD_STATE_IDLE);
 #ifdef UDC_RESUME_EVENT
-	UDC_RESUME_EVENT();
+    UDC_RESUME_EVENT();
 #endif
 }
 
 void udd_detach(void)
 {
-	usb_device_detach(&usb_device);
-	udd_sleep_mode(UDD_STATE_SUSPEND);
+    usb_device_detach(&usb_device);
+    udd_sleep_mode(UDD_STATE_SUSPEND);
 }
 
 void udd_attach(void)
 {
-	udd_sleep_mode(UDD_STATE_IDLE);
-	usb_device_attach(&usb_device);
-
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend);
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify);
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset);
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup);
-
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
+    udd_sleep_mode(UDD_STATE_IDLE);
+    usb_device_attach(&usb_device);
+
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend);
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify);
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset);
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup);
+
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP);
 #ifdef  USB_DEVICE_LPM_SUPPORT
-	usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
-	usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
+    usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend);
+    usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP);
 #endif
 }
 
@@ -1166,20 +1245,21 @@ void udd_attach(void)
  */
 static void _uhd_vbus_handler(void)
 {
-	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 # ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
-	if (is_usb_vbus_high()) {
-		udd_attach();
-	} else {
-		udd_detach();
-	}
+    if (is_usb_vbus_high())
+    {
+        udd_attach();
+    } else {
+        udd_detach();
+    }
 # endif
 # ifdef UDC_VBUS_EVENT
-	UDC_VBUS_EVENT(is_usb_vbus_high());
+    UDC_VBUS_EVENT(is_usb_vbus_high());
 # endif
-	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 
 /**
@@ -1189,24 +1269,24 @@ static void _uhd_vbus_handler(void)
 static void _usb_vbus_config(void)
 {
 
-	/* Initialize EIC for vbus checking */
-	struct extint_chan_conf eint_chan_conf;
-	extint_chan_get_config_defaults(&eint_chan_conf);
-
-	eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
-	eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
-	eint_chan_conf.gpio_pin_pull      = EXTINT_PULL_NONE;
-	eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
-	eint_chan_conf.filter_input_signal = true;
-
-	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
-	extint_register_callback(_uhd_vbus_handler,
-			USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    /* Initialize EIC for vbus checking */
+    struct extint_chan_conf eint_chan_conf;
+    extint_chan_get_config_defaults(&eint_chan_conf);
+
+    eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
+    eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
+    eint_chan_conf.gpio_pin_pull      = EXTINT_PULL_NONE;
+    eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+    eint_chan_conf.filter_input_signal = true;
+
+    extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
+    extint_register_callback(_uhd_vbus_handler,
+            USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 /** @} */
 #endif
@@ -1214,67 +1294,69 @@ static void _usb_vbus_config(void)
 bool udd_include_vbus_monitoring(void)
 {
 #if USB_VBUS_EIC
-	return true;
+    return true;
 #else
-	return false;
+    return false;
 #endif
 }
 
 void udd_enable(void)
 {
-	irqflags_t flags;
+    irqflags_t flags;
 
-	/* To avoid USB interrupt before end of initialization */
-	flags = cpu_irq_save();
+    /* To avoid USB interrupt before end of initialization */
+    flags = cpu_irq_save();
 
 #if USB_ID_EIC
-	if (usb_dual_enable()) {
-		/* The current mode has been started by otg_dual_enable() */
-		cpu_irq_restore(flags);
-		return;
-	}
+    if (usb_dual_enable())
+    {
+        /* The current mode has been started by otg_dual_enable() */
+        cpu_irq_restore(flags);
+        return;
+    }
 #endif
-	struct usb_config config_usb;
+    struct usb_config config_usb;
 
-	/* USB Module configuration */
-	usb_get_config_defaults(&config_usb);
-	config_usb.source_generator = UDD_CLOCK_GEN;
-	usb_init(&usb_device, USB, &config_usb);
+    /* USB Module configuration */
+    usb_get_config_defaults(&config_usb);
+    config_usb.source_generator = UDD_CLOCK_GEN;
+    usb_init(&usb_device, USB, &config_usb);
 
-	/* USB Module Enable */
-	usb_enable(&usb_device);
+    /* USB Module Enable */
+    usb_enable(&usb_device);
 
-	/* Check clock after enable module, request the clock */
-	udd_wait_clock_ready();
+    /* Check clock after enable module, request the clock */
+    udd_wait_clock_ready();
 
-	udd_sleep_mode(UDD_STATE_SUSPEND);
+    udd_sleep_mode(UDD_STATE_SUSPEND);
 
 #if USB_VBUS_EIC
-	_usb_vbus_config();
-	if (is_usb_vbus_high()) {
-		/* USB Attach */
-		_uhd_vbus_handler();
-	}
+    _usb_vbus_config();
+    if (is_usb_vbus_high())
+    {
+        /* USB Attach */
+        _uhd_vbus_handler();
+    }
 #else
-	// No VBus detect, assume always high
+    /* No VBus detect, assume always high*/
 # ifndef USB_DEVICE_ATTACH_AUTO_DISABLE
-	udd_attach();
+    udd_attach();
 # endif
 #endif
 
-	cpu_irq_restore(flags);
+    cpu_irq_restore(flags);
 }
 
 void udd_disable(void)
 {
-	irqflags_t flags;
+    irqflags_t flags;
 
-	udd_detach();
+    udd_detach();
 
-	udd_sleep_mode(UDD_STATE_OFF);
+    udd_sleep_mode(UDD_STATE_OFF);
 
-	flags = cpu_irq_save();
-	usb_dual_disable();
-	cpu_irq_restore(flags);
+    flags = cpu_irq_save();
+    usb_dual_disable();
+    cpu_irq_restore(flags);
 }
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c
index 4b9adee94adc..67be6ee01feb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.c
@@ -79,22 +79,22 @@ static void usb_id_handler(void);
  */
 static void usb_id_config(void)
 {
-	struct extint_chan_conf eint_chan_conf;
-	extint_chan_get_config_defaults(&eint_chan_conf);
-
-	eint_chan_conf.gpio_pin           = USB_ID_PIN;
-	eint_chan_conf.gpio_pin_mux       = USB_ID_EIC_MUX;
-	eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
-	eint_chan_conf.filter_input_signal = true;
-
-	extint_chan_disable_callback(USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
-	extint_register_callback(usb_id_handler,
-			USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_enable_callback(USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    struct extint_chan_conf eint_chan_conf;
+    extint_chan_get_config_defaults(&eint_chan_conf);
+
+    eint_chan_conf.gpio_pin           = USB_ID_PIN;
+    eint_chan_conf.gpio_pin_mux       = USB_ID_EIC_MUX;
+    eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
+    eint_chan_conf.filter_input_signal = true;
+
+    extint_chan_disable_callback(USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
+    extint_register_callback(usb_id_handler,
+            USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_enable_callback(USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 
 /**
@@ -102,19 +102,20 @@ static void usb_id_config(void)
  */
 static void usb_id_handler(void)
 {
-	extint_chan_disable_callback(USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	if (_usb_is_id_device()) {
-		uhc_stop(false);
-		UHC_MODE_CHANGE(false);
-		udc_start();
-	} else {
-		udc_stop();
-		UHC_MODE_CHANGE(true);
-		uhc_start();
-	}
-	extint_chan_enable_callback(USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_disable_callback(USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    if (_usb_is_id_device())
+    {
+        uhc_stop(false);
+        UHC_MODE_CHANGE(false);
+        udc_start();
+    } else {
+        udc_stop();
+        UHC_MODE_CHANGE(true);
+        uhc_start();
+    }
+    extint_chan_enable_callback(USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 #endif
 /** @} */
@@ -126,37 +127,39 @@ static void usb_id_handler(void)
  */
 bool usb_dual_enable(void)
 {
-	if (_initialized) {
-		return false; // Dual role already initialized
-	}
+    if (_initialized)
+    {
+        return false; /* Dual role already initialized*/
+    }
 
 #if USB_ID_EIC
-	_initialized = true;
-
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
-
-	/* Set USB ID Pin as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-	port_pin_set_config(USB_ID_PIN, &pin_conf);
-
-	usb_id_config();
-	if (_usb_is_id_device()) {
-		UHC_MODE_CHANGE(false);
-		udc_start();
-	} else {
-		UHC_MODE_CHANGE(true);
-		uhc_start();
-	}
-
-	/**
-	 * End of host or device startup,
-	 * the current mode selected is already started now
-	 */
-	return true; // ID pin management has been enabled
+    _initialized = true;
+
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
+
+    /* Set USB ID Pin as inputs */
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    pin_conf.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(USB_ID_PIN, &pin_conf);
+
+    usb_id_config();
+    if (_usb_is_id_device())
+    {
+        UHC_MODE_CHANGE(false);
+        udc_start();
+    } else {
+        UHC_MODE_CHANGE(true);
+        uhc_start();
+    }
+
+    /**
+     * End of host or device startup,
+     * the current mode selected is already started now
+     */
+    return true; /* ID pin management has been enabled*/
 #else
-	return false; // ID pin management has not been enabled
+    return false; /* ID pin management has not been enabled*/
 #endif
 }
 
@@ -165,14 +168,15 @@ bool usb_dual_enable(void)
  */
 void usb_dual_disable(void)
 {
-	if (!_initialized) {
-		return; // Dual role not initialized
-	}
-	_initialized = false;
+    if (!_initialized)
+    {
+        return; /* Dual role not initialized*/
+    }
+    _initialized = false;
 
 #if USB_ID_EIC
-	extint_chan_disable_callback(USB_ID_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_disable_callback(USB_ID_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 #endif
 }
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h
index 60125d3d6f40..40f301047b19 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_dual.h
@@ -108,4 +108,4 @@ void usb_dual_disable(void);
 }
 #endif
 
-#endif // _USB_DUAL_H_
+#endif /* _USB_DUAL_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c
index 46f57c9096f5..6505ba0a66a5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/stack_interface/usb_host_uhd.c
@@ -131,32 +131,32 @@ static uhd_callback_reset_t uhd_reset_callback = NULL;
 #include "sleepmgr.h"
 /** States of USB interface */
 enum uhd_usb_state_enum {
-	UHD_STATE_OFF = 0,
-	UHD_STATE_WAIT_ID_HOST = 1,
-	UHD_STATE_NO_VBUS = 2,
-	UHD_STATE_DISCONNECT = 3,
-	UHD_STATE_SUSPEND = 4,
-	UHD_STATE_SUSPEND_LPM = 5,
-	UHD_STATE_IDLE = 6,
+    UHD_STATE_OFF = 0,
+    UHD_STATE_WAIT_ID_HOST = 1,
+    UHD_STATE_NO_VBUS = 2,
+    UHD_STATE_DISCONNECT = 3,
+    UHD_STATE_SUSPEND = 4,
+    UHD_STATE_SUSPEND_LPM = 5,
+    UHD_STATE_IDLE = 6,
 };
 
 enum sleepmgr_mode sleep_mode[] = {
-	SLEEPMGR_STANDBY,  // UHD_STATE_OFF (not used)
+    SLEEPMGR_STANDBY,  /* UHD_STATE_OFF (not used)*/
 #if SAML21 || SAMR30
-	SLEEPMGR_IDLE,   // UHD_STATE_WAIT_ID_HOST
-	SLEEPMGR_IDLE,   // UHD_STATE_NO_VBUS
-	SLEEPMGR_IDLE,   // UHD_STATE_DISCONNECT
-	SLEEPMGR_IDLE,   // UHD_STATE_SUSPEND
-	SLEEPMGR_IDLE,   // UHD_STATE_SUSPEND_LPM
-	SLEEPMGR_IDLE,   // UHD_STATE_IDLE
+    SLEEPMGR_IDLE,   /* UHD_STATE_WAIT_ID_HOST*/
+    SLEEPMGR_IDLE,   /* UHD_STATE_NO_VBUS*/
+    SLEEPMGR_IDLE,   /* UHD_STATE_DISCONNECT*/
+    SLEEPMGR_IDLE,   /* UHD_STATE_SUSPEND*/
+    SLEEPMGR_IDLE,   /* UHD_STATE_SUSPEND_LPM*/
+    SLEEPMGR_IDLE,   /* UHD_STATE_IDLE*/
 #else
-	SLEEPMGR_IDLE_0,   // UHD_STATE_WAIT_ID_HOST
-	SLEEPMGR_IDLE_0,   // UHD_STATE_NO_VBUS
-	SLEEPMGR_IDLE_0,   // UHD_STATE_DISCONNECT
-	SLEEPMGR_IDLE_2,   // UHD_STATE_SUSPEND
-	SLEEPMGR_IDLE_2,   // UHD_STATE_SUSPEND_LPM
-	SLEEPMGR_IDLE_0,   // UHD_STATE_IDLE
-#endif	
+    SLEEPMGR_IDLE_0,   /* UHD_STATE_WAIT_ID_HOST*/
+    SLEEPMGR_IDLE_0,   /* UHD_STATE_NO_VBUS*/
+    SLEEPMGR_IDLE_0,   /* UHD_STATE_DISCONNECT*/
+    SLEEPMGR_IDLE_2,   /* UHD_STATE_SUSPEND*/
+    SLEEPMGR_IDLE_2,   /* UHD_STATE_SUSPEND_LPM*/
+    SLEEPMGR_IDLE_0,   /* UHD_STATE_IDLE*/
+#endif
 };
 
 static enum uhd_usb_state_enum uhd_state = UHD_STATE_OFF;
@@ -167,18 +167,21 @@ static enum uhd_usb_state_enum uhd_state = UHD_STATE_OFF;
  */
 static void uhd_sleep_mode(enum uhd_usb_state_enum new_state)
 {
-	if (uhd_state == new_state) {
-		return; // No change
-	}
-	if (new_state != UHD_STATE_OFF) {
-		/* Lock new limit */
-		sleepmgr_lock_mode(sleep_mode[new_state]);
-	}
-	if (uhd_state != UHD_STATE_OFF) {
-		/* Unlock old limit */
-		sleepmgr_unlock_mode(sleep_mode[uhd_state]);
-	}
-	uhd_state = new_state;
+    if (uhd_state == new_state)
+    {
+        return; /* No change*/
+    }
+    if (new_state != UHD_STATE_OFF)
+    {
+        /* Lock new limit */
+        sleepmgr_lock_mode(sleep_mode[new_state]);
+    }
+    if (uhd_state != UHD_STATE_OFF)
+    {
+        /* Unlock old limit */
+        sleepmgr_unlock_mode(sleep_mode[uhd_state]);
+    }
+    uhd_state = new_state;
 }
 
 #else
@@ -210,20 +213,20 @@ uint8_t uhd_ctrl_buffer[64];
  */
 
 struct uhd_ctrl_request_t{
-	/** Buffer to store the setup DATA phase */
-	uint8_t *payload;
-	/** Callback called when buffer is empty or full */
-	uhd_callback_setup_run_t callback_run;
-	/** Callback called when request is completed */
-	uhd_callback_setup_end_t callback_end;
-	/** Next setup request to process */
-	struct uhd_ctrl_request_t *next_request;
-	/** Setup request definition */
-	usb_setup_req_t req;
-	/** Size of buffer used in DATA phase */
-	uint16_t payload_size;
-	/** USB address of control endpoint */
-	usb_add_t add;
+    /** Buffer to store the setup DATA phase */
+    uint8_t *payload;
+    /** Callback called when buffer is empty or full */
+    uhd_callback_setup_run_t callback_run;
+    /** Callback called when request is completed */
+    uhd_callback_setup_end_t callback_end;
+    /** Next setup request to process */
+    struct uhd_ctrl_request_t *next_request;
+    /** Setup request definition */
+    usb_setup_req_t req;
+    /** Size of buffer used in DATA phase */
+    uint16_t payload_size;
+    /** USB address of control endpoint */
+    usb_add_t add;
 };
 
 /** Entry points of setup request list */
@@ -241,16 +244,16 @@ static bool uhd_b_suspend_requested;
 
 /** Bit definitions to store setup request state machine */
 typedef enum {
-	/** Wait a SETUP packet */
-	UHD_CTRL_REQ_PHASE_SETUP = 0,
-	/** Wait a OUT data packet */
-	UHD_CTRL_REQ_PHASE_DATA_OUT = 1,
-	/** Wait a IN data packet */
-	UHD_CTRL_REQ_PHASE_DATA_IN = 2,
-	/** Wait a IN ZLP packet */
-	UHD_CTRL_REQ_PHASE_ZLP_IN = 3,
-	/** Wait a OUT ZLP packet */
-	UHD_CTRL_REQ_PHASE_ZLP_OUT = 4,
+    /** Wait a SETUP packet */
+    UHD_CTRL_REQ_PHASE_SETUP = 0,
+    /** Wait a OUT data packet */
+    UHD_CTRL_REQ_PHASE_DATA_OUT = 1,
+    /** Wait a IN data packet */
+    UHD_CTRL_REQ_PHASE_DATA_IN = 2,
+    /** Wait a IN ZLP packet */
+    UHD_CTRL_REQ_PHASE_ZLP_IN = 3,
+    /** Wait a OUT ZLP packet */
+    UHD_CTRL_REQ_PHASE_ZLP_OUT = 4,
 } uhd_ctrl_request_phase_t;
 uhd_ctrl_request_phase_t uhd_ctrl_request_phase;
 
@@ -270,24 +273,24 @@ uhd_ctrl_request_phase_t uhd_ctrl_request_phase;
 
 /** Structure definition to store registered jobs on a pipe */
 typedef struct {
-	/** Buffer located in internal RAM to send or fill during job */
-	uint8_t *buf;
-	/** Internal buffer allocated in internal RAM to receive data in case of small user buffer */
-	uint8_t *buf_internal;
-	/** Size of buffer to send or fill */
-	iram_size_t buf_size;
-	/** Total number of transferred data on endpoint */
-	iram_size_t nb_trans;
-	/** Callback to call at the end of transfer */
-	uhd_callback_trans_t call_end;
-
-	/** timeout on this request (ms) */
-	uint16_t timeout;
-
-	/** A job is registered on this pipe */
-	uint8_t busy:1;
-	/** A short packet is requested for this job on endpoint IN */
-	uint8_t b_shortpacket:1;
+    /** Buffer located in internal RAM to send or fill during job */
+    uint8_t *buf;
+    /** Internal buffer allocated in internal RAM to receive data in case of small user buffer */
+    uint8_t *buf_internal;
+    /** Size of buffer to send or fill */
+    iram_size_t buf_size;
+    /** Total number of transferred data on endpoint */
+    iram_size_t nb_trans;
+    /** Callback to call at the end of transfer */
+    uhd_callback_trans_t call_end;
+
+    /** timeout on this request (ms) */
+    uint16_t timeout;
+
+    /** A job is registered on this pipe */
+    uint8_t busy:1;
+    /** A short packet is requested for this job on endpoint IN */
+    uint8_t b_shortpacket:1;
 } uhd_pipe_job_t;
 
 /** Array to register a job on bulk/interrupt/isochronous endpoint */
@@ -309,42 +312,44 @@ struct usb_module dev;
  */
 static void _uhd_ctrl_phase_setup(void)
 {
-	usb_setup_req_t setup_req;
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_SETUP;
-	memcpy( &setup_req, &uhd_ctrl_request_first->req, sizeof(usb_setup_req_t));
-	/* Manage LSB/MSB to fit with CPU usage */
-	setup_req.wValue = cpu_to_le16(setup_req.wValue);
-	setup_req.wIndex = cpu_to_le16(setup_req.wIndex);
-	setup_req.wLength = cpu_to_le16(setup_req.wLength);
-	uhd_ctrl_nb_trans = 0;
-
-  	/* Check pipe */
+    usb_setup_req_t setup_req;
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_SETUP;
+    memcpy( &setup_req, &uhd_ctrl_request_first->req, sizeof(usb_setup_req_t));
+    /* Manage LSB/MSB to fit with CPU usage */
+    setup_req.wValue = cpu_to_le16(setup_req.wValue);
+    setup_req.wIndex = cpu_to_le16(setup_req.wIndex);
+    setup_req.wLength = cpu_to_le16(setup_req.wLength);
+    uhd_ctrl_nb_trans = 0;
+
+    /* Check pipe */
 #ifdef USB_HOST_HUB_SUPPORT
-	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) {
-		_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
-		return; // Endpoint not valid
-	}
+    if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE)
+    {
+        _uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+        return; /* Endpoint not valid*/
+    }
 #error TODO check address in list
-	/* Reconfigure USB address of pipe 0 used for all control endpoints */
-	uhd_udesc_set_uhaddr(0, uhd_ctrl_request_first->add);
+    /* Reconfigure USB address of pipe 0 used for all control endpoints */
+    uhd_udesc_set_uhaddr(0, uhd_ctrl_request_first->add);
 #else
-	if ((cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) ||
-			(uhd_ctrl_request_first->add != cfg.device_address)) {
-		_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
-		return; // Endpoint not valid
-	}
+    if ((cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) ||
+            (uhd_ctrl_request_first->add != cfg.device_address))
+            {
+        _uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+        return; /* Endpoint not valid*/
+    }
 #endif
 
-	/* Fill pipe */
-	memcpy(uhd_ctrl_buffer, &setup_req, sizeof(setup_req));
-	uhd_ctrl_request_timeout = 5000;
+    /* Fill pipe */
+    memcpy(uhd_ctrl_buffer, &setup_req, sizeof(setup_req));
+    uhd_ctrl_request_timeout = 5000;
 
-	/* Start transfer */
-	usb_host_pipe_setup_job(&dev, 0, uhd_ctrl_buffer);
-	usb_host_pipe_enable_callback(&dev, 0, USB_HOST_PIPE_CALLBACK_SETUP);
+    /* Start transfer */
+    usb_host_pipe_setup_job(&dev, 0, uhd_ctrl_buffer);
+    usb_host_pipe_enable_callback(&dev, 0, USB_HOST_PIPE_CALLBACK_SETUP);
 }
 
 /**
@@ -353,12 +358,12 @@ static void _uhd_ctrl_phase_setup(void)
  */
 static void _uhd_ctrl_phase_data_in_start(void)
 {
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
 
-	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_IN;
+    uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_IN;
 
-	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
+    usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
 }
 
 /**
@@ -369,53 +374,57 @@ static void _uhd_ctrl_phase_data_in_start(void)
  */
 static void _uhd_ctrl_phase_data_in(uint16_t nb_byte_received)
 {
-	bool b_short_packet;
-	uint8_t *ptr_ep_data;
+    bool b_short_packet;
+    uint8_t *ptr_ep_data;
 
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
 
-	/** In HUB mode, the control pipe is always configured to 64B */
-	/** thus the short packet flag must be computed */
-	b_short_packet = (nb_byte_received != cfg.size);
+    /** In HUB mode, the control pipe is always configured to 64B */
+    /** thus the short packet flag must be computed */
+    b_short_packet = (nb_byte_received != cfg.size);
 
-	ptr_ep_data = uhd_ctrl_buffer;
+    ptr_ep_data = uhd_ctrl_buffer;
 uhd_ctrl_receiv_in_read_data:
-	/* Copy data from pipe to payload buffer */
-	while (uhd_ctrl_request_first->payload_size && nb_byte_received) {
-		*uhd_ctrl_request_first->payload++ = *ptr_ep_data++;
-		uhd_ctrl_nb_trans++;
-		uhd_ctrl_request_first->payload_size--;
-		nb_byte_received--;
-	}
-
-	if (!uhd_ctrl_request_first->payload_size && nb_byte_received) {
-		/* payload buffer is full to store data remaining */
-		if (uhd_ctrl_request_first->callback_run == NULL
-				|| !uhd_ctrl_request_first->callback_run(
-				cfg.device_address,
-				&uhd_ctrl_request_first->payload,
-				&uhd_ctrl_request_first->payload_size)) {
-			/* DATA phase aborted by host */
-			goto uhd_ctrl_phase_data_in_end;
-		}
-		/*
-		 * The payload buffer has been updated by the callback
-		 *  thus the data load can restart.
-		 */
-		goto uhd_ctrl_receiv_in_read_data;
-	}
-
-	/* Test short packet */
-	if ((uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength)
-			|| b_short_packet) {
-		/* End of DATA phase or DATA phase abort from device */
+    /* Copy data from pipe to payload buffer */
+    while (uhd_ctrl_request_first->payload_size && nb_byte_received)
+    {
+        *uhd_ctrl_request_first->payload++ = *ptr_ep_data++;
+        uhd_ctrl_nb_trans++;
+        uhd_ctrl_request_first->payload_size--;
+        nb_byte_received--;
+    }
+
+    if (!uhd_ctrl_request_first->payload_size && nb_byte_received)
+    {
+        /* payload buffer is full to store data remaining */
+        if (uhd_ctrl_request_first->callback_run == NULL
+                || !uhd_ctrl_request_first->callback_run(
+                cfg.device_address,
+                &uhd_ctrl_request_first->payload,
+                &uhd_ctrl_request_first->payload_size))
+                {
+            /* DATA phase aborted by host */
+            goto uhd_ctrl_phase_data_in_end;
+        }
+        /*
+         * The payload buffer has been updated by the callback
+         *  thus the data load can restart.
+         */
+        goto uhd_ctrl_receiv_in_read_data;
+    }
+
+    /* Test short packet */
+    if ((uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength)
+            || b_short_packet)
+            {
+        /* End of DATA phase or DATA phase abort from device */
 uhd_ctrl_phase_data_in_end:
-		_uhd_ctrl_phase_zlp_out();
-		return;
-	}
+        _uhd_ctrl_phase_zlp_out();
+        return;
+    }
 
-	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
+    usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, cfg.size);
 }
 
 /**
@@ -424,11 +433,11 @@ static void _uhd_ctrl_phase_data_in(uint16_t nb_byte_received)
  */
 static void _uhd_ctrl_phase_zlp_in(void)
 {
-	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_IN;
+    uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_IN;
 
-	usb_host_pipe_set_toggle(&dev, 0);
+    usb_host_pipe_set_toggle(&dev, 0);
 
-	usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, 0);
+    usb_host_pipe_read_job(&dev, 0, uhd_ctrl_buffer, 0);
 }
 
 /**
@@ -437,46 +446,50 @@ static void _uhd_ctrl_phase_zlp_in(void)
  */
 static void _uhd_ctrl_phase_data_out(void)
 {
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_OUT;
-	uint16_t nb_trans;
-
-	if (uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength) {
-		/* End of DATA phase */
-		_uhd_ctrl_phase_zlp_in();
-		return;
-	}
-
-	if (!uhd_ctrl_request_first->payload_size) {
-		/* Buffer empty, then request a new buffer */
-		if (uhd_ctrl_request_first->callback_run==NULL
-				|| !uhd_ctrl_request_first->callback_run(
-				cfg.device_address,
-				&uhd_ctrl_request_first->payload,
-				&uhd_ctrl_request_first->payload_size)) {
-			/* DATA phase aborted by host */
-			_uhd_ctrl_phase_zlp_in();
-			return;
-		}
-	}
-
-	nb_trans = uhd_ctrl_request_first->payload_size;
-	if (nb_trans > cfg.size) {
-		nb_trans = cfg.size;
-	}
-
-	/* Link the user buffer directly on USB hardware DMA */
-	memcpy(uhd_ctrl_buffer, uhd_ctrl_request_first->payload, nb_trans);
-
-	/* Update counters */
-	uhd_ctrl_request_first->payload += nb_trans;
-	uhd_ctrl_nb_trans += nb_trans;
-	uhd_ctrl_request_first->payload_size -= nb_trans;
-
-	/* Start transfer */
-	usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, nb_trans);
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_DATA_OUT;
+    uint16_t nb_trans;
+
+    if (uhd_ctrl_nb_trans == uhd_ctrl_request_first->req.wLength)
+    {
+        /* End of DATA phase */
+        _uhd_ctrl_phase_zlp_in();
+        return;
+    }
+
+    if (!uhd_ctrl_request_first->payload_size)
+    {
+        /* Buffer empty, then request a new buffer */
+        if (uhd_ctrl_request_first->callback_run==NULL
+                || !uhd_ctrl_request_first->callback_run(
+                cfg.device_address,
+                &uhd_ctrl_request_first->payload,
+                &uhd_ctrl_request_first->payload_size))
+                {
+            /* DATA phase aborted by host */
+            _uhd_ctrl_phase_zlp_in();
+            return;
+        }
+    }
+
+    nb_trans = uhd_ctrl_request_first->payload_size;
+    if (nb_trans > cfg.size)
+    {
+        nb_trans = cfg.size;
+    }
+
+    /* Link the user buffer directly on USB hardware DMA */
+    memcpy(uhd_ctrl_buffer, uhd_ctrl_request_first->payload, nb_trans);
+
+    /* Update counters */
+    uhd_ctrl_request_first->payload += nb_trans;
+    uhd_ctrl_nb_trans += nb_trans;
+    uhd_ctrl_request_first->payload_size -= nb_trans;
+
+    /* Start transfer */
+    usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, nb_trans);
 }
 
 /**
@@ -485,13 +498,13 @@ static void _uhd_ctrl_phase_data_out(void)
  */
 static void _uhd_ctrl_phase_zlp_out(void)
 {
-	uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_OUT;
+    uhd_ctrl_request_phase = UHD_CTRL_REQ_PHASE_ZLP_OUT;
 
-	usb_host_pipe_set_toggle(&dev, 0);
+    usb_host_pipe_set_toggle(&dev, 0);
 
-	/* No need to link a user buffer directly on USB hardware DMA */
-	/* Start transfer */
-	usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, 0);
+    /* No need to link a user buffer directly on USB hardware DMA */
+    /* Start transfer */
+    usb_host_pipe_write_job(&dev, 0, uhd_ctrl_buffer, 0);
 }
 
 /**
@@ -502,41 +515,44 @@ static void _uhd_ctrl_phase_zlp_out(void)
  */
 static void _uhd_ctrl_request_end(uhd_trans_status_t status)
 {
-	irqflags_t flags;
-	uhd_callback_setup_end_t callback_end;
-	struct uhd_ctrl_request_t *request_to_free;
-	bool b_new_request;
-
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	Assert (uhd_ctrl_request_first != NULL);
-
-	uhd_ctrl_request_timeout = 0;
-
-	/* Remove request from the control request list */
-	callback_end = uhd_ctrl_request_first->callback_end;
-	request_to_free = uhd_ctrl_request_first;
-	flags = cpu_irq_save();
-	uhd_ctrl_request_first = uhd_ctrl_request_first->next_request;
-	b_new_request = (uhd_ctrl_request_first != NULL);
-	cpu_irq_restore(flags);
-	free(request_to_free);
-
-	/* Call callback */
-	if (callback_end != NULL) {
-		callback_end(cfg.device_address, status, uhd_ctrl_nb_trans);
-	}
-
-	/* If a setup request is pending and no started by previous callback */
-	if (b_new_request) {
-		_uhd_ctrl_phase_setup();
-	}
-	if (uhd_b_suspend_requested) {
-		/* A suspend request has been delay after all setup request */
-		uhd_b_suspend_requested = false;
-		uhd_suspend();
-	}
+    irqflags_t flags;
+    uhd_callback_setup_end_t callback_end;
+    struct uhd_ctrl_request_t *request_to_free;
+    bool b_new_request;
+
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    Assert (uhd_ctrl_request_first != NULL);
+
+    uhd_ctrl_request_timeout = 0;
+
+    /* Remove request from the control request list */
+    callback_end = uhd_ctrl_request_first->callback_end;
+    request_to_free = uhd_ctrl_request_first;
+    flags = cpu_irq_save();
+    uhd_ctrl_request_first = uhd_ctrl_request_first->next_request;
+    b_new_request = (uhd_ctrl_request_first != NULL);
+    cpu_irq_restore(flags);
+    free(request_to_free);
+
+    /* Call callback */
+    if (callback_end != NULL)
+    {
+        callback_end(cfg.device_address, status, uhd_ctrl_nb_trans);
+    }
+
+    /* If a setup request is pending and no started by previous callback */
+    if (b_new_request)
+    {
+        _uhd_ctrl_phase_setup();
+    }
+    if (uhd_b_suspend_requested)
+    {
+        /* A suspend request has been delay after all setup request */
+        uhd_b_suspend_requested = false;
+        uhd_suspend();
+    }
 }
 
 /**
@@ -554,71 +570,83 @@ static void _uhd_ctrl_request_end(uhd_trans_status_t status)
  */
 static void _uhd_sof_interrupt(struct usb_module *module_inst)
 {
-	/* Manage a delay to enter in suspend */
-	if (uhd_suspend_start) {
-		if (--uhd_suspend_start == 0) {
-			/* In case of high CPU frequency,
-			 *  the current Keep-Alive/SOF can be always on-going
-			 *  then wait end of SOF generation
-			 *  to be sure that disable SOF has been accepted
-			 */
-			dbg_print("SUSP\n");
-			usb_host_disable_sof(&dev);
-			/* Enable wakeup/resumes interrupts */
-			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
-			usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
-
-			/* Check that the hardware state machine has left the IDLE/Active mode
-			 * before freeze USB clock
-			 */
-			while (2==usb_get_state_machine_status(&dev));
-			uhd_sleep_mode(UHD_STATE_SUSPEND);
-		}
-		return; // Abort SOF events
-	}
-	/* Manage a delay to exit of suspend */
-	if (uhd_resume_start) {
-		if (--uhd_resume_start == 0) {
-			/* Restore pipes unfrozen */
-			for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
-				if ((uhd_pipes_unfreeze >> pipe) & 0x01) {
-					usb_host_pipe_unfreeze(&dev, pipe);
-				}
-			}
-			uhc_notify_resume();
-		}
-		return; // Abort SOF events
-	}
-	/* Manage the timeout on endpoint control transfer */
-	if (uhd_ctrl_request_timeout) {
-		/* Setup request on-going */
-		if (--uhd_ctrl_request_timeout == 0) {
-			/* Stop request */
-			usb_host_pipe_freeze(&dev, 0);
-			_uhd_ctrl_request_end(UHD_TRANS_TIMEOUT);
-		}
-	}
-	/* Manage the timeouts on endpoint transfer */
-	uhd_pipe_job_t *ptr_job;
-	for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
-		ptr_job = &uhd_pipe_job[pipe - 1];
-		if (ptr_job->busy == true) {
-			if (ptr_job->timeout) {
-				/* Timeout enabled on this job */
-				if (--ptr_job->timeout == 0) {
-					/* Abort job */
-					_uhd_ep_abort_pipe(pipe,UHD_TRANS_TIMEOUT);
-				}
-			}
-		}
-	}
-
-	/* Notify the UHC */
-	uhc_notify_sof(false);
-
-	/* Notify the user application */
-	UHC_SOF_EVENT();
+    /* Manage a delay to enter in suspend */
+    if (uhd_suspend_start)
+    {
+        if (--uhd_suspend_start == 0)
+        {
+            /* In case of high CPU frequency,
+             *  the current Keep-Alive/SOF can be always on-going
+             *  then wait end of SOF generation
+             *  to be sure that disable SOF has been accepted
+             */
+            dbg_print("SUSP\n");
+            usb_host_disable_sof(&dev);
+            /* Enable wakeup/resumes interrupts */
+            usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+            usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+            usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+
+            /* Check that the hardware state machine has left the IDLE/Active mode
+             * before freeze USB clock
+             */
+            while (2==usb_get_state_machine_status(&dev));
+            uhd_sleep_mode(UHD_STATE_SUSPEND);
+        }
+        return; /* Abort SOF events*/
+    }
+    /* Manage a delay to exit of suspend */
+    if (uhd_resume_start)
+    {
+        if (--uhd_resume_start == 0)
+        {
+            /* Restore pipes unfrozen */
+            for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++)
+            {
+                if ((uhd_pipes_unfreeze >> pipe) & 0x01)
+                {
+                    usb_host_pipe_unfreeze(&dev, pipe);
+                }
+            }
+            uhc_notify_resume();
+        }
+        return; /* Abort SOF events*/
+    }
+    /* Manage the timeout on endpoint control transfer */
+    if (uhd_ctrl_request_timeout)
+    {
+        /* Setup request on-going */
+        if (--uhd_ctrl_request_timeout == 0)
+        {
+            /* Stop request */
+            usb_host_pipe_freeze(&dev, 0);
+            _uhd_ctrl_request_end(UHD_TRANS_TIMEOUT);
+        }
+    }
+    /* Manage the timeouts on endpoint transfer */
+    uhd_pipe_job_t *ptr_job;
+    for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++)
+    {
+        ptr_job = &uhd_pipe_job[pipe - 1];
+        if (ptr_job->busy == true)
+        {
+            if (ptr_job->timeout)
+            {
+                /* Timeout enabled on this job */
+                if (--ptr_job->timeout == 0)
+                {
+                    /* Abort job */
+                    _uhd_ep_abort_pipe(pipe,UHD_TRANS_TIMEOUT);
+                }
+            }
+        }
+    }
+
+    /* Notify the UHC */
+    uhc_notify_sof(false);
+
+    /* Notify the user application */
+    UHC_SOF_EVENT();
 }
 
 /**
@@ -629,9 +657,10 @@ static void _uhd_sof_interrupt(struct usb_module *module_inst)
  */
 static void _uhd_reset(struct usb_module *module_inst)
 {
-	if (uhd_reset_callback != NULL) {
-		uhd_reset_callback();
-	}
+    if (uhd_reset_callback != NULL)
+    {
+        uhd_reset_callback();
+    }
 }
 
 /**
@@ -642,28 +671,29 @@ static void _uhd_reset(struct usb_module *module_inst)
  */
 static void _uhd_wakeup(struct usb_module *module_inst)
 {
-	/* Here the wakeup interrupt has been used to detect:
-	 * - connection with an asynchronous interrupt
-	 * - down/upstream resume with an asynchronous interrupt
-	 */
-	dbg_print("WAKEUP\n");
+    /* Here the wakeup interrupt has been used to detect:
+     * - connection with an asynchronous interrupt
+     * - down/upstream resume with an asynchronous interrupt
+     */
+    dbg_print("WAKEUP\n");
 #ifdef USB_HOST_LPM_SUPPORT
-	if (uhd_lpm_suspend) {
-		usb_host_send_l1_resume(&dev);
-		uhd_lpm_suspend = false;
-		uhc_notify_resume_lpm();
-	} else
+    if (uhd_lpm_suspend)
+    {
+        usb_host_send_l1_resume(&dev);
+        uhd_lpm_suspend = false;
+        uhc_notify_resume_lpm();
+    } else
 #endif
-	{
-		usb_host_send_resume(&dev);
-		/* Wait 50ms before restarting transfer */
-		uhd_resume_start = 50;
-	}
-	/* Disable wakeup/resumes interrupts */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
-	uhd_sleep_mode(UHD_STATE_IDLE);
+    {
+        usb_host_send_resume(&dev);
+        /* Wait 50ms before restarting transfer */
+        uhd_resume_start = 50;
+    }
+    /* Disable wakeup/resumes interrupts */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+    uhd_sleep_mode(UHD_STATE_IDLE);
 }
 
 /**
@@ -674,22 +704,23 @@ static void _uhd_wakeup(struct usb_module *module_inst)
  */
 static void _uhd_downstream_resume(struct usb_module *module_inst)
 {
-	dbg_print("DOWN RES\n");
-	/* Disable wakeup/resumes interrupts */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+    dbg_print("DOWN RES\n");
+    /* Disable wakeup/resumes interrupts */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
 #ifdef USB_HOST_LPM_SUPPORT
-	if (uhd_lpm_suspend) {
-		uhd_lpm_suspend = false;
-		uhc_notify_resume_lpm();
-	} else
+    if (uhd_lpm_suspend)
+    {
+        uhd_lpm_suspend = false;
+        uhc_notify_resume_lpm();
+    } else
 #endif
-	{
-		/* Wait 50ms before restarting transfer */
-		uhd_resume_start = 50;
-	}
-	uhd_sleep_mode(UHD_STATE_IDLE);
+    {
+        /* Wait 50ms before restarting transfer */
+        uhd_resume_start = 50;
+    }
+    uhd_sleep_mode(UHD_STATE_IDLE);
 }
 
 /**
@@ -700,24 +731,25 @@ static void _uhd_downstream_resume(struct usb_module *module_inst)
  */
 static void _uhd_upstream_resume(struct usb_module *module_inst)
 {
-	dbg_print("UP RES\n");
+    dbg_print("UP RES\n");
 #ifdef USB_HOST_LPM_SUPPORT
-	if (uhd_lpm_suspend) {
-		usb_host_send_l1_resume(&dev);
-		uhd_lpm_suspend = false;
-		uhc_notify_resume_lpm();
-	} else
+    if (uhd_lpm_suspend)
+    {
+        usb_host_send_l1_resume(&dev);
+        uhd_lpm_suspend = false;
+        uhc_notify_resume_lpm();
+    } else
 #endif
-	{
-		usb_host_send_resume(&dev);
-		/* Wait 50ms before restarting transfer */
-		uhd_resume_start = 50;
-	}
-	/* Disable wakeup/resumes interrupts */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
-	uhd_sleep_mode(UHD_STATE_IDLE);
+    {
+        usb_host_send_resume(&dev);
+        /* Wait 50ms before restarting transfer */
+        uhd_resume_start = 50;
+    }
+    /* Disable wakeup/resumes interrupts */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+    uhd_sleep_mode(UHD_STATE_IDLE);
 }
 
 /**
@@ -729,9 +761,9 @@ static void _uhd_upstream_resume(struct usb_module *module_inst)
 static void _uhd_ram_error(struct usb_module *module_inst)
 {
 #ifdef UHC_RAM_ACCESS_ERR_EVENT
-	UHC_RAM_ACCESS_ERR_EVENT();
-#endif	
-	dbg_print("!!!! RAM ERR !!!!\n");
+    UHC_RAM_ACCESS_ERR_EVENT();
+#endif
+    dbg_print("!!!! RAM ERR !!!!\n");
 }
 
 /**
@@ -742,15 +774,15 @@ static void _uhd_ram_error(struct usb_module *module_inst)
  */
 static void _uhd_connect(struct usb_module *module_inst)
 {
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
-	dbg_print("CONN\n");
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	usb_host_enable_sof(&dev);
-	uhd_sleep_mode(UHD_STATE_IDLE);
-	uhd_suspend_start = 0;
-	uhd_resume_start = 0;
-	uhc_notify_connection(true);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+    dbg_print("CONN\n");
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    usb_host_enable_sof(&dev);
+    uhd_sleep_mode(UHD_STATE_IDLE);
+    uhd_suspend_start = 0;
+    uhd_resume_start = 0;
+    uhc_notify_connection(true);
 }
 
 /**
@@ -761,22 +793,22 @@ static void _uhd_connect(struct usb_module *module_inst)
  */
 static void _uhd_disconnect(struct usb_module *module_inst)
 {
-	/* This should be the normal way to handle this event. */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
-	dbg_print("DISC\n");
-	/* Disable wakeup/resumes interrupts,
-	 * in case of disconnection during suspend mode
-	 */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	/* Enable asynchronous wakeup interrupt to allow a CPU wakeup
-	 * when a connection occurs.
-	 */
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-	uhd_suspend_start = 0;
-	uhd_resume_start = 0;
-	uhd_sleep_mode(UHD_STATE_DISCONNECT);
-	uhc_notify_connection(false);
+    /* This should be the normal way to handle this event. */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+    dbg_print("DISC\n");
+    /* Disable wakeup/resumes interrupts,
+     * in case of disconnection during suspend mode
+     */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    /* Enable asynchronous wakeup interrupt to allow a CPU wakeup
+     * when a connection occurs.
+     */
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+    uhd_suspend_start = 0;
+    uhd_resume_start = 0;
+    uhd_sleep_mode(UHD_STATE_DISCONNECT);
+    uhc_notify_connection(false);
 }
 
 #if USB_VBUS_EIC
@@ -794,17 +826,19 @@ static void _uhd_disconnect(struct usb_module *module_inst)
  */
 static void _uhd_vbus_handler(void)
 {
-	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	if (is_usb_vbus_high()) {
-		UHC_VBUS_CHANGE(true);
-	}
-	if (!is_usb_vbus_high()) {
-		uhd_sleep_mode(UHD_STATE_NO_VBUS);
-		UHC_VBUS_CHANGE(false);
-	}
-	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    if (is_usb_vbus_high())
+    {
+        UHC_VBUS_CHANGE(true);
+    }
+    if (!is_usb_vbus_high())
+    {
+        uhd_sleep_mode(UHD_STATE_NO_VBUS);
+        UHC_VBUS_CHANGE(false);
+    }
+    extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 
 /**
@@ -812,277 +846,291 @@ static void _uhd_vbus_handler(void)
  */
 static void _usb_vbus_config(void)
 {
-	struct port_config pin_conf;
-	port_get_config_defaults(&pin_conf);
-
-	/* Set USB VBUS Pin as inputs */
-	pin_conf.direction  = PORT_PIN_DIR_INPUT;
-	pin_conf.input_pull = PORT_PIN_PULL_UP;
-	port_pin_set_config(USB_VBUS_PIN, &pin_conf);
-
-	/* Initialize EIC for vbus checking */
-	struct extint_chan_conf eint_chan_conf;
-	extint_chan_get_config_defaults(&eint_chan_conf);
-
-	eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
-	eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
-	eint_chan_conf.detection_criteria = EXTINT_DETECT_LOW;
-	eint_chan_conf.filter_input_signal = true;
-
-	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
-	extint_register_callback(_uhd_vbus_handler,
-			USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
-	extint_chan_enable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    struct port_config pin_conf;
+    port_get_config_defaults(&pin_conf);
+
+    /* Set USB VBUS Pin as inputs */
+    pin_conf.direction  = PORT_PIN_DIR_INPUT;
+    pin_conf.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(USB_VBUS_PIN, &pin_conf);
+
+    /* Initialize EIC for vbus checking */
+    struct extint_chan_conf eint_chan_conf;
+    extint_chan_get_config_defaults(&eint_chan_conf);
+
+    eint_chan_conf.gpio_pin           = USB_VBUS_PIN;
+    eint_chan_conf.gpio_pin_mux       = USB_VBUS_EIC_MUX;
+    eint_chan_conf.detection_criteria = EXTINT_DETECT_LOW;
+    eint_chan_conf.filter_input_signal = true;
+
+    extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf);
+    extint_register_callback(_uhd_vbus_handler,
+            USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_enable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 }
 /** @} */
 #endif
 
 void uhd_enable(void)
 {
-	irqflags_t flags;
+    irqflags_t flags;
 
-	/* To avoid USB interrupt before end of initialization */
-	flags = cpu_irq_save();
+    /* To avoid USB interrupt before end of initialization */
+    flags = cpu_irq_save();
 
 #if USB_ID_EIC
-	if (usb_dual_enable()) {
-		/* The current mode has been started by otg_dual_enable() */
-		cpu_irq_restore(flags);
-		return;
-	}
+    if (usb_dual_enable())
+    {
+        /* The current mode has been started by otg_dual_enable() */
+        cpu_irq_restore(flags);
+        return;
+    }
 #endif
-	uhd_ctrl_request_first = NULL;
-	uhd_ctrl_request_last = NULL;
-	uhd_ctrl_request_timeout = 0;
-	uhd_suspend_start = 0;
-	uhd_resume_start = 0;
-	uhd_b_suspend_requested = false;
+    uhd_ctrl_request_first = NULL;
+    uhd_ctrl_request_last = NULL;
+    uhd_ctrl_request_timeout = 0;
+    uhd_suspend_start = 0;
+    uhd_resume_start = 0;
+    uhd_b_suspend_requested = false;
 
-	struct usb_config cfg;
-	usb_get_config_defaults(&cfg);
-	cfg.select_host_mode = 1;
-	usb_init(&dev,USB, &cfg);
-	usb_enable(&dev);
+    struct usb_config cfg;
+    usb_get_config_defaults(&cfg);
+    cfg.select_host_mode = 1;
+    usb_init(&dev,USB, &cfg);
+    usb_enable(&dev);
 
-	uhd_sleep_mode(UHD_STATE_NO_VBUS);
+    uhd_sleep_mode(UHD_STATE_NO_VBUS);
 
 #if USB_VBUS_EIC
-	_usb_vbus_config();
-	if (is_usb_vbus_high()) {
-		/* Force Vbus interrupt when Vbus is always high */
-		_uhd_vbus_handler();
-		usb_host_enable(&dev);
-		uhd_sleep_mode(UHD_STATE_DISCONNECT);
-	} else {
-		dbg_print("VBUS low, there is some power issue on board!!! \n");
-	}
+    _usb_vbus_config();
+    if (is_usb_vbus_high())
+    {
+        /* Force Vbus interrupt when Vbus is always high */
+        _uhd_vbus_handler();
+        usb_host_enable(&dev);
+        uhd_sleep_mode(UHD_STATE_DISCONNECT);
+    } else {
+        dbg_print("VBUS low, there is some power issue on board!!! \n");
+    }
 #else
-	usb_host_enable(&dev);
+    usb_host_enable(&dev);
 #endif
 
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_SOF, _uhd_sof_interrupt);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_RESET, _uhd_reset);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_WAKEUP, _uhd_wakeup);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_DNRSM, _uhd_downstream_resume);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_UPRSM, _uhd_upstream_resume);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_RAMACER, _uhd_ram_error);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_CONNECT, _uhd_connect);
-	usb_host_register_callback(&dev, USB_HOST_CALLBACK_DISCONNECT, _uhd_disconnect);
-
-	/* Enable main control interrupt */
-	/* Connection, SOF and reset */
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_SOF);
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RESET);
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
-	usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
-
-	cpu_irq_restore(flags);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_SOF, _uhd_sof_interrupt);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_RESET, _uhd_reset);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_WAKEUP, _uhd_wakeup);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_DNRSM, _uhd_downstream_resume);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_UPRSM, _uhd_upstream_resume);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_RAMACER, _uhd_ram_error);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_CONNECT, _uhd_connect);
+    usb_host_register_callback(&dev, USB_HOST_CALLBACK_DISCONNECT, _uhd_disconnect);
+
+    /* Enable main control interrupt */
+    /* Connection, SOF and reset */
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_SOF);
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RESET);
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+    usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+
+    cpu_irq_restore(flags);
 }
 
 void uhd_disable(bool b_id_stop)
 {
-	irqflags_t flags;
-	UNUSED(b_id_stop);
+    irqflags_t flags;
+    UNUSED(b_id_stop);
 
-	/* Disable Vbus change interrupts */
+    /* Disable Vbus change interrupts */
 #if USB_VBUS_EIC
-	extint_chan_disable_callback(USB_VBUS_EIC_LINE,
-			EXTINT_CALLBACK_TYPE_DETECT);
+    extint_chan_disable_callback(USB_VBUS_EIC_LINE,
+            EXTINT_CALLBACK_TYPE_DETECT);
 #endif
 
- 	/* Disable main control interrupts */
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_SOF);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RESET);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
-	usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
-	usb_host_disable_sof(&dev);
-	uhc_notify_connection(false);
+    /* Disable main control interrupts */
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_SOF);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RESET);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_RAMACER);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_CONNECT);
+    usb_host_disable_callback(&dev, USB_HOST_CALLBACK_DISCONNECT);
+    usb_host_disable_sof(&dev);
+    uhc_notify_connection(false);
 
 #if USB_ID_EIC
-	uhd_sleep_mode(UHD_STATE_WAIT_ID_HOST);
-	if (!b_id_stop) {
-		return; // No need to disable host, it is done automatically by hardware
-	}
+    uhd_sleep_mode(UHD_STATE_WAIT_ID_HOST);
+    if (!b_id_stop)
+    {
+        return; /* No need to disable host, it is done automatically by hardware*/
+    }
 #endif
 
-	flags = cpu_irq_save();
-	usb_dual_disable();
-	cpu_irq_restore(flags);
+    flags = cpu_irq_save();
+    usb_dual_disable();
+    cpu_irq_restore(flags);
 }
 
 uhd_speed_t uhd_get_speed(void)
 {
-	switch (usb_host_get_speed(&dev)) {
-	case USB_SPEED_LOW:
-		return UHD_SPEED_LOW;
-	case USB_SPEED_FULL:
-		return UHD_SPEED_FULL;
-	default:
-		Assert(false);
-		return UHD_SPEED_LOW;
-	}
+    switch (usb_host_get_speed(&dev))
+    {
+    case USB_SPEED_LOW:
+        return UHD_SPEED_LOW;
+    case USB_SPEED_FULL:
+        return UHD_SPEED_FULL;
+    default:
+        Assert(false);
+        return UHD_SPEED_LOW;
+    }
 }
 
 uint16_t uhd_get_frame_number(void)
 {
-	return usb_host_get_frame_number(&dev);
+    return usb_host_get_frame_number(&dev);
 }
 
 uint16_t uhd_get_microframe_number(void)
 {
-	/* nothing to do */
-	return 0;
+    /* nothing to do */
+    return 0;
 }
 
 void uhd_send_reset(uhd_callback_reset_t callback)
 {
-	uhd_reset_callback = callback;
-	usb_host_send_reset(&dev);
+    uhd_reset_callback = callback;
+    usb_host_send_reset(&dev);
 }
 
 void uhd_suspend(void)
 {
-	if (uhd_ctrl_request_timeout) {
-		/* Delay suspend after setup requests */
-		uhd_b_suspend_requested = true;
-		return;
-	}
-	/* Save pipe freeze states and freeze pipes */
-	uhd_pipes_unfreeze = 0;
-	for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
-		uhd_pipes_unfreeze |= (!usb_host_pipe_is_frozen(&dev, pipe)) << pipe;
-		usb_host_pipe_freeze(&dev, pipe);
-	}
-	/* Wait three SOFs before entering in suspend state */
-	uhd_suspend_start = 3;
+    if (uhd_ctrl_request_timeout)
+    {
+        /* Delay suspend after setup requests */
+        uhd_b_suspend_requested = true;
+        return;
+    }
+    /* Save pipe freeze states and freeze pipes */
+    uhd_pipes_unfreeze = 0;
+    for (uint8_t pipe = 1; pipe < USB_PIPE_NUM; pipe++)
+    {
+        uhd_pipes_unfreeze |= (!usb_host_pipe_is_frozen(&dev, pipe)) << pipe;
+        usb_host_pipe_freeze(&dev, pipe);
+    }
+    /* Wait three SOFs before entering in suspend state */
+    uhd_suspend_start = 3;
 }
 
 bool uhd_is_suspend(void)
 {
-	return !usb_host_is_sof_enabled(&dev);
+    return !usb_host_is_sof_enabled(&dev);
 }
 
 void uhd_resume(void)
 {
-	if (usb_host_is_sof_enabled(&dev)) {
-		/* Currently in IDLE mode (!=Suspend) */
-		if (uhd_suspend_start) {
-			/* Suspend mode on going
-			 * then stop it and start resume event
-			 */
-			uhd_suspend_start = 0;
-			uhd_resume_start = 1;
-		}
-		return;
-	}
+    if (usb_host_is_sof_enabled(&dev))
+    {
+        /* Currently in IDLE mode (!=Suspend) */
+        if (uhd_suspend_start)
+        {
+            /* Suspend mode on going
+             * then stop it and start resume event
+             */
+            uhd_suspend_start = 0;
+            uhd_resume_start = 1;
+        }
+        return;
+    }
 
 #ifdef USB_HOST_LPM_SUPPORT
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
-		/* LPM Suspend command is on going, then ignore resume */
-		return;
-	}
-
-	if (uhd_lpm_suspend) {
-		dbg_print("SEND_RESUME_L1\n");
-		usb_host_send_l1_resume(&dev);
-	} else
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED)
+    {
+        /* LPM Suspend command is on going, then ignore resume */
+        return;
+    }
+
+    if (uhd_lpm_suspend)
+    {
+        dbg_print("SEND_RESUME_L1\n");
+        usb_host_send_l1_resume(&dev);
+    } else
 #endif
-	{
-		dbg_print("SEND_RESUME\n");
-		usb_host_send_resume(&dev);
-	}
-	uhd_sleep_mode(UHD_STATE_IDLE);
+    {
+        dbg_print("SEND_RESUME\n");
+        usb_host_send_resume(&dev);
+    }
+    uhd_sleep_mode(UHD_STATE_IDLE);
 }
 
 #ifdef USB_HOST_LPM_SUPPORT
 bool uhd_suspend_lpm(bool b_remotewakeup, uint8_t hird)
 {
-	if (uhd_ctrl_request_timeout) {
-		return false;
-	}
-	/* Do not freeze pipe to restart its immediatly after resume */
-	dbg_print("EXT_LPM\n");
-
-	/* Set the LPM job */
-	usb_host_pipe_lpm_job(&dev, 0, b_remotewakeup, hird);	
-
-	/* Wait LPM ACK through interrupt */
-	return true;
+    if (uhd_ctrl_request_timeout)
+    {
+        return false;
+    }
+    /* Do not freeze pipe to restart its immediatly after resume */
+    dbg_print("EXT_LPM\n");
+
+    /* Set the LPM job */
+    usb_host_pipe_lpm_job(&dev, 0, b_remotewakeup, hird);
+
+    /* Wait LPM ACK through interrupt */
+    return true;
 }
 #endif
 
 bool uhd_setup_request(
-		usb_add_t add,
-		usb_setup_req_t *req,
-		uint8_t *payload,
-		uint16_t payload_size,
-		uhd_callback_setup_run_t callback_run,
-		uhd_callback_setup_end_t callback_end)
+        usb_add_t add,
+        usb_setup_req_t *req,
+        uint8_t *payload,
+        uint16_t payload_size,
+        uhd_callback_setup_run_t callback_run,
+        uhd_callback_setup_end_t callback_end)
 {
-	irqflags_t flags;
-	struct uhd_ctrl_request_t *request;
-	bool b_start_request = false;
-
-	request = malloc(sizeof(struct uhd_ctrl_request_t));
-	if (request == NULL) {
-		Assert(false);
-		return false;
-	}
-
-	/* Fill structure */
-	request->add = (uint8_t) add;
-	memcpy(&request->req, req, sizeof(usb_setup_req_t));
-	request->payload = payload;
-	request->payload_size = payload_size;
-	request->callback_run = callback_run;
-	request->callback_end = callback_end;
-	request->next_request = NULL;
-
-	/* Add this request in the queue */
-	flags = cpu_irq_save();
-	if (uhd_ctrl_request_first == NULL) {
-		uhd_ctrl_request_first = request;
-		b_start_request = true;
-	} else {
-		uhd_ctrl_request_last->next_request = request;
-	}
-	uhd_ctrl_request_last = request;
-	cpu_irq_restore(flags);
-
-	if (b_start_request) {
-		/* Start immediately request */
-		_uhd_ctrl_phase_setup();
-	}
-	return true;
+    irqflags_t flags;
+    struct uhd_ctrl_request_t *request;
+    bool b_start_request = false;
+
+    request = malloc(sizeof(struct uhd_ctrl_request_t));
+    if (request == NULL)
+    {
+        Assert(false);
+        return false;
+    }
+
+    /* Fill structure */
+    request->add = (uint8_t) add;
+    memcpy(&request->req, req, sizeof(usb_setup_req_t));
+    request->payload = payload;
+    request->payload_size = payload_size;
+    request->callback_run = callback_run;
+    request->callback_end = callback_end;
+    request->next_request = NULL;
+
+    /* Add this request in the queue */
+    flags = cpu_irq_save();
+    if (uhd_ctrl_request_first == NULL)
+    {
+        uhd_ctrl_request_first = request;
+        b_start_request = true;
+    } else {
+        uhd_ctrl_request_last->next_request = request;
+    }
+    uhd_ctrl_request_last = request;
+    cpu_irq_restore(flags);
+
+    if (b_start_request)
+    {
+        /* Start immediately request */
+        _uhd_ctrl_phase_setup();
+    }
+    return true;
 }
 
 /**
@@ -1094,45 +1142,47 @@ bool uhd_setup_request(
  */
 static void _uhd_ep0_transfer_complete(struct usb_module *module_inst, void *pointer)
 {
-	struct usb_pipe_callback_parameter *p_callback_para;
-	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+    struct usb_pipe_callback_parameter *p_callback_para;
+    p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
 
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
 
 #ifdef USB_HOST_LPM_SUPPORT
-	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
-		dbg_print("EXT_LPM_ACK\n");
-		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
-		usb_host_pipe_set_config(&dev, 0, &cfg);
-		/* Enable wakeup/resumes interrupts */
-		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
-		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
-		usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
-		uhd_lpm_suspend = true;
-		uhd_sleep_mode(UHD_STATE_SUSPEND_LPM);
-		return;
-	}
+    if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED)
+    {
+        dbg_print("EXT_LPM_ACK\n");
+        cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+        usb_host_pipe_set_config(&dev, 0, &cfg);
+        /* Enable wakeup/resumes interrupts */
+        usb_host_enable_callback(&dev, USB_HOST_CALLBACK_WAKEUP);
+        usb_host_enable_callback(&dev, USB_HOST_CALLBACK_DNRSM);
+        usb_host_enable_callback(&dev, USB_HOST_CALLBACK_UPRSM);
+        uhd_lpm_suspend = true;
+        uhd_sleep_mode(UHD_STATE_SUSPEND_LPM);
+        return;
+    }
 #endif
 
-	usb_host_pipe_freeze(&dev, 0);
-	switch(uhd_ctrl_request_phase) {
-	case UHD_CTRL_REQ_PHASE_DATA_IN:
-		_uhd_ctrl_phase_data_in(p_callback_para->transfered_size);
-		break;
-	case UHD_CTRL_REQ_PHASE_ZLP_IN:
-		_uhd_ctrl_request_end(UHD_TRANS_NOERROR);
-		break;
-	case UHD_CTRL_REQ_PHASE_DATA_OUT:
-		_uhd_ctrl_phase_data_out();
-		break;
-	case UHD_CTRL_REQ_PHASE_ZLP_OUT:
-		_uhd_ctrl_request_end(UHD_TRANS_NOERROR);
-		break;
-	default:
-		Assert(false);
-		break;
-	}
+    usb_host_pipe_freeze(&dev, 0);
+    switch(uhd_ctrl_request_phase)
+    {
+    case UHD_CTRL_REQ_PHASE_DATA_IN:
+        _uhd_ctrl_phase_data_in(p_callback_para->transfered_size);
+        break;
+    case UHD_CTRL_REQ_PHASE_ZLP_IN:
+        _uhd_ctrl_request_end(UHD_TRANS_NOERROR);
+        break;
+    case UHD_CTRL_REQ_PHASE_DATA_OUT:
+        _uhd_ctrl_phase_data_out();
+        break;
+    case UHD_CTRL_REQ_PHASE_ZLP_OUT:
+        _uhd_ctrl_request_end(UHD_TRANS_NOERROR);
+        break;
+    default:
+        Assert(false);
+        break;
+    }
 }
 
 /**
@@ -1145,45 +1195,47 @@ static void _uhd_ep0_transfer_complete(struct usb_module *module_inst, void *poi
 static void _uhd_ep0_error(struct usb_module *module_inst, void *pointer)
 {
 #ifdef USB_HOST_LPM_SUPPORT
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
-		dbg_print("EXT_LPM_ERROR\n");
-		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
-		usb_host_pipe_set_config(&dev, 0, &cfg);
-		return;
-	}
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED)
+    {
+        dbg_print("EXT_LPM_ERROR\n");
+        cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+        usb_host_pipe_set_config(&dev, 0, &cfg);
+        return;
+    }
 #endif
 
-	dbg_print("CTRL Error\n");
-	struct usb_pipe_callback_parameter *p_callback_para;
-	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
-
-	uhd_trans_status_t uhd_error;
-
-	/* Get and ack error */
-	switch(p_callback_para->pipe_error_status) {
-	case USB_STATUS_PIPE_DTGLER:
-		uhd_error = UHD_TRANS_DT_MISMATCH;
-		break;
-	case USB_STATUS_PIPE_TOUTER:
-		uhd_error = UHD_TRANS_NOTRESPONDING;
-		break;
-	case USB_STATUS_PIPE_CRC16ER:
-		uhd_error = UHD_TRANS_CRC;
-		break;
-	case USB_STATUS_PIPE_DAPIDER:
-	case USB_STATUS_PIPE_PIDER:
-		uhd_error = UHD_TRANS_PIDFAILURE;
-		break;
-	default:
-		uhd_error = UHD_TRANS_TIMEOUT;
-		break;
-	}
-
-	/* Get and ack error */
-	_uhd_ctrl_request_end(uhd_error);
+    dbg_print("CTRL Error\n");
+    struct usb_pipe_callback_parameter *p_callback_para;
+    p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+    uhd_trans_status_t uhd_error;
+
+    /* Get and ack error */
+    switch(p_callback_para->pipe_error_status)
+    {
+    case USB_STATUS_PIPE_DTGLER:
+        uhd_error = UHD_TRANS_DT_MISMATCH;
+        break;
+    case USB_STATUS_PIPE_TOUTER:
+        uhd_error = UHD_TRANS_NOTRESPONDING;
+        break;
+    case USB_STATUS_PIPE_CRC16ER:
+        uhd_error = UHD_TRANS_CRC;
+        break;
+    case USB_STATUS_PIPE_DAPIDER:
+    case USB_STATUS_PIPE_PIDER:
+        uhd_error = UHD_TRANS_PIDFAILURE;
+        break;
+    default:
+        uhd_error = UHD_TRANS_TIMEOUT;
+        break;
+    }
+
+    /* Get and ack error */
+    _uhd_ctrl_request_end(uhd_error);
 }
 
 /**
@@ -1195,23 +1247,25 @@ static void _uhd_ep0_error(struct usb_module *module_inst, void *pointer)
  */
 static void _uhd_ep0_setup(struct usb_module *module_inst, void *null)
 {
-	/* SETUP packet sent */
-	usb_host_pipe_freeze(&dev, 0);
-	dbg_print("CTRL Setup\n");
-	Assert(uhd_ctrl_request_phase == UHD_CTRL_REQ_PHASE_SETUP);
-
-	/* Start DATA phase */
-	if ((uhd_ctrl_request_first->req.bmRequestType & USB_REQ_DIR_MASK)
-			== USB_REQ_DIR_IN ) {
-		_uhd_ctrl_phase_data_in_start();
-	} else {
-		if (uhd_ctrl_request_first->req.wLength) {
-			_uhd_ctrl_phase_data_out();
-		} else {
-			/* No DATA phase */
-			_uhd_ctrl_phase_zlp_in();
-		}
-	}
+    /* SETUP packet sent */
+    usb_host_pipe_freeze(&dev, 0);
+    dbg_print("CTRL Setup\n");
+    Assert(uhd_ctrl_request_phase == UHD_CTRL_REQ_PHASE_SETUP);
+
+    /* Start DATA phase */
+    if ((uhd_ctrl_request_first->req.bmRequestType & USB_REQ_DIR_MASK)
+            == USB_REQ_DIR_IN )
+            {
+        _uhd_ctrl_phase_data_in_start();
+    } else {
+        if (uhd_ctrl_request_first->req.wLength)
+        {
+            _uhd_ctrl_phase_data_out();
+        } else {
+            /* No DATA phase */
+            _uhd_ctrl_phase_zlp_in();
+        }
+    }
 }
 
 /**
@@ -1224,20 +1278,21 @@ static void _uhd_ep0_setup(struct usb_module *module_inst, void *null)
 static void _uhd_ep0_stall(struct usb_module *module_inst, void *null)
 {
 #ifdef USB_HOST_LPM_SUPPORT
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, 0, &cfg);
-
-	if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED) {
-		dbg_print("EXT_LPM_STALL\n");
-		cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
-		usb_host_pipe_set_config(&dev, 0, &cfg);
-		return;
-	}
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, 0, &cfg);
+
+    if (cfg.pipe_type == USB_HOST_PIPE_TYPE_EXTENDED)
+    {
+        dbg_print("EXT_LPM_STALL\n");
+        cfg.pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+        usb_host_pipe_set_config(&dev, 0, &cfg);
+        return;
+    }
 #endif
 
-	dbg_print("CTRL Stall\n");
-	/* Stall Handshake received */
-	_uhd_ctrl_request_end(UHD_TRANS_STALL);
+    dbg_print("CTRL Stall\n");
+    /* Stall Handshake received */
+    _uhd_ctrl_request_end(UHD_TRANS_STALL);
 }
 
 
@@ -1252,15 +1307,17 @@ static void _uhd_ep0_stall(struct usb_module *module_inst, void *null)
  */
 static uint8_t _uhd_get_pipe(usb_add_t add, usb_ep_t endp)
 {
-	struct usb_host_pipe_config cfg;
-	uint8_t usb_pipe = 1;
-	for (;usb_pipe < USB_PIPE_NUM;usb_pipe ++) {
-		usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
-		if ((add == cfg.device_address) && (endp == cfg.endpoint_address)) {
-			return usb_pipe;
-		}
-	}
-	return 0;
+    struct usb_host_pipe_config cfg;
+    uint8_t usb_pipe = 1;
+    for (;usb_pipe < USB_PIPE_NUM;usb_pipe ++)
+    {
+        usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
+        if ((add == cfg.device_address) && (endp == cfg.endpoint_address))
+        {
+            return usb_pipe;
+        }
+    }
+    return 0;
 }
 
 /**
@@ -1272,123 +1329,134 @@ static uint8_t _uhd_get_pipe(usb_add_t add, usb_ep_t endp)
  */
 static void _uhd_pipe_trans_complete(struct usb_module *module_inst, void *pointer)
 {
-	struct usb_pipe_callback_parameter *p_callback_para;
-	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
-
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, p_callback_para->pipe_num, &cfg);
-
-	uhd_pipe_job_t *ptr_job;
-	uint16_t pipe_size, nb_trans;
-	uint16_t max_trans;
-	iram_size_t next_trans;
-	irqflags_t flags;
-
-	pipe_size = cfg.size;
-
-	/* Get job corresponding at endpoint */
-	ptr_job = &uhd_pipe_job[p_callback_para->pipe_num - 1];
-
-	if (!ptr_job->busy) {
-		return; // No job is running, then ignore it (system error)
-	}
-
-	if (!(cfg.endpoint_address & USB_EP_DIR_IN)) {
-		usb_host_pipe_freeze(&dev, p_callback_para->pipe_num);
-		/* Transfer complete on OUT */
-		nb_trans = p_callback_para->transfered_size;
-
-		/* Update number of transferred data */
-		ptr_job->nb_trans += nb_trans;
-
-		/* Need to send other data */
-		if ((ptr_job->nb_trans != ptr_job->buf_size)
-				|| ptr_job->b_shortpacket) {
-			next_trans = ptr_job->buf_size - ptr_job->nb_trans;
-			if (UHD_ENDPOINT_MAX_TRANS < next_trans) {
-				/**
-				 * The USB hardware supports a maximum
-				 * transfer size of UHD_ENDPOINT_MAX_TRANS Bytes
-				 */
-				next_trans = UHD_ENDPOINT_MAX_TRANS -
-					(UHD_ENDPOINT_MAX_TRANS % pipe_size);
-				usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, false);
-			} else {
-				/* Need ZLP, if requested and last packet is not a short packet */
-				usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, ptr_job->b_shortpacket);
-				ptr_job->b_shortpacket = false; // No need to request another ZLP
-			}
-			usb_host_pipe_write_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
-
-			/* Enable interrupt */
-			flags = cpu_irq_save();
-			usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
-			cpu_irq_restore(flags);
-			return;
-		}
-	} else {
-		/* Transfer complete on IN */
-		nb_trans = p_callback_para->transfered_size;
-
-		/* May be required to copy received data from cache buffer to user buffer */
-		if (ptr_job->buf_internal != NULL) {
-			memcpy(&ptr_job->buf[ptr_job->nb_trans],
-					ptr_job->buf_internal,
-					ptr_job->buf_size % pipe_size);
-			free(ptr_job->buf_internal);
-			ptr_job->buf_internal = NULL;
-		}
-
-		/* Update number of transfered data */
-		ptr_job->nb_trans += nb_trans;
-		if (ptr_job->nb_trans > ptr_job->buf_size) {
-			ptr_job->nb_trans = ptr_job->buf_size;
-		}
-
-		/**
-		 * If all previous requested data have been received and user buffer not full
-		 * then need to receive other data
-		 */
-		if ((nb_trans == p_callback_para->required_size)
-			&& (ptr_job->nb_trans != ptr_job->buf_size)) {
-			next_trans = ptr_job->buf_size - ptr_job->nb_trans;
-			max_trans = UHD_ENDPOINT_MAX_TRANS;
-			/* 256 is the maximum of IN requests via UPINRQ */
-			if ((256L * pipe_size) < UHD_ENDPOINT_MAX_TRANS) {
-				max_trans = 256L * pipe_size;
-			}
-			if (max_trans < next_trans) {
-				/* The USB hardware support a maximum transfer size
-				  * of UHD_ENDPOINT_MAX_TRANS Bytes
-				  */
-				next_trans = max_trans;
-			}
-
-			if (next_trans < pipe_size) {
-				/* Use the cache buffer for Bulk or Interrupt size endpoint */
-				ptr_job->buf_internal = malloc(pipe_size);
-				if (ptr_job->buf_internal == NULL) {
-					Assert(ptr_job->buf_internal != NULL);
-					goto uhd_pipe_trans_complet_end;
-				}
-				usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, ptr_job->buf_internal, pipe_size);
-			} else {
-				next_trans -= next_trans % pipe_size;
-				/* Link the user buffer directly on USB hardware DMA */
-				usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
-			}
-			/* Enable interrupt */
-			flags = cpu_irq_save();
-			usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
-			cpu_irq_restore(flags);
-			return;
-		}
-	}
+    struct usb_pipe_callback_parameter *p_callback_para;
+    p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, p_callback_para->pipe_num, &cfg);
+
+    uhd_pipe_job_t *ptr_job;
+    uint16_t pipe_size, nb_trans;
+    uint16_t max_trans;
+    iram_size_t next_trans;
+    irqflags_t flags;
+
+    pipe_size = cfg.size;
+
+    /* Get job corresponding at endpoint */
+    ptr_job = &uhd_pipe_job[p_callback_para->pipe_num - 1];
+
+    if (!ptr_job->busy)
+    {
+        return; /* No job is running, then ignore it (system error)*/
+    }
+
+    if (!(cfg.endpoint_address & USB_EP_DIR_IN))
+    {
+        usb_host_pipe_freeze(&dev, p_callback_para->pipe_num);
+        /* Transfer complete on OUT */
+        nb_trans = p_callback_para->transfered_size;
+
+        /* Update number of transferred data */
+        ptr_job->nb_trans += nb_trans;
+
+        /* Need to send other data */
+        if ((ptr_job->nb_trans != ptr_job->buf_size)
+                || ptr_job->b_shortpacket)
+                {
+            next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+            if (UHD_ENDPOINT_MAX_TRANS < next_trans)
+            {
+                /**
+                 * The USB hardware supports a maximum
+                 * transfer size of UHD_ENDPOINT_MAX_TRANS Bytes
+                 */
+                next_trans = UHD_ENDPOINT_MAX_TRANS -
+                    (UHD_ENDPOINT_MAX_TRANS % pipe_size);
+                usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, false);
+            } else {
+                /* Need ZLP, if requested and last packet is not a short packet */
+                usb_host_pipe_set_auto_zlp(&dev, p_callback_para->pipe_num, ptr_job->b_shortpacket);
+                ptr_job->b_shortpacket = false; /* No need to request another ZLP*/
+            }
+            usb_host_pipe_write_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
+
+            /* Enable interrupt */
+            flags = cpu_irq_save();
+            usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+            cpu_irq_restore(flags);
+            return;
+        }
+    } else {
+        /* Transfer complete on IN */
+        nb_trans = p_callback_para->transfered_size;
+
+        /* May be required to copy received data from cache buffer to user buffer */
+        if (ptr_job->buf_internal != NULL)
+        {
+            memcpy(&ptr_job->buf[ptr_job->nb_trans],
+                    ptr_job->buf_internal,
+                    ptr_job->buf_size % pipe_size);
+            free(ptr_job->buf_internal);
+            ptr_job->buf_internal = NULL;
+        }
+
+        /* Update number of transfered data */
+        ptr_job->nb_trans += nb_trans;
+        if (ptr_job->nb_trans > ptr_job->buf_size)
+        {
+            ptr_job->nb_trans = ptr_job->buf_size;
+        }
+
+        /**
+         * If all previous requested data have been received and user buffer not full
+         * then need to receive other data
+         */
+        if ((nb_trans == p_callback_para->required_size)
+            && (ptr_job->nb_trans != ptr_job->buf_size))
+            {
+            next_trans = ptr_job->buf_size - ptr_job->nb_trans;
+            max_trans = UHD_ENDPOINT_MAX_TRANS;
+            /* 256 is the maximum of IN requests via UPINRQ */
+            if ((256L * pipe_size) < UHD_ENDPOINT_MAX_TRANS)
+            {
+                max_trans = 256L * pipe_size;
+            }
+            if (max_trans < next_trans)
+            {
+                /* The USB hardware support a maximum transfer size
+                  * of UHD_ENDPOINT_MAX_TRANS Bytes
+                  */
+                next_trans = max_trans;
+            }
+
+            if (next_trans < pipe_size)
+            {
+                /* Use the cache buffer for Bulk or Interrupt size endpoint */
+                ptr_job->buf_internal = malloc(pipe_size);
+                if (ptr_job->buf_internal == NULL)
+                {
+                    Assert(ptr_job->buf_internal != NULL);
+                    goto uhd_pipe_trans_complet_end;
+                }
+                usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, ptr_job->buf_internal, pipe_size);
+            } else {
+                next_trans -= next_trans % pipe_size;
+                /* Link the user buffer directly on USB hardware DMA */
+                usb_host_pipe_read_job(&dev, p_callback_para->pipe_num, &ptr_job->buf[ptr_job->nb_trans], next_trans);
+            }
+            /* Enable interrupt */
+            flags = cpu_irq_save();
+            usb_host_pipe_enable_callback(&dev,p_callback_para->pipe_num,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+            cpu_irq_restore(flags);
+            return;
+        }
+    }
 
 uhd_pipe_trans_complet_end:
-	/* Call callback to signal end of transfer */
-	_uhd_pipe_finish_job(p_callback_para->pipe_num, UHD_TRANS_NOERROR);
-	return;
+    /* Call callback to signal end of transfer */
+    _uhd_pipe_finish_job(p_callback_para->pipe_num, UHD_TRANS_NOERROR);
+    return;
 }
 
 /**
@@ -1400,8 +1468,8 @@ static void _uhd_pipe_trans_complete(struct usb_module *module_inst, void *point
  */
 static void _uhd_ep_abort_pipe(uint8_t pipe, uhd_trans_status_t status)
 {
-	usb_host_pipe_freeze(&dev, pipe);
-	_uhd_pipe_finish_job(pipe, status);
+    usb_host_pipe_freeze(&dev, pipe);
+    _uhd_pipe_finish_job(pipe, status);
 }
 
 /**
@@ -1413,28 +1481,31 @@ static void _uhd_ep_abort_pipe(uint8_t pipe, uhd_trans_status_t status)
  */
 static void _uhd_pipe_finish_job(uint8_t pipe, uhd_trans_status_t status)
 {
-	uhd_pipe_job_t *ptr_job;
-
-	struct usb_host_pipe_config cfg;
-	usb_host_pipe_get_config(&dev, pipe, &cfg);
-
-	/* Get job corresponding at endpoint */
-	ptr_job = &uhd_pipe_job[pipe - 1];
-	if (ptr_job->busy == false) {
-		return; // No job running
-	}
-	/* In case of abort, free the internal buffer */
-	if (ptr_job->buf_internal != NULL) {
-		free(ptr_job->buf_internal);
-		ptr_job->buf_internal = NULL;
-	}
-	ptr_job->busy = false;
-	if (NULL == ptr_job->call_end) {
-		return; // No callback linked to job
-	}
-	ptr_job->call_end(cfg.device_address,
-			cfg.endpoint_address,
-			status, ptr_job->nb_trans);
+    uhd_pipe_job_t *ptr_job;
+
+    struct usb_host_pipe_config cfg;
+    usb_host_pipe_get_config(&dev, pipe, &cfg);
+
+    /* Get job corresponding at endpoint */
+    ptr_job = &uhd_pipe_job[pipe - 1];
+    if (ptr_job->busy == false)
+    {
+        return; /* No job running*/
+    }
+    /* In case of abort, free the internal buffer */
+    if (ptr_job->buf_internal != NULL)
+    {
+        free(ptr_job->buf_internal);
+        ptr_job->buf_internal = NULL;
+    }
+    ptr_job->busy = false;
+    if (NULL == ptr_job->call_end)
+    {
+        return; /* No callback linked to job*/
+    }
+    ptr_job->call_end(cfg.device_address,
+            cfg.endpoint_address,
+            status, ptr_job->nb_trans);
 }
 
 /**
@@ -1446,32 +1517,33 @@ static void _uhd_pipe_finish_job(uint8_t pipe, uhd_trans_status_t status)
  */
 static void _uhd_ep_error(struct usb_module *module_inst, void *pointer)
 {
-	uhd_trans_status_t uhd_error;
-	struct usb_pipe_callback_parameter *p_callback_para;
-	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
-
-	dbg_print("Tr Error %x\n", p_callback_para->pipe_num);
-	/* Get and ack error */
-	switch(p_callback_para->pipe_error_status) {
-	case USB_STATUS_PIPE_DTGLER:
-		uhd_error = UHD_TRANS_DT_MISMATCH;
-		break;
-	case USB_STATUS_PIPE_TOUTER:
-		uhd_error = UHD_TRANS_NOTRESPONDING;
-		break;
-	case USB_STATUS_PIPE_CRC16ER:
-		uhd_error = UHD_TRANS_CRC;
-		break;
-	case USB_STATUS_PIPE_DAPIDER:
-	case USB_STATUS_PIPE_PIDER:
-		uhd_error = UHD_TRANS_PIDFAILURE;
-		break;
-	default:
-		uhd_error = UHD_TRANS_TIMEOUT;
-		break;
-	}
-
-	_uhd_ep_abort_pipe(p_callback_para->pipe_num, uhd_error);
+    uhd_trans_status_t uhd_error;
+    struct usb_pipe_callback_parameter *p_callback_para;
+    p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+
+    dbg_print("Tr Error %x\n", p_callback_para->pipe_num);
+    /* Get and ack error */
+    switch(p_callback_para->pipe_error_status)
+    {
+    case USB_STATUS_PIPE_DTGLER:
+        uhd_error = UHD_TRANS_DT_MISMATCH;
+        break;
+    case USB_STATUS_PIPE_TOUTER:
+        uhd_error = UHD_TRANS_NOTRESPONDING;
+        break;
+    case USB_STATUS_PIPE_CRC16ER:
+        uhd_error = UHD_TRANS_CRC;
+        break;
+    case USB_STATUS_PIPE_DAPIDER:
+    case USB_STATUS_PIPE_PIDER:
+        uhd_error = UHD_TRANS_PIDFAILURE;
+        break;
+    default:
+        uhd_error = UHD_TRANS_TIMEOUT;
+        break;
+    }
+
+    _uhd_ep_abort_pipe(p_callback_para->pipe_num, uhd_error);
 }
 
 /**
@@ -1483,185 +1555,201 @@ static void _uhd_ep_error(struct usb_module *module_inst, void *pointer)
  */
 static void _uhd_ep_stall(struct usb_module *module_inst, void *pointer)
 {
-	struct usb_pipe_callback_parameter *p_callback_para;
-	p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
+    struct usb_pipe_callback_parameter *p_callback_para;
+    p_callback_para = (struct usb_pipe_callback_parameter *)pointer;
 
-	dbg_print("Tr Stall %x\n", p_callback_para->pipe_num);
-	usb_host_pipe_clear_toggle(&dev, p_callback_para->pipe_num);
-	_uhd_ep_abort_pipe(p_callback_para->pipe_num, UHD_TRANS_STALL);
+    dbg_print("Tr Stall %x\n", p_callback_para->pipe_num);
+    usb_host_pipe_clear_toggle(&dev, p_callback_para->pipe_num);
+    _uhd_ep_abort_pipe(p_callback_para->pipe_num, UHD_TRANS_STALL);
 }
 
 bool uhd_ep0_alloc(usb_add_t add, uint8_t ep_size)
 {
-	struct usb_host_pipe_config cfg;
-
-	if (ep_size < 8) {
-		return false;
-	}
-
-	usb_host_pipe_get_config_defaults(&cfg);
-	cfg.device_address = add;
-	cfg.size = ep_size;
-	cfg.binterval = 0;
-	usb_host_pipe_set_config(&dev,0,&cfg);
-	usb_host_pipe_register_callback(&dev, 0,
-			USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_ep0_transfer_complete);
-	usb_host_pipe_register_callback(&dev, 0,
-			USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep0_error);
-	usb_host_pipe_register_callback(&dev, 0,
-			USB_HOST_PIPE_CALLBACK_SETUP, _uhd_ep0_setup);
-	usb_host_pipe_register_callback(&dev, 0,
-			USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep0_stall);
-	/* Always enable stall and error interrupts of control endpoint */
-	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
-	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_ERROR);
-	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_SETUP);
-	usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_STALL);
-	return true;
+    struct usb_host_pipe_config cfg;
+
+    if (ep_size < 8)
+    {
+        return false;
+    }
+
+    usb_host_pipe_get_config_defaults(&cfg);
+    cfg.device_address = add;
+    cfg.size = ep_size;
+    cfg.binterval = 0;
+    usb_host_pipe_set_config(&dev,0,&cfg);
+    usb_host_pipe_register_callback(&dev, 0,
+            USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_ep0_transfer_complete);
+    usb_host_pipe_register_callback(&dev, 0,
+            USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep0_error);
+    usb_host_pipe_register_callback(&dev, 0,
+            USB_HOST_PIPE_CALLBACK_SETUP, _uhd_ep0_setup);
+    usb_host_pipe_register_callback(&dev, 0,
+            USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep0_stall);
+    /* Always enable stall and error interrupts of control endpoint */
+    usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+    usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_ERROR);
+    usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_SETUP);
+    usb_host_pipe_enable_callback(&dev,0,USB_HOST_PIPE_CALLBACK_STALL);
+    return true;
 }
 
 bool uhd_ep_alloc(usb_add_t add, usb_ep_desc_t *ep_desc)
 {
-	uint8_t pipe = 1;
-	struct usb_host_pipe_config cfg;
-	uint8_t ep_type;
-	uint8_t ep_interval;
-
-	for (pipe = 1; pipe < USB_PIPE_NUM; pipe++) {
-		usb_host_pipe_get_config(&dev, pipe, &cfg);
-		if (cfg.pipe_type != USB_HOST_PIPE_TYPE_DISABLE) {
-			continue;
-		}
-		usb_host_pipe_get_config_defaults(&cfg);
-		/* Enable pipe */
-		ep_type = (ep_desc->bmAttributes & USB_EP_TYPE_MASK) + 1;
-		if (ep_type == USB_HOST_PIPE_TYPE_BULK) {
-			ep_interval = 0; // Ignore bInterval for bulk endpoint
-		} else {
-			ep_interval = ep_desc->bInterval;
-		}
-		cfg.device_address = add;
-		cfg.endpoint_address = ep_desc->bEndpointAddress;
-		cfg.pipe_type = (enum usb_host_pipe_type)ep_type;
-		cfg.binterval = ep_interval;
-		cfg.size = le16_to_cpu(ep_desc->wMaxPacketSize);
-		usb_host_pipe_set_config(&dev,pipe,&cfg);
-
-		usb_host_pipe_register_callback(&dev, pipe,
-				USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_pipe_trans_complete);
-		usb_host_pipe_register_callback(&dev,pipe,
-				USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep_error);
-		usb_host_pipe_register_callback(&dev,pipe,
-				USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep_stall);
-		/* Enable endpoint interrupts */
-		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
-		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_ERROR);
-		usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_STALL);
-		return true;
-	}
-	return false;
+    uint8_t pipe = 1;
+    struct usb_host_pipe_config cfg;
+    uint8_t ep_type;
+    uint8_t ep_interval;
+
+    for (pipe = 1; pipe < USB_PIPE_NUM; pipe++)
+    {
+        usb_host_pipe_get_config(&dev, pipe, &cfg);
+        if (cfg.pipe_type != USB_HOST_PIPE_TYPE_DISABLE)
+        {
+            continue;
+        }
+        usb_host_pipe_get_config_defaults(&cfg);
+        /* Enable pipe */
+        ep_type = (ep_desc->bmAttributes & USB_EP_TYPE_MASK) + 1;
+        if (ep_type == USB_HOST_PIPE_TYPE_BULK)
+        {
+            ep_interval = 0; /* Ignore bInterval for bulk endpoint*/
+        } else {
+            ep_interval = ep_desc->bInterval;
+        }
+        cfg.device_address = add;
+        cfg.endpoint_address = ep_desc->bEndpointAddress;
+        cfg.pipe_type = (enum usb_host_pipe_type)ep_type;
+        cfg.binterval = ep_interval;
+        cfg.size = le16_to_cpu(ep_desc->wMaxPacketSize);
+        usb_host_pipe_set_config(&dev,pipe,&cfg);
+
+        usb_host_pipe_register_callback(&dev, pipe,
+                USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, _uhd_pipe_trans_complete);
+        usb_host_pipe_register_callback(&dev,pipe,
+                USB_HOST_PIPE_CALLBACK_ERROR, _uhd_ep_error);
+        usb_host_pipe_register_callback(&dev,pipe,
+                USB_HOST_PIPE_CALLBACK_STALL, _uhd_ep_stall);
+        /* Enable endpoint interrupts */
+        usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE);
+        usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_ERROR);
+        usb_host_pipe_enable_callback(&dev,pipe,USB_HOST_PIPE_CALLBACK_STALL);
+        return true;
+    }
+    return false;
 }
 
 
 void uhd_ep_free(usb_add_t add, usb_ep_t endp)
 {
-	uint8_t usb_pipe = 0;
-	struct usb_host_pipe_config cfg;
-
-	/* Search endpoint(s) in all pipes */
-	for (usb_pipe = 0; usb_pipe < USB_PIPE_NUM; usb_pipe++) {
-		usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
-
-		if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE) {
-			continue;
-		}
-
-		if (add != cfg.device_address) {
-			continue;
-		}
-
-		if (endp != 0xFF) {
-			/* Disable specific endpoint number */
-			if (!((endp == 0) && (0 == cfg.endpoint_address))) {
-				/* It is not the control endpoint */
-				if (endp != cfg.endpoint_address) {
-					continue; // Mismatch
-				}
-			}
-		}
-
-		if (usb_pipe == 0) {
-			/* Disable and stop transfer on control endpoint */
-			if (cfg.device_address == add) {
-				usb_host_pipe_freeze(&dev, 0);
-				if (uhd_ctrl_request_timeout ||
-						(uhd_ctrl_request_first != NULL)) {
-					_uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
-				}
-				continue;
-			}
-		}
-
-		/* Endpoint interrupt, bulk or isochronous */
-		/* Disable and stop transfer on this pipe */
-		usb_host_pipe_freeze(&dev, usb_pipe);
-		_uhd_pipe_finish_job(usb_pipe, UHD_TRANS_DISCONNECT);
-	}
+    uint8_t usb_pipe = 0;
+    struct usb_host_pipe_config cfg;
+
+    /* Search endpoint(s) in all pipes */
+    for (usb_pipe = 0; usb_pipe < USB_PIPE_NUM; usb_pipe++)
+    {
+        usb_host_pipe_get_config(&dev, usb_pipe, &cfg);
+
+        if (cfg.pipe_type == USB_HOST_PIPE_TYPE_DISABLE)
+        {
+            continue;
+        }
+
+        if (add != cfg.device_address)
+        {
+            continue;
+        }
+
+        if (endp != 0xFF)
+        {
+            /* Disable specific endpoint number */
+            if (!((endp == 0) && (0 == cfg.endpoint_address)))
+            {
+                /* It is not the control endpoint */
+                if (endp != cfg.endpoint_address)
+                {
+                    continue; /* Mismatch*/
+                }
+            }
+        }
+
+        if (usb_pipe == 0)
+        {
+            /* Disable and stop transfer on control endpoint */
+            if (cfg.device_address == add)
+            {
+                usb_host_pipe_freeze(&dev, 0);
+                if (uhd_ctrl_request_timeout ||
+                        (uhd_ctrl_request_first != NULL))
+                        {
+                    _uhd_ctrl_request_end(UHD_TRANS_DISCONNECT);
+                }
+                continue;
+            }
+        }
+
+        /* Endpoint interrupt, bulk or isochronous */
+        /* Disable and stop transfer on this pipe */
+        usb_host_pipe_freeze(&dev, usb_pipe);
+        _uhd_pipe_finish_job(usb_pipe, UHD_TRANS_DISCONNECT);
+    }
 }
 
 bool uhd_ep_run(
-		usb_add_t add,
-		usb_ep_t endp,
-		bool b_shortpacket,
-		uint8_t *buf,
-		iram_size_t buf_size,
-		uint16_t timeout,
-		uhd_callback_trans_t callback)
+        usb_add_t add,
+        usb_ep_t endp,
+        bool b_shortpacket,
+        uint8_t *buf,
+        iram_size_t buf_size,
+        uint16_t timeout,
+        uhd_callback_trans_t callback)
 {
-	irqflags_t flags;
-	uhd_pipe_job_t *ptr_job;
-	uint8_t pipe = 0;
-
-	struct usb_pipe_callback_parameter callback_para;
-
-	pipe = _uhd_get_pipe(add,endp);
-	if (!pipe) {
-		return false;
-	}
-	/* Get job about pipe */
-	ptr_job = &uhd_pipe_job[pipe - 1];
-	flags = cpu_irq_save();
-	if (ptr_job->busy == true) {
-		cpu_irq_restore(flags);
-		return false; // Job already on going
-	}
-	ptr_job->busy = true;
-
-	/* No job running. Let's setup a new one. */
-	ptr_job->buf = buf;
-	ptr_job->buf_size = buf_size;
-	ptr_job->nb_trans = 0;
-	ptr_job->timeout = timeout;
-	ptr_job->b_shortpacket = b_shortpacket;
-	ptr_job->call_end = callback;
-	cpu_irq_restore(flags);
-
-	/* Request first transfer */
-	callback_para.pipe_num = pipe;
-	callback_para.transfered_size = 0;
-	callback_para.required_size = 0;
-	_uhd_pipe_trans_complete(&dev, &callback_para);
-	return true;
+    irqflags_t flags;
+    uhd_pipe_job_t *ptr_job;
+    uint8_t pipe = 0;
+
+    struct usb_pipe_callback_parameter callback_para;
+
+    pipe = _uhd_get_pipe(add,endp);
+    if (!pipe)
+    {
+        return false;
+    }
+    /* Get job about pipe */
+    ptr_job = &uhd_pipe_job[pipe - 1];
+    flags = cpu_irq_save();
+    if (ptr_job->busy == true)
+    {
+        cpu_irq_restore(flags);
+        return false; /* Job already on going*/
+    }
+    ptr_job->busy = true;
+
+    /* No job running. Let's setup a new one. */
+    ptr_job->buf = buf;
+    ptr_job->buf_size = buf_size;
+    ptr_job->nb_trans = 0;
+    ptr_job->timeout = timeout;
+    ptr_job->b_shortpacket = b_shortpacket;
+    ptr_job->call_end = callback;
+    cpu_irq_restore(flags);
+
+    /* Request first transfer */
+    callback_para.pipe_num = pipe;
+    callback_para.transfered_size = 0;
+    callback_para.required_size = 0;
+    _uhd_pipe_trans_complete(&dev, &callback_para);
+    return true;
 }
 
 void uhd_ep_abort(usb_add_t add, usb_ep_t endp)
 {
-	uint8_t usb_pipe = 0;
+    uint8_t usb_pipe = 0;
 
-	usb_pipe = _uhd_get_pipe(add, endp);
-	if (usb_pipe) {
-		_uhd_ep_abort_pipe(usb_pipe, UHD_TRANS_ABORTED);
-	}
+    usb_pipe = _uhd_get_pipe(add, endp);
+    if (usb_pipe)
+    {
+        _uhd_ep_abort_pipe(usb_pipe, UHD_TRANS_ABORTED);
+    }
 }
 
 /** @} */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h
index fa29b1ffed0c..cd6cfc324397 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb.h
@@ -121,110 +121,110 @@ extern "C" {
 
 /** Enum for the speed status for the USB module */
 enum usb_speed {
-	USB_SPEED_LOW,
-	USB_SPEED_FULL,
+    USB_SPEED_LOW,
+    USB_SPEED_FULL,
 };
 
 /** Enum for the possible callback types for the USB in host module */
 enum usb_host_callback {
-	USB_HOST_CALLBACK_SOF,
-	USB_HOST_CALLBACK_RESET,
-	USB_HOST_CALLBACK_WAKEUP,
-	USB_HOST_CALLBACK_DNRSM,
-	USB_HOST_CALLBACK_UPRSM,
-	USB_HOST_CALLBACK_RAMACER,
-	USB_HOST_CALLBACK_CONNECT,
-	USB_HOST_CALLBACK_DISCONNECT,
-	USB_HOST_CALLBACK_N,
+    USB_HOST_CALLBACK_SOF,
+    USB_HOST_CALLBACK_RESET,
+    USB_HOST_CALLBACK_WAKEUP,
+    USB_HOST_CALLBACK_DNRSM,
+    USB_HOST_CALLBACK_UPRSM,
+    USB_HOST_CALLBACK_RAMACER,
+    USB_HOST_CALLBACK_CONNECT,
+    USB_HOST_CALLBACK_DISCONNECT,
+    USB_HOST_CALLBACK_N,
 };
 
 /** Enum for the possible callback types for the USB pipe in host module */
 enum usb_host_pipe_callback {
-	USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
-	USB_HOST_PIPE_CALLBACK_ERROR,
-	USB_HOST_PIPE_CALLBACK_SETUP,
-	USB_HOST_PIPE_CALLBACK_STALL,
-	USB_HOST_PIPE_CALLBACK_N,
+    USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
+    USB_HOST_PIPE_CALLBACK_ERROR,
+    USB_HOST_PIPE_CALLBACK_SETUP,
+    USB_HOST_PIPE_CALLBACK_STALL,
+    USB_HOST_PIPE_CALLBACK_N,
 };
 
 /**
  * \brief Host pipe types.
  */
 enum usb_host_pipe_type {
-	USB_HOST_PIPE_TYPE_DISABLE,
-	USB_HOST_PIPE_TYPE_CONTROL,
-	USB_HOST_PIPE_TYPE_ISO,
-	USB_HOST_PIPE_TYPE_BULK,
-	USB_HOST_PIPE_TYPE_INTERRUPT,
-	USB_HOST_PIPE_TYPE_EXTENDED,
+    USB_HOST_PIPE_TYPE_DISABLE,
+    USB_HOST_PIPE_TYPE_CONTROL,
+    USB_HOST_PIPE_TYPE_ISO,
+    USB_HOST_PIPE_TYPE_BULK,
+    USB_HOST_PIPE_TYPE_INTERRUPT,
+    USB_HOST_PIPE_TYPE_EXTENDED,
 };
 
 /**
  * \brief Host pipe token types.
  */
 enum usb_host_pipe_token {
-	USB_HOST_PIPE_TOKEN_SETUP,
-	USB_HOST_PIPE_TOKEN_IN,
-	USB_HOST_PIPE_TOKEN_OUT,
+    USB_HOST_PIPE_TOKEN_SETUP,
+    USB_HOST_PIPE_TOKEN_IN,
+    USB_HOST_PIPE_TOKEN_OUT,
 };
 
 /**
  * \brief Enumeration for the possible callback types for the USB in device module
  */
 enum usb_device_callback {
-	USB_DEVICE_CALLBACK_SOF,
-	USB_DEVICE_CALLBACK_RESET,
-	USB_DEVICE_CALLBACK_WAKEUP,
-	USB_DEVICE_CALLBACK_RAMACER,
-	USB_DEVICE_CALLBACK_SUSPEND,
-	USB_DEVICE_CALLBACK_LPMNYET,
-	USB_DEVICE_CALLBACK_LPMSUSP,
-	USB_DEVICE_CALLBACK_N,
+    USB_DEVICE_CALLBACK_SOF,
+    USB_DEVICE_CALLBACK_RESET,
+    USB_DEVICE_CALLBACK_WAKEUP,
+    USB_DEVICE_CALLBACK_RAMACER,
+    USB_DEVICE_CALLBACK_SUSPEND,
+    USB_DEVICE_CALLBACK_LPMNYET,
+    USB_DEVICE_CALLBACK_LPMSUSP,
+    USB_DEVICE_CALLBACK_N,
 };
 
 /**
  * \brief Enumeration for the possible callback types for the USB endpoint in device module
  */
 enum usb_device_endpoint_callback {
-	USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
-	USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
-	USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
-	USB_DEVICE_ENDPOINT_CALLBACK_STALL,
-	USB_DEVICE_EP_CALLBACK_N,
+    USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
+    USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
+    USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
+    USB_DEVICE_ENDPOINT_CALLBACK_STALL,
+    USB_DEVICE_EP_CALLBACK_N,
 };
 
 /**
  * \brief Device Endpoint types.
  */
 enum usb_device_endpoint_type {
-	USB_DEVICE_ENDPOINT_TYPE_DISABLE,
-	USB_DEVICE_ENDPOINT_TYPE_CONTROL,
-	USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
-	USB_DEVICE_ENDPOINT_TYPE_BULK,
-	USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
+    USB_DEVICE_ENDPOINT_TYPE_DISABLE,
+    USB_DEVICE_ENDPOINT_TYPE_CONTROL,
+    USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
+    USB_DEVICE_ENDPOINT_TYPE_BULK,
+    USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
 };
 
 /**
  * \brief Endpoint Size
  */
 enum usb_endpoint_size {
-	USB_ENDPOINT_8_BYTE,
-	USB_ENDPOINT_16_BYTE,
-	USB_ENDPOINT_32_BYTE,
+    USB_ENDPOINT_8_BYTE,
+    USB_ENDPOINT_16_BYTE,
+    USB_ENDPOINT_32_BYTE,
     USB_ENDPOINT_64_BYTE,
-	USB_ENDPOINT_128_BYTE,
-	USB_ENDPOINT_256_BYTE,
-	USB_ENDPOINT_512_BYTE,
-	USB_ENDPOINT_1023_BYTE,
+    USB_ENDPOINT_128_BYTE,
+    USB_ENDPOINT_256_BYTE,
+    USB_ENDPOINT_512_BYTE,
+    USB_ENDPOINT_1023_BYTE,
 };
 
 /**
  * \brief Link Power Management Handshake.
  */
 enum usb_device_lpm_mode {
-	USB_DEVICE_LPM_NOT_SUPPORT,
-	USB_DEVICE_LPM_ACK,
-	USB_DEVICE_LPM_NYET,
+    USB_DEVICE_LPM_NOT_SUPPORT,
+    USB_DEVICE_LPM_ACK,
+    USB_DEVICE_LPM_NYET,
 };
 
 /**
@@ -251,14 +251,14 @@ typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, v
 
 /** USB configurations */
 struct usb_config {
-	/** \c true for host, \c false for device. */
-	bool select_host_mode;
-	/** When \c true the module is enabled during standby. */
-	bool run_in_standby;
-	/** Generic Clock Generator source channel. */
-	enum gclk_generator source_generator;
-	/** Speed mode */
-	enum usb_speed speed_mode;
+    /** \c true for host, \c false for device. */
+    bool select_host_mode;
+    /** When \c true the module is enabled during standby. */
+    bool run_in_standby;
+    /** Generic Clock Generator source channel. */
+    enum gclk_generator source_generator;
+    /** Speed mode */
+    enum usb_speed speed_mode;
 };
 
 /**
@@ -269,80 +269,80 @@ struct usb_config {
  *
  */
 struct usb_module {
-	/** Hardware module pointer of the associated USB peripheral. */
-	Usb *hw;
+    /** Hardware module pointer of the associated USB peripheral. */
+    Usb *hw;
 
 #if !SAMD11 && !SAML22
-	/** Array to store host related callback functions */
-	usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
-	usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
-	/** Bit mask for host callbacks registered */
-	uint8_t host_registered_callback_mask;
-	/** Bit mask for host callbacks enabled */
-	uint8_t host_enabled_callback_mask;
-	/** Bit mask for host pipe callbacks registered */
-	uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
-	/** Bit mask for host pipe callbacks enabled */
-	uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
+    /** Array to store host related callback functions */
+    usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
+    usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
+    /** Bit mask for host callbacks registered */
+    uint8_t host_registered_callback_mask;
+    /** Bit mask for host callbacks enabled */
+    uint8_t host_enabled_callback_mask;
+    /** Bit mask for host pipe callbacks registered */
+    uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
+    /** Bit mask for host pipe callbacks enabled */
+    uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
 #endif
 
-	/** Array to store device related callback functions */
-	usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
-	usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
-	/** Bit mask for device callbacks registered */
-	uint16_t device_registered_callback_mask;
-	/** Bit mask for device callbacks enabled */
-	uint16_t device_enabled_callback_mask;
-	/** Bit mask for device endpoint callbacks registered */
-	uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM];
-	/** Bit mask for device endpoint callbacks enabled */
-	uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
+    /** Array to store device related callback functions */
+    usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
+    usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
+    /** Bit mask for device callbacks registered */
+    uint16_t device_registered_callback_mask;
+    /** Bit mask for device callbacks enabled */
+    uint16_t device_enabled_callback_mask;
+    /** Bit mask for device endpoint callbacks registered */
+    uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM];
+    /** Bit mask for device endpoint callbacks enabled */
+    uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
 };
 
 /** USB host pipe configurations */
 struct usb_host_pipe_config {
-	/** device address */
-	uint8_t device_address;
-	/** endpoint address  */
-	uint8_t endpoint_address;
-	/** Pipe type */
-	enum usb_host_pipe_type pipe_type;
-	/** interval */
-	uint8_t binterval;
-	/** pipe size */
-	uint16_t size;
+    /** device address */
+    uint8_t device_address;
+    /** endpoint address  */
+    uint8_t endpoint_address;
+    /** Pipe type */
+    enum usb_host_pipe_type pipe_type;
+    /** interval */
+    uint8_t binterval;
+    /** pipe size */
+    uint16_t size;
 };
 
 /** USB device endpoint configurations */
 struct usb_device_endpoint_config {
-	/** device address */
-	uint8_t ep_address;
-	/** endpoint size */
-	enum usb_endpoint_size ep_size;
-	/** automatic zero length packet mode, \c true to enable */
-	bool auto_zlp;
-	/** type of endpoint with Bank */
-	enum usb_device_endpoint_type ep_type;
+    /** device address */
+    uint8_t ep_address;
+    /** endpoint size */
+    enum usb_endpoint_size ep_size;
+    /** automatic zero length packet mode, \c true to enable */
+    bool auto_zlp;
+    /** type of endpoint with Bank */
+    enum usb_device_endpoint_type ep_type;
 };
 
 /** USB host pipe callback status parameter structure */
 struct usb_pipe_callback_parameter {
-	/** current pipe number */
-	uint8_t pipe_num;
-	/** pipe error status */
-	uint8_t pipe_error_status;
-	/** actual transferred data size */
-	uint16_t transfered_size;
-	/** required data size */
-	uint16_t required_size;
+    /** current pipe number */
+    uint8_t pipe_num;
+    /** pipe error status */
+    uint8_t pipe_error_status;
+    /** actual transferred data size */
+    uint16_t transfered_size;
+    /** required data size */
+    uint16_t required_size;
 };
 
 /** USB device endpoint callback status parameter structure */
 struct usb_endpoint_callback_parameter {
-	uint16_t received_bytes;
-	uint16_t sent_bytes;
-	uint16_t out_buffer_size;
-	uint8_t endpoint_address;
+    uint16_t received_bytes;
+    uint16_t sent_bytes;
+    uint16_t out_buffer_size;
+    uint8_t endpoint_address;
 };
 
 void usb_enable(struct usb_module *module_inst);
@@ -355,16 +355,16 @@ void usb_disable(struct usb_module *module_inst);
  */
 static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return module_inst->hw->DEVICE.FSMSTATUS.reg;
+    return module_inst->hw->DEVICE.FSMSTATUS.reg;
 }
 
 void usb_get_config_defaults(struct usb_config *module_config);
 enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
-		struct usb_config *module_config);
+        struct usb_config *module_config);
 
 #if !SAMD11 && !SAML22
 /**
@@ -374,11 +374,11 @@ enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
  */
 static inline void usb_host_enable(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
+    module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
 }
 
 /**
@@ -388,11 +388,11 @@ static inline void usb_host_enable(struct usb_module *module_inst)
  */
 static inline void usb_host_send_reset(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
+    module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
 }
 
 /**
@@ -402,11 +402,11 @@ static inline void usb_host_send_reset(struct usb_module *module_inst)
  */
 static inline void usb_host_enable_sof(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
+    module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
 }
 
 /**
@@ -416,11 +416,11 @@ static inline void usb_host_enable_sof(struct usb_module *module_inst)
  */
 static inline void usb_host_disable_sof(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
+    module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
 }
 
 /**
@@ -432,11 +432,11 @@ static inline void usb_host_disable_sof(struct usb_module *module_inst)
  */
 static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return module_inst->hw->HOST.CTRLB.bit.SOFE;
+    return module_inst->hw->HOST.CTRLB.bit.SOFE;
 }
 
 /**
@@ -446,11 +446,11 @@ static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
  */
 static inline void usb_host_send_resume(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
+    module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
 }
 
 /**
@@ -460,11 +460,11 @@ static inline void usb_host_send_resume(struct usb_module *module_inst)
  */
 static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
+    module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
 }
 
 /**
@@ -476,15 +476,16 @@ static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
  */
 static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) {
-		return USB_SPEED_FULL;
-	} else {
-		return USB_SPEED_LOW;
-	}
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    if (module_inst->hw->HOST.STATUS.bit.SPEED == 0)
+    {
+        return USB_SPEED_FULL;
+    } else {
+        return USB_SPEED_LOW;
+    }
 }
 
 /**
@@ -496,11 +497,11 @@ static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
  */
 static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
+    return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
 }
 #endif
 
@@ -511,7 +512,7 @@ static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
  */
 static inline void usb_device_attach(struct usb_module *module_inst)
 {
-	module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
+    module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
 }
 
 /**
@@ -521,7 +522,7 @@ static inline void usb_device_attach(struct usb_module *module_inst)
  */
 static inline void usb_device_detach(struct usb_module *module_inst)
 {
-	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
+    module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
 }
 
 /**
@@ -532,11 +533,12 @@ static inline void usb_device_detach(struct usb_module *module_inst)
  */
 static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst)
 {
-	if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
-		return USB_SPEED_FULL;
-	} else {
-		return USB_SPEED_LOW;
-	}
+    if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk))
+    {
+        return USB_SPEED_FULL;
+    } else {
+        return USB_SPEED_LOW;
+    }
 }
 
 /**
@@ -547,7 +549,7 @@ static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst
  */
 static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
 {
-	return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
+    return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
 }
 
 /**
@@ -558,7 +560,7 @@ static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
  */
 static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address)
 {
-	module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
+    module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
 }
 
 /**
@@ -569,7 +571,7 @@ static inline void usb_device_set_address(struct usb_module *module_inst, uint8_
  */
 static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst)
 {
-	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
+    return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
 }
 
 /**
@@ -580,7 +582,7 @@ static inline uint16_t usb_device_get_frame_number(struct usb_module *module_ins
  */
 static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst)
 {
-	return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
+    return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
 }
 
 /**
@@ -590,7 +592,7 @@ static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *modu
  */
 static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst)
 {
-	module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
+    module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
 }
 
 /**
@@ -600,9 +602,9 @@ static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst
  * \param lpm_mode    LPM mode
  */
 static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
-		enum usb_device_lpm_mode lpm_mode)
+        enum usb_device_lpm_mode lpm_mode)
 {
-	module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
+    module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
 }
 
 /**
@@ -610,14 +612,14 @@ static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
  * @{
  */
 enum status_code usb_host_register_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type,
-		usb_host_callback_t callback_func);
+        enum usb_host_callback callback_type,
+        usb_host_callback_t callback_func);
 enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type);
+        enum usb_host_callback callback_type);
 enum status_code usb_host_enable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type);
+        enum usb_host_callback callback_type);
 enum status_code usb_host_disable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type);
+        enum usb_host_callback callback_type);
 /** @} */
 
 /**
@@ -625,14 +627,14 @@ enum status_code usb_host_disable_callback(struct usb_module *module_inst,
  * @{
  */
 enum status_code usb_device_register_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type,
-		usb_device_callback_t callback_func);
+        enum usb_device_callback callback_type,
+        usb_device_callback_t callback_func);
 enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type);
+        enum usb_device_callback callback_type);
 enum status_code usb_device_enable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type);
+        enum usb_device_callback callback_type);
 enum status_code usb_device_disable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type);
+        enum usb_device_callback callback_type);
 /** @} */
 
 /**
@@ -641,9 +643,9 @@ enum status_code usb_device_disable_callback(struct usb_module *module_inst,
  */
 void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config);
 enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config);
+        struct usb_host_pipe_config *ep_config);
 enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config);
+        struct usb_host_pipe_config *ep_config);
 /** @} */
 
 /**
@@ -652,7 +654,7 @@ enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_
  */
 void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
 enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
-		struct usb_device_endpoint_config *ep_config);
+        struct usb_device_endpoint_config *ep_config);
 bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
 /** @} */
 
@@ -661,18 +663,18 @@ bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t e
  * @{
  */
 enum status_code usb_host_pipe_register_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type,
-		usb_host_pipe_callback_t callback_func);
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type,
+        usb_host_pipe_callback_t callback_func);
 enum status_code usb_host_pipe_unregister_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type);
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type);
 enum status_code usb_host_pipe_enable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type);
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type);
 enum status_code usb_host_pipe_disable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type);
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type);
 /** @} */
 
 /**
@@ -680,18 +682,18 @@ enum status_code usb_host_pipe_disable_callback(
  * @{
  */
 enum status_code usb_device_endpoint_register_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type,
-		usb_device_endpoint_callback_t callback_func);
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type,
+        usb_device_endpoint_callback_t callback_func);
 enum status_code usb_device_endpoint_unregister_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type);
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type);
 enum status_code usb_device_endpoint_enable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type);
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type);
 enum status_code usb_device_endpoint_disable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type);
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type);
 /** @} */
 
 /**
@@ -699,14 +701,14 @@ enum status_code usb_device_endpoint_disable_callback(
  * @{
  */
 enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf);
+        uint8_t pipe_num, uint8_t *buf);
 enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
 enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
 enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num);
 enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
-		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird);
+        uint8_t pipe_num, bool b_remotewakeup, uint8_t hird);
 /** @} */
 
 /**
@@ -714,11 +716,11 @@ enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
  * @{
  */
 enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size);
+        uint8_t* pbuf, uint32_t buf_size);
 enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size);
+        uint8_t* pbuf, uint32_t buf_size);
 enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
-		uint8_t* pbuf);
+        uint8_t* pbuf);
 void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
 /** @} */
 
@@ -736,11 +738,11 @@ void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
  */
 static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
 }
 
 /**
@@ -751,11 +753,11 @@ static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t
  */
 static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
 }
 
 /**
@@ -766,11 +768,11 @@ static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_
  */
 static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
+    return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
 }
 
 /**
@@ -781,11 +783,11 @@ static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8
  */
 static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
 }
 
 /**
@@ -796,11 +798,11 @@ static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint
  */
 static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c
index a6fe3420d77b..d30bda542b37 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_d_r/usb.c
@@ -84,9 +84,9 @@
 COMPILER_PACK_SET(1)
 COMPILER_WORD_ALIGNED
 union {
-	UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
+    UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
 #if !SAMD11
-	UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
+    UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
 #endif
 } usb_descriptor_table;
 COMPILER_PACK_RESET()
@@ -116,23 +116,23 @@ static struct usb_endpoint_callback_parameter ep_callback_para;
  * \internal USB Device IRQ Mask Bits Map
  */
 static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
-	USB_DEVICE_INTFLAG_SOF,
-	USB_DEVICE_INTFLAG_EORST,
-	USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
-	USB_DEVICE_INTFLAG_RAMACER,
-	USB_DEVICE_INTFLAG_SUSPEND,
-	USB_DEVICE_INTFLAG_LPMNYET,
-	USB_DEVICE_INTFLAG_LPMSUSP,
+    USB_DEVICE_INTFLAG_SOF,
+    USB_DEVICE_INTFLAG_EORST,
+    USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
+    USB_DEVICE_INTFLAG_RAMACER,
+    USB_DEVICE_INTFLAG_SUSPEND,
+    USB_DEVICE_INTFLAG_LPMNYET,
+    USB_DEVICE_INTFLAG_LPMSUSP,
 };
 
 /**
  * \internal USB Device IRQ Mask Bits Map
  */
 static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {
-	USB_DEVICE_EPINTFLAG_TRCPT_Msk,
-	USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
-	USB_DEVICE_EPINTFLAG_RXSTP,
-	USB_DEVICE_EPINTFLAG_STALL_Msk
+    USB_DEVICE_EPINTFLAG_TRCPT_Msk,
+    USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
+    USB_DEVICE_EPINTFLAG_RXSTP,
+    USB_DEVICE_EPINTFLAG_STALL_Msk
 };
 
 #if !SAMD11
@@ -158,20 +158,20 @@ uint32_t host_pipe_job_busy_status = 0;
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_host_register_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type,
-		usb_host_callback_t callback_func)
+        enum usb_host_callback callback_type,
+        usb_host_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->host_callback[callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->host_callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->host_registered_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module_inst->host_registered_callback_mask |= (1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -187,18 +187,18 @@ enum status_code usb_host_register_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	/* Unregister callback function */
-	module_inst->host_callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->host_callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->host_registered_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->host_registered_callback_mask &= ~(1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -214,41 +214,49 @@ enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_host_enable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Enable callback */
-	module_inst->host_enabled_callback_mask |= (1 << callback_type);
-
-	if (callback_type == USB_HOST_CALLBACK_SOF) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RESET) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
-	}
-	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
-	}
-	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Enable callback */
+    module_inst->host_enabled_callback_mask |= (1 << callback_type);
+
+    if (callback_type == USB_HOST_CALLBACK_SOF)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RESET)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+    }
+    if (callback_type == USB_HOST_CALLBACK_WAKEUP)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DNRSM)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_UPRSM)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RAMACER)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+    }
+    if (callback_type == USB_HOST_CALLBACK_CONNECT)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DISCONNECT)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -263,41 +271,49 @@ enum status_code usb_host_enable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_host_disable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Disable callback */
-	module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
-
-	if (callback_type == USB_HOST_CALLBACK_SOF) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RESET) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
-	}
-	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
-	}
-	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Disable callback */
+    module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
+
+    if (callback_type == USB_HOST_CALLBACK_SOF)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RESET)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
+    }
+    if (callback_type == USB_HOST_CALLBACK_WAKEUP)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DNRSM)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_UPRSM)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RAMACER)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
+    }
+    if (callback_type == USB_HOST_CALLBACK_CONNECT)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DISCONNECT)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -319,14 +335,14 @@ enum status_code usb_host_disable_callback(struct usb_module *module_inst,
  */
 void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(ep_config);
-	/* Write default config to config struct */
-	ep_config->device_address = 0;
-	ep_config->endpoint_address = 0;
-	ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
-	ep_config->binterval = 0;
-	ep_config->size = 8;
+    /* Sanity check arguments */
+    Assert(ep_config);
+    /* Write default config to config struct */
+    ep_config->device_address = 0;
+    ep_config->endpoint_address = 0;
+    ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+    ep_config->binterval = 0;
+    ep_config->size = 8;
 }
 
 /**
@@ -344,51 +360,54 @@ void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
  * \retval STATUS_OK    The host pipe was configured successfully.
  */
 enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config)
+        struct usb_host_pipe_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(ep_config);
-
-	/* set pipe config */
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
-	module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
-			ep_config->binterval;
-	if (ep_config->endpoint_address == 0) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_SETUP;
-	} else if (ep_config->endpoint_address & USB_EP_DIR_IN) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_IN;
-		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
-				USB_HOST_PSTATUSSET_BK0RDY;
-	} else {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_OUT;
-		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
-				USB_HOST_PSTATUSCLR_BK0RDY;
-	}
-
-	memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
-			sizeof(usb_descriptor_table.usb_pipe_table[0]));
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
-			ep_config->device_address;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
-			ep_config->endpoint_address & USB_EP_ADDR_MASK;
-	if (ep_config->size == 1023) {
-		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
-	} else {
-		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
-				(32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
-	}
-
-	/* Clear busy status */
-	host_pipe_job_busy_status &= ~(1 << pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(ep_config);
+
+    /* set pipe config */
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
+    module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
+            ep_config->binterval;
+    if (ep_config->endpoint_address == 0)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_SETUP;
+    } else if (ep_config->endpoint_address & USB_EP_DIR_IN)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_IN;
+        module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
+                USB_HOST_PSTATUSSET_BK0RDY;
+    } else {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_OUT;
+        module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
+                USB_HOST_PSTATUSCLR_BK0RDY;
+    }
+
+    memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
+            sizeof(usb_descriptor_table.usb_pipe_table[0]));
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
+            ep_config->device_address;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
+            ep_config->endpoint_address & USB_EP_ADDR_MASK;
+    if (ep_config->size == 1023)
+    {
+        usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
+    } else {
+        usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
+                (32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
+    }
+
+    /* Clear busy status */
+    host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -404,37 +423,39 @@ enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_
  * \retval STATUS_OK    The host pipe configuration was read successfully.
  */
 enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config)
+        struct usb_host_pipe_config *ep_config)
 {
-	uint32_t size;
-
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(ep_config);
-	/* get pipe config from setting register */
-	ep_config->device_address =
-			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
-	ep_config->endpoint_address =
-			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
-				USB_HOST_PIPE_TOKEN_IN) {
-		ep_config->endpoint_address |= USB_EP_DIR_IN;
-	}
-
-	ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
-	ep_config->binterval =
-			module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
-	size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
-	if (size == 0x07) {
-		ep_config->size = 1023;
-	} else {
-		ep_config->size = (8 << size);
-	}
-
-	return STATUS_OK;
+    uint32_t size;
+
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(ep_config);
+    /* get pipe config from setting register */
+    ep_config->device_address =
+            usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
+    ep_config->endpoint_address =
+            usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
+                USB_HOST_PIPE_TOKEN_IN)
+                {
+        ep_config->endpoint_address |= USB_EP_DIR_IN;
+    }
+
+    ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
+    ep_config->binterval =
+            module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
+    size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
+    if (size == 0x07)
+    {
+        ep_config->size = 1023;
+    } else {
+        ep_config->size = (8 << size);
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -455,22 +476,22 @@ enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_host_pipe_register_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type,
-		usb_host_pipe_callback_t callback_func)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type,
+        usb_host_pipe_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -487,20 +508,20 @@ enum status_code usb_host_pipe_register_callback(
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_host_pipe_unregister_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(pipe_num < USB_PIPE_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(pipe_num < USB_PIPE_NUM);
 
-	/* Unregister callback function */
-	module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -517,32 +538,36 @@ enum status_code usb_host_pipe_unregister_callback(
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_host_pipe_enable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	/* Enable callback */
-	module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
-
-	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
-				USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    /* Enable callback */
+    module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
+
+    if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
+                USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_STALL)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -558,32 +583,36 @@ enum status_code usb_host_pipe_enable_callback(
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_host_pipe_disable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	/* Enable callback */
-	module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
-
-	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
-				USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    /* Enable callback */
+    module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+    if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
+                USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_STALL)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -601,38 +630,40 @@ enum status_code usb_host_pipe_disable_callback(
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf)
+        uint8_t pipe_num, uint8_t *buf)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			8;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_SETUP;
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            8;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_SETUP;
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -652,39 +683,41 @@ enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			0;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			buf_size;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_IN;
-
-	/* Start transfer */
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            0;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            buf_size;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_IN;
+
+    /* Start transfer */
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -704,39 +737,41 @@ enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			buf_size;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_OUT;
-
-	/* Start transfer */
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            buf_size;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_OUT;
+
+    /* Start transfer */
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -753,22 +788,23 @@ enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
  */
 enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
 
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
 
-	/* Clear busy status */
-	host_pipe_job_busy_status &= ~(1 << pipe_num);
+    /* Clear busy status */
+    host_pipe_job_busy_status &= ~(1 << pipe_num);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -787,39 +823,41 @@ enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
-		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
+        uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
-				USB_HOST_PIPE_TYPE_EXTENDED;
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
-			USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
-			USB_LPM_ATTRIBUT_HIRD(hird) |
-			USB_LPM_ATTRIBUT_BLINKSTATE_L1;
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
+                USB_HOST_PIPE_TYPE_EXTENDED;
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
+            USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
+            USB_LPM_ATTRIBUT_HIRD(hird) |
+            USB_LPM_ATTRIBUT_BLINKSTATE_L1;
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -834,191 +872,219 @@ enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
  */
 static void _usb_host_interrupt_handler(void)
 {
-	uint32_t pipe_int;
-	uint32_t flags;
-
-	/* Manage pipe interrupts */
-	pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
-	if (pipe_int < 32) {
-		/* pipe interrupts */
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
-
-		/* host pipe transfer complete interrupt */
-		if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TRCPT_Msk;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
-							USB_HOST_PIPE_TOKEN_IN) {
-					/* in  */
-					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-				} else {
-					/* out */
-					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
-					if (0 == pipe_callback_para.transfered_size) {
-						pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					}
-				}
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-		/* host pipe transfer fail interrupt */
-		if (flags & USB_HOST_PINTFLAG_TRFAIL) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TRFAIL;
-		}
-
-		/* host pipe error interrupt */
-		if (flags & USB_HOST_PINTFLAG_PERR) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_PERR;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_ERROR)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				pipe_callback_para.pipe_error_status =
-						usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-		/* host pipe transmitted setup interrupt */
-		if (flags & USB_HOST_PINTFLAG_TXSTP) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TXSTP;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_SETUP)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
-			}
-		}
-
-		/* host pipe stall interrupt */
-		if (flags & USB_HOST_PINTFLAG_STALL) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_STALL;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_STALL)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-	} else {
-		/* host interrupts */
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->HOST.INTFLAG.reg;
-
-		/* host SOF interrupt */
-		if (flags & USB_HOST_INTFLAG_HSOF) {
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
-			}
-		}
-
-		/* host reset interrupt */
-		if (flags & USB_HOST_INTFLAG_RST) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
-			}
-		}
-
-		/* host upstream resume interrupts */
-		if (flags & USB_HOST_INTFLAG_UPRSM) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
-			}
-		}
-
-		/* host downstream resume interrupts */
-		if (flags & USB_HOST_INTFLAG_DNRSM) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
-			}
-		}
-
-		/* host wakeup interrupts */
-		if (flags & USB_HOST_INTFLAG_WAKEUP) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
-			}
-		}
-
-		/* host ram access interrupt  */
-		if (flags & USB_HOST_INTFLAG_RAMACER) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
-			}
-		}
-
-		/* host connect interrupt */
-		if (flags & USB_HOST_INTFLAG_DCONN) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
-			}
-		}
-
-		/* host disconnect interrupt 	*/
-		if (flags & USB_HOST_INTFLAG_DDISC) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
-			}
-		}
-
-	}
+    uint32_t pipe_int;
+    uint32_t flags;
+
+    /* Manage pipe interrupts */
+    pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
+    if (pipe_int < 32)
+    {
+        /* pipe interrupts */
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
+
+        /* host pipe transfer complete interrupt */
+        if (flags & USB_HOST_PINTFLAG_TRCPT_Msk)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TRCPT_Msk;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
+                            USB_HOST_PIPE_TOKEN_IN)
+                            {
+                    /* in  */
+                    pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                    usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+                } else {
+                    /* out */
+                    pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                    pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+                    if (0 == pipe_callback_para.transfered_size)
+                    {
+                        pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    }
+                }
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+        /* host pipe transfer fail interrupt */
+        if (flags & USB_HOST_PINTFLAG_TRFAIL)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TRFAIL;
+        }
+
+        /* host pipe error interrupt */
+        if (flags & USB_HOST_PINTFLAG_PERR)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_PERR;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_ERROR))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                pipe_callback_para.pipe_error_status =
+                        usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+        /* host pipe transmitted setup interrupt */
+        if (flags & USB_HOST_PINTFLAG_TXSTP)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TXSTP;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_SETUP))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
+            }
+        }
+
+        /* host pipe stall interrupt */
+        if (flags & USB_HOST_PINTFLAG_STALL)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_STALL;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_STALL))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+    } else {
+        /* host interrupts */
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->HOST.INTFLAG.reg;
+
+        /* host SOF interrupt */
+        if (flags & USB_HOST_INTFLAG_HSOF)
+        {
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
+            }
+        }
+
+        /* host reset interrupt */
+        if (flags & USB_HOST_INTFLAG_RST)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
+            }
+        }
+
+        /* host upstream resume interrupts */
+        if (flags & USB_HOST_INTFLAG_UPRSM)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
+            }
+        }
+
+        /* host downstream resume interrupts */
+        if (flags & USB_HOST_INTFLAG_DNRSM)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
+            }
+        }
+
+        /* host wakeup interrupts */
+        if (flags & USB_HOST_INTFLAG_WAKEUP)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
+            }
+        }
+
+        /* host ram access interrupt  */
+        if (flags & USB_HOST_INTFLAG_RAMACER)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
+            }
+        }
+
+        /* host connect interrupt */
+        if (flags & USB_HOST_INTFLAG_DCONN)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
+            }
+        }
+
+        /* host disconnect interrupt    */
+        if (flags & USB_HOST_INTFLAG_DDISC)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
+            }
+        }
+
+    }
 }
 
 /**
@@ -1031,9 +1097,9 @@ static void _usb_host_interrupt_handler(void)
  */
 void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value)
 {
-	Assert(module_inst);
+    Assert(module_inst);
 
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
 }
 #endif
 
@@ -1054,20 +1120,20 @@ void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_device_register_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type,
-		usb_device_callback_t callback_func)
+        enum usb_device_callback callback_type,
+        usb_device_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->device_callback[callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->device_callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
+    /* Set the bit corresponding to the callback_type */
+    module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1083,18 +1149,18 @@ enum status_code usb_device_register_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	/* Unregister callback function */
-	module_inst->device_callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->device_callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1110,21 +1176,21 @@ enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_device_enable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* clear related flag */
-	module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
+    /* clear related flag */
+    module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
 
-	/* Enable callback */
-	module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
+    /* Enable callback */
+    module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
 
-	module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
+    module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1139,18 +1205,18 @@ enum status_code usb_device_enable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_device_disable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Disable callback */
-	module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
+    /* Disable callback */
+    module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
 
-	module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
+    module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1171,22 +1237,22 @@ enum status_code usb_device_disable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_device_endpoint_register_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type,
-		usb_device_endpoint_callback_t callback_func)
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type,
+        usb_device_endpoint_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_num < USB_EPT_NUM);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_num < USB_EPT_NUM);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+    /* Set the bit corresponding to the callback_type */
+    module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1203,20 +1269,20 @@ enum status_code usb_device_endpoint_register_callback(
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_device_endpoint_unregister_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_num < USB_EPT_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_num < USB_EPT_NUM);
 
-	/* Unregister callback function */
-	module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1233,52 +1299,61 @@ enum status_code usb_device_endpoint_unregister_callback(
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_device_endpoint_enable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	Assert(ep_num < USB_EPT_NUM);
-
-	/* Enable callback */
-	module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
-		if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    Assert(ep_num < USB_EPT_NUM);
+
+    /* Enable callback */
+    module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL)
+    {
+        if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1294,52 +1369,61 @@ enum status_code usb_device_endpoint_enable_callback(
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_device_endpoint_disable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	Assert(ep_num < USB_EPT_NUM);
-
-	/* Enable callback */
-	module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
-		if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    Assert(ep_num < USB_EPT_NUM);
+
+    /* Enable callback */
+    module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL)
+    {
+        if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1360,14 +1444,14 @@ enum status_code usb_device_endpoint_disable_callback(
  */
 void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(ep_config);
-
-	/* Write default config to config struct */
-	ep_config->ep_address = 0;
-	ep_config->ep_size = USB_ENDPOINT_8_BYTE;
-	ep_config->auto_zlp = false;
-	ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
+    /* Sanity check arguments */
+    Assert(ep_config);
+
+    /* Write default config to config struct */
+    ep_config->ep_address = 0;
+    ep_config->ep_size = USB_ENDPOINT_8_BYTE;
+    ep_config->auto_zlp = false;
+    ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
 }
 
 /**
@@ -1385,107 +1469,120 @@ void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *
  * \retval STATUS_ERR_DENIED The endpoint address is already configured
  */
 enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
-		struct usb_device_endpoint_config *ep_config)
+        struct usb_device_endpoint_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_config);
-
-	uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
-	uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
-
-	switch (ep_config->ep_type) {
-		case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
-			return STATUS_OK;
-
-		case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
-			if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
-				(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-			} else {
-				return STATUS_ERR_DENIED;
-			}
-			if (true == ep_config->auto_zlp) {
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-			} else {
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-			}
-			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
-			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
-			return STATUS_OK;
-
-		case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		case USB_DEVICE_ENDPOINT_TYPE_BULK:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		default:
-			break;
-	}
-
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
-
-	if (true == ep_config->auto_zlp) {
-		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-		} else {
-		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_config);
+
+    uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
+    uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
+
+    switch (ep_config->ep_type)
+    {
+        case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
+            return STATUS_OK;
+
+        case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
+            if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
+                (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+            } else {
+                return STATUS_ERR_DENIED;
+            }
+            if (true == ep_config->auto_zlp)
+            {
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+            } else {
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+            }
+            usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
+            usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
+            return STATUS_OK;
+
+        case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        case USB_DEVICE_ENDPOINT_TYPE_BULK:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        default:
+            break;
+    }
+
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
+
+    if (true == ep_config->auto_zlp)
+    {
+        usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+        } else {
+        usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1498,15 +1595,16 @@ enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
  */
 bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	uint8_t flag;
-
-	if (ep & USB_EP_DIR_IN) {
-		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
-	} else {
-		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
-	}
-	return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    uint8_t flag;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+    } else {
+        flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+    }
+    return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
 }
 
 
@@ -1518,19 +1616,20 @@ bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t e
  */
 void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num;
-	ep_num = ep & USB_EP_ADDR_MASK;
-
-	// Stop transfer
-	if (ep & USB_EP_DIR_IN) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-		// Eventually ack a transfer occur during abort
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-	} else {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-		// Eventually ack a transfer occur during abort
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-	}
+    uint8_t ep_num;
+    ep_num = ep & USB_EP_ADDR_MASK;
+
+    /* Stop transfer*/
+    if (ep & USB_EP_DIR_IN)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+        /* Eventually ack a transfer occur during abort*/
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+    } else {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+        /* Eventually ack a transfer occur during abort*/
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+    }
 }
 
 /**
@@ -1543,13 +1642,14 @@ void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
  */
 bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	if (ep & USB_EP_DIR_IN) {
-		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
-	} else {
-		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
+    } else {
+        return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
+    }
 }
 
 /**
@@ -1560,14 +1660,15 @@ bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
  */
 void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	// Stall endpoint
-	if (ep & USB_EP_DIR_IN) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
-	} else {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    /* Stall endpoint*/
+    if (ep & USB_EP_DIR_IN)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+    } else {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+    }
 }
 
 /**
@@ -1578,29 +1679,34 @@ void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
  */
 void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	if (ep & USB_EP_DIR_IN) {
-		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
-			// Remove stall request
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
-			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
-				// The Stall has occurred, then reset data toggle
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
-			}
-		}
-	} else {
-		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
-			// Remove stall request
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
-			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
-				// The Stall has occurred, then reset data toggle
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
-			}
-		}
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1)
+        {
+            /* Remove stall request*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+            if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+            {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+                /* The Stall has occurred, then reset data toggle*/
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
+            }
+        }
+    } else {
+        if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0)
+        {
+            /* Remove stall request*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+            if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+            {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+                /* The Stall has occurred, then reset data toggle*/
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
+            }
+        }
+    }
 }
 
 /**
@@ -1616,26 +1722,27 @@ void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size)
+        uint8_t* pbuf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(ep_num < USB_EPT_NUM);
-
-	uint8_t flag;
-	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
-	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
-		return STATUS_ERR_DENIED;
-	};
-
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
-	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(ep_num < USB_EPT_NUM);
+
+    uint8_t flag;
+    flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+    if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE)
+    {
+        return STATUS_ERR_DENIED;
+    };
+
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
+    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+    return STATUS_OK;
 }
 
 /**
@@ -1651,26 +1758,27 @@ enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size)
+        uint8_t* pbuf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(ep_num < USB_EPT_NUM);
-
-	uint8_t flag;
-	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
-	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
-		return STATUS_ERR_DENIED;
-	};
-
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(ep_num < USB_EPT_NUM);
+
+    uint8_t flag;
+    flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+    if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE)
+    {
+        return STATUS_ERR_DENIED;
+    };
+
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+    return STATUS_OK;
 }
 
 /**
@@ -1684,138 +1792,163 @@ enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_i
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
-		uint8_t* pbuf)
+        uint8_t* pbuf)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-	module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+    module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 static void _usb_device_interrupt_handler(void)
 {
-	uint16_t ep_inst;
-	uint16_t flags, flags_run;
-	ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
-
-	/* device interrupt */
-	if (0 == ep_inst) {
-		int i;
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
-		flags_run = flags &
-				_usb_instances->device_enabled_callback_mask &
-				_usb_instances->device_registered_callback_mask;
-
-		for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) {
-			if (flags & _usb_device_irq_bits[i]) {
-				_usb_instances->hw->DEVICE.INTFLAG.reg =
-						_usb_device_irq_bits[i];
-			}
-			if (flags_run & _usb_device_irq_bits[i]) {
-				if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
-					device_callback_lpm_wakeup_enable =
-							usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
-							& USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
-				}
-				(_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
-			}
-		}
-
-	} else {
-		/* endpoint interrupt */
-
-		for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
-
-			if (ep_inst & (1 << i)) {
-				flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
-				flags_run = flags &
-						_usb_instances->device_endpoint_enabled_callback_mask[i] &
-						_usb_instances->device_endpoint_registered_callback_mask[i];
-
-				// endpoint transfer stall interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-					}
-
-					if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint received setup interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
-					_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
-					if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
-						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint transfer complete interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-						ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
-
-					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
-						ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
-					}
-					if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint transfer fail interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
-						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
-							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
-						}
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
-							return;
-						}
-					} else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
-						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
-							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
-						}
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
-							return;
-						}
-					}
-
-					if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-			}
-		}
-	}
+    uint16_t ep_inst;
+    uint16_t flags, flags_run;
+    ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
+
+    /* device interrupt */
+    if (0 == ep_inst)
+    {
+        int i;
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
+        flags_run = flags &
+                _usb_instances->device_enabled_callback_mask &
+                _usb_instances->device_registered_callback_mask;
+
+        for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++)
+        {
+            if (flags & _usb_device_irq_bits[i])
+            {
+                _usb_instances->hw->DEVICE.INTFLAG.reg =
+                        _usb_device_irq_bits[i];
+            }
+            if (flags_run & _usb_device_irq_bits[i])
+            {
+                if (i == USB_DEVICE_CALLBACK_LPMSUSP)
+                {
+                    device_callback_lpm_wakeup_enable =
+                            usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
+                            & USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
+                }
+                (_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
+            }
+        }
+
+    } else {
+        /* endpoint interrupt */
+
+        for (uint8_t i = 0; i < USB_EPT_NUM; i++)
+        {
+
+            if (ep_inst & (1 << i))
+            {
+                flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
+                flags_run = flags &
+                        _usb_instances->device_endpoint_enabled_callback_mask[i] &
+                        _usb_instances->device_endpoint_registered_callback_mask[i];
+
+                /* endpoint transfer stall interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                    } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                    }
+
+                    if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint received setup interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_RXSTP)
+                {
+                    _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+                    if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])
+                    {
+                        ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint transfer complete interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                        ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
+
+                    } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                        ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+                        ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
+                    }
+                    if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint transfer fail interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+                        if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+                        {
+                            usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+                        }
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                        if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+                        {
+                            return;
+                        }
+                    } else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+                        if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+                        {
+                            usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+                        }
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                        if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+                        {
+                            return;
+                        }
+                    }
+
+                    if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+            }
+        }
+    }
 }
 
 /**
@@ -1825,11 +1958,11 @@ static void _usb_device_interrupt_handler(void)
  */
 void usb_enable(struct usb_module *module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
-	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+    module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+    while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
 }
 
 /**
@@ -1839,13 +1972,13 @@ void usb_enable(struct usb_module *module_inst)
  */
 void usb_disable(struct usb_module *module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
-	module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
-	module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
-	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+    module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+    module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+    module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+    while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
 }
 
 /**
@@ -1853,15 +1986,16 @@ void usb_disable(struct usb_module *module_inst)
  */
 void USB_Handler(void)
 {
-	if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) {
+    if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE)
+    {
 #if !SAMD11
-		/*host mode ISR */
-		_usb_host_interrupt_handler();
+        /*host mode ISR */
+        _usb_host_interrupt_handler();
 #endif
-	} else {
-		/*device mode ISR */
-		_usb_device_interrupt_handler();
-	}
+    } else {
+        /*device mode ISR */
+        _usb_device_interrupt_handler();
+    }
 }
 
 /**
@@ -1871,15 +2005,15 @@ void USB_Handler(void)
  */
 void usb_get_config_defaults(struct usb_config *module_config)
 {
-	Assert(module_config);
-
-	/* Sanity check arguments */
-	Assert(module_config);
-	/* Write default configuration to config struct */
-	module_config->select_host_mode = 0;
-	module_config->run_in_standby = 1;
-	module_config->source_generator = GCLK_GENERATOR_0;
-	module_config->speed_mode = USB_SPEED_FULL;
+    Assert(module_config);
+
+    /* Sanity check arguments */
+    Assert(module_config);
+    /* Write default configuration to config struct */
+    module_config->select_host_mode = 0;
+    module_config->run_in_standby = 1;
+    module_config->source_generator = GCLK_GENERATOR_0;
+    module_config->speed_mode = USB_SPEED_FULL;
 }
 
 #define NVM_USB_PAD_TRANSN_POS  45
@@ -1904,138 +2038,152 @@ void usb_get_config_defaults(struct usb_config *module_config)
  * \retval STATUS_OK           The module was initialized successfully
  */
 enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
-		struct usb_config *module_config)
+        struct usb_config *module_config)
 {
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(module_inst);
-	Assert(module_config);
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(module_inst);
+    Assert(module_config);
 
-	uint32_t i,j;
-	uint32_t pad_transn, pad_transp, pad_trim;
-	struct system_pinmux_config pin_config;
-	struct system_gclk_chan_config gclk_chan_config;
+    uint32_t i,j;
+    uint32_t pad_transn, pad_transp, pad_trim;
+    struct system_pinmux_config pin_config;
+    struct system_gclk_chan_config gclk_chan_config;
 
 #if !SAMD11
-	host_pipe_job_busy_status = 0;
+    host_pipe_job_busy_status = 0;
 #endif
 
-	_usb_instances = module_inst;
-
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_USB);
-
-	/* Set up the USB DP/DN pins */
-	system_pinmux_get_config_defaults(&pin_config);
-	pin_config.mux_position = MUX_PA24G_USB_DM;
-	system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
-	pin_config.mux_position = MUX_PA25G_USB_DP;
-	system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
-
-	/* Setup clock for module */
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = module_config->source_generator;
-	system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
-	system_gclk_chan_enable(USB_GCLK_ID);
-
-	/* Reset */
-	hw->DEVICE.CTRLA.bit.SWRST = 1;
-	while (hw->DEVICE.SYNCBUSY.bit.SWRST) {
-		/* Sync wait */
-	}
-
-	/* Change QOS values to have the best performance and correct USB behaviour */
-	USB->DEVICE.QOSCTRL.bit.CQOS = 2;
-	USB->DEVICE.QOSCTRL.bit.DQOS = 2;
-
-	/* Load Pad Calibration */
-	pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRANSN_POS / 32))
-		>> (NVM_USB_PAD_TRANSN_POS % 32))
-		& ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
-
-	if (pad_transn == 0x1F) {
-		pad_transn = 5;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
-
-	pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRANSP_POS / 32))
-			>> (NVM_USB_PAD_TRANSP_POS % 32))
-			& ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
-
-	if (pad_transp == 0x1F) {
-		pad_transp = 29;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
-
-	pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRIM_POS / 32))
-			>> (NVM_USB_PAD_TRIM_POS % 32))
-			& ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
-
-	if (pad_trim == 0x7) {
-		pad_trim = 3;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
-
-	/* Set the configuration */
-	hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
-	hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
-	hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
-	if (USB_SPEED_FULL == module_config->speed_mode) {
-		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
-	} else if(USB_SPEED_LOW == module_config->speed_mode) {
-		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
-	}
-
-	memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
-			sizeof(usb_descriptor_table.usb_endpoint_table));
+    _usb_instances = module_inst;
+
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_USB);
+
+    /* Set up the USB DP/DN pins */
+    system_pinmux_get_config_defaults(&pin_config);
+    pin_config.mux_position = MUX_PA24G_USB_DM;
+    system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
+    pin_config.mux_position = MUX_PA25G_USB_DP;
+    system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
+
+    /* Setup clock for module */
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = module_config->source_generator;
+    system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
+    system_gclk_chan_enable(USB_GCLK_ID);
+
+    /* Reset */
+    hw->DEVICE.CTRLA.bit.SWRST = 1;
+    while (hw->DEVICE.SYNCBUSY.bit.SWRST)
+    {
+        /* Sync wait */
+    }
+
+    /* Change QOS values to have the best performance and correct USB behaviour */
+    USB->DEVICE.QOSCTRL.bit.CQOS = 2;
+    USB->DEVICE.QOSCTRL.bit.DQOS = 2;
+
+    /* Load Pad Calibration */
+    pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRANSN_POS / 32))
+        >> (NVM_USB_PAD_TRANSN_POS % 32))
+        & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+    if (pad_transn == 0x1F)
+    {
+        pad_transn = 5;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
+
+    pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRANSP_POS / 32))
+            >> (NVM_USB_PAD_TRANSP_POS % 32))
+            & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+    if (pad_transp == 0x1F)
+    {
+        pad_transp = 29;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
+
+    pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRIM_POS / 32))
+            >> (NVM_USB_PAD_TRIM_POS % 32))
+            & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+    if (pad_trim == 0x7)
+    {
+        pad_trim = 3;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
+
+    /* Set the configuration */
+    hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
+    hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
+    hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
+    if (USB_SPEED_FULL == module_config->speed_mode)
+    {
+        module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+    } else if(USB_SPEED_LOW == module_config->speed_mode)
+    {
+        module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
+    }
+
+    memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
+            sizeof(usb_descriptor_table.usb_endpoint_table));
 
 #if !SAMD11
-	/* callback related init */
-	for (i = 0; i < USB_HOST_CALLBACK_N; i++) {
-		module_inst->host_callback[i] = NULL;
-	};
-	for (i = 0; i < USB_PIPE_NUM; i++) {
-		for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) {
-			module_inst->host_pipe_callback[i][j] = NULL;
-		}
-	};
-	module_inst->host_registered_callback_mask = 0;
-	module_inst->host_enabled_callback_mask = 0;
-	for (i = 0; i < USB_PIPE_NUM; i++) {
-		module_inst->host_pipe_registered_callback_mask[i] = 0;
-		module_inst->host_pipe_enabled_callback_mask[i] = 0;
-	}
+    /* callback related init */
+    for (i = 0; i < USB_HOST_CALLBACK_N; i++)
+    {
+        module_inst->host_callback[i] = NULL;
+    };
+    for (i = 0; i < USB_PIPE_NUM; i++)
+    {
+        for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++)
+        {
+            module_inst->host_pipe_callback[i][j] = NULL;
+        }
+    };
+    module_inst->host_registered_callback_mask = 0;
+    module_inst->host_enabled_callback_mask = 0;
+    for (i = 0; i < USB_PIPE_NUM; i++)
+    {
+        module_inst->host_pipe_registered_callback_mask[i] = 0;
+        module_inst->host_pipe_enabled_callback_mask[i] = 0;
+    }
 #endif
 
-	/*  device callback related */
-	for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
-		module_inst->device_callback[i] = NULL;
-	}
-	for (i = 0; i < USB_EPT_NUM; i++) {
-		for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
-			module_inst->device_endpoint_callback[i][j] = NULL;
-		}
-	}
-	module_inst->device_registered_callback_mask = 0;
-	module_inst->device_enabled_callback_mask = 0;
-	for (j = 0; j < USB_EPT_NUM; j++) {
-		module_inst->device_endpoint_registered_callback_mask[j] = 0;
-		module_inst->device_endpoint_enabled_callback_mask[j] = 0;
-	}
-
-	/* Enable interrupts for this USB module */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
-
-	return STATUS_OK;
+    /*  device callback related */
+    for (i = 0; i < USB_DEVICE_CALLBACK_N; i++)
+    {
+        module_inst->device_callback[i] = NULL;
+    }
+    for (i = 0; i < USB_EPT_NUM; i++)
+    {
+        for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++)
+        {
+            module_inst->device_endpoint_callback[i][j] = NULL;
+        }
+    }
+    module_inst->device_registered_callback_mask = 0;
+    module_inst->device_enabled_callback_mask = 0;
+    for (j = 0; j < USB_EPT_NUM; j++)
+    {
+        module_inst->device_endpoint_registered_callback_mask[j] = 0;
+        module_inst->device_endpoint_enabled_callback_mask[j] = 0;
+    }
+
+    /* Enable interrupts for this USB module */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
+
+    return STATUS_OK;
 }
 
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c
index ea612c47bcda..317b9cc7c2d7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/usb/usb_sam_l/usb.c
@@ -84,9 +84,9 @@
 COMPILER_PACK_SET(1)
 COMPILER_WORD_ALIGNED
 union {
-	UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
+    UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM];
 #if !SAML22
-	UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
+    UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM];
 #endif
 } usb_descriptor_table;
 COMPILER_PACK_RESET()
@@ -116,23 +116,23 @@ static struct usb_endpoint_callback_parameter ep_callback_para;
  * \internal USB Device IRQ Mask Bits Map
  */
 static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = {
-	USB_DEVICE_INTFLAG_SOF,
-	USB_DEVICE_INTFLAG_EORST,
-	USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
-	USB_DEVICE_INTFLAG_RAMACER,
-	USB_DEVICE_INTFLAG_SUSPEND,
-	USB_DEVICE_INTFLAG_LPMNYET,
-	USB_DEVICE_INTFLAG_LPMSUSP,
+    USB_DEVICE_INTFLAG_SOF,
+    USB_DEVICE_INTFLAG_EORST,
+    USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM,
+    USB_DEVICE_INTFLAG_RAMACER,
+    USB_DEVICE_INTFLAG_SUSPEND,
+    USB_DEVICE_INTFLAG_LPMNYET,
+    USB_DEVICE_INTFLAG_LPMSUSP,
 };
 
 /**
  * \internal USB Device IRQ Mask Bits Map
  */
 static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = {
-	USB_DEVICE_EPINTFLAG_TRCPT_Msk,
-	USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
-	USB_DEVICE_EPINTFLAG_RXSTP,
-	USB_DEVICE_EPINTFLAG_STALL_Msk
+    USB_DEVICE_EPINTFLAG_TRCPT_Msk,
+    USB_DEVICE_EPINTFLAG_TRFAIL_Msk,
+    USB_DEVICE_EPINTFLAG_RXSTP,
+    USB_DEVICE_EPINTFLAG_STALL_Msk
 };
 
 #if !SAML22
@@ -158,20 +158,20 @@ uint32_t host_pipe_job_busy_status = 0;
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_host_register_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type,
-		usb_host_callback_t callback_func)
+        enum usb_host_callback callback_type,
+        usb_host_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->host_callback[callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->host_callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->host_registered_callback_mask |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module_inst->host_registered_callback_mask |= (1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -187,18 +187,18 @@ enum status_code usb_host_register_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	/* Unregister callback function */
-	module_inst->host_callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->host_callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->host_registered_callback_mask &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->host_registered_callback_mask &= ~(1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -214,41 +214,49 @@ enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_host_enable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Enable callback */
-	module_inst->host_enabled_callback_mask |= (1 << callback_type);
-
-	if (callback_type == USB_HOST_CALLBACK_SOF) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RESET) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
-	}
-	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
-	}
-	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
-		module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Enable callback */
+    module_inst->host_enabled_callback_mask |= (1 << callback_type);
+
+    if (callback_type == USB_HOST_CALLBACK_SOF)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RESET)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST;
+    }
+    if (callback_type == USB_HOST_CALLBACK_WAKEUP)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DNRSM)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_UPRSM)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RAMACER)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER;
+    }
+    if (callback_type == USB_HOST_CALLBACK_CONNECT)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DISCONNECT)
+    {
+        module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -263,41 +271,49 @@ enum status_code usb_host_enable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_host_disable_callback(struct usb_module *module_inst,
-		enum usb_host_callback callback_type)
+        enum usb_host_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	/* Disable callback */
-	module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
-
-	if (callback_type == USB_HOST_CALLBACK_SOF) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RESET) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
-	}
-	if (callback_type == USB_HOST_CALLBACK_WAKEUP) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DNRSM) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_UPRSM) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
-	}
-	if (callback_type == USB_HOST_CALLBACK_RAMACER) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
-	}
-	if (callback_type == USB_HOST_CALLBACK_CONNECT) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
-	}
-	if (callback_type == USB_HOST_CALLBACK_DISCONNECT) {
-		module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    /* Disable callback */
+    module_inst->host_enabled_callback_mask &= ~(1 << callback_type);
+
+    if (callback_type == USB_HOST_CALLBACK_SOF)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RESET)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST;
+    }
+    if (callback_type == USB_HOST_CALLBACK_WAKEUP)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DNRSM)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_UPRSM)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM;
+    }
+    if (callback_type == USB_HOST_CALLBACK_RAMACER)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER;
+    }
+    if (callback_type == USB_HOST_CALLBACK_CONNECT)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN;
+    }
+    if (callback_type == USB_HOST_CALLBACK_DISCONNECT)
+    {
+        module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -319,14 +335,14 @@ enum status_code usb_host_disable_callback(struct usb_module *module_inst,
  */
 void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(ep_config);
-	/* Write default config to config struct */
-	ep_config->device_address = 0;
-	ep_config->endpoint_address = 0;
-	ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
-	ep_config->binterval = 0;
-	ep_config->size = 8;
+    /* Sanity check arguments */
+    Assert(ep_config);
+    /* Write default config to config struct */
+    ep_config->device_address = 0;
+    ep_config->endpoint_address = 0;
+    ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL;
+    ep_config->binterval = 0;
+    ep_config->size = 8;
 }
 
 /**
@@ -344,51 +360,54 @@ void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config)
  * \retval STATUS_OK    The host pipe was configured successfully.
  */
 enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config)
+        struct usb_host_pipe_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(ep_config);
-
-	/* set pipe config */
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
-	module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
-			ep_config->binterval;
-	if (ep_config->endpoint_address == 0) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_SETUP;
-	} else if (ep_config->endpoint_address & USB_EP_DIR_IN) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_IN;
-		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
-				USB_HOST_PSTATUSSET_BK0RDY;
-	} else {
-		module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-				USB_HOST_PIPE_TOKEN_OUT;
-		module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
-				USB_HOST_PSTATUSCLR_BK0RDY;
-	}
-
-	memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
-			sizeof(usb_descriptor_table.usb_pipe_table[0]));
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
-			ep_config->device_address;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
-			ep_config->endpoint_address & USB_EP_ADDR_MASK;
-	if (ep_config->size == 1023) {
-		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
-	} else {
-		usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
-				(32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
-	}
-
-	/* Clear busy status */
-	host_pipe_job_busy_status &= ~(1 << pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(ep_config);
+
+    /* set pipe config */
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type;
+    module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg =
+            ep_config->binterval;
+    if (ep_config->endpoint_address == 0)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_SETUP;
+    } else if (ep_config->endpoint_address & USB_EP_DIR_IN)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_IN;
+        module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg =
+                USB_HOST_PSTATUSSET_BK0RDY;
+    } else {
+        module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+                USB_HOST_PIPE_TOKEN_OUT;
+        module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg =
+                USB_HOST_PSTATUSCLR_BK0RDY;
+    }
+
+    memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0,
+            sizeof(usb_descriptor_table.usb_pipe_table[0]));
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR =
+            ep_config->device_address;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM =
+            ep_config->endpoint_address & USB_EP_ADDR_MASK;
+    if (ep_config->size == 1023)
+    {
+        usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07;
+    } else {
+        usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE =
+                (32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3);
+    }
+
+    /* Clear busy status */
+    host_pipe_job_busy_status &= ~(1 << pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -404,37 +423,39 @@ enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_
  * \retval STATUS_OK    The host pipe configuration was read successfully.
  */
 enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
-		struct usb_host_pipe_config *ep_config)
+        struct usb_host_pipe_config *ep_config)
 {
-	uint32_t size;
-
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(ep_config);
-	/* get pipe config from setting register */
-	ep_config->device_address =
-			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
-	ep_config->endpoint_address =
-			usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
-				USB_HOST_PIPE_TOKEN_IN) {
-		ep_config->endpoint_address |= USB_EP_DIR_IN;
-	}
-
-	ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
-	ep_config->binterval =
-			module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
-	size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
-	if (size == 0x07) {
-		ep_config->size = 1023;
-	} else {
-		ep_config->size = (8 << size);
-	}
-
-	return STATUS_OK;
+    uint32_t size;
+
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(ep_config);
+    /* get pipe config from setting register */
+    ep_config->device_address =
+            usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR;
+    ep_config->endpoint_address =
+            usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN ==
+                USB_HOST_PIPE_TOKEN_IN)
+                {
+        ep_config->endpoint_address |= USB_EP_DIR_IN;
+    }
+
+    ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE;
+    ep_config->binterval =
+            module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg;
+    size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE;
+    if (size == 0x07)
+    {
+        ep_config->size = 1023;
+    } else {
+        ep_config->size = (8 << size);
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -455,22 +476,22 @@ enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_host_pipe_register_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type,
-		usb_host_pipe_callback_t callback_func)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type,
+        usb_host_pipe_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(pipe_num < USB_PIPE_NUM);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(pipe_num < USB_PIPE_NUM);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
+    /* Set the bit corresponding to the callback_type */
+    module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -487,20 +508,20 @@ enum status_code usb_host_pipe_register_callback(
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_host_pipe_unregister_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(pipe_num < USB_PIPE_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(pipe_num < USB_PIPE_NUM);
 
-	/* Unregister callback function */
-	module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->host_pipe_callback[pipe_num][callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -517,32 +538,36 @@ enum status_code usb_host_pipe_unregister_callback(
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_host_pipe_enable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	/* Enable callback */
-	module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
-
-	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
-				USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    /* Enable callback */
+    module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type);
+
+    if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg =
+                USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_STALL)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -558,32 +583,36 @@ enum status_code usb_host_pipe_enable_callback(
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_host_pipe_disable_callback(
-		struct usb_module *module_inst, uint8_t pipe_num,
-		enum usb_host_pipe_callback callback_type)
+        struct usb_module *module_inst, uint8_t pipe_num,
+        enum usb_host_pipe_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	/* Enable callback */
-	module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
-
-	if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
-				USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
-	}
-	if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) {
-		module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    /* Enable callback */
+    module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type);
+
+    if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg =
+                USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP;
+    }
+    if (callback_type == USB_HOST_PIPE_CALLBACK_STALL)
+    {
+        module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -601,38 +630,40 @@ enum status_code usb_host_pipe_disable_callback(
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf)
+        uint8_t pipe_num, uint8_t *buf)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			8;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_SETUP;
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            8;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_SETUP;
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -652,39 +683,41 @@ enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			0;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			buf_size;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_IN;
-
-	/* Start transfer */
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            0;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            buf_size;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_IN;
+
+    /* Start transfer */
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -704,39 +737,41 @@ enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
-		uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
+        uint8_t pipe_num, uint8_t *buf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
-			buf_size;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
-			0;
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
-			USB_HOST_PIPE_TOKEN_OUT;
-
-	/* Start transfer */
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT =
+            buf_size;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE =
+            0;
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN =
+            USB_HOST_PIPE_TOKEN_OUT;
+
+    /* Start transfer */
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -753,22 +788,23 @@ enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
  */
 enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
 
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
 
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
 
-	/* Clear busy status */
-	host_pipe_job_busy_status &= ~(1 << pipe_num);
+    /* Clear busy status */
+    host_pipe_job_busy_status &= ~(1 << pipe_num);
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -787,39 +823,41 @@ enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t
  * \retval STATUS_ERR_NOT_INITIALIZED    The pipe has not been configured.
  */
 enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
-		uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
+        uint8_t pipe_num, bool b_remotewakeup, uint8_t hird)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(pipe_num < USB_PIPE_NUM);
-
-	if (host_pipe_job_busy_status & (1 << pipe_num)) {
-		return STATUS_BUSY;
-	}
-
-	/* Set busy status */
-	host_pipe_job_busy_status |= 1 << pipe_num;
-
-	if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
-			USB_HOST_PIPE_TYPE_DISABLE) {
-		return STATUS_ERR_NOT_INITIALIZED;
-	}
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
-				USB_HOST_PIPE_TYPE_EXTENDED;
-
-	/* get pipe config from setting register */
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
-			USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
-			USB_LPM_ATTRIBUT_HIRD(hird) |
-			USB_LPM_ATTRIBUT_BLINKSTATE_L1;
-
-	module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
-	usb_host_pipe_unfreeze(module_inst, pipe_num);
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(pipe_num < USB_PIPE_NUM);
+
+    if (host_pipe_job_busy_status & (1 << pipe_num))
+    {
+        return STATUS_BUSY;
+    }
+
+    /* Set busy status */
+    host_pipe_job_busy_status |= 1 << pipe_num;
+
+    if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE ==
+            USB_HOST_PIPE_TYPE_DISABLE)
+            {
+        return STATUS_ERR_NOT_INITIALIZED;
+    }
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE =
+                USB_HOST_PIPE_TYPE_EXTENDED;
+
+    /* get pipe config from setting register */
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE =
+            USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) |
+            USB_LPM_ATTRIBUT_HIRD(hird) |
+            USB_LPM_ATTRIBUT_BLINKSTATE_L1;
+
+    module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY;
+    usb_host_pipe_unfreeze(module_inst, pipe_num);
+
+    return STATUS_OK;
 }
 
 /**
@@ -834,191 +872,219 @@ enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
  */
 static void _usb_host_interrupt_handler(void)
 {
-	uint32_t pipe_int;
-	uint32_t flags;
-
-	/* Manage pipe interrupts */
-	pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
-	if (pipe_int < 32) {
-		/* pipe interrupts */
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
-
-		/* host pipe transfer complete interrupt */
-		if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TRCPT_Msk;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
-							USB_HOST_PIPE_TOKEN_IN) {
-					/* in  */
-					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-				} else {
-					/* out */
-					pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-					pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
-					if (0 == pipe_callback_para.transfered_size) {
-						pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
-					}
-				}
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-		/* host pipe transfer fail interrupt */
-		if (flags & USB_HOST_PINTFLAG_TRFAIL) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TRFAIL;
-		}
-
-		/* host pipe error interrupt */
-		if (flags & USB_HOST_PINTFLAG_PERR) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_PERR;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_ERROR)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				pipe_callback_para.pipe_error_status =
-						usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-		/* host pipe transmitted setup interrupt */
-		if (flags & USB_HOST_PINTFLAG_TXSTP) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_TXSTP;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_SETUP)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
-			}
-		}
-
-		/* host pipe stall interrupt */
-		if (flags & USB_HOST_PINTFLAG_STALL) {
-			/* Clear busy status */
-			host_pipe_job_busy_status &= ~(1 << pipe_int);
-			/* clear the flag */
-			_usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
-					USB_HOST_PINTFLAG_STALL;
-			if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
-					(1 << USB_HOST_PIPE_CALLBACK_STALL)) {
-				pipe_callback_para.pipe_num = pipe_int;
-				(_usb_instances->host_pipe_callback[pipe_int]
-						[USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
-			}
-		}
-
-	} else {
-		/* host interrupts */
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->HOST.INTFLAG.reg;
-
-		/* host SOF interrupt */
-		if (flags & USB_HOST_INTFLAG_HSOF) {
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
-			}
-		}
-
-		/* host reset interrupt */
-		if (flags & USB_HOST_INTFLAG_RST) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
-			}
-		}
-
-		/* host upstream resume interrupts */
-		if (flags & USB_HOST_INTFLAG_UPRSM) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
-			}
-		}
-
-		/* host downstream resume interrupts */
-		if (flags & USB_HOST_INTFLAG_DNRSM) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
-			}
-		}
-
-		/* host wakeup interrupts */
-		if (flags & USB_HOST_INTFLAG_WAKEUP) {
-			/* clear the flags */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
-			}
-		}
-
-		/* host ram access interrupt  */
-		if (flags & USB_HOST_INTFLAG_RAMACER) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
-			}
-		}
-
-		/* host connect interrupt */
-		if (flags & USB_HOST_INTFLAG_DCONN) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
-			}
-		}
-
-		/* host disconnect interrupt 	*/
-		if (flags & USB_HOST_INTFLAG_DDISC) {
-			/* Clear busy status */
-			host_pipe_job_busy_status = 0;
-			/* clear the flag */
-			_usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
-			if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) {
-				(_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
-			}
-		}
-
-	}
+    uint32_t pipe_int;
+    uint32_t flags;
+
+    /* Manage pipe interrupts */
+    pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg);
+    if (pipe_int < 32)
+    {
+        /* pipe interrupts */
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg;
+
+        /* host pipe transfer complete interrupt */
+        if (flags & USB_HOST_PINTFLAG_TRCPT_Msk)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TRCPT_Msk;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN ==
+                            USB_HOST_PIPE_TOKEN_IN)
+                            {
+                    /* in  */
+                    pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                    usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+                } else {
+                    /* out */
+                    pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                    pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+                    if (0 == pipe_callback_para.transfered_size)
+                    {
+                        pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT;
+                    }
+                }
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+        /* host pipe transfer fail interrupt */
+        if (flags & USB_HOST_PINTFLAG_TRFAIL)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TRFAIL;
+        }
+
+        /* host pipe error interrupt */
+        if (flags & USB_HOST_PINTFLAG_PERR)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_PERR;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_ERROR))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                pipe_callback_para.pipe_error_status =
+                        usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+        /* host pipe transmitted setup interrupt */
+        if (flags & USB_HOST_PINTFLAG_TXSTP)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_TXSTP;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_SETUP))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL);
+            }
+        }
+
+        /* host pipe stall interrupt */
+        if (flags & USB_HOST_PINTFLAG_STALL)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status &= ~(1 << pipe_int);
+            /* clear the flag */
+            _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg =
+                    USB_HOST_PINTFLAG_STALL;
+            if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] &
+                    (1 << USB_HOST_PIPE_CALLBACK_STALL))
+                    {
+                pipe_callback_para.pipe_num = pipe_int;
+                (_usb_instances->host_pipe_callback[pipe_int]
+                        [USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para);
+            }
+        }
+
+    } else {
+        /* host interrupts */
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->HOST.INTFLAG.reg;
+
+        /* host SOF interrupt */
+        if (flags & USB_HOST_INTFLAG_HSOF)
+        {
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances);
+            }
+        }
+
+        /* host reset interrupt */
+        if (flags & USB_HOST_INTFLAG_RST)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances);
+            }
+        }
+
+        /* host upstream resume interrupts */
+        if (flags & USB_HOST_INTFLAG_UPRSM)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances);
+            }
+        }
+
+        /* host downstream resume interrupts */
+        if (flags & USB_HOST_INTFLAG_DNRSM)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances);
+            }
+        }
+
+        /* host wakeup interrupts */
+        if (flags & USB_HOST_INTFLAG_WAKEUP)
+        {
+            /* clear the flags */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances);
+            }
+        }
+
+        /* host ram access interrupt  */
+        if (flags & USB_HOST_INTFLAG_RAMACER)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances);
+            }
+        }
+
+        /* host connect interrupt */
+        if (flags & USB_HOST_INTFLAG_DCONN)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances);
+            }
+        }
+
+        /* host disconnect interrupt    */
+        if (flags & USB_HOST_INTFLAG_DDISC)
+        {
+            /* Clear busy status */
+            host_pipe_job_busy_status = 0;
+            /* clear the flag */
+            _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC;
+            if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT))
+            {
+                (_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances);
+            }
+        }
+
+    }
 }
 
 /**
@@ -1031,9 +1097,9 @@ static void _usb_host_interrupt_handler(void)
  */
 void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value)
 {
-	Assert(module_inst);
+    Assert(module_inst);
 
-	usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
+    usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value;
 }
 #endif
 
@@ -1054,20 +1120,20 @@ void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_device_register_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type,
-		usb_device_callback_t callback_func)
+        enum usb_device_callback callback_type,
+        usb_device_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->device_callback[callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->device_callback[callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
+    /* Set the bit corresponding to the callback_type */
+    module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1083,18 +1149,18 @@ enum status_code usb_device_register_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
+    /* Sanity check arguments */
+    Assert(module_inst);
 
-	/* Unregister callback function */
-	module_inst->device_callback[callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->device_callback[callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1110,21 +1176,21 @@ enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_device_enable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* clear related flag */
-	module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
+    /* clear related flag */
+    module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type];
 
-	/* Enable callback */
-	module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
+    /* Enable callback */
+    module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type];
 
-	module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
+    module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1139,18 +1205,18 @@ enum status_code usb_device_enable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_device_disable_callback(struct usb_module *module_inst,
-		enum usb_device_callback callback_type)
+        enum usb_device_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* Disable callback */
-	module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
+    /* Disable callback */
+    module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type];
 
-	module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
+    module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1171,22 +1237,22 @@ enum status_code usb_device_disable_callback(struct usb_module *module_inst,
  * \retval STATUS_OK    The callback was registered successfully.
  */
 enum status_code usb_device_endpoint_register_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type,
-		usb_device_endpoint_callback_t callback_func)
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type,
+        usb_device_endpoint_callback_t callback_func)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_num < USB_EPT_NUM);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_num < USB_EPT_NUM);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
+    /* Register callback function */
+    module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func;
 
-	/* Set the bit corresponding to the callback_type */
-	module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+    /* Set the bit corresponding to the callback_type */
+    module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1203,20 +1269,20 @@ enum status_code usb_device_endpoint_register_callback(
  * \retval STATUS_OK    The callback was unregistered successfully.
  */
 enum status_code usb_device_endpoint_unregister_callback(
-		struct usb_module *module_inst, uint8_t ep_num,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep_num,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_num < USB_EPT_NUM);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_num < USB_EPT_NUM);
 
-	/* Unregister callback function */
-	module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
+    /* Unregister callback function */
+    module_inst->device_endpoint_callback[ep_num][callback_type] = NULL;
 
-	/* Clear the bit corresponding to the callback_type */
-	module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+    /* Clear the bit corresponding to the callback_type */
+    module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -1233,52 +1299,61 @@ enum status_code usb_device_endpoint_unregister_callback(
  * \retval STATUS_OK    The callback was enabled successfully.
  */
 enum status_code usb_device_endpoint_enable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	Assert(ep_num < USB_EPT_NUM);
-
-	/* Enable callback */
-	module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
-		if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    Assert(ep_num < USB_EPT_NUM);
+
+    /* Enable callback */
+    module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type];
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP;
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL)
+    {
+        if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1294,52 +1369,61 @@ enum status_code usb_device_endpoint_enable_callback(
  * \retval STATUS_OK    The callback was disabled successfully.
  */
 enum status_code usb_device_endpoint_disable_callback(
-		struct usb_module *module_inst, uint8_t ep,
-		enum usb_device_endpoint_callback callback_type)
+        struct usb_module *module_inst, uint8_t ep,
+        enum usb_device_endpoint_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	Assert(ep_num < USB_EPT_NUM);
-
-	/* Enable callback */
-	module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) {
-		if (ep_num == 0) { // control endpoint
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
-		} else if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
-		}
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
-	}
-
-	if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) {
-		if (ep & USB_EP_DIR_IN) {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
-		} else {
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
-		}
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    Assert(ep_num < USB_EPT_NUM);
+
+    /* Enable callback */
+    module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type];
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg =  USB_DEVICE_EPINTENCLR_TRCPT0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL)
+    {
+        if (ep_num == 0)
+        { /* control endpoint*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1;
+        } else if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0;
+        }
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP;
+    }
+
+    if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL)
+    {
+        if (ep & USB_EP_DIR_IN)
+        {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1;
+        } else {
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0;
+        }
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1360,14 +1444,14 @@ enum status_code usb_device_endpoint_disable_callback(
  */
 void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(ep_config);
-
-	/* Write default config to config struct */
-	ep_config->ep_address = 0;
-	ep_config->ep_size = USB_ENDPOINT_8_BYTE;
-	ep_config->auto_zlp = false;
-	ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
+    /* Sanity check arguments */
+    Assert(ep_config);
+
+    /* Write default config to config struct */
+    ep_config->ep_address = 0;
+    ep_config->ep_size = USB_ENDPOINT_8_BYTE;
+    ep_config->auto_zlp = false;
+    ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL;
 }
 
 /**
@@ -1385,107 +1469,120 @@ void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *
  * \retval STATUS_ERR_DENIED The endpoint address is already configured
  */
 enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
-		struct usb_device_endpoint_config *ep_config)
+        struct usb_device_endpoint_config *ep_config)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(ep_config);
-
-	uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
-	uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
-
-	switch (ep_config->ep_type) {
-		case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
-			return STATUS_OK;
-
-		case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
-			if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
-				(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-			} else {
-				return STATUS_ERR_DENIED;
-			}
-			if (true == ep_config->auto_zlp) {
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-			} else {
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-				usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-			}
-			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
-			usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
-			return STATUS_OK;
-
-		case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		case USB_DEVICE_ENDPOINT_TYPE_BULK:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
-			if (ep_bank) {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			} else {
-				if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
-					module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-				} else {
-					return STATUS_ERR_DENIED;
-				}
-			}
-			break;
-
-		default:
-			break;
-	}
-
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
-
-	if (true == ep_config->auto_zlp) {
-		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
-		} else {
-		usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(ep_config);
+
+    uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK;
+    uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0;
+
+    switch (ep_config->ep_type)
+    {
+        case USB_DEVICE_ENDPOINT_TYPE_DISABLE:
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) |  USB_DEVICE_EPCFG_EPTYPE1(0);
+            return STATUS_OK;
+
+        case USB_DEVICE_ENDPOINT_TYPE_CONTROL:
+            if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \
+                (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1);
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+            } else {
+                return STATUS_ERR_DENIED;
+            }
+            if (true == ep_config->auto_zlp)
+            {
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+            } else {
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+                usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+            }
+            usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size;
+            usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size;
+            return STATUS_OK;
+
+        case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        case USB_DEVICE_ENDPOINT_TYPE_BULK:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT:
+            if (ep_bank)
+            {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            } else {
+                if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0)
+                {
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4);
+                    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+                } else {
+                    return STATUS_ERR_DENIED;
+                }
+            }
+            break;
+
+        default:
+            break;
+    }
+
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size;
+
+    if (true == ep_config->auto_zlp)
+    {
+        usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP;
+        } else {
+        usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP;
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -1498,15 +1595,16 @@ enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
  */
 bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-	uint8_t flag;
-
-	if (ep & USB_EP_DIR_IN) {
-		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
-	} else {
-		flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
-	}
-	return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+    uint8_t flag;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+    } else {
+        flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+    }
+    return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE);
 }
 
 
@@ -1518,19 +1616,20 @@ bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t e
  */
 void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num;
-	ep_num = ep & USB_EP_ADDR_MASK;
-
-	// Stop transfer
-	if (ep & USB_EP_DIR_IN) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
-		// Eventually ack a transfer occur during abort
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-	} else {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
-		// Eventually ack a transfer occur during abort
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-	}
+    uint8_t ep_num;
+    ep_num = ep & USB_EP_ADDR_MASK;
+
+    /* Stop transfer*/
+    if (ep & USB_EP_DIR_IN)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY;
+        /* Eventually ack a transfer occur during abort*/
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+    } else {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY;
+        /* Eventually ack a transfer occur during abort*/
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+    }
 }
 
 /**
@@ -1543,13 +1642,14 @@ void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep)
  */
 bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	if (ep & USB_EP_DIR_IN) {
-		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
-	} else {
-		return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1);
+    } else {
+        return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0);
+    }
 }
 
 /**
@@ -1560,14 +1660,15 @@ bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep)
  */
 void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	// Stall endpoint
-	if (ep & USB_EP_DIR_IN) {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
-	} else {
-		module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    /* Stall endpoint*/
+    if (ep & USB_EP_DIR_IN)
+    {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1;
+    } else {
+        module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0;
+    }
 }
 
 /**
@@ -1578,29 +1679,34 @@ void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep)
  */
 void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
 {
-	uint8_t ep_num = ep & USB_EP_ADDR_MASK;
-
-	if (ep & USB_EP_DIR_IN) {
-		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) {
-			// Remove stall request
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
-			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
-				// The Stall has occurred, then reset data toggle
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
-			}
-		}
-	} else {
-		if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) {
-			// Remove stall request
-			module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
-			if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
-				// The Stall has occurred, then reset data toggle
-				module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
-			}
-		}
-	}
+    uint8_t ep_num = ep & USB_EP_ADDR_MASK;
+
+    if (ep & USB_EP_DIR_IN)
+    {
+        if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1)
+        {
+            /* Remove stall request*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1;
+            if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+            {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+                /* The Stall has occurred, then reset data toggle*/
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN;
+            }
+        }
+    } else {
+        if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0)
+        {
+            /* Remove stall request*/
+            module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0;
+            if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+            {
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+                /* The Stall has occurred, then reset data toggle*/
+                module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT;
+            }
+        }
+    }
 }
 
 /**
@@ -1616,26 +1722,27 @@ void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep)
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size)
+        uint8_t* pbuf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(ep_num < USB_EPT_NUM);
-
-	uint8_t flag;
-	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
-	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
-		return STATUS_ERR_DENIED;
-	};
-
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
-	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(ep_num < USB_EPT_NUM);
+
+    uint8_t flag;
+    flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1);
+    if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE)
+    {
+        return STATUS_ERR_DENIED;
+    };
+
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size;
+    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY;
+
+    return STATUS_OK;
 }
 
 /**
@@ -1651,26 +1758,27 @@ enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
-		uint8_t* pbuf, uint32_t buf_size)
+        uint8_t* pbuf, uint32_t buf_size)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
-	Assert(ep_num < USB_EPT_NUM);
-
-	uint8_t flag;
-	flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
-	if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) {
-		return STATUS_ERR_DENIED;
-	};
-
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
-	usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-	module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
+    Assert(ep_num < USB_EPT_NUM);
+
+    uint8_t flag;
+    flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0);
+    if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE)
+    {
+        return STATUS_ERR_DENIED;
+    };
+
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size;
+    usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+    module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+
+    return STATUS_OK;
 }
 
 /**
@@ -1684,138 +1792,163 @@ enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_i
  * \retval STATUS_ERR_DENIED Endpoint is not ready
  */
 enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
-		uint8_t* pbuf)
+        uint8_t* pbuf)
 {
-	/* Sanity check arguments */
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    /* Sanity check arguments */
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	/* get endpoint configuration from setting register */
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
-	usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
-	module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
+    /* get endpoint configuration from setting register */
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf;
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8;
+    usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0;
+    module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY;
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 static void _usb_device_interrupt_handler(void)
 {
-	uint16_t ep_inst;
-	uint16_t flags, flags_run;
-	ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
-
-	/* device interrupt */
-	if (0 == ep_inst) {
-		int i;
-
-		/* get interrupt flags */
-		flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
-		flags_run = flags &
-				_usb_instances->device_enabled_callback_mask &
-				_usb_instances->device_registered_callback_mask;
-
-		for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) {
-			if (flags & _usb_device_irq_bits[i]) {
-				_usb_instances->hw->DEVICE.INTFLAG.reg =
-						_usb_device_irq_bits[i];
-			}
-			if (flags_run & _usb_device_irq_bits[i]) {
-				if (i == USB_DEVICE_CALLBACK_LPMSUSP) {
-					device_callback_lpm_wakeup_enable =
-							usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
-							& USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
-				}
-				(_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
-			}
-		}
-
-	} else {
-		/* endpoint interrupt */
-
-		for (uint8_t i = 0; i < USB_EPT_NUM; i++) {
-
-			if (ep_inst & (1 << i)) {
-				flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
-				flags_run = flags &
-						_usb_instances->device_endpoint_enabled_callback_mask[i] &
-						_usb_instances->device_endpoint_registered_callback_mask[i];
-
-				// endpoint transfer stall interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-					}
-
-					if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint received setup interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_RXSTP) {
-					_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
-					if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) {
-						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint transfer complete interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-						ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
-
-					} else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-						ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
-						ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
-					}
-					if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-
-				// endpoint transfer fail interrupt
-				if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
-					if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
-						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
-							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
-						}
-						ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
-						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) {
-							return;
-						}
-					} else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) {
-						_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
-						if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) {
-							usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
-						}
-						ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
-						if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) {
-							return;
-						}
-					}
-
-					if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) {
-						(_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
-					}
-					return;
-				}
-			}
-		}
-	}
+    uint16_t ep_inst;
+    uint16_t flags, flags_run;
+    ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg;
+
+    /* device interrupt */
+    if (0 == ep_inst)
+    {
+        int i;
+
+        /* get interrupt flags */
+        flags = _usb_instances->hw->DEVICE.INTFLAG.reg;
+        flags_run = flags &
+                _usb_instances->device_enabled_callback_mask &
+                _usb_instances->device_registered_callback_mask;
+
+        for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++)
+        {
+            if (flags & _usb_device_irq_bits[i])
+            {
+                _usb_instances->hw->DEVICE.INTFLAG.reg =
+                        _usb_device_irq_bits[i];
+            }
+            if (flags_run & _usb_device_irq_bits[i])
+            {
+                if (i == USB_DEVICE_CALLBACK_LPMSUSP)
+                {
+                    device_callback_lpm_wakeup_enable =
+                            usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE
+                            & USB_LPM_ATTRIBUT_REMOTEWAKE_MASK;
+                }
+                (_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable);
+            }
+        }
+
+    } else {
+        /* endpoint interrupt */
+
+        for (uint8_t i = 0; i < USB_EPT_NUM; i++)
+        {
+
+            if (ep_inst & (1 << i))
+            {
+                flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg;
+                flags_run = flags &
+                        _usb_instances->device_endpoint_enabled_callback_mask[i] &
+                        _usb_instances->device_endpoint_registered_callback_mask[i];
+
+                /* endpoint transfer stall interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                    } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                    }
+
+                    if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint received setup interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_RXSTP)
+                {
+                    _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP;
+                    if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])
+                    {
+                        ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint transfer complete interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                        ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT);
+
+                    } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0;
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                        ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT);
+                        ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE);
+                    }
+                    if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+
+                /* endpoint transfer fail interrupt*/
+                if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk)
+                {
+                    if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1;
+                        if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+                        {
+                            usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+                        }
+                        ep_callback_para.endpoint_address = USB_EP_DIR_IN | i;
+                        if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1)
+                        {
+                            return;
+                        }
+                    } else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0)
+                    {
+                        _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0;
+                        if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW)
+                        {
+                            usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW;
+                        }
+                        ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i;
+                        if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0)
+                        {
+                            return;
+                        }
+                    }
+
+                    if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk)
+                    {
+                        (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para);
+                    }
+                    return;
+                }
+            }
+        }
+    }
 }
 
 /**
@@ -1825,11 +1958,11 @@ static void _usb_device_interrupt_handler(void)
  */
 void usb_enable(struct usb_module *module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
-	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+    module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE;
+    while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
 }
 
 /**
@@ -1839,13 +1972,13 @@ void usb_enable(struct usb_module *module_inst)
  */
 void usb_disable(struct usb_module *module_inst)
 {
-	Assert(module_inst);
-	Assert(module_inst->hw);
+    Assert(module_inst);
+    Assert(module_inst->hw);
 
-	module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
-	module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
-	module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
-	while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
+    module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK;
+    module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK;
+    module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE;
+    while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE);
 }
 
 /**
@@ -1853,15 +1986,16 @@ void usb_disable(struct usb_module *module_inst)
  */
 void USB_Handler(void)
 {
-	if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) {
+    if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE)
+    {
 #if !SAML22
-		/*host mode ISR */
-		_usb_host_interrupt_handler();
+        /*host mode ISR */
+        _usb_host_interrupt_handler();
 #endif
-	} else {
-		/*device mode ISR */
-		_usb_device_interrupt_handler();
-	}
+    } else {
+        /*device mode ISR */
+        _usb_device_interrupt_handler();
+    }
 }
 
 /**
@@ -1871,15 +2005,15 @@ void USB_Handler(void)
  */
 void usb_get_config_defaults(struct usb_config *module_config)
 {
-	Assert(module_config);
-
-	/* Sanity check arguments */
-	Assert(module_config);
-	/* Write default configuration to config struct */
-	module_config->select_host_mode = 0;
-	module_config->run_in_standby = 1;
-	module_config->source_generator = GCLK_GENERATOR_3;
-	module_config->speed_mode = USB_SPEED_FULL;
+    Assert(module_config);
+
+    /* Sanity check arguments */
+    Assert(module_config);
+    /* Write default configuration to config struct */
+    module_config->select_host_mode = 0;
+    module_config->run_in_standby = 1;
+    module_config->source_generator = GCLK_GENERATOR_3;
+    module_config->speed_mode = USB_SPEED_FULL;
 }
 
 #define NVM_USB_PAD_TRANSN_POS  45
@@ -1904,134 +2038,148 @@ void usb_get_config_defaults(struct usb_config *module_config)
  * \retval STATUS_OK           The module was initialized successfully
  */
 enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
-		struct usb_config *module_config)
+        struct usb_config *module_config)
 {
-	/* Sanity check arguments */
-	Assert(hw);
-	Assert(module_inst);
-	Assert(module_config);
+    /* Sanity check arguments */
+    Assert(hw);
+    Assert(module_inst);
+    Assert(module_config);
 
-	uint32_t i,j;
-	uint32_t pad_transn, pad_transp, pad_trim;
-	struct system_pinmux_config pin_config;
-	struct system_gclk_chan_config gclk_chan_config;
+    uint32_t i,j;
+    uint32_t pad_transn, pad_transp, pad_trim;
+    struct system_pinmux_config pin_config;
+    struct system_gclk_chan_config gclk_chan_config;
 
 #if !SAML22
-	host_pipe_job_busy_status = 0;
+    host_pipe_job_busy_status = 0;
 #endif
 
-	_usb_instances = module_inst;
-
-	/* Associate the software module instance with the hardware module */
-	module_inst->hw = hw;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_USB);
-
-	/* Set up the USB DP/DN pins */
-	system_pinmux_get_config_defaults(&pin_config);
-	pin_config.mux_position = MUX_PA24G_USB_DM;
-	system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
-	pin_config.mux_position = MUX_PA25G_USB_DP;
-	system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
-
-	/* Setup clock for module */
-	system_gclk_chan_get_config_defaults(&gclk_chan_config);
-	gclk_chan_config.source_generator = module_config->source_generator;
-	system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
-	system_gclk_chan_enable(USB_GCLK_ID);
-
-	/* Reset */
-	hw->DEVICE.CTRLA.bit.SWRST = 1;
-	while (hw->DEVICE.SYNCBUSY.bit.SWRST) {
-		/* Sync wait */
-	}
-
-	/* Load Pad Calibration */
-	pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRANSN_POS / 32))
-		>> (NVM_USB_PAD_TRANSN_POS % 32))
-		& ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
-
-	if (pad_transn == 0x1F) {
-		pad_transn = 5;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
-
-	pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRANSP_POS / 32))
-			>> (NVM_USB_PAD_TRANSP_POS % 32))
-			& ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
-
-	if (pad_transp == 0x1F) {
-		pad_transp = 29;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
-
-	pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
-			+ (NVM_USB_PAD_TRIM_POS / 32))
-			>> (NVM_USB_PAD_TRIM_POS % 32))
-			& ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
-
-	if (pad_trim == 0x7) {
-		pad_trim = 3;
-	}
-
-	hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
-
-	/* Set the configuration */
-	hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
-	hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
-	hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
-	if (USB_SPEED_FULL == module_config->speed_mode) {
-		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
-	} else if(USB_SPEED_LOW == module_config->speed_mode) {
-		module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
-	}
-
-	memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
-			sizeof(usb_descriptor_table.usb_endpoint_table));
+    _usb_instances = module_inst;
+
+    /* Associate the software module instance with the hardware module */
+    module_inst->hw = hw;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_USB);
+
+    /* Set up the USB DP/DN pins */
+    system_pinmux_get_config_defaults(&pin_config);
+    pin_config.mux_position = MUX_PA24G_USB_DM;
+    system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config);
+    pin_config.mux_position = MUX_PA25G_USB_DP;
+    system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config);
+
+    /* Setup clock for module */
+    system_gclk_chan_get_config_defaults(&gclk_chan_config);
+    gclk_chan_config.source_generator = module_config->source_generator;
+    system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config);
+    system_gclk_chan_enable(USB_GCLK_ID);
+
+    /* Reset */
+    hw->DEVICE.CTRLA.bit.SWRST = 1;
+    while (hw->DEVICE.SYNCBUSY.bit.SWRST)
+    {
+        /* Sync wait */
+    }
+
+    /* Load Pad Calibration */
+    pad_transn =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRANSN_POS / 32))
+        >> (NVM_USB_PAD_TRANSN_POS % 32))
+        & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1);
+
+    if (pad_transn == 0x1F)
+    {
+        pad_transn = 5;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRANSN = pad_transn;
+
+    pad_transp =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRANSP_POS / 32))
+            >> (NVM_USB_PAD_TRANSP_POS % 32))
+            & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1);
+
+    if (pad_transp == 0x1F)
+    {
+        pad_transp = 29;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRANSP = pad_transp;
+
+    pad_trim =( *((uint32_t *)(NVMCTRL_OTP4)
+            + (NVM_USB_PAD_TRIM_POS / 32))
+            >> (NVM_USB_PAD_TRIM_POS % 32))
+            & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1);
+
+    if (pad_trim == 0x7)
+    {
+        pad_trim = 3;
+    }
+
+    hw->DEVICE.PADCAL.bit.TRIM = pad_trim;
+
+    /* Set the configuration */
+    hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode;
+    hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby;
+    hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]);
+    if (USB_SPEED_FULL == module_config->speed_mode)
+    {
+        module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val;
+    } else if(USB_SPEED_LOW == module_config->speed_mode)
+    {
+        module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val;
+    }
+
+    memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0,
+            sizeof(usb_descriptor_table.usb_endpoint_table));
 
 #if !SAML22
-	/* callback related init */
-	for (i = 0; i < USB_HOST_CALLBACK_N; i++) {
-		module_inst->host_callback[i] = NULL;
-	};
-	for (i = 0; i < USB_PIPE_NUM; i++) {
-		for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) {
-			module_inst->host_pipe_callback[i][j] = NULL;
-		}
-	};
-	module_inst->host_registered_callback_mask = 0;
-	module_inst->host_enabled_callback_mask = 0;
-	for (i = 0; i < USB_PIPE_NUM; i++) {
-		module_inst->host_pipe_registered_callback_mask[i] = 0;
-		module_inst->host_pipe_enabled_callback_mask[i] = 0;
-	}
+    /* callback related init */
+    for (i = 0; i < USB_HOST_CALLBACK_N; i++)
+    {
+        module_inst->host_callback[i] = NULL;
+    };
+    for (i = 0; i < USB_PIPE_NUM; i++)
+    {
+        for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++)
+        {
+            module_inst->host_pipe_callback[i][j] = NULL;
+        }
+    };
+    module_inst->host_registered_callback_mask = 0;
+    module_inst->host_enabled_callback_mask = 0;
+    for (i = 0; i < USB_PIPE_NUM; i++)
+    {
+        module_inst->host_pipe_registered_callback_mask[i] = 0;
+        module_inst->host_pipe_enabled_callback_mask[i] = 0;
+    }
 #endif
 
-	/*  device callback related */
-	for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) {
-		module_inst->device_callback[i] = NULL;
-	}
-	for (i = 0; i < USB_EPT_NUM; i++) {
-		for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) {
-			module_inst->device_endpoint_callback[i][j] = NULL;
-		}
-	}
-	module_inst->device_registered_callback_mask = 0;
-	module_inst->device_enabled_callback_mask = 0;
-	for (j = 0; j < USB_EPT_NUM; j++) {
-		module_inst->device_endpoint_registered_callback_mask[j] = 0;
-		module_inst->device_endpoint_enabled_callback_mask[j] = 0;
-	}
-
-	/* Enable interrupts for this USB module */
-	system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
-
-	return STATUS_OK;
+    /*  device callback related */
+    for (i = 0; i < USB_DEVICE_CALLBACK_N; i++)
+    {
+        module_inst->device_callback[i] = NULL;
+    }
+    for (i = 0; i < USB_EPT_NUM; i++)
+    {
+        for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++)
+        {
+            module_inst->device_endpoint_callback[i][j] = NULL;
+        }
+    }
+    module_inst->device_registered_callback_mask = 0;
+    module_inst->device_enabled_callback_mask = 0;
+    for (j = 0; j < USB_EPT_NUM; j++)
+    {
+        module_inst->device_endpoint_registered_callback_mask[j] = 0;
+        module_inst->device_endpoint_enabled_callback_mask[j] = 0;
+    }
+
+    /* Enable interrupts for this USB module */
+    system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB);
+
+    return STATUS_OK;
 }
 
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c
index d6a0b115b4a6..be35601f2282 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.c
@@ -62,184 +62,206 @@
  */
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
 enum status_code wdt_set_config(
-		const struct wdt_conf *const config)
+        const struct wdt_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	Wdt *const WDT_module = WDT;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_WDT);
-
-	/* Check of the Watchdog has been locked to be always on, if so, abort */
-	if (wdt_is_locked()) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Check for an invalid timeout period, abort if found */
-	if (config->timeout_period == WDT_PERIOD_NONE) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Make sure the Window and Early Warning periods are not more than the
-	 * reset period, abort if either is invalid */
-	if ((config->timeout_period < config->window_period) ||
-			(config->timeout_period < config->early_warning_period)) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Disable the Watchdog module */
-	WDT_module->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	if(config->enable == false) {
-		return STATUS_OK;
-	}
-
-	uint32_t new_config = 0;
-
-	/* Update the timeout period value with the requested period */
-	new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
-
-	/* Check if the user has requested a reset window period */
-	if (config->window_period != WDT_PERIOD_NONE) {
-		WDT_module->CTRLA.reg |= WDT_CTRLA_WEN;
-
-		/* Update and enable the timeout period value */
-		new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
-	} else {
-		/* Ensure the window enable control flag is cleared */
-		WDT_module->CTRLA.reg &= ~WDT_CTRLA_WEN;
-	}
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	/* Write the new Watchdog configuration */
-	WDT_module->CONFIG.reg = new_config;
-
-	/* Check if the user has requested an early warning period */
-	if (config->early_warning_period != WDT_PERIOD_NONE) {
-		/* Set the Early Warning period */
-		WDT_module->EWCTRL.reg
-			= (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
-	}
-
-	/* Either enable or lock-enable the Watchdog timer depending on the user
-	 * settings */
-	if (config->always_on) {
-		WDT_module->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
-	} else {
-		WDT_module->CTRLA.reg |= WDT_CTRLA_ENABLE;
-	}
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(config);
+
+    Wdt *const WDT_module = WDT;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_WDT);
+
+    /* Check of the Watchdog has been locked to be always on, if so, abort */
+    if (wdt_is_locked())
+    {
+        return STATUS_ERR_IO;
+    }
+
+    /* Check for an invalid timeout period, abort if found */
+    if (config->timeout_period == WDT_PERIOD_NONE)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Make sure the Window and Early Warning periods are not more than the
+     * reset period, abort if either is invalid */
+    if ((config->timeout_period < config->window_period) ||
+            (config->timeout_period < config->early_warning_period))
+            {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Disable the Watchdog module */
+    WDT_module->CTRLA.reg &= ~WDT_CTRLA_ENABLE;
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    if(config->enable == false)
+    {
+        return STATUS_OK;
+    }
+
+    uint32_t new_config = 0;
+
+    /* Update the timeout period value with the requested period */
+    new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
+
+    /* Check if the user has requested a reset window period */
+    if (config->window_period != WDT_PERIOD_NONE)
+    {
+        WDT_module->CTRLA.reg |= WDT_CTRLA_WEN;
+
+        /* Update and enable the timeout period value */
+        new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
+    } else {
+        /* Ensure the window enable control flag is cleared */
+        WDT_module->CTRLA.reg &= ~WDT_CTRLA_WEN;
+    }
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    /* Write the new Watchdog configuration */
+    WDT_module->CONFIG.reg = new_config;
+
+    /* Check if the user has requested an early warning period */
+    if (config->early_warning_period != WDT_PERIOD_NONE)
+    {
+        /* Set the Early Warning period */
+        WDT_module->EWCTRL.reg
+            = (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
+    }
+
+    /* Either enable or lock-enable the Watchdog timer depending on the user
+     * settings */
+    if (config->always_on)
+    {
+        WDT_module->CTRLA.reg |= WDT_CTRLA_ALWAYSON;
+    } else {
+        WDT_module->CTRLA.reg |= WDT_CTRLA_ENABLE;
+    }
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    return STATUS_OK;
 }
 #else
 enum status_code wdt_set_config(
-		const struct wdt_conf *const config)
+        const struct wdt_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
-
-	Wdt *const WDT_module = WDT;
-
-	/* Turn on the digital interface clock */
-	system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_WDT);
-
-	/* Check of the Watchdog has been locked to be always on, if so, abort */
-	if (wdt_is_locked()) {
-		return STATUS_ERR_IO;
-	}
-
-	/* Check for an invalid timeout period, abort if found */
-	if (config->timeout_period == WDT_PERIOD_NONE) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Make sure the Window and Early Warning periods are not more than the
-	 * reset period, abort if either is invalid */
-	if ((config->timeout_period < config->window_period) ||
-			(config->timeout_period < config->early_warning_period)) {
-		return STATUS_ERR_INVALID_ARG;
-	}
-
-	/* Disable the Watchdog module */
-	WDT_module->CTRL.reg &= ~WDT_CTRL_ENABLE;
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	if(config->enable == false) {
-		return STATUS_OK;
-	}
-
-	/* Configure GCLK channel and enable clock */
-	struct system_gclk_chan_config gclk_chan_conf;
-	gclk_chan_conf.source_generator = config->clock_source;
-	system_gclk_chan_set_config(WDT_GCLK_ID, &gclk_chan_conf);
-	system_gclk_chan_enable(WDT_GCLK_ID);
-	if (config->always_on) {
-		system_gclk_chan_lock(WDT_GCLK_ID);
-	}
-
-	uint32_t new_config = 0;
-
-	/* Update the timeout period value with the requested period */
-	new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
-
-	/* Check if the user has requested a reset window period */
-	if (config->window_period != WDT_PERIOD_NONE) {
-		WDT_module->CTRL.reg |= WDT_CTRL_WEN;
-
-		/* Update and enable the timeout period value */
-		new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
-	} else {
-		/* Ensure the window enable control flag is cleared */
-		WDT_module->CTRL.reg &= ~WDT_CTRL_WEN;
-	}
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	/* Write the new Watchdog configuration */
-	WDT_module->CONFIG.reg = new_config;
-
-	/* Check if the user has requested an early warning period */
-	if (config->early_warning_period != WDT_PERIOD_NONE) {
-		while (wdt_is_syncing()) {
-			/* Wait for all hardware modules to complete synchronization */
-		}
-
-		/* Set the Early Warning period */
-		WDT_module->EWCTRL.reg
-			= (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
-	}
-
-	/* Either enable or lock-enable the Watchdog timer depending on the user
-	 * settings */
-	if (config->always_on) {
-		WDT_module->CTRL.reg |= WDT_CTRL_ALWAYSON;
-	} else {
-		WDT_module->CTRL.reg |= WDT_CTRL_ENABLE;
-	}
-
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
-
-	return STATUS_OK;
+    /* Sanity check arguments */
+    Assert(config);
+
+    Wdt *const WDT_module = WDT;
+
+    /* Turn on the digital interface clock */
+    system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_WDT);
+
+    /* Check of the Watchdog has been locked to be always on, if so, abort */
+    if (wdt_is_locked())
+    {
+        return STATUS_ERR_IO;
+    }
+
+    /* Check for an invalid timeout period, abort if found */
+    if (config->timeout_period == WDT_PERIOD_NONE)
+    {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Make sure the Window and Early Warning periods are not more than the
+     * reset period, abort if either is invalid */
+    if ((config->timeout_period < config->window_period) ||
+            (config->timeout_period < config->early_warning_period))
+            {
+        return STATUS_ERR_INVALID_ARG;
+    }
+
+    /* Disable the Watchdog module */
+    WDT_module->CTRL.reg &= ~WDT_CTRL_ENABLE;
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    if(config->enable == false)
+    {
+        return STATUS_OK;
+    }
+
+    /* Configure GCLK channel and enable clock */
+    struct system_gclk_chan_config gclk_chan_conf;
+    gclk_chan_conf.source_generator = config->clock_source;
+    system_gclk_chan_set_config(WDT_GCLK_ID, &gclk_chan_conf);
+    system_gclk_chan_enable(WDT_GCLK_ID);
+    if (config->always_on)
+    {
+        system_gclk_chan_lock(WDT_GCLK_ID);
+    }
+
+    uint32_t new_config = 0;
+
+    /* Update the timeout period value with the requested period */
+    new_config |= (config->timeout_period - 1) << WDT_CONFIG_PER_Pos;
+
+    /* Check if the user has requested a reset window period */
+    if (config->window_period != WDT_PERIOD_NONE)
+    {
+        WDT_module->CTRL.reg |= WDT_CTRL_WEN;
+
+        /* Update and enable the timeout period value */
+        new_config |= (config->window_period - 1) << WDT_CONFIG_WINDOW_Pos;
+    } else {
+        /* Ensure the window enable control flag is cleared */
+        WDT_module->CTRL.reg &= ~WDT_CTRL_WEN;
+    }
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    /* Write the new Watchdog configuration */
+    WDT_module->CONFIG.reg = new_config;
+
+    /* Check if the user has requested an early warning period */
+    if (config->early_warning_period != WDT_PERIOD_NONE)
+    {
+        while (wdt_is_syncing())
+        {
+            /* Wait for all hardware modules to complete synchronization */
+        }
+
+        /* Set the Early Warning period */
+        WDT_module->EWCTRL.reg
+            = (config->early_warning_period - 1) << WDT_EWCTRL_EWOFFSET_Pos;
+    }
+
+    /* Either enable or lock-enable the Watchdog timer depending on the user
+     * settings */
+    if (config->always_on)
+    {
+        WDT_module->CTRL.reg |= WDT_CTRL_ALWAYSON;
+    } else {
+        WDT_module->CTRL.reg |= WDT_CTRL_ENABLE;
+    }
+
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
+
+    return STATUS_OK;
 }
 #endif
 
@@ -253,12 +275,13 @@ enum status_code wdt_set_config(
  */
 void wdt_reset_count(void)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
-	/* Disable the Watchdog module */
-	WDT_module->CLEAR.reg = WDT_CLEAR_CLEAR_KEY;
+    /* Disable the Watchdog module */
+    WDT_module->CLEAR.reg = WDT_CLEAR_CLEAR_KEY;
 
-	while (wdt_is_syncing()) {
-		/* Wait for all hardware modules to complete synchronization */
-	}
+    while (wdt_is_syncing())
+    {
+        /* Wait for all hardware modules to complete synchronization */
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h
index 0109e9def61b..27c825e2b8ae 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt.h
@@ -211,34 +211,34 @@ extern "C" {
  * values requiring a period as a number of Watchdog timer clock ticks.
  */
 enum wdt_period {
-	/** No Watchdog period. This value can only be used when setting the
-	 *  Window and Early Warning periods; its use as the Watchdog Reset
-	 *  Period is invalid. */
-	WDT_PERIOD_NONE     = 0,
-	/** Watchdog period of 8 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_8CLK     = 1,
-	/** Watchdog period of 16 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_16CLK    = 2,
-	/** Watchdog period of 32 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_32CLK    = 3,
-	/** Watchdog period of 64 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_64CLK    = 4,
-	/** Watchdog period of 128 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_128CLK   = 5,
-	/** Watchdog period of 256 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_256CLK   = 6,
-	/** Watchdog period of 512 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_512CLK   = 7,
-	/** Watchdog period of 1024 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_1024CLK  = 8,
-	/** Watchdog period of 2048 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_2048CLK  = 9,
-	/** Watchdog period of 4096 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_4096CLK  = 10,
-	/** Watchdog period of 8192 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_8192CLK  = 11,
-	/** Watchdog period of 16384 clocks of the Watchdog Timer Generic Clock */
-	WDT_PERIOD_16384CLK = 12,
+    /** No Watchdog period. This value can only be used when setting the
+     *  Window and Early Warning periods; its use as the Watchdog Reset
+     *  Period is invalid. */
+    WDT_PERIOD_NONE     = 0,
+    /** Watchdog period of 8 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_8CLK     = 1,
+    /** Watchdog period of 16 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_16CLK    = 2,
+    /** Watchdog period of 32 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_32CLK    = 3,
+    /** Watchdog period of 64 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_64CLK    = 4,
+    /** Watchdog period of 128 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_128CLK   = 5,
+    /** Watchdog period of 256 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_256CLK   = 6,
+    /** Watchdog period of 512 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_512CLK   = 7,
+    /** Watchdog period of 1024 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_1024CLK  = 8,
+    /** Watchdog period of 2048 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_2048CLK  = 9,
+    /** Watchdog period of 4096 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_4096CLK  = 10,
+    /** Watchdog period of 8192 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_8192CLK  = 11,
+    /** Watchdog period of 16384 clocks of the Watchdog Timer Generic Clock */
+    WDT_PERIOD_16384CLK = 12,
 };
 
 /**
@@ -249,22 +249,22 @@ enum wdt_period {
  *  function before being modified by the user application.
  */
 struct wdt_conf {
-	/** If \c true, the Watchdog will be locked to the current configuration
-	 *  settings when the Watchdog is enabled */
-	bool always_on;
-	/** Enable/Disable the Watchdog Timer */
-	bool enable;
+    /** If \c true, the Watchdog will be locked to the current configuration
+     *  settings when the Watchdog is enabled */
+    bool always_on;
+    /** Enable/Disable the Watchdog Timer */
+    bool enable;
 #if !(SAML21) && !(SAML22) && !(SAMC20) && !(SAMC21) && !(SAMR30)
-	/** GCLK generator used to clock the peripheral except SAM L21/L22/C21/C20/R30*/
-	enum gclk_generator clock_source;
+    /** GCLK generator used to clock the peripheral except SAM L21/L22/C21/C20/R30*/
+    enum gclk_generator clock_source;
 #endif
-	/** Number of Watchdog timer clock ticks until the Watchdog expires */
-	enum wdt_period timeout_period;
-	/** Number of Watchdog timer clock ticks until the reset window opens */
-	enum wdt_period window_period;
-	/** Number of Watchdog timer clock ticks until the early warning flag is
-	 *  set */
-	enum wdt_period early_warning_period;
+    /** Number of Watchdog timer clock ticks until the Watchdog expires */
+    enum wdt_period timeout_period;
+    /** Number of Watchdog timer clock ticks until the reset window opens */
+    enum wdt_period window_period;
+    /** Number of Watchdog timer clock ticks until the early warning flag is
+     *  set */
+    enum wdt_period early_warning_period;
 };
 
 /** \name Configuration and Initialization
@@ -287,17 +287,19 @@ struct wdt_conf {
  */
 static inline bool wdt_is_syncing(void)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	if (WDT_module->SYNCBUSY.reg) {
+    if (WDT_module->SYNCBUSY.reg)
+    {
 #else
-	if (WDT_module->STATUS.reg & WDT_STATUS_SYNCBUSY) {
+    if (WDT_module->STATUS.reg & WDT_STATUS_SYNCBUSY)
+    {
 #endif
-		return true;
-	}
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /**
@@ -319,24 +321,24 @@ static inline bool wdt_is_syncing(void)
  *  \param[out] config  Configuration structure to initialize to default values
  */
 static inline void wdt_get_config_defaults(
-		struct wdt_conf *const config)
+        struct wdt_conf *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	/* Default configuration values */
-	config->always_on            = false;
-	config->enable               = true;
+    /* Default configuration values */
+    config->always_on            = false;
+    config->enable               = true;
 #if !(SAML21) && !(SAML22) && !(SAMC20) && !(SAMC21) && !(SAMR30)
-	config->clock_source         = GCLK_GENERATOR_4;
+    config->clock_source         = GCLK_GENERATOR_4;
 #endif
-	config->timeout_period       = WDT_PERIOD_16384CLK;
-	config->window_period        = WDT_PERIOD_NONE;
-	config->early_warning_period = WDT_PERIOD_NONE;
+    config->timeout_period       = WDT_PERIOD_16384CLK;
+    config->window_period        = WDT_PERIOD_NONE;
+    config->early_warning_period = WDT_PERIOD_NONE;
 }
 
 enum status_code wdt_set_config(
-		const struct wdt_conf *const config);
+        const struct wdt_conf *const config);
 
 /** \brief Determines if the Watchdog timer is currently locked in an enabled state.
  *
@@ -347,12 +349,12 @@ enum status_code wdt_set_config(
  */
 static inline bool wdt_is_locked(void)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
 #if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30)
-	return (WDT_module->CTRLA.reg & WDT_CTRLA_ALWAYSON);
+    return (WDT_module->CTRLA.reg & WDT_CTRLA_ALWAYSON);
 #else
-	return (WDT_module->CTRL.reg & WDT_CTRL_ALWAYSON);
+    return (WDT_module->CTRL.reg & WDT_CTRL_ALWAYSON);
 #endif
 }
 
@@ -369,9 +371,9 @@ static inline bool wdt_is_locked(void)
  */
 static inline void wdt_clear_early_warning(void)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
-	WDT_module->INTFLAG.reg = WDT_INTFLAG_EW;
+    WDT_module->INTFLAG.reg = WDT_INTFLAG_EW;
 }
 
 /** \brief Determines if the Watchdog timer early warning period has elapsed.
@@ -385,9 +387,9 @@ static inline void wdt_clear_early_warning(void)
  */
 static inline bool wdt_is_early_warning(void)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
-	return (WDT_module->INTFLAG.reg & WDT_INTFLAG_EW);
+    return (WDT_module->INTFLAG.reg & WDT_INTFLAG_EW);
 }
 
 void wdt_reset_count(void);
@@ -407,14 +409,14 @@ void wdt_reset_count(void);
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>WDT</td>
- *		<td>Watchdog Timer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>WDT</td>
+ *      <td>Watchdog Timer</td>
+ *  </tr>
  * </table>
  *
  *
@@ -435,18 +437,18 @@ void wdt_reset_count(void);
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Driver updated to follow driver type convention:
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Driver updated to follow driver type convention:
  *             \li wdt_init, wdt_enable, wdt_disable functions removed
  *             \li wdt_set_config function added
  *             \li WDT module enable state moved inside the configuration struct </td>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -467,36 +469,36 @@ void wdt_reset_count(void);
  * \page asfdoc_sam0_wdt_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</th>
- *		<th>Date</th>
- *		<th>Comments</th>
- *	</tr>
- *	<tr>
- *		<td>42124E</td>
- *		<td>12/2015</td>
- *		<td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAM R30, and SAM C20/C21</td>
- *	</tr>
- *	<tr>
- *		<td>42124D</td>
- *		<td>12/2014</td>
- *		<td>Added SAM R21 and SAM D10/D11 support</td>
- *	</tr>
- *	<tr>
- *		<td>42124C</td>
- *		<td>01/2014</td>
- *		<td>Add SAM D21 support</td>
- *	</tr>
- *	<tr>
- *		<td>42124B</td>
- *		<td>06/2013</td>
- *		<td>Corrected documentation typos</td>
- *	</tr>
- *	<tr>
- *		<td>42124A</td>
- *		<td>06/2013</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</th>
+ *      <th>Date</th>
+ *      <th>Comments</th>
+ *  </tr>
+ *  <tr>
+ *      <td>42124E</td>
+ *      <td>12/2015</td>
+ *      <td>Added support for SAM L21/L22, SAM DA1, SAM D09, SAM R30, and SAM C20/C21</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42124D</td>
+ *      <td>12/2014</td>
+ *      <td>Added SAM R21 and SAM D10/D11 support</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42124C</td>
+ *      <td>01/2014</td>
+ *      <td>Add SAM D21 support</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42124B</td>
+ *      <td>06/2013</td>
+ *      <td>Corrected documentation typos</td>
+ *  </tr>
+ *  <tr>
+ *      <td>42124A</td>
+ *      <td>06/2013</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c
index 89429595a412..08ee73812b2f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.c
@@ -64,21 +64,21 @@ wdt_callback_t wdt_early_warning_callback;
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code wdt_register_callback(
-		const wdt_callback_t callback,
-		const enum wdt_callback type)
+        const wdt_callback_t callback,
+        const enum wdt_callback type)
 {
-	/* Sanity check arguments */
-	Assert(callback);
+    /* Sanity check arguments */
+    Assert(callback);
 
-	switch (type)
-	{
-	case WDT_CALLBACK_EARLY_WARNING:
-		wdt_early_warning_callback = callback;
-		return STATUS_OK;
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    switch (type)
+    {
+    case WDT_CALLBACK_EARLY_WARNING:
+        wdt_early_warning_callback = callback;
+        return STATUS_OK;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -94,17 +94,17 @@ enum status_code wdt_register_callback(
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code wdt_unregister_callback(
-		const enum wdt_callback type)
+        const enum wdt_callback type)
 {
-	switch (type)
-	{
-	case WDT_CALLBACK_EARLY_WARNING:
-		wdt_early_warning_callback = NULL;
-		return STATUS_OK;
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    switch (type)
+    {
+    case WDT_CALLBACK_EARLY_WARNING:
+        wdt_early_warning_callback = NULL;
+        return STATUS_OK;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -120,20 +120,20 @@ enum status_code wdt_unregister_callback(
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code wdt_enable_callback(
-		const enum wdt_callback type)
+        const enum wdt_callback type)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
-	switch (type)
-	{
-	case WDT_CALLBACK_EARLY_WARNING:
-		WDT_module->INTENSET.reg = WDT_INTENSET_EW;
-		system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_WDT);
-		return STATUS_OK;
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    switch (type)
+    {
+    case WDT_CALLBACK_EARLY_WARNING:
+        WDT_module->INTENSET.reg = WDT_INTENSET_EW;
+        system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_WDT);
+        return STATUS_OK;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /**
@@ -148,27 +148,28 @@ enum status_code wdt_enable_callback(
  * \retval STATUS_ERR_INVALID_ARG  If an invalid callback type was supplied
  */
 enum status_code wdt_disable_callback(
-		const enum wdt_callback type)
+        const enum wdt_callback type)
 {
-	Wdt *const WDT_module = WDT;
+    Wdt *const WDT_module = WDT;
 
-	switch (type)
-	{
-	case WDT_CALLBACK_EARLY_WARNING:
-		WDT_module->INTENCLR.reg = WDT_INTENCLR_EW;
-		return STATUS_OK;
-	default:
-		Assert(false);
-		return STATUS_ERR_INVALID_ARG;
-	}
+    switch (type)
+    {
+    case WDT_CALLBACK_EARLY_WARNING:
+        WDT_module->INTENCLR.reg = WDT_INTENCLR_EW;
+        return STATUS_OK;
+    default:
+        Assert(false);
+        return STATUS_ERR_INVALID_ARG;
+    }
 }
 
 /** Handler for the WDT hardware module interrupt. */
 void WDT_Handler(void)
 {
-	wdt_clear_early_warning();
+    wdt_clear_early_warning();
 
-	if (wdt_early_warning_callback) {
-		wdt_early_warning_callback();
-	}
+    if (wdt_early_warning_callback)
+    {
+        wdt_early_warning_callback();
+    }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h
index af76dc344b30..4b33a7a9a742 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_callback.h
@@ -69,18 +69,18 @@ typedef void (*wdt_callback_t)(void);
 /** Enum for the possible callback types for the WDT module. */
 enum wdt_callback
 {
-	/** Callback type for when an early warning callback from the WDT module
-	 *  is issued
-	 */
-	WDT_CALLBACK_EARLY_WARNING,
+    /** Callback type for when an early warning callback from the WDT module
+     *  is issued
+     */
+    WDT_CALLBACK_EARLY_WARNING,
 };
 
 enum status_code wdt_register_callback(
-		const wdt_callback_t callback,
-		const enum wdt_callback type);
+        const wdt_callback_t callback,
+        const enum wdt_callback type);
 
 enum status_code wdt_unregister_callback(
-		const enum wdt_callback type);
+        const enum wdt_callback type);
 
 /** @} */
 
@@ -89,10 +89,10 @@ enum status_code wdt_unregister_callback(
  */
 
 enum status_code wdt_enable_callback(
-		const enum wdt_callback type);
+        const enum wdt_callback type);
 
 enum status_code wdt_disable_callback(
-		const enum wdt_callback type);
+        const enum wdt_callback type);
 
 /** @} */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c
index 14276b3b3af1..fc1861fd78d8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.c
@@ -49,28 +49,34 @@ struct wdt_module *_wdt_instances[WDT_INST_NUM];
 
 static void wdt_isr_handler(void)
 {
-	struct wdt_module *module = NULL;
-	
-	if (WDT0->WDOGMIS.reg) {
-		module = _wdt_instances[0];
-		if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN)) {
-			module->hw->WDOGINTCLR.reg = 0x01;
-		}
-		if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
-			(module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING))) {
-			(module->callback[WDT_CALLBACK_EARLY_WARNING])();
-		}
-	}
-	if (WDT1->WDOGMIS.reg) {
-		module = _wdt_instances[1];
-		if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN)) {
-			module->hw->WDOGINTCLR.reg = 0x01;
-		}
-		if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
-			(module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING))) {
-			(module->callback[WDT_CALLBACK_EARLY_WARNING])();
-		}
-	}
+    struct wdt_module *module = NULL;
+
+    if (WDT0->WDOGMIS.reg)
+    {
+        module = _wdt_instances[0];
+        if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN))
+        {
+            module->hw->WDOGINTCLR.reg = 0x01;
+        }
+        if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
+            (module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING)))
+            {
+            (module->callback[WDT_CALLBACK_EARLY_WARNING])();
+        }
+    }
+    if (WDT1->WDOGMIS.reg)
+    {
+        module = _wdt_instances[1];
+        if (!(module->hw->WDOGCONTROL.reg & WDT_WDOGCONTROL_RESEN))
+        {
+            module->hw->WDOGINTCLR.reg = 0x01;
+        }
+        if ((module->callback_enable_mask & (1 << WDT_CALLBACK_EARLY_WARNING)) &&
+            (module->callback_reg_mask & (1 << WDT_CALLBACK_EARLY_WARNING)))
+            {
+            (module->callback[WDT_CALLBACK_EARLY_WARNING])();
+        }
+    }
 }
 
 /**
@@ -90,12 +96,12 @@ static void wdt_isr_handler(void)
  */
 void wdt_get_config_defaults(struct wdt_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(config);
 
-	config->load_value = 0xFFFFFFFF;
-	config->enable_reset = true;
-	config->write_access = true;
+    config->load_value = 0xFFFFFFFF;
+    config->enable_reset = true;
+    config->write_access = true;
 }
 
 /**
@@ -114,53 +120,60 @@ void wdt_get_config_defaults(struct wdt_config *const config)
  * \retval STATUS_ERR_BAD_DATA  If the value isn't available
  */
 enum status_code wdt_set_config(struct wdt_module *const module, Wdt * const hw,
-		const struct wdt_config *const config)
+        const struct wdt_config *const config)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(hw);
-	Assert(config);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(hw);
+    Assert(config);
+
+    /* Assign module pointer to software instance struct */
+    module->hw = hw;
+
+    if (config->load_value == 0)
+    {
+        return STATUS_ERR_BAD_DATA;
+    }
 
-	/* Assign module pointer to software instance struct */
-	module->hw = hw;
+    if (module->hw == WDT0)
+    {
+        system_clock_peripheral_disable(PERIPHERAL_WDT0);
+    } else if (module->hw ==WDT1)
+    {
+        system_clock_peripheral_disable(PERIPHERAL_WDT1);
+    }
 
-	if (config->load_value == 0) {
-		return STATUS_ERR_BAD_DATA;
-	}
-	
-	if (module->hw == WDT0) {
-		system_clock_peripheral_disable(PERIPHERAL_WDT0);
-	} else if (module->hw ==WDT1) {
-		system_clock_peripheral_disable(PERIPHERAL_WDT1);
-	}
+    /* Unlock register */
+    module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
 
-	/* Unlock register */
-	module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
+    module->hw->WDOGLOAD.reg = config->load_value;
 
-	module->hw->WDOGLOAD.reg = config->load_value;
+    if (config->enable_reset)
+    {
+        module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_RESEN;
+    }
+    module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_INTEN;
 
-	if (config->enable_reset) {
-		module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_RESEN;
-	}
-	module->hw->WDOGCONTROL.reg |= WDT_WDOGCONTROL_INTEN;
-	
-	/* Lock register */
-	if (config->write_access == false) {
-		module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
-	}
-	
-	system_register_isr(RAM_ISR_TABLE_NMI_INDEX, (uint32_t)wdt_isr_handler);
-	
-	/* Enable WDT clock */
-	if (module->hw == WDT0) {
-		_wdt_instances[0] = module;
-		system_clock_peripheral_enable(PERIPHERAL_WDT0);
-	} else if (module->hw == WDT1) {
-		_wdt_instances[1] = module;
-		system_clock_peripheral_enable(PERIPHERAL_WDT1);
-	}
+    /* Lock register */
+    if (config->write_access == false)
+    {
+        module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
+    }
 
-	return STATUS_OK;
+    system_register_isr(RAM_ISR_TABLE_NMI_INDEX, (uint32_t)wdt_isr_handler);
+
+    /* Enable WDT clock */
+    if (module->hw == WDT0)
+    {
+        _wdt_instances[0] = module;
+        system_clock_peripheral_enable(PERIPHERAL_WDT0);
+    } else if (module->hw == WDT1)
+    {
+        _wdt_instances[1] = module;
+        system_clock_peripheral_enable(PERIPHERAL_WDT1);
+    }
+
+    return STATUS_OK;
 }
 
 /**
@@ -172,11 +185,13 @@ enum status_code wdt_set_config(struct wdt_module *const module, Wdt * const hw,
  */
 void wdt_reset(struct wdt_module *const module)
 {
-	if (module->hw == WDT0) {
-		system_peripheral_reset(PERIPHERAL_WDT0);
-	} else if (module->hw == WDT1) {
-		system_peripheral_reset(PERIPHERAL_WDT1);
-	}
+    if (module->hw == WDT0)
+    {
+        system_peripheral_reset(PERIPHERAL_WDT0);
+    } else if (module->hw == WDT1)
+    {
+        system_peripheral_reset(PERIPHERAL_WDT1);
+    }
 }
 
 /**
@@ -188,7 +203,7 @@ void wdt_reset(struct wdt_module *const module)
  */
 uint8_t wdt_get_interrupt_status(struct wdt_module *const module)
 {
-	return module->hw->WDOGMIS.reg;
+    return module->hw->WDOGMIS.reg;
 }
 
 /**
@@ -200,7 +215,7 @@ uint8_t wdt_get_interrupt_status(struct wdt_module *const module)
  */
 uint8_t wdt_get_status(struct wdt_module *const module)
 {
-	return module->hw->WDOGRIS.reg;
+    return module->hw->WDOGRIS.reg;
 }
 
 /**
@@ -212,7 +227,7 @@ uint8_t wdt_get_status(struct wdt_module *const module)
  */
 void wdt_clear_status(struct wdt_module *const module)
 {
-	module->hw->WDOGINTCLR.reg = 0x01;
+    module->hw->WDOGINTCLR.reg = 0x01;
 }
 
 /**
@@ -230,19 +245,21 @@ void wdt_clear_status(struct wdt_module *const module)
  */
 enum status_code wdt_set_reload_count(struct wdt_module *const module, uint32_t load_value)
 {
-	if (load_value == 0) {
-		return STATUS_ERR_BAD_DATA;
-	} else {
-		if (module->hw->WDOGLOCK.bit.ENABLE_STATUS) {
-			module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
-			module->hw->WDOGLOAD.reg = load_value;
-			module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
-		} else {
-			module->hw->WDOGLOAD.reg = load_value;
-		}
-	}
+    if (load_value == 0)
+    {
+        return STATUS_ERR_BAD_DATA;
+    } else {
+        if (module->hw->WDOGLOCK.bit.ENABLE_STATUS)
+        {
+            module->hw->WDOGLOCK.reg = WDT_WRITE_ACCESS_KEY;
+            module->hw->WDOGLOAD.reg = load_value;
+            module->hw->WDOGLOCK.reg = WDT_WDOGLOCK_ENABLE_STATUS;
+        } else {
+            module->hw->WDOGLOAD.reg = load_value;
+        }
+    }
 
-	return STATUS_OK;
+    return STATUS_OK;
 }
 
 /**
@@ -255,9 +272,9 @@ enum status_code wdt_set_reload_count(struct wdt_module *const module, uint32_t
  *
  */
 void wdt_get_current_count(struct wdt_module *const module, \
-			uint32_t * count_value)
+            uint32_t * count_value)
 {
-	*count_value = module->hw->WDOGVALUE.reg;
+    *count_value = module->hw->WDOGVALUE.reg;
 }
 
 /**
@@ -275,17 +292,17 @@ void wdt_get_current_count(struct wdt_module *const module, \
  *
  */
 void wdt_register_callback(struct wdt_module *const module,
-		wdt_callback_t callback_func,
-		enum wdt_callback callback_type)
+        wdt_callback_t callback_func,
+        enum wdt_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
-	Assert(callback_func);
+    /* Sanity check arguments */
+    Assert(module);
+    Assert(callback_func);
 
-	/* Register callback function */
-	module->callback[callback_type] = callback_func;
-	/* Set the bit corresponding to the callback_type */
-	module->callback_reg_mask |= (1 << callback_type);
+    /* Register callback function */
+    module->callback[callback_type] = callback_func;
+    /* Set the bit corresponding to the callback_type */
+    module->callback_reg_mask |= (1 << callback_type);
 }
 
 /**
@@ -298,15 +315,15 @@ void wdt_register_callback(struct wdt_module *const module,
  *
  */
 void wdt_unregister_callback(struct wdt_module *module,
-		enum wdt_callback callback_type)
+        enum wdt_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Unregister callback function */
-	module->callback[callback_type] = NULL;
-	/* Clear the bit corresponding to the callback_type */
-	module->callback_reg_mask &= ~(1 << callback_type);
+    /* Unregister callback function */
+    module->callback[callback_type] = NULL;
+    /* Clear the bit corresponding to the callback_type */
+    module->callback_reg_mask &= ~(1 << callback_type);
 }
 
 /**
@@ -320,13 +337,13 @@ void wdt_unregister_callback(struct wdt_module *module,
  * \param[in]  callback_type  Callback type given by an enum
  */
 void wdt_enable_callback(struct wdt_module *const module,
-		enum wdt_callback callback_type)
+        enum wdt_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Enable callback */
-	module->callback_enable_mask |= (1 << callback_type);
+    /* Enable callback */
+    module->callback_enable_mask |= (1 << callback_type);
 }
 
 /**
@@ -339,11 +356,11 @@ void wdt_enable_callback(struct wdt_module *const module,
  * \param[in]  callback_type  Callback type given by an enum
  */
 void wdt_disable_callback(struct wdt_module *const module,
-		enum wdt_callback callback_type)
+        enum wdt_callback callback_type)
 {
-	/* Sanity check arguments */
-	Assert(module);
+    /* Sanity check arguments */
+    Assert(module);
 
-	/* Disable callback */
-	module->callback_enable_mask &= ~(1 << callback_type);
-}
\ No newline at end of file
+    /* Disable callback */
+    module->callback_enable_mask &= ~(1 << callback_type);
+}
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h
index 3cd162211b7b..d1dcf3c9c71c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/drivers/wdt/wdt_sam_b.h
@@ -127,13 +127,13 @@ typedef void (*wdt_callback_t)(void);
 /** Enum for the possible callback types for the WDT module. */
 enum wdt_callback
 {
-	/** 
-	 * Callback type for when an early warning callback from the WDT module
-	 * is issued
-	 */
-	WDT_CALLBACK_EARLY_WARNING,
-	/** Number of available callbacks */
-	WDT_CALLBACK_N,
+    /**
+     * Callback type for when an early warning callback from the WDT module
+     * is issued
+     */
+    WDT_CALLBACK_EARLY_WARNING,
+    /** Number of available callbacks */
+    WDT_CALLBACK_N,
 };
 
 /**
@@ -144,12 +144,12 @@ enum wdt_callback
  *  function before being modified by the user application.
  */
 struct wdt_config {
-	/** Watchdog load value */
-	uint32_t load_value;
-	/** Enable reset output */
-	bool enable_reset;
-	/** Enable write access */
-	bool write_access;
+    /** Watchdog load value */
+    uint32_t load_value;
+    /** Enable reset output */
+    bool enable_reset;
+    /** Enable write access */
+    bool write_access;
 };
 
 /**
@@ -163,14 +163,14 @@ struct wdt_config {
  */
 struct wdt_module {
 #if !defined(__DOXYGEN__)
-	/** Pointer to the hardware instance */
-	Wdt *hw;
-	/** Array to store callback function pointers in */
-	wdt_callback_t callback[WDT_CALLBACK_N];
-	/** Bit mask for callbacks registered */
-	uint8_t callback_reg_mask;
-	/** Bit mask for callbacks enabled */
-	uint8_t callback_enable_mask;
+    /** Pointer to the hardware instance */
+    Wdt *hw;
+    /** Array to store callback function pointers in */
+    wdt_callback_t callback[WDT_CALLBACK_N];
+    /** Bit mask for callbacks registered */
+    uint8_t callback_reg_mask;
+    /** Bit mask for callbacks enabled */
+    uint8_t callback_enable_mask;
 #endif
 };
 
@@ -180,7 +180,7 @@ struct wdt_module {
  */
 void wdt_get_config_defaults(struct wdt_config *const config);
 enum status_code wdt_set_config(struct wdt_module *const module, Wdt * const hw, \
-			const struct wdt_config *const config);
+            const struct wdt_config *const config);
 /** @} */
 
 /**
@@ -204,9 +204,9 @@ void wdt_clear_status(struct wdt_module *const module);
  * @{
  */
 enum status_code wdt_set_reload_count(struct wdt_module *const module, \
-			uint32_t load_value);
+            uint32_t load_value);
 void wdt_get_current_count(struct wdt_module *const module, \
-			uint32_t * count_value);
+            uint32_t * count_value);
 /** @} */
 
 /**
@@ -214,14 +214,14 @@ void wdt_get_current_count(struct wdt_module *const module, \
  * @{
  */
 void wdt_register_callback(struct wdt_module *const module,
-		wdt_callback_t callback_func,
-		enum wdt_callback callback_type);
+        wdt_callback_t callback_func,
+        enum wdt_callback callback_type);
 void wdt_unregister_callback(struct wdt_module *module,
-		enum wdt_callback callback_type);
+        enum wdt_callback callback_type);
 void wdt_enable_callback(struct wdt_module *module,
-		enum wdt_callback callback_type);
+        enum wdt_callback callback_type);
 void wdt_disable_callback(struct wdt_module *const module,
-		enum wdt_callback callback_type);
+        enum wdt_callback callback_type);
 /** @} */
 
 /** @} */
@@ -239,14 +239,14 @@ void wdt_disable_callback(struct wdt_module *const module,
  * The table below presents the acronyms used in this module:
  *
  * <table>
- *	<tr>
- *		<th>Acronym</th>
- *		<th>Description</th>
- *	</tr>
- *	<tr>
- *		<td>WDT</td>
- *		<td>Watchdog Timer</td>
- *	</tr>
+ *  <tr>
+ *      <th>Acronym</th>
+ *      <th>Description</th>
+ *  </tr>
+ *  <tr>
+ *      <td>WDT</td>
+ *      <td>Watchdog Timer</td>
+ *  </tr>
  * </table>
  *
  *
@@ -265,12 +265,12 @@ void wdt_disable_callback(struct wdt_module *const module,
  * the table.
  *
  * <table>
- *	<tr>
- *		<th>Changelog</th>
- *	</tr>
- *	<tr>
- *		<td>Initial Release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Changelog</th>
+ *  </tr>
+ *  <tr>
+ *      <td>Initial Release</td>
+ *  </tr>
  * </table>
  */
 
@@ -288,16 +288,16 @@ void wdt_disable_callback(struct wdt_module *const module,
  * \page asfdoc_samb_wdt_document_revision_history Document Revision History
  *
  * <table>
- *	<tr>
- *		<th>Doc. Rev.</td>
- *		<th>Date</td>
- *		<th>Comments</td>
- *	</tr>
- *	<tr>
- *		<td>A</td>
- *		<td>09/2015</td>
- *		<td>Initial release</td>
- *	</tr>
+ *  <tr>
+ *      <th>Doc. Rev.</td>
+ *      <th>Date</td>
+ *      <th>Comments</td>
+ *  </tr>
+ *  <tr>
+ *      <td>A</td>
+ *      <td>09/2015</td>
+ *      <td>Initial release</td>
+ *  </tr>
  * </table>
  */
 
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h
index 1f3db56dc447..bfe5dfad1480 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/ac.h
@@ -81,10 +81,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for AC peripheral ========== */
-#define AC_CMP_NUM                  2        // Number of comparators
-#define AC_GCLK_ID_ANA              25       // Index of Generic Clock for analog
-#define AC_GCLK_ID_DIG              24       // Index of Generic Clock for digital
-#define AC_NUM_CMP                  2       
-#define AC_PAIRS                    1        // Number of pairs of comparators
+#define AC_CMP_NUM                  2        /* Number of comparators*/
+#define AC_GCLK_ID_ANA              25       /* Index of Generic Clock for analog*/
+#define AC_GCLK_ID_DIG              24       /* Index of Generic Clock for digital*/
+#define AC_NUM_CMP                  2
+#define AC_PAIRS                    1        /* Number of pairs of comparators*/
 
 #endif /* _SAMD20_AC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h
index 1966ef868406..abab5ae22720 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/adc.h
@@ -93,9 +93,9 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for ADC peripheral ========== */
-#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
-#define ADC_GCLK_ID                 23       // Index of Generic Clock
-#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
-#define ADC_RESULT_MSB              15       // Size of Result
+#define ADC_EXTCHANNEL_MSB          19       /* Number of external channels*/
+#define ADC_GCLK_ID                 23       /* Index of Generic Clock*/
+#define ADC_RESULT_BITS             16       /* Size of RESULT.RESULT bitfield*/
+#define ADC_RESULT_MSB              15       /* Size of Result*/
 
 #endif /* _SAMD20_ADC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h
index 6da39681b110..1966547f3178 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/eic.h
@@ -75,10 +75,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for EIC peripheral ========== */
-#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
-#define EIC_EXTINT_NUM              16       // Number of External Interrupts
-#define EIC_GCLK_ID                 3        // Index of Generic Clock
-#define EIC_NUMBER_OF_CONFIG_REGS   2        // Number of CONFIG registers (obsolete)
-#define EIC_NUMBER_OF_INTERRUPTS    16       // Number of External Interrupts (obsolete)
+#define EIC_CONFIG_NUM              2        /* Number of CONFIG registers*/
+#define EIC_EXTINT_NUM              16       /* Number of External Interrupts*/
+#define EIC_GCLK_ID                 3        /* Index of Generic Clock*/
+#define EIC_NUMBER_OF_CONFIG_REGS   2        /* Number of CONFIG registers (obsolete)*/
+#define EIC_NUMBER_OF_INTERRUPTS    16       /* Number of External Interrupts (obsolete)*/
 
 #endif /* _SAMD20_EIC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h
index e91ca9d73490..4b32ec9284d1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/evsys.h
@@ -67,11 +67,11 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for EVSYS peripheral ========== */
-#define EVSYS_CHANNELS              8        // Number of Channels
-#define EVSYS_CHANNELS_BITS         3        // Number of bits to select Channel
-#define EVSYS_CHANNELS_MSB          7        // Number of Channels - 1
-#define EVSYS_EXTEVT_NUM                     // Number of External Event Generators
-#define EVSYS_EXT_EVT_MSB           0        // Number of External Event Generators - 1
+#define EVSYS_CHANNELS              8        /* Number of Channels*/
+#define EVSYS_CHANNELS_BITS         3        /* Number of bits to select Channel*/
+#define EVSYS_CHANNELS_MSB          7        /* Number of Channels - 1*/
+#define EVSYS_EXTEVT_NUM                     /* Number of External Event Generators*/
+#define EVSYS_EXT_EVT_MSB           0        /* Number of External Event Generators - 1*/
 #define EVSYS_GCLK_ID_0             4
 #define EVSYS_GCLK_ID_1             5
 #define EVSYS_GCLK_ID_2             6
@@ -83,12 +83,12 @@
 #define EVSYS_GCLK_ID_LSB           4
 #define EVSYS_GCLK_ID_MSB           11
 #define EVSYS_GCLK_ID_SIZE          8
-#define EVSYS_GENERATORS            59       // Total Number of Event Generators
-#define EVSYS_GENERATORS_BITS       6        // Number of bits to select Event Generator
-#define EVSYS_USERS                 14       // Total Number of Event Users
-#define EVSYS_USERS_BITS            4        // Number of bits to select Event User
+#define EVSYS_GENERATORS            59       /* Total Number of Event Generators*/
+#define EVSYS_GENERATORS_BITS       6        /* Number of bits to select Event Generator*/
+#define EVSYS_USERS                 14       /* Total Number of Event Users*/
+#define EVSYS_USERS_BITS            4        /* Number of bits to select Event User*/
 
-// GENERATORS
+/* GENERATORS*/
 #define EVSYS_ID_GEN_RTC_CMP_0      1
 #define EVSYS_ID_GEN_RTC_CMP_1      2
 #define EVSYS_ID_GEN_RTC_OVF        3
@@ -149,7 +149,7 @@
 #define EVSYS_ID_GEN_PTC_EOC        58
 #define EVSYS_ID_GEN_PTC_WCOMP      59
 
-// USERS
+/* USERS*/
 #define EVSYS_ID_USER_TC0_EVU       0
 #define EVSYS_ID_USER_TC1_EVU       1
 #define EVSYS_ID_USER_TC2_EVU       2
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h
index b6f6bde59e79..1ec7636d8082 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/gclk.h
@@ -63,20 +63,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS            16      
-#define GCLK_GEN_NUM                8        // Number of Generic Clock Generators
-#define GCLK_GEN_NUM_MSB            7        // Number of Generic Clock Generators - 1
-#define GCLK_GEN_SOURCE_NUM_MSB     7        // Number of Generic Clock Sources - 1
-#define GCLK_NUM                    28       // Number of Generic Clock Users
-#define GCLK_SOURCE_DFLL48M         7       
-#define GCLK_SOURCE_FDPLL                   
-#define GCLK_SOURCE_GCLKGEN1        2       
-#define GCLK_SOURCE_GCLKIN          1       
-#define GCLK_SOURCE_NUM             8        // Number of Generic Clock Sources
-#define GCLK_SOURCE_OSCULP32K       3       
-#define GCLK_SOURCE_OSC8M           6       
-#define GCLK_SOURCE_OSC32K          4       
-#define GCLK_SOURCE_XOSC            0       
-#define GCLK_SOURCE_XOSC32K         5       
+#define GCLK_GENDIV_BITS            16
+#define GCLK_GEN_NUM                8        /* Number of Generic Clock Generators*/
+#define GCLK_GEN_NUM_MSB            7        /* Number of Generic Clock Generators - 1*/
+#define GCLK_GEN_SOURCE_NUM_MSB     7        /* Number of Generic Clock Sources - 1*/
+#define GCLK_NUM                    28       /* Number of Generic Clock Users*/
+#define GCLK_SOURCE_DFLL48M         7
+#define GCLK_SOURCE_FDPLL
+#define GCLK_SOURCE_GCLKGEN1        2
+#define GCLK_SOURCE_GCLKIN          1
+#define GCLK_SOURCE_NUM             8        /* Number of Generic Clock Sources*/
+#define GCLK_SOURCE_OSCULP32K       3
+#define GCLK_SOURCE_OSC8M           6
+#define GCLK_SOURCE_OSC32K          4
+#define GCLK_SOURCE_XOSC            0
+#define GCLK_SOURCE_XOSC32K         5
 
 #endif /* _SAMD20_GCLK_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h
index e00b812b9de4..7441f2c594a8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/nvmctrl.h
@@ -75,18 +75,18 @@
 #define NVMCTRL_AUX1_ADDRESS        0x00806000
 #define NVMCTRL_AUX2_ADDRESS        0x00808000
 #define NVMCTRL_AUX3_ADDRESS        0x0080A000
-#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_CLK_AHB_ID          4        /* Index of AHB Clock in PM.AHBMASK register*/
 #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE          262144  
+#define NVMCTRL_FLASH_SIZE          262144
 #define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
-#define NVMCTRL_PAGES               4096    
-#define NVMCTRL_PAGE_HW             32      
-#define NVMCTRL_PAGE_SIZE           64      
-#define NVMCTRL_PAGE_W              16      
-#define NVMCTRL_PMSB                3       
-#define NVMCTRL_PSZ_BITS            6       
-#define NVMCTRL_ROW_PAGES           4       
-#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_PAGES               4096
+#define NVMCTRL_PAGE_HW             32
+#define NVMCTRL_PAGE_SIZE           64
+#define NVMCTRL_PAGE_W              16
+#define NVMCTRL_PMSB                3
+#define NVMCTRL_PSZ_BITS            6
+#define NVMCTRL_ROW_PAGES           4
+#define NVMCTRL_ROW_SIZE            256
 #define NVMCTRL_TEMP_LOG_ADDRESS    0x00806030
 #define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
 #define NVMCTRL_USER_PAGE_OFFSET    0x00800000
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h
index 9ce099609821..faf45b7e6a08 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac0.h
@@ -57,6 +57,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC0 peripheral ========== */
-#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 /* PAC protection mask at reset*/
 
 #endif /* _SAMD20_PAC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h
index 613cd3a4f65a..29f4241f4cd2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac1.h
@@ -57,6 +57,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC1 peripheral ========== */
-#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 /* PAC protection mask at reset*/
 
 #endif /* _SAMD20_PAC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h
index 8fddf58573ef..b2025e55f70d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pac2.h
@@ -57,6 +57,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC2 peripheral ========== */
-#define PAC2_WPROT_DEFAULT_VAL      0x00100000 // PAC protection mask at reset
+#define PAC2_WPROT_DEFAULT_VAL      0x00100000 /* PAC protection mask at reset*/
 
 #endif /* _SAMD20_PAC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h
index ad094fbf08ff..a61fb3412dbb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/pm.h
@@ -81,11 +81,11 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M       3       
-#define PM_CTRL_MCSEL_GCLK          0       
-#define PM_CTRL_MCSEL_OSC8M         1       
-#define PM_CTRL_MCSEL_XOSC          2       
-#define PM_PM_CLK_APB_NUM           2       
-#define PM_SYSTEM_CLOCK             1000000  // System Clock Frequency at Reset
+#define PM_CTRL_MCSEL_DFLL48M       3
+#define PM_CTRL_MCSEL_GCLK          0
+#define PM_CTRL_MCSEL_OSC8M         1
+#define PM_CTRL_MCSEL_XOSC          2
+#define PM_PM_CLK_APB_NUM           2
+#define PM_SYSTEM_CLOCK             1000000  /* System Clock Frequency at Reset*/
 
 #endif /* _SAMD20_PM_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h
index 5872ed858fe3..cde1e63d7153 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/port.h
@@ -105,35 +105,35 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PORT peripheral ========== */
-#define PORT_BITS                   64       // Number of PORT pins
-#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
-#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
-#define PORT_DRVSTR                 1        // DRVSTR supported
-#define PORT_DRVSTR_DEFAULT_VAL     { 0xDBFFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
-#define PORT_DRVSTR_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_BITS                   64       /* Number of PORT pins*/
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } /* Default value for DIR of all pins*/
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for DIR of all pins*/
+#define PORT_DRVSTR                 1        /* DRVSTR supported*/
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xDBFFFFFF, 0xC0C3FFFF } /* Default value for DRVSTR of all pins*/
+#define PORT_DRVSTR_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for DRVSTR of all pins*/
 #define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
-#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
-#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
-#define PORT_ODRAIN                 0        // ODRAIN supported
-#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
-#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
-#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
-#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
-#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
-#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
-#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
-#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
-#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
-#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
-#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
-#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
-#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
-#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
-#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
-#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
-#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
-#define PORT_SLEWLIM                0        // SLEWLIM supported
-#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
-#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } /* Default value for INEN of all pins*/
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for INEN of all pins*/
+#define PORT_ODRAIN                 0        /* ODRAIN supported*/
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } /* Default value for ODRAIN of all pins*/
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } /* Implementation mask for ODRAIN of all pins*/
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } /* Default value for OUT of all pins*/
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for OUT of all pins*/
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for all PORT pins*/
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } /* Default value for PMUX[0] of all pins*/
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PMUX[0] of all pins*/
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } /* Default value for PMUX[1] of all pins*/
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } /* Implementation mask for PMUX[1] of all pins*/
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } /* Default value for PMUX[2] of all pins*/
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } /* Implementation mask for PMUX[2] of all pins*/
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } /* Default value for PMUX[3] of all pins*/
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } /* Implementation mask for PMUX[3] of all pins*/
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } /* Default value for PMUXEN of all pins*/
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PMUXEN of all pins*/
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } /* Default value for PULLEN of all pins*/
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PULLEN of all pins*/
+#define PORT_SLEWLIM                0        /* SLEWLIM supported*/
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } /* Default value for SLEWLIM of all pins*/
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } /* Implementation mask for SLEWLIM of all pins*/
 
 #endif /* _SAMD20_PORT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h
index dec6f6ec2467..6fb9cbd58999 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/rtc.h
@@ -109,12 +109,12 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for RTC peripheral ========== */
-#define RTC_ALARM_NUM               1        // Number of Alarms
-#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
-#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
-#define RTC_GCLK_ID                 2        // Index of Generic Clock
-#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
-#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
-#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+#define RTC_ALARM_NUM               1        /* Number of Alarms*/
+#define RTC_COMP16_NUM              2        /* Number of 16-bit Comparators*/
+#define RTC_COMP32_NUM              1        /* Number of 32-bit Comparators*/
+#define RTC_GCLK_ID                 2        /* Index of Generic Clock*/
+#define RTC_NUM_OF_ALARMS           1        /* Number of Alarms (obsolete)*/
+#define RTC_NUM_OF_COMP16           2        /* Number of 16-bit Comparators (obsolete)*/
+#define RTC_NUM_OF_COMP32           1        /* Number of 32-bit Comparators (obsolete)*/
 
 #endif /* _SAMD20_RTC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h
index 76bc298ac7d6..b20bf4d8fded 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/sysctrl.h
@@ -100,14 +100,14 @@
 #define SYSCTRL_VREG_LEVEL_MSB      2
 #define SYSCTRL_BOD12_VERSION       0x111
 #define SYSCTRL_BOD33_VERSION       0x111
-#define SYSCTRL_DFLL48M_VERSION     0x211   
+#define SYSCTRL_DFLL48M_VERSION     0x211
 #define SYSCTRL_GCLK_VERSION        0x210
 #define SYSCTRL_OSCULP32K_VERSION   0x111
 #define SYSCTRL_OSC8M_VERSION       0x120
-#define SYSCTRL_OSC32K_VERSION      0x1101  
+#define SYSCTRL_OSC32K_VERSION      0x1101
 #define SYSCTRL_VREF_VERSION        0x200
 #define SYSCTRL_VREG_VERSION        0x201
-#define SYSCTRL_XOSC_VERSION        0x1101  
-#define SYSCTRL_XOSC32K_VERSION     0x1101  
+#define SYSCTRL_XOSC_VERSION        0x1101
+#define SYSCTRL_XOSC32K_VERSION     0x1101
 
 #endif /* _SAMD20_SYSCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h
index 22470ad3b1b2..b2419654e205 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/instance/wdt.h
@@ -69,6 +69,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for WDT peripheral ========== */
-#define WDT_GCLK_ID                 1        // Index of Generic Clock
+#define WDT_GCLK_ID                 1        /* Index of Generic Clock*/
 
 #endif /* _SAMD20_WDT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h
index 489f8b046013..6439212c2ef3 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e14.h
@@ -212,7 +212,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -294,7 +294,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20E14_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -303,13 +303,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h
index 859e12c914af..caa5fed37851 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e15.h
@@ -212,7 +212,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -294,7 +294,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20E15_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -303,13 +303,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h
index 94c5e1714bf3..4bfead48023d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e16.h
@@ -212,7 +212,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -294,7 +294,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20E16_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -303,13 +303,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h
index 263ed30de898..24dbd4e03354 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e17.h
@@ -212,7 +212,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -294,7 +294,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20E17_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -303,13 +303,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h
index 10c58da3d186..4480c7854d0a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20e18.h
@@ -212,7 +212,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -294,7 +294,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20E18_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -303,13 +303,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h
index 04043424b654..f4d0989dab49 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g14.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G14_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h
index 795073e337f4..f15bf43faf51 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g15.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G15_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h
index 1e9a6410b181..6a6fa63fe94a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g16.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G16_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h
index 2ae1b9caddb4..499659a4b8dc 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G17_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h
index b3223c963a3a..a300f60670ad 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g17u.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G17U_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h
index dda5bf7e6ea0..4bc22959272f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G18_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h
index ff9c56a56060..f9d7cbec4352 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20g18u.h
@@ -213,7 +213,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -297,7 +297,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20G18U_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -306,13 +306,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h
index 539c39890eb0..ae89f0c72306 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j14.h
@@ -220,7 +220,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -306,7 +306,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20J14_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -315,13 +315,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h
index a03cc5cf232d..604d8d8930ee 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j15.h
@@ -220,7 +220,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -306,7 +306,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20J15_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -315,13 +315,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h
index c78802e14d3a..c4f6096f7b0d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j16.h
@@ -220,7 +220,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -306,7 +306,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20J16_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -315,13 +315,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h
index b063819586b4..5a43accd135d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j17.h
@@ -220,7 +220,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -306,7 +306,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20J17_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -315,13 +315,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h
index 57c7ef154d9d..165531454aa8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/include/samd20j18.h
@@ -220,7 +220,7 @@ void PTC_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -306,7 +306,7 @@ void PTC_Handler                 ( void );
 /** \defgroup SAMD20J18_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -315,13 +315,13 @@ void PTC_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
 #define ID_PORT          35 /**< \brief Port Module (PORT) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c
index e2a10d926e15..de5ccbabf376 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/gcc/startup_samd20.c
@@ -211,14 +211,17 @@ void Reset_Handler(void)
         pSrc = &_etext;
         pDest = &_srelocate;
 
-        if (pSrc != pDest) {
-                for (; pDest < &_erelocate;) {
+        if (pSrc != pDest)
+        {
+                for (; pDest < &_erelocate;)
+                {
                         *pDest++ = *pSrc++;
                 }
         }
 
         /* Clear the zero segment */
-        for (pDest = &_szero; pDest < &_ezero;) {
+        for (pDest = &_szero; pDest < &_ezero;)
+        {
                 *pDest++ = 0;
         }
 
@@ -244,6 +247,7 @@ void Reset_Handler(void)
  */
 void Dummy_Handler(void)
 {
-        while (1) {
+        while (1)
+        {
         }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c
index 2c66a7f83fc1..b98240fe7a8a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/iar/startup_samd20.c
@@ -255,6 +255,7 @@ void Reset_Handler(void)
  */
 void Dummy_Handler(void)
 {
-        while (1) {
+        while (1)
+        {
         }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c
index 84d7ed7628bd..d5cf604c861f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd20/source/system_samd20.c
@@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
  */
 void SystemInit(void)
 {
-	// Keep the default device state after reset
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
+    /* Keep the default device state after reset*/
+    SystemCoreClock = __SYSTEM_CLOCK;
+    return;
 }
 
 /**
@@ -75,7 +75,7 @@ void SystemInit(void)
  */
 void SystemCoreClockUpdate(void)
 {
-	// Not implemented
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
+    /* Not implemented*/
+    SystemCoreClock = __SYSTEM_CLOCK;
+    return;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h
index 9ede7e095e5d..e9780c4d0f7e 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/ac.h
@@ -234,7 +234,7 @@ typedef union {
 
 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  COMP0:1;          /*!< bit:      0  Comparator 0                       */
     __I uint8_t  COMP1:1;          /*!< bit:      1  Comparator 1                       */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h
index 918051e1cb12..4c792e7e802b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/adc.h
@@ -486,7 +486,7 @@ typedef union {
 
 /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  RESRDY:1;         /*!< bit:      0  Result Ready                       */
     __I uint8_t  OVERRUN:1;        /*!< bit:      1  Overrun                            */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h
index 79cfe0ce6893..24bdaf3cf6bf 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dac.h
@@ -188,7 +188,7 @@ typedef union {
 
 /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  UNDERRUN:1;       /*!< bit:      0  Underrun                           */
     __I uint8_t  EMPTY:1;          /*!< bit:      1  Data Buffer Empty                  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h
index 49430bb91786..e2f270664ae9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/dmac.h
@@ -833,7 +833,7 @@ typedef union {
 
 /* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  TERR:1;           /*!< bit:      0  Transfer Error                     */
     __I uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete                  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h
index 5a9e85185ce8..ecf4b41f0309 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/eic.h
@@ -356,7 +356,7 @@ typedef union {
 
 /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint32_t EXTINT0:1;        /*!< bit:      0  External Interrupt 0               */
     __I uint32_t EXTINT1:1;        /*!< bit:      1  External Interrupt 1               */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h
index 9253ef69b08e..a1dae545d5de 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/evsys.h
@@ -478,7 +478,7 @@ typedef union {
 
 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint32_t OVR0:1;           /*!< bit:      0  Channel 0 Overrun                  */
     __I uint32_t OVR1:1;           /*!< bit:      1  Channel 1 Overrun                  */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h
index 38866f83b7ce..ee4dbb84578a 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/i2s.h
@@ -324,7 +324,7 @@ typedef union {
 
 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint16_t RXRDY0:1;         /*!< bit:      0  Receive Ready 0                    */
     __I uint16_t RXRDY1:1;         /*!< bit:      1  Receive Ready 1                    */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
index 5d838b26828e..5d21bfe0e328 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/nvmctrl.h
@@ -249,7 +249,7 @@ typedef union {
 
 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  READY:1;          /*!< bit:      0  NVM Ready                          */
     __I uint8_t  ERROR:1;          /*!< bit:      1  Error                              */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h
index 216668a7a78e..10f90921a016 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/pm.h
@@ -475,7 +475,7 @@ typedef union {
 
 /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  CKRDY:1;          /*!< bit:      0  Clock Ready                        */
     __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h
index 3f9f034b0e68..4a287900873b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/rtc.h
@@ -626,7 +626,7 @@ typedef union {
 
 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
     __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
@@ -657,7 +657,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  CMP0:1;           /*!< bit:      0  Compare 0                          */
     __I uint8_t  CMP1:1;           /*!< bit:      1  Compare 1                          */
@@ -691,7 +691,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W  8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  ALARM0:1;         /*!< bit:      0  Alarm 0                            */
     __I uint8_t  :5;               /*!< bit:  1.. 5  Reserved                           */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h
index 8667a48b434b..c333023f7220 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sercom.h
@@ -537,15 +537,15 @@ typedef union {
   struct {
     uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
   } bit;                       /*!< Structure used for bit  access                  */
-  struct { // FRAC mode
+  struct { /* FRAC mode*/
     uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
     uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
   } FRAC;                      /*!< Structure used for FRAC                         */
-  struct { // FRACFP mode
+  struct { /* FRACFP mode*/
     uint16_t BAUD:13;          /*!< bit:  0..12  Baud Rate Value                    */
     uint16_t FP:3;             /*!< bit: 13..15  Fractional Part                    */
   } FRACFP;                    /*!< Structure used for FRACFP                       */
-  struct { // USARTFP mode
+  struct { /* USARTFP mode*/
     uint16_t BAUD:16;          /*!< bit:  0..15  Baud Rate Value                    */
   } USARTFP;                   /*!< Structure used for USARTFP                      */
   uint16_t reg;                /*!< Type      used for register access              */
@@ -560,7 +560,7 @@ typedef union {
 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos))
 #define SERCOM_USART_BAUD_MASK      0xFFFFul     /**< \brief (SERCOM_USART_BAUD) MASK Register */
 
-// FRAC mode
+/* FRAC mode*/
 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */
 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRAC_BAUD_Pos)
 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos))
@@ -569,7 +569,7 @@ typedef union {
 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos))
 #define SERCOM_USART_BAUD_FRAC_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */
 
-// FRACFP mode
+/* FRACFP mode*/
 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */
 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (0x1FFFul << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)
 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos))
@@ -578,7 +578,7 @@ typedef union {
 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos))
 #define SERCOM_USART_BAUD_FRACFP_MASK 0xFFFFul     /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */
 
-// USARTFP mode
+/* USARTFP mode*/
 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0            /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */
 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (0xFFFFul << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)
 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos))
@@ -838,7 +838,7 @@ typedef union {
 
 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CM I2CM Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  MB:1;             /*!< bit:      0  Master On Bus Interrupt            */
     __I uint8_t  SB:1;             /*!< bit:      1  Slave On Bus Interrupt             */
@@ -862,7 +862,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) I2CS I2CS Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  PREC:1;           /*!< bit:      0  Stop Received Interrupt            */
     __I uint8_t  AMATCH:1;         /*!< bit:      1  Address Match Interrupt            */
@@ -889,7 +889,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) SPI SPI Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
     __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
@@ -919,7 +919,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W  8) USART USART Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  DRE:1;            /*!< bit:      0  Data Register Empty Interrupt      */
     __I uint8_t  TXC:1;            /*!< bit:      1  Transmit Complete Interrupt        */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h
index 4a41633941cc..d4e20ff4c154 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/sysctrl.h
@@ -177,7 +177,7 @@ typedef union {
 
 /* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint32_t XOSCRDY:1;        /*!< bit:      0  XOSC Ready                         */
     __I uint32_t XOSC32KRDY:1;     /*!< bit:      1  XOSC32K Ready                      */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h
index c4b11d34701c..7d4ac8d9b313 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tc.h
@@ -415,7 +415,7 @@ typedef union {
 
 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  OVF:1;            /*!< bit:      0  Overflow                           */
     __I uint8_t  ERR:1;            /*!< bit:      1  Error                              */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h
index 2f92425338c0..081e12e4b445 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc.h
@@ -981,7 +981,7 @@ typedef union {
 
 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
     __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
@@ -1149,17 +1149,17 @@ typedef union {
 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
     uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
     uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
     uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1175,19 +1175,19 @@ typedef union {
 #define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
 #define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
 #define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
 #define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
 #define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
 #define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
 #define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
@@ -1379,17 +1379,17 @@ typedef union {
 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
     uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
     uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
     uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1405,7 +1405,7 @@ typedef union {
 #define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
 #define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
 #define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
 #define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
@@ -1414,7 +1414,7 @@ typedef union {
 #define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
 #define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
 #define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
 #define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
@@ -1423,7 +1423,7 @@ typedef union {
 #define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
 #define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
 #define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
 #define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
@@ -1440,17 +1440,17 @@ typedef union {
 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
     uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
     uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
     uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1466,7 +1466,7 @@ typedef union {
 #define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
 #define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
 #define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
 #define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
@@ -1475,7 +1475,7 @@ typedef union {
 #define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
 #define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
 #define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
 #define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
@@ -1484,7 +1484,7 @@ typedef union {
 #define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
 #define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
 #define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
 #define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
@@ -1679,17 +1679,17 @@ typedef union {
 /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
     uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
     uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
     uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1705,7 +1705,7 @@ typedef union {
 #define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
 #define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
 #define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
@@ -1714,7 +1714,7 @@ typedef union {
 #define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
 #define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
 #define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
@@ -1723,7 +1723,7 @@ typedef union {
 #define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
 #define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
 #define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
@@ -1740,17 +1740,17 @@ typedef union {
 /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
     uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
     uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
     uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1766,7 +1766,7 @@ typedef union {
 #define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
 #define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
 #define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
@@ -1775,7 +1775,7 @@ typedef union {
 #define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
 #define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
 #define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
@@ -1784,7 +1784,7 @@ typedef union {
 #define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
 #define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
 #define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
index 2f92425338c0..081e12e4b445 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/tcc_lighting.h
@@ -981,7 +981,7 @@ typedef union {
 
 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint32_t OVF:1;            /*!< bit:      0  Overflow                           */
     __I uint32_t TRG:1;            /*!< bit:      1  Retrigger                          */
@@ -1149,17 +1149,17 @@ typedef union {
 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t :4;               /*!< bit:  0.. 3  Reserved                           */
     uint32_t COUNT:20;         /*!< bit:  4..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t :5;               /*!< bit:  0.. 4  Reserved                           */
     uint32_t COUNT:19;         /*!< bit:  5..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t :6;               /*!< bit:  0.. 5  Reserved                           */
     uint32_t COUNT:18;         /*!< bit:  6..23  Counter Value                      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1175,19 +1175,19 @@ typedef union {
 #define TCC_COUNT_OFFSET            0x34         /**< \brief (TCC_COUNT offset) Count */
 #define TCC_COUNT_RESETVALUE        0x00000000ul /**< \brief (TCC_COUNT reset_value) Count */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_COUNT_DITH4_COUNT_Pos   4            /**< \brief (TCC_COUNT_DITH4) Counter Value */
 #define TCC_COUNT_DITH4_COUNT_Msk   (0xFFFFFul << TCC_COUNT_DITH4_COUNT_Pos)
 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos))
 #define TCC_COUNT_DITH4_MASK        0x00FFFFF0ul /**< \brief (TCC_COUNT_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_COUNT_DITH5_COUNT_Pos   5            /**< \brief (TCC_COUNT_DITH5) Counter Value */
 #define TCC_COUNT_DITH5_COUNT_Msk   (0x7FFFFul << TCC_COUNT_DITH5_COUNT_Pos)
 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos))
 #define TCC_COUNT_DITH5_MASK        0x00FFFFE0ul /**< \brief (TCC_COUNT_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_COUNT_DITH6_COUNT_Pos   6            /**< \brief (TCC_COUNT_DITH6) Counter Value */
 #define TCC_COUNT_DITH6_COUNT_Msk   (0x3FFFFul << TCC_COUNT_DITH6_COUNT_Pos)
 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos))
@@ -1379,17 +1379,17 @@ typedef union {
 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
     uint32_t PER:20;           /*!< bit:  4..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
     uint32_t PER:19;           /*!< bit:  5..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
     uint32_t PER:18;           /*!< bit:  6..23  Period Value                       */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1405,7 +1405,7 @@ typedef union {
 #define TCC_PER_OFFSET              0x40         /**< \brief (TCC_PER offset) Period */
 #define TCC_PER_RESETVALUE          0xFFFFFFFFul /**< \brief (TCC_PER reset_value) Period */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_PER_DITH4_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */
 #define TCC_PER_DITH4_DITHERCY_Msk  (0xFul << TCC_PER_DITH4_DITHERCY_Pos)
 #define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos))
@@ -1414,7 +1414,7 @@ typedef union {
 #define TCC_PER_DITH4_PER(value)    (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos))
 #define TCC_PER_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_PER_DITH5_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */
 #define TCC_PER_DITH5_DITHERCY_Msk  (0x1Ful << TCC_PER_DITH5_DITHERCY_Pos)
 #define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos))
@@ -1423,7 +1423,7 @@ typedef union {
 #define TCC_PER_DITH5_PER(value)    (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos))
 #define TCC_PER_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_PER_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_PER_DITH6_DITHERCY_Pos  0            /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */
 #define TCC_PER_DITH6_DITHERCY_Msk  (0x3Ful << TCC_PER_DITH6_DITHERCY_Pos)
 #define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos))
@@ -1440,17 +1440,17 @@ typedef union {
 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCY:4;       /*!< bit:  0.. 3  Dithering Cycle Number             */
     uint32_t CC:20;            /*!< bit:  4..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCY:5;       /*!< bit:  0.. 4  Dithering Cycle Number             */
     uint32_t CC:19;            /*!< bit:  5..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCY:6;       /*!< bit:  0.. 5  Dithering Cycle Number             */
     uint32_t CC:18;            /*!< bit:  6..23  Channel Compare/Capture Value      */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1466,7 +1466,7 @@ typedef union {
 #define TCC_CC_OFFSET               0x44         /**< \brief (TCC_CC offset) Compare and Capture */
 #define TCC_CC_RESETVALUE           0x00000000ul /**< \brief (TCC_CC reset_value) Compare and Capture */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_CC_DITH4_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */
 #define TCC_CC_DITH4_DITHERCY_Msk   (0xFul << TCC_CC_DITH4_DITHERCY_Pos)
 #define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos))
@@ -1475,7 +1475,7 @@ typedef union {
 #define TCC_CC_DITH4_CC(value)      (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos))
 #define TCC_CC_DITH4_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_CC_DITH5_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */
 #define TCC_CC_DITH5_DITHERCY_Msk   (0x1Ful << TCC_CC_DITH5_DITHERCY_Pos)
 #define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos))
@@ -1484,7 +1484,7 @@ typedef union {
 #define TCC_CC_DITH5_CC(value)      (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos))
 #define TCC_CC_DITH5_MASK           0x00FFFFFFul /**< \brief (TCC_CC_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_CC_DITH6_DITHERCY_Pos   0            /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */
 #define TCC_CC_DITH6_DITHERCY_Msk   (0x3Ful << TCC_CC_DITH6_DITHERCY_Pos)
 #define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos))
@@ -1679,17 +1679,17 @@ typedef union {
 /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
     uint32_t PERB:20;          /*!< bit:  4..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
     uint32_t PERB:19;          /*!< bit:  5..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
     uint32_t PERB:18;          /*!< bit:  6..23  Period Buffer Value                */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1705,7 +1705,7 @@ typedef union {
 #define TCC_PERB_OFFSET             0x6C         /**< \brief (TCC_PERB offset) Period Buffer */
 #define TCC_PERB_RESETVALUE         0xFFFFFFFFul /**< \brief (TCC_PERB reset_value) Period Buffer */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_PERB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH4_DITHERCYB_Msk (0xFul << TCC_PERB_DITH4_DITHERCYB_Pos)
 #define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos))
@@ -1714,7 +1714,7 @@ typedef union {
 #define TCC_PERB_DITH4_PERB(value)  (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos))
 #define TCC_PERB_DITH4_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_PERB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_PERB_DITH5_DITHERCYB_Pos)
 #define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos))
@@ -1723,7 +1723,7 @@ typedef union {
 #define TCC_PERB_DITH5_PERB(value)  (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos))
 #define TCC_PERB_DITH5_MASK         0x00FFFFFFul /**< \brief (TCC_PERB_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_PERB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */
 #define TCC_PERB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_PERB_DITH6_DITHERCYB_Pos)
 #define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos))
@@ -1740,17 +1740,17 @@ typedef union {
 /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
 typedef union {
-  struct { // DITH4 mode
+  struct { /* DITH4 mode*/
     uint32_t DITHERCYB:4;      /*!< bit:  0.. 3  Dithering Buffer Cycle Number      */
     uint32_t CCB:20;           /*!< bit:  4..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH4;                     /*!< Structure used for DITH4                        */
-  struct { // DITH5 mode
+  struct { /* DITH5 mode*/
     uint32_t DITHERCYB:5;      /*!< bit:  0.. 4  Dithering Buffer Cycle Number      */
     uint32_t CCB:19;           /*!< bit:  5..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
   } DITH5;                     /*!< Structure used for DITH5                        */
-  struct { // DITH6 mode
+  struct { /* DITH6 mode*/
     uint32_t DITHERCYB:6;      /*!< bit:  0.. 5  Dithering Buffer Cycle Number      */
     uint32_t CCB:18;           /*!< bit:  6..23  Channel Compare/Capture Buffer Value */
     uint32_t :8;               /*!< bit: 24..31  Reserved                           */
@@ -1766,7 +1766,7 @@ typedef union {
 #define TCC_CCB_OFFSET              0x70         /**< \brief (TCC_CCB offset) Compare and Capture Buffer */
 #define TCC_CCB_RESETVALUE          0x00000000ul /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */
 
-// DITH4 mode
+/* DITH4 mode*/
 #define TCC_CCB_DITH4_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH4_DITHERCYB_Msk (0xFul << TCC_CCB_DITH4_DITHERCYB_Pos)
 #define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos))
@@ -1775,7 +1775,7 @@ typedef union {
 #define TCC_CCB_DITH4_CCB(value)    (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos))
 #define TCC_CCB_DITH4_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH4) MASK Register */
 
-// DITH5 mode
+/* DITH5 mode*/
 #define TCC_CCB_DITH5_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH5_DITHERCYB_Msk (0x1Ful << TCC_CCB_DITH5_DITHERCYB_Pos)
 #define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos))
@@ -1784,7 +1784,7 @@ typedef union {
 #define TCC_CCB_DITH5_CCB(value)    (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos))
 #define TCC_CCB_DITH5_MASK          0x00FFFFFFul /**< \brief (TCC_CCB_DITH5) MASK Register */
 
-// DITH6 mode
+/* DITH6 mode*/
 #define TCC_CCB_DITH6_DITHERCYB_Pos 0            /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */
 #define TCC_CCB_DITH6_DITHERCYB_Msk (0x3Ful << TCC_CCB_DITH6_DITHERCYB_Pos)
 #define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos))
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h
index 7a3ad226b396..b5ba0eb47b08 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/usb.h
@@ -629,7 +629,7 @@ typedef union {
 
 /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint16_t SUSPEND:1;        /*!< bit:      0  Suspend                            */
     __I uint16_t MSOF:1;           /*!< bit:      1  Micro Start of Frame in High Speed Mode */
@@ -674,7 +674,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint16_t :2;               /*!< bit:  0.. 1  Reserved                           */
     __I uint16_t HSOF:1;           /*!< bit:      2  Host Start Of Frame                */
@@ -1151,7 +1151,7 @@ typedef union {
 
 /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W  8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0                */
     __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1                */
@@ -1203,7 +1203,7 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
 
 /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W  8) HOST HOST_PIPE Pipe Interrupt Flag -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  TRCPT0:1;         /*!< bit:      0  Transfer Complete 0 Interrupt Flag */
     __I uint8_t  TRCPT1:1;         /*!< bit:      1  Transfer Complete 1 Interrupt Flag */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h
index 89f4796c6d02..e44ef6480452 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/component/wdt.h
@@ -229,7 +229,7 @@ typedef union {
 
 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W  8) Interrupt Flag Status and Clear -------- */
 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
-typedef union { // __I to avoid read-modify-write on write-to-clear register
+typedef union { /* __I to avoid read-modify-write on write-to-clear register*/
   struct {
     __I uint8_t  EW:1;             /*!< bit:      0  Early Warning                      */
     __I uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h
index d4ea692e1284..79e49a1fa673 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac.h
@@ -78,10 +78,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for AC peripheral ========== */
-#define AC_CMP_NUM                  2        // Number of comparators
-#define AC_GCLK_ID_ANA              32       // Index of Generic Clock for analog
-#define AC_GCLK_ID_DIG              31       // Index of Generic Clock for digital
-#define AC_NUM_CMP                  2       
-#define AC_PAIRS                    1        // Number of pairs of comparators
+#define AC_CMP_NUM                  2        /* Number of comparators*/
+#define AC_GCLK_ID_ANA              32       /* Index of Generic Clock for analog*/
+#define AC_GCLK_ID_DIG              31       /* Index of Generic Clock for digital*/
+#define AC_NUM_CMP                  2
+#define AC_PAIRS                    1        /* Number of pairs of comparators*/
 
 #endif /* _SAMD21_AC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h
index 02631053a14b..ca9de58785be 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/ac1.h
@@ -78,10 +78,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for AC1 peripheral ========== */
-#define AC1_CMP_NUM                 2        // Number of comparators
-#define AC1_GCLK_ID_ANA             32       // Index of Generic Clock for analog
-#define AC1_GCLK_ID_DIG             31       // Index of Generic Clock for digital
-#define AC1_NUM_CMP                 2       
-#define AC1_PAIRS                   1        // Number of pairs of comparators
+#define AC1_CMP_NUM                 2        /* Number of comparators*/
+#define AC1_GCLK_ID_ANA             32       /* Index of Generic Clock for analog*/
+#define AC1_GCLK_ID_DIG             31       /* Index of Generic Clock for digital*/
+#define AC1_NUM_CMP                 2
+#define AC1_PAIRS                   1        /* Number of pairs of comparators*/
 
 #endif /* _SAMD21_AC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h
index d80c035c44cc..d110465d53e1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/adc.h
@@ -90,10 +90,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for ADC peripheral ========== */
-#define ADC_DMAC_ID_RESRDY          39       // Index of DMA RESRDY trigger
-#define ADC_EXTCHANNEL_MSB          19       // Number of external channels
-#define ADC_GCLK_ID                 30       // Index of Generic Clock
-#define ADC_RESULT_BITS             16       // Size of RESULT.RESULT bitfield
-#define ADC_RESULT_MSB              15       // Size of Result
+#define ADC_DMAC_ID_RESRDY          39       /* Index of DMA RESRDY trigger*/
+#define ADC_EXTCHANNEL_MSB          19       /* Number of external channels*/
+#define ADC_GCLK_ID                 30       /* Index of Generic Clock*/
+#define ADC_RESULT_BITS             16       /* Size of RESULT.RESULT bitfield*/
+#define ADC_RESULT_MSB              15       /* Size of Result*/
 
 #endif /* _SAMD21_ADC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h
index dad52f7a1a44..cc8ecb84c586 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dac.h
@@ -68,7 +68,7 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for DAC peripheral ========== */
-#define DAC_DMAC_ID_EMPTY           40       // Index of DMAC EMPTY trigger
-#define DAC_GCLK_ID                 33       // Index of Generic Clock
+#define DAC_DMAC_ID_EMPTY           40       /* Index of DMAC EMPTY trigger*/
+#define DAC_GCLK_ID                 33       /* Index of Generic Clock*/
 
 #endif /* _SAMD21_DAC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h
index efa83a506ed4..b64d6da4fcfa 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dmac.h
@@ -96,14 +96,14 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for DMAC peripheral ========== */
-#define DMAC_CH_BITS                4        // Number of bits to select channel
-#define DMAC_CH_NUM                 12       // Number of channels
-#define DMAC_CLK_AHB_ID             5        // AHB clock index
-#define DMAC_EVIN_NUM               4        // Number of input events
-#define DMAC_EVOUT_NUM              4        // Number of output events
-#define DMAC_LVL_BITS               2        // Number of bit to select level priority
-#define DMAC_LVL_NUM                4        // Enable priority level number
-#define DMAC_TRIG_BITS              6        // Number of bits to select trigger source
-#define DMAC_TRIG_NUM               45       // Number of peripheral triggers
+#define DMAC_CH_BITS                4        /* Number of bits to select channel*/
+#define DMAC_CH_NUM                 12       /* Number of channels*/
+#define DMAC_CLK_AHB_ID             5        /* AHB clock index*/
+#define DMAC_EVIN_NUM               4        /* Number of input events*/
+#define DMAC_EVOUT_NUM              4        /* Number of output events*/
+#define DMAC_LVL_BITS               2        /* Number of bit to select level priority*/
+#define DMAC_LVL_NUM                4        /* Enable priority level number*/
+#define DMAC_TRIG_BITS              6        /* Number of bits to select trigger source*/
+#define DMAC_TRIG_NUM               45       /* Number of peripheral triggers*/
 
 #endif /* _SAMD21_DMAC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h
index 79395ceba416..f0c819c80ebb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/dsu.h
@@ -94,6 +94,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for DSU peripheral ========== */
-#define DSU_CLK_HSB_ID              3        // Index of AHB clock in PM.AHBMASK register
+#define DSU_CLK_HSB_ID              3        /* Index of AHB clock in PM.AHBMASK register*/
 
 #endif /* _SAMD21_DSU_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h
index ed8fd65974d0..f2f56ca4d906 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/eic.h
@@ -72,7 +72,7 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for EIC peripheral ========== */
-#define EIC_CONFIG_NUM              2        // Number of CONFIG registers
-#define EIC_GCLK_ID                 5        // Index of Generic Clock
+#define EIC_CONFIG_NUM              2        /* Number of CONFIG registers*/
+#define EIC_GCLK_ID                 5        /* Index of Generic Clock*/
 
 #endif /* _SAMD21_EIC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h
index 85573b789126..6fb2dacef860 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/evsys.h
@@ -64,10 +64,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for EVSYS peripheral ========== */
-#define EVSYS_CHANNELS              12       // Number of Channels
-#define EVSYS_CHANNELS_BITS         4        // Number of bits to select Channel
-#define EVSYS_CHANNELS_MSB          11       // Number of Channels - 1
-#define EVSYS_EXTEVT_NUM            0        // Number of External Event Generators
+#define EVSYS_CHANNELS              12       /* Number of Channels*/
+#define EVSYS_CHANNELS_BITS         4        /* Number of bits to select Channel*/
+#define EVSYS_CHANNELS_MSB          11       /* Number of Channels - 1*/
+#define EVSYS_EXTEVT_NUM            0        /* Number of External Event Generators*/
 #define EVSYS_GCLK_ID_0             7
 #define EVSYS_GCLK_ID_1             8
 #define EVSYS_GCLK_ID_2             9
@@ -83,12 +83,12 @@
 #define EVSYS_GCLK_ID_LSB           7
 #define EVSYS_GCLK_ID_MSB           18
 #define EVSYS_GCLK_ID_SIZE          12
-#define EVSYS_GENERATORS            76       // Total Number of Event Generators
-#define EVSYS_GENERATORS_BITS       7        // Number of bits to select Event Generator
-#define EVSYS_USERS                 31       // Total Number of Event Users
-#define EVSYS_USERS_BITS            5        // Number of bits to select Event User
+#define EVSYS_GENERATORS            76       /* Total Number of Event Generators*/
+#define EVSYS_GENERATORS_BITS       7        /* Number of bits to select Event Generator*/
+#define EVSYS_USERS                 31       /* Total Number of Event Users*/
+#define EVSYS_USERS_BITS            5        /* Number of bits to select Event User*/
 
-// GENERATORS
+/* GENERATORS*/
 #define EVSYS_ID_GEN_RTC_CMP_0      1
 #define EVSYS_ID_GEN_RTC_CMP_1      2
 #define EVSYS_ID_GEN_RTC_OVF        3
@@ -166,7 +166,7 @@
 #define EVSYS_ID_GEN_AC1_COMP_1     75
 #define EVSYS_ID_GEN_AC1_WIN_0      76
 
-// USERS
+/* USERS*/
 #define EVSYS_ID_USER_DMAC_CH_0     0
 #define EVSYS_ID_USER_DMAC_CH_1     1
 #define EVSYS_ID_USER_DMAC_CH_2     2
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h
index e76ddf1e9fbf..c74c101b1e4f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/gclk.h
@@ -60,20 +60,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for GCLK peripheral ========== */
-#define GCLK_GENDIV_BITS            16      
-#define GCLK_GEN_NUM                9        // Number of Generic Clock Generators
-#define GCLK_GEN_NUM_MSB            8        // Number of Generic Clock Generators - 1
-#define GCLK_GEN_SOURCE_NUM_MSB     8        // Number of Generic Clock Sources - 1
-#define GCLK_NUM                    37       // Number of Generic Clock Users
-#define GCLK_SOURCE_DFLL48M         7        // DFLL48M output
-#define GCLK_SOURCE_FDPLL           8        // FDPLL output
-#define GCLK_SOURCE_GCLKGEN1        2        // Generic clock generator 1 output
-#define GCLK_SOURCE_GCLKIN          1        // Generator input pad
-#define GCLK_SOURCE_NUM             9        // Number of Generic Clock Sources
-#define GCLK_SOURCE_OSCULP32K       3        // OSCULP32K oscillator output
-#define GCLK_SOURCE_OSC8M           6        // OSC8M oscillator output
-#define GCLK_SOURCE_OSC32K          4        // OSC32K oscillator outpur
-#define GCLK_SOURCE_XOSC            0        // XOSC oscillator output
-#define GCLK_SOURCE_XOSC32K         5        // XOSC32K oscillator output
+#define GCLK_GENDIV_BITS            16
+#define GCLK_GEN_NUM                9        /* Number of Generic Clock Generators*/
+#define GCLK_GEN_NUM_MSB            8        /* Number of Generic Clock Generators - 1*/
+#define GCLK_GEN_SOURCE_NUM_MSB     8        /* Number of Generic Clock Sources - 1*/
+#define GCLK_NUM                    37       /* Number of Generic Clock Users*/
+#define GCLK_SOURCE_DFLL48M         7        /* DFLL48M output*/
+#define GCLK_SOURCE_FDPLL           8        /* FDPLL output*/
+#define GCLK_SOURCE_GCLKGEN1        2        /* Generic clock generator 1 output*/
+#define GCLK_SOURCE_GCLKIN          1        /* Generator input pad*/
+#define GCLK_SOURCE_NUM             9        /* Number of Generic Clock Sources*/
+#define GCLK_SOURCE_OSCULP32K       3        /* OSCULP32K oscillator output*/
+#define GCLK_SOURCE_OSC8M           6        /* OSC8M oscillator output*/
+#define GCLK_SOURCE_OSC32K          4        /* OSC32K oscillator outpur*/
+#define GCLK_SOURCE_XOSC            0        /* XOSC oscillator output*/
+#define GCLK_SOURCE_XOSC32K         5        /* XOSC32K oscillator output*/
 
 #endif /* _SAMD21_GCLK_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h
index d299a86f7c22..be458b7982d6 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/i2s.h
@@ -72,7 +72,7 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for I2S peripheral ========== */
-#define I2S_CLK_NUM                 2        // Number of clock units
+#define I2S_CLK_NUM                 2        /* Number of clock units*/
 #define I2S_DMAC_ID_RX_0            41
 #define I2S_DMAC_ID_RX_1            42
 #define I2S_DMAC_ID_RX_LSB          41
@@ -88,7 +88,7 @@
 #define I2S_GCLK_ID_LSB             35
 #define I2S_GCLK_ID_MSB             36
 #define I2S_GCLK_ID_SIZE            2
-#define I2S_MAX_SLOTS               8        // Max number of data slots in frame
-#define I2S_SER_NUM                 2        // Number of serializers
+#define I2S_MAX_SLOTS               8        /* Max number of data slots in frame*/
+#define I2S_SER_NUM                 2        /* Number of serializers*/
 
 #endif /* _SAMD21_I2S_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
index 152f2d5ec216..f800d32bf336 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h
@@ -72,21 +72,21 @@
 #define NVMCTRL_AUX1_ADDRESS        0x00806000
 #define NVMCTRL_AUX2_ADDRESS        0x00808000
 #define NVMCTRL_AUX3_ADDRESS        0x0080A000
-#define NVMCTRL_CLK_AHB_ID          4        // Index of AHB Clock in PM.AHBMASK register
+#define NVMCTRL_CLK_AHB_ID          4        /* Index of AHB Clock in PM.AHBMASK register*/
 #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
-#define NVMCTRL_FLASH_SIZE          65536   
+#define NVMCTRL_FLASH_SIZE          65536
 #define NVMCTRL_LOCKBIT_ADDRESS     0x00802000
-#define NVMCTRL_PAGE_HW             32      
-#define NVMCTRL_PAGE_SIZE           64      
-#define NVMCTRL_PAGE_W              16      
-#define NVMCTRL_PMSB                3       
-#define NVMCTRL_PSZ_BITS            6       
-#define NVMCTRL_ROW_PAGES           4       
-#define NVMCTRL_ROW_SIZE            256     
+#define NVMCTRL_PAGE_HW             32
+#define NVMCTRL_PAGE_SIZE           64
+#define NVMCTRL_PAGE_W              16
+#define NVMCTRL_PMSB                3
+#define NVMCTRL_PSZ_BITS            6
+#define NVMCTRL_ROW_PAGES           4
+#define NVMCTRL_ROW_SIZE            256
 #define NVMCTRL_USER_PAGE_ADDRESS   0x00800000
 #define NVMCTRL_USER_PAGE_OFFSET    0x00800000
 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
-#define NVMCTRL_RWWEE_PAGES         32       // Page size
-#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 // Start address of the RWW EEPROM area
+#define NVMCTRL_RWWEE_PAGES         32       /* Page size*/
+#define NVMCTRL_RWW_EEPROM_ADDR     0x00400000 /* Start address of the RWW EEPROM area*/
 
 #endif /* _SAMD21_NVMCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h
index 8af8b0e624e1..7c5db5b883f8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac0.h
@@ -54,6 +54,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC0 peripheral ========== */
-#define PAC0_WPROT_DEFAULT_VAL      0x00000000 // PAC protection mask at reset
+#define PAC0_WPROT_DEFAULT_VAL      0x00000000 /* PAC protection mask at reset*/
 
 #endif /* _SAMD21_PAC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h
index 1b2b6a039f0d..884c8d0ac998 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac1.h
@@ -54,6 +54,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC1 peripheral ========== */
-#define PAC1_WPROT_DEFAULT_VAL      0x00000002 // PAC protection mask at reset
+#define PAC1_WPROT_DEFAULT_VAL      0x00000002 /* PAC protection mask at reset*/
 
 #endif /* _SAMD21_PAC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h
index 32443eec738e..a7624c219413 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pac2.h
@@ -54,6 +54,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PAC2 peripheral ========== */
-#define PAC2_WPROT_DEFAULT_VAL      0x00800000 // PAC protection mask at reset
+#define PAC2_WPROT_DEFAULT_VAL      0x00800000 /* PAC protection mask at reset*/
 
 #endif /* _SAMD21_PAC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h
index 0190be611f26..420967b20dbc 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/pm.h
@@ -80,10 +80,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PM peripheral ========== */
-#define PM_CTRL_MCSEL_DFLL48M       3       
-#define PM_CTRL_MCSEL_GCLK          0       
-#define PM_CTRL_MCSEL_OSC8M         1       
-#define PM_CTRL_MCSEL_XOSC          2       
-#define PM_PM_CLK_APB_NUM           2       
+#define PM_CTRL_MCSEL_DFLL48M       3
+#define PM_CTRL_MCSEL_GCLK          0
+#define PM_CTRL_MCSEL_OSC8M         1
+#define PM_CTRL_MCSEL_XOSC          2
+#define PM_PM_CLK_APB_NUM           2
 
 #endif /* _SAMD21_PM_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h
index 026730734fa4..0f476d8ee31f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/port.h
@@ -102,35 +102,35 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for PORT peripheral ========== */
-#define PORT_BITS                   64       // Number of PORT pins
-#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for DIR of all pins
-#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for DIR of all pins
-#define PORT_DRVSTR                 1        // DRVSTR supported
-#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } // Default value for DRVSTR of all pins
-#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } // Implementation mask for DRVSTR of all pins
+#define PORT_BITS                   64       /* Number of PORT pins*/
+#define PORT_DIR_DEFAULT_VAL        { 0x00000000, 0x00000000 } /* Default value for DIR of all pins*/
+#define PORT_DIR_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for DIR of all pins*/
+#define PORT_DRVSTR                 1        /* DRVSTR supported*/
+#define PORT_DRVSTR_DEFAULT_VAL     { 0xD8FFFFFF, 0xC0C3FFFF } /* Default value for DRVSTR of all pins*/
+#define PORT_DRVSTR_IMPLEMENTED     { 0xD8FFFFFF, 0xC0C3FFFF } /* Implementation mask for DRVSTR of all pins*/
 #define PORT_EVENT_IMPLEMENTED      { 0x00000000, 0x00000000 }
-#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } // Default value for INEN of all pins
-#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for INEN of all pins
-#define PORT_ODRAIN                 0        // ODRAIN supported
-#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
-#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
-#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } // Default value for OUT of all pins
-#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for OUT of all pins
-#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for all PORT pins
-#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
-#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUX[0] of all pins
-#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[1] of all pins
-#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } // Implementation mask for PMUX[1] of all pins
-#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } // Default value for PMUX[2] of all pins
-#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } // Implementation mask for PMUX[2] of all pins
-#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
-#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
-#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } // Default value for PMUXEN of all pins
-#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PMUXEN of all pins
-#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
-#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } // Implementation mask for PULLEN of all pins
-#define PORT_SLEWLIM                0        // SLEWLIM supported
-#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
-#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
+#define PORT_INEN_DEFAULT_VAL       { 0x00000000, 0x00000000 } /* Default value for INEN of all pins*/
+#define PORT_INEN_IMPLEMENTED       { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for INEN of all pins*/
+#define PORT_ODRAIN                 0        /* ODRAIN supported*/
+#define PORT_ODRAIN_DEFAULT_VAL     { 0x00000000, 0x00000000 } /* Default value for ODRAIN of all pins*/
+#define PORT_ODRAIN_IMPLEMENTED     { 0x00000000, 0x00000000 } /* Implementation mask for ODRAIN of all pins*/
+#define PORT_OUT_DEFAULT_VAL        { 0x00000000, 0x00000000 } /* Default value for OUT of all pins*/
+#define PORT_OUT_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for OUT of all pins*/
+#define PORT_PIN_IMPLEMENTED        { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for all PORT pins*/
+#define PORT_PMUXBIT0_DEFAULT_VAL   { 0x00000000, 0x00000000 } /* Default value for PMUX[0] of all pins*/
+#define PORT_PMUXBIT0_IMPLEMENTED   { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PMUX[0] of all pins*/
+#define PORT_PMUXBIT1_DEFAULT_VAL   { 0x40000000, 0x00000000 } /* Default value for PMUX[1] of all pins*/
+#define PORT_PMUXBIT1_IMPLEMENTED   { 0xDBFFFFF3, 0xC0C3FF0F } /* Implementation mask for PMUX[1] of all pins*/
+#define PORT_PMUXBIT2_DEFAULT_VAL   { 0x40000000, 0x00000000 } /* Default value for PMUX[2] of all pins*/
+#define PORT_PMUXBIT2_IMPLEMENTED   { 0xDBFFFFF7, 0xC0C3FF0F } /* Implementation mask for PMUX[2] of all pins*/
+#define PORT_PMUXBIT3_DEFAULT_VAL   { 0x00000000, 0x00000000 } /* Default value for PMUX[3] of all pins*/
+#define PORT_PMUXBIT3_IMPLEMENTED   { 0x00000000, 0x00000000 } /* Implementation mask for PMUX[3] of all pins*/
+#define PORT_PMUXEN_DEFAULT_VAL     { 0x64000000, 0x3F3C0000 } /* Default value for PMUXEN of all pins*/
+#define PORT_PMUXEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PMUXEN of all pins*/
+#define PORT_PULLEN_DEFAULT_VAL     { 0x00000000, 0x00000000 } /* Default value for PULLEN of all pins*/
+#define PORT_PULLEN_IMPLEMENTED     { 0xDBFFFFFF, 0xC0C3FFFF } /* Implementation mask for PULLEN of all pins*/
+#define PORT_SLEWLIM                0        /* SLEWLIM supported*/
+#define PORT_SLEWLIM_DEFAULT_VAL    { 0x00000000, 0x00000000 } /* Default value for SLEWLIM of all pins*/
+#define PORT_SLEWLIM_IMPLEMENTED    { 0x00000000, 0x00000000 } /* Implementation mask for SLEWLIM of all pins*/
 
 #endif /* _SAMD21_PORT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h
index 36f16449c7c7..c5d66dc0bdbb 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/rtc.h
@@ -106,12 +106,12 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for RTC peripheral ========== */
-#define RTC_ALARM_NUM               1        // Number of Alarms
-#define RTC_COMP16_NUM              2        // Number of 16-bit Comparators
-#define RTC_COMP32_NUM              1        // Number of 32-bit Comparators
-#define RTC_GCLK_ID                 4        // Index of Generic Clock
-#define RTC_NUM_OF_ALARMS           1        // Number of Alarms (obsolete)
-#define RTC_NUM_OF_COMP16           2        // Number of 16-bit Comparators (obsolete)
-#define RTC_NUM_OF_COMP32           1        // Number of 32-bit Comparators (obsolete)
+#define RTC_ALARM_NUM               1        /* Number of Alarms*/
+#define RTC_COMP16_NUM              2        /* Number of 16-bit Comparators*/
+#define RTC_COMP32_NUM              1        /* Number of 32-bit Comparators*/
+#define RTC_GCLK_ID                 4        /* Index of Generic Clock*/
+#define RTC_NUM_OF_ALARMS           1        /* Number of Alarms (obsolete)*/
+#define RTC_NUM_OF_COMP16           2        /* Number of 16-bit Comparators (obsolete)*/
+#define RTC_NUM_OF_COMP32           1        /* Number of 32-bit Comparators (obsolete)*/
 
 #endif /* _SAMD21_RTC_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
index fa9d0b849973..1cf5cbd9d5da 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sbmatrix.h
@@ -146,7 +146,7 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SBMATRIX peripheral ========== */
-#define SBMATRIX_DEFINED                    
+#define SBMATRIX_DEFINED
 /* ========== Instance parameters for SBMATRIX ========== */
 #define SBMATRIX_SLAVE_FLASH        0
 #define SBMATRIX_SLAVE_HPB0         1
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h
index 275ce8c1fcbd..42c3cb2dff1c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom0.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM0 peripheral ========== */
-#define SERCOM0_DMAC_ID_RX          1        // Index of DMA RX trigger
-#define SERCOM0_DMAC_ID_TX          2        // Index of DMA TX trigger
-#define SERCOM0_GCLK_ID_CORE        20       // Index of Generic Clock for Core
-#define SERCOM0_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM0_INT_MSB             6       
+#define SERCOM0_DMAC_ID_RX          1        /* Index of DMA RX trigger*/
+#define SERCOM0_DMAC_ID_TX          2        /* Index of DMA TX trigger*/
+#define SERCOM0_GCLK_ID_CORE        20       /* Index of Generic Clock for Core*/
+#define SERCOM0_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM0_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h
index c661025b258d..aba1176b99f1 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom1.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM1 peripheral ========== */
-#define SERCOM1_DMAC_ID_RX          3        // Index of DMA RX trigger
-#define SERCOM1_DMAC_ID_TX          4        // Index of DMA TX trigger
-#define SERCOM1_GCLK_ID_CORE        21       // Index of Generic Clock for Core
-#define SERCOM1_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM1_INT_MSB             6       
+#define SERCOM1_DMAC_ID_RX          3        /* Index of DMA RX trigger*/
+#define SERCOM1_DMAC_ID_TX          4        /* Index of DMA TX trigger*/
+#define SERCOM1_GCLK_ID_CORE        21       /* Index of Generic Clock for Core*/
+#define SERCOM1_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM1_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h
index 3dc3043a0451..0e1b065a4355 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom2.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM2 peripheral ========== */
-#define SERCOM2_DMAC_ID_RX          5        // Index of DMA RX trigger
-#define SERCOM2_DMAC_ID_TX          6        // Index of DMA TX trigger
-#define SERCOM2_GCLK_ID_CORE        22       // Index of Generic Clock for Core
-#define SERCOM2_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM2_INT_MSB             6       
+#define SERCOM2_DMAC_ID_RX          5        /* Index of DMA RX trigger*/
+#define SERCOM2_DMAC_ID_TX          6        /* Index of DMA TX trigger*/
+#define SERCOM2_GCLK_ID_CORE        22       /* Index of Generic Clock for Core*/
+#define SERCOM2_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM2_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h
index 9aef2593349d..1c6b2e99da96 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom3.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM3 peripheral ========== */
-#define SERCOM3_DMAC_ID_RX          7        // Index of DMA RX trigger
-#define SERCOM3_DMAC_ID_TX          8        // Index of DMA TX trigger
-#define SERCOM3_GCLK_ID_CORE        23       // Index of Generic Clock for Core
-#define SERCOM3_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM3_INT_MSB             6       
+#define SERCOM3_DMAC_ID_RX          7        /* Index of DMA RX trigger*/
+#define SERCOM3_DMAC_ID_TX          8        /* Index of DMA TX trigger*/
+#define SERCOM3_GCLK_ID_CORE        23       /* Index of Generic Clock for Core*/
+#define SERCOM3_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM3_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h
index daf636de3b52..70fe073672d8 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom4.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM4 peripheral ========== */
-#define SERCOM4_DMAC_ID_RX          9        // Index of DMA RX trigger
-#define SERCOM4_DMAC_ID_TX          10       // Index of DMA TX trigger
-#define SERCOM4_GCLK_ID_CORE        24       // Index of Generic Clock for Core
-#define SERCOM4_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM4_INT_MSB             6       
+#define SERCOM4_DMAC_ID_RX          9        /* Index of DMA RX trigger*/
+#define SERCOM4_DMAC_ID_TX          10       /* Index of DMA TX trigger*/
+#define SERCOM4_GCLK_ID_CORE        24       /* Index of Generic Clock for Core*/
+#define SERCOM4_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM4_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h
index 86386c78fcb9..be2e0c473701 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sercom5.h
@@ -134,10 +134,10 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SERCOM5 peripheral ========== */
-#define SERCOM5_DMAC_ID_RX          11       // Index of DMA RX trigger
-#define SERCOM5_DMAC_ID_TX          12       // Index of DMA TX trigger
-#define SERCOM5_GCLK_ID_CORE        25       // Index of Generic Clock for Core
-#define SERCOM5_GCLK_ID_SLOW        19       // Index of Generic Clock for SMbus timeout
-#define SERCOM5_INT_MSB             6       
+#define SERCOM5_DMAC_ID_RX          11       /* Index of DMA RX trigger*/
+#define SERCOM5_DMAC_ID_TX          12       /* Index of DMA TX trigger*/
+#define SERCOM5_GCLK_ID_CORE        25       /* Index of Generic Clock for Core*/
+#define SERCOM5_GCLK_ID_SLOW        19       /* Index of Generic Clock for SMbus timeout*/
+#define SERCOM5_INT_MSB             6
 
 #endif /* _SAMD21_SERCOM5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
index 0c38eccb632b..cd296c07d6a2 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/sysctrl.h
@@ -90,32 +90,32 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for SYSCTRL peripheral ========== */
-#define SYSCTRL_BGAP_CALIB_MSB      11      
-#define SYSCTRL_BOD33_CALIB_MSB     5       
-#define SYSCTRL_DFLL48M_COARSE_MSB  5       
-#define SYSCTRL_DFLL48M_FINE_MSB    9       
-#define SYSCTRL_GCLK_ID_DFLL48      0        // Index of Generic Clock for DFLL48
-#define SYSCTRL_GCLK_ID_FDPLL       1        // Index of Generic Clock for DPLL
-#define SYSCTRL_GCLK_ID_FDPLL32K    2        // Index of Generic Clock for DPLL 32K
-#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6       
-#define SYSCTRL_POR33_ENTEST_MSB    1       
-#define SYSCTRL_SYSTEM_CLOCK        1000000  // Initial system clock frequency
-#define SYSCTRL_ULPVREF_DIVLEV_MSB  3       
-#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1       
-#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2       
-#define SYSCTRL_VREF_CONTROL_MSB    48      
-#define SYSCTRL_VREF_STATUS_MSB     7       
-#define SYSCTRL_VREG_LEVEL_MSB      2       
-#define SYSCTRL_BOD12_VERSION       0x112   
-#define SYSCTRL_BOD33_VERSION       0x112   
-#define SYSCTRL_DFLL48M_VERSION     0x301   
-#define SYSCTRL_FDPLL_VERSION       0x111   
-#define SYSCTRL_OSCULP32K_VERSION   0x111   
-#define SYSCTRL_OSC8M_VERSION       0x120   
-#define SYSCTRL_OSC32K_VERSION      0x112   
-#define SYSCTRL_VREF_VERSION        0x201   
-#define SYSCTRL_VREG_VERSION        0x201   
-#define SYSCTRL_XOSC_VERSION        0x114   
-#define SYSCTRL_XOSC32K_VERSION     0x113   
+#define SYSCTRL_BGAP_CALIB_MSB      11
+#define SYSCTRL_BOD33_CALIB_MSB     5
+#define SYSCTRL_DFLL48M_COARSE_MSB  5
+#define SYSCTRL_DFLL48M_FINE_MSB    9
+#define SYSCTRL_GCLK_ID_DFLL48      0        /* Index of Generic Clock for DFLL48*/
+#define SYSCTRL_GCLK_ID_FDPLL       1        /* Index of Generic Clock for DPLL*/
+#define SYSCTRL_GCLK_ID_FDPLL32K    2        /* Index of Generic Clock for DPLL 32K*/
+#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
+#define SYSCTRL_POR33_ENTEST_MSB    1
+#define SYSCTRL_SYSTEM_CLOCK        1000000  /* Initial system clock frequency*/
+#define SYSCTRL_ULPVREF_DIVLEV_MSB  3
+#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
+#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
+#define SYSCTRL_VREF_CONTROL_MSB    48
+#define SYSCTRL_VREF_STATUS_MSB     7
+#define SYSCTRL_VREG_LEVEL_MSB      2
+#define SYSCTRL_BOD12_VERSION       0x112
+#define SYSCTRL_BOD33_VERSION       0x112
+#define SYSCTRL_DFLL48M_VERSION     0x301
+#define SYSCTRL_FDPLL_VERSION       0x111
+#define SYSCTRL_OSCULP32K_VERSION   0x111
+#define SYSCTRL_OSC8M_VERSION       0x120
+#define SYSCTRL_OSC32K_VERSION      0x112
+#define SYSCTRL_VREF_VERSION        0x201
+#define SYSCTRL_VREG_VERSION        0x201
+#define SYSCTRL_XOSC_VERSION        0x114
+#define SYSCTRL_XOSC32K_VERSION     0x113
 
 #endif /* _SAMD21_SYSCTRL_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h
index b5b100854d4e..322081dd1324 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc3.h
@@ -92,20 +92,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TC3 peripheral ========== */
-#define TC3_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC3_CC16_NUM                2        // Number of 16-bit Counters
-#define TC3_CC32_NUM                2        // Number of 32-bit Counters
-#define TC3_DITHERING_EXT           0        // Dithering feature implemented
+#define TC3_CC8_NUM                 2        /* Number of 8-bit Counters*/
+#define TC3_CC16_NUM                2        /* Number of 16-bit Counters*/
+#define TC3_CC32_NUM                2        /* Number of 32-bit Counters*/
+#define TC3_DITHERING_EXT           0        /* Dithering feature implemented*/
 #define TC3_DMAC_ID_MC_0            25
 #define TC3_DMAC_ID_MC_1            26
 #define TC3_DMAC_ID_MC_LSB          25
 #define TC3_DMAC_ID_MC_MSB          26
 #define TC3_DMAC_ID_MC_SIZE         2
-#define TC3_DMAC_ID_OVF             24       // Indexes of DMA Overflow trigger
-#define TC3_GCLK_ID                 27       // Index of Generic Clock
-#define TC3_MASTER                  0       
-#define TC3_OW_NUM                  2        // Number of Output Waveforms
-#define TC3_PERIOD_EXT              0        // Period feature implemented
-#define TC3_SHADOW_EXT              0        // Shadow feature implemented
+#define TC3_DMAC_ID_OVF             24       /* Indexes of DMA Overflow trigger*/
+#define TC3_GCLK_ID                 27       /* Index of Generic Clock*/
+#define TC3_MASTER                  0
+#define TC3_OW_NUM                  2        /* Number of Output Waveforms*/
+#define TC3_PERIOD_EXT              0        /* Period feature implemented*/
+#define TC3_SHADOW_EXT              0        /* Shadow feature implemented*/
 
 #endif /* _SAMD21_TC3_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h
index 51d3f19e76af..d622e340d835 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc4.h
@@ -92,20 +92,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TC4 peripheral ========== */
-#define TC4_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC4_CC16_NUM                2        // Number of 16-bit Counters
-#define TC4_CC32_NUM                2        // Number of 32-bit Counters
-#define TC4_DITHERING_EXT           0        // Dithering feature implemented
+#define TC4_CC8_NUM                 2        /* Number of 8-bit Counters*/
+#define TC4_CC16_NUM                2        /* Number of 16-bit Counters*/
+#define TC4_CC32_NUM                2        /* Number of 32-bit Counters*/
+#define TC4_DITHERING_EXT           0        /* Dithering feature implemented*/
 #define TC4_DMAC_ID_MC_0            28
 #define TC4_DMAC_ID_MC_1            29
 #define TC4_DMAC_ID_MC_LSB          28
 #define TC4_DMAC_ID_MC_MSB          29
 #define TC4_DMAC_ID_MC_SIZE         2
-#define TC4_DMAC_ID_OVF             27       // Indexes of DMA Overflow trigger
-#define TC4_GCLK_ID                 28       // Index of Generic Clock
-#define TC4_MASTER                  1       
-#define TC4_OW_NUM                  2        // Number of Output Waveforms
-#define TC4_PERIOD_EXT              0        // Period feature implemented
-#define TC4_SHADOW_EXT              0        // Shadow feature implemented
+#define TC4_DMAC_ID_OVF             27       /* Indexes of DMA Overflow trigger*/
+#define TC4_GCLK_ID                 28       /* Index of Generic Clock*/
+#define TC4_MASTER                  1
+#define TC4_OW_NUM                  2        /* Number of Output Waveforms*/
+#define TC4_PERIOD_EXT              0        /* Period feature implemented*/
+#define TC4_SHADOW_EXT              0        /* Shadow feature implemented*/
 
 #endif /* _SAMD21_TC4_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h
index 1e819163e7ac..4e296716fd1b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc5.h
@@ -92,20 +92,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TC5 peripheral ========== */
-#define TC5_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC5_CC16_NUM                2        // Number of 16-bit Counters
-#define TC5_CC32_NUM                2        // Number of 32-bit Counters
-#define TC5_DITHERING_EXT           0        // Dithering feature implemented
+#define TC5_CC8_NUM                 2        /* Number of 8-bit Counters*/
+#define TC5_CC16_NUM                2        /* Number of 16-bit Counters*/
+#define TC5_CC32_NUM                2        /* Number of 32-bit Counters*/
+#define TC5_DITHERING_EXT           0        /* Dithering feature implemented*/
 #define TC5_DMAC_ID_MC_0            31
 #define TC5_DMAC_ID_MC_1            32
 #define TC5_DMAC_ID_MC_LSB          31
 #define TC5_DMAC_ID_MC_MSB          32
 #define TC5_DMAC_ID_MC_SIZE         2
-#define TC5_DMAC_ID_OVF             30       // Indexes of DMA Overflow trigger
-#define TC5_GCLK_ID                 28       // Index of Generic Clock
-#define TC5_MASTER                  0       
-#define TC5_OW_NUM                  2        // Number of Output Waveforms
-#define TC5_PERIOD_EXT              0        // Period feature implemented
-#define TC5_SHADOW_EXT              0        // Shadow feature implemented
+#define TC5_DMAC_ID_OVF             30       /* Indexes of DMA Overflow trigger*/
+#define TC5_GCLK_ID                 28       /* Index of Generic Clock*/
+#define TC5_MASTER                  0
+#define TC5_OW_NUM                  2        /* Number of Output Waveforms*/
+#define TC5_PERIOD_EXT              0        /* Period feature implemented*/
+#define TC5_SHADOW_EXT              0        /* Shadow feature implemented*/
 
 #endif /* _SAMD21_TC5_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h
index b53e9ff0879f..eaba327ad984 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc6.h
@@ -92,20 +92,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TC6 peripheral ========== */
-#define TC6_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC6_CC16_NUM                2        // Number of 16-bit Counters
-#define TC6_CC32_NUM                2        // Number of 32-bit Counters
-#define TC6_DITHERING_EXT           0        // Dithering feature implemented
+#define TC6_CC8_NUM                 2        /* Number of 8-bit Counters*/
+#define TC6_CC16_NUM                2        /* Number of 16-bit Counters*/
+#define TC6_CC32_NUM                2        /* Number of 32-bit Counters*/
+#define TC6_DITHERING_EXT           0        /* Dithering feature implemented*/
 #define TC6_DMAC_ID_MC_0            34
 #define TC6_DMAC_ID_MC_1            35
 #define TC6_DMAC_ID_MC_LSB          34
 #define TC6_DMAC_ID_MC_MSB          35
 #define TC6_DMAC_ID_MC_SIZE         2
-#define TC6_DMAC_ID_OVF             33       // Indexes of DMA Overflow trigger
-#define TC6_GCLK_ID                 29       // Index of Generic Clock
-#define TC6_MASTER                  1       
-#define TC6_OW_NUM                  2        // Number of Output Waveforms
-#define TC6_PERIOD_EXT              0        // Period feature implemented
-#define TC6_SHADOW_EXT              0        // Shadow feature implemented
+#define TC6_DMAC_ID_OVF             33       /* Indexes of DMA Overflow trigger*/
+#define TC6_GCLK_ID                 29       /* Index of Generic Clock*/
+#define TC6_MASTER                  1
+#define TC6_OW_NUM                  2        /* Number of Output Waveforms*/
+#define TC6_PERIOD_EXT              0        /* Period feature implemented*/
+#define TC6_SHADOW_EXT              0        /* Shadow feature implemented*/
 
 #endif /* _SAMD21_TC6_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h
index 40fd453b4ccc..0bed78151a4b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tc7.h
@@ -92,20 +92,20 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TC7 peripheral ========== */
-#define TC7_CC8_NUM                 2        // Number of 8-bit Counters
-#define TC7_CC16_NUM                2        // Number of 16-bit Counters
-#define TC7_CC32_NUM                2        // Number of 32-bit Counters
-#define TC7_DITHERING_EXT           0        // Dithering feature implemented
+#define TC7_CC8_NUM                 2        /* Number of 8-bit Counters*/
+#define TC7_CC16_NUM                2        /* Number of 16-bit Counters*/
+#define TC7_CC32_NUM                2        /* Number of 32-bit Counters*/
+#define TC7_DITHERING_EXT           0        /* Dithering feature implemented*/
 #define TC7_DMAC_ID_MC_0            37
 #define TC7_DMAC_ID_MC_1            38
 #define TC7_DMAC_ID_MC_LSB          37
 #define TC7_DMAC_ID_MC_MSB          38
 #define TC7_DMAC_ID_MC_SIZE         2
-#define TC7_DMAC_ID_OVF             36       // Indexes of DMA Overflow trigger
-#define TC7_GCLK_ID                 29       // Index of Generic Clock
-#define TC7_MASTER                  0       
-#define TC7_OW_NUM                  2        // Number of Output Waveforms
-#define TC7_PERIOD_EXT              0        // Period feature implemented
-#define TC7_SHADOW_EXT              0        // Shadow feature implemented
+#define TC7_DMAC_ID_OVF             36       /* Indexes of DMA Overflow trigger*/
+#define TC7_GCLK_ID                 29       /* Index of Generic Clock*/
+#define TC7_MASTER                  0
+#define TC7_OW_NUM                  2        /* Number of Output Waveforms*/
+#define TC7_PERIOD_EXT              0        /* Period feature implemented*/
+#define TC7_SHADOW_EXT              0        /* Shadow feature implemented*/
 
 #endif /* _SAMD21_TC7_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h
index 7e26234a5bed..7d93aa3a154b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc0.h
@@ -108,8 +108,8 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TCC0 peripheral ========== */
-#define TCC0_CC_NUM                 4        // Number of Compare/Capture units
-#define TCC0_DITHERING              1        // Dithering feature implemented
+#define TCC0_CC_NUM                 4        /* Number of Compare/Capture units*/
+#define TCC0_DITHERING              1        /* Dithering feature implemented*/
 #define TCC0_DMAC_ID_MC_0           14
 #define TCC0_DMAC_ID_MC_1           15
 #define TCC0_DMAC_ID_MC_2           16
@@ -117,16 +117,16 @@
 #define TCC0_DMAC_ID_MC_LSB         14
 #define TCC0_DMAC_ID_MC_MSB         17
 #define TCC0_DMAC_ID_MC_SIZE        4
-#define TCC0_DMAC_ID_OVF            13       // DMA overflow/underflow/retrigger trigger
-#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented
-#define TCC0_EXT                    31       // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
-#define TCC0_GCLK_ID                26       // Index of Generic Clock
-#define TCC0_MASTER                 0       
-#define TCC0_OTMX                   1        // Output Matrix feature implemented
-#define TCC0_OW_NUM                 8        // Number of Output Waveforms
-#define TCC0_PG                     1        // Pattern Generation feature implemented
-#define TCC0_SIZE                   24      
-#define TCC0_SWAP                   1        // DTI outputs swap feature implemented
-#define TCC0_TYPE                   1        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC0_DMAC_ID_OVF            13       /* DMA overflow/underflow/retrigger trigger*/
+#define TCC0_DTI                    1        /* Dead-Time-Insertion feature implemented*/
+#define TCC0_EXT                    31       /* (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)*/
+#define TCC0_GCLK_ID                26       /* Index of Generic Clock*/
+#define TCC0_MASTER                 0
+#define TCC0_OTMX                   1        /* Output Matrix feature implemented*/
+#define TCC0_OW_NUM                 8        /* Number of Output Waveforms*/
+#define TCC0_PG                     1        /* Pattern Generation feature implemented*/
+#define TCC0_SIZE                   24
+#define TCC0_SWAP                   1        /* DTI outputs swap feature implemented*/
+#define TCC0_TYPE                   1        /* TCC type 0 : NA, 1 : Master, 2 : Slave*/
 
 #endif /* _SAMD21_TCC0_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h
index fdf00b3ceb8b..d876037194b5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc1.h
@@ -98,23 +98,23 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TCC1 peripheral ========== */
-#define TCC1_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC1_DITHERING              1        // Dithering feature implemented
+#define TCC1_CC_NUM                 2        /* Number of Compare/Capture units*/
+#define TCC1_DITHERING              1        /* Dithering feature implemented*/
 #define TCC1_DMAC_ID_MC_0           19
 #define TCC1_DMAC_ID_MC_1           20
 #define TCC1_DMAC_ID_MC_LSB         19
 #define TCC1_DMAC_ID_MC_MSB         20
 #define TCC1_DMAC_ID_MC_SIZE        2
-#define TCC1_DMAC_ID_OVF            18       // DMA overflow/underflow/retrigger trigger
-#define TCC1_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC1_EXT                    24       // Coding of implemented extended features
-#define TCC1_GCLK_ID                26       // Index of Generic Clock
-#define TCC1_MASTER                 1       
-#define TCC1_OTMX                   0        // Output Matrix feature implemented
-#define TCC1_OW_NUM                 4        // Number of Output Waveforms
-#define TCC1_PG                     1        // Pattern Generation feature implemented
-#define TCC1_SIZE                   24      
-#define TCC1_SWAP                   0        // DTI outputs swap feature implemented
-#define TCC1_TYPE                   2        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC1_DMAC_ID_OVF            18       /* DMA overflow/underflow/retrigger trigger*/
+#define TCC1_DTI                    0        /* Dead-Time-Insertion feature implemented*/
+#define TCC1_EXT                    24       /* Coding of implemented extended features*/
+#define TCC1_GCLK_ID                26       /* Index of Generic Clock*/
+#define TCC1_MASTER                 1
+#define TCC1_OTMX                   0        /* Output Matrix feature implemented*/
+#define TCC1_OW_NUM                 4        /* Number of Output Waveforms*/
+#define TCC1_PG                     1        /* Pattern Generation feature implemented*/
+#define TCC1_SIZE                   24
+#define TCC1_SWAP                   0        /* DTI outputs swap feature implemented*/
+#define TCC1_TYPE                   2        /* TCC type 0 : NA, 1 : Master, 2 : Slave*/
 
 #endif /* _SAMD21_TCC1_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h
index 9a2900710479..d9184b837a3f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/tcc2.h
@@ -94,23 +94,23 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for TCC2 peripheral ========== */
-#define TCC2_CC_NUM                 2        // Number of Compare/Capture units
-#define TCC2_DITHERING              0        // Dithering feature implemented
+#define TCC2_CC_NUM                 2        /* Number of Compare/Capture units*/
+#define TCC2_DITHERING              0        /* Dithering feature implemented*/
 #define TCC2_DMAC_ID_MC_0           22
 #define TCC2_DMAC_ID_MC_1           23
 #define TCC2_DMAC_ID_MC_LSB         22
 #define TCC2_DMAC_ID_MC_MSB         23
 #define TCC2_DMAC_ID_MC_SIZE        2
-#define TCC2_DMAC_ID_OVF            21       // DMA overflow/underflow/retrigger trigger
-#define TCC2_DTI                    0        // Dead-Time-Insertion feature implemented
-#define TCC2_EXT                    0        // Coding of implemented extended features
-#define TCC2_GCLK_ID                27       // Index of Generic Clock
-#define TCC2_MASTER                 0       
-#define TCC2_OTMX                   0        // Output Matrix feature implemented
-#define TCC2_OW_NUM                 2        // Number of Output Waveforms
-#define TCC2_PG                     0        // Pattern Generation feature implemented
-#define TCC2_SIZE                   16      
-#define TCC2_SWAP                   0        // DTI outputs swap feature implemented
-#define TCC2_TYPE                   0        // TCC type 0 : NA, 1 : Master, 2 : Slave
+#define TCC2_DMAC_ID_OVF            21       /* DMA overflow/underflow/retrigger trigger*/
+#define TCC2_DTI                    0        /* Dead-Time-Insertion feature implemented*/
+#define TCC2_EXT                    0        /* Coding of implemented extended features*/
+#define TCC2_GCLK_ID                27       /* Index of Generic Clock*/
+#define TCC2_MASTER                 0
+#define TCC2_OTMX                   0        /* Output Matrix feature implemented*/
+#define TCC2_OW_NUM                 2        /* Number of Output Waveforms*/
+#define TCC2_PG                     0        /* Pattern Generation feature implemented*/
+#define TCC2_SIZE                   16
+#define TCC2_SWAP                   0        /* DTI outputs swap feature implemented*/
+#define TCC2_TYPE                   0        /* TCC type 0 : NA, 1 : Master, 2 : Slave*/
 
 #endif /* _SAMD21_TCC2_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h
index 13b08bfbcdd2..3a1f637475e4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/usb.h
@@ -336,9 +336,9 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for USB peripheral ========== */
-#define USB_EPT_NBR                 8        // Number of USB end points (obsolete)
-#define USB_EPT_NUM                 8        // Number of USB end points
-#define USB_GCLK_ID                 6        // Index of Generic Clock
-#define USB_PIPE_NUM                8        // Number of USB pipes
+#define USB_EPT_NBR                 8        /* Number of USB end points (obsolete)*/
+#define USB_EPT_NUM                 8        /* Number of USB end points*/
+#define USB_GCLK_ID                 6        /* Index of Generic Clock*/
+#define USB_PIPE_NUM                8        /* Number of USB pipes*/
 
 #endif /* _SAMD21_USB_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h
index c8ee0e89b763..7f67f4af94af 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/instance/wdt.h
@@ -66,6 +66,6 @@
 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
 
 /* ========== Instance parameters for WDT peripheral ========== */
-#define WDT_GCLK_ID                 3        // Index of Generic Clock
+#define WDT_GCLK_ID                 3        /* Index of Generic Clock*/
 
 #endif /* _SAMD21_WDT_INSTANCE_ */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h
index 405627e39b75..3c5f38c01630 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15a.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E15A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h
index e0d7f89b8b89..5a48ba1e3c54 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15b.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E15B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h
index 712124e8c7f5..c5ade3927553 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15bu.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h
index 63d45a8e6c6b..2c2d41760a14 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e15l.h
@@ -215,7 +215,7 @@ void AC1_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -305,7 +305,7 @@ void AC1_Handler                 ( void );
 /** \defgroup SAMD21E15L_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -314,7 +314,7 @@ void AC1_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -323,7 +323,7 @@ void AC1_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h
index 355a9f70ad42..3df7f71d47aa 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16a.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E16A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h
index 1d9f1b72c7a6..e017f555569b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16b.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E16B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h
index 19b75a0b77fb..8b1a8e0432f9 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16bu.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h
index ea3e71e4a7a8..386389e34d8d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e16l.h
@@ -215,7 +215,7 @@ void AC1_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -305,7 +305,7 @@ void AC1_Handler                 ( void );
 /** \defgroup SAMD21E16L_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -314,7 +314,7 @@ void AC1_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -323,7 +323,7 @@ void AC1_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h
index e4eb4badff65..9beb335e3d2c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e17a.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E17A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h
index 08c0f0c6723d..41d36aeb1337 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21e18a.h
@@ -219,7 +219,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -312,7 +312,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21E18A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -321,7 +321,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -331,7 +331,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h
index 7b280b6c0f5d..23ea6dfe22e5 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15a.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G15A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h
index 0d490fe5dc99..eae24dd41108 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15b.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G15B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h
index d0d9d06a98fc..3ab302fa7459 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g15l.h
@@ -223,7 +223,7 @@ void AC1_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -317,7 +317,7 @@ void AC1_Handler                 ( void );
 /** \defgroup SAMD21G15L_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -326,7 +326,7 @@ void AC1_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -335,7 +335,7 @@ void AC1_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h
index c09b6eb0c2f7..2fbdc59d342b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16a.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G16A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h
index 19220f35f089..71b251f2e6d7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16b.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G16B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h
index 833345ce9895..266cd38b4007 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g16l.h
@@ -223,7 +223,7 @@ void AC1_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -317,7 +317,7 @@ void AC1_Handler                 ( void );
 /** \defgroup SAMD21G16L_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -326,7 +326,7 @@ void AC1_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -335,7 +335,7 @@ void AC1_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h
index 2f8573e5fb29..44e85923b40d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17a.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G17A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h
index 7741063f225c..02f4119702ee 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g17au.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h
index b6b2c5b8f542..bcdc5c26d723 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18a.h
@@ -223,7 +223,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -318,7 +318,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G18A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -327,7 +327,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -337,7 +337,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h
index e111aa7f207b..7caa0a88a20d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21g18au.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h
index 8e582fbc423f..bd709e9fdde7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15a.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J15A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h
index d60dfdce5d37..03e3687c568f 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j15b.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J15B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h
index 8cbf537709ba..2b487d09aded 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16a.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J16A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h
index 97388d8ec3e8..8f25eb156a1b 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j16b.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J16B_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h
index e6397a1ea71d..97db93772aa7 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j17a.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J17A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h
index b23bd6bd698e..f04f8a1368e0 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/include/samd21j18a.h
@@ -227,7 +227,7 @@ void I2S_Handler                 ( void );
  * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  */
 
-#define LITTLE_ENDIAN          1        
+#define LITTLE_ENDIAN          1
 #define __CM0PLUS_REV          1         /*!< Core revision r0p1 */
 #define __MPU_PRESENT          0         /*!< MPU present or not */
 #define __NVIC_PRIO_BITS       2         /*!< Number of bits used for Priority Levels */
@@ -324,7 +324,7 @@ void I2S_Handler                 ( void );
 /** \defgroup SAMD21J18A_id Peripheral Ids Definitions */
 /*@{*/
 
-// Peripheral instances on HPB0 bridge
+/* Peripheral instances on HPB0 bridge*/
 #define ID_PAC0           0 /**< \brief Peripheral Access Controller 0 (PAC0) */
 #define ID_PM             1 /**< \brief Power Manager (PM) */
 #define ID_SYSCTRL        2 /**< \brief System Control (SYSCTRL) */
@@ -333,7 +333,7 @@ void I2S_Handler                 ( void );
 #define ID_RTC            5 /**< \brief Real-Time Counter (RTC) */
 #define ID_EIC            6 /**< \brief External Interrupt Controller (EIC) */
 
-// Peripheral instances on HPB1 bridge
+/* Peripheral instances on HPB1 bridge*/
 #define ID_PAC1          32 /**< \brief Peripheral Access Controller 1 (PAC1) */
 #define ID_DSU           33 /**< \brief Device Service Unit (DSU) */
 #define ID_NVMCTRL       34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
@@ -343,7 +343,7 @@ void I2S_Handler                 ( void );
 #define ID_MTB           38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
 #define ID_SBMATRIX      39 /**< \brief HSB Matrix (SBMATRIX) */
 
-// Peripheral instances on HPB2 bridge
+/* Peripheral instances on HPB2 bridge*/
 #define ID_PAC2          64 /**< \brief Peripheral Access Controller 2 (PAC2) */
 #define ID_EVSYS         65 /**< \brief Event System Interface (EVSYS) */
 #define ID_SERCOM0       66 /**< \brief Serial Communication Interface 0 (SERCOM0) */
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
index d2611b3d57ec..56fce9ad1d86 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c
@@ -234,14 +234,17 @@ void Reset_Handler(void)
         pSrc = &_etext;
         pDest = &_srelocate;
 
-        if (pSrc != pDest) {
-                for (; pDest < &_erelocate;) {
+        if (pSrc != pDest)
+        {
+                for (; pDest < &_erelocate;)
+                {
                         *pDest++ = *pSrc++;
                 }
         }
 
         /* Clear the zero segment */
-        for (pDest = &_szero; pDest < &_ezero;) {
+        for (pDest = &_szero; pDest < &_ezero;)
+        {
                 *pDest++ = 0;
         }
 
@@ -277,6 +280,7 @@ void Reset_Handler(void)
  */
 void Dummy_Handler(void)
 {
-        while (1) {
+        while (1)
+        {
         }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c
index 2e8aae7d8394..abbc83dad77d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c
@@ -254,6 +254,7 @@ void Reset_Handler(void)
  */
 void Dummy_Handler(void)
 {
-        while (1) {
+        while (1)
+        {
         }
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c
index f3ebdc8b768b..73d6897a27d4 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/cmsis/samd21/source/system_samd21.c
@@ -62,9 +62,9 @@ uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Cloc
  */
 void SystemInit(void)
 {
-	// Keep the default device state after reset
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
+    /* Keep the default device state after reset*/
+    SystemCoreClock = __SYSTEM_CLOCK;
+    return;
 }
 
 /**
@@ -75,7 +75,7 @@ void SystemInit(void)
  */
 void SystemCoreClockUpdate(void)
 {
-	// Not implemented
-	SystemCoreClock = __SYSTEM_CLOCK;
-	return;
+    /* Not implemented*/
+    SystemCoreClock = __SYSTEM_CLOCK;
+    return;
 }
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h
index ca488dce9b45..41187d0f7a25 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/compiler.h
@@ -962,66 +962,66 @@ typedef struct
 #define LOW       0
 #define HIGH      1
 
-typedef int8_t                  S8 ;  //!< 8-bit signed integer.
-typedef uint8_t                 U8 ;  //!< 8-bit unsigned integer.
-typedef int16_t                 S16;  //!< 16-bit signed integer.
-typedef uint16_t                U16;  //!< 16-bit unsigned integer.
-typedef int32_t                 S32;  //!< 32-bit signed integer.
-typedef uint32_t                U32;  //!< 32-bit unsigned integer.
-typedef int64_t                 S64;  //!< 64-bit signed integer.
-typedef uint64_t                U64;  //!< 64-bit unsigned integer.
-typedef float                   F32;  //!< 32-bit floating-point number.
-typedef double                  F64;  //!< 64-bit floating-point number.
-
-#define  MSB(u16)       (((U8  *)&(u16))[1]) //!< Most significant byte of \a u16.
-#define  LSB(u16)       (((U8  *)&(u16))[0]) //!< Least significant byte of \a u16.
-
-#define  MSH(u32)       (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32.
-#define  LSH(u32)       (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32.
-#define  MSB0W(u32)     (((U8  *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32.
-#define  MSB1W(u32)     (((U8  *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32.
-#define  MSB2W(u32)     (((U8  *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32.
-#define  MSB3W(u32)     (((U8  *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32.
-#define  LSB3W(u32)     MSB0W(u32)           //!< Least significant byte of 4th rank of \a u32.
-#define  LSB2W(u32)     MSB1W(u32)           //!< Least significant byte of 3rd rank of \a u32.
-#define  LSB1W(u32)     MSB2W(u32)           //!< Least significant byte of 2nd rank of \a u32.
-#define  LSB0W(u32)     MSB3W(u32)           //!< Least significant byte of 1st rank of \a u32.
-
-#define  MSW(u64)       (((U32 *)&(u64))[1]) //!< Most significant word of \a u64.
-#define  LSW(u64)       (((U32 *)&(u64))[0]) //!< Least significant word of \a u64.
-#define  MSH0(u64)      (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64.
-#define  MSH1(u64)      (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64.
-#define  MSH2(u64)      (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64.
-#define  MSH3(u64)      (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64.
-#define  LSH3(u64)      MSH0(u64)            //!< Least significant half-word of 4th rank of \a u64.
-#define  LSH2(u64)      MSH1(u64)            //!< Least significant half-word of 3rd rank of \a u64.
-#define  LSH1(u64)      MSH2(u64)            //!< Least significant half-word of 2nd rank of \a u64.
-#define  LSH0(u64)      MSH3(u64)            //!< Least significant half-word of 1st rank of \a u64.
-#define  MSB0D(u64)     (((U8  *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64.
-#define  MSB1D(u64)     (((U8  *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64.
-#define  MSB2D(u64)     (((U8  *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64.
-#define  MSB3D(u64)     (((U8  *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64.
-#define  MSB4D(u64)     (((U8  *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64.
-#define  MSB5D(u64)     (((U8  *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64.
-#define  MSB6D(u64)     (((U8  *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64.
-#define  MSB7D(u64)     (((U8  *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64.
-#define  LSB7D(u64)     MSB0D(u64)           //!< Least significant byte of 8th rank of \a u64.
-#define  LSB6D(u64)     MSB1D(u64)           //!< Least significant byte of 7th rank of \a u64.
-#define  LSB5D(u64)     MSB2D(u64)           //!< Least significant byte of 6th rank of \a u64.
-#define  LSB4D(u64)     MSB3D(u64)           //!< Least significant byte of 5th rank of \a u64.
-#define  LSB3D(u64)     MSB4D(u64)           //!< Least significant byte of 4th rank of \a u64.
-#define  LSB2D(u64)     MSB5D(u64)           //!< Least significant byte of 3rd rank of \a u64.
-#define  LSB1D(u64)     MSB6D(u64)           //!< Least significant byte of 2nd rank of \a u64.
-#define  LSB0D(u64)     MSB7D(u64)           //!< Least significant byte of 1st rank of \a u64.
-
-#define LSB0(u32)           LSB0W(u32)  //!< Least significant byte of 1st rank of \a u32.
-#define LSB1(u32)           LSB1W(u32)  //!< Least significant byte of 2nd rank of \a u32.
-#define LSB2(u32)           LSB2W(u32)  //!< Least significant byte of 3rd rank of \a u32.
-#define LSB3(u32)           LSB3W(u32)  //!< Least significant byte of 4th rank of \a u32.
-#define MSB3(u32)           MSB3W(u32)  //!< Most significant byte of 4th rank of \a u32.
-#define MSB2(u32)           MSB2W(u32)  //!< Most significant byte of 3rd rank of \a u32.
-#define MSB1(u32)           MSB1W(u32)  //!< Most significant byte of 2nd rank of \a u32.
-#define MSB0(u32)           MSB0W(u32)  //!< Most significant byte of 1st rank of \a u32.
+typedef int8_t                  S8 ;  /*!< 8-bit signed integer.*/
+typedef uint8_t                 U8 ;  /*!< 8-bit unsigned integer.*/
+typedef int16_t                 S16;  /*!< 16-bit signed integer.*/
+typedef uint16_t                U16;  /*!< 16-bit unsigned integer.*/
+typedef int32_t                 S32;  /*!< 32-bit signed integer.*/
+typedef uint32_t                U32;  /*!< 32-bit unsigned integer.*/
+typedef int64_t                 S64;  /*!< 64-bit signed integer.*/
+typedef uint64_t                U64;  /*!< 64-bit unsigned integer.*/
+typedef float                   F32;  /*!< 32-bit floating-point number.*/
+typedef double                  F64;  /*!< 64-bit floating-point number.*/
+
+#define  MSB(u16)       (((U8  *)&(u16))[1]) /*!< Most significant byte of \a u16.*/
+#define  LSB(u16)       (((U8  *)&(u16))[0]) /*!< Least significant byte of \a u16.*/
+
+#define  MSH(u32)       (((U16 *)&(u32))[1]) /*!< Most significant half-word of \a u32.*/
+#define  LSH(u32)       (((U16 *)&(u32))[0]) /*!< Least significant half-word of \a u32.*/
+#define  MSB0W(u32)     (((U8  *)&(u32))[3]) /*!< Most significant byte of 1st rank of \a u32.*/
+#define  MSB1W(u32)     (((U8  *)&(u32))[2]) /*!< Most significant byte of 2nd rank of \a u32.*/
+#define  MSB2W(u32)     (((U8  *)&(u32))[1]) /*!< Most significant byte of 3rd rank of \a u32.*/
+#define  MSB3W(u32)     (((U8  *)&(u32))[0]) /*!< Most significant byte of 4th rank of \a u32.*/
+#define  LSB3W(u32)     MSB0W(u32)           /*!< Least significant byte of 4th rank of \a u32.*/
+#define  LSB2W(u32)     MSB1W(u32)           /*!< Least significant byte of 3rd rank of \a u32.*/
+#define  LSB1W(u32)     MSB2W(u32)           /*!< Least significant byte of 2nd rank of \a u32.*/
+#define  LSB0W(u32)     MSB3W(u32)           /*!< Least significant byte of 1st rank of \a u32.*/
+
+#define  MSW(u64)       (((U32 *)&(u64))[1]) /*!< Most significant word of \a u64.*/
+#define  LSW(u64)       (((U32 *)&(u64))[0]) /*!< Least significant word of \a u64.*/
+#define  MSH0(u64)      (((U16 *)&(u64))[3]) /*!< Most significant half-word of 1st rank of \a u64.*/
+#define  MSH1(u64)      (((U16 *)&(u64))[2]) /*!< Most significant half-word of 2nd rank of \a u64.*/
+#define  MSH2(u64)      (((U16 *)&(u64))[1]) /*!< Most significant half-word of 3rd rank of \a u64.*/
+#define  MSH3(u64)      (((U16 *)&(u64))[0]) /*!< Most significant half-word of 4th rank of \a u64.*/
+#define  LSH3(u64)      MSH0(u64)            /*!< Least significant half-word of 4th rank of \a u64.*/
+#define  LSH2(u64)      MSH1(u64)            /*!< Least significant half-word of 3rd rank of \a u64.*/
+#define  LSH1(u64)      MSH2(u64)            /*!< Least significant half-word of 2nd rank of \a u64.*/
+#define  LSH0(u64)      MSH3(u64)            /*!< Least significant half-word of 1st rank of \a u64.*/
+#define  MSB0D(u64)     (((U8  *)&(u64))[7]) /*!< Most significant byte of 1st rank of \a u64.*/
+#define  MSB1D(u64)     (((U8  *)&(u64))[6]) /*!< Most significant byte of 2nd rank of \a u64.*/
+#define  MSB2D(u64)     (((U8  *)&(u64))[5]) /*!< Most significant byte of 3rd rank of \a u64.*/
+#define  MSB3D(u64)     (((U8  *)&(u64))[4]) /*!< Most significant byte of 4th rank of \a u64.*/
+#define  MSB4D(u64)     (((U8  *)&(u64))[3]) /*!< Most significant byte of 5th rank of \a u64.*/
+#define  MSB5D(u64)     (((U8  *)&(u64))[2]) /*!< Most significant byte of 6th rank of \a u64.*/
+#define  MSB6D(u64)     (((U8  *)&(u64))[1]) /*!< Most significant byte of 7th rank of \a u64.*/
+#define  MSB7D(u64)     (((U8  *)&(u64))[0]) /*!< Most significant byte of 8th rank of \a u64.*/
+#define  LSB7D(u64)     MSB0D(u64)           /*!< Least significant byte of 8th rank of \a u64.*/
+#define  LSB6D(u64)     MSB1D(u64)           /*!< Least significant byte of 7th rank of \a u64.*/
+#define  LSB5D(u64)     MSB2D(u64)           /*!< Least significant byte of 6th rank of \a u64.*/
+#define  LSB4D(u64)     MSB3D(u64)           /*!< Least significant byte of 5th rank of \a u64.*/
+#define  LSB3D(u64)     MSB4D(u64)           /*!< Least significant byte of 4th rank of \a u64.*/
+#define  LSB2D(u64)     MSB5D(u64)           /*!< Least significant byte of 3rd rank of \a u64.*/
+#define  LSB1D(u64)     MSB6D(u64)           /*!< Least significant byte of 2nd rank of \a u64.*/
+#define  LSB0D(u64)     MSB7D(u64)           /*!< Least significant byte of 1st rank of \a u64.*/
+
+#define LSB0(u32)           LSB0W(u32)  /*!< Least significant byte of 1st rank of \a u32.*/
+#define LSB1(u32)           LSB1W(u32)  /*!< Least significant byte of 2nd rank of \a u32.*/
+#define LSB2(u32)           LSB2W(u32)  /*!< Least significant byte of 3rd rank of \a u32.*/
+#define LSB3(u32)           LSB3W(u32)  /*!< Least significant byte of 4th rank of \a u32.*/
+#define MSB3(u32)           MSB3W(u32)  /*!< Most significant byte of 4th rank of \a u32.*/
+#define MSB2(u32)           MSB2W(u32)  /*!< Most significant byte of 3rd rank of \a u32.*/
+#define MSB1(u32)           MSB1W(u32)  /*!< Most significant byte of 2nd rank of \a u32.*/
+#define MSB0(u32)           MSB0W(u32)  /*!< Most significant byte of 1st rank of \a u32.*/
 
 #if defined(__ICCARM__)
 #define SHORTENUM           __packed
@@ -1130,17 +1130,17 @@ static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data)
 /* Converts a 4 Byte array into a 32-Bit value */
 static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data)
 {
-	union
-	{
-		uint32_t u32;
-		uint8_t u8[4];
-	}long_addr;
-	uint8_t index;
-	for (index = 0; index < 4; index++)
-	{
-		long_addr.u8[index] = *data++;
-	}
-	return long_addr.u32;
+    union
+    {
+        uint32_t u32;
+        uint8_t u8[4];
+    }long_addr;
+    uint8_t index;
+    for (index = 0; index < 4; index++)
+    {
+        long_addr.u8[index] = *data++;
+    }
+    return long_addr.u32;
 }
 
 /**
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h
index 84feda5a9f52..3bc7cb032861 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/mrecursion.h
@@ -328,7 +328,7 @@
  * \param[in] macro  A binary operation of the form macro(data, n).  This macro
  *                   is expanded by MRECURSION with the current repetition number
  *                   and the auxiliary data argument.
- * \param[in] data   A recursive threshold, building on this to decline by times 
+ * \param[in] data   A recursive threshold, building on this to decline by times
  *                   defined with param count.
  *
  * \return       <tt>macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1)</tt>
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h
index 8576e1e47353..f2dd3d249e03 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/preprocessor.h
@@ -52,4 +52,4 @@
 #include "mrepeat.h"
 #include "mrecursion.h"
 
-#endif  // _PREPROCESSOR_H_
+#endif  /* _PREPROCESSOR_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h
index 340604844051..bfffdba2ed6e 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/stringz.h
@@ -81,4 +81,4 @@
 
 /** @} */
 
-#endif  // _STRINGZ_H_
+#endif  /* _STRINGZ_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h
index b1c77c623d7b..afe2b43a730c 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/preprocessor/tpaste.h
@@ -100,4 +100,4 @@
 
 /** @} */
 
-#endif  // _TPASTE_H_
+#endif  /* _TPASTE_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h
index 6501e7e474ec..d8e323fdf26d 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/status_codes.h
@@ -68,11 +68,11 @@
 
 /** Status code error categories. */
 enum status_categories {
-	STATUS_CATEGORY_OK                = 0x00,
-	STATUS_CATEGORY_COMMON            = 0x10,
-	STATUS_CATEGORY_ANALOG            = 0x30,
-	STATUS_CATEGORY_COM               = 0x40,
-	STATUS_CATEGORY_IO                = 0x50,
+    STATUS_CATEGORY_OK                = 0x00,
+    STATUS_CATEGORY_COMMON            = 0x10,
+    STATUS_CATEGORY_ANALOG            = 0x30,
+    STATUS_CATEGORY_COM               = 0x40,
+    STATUS_CATEGORY_IO                = 0x50,
 };
 
 /**
@@ -85,37 +85,37 @@ enum status_categories {
  * at the same time.
  */
 enum status_code {
-	STATUS_OK                         = STATUS_CATEGORY_OK     | 0x00,
-	STATUS_VALID_DATA                 = STATUS_CATEGORY_OK     | 0x01,
-	STATUS_NO_CHANGE                  = STATUS_CATEGORY_OK     | 0x02,
-	STATUS_ABORTED                    = STATUS_CATEGORY_OK     | 0x04,
-	STATUS_BUSY                       = STATUS_CATEGORY_OK     | 0x05,
-	STATUS_SUSPEND                    = STATUS_CATEGORY_OK     | 0x06,
-
-	STATUS_ERR_IO                     = STATUS_CATEGORY_COMMON | 0x00,
-	STATUS_ERR_REQ_FLUSHED            = STATUS_CATEGORY_COMMON | 0x01,
-	STATUS_ERR_TIMEOUT                = STATUS_CATEGORY_COMMON | 0x02,
-	STATUS_ERR_BAD_DATA               = STATUS_CATEGORY_COMMON | 0x03,
-	STATUS_ERR_NOT_FOUND              = STATUS_CATEGORY_COMMON | 0x04,
-	STATUS_ERR_UNSUPPORTED_DEV        = STATUS_CATEGORY_COMMON | 0x05,
-	STATUS_ERR_NO_MEMORY              = STATUS_CATEGORY_COMMON | 0x06,
-	STATUS_ERR_INVALID_ARG            = STATUS_CATEGORY_COMMON | 0x07,
-	STATUS_ERR_BAD_ADDRESS            = STATUS_CATEGORY_COMMON | 0x08,
-	STATUS_ERR_BAD_FORMAT             = STATUS_CATEGORY_COMMON | 0x0A,
-	STATUS_ERR_BAD_FRQ                = STATUS_CATEGORY_COMMON | 0x0B,
-	STATUS_ERR_DENIED                 = STATUS_CATEGORY_COMMON | 0x0c,
-	STATUS_ERR_ALREADY_INITIALIZED    = STATUS_CATEGORY_COMMON | 0x0d,
-	STATUS_ERR_OVERFLOW               = STATUS_CATEGORY_COMMON | 0x0e,
-	STATUS_ERR_NOT_INITIALIZED        = STATUS_CATEGORY_COMMON | 0x0f,
-
-	STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
-	STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
-
-	STATUS_ERR_BAUDRATE_UNAVAILABLE   = STATUS_CATEGORY_COM    | 0x00,
-	STATUS_ERR_PACKET_COLLISION       = STATUS_CATEGORY_COM    | 0x01,
-	STATUS_ERR_PROTOCOL               = STATUS_CATEGORY_COM    | 0x02,
-
-	STATUS_ERR_PIN_MUX_INVALID        = STATUS_CATEGORY_IO     | 0x00,
+    STATUS_OK                         = STATUS_CATEGORY_OK     | 0x00,
+    STATUS_VALID_DATA                 = STATUS_CATEGORY_OK     | 0x01,
+    STATUS_NO_CHANGE                  = STATUS_CATEGORY_OK     | 0x02,
+    STATUS_ABORTED                    = STATUS_CATEGORY_OK     | 0x04,
+    STATUS_BUSY                       = STATUS_CATEGORY_OK     | 0x05,
+    STATUS_SUSPEND                    = STATUS_CATEGORY_OK     | 0x06,
+
+    STATUS_ERR_IO                     = STATUS_CATEGORY_COMMON | 0x00,
+    STATUS_ERR_REQ_FLUSHED            = STATUS_CATEGORY_COMMON | 0x01,
+    STATUS_ERR_TIMEOUT                = STATUS_CATEGORY_COMMON | 0x02,
+    STATUS_ERR_BAD_DATA               = STATUS_CATEGORY_COMMON | 0x03,
+    STATUS_ERR_NOT_FOUND              = STATUS_CATEGORY_COMMON | 0x04,
+    STATUS_ERR_UNSUPPORTED_DEV        = STATUS_CATEGORY_COMMON | 0x05,
+    STATUS_ERR_NO_MEMORY              = STATUS_CATEGORY_COMMON | 0x06,
+    STATUS_ERR_INVALID_ARG            = STATUS_CATEGORY_COMMON | 0x07,
+    STATUS_ERR_BAD_ADDRESS            = STATUS_CATEGORY_COMMON | 0x08,
+    STATUS_ERR_BAD_FORMAT             = STATUS_CATEGORY_COMMON | 0x0A,
+    STATUS_ERR_BAD_FRQ                = STATUS_CATEGORY_COMMON | 0x0B,
+    STATUS_ERR_DENIED                 = STATUS_CATEGORY_COMMON | 0x0c,
+    STATUS_ERR_ALREADY_INITIALIZED    = STATUS_CATEGORY_COMMON | 0x0d,
+    STATUS_ERR_OVERFLOW               = STATUS_CATEGORY_COMMON | 0x0e,
+    STATUS_ERR_NOT_INITIALIZED        = STATUS_CATEGORY_COMMON | 0x0f,
+
+    STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00,
+    STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01,
+
+    STATUS_ERR_BAUDRATE_UNAVAILABLE   = STATUS_CATEGORY_COM    | 0x00,
+    STATUS_ERR_PACKET_COLLISION       = STATUS_CATEGORY_COM    | 0x01,
+    STATUS_ERR_PROTOCOL               = STATUS_CATEGORY_COM    | 0x02,
+
+    STATUS_ERR_PIN_MUX_INVALID        = STATUS_CATEGORY_IO     | 0x00,
 };
 typedef enum status_code status_code_genare_t;
 
@@ -123,32 +123,32 @@ typedef enum status_code status_code_genare_t;
   Status codes used by MAC stack.
  */
 enum status_code_wireless {
-	//STATUS_OK               =  0, //!< Success
-	ERR_IO_ERROR            =  -1, //!< I/O error
-	ERR_FLUSHED             =  -2, //!< Request flushed from queue
-	ERR_TIMEOUT             =  -3, //!< Operation timed out
-	ERR_BAD_DATA            =  -4, //!< Data integrity check failed
-	ERR_PROTOCOL            =  -5, //!< Protocol error
-	ERR_UNSUPPORTED_DEV     =  -6, //!< Unsupported device
-	ERR_NO_MEMORY           =  -7, //!< Insufficient memory
-	ERR_INVALID_ARG         =  -8, //!< Invalid argument
-	ERR_BAD_ADDRESS         =  -9, //!< Bad address
-	ERR_BUSY                =  -10, //!< Resource is busy
-	ERR_BAD_FORMAT          =  -11, //!< Data format not recognized
-	ERR_NO_TIMER            =  -12, //!< No timer available
-	ERR_TIMER_ALREADY_RUNNING   =  -13, //!< Timer already running
-	ERR_TIMER_NOT_RUNNING   =  -14, //!< Timer not running
-
-	/**
-	 * \brief Operation in progress
-	 *
-	 * This status code is for driver-internal use when an operation
-	 * is currently being performed.
-	 *
-	 * \note Drivers should never return this status code to any
-	 * callers. It is strictly for internal use.
-	 */
-	OPERATION_IN_PROGRESS	= -128,
+    /*STATUS_OK               =  0, //!< Success*/
+    ERR_IO_ERROR            =  -1, /*!< I/O error*/
+    ERR_FLUSHED             =  -2, /*!< Request flushed from queue*/
+    ERR_TIMEOUT             =  -3, /*!< Operation timed out*/
+    ERR_BAD_DATA            =  -4, /*!< Data integrity check failed*/
+    ERR_PROTOCOL            =  -5, /*!< Protocol error*/
+    ERR_UNSUPPORTED_DEV     =  -6, /*!< Unsupported device*/
+    ERR_NO_MEMORY           =  -7, /*!< Insufficient memory*/
+    ERR_INVALID_ARG         =  -8, /*!< Invalid argument*/
+    ERR_BAD_ADDRESS         =  -9, /*!< Bad address*/
+    ERR_BUSY                =  -10, /*!< Resource is busy*/
+    ERR_BAD_FORMAT          =  -11, /*!< Data format not recognized*/
+    ERR_NO_TIMER            =  -12, /*!< No timer available*/
+    ERR_TIMER_ALREADY_RUNNING   =  -13, /*!< Timer already running*/
+    ERR_TIMER_NOT_RUNNING   =  -14, /*!< Timer not running*/
+
+    /**
+     * \brief Operation in progress
+     *
+     * This status code is for driver-internal use when an operation
+     * is currently being performed.
+     *
+     * \note Drivers should never return this status code to any
+     * callers. It is strictly for internal use.
+     */
+    OPERATION_IN_PROGRESS   = -128,
 };
 
 typedef enum status_code_wireless status_code_t;
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c
index 77c7cbd63dfe..cf3975192fec 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/read.c
@@ -60,7 +60,7 @@ extern volatile void *volatile stdio_base;
 void (*ptr_get)(void volatile*, char*);
 
 
-// IAR common implementation
+/* IAR common implementation*/
 #if ( defined(__ICCARM__) )
 
 #include <yfuns.h>
@@ -81,18 +81,20 @@ _STD_BEGIN
  */
 size_t __read(int handle, unsigned char *buffer, size_t size)
 {
-	int nChars = 0;
-	// This implementation only reads from stdin.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDIN) {
-		return _LLIO_ERROR;
-	}
-	for (; size > 0; --size) {
-		ptr_get(stdio_base, (char*)buffer);
-		buffer++;
-		nChars++;
-	}
-	return nChars;
+    int nChars = 0;
+    /* This implementation only reads from stdin.*/
+    /* For all other file handles, it returns failure.*/
+    if (handle != _LLIO_STDIN)
+    {
+        return _LLIO_ERROR;
+    }
+    for (; size > 0; --size)
+    {
+        ptr_get(stdio_base, (char*)buffer);
+        buffer++;
+        nChars++;
+    }
+    return nChars;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -100,8 +102,8 @@ size_t __read(int handle, unsigned char *buffer, size_t size)
  */
 int __close(int handle)
 {
-	UNUSED(handle);
-	return 0;
+    UNUSED(handle);
+    return 0;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -109,8 +111,8 @@ int __close(int handle)
  */
 int remove(const char* val)
 {
-	UNUSED(val);
-	return 0;
+    UNUSED(val);
+    return 0;
 }
 
 /*! \brief This routine is required by IAR DLIB library since EWAVR V6.10
@@ -118,34 +120,36 @@ int remove(const char* val)
  */
 long __lseek(int handle, long val, int val2)
 {
-	UNUSED(handle);
-	UNUSED(val2);
-	return val;
+    UNUSED(handle);
+    UNUSED(val2);
+    return val;
 }
 
 _STD_END
 
-// GCC implementation
+/* GCC implementation*/
 #elif (defined(__GNUC__))
 
 int __attribute__((weak))
-_read (int file, char * ptr, int len); // Remove GCC compiler warning
+_read (int file, char * ptr, int len); /* Remove GCC compiler warning*/
 
 int __attribute__((weak))
 _read (int file, char * ptr, int len)
 {
-	int nChars = 0;
-
-	if (file != 0) {
-		return -1;
-	}
-
-	for (; len > 0; --len) {
-		ptr_get(stdio_base, ptr);
-		ptr++;
-		nChars++;
-	}
-	return nChars;
+    int nChars = 0;
+
+    if (file != 0)
+    {
+        return -1;
+    }
+
+    for (; len > 0; --len)
+    {
+        ptr_get(stdio_base, ptr);
+        ptr++;
+        nChars++;
+    }
+    return nChars;
 }
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h
index 24ae1dae33ac..02a3d619b961 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/stdio_serial/stdio_serial.h
@@ -88,23 +88,23 @@ extern void (*ptr_get)(void volatile*, char*);
  *
  */
 static inline void stdio_serial_init(
-		struct usart_module *const module,
-		usart_inst_t const hw,
-		const struct usart_config *const config)
+        struct usart_module *const module,
+        usart_inst_t const hw,
+        const struct usart_config *const config)
 {
-	stdio_base = (void *)module;
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+    stdio_base = (void *)module;
+    ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+    ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
 
-	usart_serial_init(module, hw, config);
+    usart_serial_init(module, hw, config);
 # if defined(__GNUC__)
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
+    /* Specify that stdout and stdin should not be buffered.*/
+    setbuf(stdout, NULL);
+    setbuf(stdin, NULL);
+    /* Note: Already the case in IAR's Normal DLIB default configuration*/
+    /* and AVR GCC library:*/
+    /* - printf() emits one character at a time.*/
+    /* - getchar() requests only 1 byte to exit.*/
 #  endif
 }
 #endif
@@ -118,23 +118,23 @@ static inline void stdio_serial_init(
  *
  */
 static inline void stdio_serial_init(
-		struct uart_module *const module,
-		Uart * const hw,
-		const struct uart_config *const config)
+        struct uart_module *const module,
+        Uart * const hw,
+        const struct uart_config *const config)
 {
-	stdio_base = (void *)module;
-	ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
-	ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
+    stdio_base = (void *)module;
+    ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar;
+    ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar;
 
-	usart_serial_init(module, hw, config);
+    usart_serial_init(module, hw, config);
 # if defined(__GNUC__)
-	// Specify that stdout and stdin should not be buffered.
-	setbuf(stdout, NULL);
-	setbuf(stdin, NULL);
-	// Note: Already the case in IAR's Normal DLIB default configuration
-	// and AVR GCC library:
-	// - printf() emits one character at a time.
-	// - getchar() requests only 1 byte to exit.
+    /* Specify that stdout and stdin should not be buffered.*/
+    setbuf(stdout, NULL);
+    setbuf(stdin, NULL);
+    /* Note: Already the case in IAR's Normal DLIB default configuration*/
+    /* and AVR GCC library:*/
+    /* - printf() emits one character at a time.*/
+    /* - getchar() requests only 1 byte to exit.*/
 #  endif
 }
 #endif
@@ -147,4 +147,4 @@ static inline void stdio_serial_init(
 }
 #endif
 
-#endif  // _STDIO_SERIAL_H_
+#endif  /* _STDIO_SERIAL_H_*/
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c
index 9ef442a42344..85c5a8187509 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/stdio/write.c
@@ -80,26 +80,30 @@ _STD_BEGIN
  */
 size_t __write(int handle, const unsigned char *buffer, size_t size)
 {
-	size_t nChars = 0;
-
-	if (buffer == 0) {
-		// This means that we should flush internal buffers.
-		return 0;
-	}
-
-	// This implementation only writes to stdout and stderr.
-	// For all other file handles, it returns failure.
-	if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) {
-		return _LLIO_ERROR;
-	}
-
-	for (; size != 0; --size) {
-		if (ptr_put(stdio_base, *buffer++) < 0) {
-			return _LLIO_ERROR;
-		}
-		++nChars;
-	}
-	return nChars;
+    size_t nChars = 0;
+
+    if (buffer == 0)
+    {
+        /* This means that we should flush internal buffers.*/
+        return 0;
+    }
+
+    /* This implementation only writes to stdout and stderr.*/
+    /* For all other file handles, it returns failure.*/
+    if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
+    {
+        return _LLIO_ERROR;
+    }
+
+    for (; size != 0; --size)
+    {
+        if (ptr_put(stdio_base, *buffer++) < 0)
+        {
+            return _LLIO_ERROR;
+        }
+        ++nChars;
+    }
+    return nChars;
 }
 
 _STD_END
@@ -113,19 +117,22 @@ _write (int file, char * ptr, int len);
 int __attribute__((weak))
 _write (int file, char * ptr, int len)
 {
-	int nChars = 0;
-
-	if ((file != 1) && (file != 2) && (file!=3)) {
-		return -1;
-	}
-
-	for (; len != 0; --len) {
-		if (ptr_put(stdio_base, *ptr++) < 0) {
-			return -1;
-		}
-		++nChars;
-	}
-	return nChars;
+    int nChars = 0;
+
+    if ((file != 1) && (file != 2) && (file!=3))
+    {
+        return -1;
+    }
+
+    for (; len != 0; --len)
+    {
+        if (ptr_put(stdio_base, *ptr++) < 0)
+        {
+            return -1;
+        }
+        ++nChars;
+    }
+    return nChars;
 }
 
 #endif
diff --git a/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c b/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c
index d3e2fbf0716c..e74e9f109e45 100644
--- a/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c
+++ b/bsp/samd21/sam_d2x_asflib/sam0/utils/syscalls/gcc/syscalls.c
@@ -69,60 +69,61 @@ extern int _getpid(void);
 
 extern caddr_t _sbrk(int incr)
 {
-	static unsigned char *heap = NULL;
-	unsigned char *prev_heap;
+    static unsigned char *heap = NULL;
+    unsigned char *prev_heap;
 
-	if (heap == NULL) {
-		heap = (unsigned char *)&_end;
-	}
-	prev_heap = heap;
+    if (heap == NULL)
+    {
+        heap = (unsigned char *)&_end;
+    }
+    prev_heap = heap;
 
-	heap += incr;
+    heap += incr;
 
-	return (caddr_t) prev_heap;
+    return (caddr_t) prev_heap;
 }
 
 extern int link(char *old, char *new)
 {
-	return -1;
+    return -1;
 }
 
 extern int _close(int file)
 {
-	return -1;
+    return -1;
 }
 
 extern int _fstat(int file, struct stat *st)
 {
-	st->st_mode = S_IFCHR;
+    st->st_mode = S_IFCHR;
 
-	return 0;
+    return 0;
 }
 
 extern int _isatty(int file)
 {
-	return 1;
+    return 1;
 }
 
 extern int _lseek(int file, int ptr, int dir)
 {
-	return 0;
+    return 0;
 }
 
 extern void _exit(int status)
 {
-	asm("BKPT #0");
-	for (;;);
+    asm("BKPT #0");
+    for (;;);
 }
 
 extern void _kill(int pid, int sig)
 {
-	return;
+    return;
 }
 
 extern int _getpid(void)
 {
-	return -1;
+    return -1;
 }
 
 #ifdef __cplusplus