sv-tute/lessons/1-simple_in_n_out at main · STFleming/sv-tute · GitHub

Name		Name	Last commit message	Last commit date
parent directory ..
.build_files		.build_files
misc		misc
Makefile		Makefile
README.md		README.md
simple_in_n_out.sv		simple_in_n_out.sv
top_tb.sv		top_tb.sv

README.md

Learning outcomes

Understanding of a Verilog module.
Understanding of Verilog ports.
Understanding of combinatorial logic assignments.

Video

Exercise

Edit the file simple_in_n_out.sv so that out_1 is an XOR of all the inputs.
Edit the file simple_in_n_out.sv so that out_2 is the NAND of all the inputs.
Type make in the terminal to run the simulation.
Open wavedump.vcd in gtkwave and verify that your changes are correct.

Exercise hints

Information on the different bitwise operators of Verilog can be found [here].