GC_SiN_TE_1550_8degOxide_BB pin issue

[newmansc2]

This question is directed at the openEBL-2024-10-SiN run. However, I don't see a link to post issues there.

Running functional verification ("V") on a layout with a single GC_SiN_TE_1550_8degOxide_BB component produces the following error:

Invalid Pin [TOP]
Invalid pin found. Read more about requirements for components: https://github.com/SiEPIC/SiEPIC-Tools/wiki/Component-and-PCell-Layout
polygon: (9.115,0.575;9.115,0.585;9.125,0.585;9.125,0.575)
The components with the pin problem is: GC_SiN_TE_1550_8degOxide_BB

As a result, it is not possible to connect GC_SiN_TE_1550_8degOxide_BB to a waveguide without generating DRC errors.

[newmansc2]

Also note that due to the vertical size of the GC_SiN_TE_1550_8degOxide_BB component, it is not possible to fit a (4) element vertical array within the flooplan.