You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
The problem description is in the pdf file named homework 1.
Submission report of the implementation and explanation of the parts are in the other pdf.
Verilog code and testbench of the homework is provided in this repository.