Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fix links #42

Open
ryanvergel opened this issue Feb 9, 2023 · 1 comment
Open

Fix links #42

ryanvergel opened this issue Feb 9, 2023 · 1 comment
Assignees
@ryanvergel

Comments

@ryanvergel
Copy link
Collaborator

ryanvergel commented Feb 9, 2023 •
edited
Loading

Xilinx/Vitis-Tutorials#112

The ref_design <https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT/ref_files/design1>_ for this example provides not only the source code for applications, but also a Makefile to run
through the design generation process. To generate the binaries, run the following command:

Immediate-term Solution: Push a copy of docs (check docs-jp & docs-cn with @mkmatsui ) from the 2022.2 branch to the master branch.

Near-term solution: @RebeccaOHagan & @dasmohana will FAR links that have /tree/master/ to use /tree/version/ instead.

Longer-term solution: Maybe create a package or a release?
@ryanvergel ryanvergel self-assigned this Feb 9, 2023
@ryanvergel
Copy link
Collaborator Author

@aakratic

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees

@ryanvergel ryanvergel

Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@ryanvergel