diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
index bf9983a2b..8ddce86b4 100644
--- a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
+++ b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
@@ -1475,12 +1475,8 @@ public void testGetConnectedCellsVersal() {
             Assertions.assertEquals("[processor/zero_flag_flop(BEL: DFF2)]",
                     DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
         }
-        // This design has no site routing for CLK
-        // {
-        //     SitePinInst spi = si.getSitePinInst("CLK");
-        //     Assertions.assertEquals("[]",
-        //             DesignTools.getConnectedCells(spi).stream().map(Cell::toString).sorted().collect(Collectors.toList()).toString());
-        // }
+        // This design has no intra-site routing for CLK so this test
+        // does not check for connected cells as done in other tests
     }
 
     @Test
@@ -1507,12 +1503,8 @@ public void testGetConnectedBELPinsVersal() {
             Assertions.assertEquals("[DFF2.CE]",
                     DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
         }
-        // This design has no site routing for CLK
-        // {
-        //     SitePinInst spi = si.getSitePinInst("CLK");
-        //     Assertions.assertEquals("[]",
-        //             DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
-        // }
+        // This design has no intra-site routing for CLK so this test
+        // does not check for connected cells as done in other tests
     }
 
     @ParameterizedTest