From 5b231317a77c03614691cae4d36d1c56e162d8d3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie.hung@amd.com>
Date: Mon, 23 Dec 2024 23:01:48 -0800
Subject: [PATCH] Tidy up

Signed-off-by: Eddie Hung <eddie.hung@amd.com>
---
 src/com/xilinx/rapidwright/design/DesignTools.java       | 9 +++++++--
 src/com/xilinx/rapidwright/rwroute/RouterHelper.java     | 7 +++----
 .../com/xilinx/rapidwright/design/TestDesignTools.java   | 1 +
 3 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java
index bdc316803..f7f5a8da3 100644
--- a/src/com/xilinx/rapidwright/design/DesignTools.java
+++ b/src/com/xilinx/rapidwright/design/DesignTools.java
@@ -2003,7 +2003,8 @@ public static boolean stampPlacement(Design design, Module stamp, Map<String,Sit
     }
 
     /**
-     * Looks in the site instance for BEL pins connected to this site pin.
+     * Looks in the site instance for used BEL pins connected to this site pin.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The BELPin to examine for connected BEL pins.
      * @param si The SiteInst to examine for connected cells.
      * @param action Perform this action on each connected BELPin.
@@ -2020,6 +2021,7 @@ private static void foreachConnectedBELPin(BELPin pin, SiteInst si, Consumer<BEL
                     p = pip.getInputPin().getSiteConns().get(0);
                     action.accept(p);
                 } else {
+                    // Walk through any used SitePIPs
                     foreachConnectedBELPin(pip.getOutputPin(), si, action);
                 }
             } else {
@@ -2042,7 +2044,8 @@ private static void foreachConnectedBELPin(BELPin pin, SiteInst si, Consumer<BEL
     }
 
     /**
-     * Looks in the site instance for cells connected to this BEL pin and SiteInst.
+     * Looks in the site instance for used cells connected to this BEL pin and SiteInst.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The BELPin to examine for connected cells.
      * @param si The SiteInst to examine for connected cells.
      * @return Set of connected cells to this pin.
@@ -2060,6 +2063,7 @@ public static Set<Cell> getConnectedCells(BELPin pin, SiteInst si) {
 
     /**
      * Looks in the site instance for cells connected to this site pin.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The SitePinInst to examine for connected cells.
      * @return Set of connected cells to this pin.
      */
@@ -2069,6 +2073,7 @@ public static Set<Cell> getConnectedCells(SitePinInst pin) {
 
     /**
      * Looks in the site instance for BEL pins connected to this BEL pin and SiteInst.
+     * Will walk through used SitePIPs and routethru cells (e.g. LUTs, IMR registers, etc.)
      * @param pin The SitePinInst to examine for connected BEL pins.
      * @param si The SiteInst to examine for connected cells.
      * @return Set of BEL pins to this site pin.
diff --git a/src/com/xilinx/rapidwright/rwroute/RouterHelper.java b/src/com/xilinx/rapidwright/rwroute/RouterHelper.java
index 59c5ff10f..329db13a9 100644
--- a/src/com/xilinx/rapidwright/rwroute/RouterHelper.java
+++ b/src/com/xilinx/rapidwright/rwroute/RouterHelper.java
@@ -360,10 +360,9 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
             SiteInst si = spi.getSiteInst();
             String siteWireName = spi.getSiteWireName();
             if (invertLutInputs && spi.isLUTInputPin()) {
-                BELPin spiBelPin = spi.getBELPin();
-                Collection<Cell> connectedCells = DesignTools.getConnectedCells(spiBelPin, si);
+                Collection<Cell> connectedCells = DesignTools.getConnectedCells(spi);
                 if (connectedCells.isEmpty()) {
-                    for (BELPin belPin : si.getSiteWirePins(spiBelPin.getSiteWireName())) {
+                    for (BELPin belPin : si.getSiteWirePins(spi.getSiteWireName())) {
                         if (belPin.isSitePort()) {
                             continue;
                         }
@@ -405,7 +404,7 @@ public static Set<SitePinInst> invertPossibleGndPinsToVccPins(Design design,
                 toInvertPins.add(spi);
                 // Re-paint the intra-site routing from GND to VCC
                 // (no intra site routing will occur during Net.addPin() later)
-                si.routeIntraSiteNet(vccNet, spi.getBELPin(), spiBelPin);
+                si.routeIntraSiteNet(vccNet, spi.getBELPin(), spi.getBELPin());
 
                 for (Cell cell : connectedCells) {
                     // Find the logical pin name
diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
index bf9983a2b..6650248e1 100644
--- a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
+++ b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
@@ -1446,6 +1446,7 @@ public void testGetConnectedBELPins() {
         {
             DesignTools.createMissingSitePinInsts(design, design.getNet("clk"));
             SitePinInst spi = si.getSitePinInst("CLK2");
+            Assertions.assertNull(si.getCell("EF2"));
             Assertions.assertEquals("[EFF.CLK, FFF.CLK, FFF2.CLK, GFF.CLK, GFF2.CLK, HFF.CLK, HFF2.CLK]",
                     DesignTools.getConnectedBELPins(spi).stream().map(BELPin::toString).sorted().collect(Collectors.toList()).toString());
         }