diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java index 382c16eda..2384377ed 100644 --- a/src/com/xilinx/rapidwright/design/DesignTools.java +++ b/src/com/xilinx/rapidwright/design/DesignTools.java @@ -4367,13 +4367,18 @@ public static void addProhibitConstraint(Design design, List belLocation * tied to GND or VCC) when following the Net's PIPs. * A source pin will be marked as being routed if it drives at least one PIP. * @param net Net on which pins are to be updated. + * @return Number of unrouted sink pins on net. */ - public static void updatePinsIsRouted(Net net) { + public static int updatePinsIsRouted(Net net) { + int numUnroutedSinkPins = 0; for (SitePinInst spi : net.getPins()) { spi.setRouted(false); + if (!spi.isOutPin()) { + numUnroutedSinkPins++; + } } if (!net.hasPIPs()) { - return; + return numUnroutedSinkPins; } Map node2spi = new HashMap<>(); @@ -4392,23 +4397,34 @@ public static void updatePinsIsRouted(Net net) { } while (!queue.isEmpty()) { NetTools.NodeTree node = queue.poll(); - SitePinInst spi = node2spi.get(node); + SitePinInst spi = node2spi.remove(node); if (spi != null) { spi.setRouted(true); + if (!spi.isOutPin()) { + assert(numUnroutedSinkPins > 0); + numUnroutedSinkPins--; + } } queue.addAll(node.fanouts); } + return numUnroutedSinkPins; } /** * Update the SitePinInst.isRouted() value of all sink pins in the given * Design. See {@link #updatePinsIsRouted(Net)}. * @param design Design in which pins are to be updated. + * @return Number of unrouted sink pins (not driven by hierarchical ports) across design. */ - public static void updatePinsIsRouted(Design design) { + public static int updatePinsIsRouted(Design design) { + int totalUnroutedSinkPins = 0; for (Net net : design.getNets()) { - updatePinsIsRouted(net); + int numUnroutedSinkPins = updatePinsIsRouted(net); + if (!DesignTools.isNetDrivenByHierPort(net)) { + totalUnroutedSinkPins += numUnroutedSinkPins; + } } + return totalUnroutedSinkPins; } /** diff --git a/test/src/com/xilinx/rapidwright/eco/TestECOTools.java b/test/src/com/xilinx/rapidwright/eco/TestECOTools.java index c8cb113ad..bfd9725ea 100644 --- a/test/src/com/xilinx/rapidwright/eco/TestECOTools.java +++ b/test/src/com/xilinx/rapidwright/eco/TestECOTools.java @@ -187,7 +187,7 @@ public void testConnectNetSwapSinks() { EDIFNetlist netlist = design.getNetlist(); Map> deferredRemovals = new HashMap<>(); - DesignTools.updatePinsIsRouted(design); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design)); // Disconnect the ILA inputs List disconnectPins = new ArrayList<>(); @@ -253,7 +253,7 @@ public void testConnectNetSwapSource() { EDIFNetlist netlist = design.getNetlist(); Map> deferredRemovals = new HashMap<>(); - DesignTools.updatePinsIsRouted(design); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design)); // Disconnect the outputs List disconnectPins = new ArrayList<>(); @@ -386,7 +386,7 @@ public void testCreateCell() { Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp"); EDIFNetlist netlist = design.getNetlist(); - DesignTools.updatePinsIsRouted(design); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design)); EDIFCell reference = netlist.getCell("kcpsm6"); List instNames = Arrays.asList("processor2", "processor3"); @@ -474,7 +474,7 @@ public void testCreateNet() { Design design = RapidWrightDCP.loadDCP("picoblaze_ooc_X10Y235.dcp"); EDIFNetlist netlist = design.getNetlist(); - DesignTools.updatePinsIsRouted(design); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(design)); List netNames = Arrays.asList("processor/foo", "your_program/bar"); ECOTools.createNet(design, netNames); diff --git a/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java b/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java index 5d358408e..2fb12f203 100644 --- a/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java +++ b/test/src/com/xilinx/rapidwright/interchange/TestPhysNetlistWriter.java @@ -331,7 +331,7 @@ public void testSimulateSwappedLutPinsWithRWRoute(String path, @TempDir Path tem inputDesign = null; Assertions.assertTrue(LUTTools.swapLutPinsFromPIPs(outputDesign) > 0); - DesignTools.updatePinsIsRouted(outputDesign); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(outputDesign)); TestRWRoute.assertAllSourcesRoutedFlagSet(outputDesign); TestRWRoute.assertAllPinsRouted(outputDesign); VivadoToolsHelper.assertFullyRouted(outputDesign); diff --git a/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java b/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java index 379dd822d..354cdc7d0 100644 --- a/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java +++ b/test/src/com/xilinx/rapidwright/rwroute/TestGlobalSignalRouting.java @@ -339,7 +339,7 @@ public void testSymmetricClkRouting() { if (node != null) used.add(node); } } - DesignTools.updatePinsIsRouted(net); + Assertions.assertEquals(0, DesignTools.updatePinsIsRouted(net)); for (SitePinInst spi : net.getPins()) { Assertions.assertTrue(spi.isRouted()); }