Simulation waveform

[MFJI]

Hello,
Is it possible to open a waveform for the simulation of the models after FINN? How can I do this? Thank you.

[fpjentzsch]

Hi,
yes, you can use the following attribute on a FINN graph node to generate a .vcd trace file during rtlsim.

node_inst = getCustomOp(SOME_NODE)
node_inst.set_nodeattr("rtlsim_trace", "PATH_TO_VCD_FILE")

You can control the trace depth using an environment variable inside the FINN Docker container: RTLSIM_TRACE_DEPTH=3

You can display the waveworm using a program like gtkwave or some VS Code extension.

[MFJI]

Hello,
Thank you for your reply. I am not sure in which step I should use these code. Is that after I export the onnx file from Breivtas, I use python code to add extra node to the model I just export and I use the model with the extra node in FINN? Should this node be at the end of the model? Thank you.

[auphelia]

Hi @MFJI ,

If you want to save the waveforms per layer during node-by-node rtlsim, you will need to set up an execution yourself. You can enable the tracing for the node like described by @fpjentzsch above and then you can use the rtlsim node-by-node execution, like described in the tfc_end2end_verification.ipynb notebook.

The builder also offers the possibility to save the waveform of the rtlsim of the stitched IP, using this configuration parameter: verify_save_rtlsim_waveforms.

The waveforms then get saved in the output folder, when the verification step is enabled for the stitched IP or in the builder step step_measure_rtlsim_performance.

[MFJI]

Hello,
Thank you for your answer.
I still would like to know whether there is a possibility to have the waveform of the whole neural network from the top level. Thank you.

[auphelia]

Hi @MFJI ,

Yes, the stitched IP is the whole neural network from the top level.

[MFJI]

Hello,

I did it in this way:

import finn.builder.build_dataflow as build
import finn.builder.build_dataflow_config as build_cfg
import os
import shutil

model_file = "xxx.onnx"

final_output_dir = "output_final"

#Delete previous run results if exist
if os.path.exists(final_output_dir):
shutil.rmtree(final_output_dir)
print("Previous run results deleted!")

cfg = build.DataflowBuildConfig(
output_dir = final_output_dir,
mvau_wwidth_max = 80,
target_fps = 1000000,
synth_clk_period_ns = 10.0,
#board = "Pynq-Z2",
fpga_part = "xc7z020clg400-1",
shell_flow_type = build_cfg.ShellFlowType.VIVADO_ZYNQ,
verify_save_rtlsim_waveforms = True,
generate_outputs=[
build_cfg.DataflowOutputType.STITCHED_IP,
build_cfg.DataflowOutputType.RTLSIM_PERFORMANCE,
build_cfg.DataflowOutputType.OOC_SYNTH,
#build_cfg.DataflowOutputType.BITFILE,
#build_cfg.DataflowOutputType.PYNQ_DRIVER,
#build_cfg.DataflowOutputType.DEPLOYMENT_PACKAGE,
]
)

%%time
build.build_dataflow_cfg(model_file, cfg)

But I didn't find any .vcd file in the output_dir. There is a rtlsim_performance.json file under the report folder of the output_dir folder. But there is no .vcd file anywhere. Do you have any ideas what can be wrong? Thank you.

[fpjentzsch]

Hi,
I believe you need to enable the corresponding verification step (STITCHED_IP_RTLSIM) in the DataflowBuildConfig using this parameter:

finn/src/finn/builder/build_dataflow_config.py

Line 198 in ef9bb5f

verify_steps: Optional[List[VerificationStepType]] = None

This tutorial notebook shows how to use these verification steps in general: https://github.com/Xilinx/finn/blob/dev/notebooks/advanced/4_advanced_builder_settings.ipynb