From 05eba862b36717dc2f270a15e6336b4ceac8ae2d Mon Sep 17 00:00:00 2001 From: Hamza Khallouki Date: Thu, 30 Jan 2025 13:56:35 +0000 Subject: [PATCH] fixup! [AIE2P] ISel support for fifo loads --- .../AIE/aie2p/AIE2PInstructionSelector.cpp | 57 +++++--------- .../GlobalIsel/inst-select-fifo-loads.mir | 78 +++++++------------ llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll | 4 +- 3 files changed, 45 insertions(+), 94 deletions(-) diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp index e144ec087edd..0fbd728d4a47 100644 --- a/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp +++ b/llvm/lib/Target/AIE/aie2p/AIE2PInstructionSelector.cpp @@ -21,7 +21,6 @@ #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/IR/IntrinsicsAIE2P.h" #include "llvm/MC/MCContext.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TypeSize.h" #include @@ -91,8 +90,9 @@ class AIE2PInstructionSelector : public AIEBaseInstructionSelector { MachineRegisterInfo &MRI) override; Register createPLFRRegSequence(Register PtrReg, Register FifoReg, Register AvailReg, MachineRegisterInfo &MRI); - bool buildAndConstrainFifoLoadCopies(Register Bfp16Vec, Register Mantissa, - Register Exponent, + bool buildAndConstrainFifoLoadCopies(Register Bfp16VecDst, + Register MantissaDst, + Register ExponentDst, MachineRegisterInfo &MRI); Register createDSRegSequence(Register ModifierReg, Register Incr1Reg, Register Incr2Reg, Register Size1Reg, @@ -1616,13 +1616,13 @@ Register AIE2PInstructionSelector::createPLFRRegSequence( return MI.getReg(0); } bool AIE2PInstructionSelector::buildAndConstrainFifoLoadCopies( - Register Bfp16Vec, Register Mantissa, Register Exponent, + Register Bfp16VecDest, Register MantissaDst, Register ExponentDst, MachineRegisterInfo &MRI) { - auto CopyMI1 = MIB.buildInstr(TargetOpcode::COPY, {Mantissa}, {}) - .addReg(Bfp16Vec, 0, AIE2P::sub_bfp16_x); - auto CopyMI2 = MIB.buildInstr(TargetOpcode::COPY, {Exponent}, {}) - .addReg(Bfp16Vec, 0, AIE2P::sub_bfp16_e); + auto CopyMI1 = MIB.buildInstr(TargetOpcode::COPY, {MantissaDst}, {}) + .addReg(Bfp16VecDest, 0, AIE2P::sub_bfp16_x); + auto CopyMI2 = MIB.buildInstr(TargetOpcode::COPY, {ExponentDst}, {}) + .addReg(Bfp16VecDest, 0, AIE2P::sub_bfp16_e); return constrainOperandRegClass(*MF, TRI, MRI, TII, RBI, *CopyMI2, AIE2P::EXPVEC64RegClass, @@ -2543,7 +2543,7 @@ bool AIE2PInstructionSelector::selectG_STORE(MachineInstr &I, return selectImpl(I, *CoverageInfo); } -unsigned int getLoadFifoOpcode(MachineInstr &I) { +unsigned getLoadFifoOpcode(MachineInstr &I) { switch (cast(I).getIntrinsicID()) { case Intrinsic::aie2p_fifo_ld_fill: return AIE2P::VLDB_FILL_512; @@ -2577,7 +2577,7 @@ unsigned int getLoadFifoOpcode(MachineInstr &I) { } bool AIE2PInstructionSelector::selectVLD_FIFO_FILL(MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_fill); Register PtrOut = I.getOperand(0).getReg(); Register FifoOut = I.getOperand(1).getReg(); @@ -2594,7 +2594,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_FILL(MachineInstr &I, bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_unaligned); Register VecOut = I.getOperand(0).getReg(); Register PtrOut = I.getOperand(1).getReg(); @@ -2612,7 +2612,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_1D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_1d_unaligned); Register VecOut = I.getOperand(0).getReg(); Register PtrOut = I.getOperand(1).getReg(); @@ -2631,7 +2631,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_1D( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_2D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_2d_unaligned); Register VecOut = I.getOperand(0).getReg(); Register PtrOut = I.getOperand(1).getReg(); @@ -2645,8 +2645,6 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_2D( Register SizeReg = I.getOperand(10).getReg(); Register CountIn1Reg = I.getOperand(11).getReg(); Register IncrReg = I.getOperand(12).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, AIE2P::eDCRegClass, MRI)) - return false; Register DReg = createDRegSequence(OffsetReg, IncrReg, SizeReg, CountIn1Reg, MRI); MachineInstrBuilder MI = MIB.buildInstr( @@ -2658,7 +2656,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_2D( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_3D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_3d_unaligned); Register VecOut = I.getOperand(0).getReg(); Register PtrOut = I.getOperand(1).getReg(); @@ -2676,11 +2674,6 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_3D( Register Size2Reg = I.getOperand(14).getReg(); Register CountIn2Reg = I.getOperand(15).getReg(); Register Incr2Reg = I.getOperand(16).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, *TRI.getAddrCountRegClass(), - MRI) || - !RBI.constrainGenericRegister(CountOut2Reg, *TRI.getAddrCountRegClass(), - MRI)) - return false; Register DSReg = createDSRegSequence(OffsetReg, Incr1Reg, Incr2Reg, Size1Reg, CountIn1Reg, Size2Reg, CountIn2Reg, MRI); MachineInstrBuilder MI = MIB.buildInstr( @@ -2693,7 +2686,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_512_3D( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_576_bfp16 || (IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_544_bfp16)); Register PtrOut = I.getOperand(0).getReg(); @@ -2717,7 +2710,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_1D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_576_1d_bfp16 || (IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_544_1d_bfp16)); Register PtrOut = I.getOperand(0).getReg(); @@ -2742,7 +2735,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_1D( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_2D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_576_2d_bfp16 || (IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_544_2d_bfp16)); Register PtrOut = I.getOperand(0).getReg(); @@ -2759,8 +2752,6 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_2D( Register IncrReg = I.getOperand(13).getReg(); Register MantVecOut = I.getOperand(4).getReg(); Register ExpVecOut = I.getOperand(5).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, AIE2P::eDCRegClass, MRI)) - return false; Register DReg = createDRegSequence(OffsetReg, IncrReg, SizeReg, CountIn1Reg, MRI); MachineInstrBuilder MI = @@ -2776,7 +2767,7 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_2D( bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_3D( MachineInstr &I, MachineRegisterInfo &MRI) { - auto IntrinsicID = cast(I).getIntrinsicID(); + unsigned IntrinsicID = cast(I).getIntrinsicID(); assert(IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_576_3d_bfp16 || (IntrinsicID == Intrinsic::aie2p_fifo_ld_pop_544_3d_bfp16)); Register PtrOut = I.getOperand(0).getReg(); @@ -2797,11 +2788,6 @@ bool AIE2PInstructionSelector::selectVLD_FIFO_POP_BFP16_3D( Register Incr2Reg = I.getOperand(17).getReg(); Register MantVecOut = I.getOperand(5).getReg(); Register ExpVecOut = I.getOperand(6).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, *TRI.getAddrCountRegClass(), - MRI) || - !RBI.constrainGenericRegister(CountOut2Reg, *TRI.getAddrCountRegClass(), - MRI)) - return false; Register DSReg = createDSRegSequence(OffsetReg, Incr1Reg, Incr2Reg, Size1Reg, CountIn1Reg, Size2Reg, CountIn2Reg, MRI); MachineInstrBuilder MI = MIB.buildInstr( @@ -4450,8 +4436,6 @@ bool AIE2PInstructionSelector::selectVST_FIFO(MachineInstr &I, Register SizeReg = I.getOperand(9).getReg(); Register CountIn1Reg = I.getOperand(10).getReg(); Register IncrReg = I.getOperand(11).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, AIE2P::eDCRegClass, MRI)) - return false; Register DReg = createDRegSequence(OffsetReg, IncrReg, SizeReg, CountIn1Reg, MRI); @@ -4478,11 +4462,6 @@ bool AIE2PInstructionSelector::selectVST_FIFO(MachineInstr &I, Register CountIn2Reg = I.getOperand(14).getReg(); Register Incr2Reg = I.getOperand(15).getReg(); - if (!RBI.constrainGenericRegister(CountOut1Reg, *TRI.getAddrCountRegClass(), - MRI) || - !RBI.constrainGenericRegister(CountOut2Reg, *TRI.getAddrCountRegClass(), - MRI)) - return false; Register DSReg = createDSRegSequence(OffsetReg, Incr1Reg, Incr2Reg, Size1Reg, CountIn1Reg, Size2Reg, CountIn2Reg, MRI); diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir index a2ee99cc3c19..8a02b3526913 100644 --- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir +++ b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-fifo-loads.mir @@ -14,11 +14,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1 + liveins: ; CHECK-LABEL: name: ld_fill - ; CHECK: liveins: $p0, $p1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[VLDB_FILL_512_:%[0-9]+]]:eps, [[VLDB_FILL_512_1:%[0-9]+]]:eldfiforeg, [[VLDB_FILL_512_2:%[0-9]+]]:erf2 = VLDB_FILL_512 [[DEF]], [[DEF1]], [[DEF2]] @@ -38,11 +36,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1 + liveins: ; CHECK-LABEL: name: pop_unaligned - ; CHECK: liveins: $p0, $p1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[VLDB_POP_512_normal_pop:%[0-9]+]]:vec512, [[VLDB_POP_512_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_512_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_512_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_512_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf @@ -62,11 +58,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1 + liveins: ; CHECK-LABEL: name: pop_544 - ; CHECK: liveins: $p0, $p1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[VLDB_POP_544_normal_pop:%[0-9]+]]:mexb, [[VLDB_POP_544_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_544_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_544_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_544_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf @@ -89,11 +83,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1 + liveins: ; CHECK-LABEL: name: pop_576 - ; CHECK: liveins: $p0, $p1 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[VLDB_POP_576_normal_pop:%[0-9]+]]:mexb, [[VLDB_POP_576_normal_pop1:%[0-9]+]]:eps, [[VLDB_POP_576_normal_pop2:%[0-9]+]]:eldfiforeg, [[VLDB_POP_576_normal_pop3:%[0-9]+]]:erf2 = VLDB_POP_576_normal_pop [[DEF]], [[DEF1]], [[DEF2]], implicit-def $srfifo_uf @@ -116,11 +108,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $r0 + liveins: ; CHECK-LABEL: name: pop_unaligned_1d - ; CHECK: liveins: $p0, $p1, $r0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -141,11 +131,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $r0 + liveins: ; CHECK-LABEL: name: pop_544_1d - ; CHECK: liveins: $p0, $p1, $r0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -171,11 +159,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $r0 + liveins: ; CHECK-LABEL: name: pop_576_1d - ; CHECK: liveins: $p0, $p1, $r0 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -200,11 +186,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $r0, $r1, $r2 + liveins: ; CHECK-LABEL: name: pop_unaligned_2d - ; CHECK: liveins: $p0, $p1, $p2, $r0, $r1, $r2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -233,11 +217,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $r0, $r1, $r2 + liveins: ; CHECK-LABEL: name: pop_544_2d - ; CHECK: liveins: $p0, $p1, $p2, $r0, $r1, $r2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -270,11 +252,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $r0, $r1, $r2 + liveins: ; CHECK-LABEL: name: pop_576_2d - ; CHECK: liveins: $p0, $p1, $p2, $r0, $r1, $r2 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -307,11 +287,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 + liveins: ; CHECK-LABEL: name: pop_unaligned_3d - ; CHECK: liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -345,11 +323,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 + liveins: ; CHECK-LABEL: name: pop_544_3d - ; CHECK: liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF @@ -387,11 +363,9 @@ legalized: true regBankSelected: true body: | bb.1.entry: - liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 + liveins: ; CHECK-LABEL: name: pop_576_3d - ; CHECK: liveins: $p0, $p1, $p2, $p3, $r0, $r1, $r2, $r3, $r4 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF + ; CHECK: [[DEF:%[0-9]+]]:eps = IMPLICIT_DEF ; CHECK-NEXT: [[DEF1:%[0-9]+]]:eldfiforeg = IMPLICIT_DEF ; CHECK-NEXT: [[DEF2:%[0-9]+]]:erf2 = IMPLICIT_DEF ; CHECK-NEXT: [[DEF3:%[0-9]+]]:em = IMPLICIT_DEF diff --git a/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll b/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll index 0396ae6d059e..5614eebfea32 100644 --- a/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll +++ b/llvm/test/CodeGen/AIE/aie2p/fifo-loads.ll @@ -4,7 +4,7 @@ ; See https://llvm.org/LICENSE.txt for license information. ; SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception ; -; (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates +; (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates ; RUN: llc < %s -verify-machineinstrs -mtriple=aie2p | FileCheck %s %struct.v64bfp16ebs8 = type <{ <64 x i8>, <8 x i8> }> @@ -640,8 +640,6 @@ declare { ptr, <32 x i32>, i32, <64 x i8>, <8 x i8> } @llvm.aie2p.fifo.ld.pop.54 declare { ptr, <32 x i32>, i32, i20, <64 x i8>, <8 x i8> } @llvm.aie2p.fifo.ld.pop.544.2d.bfp16(ptr, <32 x i32>, i32, i20, i20, i20, i20) #5 declare { ptr, <32 x i32>, i32, i20, i20, <64 x i8>, <8 x i8> } @llvm.aie2p.fifo.ld.pop.544.3d.bfp16(ptr, <32 x i32>, i32, i20, i20, i20, i20, i20, i20, i20) #5 -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{!"clang version 19.0.0git (git@gitenterprise.xilinx.com:XRLabs/llvm-aie.git 35e685a28ac5e78c6c8a5ab733508f3e0aaedf24)"} !2 = !{!3, !3, i64 0} !3 = !{!"any pointer", !4, i64 0} !4 = !{!"omnipotent char", !5, i64 0}