diff --git a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp index 9890eab5f7e4..151aa586f8c1 100644 --- a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp +++ b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp @@ -832,6 +832,15 @@ void InterBlockScheduling::emitInterBlockTop(BlockState &BS) { // state is also necessary. auto *DedicatedExit = makeDedicatedLoopExit(Loop, BB); if (DedicatedExit == BB) { + + // Trim excedent empty bundles. Empty TopInsert means 1-stage pipeline. + if (!BS.TopInsert.empty()) { + while (BS.TopInsert.back().empty()) { + assert(BS.TopInsert.back().getMetaInstrs().empty()); + BS.TopInsert.pop_back(); + } + } + // If we are in the same BB, just emit. emitBundles(BS.TopInsert, DedicatedExit, DedicatedExit->begin(), /*Move=*/false, /*EmitNops=*/false); diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir index 2990b88b8dec..faf5d88fb6f9 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir @@ -51,7 +51,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; vst wh6, [p2, #32]; nopx ; vbneg_ltz.s8 x3, r25:r24, x1; nopv ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: vst wl6, [p2], #64; nopx ; vband x4, x0, x3 + ; CHECK-NEXT: nopb ; nopa ; vst wl6, [p2], #64; nopx ; vband x4, x0, x3; nopv ; CHECK-NEXT: vband x5, x1, x2 ; CHECK-NEXT: vbor x6, x4, x5 ; CHECK-NEXT: vbneg_ltz.s8 x2, r25:r24, x0 @@ -63,9 +63,6 @@ ; CHECK-NEXT: vst wh6, [p2, #32] ; CHECK-NEXT: vst wl6, [p2], #64 ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16-1.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16-1.mir index 6866f48a3518..51f7b0931268 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16-1.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16-1.mir @@ -78,7 +78,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopxm ; vmac.f bml0, bml0, x10, x5, r29 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopb ; nopa ; nops ; nopxm ; vmac.f bmh3, bmh3, x3, x9, r29 + ; CHECK-NEXT: vmac.f bmh3, bmh3, x3, x9, r29 ; CHECK-NEXT: vmac.f bmh2, bmh2, x10, x9, r29 ; CHECK-NEXT: vmac.f bml3, bml3, x1, x7, r29 ; CHECK-NEXT: vmac.f bml6, bml6, x3, x7, r29 @@ -87,15 +87,6 @@ ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x11, r29 ; CHECK-NEXT: vmac.f bml1, bml1, x3, x11, r29 ; CHECK-NEXT: vmac.f bmh8, bmh8, x10, x11, r29 - ; CHECK-NEXT: nopx - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16.mir index 85064a43cb53..325109402812 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/conv2d_bf16.mir @@ -74,7 +74,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; mov p2, p5; vmac.f bmh5, bmh5, x1, x7, r29 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopa ; nopb ; nopxm ; vmac.f bml2, bml2, x3, x7, r29 + ; CHECK-NEXT: vmac.f bml2, bml2, x3, x7, r29 ; CHECK-NEXT: vmac.f bml4, bml4, x8, x5, r29 ; CHECK-NEXT: vmac.f bmh1, bmh1, x8, x9, r29 ; CHECK-NEXT: vmac.f bmh0, bmh0, x1, x9, r29 @@ -93,9 +93,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-1.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-1.mir index d2e5db47a8e9..34fb40df9b3a 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-1.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-1.mir @@ -73,8 +73,8 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x0, x6, x3, r4; vmac.f bmh0, bmh0, x1, x11, r3 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x8, x11, r3 - ; CHECK-NEXT: nopa ; nopx ; vmac.f bmh2, bmh2, x0, x11, r3 + ; CHECK-NEXT: vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x8, x11, r3 + ; CHECK-NEXT: vmac.f bmh2, bmh2, x0, x11, r3 ; CHECK-NEXT: vshuffle x3, x3, x3, r2; vmac.f bmh3, bmh3, x6, x11, r3 ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x5, r3 ; CHECK-NEXT: vmac.f bmh5, bmh5, x8, x5, r3 @@ -94,7 +94,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-2.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-2.mir index 0cd59c1838d1..0f5200dd62aa 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-2.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-2.mir @@ -73,8 +73,8 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x10, x6, x3, r4; vmac.f bmh0, bmh0, x1, x11, r3 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x0, x11, r3 - ; CHECK-NEXT: nopa ; nopx ; vmac.f bmh2, bmh2, x10, x11, r3 + ; CHECK-NEXT: vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x0, x11, r3 + ; CHECK-NEXT: vmac.f bmh2, bmh2, x10, x11, r3 ; CHECK-NEXT: vshuffle x3, x3, x3, r2; vmac.f bmh3, bmh3, x6, x11, r3 ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x5, r3 ; CHECK-NEXT: vmac.f bmh5, bmh5, x0, x5, r3 @@ -94,7 +94,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-3.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-3.mir index 7be844a699a2..626878424dcd 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-3.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-3.mir @@ -73,8 +73,8 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x0, x6, x3, r4; vmac.f bmh0, bmh0, x1, x11, r3 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x2, x11, r3 - ; CHECK-NEXT: nopa ; nopx ; vmac.f bmh2, bmh2, x0, x11, r3 + ; CHECK-NEXT: vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x2, x11, r3 + ; CHECK-NEXT: vmac.f bmh2, bmh2, x0, x11, r3 ; CHECK-NEXT: vshuffle x3, x3, x3, r2; vmac.f bmh3, bmh3, x6, x11, r3 ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x5, r3 ; CHECK-NEXT: vmac.f bmh5, bmh5, x2, x5, r3 @@ -94,7 +94,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-feasibleRA.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-feasibleRA.mir index 55b804bc9868..ff3118090cd9 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-feasibleRA.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-feasibleRA.mir @@ -78,7 +78,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: vldb.3d wh11, [p1], d1; nopa ; nops ; nopx ; vshuffle x5, x0, x2, r16; vmac.f bml5, bmh2, x5, x11, r2 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopa ; nopb ; nopxm ; vmac.f bmh0, bmh0, x4, x8, r2 + ; CHECK-NEXT: nopa ; nopb ; nopx ; vmac.f bmh0, bmh0, x4, x8, r2 ; CHECK-NEXT: vshuffle x6, x1, x3, r3; vmac.f bmh2, bmh2, x5, x8, r2 ; CHECK-NEXT: vshuffle x7, x1, x3, r16; vmac.f bml6, bmh3, x7, x11, r2 ; CHECK-NEXT: vshuffle x9, x9, x9, r6; vmac.f bmh1, bmh1, x6, x8, r2 @@ -103,13 +103,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nooffset.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nooffset.mir index 7653de7caab9..0dc14d842dcd 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nooffset.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nooffset.mir @@ -80,7 +80,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: vldb.3d wh7, [p1], d1; nopa ; nops ; nopxm ; vmac.f bml6, bml6, x10, x7, r3 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: vshuffle x2, x8, x0, r16; vmac.f bml4, bml4, x9, x7, r3 + ; CHECK-NEXT: nopa ; nopx ; vshuffle x2, x8, x0, r16; vmac.f bml4, bml4, x9, x7, r3 ; CHECK-NEXT: vshuffle x6, x8, x0, r4 ; CHECK-NEXT: vshuffle x9, x1, x3, r16; vmac.f bmh5, bmh5, x2, x5, r3 ; CHECK-NEXT: vshuffle x10, x1, x3, r4; vmac.f bmh4, bmh4, x6, x5, r3 @@ -104,16 +104,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nopresched.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nopresched.mir index 224c8d8cd80a..e6f979f20b82 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nopresched.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-nopresched.mir @@ -62,7 +62,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x10, x1, x3, r3; vmac.f bmh4, bmh4, x6, x5, r2 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopa ; nopb ; nopx ; vshuffle x9, x1, x3, r16; vmac.f bmh5, bmh5, x2, x5, r2 + ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x9, x1, x3, r16; vmac.f bmh5, bmh5, x2, x5, r2 ; CHECK-NEXT: vshuffle x3, x11, x11, r6; vmac.f bmh6, bmh6, x10, x5, r2 ; CHECK-NEXT: vshuffle x0, x0, x0, r6; vmac.f bmh7, bmh7, x9, x5, r2 ; CHECK-NEXT: vshuffle x7, x7, x7, r6; vmac.f bmh0, bmh0, x6, x3, r2 @@ -83,7 +83,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-waw.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-waw.mir index 7d104433c220..9d785e292122 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-waw.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm-waw.mir @@ -76,7 +76,7 @@ ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x10, x6, x3, r4; vmac.f bmh0, bmh0, x1, x11, r3 ; CHECK-NEXT: // %bb.3: // %loop.exit ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x8, x11, r3 - ; CHECK-NEXT: nopx ; vmac.f bmh2, bmh2, x10, x11, r3 + ; CHECK-NEXT: nopa ; nopx ; vmac.f bmh2, bmh2, x10, x11, r3 ; CHECK-NEXT: vshuffle x3, x3, x3, r2; vmac.f bmh3, bmh3, x6, x11, r3 ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x5, r3 ; CHECK-NEXT: vmac.f bmh5, bmh5, x8, x5, r3 @@ -96,7 +96,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: vmov bml4, x0 - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm.mir index faa3459fca85..800e684c08b7 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/gemm.mir @@ -73,8 +73,8 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x10, x6, x3, r4; vmac.f bmh0, bmh0, x1, x11, r3 ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: nopb ; nopa ; nops ; nopx ; vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x8, x11, r3 - ; CHECK-NEXT: nopa ; nopx ; vmac.f bmh2, bmh2, x10, x11, r3 + ; CHECK-NEXT: vshuffle x6, x6, x3, r16; vmac.f bmh1, bmh1, x8, x11, r3 + ; CHECK-NEXT: vmac.f bmh2, bmh2, x10, x11, r3 ; CHECK-NEXT: vshuffle x3, x3, x3, r2; vmac.f bmh3, bmh3, x6, x11, r3 ; CHECK-NEXT: vmac.f bmh4, bmh4, x1, x5, r3 ; CHECK-NEXT: vmac.f bmh5, bmh5, x8, x5, r3 @@ -94,7 +94,6 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir index 934ad5b340fc..793d9bb52aa2 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir @@ -51,7 +51,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; lda r7, [p0], #4; st r0, [p1], #4; nopxm ; nopv ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: st r1, [p1], #4 + ; CHECK-NEXT: st r1, [p1], #4; nopx ; CHECK-NEXT: st r2, [p1], #4 ; CHECK-NEXT: st r3, [p1], #4 ; CHECK-NEXT: st r4, [p1], #4 @@ -59,7 +59,6 @@ ; CHECK-NEXT: st r6, [p1], #4 ; CHECK-NEXT: st r7, [p1], #4 ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir index e737ec549a59..236f58737c6a 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir @@ -42,7 +42,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: st r0, [p0], #4 + ; CHECK-NEXT: st r0, [p0], #4; nopx ; CHECK-NEXT: add r0, r0, #1 ; CHECK-NEXT: st r0, [p0], #4 ; CHECK-NEXT: add r0, r0, #1 @@ -50,7 +50,6 @@ ; CHECK-NEXT: add r0, r0, #1 ; CHECK-NEXT: st r0, [p0], #4 ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir index e737ec549a59..236f58737c6a 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir @@ -42,7 +42,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: st r0, [p0], #4 + ; CHECK-NEXT: st r0, [p0], #4; nopx ; CHECK-NEXT: add r0, r0, #1 ; CHECK-NEXT: st r0, [p0], #4 ; CHECK-NEXT: add r0, r0, #1 @@ -50,7 +50,6 @@ ; CHECK-NEXT: add r0, r0, #1 ; CHECK-NEXT: st r0, [p0], #4 ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir index 5e32b1cb70b4..dd4da83e4766 100644 --- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir +++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir @@ -47,7 +47,7 @@ ; CHECK-NEXT: .L_LEnd0: ; CHECK-NEXT: nopb ; lda r3, [p0], #4; st r0, [p1], #4; nopxm ; nopv ; CHECK-NEXT: // %bb.3: // %for.cond.cleanup - ; CHECK-NEXT: st r1, [p1], #4 + ; CHECK-NEXT: st r1, [p1], #4; nopx ; CHECK-NEXT: st r2, [p1], #4 ; CHECK-NEXT: st r3, [p1], #4 ; CHECK-NEXT: st r0, [p1], #4 @@ -55,7 +55,6 @@ ; CHECK-NEXT: st r2, [p1], #4 ; CHECK-NEXT: st r3, [p1], #4 ; CHECK-NEXT: nop - ; CHECK-NEXT: nop ; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .LBB0_4: // %for.cond.cleanup ; CHECK-NEXT: nopa ; ret lr