[AIE2P] Support fifo loads with extra storage

[khallouh]

No description provided.

[khallouh]

We select the vector load because of the mapping to the vector bank instead of the fifo bank. This is because we introduce a copy during InstructionSelect to map the extra fifo input and output operands of the llvm intrinsic to the implicit use and def of lfe register in the instruction. The reason being we don't currently look into the uses beyond copies, bitcasts and phi nodes when determining the register bank assignments.

[gbossu]

I'd be happy if you could look at the changes I've made in https://github.com/Xilinx/llvm-aie/pull/331/files and already apply them here for the new frontend intrinsics, builtins, and LLVM intrinsics. LMK if you need more details :)

[khallouh]

I'd be happy if you could look at the changes I've made in https://github.com/Xilinx/llvm-aie/pull/331/files and already apply them here for the new frontend intrinsics, builtins, and LLVM intrinsics. LMK if you need more details :)

Updated