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pdp11_cpu.c
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/* pdp11_cpu.c: PDP-11 CPU simulator
Copyright (c) 1993, 1994, 1996,
Robert M Supnik, Digital Equipment Corporation
Commercial use prohibited
06-Apr-96 RMS Added dynamic memory sizing
29-Feb-96 RMS Added TM11 support
17-Jul-94 RMS Corrected updating of MMR1 if MMR0 locked
The register state for the PDP-11 is:
REGFILE[0:5][0] general register set
REGFILE[0:5][1] alternate general register set
STACKFILE[4] stack pointers for kernel, supervisor, unused, user
PC program counter
PSW processor status word
<15:14> = CM current processor mode
<13:12> = PM previous processor mode
<11> = RS register set select
<7:5> = IPL interrupt priority level
<4> = TBIT trace trap enable
<3:0> = NZVC condition codes
FR[0:5] floating point accumulators
FPS floating point status register
FEC floating exception code
FEA floating exception address
MMR0,1,2,3 memory management control registers
APRFILE[0:63] memory management relocation registers for
kernel, supervisor, unused, user
<31:16> = PAR processor address registers
<15:0> = PDR processor data registers
PIRQ processor interrupt request register
CPUERR CPU error register
MEMERR memory system error register
CCR cache control register
MAINT maintenance register
HITMISS cache status register
SR switch register
DR display register
*/
/* The PDP-11 has many instruction formats:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ double operand
| opcode | source spec | dest spec | 010000:067777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 110000:167777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ register + operand
| opcode | src reg| dest spec | 004000:004777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 070000:077777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ single operand
| opcode | dest spec | 000100:000177
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 000300:000377
005000:007777
105000:107777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ single register
| opcode |dest reg| 000200:000207
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 000230:000237
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ no operand
| opcode | 000000:000007
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ branch
| opcode | branch displacement | 000400:003477
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 100000:103477
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ EMT/TRAP
| opcode | trap code | 104000:104777
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ cond code operator
| opcode | immediate | 000240:000277
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
An operand specifier consists of an addressing mode and a register.
The addressing modes are:
0 register direct R op = R
1 register deferred (R) op = M[R]
2 autoincrement (R)+ op = M[R]; R = R + length
3 autoincrement deferred @(R)+ op = M[M[R]]; R = R + 2
4 autodecrement -(R) R = R - length; op = M[R]
5 autodecrement deferred @-(R) R = R - 2; op = M[M[R]]
6 displacement d(R) op = M[R + disp]
7 displacement deferred @d(R) op = M[M[R + disp]]
There are eight general registers, R0-R7. R6 is the stack pointer,
R7 the PC. The combination of addressing modes with R7 yields:
27 immediate #n op = M[PC]; PC = PC + 2
37 absolute @#n op = M[M[PC]]; PC = PC + 2
67 relative d(PC) op = M[PC + disp]
77 relative deferred @d(PC) op = M[M[PC + disp]]
*/
/* This routine is the instruction decode routine for the PDP-11. It
is called from the simulator control program to execute instructions
in simulated memory, starting at the simulated PC. It runs until an
enabled exception is encountered.
General notes:
1. Virtual address format. PDP-11 memory management uses the 16b
virtual address, the type of reference (instruction or data), and
the current mode, to construct the 22b physical address. To
package this conveniently, the simulator uses a 19b pseudo virtual
address, consisting of the 16b virtual address prefixed with the
current mode and ispace/dspace indicator. These are precalculated
as isenable and dsenable for ispace and dspace, respectively, and
must be recalculated whenever MMR0, MMR3, or PSW<cm> changes.
2. Traps and interrupts. Variable trap_req bit-encodes all possible
traps. In addition, an interrupt pending bit is encoded as the
lowest priority trap. Traps are processed by trap_vec and trap_clear,
which provide the vector and subordinate traps to clear, respectively.
Variable int_req bit encodes all possible interrupts. It is masked
under the interrupt masks, int_mask[ipl]. If any interrupt request
is not masked, the interrupt bit is set in trap_req. While most
interrupts are handled centrally, a device can supply an interrupt
acknowledge routine.
3. PSW handling. The PSW is kept as components, for easier access.
Because the PSW can be explicitly written as address 17777776,
all instructions must update PSW before executing their last write.
4. Adding I/O devices. This requires modifications to three modules:
pdp11_defs.h add interrupt request definitions
pdp11_cpu.c add I/O page linkages
pdp11_sys.c add to sim_devices
*/
/* Definitions */
#ifdef PERF_MONITOR
/* NOTE: for some reason it does *not* work to include this later on with
* older SunOS-4.
*/
#include <signal.h>
#include <string.h>
#include <unistd.h>
#endif
#include "pdp11_defs.h"
#include <setjmp.h>
#define calc_is(md) ((md) << VA_V_MODE)
#define calc_ds(md) (calc_is((md)) | ((MMR3 & dsmask[(md)])? VA_DS: 0))
/* XXX macro replaced with version from later SIMH
#define calc_MMR1(val) (MMR1 = MMR1? ((val) << 8) | MMR1: (val))
*/
#define calc_MMR1(val) ((MMR1)? (((val) << 8) | MMR1): (val))
#define calc_ints(lv,rq,tr) (((rq) & int_mask[(lv)])? \
((tr) | TRAP_INT) : ((tr) & ~TRAP_INT))
#define GET_SIGN_W(v) ((v) >> 15)
#define GET_SIGN_B(v) ((v) >> 7)
#define GET_Z(v) ((v) == 0)
/* XXX PRO allows jumps to odd (!) addresses. Grrrr.... */
#define JMP_PC(x) old_PC = PC; PC = (x)
#define BRANCH_F(x) old_PC = PC; PC = (PC + (((x) + (x)) & 0377)) & 0177777
#define BRANCH_B(x) old_PC = PC; PC = (PC + (((x) + (x)) | 0177400)) & 0177777
#define ILL_ADR_FLAG 0200000
#define save_ibkpt (cpu_unit.u3) /* will be SAVEd */
#define last_pa (cpu_unit.u4) /* and RESTOREd */
#define UNIT_V_18B (UNIT_V_UF) /* force 18b addr */
#define UNIT_18B (1u << UNIT_V_18B)
#define UNIT_V_MSIZE (UNIT_V_UF + 1) /* dummy */
#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
/* Global state */
#if (MM_CACHE>0)
#define MM_CACHE_SIZE (1<<MM_CACHE)
#define MM_CACHE_MASK (MM_CACHE_SIZE-1)
static int av[MM_CACHE_SIZE]; /* MMU cache v addr (down to block num) */
static int ap[MM_CACHE_SIZE]; /* MMU cache p addr offset */
static int avW[MM_CACHE_SIZE]; /* MMU cache v addr (down to block num) */
static int apW[MM_CACHE_SIZE]; /* MMU cache p addr offset */
static void mm_cache_init()
{
int i;
for (i=0; i<MM_CACHE_SIZE; i++) av[i]=avW[i]=~0; /* clear MMU cache */
}
#endif
unsigned short *M = NULL; /* address of memory */
int REGFILE[6][2] = { { 0 } }; /* R0-R5, two sets */
/* XXX Caution: I think the { 0 } notations only set REGFILE[0][0] to 0! */
int STACKFILE[4] = { 0 }; /* SP, four modes */
int saved_PC = 0; /* program counter */
int R[8] = { 0 }; /* working registers */
int PSW = 0; /* PSW */
int cm = 0; /* current mode */
int pm = 0; /* previous mode */
int rs = 0; /* register set */
int ipl = 0; /* int pri level */
int tbit = 0; /* trace flag */
int N = 0, Z = 0, V = 0, C = 0; /* condition codes */
int wait_state = 0; /* wait state */
int trap_req = 0; /* trap requests */
int int_req = 0; /* interrupt requests */
int PIRQ = 0; /* programmed int req */
int SR = 0; /* switch register */
int DR = 0; /* display register */
fpac_t FR[6] = { { 0 } }; /* fp accumulators */
int FPS = 0; /* fp status */
int FEC = 0; /* fp exception code */
int FEA = 0; /* fp exception addr */
int APRFILE[64] = { 0 }; /* PARs/PDRs */
int MMR0 = 0; /* MMR0 - status */
int MMR1 = 0; /* MMR1 - R+/-R */
int MMR2 = 0; /* MMR2 - saved PC */
int MMR3 = 0; /* MMR3 - 22b status */
int isenable = 0, dsenable = 0; /* i, d space flags */
int CPUERR = 0; /* CPU error reg */
int MEMERR = 0; /* memory error reg */
int CCR = 0; /* cache control reg */
int HITMISS = 0; /* hit/miss reg */
int MAINT = (0 << 9) + (0 << 8) + (4 << 4); /* maint bit<9> = Q/U */
/* <8> = hwre FP */
/* <6:4> = sys type */
int stop_trap = 1; /* stop on trap */
int stop_vecabort = 1; /* stop on vec abort */
int stop_spabort = 1; /* stop on SP abort */
int wait_enable = 0; /* wait state enable */
int ibkpt_addr = ILL_ADR_FLAG | VAMASK; /* breakpoint addr */
int old_PC = 0; /* previous PC */
jmp_buf save_env; /* abort handler */
int dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
unsigned int int_mask[8] = { INT_IPL0, INT_IPL1, INT_IPL2, /* interrupt masks */ /* XXX added unsigned */
INT_IPL3, INT_IPL4, INT_IPL5, INT_IPL6, INT_IPL7 };
extern int sim_int_char;
/* Function declarations */
/* XXX added LOCAL, GLOBAL, and INLINE; define to nothing to compile old way */
LOCAL int cpu_ex (int *vptr, int addr, UNIT *uptr, int sw);
LOCAL int cpu_dep (int val, int addr, UNIT *uptr, int sw);
LOCAL int cpu_reset (DEVICE *dptr);
LOCAL int cpu_svc (UNIT *uptr);
LOCAL int cpu_set_size (UNIT *uptr, int value);
LOCAL int GeteaB (int spec);
GLOBAL int GeteaW (int spec);
LOCAL INLINE int GeteaW_inl (int spec); /* XXX gcc freaks out if all 40 instances are inlined */
LOCAL INLINE int relocR (int addr);
LOCAL INLINE int relocW (int addr);
GLOBAL INLINE int ReadW (int addr);
LOCAL int ReadB (int addr);
LOCAL int ReadMW (int addr);
LOCAL int ReadMB (int addr);
GLOBAL void WriteW (int data, int addr);
LOCAL void WriteB (int data, int addr);
LOCAL void PWriteW (int data, int addr);
LOCAL void PWriteB (int data, int addr);
LOCAL int iopageR (int *data, int addr, int access);
LOCAL int iopageW (int data, int addr, int access);
LOCAL int CPU_rd (int *data, int addr, int access);
LOCAL int CPU_wr (int data, int addr, int access);
LOCAL int APR_rd (int *data, int addr, int access);
LOCAL int APR_wr (int data, int addr, int access);
LOCAL int SR_MMR012_rd (int *data, int addr, int access);
LOCAL int SR_MMR012_wr (int data, int addr, int access);
LOCAL int MMR3_rd (int *data, int addr, int access);
LOCAL int MMR3_wr (int data, int addr, int access);
extern int std_rd (int *data, int addr, int access);
extern int std_wr (int data, int addr, int access);
extern int lpt_rd (int *data, int addr, int access);
extern int lpt_wr (int data, int addr, int access);
extern int rk_rd (int *data, int addr, int access);
extern int rk_wr (int data, int addr, int access);
extern int rk_inta (void);
extern int rl_rd (int *data, int addr, int access);
extern int rl_wr (int data, int addr, int access);
extern int rx_rd (int *data, int addr, int access);
extern int rx_wr (int data, int addr, int access);
extern int tm_rd (int *data, int addr, int access);
extern int tm_wr (int data, int addr, int access);
/* XXX remove when no longer needed */
extern double sim_gtime(void);
/* Auxiliary data structures */
struct iolink { /* I/O page linkage */
int low; /* low I/O addr */
int high; /* high I/O addr */
int (*read)(); /* read routine */
int (*write)(); }; /* write routine */
struct iolink iotable[] = {
#ifdef PRO
/* XXX Video memory location is temporarily hardcoded */
{ 014000000, 014077777, &pro_vram_rd, &pro_vram_wr }, /* 32K video memory */
/* XXX define non-existent RAM as NXM? */
/* Note supervisor PDRs/PARs are disabled */
{ 017777600, 017777617, &APR_rd, &APR_wr }, /* user PDRs */
{ 017777640, 017777657, &APR_rd, &APR_wr }, /* user PARs */
{ 017772300, 017772317, &APR_rd, &APR_wr }, /* kernel PDRs */
{ 017772340, 017772357, &APR_rd, &APR_wr }, /* kernel PARs */
{ 017777572, 017777577, &SR_MMR012_rd, &SR_MMR012_wr },
{ 017772516, 017772517, &MMR3_rd, &MMR3_wr }, /* MMU SR3 */
{ 017730000, 017767777, &rom_rd, &rom_wr }, /* Boot/diag ROM */
{ 017773000, 017777567, ®_rd, ®_wr }, /* Decode almost everything */
{ 017777700, 017777775, ®_rd, ®_wr },
{ 017777776, 017777777, &CPU_rd, &CPU_wr },
{ 014000000, 017777777, ®_rd, ®_wr }, /* XXX video mem */
#else
{ 017777740, 017777777, &CPU_rd, &CPU_wr },
{ 017777546, 017777567, &std_rd, &std_wr },
{ 017777514, 017777517, &lpt_rd, &lpt_wr },
{ 017777400, 017777417, &rk_rd, &rk_wr },
{ 017774400, 017774411, &rl_rd, &rl_wr },
{ 017777170, 017777173, &rx_rd, &rx_wr },
{ 017772520, 017772533, &tm_rd, &tm_wr },
{ 017777600, 017777677, &APR_rd, &APR_wr },
{ 017772200, 017772377, &APR_rd, &APR_wr },
{ 017777570, 017777577, &SR_MMR012_rd, &SR_MMR012_wr },
{ 017772516, 017772517, &MMR3_rd, &MMR3_wr },
#endif
{ 0, 0, NULL } };
int int_vec[32] = { /* int req to vector */
0, 0, 0, VEC_PIRQ, VEC_CLK, 0, 0, VEC_PIRQ,
VEC_RK, VEC_RL, VEC_RX, VEC_TM, 0, 0, 0, VEC_PIRQ,
VEC_TTI, VEC_TTO, VEC_PTR, VEC_PTP, VEC_LPT, 0, 0, 0,
0, 0, 0, 0, VEC_PIRQ, VEC_PIRQ, VEC_PIRQ, VEC_PIRQ };
int (*int_ack[32])() = /* int ack routines */
#ifdef PRO
{ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, &pro_int_ack, NULL, NULL, NULL };
#else
{ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
&rk_inta, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
#endif
int trap_vec[TRAP_V_MAX] = { /* trap req to vector */
VEC_RED, VEC_ODD, VEC_MME, VEC_NXM,
VEC_PAR, VEC_PRV, VEC_ILL, VEC_BPT,
VEC_IOT, VEC_EMT, VEC_TRAP, VEC_TRC,
VEC_YEL, VEC_PWRFL, VEC_FPE };
int trap_clear[TRAP_V_MAX] = { /* trap clears */
TRAP_RED+TRAP_PAR+TRAP_YEL+TRAP_TRC,
TRAP_ODD+TRAP_PAR+TRAP_YEL+TRAP_TRC,
TRAP_MME+TRAP_PAR+TRAP_YEL+TRAP_TRC,
TRAP_NXM+TRAP_PAR+TRAP_YEL+TRAP_TRC,
TRAP_PAR+TRAP_TRC, TRAP_PRV+TRAP_TRC,
TRAP_ILL+TRAP_TRC, TRAP_BPT+TRAP_TRC,
TRAP_IOT+TRAP_TRC, TRAP_EMT+TRAP_TRC,
TRAP_TRAP+TRAP_TRC, TRAP_TRC,
TRAP_YEL, TRAP_PWRFL, TRAP_FPE };
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
cpu_reg CPU register list
cpu_mod CPU modifier list
*/
UNIT cpu_unit = { UDATA (&cpu_svc, UNIT_FIX + UNIT_BINK, INIMEMSIZE) };
REG cpu_reg[] = {
{ ORDATA (PC, saved_PC, 16) },
{ ORDATA (R0, REGFILE[0][0], 16) },
{ ORDATA (R1, REGFILE[1][0], 16) },
{ ORDATA (R2, REGFILE[2][0], 16) },
{ ORDATA (R3, REGFILE[3][0], 16) },
{ ORDATA (R4, REGFILE[4][0], 16) },
{ ORDATA (R5, REGFILE[5][0], 16) },
{ ORDATA (R10, REGFILE[0][1], 16) },
{ ORDATA (R11, REGFILE[1][1], 16) },
{ ORDATA (R12, REGFILE[2][1], 16) },
{ ORDATA (R13, REGFILE[3][1], 16) },
{ ORDATA (R14, REGFILE[4][1], 16) },
{ ORDATA (R15, REGFILE[5][1], 16) },
{ ORDATA (KSP, STACKFILE[KERNEL], 16) },
{ ORDATA (SSP, STACKFILE[SUPER], 16) },
{ ORDATA (USP, STACKFILE[USER], 16) },
{ ORDATA (PSW, PSW, 16) },
{ GRDATA (CM, PSW, 8, 2, PSW_V_CM) },
{ GRDATA (PM, PSW, 8, 2, PSW_V_PM) },
{ FLDATA (RS, PSW, PSW_V_RS) },
{ GRDATA (IPL, PSW, 8, 3, PSW_V_IPL) },
{ FLDATA (T, PSW, PSW_V_TBIT) },
{ FLDATA (N, PSW, PSW_V_N) },
{ FLDATA (Z, PSW, PSW_V_Z) },
{ FLDATA (V, PSW, PSW_V_V) },
{ FLDATA (C, PSW, PSW_V_C) },
{ ORDATA (SR, SR, 16) },
{ ORDATA (DR, DR, 16) },
{ ORDATA (MEMERR, MEMERR, 16) },
{ ORDATA (CCR, CCR, 16) },
{ ORDATA (MAINT, MAINT, 16) },
{ ORDATA (HITMISS, HITMISS, 16) },
{ ORDATA (CPUERR, CPUERR, 16) },
{ ORDATA (INT, int_req, 32), REG_RO },
{ ORDATA (TRAPS, trap_req, TRAP_V_MAX) },
{ ORDATA (PIRQ, PIRQ, 16) },
{ FLDATA (WAIT, wait_state, 0) },
{ FLDATA (WAIT_ENABLE, wait_enable, 0) },
{ ORDATA (STOP_TRAPS, stop_trap, TRAP_V_MAX) },
{ FLDATA (STOP_VECA, stop_vecabort, 0) },
{ FLDATA (STOP_SPA, stop_spabort, 0) },
{ ORDATA (FAC0H, FR[0].h, 32) },
{ ORDATA (FAC0L, FR[0].l, 32) },
{ ORDATA (FAC1H, FR[1].h, 32) },
{ ORDATA (FAC1L, FR[1].l, 32) },
{ ORDATA (FAC2H, FR[2].h, 32) },
{ ORDATA (FAC2L, FR[2].l, 32) },
{ ORDATA (FAC3H, FR[3].h, 32) },
{ ORDATA (FAC3L, FR[3].l, 32) },
{ ORDATA (FAC4H, FR[4].h, 32) },
{ ORDATA (FAC4L, FR[4].l, 32) },
{ ORDATA (FAC5H, FR[5].h, 32) },
{ ORDATA (FAC5L, FR[5].l, 32) },
{ ORDATA (FPS, FPS, 16) },
{ ORDATA (FEA, FEA, 16) },
{ ORDATA (FEC, FEC, 4) },
{ ORDATA (MMR0, MMR0, 16) },
{ ORDATA (MMR1, MMR1, 16) },
{ ORDATA (MMR2, MMR2, 16) },
{ ORDATA (MMR3, MMR3, 16) },
{ GRDATA (KIPAR0, APRFILE[000], 8, 16, 16) },
{ GRDATA (KIPDR0, APRFILE[000], 8, 16, 0) },
{ GRDATA (KIPAR1, APRFILE[001], 8, 16, 16) },
{ GRDATA (KIPDR1, APRFILE[001], 8, 16, 0) },
{ GRDATA (KIPAR2, APRFILE[002], 8, 16, 16) },
{ GRDATA (KIPDR2, APRFILE[002], 8, 16, 0) },
{ GRDATA (KIPAR3, APRFILE[003], 8, 16, 16) },
{ GRDATA (KIPDR3, APRFILE[003], 8, 16, 0) },
{ GRDATA (KIPAR4, APRFILE[004], 8, 16, 16) },
{ GRDATA (KIPDR4, APRFILE[004], 8, 16, 0) },
{ GRDATA (KIPAR5, APRFILE[005], 8, 16, 16) },
{ GRDATA (KIPDR5, APRFILE[005], 8, 16, 0) },
{ GRDATA (KIPAR6, APRFILE[006], 8, 16, 16) },
{ GRDATA (KIPDR6, APRFILE[006], 8, 16, 0) },
{ GRDATA (KIPAR7, APRFILE[007], 8, 16, 16) },
{ GRDATA (KIPDR7, APRFILE[007], 8, 16, 0) },
{ GRDATA (KDPAR0, APRFILE[010], 8, 16, 16) },
{ GRDATA (KDPDR0, APRFILE[010], 8, 16, 0) },
{ GRDATA (KDPAR1, APRFILE[011], 8, 16, 16) },
{ GRDATA (KDPDR1, APRFILE[011], 8, 16, 0) },
{ GRDATA (KDPAR2, APRFILE[012], 8, 16, 16) },
{ GRDATA (KDPDR2, APRFILE[012], 8, 16, 0) },
{ GRDATA (KDPAR3, APRFILE[013], 8, 16, 16) },
{ GRDATA (KDPDR3, APRFILE[013], 8, 16, 0) },
{ GRDATA (KDPAR4, APRFILE[014], 8, 16, 16) },
{ GRDATA (KDPDR4, APRFILE[014], 8, 16, 0) },
{ GRDATA (KDPAR5, APRFILE[015], 8, 16, 16) },
{ GRDATA (KDPDR5, APRFILE[015], 8, 16, 0) },
{ GRDATA (KDPAR6, APRFILE[016], 8, 16, 16) },
{ GRDATA (KDPDR6, APRFILE[016], 8, 16, 0) },
{ GRDATA (KDPAR7, APRFILE[017], 8, 16, 16) },
{ GRDATA (KDPDR7, APRFILE[017], 8, 16, 0) },
{ GRDATA (SIPAR0, APRFILE[020], 8, 16, 16) },
{ GRDATA (SIPDR0, APRFILE[020], 8, 16, 0) },
{ GRDATA (SIPAR1, APRFILE[021], 8, 16, 16) },
{ GRDATA (SIPDR1, APRFILE[021], 8, 16, 0) },
{ GRDATA (SIPAR2, APRFILE[022], 8, 16, 16) },
{ GRDATA (SIPDR2, APRFILE[022], 8, 16, 0) },
{ GRDATA (SIPAR3, APRFILE[023], 8, 16, 16) },
{ GRDATA (SIPDR3, APRFILE[023], 8, 16, 0) },
{ GRDATA (SIPAR4, APRFILE[024], 8, 16, 16) },
{ GRDATA (SIPDR4, APRFILE[024], 8, 16, 0) },
{ GRDATA (SIPAR5, APRFILE[025], 8, 16, 16) },
{ GRDATA (SIPDR5, APRFILE[025], 8, 16, 0) },
{ GRDATA (SIPAR6, APRFILE[026], 8, 16, 16) },
{ GRDATA (SIPDR6, APRFILE[026], 8, 16, 0) },
{ GRDATA (SIPAR7, APRFILE[027], 8, 16, 16) },
{ GRDATA (SIPDR7, APRFILE[027], 8, 16, 0) },
{ GRDATA (SDPAR0, APRFILE[030], 8, 16, 16) },
{ GRDATA (SDPDR0, APRFILE[030], 8, 16, 0) },
{ GRDATA (SDPAR1, APRFILE[031], 8, 16, 16) },
{ GRDATA (SDPDR1, APRFILE[031], 8, 16, 0) },
{ GRDATA (SDPAR2, APRFILE[032], 8, 16, 16) },
{ GRDATA (SDPDR2, APRFILE[032], 8, 16, 0) },
{ GRDATA (SDPAR3, APRFILE[033], 8, 16, 16) },
{ GRDATA (SDPDR3, APRFILE[033], 8, 16, 0) },
{ GRDATA (SDPAR4, APRFILE[034], 8, 16, 16) },
{ GRDATA (SDPDR4, APRFILE[034], 8, 16, 0) },
{ GRDATA (SDPAR5, APRFILE[035], 8, 16, 16) },
{ GRDATA (SDPDR5, APRFILE[035], 8, 16, 0) },
{ GRDATA (SDPAR6, APRFILE[036], 8, 16, 16) },
{ GRDATA (SDPDR6, APRFILE[036], 8, 16, 0) },
{ GRDATA (SDPAR7, APRFILE[037], 8, 16, 16) },
{ GRDATA (SDPDR7, APRFILE[037], 8, 16, 0) },
{ GRDATA (UIPAR0, APRFILE[060], 8, 16, 16) },
{ GRDATA (UIPDR0, APRFILE[060], 8, 16, 0) },
{ GRDATA (UIPAR1, APRFILE[061], 8, 16, 16) },
{ GRDATA (UIPDR1, APRFILE[061], 8, 16, 0) },
{ GRDATA (UIPAR2, APRFILE[062], 8, 16, 16) },
{ GRDATA (UIPDR2, APRFILE[062], 8, 16, 0) },
{ GRDATA (UIPAR3, APRFILE[063], 8, 16, 16) },
{ GRDATA (UIPDR3, APRFILE[063], 8, 16, 0) },
{ GRDATA (UIPAR4, APRFILE[064], 8, 16, 16) },
{ GRDATA (UIPDR4, APRFILE[064], 8, 16, 0) },
{ GRDATA (UIPAR5, APRFILE[065], 8, 16, 16) },
{ GRDATA (UIPDR5, APRFILE[065], 8, 16, 0) },
{ GRDATA (UIPAR6, APRFILE[066], 8, 16, 16) },
{ GRDATA (UIPDR6, APRFILE[066], 8, 16, 0) },
{ GRDATA (UIPAR7, APRFILE[067], 8, 16, 16) },
{ GRDATA (UIPDR7, APRFILE[067], 8, 16, 0) },
{ GRDATA (UDPAR0, APRFILE[070], 8, 16, 16) },
{ GRDATA (UDPDR0, APRFILE[070], 8, 16, 0) },
{ GRDATA (UDPAR1, APRFILE[071], 8, 16, 16) },
{ GRDATA (UDPDR1, APRFILE[071], 8, 16, 0) },
{ GRDATA (UDPAR2, APRFILE[072], 8, 16, 16) },
{ GRDATA (UDPDR2, APRFILE[072], 8, 16, 0) },
{ GRDATA (UDPAR3, APRFILE[073], 8, 16, 16) },
{ GRDATA (UDPDR3, APRFILE[073], 8, 16, 0) },
{ GRDATA (UDPAR4, APRFILE[074], 8, 16, 16) },
{ GRDATA (UDPDR4, APRFILE[074], 8, 16, 0) },
{ GRDATA (UDPAR5, APRFILE[075], 8, 16, 16) },
{ GRDATA (UDPDR5, APRFILE[075], 8, 16, 0) },
{ GRDATA (UDPAR6, APRFILE[076], 8, 16, 16) },
{ GRDATA (UDPDR6, APRFILE[076], 8, 16, 0) },
{ GRDATA (UDPAR7, APRFILE[077], 8, 16, 16) },
{ GRDATA (UDPDR7, APRFILE[077], 8, 16, 0) },
{ FLDATA (18B_ADDR, cpu_unit.flags, UNIT_V_18B), REG_HRO },
{ ORDATA (OLDPC, old_PC, 16), REG_RO },
{ ORDATA (BREAK, ibkpt_addr, 17) },
{ ORDATA (WRU, sim_int_char, 8) },
{ NULL} };
MTAB cpu_mod[] = {
{ UNIT_18B, UNIT_18B, "18b addressing", "18B", NULL },
{ UNIT_18B, 0, NULL, "22B", NULL },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size},
{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size},
{ UNIT_MSIZE, 98304, NULL, "96K", &cpu_set_size},
{ UNIT_MSIZE, 131072, NULL, "128K", &cpu_set_size},
{ UNIT_MSIZE, 229376, NULL, "192K", &cpu_set_size},
{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size},
{ UNIT_MSIZE, 393216, NULL, "384K", &cpu_set_size},
{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size},
{ UNIT_MSIZE, 786432, NULL, "768K", &cpu_set_size},
{ UNIT_MSIZE, 1048576, NULL, "1024K", &cpu_set_size},
{ UNIT_MSIZE, 2097152, NULL, "2048K", &cpu_set_size},
{ UNIT_MSIZE, 3145728, NULL, "3072K", &cpu_set_size},
{ UNIT_MSIZE, 4194304, NULL, "4096K", &cpu_set_size},
{ UNIT_MSIZE, 1048576, NULL, "1M", &cpu_set_size},
{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size},
{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size},
{ UNIT_MSIZE, 4194304, NULL, "4M", &cpu_set_size},
{ 0 } };
DEVICE cpu_dev = {
"CPU", &cpu_unit, cpu_reg, cpu_mod,
1, 8, 22, 2, 8, 16,
&cpu_ex, &cpu_dep, &cpu_reset,
NULL, NULL, NULL };
/* XXX MOVED sim_instr to end to allow inlined functions */
/* XXX MOVED reloc and readW functions here to allow inlined functions */
/* XXX START MOVED BLOCK */
#ifdef PERF_MONITOR
LOCAL int cache_tries = 1;
LOCAL int cache_misses = 1;
LOCAL void perf_monitor_disp(int sig
#ifdef SIG_RESTART
/* need a couple of extra args on hpux */
, int code, struct sigcontext *scp
#endif
)
{
static char title[256];
static int count = 0;
static double last_sim_time = 0;
static double sim_time;
static double tips = 0;
alarm(1);
sim_time = sim_gtime();
if (last_sim_time==0) { last_sim_time = sim_time; return; }
/* XXX
tips = (tips*2. + (sim_time - last_sim_time)/1000.)/3.;
*/
tips = (sim_time - last_sim_time)/1000.;
sprintf(title,
"XHOMER up:%d"
" tips:%.0f"
#ifdef EXTRA_STATUS
" hits:%2d%%"
#endif
#ifdef PRO
" led:%d%d%d%d"
#endif
, ++count
, tips
#ifdef EXTRA_STATUS
, 100-cache_misses*100/cache_tries
#endif
#ifdef PRO
,~(pro_led>>3)&1, ~(pro_led>>2)&1,
~(pro_led>>1)&1, ~pro_led&1
#endif
);
#ifdef PRO
pro_screen_title(title);
#else
fprintf(stderr, "\033]2;%s\a", title);
#endif
last_sim_time = sim_time;
cache_tries = 1;
cache_misses = 1;
#ifdef SIG_RESTART
/* if context pointer not NULL, tell the system call to restart (hpux) */
if (scp!=NULL)
scp->sc_syscall_action = SIG_RESTART;
#endif
}
LOCAL void perf_monitor_init(void)
{
struct sigaction vec_trap;
vec_trap.sa_handler = perf_monitor_disp;
sigemptyset(&vec_trap.sa_mask);
#ifdef SA_RESTART
vec_trap.sa_flags = SA_RESTART;
#else
vec_trap.sa_flags = 0;
#endif
sigaction(SIGALRM, &vec_trap, NULL);
alarm(1);
}
#endif
/* Relocate virtual address, read access
Inputs:
va = virtual address, <18:16> = mode, I/D space
Outputs:
pa = physical address
On aborts, this routine aborts back to the top level simulator
with an appropriate trap code.
Notes:
- APRFILE[UNUSED] is all zeroes, forcing non-resident abort
- Aborts must update MMR0<15:13,6:1> if updating is enabled
*/
int relocR (int va)
{
int dbn, plf, apridx, apr, pa;
if (MMR0 & MMR0_MME) { /* if mmgt */
#if (MM_CACHE>0)
int va_block = va >> 6;
int va_cache_pos = va_block & MM_CACHE_MASK;
#ifdef PERF_MONITOR
cache_tries++;
#endif
if (av[va_cache_pos]==va_block)
return (ap[va_cache_pos] | (va & 00000077));
#ifdef PERF_MONITOR
cache_misses++;
#endif
/* av = ~0; */ /* move this */
#endif
apridx = (va >> VA_V_APF) & 077; /* index into APR */
apr = APRFILE[apridx]; /* with va<18:13> */
dbn = va & VA_BN; /* extr block num */
plf = (apr & PDR_PLF) >> 2; /* extr page length */
if ((apr & PDR_NR) == 0) { /* if non-resident */
if (update_MM) MMR0 = MMR0 | (apridx << MMR0_V_PAGE);
MMR0 = MMR0 | MMR0_NR;
ABORT (TRAP_MME); } /* abort ref */
if ((apr & PDR_ED)? dbn < plf: dbn > plf) { /* if pg lnt error */
if (update_MM) MMR0 = MMR0 | (apridx << MMR0_V_PAGE);
MMR0 = MMR0 | MMR0_PL;
ABORT (TRAP_MME); } /* abort ref */
/* XXX old code
pa = (va & VA_DF) + ((apr >> 10) & 017777700);
*/
pa = ((va & VA_DF) + ((apr >> 10) & 017777700)) & 017777777;
if ((MMR3 & MMR3_M22E) == 0) {
pa = pa & 0777777;
if (pa >= 0760000) pa = 017000000 | pa; } /* XXX */
#if (MM_CACHE>0)
av[va_cache_pos] = va_block;
ap[va_cache_pos] = pa & 017777700;
#endif
} /* XXX */
else { pa = va & 0177777; /* mmgt off */
if (pa >= 0160000) pa = 017600000 | pa; }
return pa;
}
/* Relocate virtual address, write access
Inputs:
va = virtual address, <18:16> = mode, I/D space
Outputs:
pa = physical address
On aborts, this routine aborts back to the top level simulator
with an appropriate trap code.
Notes:
- APRFILE[UNUSED] is all zeroes, forcing non-resident abort
- Aborts must update MMR0<15:13,6:1> if updating is enabled
*/
int relocW (int va)
{
int dbn, plf, apridx, apr, pa;
if (MMR0 & MMR0_MME) { /* if mmgt */
#if (MM_CACHE>0)
int va_block = va >> 6;
int va_cache_pos = va_block & MM_CACHE_MASK;
#ifdef PERF_MONITOR
cache_tries++;
#endif
if (avW[va_cache_pos]==va_block)
return (apW[va_cache_pos] | (va & 00000077));
#ifdef PERF_MONITOR
cache_misses++;
#endif
/* avW = ~0; */ /* move this */
#endif
apridx = (va >> VA_V_APF) & 077; /* index into APR */
apr = APRFILE[apridx]; /* with va<18:13> */
dbn = va & VA_BN; /* extr block num */
plf = (apr & PDR_PLF) >> 2; /* extr page length */
if ((apr & PDR_NR) == 0) { /* if non-resident */
if (update_MM) MMR0 = MMR0 | (apridx << MMR0_V_PAGE);
MMR0 = MMR0 | MMR0_NR;
ABORT (TRAP_MME); } /* abort ref */
if ((apr & PDR_ED)? dbn < plf: dbn > plf) { /* if pg lnt error */
if (update_MM) MMR0 = MMR0 | (apridx << MMR0_V_PAGE);
MMR0 = MMR0 | MMR0_PL;
ABORT (TRAP_MME); } /* abort ref */
/* XXX PDR_RW changed to PDR_WE */
if ((apr & PDR_WE) == 0) { /* if rd only error */
if (update_MM) MMR0 = MMR0 | (apridx << MMR0_V_PAGE);
MMR0 = MMR0 | MMR0_RO;
ABORT (TRAP_MME); } /* abort ref */
APRFILE[apridx] = apr | PDR_W; /* set W */
/* XXX old code
pa = (va & VA_DF) + ((apr >> 10) & 017777700);
*/
pa = ((va & VA_DF) + ((apr >> 10) & 017777700)) & 017777777;
if ((MMR3 & MMR3_M22E) == 0) {
pa = pa & 0777777;
if (pa >= 0760000) pa = 017000000 | pa; } /* XXX */
#if (MM_CACHE>0)
avW[va_cache_pos] = va_block;
apW[va_cache_pos] = pa & 017777700;
#endif
} /* XXX */
else { pa = va & 0177777; /* mmgt off */
if (pa >= 0160000) pa = 017600000 | pa; }
return pa;
}
/* Relocate virtual address, console access
Inputs:
va = virtual address
sw = switches
Outputs:
pa = physical address
On aborts, this routine returns -1
*/
int relocC (int va, int sw)
{
int mode, dbn, plf, apridx, apr, pa;
if (MMR0 & MMR0_MME) { /* if mmgt */
if (sw & SWMASK ('K')) mode = KERNEL;
else if (sw & SWMASK ('S')) mode = SUPER;
else if (sw & SWMASK ('U')) mode = USER;
else if (sw & SWMASK ('P')) mode = (PSW >> PSW_V_PM) & 03;
else mode = (PSW >> PSW_V_CM) & 03;
va = va | ((sw & SWMASK ('D'))? calc_ds (mode): calc_is (mode));
apridx = (va >> VA_V_APF) & 077; /* index into APR */
apr = APRFILE[apridx]; /* with va<18:13> */
dbn = va & VA_BN; /* extr block num */
plf = (apr & PDR_PLF) >> 2; /* extr page length */
if ((apr & PDR_NR) == 0) return -1;
if ((apr & PDR_ED)? dbn < plf: dbn > plf) return -1;
/* XXX old code
pa = (va & VA_DF) + ((apr >> 10) & 017777700);
*/
pa = ((va & VA_DF) + ((apr >> 10) & 017777700)) & 017777777;
if ((MMR3 & MMR3_M22E) == 0) {
pa = pa & 0777777;
if (pa >= 0760000) pa = 017000000 | pa; } }
else { pa = va & 0177777; /* mmgt off */
if (pa >= 0160000) pa = 017600000 | pa; }
return pa;
}
/* Read byte and word routines, read only and read-modify-write versions
Inputs:
va = virtual address, <18:16> = mode, I/D space
Outputs:
data = data read from memory or I/O space
*/
int ReadW (int va)
{
int pa, data;
/* Odd addressing errors are NOT detected on the PRO */
#ifndef PRO
if (va & 1) { /* odd address? */
setCPUERR (CPUE_ODD);
ABORT (TRAP_ODD); }
#endif
pa = relocR (va); /* relocate */
if (pa < MEMSIZE) return (M[pa >> 1]); /* memory address? */
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageR (&data, pa, READ) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return data;
}
int ReadB (int va)
{
int pa, data;
pa = relocR (va); /* relocate */
if (pa < MEMSIZE) return (va & 1? M[pa >> 1] >> 8: M[pa >> 1]) & 0377;
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageR (&data, pa, READ) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return ((va & 1)? data >> 8: data) & 0377;
}
int ReadMW (int va)
{
int data;
#ifndef PRO
if (va & 1) { /* odd address? */
setCPUERR (CPUE_ODD);
ABORT (TRAP_ODD); }
#endif
last_pa = relocW (va); /* reloc, wrt chk */
if (last_pa < MEMSIZE) return (M[last_pa >> 1]); /* memory address? */
if (last_pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageR (&data, last_pa, READ) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return data;
}
int ReadMB (int va)
{
int data;
last_pa = relocW (va); /* reloc, wrt chk */
if (last_pa < MEMSIZE)
return (va & 1? M[last_pa >> 1] >> 8: M[last_pa >> 1]) & 0377;
if (last_pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageR (&data, last_pa, READ) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return ((va & 1)? data >> 8: data) & 0377;
}
/* Write byte and word routines
Inputs:
data = data to be written
va = virtual address, <18:16> = mode, I/D space, or
pa = physical address
Outputs: none
*/
void WriteW (int data, int va)
{
int pa;
#ifndef PRO
if (va & 1) { /* odd address? */
setCPUERR (CPUE_ODD);
ABORT (TRAP_ODD); }
#endif
pa = relocW (va); /* relocate */
if (pa < MEMSIZE) { /* memory address? */
M[pa >> 1] = data;
return; }
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageW (data, pa, WRITE) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return;
}
void WriteB (int data, int va)
{
int pa;
pa = relocW (va); /* relocate */
if (pa < MEMSIZE) { /* memory address? */
if (va & 1) M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
return; }
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageW (data, pa, WRITEB) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return;
}
void PWriteW (int data, int pa)
{
if (pa < MEMSIZE) { /* memory address? */
M[pa >> 1] = data;
return; }
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageW (data, pa, WRITE) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return;
}
void PWriteB (int data, int pa)
{
if (pa < MEMSIZE) { /* memory address? */
if (pa & 1) M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
return; }
if (pa < IOPAGEBASE) { /* I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM); }
if (iopageW (data, pa, WRITEB) != SCPE_OK) { /* invalid I/O addr? */
setCPUERR (CPUE_TMO);
ABORT (TRAP_NXM); }
return;
}
/* XXX END MOVED BLOCK */
/* Effective address calculations
Inputs:
spec = specifier <5:0>
Outputs:
ea = effective address
<15:0> = virtual address
<16> = instruction/data data space
<18:17> = mode
Data space calculation: the PDP-11 features both instruction and data
spaces. Instruction space contains the instruction and any sequential
add ons (eg, immediates, absolute addresses). Data space contains all
data operands and indirect addresses. If data space is enabled, then
memory references are directed according to these rules:
Mode Index ref Indirect ref Direct ref
10..16 na na data
17 na na instruction