diff --git a/_unittest/test_45_FilterSolutions/resources/__init__.py b/_unittest/test_45_FilterSolutions/resources/__init__.py index d2b2bdb76b9..f744b86ba71 100644 --- a/_unittest/test_45_FilterSolutions/resources/__init__.py +++ b/_unittest/test_45_FilterSolutions/resources/__init__.py @@ -23,3 +23,4 @@ # SOFTWARE. from .resources import read_resource_file +from .resources import resource_path diff --git a/_unittest/test_45_FilterSolutions/resources/import_tuned_variables.ckt b/_unittest/test_45_FilterSolutions/resources/import_tuned_variables.ckt new file mode 100644 index 00000000000..dd8016e153c --- /dev/null +++ b/_unittest/test_45_FilterSolutions/resources/import_tuned_variables.ckt @@ -0,0 +1,17 @@ +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +R0 1 2 50 +C1 2 0 2.296E-12 +L2 2 3 1.688E-08 +C3 3 0 4.517E-12 +L4 3 4 1.688E-08 +C5 4 0 2.296E-12 +R6 4 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(4) -90 0 +.PLOT AC VP(4) -200 200 +.PLOT AC VG(4) 0 1.2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(4) 0 0.6 +.END diff --git a/_unittest/test_45_FilterSolutions/resources/imported_netlist.ckt b/_unittest/test_45_FilterSolutions/resources/imported_netlist.ckt new file mode 100644 index 00000000000..dd8016e153c --- /dev/null +++ b/_unittest/test_45_FilterSolutions/resources/imported_netlist.ckt @@ -0,0 +1,17 @@ +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +R0 1 2 50 +C1 2 0 2.296E-12 +L2 2 3 1.688E-08 +C3 3 0 4.517E-12 +L4 3 4 1.688E-08 +C5 4 0 2.296E-12 +R6 4 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(4) -90 0 +.PLOT AC VP(4) -200 200 +.PLOT AC VG(4) 0 1.2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(4) 0 0.6 +.END diff --git a/_unittest/test_45_FilterSolutions/resources/library_parts.cfg b/_unittest/test_45_FilterSolutions/resources/library_parts.cfg new file mode 100644 index 00000000000..d53e30325bd --- /dev/null +++ b/_unittest/test_45_FilterSolutions/resources/library_parts.cfg @@ -0,0 +1,45 @@ +modsubType=2 +modsubEr=4.5 +modsubRho=5.8E+07 +modsubTand=0.035 +modsubH=0.002 +modsubT=5E-07 +modsubS=0.00127 +modsubC=0.00635 +modsubErsel=-1 +modsubRhosel=-1 +modsubTandsel=-1 +modsubTanddef=0 +modsubiSubSel=0 +modsubName=User Defined Substrate +modsubBrow= +modsubNameVal=4.5 +modAnsSubIndex=0 +modAWRSubIndex=0 +webAWRSubIndex=0 +locAWRSubIndex=0 +ModelData=2 +ModelDataV=1 +ModelInd=0 +ModelCap=3 +ModelRes=0 +ModelIndV=1 +ModelCapV=1 +ModelResV=1 +modRatLen=2 +modRatZ=1 +Interc=1 +modActLen=0.00254 +modActWid=0.00127 +modRatZMin=0.5 +modRatZMax=2 +modRatLenMin=0.5 +modRatLenMax=2 +modActLenMin=0.00127 +modActWidMin=0.000635 +modActLenMax=0.00508 +modActWidMax=0.00254 +useGeo=0 +OptGeo=1 +indTol=1 +capTol=1 diff --git a/_unittest/test_45_FilterSolutions/resources/library_parts_test.cfg b/_unittest/test_45_FilterSolutions/resources/library_parts_test.cfg new file mode 100644 index 00000000000..e69de29bb2d diff --git a/_unittest/test_45_FilterSolutions/test_lumped_export/__init__.py b/_unittest/test_45_FilterSolutions/test_lumped_export/__init__.py new file mode 100644 index 00000000000..9c4476773da --- /dev/null +++ b/_unittest/test_45_FilterSolutions/test_lumped_export/__init__.py @@ -0,0 +1,23 @@ +# -*- coding: utf-8 -*- +# +# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# SPDX-License-Identifier: MIT +# +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. diff --git a/_unittest/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/_unittest/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 8e28035d6bf..9ca433a806f 100644 --- a/_unittest/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/_unittest/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -23,132 +23,594 @@ # SOFTWARE. from _unittest.conftest import config -import pyaedt -from pyaedt.filtersolutions_core.attributes import FilterImplementation -from pyaedt.generic.general_methods import is_linux - -# from ..filtersolutions_resources import resource_path +import ansys.aedt.core +from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +from ansys.aedt.core.filtersolutions_core.export_to_aedt import PartLibraries +from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateEr +from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateResistivity +from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateType +from ansys.aedt.core.generic.general_methods import is_linux import pytest +from ..resources import read_resource_file +from ..resources import resource_path + +first_modelithics_inductor = "AVX -> IND_AVX_0201_101 Accu-L" +second_modelithics_inductor = "AVX -> IND_AVX_0402_101 AccuL" +third_modelithics_inductor = "Wurth -> IND_WTH_0603_003 WE-KI" +first_modelithics_capacitor = "Amotech -> CAP_AMH_0201_001 A60Z" +second_modelithics_capacitor = "Murata -> CAP_MUR_0805_004 GRM219" +first_modelithics_resistor = "AVX -> RES_AVX_0402_001 UBR0402" +second_modelithics_resistor = "Vishay -> RES_VIS_0603_001 D11" + @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: + def test_modelithics_inductor_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_inductor_list_count == 116 + + def test_modelithics_inductor_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_inductor_list(-1) + assert info.value.args[0] == "The Modelithics inductor at the given index is not available" + lumpdesign.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor + assert lumpdesign.export_to_aedt.modelithics_inductor_list(0) == first_modelithics_inductor + + def test_modelithics_inductor_selection(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_inductor_selection + assert info.value.args[0] == "No Modelithics inductor is selected" + lumpdesign.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor + assert lumpdesign.export_to_aedt.modelithics_inductor_selection == first_modelithics_inductor + + def test_modelithics_inductor_family_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 0 + lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 1 + lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 2 + + def test_modelithics_inductor_family_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor + + def test_modelithics_inductor_family_list_add_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor + + def test_modelithics_inductor_family_list_remove_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 2 + lumpdesign.export_to_aedt.modelithics_inductor_remove_family(third_modelithics_inductor) + assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 1 + + def test_modelithics_capacitor_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 140 + + def test_modelithics_capacitor_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_capacitor_list(-1) + assert info.value.args[0] == "The Modelithics capacitor at the given index is not available" + lumpdesign.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor + assert lumpdesign.export_to_aedt.modelithics_capacitor_list(0) == first_modelithics_capacitor + + def test_modelithics_capacitor_selection(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_capacitor_selection + assert info.value.args[0] == "No Modelithics capacitor is selected" + lumpdesign.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor + assert lumpdesign.export_to_aedt.modelithics_capacitor_selection == first_modelithics_capacitor + + def test_modelithics_capacitor_family_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 0 + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 1 + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 2 + + def test_modelithics_capacitor_family_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor + + def test_modelithics_capacitor_family_list_add_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor + + def test_modelithics_capacitor_family_list_remove_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 2 + lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) + assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 1 + + def test_modelithics_resistor_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_resistor_list_count == 39 + + def test_modelithics_resistor_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_resistor_list(-1) + assert info.value.args[0] == "The Modelithics resistor at the given index is not available" + lumpdesign.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor + assert lumpdesign.export_to_aedt.modelithics_resistor_list(0) == first_modelithics_resistor + + def test_modelithics_resistor_selection(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_resistor_selection + assert info.value.args[0] == "No Modelithics resistor is selected" + lumpdesign.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor + assert lumpdesign.export_to_aedt.modelithics_resistor_selection == first_modelithics_resistor + + def test_modelithics_resistor_family_list_count(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 0 + lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 1 + lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 2 + + def test_modelithics_resistor_family_list(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor + + def test_modelithics_resistor_family_list_add_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor + + def test_modelithics_resistor_family_list_remove_family(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + with pytest.raises(RuntimeError) as info: + lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" + lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 2 + lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) + assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 1 def test_schematic_name(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.export_to_aedt.schematic_name = "my_schematic" assert lumpdesign.export_to_aedt.schematic_name == "my_schematic" def test_simulate_after_export_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.simulate_after_export_enabled == False lumpdesign.export_to_aedt.simulate_after_export_enabled = True assert lumpdesign.export_to_aedt.simulate_after_export_enabled == True def test_include_group_delay_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_group_delay_enabled == False lumpdesign.export_to_aedt.include_group_delay_enabled = True assert lumpdesign.export_to_aedt.include_group_delay_enabled == True def test_include_gt_gain_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_gt_gain_enabled == False lumpdesign.export_to_aedt.include_gt_gain_enabled = True assert lumpdesign.export_to_aedt.include_gt_gain_enabled == True def test_include_vgsl_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgsl_enabled == False lumpdesign.export_to_aedt.include_vgsl_enabled = True assert lumpdesign.export_to_aedt.include_vgsl_enabled == True def test_include_vgin_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_vgin_enabled == False lumpdesign.export_to_aedt.include_vgin_enabled = True assert lumpdesign.export_to_aedt.include_vgin_enabled == True def test_include_input_return_loss_s11_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == True lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled = False assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == False def test_include_forward_transfer_s21_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == True lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled = False assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == False def test_include_reverse_transfer_s12_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == False lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled = True assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == True def test_include_output_return_loss_s22_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == False lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled = True assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == True def test_db_format_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.db_format_enabled == True lumpdesign.export_to_aedt.db_format_enabled = False assert lumpdesign.export_to_aedt.db_format_enabled == False def test_rectangular_plot_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.rectangular_plot_enabled == True lumpdesign.export_to_aedt.rectangular_plot_enabled = False assert lumpdesign.export_to_aedt.rectangular_plot_enabled == False def test_smith_plot_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.smith_plot_enabled == False lumpdesign.export_to_aedt.smith_plot_enabled = True assert lumpdesign.export_to_aedt.smith_plot_enabled == True def test_polar_plot_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.polar_plot_enabled == False lumpdesign.export_to_aedt.polar_plot_enabled = True assert lumpdesign.export_to_aedt.polar_plot_enabled == True def test_table_data_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.table_data_enabled == False lumpdesign.export_to_aedt.table_data_enabled = True assert lumpdesign.export_to_aedt.table_data_enabled == True def test_optimitrics_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimitrics_enabled == True lumpdesign.export_to_aedt.optimitrics_enabled = False assert lumpdesign.export_to_aedt.optimitrics_enabled == False def test_optimize_after_export_enabled(self): - lumpdesign = pyaedt.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() assert lumpdesign.export_to_aedt.optimize_after_export_enabled == False lumpdesign.export_to_aedt.optimize_after_export_enabled = True assert lumpdesign.export_to_aedt.optimize_after_export_enabled == True + + def test_load_library_parts_config(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) + assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS + assert lumpdesign.export_to_aedt.substrate_er == "4.5" + assert lumpdesign.export_to_aedt.substrate_resistivity == "5.8E+07 " + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "500 nm" + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "2 mm" + assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.035 " + + def test_save_library_parts_config(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumpdesign.export_to_aedt.substrate_er = "2.25" + lumpdesign.export_to_aedt.substrate_resistivity = "4.2E+07 " + lumpdesign.export_to_aedt.substrate_conductor_thickness = "350 nm" + lumpdesign.export_to_aedt.substrate_dielectric_height = "3 mm" + lumpdesign.export_to_aedt.substrate_loss_tangent = "0.065 " + lumpdesign.export_to_aedt.save_library_parts_config(resource_path("library_parts_test.cfg")) + lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts_test.cfg")) + assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS + assert lumpdesign.export_to_aedt.substrate_er == "2.25" + assert lumpdesign.export_to_aedt.substrate_resistivity == "4.2E+07 " + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "350 nm" + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "3 mm" + assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.065 " + + def test_import_tuned_variables(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.simulate_after_export_enabled = True + lumpdesign.export_to_aedt.optimize_after_export_enabled = True + lumpdesign.export_to_aedt.export_design() + assert lumpdesign.export_to_aedt.import_tuned_variables().splitlines() == read_resource_file( + "imported_netlist.ckt" + ) + + def test_part_libraries(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt._open_aedt_export() + + assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.LUMPED + assert len(PartLibraries) == 3 + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS + + def test_interconnect_length_to_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "2" + lumpdesign.export_to_aedt.interconnect_length_to_width_ratio = "3" + assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "3" + + def test_interconnect_minimum_length_to_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" + lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" + assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" + + def test_interconnect_maximum_length_to_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" + lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" + assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" + + def test_interconnect_line_to_termination_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" + lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" + assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" + + def test_interconnect_minimum_line_to_termination_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" + lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" + assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" + + def test_interconnect_maximum_line_to_termination_width_ratio(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" + lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" + assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" + + def test_interconnect_length_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_length_value == "2.54 mm" + lumpdesign.export_to_aedt.interconnect_length_value = "3 mm" + assert lumpdesign.export_to_aedt.interconnect_length_value == "3 mm" + + def test_interconnect_minimum_length_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" + lumpdesign.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" + assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" + + def test_interconnect_maximum_length_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" + lumpdesign.export_to_aedt.interconnect_maximum_length_value = "6 mm" + assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "6 mm" + + def test_interconnect_line_width_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_line_width_value == "1.27 mm" + lumpdesign.export_to_aedt.interconnect_line_width_value = "2 mm" + assert lumpdesign.export_to_aedt.interconnect_line_width_value == "2 mm" + + def test_interconnect_minimum_width_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "635 um" + lumpdesign.export_to_aedt.interconnect_minimum_width_value = "725 um" + assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "725 um" + + def test_interconnect_maximum_width_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" + lumpdesign.export_to_aedt.interconnect_maximum_width_value = "3 mm" + assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "3 mm" + + def test_interconnect_inductor_tolerance_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "1" + lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value = "10" + assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "10" + + def test_interconnect_capacitor_tolerance_value(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "1" + lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value = "10" + assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "10" + + def test_interconnect_geometry_optimization_enabled(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == True + lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled = False + assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == False + + def test_substrate_type(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP + assert len(SubstrateType) == 5 + for substrate in SubstrateType: + lumpdesign.export_to_aedt.substrate_type = substrate + assert lumpdesign.export_to_aedt.substrate_type == substrate + + def test_substrate_er(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA + assert len(SubstrateEr) == 17 + for er in SubstrateEr: + lumpdesign.export_to_aedt.substrate_er = er + assert lumpdesign.export_to_aedt.substrate_er == er + lumpdesign.export_to_aedt.substrate_er = "3.2" + assert lumpdesign.export_to_aedt.substrate_er == "3.2" + + def test_substrate_resistivity(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD + assert len(SubstrateResistivity) == 11 + for resistivity in SubstrateResistivity: + lumpdesign.export_to_aedt.substrate_resistivity = resistivity + assert lumpdesign.export_to_aedt.substrate_resistivity == resistivity + lumpdesign.export_to_aedt.substrate_resistivity = "0.02" + assert lumpdesign.export_to_aedt.substrate_resistivity == "0.02" + + def test_substrate_loss_tangent(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA + assert len(SubstrateEr) == 17 + for loss in SubstrateEr: + lumpdesign.export_to_aedt.substrate_loss_tangent = loss + assert lumpdesign.export_to_aedt.substrate_loss_tangent == loss + lumpdesign.export_to_aedt.substrate_loss_tangent = "0.0002" + assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.0002" + + def test_substrate_conductor_thickness(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" + lumpdesign.export_to_aedt.substrate_conductor_thickness = "1.25 um" + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "1.25 um" + + def test_substrate_dielectric_height(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" + lumpdesign.export_to_aedt.substrate_dielectric_height = "1.22 mm" + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.22 mm" + + def test_substrate_unbalanced_lower_dielectric_height(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE + lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True + assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" + lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height = "5.2 mm" + assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "5.2 mm" + + def test_substrate_suspend_dielectric_height(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.substrate_type = SubstrateType.SUSPEND + assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" + lumpdesign.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" + assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "3.2 mm" + + def test_substrate_cover_height(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.substrate_cover_height_enabled = True + assert lumpdesign.export_to_aedt.substrate_cover_height == "6.35 mm" + lumpdesign.export_to_aedt.substrate_cover_height = "2.5 mm" + assert lumpdesign.export_to_aedt.substrate_cover_height == "2.5 mm" + + def test_substrate_unbalanced_stripline_enabled(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE + assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == False + lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True + assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == True + + def test_substrate_cover_height_enabled(self): + lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign.export_to_aedt._open_aedt_export() + assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == False + lumpdesign.export_to_aedt.substrate_cover_height_enabled = True + assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == True diff --git a/_unittest/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py b/_unittest/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py index a728b75d77b..09d87471f80 100644 --- a/_unittest/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py +++ b/_unittest/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py @@ -37,13 +37,13 @@ class TestClass: def test_row_count(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() assert lumpdesign.optimization_goals_table.row_count == 2 def test_row(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() assert lumpdesign.optimization_goals_table.row(0) == [ "200 MHz", "1 GHz", @@ -71,7 +71,7 @@ def test_row(self): def test_update_row(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.update_row( 0, lower_frequency="100 MHz", upper_frequency="2 GHz", condition=">", weight="0.7" ) @@ -88,7 +88,7 @@ def test_update_row(self): def test_append_row(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.append_row("100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y") assert lumpdesign.optimization_goals_table.row(2) == [ "100 MHz", @@ -103,7 +103,7 @@ def test_append_row(self): def test_insert_row(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.insert_row( 1, "100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y" ) @@ -120,7 +120,7 @@ def test_insert_row(self): def test_remove_row(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.remove_row(1) assert lumpdesign.optimization_goals_table.row_count == 1 assert lumpdesign.optimization_goals_table.row(0) == [ @@ -136,7 +136,7 @@ def test_remove_row(self): def test_adjust_goal_frequency(self): lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.set_design_goals() + lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.adjust_goal_frequency("150 MHz") assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.LOWER_FREQUENCY.value] == "350 MHz" assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.UPPER_FREQUENCY.value] == "1.15 GHz" diff --git a/examples/08-FilterSolutions/Lumped_Element_Response.py b/examples/08-FilterSolutions/Lumped_Element_Response.py index 1e0bb85cd20..971463f3195 100644 --- a/examples/08-FilterSolutions/Lumped_Element_Response.py +++ b/examples/08-FilterSolutions/Lumped_Element_Response.py @@ -14,14 +14,14 @@ import ansys.aedt.core.filtersolutions_core.attributes from ansys.aedt.core.filtersolutions_core.attributes import FilterType, FilterClass, FilterImplementation from ansys.aedt.core.filtersolutions_core.ideal_response import FrequencyResponseColumn +from ansys.aedt.core.filtersolutions_core.export_to_aedt import PartLibraries, ExportFormat import matplotlib.pyplot as plt ############################################################################### # Create the lumped design # ~~~~~~~~~~~~~~~~~~~~~~~~ # Create a lumped element filter design and assign the class, type, frequency, and order. -design = ansys.aedt.core.FilterSolutions(version="2025.1", implementation_type= FilterImplementation.LUMPED) - +design = ansys.aedt.core.FilterSolutions(version="2025.1", implementation_type= FilterImplementation.LUMPED) design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.BUTTERWORTH design.attributes.pass_band_center_frequency = "1G" diff --git a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py index 24e7ce7dbf4..31241b1a7dc 100644 --- a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py +++ b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py @@ -27,8 +27,10 @@ from ctypes import c_bool from ctypes import c_char_p from ctypes import c_int +from ctypes import create_string_buffer from enum import Enum import os +from typing import Union import ansys.aedt.core @@ -59,6 +61,116 @@ class ExportCreationMode(Enum): APPEND = 1 +class PartLibraries(Enum): + """Provides an enum of export format types. + + **Attributes:** + + - LUMPED = Represents a lumped part library. + - INTERCONNECT_ONLY = Represents an interconnect only part library. + - MODELITHICS = Represents a ``Modelithics`` part library. + """ + + LUMPED = 0 + INTERCONNECT = 1 + MODELITHICS = 2 + + +class SubstrateType(Enum): + """Provides an enum of substrate types for various materials. + + **Attributes:** + + - RGLC = Represents a RGLC substrate type. + - STRIPLINE = Represents a stripline substrate type. + - MICROSTRIP = Represents a microstrip substrate type. + - SUSPEND = Represents a suspended substrate type. + - INVERTED = Represents an inverted substrate type. + """ + + RGLC = 0 + STRIPLINE = 1 + MICROSTRIP = 2 + SUSPEND = 3 + INVERTED = 4 + + +class SubstrateEr(Enum): + """Provides an enum of substrate relative permitivity (``Er``) for various materials.. + The enum values represent common materials used in substrates and their associated ``Er`` value. + + **Attributes:** + + - AIR = Represents air substrate with an ``Er`` of ``1.00``. + - ALUMINA = Represents alumina substrate with an ``Er`` of ``9.8``. + - GA_AS = Represents Gallium Arsenide substrate with an ``Er`` of ``12.9``. + - GERMANIUM = Represents Germanium substrate with an ``Er`` of ``16.0``. + - INDIUM_PHOSPHATE = Represents Indium Phosphate substrate with an ``Er`` of ``12.4``. + - SILICON = Represents Silicon substrate with an ``Er`` of ``11.7``. + - QUARTZ = Represents Quartz substrate with an ``Er`` of ``3.78``. + - RT_DUROID_5880 = Represents RT Duroid 5880 substrate with an ``Er`` of ``2.2``. + - RT_DUROID_5870 = Represents RT Duroid 5870 substrate with an ``Er`` of ``2.33``. + - RT_DUROID_6006 = Represents RT Duroid 6006 substrate with an ``Er`` of ``6.15``. + - G_10_LOW_RESIN = Represents G-10 Low Resin substrate with an ``Er`` of ``4.8``. + - G_10_HIGH_RESIN = Represents G-10 High Resin substrate with an ``Er`` of ``3.5``. + - PAPER_PHONELIC = Represents Paper Phenolic substrate with an ``Er`` of ``4.5``. + - POLYTHYLENE = Represents Polyethylene substrate with an ``Er`` of ``2.25``. + - POLYSTYRENE = Represents Polystyrene substrate with an ``Er`` of ``2.56``. + - CORNING_GLASS_7059 = Represents Corning Glass 7059 substrate with an ``Er`` of ``7.9``. + - BERYLIUM_OXIDE = Represents Beryllium Oxide substrate with an ``Er`` of ``6.7``. + """ + + AIR = 0 + ALUMINA = 1 + GA_AS = 2 + GERMANIUM = 3 + INDIUM_PHOSPHATE = 4 + SILICON = 5 + QUARTZ = 6 + RT_DUROID_5880 = 7 + RT_DUROID_5870 = 8 + RT_DUROID_6006 = 9 + G_10_LOW_RESIN = 10 + G_10_HIGH_RESIN = 11 + PAPER_PHONELIC = 12 + POLYTHYLENE = 13 + POLYSTYRENE = 14 + CORNING_GLASS_7059 = 15 + BERYLIUM_OXIDE = 16 + + +class SubstrateResistivity(Enum): + """Provides an enum of substrate resistivity types for various materials. + The enum values represent common materials used in substrates and their associated resistivity index. + + **Attributes:** + + - IDEAL: Represents an ideal, perfect conductor, ``0`` with respect to copper resistivity. + - SILVER: Represents Silver resitivity, ``0.95`` with respect to copper resistivity. + - COPPER: Represents Copper, ``1.00`` as referernce resistivity. + - GOLD: Represents Gold, ``1.43`` with respect to copper resistivity. + - ALUMINUM: Represents Aluminum, ``1.67`` with respect to copper resistivity. + - MAGNESIUM: Represents Magnesium, ``2.67`` with respect to copper resistivity. + - TUNGSTEN: Represents Tungsten, ``3.23`` with respect to copper resistivity. + - ZINC: Represents Zinc, ``3.56`` with respect to copper resistivity. + - NICKEL: Represents Nickel, ``4.00`` with respect to copper resistivity. + - IRON: Represents Iron, ``5.80`` with respect to copper resistivity. + - PLATINUM: Represents Platinum, ``6.34`` with respect to copper resistivity. + """ + + IDEAL = 0 + SILVER = 1 + COPPER = 2 + GOLD = 3 + ALUMINUM = 4 + MAGNESIUM = 5 + TUNGSTEN = 6 + ZINC = 7 + NICKEL = 8 + IRON = 9 + PLATINUM = 10 + + class ExportToAedt: """Defines attributes and parameters for exporting filter . @@ -69,6 +181,7 @@ def __init__(self): self._dll = ansys.aedt.core.filtersolutions_core._dll_interface()._dll self._dll_interface = ansys.aedt.core.filtersolutions_core._dll_interface() self._define_export_to_desktop_dll_functions() + self._substrate_er = SubstrateEr.AIR.value # Default to AIR's Er value def _define_export_to_desktop_dll_functions(self): """Define C++ API DLL functions.""" @@ -158,16 +271,235 @@ def _define_export_to_desktop_dll_functions(self): self._dll.getOptimizeAfterExport.argtype = POINTER(c_bool) self._dll.getOptimizeAfterExport.restype = c_int + self._dll.loadLibraryPartsConf.argtype = c_char_p + self._dll.loadLibraryPartsConf.restype = c_int + + self._dll.saveLibraryPartsConf.argtype = c_char_p + self._dll.saveLibraryPartsConf.restype = c_int + + self._dll.importTunedVariablesSize.argtype = POINTER(c_int) + self._dll.importTunedVariablesSize.restype = c_int + self._dll.importTunedVariables.argtypes = [c_char_p, c_int] + self._dll.importTunedVariables.restype = c_int + def _open_aedt_export(self): """Open export page to accept manipulate export parameters""" status = self._dll.openLumpedExportPage() ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + self._dll.setPartLibraries.argtype = c_int + self._dll.setPartLibraries.restype = c_int + self._dll.getPartLibraries.argtype = POINTER(c_int) + self._dll.getPartLibraries.restype = c_int + + self._dll.setLengthToWidthRatio.argtype = c_char_p + self._dll.setLengthToWidthRatio.restype = c_int + self._dll.getLengthToWidthRatio.argtypes = [c_char_p, c_int] + self._dll.getLengthToWidthRatio.restype = c_int + + self._dll.setLowerLengthGeometricLimitRatio.argtype = c_char_p + self._dll.setLowerLengthGeometricLimitRatio.restype = c_int + self._dll.getLowerLengthGeometricLimitRatio.argtypes = [c_char_p, c_int] + self._dll.getLowerLengthGeometricLimitRatio.restype = c_int + + self._dll.setUpperLengthGeometricLimitRatio.argtype = c_char_p + self._dll.setUpperLengthGeometricLimitRatio.restype = c_int + self._dll.getUpperLengthGeometricLimitRatio.argtypes = [c_char_p, c_int] + self._dll.getUpperLengthGeometricLimitRatio.restype = c_int + + self._dll.setLineWidthToTerminationWidthRatio.argtype = c_char_p + self._dll.setLineWidthToTerminationWidthRatio.restype = c_int + self._dll.getLineWidthToTerminationWidthRatio.argtypes = [c_char_p, c_int] + self._dll.getLineWidthToTerminationWidthRatio.restype = c_int + + self._dll.setLowerWidthGeometricLimitRatio.argtype = c_char_p + self._dll.setLowerWidthGeometricLimitRatio.restype = c_int + self._dll.getLowerWidthGeometricLimitRatio.argtypes = [c_char_p, c_int] + self._dll.getLowerWidthGeometricLimitRatio.restype = c_int + + self._dll.setUpperWidthGeometricLimitRatio.argtype = c_char_p + self._dll.setUpperWidthGeometricLimitRatio.restype = c_int + self._dll.getUpperWidthGeometricLimitRatio.argtypes = [c_char_p, c_int] + self._dll.getUpperWidthGeometricLimitRatio.restype = c_int + + self._dll.setLengthToWidthValue.argtype = c_char_p + self._dll.setLengthToWidthValue.restype = c_int + self._dll.getLengthToWidthValue.argtypes = [c_char_p, c_int] + self._dll.getLengthToWidthValue.restype = c_int + + self._dll.setLowerLengthGeometricLimitValue.argtype = c_char_p + self._dll.setLowerLengthGeometricLimitValue.restype = c_int + self._dll.getLowerLengthGeometricLimitValue.argtypes = [c_char_p, c_int] + self._dll.getLowerLengthGeometricLimitValue.restype = c_int + + self._dll.setUpperLengthGeometricLimitValue.argtype = c_char_p + self._dll.setUpperLengthGeometricLimitValue.restype = c_int + self._dll.getUpperLengthGeometricLimitValue.argtypes = [c_char_p, c_int] + self._dll.getUpperLengthGeometricLimitValue.restype = c_int + + self._dll.setLineWidthToTerminationWidthValue.argtype = c_char_p + self._dll.setLineWidthToTerminationWidthValue.restype = c_int + self._dll.getLineWidthToTerminationWidthValue.argtypes = [c_char_p, c_int] + self._dll.getLineWidthToTerminationWidthValue.restype = c_int + + self._dll.setLowerWidthGeometricLimitValue.argtype = c_char_p + self._dll.setLowerWidthGeometricLimitValue.restype = c_int + self._dll.getLowerWidthGeometricLimitValue.argtypes = [c_char_p, c_int] + self._dll.getLowerWidthGeometricLimitValue.restype = c_int + + self._dll.setUpperWidthGeometricLimitValue.argtype = c_char_p + self._dll.setUpperWidthGeometricLimitValue.restype = c_int + self._dll.getUpperWidthGeometricLimitValue.argtypes = [c_char_p, c_int] + self._dll.getUpperWidthGeometricLimitValue.restype = c_int + + self._dll.setInterConnectInductorTolerance.argtype = c_char_p + self._dll.setInterConnectInductorTolerance.restype = c_int + self._dll.getInterConnectInductorTolerance.argtypes = [c_char_p, c_int] + self._dll.getInterConnectInductorTolerance.restype = c_int + + self._dll.setInterConnectCapacitorTolerance.argtype = c_char_p + self._dll.setInterConnectCapacitorTolerance.restype = c_int + self._dll.getInterConnectCapacitorTolerance.argtypes = [c_char_p, c_int] + self._dll.getInterConnectCapacitorTolerance.restype = c_int + + self._dll.setInterconnectGeometryOptimization.argtype = c_bool + self._dll.setInterconnectGeometryOptimization.restype = c_int + self._dll.getInterconnectGeometryOptimization.argtype = POINTER(c_bool) + self._dll.getInterconnectGeometryOptimization.restype = c_int + + self._dll.setSubstrateType.argtype = c_char_p + self._dll.setSubstrateType.restype = int + self._dll.getSubstrateType.argtypes = [c_char_p, c_int] + self._dll.getSubstrateType.restype = int + + self._dll.setEr.argtype = [c_char_p, c_int] + self._dll.setEr.restype = c_int + self._dll.getEr.argtype = [c_char_p, POINTER(c_int), c_int] + self._dll.getEr.restype = c_int + + self._dll.setResistivity.argtype = [c_char_p, c_int] + self._dll.setResistivity.restype = c_int + self._dll.getResistivity.argtype = [c_char_p, POINTER(c_int), c_int] + self._dll.getResistivity.restype = c_int + + self._dll.setLossTangent.argtype = [c_char_p, c_int] + self._dll.setLossTangent.restype = c_int + self._dll.getLossTangent.argtype = [c_char_p, POINTER(c_int), c_int] + self._dll.getLossTangent.restype = c_int + + self._dll.setConductorThickness.argtype = c_char_p + self._dll.setConductorThickness.restype = c_int + self._dll.getConductorThickness.argtypes = [c_char_p, c_int] + self._dll.getConductorThickness.restype = c_int + + self._dll.setDielectricHeight.argtype = c_char_p + self._dll.setDielectricHeight.restype = c_int + self._dll.getDielectricHeight.argtypes = [c_char_p, c_int] + self._dll.getDielectricHeight.restype = c_int + + self._dll.setLowerDielectricHeight.argtype = c_char_p + self._dll.setLowerDielectricHeight.restype = c_int + self._dll.getLowerDielectricHeight.argtypes = [c_char_p, c_int] + self._dll.getLowerDielectricHeight.restype = c_int + + self._dll.setSuspendDielectricHeight.argtype = c_char_p + self._dll.setSuspendDielectricHeight.restype = c_int + self._dll.getSuspendDielectricHeight.argtypes = [c_char_p, c_int] + self._dll.getSuspendDielectricHeight.restype = c_int + + self._dll.setCoverHeight.argtype = c_char_p + self._dll.setCoverHeight.restype = c_int + self._dll.getCoverHeight.argtypes = [c_char_p, c_int] + self._dll.getCoverHeight.restype = c_int + + self._dll.setUnbalancedStripLine.argtype = c_bool + self._dll.setUnbalancedStripLine.restype = c_int + self._dll.getUnbalancedStripLine.argtype = POINTER(c_bool) + self._dll.getUnbalancedStripLine.restype = c_int + + self._dll.setGroundedCoverAboveLine.argtype = c_bool + self._dll.setGroundedCoverAboveLine.restype = c_int + self._dll.getGroundedCoverAboveLine.argtype = POINTER(c_bool) + self._dll.getGroundedCoverAboveLine.restype = c_int + + self._dll.setModelithicsIncludeInterconnect.argtype = c_bool + self._dll.setModelithicsIncludeInterconnect.restype = c_int + self._dll.getModelithicsIncludeInterconnect.argtype = POINTER(c_bool) + self._dll.getModelithicsIncludeInterconnect.restype = c_int + + self._dll.getModelithicsInductorsListCount.argtype = POINTER(c_int) + self._dll.getModelithicsInductorsListCount.restype = c_int + + self._dll.getModelithicsInductorsList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsInductorsList.restype = c_int + + self._dll.setModelithicsInductors.argtype = c_char_p + self._dll.setModelithicsInductors.restype = c_int + self._dll.getModelithicsInductors.argtypes = [c_char_p, c_int] + self._dll.getModelithicsInductors.restype = c_int + + self._dll.getModelithicsInductorsFamilyListCount.argtype = POINTER(c_int) + self._dll.getModelithicsInductorsFamilyListCount.restype = c_int + + self._dll.getModelithicsInductorsFamilyList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsInductorsFamilyList.restype = c_int + + self._dll.addModelithicsInductorsFamily.argtype = c_char_p + self._dll.addModelithicsInductorsFamily.restype = c_int + + self._dll.removeModelithicsInductorsFamily.argtype = c_char_p + self._dll.removeModelithicsInductorsFamily.restype = c_int + + self._dll.getModelithicsCapacitorsListCount.argtype = POINTER(c_int) + self._dll.getModelithicsCapacitorsListCount.restype = c_int + + self._dll.getModelithicsCapacitorsList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsCapacitorsList.restype = c_int + + self._dll.setModelithicsCapacitors.argtype = c_char_p + self._dll.setModelithicsCapacitors.restype = c_int + self._dll.getModelithicsCapacitors.argtypes = [c_char_p, c_int] + self._dll.getModelithicsCapacitors.restype = c_int + + self._dll.getModelithicsCapacitorsFamilyListCount.argtype = POINTER(c_int) + self._dll.getModelithicsCapacitorsFamilyListCount.restype = c_int + + self._dll.getModelithicsCapacitorsFamilyList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsCapacitorsFamilyList.restype = c_int + + self._dll.addModelithicsCapacitorsFamily.argtype = c_char_p + self._dll.addModelithicsCapacitorsFamily.restype = c_int + + self._dll.removeModelithicsCapacitorsFamily.argtype = c_char_p + self._dll.removeModelithicsCapacitorsFamily.restype = c_int + + self._dll.getModelithicsResistorsListCount.argtype = POINTER(c_int) + self._dll.getModelithicsResistorsListCount.restype = c_int + + self._dll.getModelithicsResistorsList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsResistorsList.restype = c_int + + self._dll.setModelithicsResistors.argtype = c_char_p + self._dll.setModelithicsResistors.restype = c_int + self._dll.getModelithicsResistors.argtypes = [c_char_p, c_int] + self._dll.getModelithicsResistors.restype = c_int + + self._dll.getModelithicsResistorsFamilyListCount.argtype = POINTER(c_int) + self._dll.getModelithicsResistorsFamilyListCount.restype = c_int + + self._dll.getModelithicsResistorsFamilyList.argtype = [c_int, c_char_p, c_int] + self._dll.getModelithicsResistorsFamilyList.restype = c_int + + self._dll.addModelithicsResistorsFamily.argtype = c_char_p + self._dll.addModelithicsResistorsFamily.restype = c_int + self._dll.removeModelithicsResistorsFamily.argtype = c_char_p + self._dll.removeModelithicsResistorsFamily.restype = c_int @property def schematic_name(self) -> str: """Name of the exported schematic in ``AEDT``, displayed as the project and design names. The default name is ``FilterSolutions`` if not specified. + Returns ------- str @@ -464,7 +796,7 @@ def optimitrics_enabled(self, optimitrics_enabled: bool): @property def optimize_after_export_enabled(self) -> bool: - """Flag indicating if the optimization option after exporting to ``AEDT`` is enabled. + """Flag indicating if the optimization after exporting to ``AEDT`` is enabled. Returns ------- @@ -480,7 +812,7 @@ def optimize_after_export_enabled(self, optimize_after_export_enabled: bool): status = self._dll.setOptimizeAfterExport(optimize_after_export_enabled) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - def export_design(self, export_format: ExportFormat.DIRECT_TO_AEDT, export_creation_mode=None, export_path=None): + def export_design(self, export_format=None, export_creation_mode=None, export_path=None): """Export the design directly to ``AEDT` or generate a ``Python`` script for exporting. When exporting to ``AEDT``, the design can either be appended to an existing project or overwrite it. When generating a Python script, the script is created and saved to the specified file location. @@ -489,7 +821,7 @@ def export_design(self, export_format: ExportFormat.DIRECT_TO_AEDT, export_creat ---------- export_format : `ExportFormat` The export format type. - The default is ``DIRECT_TO_AEDT``. + The default is ``None``. design_creation_mode : `ExportCreationMode` The design creation mode. The default is ``None``. @@ -497,6 +829,8 @@ def export_design(self, export_format: ExportFormat.DIRECT_TO_AEDT, export_creat The export path for Python script. The default is ``None``. """ + if export_format is None: + export_format = ExportFormat.DIRECT_TO_AEDT if export_creation_mode is None: export_creation_mode = ExportCreationMode.OVERWRITE if export_path is None: @@ -509,7 +843,917 @@ def export_design(self, export_format: ExportFormat.DIRECT_TO_AEDT, export_creat status = self._dll.exportDesign(export_format.value, export_creation_mode.value, export_path_bytes) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + def load_library_parts_config(self, load_library_parts_config_string): + self._dll_interface.set_string(self._dll.loadLibraryPartsConf, load_library_parts_config_string) + + def save_library_parts_config(self, save_library_parts_config_string): + self._dll_interface.set_string(self._dll.saveLibraryPartsConf, save_library_parts_config_string) + def import_tuned_variables(self): """Imported ``AEDT`` tuned parameter variables back into the ``FilterSolutions`` project.""" - status = self._dll.importTunedVariables() + size = c_int() + status = self._dll.importTunedVariablesSize(byref(size)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + circuit_response_string = self._dll_interface.get_string(self._dll.importTunedVariables, max_size=size.value) + return circuit_response_string + + @property + def part_libraries(self) -> PartLibraries: + """Part libraries selection. The default is ``LUMPED``. + The ``PartLibraries`` enum provides a list of all options. + + Returns + ------- + :enum:`PartLibraries` + + """ + index = c_int() + part_libraries_list = list(PartLibraries) + status = self._dll.getPartLibraries(byref(index)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + part_libraries = part_libraries_list[index.value] + return part_libraries + + @part_libraries.setter + def part_libraries(self, library_type: PartLibraries): + status = self._dll.setPartLibraries(library_type.value) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def interconnect_length_to_width_ratio(self) -> str: + """Length to width ratio of interconnect line. + The length to width ratio is a measure of the proportion between the length and width of the interconnect line. + This ratio is important for determining the electrical characteristics of the interconnect, such as impedance + and signal integrity. + The default is ``2``. + + Returns + ------- + str + """ + interconnect_length_to_width_ratio_string = self._dll_interface.get_string(self._dll.getLengthToWidthRatio) + return interconnect_length_to_width_ratio_string + + @interconnect_length_to_width_ratio.setter + def interconnect_length_to_width_ratio(self, interconnect_length_to_width_ratio_string): + self._dll_interface.set_string(self._dll.setLengthToWidthRatio, interconnect_length_to_width_ratio_string) + + @property + def interconnect_minimum_length_to_width_ratio(self) -> str: + """Minimum length to width ratio of interconnect line. + The minimum length to width ratio is a measure of the smallest proportion between the length and width + of the interconnect line that is allowed. This parameter is used to determine the minimum dimensions of + interconnect lines for optimization purposes. + The default is ``0.5``. + + Returns + ------- + str + """ + interconnect_minimum_length_to_width_ratio_string = self._dll_interface.get_string( + self._dll.getLowerLengthGeometricLimitRatio + ) + return interconnect_minimum_length_to_width_ratio_string + + @interconnect_minimum_length_to_width_ratio.setter + def interconnect_minimum_length_to_width_ratio(self, interconnect_minimum_length_to_width_ratio_string): + self._dll_interface.set_string( + self._dll.setLowerLengthGeometricLimitRatio, interconnect_minimum_length_to_width_ratio_string + ) + + @property + def interconnect_maximum_length_to_width_ratio(self) -> str: + """Maximum length to width ratio of interconnect line. + The maximum length to width ratio is a measure of the largest proportion between the length and width + of the interconnect line that is allowed. This parameter is used to determine the maximum dimensions of + interconnect lines for optimization purposes. + The default is ``2``. + + Returns + ------- + str + """ + interconnect_maximum_length_to_width_ratio_string = self._dll_interface.get_string( + self._dll.getUpperLengthGeometricLimitRatio + ) + return interconnect_maximum_length_to_width_ratio_string + + @interconnect_maximum_length_to_width_ratio.setter + def interconnect_maximum_length_to_width_ratio(self, interconnect_maximum_length_to_width_ratio_string): + self._dll_interface.set_string( + self._dll.setUpperLengthGeometricLimitRatio, interconnect_maximum_length_to_width_ratio_string + ) + + @property + def interconnect_line_to_termination_width_ratio(self) -> str: + """Line width to termination width ratio of interconnect line. + The line width to termination width ratio is a measure of the proportion between the width of the + interconnect line and the width of its termination. This ratio is crucial for ensuring proper + impedance matching and signal integrity at the points where the interconnect line connects to + other components or circuits. + The default is ``1``. + + Returns + ------- + str + """ + interconnect_line_to_termination_width_ratio_string = self._dll_interface.get_string( + self._dll.getLineWidthToTerminationWidthRatio + ) + return interconnect_line_to_termination_width_ratio_string + + @interconnect_line_to_termination_width_ratio.setter + def interconnect_line_to_termination_width_ratio(self, interconnect_line_to_termination_width_ratio_string): + self._dll_interface.set_string( + self._dll.setLineWidthToTerminationWidthRatio, interconnect_line_to_termination_width_ratio_string + ) + + @property + def interconnect_minimum_line_to_termination_width_ratio(self) -> str: + """Minimum line width to termination width ratio of interconnect line. + The minimum line width to termination width ratio is a measure of the smallest proportion between the + width of the interconnect line and the width of its termination that is allowed. This parameter is used + to determine the minimum dimensions of interconnect lines for optimization purposes. + The default is ``0.5``. + + Returns + ------- + str + """ + interconnect_minimum_line_to_termination_width_ratio_string = self._dll_interface.get_string( + self._dll.getLowerWidthGeometricLimitRatio + ) + return interconnect_minimum_line_to_termination_width_ratio_string + + @interconnect_minimum_line_to_termination_width_ratio.setter + def interconnect_minimum_line_to_termination_width_ratio( + self, interconnect_minimum_line_to_termination_width_ratio_string + ): + self._dll_interface.set_string( + self._dll.setLowerWidthGeometricLimitRatio, interconnect_minimum_line_to_termination_width_ratio_string + ) + + @property + def interconnect_maximum_line_to_termination_width_ratio(self) -> str: + """Maximum line width to termination width ratio of interconnect line. + The maximum line width to termination width ratio is a measure of the largest proportion between the + width of the interconnect line and the width of its termination that is allowed. This parameter is used + to determine the maximum dimensions of interconnect lines for optimization purposes. + The default is ``2``. + + Returns + ------- + str + """ + interconnect_maximum_line_to_termination_width_ratio_string = self._dll_interface.get_string( + self._dll.getUpperWidthGeometricLimitRatio + ) + return interconnect_maximum_line_to_termination_width_ratio_string + + @interconnect_maximum_line_to_termination_width_ratio.setter + def interconnect_maximum_line_to_termination_width_ratio( + self, interconnect_maximum_line_to_termination_width_ratio_string + ): + self._dll_interface.set_string( + self._dll.setUpperWidthGeometricLimitRatio, interconnect_maximum_line_to_termination_width_ratio_string + ) + + @property + def interconnect_length_value(self) -> str: + """Interconnect physical length value. + The interconnect physical length value represents the actual length of the interconnect line in the design. + This value is crucial for determining the electrical characteristics of the interconnect, such as signal delay, + impedance, and potential signal loss. Accurate length measurements are essential for ensuring that the + interconnect performsas expected in high-frequency and high-speed applications. + The default is ``2.54 mm``. + + Returns + ------- + str + """ + interconnect_length_value_string = self._dll_interface.get_string(self._dll.getLengthToWidthValue) + return interconnect_length_value_string + + @interconnect_length_value.setter + def interconnect_length_value(self, interconnect_length_value_string): + self._dll_interface.set_string(self._dll.setLengthToWidthValue, interconnect_length_value_string) + + @property + def interconnect_minimum_length_value(self) -> str: + """Minimum value of interconnect physical length. + The minimum value of the interconnect physical length represents the smallest length that the interconnect + line can have in the design. This value is used to determine the minimum dimensions of interconnect lines + for optimization purposes. + The default is ``1.27 mm``. + + Returns + ------- + str + """ + interconnect_minimum_length_value_string = self._dll_interface.get_string( + self._dll.getLowerLengthGeometricLimitValue + ) + return interconnect_minimum_length_value_string + + @interconnect_minimum_length_value.setter + def interconnect_minimum_length_value(self, interconnect_minimum_length_value_string): + self._dll_interface.set_string( + self._dll.setLowerLengthGeometricLimitValue, interconnect_minimum_length_value_string + ) + + @property + def interconnect_maximum_length_value(self) -> str: + """Maximum value of interconnect physical length. + The maximum value of the interconnect physical length represents the largest length that the interconnect + line can have in the design. This value is used to determine the maximum dimensions of interconnect lines + for optimization purposes. + The default is ``5.08 mm``. + + Returns + ------- + str + """ + interconnect_maximum_length_value_string = self._dll_interface.get_string( + self._dll.getUpperLengthGeometricLimitValue + ) + return interconnect_maximum_length_value_string + + @interconnect_maximum_length_value.setter + def interconnect_maximum_length_value(self, interconnect_maximum_length_value_string): + self._dll_interface.set_string( + self._dll.setUpperLengthGeometricLimitValue, interconnect_maximum_length_value_string + ) + + @property + def interconnect_line_width_value(self) -> str: + """Interconnect conductor width value. + The interconnect conductor width value represents the actual width of the interconnect line in the design. + This value is crucial for determining the electrical characteristics of the interconnect, such as impedance, + signal integrity, and potential signal loss. Accurate width measurements are essential for ensuring that the + interconnect performs as expected in high-frequency and high-speed applications. + The default is ``1.27 mm``. + + Returns + ------- + str + """ + interconnect_line_width_value_string = self._dll_interface.get_string( + self._dll.getLineWidthToTerminationWidthValue + ) + return interconnect_line_width_value_string + + @interconnect_line_width_value.setter + def interconnect_line_width_value(self, interconnect_line_width_value_string): + self._dll_interface.set_string( + self._dll.setLineWidthToTerminationWidthValue, interconnect_line_width_value_string + ) + + @property + def interconnect_minimum_width_value(self) -> str: + """Minimum value of interconnect conductor width. + The minimum value of the interconnect conductor width represents the smallest width that the interconnect + line can have in the design. This value is used to determine the minimum dimensions of interconnect lines + for optimization purposes. + The default is ``635 um``. + + Returns + ------- + str + """ + interconnect_minimum_width_value_string = self._dll_interface.get_string( + self._dll.getLowerWidthGeometricLimitValue + ) + return interconnect_minimum_width_value_string + + @interconnect_minimum_width_value.setter + def interconnect_minimum_width_value(self, interconnect_minimum_width_value_string): + self._dll_interface.set_string( + self._dll.setLowerWidthGeometricLimitValue, interconnect_minimum_width_value_string + ) + + @property + def interconnect_maximum_width_value(self) -> str: + """Maximum value of interconnect conductor width. + The maximum value of the interconnect conductor width represents the largest width that the interconnect + line can have in the design. This value is used to determine the maximum dimensions of interconnect lines + for optimization purposes. + The default is ``2.54 mm``. + + Returns + ------- + str + """ + interconnect_maximum_width_value_string = self._dll_interface.get_string( + self._dll.getUpperWidthGeometricLimitValue + ) + return interconnect_maximum_width_value_string + + @interconnect_maximum_width_value.setter + def interconnect_maximum_width_value(self, interconnect_maximum_width_value_string): + self._dll_interface.set_string( + self._dll.setUpperWidthGeometricLimitValue, interconnect_maximum_width_value_string + ) + + @property + def interconnect_inductor_tolerance_value(self) -> str: + """Tolerance value of interconnect inductor in ``%``. + The default is ``1``. + + Returns + ------- + str + """ + interconnect_inductor_tolerance_value_string = self._dll_interface.get_string( + self._dll.getInterConnectInductorTolerance + ) + return interconnect_inductor_tolerance_value_string + + @interconnect_inductor_tolerance_value.setter + def interconnect_inductor_tolerance_value(self, interconnect_inductor_tolerance_value_string): + self._dll_interface.set_string( + self._dll.setInterConnectInductorTolerance, interconnect_inductor_tolerance_value_string + ) + + @property + def interconnect_capacitor_tolerance_value(self) -> str: + """Tolerance value of interconnect capacitor in ``%``. + The default is ``1``. + + Returns + ------- + str + """ + interconnect_capacitor_tolerance_value_string = self._dll_interface.get_string( + self._dll.getInterConnectCapacitorTolerance + ) + return interconnect_capacitor_tolerance_value_string + + @interconnect_capacitor_tolerance_value.setter + def interconnect_capacitor_tolerance_value(self, interconnect_capacitor_tolerance_value_string): + self._dll_interface.set_string( + self._dll.setInterConnectCapacitorTolerance, interconnect_capacitor_tolerance_value_string + ) + + @property + def interconnect_geometry_optimization_enabled(self) -> bool: + """Flag indicating if the interconnect geometry optimization is enabled. + + Returns + ------- + bool + """ + interconnect_geometry_optimization_enabled = c_bool() + status = self._dll.getInterconnectGeometryOptimization(byref(interconnect_geometry_optimization_enabled)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(interconnect_geometry_optimization_enabled.value) + + @interconnect_geometry_optimization_enabled.setter + def interconnect_geometry_optimization_enabled(self, interconnect_geometry_optimization_enabled: bool): + status = self._dll.setInterconnectGeometryOptimization(interconnect_geometry_optimization_enabled) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + def update_interconncet_parameters(self): + """Update interconnect geometry equations with entered and selected parameters""" + status = self._dll.updateInterConnectParmeters() + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + def update_inductor_capacitor_tolerances(self): + """Update interconnect inductor and capacitor tolerances with entered values""" + status = self._dll.updatePartsTolerances() + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def substrate_type(self) -> SubstrateType: + """Subctrate type of the filter. + The ``SubstrateType`` enum provides a list of all substrate types. + + Returns + ------- + :enum:`SubstrateType` + """ + type_string = self._dll_interface.get_string(self._dll.getSubstrateType) + return self._dll_interface.string_to_enum(SubstrateType, type_string) + + @substrate_type.setter + def substrate_type(self, substrate_type: SubstrateType): + if substrate_type: + string_value = self._dll_interface.enum_to_string(substrate_type) + self._dll_interface.set_string(self._dll.setSubstrateType, string_value) + + @property + def substrate_er(self) -> Union[SubstrateType, str]: + """Substrate's relative permittivity ``Er``. + The value can be either a string or an instance of the ``SubstrateEr`` enum. + The default is ``9.8`` for ``SubstrateEr.ALUMINA``. + + Returns: + ------- + Union[SubstrateEr, str] + + """ + substrate_er_index = c_int() + substrate_er_value_str = create_string_buffer(100) + status = self._dll.getEr(substrate_er_value_str, byref(substrate_er_index), 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + if substrate_er_index.value in [e.value for e in SubstrateEr]: + return SubstrateEr(substrate_er_index.value) + else: + return substrate_er_value_str.value.decode("ascii") + + @substrate_er.setter + def substrate_er(self, substrate_input): + if substrate_input in list(SubstrateEr): + substrate_er_index = SubstrateEr(substrate_input).value + substrate_er_value = "" + elif isinstance(substrate_input, str): + substrate_er_value = substrate_input + substrate_er_index = -1 + else: + raise ValueError("Invalid substrate input. Must be a SubstrateEr enum member or a string.") + + substrate_er_value_bytes = bytes(substrate_er_value, "ascii") + status = self._dll.setEr(substrate_er_value_bytes, substrate_er_index) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def substrate_resistivity(self) -> Union[SubstrateResistivity, str]: + """Substrate's resistivity. + The value can be either a string or an instance of the ``SubstrateResistivity`` enum. + The default is ``1.43`` for ``SubstrateResistivity.GOLD``. + + Returns: + ------- + Union[SubstrateResistivity, str] + """ + substrate_resistivity_index = c_int() + substrate_resistivity_value_str = create_string_buffer(100) + status = self._dll.getResistivity(substrate_resistivity_value_str, byref(substrate_resistivity_index), 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + if substrate_resistivity_index.value in [e.value for e in SubstrateResistivity]: + return SubstrateResistivity(substrate_resistivity_index.value) + else: + return substrate_resistivity_value_str.value.decode("ascii") + + @substrate_resistivity.setter + def substrate_resistivity(self, substrate_input): + if substrate_input in list(SubstrateResistivity): + substrate_resistivity_index = SubstrateResistivity(substrate_input).value + substrate_resistivity_value = "" + elif isinstance(substrate_input, str): + substrate_resistivity_value = substrate_input + substrate_resistivity_index = -1 + else: + raise ValueError("Invalid substrate input. Must be a SubstrateResistivity enum member or a string.") + substrate_resistivity_value_bytes = bytes(substrate_resistivity_value, "ascii") + status = self._dll.setResistivity(substrate_resistivity_value_bytes, substrate_resistivity_index) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def substrate_loss_tangent(self) -> Union[SubstrateType, str]: + """Substrate's loss tangent. + The value can be either a string or an instance of the ``SubstrateEr`` enum. + The default is ``0.0005`` for ``SubstrateEr.ALUMINA``. + + Returns: + ------- + Union[SubstrateEr, str] + """ + substrate_loss_tangent_index = c_int() + substrate_loss_tangent_value_str = create_string_buffer(100) + status = self._dll.getLossTangent(substrate_loss_tangent_value_str, byref(substrate_loss_tangent_index), 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + if substrate_loss_tangent_index.value in [e.value for e in SubstrateEr]: + return SubstrateEr(substrate_loss_tangent_index.value) + else: + return substrate_loss_tangent_value_str.value.decode("ascii") + + @substrate_loss_tangent.setter + def substrate_loss_tangent(self, substrate_input): + if substrate_input in list(SubstrateEr): + substrate_loss_tangent_index = SubstrateEr(substrate_input).value + substrate_loss_tangent_value = "" + elif isinstance(substrate_input, str): + substrate_loss_tangent_value = substrate_input + substrate_loss_tangent_index = -1 + else: + raise ValueError("Invalid substrate input. Must be a SubstrateEr enum member or a string.") + substrate_loss_tangent_value_bytes = bytes(substrate_loss_tangent_value, "ascii") + status = self._dll.setLossTangent(substrate_loss_tangent_value_bytes, substrate_loss_tangent_index) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def substrate_conductor_thickness(self) -> str: + """Substrate's conductor thickness. + The default is ``2.54 um``. + + Returns + ------- + str + """ + substrate_conductor_thickness_string = self._dll_interface.get_string(self._dll.getConductorThickness) + return substrate_conductor_thickness_string + + @substrate_conductor_thickness.setter + def substrate_conductor_thickness(self, substrate_conductor_thickness_string): + self._dll_interface.set_string(self._dll.setConductorThickness, substrate_conductor_thickness_string) + + @property + def substrate_dielectric_height(self) -> str: + """Substrate's dielectric height. + The default is ``1.27 mm``. + + Returns + ------- + str + """ + substrate_dielectric_height_string = self._dll_interface.get_string(self._dll.getDielectricHeight) + return substrate_dielectric_height_string + + @substrate_dielectric_height.setter + def substrate_dielectric_height(self, substrate_dielectric_height_string): + self._dll_interface.set_string(self._dll.setDielectricHeight, substrate_dielectric_height_string) + + @property + def substrate_unbalanced_lower_dielectric_height(self) -> str: + """Substrate's lower dielectric height for unbalanced stripline substrate type. + The default is ``6.35 mm``. + + Returns + ------- + str + """ + substrate_unbalanced_lower_dielectric_height_string = self._dll_interface.get_string( + self._dll.getLowerDielectricHeight + ) + return substrate_unbalanced_lower_dielectric_height_string + + @substrate_unbalanced_lower_dielectric_height.setter + def substrate_unbalanced_lower_dielectric_height(self, substrate_unbalanced_lower_dielectric_height_string): + self._dll_interface.set_string( + self._dll.setLowerDielectricHeight, substrate_unbalanced_lower_dielectric_height_string + ) + + @property + def substrate_suspend_dielectric_height(self) -> str: + """Substrate's suspend dielectric height above ground plane for suspend and inverted substrate types. + The default is ``1.27 mm``. + + Returns + ------- + str + """ + substrate_suspend_dielectric_height_string = self._dll_interface.get_string( + self._dll.getSuspendDielectricHeight + ) + return substrate_suspend_dielectric_height_string + + @substrate_suspend_dielectric_height.setter + def substrate_suspend_dielectric_height(self, substrate_suspend_dielectric_height_string): + self._dll_interface.set_string(self._dll.setSuspendDielectricHeight, substrate_suspend_dielectric_height_string) + + @property + def substrate_cover_height(self) -> str: + """Substrate's cover height for microstrip, suspend, and inverted substrate types. + The default is ``6.35 mm``. + + Returns + ------- + str + """ + substrate_cover_height_string = self._dll_interface.get_string(self._dll.getCoverHeight) + return substrate_cover_height_string + + @substrate_cover_height.setter + def substrate_cover_height(self, substrate_cover_height_string): + self._dll_interface.set_string(self._dll.setCoverHeight, substrate_cover_height_string) + + @property + def substrate_unbalanced_stripline_enabled(self) -> bool: + """Flag indicating if the substrate unbalanced stripline is enabled. + + Returns + ------- + bool + """ + substrate_unbalanced_stripline_enabled = c_bool() + status = self._dll.getUnbalancedStripLine(byref(substrate_unbalanced_stripline_enabled)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(substrate_unbalanced_stripline_enabled.value) + + @substrate_unbalanced_stripline_enabled.setter + def substrate_unbalanced_stripline_enabled(self, substrate_unbalanced_stripline_enabled: bool): + status = self._dll.setUnbalancedStripLine(substrate_unbalanced_stripline_enabled) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def substrate_cover_height_enabled(self) -> bool: + """Flag indicating if the substrate cover height is enabled. + + Returns + ------- + bool + """ + substrate_cover_height_enabled = c_bool() + status = self._dll.getGroundedCoverAboveLine(byref(substrate_cover_height_enabled)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(substrate_cover_height_enabled.value) + + @substrate_cover_height_enabled.setter + def substrate_cover_height_enabled(self, substrate_cover_height_enabled: bool): + status = self._dll.setGroundedCoverAboveLine(substrate_cover_height_enabled) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + def load_modelithics_models(self): + """Load ``Modelithics`` models from ``AEDT``.""" + status = self._dll.loadModelitichsModels() + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def modelithics_include_interconnect_enabled(self) -> bool: + """Flag indicating if the inclusion of interconnects is enabled for``Modelithics`` export. + + Returns + ------- + bool + """ + modelithics_include_interconnect_enabled = c_bool() + status = self._dll.getModelithicsIncludeInterconnect(byref(modelithics_include_interconnect_enabled)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(modelithics_include_interconnect_enabled.value) + + @modelithics_include_interconnect_enabled.setter + def modelithics_include_interconnect_enabled(self, modelithics_include_interconnect_enabled: bool): + status = self._dll.setModelithicsIncludeInterconnect(modelithics_include_interconnect_enabled) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def modelithics_inductor_list_count(self) -> int: + """Total count of ``Modelithics`` inductor families that have been loaded into the current design. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsInductorsListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_inductor_list(self, row_index) -> str: + """Get the name of the ``Modelithics` inductor family model from the loaded list based + on the specified index.""" + + modelithics_inductor_buffer = create_string_buffer(100) + status = self._dll.getModelithicsInductorsList(row_index, modelithics_inductor_buffer, 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_inductor = modelithics_inductor_buffer.value.decode("utf-8") + return modelithics_inductor + + @property + def modelithics_inductor_selection(self) -> str: + """Selected ``Modelithics`` inductor family from the loaded list. + The Modelithics inductor family selection allows you to choose a specific inductor model from the + Modelithics library. + + Returns + ------- + str + """ + modelithics_inductor_selection_string = self._dll_interface.get_string(self._dll.getModelithicsInductors) + return modelithics_inductor_selection_string + + @modelithics_inductor_selection.setter + def modelithics_inductor_selection(self, modelithics_inductor_selection_string): + self._dll_interface.set_string(self._dll.setModelithicsInductors, modelithics_inductor_selection_string) + + @property + def modelithics_inductor_family_list_count(self) -> int: + """Total count of ``Modelithics`` family inductors added to the inductor family list. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsInductorsFamilyListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_inductor_family_list(self, index) -> str: + """Get the name of ``Modelithics`` inductor family from the inductor family list based on the specified index. + + Parameters + ---------- + index : int + Index of the inductor family list. + + Returns + ------- + str + """ + modelithics_inductor_family_buffer = create_string_buffer(100) + status = self._dll.getModelithicsInductorsFamilyList(index, modelithics_inductor_family_buffer, 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_inductor_family = modelithics_inductor_family_buffer.value.decode("utf-8") + return modelithics_inductor_family + + def modelithics_inductor_add_family(self, modelithics_inductor) -> str: + """Add a specified ``Modelithics`` inductor family to the inductor family list. + + Parameters + ---------- + modelithics_inductor : str + Name of the inductor family. + """ + self._dll_interface.set_string(self._dll.addModelithicsInductorsFamily, modelithics_inductor) + + def modelithics_inductor_remove_family(self, modelithics_inductor) -> str: + """Remove a specified ``Modelithics`` inductor family from the inductor family list. + + Parameters + ---------- + modelithics_inductor : str + Name of the inductor family. + """ + self._dll_interface.set_string(self._dll.removeModelithicsInductorsFamily, modelithics_inductor) + + @property + def modelithics_capacitor_list_count(self) -> int: + """Total count of ``Modelithics`` capacitor families that have been loaded into the current design. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsCapacitorsListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_capacitor_list(self, row_index) -> str: + """Get the name of the ``Modelithics`` capacitor family model from the loaded list based on + the specified index.""" + + modelithics_capacitor_buffer = create_string_buffer(100) + status = self._dll.getModelithicsCapacitorsList(row_index, modelithics_capacitor_buffer, 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_capacitor = modelithics_capacitor_buffer.value.decode("utf-8") + return modelithics_capacitor + + @property + def modelithics_capacitor_selection(self) -> str: + """Selected ``Modelithics`` capacitor family from the loaded list. + The Modelithics capacitor family selection allows you to choose a specific capacitor model from the + Modelithics library. + + Returns + ------- + str + """ + modelithics_capacitor_selection_string = self._dll_interface.get_string(self._dll.getModelithicsCapacitors) + return modelithics_capacitor_selection_string + + @modelithics_capacitor_selection.setter + def modelithics_capacitor_selection(self, modelithics_capacitor_selection_string): + self._dll_interface.set_string(self._dll.setModelithicsCapacitors, modelithics_capacitor_selection_string) + + @property + def modelithics_capacitor_family_list_count(self) -> int: + """Total count of ``Modelithics`` family capacitors added to the capacitor family list. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsCapacitorsFamilyListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_capacitor_family_list(self, index) -> str: + """Get the name of ``Modelithics`` capacitor family from the capacitor family list based on the specified index. + + Parameters + ---------- + index : int + Index of the capacitor family list. + + Returns + ------- + str + """ + modelithics_capacitor_family_buffer = create_string_buffer(100) + status = self._dll.getModelithicsCapacitorsFamilyList(index, modelithics_capacitor_family_buffer, 100) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_capacitor_family = modelithics_capacitor_family_buffer.value.decode("utf-8") + return modelithics_capacitor_family + + def modelithics_capacitor_add_family(self, modelithics_capacitor) -> str: + """Add a specified``Modelithics`` capacitor family to the capacitor family list. + + Parameters + ---------- + modelithics_capacitor : str + Name of the capacitor family. + """ + self._dll_interface.set_string(self._dll.addModelithicsCapacitorsFamily, modelithics_capacitor) + + def modelithics_capacitor_remove_family(self, modelithics_capacitor) -> str: + """Remove a specified ``Modelithics`` capacitor family from the capacitor family list. + Parameters + ---------- + modelithics_capacitor : str + Name of the capacitor family. + """ + self._dll_interface.set_string(self._dll.removeModelithicsCapacitorsFamily, modelithics_capacitor) + + @property + def modelithics_resistor_list_count(self) -> int: + """Total count of ``Modelithics`` resistor families that have been loaded into the current design. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsResistorsListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_resistor_list(self, row_index) -> str: + """Get the name of the ``Modelithics`` resistor family model from the loaded list based on the + specified index.""" + + modelithics_resistor_buffer = create_string_buffer(100) + status = self._dll.getModelithicsResistorsList(row_index, modelithics_resistor_buffer, 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_resistor = modelithics_resistor_buffer.value.decode("utf-8") + return modelithics_resistor + + @property + def modelithics_resistor_selection(self) -> str: + """Selected ``Modelithics`` resistor family from the loaded list. + The Modelithics resistor family selection allows you to choose a specific resistor model from the + Modelithics library. + Returns + ------- + str + """ + modelithics_resistor_selection_string = self._dll_interface.get_string(self._dll.getModelithicsResistors) + return modelithics_resistor_selection_string + + @modelithics_resistor_selection.setter + def modelithics_resistor_selection(self, modelithics_resistor_selection_string): + self._dll_interface.set_string(self._dll.setModelithicsResistors, modelithics_resistor_selection_string) + + @property + def modelithics_resistor_family_list_count(self) -> int: + """Total count of ``Modelithics`` family resistors added to the resistor family list. + + Returns + ------- + int + """ + count = c_int() + status = self._dll.getModelithicsResistorsFamilyListCount(byref(count)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return int(count.value) + + def modelithics_resistor_family_list(self, index) -> str: + """Get the name of ``Modelithics`` resistor family from the resistor family list based on + the specified index. + + Parameters + ---------- + index : int + Index of the resistor family list. + + Returns + ------- + str + """ + modelithics_resistor_family_buffer = create_string_buffer(100) + status = self._dll.getModelithicsResistorsFamilyList(index, modelithics_resistor_family_buffer, 100) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + modelithics_resistor_family = modelithics_resistor_family_buffer.value.decode("utf-8") + return modelithics_resistor_family + + def modelithics_resistor_add_family(self, modelithics_resistor) -> str: + """Add a specified ``Modelithics`` resistor family to the resistor family list. + + Parameters + ---------- + modelithics_resistor : str + Name of the resistor family. + """ + self._dll_interface.set_string(self._dll.addModelithicsResistorsFamily, modelithics_resistor) + + def modelithics_resistor_remove_family(self, modelithics_resistor) -> str: + """Remove a specified ``Modelithics`` resistor family from the resistor family list. + + Parameters + ---------- + modelithics_resistor : str + Name of the resistor family. + """ + self._dll_interface.set_string(self._dll.removeModelithicsResistorsFamily, modelithics_resistor) diff --git a/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py b/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py index 68e613cae65..79852ae2753 100644 --- a/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py +++ b/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py @@ -291,9 +291,9 @@ def remove_row(self, row_index): status = self._dll.removeOptimizationGoalDefinitionRow(row_index) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - def set_design_goals(self): + def restore_design_goals(self): """Configure the optimization goal table according to the recommended goals for the current design.""" - status = self._dll.designGoals() + status = self._dll.setDesignGoals() ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) def save_goals(self, design, file_path) -> str: