From 2f37b0dc0dc72737220f1994d03e66e2bcbe0b02 Mon Sep 17 00:00:00 2001 From: raghajaf Date: Mon, 23 Dec 2024 14:55:44 -0500 Subject: [PATCH 1/6] FEAT: Add distributed filters --- src/ansys/aedt/core/filtersolutions.py | 55 +- .../core/filtersolutions_core/__init__.py | 4 +- .../core/filtersolutions_core/attributes.py | 21 +- .../distributed_topology.py | 895 ++++++++++++++++++ .../filtersolutions_core/dll_interface.py | 8 +- src/ansys/aedt/core/generic/design_types.py | 2 - .../Distributed/center_z0_impedance.ckt | 32 + .../resources/Distributed/combine_stubs.ckt | 26 + .../combline_half_length_frequency.ckt | 30 + ...pled_segments_quarter_length_frequency.ckt | 32 + .../resources/Distributed/default.ckt | 32 + .../Distributed/equal_stub_widths.ckt | 35 + .../Distributed/equal_width_approx.ckt | 27 + .../Distributed/equal_width_conductors.ckt | 37 + .../resources/Distributed/first_fat.ckt | 29 + .../resources/Distributed/first_series.ckt | 31 + .../resources/Distributed/first_shunt.ckt | 32 + .../resources/Distributed/first_thin.ckt | 29 + .../Distributed/generator_resistor.ckt | 32 + .../Distributed/hairpin_extension_length.ckt | 42 + .../Distributed/hairpin_gap_width.ckt | 40 + .../Distributed/left_ground_side.ckt | 19 + .../resources/Distributed/load_resistor.ckt | 32 + .../miniature_hairpin_end_curl_extension.ckt | 42 + .../miniature_hairpin_gap_width.ckt | 40 + .../resources/Distributed/mitered_corners.ckt | 40 + .../resources/Distributed/open_ends.ckt | 27 + .../Distributed/open_stub_ground.ckt | 19 + .../resources/Distributed/pinned.ckt | 27 + .../resources/Distributed/quick_optimize.ckt | 32 + .../resonator_length_extension.ckt | 27 + .../Distributed/resonator_line_width.ckt | 40 + .../Distributed/resonator_rotation_angle.ckt | 33 + .../ring_resonator_end_gap_extension.ckt | 42 + .../Distributed/ring_resonator_gap_width.ckt | 40 + .../resources/Distributed/stub_taps.ckt | 33 + .../resources/Distributed/tap_position.ckt | 40 + .../resources/Distributed/tapped.ckt | 33 + .../resources/Distributed/tuning_type_1.ckt | 40 + .../resources/Distributed/tuning_type_2.ckt | 40 + .../Distributed/use_coupled_lines.ckt | 51 + .../resources/Distributed/use_series_caps.ckt | 43 + .../resources/Distributed/via_ends.ckt | 33 + .../resources/Distributed/wide_band.ckt | 29 + .../resources/{ => Lumped}/bridge_t.ckt | 0 .../resources/{ => Lumped}/bridge_t_high.ckt | 0 .../resources/{ => Lumped}/bridge_t_low.ckt | 0 .../{ => Lumped}/c_lead_inductor.ckt | 0 .../{ => Lumped}/c_node_capacitor.ckt | 0 .../{ => Lumped}/c_node_compensate.ckt | 0 .../resources/{ => Lumped}/capacitor_ls.ckt | 0 .../resources/{ => Lumped}/capacitor_q.ckt | 0 .../resources/{ => Lumped}/capacitor_rp.ckt | 0 .../resources/{ => Lumped}/capacitor_rs.ckt | 0 .../resources/{ => Lumped}/complex.ckt | 0 .../resources/{ => Lumped}/current_source.ckt | 0 .../resources/{ => Lumped}/diplexer1_bp_1.ckt | 0 .../resources/{ => Lumped}/diplexer1_bp_2.ckt | 0 .../{ => Lumped}/diplexer1_bp_bs.ckt | 0 .../{ => Lumped}/diplexer1_hi_lo.ckt | 0 .../{ => Lumped}/diplexer2_bp_bs.ckt | 0 .../{ => Lumped}/diplexer2_triplexer_1.ckt | 0 .../{ => Lumped}/diplexer2_triplexer_2.ckt | 0 .../{ => Lumped}/equal_capacitors.ckt | 0 .../{ => Lumped}/equal_inductors.ckt | 0 .../resources/{ => Lumped}/equal_legs.ckt | 0 .../resources/{ => Lumped}/first_series.ckt | 0 .../resources/{ => Lumped}/first_shunt.ckt | 0 .../{ => Lumped}/generator_resistor.ckt | 0 .../resources/{ => Lumped}/high_low_pass.ckt | 0 .../{ => Lumped}/high_low_pass_min_ind.ckt | 0 .../{ => Lumped}/import_tuned_variables.ckt | 0 .../{ => Lumped}/imported_netlist.ckt | 0 .../resources/{ => Lumped}/inductor_cp.ckt | 0 .../resources/{ => Lumped}/inductor_q.ckt | 0 .../resources/{ => Lumped}/inductor_rp.ckt | 0 .../resources/{ => Lumped}/inductor_rs.ckt | 0 .../{ => Lumped}/l_lead_inductor.ckt | 0 .../{ => Lumped}/l_node_capacitor.ckt | 0 .../{ => Lumped}/l_node_compensate.ckt | 0 .../resources/{ => Lumped}/laod_resistor.ckt | 0 .../resources/{ => Lumped}/library_parts.cfg | 0 .../resources/Lumped/library_parts_test.cfg | 45 + .../{ => Lumped}/match_impedance.ckt | 0 .../resources/{ => Lumped}/min_cap.ckt | 0 .../resources/{ => Lumped}/min_ind.ckt | 0 .../resources/{ => Lumped}/multiband.ckt | 0 .../resources/{ => Lumped}/netlist.ckt | 0 .../{ => Lumped}/node_cap_ground.ckt | 0 .../resources/{ => Lumped}/pspice.ckt | 0 .../{ => Lumped}/r_lead_inductor.ckt | 0 .../{ => Lumped}/r_node_capacitor.ckt | 0 .../resources/{ => Lumped}/set_source_res.ckt | 0 .../resources/{ => Lumped}/source_res.ckt | 0 .../{ => Lumped}/transferfunction.ckt | 0 .../resources/{ => Lumped}/trap_topology.ckt | 0 .../resources/{ => Lumped}/zig_zag.ckt | 0 .../resources/resources.py | 8 +- .../test_distributed_filter/__init__.py | 23 + .../test_distributed_topology.py | 541 +++++++++++ .../test_filter/test_attributes.py | 166 ++-- .../test_filter/test_dll_interface.py | 5 +- .../test_filter/test_graph_setup.py | 14 +- .../test_filter/test_ideal_response.py | 33 +- .../test_filter/test_multiple_bands_table.py | 23 +- .../test_filter/test_transmission_zeros.py | 26 +- .../test_lumped_export/test_export_to_aedt.py | 208 ++-- .../test_optimization_goals_table.py | 23 +- .../test_lumped_nodes_and_leads.py | 58 +- .../test_lumped_parasitics.py | 42 +- ...test_lumped_termination_impedance_table.py | 32 +- .../test_lumped_topology.py | 161 ++-- .../test_raise_error.py | 5 +- 113 files changed, 3379 insertions(+), 307 deletions(-) create mode 100644 src/ansys/aedt/core/filtersolutions_core/distributed_topology.py create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/center_z0_impedance.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/combline_half_length_frequency.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/coupled_segments_quarter_length_frequency.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/default.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/first_fat.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/first_series.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/first_shunt.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/first_thin.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_extension_length.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_gap_width.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_end_curl_extension.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_gap_width.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_line_width.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_rotation_angle.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_end_gap_extension.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_gap_width.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_1.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_2.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/bridge_t.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/bridge_t_high.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/bridge_t_low.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/c_lead_inductor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/c_node_capacitor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/c_node_compensate.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/capacitor_ls.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/capacitor_q.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/capacitor_rp.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/capacitor_rs.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/complex.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/current_source.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer1_bp_1.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer1_bp_2.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer1_bp_bs.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer1_hi_lo.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer2_bp_bs.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer2_triplexer_1.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/diplexer2_triplexer_2.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/equal_capacitors.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/equal_inductors.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/equal_legs.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/first_series.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/first_shunt.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/generator_resistor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/high_low_pass.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/high_low_pass_min_ind.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/import_tuned_variables.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/imported_netlist.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/inductor_cp.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/inductor_q.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/inductor_rp.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/inductor_rs.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/l_lead_inductor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/l_node_capacitor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/l_node_compensate.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/laod_resistor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/library_parts.cfg (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts_test.cfg rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/match_impedance.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/min_cap.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/min_ind.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/multiband.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/netlist.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/node_cap_ground.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/pspice.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/r_lead_inductor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/r_node_capacitor.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/set_source_res.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/source_res.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/transferfunction.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/trap_topology.ckt (100%) rename tests/system/general/test_45_FilterSolutions/resources/{ => Lumped}/zig_zag.ckt (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py create mode 100644 tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py diff --git a/src/ansys/aedt/core/filtersolutions.py b/src/ansys/aedt/core/filtersolutions.py index a0835f7c531..4bba1f20334 100644 --- a/src/ansys/aedt/core/filtersolutions.py +++ b/src/ansys/aedt/core/filtersolutions.py @@ -22,9 +22,9 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core +import ansys.aedt.core.filtersolutions_core from ansys.aedt.core.filtersolutions_core.attributes import Attributes -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +from ansys.aedt.core.filtersolutions_core.distributed_topology import DistributedTopology from ansys.aedt.core.filtersolutions_core.export_to_aedt import ExportToAedt from ansys.aedt.core.filtersolutions_core.graph_setup import GraphSetup from ansys.aedt.core.filtersolutions_core.ideal_response import IdealResponse @@ -40,49 +40,67 @@ class FilterSolutions: - """ - Provides the :doc:`FilterSolutions` application interface. + """Provides the `FilterSolutions` application interface. This class has access to ideal filter attributes and calculated output parameters. Parameters ---------- version : str, optional Version of AEDT in ``xxxx.x`` format. The default is ``None``. - implementation_type : FilterImplementation, optional - Technology used to implement the filter. The default is ``LUMPED``. - The ``FilterImplementation`` enum provides the list of implementations. Examples -------- Create a ``FilterSolutions`` instance with a band-pass elliptic ideal filter. >>> import ansys.aedt.core - >>> from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation + >>> import ansys.aedt.core.filtersolutions + >>> from ansys.aedt.core.filtersolutions_core.dll_interface import DllInterface + >>> desktop_version = DllInterface.desktop_version + + >>> design = ansys.aedt.core.FilterSolutions.LumpDesign(version= desktop_version) - >>> design = ansys.aedt.core.FilterSolutions(version="2025 R1", projectname= "fs1", - >>> implementation_type= FilterImplementation.LUMPED, - >>> ) + See Also + -------- + :doc:`filtersolutions` """ - def __init__(self, version=None, implementation_type=None): + def __init__(self, version=None): self.version = version - self.implementation_type = implementation_type ansys.aedt.core.filtersolutions_core._dll_interface(version) - if implementation_type == FilterImplementation.LUMPED or implementation_type is None: - self._init_lumped_design() - else: - raise RuntimeError("The " + str(implementation_type) + " is not supported in this release.") + +class LumpDesign(FilterSolutions): + def __init__(self, version=None): + super().__init__(version) + self._init_lumped_design() def _init_lumped_design(self): """Initialize the ``FilterSolutions`` object to support a lumped filter design.""" - self.attributes = Attributes() self.ideal_response = IdealResponse() self.graph_setup = GraphSetup() + self.source_impedance_table = LumpedTerminationImpedance(TerminationType.SOURCE) + self.load_impedance_table = LumpedTerminationImpedance(TerminationType.LOAD) + self.multiple_bands_table = MultipleBandsTable() + self.transmission_zeros_ratio = TransmissionZeros(TableFormat.RATIO) + self.transmission_zeros_bandwidth = TransmissionZeros(TableFormat.BANDWIDTH) + self.export_to_aedt = ExportToAedt() + self.optimization_goals_table = OptimizationGoalsTable() self.topology = LumpedTopology() self.parasitics = LumpedParasitics() self.leads_and_nodes = LumpedNodesandLeads() + + +class DistributedDesign(FilterSolutions): + def __init__(self, version=None): + super().__init__(version) + self._init_distributed_design() + + def _init_distributed_design(self): + """Initialize the ``FilterSolutions`` object to support a distributed filter design.""" + self.attributes = Attributes() + self.ideal_response = IdealResponse() + self.graph_setup = GraphSetup() self.source_impedance_table = LumpedTerminationImpedance(TerminationType.SOURCE) self.load_impedance_table = LumpedTerminationImpedance(TerminationType.LOAD) self.multiple_bands_table = MultipleBandsTable() @@ -90,3 +108,4 @@ def _init_lumped_design(self): self.transmission_zeros_bandwidth = TransmissionZeros(TableFormat.BANDWIDTH) self.export_to_aedt = ExportToAedt() self.optimization_goals_table = OptimizationGoalsTable() + self.topology = DistributedTopology() diff --git a/src/ansys/aedt/core/filtersolutions_core/__init__.py b/src/ansys/aedt/core/filtersolutions_core/__init__.py index 6d4c9c6d0cd..8937ab483be 100644 --- a/src/ansys/aedt/core/filtersolutions_core/__init__.py +++ b/src/ansys/aedt/core/filtersolutions_core/__init__.py @@ -37,9 +37,9 @@ def _dll_interface(version=None) -> DllInterface: if _this._internal_dll_interface is None: _this._internal_dll_interface = DllInterface(show_gui=False, version=version) - elif version is not None and version != _this._internal_dll_interface.version: + elif version is not None and version != _this._internal_dll_interface._version: raise Exception( - f"The requested version {version} does not match with the previously defined version {_this._internal_dll_interface.version}." + f"The requested version {version} does not match with the previously defined version {_this._internal_dll_interface._version}." f"{_this._internal_dll_interface.version}." ) diff --git a/src/ansys/aedt/core/filtersolutions_core/attributes.py b/src/ansys/aedt/core/filtersolutions_core/attributes.py index d7073d9ec22..a61dee7d06b 100644 --- a/src/ansys/aedt/core/filtersolutions_core/attributes.py +++ b/src/ansys/aedt/core/filtersolutions_core/attributes.py @@ -110,7 +110,7 @@ class FilterImplementation(Enum): """ LUMPED = 0 - DISTRIB = 1 + DISTRIBUTED = 1 ACTIVE = 2 SWCAP = 3 DIGITAL = 4 @@ -303,9 +303,9 @@ def _define_attributes_dll_functions(self): self._dll.getFilterClass.argtypes = [c_char_p, c_int] self._dll.getFilterClass.restype = int - self._dll.setFilterImplementation.argtype = c_char_p + self._dll.setFilterImplementation.argtype = c_int self._dll.setFilterImplementation.restype = c_int - self._dll.getFilterImplementation.argtypes = [c_char_p, c_int] + self._dll.getFilterImplementation.argtype = POINTER(c_int) self._dll.getFilterImplementation.restype = c_int self._dll.setMultipleBandsEnabled.argtype = c_bool @@ -659,14 +659,17 @@ def filter_implementation(self) -> FilterImplementation: ------- :enum:`FilterImplementation` """ - type_string = self._dll_interface.get_string(self._dll.getFilterImplementation) - return self._dll_interface.string_to_enum(FilterImplementation, type_string) + index = c_int() + filter_implementation = list(FilterImplementation) + status = self._dll.getFilterImplementation(byref(index)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + filter_implementation = filter_implementation[index.value] + return filter_implementation @filter_implementation.setter - def filter_implementation(self, filter_implementation: FilterImplementation): - if filter_implementation: - string_value = self._dll_interface.enum_to_string(filter_implementation) - self._dll_interface.set_string(self._dll.setFilterImplementation, string_value) + def filter_implementation(self, column: FilterImplementation): + status = self._dll.setFilterImplementation(column.value) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) @property def diplexer_type(self) -> DiplexerType: diff --git a/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py new file mode 100644 index 00000000000..5f931948e22 --- /dev/null +++ b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py @@ -0,0 +1,895 @@ +# -*- coding: utf-8 -*- +# +# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# SPDX-License-Identifier: MIT +# +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +from ctypes import POINTER +from ctypes import byref +from ctypes import c_bool +from ctypes import c_char_p +from ctypes import c_int +from enum import Enum + +import ansys.aedt.core + + +class TopologyList(Enum): + """Provides an enum of distributed topologies. + + **Attributes:** + + - LUMPED_TRANSLATION: Represents lumped translation topology. + - INDUCTOR_TRANSLATION: Represents inductor translation topology. + - STEPPED_IMPEDANCE: Represents stepped impedance topology. + - COUPLED_SEGMENTS: Represents coupled segments topology. + - SPACED_STUBS: Represents spaced stubs topology. + - SHUNT_STUB_RESONATORS: Represents shunt stub resonators topology. + - OPEN_STUB_RESONATORS: Represents open stub resonators topology. + - PARALLEL_EDGE_COUPLED: Represents parallel edge coupled topology. + - HAIRPIN: Represents hairpin topology. + - MINIATURE_HAIRPIN: Represents miniature hairpin topology. + - RING_RESONATORS: Represents ring resonators topology. + - INTERDIGITAL: Represents interdigital topology. + - COMBLINE: Represents combline topology. + - DUAL_RESONATORS: Represents dual resonators topology. + - SPACED_DUAl_RESONATORS: Represents spaced dual resonators topology. + - NOTCH_RESONATORs: Represents notch resonators topology. + """ + + LUMPED_TRANSLATION = 0 + INDUCTOR_TRANSLATION = 1 + STEPPED_IMPEDANCE = 2 + COUPLED_SEGMENTS = 3 + SPACED_STUBS = 4 + SHUNT_STUB_RESONATORS = 5 + OPEN_STUB_RESONATORS = 6 + PARALLEL_EDGE_COUPLED = 7 + HAIRPIN = 8 + MINIATURE_HAIRPIN = 9 + RING_RESONATOR = 10 + INTERDIGITAL = 11 + COMBLINE = 12 + DUAL_RESONATORS = 13 + SPACED_DUAl_RESONATORS = 14 + NOTCH_RESONATORS = 15 + + +class TapPosition(Enum): + """Provides an enum of position of tap points of ``Miniature Hairpin`` and ``Ring Resonator`` topologies. + + **Attributes:** + + - AUTO: Represents an automatic tap position. + - BACK: Represents a tap position at the back of the ending resonator. + - SIDES: Represents tap positions at the sides of the ending resonator. + - CORNER: Represents tap positions at the corners of the ending resonator. + """ + + AUTO = 0 + BACK = 1 + SIDES = 2 + CORNER = 3 + + +class DistributedTopology: + """Defines attributes and parameters of distributed filters. + + This class lets you construct all the necessary attributes for the ``DistributedDesign`` class. + """ + + def __init__(self): + self._dll = ansys.aedt.core.filtersolutions_core._dll_interface()._dll + self._dll_interface = ansys.aedt.core.filtersolutions_core._dll_interface() + self._define_topology_dll_functions() + self._set_distributed_implementation() + + def _define_topology_dll_functions(self): + """Define C++ API DLL functions.""" + self._dll.setDistributedTopology.argtype = c_char_p + self._dll.setDistributedTopology.restype = int + self._dll.getDistributedTopology.argtypes = [c_char_p, c_int] + self._dll.getDistributedTopology.restype = int + + self._dll.setDistributedGeneratorResistor.argtype = c_char_p + self._dll.setDistributedGeneratorResistor.restype = c_int + self._dll.getDistributedGeneratorResistor.argtypes = [c_char_p, c_int] + self._dll.getDistributedGeneratorResistor.restype = c_int + + self._dll.setDistributedLoadResistor.argtype = c_char_p + self._dll.setDistributedLoadResistor.restype = c_int + self._dll.getDistributedLoadResistor.argtypes = [c_char_p, c_int] + self._dll.getDistributedLoadResistor.restype = c_int + + self._dll.setDistributedFirstElementShunt.argtype = c_bool + self._dll.setDistributedFirstElementShunt.restype = c_int + self._dll.getDistributedFirstElementShunt.argtype = POINTER(c_bool) + self._dll.getDistributedFirstElementShunt.restype = c_int + + self._dll.setDistributedFirstElementFat.argtype = c_bool + self._dll.setDistributedFirstElementFat.restype = c_int + self._dll.getDistributedFirstElementFat.argtype = POINTER(c_bool) + self._dll.getDistributedFirstElementFat.restype = c_int + + self._dll.setDistributedSeriesCaps.argtype = c_bool + self._dll.setDistributedSeriesCaps.restype = c_int + self._dll.getDistributedSeriesCaps.argtype = POINTER(c_bool) + self._dll.getDistributedSeriesCaps.restype = c_int + + self._dll.setDistributedCombineStubs.argtype = c_bool + self._dll.setDistributedCombineStubs.restype = c_int + self._dll.getDistributedCombineStubs.argtype = POINTER(c_bool) + self._dll.getDistributedCombineStubs.restype = c_int + + self._dll.setDistributedCoupledLines.argtype = c_bool + self._dll.setDistributedCoupledLines.restype = c_int + self._dll.getDistributedCoupledLines.argtype = POINTER(c_bool) + self._dll.getDistributedCoupledLines.restype = c_int + + self._dll.setDistributedQuickOptimize.argtype = c_bool + self._dll.setDistributedQuickOptimize.restype = c_int + self._dll.getDistributedQuickOptimize.argtype = POINTER(c_bool) + self._dll.getDistributedQuickOptimize.restype = c_int + + self._dll.setDistributedEnableExtensions.argtype = c_bool + self._dll.setDistributedEnableExtensions.restype = c_int + self._dll.getDistributedEnableExtensions.argtype = POINTER(c_bool) + self._dll.getDistributedEnableExtensions.restype = c_int + + self._dll.setDistributedEqualWidthApprox.argtype = c_bool + self._dll.setDistributedEqualWidthApprox.restype = c_int + self._dll.getDistributedEqualWidthApprox.argtype = POINTER(c_bool) + self._dll.getDistributedEqualWidthApprox.restype = c_int + + self._dll.setDistributedOpenStubGround.argtype = c_bool + self._dll.setDistributedOpenStubGround.restype = c_int + self._dll.getDistributedOpenStubGround.argtype = POINTER(c_bool) + self._dll.getDistributedOpenStubGround.restype = c_int + + self._dll.setDistributedGroundSideLeft.argtype = c_bool + self._dll.setDistributedGroundSideLeft.restype = c_int + self._dll.getDistributedGroundSideLeft.argtype = POINTER(c_bool) + self._dll.getDistributedGroundSideLeft.restype = c_int + + self._dll.setDistributedEqualStubWidths.argtype = c_bool + self._dll.setDistributedEqualStubWidths.restype = c_int + self._dll.getDistributedEqualStubWidths.argtype = POINTER(c_bool) + self._dll.getDistributedEqualStubWidths.restype = c_int + + self._dll.setDistributedCenterImpedance.argtype = c_char_p + self._dll.setDistributedCenterImpedance.restype = c_int + self._dll.getDistributedCenterImpedance.argtypes = [c_char_p, c_int] + self._dll.getDistributedCenterImpedance.restype = c_int + + self._dll.setDistributedTapped.argtype = c_bool + self._dll.setDistributedTapped.restype = c_int + self._dll.getDistributedTapped.argtype = POINTER(c_bool) + self._dll.getDistributedTapped.restype = c_int + + self._dll.setDistributedPinned.argtype = c_bool + self._dll.setDistributedPinned.restype = c_int + self._dll.getDistributedPinned.argtype = POINTER(c_bool) + self._dll.getDistributedPinned.restype = c_int + + self._dll.setDistributedStubTaps.argtype = c_bool + self._dll.setDistributedStubTaps.restype = c_int + self._dll.getDistributedStubTaps.argtype = POINTER(c_bool) + self._dll.getDistributedStubTaps.restype = c_int + + self._dll.setDistributedViaEnds.argtype = c_bool + self._dll.setDistributedViaEnds.restype = c_int + self._dll.getDistributedViaEnds.argtype = POINTER(c_bool) + self._dll.getDistributedViaEnds.restype = c_int + + self._dll.setDistributedLineWidth.argtype = c_char_p + self._dll.setDistributedLineWidth.restype = c_int + self._dll.getDistributedLineWidth.argtypes = [c_char_p, c_int] + self._dll.getDistributedLineWidth.restype = c_int + + self._dll.setDistributedResonatorRotationAngle.argtype = c_char_p + self._dll.setDistributedResonatorRotationAngle.restype = c_int + self._dll.getDistributedResonatorRotationAngle.argtypes = [c_char_p, c_int] + self._dll.getDistributedResonatorRotationAngle.restype = c_int + + self._dll.setDistributedMiteredCorners.argtype = c_bool + self._dll.setDistributedMiteredCorners.restype = c_int + self._dll.getDistributedMiteredCorners.argtype = POINTER(c_bool) + self._dll.getDistributedMiteredCorners.restype = c_int + + self._dll.setDistributedHGapWidth.argtype = c_char_p + self._dll.setDistributedHGapWidth.restype = c_int + self._dll.getDistributedHGapWidth.argtypes = [c_char_p, c_int] + self._dll.getDistributedHGapWidth.restype = c_int + + self._dll.setDistributedRHGapWidth.argtype = c_char_p + self._dll.setDistributedRHGapWidth.restype = c_int + self._dll.getDistributedRHGapWidth.argtypes = [c_char_p, c_int] + self._dll.getDistributedRHGapWidth.restype = c_int + + self._dll.setDistributedTuningExtensionValue.argtype = c_char_p + self._dll.setDistributedTuningExtensionValue.restype = c_int + self._dll.getDistributedTuningExtensionValue.argtypes = [c_char_p, c_int] + self._dll.getDistributedTuningExtensionValue.restype = c_int + + self._dll.setDistributedTuningType1.argtype = c_bool + self._dll.setDistributedTuningType1.restype = c_int + self._dll.getDistributedTuningType1.argtype = POINTER(c_bool) + self._dll.getDistributedTuningType1.restype = c_int + + self._dll.setDistributedTapPosition.argtype = c_char_p + self._dll.setDistributedTapPosition.restype = c_int + self._dll.getDistributedTapPosition.argtypes = [c_char_p, c_int] + self._dll.getDistributedTapPosition.restype = c_int + + self._dll.setDistributedWideBand.argtype = c_bool + self._dll.setDistributedWideBand.restype = c_int + self._dll.getDistributedWideBand.argtype = POINTER(c_bool) + self._dll.getDistributedWideBand.restype = c_int + + self._dll.setDistributedOpenEnds.argtype = c_bool + self._dll.setDistributedOpenEnds.restype = c_int + self._dll.getDistributedOpenEnds.argtype = POINTER(c_bool) + self._dll.getDistributedOpenEnds.restype = c_int + + self._dll.setDistributedHalfLengthFrequency.argtype = c_char_p + self._dll.setDistributedHalfLengthFrequency.restype = c_int + self._dll.getDistributedHalfLengthFrequency.argtypes = [c_char_p, c_int] + self._dll.getDistributedHalfLengthFrequency.restype = c_int + + self._dll.setDistributedQuarterLengthFrequency.argtype = c_char_p + self._dll.setDistributedQuarterLengthFrequency.restype = c_int + self._dll.getDistributedQuarterLengthFrequency.argtypes = [c_char_p, c_int] + self._dll.getDistributedQuarterLengthFrequency.restype = c_int + + self._dll.getDistributedCircuitResponseSize.argtype = POINTER(c_int) + self._dll.getDistributedCircuitResponseSize.restype = c_int + self._dll.getDistributedCircuitResponse.argtypes = [c_char_p, c_int] + self._dll.getDistributedCircuitResponse.restype = c_int + + def _set_distributed_implementation(self): + """Set ``FilterSolutions`` attributes to distributed design.""" + filter_implementation_status = self._dll.setFilterImplementation(1) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(filter_implementation_status) + first_shunt_status = self._dll.setDistributedFirstElementShunt(True) + self._dll_interface.raise_error(first_shunt_status) + + @property + def topology_list(self) -> TopologyList: + """Topology type of the distributed filter. The default is ``LUMPED_TRANSLATION``. + The ``TopologyList`` enum provides a list of all classes. + + Returns + ------- + :enum:`TopologyList` + """ + type_string = self._dll_interface.get_string(self._dll.getDistributedTopology) + return self._dll_interface.string_to_enum(TopologyList, type_string) + + @topology_list.setter + def topology_list(self, topology_list: TopologyList): + if topology_list: + string_value = self._dll_interface.enum_to_string(topology_list) + self._dll_interface.set_string(self._dll.setDistributedTopology, string_value) + + @property + def generator_resistor(self) -> str: + """Generator resistor. The default is ``50``. + + Returns + ------- + str + """ + generator_resistor_string = self._dll_interface.get_string(self._dll.getDistributedGeneratorResistor) + return generator_resistor_string + + @generator_resistor.setter + def generator_resistor(self, generator_resistor_string): + self._dll_interface.set_string(self._dll.setDistributedGeneratorResistor, generator_resistor_string) + + @property + def load_resistor(self) -> str: + """Load resistor. The default is ``50``. + + Returns + ------- + str + """ + load_resistor_string = self._dll_interface.get_string(self._dll.getDistributedLoadResistor) + return load_resistor_string + + @load_resistor.setter + def load_resistor(self, load_resistor_string): + self._dll_interface.set_string(self._dll.setDistributedLoadResistor, load_resistor_string) + + @property + def first_shunt(self) -> bool: + """Flag indicating if shunt elements are first in the synthesized circuit. + If ``False``, series elements are first. + + Returns + ------- + bool + """ + first_shunt = c_bool() + status = self._dll.getDistributedFirstElementShunt(byref(first_shunt)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(first_shunt.value) + + @first_shunt.setter + def first_shunt(self, first_shunt: bool): + status = self._dll.setDistributedFirstElementShunt(first_shunt) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def first_fat(self) -> bool: + """Flag indicating if fat segments are first in the synthesized circuit. + If ``False``, thin segments are first. + + Returns + ------- + bool + """ + first_fat = c_bool() + status = self._dll.getDistributedFirstElementFat(byref(first_fat)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(first_fat.value) + + @first_fat.setter + def first_fat(self, first_fat: bool): + status = self._dll.setDistributedFirstElementFat(first_fat) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def use_series_caps(self) -> bool: + """Flag indicating if lumped capacitors are implemented in series segments. + + Returns + ------- + bool + """ + use_series_caps = c_bool() + status = self._dll.getDistributedSeriesCaps(byref(use_series_caps)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(use_series_caps.value) + + @use_series_caps.setter + def use_series_caps(self, use_series_caps: bool): + status = self._dll.setDistributedSeriesCaps(use_series_caps) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def combine_stubs(self) -> bool: + """Flag indicating if resonators are created with only one stub. + + Returns + ------- + bool + """ + combine_stubs = c_bool() + status = self._dll.getDistributedCombineStubs(byref(combine_stubs)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(combine_stubs.value) + + @combine_stubs.setter + def combine_stubs(self, combine_stubs: bool): + status = self._dll.setDistributedCombineStubs(combine_stubs) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def use_coupled_lines(self) -> bool: + """Flag indicating if coupled segments are used between stubs. + + Returns + ------- + bool + """ + use_coupled_lines = c_bool() + status = self._dll.getDistributedCoupledLines(byref(use_coupled_lines)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(use_coupled_lines.value) + + @use_coupled_lines.setter + def use_coupled_lines(self, use_coupled_lines: bool): + status = self._dll.setDistributedCoupledLines(use_coupled_lines) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def equal_width_approx(self) -> bool: + """Flag indicating if stubs with equal width are implemented. + + Returns + ------- + bool + """ + equal_width_approx = c_bool() + status = self._dll.getDistributedEqualWidthApprox(byref(equal_width_approx)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(equal_width_approx.value) + + @equal_width_approx.setter + def equal_width_approx(self, equal_width_approx: bool): + status = self._dll.setDistributedEqualWidthApprox(equal_width_approx) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def open_stub_ground(self) -> bool: + """Flag indicating if quarter length open stubs are implemented to simulate ground. + + Returns + ------- + bool + """ + open_stub_ground = c_bool() + status = self._dll.getDistributedOpenStubGround(byref(open_stub_ground)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(open_stub_ground.value) + + @open_stub_ground.setter + def open_stub_ground(self, open_stub_ground: bool): + status = self._dll.setDistributedOpenStubGround(open_stub_ground) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def left_ground_side(self) -> bool: + """Flag indicating if grounded pins are placed on left side. + If ``False``, right side is selected. + + Returns + ------- + bool + """ + left_ground_side = c_bool() + status = self._dll.getDistributedGroundSideLeft(byref(left_ground_side)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(left_ground_side.value) + + @left_ground_side.setter + def left_ground_side(self, left_ground_side: bool): + status = self._dll.setDistributedGroundSideLeft(left_ground_side) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def equal_stub_widths(self) -> bool: + """Flag indicating if stubs with equal width are implemented. + + Returns + ------- + bool + """ + equal_stub_widths = c_bool() + status = self._dll.getDistributedEqualStubWidths(byref(equal_stub_widths)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(equal_stub_widths.value) + + @equal_stub_widths.setter + def equal_stub_widths(self, equal_stub_widths: bool): + status = self._dll.setDistributedEqualStubWidths(equal_stub_widths) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def center_z0_impedance(self) -> str: + """Resonator internal impednace. The default is ``75``. + + Returns + ------- + str + """ + center_z0_impedance_string = self._dll_interface.get_string(self._dll.getDistributedCenterImpedance) + return center_z0_impedance_string + + @center_z0_impedance.setter + def center_z0_impedance(self, center_z0_impedance_string): + self._dll_interface.set_string(self._dll.setDistributedCenterImpedance, center_z0_impedance_string) + + @property + def equal_width_conductors(self) -> bool: + """Flag indicating if all resonators are set to the same width. + + Returns + ------- + bool + """ + equal_width_conductors = c_bool() + status = self._dll.getDistributedEqualWidthApprox(byref(equal_width_conductors)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(equal_width_conductors.value) + + @equal_width_conductors.setter + def equal_width_conductors(self, equal_width_conductors: bool): + status = self._dll.setDistributedEqualWidthApprox(equal_width_conductors) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def tapped(self) -> bool: + """Flag indicating if the outer couplers are removed and the remaining outer couplers are tapped. + + Returns + ------- + bool + """ + tapped = c_bool() + status = self._dll.getDistributedTapped(byref(tapped)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(tapped.value) + + @tapped.setter + def tapped(self, tapped: bool): + status = self._dll.setDistributedTapped(tapped) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def pinned(self) -> bool: + """Flag indicating if the outer couplers are replaced with hairpin resonators. + + Returns + ------- + bool + """ + pinned = c_bool() + status = self._dll.getDistributedPinned(byref(pinned)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(pinned.value) + + @pinned.setter + def pinned(self, pinned: bool): + status = self._dll.setDistributedPinned(pinned) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def stub_taps(self) -> bool: + """Flag indicating if vertical stubs are implemented at the tap points. + + Returns + ------- + bool + """ + stub_taps = c_bool() + status = self._dll.getDistributedStubTaps(byref(stub_taps)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(stub_taps.value) + + @stub_taps.setter + def stub_taps(self, stub_taps: bool): + status = self._dll.setDistributedStubTaps(stub_taps) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def via_ends(self) -> bool: + """Flag indicating if resonators are terminated with vias instead of open ends. + + Returns + ------- + bool + """ + via_ends = c_bool() + status = self._dll.getDistributedViaEnds(byref(via_ends)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(via_ends.value) + + @via_ends.setter + def via_ends(self, via_ends: bool): + status = self._dll.setDistributedViaEnds(via_ends) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def resonator_line_width(self) -> str: + """Line width to set in ``Haripin`` and ``Ring Resonator`` filters. The default is ``1.27 mm``. + + Returns + ------- + str + """ + resonator_line_width_string = self._dll_interface.get_string(self._dll.getDistributedLineWidth) + return resonator_line_width_string + + @resonator_line_width.setter + def resonator_line_width(self, resonator_line_width_string): + self._dll_interface.set_string(self._dll.setDistributedLineWidth, resonator_line_width_string) + + @property + def resonator_rotation_angle(self) -> str: + """Net filter rotation angle in degrees. The default is ``0``. + + Returns + ------- + str + """ + resonator_rotation_angle_string = self._dll_interface.get_string(self._dll.getDistributedResonatorRotationAngle) + return resonator_rotation_angle_string + + @resonator_rotation_angle.setter + def resonator_rotation_angle(self, resonator_rotation_angle_string): + self._dll_interface.set_string(self._dll.setDistributedResonatorRotationAngle, resonator_rotation_angle_string) + + @property + def mitered_corners(self) -> bool: + """Flag indicating if mitered corners are implemented. + + Returns + ------- + bool + """ + mitered_corners = c_bool() + status = self._dll.getDistributedMiteredCorners(byref(mitered_corners)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(mitered_corners.value) + + @mitered_corners.setter + def mitered_corners(self, mitered_corners: bool): + status = self._dll.setDistributedMiteredCorners(mitered_corners) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def hairpin_gap_width(self) -> str: + """Gap width to set in ``Haripin`` filters. The default is ``2.54 mm``. + + Returns + ------- + str + """ + hairpin_gap_width_string = self._dll_interface.get_string(self._dll.getDistributedHGapWidth) + return hairpin_gap_width_string + + @hairpin_gap_width.setter + def hairpin_gap_width(self, hairpin_gap_width_string): + self._dll_interface.set_string(self._dll.setDistributedHGapWidth, hairpin_gap_width_string) + + @property + def miniature_hairpin_gap_width(self) -> str: + """Gap width to set in ``Miniature Haripin`` filters. The default is ``635 um``. + + Returns + ------- + str + """ + miniature_hairpin_gap_width_string = self._dll_interface.get_string(self._dll.getDistributedRHGapWidth) + return miniature_hairpin_gap_width_string + + @miniature_hairpin_gap_width.setter + def miniature_hairpin_gap_width(self, miniature_hairpin_gap_width_string): + self._dll_interface.set_string(self._dll.setDistributedRHGapWidth, miniature_hairpin_gap_width_string) + + @property + def ring_resonator_gap_width(self) -> str: + """Gap width to set in ``Ring Resonator`` filters. The default is ``635 um``. + + Returns + ------- + str + """ + ring_resonator_gap_width_string = self._dll_interface.get_string(self._dll.getDistributedRHGapWidth) + return ring_resonator_gap_width_string + + @ring_resonator_gap_width.setter + def ring_resonator_gap_width(self, ring_resonator_gap_width_string): + self._dll_interface.set_string(self._dll.setDistributedRHGapWidth, ring_resonator_gap_width_string) + + @property + def hairpin_extension_length(self) -> str: + """Extension length to set in ``Haripin`` filters for tuning purpose. The default is ``0 mm``. + + Returns + ------- + str + """ + hairpin_extension_length_string = self._dll_interface.get_string(self._dll.getDistributedTuningExtensionValue) + return hairpin_extension_length_string + + @hairpin_extension_length.setter + def hairpin_extension_length(self, hairpin_extension_length_string): + self._dll_interface.set_string(self._dll.setDistributedTuningExtensionValue, hairpin_extension_length_string) + + @property + def miniature_hairpin_end_curl_extension(self) -> str: + """End curl extension length to set in ``Miniature Haripin`` filters for tuning purpose. + The default is ``0 mm``. + + Returns + ------- + str + """ + miniature_hairpin_end_curl_extension_string = self._dll_interface.get_string( + self._dll.getDistributedTuningExtensionValue + ) + return miniature_hairpin_end_curl_extension_string + + @miniature_hairpin_end_curl_extension.setter + def miniature_hairpin_end_curl_extension(self, miniature_hairpin_end_curl_extension_string): + self._dll_interface.set_string( + self._dll.setDistributedTuningExtensionValue, miniature_hairpin_end_curl_extension_string + ) + + @property + def ring_resonator_end_gap_extension(self) -> str: + """End gap extension length to set in ``Ring Resonator`` filters for tuning purpose. The default is ``0 mm``. + + Returns + ------- + str + """ + ring_resonator_end_gap_extension_string = self._dll_interface.get_string( + self._dll.getDistributedTuningExtensionValue + ) + return ring_resonator_end_gap_extension_string + + @ring_resonator_end_gap_extension.setter + def ring_resonator_end_gap_extension(self, ring_resonator_end_gap_extension_string): + self._dll_interface.set_string( + self._dll.setDistributedTuningExtensionValue, ring_resonator_end_gap_extension_string + ) + + @property + def tuning_type_1(self) -> bool: + """Flag indicating if both legs of the outer hairpins are set for tuning in ``Haripin`` filters. + If ``False``, only the outer legs of the outer hairpins are set. + + Returns + ------- + bool + """ + tuning_type_1 = c_bool() + status = self._dll.getDistributedTuningType1(byref(tuning_type_1)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(tuning_type_1.value) + + @tuning_type_1.setter + def tuning_type_1(self, tuning_type_1: bool): + status = self._dll.setDistributedTuningType1(tuning_type_1) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def tap_position(self) -> TapPosition: + """Tap position of the tap points in ``Miniature Hairpin`` and ``Ring Resonator`` filters. + The default is ``AUTO``. + The ``TapPosition`` enum provides a list of all types. + + Returns + ------- + :enum:`TapPosition` + """ + type_string = self._dll_interface.get_string(self._dll.getDistributedTapPosition) + return self._dll_interface.string_to_enum(TapPosition, type_string) + + @tap_position.setter + def tap_position(self, tap_position: TapPosition): + if tap_position: + string_value = self._dll_interface.enum_to_string(tap_position) + self._dll_interface.set_string(self._dll.setDistributedTapPosition, string_value) + + @property + def wide_band(self) -> bool: + """Flag indicating if ``Interdigital`` filters are optimized for wideband applications. + + Returns + ------- + bool + """ + wide_band = c_bool() + status = self._dll.getDistributedWideBand(byref(wide_band)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(wide_band.value) + + @wide_band.setter + def wide_band(self, wide_band: bool): + status = self._dll.setDistributedWideBand(wide_band) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def open_ends(self) -> bool: + """Flag indicating if resonators are terminated with open ends instead of vias. + + Returns + ------- + bool + """ + open_ends = c_bool() + status = self._dll.getDistributedOpenEnds(byref(open_ends)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(open_ends.value) + + @open_ends.setter + def open_ends(self, open_ends: bool): + status = self._dll.setDistributedOpenEnds(open_ends) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def combline_half_length_frequency(self) -> str: + """Half length frequency in ``Combline`` filters where open remains open. The default is ``4G``. + + Returns + ------- + str + """ + combline_half_length_frequency_string = self._dll_interface.get_string( + self._dll.getDistributedHalfLengthFrequency + ) + return combline_half_length_frequency_string + + @combline_half_length_frequency.setter + def combline_half_length_frequency(self, combline_half_length_frequency_string): + self._dll_interface.set_string( + self._dll.setDistributedHalfLengthFrequency, combline_half_length_frequency_string + ) + + @property + def coupled_segments_quarter_length_frequency(self) -> str: + """Quarter length frequency in ``Coupled Segments`` filters where open becomes ground. The default is ``4G``. + + Returns + ------- + str + """ + coupled_segments_quarter_length_frequency_string = self._dll_interface.get_string( + self._dll.getDistributedQuarterLengthFrequency + ) + return coupled_segments_quarter_length_frequency_string + + @coupled_segments_quarter_length_frequency.setter + def coupled_segments_quarter_length_frequency(self, coupled_segments_quarter_length_frequency_string): + self._dll_interface.set_string( + self._dll.setDistributedQuarterLengthFrequency, coupled_segments_quarter_length_frequency_string + ) + + def circuit_response(self): + """Execute real filter synthesis""" + size = c_int() + status = self._dll.getDistributedCircuitResponseSize(byref(size)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + circuit_response_string = self._dll_interface.get_string( + self._dll.getDistributedCircuitResponse, max_size=size.value + ) + return circuit_response_string + + @property + def quick_optimize(self) -> bool: + """Flag indicating if the quick optimization of the synthesized circuit is enabled. + + Returns + ------- + bool + """ + quick_optimize = c_bool() + status = self._dll.getDistributedQuickOptimize(byref(quick_optimize)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(quick_optimize.value) + + @quick_optimize.setter + def quick_optimize(self, quick_optimize: bool): + status = self._dll.setDistributedQuickOptimize(quick_optimize) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + + @property + def resonator_length_extension(self) -> bool: + """Flag indicating if the resonator length extension for optimization of the synthesized circuit is enabled. + + Returns + ------- + bool + """ + resonator_length_extension = c_bool() + status = self._dll.getDistributedEnableExtensions(byref(resonator_length_extension)) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) + return bool(resonator_length_extension.value) + + @resonator_length_extension.setter + def resonator_length_extension(self, resonator_length_extension: bool): + status = self._dll.setDistributedEnableExtensions(resonator_length_extension) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) diff --git a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py index f2528221887..733e83a485f 100644 --- a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py +++ b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py @@ -36,6 +36,7 @@ class DllInterface: """Interfaces with the FilterSolutions C++ API DLL.""" def __init__(self, show_gui=False, version=None): + self._version = version self._init_dll_path(version) self._init_dll(show_gui) @@ -63,7 +64,7 @@ def _init_dll_path(self, version): print("DLL Path:", self.dll_path) if not os.path.isfile(self.dll_path): raise RuntimeError(f"The 'FilterSolutions' API DLL was not found at {self.dll_path}.") # pragma: no cover - self.version = version + self._version = version def _init_dll(self, show_gui): """Load DLL and initialize application parameters to default values.""" @@ -188,3 +189,8 @@ def raise_error(self, error_status): if error_status != 0: error_message = self.get_string(self._dll.getErrorMessage, 4096) raise RuntimeError(error_message) + + @property + def desktop_version(self): + """Return the version of the AEDT.""" + return self._version diff --git a/src/ansys/aedt/core/generic/design_types.py b/src/ansys/aedt/core/generic/design_types.py index 98519369059..d675ad1f158 100644 --- a/src/ansys/aedt/core/generic/design_types.py +++ b/src/ansys/aedt/core/generic/design_types.py @@ -52,7 +52,6 @@ def FilterSolutions( version=None, - implementation_type=None, ): """Initialize a ``FilterSolutions` instance. @@ -83,7 +82,6 @@ def FilterSolutions( return app( version=version, - implementation_type=implementation_type, ) diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/center_z0_impedance.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/center_z0_impedance.ckt new file mode 100644 index 00000000000..88a58a8c1d5 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/center_z0_impedance.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=5E-05 Len=0.03093 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 0 Wid=0.0006568 Len=0.02975 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=5E-05 Len=0.03093 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 0 Wid=0.001006 Len=0.02935 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=5E-05 Len=0.03093 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 5 0 Wid=0.0006568 Len=0.02975 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=5E-05 Len=0.03093 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 6 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 6 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg4 3 0 5E+09 +Rseg5 4 0 5E+09 +Rseg6 5 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1.5E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.05 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt new file mode 100644 index 00000000000..fb9fee4c419 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt @@ -0,0 +1,26 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=5E-05 Len=0.06187 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=5E-05 Len=0.06187 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg2 3 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1.5E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.09 0.07 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/combline_half_length_frequency.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combline_half_length_frequency.ckt new file mode 100644 index 00000000000..368efad5d6d --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combline_half_length_frequency.ckt @@ -0,0 +1,30 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.00159 Len=0.005702 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.00159 Len=0.007848 Er=9.8 Thick=2.54E-06 Height=0.00127 +C2 3 0 4.004E-12 +MT3 0 0 3 4 Gap=0.001385 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 4 Wid=0.00159 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +C4 4 0 3.853E-12 +MT5 0 0 4 5 Gap=0.002114 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 0 5 Wid=0.00159 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +C6 5 0 3.853E-12 +MT7 0 0 5 6 Gap=0.002114 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 6 Wid=0.00159 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +C8 6 0 3.853E-12 +MT9 0 0 6 7 Gap=0.001385 Len=0.01355 Er=9.8 Thick=2.54E-06 Height=0.00127 +C9 7 0 4.004E-12 +MT10 0 8 Wid=0.00159 Len=0.005702 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 8 7 Wid=0.00159 Len=0.007848 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 8 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -80 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) 0 1.6E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.05 0.07 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/coupled_segments_quarter_length_frequency.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/coupled_segments_quarter_length_frequency.ckt new file mode 100644 index 00000000000..e5c9f9942d6 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/coupled_segments_quarter_length_frequency.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.0003175 Len=0.01415 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.001048 Len=0.0005239 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.001048 Gap=5E-05 Len=0.01401 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 6 7 Wid=0.001048 Len=0.0005239 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 7 0 Wid=0.0003175 Len=0.004934 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 7 8 Wid=0.001048 Len=0.0005239 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 9 8 11 10 Wid=0.001048 Gap=5E-05 Len=0.01401 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 11 12 Wid=0.001048 Len=0.0005239 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 12 0 Wid=0.0003175 Len=0.01415 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 12 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg6 3 0 5E+09 +Rseg7 7 0 5E+09 +Rseg8 8 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -90 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -4E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.2 0.15 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/default.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/default.ckt new file mode 100644 index 00000000000..982129e7efa --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/default.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 5E+09 +Rstb3 6 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 9 0 5E+09 +Rstb8 10 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -70 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt new file mode 100644 index 00000000000..970b97671c7 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt @@ -0,0 +1,35 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.000921 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 3 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0004979 Len=0.02996 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 4 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 4 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=0.0004979 Len=0.02996 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S6 5 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 5 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=0.000921 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S8 6 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 6 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg4 3 0 5E+09 +Rseg5 4 0 5E+09 +Rseg6 5 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1.5E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt new file mode 100644 index 00000000000..79d41b9018b --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001665 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001665 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001665 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001671 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001671 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001665 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001665 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001665 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -80 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-09 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt new file mode 100644 index 00000000000..c9d5c6a3f41 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt @@ -0,0 +1,37 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.0009521 Len=0.00873 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S1 3 19 Wid=0.0001914 Len=0.01932 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0009521 Len=0.00873 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 5 4 7 6 Wid=0.0009521 Gap=0.0004417 Len=0.02915 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 7 10 9 Wid=0.001061 Gap=0.001016 Len=0.02886 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 11 10 13 12 Wid=0.001061 Gap=0.001016 Len=0.02886 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup5 14 13 16 15 Wid=0.0009521 Gap=0.0004417 Len=0.02915 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg6 16 17 Wid=0.0009521 Len=0.00873 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 17 26 Wid=0.0001914 Len=0.01932 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg7 17 18 Wid=0.0009521 Len=0.00873 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 18 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg8 3 0 5E+09 +Rstb9 19 0 5E+09 +Rstb10 20 0 5E+09 +Rseg11 4 0 5E+09 +Rseg12 17 0 5E+09 +Rstb13 26 0 5E+09 +Rstb14 27 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -4E-08 3E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.06 0.06 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_fat.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_fat.ckt new file mode 100644 index 00000000000..e81a589541c --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_fat.ckt @@ -0,0 +1,29 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.00508 Len=0.003575 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.01961 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=0.00508 Len=0.01356 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=0.0003175 Len=0.01961 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg4 6 7 Wid=0.00508 Len=0.003575 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 7 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg5 3 0 5E+09 +Rseg6 4 0 5E+09 +Rseg7 5 0 5E+09 +Rseg8 6 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -30 -5 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) 0 2.5E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_series.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_series.ckt new file mode 100644 index 00000000000..eb458574a8a --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_series.ckt @@ -0,0 +1,31 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.0003175 Len=0.006689 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S1 3 6 Wid=0.00508 Len=0.009004 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.028 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 4 8 Wid=0.00508 Len=0.009004 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=0.0003175 Len=0.006689 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 5 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg3 3 0 5E+09 +Rstb4 6 0 5E+09 +Rstb5 7 0 5E+09 +Rseg6 4 0 5E+09 +Rstb7 8 0 5E+09 +Rstb8 9 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -7E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_shunt.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_shunt.ckt new file mode 100644 index 00000000000..982129e7efa --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_shunt.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 5E+09 +Rstb3 6 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 9 0 5E+09 +Rstb8 10 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -70 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_thin.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_thin.ckt new file mode 100644 index 00000000000..c9941ed9d20 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/first_thin.ckt @@ -0,0 +1,29 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.0003175 Len=0.005799 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.00508 Len=0.0103 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=0.0003175 Len=0.02428 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=0.00508 Len=0.0103 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg4 6 7 Wid=0.0003175 Len=0.005799 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 7 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg5 3 0 5E+09 +Rseg6 4 0 5E+09 +Rseg7 5 0 5E+09 +Rseg8 6 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -30 -5 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) 0 2.5E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt new file mode 100644 index 00000000000..c4c17bfc86f --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 30 +MT1S1 2 5 Wid=0.00508 Len=0.00363 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.007154 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.0138 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.01414 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.01364 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 5E+09 +Rstb3 6 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 9 0 5E+09 +Rstb8 10 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -120 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -6E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.7 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_extension_length.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_extension_length.ckt new file mode 100644 index 00000000000..1c979e492e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_extension_length.ckt @@ -0,0 +1,42 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 4 5 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 3 6 4 7 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 6 7 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 3 6 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 6 8 7 9 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 8 9 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 8 10 9 11 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 10 11 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 10 12 11 13 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 12 13 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 12 14 13 15 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 14 15 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 12 14 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 14 16 15 17 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 16 17 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 16 18 17 19 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 18 19 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 18 20 19 21 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 20 21 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 20 22 21 23 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 20 22 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 22 24 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT27 24 23 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT28 23 25 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 24 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.08 0.06 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_gap_width.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_gap_width.ckt new file mode 100644 index 00000000000..070dc594ab3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/hairpin_gap_width.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.001 Len=0.01149 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.001 Len=0.01569 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.004 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.001 Len=0.004 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=0.0003201 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.004 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.001 Len=0.004 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0009436 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.004 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.001 Len=0.004 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0009436 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.004 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.001 Len=0.004 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=0.0003201 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.001 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.004 Len=0.02718 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.001 Len=0.004 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.001 Len=0.01149 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.001 Len=0.01569 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.07 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt new file mode 100644 index 00000000000..5e88de69fa7 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt @@ -0,0 +1,19 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MXTcoup0 2 3 4 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 5 6 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 6 7 8 0 Wid=0.0005798 Gap=0.0001159 Len=0.02952 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 9 10 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 10 11 12 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 12 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) 0 0.7 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt new file mode 100644 index 00000000000..78c1ab4d3d1 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 5 Wid=0.00508 Len=0.01364 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.01414 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.0138 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.007154 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.00363 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 30 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 3E+09 +Rstb3 6 0 3E+09 +Rseg4 3 0 3E+09 +Rstb5 7 0 3E+09 +Rstb6 8 0 3E+09 +Rstb7 9 0 3E+09 +Rstb8 10 0 3E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -120 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -6E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.5 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_end_curl_extension.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_end_curl_extension.ckt new file mode 100644 index 00000000000..45054c3578b --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_end_curl_extension.ckt @@ -0,0 +1,42 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 4 5 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 3 6 4 7 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 6 7 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 3 6 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 6 8 7 9 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 8 9 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 8 10 9 11 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 10 11 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 10 12 11 13 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 12 13 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 12 14 13 15 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 14 15 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 12 14 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 14 16 15 17 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 16 17 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 16 18 17 19 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 18 19 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 18 20 19 21 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 20 21 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 20 22 21 23 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 20 22 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 22 24 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT27 24 23 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT28 23 25 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 24 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -100 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) 0 1.6E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_gap_width.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_gap_width.ckt new file mode 100644 index 00000000000..7aa9b02e484 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/miniature_hairpin_gap_width.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.008571 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.001294 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.009865 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=7.937E-05 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.009865 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.000354 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.009865 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.000354 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.009865 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=7.937E-05 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.009865 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.009865 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.008571 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.001294 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -100 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) 0 1.8E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt new file mode 100644 index 00000000000..907a754e0f4 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=0.0002693 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0008822 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0008822 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=0.0002693 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-08 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.05 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt new file mode 100644 index 00000000000..ee0c80bf8e4 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.002046 Len=0.02902 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.002046 Len=0.02446 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.002046 Len=0.003259 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.0004828 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.002046 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.00105 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.002046 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.00105 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.002046 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.0004828 Len=0.05348 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.002046 Len=0.02902 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.002046 Len=0.02446 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.002046 Len=0.003259 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -80 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -3E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.06 0.06 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt new file mode 100644 index 00000000000..532ed259168 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt @@ -0,0 +1,19 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MXTcoup0 2 0 4 3 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 0 6 5 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 6 0 8 7 Wid=0.0005798 Gap=0.0001159 Len=0.02952 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 0 10 9 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 10 0 12 11 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 12 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) 0 0.7 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt new file mode 100644 index 00000000000..5c1c997b003 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.002204 Len=0.02834 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.0009521 Gap=0.0004417 Len=0.0293 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.001061 Gap=0.001016 Len=0.029 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.001061 Gap=0.001016 Len=0.029 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.0009521 Gap=0.0004417 Len=0.0293 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.002204 Len=0.02834 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg6 3 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -3E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.06 0.1 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt new file mode 100644 index 00000000000..45a5b8d9671 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 5 Wid=0.00508 Len=0.002994 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.02163 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.01024 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.02163 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.002994 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 5E+09 +Rstb3 6 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 9 0 5E+09 +Rstb8 10 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt new file mode 100644 index 00000000000..263e807e2e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-09 9E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_line_width.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_line_width.ckt new file mode 100644 index 00000000000..eadb1c49dce --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_line_width.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.005 Len=0.01652 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.005 Len=0.000635 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.00508 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.005 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=7.937E-05 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.00508 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.005 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0002533 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.00508 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.005 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0002533 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.00508 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.005 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=7.937E-05 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.005 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.00508 Len=0.01716 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.005 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.005 Len=0.01652 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.005 Len=0.000635 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -120 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-09 1.8E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.06 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_rotation_angle.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_rotation_angle.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_rotation_angle.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_end_gap_extension.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_end_gap_extension.ckt new file mode 100644 index 00000000000..cc66f914384 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_end_gap_extension.ckt @@ -0,0 +1,42 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.007534 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.006381 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 4 5 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 3 6 4 7 Gap=0.01391 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 6 7 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 3 6 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 6 8 7 9 Gap=7.937E-05 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 8 9 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 8 10 9 11 Gap=0.01391 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 10 11 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 10 12 11 13 Gap=0.0005276 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 12 13 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 12 14 13 15 Gap=0.01391 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 14 15 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 12 14 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 14 16 15 17 Gap=0.0005276 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 16 17 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 16 18 17 19 Gap=0.01391 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 18 19 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 18 20 19 21 Gap=7.937E-05 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 20 21 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 20 22 21 23 Gap=0.01391 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 20 22 Wid=0.00127 Len=0.01391 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 22 24 Wid=0.00127 Len=0.007534 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT27 24 23 Wid=0.00127 Len=0.006381 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT28 23 25 Wid=0.00127 Len=0.002 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 24 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -5E-09 1.5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.05 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_gap_width.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_gap_width.ckt new file mode 100644 index 00000000000..8eaca363479 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/ring_resonator_gap_width.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.008113 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.005675 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.01379 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=7.937E-05 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.01379 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0005237 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.01379 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0005237 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.01379 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=7.937E-05 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.01379 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.01379 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.008113 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.005675 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -5E-09 2.5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt new file mode 100644 index 00000000000..5ddaf2311fc --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -100 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_1.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_1.ckt new file mode 100644 index 00000000000..4ed7609b15c --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_1.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -3E-08 3E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.05 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_2.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_2.ckt new file mode 100644 index 00000000000..3b1903ab429 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tuning_type_2.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -4E-08 3E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.07 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt new file mode 100644 index 00000000000..5b2f2da3c55 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt @@ -0,0 +1,51 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MXTcoup0 3 2 5 4 Wid=5E-05 Gap=5E-05 Len=0.03147 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 5 6 Wid=5E-05 Len=2.5E-05 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S2 6 19 Wid=0.0003175 Len=0.03065 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 19 17 Wid=0.00508 Len=0.0003439 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S3 6 23 Wid=0.0003175 Len=0.01956 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 23 21 Wid=0.00508 Len=0.0002689 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 6 7 Wid=5E-05 Len=2.5E-05 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 7 10 9 Wid=5E-05 Gap=5E-05 Len=0.03145 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg4 10 11 Wid=5E-05 Len=2.5E-05 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S6 11 29 Wid=0.0003175 Len=0.02845 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S6 29 27 Wid=0.00508 Len=0.002097 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S7 11 33 Wid=0.0003175 Len=0.0149 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 33 31 Wid=0.00508 Len=0.00134 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 11 12 Wid=5E-05 Len=2.5E-05 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup6 13 12 15 14 Wid=5E-05 Gap=5E-05 Len=0.03147 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 15 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg7 6 0 5E+09 +Rstb8 17 0 5E+09 +Rstb9 18 0 5E+09 +Rstb10 19 0 5E+09 +Rstb11 21 0 5E+09 +Rstb12 22 0 5E+09 +Rstb13 23 0 5E+09 +Rseg14 7 0 5E+09 +Rseg15 11 0 5E+09 +Rstb16 27 0 5E+09 +Rstb17 28 0 5E+09 +Rstb18 29 0 5E+09 +Rstb19 31 0 5E+09 +Rstb20 32 0 5E+09 +Rstb21 33 0 5E+09 +Rseg22 12 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -120 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -3E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt new file mode 100644 index 00000000000..80412eecb4e --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt @@ -0,0 +1,43 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 2 10 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.0304 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +C1 3 4 3.935E-13 +MTSeg2 4 5 Wid=0.0003175 Len=0.0304 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 5 0 Wid=0.0003175 Len=0.000573 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S6 5 15 Wid=0.00508 Len=0.0226 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=0.0003175 Len=0.0304 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +C4 6 7 3.935E-13 +MTSeg5 7 8 Wid=0.0003175 Len=0.0304 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S9 8 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S10 8 20 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 8 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 10 0 5E+09 +Rstb7 11 0 5E+09 +Rseg8 3 0 5E+09 +Rseg9 4 0 5E+09 +Rseg10 5 0 5E+09 +Rstb11 15 0 5E+09 +Rstb12 16 0 5E+09 +Rseg13 6 0 5E+09 +Rseg14 7 0 5E+09 +Rstb15 20 0 5E+09 +Rstb16 21 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -6E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.06 0.06 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt new file mode 100644 index 00000000000..1c7ee82bce8 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.0007792 Len=0.01449 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S1 3 0 Wid=0.0007792 Len=0.018 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0007792 Len=0.01449 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 0 4 5 0 Wid=0.0003763 Gap=0.0005407 Len=0.02947 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 0 5 6 0 Wid=0.0004225 Gap=0.001121 Len=0.02926 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 0 6 7 0 Wid=0.0004225 Gap=0.001121 Len=0.02926 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup5 0 7 8 0 Wid=0.0003763 Gap=0.0005407 Len=0.02947 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg6 8 9 Wid=0.0007792 Len=0.01449 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 9 0 Wid=0.0007792 Len=0.018 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg7 9 10 Wid=0.0007792 Len=0.01449 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 10 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg8 3 0 5E+09 +Rseg9 4 0 5E+09 +Rseg10 9 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -5E-08 1.5E-07 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt new file mode 100644 index 00000000000..cd31a811b98 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt @@ -0,0 +1,29 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.0004828 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 0 3 4 Gap=0.000635 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 0 4 Wid=0.0004828 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 3 4 Wid=0.0004828 Len=0.000635 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 0 5 4 0 Gap=0.0008077 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 Wid=0.001735 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 5 0 0 6 Gap=0.001635 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 6 Wid=0.001735 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 0 7 6 0 Gap=0.001635 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 Wid=0.001735 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 7 0 0 8 Gap=0.0008077 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 0 8 Wid=0.0004828 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 0 9 8 10 Gap=0.000635 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 9 10 Wid=0.0004828 Len=0.02763 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 8 10 Wid=0.0004828 Len=0.000635 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -70 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -3E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/bridge_t.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/bridge_t.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/bridge_t_high.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t_high.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/bridge_t_high.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t_high.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/bridge_t_low.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t_low.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/bridge_t_low.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/bridge_t_low.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/c_lead_inductor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/c_lead_inductor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/c_lead_inductor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/c_lead_inductor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/c_node_capacitor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/c_node_capacitor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/c_node_capacitor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/c_node_capacitor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/c_node_compensate.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/c_node_compensate.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/c_node_compensate.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/c_node_compensate.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/capacitor_ls.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_ls.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/capacitor_ls.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_ls.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/capacitor_q.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_q.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/capacitor_q.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_q.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/capacitor_rp.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_rp.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/capacitor_rp.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_rp.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/capacitor_rs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_rs.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/capacitor_rs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/capacitor_rs.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/complex.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/complex.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/complex.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/complex.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/current_source.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/current_source.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/current_source.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/current_source.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_1.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_1.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_1.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_1.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_2.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_2.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_2.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_2.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_bs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_bs.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer1_bp_bs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_bp_bs.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer1_hi_lo.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_hi_lo.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer1_hi_lo.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer1_hi_lo.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer2_bp_bs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_bp_bs.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer2_bp_bs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_bp_bs.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer2_triplexer_1.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_triplexer_1.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer2_triplexer_1.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_triplexer_1.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/diplexer2_triplexer_2.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_triplexer_2.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/diplexer2_triplexer_2.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/diplexer2_triplexer_2.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/equal_capacitors.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_capacitors.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/equal_capacitors.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_capacitors.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/equal_inductors.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_inductors.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/equal_inductors.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_inductors.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/equal_legs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_legs.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/equal_legs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/equal_legs.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/first_series.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/first_series.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/first_series.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/first_series.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/first_shunt.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/first_shunt.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/first_shunt.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/first_shunt.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/generator_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/generator_resistor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/generator_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/generator_resistor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/high_low_pass.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/high_low_pass.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/high_low_pass.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/high_low_pass.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/high_low_pass_min_ind.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/high_low_pass_min_ind.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/high_low_pass_min_ind.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/high_low_pass_min_ind.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/import_tuned_variables.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/import_tuned_variables.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/import_tuned_variables.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/import_tuned_variables.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/imported_netlist.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/imported_netlist.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/imported_netlist.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/imported_netlist.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/inductor_cp.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_cp.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/inductor_cp.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_cp.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/inductor_q.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_q.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/inductor_q.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_q.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/inductor_rp.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_rp.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/inductor_rp.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_rp.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/inductor_rs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_rs.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/inductor_rs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/inductor_rs.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/l_lead_inductor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/l_lead_inductor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/l_lead_inductor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/l_lead_inductor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/l_node_capacitor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/l_node_capacitor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/l_node_capacitor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/l_node_capacitor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/l_node_compensate.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/l_node_compensate.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/l_node_compensate.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/l_node_compensate.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/laod_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/laod_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg b/tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts.cfg similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/library_parts.cfg rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts.cfg diff --git a/tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts_test.cfg b/tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts_test.cfg new file mode 100644 index 00000000000..4413ec85924 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Lumped/library_parts_test.cfg @@ -0,0 +1,45 @@ +modsubType=2 +modsubEr=2.25 +modsubRho=4.2E+07 +modsubTand=0.065 +modsubH=0.003 +modsubT=3.5E-07 +modsubS=0.00127 +modsubC=0.00635 +modsubErsel=-1 +modsubRhosel=-1 +modsubTandsel=-1 +modsubTanddef=0 +modsubiSubSel=0 +modsubName=User Defined Substrate +modsubBrow= +modsubNameVal=2.25 +modAnsSubIndex=0 +modAWRSubIndex=0 +webAWRSubIndex=0 +locAWRSubIndex=0 +ModelData=2 +ModelDataV=1 +ModelInd=0 +ModelCap=0 +ModelRes=0 +ModelIndV=1 +ModelCapV=1 +ModelResV=1 +modRatLen=2 +modRatZ=1 +Interc=1 +modActLen=0.00254 +modActWid=0.00127 +modRatZMin=0.5 +modRatZMax=2 +modRatLenMin=0.5 +modRatLenMax=2 +modActLenMin=0.00127 +modActWidMin=0.000635 +modActLenMax=0.00508 +modActWidMax=0.00254 +useGeo=0 +OptGeo=1 +indTol=1 +capTol=1 diff --git a/tests/system/general/test_45_FilterSolutions/resources/match_impedance.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/match_impedance.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/match_impedance.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/match_impedance.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/min_cap.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/min_cap.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/min_cap.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/min_cap.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/min_ind.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/min_ind.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/min_ind.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/min_ind.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/multiband.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/multiband.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/multiband.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/multiband.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/netlist.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/netlist.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/netlist.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/netlist.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/node_cap_ground.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/node_cap_ground.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/node_cap_ground.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/node_cap_ground.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/pspice.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/pspice.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/pspice.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/pspice.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/r_lead_inductor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/r_lead_inductor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/r_lead_inductor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/r_lead_inductor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/r_node_capacitor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/r_node_capacitor.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/r_node_capacitor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/r_node_capacitor.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/set_source_res.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/set_source_res.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/set_source_res.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/set_source_res.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/source_res.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/source_res.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/source_res.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/source_res.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/transferfunction.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/transferfunction.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/transferfunction.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/transferfunction.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/trap_topology.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/trap_topology.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/trap_topology.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/trap_topology.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/zig_zag.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/zig_zag.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/zig_zag.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/zig_zag.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/resources.py b/tests/system/general/test_45_FilterSolutions/resources/resources.py index 2cdcbbb2952..e17da0a83f1 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/resources.py +++ b/tests/system/general/test_45_FilterSolutions/resources/resources.py @@ -32,10 +32,12 @@ def resources_directory(): return resources_path -def resource_path(resource_file_name): +def resource_path(resource_file_name, implementation=None): + if implementation: + return os.path.join(resources_directory(), implementation, resource_file_name) return os.path.join(resources_directory(), resource_file_name) -def read_resource_file(filename): - with open(resource_path(filename)) as f: +def read_resource_file(filename, implementation=None): + with open(resource_path(filename, implementation)) as f: return f.read().splitlines() diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py new file mode 100644 index 00000000000..9c4476773da --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py @@ -0,0 +1,23 @@ +# -*- coding: utf-8 -*- +# +# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# SPDX-License-Identifier: MIT +# +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py new file mode 100644 index 00000000000..ca321697ef5 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py @@ -0,0 +1,541 @@ +# -*- coding: utf-8 -*- +# +# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# SPDX-License-Identifier: MIT +# +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +import ansys.aedt.core +import ansys.aedt.core.filtersolutions +from ansys.aedt.core.filtersolutions_core.attributes import FilterClass +from ansys.aedt.core.filtersolutions_core.attributes import FilterType +from ansys.aedt.core.filtersolutions_core.distributed_topology import TapPosition +from ansys.aedt.core.filtersolutions_core.distributed_topology import TopologyList +from ansys.aedt.core.generic.general_methods import is_linux +import pytest + +from tests.system.general.conftest import config + +from ..resources import read_resource_file + + +@pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") +@pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") +class TestClass: + def test_distributed_generator_resistor_30(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + assert design.topology.generator_resistor == "50" + design.topology.generator_resistor = "30" + assert design.topology.generator_resistor == "30" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "generator_resistor.ckt", "Distributed" + ) + + def test_distributed_load_resistor_30(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + assert design.topology.load_resistor == "50" + design.topology.load_resistor = "30" + assert design.topology.load_resistor == "30" + assert design.topology.circuit_response().splitlines() == read_resource_file("load_resistor.ckt", "Distributed") + + def test_distributed_first_shunt(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + assert design.topology.first_shunt + design.topology.first_shunt = True + assert design.topology.first_shunt + assert design.topology.circuit_response().splitlines() == read_resource_file("first_shunt.ckt", "Distributed") + + def test_distributed_first_series(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + assert design.topology.first_shunt + design.topology.first_shunt = False + assert design.topology.first_shunt is False + assert design.topology.circuit_response().splitlines() == read_resource_file("first_series.ckt", "Distributed") + + def test_distributed_first_fat(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.first_fat = True + assert info.value.args[0] == "The First Segment Fat or Thin property is not supported for the selected topology" + design.topology.topology_list = TopologyList.STEPPED_IMPEDANCE + assert design.topology.first_fat + design.topology.first_fat = True + assert design.topology.first_fat + assert design.topology.circuit_response().splitlines() == read_resource_file("first_fat.ckt", "Distributed") + + def test_distributed_first_thin(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.first_fat = False + assert info.value.args[0] == "The First Segment Fat or Thin property is not supported for the selected topology" + design.topology.topology_list = TopologyList.STEPPED_IMPEDANCE + assert design.topology.first_fat + design.topology.first_fat = False + assert design.topology.first_fat is False + assert design.topology.circuit_response().splitlines() == read_resource_file("first_thin.ckt", "Distributed") + + def test_distributed_use_series_caps(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.use_series_caps = True + assert info.value.args[0] == "The Series Caps property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + assert design.topology.use_series_caps is False + design.topology.use_series_caps = True + assert design.topology.use_series_caps + assert design.topology.circuit_response().splitlines() == read_resource_file( + "use_series_caps.ckt", "Distributed" + ) + + def test_distributed_combine_stubs(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.combine_stubs = True + assert info.value.args[0] == "The Combine Stubs property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + assert design.topology.combine_stubs is False + design.topology.combine_stubs = True + assert design.topology.combine_stubs + assert design.topology.circuit_response().splitlines() == read_resource_file("combine_stubs.ckt", "Distributed") + + def test_use_coupled_lines(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.use_coupled_lines = True + assert info.value.args[0] == "The Coupled Lines property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.attributes.filter_type = FilterType.ELLIPTIC + assert design.topology.use_coupled_lines is False + design.topology.use_coupled_lines = True + assert design.topology.use_coupled_lines + assert design.topology.circuit_response().splitlines() == read_resource_file( + "use_coupled_lines.ckt", "Distributed" + ) + + def test_equal_width_approx(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.equal_width_approx = True + assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.INTERDIGITAL + assert design.topology.equal_width_approx + design.topology.equal_width_approx = False + assert design.topology.equal_width_approx is False + assert design.topology.circuit_response().splitlines() == read_resource_file( + "equal_width_approx.ckt", "Distributed" + ) + + def test_open_stub_ground(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.open_stub_ground = True + assert info.value.args[0] == "The Open Stub Ground property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_STOP + design.topology.topology_list = TopologyList.NOTCH_RESONATORS + assert design.topology.open_stub_ground is False + design.topology.open_stub_ground = True + assert design.topology.open_stub_ground + design.topology.open_stub_ground = False + assert design.topology.circuit_response().splitlines() == read_resource_file( + "open_stub_ground.ckt", "Distributed" + ) + + def test_left_ground_side(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.left_ground_side = True + assert info.value.args[0] == "The Left Ground Side property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_STOP + design.topology.topology_list = TopologyList.NOTCH_RESONATORS + assert design.topology.left_ground_side + design.topology.left_ground_side = False + assert design.topology.left_ground_side is False + assert design.topology.circuit_response().splitlines() == read_resource_file( + "left_ground_side.ckt", "Distributed" + ) + + def test_equal_stub_widths(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.equal_stub_widths = True + assert info.value.args[0] == "The Equal Stub Widths property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.SHUNT_STUB_RESONATORS + assert design.topology.equal_stub_widths is False + design.topology.equal_stub_widths = True + assert design.topology.equal_stub_widths + assert design.topology.circuit_response().splitlines() == read_resource_file( + "equal_stub_widths.ckt", "Distributed" + ) + + def test_center_z0_impedance(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.center_z0_impedance = "55" + assert info.value.args[0] == "The Center Z0 property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.SHUNT_STUB_RESONATORS + design.topology.equal_stub_widths = False + assert design.topology.center_z0_impedance == "75" + design.topology.center_z0_impedance = "55" + assert design.topology.center_z0_impedance == "55" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "center_z0_impedance.ckt", "Distributed" + ) + + def test_equal_width_conductors(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.equal_width_conductors = True + assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.equal_width_conductors + design.topology.equal_width_conductors = False + assert design.topology.equal_width_conductors is False + assert design.topology.circuit_response().splitlines() == read_resource_file( + "equal_width_conductors.ckt", "Distributed" + ) + + def test_tapped(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.tapped = True + assert info.value.args[0] == "The Tapped property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.tapped + design.topology.tapped = False + assert design.topology.tapped is False + assert design.topology.circuit_response().splitlines() == read_resource_file("tapped.ckt", "Distributed") + + def test_pinned(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.pinned = True + assert info.value.args[0] == "The Pinned property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.pinned is False + design.topology.pinned = True + assert design.topology.pinned + assert design.topology.equal_width_conductors is False + assert design.topology.circuit_response().splitlines() == read_resource_file("pinned.ckt", "Distributed") + + def test_stub_taps(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.stub_taps = True + assert info.value.args[0] == "The Stub Taps property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.stub_taps is False + design.topology.stub_taps = True + assert design.topology.stub_taps + assert design.topology.circuit_response().splitlines() == read_resource_file("stub_taps.ckt", "Distributed") + + def test_via_ends(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.via_ends = True + assert info.value.args[0] == "The Via Ends property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.via_ends is False + design.topology.via_ends = True + assert design.topology.via_ends + assert design.topology.equal_width_conductors is False + assert design.topology.circuit_response().splitlines() == read_resource_file("via_ends.ckt", "Distributed") + + def test_resonator_line_width(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.resonator_line_width = "1.27 mm" + assert info.value.args[0] == "The Line Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.resonator_line_width == "1.27 mm" + design.topology.resonator_line_width = "5 mm" + assert design.topology.resonator_line_width == "5 mm" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "resonator_line_width.ckt", "Distributed" + ) + + def test_resonator_rotation_angle(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.resonator_rotation_angle = "0" + assert info.value.args[0] == "The Rotation Angle property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED + assert design.topology.resonator_rotation_angle == "0" + design.topology.resonator_rotation_angle = "5" + assert design.topology.resonator_rotation_angle == "5" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "resonator_rotation_angle.ckt", "Distributed" + ) + + def test_mitered_corners(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.mitered_corners = True + assert info.value.args[0] == "The Mitered Corners property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.mitered_corners is False + design.topology.mitered_corners = True + assert design.topology.mitered_corners + assert design.topology.circuit_response().splitlines() == read_resource_file( + "mitered_corners.ckt", "Distributed" + ) + + def test_hairpin_gap_width(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.hairpin_gap_width = "0.127 mm" + assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.hairpin_gap_width == "2.54 mm" + design.topology.hairpin_gap_width = "4 mm" + assert design.topology.hairpin_gap_width == "4 mm" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "hairpin_gap_width.ckt", "Distributed" + ) + + def test_miniature_hairpin_gap_width(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.miniature_hairpin_gap_width = "635 um" + assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN + assert design.topology.miniature_hairpin_gap_width == "635 um" + design.topology.miniature_hairpin_gap_width = "450 um" + assert design.topology.miniature_hairpin_gap_width == "450 um" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "miniature_hairpin_gap_width.ckt", "Distributed" + ) + + def test_ring_resonator_gap_width(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.ring_resonator_gap_width = "635 um" + assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.RING_RESONATOR + assert design.topology.ring_resonator_gap_width == "635 um" + design.topology.ring_resonator_gap_width = "450 um" + assert design.topology.ring_resonator_gap_width == "450 um" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "ring_resonator_gap_width.ckt", "Distributed" + ) + + def test_hairpin_extension_length(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.hairpin_extension_length = "0 mm" + assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.hairpin_extension_length == "0 um" + design.topology.hairpin_extension_length = "2 mm" + assert design.topology.hairpin_extension_length == "2 mm" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "hairpin_extension_length.ckt", "Distributed" + ) + + def test_miniature_hairpin_end_curl_extension(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.miniature_hairpin_end_curl_extension = "0 mm" + assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN + assert design.topology.miniature_hairpin_end_curl_extension == "0 um" + design.topology.miniature_hairpin_end_curl_extension = "2 mm" + assert design.topology.miniature_hairpin_end_curl_extension == "2 mm" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "miniature_hairpin_end_curl_extension.ckt", "Distributed" + ) + + def test_ring_resonator_end_gap_extension(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.ring_resonator_end_gap_extension = "0 mm" + assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.RING_RESONATOR + assert design.topology.ring_resonator_end_gap_extension == "0 um" + design.topology.ring_resonator_end_gap_extension = "2 mm" + assert design.topology.ring_resonator_end_gap_extension == "2 mm" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "ring_resonator_end_gap_extension.ckt", "Distributed" + ) + + def test_tuning_type_1(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.tuning_type_1 = True + assert info.value.args[0] == "The Tuning Type property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.tuning_type_1 + design.topology.tuning_type_1 = False + assert design.topology.tuning_type_1 is False + assert design.topology.circuit_response().splitlines() == read_resource_file("tuning_type_1.ckt", "Distributed") + + def test_tuning_type_2(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.tuning_type_1 = True + assert info.value.args[0] == "The Tuning Type property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.HAIRPIN + assert design.topology.tuning_type_1 + assert design.topology.circuit_response().splitlines() == read_resource_file("tuning_type_2.ckt", "Distributed") + + def test_tap_position(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.tap_position = TapPosition.AUTO + assert info.value.args[0] == "The Tap Position property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN + assert design.topology.tap_position == TapPosition.AUTO + design.topology.tap_position = TapPosition.SIDES + assert design.topology.tap_position == TapPosition.SIDES + assert design.topology.circuit_response().splitlines() == read_resource_file("tap_position.ckt", "Distributed") + + def test_wide_band(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.wide_band = True + assert info.value.args[0] == "The Wide Band property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.INTERDIGITAL + assert design.topology.wide_band is False + design.topology.wide_band = True + design.topology.pinned = True + assert design.topology.wide_band + assert design.topology.circuit_response().splitlines() == read_resource_file("wide_band.ckt", "Distributed") + + def test_open_ends(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.open_ends = True + assert info.value.args[0] == "The Open Ends property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.INTERDIGITAL + assert design.topology.open_ends is False + design.topology.open_ends = True + assert design.topology.open_ends + assert design.topology.circuit_response().splitlines() == read_resource_file("open_ends.ckt", "Distributed") + + def test_combline_half_length_frequency(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.combline_half_length_frequency = "4G" + assert info.value.args[0] == "The 1/2 Length Frequency property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.COMBLINE + assert design.topology.combline_half_length_frequency == "4G" + design.topology.combline_half_length_frequency = "2 GHz" + assert design.topology.combline_half_length_frequency == "2 GHz" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "combline_half_length_frequency.ckt", "Distributed" + ) + + def test_coupled_segments_quarter_length_frequency(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + + with pytest.raises(RuntimeError) as info: + design.topology.coupled_segments_quarter_length_frequency = "4G" + assert info.value.args[0] == "The 1/4 Length Frequency property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.HIGH_PASS + design.topology.topology_list = TopologyList.COUPLED_SEGMENTS + assert design.topology.coupled_segments_quarter_length_frequency == "4G" + design.topology.coupled_segments_quarter_length_frequency = "2 GHz" + assert design.topology.coupled_segments_quarter_length_frequency == "2 GHz" + assert design.topology.circuit_response().splitlines() == read_resource_file( + "coupled_segments_quarter_length_frequency.ckt", "Distributed" + ) + + def test_circuit_response(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + assert design.topology.circuit_response().splitlines() == read_resource_file("default.ckt", "Distributed") + + def test_quick_optimize(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + assert design.topology.quick_optimize is False + design.topology.quick_optimize = True + assert design.topology.quick_optimize + assert design.topology.circuit_response().splitlines() == read_resource_file( + "quick_optimize.ckt", "Distributed" + ) + + def test_resonator_length_extension(self): + design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: + design.topology.resonator_length_extension = True + assert info.value.args[0] == "The Enable Extension property is not supported for the selected topology" + design.attributes.filter_class = FilterClass.BAND_PASS + design.topology.topology_list = TopologyList.INTERDIGITAL + assert design.topology.resonator_length_extension is False + design.topology.resonator_length_extension = True + assert design.topology.resonator_length_extension + assert design.topology.circuit_response().splitlines() == read_resource_file( + "resonator_length_extension.ckt", "Distributed" + ) diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py index 28ade85e37f..6f961af19a7 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py @@ -23,6 +23,7 @@ # SOFTWARE. import ansys.aedt.core +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import BesselRipplePercentage from ansys.aedt.core.filtersolutions_core.attributes import DiplexerType from ansys.aedt.core.filtersolutions_core.attributes import FilterClass @@ -44,7 +45,8 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_filter_type(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.filter_type == FilterType.BUTTERWORTH assert len(FilterType) == 10 @@ -56,7 +58,8 @@ def test_filter_type(self): assert design.attributes.filter_type == ftype def test_filter_class(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.filter_class == FilterClass.LOW_PASS # Only lumped supports all classes @@ -70,13 +73,15 @@ def test_filter_class(self): assert design.attributes.filter_class == fclass def test_filter_multiple_bands_enabled(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.filter_multiple_bands_enabled is False design.attributes.filter_multiple_bands_enabled = True assert design.attributes.filter_multiple_bands_enabled def test_filter_multiple_bands_low_pass_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True design.attributes.filter_class = FilterClass.LOW_BAND assert design.attributes.filter_multiple_bands_low_pass_frequency == "1G" @@ -84,7 +89,8 @@ def test_filter_multiple_bands_low_pass_frequency(self): assert design.attributes.filter_multiple_bands_low_pass_frequency == "500M" def test_filter_multiple_bands_high_pass_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True design.attributes.filter_class = FilterClass.BAND_HIGH assert design.attributes.filter_multiple_bands_high_pass_frequency == "1G" @@ -92,14 +98,16 @@ def test_filter_multiple_bands_high_pass_frequency(self): assert design.attributes.filter_multiple_bands_high_pass_frequency == "500M" def test_filter_implementation(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert len(FilterImplementation) == 5 for fimplementation in FilterImplementation: design.attributes.filter_implementation = fimplementation assert design.attributes.filter_implementation == fimplementation def test_diplexer_type(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert len(DiplexerType) == 6 for index, diplexer_type in enumerate(DiplexerType): if index < 3: @@ -110,7 +118,8 @@ def test_diplexer_type(self): assert design.attributes.diplexer_type == diplexer_type def test_filter_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.filter_order == 5 with pytest.raises(RuntimeError) as info: @@ -126,45 +135,52 @@ def test_filter_order(self): assert info.value.args[0] == "The maximum order is 21" def test_minimum_order_stop_band_att(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.minimum_order_stop_band_attenuation_db == "60 dB" design.attributes.minimum_order_stop_band_attenuation_db = "40 dB" assert design.attributes.minimum_order_stop_band_attenuation_db == "40 dB" def test_minimum_order_stop_band_freq(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.minimum_order_stop_band_frequency == "10 GHz" design.attributes.minimum_order_stop_band_frequency = "500 MHz" assert design.attributes.minimum_order_stop_band_frequency == "500 MHz" def test_minimum_order_group_delay_error_percent(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.DELAY assert design.attributes.minimum_order_group_delay_error_percent == "5" design.attributes.minimum_order_group_delay_error_percent = "7" assert design.attributes.minimum_order_group_delay_error_percent == "7" def test_minimum_order_group_delay_cutoff(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.DELAY assert design.attributes.minimum_order_group_delay_cutoff == "2 GHz" design.attributes.minimum_order_group_delay_cutoff = "500 MHz" assert design.attributes.minimum_order_group_delay_cutoff == "500 MHz" def test_minimum_order_stop_band_freq(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.minimum_order_stop_band_frequency == "10 GHz" design.attributes.minimum_order_stop_band_frequency = "500 MHz" assert design.attributes.minimum_order_stop_band_frequency == "500 MHz" def test_minimum_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.filter_order == 5 design.attributes.ideal_minimum_order assert design.attributes.filter_order == 3 def test_pass_band_definition(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS assert len(PassbandDefinition) == 2 assert design.attributes.pass_band_definition == PassbandDefinition.CENTER_FREQUENCY @@ -173,20 +189,23 @@ def test_pass_band_definition(self): assert design.attributes.pass_band_definition == pbd def test_pass_band_center_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.pass_band_center_frequency == "1G" design.attributes.pass_band_center_frequency = "500M" assert design.attributes.pass_band_center_frequency == "500M" def test_pass_band_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS assert design.attributes.pass_band_width_frequency == "200M" design.attributes.pass_band_width_frequency = "500M" assert design.attributes.pass_band_width_frequency == "500M" def test_lower_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES assert design.attributes.lower_frequency == "905 M" @@ -194,7 +213,8 @@ def test_lower_frequency(self): assert design.attributes.lower_frequency == "800M" def test_upper_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES assert design.attributes.upper_frequency == "1.105 G" @@ -202,7 +222,8 @@ def test_upper_frequency(self): assert design.attributes.upper_frequency == "1.2 G" def test_stop_band_definition(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert len(StopbandDefinition) == 3 assert design.attributes.stop_band_definition == StopbandDefinition.RATIO @@ -211,14 +232,16 @@ def test_stop_band_definition(self): assert design.attributes.stop_band_definition == sbd def test_stop_band_ratio(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert design.attributes.stop_band_ratio == "1.2" design.attributes.stop_band_ratio = "1.5" assert design.attributes.stop_band_ratio == "1.5" def test_stop_band_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.stop_band_definition = StopbandDefinition.FREQUENCY assert design.attributes.stop_band_frequency == "1.2 G" @@ -226,7 +249,8 @@ def test_stop_band_frequency(self): assert design.attributes.stop_band_frequency == "1.5 G" def test_stop_band_attenuation(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.stop_band_definition = StopbandDefinition.ATTENUATION_DB assert design.attributes.stop_band_attenuation_db == "60" @@ -234,34 +258,39 @@ def test_stop_band_attenuation(self): assert design.attributes.stop_band_attenuation_db == "40" def test_standard_pass_band_attenuation(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.standard_pass_band_attenuation design.attributes.standard_pass_band_attenuation = False assert design.attributes.standard_pass_band_attenuation is False def test_standard_pass_band_attenuation_value_db(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.standard_pass_band_attenuation = False assert design.attributes.standard_pass_band_attenuation_value_db == "3.01" design.attributes.standard_pass_band_attenuation_value_db = "4" assert design.attributes.standard_pass_band_attenuation_value_db == "4" def test_equiripple_delay(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.DELAY assert design.attributes.equiripple_delay design.attributes.equiripple_delay = False assert design.attributes.equiripple_delay is False def test_group_delay_ripple_period(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.DELAY assert design.attributes.group_delay_ripple_period == "2" design.attributes.group_delay_ripple_period = "3" assert design.attributes.group_delay_ripple_period == "3" def test_normalized_group_delay_percentage(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.DELAY assert len(BesselRipplePercentage) == 6 for normalized_group_delay_percentage in BesselRipplePercentage: @@ -269,14 +298,16 @@ def test_normalized_group_delay_percentage(self): assert design.attributes.normalized_group_delay_percentage == normalized_group_delay_percentage def test_bessel_normalized_delay(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.BESSEL assert design.attributes.bessel_normalized_delay is False design.attributes.bessel_normalized_delay = True assert design.attributes.bessel_normalized_delay def test_bessel_normalized_delay_period(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.BESSEL design.attributes.bessel_normalized_delay = True assert design.attributes.bessel_normalized_delay_period == "2" @@ -284,7 +315,8 @@ def test_bessel_normalized_delay_period(self): assert design.attributes.bessel_normalized_delay_period == "3" def test_bessel_normalized_delay_percentage(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.BESSEL design.attributes.bessel_normalized_delay = True assert len(BesselRipplePercentage) == 6 @@ -293,14 +325,16 @@ def test_bessel_normalized_delay_percentage(self): assert design.attributes.bessel_normalized_delay_percentage == bessel_normalized_delay_percentage def test_pass_band_ripple(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert design.attributes.pass_band_ripple == ".05" design.attributes.pass_band_ripple = ".03" assert design.attributes.pass_band_ripple == ".03" def test_arith_symmetry(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.filter_class = FilterClass.BAND_PASS assert design.attributes.arith_symmetry is False @@ -308,14 +342,16 @@ def test_arith_symmetry(self): assert design.attributes.arith_symmetry def test_asymmetric(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS assert design.attributes.asymmetric is False design.attributes.asymmetric = True assert design.attributes.asymmetric def test_asymmetric_low_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.asymmetric = True assert design.attributes.asymmetric_low_order == 5 @@ -333,7 +369,8 @@ def test_asymmetric_low_order(self): assert info.value.args[0] == "The maximum order is 21" def test_asymmetric_high_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.asymmetric = True assert design.attributes.asymmetric_high_order == 5 @@ -351,7 +388,8 @@ def test_asymmetric_high_order(self): assert info.value.args[0] == "The maximum order is 21" def test_asymmetric_low_stop_band_ratio(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.asymmetric = True @@ -360,7 +398,8 @@ def test_asymmetric_low_stop_band_ratio(self): assert design.attributes.asymmetric_low_stop_band_ratio == "1.5" def test_asymmetric_high_stop_band_ratio(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.asymmetric = True @@ -369,7 +408,8 @@ def test_asymmetric_high_stop_band_ratio(self): assert design.attributes.asymmetric_high_stop_band_ratio == "1.5" def test_asymmetric_low_stop_band_attenuation_db(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.asymmetric = True @@ -378,7 +418,8 @@ def test_asymmetric_low_stop_band_attenuation_db(self): assert design.attributes.asymmetric_low_stop_band_attenuation_db == "40" def test_asymmetric_high_stop_band_attenuation_db(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.asymmetric = True @@ -387,7 +428,8 @@ def test_asymmetric_high_stop_band_attenuation_db(self): assert design.attributes.asymmetric_high_stop_band_attenuation_db == "40" def test_gaussian_transition(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.GAUSSIAN assert len(GaussianTransition) == 6 for gaussian_transition in GaussianTransition: @@ -395,7 +437,8 @@ def test_gaussian_transition(self): assert design.attributes.gaussian_transition == gaussian_transition def test_gaussian_bessel_reflection(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.BESSEL assert len(GaussianBesselReflection) == 3 for gaussian_bessel_reflection in GaussianBesselReflection: @@ -403,7 +446,8 @@ def test_gaussian_bessel_reflection(self): assert design.attributes.gaussian_bessel_reflection == gaussian_bessel_reflection def test_even_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.filter_order = 4 assert design.attributes.even_order @@ -411,7 +455,8 @@ def test_even_order(self): assert design.attributes.even_order is False def test_even_order_refl_zero(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.filter_order = 4 assert design.attributes.even_order_refl_zero @@ -419,7 +464,8 @@ def test_even_order_refl_zero(self): assert design.attributes.even_order_refl_zero is False def test_even_order_trn_zero(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.filter_order = 4 assert design.attributes.even_order_trn_zero @@ -427,28 +473,32 @@ def test_even_order_trn_zero(self): assert design.attributes.even_order_trn_zero is False def test_constrict_ripple(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert design.attributes.constrict_ripple is False design.attributes.constrict_ripple = True assert design.attributes.constrict_ripple def test_single_point_ripple(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert design.attributes.single_point_ripple is False design.attributes.single_point_ripple = True assert design.attributes.single_point_ripple def test_half_band_ripple(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC assert design.attributes.half_band_ripple is False design.attributes.half_band_ripple = True assert design.attributes.half_band_ripple def test_constrict_ripple_percent(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.constrict_ripple = True assert design.attributes.constrict_ripple_percent == "50%" @@ -456,7 +506,8 @@ def test_constrict_ripple_percent(self): assert design.attributes.constrict_ripple_percent == "40%" def test_ripple_constriction_band(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.constrict_ripple = True assert len(RippleConstrictionBandSelect) == 3 @@ -465,7 +516,8 @@ def test_ripple_constriction_band(self): assert design.attributes.ripple_constriction_band == ripple_constriction_band def test_single_point_ripple_inf_zeros(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_type = FilterType.ELLIPTIC design.attributes.single_point_ripple = True assert len(SinglePointRippleInfZeros) == 2 @@ -474,13 +526,15 @@ def test_single_point_ripple_inf_zeros(self): assert design.attributes.single_point_ripple_inf_zeros == single_point_ripple_inf_zeros def test_delay_equalizer(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.attributes.delay_equalizer is False design.attributes.delay_equalizer = True assert design.attributes.delay_equalizer def test_delay_equalizer_order(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.delay_equalizer = True assert design.attributes.delay_equalizer_order == 2 @@ -493,14 +547,16 @@ def test_delay_equalizer_order(self): assert info.value.args[0] == "The maximum order is 20" def test_standard_delay_equ_pass_band_attenuation(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.delay_equalizer = True assert design.attributes.standard_delay_equ_pass_band_attenuation design.attributes.standard_delay_equ_pass_band_attenuation = False assert design.attributes.standard_delay_equ_pass_band_attenuation is False def test_standard_delay_equ_pass_band_attenuation_value_db(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.delay_equalizer = True design.attributes.standard_delay_equ_pass_band_attenuation = False assert design.attributes.standard_delay_equ_pass_band_attenuation_value_db == "3.01" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py index 78059eb3ad7..33a10fc59cd 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import FilterType from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -50,7 +50,8 @@ def test_enum_to_string(self): assert ansys.aedt.core.filtersolutions_core._dll_interface().enum_to_string(FilterType.GAUSSIAN) == "gaussian" def test_raise_error(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_ratio.row(0) assert info.value.args[0] == test_transmission_zeros.TestClass.no_transmission_zero_msg diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py index 24cdaf46449..ecf87eb1969 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -35,25 +35,29 @@ class TestClass: def test_minimum_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.graph_setup.minimum_frequency == "200 MHz" design.graph_setup.minimum_frequency = "500 MHz" assert design.graph_setup.minimum_frequency == "500 MHz" def test_maximum_frequency(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.graph_setup.maximum_frequency == "5 GHz" design.graph_setup.maximum_frequency = "2 GHz" assert design.graph_setup.maximum_frequency == "2 GHz" def test_minimum_time(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.graph_setup.minimum_time == "0" design.graph_setup.minimum_time = "5 ns" assert design.graph_setup.minimum_time == "5 ns" def test_maximum_time(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.graph_setup.maximum_time == "10 ns" design.graph_setup.maximum_time = "8 ns" assert design.graph_setup.maximum_time == "8 ns" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py index 1bfd2dd1568..7cd3847462d 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.ideal_response import FrequencyResponseColumn from ansys.aedt.core.filtersolutions_core.ideal_response import PoleZerosResponseColumn from ansys.aedt.core.filtersolutions_core.ideal_response import SParametersResponseColumn @@ -40,7 +40,7 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_frequency_response_getter(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) mag_db = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_DB) assert len(mag_db) == 500 @@ -94,7 +94,8 @@ def test_frequency_response_getter(self): assert freqs[-1] == 31214328219.225075 def test_time_response_getter(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + step_response = design.ideal_response._time_response_getter(TimeResponseColumn.STEP_RESPONSE) assert len(step_response) == 300 assert step_response[100] == pytest.approx(1.0006647872833518) @@ -132,7 +133,8 @@ def test_time_response_getter(self): assert time[-1] == pytest.approx(9.966666666666667e-09) def test_sparameters_response_getter(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + s11_response_db = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S11_DB) assert len(s11_response_db) == 500 assert s11_response_db[100] == pytest.approx(-41.93847819973562) @@ -160,7 +162,8 @@ def test_sparameters_response_getter(self): assert freqs[-1] == pytest.approx(31214328219.225075) def test_pole_zeros_response_getter(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + pole_zero_den_x = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.TX_ZERO_DEN_X) assert len(pole_zero_den_x) == 5 assert pole_zero_den_x[0] == pytest.approx(-1000000000.0) @@ -271,13 +274,15 @@ def test_pole_zeros_response_getter(self): assert proto_rx_zero_num_y[4] == pytest.approx(0.0) def test_filter_vsg_analysis_enabled(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.ideal_response.vsg_analysis_enabled is False design.ideal_response.vsg_analysis_enabled = True assert design.ideal_response.vsg_analysis_enabled def test_frequency_response(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + freq, mag_db = design.ideal_response.frequency_response( y_axis_parameter=FrequencyResponseColumn.MAGNITUDE_DB, minimum_frequency=None, @@ -304,7 +309,8 @@ def test_frequency_response(self): assert mag_db[-1] == pytest.approx(-47.41677994558435) def test_time_response(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + time, step_response = design.ideal_response.time_response( y_axis_parameter=TimeResponseColumn.STEP_RESPONSE, minimum_time=None, @@ -331,7 +337,8 @@ def test_time_response(self): assert step_response[-1] == pytest.approx(0.9999962734156826) def test_s_parameters(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + freq, s21_db = design.ideal_response.s_parameters( y_axis_parameter=SParametersResponseColumn.S21_DB, minimum_frequency=None, @@ -356,7 +363,8 @@ def test_s_parameters(self): assert s21_db[-1] == pytest.approx(-47.41677994558435) def test_pole_zero_locations(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + tx_zero_den_x, tx_zero_den_y = design.ideal_response.pole_zero_locations( x_axis_parameter=PoleZerosResponseColumn.TX_ZERO_DEN_X, y_axis_parameter=PoleZerosResponseColumn.TX_ZERO_DEN_Y, @@ -375,7 +383,8 @@ def test_pole_zero_locations(self): assert tx_zero_den_y[4] == pytest.approx(-951056516.2951534) def test_transfer_function_response(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.ideal_response.transfer_function_response().splitlines() == read_resource_file( - "transferfunction.ckt" + "transferfunction.ckt", "Lumped" ) diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py index 2050efce0a8..c681d84e15a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -34,17 +34,20 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_row_count(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True assert design.multiple_bands_table.row_count == 2 def test_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True assert design.multiple_bands_table.row(0) == ("2G", "3G") def test_update_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True with pytest.raises(RuntimeError) as info: design.multiple_bands_table.update_row(0) @@ -57,7 +60,8 @@ def test_update_row(self): assert design.multiple_bands_table.row(0) == ("200M", "5G") def test_append_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True design.multiple_bands_table.append_row("100M", "500M") assert design.multiple_bands_table.row_count == 3 @@ -70,7 +74,8 @@ def test_append_row(self): assert info.value.args[0] == "It is not possible to append an empty value" def test_insert_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True design.multiple_bands_table.insert_row(0, "200M", "5G") assert design.multiple_bands_table.row(0) == ("200M", "5G") @@ -81,7 +86,8 @@ def test_insert_row(self): assert info.value.args[0] == "The rowIndex must be greater than zero and less than row count" def test_remove_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True design.multiple_bands_table.remove_row(0) assert design.multiple_bands_table.row(0) == ("4G", "5G") @@ -93,7 +99,8 @@ def test_remove_row(self): ) def test_clear_table(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.attributes.filter_multiple_bands_enabled = True # There are 2 rows in the table by default assert design.multiple_bands_table.row_count == 2 diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py index 1cf81d7b2b3..ebc8f049470 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -38,12 +38,14 @@ class TestClass: input_value_blank_msg = "The input value is blank" def test_row_count(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert design.transmission_zeros_bandwidth.row_count == 0 assert design.transmission_zeros_ratio.row_count == 0 def test_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_bandwidth.row(0) assert info.value.args[0] == self.no_transmission_zero_msg @@ -52,7 +54,8 @@ def test_row(self): assert info.value.args[0] == self.no_transmission_zero_msg def test_update_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_bandwidth.update_row(0, zero="1.3G", position="2") assert info.value.args[0] == self.no_transmission_zero_update_msg @@ -61,7 +64,8 @@ def test_update_row(self): assert info.value.args[0] == self.no_transmission_zero_update_msg def test_append_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_bandwidth.append_row(zero="", position="") assert info.value.args[0] == self.input_value_blank_msg @@ -81,7 +85,8 @@ def test_append_row(self): assert design.transmission_zeros_ratio.row(0) == ("1.6", "2") def test_insert_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_bandwidth.insert_row(6, zero="1.3G", position="2") assert info.value.args[0] == "The given index 6 is larger than zeros order" @@ -105,7 +110,8 @@ def test_insert_row(self): assert design.transmission_zeros_ratio.row(0) == ("1.6", "2") def test_remove_row(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_bandwidth.remove_row(2) assert info.value.args[0] == "The given index 2 is larger than zeros order" @@ -116,7 +122,8 @@ def test_remove_row(self): assert info.value.args[0] == self.no_transmission_zero_msg def test_clear_table(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") design.transmission_zeros_bandwidth.clear_table() @@ -131,7 +138,8 @@ def test_clear_table(self): assert info.value.args[0] == self.no_transmission_zero_msg def test_restore_default_positions(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") design.transmission_zeros_bandwidth.restore_default_positions() assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "3") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 876c335be0a..0818334b2a7 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.export_to_aedt import PartLibraries from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateEr from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateResistivity @@ -49,7 +49,8 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2") class TestClass: def test_modelithics_inductor_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -57,7 +58,8 @@ def test_modelithics_inductor_list_count(self): assert lumpdesign.export_to_aedt.modelithics_inductor_list_count == 116 def test_modelithics_inductor_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -69,7 +71,8 @@ def test_modelithics_inductor_list(self): assert lumpdesign.export_to_aedt.modelithics_inductor_list(0) == first_modelithics_inductor def test_modelithics_inductor_selection(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -81,7 +84,8 @@ def test_modelithics_inductor_selection(self): assert lumpdesign.export_to_aedt.modelithics_inductor_selection == first_modelithics_inductor def test_modelithics_inductor_family_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -93,7 +97,8 @@ def test_modelithics_inductor_family_list_count(self): assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 2 def test_modelithics_inductor_family_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -107,7 +112,8 @@ def test_modelithics_inductor_family_list(self): assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor def test_modelithics_inductor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -121,7 +127,8 @@ def test_modelithics_inductor_family_list_add_family(self): assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor def test_modelithics_inductor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_inductor_remove_family(second_modelithics_inductor) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS @@ -135,7 +142,8 @@ def test_modelithics_inductor_family_list_remove_family(self): assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 1 def test_modelithics_capacitor_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -143,7 +151,8 @@ def test_modelithics_capacitor_list_count(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 143 def test_modelithics_capacitor_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -155,7 +164,8 @@ def test_modelithics_capacitor_list(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_list(0) == first_modelithics_capacitor def test_modelithics_capacitor_selection(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -167,7 +177,8 @@ def test_modelithics_capacitor_selection(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_selection == first_modelithics_capacitor def test_modelithics_capacitor_family_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -179,7 +190,8 @@ def test_modelithics_capacitor_family_list_count(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 2 def test_modelithics_capacitor_family_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -193,7 +205,8 @@ def test_modelithics_capacitor_family_list(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor def test_modelithics_capacitor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -207,7 +220,8 @@ def test_modelithics_capacitor_family_list_add_family(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor def test_modelithics_capacitor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -222,7 +236,8 @@ def test_modelithics_capacitor_family_list_remove_family(self): assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 1 def test_modelithics_resistor_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -230,7 +245,8 @@ def test_modelithics_resistor_list_count(self): assert lumpdesign.export_to_aedt.modelithics_resistor_list_count == 39 def test_modelithics_resistor_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -242,7 +258,8 @@ def test_modelithics_resistor_list(self): assert lumpdesign.export_to_aedt.modelithics_resistor_list(0) == first_modelithics_resistor def test_modelithics_resistor_selection(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_selection assert info.value.args[0] == "The part library is not set to Modelithics" @@ -254,7 +271,8 @@ def test_modelithics_resistor_selection(self): assert lumpdesign.export_to_aedt.modelithics_resistor_selection == first_modelithics_resistor def test_modelithics_resistor_family_list_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" @@ -266,7 +284,8 @@ def test_modelithics_resistor_family_list_count(self): assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 2 def test_modelithics_resistor_family_list(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -280,7 +299,8 @@ def test_modelithics_resistor_family_list(self): assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor def test_modelithics_resistor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -294,7 +314,8 @@ def test_modelithics_resistor_family_list_add_family(self): assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor def test_modelithics_resistor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" @@ -309,108 +330,126 @@ def test_modelithics_resistor_family_list_remove_family(self): assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 1 def test_schematic_name(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.schematic_name = "my_schematic" assert lumpdesign.export_to_aedt.schematic_name == "my_schematic" def test_simulate_after_export_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.simulate_after_export_enabled == False lumpdesign.export_to_aedt.simulate_after_export_enabled = True assert lumpdesign.export_to_aedt.simulate_after_export_enabled == True def test_include_group_delay_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_group_delay_enabled == False lumpdesign.export_to_aedt.include_group_delay_enabled = True assert lumpdesign.export_to_aedt.include_group_delay_enabled == True def test_include_gt_gain_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_gt_gain_enabled == False lumpdesign.export_to_aedt.include_gt_gain_enabled = True assert lumpdesign.export_to_aedt.include_gt_gain_enabled == True def test_include_vgsl_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_vgsl_enabled == False lumpdesign.export_to_aedt.include_vgsl_enabled = True assert lumpdesign.export_to_aedt.include_vgsl_enabled == True def test_include_vgin_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_vgin_enabled == False lumpdesign.export_to_aedt.include_vgin_enabled = True assert lumpdesign.export_to_aedt.include_vgin_enabled == True def test_include_input_return_loss_s11_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == True lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled = False assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == False def test_include_forward_transfer_s21_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == True lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled = False assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == False def test_include_reverse_transfer_s12_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == False lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled = True assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == True def test_include_output_return_loss_s22_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == False lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled = True assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == True def test_db_format_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.db_format_enabled == True lumpdesign.export_to_aedt.db_format_enabled = False assert lumpdesign.export_to_aedt.db_format_enabled == False def test_rectangular_plot_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.rectangular_plot_enabled == True lumpdesign.export_to_aedt.rectangular_plot_enabled = False assert lumpdesign.export_to_aedt.rectangular_plot_enabled == False def test_smith_plot_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.smith_plot_enabled == False lumpdesign.export_to_aedt.smith_plot_enabled = True assert lumpdesign.export_to_aedt.smith_plot_enabled == True def test_polar_plot_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.polar_plot_enabled == False lumpdesign.export_to_aedt.polar_plot_enabled = True assert lumpdesign.export_to_aedt.polar_plot_enabled == True def test_table_data_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.table_data_enabled == False lumpdesign.export_to_aedt.table_data_enabled = True assert lumpdesign.export_to_aedt.table_data_enabled == True def test_optimitrics_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.optimitrics_enabled == True lumpdesign.export_to_aedt.optimitrics_enabled = False assert lumpdesign.export_to_aedt.optimitrics_enabled == False def test_optimize_after_export_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.optimize_after_export_enabled == False lumpdesign.export_to_aedt.optimize_after_export_enabled = True assert lumpdesign.export_to_aedt.optimize_after_export_enabled == True def test_load_library_parts_config(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA @@ -420,7 +459,8 @@ def test_load_library_parts_config(self): assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA def test_save_library_parts_config(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS lumpdesign.export_to_aedt.substrate_er = "2.25" lumpdesign.export_to_aedt.substrate_resistivity = "4.2E+07 " @@ -437,115 +477,133 @@ def test_save_library_parts_config(self): assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.065 " def test_import_tuned_variables(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.simulate_after_export_enabled = True lumpdesign.export_to_aedt.optimize_after_export_enabled = True lumpdesign.export_to_aedt.export_design() assert lumpdesign.export_to_aedt.import_tuned_variables().splitlines() == read_resource_file( - "imported_netlist.ckt" + "imported_netlist.ckt", "Lumped" ) def test_part_libraries(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.LUMPED assert len(PartLibraries) == 3 lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS def test_interconnect_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "3" def test_interconnect_minimum_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" def test_interconnect_maximum_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" def test_interconnect_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" def test_interconnect_minimum_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" def test_interconnect_maximum_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" def test_interconnect_length_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_length_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_length_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_length_value == "3 mm" def test_interconnect_minimum_length_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" def test_interconnect_maximum_length_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" lumpdesign.export_to_aedt.interconnect_maximum_length_value = "6 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "6 mm" def test_interconnect_line_width_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_line_width_value == "1.27 mm" lumpdesign.export_to_aedt.interconnect_line_width_value = "2 mm" assert lumpdesign.export_to_aedt.interconnect_line_width_value == "2 mm" def test_interconnect_minimum_width_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "635 um" lumpdesign.export_to_aedt.interconnect_minimum_width_value = "725 um" assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "725 um" def test_interconnect_maximum_width_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" lumpdesign.export_to_aedt.interconnect_maximum_width_value = "3 mm" assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "3 mm" def test_interconnect_inductor_tolerance_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value = "10" assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "10" def test_interconnect_capacitor_tolerance_value(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "1" lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value = "10" assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "10" def test_interconnect_geometry_optimization_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == True lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled = False assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == False def test_substrate_type(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP assert len(SubstrateType) == 5 for substrate in SubstrateType: @@ -553,7 +611,8 @@ def test_substrate_type(self): assert lumpdesign.export_to_aedt.substrate_type == substrate def test_substrate_er(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for er in SubstrateEr: @@ -563,7 +622,8 @@ def test_substrate_er(self): assert lumpdesign.export_to_aedt.substrate_er == "3.2" def test_substrate_resistivity(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD assert len(SubstrateResistivity) == 11 for resistivity in SubstrateResistivity: @@ -573,7 +633,8 @@ def test_substrate_resistivity(self): assert lumpdesign.export_to_aedt.substrate_resistivity == "0.02" def test_substrate_loss_tangent(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for loss in SubstrateEr: @@ -583,19 +644,22 @@ def test_substrate_loss_tangent(self): assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.0002" def test_substrate_conductor_thickness(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" lumpdesign.export_to_aedt.substrate_conductor_thickness = "1.25 um" assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "1.25 um" def test_substrate_dielectric_height(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_dielectric_height = "1.22 mm" assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.22 mm" def test_substrate_unbalanced_lower_dielectric_height(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" @@ -603,28 +667,32 @@ def test_substrate_unbalanced_lower_dielectric_height(self): assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "5.2 mm" def test_substrate_suspend_dielectric_height(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.substrate_type = SubstrateType.SUSPEND assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" lumpdesign.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "3.2 mm" def test_substrate_cover_height(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height == "6.35 mm" lumpdesign.export_to_aedt.substrate_cover_height = "2.5 mm" assert lumpdesign.export_to_aedt.substrate_cover_height == "2.5 mm" def test_substrate_unbalanced_stripline_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == False lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == True def test_substrate_cover_height_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == False lumpdesign.export_to_aedt.substrate_cover_height_enabled = True assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == True diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py index 902f18a3753..c87ac3fc32a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.optimization_goals_table import OptimizationGoalParameter from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -36,13 +36,15 @@ class TestClass: def test_row_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() assert lumpdesign.optimization_goals_table.row_count == 2 def test_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() assert lumpdesign.optimization_goals_table.row(0) == [ @@ -70,7 +72,8 @@ def test_row(self): assert lumpdesign.optimization_goals_table.row(1)[OptimizationGoalParameter.WEIGHT.value] == "0.5" def test_update_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.update_row( @@ -87,7 +90,8 @@ def test_update_row(self): ] def test_append_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.append_row("100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y") @@ -102,7 +106,8 @@ def test_append_row(self): ] def test_insert_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.insert_row( @@ -119,7 +124,8 @@ def test_insert_row(self): ] def test_remove_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.remove_row(1) @@ -135,7 +141,8 @@ def test_remove_row(self): ] def test_adjust_goal_frequency(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.export_to_aedt._open_aedt_export() lumpdesign.optimization_goals_table.restore_design_goals() lumpdesign.optimization_goals_table.adjust_goal_frequency("150 MHz") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py index 066fa910254..4e418e851c6 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -37,57 +37,81 @@ class TestClass: def test_lumped_c_node_capacitor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.c_node_capacitor == "0" lumpdesign.leads_and_nodes.c_node_capacitor = "1n" assert lumpdesign.leads_and_nodes.c_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("c_node_capacitor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "c_node_capacitor.ckt", "Lumped" + ) def test_lumped_c_lead_inductor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.c_lead_inductor == "0" lumpdesign.leads_and_nodes.c_lead_inductor = "1n" assert lumpdesign.leads_and_nodes.c_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("c_lead_inductor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "c_lead_inductor.ckt", "Lumped" + ) def test_lumped_l_node_capacitor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.l_node_capacitor == "0" lumpdesign.leads_and_nodes.l_node_capacitor = "1n" assert lumpdesign.leads_and_nodes.l_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("l_node_capacitor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "l_node_capacitor.ckt", "Lumped" + ) def test_lumped_l_lead_inductor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.l_lead_inductor == "0" lumpdesign.leads_and_nodes.l_lead_inductor = "1n" assert lumpdesign.leads_and_nodes.l_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("l_lead_inductor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "l_lead_inductor.ckt", "Lumped" + ) def test_lumped_r_node_capacitor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.r_node_capacitor == "0" lumpdesign.leads_and_nodes.r_node_capacitor = "1n" assert lumpdesign.leads_and_nodes.r_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("r_node_capacitor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "r_node_capacitor.ckt", "Lumped" + ) def test_lumped_r_lead_inductor(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.r_lead_inductor == "0" lumpdesign.leads_and_nodes.r_lead_inductor = "1n" assert lumpdesign.leads_and_nodes.r_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("r_lead_inductor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "r_lead_inductor.ckt", "Lumped" + ) def test_lumped_c_node_compensate(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.c_node_compensate is False lumpdesign.leads_and_nodes.c_node_compensate = True assert lumpdesign.leads_and_nodes.c_node_compensate - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("c_node_compensate.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "c_node_compensate.ckt", "Lumped" + ) def test_lumped_l_node_compensate(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.leads_and_nodes.l_node_compensate is False lumpdesign.leads_and_nodes.l_node_compensate = True assert lumpdesign.leads_and_nodes.l_node_compensate - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("l_node_compensate.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "l_node_compensate.ckt", "Lumped" + ) diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py index f0d455c6c69..e9b8aae2ba6 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -37,57 +37,65 @@ class TestClass: def test_lumped_capacitor_q(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.capacitor_q == "Inf" lumpdesign.parasitics.capacitor_q = "100" assert lumpdesign.parasitics.capacitor_q == "100" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_q.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_q.ckt", "Lumped") def test_lumped_capacitor_rs(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.capacitor_rs == "0" lumpdesign.parasitics.capacitor_rs = "1" assert lumpdesign.parasitics.capacitor_rs == "1" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rs.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rs.ckt", "Lumped") def test_lumped_capacitor_rp(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.capacitor_rp == "Inf" lumpdesign.parasitics.capacitor_rp = "1000" assert lumpdesign.parasitics.capacitor_rp == "1000" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rp.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rp.ckt", "Lumped") def test_lumped_capacitor_ls(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.capacitor_ls == "0" lumpdesign.parasitics.capacitor_ls = "1n" assert lumpdesign.parasitics.capacitor_ls == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_ls.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_ls.ckt", "Lumped") def test_lumped_inductor_q(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.inductor_q == "Inf" lumpdesign.parasitics.inductor_q = "100" assert lumpdesign.parasitics.inductor_q == "100" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_q.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_q.ckt", "Lumped") def test_lumped_inductor_rs(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.inductor_rs == "0" lumpdesign.parasitics.inductor_rs = "1" assert lumpdesign.parasitics.inductor_rs == "1" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rs.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rs.ckt", "Lumped") def test_lumped_inductor_rp(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.inductor_rp == "Inf" lumpdesign.parasitics.inductor_rp = "1000" assert lumpdesign.parasitics.inductor_rp == "1000" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rp.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rp.ckt", "Lumped") def test_lumped_inductor_cp(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.parasitics.inductor_cp == "0" lumpdesign.parasitics.inductor_cp = "1n" assert lumpdesign.parasitics.inductor_cp == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_cp.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_cp.ckt", "Lumped") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py index a8a9f4c37d0..f94d2c16547 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.lumped_termination_impedance_table import ComplexReactanceType from ansys.aedt.core.filtersolutions_core.lumped_termination_impedance_table import ComplexTerminationDefinition from ansys.aedt.core.generic.general_methods import is_linux @@ -36,19 +36,22 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_row_count(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert lumpdesign.source_impedance_table.row_count == 3 assert lumpdesign.load_impedance_table.row_count == 3 def test_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert lumpdesign.source_impedance_table.row(0) == ("0.100G", "1.000", "0.000") assert lumpdesign.load_impedance_table.row(0) == ("0.100G", "1.000", "0.000") def test_update_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True with pytest.raises(RuntimeError) as info: lumpdesign.source_impedance_table.update_row(0) @@ -70,7 +73,8 @@ def test_update_row(self): assert lumpdesign.load_impedance_table.row(0) == ("2G", "50", "0") def test_append_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True lumpdesign.source_impedance_table.append_row("100M", "10", "20") assert lumpdesign.source_impedance_table.row_count == 4 @@ -81,7 +85,8 @@ def test_append_row(self): assert lumpdesign.load_impedance_table.row(3) == ("100M", "10", "20") def test_insert_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True lumpdesign.source_impedance_table.insert_row(0, "2G", "50", "0") assert lumpdesign.source_impedance_table.row(0) == ("2G", "50", "0") @@ -89,7 +94,8 @@ def test_insert_row(self): assert lumpdesign.load_impedance_table.row(0) == ("2G", "50", "0") def test_remove_row(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True lumpdesign.source_impedance_table.remove_row(0) assert lumpdesign.source_impedance_table.row(0) == ("1.000G", "1.000", "0.000") @@ -103,7 +109,8 @@ def test_remove_row(self): assert info.value.args[0] == "No value is set for this band" def test_complex_definition(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert len(ComplexTerminationDefinition) == 4 assert lumpdesign.source_impedance_table.complex_definition == ComplexTerminationDefinition.CARTESIAN @@ -116,7 +123,8 @@ def test_complex_definition(self): assert lumpdesign.load_impedance_table.complex_definition == cdef def test_reactance_type(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert len(ComplexReactanceType) == 3 assert lumpdesign.source_impedance_table.reactance_type == ComplexReactanceType.REAC @@ -129,7 +137,8 @@ def test_reactance_type(self): assert lumpdesign.load_impedance_table.reactance_type == creac def test_compensation_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert lumpdesign.source_impedance_table.compensation_enabled is False lumpdesign.source_impedance_table.compensation_enabled = True @@ -139,7 +148,8 @@ def test_compensation_enabled(self): assert lumpdesign.load_impedance_table.compensation_enabled def test_compensation_order(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True lumpdesign.source_impedance_table.compensation_enabled = True assert lumpdesign.source_impedance_table.compensation_order == 2 diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py index 24d9dd32a68..9e9a7596aec 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py @@ -23,9 +23,9 @@ # SOFTWARE. import ansys.aedt.core +import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import DiplexerType from ansys.aedt.core.filtersolutions_core.attributes import FilterClass -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation from ansys.aedt.core.filtersolutions_core.attributes import FilterType from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -39,50 +39,59 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_lumped_generator_resistor_30(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.generator_resistor == "50" lumpdesign.topology.generator_resistor = "30" assert lumpdesign.topology.generator_resistor == "30" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("generator_resistor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "generator_resistor.ckt", "Lumped" + ) def test_lumped_load_resistor_30(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.load_resistor == "50" lumpdesign.topology.load_resistor = "30" assert lumpdesign.topology.load_resistor == "30" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("laod_resistor.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("laod_resistor.ckt", "Lumped") def test_lumped_current_source(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.current_source is False lumpdesign.topology.current_source = True assert lumpdesign.topology.current_source def test_lumped_first_shunt(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.first_shunt lumpdesign.topology.first_shunt = True assert lumpdesign.topology.first_shunt - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_shunt.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_shunt.ckt", "Lumped") def test_lumped_first_series(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.first_shunt lumpdesign.topology.first_shunt = False assert lumpdesign.topology.first_shunt is False - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_series.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_series.ckt", "Lumped") def test_lumped_bridge_t(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_type = FilterType.ELLIPTIC assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC assert lumpdesign.topology.bridge_t is False lumpdesign.topology.bridge_t = True assert lumpdesign.topology.bridge_t - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t.ckt", "Lumped") def test_lumped_bridge_t_low(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO @@ -92,10 +101,11 @@ def test_lumped_bridge_t_low(self): assert lumpdesign.topology.bridge_t_low is False lumpdesign.topology.bridge_t_low = True assert lumpdesign.topology.bridge_t_low - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_low.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_low.ckt", "Lumped") def test_lumped_bridge_t_high(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO @@ -105,19 +115,23 @@ def test_lumped_bridge_t_high(self): assert lumpdesign.topology.bridge_t_high is False lumpdesign.topology.bridge_t_high = True assert lumpdesign.topology.bridge_t_high - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_high.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_high.ckt", "Lumped") def test_lumped_equal_inductors(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS assert lumpdesign.topology.equal_inductors is False lumpdesign.topology.equal_inductors = True assert lumpdesign.topology.equal_inductors - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("equal_inductors.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "equal_inductors.ckt", "Lumped" + ) def test_lumped_equal_capacitors(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC lumpdesign.topology.zig_zag = True @@ -130,28 +144,33 @@ def test_lumped_equal_capacitors(self): lumpdesign.topology.equal_capacitors = True assert lumpdesign.topology.min_cap assert lumpdesign.topology.equal_capacitors - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("equal_capacitors.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "equal_capacitors.ckt", "Lumped" + ) def test_lumped_equal_legs(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS assert lumpdesign.topology.equal_legs is False lumpdesign.topology.equal_legs = True assert lumpdesign.topology.equal_legs - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("equal_legs.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("equal_legs.ckt", "Lumped") def test_lumped_high_low_pass(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS assert lumpdesign.topology.high_low_pass is False lumpdesign.topology.high_low_pass = True assert lumpdesign.topology.high_low_pass - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("high_low_pass.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("high_low_pass.ckt", "Lumped") def test_lumped_high_low_pass_min_ind(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS @@ -159,10 +178,13 @@ def test_lumped_high_low_pass_min_ind(self): assert lumpdesign.topology.high_low_pass_min_ind is False lumpdesign.topology.high_low_pass_min_ind = True assert lumpdesign.topology.high_low_pass_min_ind - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("high_low_pass_min_ind.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "high_low_pass_min_ind.ckt", "Lumped" + ) def test_lumped_zig_zag(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS @@ -170,10 +192,11 @@ def test_lumped_zig_zag(self): assert lumpdesign.topology.zig_zag is False lumpdesign.topology.zig_zag = True assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("zig_zag.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("zig_zag.ckt", "Lumped") def test_lumped_min_ind(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC lumpdesign.topology.zig_zag = True @@ -183,10 +206,11 @@ def test_lumped_min_ind(self): assert lumpdesign.topology.min_ind lumpdesign.topology.min_ind = True assert lumpdesign.topology.min_ind - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_ind.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_ind.ckt", "Lumped") def test_lumped_min_cap(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC lumpdesign.topology.zig_zag = True @@ -196,10 +220,11 @@ def test_lumped_min_cap(self): assert lumpdesign.topology.min_cap is False lumpdesign.topology.min_cap = True assert lumpdesign.topology.min_cap - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_cap.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_cap.ckt", "Lumped") def test_lumped_set_source_res(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC lumpdesign.topology.zig_zag = True @@ -210,10 +235,11 @@ def test_lumped_set_source_res(self): assert lumpdesign.topology.zig_zag lumpdesign.topology.set_source_res = True assert lumpdesign.topology.set_source_res - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("set_source_res.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("set_source_res.ckt", "Lumped") def test_lumped_trap_topology(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC lumpdesign.topology.zig_zag = True @@ -223,10 +249,11 @@ def test_lumped_trap_topology(self): assert lumpdesign.topology.trap_topology is False lumpdesign.topology.trap_topology = True assert lumpdesign.topology.trap_topology - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("trap_topology.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("trap_topology.ckt", "Lumped") def test_lumped_node_cap_ground(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.attributes.filter_type = FilterType.ELLIPTIC assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS @@ -234,10 +261,13 @@ def test_lumped_node_cap_ground(self): assert lumpdesign.topology.node_cap_ground is False lumpdesign.topology.node_cap_ground = True assert lumpdesign.topology.node_cap_ground - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("node_cap_ground.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "node_cap_ground.ckt", "Lumped" + ) def test_lumped_match_impedance(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.BAND_PASS lumpdesign.topology.generator_resistor = "75" assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS @@ -245,69 +275,88 @@ def test_lumped_match_impedance(self): assert lumpdesign.topology.match_impedance is False lumpdesign.topology.match_impedance = True assert lumpdesign.topology.match_impedance - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("match_impedance.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "match_impedance.ckt", "Lumped" + ) def test_lumped_complex_termination(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumpdesign.topology.complex_termination is False lumpdesign.topology.complex_termination = True assert lumpdesign.topology.complex_termination def test_complex_element_tune_enabled(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.topology.complex_termination = True assert lumpdesign.topology.complex_element_tune_enabled lumpdesign.topology.complex_element_tune_enabled = False assert lumpdesign.topology.complex_element_tune_enabled is False def test_lumped_circuit_export(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("netlist.ckt") + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("netlist.ckt", "Lumped") def test_lumped_diplexer1_hi_lo(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 assert lumpdesign.attributes.diplexer_type == DiplexerType.HI_LO - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_hi_lo.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "diplexer1_hi_lo.ckt", "Lumped" + ) def test_lumped_diplexer1_bp_1(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 lumpdesign.attributes.diplexer_type = DiplexerType.BP_1 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_1 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_1.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_1.ckt", "Lumped") def test_lumped_diplexer1_bp_2(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 lumpdesign.attributes.diplexer_type = DiplexerType.BP_2 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_2 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_2.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_2.ckt", "Lumped") def test_lumped_diplexer2_bp_bs(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 lumpdesign.attributes.diplexer_type = DiplexerType.BP_BS assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_BS - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer2_bp_bs.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "diplexer2_bp_bs.ckt", "Lumped" + ) def test_lumped_diplexer2_triplexer_1(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 lumpdesign.attributes.diplexer_type = DiplexerType.TRIPLEXER_1 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 assert lumpdesign.attributes.diplexer_type == DiplexerType.TRIPLEXER_1 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer2_triplexer_1.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "diplexer2_triplexer_1.ckt", "Lumped" + ) def test_lumped_diplexer2_triplexer_2(self): - lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 lumpdesign.attributes.diplexer_type = DiplexerType.TRIPLEXER_2 assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 assert lumpdesign.attributes.diplexer_type == DiplexerType.TRIPLEXER_2 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer2_triplexer_2.ckt") + assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + "diplexer2_triplexer_2.ckt", "Lumped" + ) diff --git a/tests/system/general/test_45_FilterSolutions/test_raise_error.py b/tests/system/general/test_45_FilterSolutions/test_raise_error.py index 8fc957e7f21..3d91b5a8ba3 100644 --- a/tests/system/general/test_45_FilterSolutions/test_raise_error.py +++ b/tests/system/general/test_45_FilterSolutions/test_raise_error.py @@ -23,7 +23,7 @@ # SOFTWARE. import ansys.aedt.core -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation +import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -35,7 +35,8 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: def test_raise_error(self): - design = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED) + design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + with pytest.raises(RuntimeError) as info: design.transmission_zeros_ratio.row(0) assert info.value.args[0] == test_transmission_zeros.TestClass.no_transmission_zero_msg From da0174d989d65e35d22ef56d3f14904b23b903b2 Mon Sep 17 00:00:00 2001 From: raghajaf Date: Sat, 28 Dec 2024 18:07:52 -0500 Subject: [PATCH 2/6] FAET: Filter implementation is removed --- .../core/filtersolutions_core/attributes.py | 40 ------------------- .../filtersolutions_core/dll_interface.py | 11 ++++- .../filtersolutions_core/lumped_topology.py | 6 +++ src/ansys/aedt/core/generic/design_types.py | 5 +-- .../test_filter/test_attributes.py | 19 ++------- 5 files changed, 19 insertions(+), 62 deletions(-) diff --git a/src/ansys/aedt/core/filtersolutions_core/attributes.py b/src/ansys/aedt/core/filtersolutions_core/attributes.py index a61dee7d06b..1cf14ee7183 100644 --- a/src/ansys/aedt/core/filtersolutions_core/attributes.py +++ b/src/ansys/aedt/core/filtersolutions_core/attributes.py @@ -97,25 +97,6 @@ class FilterClass(Enum): STOP_STOP = 9 -class FilterImplementation(Enum): - """Provides an enum of filter implementation types. - - **Attributes:** - - - LUMPED: Represents a lumped implementation. - - DISTRIB: Represents a distributed implementation. - - ACTIVE: Represents an active implementation. - - SWCAP: Represents a switched capacitor implementation. - - DIGITAL: Represents a digital implementation. - """ - - LUMPED = 0 - DISTRIBUTED = 1 - ACTIVE = 2 - SWCAP = 3 - DIGITAL = 4 - - class DiplexerType(Enum): """Provides an enum of diplexer and triplexer types. @@ -650,27 +631,6 @@ def filter_class(self, filter_class: FilterClass): string_value = self._dll_interface.enum_to_string(filter_class) self._dll_interface.set_string(self._dll.setFilterClass, string_value) - @property - def filter_implementation(self) -> FilterImplementation: - """Technology for implementing the filter. The default is ``LUMPED``. - The ``FilterImplementation`` enum provides a list of all implementations. - - Returns - ------- - :enum:`FilterImplementation` - """ - index = c_int() - filter_implementation = list(FilterImplementation) - status = self._dll.getFilterImplementation(byref(index)) - ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - filter_implementation = filter_implementation[index.value] - return filter_implementation - - @filter_implementation.setter - def filter_implementation(self, column: FilterImplementation): - status = self._dll.setFilterImplementation(column.value) - ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - @property def diplexer_type(self) -> DiplexerType: """Type of diplexer topology. This property is only applicable to lumped filters. diff --git a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py index 733e83a485f..1f84552c98e 100644 --- a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py +++ b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py @@ -191,6 +191,13 @@ def raise_error(self, error_status): raise RuntimeError(error_message) @property - def desktop_version(self): - """Return the version of the AEDT.""" + def desktop_version(self) -> str: + """Return the version of the AEDT. + + Returns + ------- + str + Desktop version. + """ + return self._version diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py index 1df310d3924..bfdcf7b9a50 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py @@ -41,6 +41,7 @@ def __init__(self): self._dll = ansys.aedt.core.filtersolutions_core._dll_interface()._dll self._dll_interface = ansys.aedt.core.filtersolutions_core._dll_interface() self._define_topology_dll_functions() + self._set_lump_implementation() def _define_topology_dll_functions(self): """Define C++ API DLL functions.""" @@ -154,6 +155,11 @@ def _define_topology_dll_functions(self): self._dll.getLumpedCircuitResponse.argtypes = [c_char_p, c_int] self._dll.getLumpedCircuitResponse.restype = c_int + def _set_lump_implementation(self): + """Set ``FilterSolutions`` attributes to lump design.""" + filter_implementation_status = self._dll.setFilterImplementation(0) + ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(filter_implementation_status) + @property def generator_resistor(self) -> str: """Generator resistor. The default is ``50``. diff --git a/src/ansys/aedt/core/generic/design_types.py b/src/ansys/aedt/core/generic/design_types.py index d675ad1f158..d53338d17eb 100644 --- a/src/ansys/aedt/core/generic/design_types.py +++ b/src/ansys/aedt/core/generic/design_types.py @@ -60,9 +60,6 @@ def FilterSolutions( version : str optional Version of AEDT to use in ``xxxx.x`` format to use. The default is ``None``, in which case the active setup or latest installed version is used. - implementation_type : enum, optional - Type of filter implementation available from the ``FilterImplementation`` enum. - The default is ``None``, in which case the lumped implementation is used. Returns ------- @@ -72,7 +69,7 @@ def FilterSolutions( -------- Define a band-pass Butterworth filter with a center frequency of 1 GHz and a pass band width of 500 MHz. - design = ansys.aedt.core.FilterSolutions(version="2025.1", implementation_type= FilterImplementation.LUMPED) + design = ansys.aedt.core.LumpDesign(version="2025.1") design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.BUTTERWORTH design.attributes.pass_band_center_frequency = "1G" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py index 6f961af19a7..2ffbfa5bf66 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py @@ -27,7 +27,6 @@ from ansys.aedt.core.filtersolutions_core.attributes import BesselRipplePercentage from ansys.aedt.core.filtersolutions_core.attributes import DiplexerType from ansys.aedt.core.filtersolutions_core.attributes import FilterClass -from ansys.aedt.core.filtersolutions_core.attributes import FilterImplementation from ansys.aedt.core.filtersolutions_core.attributes import FilterType from ansys.aedt.core.filtersolutions_core.attributes import GaussianBesselReflection from ansys.aedt.core.filtersolutions_core.attributes import GaussianTransition @@ -48,14 +47,10 @@ def test_filter_type(self): design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) assert design.attributes.filter_type == FilterType.BUTTERWORTH - assert len(FilterType) == 10 - - for fimp in [FilterImplementation.LUMPED]: - design.attributes.filter_implementation = fimp - for ftype in FilterType: - design.attributes.filter_type = ftype - assert design.attributes.filter_type == ftype + for ftype in FilterType: + design.attributes.filter_type = ftype + assert design.attributes.filter_type == ftype def test_filter_class(self): design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) @@ -97,14 +92,6 @@ def test_filter_multiple_bands_high_pass_frequency(self): design.attributes.filter_multiple_bands_high_pass_frequency = "500M" assert design.attributes.filter_multiple_bands_high_pass_frequency == "500M" - def test_filter_implementation(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert len(FilterImplementation) == 5 - for fimplementation in FilterImplementation: - design.attributes.filter_implementation = fimplementation - assert design.attributes.filter_implementation == fimplementation - def test_diplexer_type(self): design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) From c3676da11cb3046ed2b5ad577cfa63f82038ce6a Mon Sep 17 00:00:00 2001 From: "pre-commit-ci[bot]" <66853113+pre-commit-ci[bot]@users.noreply.github.com> Date: Thu, 2 Jan 2025 12:22:51 +0000 Subject: [PATCH 3/6] CHORE: Auto fixes from pre-commit.com hooks For more information, see https://pre-commit.ci --- LICENSE | 2 +- src/ansys/aedt/core/__init__.py | 2 +- src/ansys/aedt/core/aedt_logger.py | 2 +- src/ansys/aedt/core/application/__init__.py | 2 +- src/ansys/aedt/core/application/aedt_file_management.py | 2 +- src/ansys/aedt/core/application/aedt_objects.py | 2 +- src/ansys/aedt/core/application/analysis.py | 2 +- src/ansys/aedt/core/application/analysis_3d.py | 2 +- src/ansys/aedt/core/application/analysis_3d_layout.py | 2 +- src/ansys/aedt/core/application/analysis_circuit_netlist.py | 2 +- src/ansys/aedt/core/application/analysis_hf.py | 2 +- src/ansys/aedt/core/application/analysis_icepak.py | 2 +- src/ansys/aedt/core/application/analysis_maxwell_circuit.py | 2 +- src/ansys/aedt/core/application/analysis_nexxim.py | 2 +- src/ansys/aedt/core/application/analysis_r_m_xprt.py | 2 +- src/ansys/aedt/core/application/analysis_twin_builder.py | 2 +- src/ansys/aedt/core/application/design.py | 2 +- src/ansys/aedt/core/application/design_solutions.py | 2 +- src/ansys/aedt/core/application/job_manager.py | 2 +- src/ansys/aedt/core/application/variables.py | 2 +- src/ansys/aedt/core/circuit.py | 2 +- src/ansys/aedt/core/circuit_netlist.py | 2 +- src/ansys/aedt/core/common_rpc.py | 2 +- src/ansys/aedt/core/desktop.py | 2 +- src/ansys/aedt/core/downloads.py | 2 +- src/ansys/aedt/core/edb.py | 2 +- src/ansys/aedt/core/emit.py | 2 +- src/ansys/aedt/core/emit_core/__init__.py | 2 +- src/ansys/aedt/core/emit_core/couplings.py | 2 +- src/ansys/aedt/core/emit_core/emit_constants.py | 2 +- src/ansys/aedt/core/emit_core/results/__init__.py | 2 +- src/ansys/aedt/core/emit_core/results/results.py | 2 +- src/ansys/aedt/core/emit_core/results/revision.py | 2 +- src/ansys/aedt/core/filtersolutions.py | 2 +- src/ansys/aedt/core/filtersolutions_core/__init__.py | 2 +- src/ansys/aedt/core/filtersolutions_core/attributes.py | 2 +- .../aedt/core/filtersolutions_core/distributed_topology.py | 2 +- src/ansys/aedt/core/filtersolutions_core/dll_interface.py | 2 +- src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py | 2 +- src/ansys/aedt/core/filtersolutions_core/graph_setup.py | 2 +- src/ansys/aedt/core/filtersolutions_core/ideal_response.py | 2 +- .../aedt/core/filtersolutions_core/lumped_nodes_and_leads.py | 2 +- src/ansys/aedt/core/filtersolutions_core/lumped_parasitics.py | 2 +- .../filtersolutions_core/lumped_termination_impedance_table.py | 2 +- src/ansys/aedt/core/filtersolutions_core/lumped_topology.py | 2 +- .../aedt/core/filtersolutions_core/multiple_bands_table.py | 2 +- .../aedt/core/filtersolutions_core/optimization_goals_table.py | 2 +- src/ansys/aedt/core/filtersolutions_core/transmission_zeros.py | 2 +- src/ansys/aedt/core/generic/__init__.py | 2 +- src/ansys/aedt/core/generic/aedt_versions.py | 2 +- src/ansys/aedt/core/generic/clr_module.py | 2 +- src/ansys/aedt/core/generic/configurations.py | 2 +- src/ansys/aedt/core/generic/constants.py | 2 +- src/ansys/aedt/core/generic/data_handlers.py | 2 +- src/ansys/aedt/core/generic/design_types.py | 2 +- src/ansys/aedt/core/generic/desktop_sessions.py | 2 +- src/ansys/aedt/core/generic/filesystem.py | 2 +- src/ansys/aedt/core/generic/general_methods.py | 2 +- src/ansys/aedt/core/generic/grpc_plugin_dll_class.py | 2 +- src/ansys/aedt/core/generic/ibis_reader.py | 2 +- src/ansys/aedt/core/generic/load_aedt_file.py | 2 +- src/ansys/aedt/core/generic/python_optimizers.py | 2 +- src/ansys/aedt/core/generic/settings.py | 2 +- src/ansys/aedt/core/hfss.py | 2 +- src/ansys/aedt/core/hfss3dlayout.py | 2 +- src/ansys/aedt/core/icepak.py | 2 +- src/ansys/aedt/core/maxwell.py | 2 +- src/ansys/aedt/core/maxwellcircuit.py | 2 +- src/ansys/aedt/core/mechanical.py | 2 +- src/ansys/aedt/core/misc/__init__.py | 2 +- src/ansys/aedt/core/misc/create_remote_dir.py | 2 +- src/ansys/aedt/core/modeler/__init__.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/__init__.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/actors.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/multiparts.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/oms.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/parts.py | 2 +- src/ansys/aedt/core/modeler/advanced_cad/stackup_3d.py | 2 +- src/ansys/aedt/core/modeler/cad/__init__.py | 2 +- src/ansys/aedt/core/modeler/cad/component_array.py | 2 +- src/ansys/aedt/core/modeler/cad/components_3d.py | 2 +- src/ansys/aedt/core/modeler/cad/elements_3d.py | 2 +- src/ansys/aedt/core/modeler/cad/modeler.py | 2 +- src/ansys/aedt/core/modeler/cad/object_3d.py | 2 +- src/ansys/aedt/core/modeler/cad/polylines.py | 2 +- src/ansys/aedt/core/modeler/cad/primitives.py | 2 +- src/ansys/aedt/core/modeler/cad/primitives_2d.py | 2 +- src/ansys/aedt/core/modeler/cad/primitives_3d.py | 2 +- src/ansys/aedt/core/modeler/calculators.py | 2 +- src/ansys/aedt/core/modeler/circuits/__init__.py | 2 +- src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py | 2 +- src/ansys/aedt/core/modeler/circuits/primitives_circuit.py | 2 +- src/ansys/aedt/core/modeler/circuits/primitives_emit.py | 2 +- .../aedt/core/modeler/circuits/primitives_maxwell_circuit.py | 2 +- src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py | 2 +- src/ansys/aedt/core/modeler/circuits/primitives_twin_builder.py | 2 +- src/ansys/aedt/core/modeler/geometry_operators.py | 2 +- src/ansys/aedt/core/modeler/modeler_2d.py | 2 +- src/ansys/aedt/core/modeler/modeler_3d.py | 2 +- src/ansys/aedt/core/modeler/modeler_pcb.py | 2 +- src/ansys/aedt/core/modeler/pcb/__init__.py | 2 +- src/ansys/aedt/core/modeler/pcb/object_3d_layout.py | 2 +- src/ansys/aedt/core/modeler/pcb/primitives_3d_layout.py | 2 +- src/ansys/aedt/core/modeler/schematic.py | 2 +- src/ansys/aedt/core/modules/__init__.py | 2 +- src/ansys/aedt/core/modules/boundary/__init__.py | 2 +- src/ansys/aedt/core/modules/boundary/circuit_boundary.py | 2 +- src/ansys/aedt/core/modules/boundary/common.py | 2 +- src/ansys/aedt/core/modules/boundary/hfss_boundary.py | 2 +- src/ansys/aedt/core/modules/boundary/icepak_boundary.py | 2 +- src/ansys/aedt/core/modules/boundary/layout_boundary.py | 2 +- src/ansys/aedt/core/modules/boundary/maxwell_boundary.py | 2 +- src/ansys/aedt/core/modules/boundary/q3d_boundary.py | 2 +- src/ansys/aedt/core/modules/cable_modeling.py | 2 +- src/ansys/aedt/core/modules/circuit_templates.py | 2 +- src/ansys/aedt/core/modules/design_xploration.py | 2 +- src/ansys/aedt/core/modules/layer_stackup.py | 2 +- src/ansys/aedt/core/modules/material.py | 2 +- src/ansys/aedt/core/modules/material_lib.py | 2 +- src/ansys/aedt/core/modules/material_workbench.py | 2 +- src/ansys/aedt/core/modules/mesh.py | 2 +- src/ansys/aedt/core/modules/mesh_3d_layout.py | 2 +- src/ansys/aedt/core/modules/mesh_icepak.py | 2 +- src/ansys/aedt/core/modules/optimetrics_templates.py | 2 +- src/ansys/aedt/core/modules/setup_templates.py | 2 +- src/ansys/aedt/core/modules/solve_setup.py | 2 +- src/ansys/aedt/core/modules/solve_sweeps.py | 2 +- src/ansys/aedt/core/q3d.py | 2 +- src/ansys/aedt/core/rmxprt.py | 2 +- src/ansys/aedt/core/twinbuilder.py | 2 +- src/ansys/aedt/core/visualization/__init__.py | 2 +- src/ansys/aedt/core/visualization/advanced/__init__.py | 2 +- .../aedt/core/visualization/advanced/farfield_visualization.py | 2 +- src/ansys/aedt/core/visualization/advanced/hdm_plot.py | 2 +- src/ansys/aedt/core/visualization/advanced/misc.py | 2 +- src/ansys/aedt/core/visualization/advanced/rcs_visualization.py | 2 +- src/ansys/aedt/core/visualization/advanced/sbrplus/__init__.py | 2 +- .../aedt/core/visualization/advanced/sbrplus/hdm_parser.py | 2 +- src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_utils.py | 2 +- src/ansys/aedt/core/visualization/advanced/touchstone_parser.py | 2 +- src/ansys/aedt/core/visualization/plot/__init__.py | 2 +- src/ansys/aedt/core/visualization/plot/matplotlib.py | 2 +- src/ansys/aedt/core/visualization/plot/pdf.py | 2 +- src/ansys/aedt/core/visualization/plot/pyvista.py | 2 +- src/ansys/aedt/core/visualization/post/__init__.py | 2 +- src/ansys/aedt/core/visualization/post/common.py | 2 +- src/ansys/aedt/core/visualization/post/compliance.py | 2 +- src/ansys/aedt/core/visualization/post/farfield_exporter.py | 2 +- src/ansys/aedt/core/visualization/post/field_data.py | 2 +- src/ansys/aedt/core/visualization/post/field_summary.py | 2 +- src/ansys/aedt/core/visualization/post/fields_calculator.py | 2 +- src/ansys/aedt/core/visualization/post/monitor_icepak.py | 2 +- src/ansys/aedt/core/visualization/post/post_3dlayout.py | 2 +- src/ansys/aedt/core/visualization/post/post_circuit.py | 2 +- src/ansys/aedt/core/visualization/post/post_common_3d.py | 2 +- src/ansys/aedt/core/visualization/post/post_icepak.py | 2 +- src/ansys/aedt/core/visualization/post/rcs_exporter.py | 2 +- src/ansys/aedt/core/visualization/post/solution_data.py | 2 +- src/ansys/aedt/core/visualization/post/spisim.py | 2 +- .../post/spisim_com_configuration_files/__init__.py | 2 +- .../post/spisim_com_configuration_files/com_parameters.py | 2 +- .../post/spisim_com_configuration_files/com_settings_mapping.py | 2 +- src/ansys/aedt/core/visualization/post/vrt_data.py | 2 +- src/ansys/aedt/core/visualization/report/__init__.py | 2 +- src/ansys/aedt/core/visualization/report/common.py | 2 +- src/ansys/aedt/core/visualization/report/constants.py | 2 +- src/ansys/aedt/core/visualization/report/emi.py | 2 +- src/ansys/aedt/core/visualization/report/eye.py | 2 +- src/ansys/aedt/core/visualization/report/field.py | 2 +- src/ansys/aedt/core/visualization/report/standard.py | 2 +- src/ansys/aedt/core/workflows/__init__.py | 2 +- src/ansys/aedt/core/workflows/circuit/__init__.py | 2 +- src/ansys/aedt/core/workflows/circuit/import_schematic.py | 2 +- src/ansys/aedt/core/workflows/customize_automation_tab.py | 2 +- src/ansys/aedt/core/workflows/emit/__init__.py | 2 +- src/ansys/aedt/core/workflows/hfss/__init__.py | 2 +- src/ansys/aedt/core/workflows/hfss/choke_designer.py | 2 +- src/ansys/aedt/core/workflows/hfss/push_excitation_from_file.py | 2 +- src/ansys/aedt/core/workflows/hfss3dlayout/__init__.py | 2 +- src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py | 2 +- src/ansys/aedt/core/workflows/hfss3dlayout/export_layout.py | 2 +- src/ansys/aedt/core/workflows/hfss3dlayout/export_to_3d.py | 2 +- .../workflows/hfss3dlayout/generate_arbitrary_wave_ports.py | 2 +- src/ansys/aedt/core/workflows/hfss3dlayout/parametrize_edb.py | 2 +- .../workflows/hfss3dlayout/push_excitation_from_file_3dl.py | 2 +- src/ansys/aedt/core/workflows/icepak/__init__.py | 2 +- src/ansys/aedt/core/workflows/icepak/power_map_from_csv.py | 2 +- src/ansys/aedt/core/workflows/maxwell2d/__init__.py | 2 +- src/ansys/aedt/core/workflows/maxwell3d/__init__.py | 2 +- src/ansys/aedt/core/workflows/mechanical/__init__.py | 2 +- src/ansys/aedt/core/workflows/misc.py | 2 +- src/ansys/aedt/core/workflows/project/__init__.py | 2 +- .../aedt/core/workflows/project/advanced_fields_calculator.py | 2 +- src/ansys/aedt/core/workflows/project/configure_edb.py | 2 +- src/ansys/aedt/core/workflows/project/create_report.py | 2 +- src/ansys/aedt/core/workflows/project/import_nastran.py | 2 +- src/ansys/aedt/core/workflows/project/kernel_converter.py | 2 +- src/ansys/aedt/core/workflows/q2d/__init__.py | 2 +- src/ansys/aedt/core/workflows/q3d/__init__.py | 2 +- src/ansys/aedt/core/workflows/templates/__init__.py | 2 +- src/ansys/aedt/core/workflows/templates/pyaedt_utils.py | 2 +- src/ansys/aedt/core/workflows/templates/template_get_started.py | 2 +- src/ansys/aedt/core/workflows/twinbuilder/__init__.py | 2 +- src/ansys/aedt/core/workflows/twinbuilder/convert_to_circuit.py | 2 +- tests/__init__.py | 2 +- tests/conftest.py | 2 +- tests/integration/__init__.py | 2 +- tests/integration/test_monostatic_rcs_data.py | 2 +- tests/integration/test_touchstone_data.py | 2 +- tests/system/__init__.py | 2 +- tests/system/general/__init__.py | 2 +- tests/system/general/conftest.py | 2 +- tests/system/general/test_01_3dlayout_edb.py | 2 +- tests/system/general/test_01_Design.py | 2 +- tests/system/general/test_01_GeometryOperators.py | 2 +- tests/system/general/test_01_configuration_files.py | 2 +- tests/system/general/test_01_data_handlers.py | 2 +- tests/system/general/test_01_downloads.py | 2 +- tests/system/general/test_01_general_methods.py | 2 +- tests/system/general/test_01_report_file_parser.py | 2 +- tests/system/general/test_01_toolkit_icons.py | 2 +- tests/system/general/test_02_2D_modeler.py | 2 +- tests/system/general/test_02_3D_modeler.py | 2 +- tests/system/general/test_03_Materials.py | 2 +- tests/system/general/test_04_SBR.py | 2 +- tests/system/general/test_05_Mesh.py | 2 +- tests/system/general/test_06_MessageManager.py | 2 +- tests/system/general/test_07_Object3D.py | 2 +- tests/system/general/test_08_Primitives3D.py | 2 +- tests/system/general/test_09_Primitives2D.py | 2 +- tests/system/general/test_09_VariableManager.py | 2 +- tests/system/general/test_11_Setup.py | 2 +- tests/system/general/test_12_1_PostProcessing.py | 2 +- tests/system/general/test_12_PostProcessing.py | 2 +- tests/system/general/test_13_LoadAEDTFile.py | 2 +- tests/system/general/test_14_AedtLogger.py | 2 +- tests/system/general/test_15_ibs_reader.py | 2 +- tests/system/general/test_16_3d_stackup.py | 2 +- tests/system/general/test_20_HFSS.py | 2 +- tests/system/general/test_21_Circuit.py | 2 +- tests/system/general/test_22_Circuit_DynamicLink.py | 2 +- tests/system/general/test_27_Maxwell2D.py | 2 +- tests/system/general/test_28_Maxwell3D.py | 2 +- tests/system/general/test_29_Mechanical.py | 2 +- tests/system/general/test_30_Q2D.py | 2 +- tests/system/general/test_32_RMxprt.py | 2 +- tests/system/general/test_34_TwinBuilder.py | 2 +- tests/system/general/test_35_MaxwellCircuit.py | 2 +- tests/system/general/test_36_Q2D_PostProcessing.py | 2 +- tests/system/general/test_37_Genetic_Algorithm.py | 2 +- tests/system/general/test_41_3dlayout_modeler.py | 2 +- tests/system/general/test_43_CableModeling.py | 2 +- tests/system/general/test_44_TouchstoneParser.py | 2 +- tests/system/general/test_45_FilterSolutions/__init__.py | 2 +- .../general/test_45_FilterSolutions/resources/__init__.py | 2 +- .../general/test_45_FilterSolutions/resources/resources.py | 2 +- .../test_45_FilterSolutions/test_distributed_filter/__init__.py | 2 +- .../test_distributed_filter/test_distributed_topology.py | 2 +- .../general/test_45_FilterSolutions/test_filter/__init__.py | 2 +- .../test_45_FilterSolutions/test_filter/test_attributes.py | 2 +- .../test_45_FilterSolutions/test_filter/test_dll_interface.py | 2 +- .../test_45_FilterSolutions/test_filter/test_graph_setup.py | 2 +- .../test_45_FilterSolutions/test_filter/test_ideal_response.py | 2 +- .../test_filter/test_multiple_bands_table.py | 2 +- .../test_filter/test_transmission_zeros.py | 2 +- .../test_45_FilterSolutions/test_lumped_export/__init__.py | 2 +- .../test_lumped_export/test_export_to_aedt.py | 2 +- .../test_lumped_export/test_optimization_goals_table.py | 2 +- .../test_45_FilterSolutions/test_lumped_filter/__init__.py | 2 +- .../test_lumped_filter/test_lumped_nodes_and_leads.py | 2 +- .../test_lumped_filter/test_lumped_parasitics.py | 2 +- .../test_lumped_termination_impedance_table.py | 2 +- .../test_lumped_filter/test_lumped_topology.py | 2 +- .../system/general/test_45_FilterSolutions/test_raise_error.py | 2 +- tests/system/general/test_46_FarField.py | 2 +- tests/system/general/test_47_CircuitNetlist.py | 2 +- tests/system/general/test_48_RCS_export.py | 2 +- tests/system/general/test_49_RCS_data_plotter.py | 2 +- tests/system/general/test_98_Icepak.py | 2 +- tests/system/general/test_launch_desktop.py | 2 +- tests/system/general/test_utils.py | 2 +- tests/system/solvers/__init__.py | 2 +- tests/system/solvers/conftest.py | 2 +- tests/system/solvers/test_00_analyze.py | 2 +- tests/system/solvers/test_01_pdf.py | 2 +- tests/system/solvers/test_26_emit.py | 2 +- tests/system/solvers/test_31_Q3D.py | 2 +- tests/system/solvers/test_45_workflows.py | 2 +- tests/unit/__init__.py | 2 +- tests/unit/conftest.py | 2 +- tests/unit/test_aedt_versions.py | 2 +- tests/unit/test_clr_module.py | 2 +- tests/unit/test_desktop.py | 2 +- tests/unit/test_extension_misc.py | 2 +- tests/unit/test_generic_filesystem.py | 2 +- tests/unit/test_hdm_parser.py | 2 +- tests/unit/test_maxwell_3d.py | 2 +- tests/unit/test_monostatic_rcs_data.py | 2 +- tests/unit/test_monostatic_rcs_exporter.py | 2 +- tests/unit/test_utils.py | 2 +- tests/unit/test_warnings.py | 2 +- 301 files changed, 301 insertions(+), 301 deletions(-) diff --git a/LICENSE b/LICENSE index 6a949e7fd8c..4a8652561be 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ MIT License -Copyright (c) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +Copyright (c) 2021 - 2025 ANSYS, Inc. and/or its affiliates. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in diff --git a/src/ansys/aedt/core/__init__.py b/src/ansys/aedt/core/__init__.py index e0c8111cb18..2b3d78a9d33 100644 --- a/src/ansys/aedt/core/__init__.py +++ b/src/ansys/aedt/core/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/aedt_logger.py b/src/ansys/aedt/core/aedt_logger.py index b49b4a8664f..4a8011a99c3 100644 --- a/src/ansys/aedt/core/aedt_logger.py +++ b/src/ansys/aedt/core/aedt_logger.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/__init__.py b/src/ansys/aedt/core/application/__init__.py index a83f6a966d8..898778ba6a4 100644 --- a/src/ansys/aedt/core/application/__init__.py +++ b/src/ansys/aedt/core/application/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/aedt_file_management.py b/src/ansys/aedt/core/application/aedt_file_management.py index a7cc998f120..e2af1362e74 100644 --- a/src/ansys/aedt/core/application/aedt_file_management.py +++ b/src/ansys/aedt/core/application/aedt_file_management.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/aedt_objects.py b/src/ansys/aedt/core/application/aedt_objects.py index 51e79a7f568..e0ff57e368c 100644 --- a/src/ansys/aedt/core/application/aedt_objects.py +++ b/src/ansys/aedt/core/application/aedt_objects.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis.py b/src/ansys/aedt/core/application/analysis.py index 494e4b58d8c..516856ae94a 100644 --- a/src/ansys/aedt/core/application/analysis.py +++ b/src/ansys/aedt/core/application/analysis.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_3d.py b/src/ansys/aedt/core/application/analysis_3d.py index 58377f595e5..56c862032e4 100644 --- a/src/ansys/aedt/core/application/analysis_3d.py +++ b/src/ansys/aedt/core/application/analysis_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_3d_layout.py b/src/ansys/aedt/core/application/analysis_3d_layout.py index 796953d1bee..a54fd0aeab6 100644 --- a/src/ansys/aedt/core/application/analysis_3d_layout.py +++ b/src/ansys/aedt/core/application/analysis_3d_layout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_circuit_netlist.py b/src/ansys/aedt/core/application/analysis_circuit_netlist.py index 95103c9accd..3e3907fc0d8 100644 --- a/src/ansys/aedt/core/application/analysis_circuit_netlist.py +++ b/src/ansys/aedt/core/application/analysis_circuit_netlist.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_hf.py b/src/ansys/aedt/core/application/analysis_hf.py index 7d0ba7dea71..3cb7e850deb 100644 --- a/src/ansys/aedt/core/application/analysis_hf.py +++ b/src/ansys/aedt/core/application/analysis_hf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_icepak.py b/src/ansys/aedt/core/application/analysis_icepak.py index d4c1400bce6..3a4cad4c065 100644 --- a/src/ansys/aedt/core/application/analysis_icepak.py +++ b/src/ansys/aedt/core/application/analysis_icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_maxwell_circuit.py b/src/ansys/aedt/core/application/analysis_maxwell_circuit.py index 4a58ff6879b..39441909e01 100644 --- a/src/ansys/aedt/core/application/analysis_maxwell_circuit.py +++ b/src/ansys/aedt/core/application/analysis_maxwell_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_nexxim.py b/src/ansys/aedt/core/application/analysis_nexxim.py index c5e653e257d..9176d328c39 100644 --- a/src/ansys/aedt/core/application/analysis_nexxim.py +++ b/src/ansys/aedt/core/application/analysis_nexxim.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_r_m_xprt.py b/src/ansys/aedt/core/application/analysis_r_m_xprt.py index e8f7f3f8d7f..e2ad0e6e68f 100644 --- a/src/ansys/aedt/core/application/analysis_r_m_xprt.py +++ b/src/ansys/aedt/core/application/analysis_r_m_xprt.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/analysis_twin_builder.py b/src/ansys/aedt/core/application/analysis_twin_builder.py index d2008966d90..185109e6b4a 100644 --- a/src/ansys/aedt/core/application/analysis_twin_builder.py +++ b/src/ansys/aedt/core/application/analysis_twin_builder.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/design.py b/src/ansys/aedt/core/application/design.py index 8bd231884eb..4f5ba3ea57d 100644 --- a/src/ansys/aedt/core/application/design.py +++ b/src/ansys/aedt/core/application/design.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/design_solutions.py b/src/ansys/aedt/core/application/design_solutions.py index 8531a688e7b..000fef1aecc 100644 --- a/src/ansys/aedt/core/application/design_solutions.py +++ b/src/ansys/aedt/core/application/design_solutions.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/job_manager.py b/src/ansys/aedt/core/application/job_manager.py index 67f2777b570..f7f141a7f69 100644 --- a/src/ansys/aedt/core/application/job_manager.py +++ b/src/ansys/aedt/core/application/job_manager.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/application/variables.py b/src/ansys/aedt/core/application/variables.py index ff951562e54..84a545533fb 100644 --- a/src/ansys/aedt/core/application/variables.py +++ b/src/ansys/aedt/core/application/variables.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/circuit.py b/src/ansys/aedt/core/circuit.py index c7917d140b5..33100686fc7 100644 --- a/src/ansys/aedt/core/circuit.py +++ b/src/ansys/aedt/core/circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/circuit_netlist.py b/src/ansys/aedt/core/circuit_netlist.py index b5b4579ba1b..32a2ca72e58 100644 --- a/src/ansys/aedt/core/circuit_netlist.py +++ b/src/ansys/aedt/core/circuit_netlist.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/common_rpc.py b/src/ansys/aedt/core/common_rpc.py index 7673a04fe3e..ea0b93a4e75 100644 --- a/src/ansys/aedt/core/common_rpc.py +++ b/src/ansys/aedt/core/common_rpc.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/desktop.py b/src/ansys/aedt/core/desktop.py index f25703d17bb..4893517bf56 100644 --- a/src/ansys/aedt/core/desktop.py +++ b/src/ansys/aedt/core/desktop.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/downloads.py b/src/ansys/aedt/core/downloads.py index 9929387b0f3..137e697129a 100644 --- a/src/ansys/aedt/core/downloads.py +++ b/src/ansys/aedt/core/downloads.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/edb.py b/src/ansys/aedt/core/edb.py index c6934a099b0..4bfc71680ba 100644 --- a/src/ansys/aedt/core/edb.py +++ b/src/ansys/aedt/core/edb.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit.py b/src/ansys/aedt/core/emit.py index 46eb22676ea..e055069d053 100644 --- a/src/ansys/aedt/core/emit.py +++ b/src/ansys/aedt/core/emit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/__init__.py b/src/ansys/aedt/core/emit_core/__init__.py index ee70a199e8d..1bd5357b690 100644 --- a/src/ansys/aedt/core/emit_core/__init__.py +++ b/src/ansys/aedt/core/emit_core/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/couplings.py b/src/ansys/aedt/core/emit_core/couplings.py index 738101b04a1..a7166894664 100644 --- a/src/ansys/aedt/core/emit_core/couplings.py +++ b/src/ansys/aedt/core/emit_core/couplings.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/emit_constants.py b/src/ansys/aedt/core/emit_core/emit_constants.py index 108bc579bf5..d5e6ef461fa 100644 --- a/src/ansys/aedt/core/emit_core/emit_constants.py +++ b/src/ansys/aedt/core/emit_core/emit_constants.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/results/__init__.py b/src/ansys/aedt/core/emit_core/results/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/emit_core/results/__init__.py +++ b/src/ansys/aedt/core/emit_core/results/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/results/results.py b/src/ansys/aedt/core/emit_core/results/results.py index a3e358fcb7b..4c7265cd16e 100644 --- a/src/ansys/aedt/core/emit_core/results/results.py +++ b/src/ansys/aedt/core/emit_core/results/results.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/emit_core/results/revision.py b/src/ansys/aedt/core/emit_core/results/revision.py index fa42e4d732a..d5282fcbd5c 100644 --- a/src/ansys/aedt/core/emit_core/results/revision.py +++ b/src/ansys/aedt/core/emit_core/results/revision.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions.py b/src/ansys/aedt/core/filtersolutions.py index 4bba1f20334..a520d681e0f 100644 --- a/src/ansys/aedt/core/filtersolutions.py +++ b/src/ansys/aedt/core/filtersolutions.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/__init__.py b/src/ansys/aedt/core/filtersolutions_core/__init__.py index 8937ab483be..b56d991d8b2 100644 --- a/src/ansys/aedt/core/filtersolutions_core/__init__.py +++ b/src/ansys/aedt/core/filtersolutions_core/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/attributes.py b/src/ansys/aedt/core/filtersolutions_core/attributes.py index f5d6ec23562..ea10ac49f17 100644 --- a/src/ansys/aedt/core/filtersolutions_core/attributes.py +++ b/src/ansys/aedt/core/filtersolutions_core/attributes.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py index 5f931948e22..86ac9ce5e2a 100644 --- a/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py index 1f84552c98e..2fb450cae31 100644 --- a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py +++ b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py index 1e1db5c7b8f..d1012e8b7a1 100644 --- a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py +++ b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/graph_setup.py b/src/ansys/aedt/core/filtersolutions_core/graph_setup.py index 98a64b4efaf..145822c00a2 100644 --- a/src/ansys/aedt/core/filtersolutions_core/graph_setup.py +++ b/src/ansys/aedt/core/filtersolutions_core/graph_setup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/ideal_response.py b/src/ansys/aedt/core/filtersolutions_core/ideal_response.py index 758116df5e6..2fe400c0252 100644 --- a/src/ansys/aedt/core/filtersolutions_core/ideal_response.py +++ b/src/ansys/aedt/core/filtersolutions_core/ideal_response.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_nodes_and_leads.py b/src/ansys/aedt/core/filtersolutions_core/lumped_nodes_and_leads.py index b474ce4bc22..55e82767cda 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_nodes_and_leads.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_nodes_and_leads.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_parasitics.py b/src/ansys/aedt/core/filtersolutions_core/lumped_parasitics.py index 3f57e77686e..517e6579d69 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_parasitics.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_parasitics.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_termination_impedance_table.py b/src/ansys/aedt/core/filtersolutions_core/lumped_termination_impedance_table.py index 31561639a9c..b90e88abc62 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_termination_impedance_table.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_termination_impedance_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py index bfdcf7b9a50..a513b9ca9a2 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/multiple_bands_table.py b/src/ansys/aedt/core/filtersolutions_core/multiple_bands_table.py index c5d0b1b52df..a6023e265d8 100644 --- a/src/ansys/aedt/core/filtersolutions_core/multiple_bands_table.py +++ b/src/ansys/aedt/core/filtersolutions_core/multiple_bands_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py b/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py index 242ec992512..bee9b573abb 100644 --- a/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py +++ b/src/ansys/aedt/core/filtersolutions_core/optimization_goals_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/filtersolutions_core/transmission_zeros.py b/src/ansys/aedt/core/filtersolutions_core/transmission_zeros.py index 18fe4233244..d5547657ff6 100644 --- a/src/ansys/aedt/core/filtersolutions_core/transmission_zeros.py +++ b/src/ansys/aedt/core/filtersolutions_core/transmission_zeros.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/__init__.py b/src/ansys/aedt/core/generic/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/generic/__init__.py +++ b/src/ansys/aedt/core/generic/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/aedt_versions.py b/src/ansys/aedt/core/generic/aedt_versions.py index 187296bb304..28be63ff5ec 100644 --- a/src/ansys/aedt/core/generic/aedt_versions.py +++ b/src/ansys/aedt/core/generic/aedt_versions.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/clr_module.py b/src/ansys/aedt/core/generic/clr_module.py index 357250f6d52..99d0424c45b 100644 --- a/src/ansys/aedt/core/generic/clr_module.py +++ b/src/ansys/aedt/core/generic/clr_module.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/configurations.py b/src/ansys/aedt/core/generic/configurations.py index 909a79c2b12..4dc4af88361 100644 --- a/src/ansys/aedt/core/generic/configurations.py +++ b/src/ansys/aedt/core/generic/configurations.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/constants.py b/src/ansys/aedt/core/generic/constants.py index 0598c66191c..57616c79e92 100644 --- a/src/ansys/aedt/core/generic/constants.py +++ b/src/ansys/aedt/core/generic/constants.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/data_handlers.py b/src/ansys/aedt/core/generic/data_handlers.py index 225507fb64b..0da70b82f2a 100644 --- a/src/ansys/aedt/core/generic/data_handlers.py +++ b/src/ansys/aedt/core/generic/data_handlers.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/design_types.py b/src/ansys/aedt/core/generic/design_types.py index 4dab9552acc..20ff33ab848 100644 --- a/src/ansys/aedt/core/generic/design_types.py +++ b/src/ansys/aedt/core/generic/design_types.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/desktop_sessions.py b/src/ansys/aedt/core/generic/desktop_sessions.py index d348a47d551..b3ae6ff05ae 100644 --- a/src/ansys/aedt/core/generic/desktop_sessions.py +++ b/src/ansys/aedt/core/generic/desktop_sessions.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/filesystem.py b/src/ansys/aedt/core/generic/filesystem.py index 506b4a6fa07..a2f7811163f 100644 --- a/src/ansys/aedt/core/generic/filesystem.py +++ b/src/ansys/aedt/core/generic/filesystem.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/general_methods.py b/src/ansys/aedt/core/generic/general_methods.py index b5dcd1ddb91..76f6c91a94e 100644 --- a/src/ansys/aedt/core/generic/general_methods.py +++ b/src/ansys/aedt/core/generic/general_methods.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/grpc_plugin_dll_class.py b/src/ansys/aedt/core/generic/grpc_plugin_dll_class.py index 822ee78e5de..de715b3d428 100644 --- a/src/ansys/aedt/core/generic/grpc_plugin_dll_class.py +++ b/src/ansys/aedt/core/generic/grpc_plugin_dll_class.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/ibis_reader.py b/src/ansys/aedt/core/generic/ibis_reader.py index 0cc4ea19977..f7ef9f147b5 100644 --- a/src/ansys/aedt/core/generic/ibis_reader.py +++ b/src/ansys/aedt/core/generic/ibis_reader.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/load_aedt_file.py b/src/ansys/aedt/core/generic/load_aedt_file.py index 4ba4ce73cf2..641d6c7ac0f 100644 --- a/src/ansys/aedt/core/generic/load_aedt_file.py +++ b/src/ansys/aedt/core/generic/load_aedt_file.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/python_optimizers.py b/src/ansys/aedt/core/generic/python_optimizers.py index 692b1231838..57b9b4a149b 100644 --- a/src/ansys/aedt/core/generic/python_optimizers.py +++ b/src/ansys/aedt/core/generic/python_optimizers.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/generic/settings.py b/src/ansys/aedt/core/generic/settings.py index 02b6ed9f889..83c4ecf1fb0 100644 --- a/src/ansys/aedt/core/generic/settings.py +++ b/src/ansys/aedt/core/generic/settings.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/hfss.py b/src/ansys/aedt/core/hfss.py index 3183bbaa4cf..f1b61b2b82d 100644 --- a/src/ansys/aedt/core/hfss.py +++ b/src/ansys/aedt/core/hfss.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/hfss3dlayout.py b/src/ansys/aedt/core/hfss3dlayout.py index 81243de5679..2a2e4a5d73b 100644 --- a/src/ansys/aedt/core/hfss3dlayout.py +++ b/src/ansys/aedt/core/hfss3dlayout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/icepak.py b/src/ansys/aedt/core/icepak.py index 4547ab2b356..e449ea60c2b 100644 --- a/src/ansys/aedt/core/icepak.py +++ b/src/ansys/aedt/core/icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/maxwell.py b/src/ansys/aedt/core/maxwell.py index 1f4ebca5d1f..8801cfb8dcf 100644 --- a/src/ansys/aedt/core/maxwell.py +++ b/src/ansys/aedt/core/maxwell.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/maxwellcircuit.py b/src/ansys/aedt/core/maxwellcircuit.py index 033424e26f7..bf350befce7 100644 --- a/src/ansys/aedt/core/maxwellcircuit.py +++ b/src/ansys/aedt/core/maxwellcircuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/mechanical.py b/src/ansys/aedt/core/mechanical.py index 26f26ad2e79..cd27f361fa3 100644 --- a/src/ansys/aedt/core/mechanical.py +++ b/src/ansys/aedt/core/mechanical.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/misc/__init__.py b/src/ansys/aedt/core/misc/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/misc/__init__.py +++ b/src/ansys/aedt/core/misc/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/misc/create_remote_dir.py b/src/ansys/aedt/core/misc/create_remote_dir.py index 2996053836f..7063056140d 100644 --- a/src/ansys/aedt/core/misc/create_remote_dir.py +++ b/src/ansys/aedt/core/misc/create_remote_dir.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/__init__.py b/src/ansys/aedt/core/modeler/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modeler/__init__.py +++ b/src/ansys/aedt/core/modeler/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/__init__.py b/src/ansys/aedt/core/modeler/advanced_cad/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/__init__.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/actors.py b/src/ansys/aedt/core/modeler/advanced_cad/actors.py index fe150bdce75..e2848a903f1 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/actors.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/actors.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/multiparts.py b/src/ansys/aedt/core/modeler/advanced_cad/multiparts.py index dc8bfb72b26..5728362747c 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/multiparts.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/multiparts.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/oms.py b/src/ansys/aedt/core/modeler/advanced_cad/oms.py index 822c6c2454b..b301485e68f 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/oms.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/oms.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/parts.py b/src/ansys/aedt/core/modeler/advanced_cad/parts.py index dd6e4b1dbc2..cd1fb32e01e 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/parts.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/parts.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/advanced_cad/stackup_3d.py b/src/ansys/aedt/core/modeler/advanced_cad/stackup_3d.py index e7e1258784e..7b997150e61 100644 --- a/src/ansys/aedt/core/modeler/advanced_cad/stackup_3d.py +++ b/src/ansys/aedt/core/modeler/advanced_cad/stackup_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/__init__.py b/src/ansys/aedt/core/modeler/cad/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modeler/cad/__init__.py +++ b/src/ansys/aedt/core/modeler/cad/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/component_array.py b/src/ansys/aedt/core/modeler/cad/component_array.py index 540ded9f2da..bd54b5caec7 100644 --- a/src/ansys/aedt/core/modeler/cad/component_array.py +++ b/src/ansys/aedt/core/modeler/cad/component_array.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/components_3d.py b/src/ansys/aedt/core/modeler/cad/components_3d.py index 614c7526706..10cc88351fd 100644 --- a/src/ansys/aedt/core/modeler/cad/components_3d.py +++ b/src/ansys/aedt/core/modeler/cad/components_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/elements_3d.py b/src/ansys/aedt/core/modeler/cad/elements_3d.py index 78c25db6661..a905ae03cd2 100644 --- a/src/ansys/aedt/core/modeler/cad/elements_3d.py +++ b/src/ansys/aedt/core/modeler/cad/elements_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/modeler.py b/src/ansys/aedt/core/modeler/cad/modeler.py index 41fcb489dd2..034943ac4b9 100644 --- a/src/ansys/aedt/core/modeler/cad/modeler.py +++ b/src/ansys/aedt/core/modeler/cad/modeler.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/object_3d.py b/src/ansys/aedt/core/modeler/cad/object_3d.py index 4dedb6e44a1..157acc22ae7 100644 --- a/src/ansys/aedt/core/modeler/cad/object_3d.py +++ b/src/ansys/aedt/core/modeler/cad/object_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/polylines.py b/src/ansys/aedt/core/modeler/cad/polylines.py index 706bd3f4339..b8ef126cb83 100644 --- a/src/ansys/aedt/core/modeler/cad/polylines.py +++ b/src/ansys/aedt/core/modeler/cad/polylines.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/primitives.py b/src/ansys/aedt/core/modeler/cad/primitives.py index 820eba9b6d0..20d981f983f 100644 --- a/src/ansys/aedt/core/modeler/cad/primitives.py +++ b/src/ansys/aedt/core/modeler/cad/primitives.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/primitives_2d.py b/src/ansys/aedt/core/modeler/cad/primitives_2d.py index 004de148811..fee3a4a67d9 100644 --- a/src/ansys/aedt/core/modeler/cad/primitives_2d.py +++ b/src/ansys/aedt/core/modeler/cad/primitives_2d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/cad/primitives_3d.py b/src/ansys/aedt/core/modeler/cad/primitives_3d.py index af17422ac1a..51fb08aebd7 100644 --- a/src/ansys/aedt/core/modeler/cad/primitives_3d.py +++ b/src/ansys/aedt/core/modeler/cad/primitives_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/calculators.py b/src/ansys/aedt/core/modeler/calculators.py index 94fe8241ba9..626baae79df 100644 --- a/src/ansys/aedt/core/modeler/calculators.py +++ b/src/ansys/aedt/core/modeler/calculators.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/__init__.py b/src/ansys/aedt/core/modeler/circuits/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modeler/circuits/__init__.py +++ b/src/ansys/aedt/core/modeler/circuits/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py b/src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py index 6c67f490567..b388526f251 100644 --- a/src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py +++ b/src/ansys/aedt/core/modeler/circuits/object_3d_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py index b5f32fc57d3..ae65b5ff19a 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_emit.py b/src/ansys/aedt/core/modeler/circuits/primitives_emit.py index 3f3aef61c98..36279a9ab78 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_emit.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_emit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_maxwell_circuit.py b/src/ansys/aedt/core/modeler/circuits/primitives_maxwell_circuit.py index d5a815724bf..45172f45010 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_maxwell_circuit.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_maxwell_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py index e5afd8a57d0..8494f0ff950 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/circuits/primitives_twin_builder.py b/src/ansys/aedt/core/modeler/circuits/primitives_twin_builder.py index 3e323a757aa..2c6e9006290 100644 --- a/src/ansys/aedt/core/modeler/circuits/primitives_twin_builder.py +++ b/src/ansys/aedt/core/modeler/circuits/primitives_twin_builder.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/geometry_operators.py b/src/ansys/aedt/core/modeler/geometry_operators.py index 0b8394c37f3..0b5ff383274 100644 --- a/src/ansys/aedt/core/modeler/geometry_operators.py +++ b/src/ansys/aedt/core/modeler/geometry_operators.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/modeler_2d.py b/src/ansys/aedt/core/modeler/modeler_2d.py index 9476d7a78b9..e6ffde867d9 100644 --- a/src/ansys/aedt/core/modeler/modeler_2d.py +++ b/src/ansys/aedt/core/modeler/modeler_2d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/modeler_3d.py b/src/ansys/aedt/core/modeler/modeler_3d.py index 907d396a32c..4945c344536 100644 --- a/src/ansys/aedt/core/modeler/modeler_3d.py +++ b/src/ansys/aedt/core/modeler/modeler_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/modeler_pcb.py b/src/ansys/aedt/core/modeler/modeler_pcb.py index c133eab086e..112000444e0 100644 --- a/src/ansys/aedt/core/modeler/modeler_pcb.py +++ b/src/ansys/aedt/core/modeler/modeler_pcb.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/pcb/__init__.py b/src/ansys/aedt/core/modeler/pcb/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modeler/pcb/__init__.py +++ b/src/ansys/aedt/core/modeler/pcb/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py b/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py index 2c486165bff..f3495c0297b 100644 --- a/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py +++ b/src/ansys/aedt/core/modeler/pcb/object_3d_layout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/pcb/primitives_3d_layout.py b/src/ansys/aedt/core/modeler/pcb/primitives_3d_layout.py index ca12d6eae8a..ac698642a0b 100644 --- a/src/ansys/aedt/core/modeler/pcb/primitives_3d_layout.py +++ b/src/ansys/aedt/core/modeler/pcb/primitives_3d_layout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modeler/schematic.py b/src/ansys/aedt/core/modeler/schematic.py index af339756a57..808ffcfda33 100644 --- a/src/ansys/aedt/core/modeler/schematic.py +++ b/src/ansys/aedt/core/modeler/schematic.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/__init__.py b/src/ansys/aedt/core/modules/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modules/__init__.py +++ b/src/ansys/aedt/core/modules/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/__init__.py b/src/ansys/aedt/core/modules/boundary/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/modules/boundary/__init__.py +++ b/src/ansys/aedt/core/modules/boundary/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/circuit_boundary.py b/src/ansys/aedt/core/modules/boundary/circuit_boundary.py index 7d3336a3189..e027c796752 100644 --- a/src/ansys/aedt/core/modules/boundary/circuit_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/circuit_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/common.py b/src/ansys/aedt/core/modules/boundary/common.py index adeeb9ff1a6..8027747eb4f 100644 --- a/src/ansys/aedt/core/modules/boundary/common.py +++ b/src/ansys/aedt/core/modules/boundary/common.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/hfss_boundary.py b/src/ansys/aedt/core/modules/boundary/hfss_boundary.py index decad53ed56..e5727bf8033 100644 --- a/src/ansys/aedt/core/modules/boundary/hfss_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/hfss_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/icepak_boundary.py b/src/ansys/aedt/core/modules/boundary/icepak_boundary.py index 817b5e7265e..3838641dc7e 100644 --- a/src/ansys/aedt/core/modules/boundary/icepak_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/icepak_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/layout_boundary.py b/src/ansys/aedt/core/modules/boundary/layout_boundary.py index 775c12195eb..e539655934d 100644 --- a/src/ansys/aedt/core/modules/boundary/layout_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/layout_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/maxwell_boundary.py b/src/ansys/aedt/core/modules/boundary/maxwell_boundary.py index 8658dc55c85..1d917aca644 100644 --- a/src/ansys/aedt/core/modules/boundary/maxwell_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/maxwell_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/boundary/q3d_boundary.py b/src/ansys/aedt/core/modules/boundary/q3d_boundary.py index 5745ca23a28..ddd2f5e2e34 100644 --- a/src/ansys/aedt/core/modules/boundary/q3d_boundary.py +++ b/src/ansys/aedt/core/modules/boundary/q3d_boundary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/cable_modeling.py b/src/ansys/aedt/core/modules/cable_modeling.py index 8f28443f3b7..a8bc5f96622 100644 --- a/src/ansys/aedt/core/modules/cable_modeling.py +++ b/src/ansys/aedt/core/modules/cable_modeling.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/circuit_templates.py b/src/ansys/aedt/core/modules/circuit_templates.py index 7560bd30952..0212f2d1c20 100644 --- a/src/ansys/aedt/core/modules/circuit_templates.py +++ b/src/ansys/aedt/core/modules/circuit_templates.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/design_xploration.py b/src/ansys/aedt/core/modules/design_xploration.py index 5ef05363145..e934bc1a2f7 100644 --- a/src/ansys/aedt/core/modules/design_xploration.py +++ b/src/ansys/aedt/core/modules/design_xploration.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/layer_stackup.py b/src/ansys/aedt/core/modules/layer_stackup.py index b02b5b9f6ac..117cc8b9d5b 100644 --- a/src/ansys/aedt/core/modules/layer_stackup.py +++ b/src/ansys/aedt/core/modules/layer_stackup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/material.py b/src/ansys/aedt/core/modules/material.py index 1a1369f29c9..45ee304779b 100644 --- a/src/ansys/aedt/core/modules/material.py +++ b/src/ansys/aedt/core/modules/material.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/material_lib.py b/src/ansys/aedt/core/modules/material_lib.py index 88b15962000..f03282c6a2c 100644 --- a/src/ansys/aedt/core/modules/material_lib.py +++ b/src/ansys/aedt/core/modules/material_lib.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/material_workbench.py b/src/ansys/aedt/core/modules/material_workbench.py index 0fa47920eac..3189d9a74e9 100644 --- a/src/ansys/aedt/core/modules/material_workbench.py +++ b/src/ansys/aedt/core/modules/material_workbench.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/mesh.py b/src/ansys/aedt/core/modules/mesh.py index fa432c43661..0053300274b 100644 --- a/src/ansys/aedt/core/modules/mesh.py +++ b/src/ansys/aedt/core/modules/mesh.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/mesh_3d_layout.py b/src/ansys/aedt/core/modules/mesh_3d_layout.py index 0967cd81770..0c3103b8c56 100644 --- a/src/ansys/aedt/core/modules/mesh_3d_layout.py +++ b/src/ansys/aedt/core/modules/mesh_3d_layout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/mesh_icepak.py b/src/ansys/aedt/core/modules/mesh_icepak.py index 217d2937e09..252cadd6b20 100644 --- a/src/ansys/aedt/core/modules/mesh_icepak.py +++ b/src/ansys/aedt/core/modules/mesh_icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/optimetrics_templates.py b/src/ansys/aedt/core/modules/optimetrics_templates.py index 76da1ac27c4..211afaba94a 100644 --- a/src/ansys/aedt/core/modules/optimetrics_templates.py +++ b/src/ansys/aedt/core/modules/optimetrics_templates.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/setup_templates.py b/src/ansys/aedt/core/modules/setup_templates.py index 9f47b9e38f4..7e2a406e1d2 100644 --- a/src/ansys/aedt/core/modules/setup_templates.py +++ b/src/ansys/aedt/core/modules/setup_templates.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/solve_setup.py b/src/ansys/aedt/core/modules/solve_setup.py index c19d96fdaec..e2ac772f803 100644 --- a/src/ansys/aedt/core/modules/solve_setup.py +++ b/src/ansys/aedt/core/modules/solve_setup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/modules/solve_sweeps.py b/src/ansys/aedt/core/modules/solve_sweeps.py index 5e7045deb68..3b85a3b29e9 100644 --- a/src/ansys/aedt/core/modules/solve_sweeps.py +++ b/src/ansys/aedt/core/modules/solve_sweeps.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/q3d.py b/src/ansys/aedt/core/q3d.py index 380b5f69080..fb2d145b0c8 100644 --- a/src/ansys/aedt/core/q3d.py +++ b/src/ansys/aedt/core/q3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/rmxprt.py b/src/ansys/aedt/core/rmxprt.py index f4c1d7a83f5..c7066a5cae4 100644 --- a/src/ansys/aedt/core/rmxprt.py +++ b/src/ansys/aedt/core/rmxprt.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/twinbuilder.py b/src/ansys/aedt/core/twinbuilder.py index 79599b250a2..a6216d53b39 100644 --- a/src/ansys/aedt/core/twinbuilder.py +++ b/src/ansys/aedt/core/twinbuilder.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/__init__.py b/src/ansys/aedt/core/visualization/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/visualization/__init__.py +++ b/src/ansys/aedt/core/visualization/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/__init__.py b/src/ansys/aedt/core/visualization/advanced/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/visualization/advanced/__init__.py +++ b/src/ansys/aedt/core/visualization/advanced/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py b/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py index e215eceb3c3..2505def180f 100644 --- a/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py +++ b/src/ansys/aedt/core/visualization/advanced/farfield_visualization.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/hdm_plot.py b/src/ansys/aedt/core/visualization/advanced/hdm_plot.py index 55b6590c4b2..9699b031e95 100644 --- a/src/ansys/aedt/core/visualization/advanced/hdm_plot.py +++ b/src/ansys/aedt/core/visualization/advanced/hdm_plot.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/misc.py b/src/ansys/aedt/core/visualization/advanced/misc.py index 99157dc6800..131f8301e5a 100644 --- a/src/ansys/aedt/core/visualization/advanced/misc.py +++ b/src/ansys/aedt/core/visualization/advanced/misc.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/rcs_visualization.py b/src/ansys/aedt/core/visualization/advanced/rcs_visualization.py index f988d697d27..d4fa1d309c8 100644 --- a/src/ansys/aedt/core/visualization/advanced/rcs_visualization.py +++ b/src/ansys/aedt/core/visualization/advanced/rcs_visualization.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/sbrplus/__init__.py b/src/ansys/aedt/core/visualization/advanced/sbrplus/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/visualization/advanced/sbrplus/__init__.py +++ b/src/ansys/aedt/core/visualization/advanced/sbrplus/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_parser.py b/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_parser.py index 6e432468ee7..d470f4b15ac 100644 --- a/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_parser.py +++ b/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_parser.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_utils.py b/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_utils.py index beb52ec1dcf..10524971784 100644 --- a/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_utils.py +++ b/src/ansys/aedt/core/visualization/advanced/sbrplus/hdm_utils.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py b/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py index bc48aff3624..ff44c50950f 100644 --- a/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py +++ b/src/ansys/aedt/core/visualization/advanced/touchstone_parser.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/plot/__init__.py b/src/ansys/aedt/core/visualization/plot/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/visualization/plot/__init__.py +++ b/src/ansys/aedt/core/visualization/plot/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/plot/matplotlib.py b/src/ansys/aedt/core/visualization/plot/matplotlib.py index 6fd2ef9de77..e9377d75de6 100644 --- a/src/ansys/aedt/core/visualization/plot/matplotlib.py +++ b/src/ansys/aedt/core/visualization/plot/matplotlib.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/plot/pdf.py b/src/ansys/aedt/core/visualization/plot/pdf.py index a220b967568..3a1d77c9923 100644 --- a/src/ansys/aedt/core/visualization/plot/pdf.py +++ b/src/ansys/aedt/core/visualization/plot/pdf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/plot/pyvista.py b/src/ansys/aedt/core/visualization/plot/pyvista.py index f4fa4ec0315..5101ac9f675 100644 --- a/src/ansys/aedt/core/visualization/plot/pyvista.py +++ b/src/ansys/aedt/core/visualization/plot/pyvista.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/__init__.py b/src/ansys/aedt/core/visualization/post/__init__.py index 4009620b257..48fcb1b8703 100644 --- a/src/ansys/aedt/core/visualization/post/__init__.py +++ b/src/ansys/aedt/core/visualization/post/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/common.py b/src/ansys/aedt/core/visualization/post/common.py index 808675537f2..b1057a9e28a 100644 --- a/src/ansys/aedt/core/visualization/post/common.py +++ b/src/ansys/aedt/core/visualization/post/common.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/compliance.py b/src/ansys/aedt/core/visualization/post/compliance.py index 21fa228c71a..4863b423e01 100644 --- a/src/ansys/aedt/core/visualization/post/compliance.py +++ b/src/ansys/aedt/core/visualization/post/compliance.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/farfield_exporter.py b/src/ansys/aedt/core/visualization/post/farfield_exporter.py index f81f88a8d66..03d7709fc2e 100644 --- a/src/ansys/aedt/core/visualization/post/farfield_exporter.py +++ b/src/ansys/aedt/core/visualization/post/farfield_exporter.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/field_data.py b/src/ansys/aedt/core/visualization/post/field_data.py index a479fb8ebe3..2882fae70c6 100644 --- a/src/ansys/aedt/core/visualization/post/field_data.py +++ b/src/ansys/aedt/core/visualization/post/field_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/field_summary.py b/src/ansys/aedt/core/visualization/post/field_summary.py index d448abac347..39b9a1b3273 100644 --- a/src/ansys/aedt/core/visualization/post/field_summary.py +++ b/src/ansys/aedt/core/visualization/post/field_summary.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/fields_calculator.py b/src/ansys/aedt/core/visualization/post/fields_calculator.py index b45089740d5..27bf33c7427 100644 --- a/src/ansys/aedt/core/visualization/post/fields_calculator.py +++ b/src/ansys/aedt/core/visualization/post/fields_calculator.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/visualization/post/monitor_icepak.py b/src/ansys/aedt/core/visualization/post/monitor_icepak.py index ffae885db47..121d3cd8bea 100644 --- a/src/ansys/aedt/core/visualization/post/monitor_icepak.py +++ b/src/ansys/aedt/core/visualization/post/monitor_icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/post_3dlayout.py b/src/ansys/aedt/core/visualization/post/post_3dlayout.py index 09e814dd6a9..e9f262bd02b 100644 --- a/src/ansys/aedt/core/visualization/post/post_3dlayout.py +++ b/src/ansys/aedt/core/visualization/post/post_3dlayout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/post_circuit.py b/src/ansys/aedt/core/visualization/post/post_circuit.py index ec367e7b998..d251a305b65 100644 --- a/src/ansys/aedt/core/visualization/post/post_circuit.py +++ b/src/ansys/aedt/core/visualization/post/post_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/post_common_3d.py b/src/ansys/aedt/core/visualization/post/post_common_3d.py index 608e31e2382..6724d5c5af3 100644 --- a/src/ansys/aedt/core/visualization/post/post_common_3d.py +++ b/src/ansys/aedt/core/visualization/post/post_common_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/post_icepak.py b/src/ansys/aedt/core/visualization/post/post_icepak.py index 34a6ca97256..d093a675751 100644 --- a/src/ansys/aedt/core/visualization/post/post_icepak.py +++ b/src/ansys/aedt/core/visualization/post/post_icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/rcs_exporter.py b/src/ansys/aedt/core/visualization/post/rcs_exporter.py index 7767c1060a1..8146c296ec6 100644 --- a/src/ansys/aedt/core/visualization/post/rcs_exporter.py +++ b/src/ansys/aedt/core/visualization/post/rcs_exporter.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/solution_data.py b/src/ansys/aedt/core/visualization/post/solution_data.py index aa24e3212ad..92d67cb3ef1 100644 --- a/src/ansys/aedt/core/visualization/post/solution_data.py +++ b/src/ansys/aedt/core/visualization/post/solution_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/spisim.py b/src/ansys/aedt/core/visualization/post/spisim.py index 295c4527b34..d9bd14bf3ab 100644 --- a/src/ansys/aedt/core/visualization/post/spisim.py +++ b/src/ansys/aedt/core/visualization/post/spisim.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/__init__.py b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/__init__.py index addb0938ec4..39f7bda009b 100644 --- a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/__init__.py +++ b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_parameters.py b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_parameters.py index dbe5b79d50f..7576319a8d4 100644 --- a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_parameters.py +++ b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_parameters.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_settings_mapping.py b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_settings_mapping.py index b41e73b8e1d..58434e72e24 100644 --- a/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_settings_mapping.py +++ b/src/ansys/aedt/core/visualization/post/spisim_com_configuration_files/com_settings_mapping.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/post/vrt_data.py b/src/ansys/aedt/core/visualization/post/vrt_data.py index d556d4a20ed..d0ccf53d20f 100644 --- a/src/ansys/aedt/core/visualization/post/vrt_data.py +++ b/src/ansys/aedt/core/visualization/post/vrt_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/__init__.py b/src/ansys/aedt/core/visualization/report/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/src/ansys/aedt/core/visualization/report/__init__.py +++ b/src/ansys/aedt/core/visualization/report/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/common.py b/src/ansys/aedt/core/visualization/report/common.py index 4889d1a187b..e75df8225a6 100644 --- a/src/ansys/aedt/core/visualization/report/common.py +++ b/src/ansys/aedt/core/visualization/report/common.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/constants.py b/src/ansys/aedt/core/visualization/report/constants.py index 4af74811b1d..e4f9a7c5ce7 100644 --- a/src/ansys/aedt/core/visualization/report/constants.py +++ b/src/ansys/aedt/core/visualization/report/constants.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/emi.py b/src/ansys/aedt/core/visualization/report/emi.py index 6b4eb1eb4f9..78e23655a62 100644 --- a/src/ansys/aedt/core/visualization/report/emi.py +++ b/src/ansys/aedt/core/visualization/report/emi.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/eye.py b/src/ansys/aedt/core/visualization/report/eye.py index 68c9af68a30..344c8df3032 100644 --- a/src/ansys/aedt/core/visualization/report/eye.py +++ b/src/ansys/aedt/core/visualization/report/eye.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/field.py b/src/ansys/aedt/core/visualization/report/field.py index ee1cc945b10..3440ac55ea0 100644 --- a/src/ansys/aedt/core/visualization/report/field.py +++ b/src/ansys/aedt/core/visualization/report/field.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/visualization/report/standard.py b/src/ansys/aedt/core/visualization/report/standard.py index 6e27c94ef34..2b271ba3f8c 100644 --- a/src/ansys/aedt/core/visualization/report/standard.py +++ b/src/ansys/aedt/core/visualization/report/standard.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/workflows/__init__.py b/src/ansys/aedt/core/workflows/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/__init__.py +++ b/src/ansys/aedt/core/workflows/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/circuit/__init__.py b/src/ansys/aedt/core/workflows/circuit/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/circuit/__init__.py +++ b/src/ansys/aedt/core/workflows/circuit/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/circuit/import_schematic.py b/src/ansys/aedt/core/workflows/circuit/import_schematic.py index c4ce40b1723..9c40a76ae98 100644 --- a/src/ansys/aedt/core/workflows/circuit/import_schematic.py +++ b/src/ansys/aedt/core/workflows/circuit/import_schematic.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/customize_automation_tab.py b/src/ansys/aedt/core/workflows/customize_automation_tab.py index ed3c305b043..c0b70b56d11 100644 --- a/src/ansys/aedt/core/workflows/customize_automation_tab.py +++ b/src/ansys/aedt/core/workflows/customize_automation_tab.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/emit/__init__.py b/src/ansys/aedt/core/workflows/emit/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/emit/__init__.py +++ b/src/ansys/aedt/core/workflows/emit/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss/__init__.py b/src/ansys/aedt/core/workflows/hfss/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/hfss/__init__.py +++ b/src/ansys/aedt/core/workflows/hfss/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss/choke_designer.py b/src/ansys/aedt/core/workflows/hfss/choke_designer.py index 8998cc36e3e..7ddc60a3edd 100644 --- a/src/ansys/aedt/core/workflows/hfss/choke_designer.py +++ b/src/ansys/aedt/core/workflows/hfss/choke_designer.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss/push_excitation_from_file.py b/src/ansys/aedt/core/workflows/hfss/push_excitation_from_file.py index d520e4911c9..e6a417276d3 100644 --- a/src/ansys/aedt/core/workflows/hfss/push_excitation_from_file.py +++ b/src/ansys/aedt/core/workflows/hfss/push_excitation_from_file.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/__init__.py b/src/ansys/aedt/core/workflows/hfss3dlayout/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/__init__.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py b/src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py index 3733783f6b8..43a6f7b75b3 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/export_layout.py b/src/ansys/aedt/core/workflows/hfss3dlayout/export_layout.py index 288af100638..7032fdd67c0 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/export_layout.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/export_layout.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/export_to_3d.py b/src/ansys/aedt/core/workflows/hfss3dlayout/export_to_3d.py index ae049bcddb1..49adbabda7d 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/export_to_3d.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/export_to_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/generate_arbitrary_wave_ports.py b/src/ansys/aedt/core/workflows/hfss3dlayout/generate_arbitrary_wave_ports.py index 20336329276..2e7469b6b36 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/generate_arbitrary_wave_ports.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/generate_arbitrary_wave_ports.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/parametrize_edb.py b/src/ansys/aedt/core/workflows/hfss3dlayout/parametrize_edb.py index ed53ddd96a0..b36756b7606 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/parametrize_edb.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/parametrize_edb.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/hfss3dlayout/push_excitation_from_file_3dl.py b/src/ansys/aedt/core/workflows/hfss3dlayout/push_excitation_from_file_3dl.py index a86246c0f61..f8e57f7911c 100644 --- a/src/ansys/aedt/core/workflows/hfss3dlayout/push_excitation_from_file_3dl.py +++ b/src/ansys/aedt/core/workflows/hfss3dlayout/push_excitation_from_file_3dl.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/icepak/__init__.py b/src/ansys/aedt/core/workflows/icepak/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/icepak/__init__.py +++ b/src/ansys/aedt/core/workflows/icepak/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/icepak/power_map_from_csv.py b/src/ansys/aedt/core/workflows/icepak/power_map_from_csv.py index 0d0bb86b893..ec879837374 100644 --- a/src/ansys/aedt/core/workflows/icepak/power_map_from_csv.py +++ b/src/ansys/aedt/core/workflows/icepak/power_map_from_csv.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/maxwell2d/__init__.py b/src/ansys/aedt/core/workflows/maxwell2d/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/maxwell2d/__init__.py +++ b/src/ansys/aedt/core/workflows/maxwell2d/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/maxwell3d/__init__.py b/src/ansys/aedt/core/workflows/maxwell3d/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/maxwell3d/__init__.py +++ b/src/ansys/aedt/core/workflows/maxwell3d/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/mechanical/__init__.py b/src/ansys/aedt/core/workflows/mechanical/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/mechanical/__init__.py +++ b/src/ansys/aedt/core/workflows/mechanical/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/misc.py b/src/ansys/aedt/core/workflows/misc.py index 12abbce5fff..65c8ab1165e 100644 --- a/src/ansys/aedt/core/workflows/misc.py +++ b/src/ansys/aedt/core/workflows/misc.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/__init__.py b/src/ansys/aedt/core/workflows/project/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/project/__init__.py +++ b/src/ansys/aedt/core/workflows/project/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/advanced_fields_calculator.py b/src/ansys/aedt/core/workflows/project/advanced_fields_calculator.py index 933cc160f7a..98785b45f95 100644 --- a/src/ansys/aedt/core/workflows/project/advanced_fields_calculator.py +++ b/src/ansys/aedt/core/workflows/project/advanced_fields_calculator.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/configure_edb.py b/src/ansys/aedt/core/workflows/project/configure_edb.py index 382a67a160a..db468c45988 100644 --- a/src/ansys/aedt/core/workflows/project/configure_edb.py +++ b/src/ansys/aedt/core/workflows/project/configure_edb.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/create_report.py b/src/ansys/aedt/core/workflows/project/create_report.py index db376b51bde..1a4cc9f1915 100644 --- a/src/ansys/aedt/core/workflows/project/create_report.py +++ b/src/ansys/aedt/core/workflows/project/create_report.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/import_nastran.py b/src/ansys/aedt/core/workflows/project/import_nastran.py index e156e8fcd5b..e78aa23445f 100644 --- a/src/ansys/aedt/core/workflows/project/import_nastran.py +++ b/src/ansys/aedt/core/workflows/project/import_nastran.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/project/kernel_converter.py b/src/ansys/aedt/core/workflows/project/kernel_converter.py index c14738d2f0c..c1079764504 100644 --- a/src/ansys/aedt/core/workflows/project/kernel_converter.py +++ b/src/ansys/aedt/core/workflows/project/kernel_converter.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/src/ansys/aedt/core/workflows/q2d/__init__.py b/src/ansys/aedt/core/workflows/q2d/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/q2d/__init__.py +++ b/src/ansys/aedt/core/workflows/q2d/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/q3d/__init__.py b/src/ansys/aedt/core/workflows/q3d/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/q3d/__init__.py +++ b/src/ansys/aedt/core/workflows/q3d/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/templates/__init__.py b/src/ansys/aedt/core/workflows/templates/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/templates/__init__.py +++ b/src/ansys/aedt/core/workflows/templates/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py b/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py index 11c0923cd3f..f2fc5ba6665 100644 --- a/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py +++ b/src/ansys/aedt/core/workflows/templates/pyaedt_utils.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/templates/template_get_started.py b/src/ansys/aedt/core/workflows/templates/template_get_started.py index 0b9b1002888..cbac809c7a2 100644 --- a/src/ansys/aedt/core/workflows/templates/template_get_started.py +++ b/src/ansys/aedt/core/workflows/templates/template_get_started.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/twinbuilder/__init__.py b/src/ansys/aedt/core/workflows/twinbuilder/__init__.py index f10103137e9..4b4bef088b4 100644 --- a/src/ansys/aedt/core/workflows/twinbuilder/__init__.py +++ b/src/ansys/aedt/core/workflows/twinbuilder/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/src/ansys/aedt/core/workflows/twinbuilder/convert_to_circuit.py b/src/ansys/aedt/core/workflows/twinbuilder/convert_to_circuit.py index c9ed24cb098..0c7ae914447 100644 --- a/src/ansys/aedt/core/workflows/twinbuilder/convert_to_circuit.py +++ b/src/ansys/aedt/core/workflows/twinbuilder/convert_to_circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # Permission is hereby granted, free of charge, to any person obtaining a copy diff --git a/tests/__init__.py b/tests/__init__.py index 3a26ec85f77..354fd81f25f 100644 --- a/tests/__init__.py +++ b/tests/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/conftest.py b/tests/conftest.py index 2daabf60f5b..4640dcda5b5 100644 --- a/tests/conftest.py +++ b/tests/conftest.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/integration/__init__.py b/tests/integration/__init__.py index 822cc1f80fb..1a157585db4 100644 --- a/tests/integration/__init__.py +++ b/tests/integration/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/integration/test_monostatic_rcs_data.py b/tests/integration/test_monostatic_rcs_data.py index 8b224837656..46684abcef8 100644 --- a/tests/integration/test_monostatic_rcs_data.py +++ b/tests/integration/test_monostatic_rcs_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/integration/test_touchstone_data.py b/tests/integration/test_touchstone_data.py index 336b86bd7e2..837c7aeead0 100644 --- a/tests/integration/test_touchstone_data.py +++ b/tests/integration/test_touchstone_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/__init__.py b/tests/system/__init__.py index 296abe8d52c..ed642961485 100644 --- a/tests/system/__init__.py +++ b/tests/system/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/__init__.py b/tests/system/general/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/__init__.py +++ b/tests/system/general/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/conftest.py b/tests/system/general/conftest.py index f36c07515f2..faadc215643 100644 --- a/tests/system/general/conftest.py +++ b/tests/system/general/conftest.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_3dlayout_edb.py b/tests/system/general/test_01_3dlayout_edb.py index 4d9f0b98e61..1afbe1e7eda 100644 --- a/tests/system/general/test_01_3dlayout_edb.py +++ b/tests/system/general/test_01_3dlayout_edb.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_Design.py b/tests/system/general/test_01_Design.py index 040740de3fc..4f284f1e1fb 100644 --- a/tests/system/general/test_01_Design.py +++ b/tests/system/general/test_01_Design.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_GeometryOperators.py b/tests/system/general/test_01_GeometryOperators.py index 1c18398a7c4..fffe6d3f165 100644 --- a/tests/system/general/test_01_GeometryOperators.py +++ b/tests/system/general/test_01_GeometryOperators.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_configuration_files.py b/tests/system/general/test_01_configuration_files.py index 27045e04704..22a62e189c6 100644 --- a/tests/system/general/test_01_configuration_files.py +++ b/tests/system/general/test_01_configuration_files.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_data_handlers.py b/tests/system/general/test_01_data_handlers.py index d46d20fb785..dd8dd0f8914 100644 --- a/tests/system/general/test_01_data_handlers.py +++ b/tests/system/general/test_01_data_handlers.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_downloads.py b/tests/system/general/test_01_downloads.py index 6323318e86e..12ffa4b806c 100644 --- a/tests/system/general/test_01_downloads.py +++ b/tests/system/general/test_01_downloads.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_general_methods.py b/tests/system/general/test_01_general_methods.py index a76677f2a8f..d9b8f13c872 100644 --- a/tests/system/general/test_01_general_methods.py +++ b/tests/system/general/test_01_general_methods.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_report_file_parser.py b/tests/system/general/test_01_report_file_parser.py index 2dc5f54c7ef..1e9b582acb7 100644 --- a/tests/system/general/test_01_report_file_parser.py +++ b/tests/system/general/test_01_report_file_parser.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_01_toolkit_icons.py b/tests/system/general/test_01_toolkit_icons.py index 738b460fb52..1e1081a9a18 100644 --- a/tests/system/general/test_01_toolkit_icons.py +++ b/tests/system/general/test_01_toolkit_icons.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_02_2D_modeler.py b/tests/system/general/test_02_2D_modeler.py index 7d9f87a58e1..d435c419e59 100644 --- a/tests/system/general/test_02_2D_modeler.py +++ b/tests/system/general/test_02_2D_modeler.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_02_3D_modeler.py b/tests/system/general/test_02_3D_modeler.py index d9592567d97..f5e9b833b6a 100644 --- a/tests/system/general/test_02_3D_modeler.py +++ b/tests/system/general/test_02_3D_modeler.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_03_Materials.py b/tests/system/general/test_03_Materials.py index c3758a23de7..95cec4cb59b 100644 --- a/tests/system/general/test_03_Materials.py +++ b/tests/system/general/test_03_Materials.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_04_SBR.py b/tests/system/general/test_04_SBR.py index 34b61ce98bb..919093c1b26 100644 --- a/tests/system/general/test_04_SBR.py +++ b/tests/system/general/test_04_SBR.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_05_Mesh.py b/tests/system/general/test_05_Mesh.py index 10632fa98fd..1678f4a2ca5 100644 --- a/tests/system/general/test_05_Mesh.py +++ b/tests/system/general/test_05_Mesh.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_06_MessageManager.py b/tests/system/general/test_06_MessageManager.py index ccddc65df60..704a79a271e 100644 --- a/tests/system/general/test_06_MessageManager.py +++ b/tests/system/general/test_06_MessageManager.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_07_Object3D.py b/tests/system/general/test_07_Object3D.py index 128f1d4e612..e066b9e568d 100644 --- a/tests/system/general/test_07_Object3D.py +++ b/tests/system/general/test_07_Object3D.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_08_Primitives3D.py b/tests/system/general/test_08_Primitives3D.py index 544fa53c2ea..4f3a71e6d85 100644 --- a/tests/system/general/test_08_Primitives3D.py +++ b/tests/system/general/test_08_Primitives3D.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_09_Primitives2D.py b/tests/system/general/test_09_Primitives2D.py index d9da2c97bc0..5e4764902ef 100644 --- a/tests/system/general/test_09_Primitives2D.py +++ b/tests/system/general/test_09_Primitives2D.py @@ -2,7 +2,7 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_09_VariableManager.py b/tests/system/general/test_09_VariableManager.py index 024996eefb8..c7407a39024 100644 --- a/tests/system/general/test_09_VariableManager.py +++ b/tests/system/general/test_09_VariableManager.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_11_Setup.py b/tests/system/general/test_11_Setup.py index c3885a87f71..ae48203a6ea 100644 --- a/tests/system/general/test_11_Setup.py +++ b/tests/system/general/test_11_Setup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_12_1_PostProcessing.py b/tests/system/general/test_12_1_PostProcessing.py index 7a65c67fbbc..c03c327e662 100644 --- a/tests/system/general/test_12_1_PostProcessing.py +++ b/tests/system/general/test_12_1_PostProcessing.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_12_PostProcessing.py b/tests/system/general/test_12_PostProcessing.py index 3680d734aa7..6289b68e246 100644 --- a/tests/system/general/test_12_PostProcessing.py +++ b/tests/system/general/test_12_PostProcessing.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_13_LoadAEDTFile.py b/tests/system/general/test_13_LoadAEDTFile.py index 4d58b2b2743..1fc85f3da85 100644 --- a/tests/system/general/test_13_LoadAEDTFile.py +++ b/tests/system/general/test_13_LoadAEDTFile.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_14_AedtLogger.py b/tests/system/general/test_14_AedtLogger.py index 14cb9c28698..d56e5fa29cf 100644 --- a/tests/system/general/test_14_AedtLogger.py +++ b/tests/system/general/test_14_AedtLogger.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_15_ibs_reader.py b/tests/system/general/test_15_ibs_reader.py index 1d4b4e7be71..8105d88f68e 100644 --- a/tests/system/general/test_15_ibs_reader.py +++ b/tests/system/general/test_15_ibs_reader.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_16_3d_stackup.py b/tests/system/general/test_16_3d_stackup.py index 9250fdd7dea..24833e63a12 100644 --- a/tests/system/general/test_16_3d_stackup.py +++ b/tests/system/general/test_16_3d_stackup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py index 572799e5995..b38d1f00ab1 100644 --- a/tests/system/general/test_20_HFSS.py +++ b/tests/system/general/test_20_HFSS.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_21_Circuit.py b/tests/system/general/test_21_Circuit.py index cb00a8bbe25..b6e53eb1bc4 100644 --- a/tests/system/general/test_21_Circuit.py +++ b/tests/system/general/test_21_Circuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_22_Circuit_DynamicLink.py b/tests/system/general/test_22_Circuit_DynamicLink.py index 3a5fbcfc2e6..9f17d7e2de2 100644 --- a/tests/system/general/test_22_Circuit_DynamicLink.py +++ b/tests/system/general/test_22_Circuit_DynamicLink.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_27_Maxwell2D.py b/tests/system/general/test_27_Maxwell2D.py index 55371228e03..7b66f96e10f 100644 --- a/tests/system/general/test_27_Maxwell2D.py +++ b/tests/system/general/test_27_Maxwell2D.py @@ -2,7 +2,7 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_28_Maxwell3D.py b/tests/system/general/test_28_Maxwell3D.py index 78eb079aab1..b50c35dd4f9 100644 --- a/tests/system/general/test_28_Maxwell3D.py +++ b/tests/system/general/test_28_Maxwell3D.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_29_Mechanical.py b/tests/system/general/test_29_Mechanical.py index 844265eb938..dc2680b060a 100644 --- a/tests/system/general/test_29_Mechanical.py +++ b/tests/system/general/test_29_Mechanical.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_30_Q2D.py b/tests/system/general/test_30_Q2D.py index b3726af921d..6842f7e2a08 100644 --- a/tests/system/general/test_30_Q2D.py +++ b/tests/system/general/test_30_Q2D.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_32_RMxprt.py b/tests/system/general/test_32_RMxprt.py index 6e9816f5d2c..800282d1ccc 100644 --- a/tests/system/general/test_32_RMxprt.py +++ b/tests/system/general/test_32_RMxprt.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_34_TwinBuilder.py b/tests/system/general/test_34_TwinBuilder.py index 717adda63a0..71cfbc4fc4e 100644 --- a/tests/system/general/test_34_TwinBuilder.py +++ b/tests/system/general/test_34_TwinBuilder.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_35_MaxwellCircuit.py b/tests/system/general/test_35_MaxwellCircuit.py index 39ef4277df4..3df6672e2f3 100644 --- a/tests/system/general/test_35_MaxwellCircuit.py +++ b/tests/system/general/test_35_MaxwellCircuit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_36_Q2D_PostProcessing.py b/tests/system/general/test_36_Q2D_PostProcessing.py index bb674a5464a..d921c9634c0 100644 --- a/tests/system/general/test_36_Q2D_PostProcessing.py +++ b/tests/system/general/test_36_Q2D_PostProcessing.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_37_Genetic_Algorithm.py b/tests/system/general/test_37_Genetic_Algorithm.py index 263d8deff65..2da18ff88d3 100644 --- a/tests/system/general/test_37_Genetic_Algorithm.py +++ b/tests/system/general/test_37_Genetic_Algorithm.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_41_3dlayout_modeler.py b/tests/system/general/test_41_3dlayout_modeler.py index be902599c7d..53277fd743a 100644 --- a/tests/system/general/test_41_3dlayout_modeler.py +++ b/tests/system/general/test_41_3dlayout_modeler.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_43_CableModeling.py b/tests/system/general/test_43_CableModeling.py index b8101c28209..e80faac5693 100644 --- a/tests/system/general/test_43_CableModeling.py +++ b/tests/system/general/test_43_CableModeling.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_44_TouchstoneParser.py b/tests/system/general/test_44_TouchstoneParser.py index 77068edea35..37b457253d0 100644 --- a/tests/system/general/test_44_TouchstoneParser.py +++ b/tests/system/general/test_44_TouchstoneParser.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/__init__.py b/tests/system/general/test_45_FilterSolutions/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/test_45_FilterSolutions/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/resources/__init__.py b/tests/system/general/test_45_FilterSolutions/resources/__init__.py index f744b86ba71..71f363ec64c 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/resources/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/resources/resources.py b/tests/system/general/test_45_FilterSolutions/resources/resources.py index e17da0a83f1..cc5fa165c11 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/resources.py +++ b/tests/system/general/test_45_FilterSolutions/resources/resources.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py index ca321697ef5..215698219d3 100644 --- a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/__init__.py b/tests/system/general/test_45_FilterSolutions/test_filter/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py index 2ffbfa5bf66..e2920157880 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py index 33a10fc59cd..4501df23c8a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py index ecf87eb1969..468ffe2fe60 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py index 7cd3847462d..a70c45cf38f 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py index c681d84e15a..cab35dcfa50 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py index ebc8f049470..79470965f16 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/__init__.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 0818334b2a7..041f92eb3b4 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py index c87ac3fc32a..2ff330772e9 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/__init__.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/__init__.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py index 4e418e851c6..40412dcdd10 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py index e9b8aae2ba6..57f2426b74e 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py index f94d2c16547..dff2a082609 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py index 9e9a7596aec..90fe1d73a78 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_45_FilterSolutions/test_raise_error.py b/tests/system/general/test_45_FilterSolutions/test_raise_error.py index 3d91b5a8ba3..8015dc8b992 100644 --- a/tests/system/general/test_45_FilterSolutions/test_raise_error.py +++ b/tests/system/general/test_45_FilterSolutions/test_raise_error.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_46_FarField.py b/tests/system/general/test_46_FarField.py index 786599e97be..54ef87494c6 100644 --- a/tests/system/general/test_46_FarField.py +++ b/tests/system/general/test_46_FarField.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_47_CircuitNetlist.py b/tests/system/general/test_47_CircuitNetlist.py index e3c71e6c9b1..a148ad9a9a8 100644 --- a/tests/system/general/test_47_CircuitNetlist.py +++ b/tests/system/general/test_47_CircuitNetlist.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_48_RCS_export.py b/tests/system/general/test_48_RCS_export.py index c34d7e3794e..72eba6c9d43 100644 --- a/tests/system/general/test_48_RCS_export.py +++ b/tests/system/general/test_48_RCS_export.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_49_RCS_data_plotter.py b/tests/system/general/test_49_RCS_data_plotter.py index 11488f30117..2dfc9a3deb4 100644 --- a/tests/system/general/test_49_RCS_data_plotter.py +++ b/tests/system/general/test_49_RCS_data_plotter.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_98_Icepak.py b/tests/system/general/test_98_Icepak.py index 54848cda534..8155af94e18 100644 --- a/tests/system/general/test_98_Icepak.py +++ b/tests/system/general/test_98_Icepak.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_launch_desktop.py b/tests/system/general/test_launch_desktop.py index 12894b436b1..0a2fa78fd58 100644 --- a/tests/system/general/test_launch_desktop.py +++ b/tests/system/general/test_launch_desktop.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/general/test_utils.py b/tests/system/general/test_utils.py index 46d74604fa9..24a4a451ad1 100644 --- a/tests/system/general/test_utils.py +++ b/tests/system/general/test_utils.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/__init__.py b/tests/system/solvers/__init__.py index 9c4476773da..b78d8fed76c 100644 --- a/tests/system/solvers/__init__.py +++ b/tests/system/solvers/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/conftest.py b/tests/system/solvers/conftest.py index 17e04079bc5..0441921f808 100644 --- a/tests/system/solvers/conftest.py +++ b/tests/system/solvers/conftest.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/test_00_analyze.py b/tests/system/solvers/test_00_analyze.py index 58ac97c911b..bfdd63ac9ee 100644 --- a/tests/system/solvers/test_00_analyze.py +++ b/tests/system/solvers/test_00_analyze.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/test_01_pdf.py b/tests/system/solvers/test_01_pdf.py index c6afef2f25f..96a06e7cd48 100644 --- a/tests/system/solvers/test_01_pdf.py +++ b/tests/system/solvers/test_01_pdf.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/test_26_emit.py b/tests/system/solvers/test_26_emit.py index a63ebd112bd..54e0baca9d2 100644 --- a/tests/system/solvers/test_26_emit.py +++ b/tests/system/solvers/test_26_emit.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/test_31_Q3D.py b/tests/system/solvers/test_31_Q3D.py index e3e797308e5..ff09719b5f2 100644 --- a/tests/system/solvers/test_31_Q3D.py +++ b/tests/system/solvers/test_31_Q3D.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/system/solvers/test_45_workflows.py b/tests/system/solvers/test_45_workflows.py index 58f75584fdd..a04d3757256 100644 --- a/tests/system/solvers/test_45_workflows.py +++ b/tests/system/solvers/test_45_workflows.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/__init__.py b/tests/unit/__init__.py index 3907083f623..65bb3bf87f3 100644 --- a/tests/unit/__init__.py +++ b/tests/unit/__init__.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/conftest.py b/tests/unit/conftest.py index f172d934ac1..b47473860d7 100644 --- a/tests/unit/conftest.py +++ b/tests/unit/conftest.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_aedt_versions.py b/tests/unit/test_aedt_versions.py index 7ec295331bf..ce91e869376 100644 --- a/tests/unit/test_aedt_versions.py +++ b/tests/unit/test_aedt_versions.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_clr_module.py b/tests/unit/test_clr_module.py index 740bd22e877..0e613fe78e2 100644 --- a/tests/unit/test_clr_module.py +++ b/tests/unit/test_clr_module.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_desktop.py b/tests/unit/test_desktop.py index 5d8a0660aef..fbf62c923b5 100644 --- a/tests/unit/test_desktop.py +++ b/tests/unit/test_desktop.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_extension_misc.py b/tests/unit/test_extension_misc.py index 9e8a4c89b6f..8867d7d7fd4 100644 --- a/tests/unit/test_extension_misc.py +++ b/tests/unit/test_extension_misc.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_generic_filesystem.py b/tests/unit/test_generic_filesystem.py index b2dc74364c1..8b5b1c91cbf 100644 --- a/tests/unit/test_generic_filesystem.py +++ b/tests/unit/test_generic_filesystem.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_hdm_parser.py b/tests/unit/test_hdm_parser.py index 13811987310..9d6dc6469da 100644 --- a/tests/unit/test_hdm_parser.py +++ b/tests/unit/test_hdm_parser.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_maxwell_3d.py b/tests/unit/test_maxwell_3d.py index d731e088aae..dbd014dba77 100644 --- a/tests/unit/test_maxwell_3d.py +++ b/tests/unit/test_maxwell_3d.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_monostatic_rcs_data.py b/tests/unit/test_monostatic_rcs_data.py index ac396343b1b..c519a4f0b0b 100644 --- a/tests/unit/test_monostatic_rcs_data.py +++ b/tests/unit/test_monostatic_rcs_data.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_monostatic_rcs_exporter.py b/tests/unit/test_monostatic_rcs_exporter.py index 085a4205393..01dfd670633 100644 --- a/tests/unit/test_monostatic_rcs_exporter.py +++ b/tests/unit/test_monostatic_rcs_exporter.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_utils.py b/tests/unit/test_utils.py index 49bc5638e03..7e29982b83f 100644 --- a/tests/unit/test_utils.py +++ b/tests/unit/test_utils.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # diff --git a/tests/unit/test_warnings.py b/tests/unit/test_warnings.py index 078af6ce367..8711af96542 100644 --- a/tests/unit/test_warnings.py +++ b/tests/unit/test_warnings.py @@ -1,6 +1,6 @@ # -*- coding: utf-8 -*- # -# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates. +# Copyright (C) 2021 - 2025 ANSYS, Inc. and/or its affiliates. # SPDX-License-Identifier: MIT # # From 619e77b87f9d96ee181e446348403fe37ad5c3be Mon Sep 17 00:00:00 2001 From: raghajaf Date: Mon, 6 Jan 2025 16:09:08 -0500 Subject: [PATCH 4/6] Comments are applied. --- src/ansys/aedt/core/filtersolutions.py | 80 +- .../distributed_topology.py | 169 ++-- .../filtersolutions_core/dll_interface.py | 13 - .../filtersolutions_core/export_to_aedt.py | 4 +- .../filtersolutions_core/lumped_topology.py | 60 +- src/ansys/aedt/core/generic/design_types.py | 2 +- tests/system/general/conftest.py | 14 + .../Distributed/combine_stubs_false.ckt | 35 + ...mbine_stubs.ckt => combine_stubs_true.ckt} | 0 .../Distributed/equal_stub_widths_false.ckt | 32 + ..._widths.ckt => equal_stub_widths_true.ckt} | 0 ...pprox.ckt => equal_width_approx_false.ckt} | 0 ...ension.ckt => equal_width_approx_true.ckt} | 0 ...s.ckt => equal_width_conductors_false.ckt} | 0 ...ps.ckt => equal_width_conductors_true.ckt} | 0 .../Distributed/left_ground_side.ckt | 10 +- ...{load_resistor.ckt => load_resistance.ckt} | 0 .../Distributed/mitered_corners_false.ckt | 40 + ...d_corners.ckt => mitered_corners_true.ckt} | 0 .../resources/Distributed/open_ends_false.ckt | 27 + .../{open_ends.ckt => open_ends_true.ckt} | 0 ..._ground.ckt => open_stub_ground_false.ckt} | 0 .../Distributed/open_stub_ground_true.ckt | 24 + .../{tapped.ckt => pinned_false.ckt} | 0 .../{pinned.ckt => pinned_true.ckt} | 0 .../Distributed/quick_optimize_false.ckt | 32 + ...k_optimize.ckt => quick_optimize_true.ckt} | 0 .../resonator_length_extension_false.ckt | 27 + .../resonator_length_extension_true.ckt | 27 + .../Distributed/right_ground_side.ckt | 19 + ...tor_resistor.ckt => source_resistance.ckt} | 0 .../resources/Distributed/stub_taps_false.ckt | 33 + .../resources/Distributed/stub_taps_true.ckt | 33 + ...tap_position.ckt => tap_position_auto.ckt} | 0 .../Distributed/tap_position_sides.ckt | 40 + .../resources/Distributed/tapped_false.ckt | 33 + .../resources/Distributed/tapped_true.ckt | 33 + .../Distributed/use_coupled_lines_false.ckt | 45 + ...d_lines.ckt => use_coupled_lines_true.ckt} | 0 .../Distributed/use_series_caps_false.ckt | 35 + ...ries_caps.ckt => use_series_caps_true.ckt} | 0 .../resources/Distributed/via_ends_false.ckt | 33 + .../{via_ends.ckt => via_ends_true.ckt} | 0 .../resources/Distributed/wide_band_false.ckt | 27 + .../{wide_band.ckt => wide_band_true.ckt} | 0 ...{laod_resistor.ckt => laod_resistance.ckt} | 0 ...tor_resistor.ckt => source_resistance.ckt} | 0 .../test_distributed_topology.py | 736 +++++++------- .../test_filter/test_attributes.py | 766 ++++++-------- .../test_filter/test_dll_interface.py | 6 +- .../test_filter/test_graph_setup.py | 48 +- .../test_filter/test_ideal_response.py | 148 ++- .../test_filter/test_multiple_bands_table.py | 98 +- .../test_filter/test_transmission_zeros.py | 138 ++- .../test_lumped_export/test_export_to_aedt.py | 950 ++++++++---------- .../test_optimization_goals_table.py | 104 +- .../test_lumped_nodes_and_leads.py | 128 +-- .../test_lumped_parasitics.py | 112 +-- ...test_lumped_termination_impedance_table.py | 206 ++-- .../test_lumped_topology.py | 558 +++++----- .../test_raise_error.py | 8 +- 61 files changed, 2533 insertions(+), 2400 deletions(-) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{combine_stubs.ckt => combine_stubs_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{equal_stub_widths.ckt => equal_stub_widths_true.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{equal_width_approx.ckt => equal_width_approx_false.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{resonator_length_extension.ckt => equal_width_approx_true.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{equal_width_conductors.ckt => equal_width_conductors_false.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{stub_taps.ckt => equal_width_conductors_true.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{load_resistor.ckt => load_resistance.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{mitered_corners.ckt => mitered_corners_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{open_ends.ckt => open_ends_true.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{open_stub_ground.ckt => open_stub_ground_false.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{tapped.ckt => pinned_false.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{pinned.ckt => pinned_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{quick_optimize.ckt => quick_optimize_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_false.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_true.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/right_ground_side.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{generator_resistor.ckt => source_resistance.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_false.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_true.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{tap_position.ckt => tap_position_auto.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_sides.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_false.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_true.ckt create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{use_coupled_lines.ckt => use_coupled_lines_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{use_series_caps.ckt => use_series_caps_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{via_ends.ckt => via_ends_true.ckt} (100%) create mode 100644 tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_false.ckt rename tests/system/general/test_45_FilterSolutions/resources/Distributed/{wide_band.ckt => wide_band_true.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Lumped/{laod_resistor.ckt => laod_resistance.ckt} (100%) rename tests/system/general/test_45_FilterSolutions/resources/Lumped/{generator_resistor.ckt => source_resistance.ckt} (100%) diff --git a/src/ansys/aedt/core/filtersolutions.py b/src/ansys/aedt/core/filtersolutions.py index a520d681e0f..101c4180928 100644 --- a/src/ansys/aedt/core/filtersolutions.py +++ b/src/ansys/aedt/core/filtersolutions.py @@ -39,51 +39,54 @@ from ansys.aedt.core.filtersolutions_core.transmission_zeros import TransmissionZeros -class FilterSolutions: - """Provides the `FilterSolutions` application interface. +class FilterDesignBase: + """Provides the `FilterSolutions` main parameters applicable for all design types. This class has access to ideal filter attributes and calculated output parameters. + """ + + # See Also + # -------- + # :doc:`filtersolutions` + + def __init__(self, version=None): + self.version = version + ansys.aedt.core.filtersolutions_core._dll_interface(version) + self.attributes = Attributes() + self.ideal_response = IdealResponse() + self.graph_setup = GraphSetup() + self.transmission_zeros_ratio = TransmissionZeros(TableFormat.RATIO) + self.transmission_zeros_bandwidth = TransmissionZeros(TableFormat.BANDWIDTH) + + +class LumpedDesign(FilterDesignBase): + """Provides the `FilterSolutions` application interface for lumped filter designs. + This class provides access to lumped filter design parameters. Parameters ---------- version : str, optional Version of AEDT in ``xxxx.x`` format. The default is ``None``. - Examples + Example -------- - Create a ``FilterSolutions`` instance with a band-pass elliptic ideal filter. + Create a ``FilterSolutions.LumpedDesign`` instance with a band-pass elliptic filter. >>> import ansys.aedt.core >>> import ansys.aedt.core.filtersolutions - >>> from ansys.aedt.core.filtersolutions_core.dll_interface import DllInterface - >>> desktop_version = DllInterface.desktop_version - - >>> design = ansys.aedt.core.FilterSolutions.LumpDesign(version= desktop_version) - - See Also - -------- - :doc:`filtersolutions` + >>> LumpedDesign = ansys.aedt.core.FilterSolutions.LumpedDesign(version= "2025.1") + >>> LumpedDesign.attributes.filter_class = FilterClass.BAND_PASS + >>> LumpedDesign.attributes.filter_type = FilterType.ELLIPTIC """ - def __init__(self, version=None): - self.version = version - ansys.aedt.core.filtersolutions_core._dll_interface(version) - - -class LumpDesign(FilterSolutions): def __init__(self, version=None): super().__init__(version) self._init_lumped_design() def _init_lumped_design(self): """Initialize the ``FilterSolutions`` object to support a lumped filter design.""" - self.attributes = Attributes() - self.ideal_response = IdealResponse() - self.graph_setup = GraphSetup() self.source_impedance_table = LumpedTerminationImpedance(TerminationType.SOURCE) self.load_impedance_table = LumpedTerminationImpedance(TerminationType.LOAD) self.multiple_bands_table = MultipleBandsTable() - self.transmission_zeros_ratio = TransmissionZeros(TableFormat.RATIO) - self.transmission_zeros_bandwidth = TransmissionZeros(TableFormat.BANDWIDTH) self.export_to_aedt = ExportToAedt() self.optimization_goals_table = OptimizationGoalsTable() self.topology = LumpedTopology() @@ -91,21 +94,30 @@ def _init_lumped_design(self): self.leads_and_nodes = LumpedNodesandLeads() -class DistributedDesign(FilterSolutions): +class DistributedDesign(FilterDesignBase): + """Provides the `FilterSolutions` application interface for distributed filter designs. + This class provides access to distributed filter design parameters. + + Parameters + ---------- + version : str, optional + Version of AEDT in ``xxxx.x`` format. The default is ``None``. + + Example + -------- + Create a ``FilterSolutions.DistributedDesign`` instance with a band-pass interdigital filter. + + >>> import ansys.aedt.core + >>> import ansys.aedt.core.filtersolutions + >>> DistributedDesign = ansys.aedt.core.FilterSolutions.DistributedDesign(version= "2025.2") + >>> DistributedDesign.attributes.filter_class = FilterClass.BAND_PASS + >>> DistributedDesign.topology.topology_type = TopologyType.INTERDIGITAL + """ + def __init__(self, version=None): super().__init__(version) self._init_distributed_design() def _init_distributed_design(self): """Initialize the ``FilterSolutions`` object to support a distributed filter design.""" - self.attributes = Attributes() - self.ideal_response = IdealResponse() - self.graph_setup = GraphSetup() - self.source_impedance_table = LumpedTerminationImpedance(TerminationType.SOURCE) - self.load_impedance_table = LumpedTerminationImpedance(TerminationType.LOAD) - self.multiple_bands_table = MultipleBandsTable() - self.transmission_zeros_ratio = TransmissionZeros(TableFormat.RATIO) - self.transmission_zeros_bandwidth = TransmissionZeros(TableFormat.BANDWIDTH) - self.export_to_aedt = ExportToAedt() - self.optimization_goals_table = OptimizationGoalsTable() self.topology = DistributedTopology() diff --git a/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py index 86ac9ce5e2a..d42af5ed385 100644 --- a/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/distributed_topology.py @@ -32,7 +32,7 @@ import ansys.aedt.core -class TopologyList(Enum): +class TopologyType(Enum): """Provides an enum of distributed topologies. **Attributes:** @@ -51,7 +51,7 @@ class TopologyList(Enum): - INTERDIGITAL: Represents interdigital topology. - COMBLINE: Represents combline topology. - DUAL_RESONATORS: Represents dual resonators topology. - - SPACED_DUAl_RESONATORS: Represents spaced dual resonators topology. + - SPACED_DUAL_RESONATORS: Represents spaced dual resonators topology. - NOTCH_RESONATORs: Represents notch resonators topology. """ @@ -69,7 +69,7 @@ class TopologyList(Enum): INTERDIGITAL = 11 COMBLINE = 12 DUAL_RESONATORS = 13 - SPACED_DUAl_RESONATORS = 14 + SPACED_DUAL_RESONATORS = 14 NOTCH_RESONATORS = 15 @@ -91,9 +91,9 @@ class TapPosition(Enum): class DistributedTopology: - """Defines attributes and parameters of distributed filters. + """Defines topology parameters of distributed filters. - This class lets you construct all the necessary attributes for the ``DistributedDesign`` class. + This class lets you construct all paramaeters for the ``DistributedDesign`` class. """ def __init__(self): @@ -109,15 +109,15 @@ def _define_topology_dll_functions(self): self._dll.getDistributedTopology.argtypes = [c_char_p, c_int] self._dll.getDistributedTopology.restype = int - self._dll.setDistributedGeneratorResistor.argtype = c_char_p - self._dll.setDistributedGeneratorResistor.restype = c_int - self._dll.getDistributedGeneratorResistor.argtypes = [c_char_p, c_int] - self._dll.getDistributedGeneratorResistor.restype = c_int + self._dll.setDistributedSourceResistance.argtype = c_char_p + self._dll.setDistributedSourceResistance.restype = c_int + self._dll.getDistributedSourceResistance.argtypes = [c_char_p, c_int] + self._dll.getDistributedSourceResistance.restype = c_int - self._dll.setDistributedLoadResistor.argtype = c_char_p - self._dll.setDistributedLoadResistor.restype = c_int - self._dll.getDistributedLoadResistor.argtypes = [c_char_p, c_int] - self._dll.getDistributedLoadResistor.restype = c_int + self._dll.setDistributedLoadResistance.argtype = c_char_p + self._dll.setDistributedLoadResistance.restype = c_int + self._dll.getDistributedLoadResistance.argtypes = [c_char_p, c_int] + self._dll.getDistributedLoadResistance.restype = c_int self._dll.setDistributedFirstElementShunt.argtype = c_bool self._dll.setDistributedFirstElementShunt.restype = c_int @@ -259,10 +259,10 @@ def _define_topology_dll_functions(self): self._dll.getDistributedQuarterLengthFrequency.argtypes = [c_char_p, c_int] self._dll.getDistributedQuarterLengthFrequency.restype = c_int - self._dll.getDistributedCircuitResponseSize.argtype = POINTER(c_int) - self._dll.getDistributedCircuitResponseSize.restype = c_int - self._dll.getDistributedCircuitResponse.argtypes = [c_char_p, c_int] - self._dll.getDistributedCircuitResponse.restype = c_int + self._dll.getDistributedNetlistSize.argtype = POINTER(c_int) + self._dll.getDistributedNetlistSize.restype = c_int + self._dll.getDistributedNetlist.argtypes = [c_char_p, c_int] + self._dll.getDistributedNetlist.restype = c_int def _set_distributed_implementation(self): """Set ``FilterSolutions`` attributes to distributed design.""" @@ -272,57 +272,58 @@ def _set_distributed_implementation(self): self._dll_interface.raise_error(first_shunt_status) @property - def topology_list(self) -> TopologyList: + def topology_type(self) -> TopologyType: """Topology type of the distributed filter. The default is ``LUMPED_TRANSLATION``. - The ``TopologyList`` enum provides a list of all classes. + The ``TopologyType`` enum provides a list of all classes. Returns ------- - :enum:`TopologyList` + :enum:`TopologyType` """ type_string = self._dll_interface.get_string(self._dll.getDistributedTopology) - return self._dll_interface.string_to_enum(TopologyList, type_string) + return self._dll_interface.string_to_enum(TopologyType, type_string) - @topology_list.setter - def topology_list(self, topology_list: TopologyList): - if topology_list: - string_value = self._dll_interface.enum_to_string(topology_list) + @topology_type.setter + def topology_type(self, topology_type: TopologyType): + if topology_type: + string_value = self._dll_interface.enum_to_string(topology_type) self._dll_interface.set_string(self._dll.setDistributedTopology, string_value) @property - def generator_resistor(self) -> str: + def source_resistance(self) -> str: """Generator resistor. The default is ``50``. Returns ------- str """ - generator_resistor_string = self._dll_interface.get_string(self._dll.getDistributedGeneratorResistor) - return generator_resistor_string + source_resistance_string = self._dll_interface.get_string(self._dll.getDistributedSourceResistance) + return source_resistance_string - @generator_resistor.setter - def generator_resistor(self, generator_resistor_string): - self._dll_interface.set_string(self._dll.setDistributedGeneratorResistor, generator_resistor_string) + @source_resistance.setter + def source_resistance(self, source_resistance_string): + self._dll_interface.set_string(self._dll.setDistributedSourceResistance, source_resistance_string) @property - def load_resistor(self) -> str: + def load_resistance(self) -> str: """Load resistor. The default is ``50``. Returns ------- str """ - load_resistor_string = self._dll_interface.get_string(self._dll.getDistributedLoadResistor) - return load_resistor_string + load_resistance_string = self._dll_interface.get_string(self._dll.getDistributedLoadResistance) + return load_resistance_string - @load_resistor.setter - def load_resistor(self, load_resistor_string): - self._dll_interface.set_string(self._dll.setDistributedLoadResistor, load_resistor_string) + @load_resistance.setter + def load_resistance(self, load_resistance_string): + self._dll_interface.set_string(self._dll.setDistributedLoadResistance, load_resistance_string) @property def first_shunt(self) -> bool: """Flag indicating if shunt elements are first in the synthesized circuit. - If ``False``, series elements are first. + This parameter is applicable for the ``Lumped Translation``, ``Inductor Translation``, + and ``Coupled Segments`` topologies. If ``False``, series elements are first. Returns ------- @@ -341,6 +342,7 @@ def first_shunt(self, first_shunt: bool): @property def first_fat(self) -> bool: """Flag indicating if fat segments are first in the synthesized circuit. + This parameter is applicable for the ``Stepped Impedance`` topology. If ``False``, thin segments are first. Returns @@ -359,7 +361,11 @@ def first_fat(self, first_fat: bool): @property def use_series_caps(self) -> bool: - """Flag indicating if lumped capacitors are implemented in series segments. + """Flag indicating if lumped capacitors and inductor segments are implemented as series LC segments. + Series capacitors enable capacitive coupling between resonators, which can be achieved through either + series capacitors or coupled transmission lines. + This parameter is applicable for the ``Lumped Translation``and ``Inductor Translation`` topologies + of band pass and high pass filters, and ``Dual Resonator`` topology of band pass filters. Returns ------- @@ -378,6 +384,9 @@ def use_series_caps(self, use_series_caps: bool): @property def combine_stubs(self) -> bool: """Flag indicating if resonators are created with only one stub. + This parameter is applicable for the ``Lumped Translation``and ``Inductor Translation`` topologies + of band pass and band stop filters, and ``Dual Resonator`` and ``Spaced Dual Resonator`` topologies + of band pass filters. Returns ------- @@ -395,7 +404,10 @@ def combine_stubs(self, combine_stubs: bool): @property def use_coupled_lines(self) -> bool: - """Flag indicating if coupled segments are used between stubs. + """Flag indicating if coupled segments are used between stubs to enable capacitive coupling between resonators, + which can be achieved through either series capacitors or coupled transmission lines. + This parameter is applicable for the ``Lumped Translation``, ``Inductor Translation``, and ``Dual Resonator`` + topologies of band pass filters. Returns ------- @@ -413,7 +425,9 @@ def use_coupled_lines(self, use_coupled_lines: bool): @property def equal_width_approx(self) -> bool: - """Flag indicating if stubs with equal width are implemented. + """Flag indicating if all stubs are set to equal width. + This parameter is applicable for the ``Interdigital``, ``Combline`` topologies of + band pass filters, and ``Notch Resonators`` topology of band stop filters. Returns ------- @@ -432,6 +446,7 @@ def equal_width_approx(self, equal_width_approx: bool): @property def open_stub_ground(self) -> bool: """Flag indicating if quarter length open stubs are implemented to simulate ground. + This parameter is applicable for the ``Notch Resonators`` topology of band stop filters. Returns ------- @@ -450,6 +465,7 @@ def open_stub_ground(self, open_stub_ground: bool): @property def left_ground_side(self) -> bool: """Flag indicating if grounded pins are placed on left side. + This parameter is applicable for the ``Notch Resonators`` topology of band stop filters. If ``False``, right side is selected. Returns @@ -468,7 +484,8 @@ def left_ground_side(self, left_ground_side: bool): @property def equal_stub_widths(self) -> bool: - """Flag indicating if stubs with equal width are implemented. + """Flag indicating if all stubs widths are set with equal. + This parameter is applicable for the ``Shunt Stub Resonators`` topology of band pass filters. Returns ------- @@ -486,7 +503,9 @@ def equal_stub_widths(self, equal_stub_widths: bool): @property def center_z0_impedance(self) -> str: - """Resonator internal impednace. The default is ``75``. + """Resonator internal impedance. The default is ``75``. + This parameter is applicable for the ``Interdigital``, ``Combline``, ``Parallel Edge Coupled``, + and ``Shunt Stub Resonators`` topologies of band pass filters. Returns ------- @@ -501,8 +520,8 @@ def center_z0_impedance(self, center_z0_impedance_string): @property def equal_width_conductors(self) -> bool: - """Flag indicating if all resonators are set to the same width. - + """Flag indicating if all stubs are set to equal width. + This parameter is applicable for the ``Parallel Edge Coupled`` topologiy of band pass filters. Returns ------- bool @@ -520,6 +539,8 @@ def equal_width_conductors(self, equal_width_conductors: bool): @property def tapped(self) -> bool: """Flag indicating if the outer couplers are removed and the remaining outer couplers are tapped. + This parameter is applicable for the ``Interdigital``, ``Combline``, and ``Parallel Edge Coupled`` + topologies of band pass filters. Returns ------- @@ -538,6 +559,8 @@ def tapped(self, tapped: bool): @property def pinned(self) -> bool: """Flag indicating if the outer couplers are replaced with hairpin resonators. + This parameter is applicable for the wide band ``Interdigital``, and ``Parallel Edge Coupled`` + topologies of band pass filters. Returns ------- @@ -556,6 +579,8 @@ def pinned(self, pinned: bool): @property def stub_taps(self) -> bool: """Flag indicating if vertical stubs are implemented at the tap points. + This parameter is applicable for the ``Parallel Edge Coupled`` topology with all resonators + set to equal width of band pass filters. Returns ------- @@ -574,6 +599,7 @@ def stub_taps(self, stub_taps: bool): @property def via_ends(self) -> bool: """Flag indicating if resonators are terminated with vias instead of open ends. + This parameter is applicable for the ``Parallel Edge Coupled`` topology of band pass filters. Returns ------- @@ -591,7 +617,8 @@ def via_ends(self, via_ends: bool): @property def resonator_line_width(self) -> str: - """Line width to set in ``Haripin`` and ``Ring Resonator`` filters. The default is ``1.27 mm``. + """Line width to set in ``Haripin``, ``Miniature Hairpin``, and ``Ring Resonator`` topologies + of band pass filters. The default is ``1.27 mm``. Returns ------- @@ -606,7 +633,8 @@ def resonator_line_width(self, resonator_line_width_string): @property def resonator_rotation_angle(self) -> str: - """Net filter rotation angle in degrees. The default is ``0``. + """Net filter rotation angle for the ``Parallel Edge Coupled`` topology of band pass filters in degrees. + The default is ``0``. Returns ------- @@ -622,6 +650,8 @@ def resonator_rotation_angle(self, resonator_rotation_angle_string): @property def mitered_corners(self) -> bool: """Flag indicating if mitered corners are implemented. + This parameter is applicable for the ``Haripin``, ``Miniature Hairpin``, and ``Ring Resonator`` topologies + of band pass filters. Returns ------- @@ -639,7 +669,7 @@ def mitered_corners(self, mitered_corners: bool): @property def hairpin_gap_width(self) -> str: - """Gap width to set in ``Haripin`` filters. The default is ``2.54 mm``. + """Gap width to set in ``Haripin`` topology of band pass filters. The default is ``2.54 mm``. Returns ------- @@ -654,7 +684,7 @@ def hairpin_gap_width(self, hairpin_gap_width_string): @property def miniature_hairpin_gap_width(self) -> str: - """Gap width to set in ``Miniature Haripin`` filters. The default is ``635 um``. + """Gap width to set in ``Miniature Haripin`` topology of band pass filters. The default is ``635 um``. Returns ------- @@ -669,7 +699,7 @@ def miniature_hairpin_gap_width(self, miniature_hairpin_gap_width_string): @property def ring_resonator_gap_width(self) -> str: - """Gap width to set in ``Ring Resonator`` filters. The default is ``635 um``. + """Gap width to set in ``Ring Resonator`` topology of band pass filters. The default is ``635 um``. Returns ------- @@ -684,7 +714,8 @@ def ring_resonator_gap_width(self, ring_resonator_gap_width_string): @property def hairpin_extension_length(self) -> str: - """Extension length to set in ``Haripin`` filters for tuning purpose. The default is ``0 mm``. + """Extension length to set in ``Haripin`` topology of band pass filters for tuning purpose. + The default is ``0 mm``. Returns ------- @@ -699,7 +730,7 @@ def hairpin_extension_length(self, hairpin_extension_length_string): @property def miniature_hairpin_end_curl_extension(self) -> str: - """End curl extension length to set in ``Miniature Haripin`` filters for tuning purpose. + """End curl extension length to set in ``Miniature Haripin`` topology of band pass filters for tuning purpose. The default is ``0 mm``. Returns @@ -719,7 +750,8 @@ def miniature_hairpin_end_curl_extension(self, miniature_hairpin_end_curl_extens @property def ring_resonator_end_gap_extension(self) -> str: - """End gap extension length to set in ``Ring Resonator`` filters for tuning purpose. The default is ``0 mm``. + """End gap extension length to set in ``Ring Resonator`` topology of band pass filters for tuning purpose. + The default is ``0 mm``. Returns ------- @@ -738,8 +770,8 @@ def ring_resonator_end_gap_extension(self, ring_resonator_end_gap_extension_stri @property def tuning_type_1(self) -> bool: - """Flag indicating if both legs of the outer hairpins are set for tuning in ``Haripin`` filters. - If ``False``, only the outer legs of the outer hairpins are set. + """Flag indicating if both legs of the outer hairpins are set for tuning in ``Haripin`` + topology of band pass filters. If ``False``, only the outer legs of the outer hairpins are set. Returns ------- @@ -757,8 +789,8 @@ def tuning_type_1(self, tuning_type_1: bool): @property def tap_position(self) -> TapPosition: - """Tap position of the tap points in ``Miniature Hairpin`` and ``Ring Resonator`` filters. - The default is ``AUTO``. + """Tap position of the tap points in ``Miniature Hairpin`` and ``Ring Resonator`` + topologies of band pass filters. The default is ``AUTO``. The ``TapPosition`` enum provides a list of all types. Returns @@ -776,7 +808,7 @@ def tap_position(self, tap_position: TapPosition): @property def wide_band(self) -> bool: - """Flag indicating if ``Interdigital`` filters are optimized for wideband applications. + """Flag indicating if ``Interdigital`` topology of band pass filters are optimized for wideband applications. Returns ------- @@ -795,6 +827,7 @@ def wide_band(self, wide_band: bool): @property def open_ends(self) -> bool: """Flag indicating if resonators are terminated with open ends instead of vias. + This parameter is applicable for the ``Interdigital`` topology of band pass filters. Returns ------- @@ -812,7 +845,8 @@ def open_ends(self, open_ends: bool): @property def combline_half_length_frequency(self) -> str: - """Half length frequency in ``Combline`` filters where open remains open. The default is ``4G``. + """Half length frequency in ``Combline`` topology of band pass filters where open remains open. + The default is ``4G``. Returns ------- @@ -831,7 +865,8 @@ def combline_half_length_frequency(self, combline_half_length_frequency_string): @property def coupled_segments_quarter_length_frequency(self) -> str: - """Quarter length frequency in ``Coupled Segments`` filters where open becomes ground. The default is ``4G``. + """Quarter length frequency in ``Coupled Segments`` topology of band pass filters where open becomes ground. + The default is ``4G``. Returns ------- @@ -848,19 +883,18 @@ def coupled_segments_quarter_length_frequency(self, coupled_segments_quarter_len self._dll.setDistributedQuarterLengthFrequency, coupled_segments_quarter_length_frequency_string ) - def circuit_response(self): - """Execute real filter synthesis""" + def netlist(self): + """Calculate and generate spice nelist of the synthesized circuit""" size = c_int() - status = self._dll.getDistributedCircuitResponseSize(byref(size)) + status = self._dll.getDistributedNetlistSize(byref(size)) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - circuit_response_string = self._dll_interface.get_string( - self._dll.getDistributedCircuitResponse, max_size=size.value - ) - return circuit_response_string + netlist_string = self._dll_interface.get_string(self._dll.getDistributedNetlist, max_size=size.value) + return netlist_string @property def quick_optimize(self) -> bool: """Flag indicating if the quick optimization of the synthesized circuit is enabled. + This option provides a more accurate solution than raw synthesis alone. Returns ------- @@ -879,6 +913,7 @@ def quick_optimize(self, quick_optimize: bool): @property def resonator_length_extension(self) -> bool: """Flag indicating if the resonator length extension for optimization of the synthesized circuit is enabled. + This parameter is applicable for the ``Interdigital`` topology of band pass filters. Returns ------- diff --git a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py index 2fb450cae31..224b9e1e754 100644 --- a/src/ansys/aedt/core/filtersolutions_core/dll_interface.py +++ b/src/ansys/aedt/core/filtersolutions_core/dll_interface.py @@ -36,7 +36,6 @@ class DllInterface: """Interfaces with the FilterSolutions C++ API DLL.""" def __init__(self, show_gui=False, version=None): - self._version = version self._init_dll_path(version) self._init_dll(show_gui) @@ -189,15 +188,3 @@ def raise_error(self, error_status): if error_status != 0: error_message = self.get_string(self._dll.getErrorMessage, 4096) raise RuntimeError(error_message) - - @property - def desktop_version(self) -> str: - """Return the version of the AEDT. - - Returns - ------- - str - Desktop version. - """ - - return self._version diff --git a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py index d1012e8b7a1..6deaf04bdd6 100644 --- a/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py +++ b/src/ansys/aedt/core/filtersolutions_core/export_to_aedt.py @@ -852,8 +852,8 @@ def import_tuned_variables(self): size = c_int() status = self._dll.importTunedVariablesSize(byref(size)) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - circuit_response_string = self._dll_interface.get_string(self._dll.importTunedVariables, max_size=size.value) - return circuit_response_string + netlist_string = self._dll_interface.get_string(self._dll.importTunedVariables, max_size=size.value) + return netlist_string @property def part_libraries(self) -> PartLibraries: diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py index a513b9ca9a2..f7ad4b2e7ca 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py @@ -32,9 +32,9 @@ class LumpedTopology: - """Defines attributes and parameters of lumped filters. + """Defines topology parameters of lumped filters. - This class lets you construct all the necessary attributes for the ``LumpedDesign`` class. + This class lets you construct all parameters for the ``LumpedDesign`` class. """ def __init__(self): @@ -45,15 +45,15 @@ def __init__(self): def _define_topology_dll_functions(self): """Define C++ API DLL functions.""" - self._dll.setLumpedGeneratorResistor.argtype = c_char_p - self._dll.setLumpedGeneratorResistor.restype = c_int - self._dll.getLumpedGeneratorResistor.argtypes = [c_char_p, c_int] - self._dll.getLumpedGeneratorResistor.restype = c_int + self._dll.setLumpedSourceResistance.argtype = c_char_p + self._dll.setLumpedSourceResistance.restype = c_int + self._dll.getLumpedSourceResistance.argtypes = [c_char_p, c_int] + self._dll.getLumpedSourceResistance.restype = c_int - self._dll.setLumpedLoadResistor.argtype = c_char_p - self._dll.setLumpedLoadResistor.restype = c_int - self._dll.getLumpedLoadResistor.argtypes = [c_char_p, c_int] - self._dll.getLumpedLoadResistor.restype = c_int + self._dll.setLumpedLoadResistance.argtype = c_char_p + self._dll.setLumpedLoadResistance.restype = c_int + self._dll.getLumpedLoadResistance.argtypes = [c_char_p, c_int] + self._dll.getLumpedLoadResistance.restype = c_int self._dll.setLumpedCurrentSource.argtype = c_bool self._dll.setLumpedCurrentSource.restype = c_int @@ -150,10 +150,10 @@ def _define_topology_dll_functions(self): self._dll.getLumpedComplexElementTuneEnabled.argtype = POINTER(c_bool) self._dll.getLumpedComplexElementTuneEnabled.restype = c_int - self._dll.getLumpedCircuitResponseSize.argtype = POINTER(c_int) - self._dll.getLumpedCircuitResponseSize.restype = c_int - self._dll.getLumpedCircuitResponse.argtypes = [c_char_p, c_int] - self._dll.getLumpedCircuitResponse.restype = c_int + self._dll.getLumpedNetlistSize.argtype = POINTER(c_int) + self._dll.getLumpedNetlistSize.restype = c_int + self._dll.getLumpedNetlist.argtypes = [c_char_p, c_int] + self._dll.getLumpedNetlist.restype = c_int def _set_lump_implementation(self): """Set ``FilterSolutions`` attributes to lump design.""" @@ -161,34 +161,34 @@ def _set_lump_implementation(self): ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(filter_implementation_status) @property - def generator_resistor(self) -> str: + def source_resistance(self) -> str: """Generator resistor. The default is ``50``. Returns ------- str """ - generator_resistor_string = self._dll_interface.get_string(self._dll.getLumpedGeneratorResistor) - return generator_resistor_string + source_resistance_string = self._dll_interface.get_string(self._dll.getLumpedSourceResistance) + return source_resistance_string - @generator_resistor.setter - def generator_resistor(self, generator_resistor_string): - self._dll_interface.set_string(self._dll.setLumpedGeneratorResistor, generator_resistor_string) + @source_resistance.setter + def source_resistance(self, source_resistance_string): + self._dll_interface.set_string(self._dll.setLumpedSourceResistance, source_resistance_string) @property - def load_resistor(self) -> str: + def load_resistance(self) -> str: """Load resistor. The default is ``50``. Returns ------- str """ - load_resistor_string = self._dll_interface.get_string(self._dll.getLumpedLoadResistor) - return load_resistor_string + load_resistance_string = self._dll_interface.get_string(self._dll.getLumpedLoadResistance) + return load_resistance_string - @load_resistor.setter - def load_resistor(self, load_resistor_string): - self._dll_interface.set_string(self._dll.setLumpedLoadResistor, load_resistor_string) + @load_resistance.setter + def load_resistance(self, load_resistance_string): + self._dll_interface.set_string(self._dll.setLumpedLoadResistance, load_resistance_string) @property def current_source(self) -> bool: @@ -534,12 +534,10 @@ def complex_element_tune_enabled(self, complex_element_tune_enabled: bool): status = self._dll.setLumpedComplexElementTuneEnabled(complex_element_tune_enabled) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - def circuit_response(self): + def netlist(self): """Execute real filter synthesis""" size = c_int() status = self._dll.getLumpedCircuitResponseSize(byref(size)) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - circuit_response_string = self._dll_interface.get_string( - self._dll.getLumpedCircuitResponse, max_size=size.value - ) - return circuit_response_string + netlist_string = self._dll_interface.get_string(self._dll.getLumpedCircuitResponse, max_size=size.value) + return netlist_string diff --git a/src/ansys/aedt/core/generic/design_types.py b/src/ansys/aedt/core/generic/design_types.py index 20ff33ab848..58bbb87e3aa 100644 --- a/src/ansys/aedt/core/generic/design_types.py +++ b/src/ansys/aedt/core/generic/design_types.py @@ -69,7 +69,7 @@ def FilterSolutions( -------- Define a band-pass Butterworth filter with a center frequency of 1 GHz and a pass band width of 500 MHz. - design = ansys.aedt.core.LumpDesign(version="2025.1") + design = ansys.aedt.core.LumpedDesign(version="2025.1") design.attributes.filter_class = FilterClass.BAND_PASS design.attributes.filter_type = FilterType.BUTTERWORTH design.attributes.pass_band_center_frequency = "1G" diff --git a/tests/system/general/conftest.py b/tests/system/general/conftest.py index faadc215643..905d8ef10f3 100644 --- a/tests/system/general/conftest.py +++ b/tests/system/general/conftest.py @@ -71,6 +71,8 @@ from ansys.aedt.core.aedt_logger import pyaedt_logger from ansys.aedt.core.desktop import Desktop from ansys.aedt.core.desktop import _delete_objects +from ansys.aedt.core.filtersolutions import DistributedDesign +from ansys.aedt.core.filtersolutions import LumpedDesign from ansys.aedt.core.generic.desktop_sessions import _desktop_sessions from ansys.aedt.core.generic.filesystem import Scratch from ansys.aedt.core.generic.general_methods import generate_unique_name @@ -249,3 +251,15 @@ def _method(project_name=None, subfolder=""): ) return _method + + +@pytest.fixture(scope="function") +def lumped_design(): + """Fixture for creating a LumpedDesign object.""" + return LumpedDesign(config["desktopVersion"]) + + +@pytest.fixture(scope="function") +def distributed_design(): + """Fixture for creating a DistributedDesign object.""" + return DistributedDesign(config["desktopVersion"]) diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_false.ckt new file mode 100644 index 00000000000..925e887b6c9 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_false.ckt @@ -0,0 +1,35 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 2 6 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=5E-05 Len=0.06218 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 3 0 Wid=0.0003175 Len=0.000573 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 3 9 Wid=0.00508 Len=0.0226 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=5E-05 Len=0.06218 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 4 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S6 4 12 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 6 0 5E+09 +Rstb3 7 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 9 0 5E+09 +Rstb6 10 0 5E+09 +Rstb7 12 0 5E+09 +Rstb8 13 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -9E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.03 0.03 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/combine_stubs_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_false.ckt new file mode 100644 index 00000000000..874aa1d4381 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_false.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.000921 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0004979 Len=0.02996 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=0.0004979 Len=0.02996 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 5 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg3 5 6 Wid=0.000921 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 6 0 Wid=0.00635 Len=0.02672 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 6 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg4 3 0 5E+09 +Rseg5 4 0 5E+09 +Rseg6 5 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -200 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1.5E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.09 0.07 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_stub_widths_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx_false.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx_false.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_approx_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors_false.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors_false.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/equal_width_conductors_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt index 5e88de69fa7..532ed259168 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/left_ground_side.ckt @@ -3,11 +3,11 @@ * V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 Rg 1 2 50 -MXTcoup0 2 3 4 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MXTcoup1 4 5 6 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MXTcoup2 6 7 8 0 Wid=0.0005798 Gap=0.0001159 Len=0.02952 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MXTcoup3 8 9 10 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MXTcoup4 10 11 12 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup0 2 0 4 3 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 0 6 5 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 6 0 8 7 Wid=0.0005798 Gap=0.0001159 Len=0.02952 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 0 10 9 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 10 0 12 11 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 Rl 12 0 50 * .AC DEC 200 2E+08 5E+09 diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistance.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/load_resistance.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_false.ckt new file mode 100644 index 00000000000..3b1903ab429 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_false.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0008834 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=0.0002694 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.00508 Len=0.02561 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.00508 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.01137 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.01424 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -4E-08 3E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.07 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/mitered_corners_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_false.ckt new file mode 100644 index 00000000000..263e807e2e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_false.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-09 9E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/open_ends_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_false.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_false.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt new file mode 100644 index 00000000000..2ed3460232e --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt @@ -0,0 +1,24 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MXTcoup0 2 5 6 3 Wid=0.0009605 Gap=0.00045 Len=0.02903 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT0 4 5 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MXTcoup1 6 9 10 7 Wid=0.0006633 Gap=0.0001582 Len=0.02955 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1 8 9 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MXTcoup2 10 13 14 11 Wid=0.0005798 Gap=0.0001159 Len=0.02969 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2 12 13 Wid=0.0005798 Len=0.02969 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MXTcoup3 14 17 18 15 Wid=0.0006633 Gap=0.0001582 Len=0.02955 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT3 16 17 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MXTcoup4 18 21 22 19 Wid=0.0009605 Gap=0.00045 Len=0.02903 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT4 20 21 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +Rl 22 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -120 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned_false.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned_false.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/pinned_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_false.ckt new file mode 100644 index 00000000000..982129e7efa --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_false.ckt @@ -0,0 +1,32 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 5 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 3 7 Wid=0.00508 Len=0.01008 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=0.0003175 Len=0.02172 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 4 9 Wid=0.00508 Len=0.003362 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 5 0 5E+09 +Rstb3 6 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 9 0 5E+09 +Rstb8 10 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -70 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.1 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/quick_optimize_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_false.ckt new file mode 100644 index 00000000000..263e807e2e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_false.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-09 9E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_true.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_true.ckt new file mode 100644 index 00000000000..263e807e2e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/resonator_length_extension_true.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-09 9E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/right_ground_side.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/right_ground_side.ckt new file mode 100644 index 00000000000..5e88de69fa7 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/right_ground_side.ckt @@ -0,0 +1,19 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MXTcoup0 2 3 4 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 5 6 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 6 7 8 0 Wid=0.0005798 Gap=0.0001159 Len=0.02952 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 8 9 10 0 Wid=0.0006633 Gap=0.0001582 Len=0.02944 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 10 11 12 0 Wid=0.0009605 Gap=0.00045 Len=0.02909 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 12 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -140 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -2E-07 5E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) 0 0.7 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/source_resistance.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/generator_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/source_resistance.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_false.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_false.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_true.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_true.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/stub_taps_true.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_auto.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_auto.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_sides.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_sides.ckt new file mode 100644 index 00000000000..5ddaf2311fc --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tap_position_sides.ckt @@ -0,0 +1,40 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 3 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 4 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 5 4 6 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 5 6 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 3 5 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 7 6 8 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 7 8 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 7 9 8 10 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 9 10 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 8 10 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 9 11 10 12 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 11 12 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 11 13 12 14 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT14 13 14 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT15 11 13 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT16 13 15 14 16 Gap=0.0003619 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT17 15 16 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT18 15 17 16 18 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT19 17 18 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT20 16 18 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT21 17 19 18 20 Gap=7.937E-05 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT22 19 20 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT23 19 21 20 22 Gap=0.01003 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT24 19 21 Wid=0.00127 Len=0.01003 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT25 21 23 Wid=0.00127 Len=0.009046 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT26 23 22 Wid=0.00127 Len=0.0009879 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 23 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -100 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-08 2E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.05 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_false.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_false.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_true.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_true.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/tapped_true.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_false.ckt new file mode 100644 index 00000000000..0164fc88ad5 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_false.ckt @@ -0,0 +1,45 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MTSeg0 2 3 Wid=0.0008533 Len=0.05933 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S1 3 8 Wid=0.0003175 Len=0.03065 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S1 8 6 Wid=0.00508 Len=0.0003439 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S2 3 12 Wid=0.0003175 Len=0.01956 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 12 10 Wid=0.00508 Len=0.0002689 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=5E-05 Len=0.06218 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S3 4 16 Wid=0.0003175 Len=0.02845 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 16 14 Wid=0.00508 Len=0.002097 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT2S4 4 20 Wid=0.0003175 Len=0.0149 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 20 18 Wid=0.00508 Len=0.00134 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg2 4 5 Wid=7.267E-05 Len=0.06198 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 5 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rseg3 3 0 5E+09 +Rstb4 6 0 5E+09 +Rstb5 7 0 5E+09 +Rstb6 8 0 5E+09 +Rstb7 10 0 5E+09 +Rstb8 11 0 5E+09 +Rstb9 12 0 5E+09 +Rseg10 4 0 5E+09 +Rstb11 14 0 5E+09 +Rstb12 15 0 5E+09 +Rstb13 16 0 5E+09 +Rstb14 18 0 5E+09 +Rstb15 19 0 5E+09 +Rstb16 20 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -80 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -4E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) 0 0.6 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/use_coupled_lines_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_false.ckt new file mode 100644 index 00000000000..925e887b6c9 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_false.ckt @@ -0,0 +1,35 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S2 2 6 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=5E-05 Len=0.06218 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S3 3 0 Wid=0.0003175 Len=0.000573 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S4 3 9 Wid=0.00508 Len=0.0226 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg1 3 4 Wid=5E-05 Len=0.06218 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S5 4 0 Wid=0.0003175 Len=0.003025 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S6 4 12 Wid=0.00508 Len=0.01527 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 4 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb2 6 0 5E+09 +Rstb3 7 0 5E+09 +Rseg4 3 0 5E+09 +Rstb5 9 0 5E+09 +Rstb6 10 0 5E+09 +Rstb7 12 0 5E+09 +Rstb8 13 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -160 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -9E-08 1E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.03 0.03 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/use_series_caps_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_false.ckt new file mode 100644 index 00000000000..0e08635d5ae --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_false.ckt @@ -0,0 +1,33 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1S1 2 17 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg0 2 3 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup1 4 3 6 5 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup2 7 6 9 8 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup3 10 9 12 11 Wid=0.00127 Gap=0.0009881 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MXTcoup4 13 12 15 14 Wid=0.00127 Gap=0.0003397 Len=0.02927 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MTSeg5 15 16 Wid=0.00127 Len=0.01351 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +MT1S7 16 24 Wid=0.00127 Len=0.01385 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 +Rl 16 0 50 +* +* The Following Dummy Resistors May Be Required For Spice. +* +Rstb6 17 0 5E+09 +Rstb7 18 0 5E+09 +Rseg8 3 0 5E+09 +Rstb9 24 0 5E+09 +Rstb10 25 0 5E+09 +* +* End Dummy Resistors +* +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -180 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-07 4E-08 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/via_ends_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_false.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_false.ckt new file mode 100644 index 00000000000..263e807e2e3 --- /dev/null +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_false.ckt @@ -0,0 +1,27 @@ +* +*Length Units: Meters +* +V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 +Rg 1 2 50 +MT1 2 0 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT2 2 3 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT3 3 4 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT4 0 5 3 0 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT5 5 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT6 5 0 0 6 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT7 0 6 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT8 0 7 6 0 Gap=0.001726 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT9 7 0 Wid=0.001749 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT10 7 0 0 8 Gap=0.001031 Len=0.02781 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT11 0 9 Wid=0.001749 Len=0.01084 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT12 9 8 Wid=0.001749 Len=0.01697 Er=9.8 Thick=2.54E-06 Height=0.00127 +MT13 8 10 Wid=0.001749 Len=0.001888 Er=9.8 Thick=2.54E-06 Height=0.00127 +Rl 9 0 50 +* +.AC DEC 200 2E+08 5E+09 +.PLOT AC VDB(Rl) -60 0 +.PLOT AC VP(Rl) -200 200 +.PLOT AC VG(Rl) -1E-09 9E-09 +.TRAN 5E-11 1E-08 0 +.PLOT TRAN V(Rl) -0.04 0.04 +.END diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_true.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Distributed/wide_band_true.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistance.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/laod_resistance.ckt diff --git a/tests/system/general/test_45_FilterSolutions/resources/Lumped/generator_resistor.ckt b/tests/system/general/test_45_FilterSolutions/resources/Lumped/source_resistance.ckt similarity index 100% rename from tests/system/general/test_45_FilterSolutions/resources/Lumped/generator_resistor.ckt rename to tests/system/general/test_45_FilterSolutions/resources/Lumped/source_resistance.ckt diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py index 215698219d3..4676b2dffc1 100644 --- a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py @@ -22,12 +22,10 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import FilterClass from ansys.aedt.core.filtersolutions_core.attributes import FilterType from ansys.aedt.core.filtersolutions_core.distributed_topology import TapPosition -from ansys.aedt.core.filtersolutions_core.distributed_topology import TopologyList +from ansys.aedt.core.filtersolutions_core.distributed_topology import TopologyType from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -37,505 +35,493 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") -@pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") +@pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2") class TestClass: - def test_distributed_generator_resistor_30(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - assert design.topology.generator_resistor == "50" - design.topology.generator_resistor = "30" - assert design.topology.generator_resistor == "30" - assert design.topology.circuit_response().splitlines() == read_resource_file( - "generator_resistor.ckt", "Distributed" + def test_distributed_source_resistance_30(self, distributed_design): + assert distributed_design.topology.source_resistance == "50" + distributed_design.topology.source_resistance = "30" + assert distributed_design.topology.source_resistance == "30" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "source_resistance.ckt", "Distributed" ) - def test_distributed_load_resistor_30(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - - assert design.topology.load_resistor == "50" - design.topology.load_resistor = "30" - assert design.topology.load_resistor == "30" - assert design.topology.circuit_response().splitlines() == read_resource_file("load_resistor.ckt", "Distributed") - - def test_distributed_first_shunt(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - - assert design.topology.first_shunt - design.topology.first_shunt = True - assert design.topology.first_shunt - assert design.topology.circuit_response().splitlines() == read_resource_file("first_shunt.ckt", "Distributed") - - def test_distributed_first_series(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - - assert design.topology.first_shunt - design.topology.first_shunt = False - assert design.topology.first_shunt is False - assert design.topology.circuit_response().splitlines() == read_resource_file("first_series.ckt", "Distributed") - - def test_distributed_first_fat(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - - with pytest.raises(RuntimeError) as info: - design.topology.first_fat = True - assert info.value.args[0] == "The First Segment Fat or Thin property is not supported for the selected topology" - design.topology.topology_list = TopologyList.STEPPED_IMPEDANCE - assert design.topology.first_fat - design.topology.first_fat = True - assert design.topology.first_fat - assert design.topology.circuit_response().splitlines() == read_resource_file("first_fat.ckt", "Distributed") + def test_distributed_load_resistance_30(self, distributed_design): + assert distributed_design.topology.load_resistance == "50" + distributed_design.topology.load_resistance = "30" + assert distributed_design.topology.load_resistance == "30" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "load_resistance.ckt", "Distributed" + ) - def test_distributed_first_thin(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + def test_distributed_first_shunt(self, distributed_design): + assert distributed_design.topology.first_shunt + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "first_shunt.ckt", "Distributed" + ) + distributed_design.topology.first_shunt = False + assert distributed_design.topology.first_shunt is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "first_series.ckt", "Distributed" + ) + def test_distributed_first_fat(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.first_fat = False + distributed_design.topology.first_fat = True assert info.value.args[0] == "The First Segment Fat or Thin property is not supported for the selected topology" - design.topology.topology_list = TopologyList.STEPPED_IMPEDANCE - assert design.topology.first_fat - design.topology.first_fat = False - assert design.topology.first_fat is False - assert design.topology.circuit_response().splitlines() == read_resource_file("first_thin.ckt", "Distributed") - - def test_distributed_use_series_caps(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.topology.topology_type = TopologyType.STEPPED_IMPEDANCE + assert distributed_design.topology.first_fat + assert distributed_design.topology.netlist().splitlines() == read_resource_file("first_fat.ckt", "Distributed") + distributed_design.topology.first_fat = False + assert distributed_design.topology.first_fat is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file("first_thin.ckt", "Distributed") + def test_distributed_use_series_caps(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.use_series_caps = True + distributed_design.topology.use_series_caps = True assert info.value.args[0] == "The Series Caps property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - assert design.topology.use_series_caps is False - design.topology.use_series_caps = True - assert design.topology.use_series_caps - assert design.topology.circuit_response().splitlines() == read_resource_file( - "use_series_caps.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + assert distributed_design.topology.use_series_caps is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "use_series_caps_false.ckt", "Distributed" + ) + distributed_design.topology.use_series_caps = True + assert distributed_design.topology.use_series_caps + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "use_series_caps_true.ckt", "Distributed" ) - def test_distributed_combine_stubs(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_distributed_combine_stubs(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.combine_stubs = True + distributed_design.topology.combine_stubs = True assert info.value.args[0] == "The Combine Stubs property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - assert design.topology.combine_stubs is False - design.topology.combine_stubs = True - assert design.topology.combine_stubs - assert design.topology.circuit_response().splitlines() == read_resource_file("combine_stubs.ckt", "Distributed") - - def test_use_coupled_lines(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + assert distributed_design.topology.combine_stubs is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "combine_stubs_false.ckt", "Distributed" + ) + distributed_design.topology.combine_stubs = True + assert distributed_design.topology.combine_stubs + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "combine_stubs_true.ckt", "Distributed" + ) + def test_use_coupled_lines(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.use_coupled_lines = True + distributed_design.topology.use_coupled_lines = True assert info.value.args[0] == "The Coupled Lines property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.topology.use_coupled_lines is False - design.topology.use_coupled_lines = True - assert design.topology.use_coupled_lines - assert design.topology.circuit_response().splitlines() == read_resource_file( - "use_coupled_lines.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.attributes.filter_type = FilterType.ELLIPTIC + assert distributed_design.topology.use_coupled_lines is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "use_coupled_lines_false.ckt", "Distributed" + ) + distributed_design.topology.use_coupled_lines = True + assert distributed_design.topology.use_coupled_lines + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "use_coupled_lines_true.ckt", "Distributed" ) - def test_equal_width_approx(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_equal_width_approx(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.equal_width_approx = True + distributed_design.topology.equal_width_approx = True assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.INTERDIGITAL - assert design.topology.equal_width_approx - design.topology.equal_width_approx = False - assert design.topology.equal_width_approx is False - assert design.topology.circuit_response().splitlines() == read_resource_file( - "equal_width_approx.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.INTERDIGITAL + assert distributed_design.topology.equal_width_approx + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_width_approx_true.ckt", "Distributed" + ) + distributed_design.topology.equal_width_approx = False + assert distributed_design.topology.equal_width_approx is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_width_approx_false.ckt", "Distributed" ) - def test_open_stub_ground(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_open_stub_ground(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.open_stub_ground = True + distributed_design.topology.open_stub_ground = True assert info.value.args[0] == "The Open Stub Ground property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_STOP - design.topology.topology_list = TopologyList.NOTCH_RESONATORS - assert design.topology.open_stub_ground is False - design.topology.open_stub_ground = True - assert design.topology.open_stub_ground - design.topology.open_stub_ground = False - assert design.topology.circuit_response().splitlines() == read_resource_file( - "open_stub_ground.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_STOP + distributed_design.topology.topology_type = TopologyType.NOTCH_RESONATORS + assert distributed_design.topology.open_stub_ground is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "open_stub_ground_false.ckt", "Distributed" ) + # distributed_design.topology.open_stub_ground = True + # assert distributed_design.topology.open_stub_ground + # assert distributed_design.topology.netlist().splitlines() == read_resource_file( + # "open_stub_ground_true.ckt", "Distributed" + # ) - def test_left_ground_side(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_left_ground_side(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.left_ground_side = True + distributed_design.topology.left_ground_side = True assert info.value.args[0] == "The Left Ground Side property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_STOP - design.topology.topology_list = TopologyList.NOTCH_RESONATORS - assert design.topology.left_ground_side - design.topology.left_ground_side = False - assert design.topology.left_ground_side is False - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_STOP + distributed_design.topology.topology_type = TopologyType.NOTCH_RESONATORS + assert distributed_design.topology.left_ground_side + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "left_ground_side.ckt", "Distributed" ) + distributed_design.topology.left_ground_side = False + assert distributed_design.topology.left_ground_side is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "right_ground_side.ckt", "Distributed" + ) - def test_equal_stub_widths(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_equal_stub_widths(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.equal_stub_widths = True + distributed_design.topology.equal_stub_widths = True assert info.value.args[0] == "The Equal Stub Widths property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.SHUNT_STUB_RESONATORS - assert design.topology.equal_stub_widths is False - design.topology.equal_stub_widths = True - assert design.topology.equal_stub_widths - assert design.topology.circuit_response().splitlines() == read_resource_file( - "equal_stub_widths.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.SHUNT_STUB_RESONATORS + assert distributed_design.topology.equal_stub_widths is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_stub_widths_false.ckt", "Distributed" + ) + distributed_design.topology.equal_stub_widths = True + assert distributed_design.topology.equal_stub_widths + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_stub_widths_true.ckt", "Distributed" ) - def test_center_z0_impedance(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_center_z0_impedance_55(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.center_z0_impedance = "55" + distributed_design.topology.center_z0_impedance = "55" assert info.value.args[0] == "The Center Z0 property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.SHUNT_STUB_RESONATORS - design.topology.equal_stub_widths = False - assert design.topology.center_z0_impedance == "75" - design.topology.center_z0_impedance = "55" - assert design.topology.center_z0_impedance == "55" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.SHUNT_STUB_RESONATORS + distributed_design.topology.equal_stub_widths = False + assert distributed_design.topology.center_z0_impedance == "75" + distributed_design.topology.center_z0_impedance = "55" + assert distributed_design.topology.center_z0_impedance == "55" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "center_z0_impedance.ckt", "Distributed" ) - def test_equal_width_conductors(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_equal_width_conductors(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.equal_width_conductors = True + distributed_design.topology.equal_width_conductors = True assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.equal_width_conductors - design.topology.equal_width_conductors = False - assert design.topology.equal_width_conductors is False - assert design.topology.circuit_response().splitlines() == read_resource_file( - "equal_width_conductors.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.equal_width_conductors + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_width_conductors_true.ckt", "Distributed" + ) + distributed_design.topology.equal_width_conductors = False + assert distributed_design.topology.equal_width_conductors is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "equal_width_conductors_false.ckt", "Distributed" ) - def test_tapped(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_tapped(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.tapped = True + distributed_design.topology.tapped = True assert info.value.args[0] == "The Tapped property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.tapped - design.topology.tapped = False - assert design.topology.tapped is False - assert design.topology.circuit_response().splitlines() == read_resource_file("tapped.ckt", "Distributed") - - def test_pinned(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.tapped + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tapped_true.ckt", "Distributed" + ) + distributed_design.topology.tapped = False + assert distributed_design.topology.tapped is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tapped_false.ckt", "Distributed" + ) + def test_pinned(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.pinned = True + distributed_design.topology.pinned = True assert info.value.args[0] == "The Pinned property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.pinned is False - design.topology.pinned = True - assert design.topology.pinned - assert design.topology.equal_width_conductors is False - assert design.topology.circuit_response().splitlines() == read_resource_file("pinned.ckt", "Distributed") - - def test_stub_taps(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.pinned is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "pinned_false.ckt", "Distributed" + ) + distributed_design.topology.pinned = True + assert distributed_design.topology.pinned + # Check if the equal width conductors property is set to False when the pinned property is set to True + assert distributed_design.topology.equal_width_conductors is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "pinned_true.ckt", "Distributed" + ) + def test_stub_taps(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.stub_taps = True + distributed_design.topology.stub_taps = True assert info.value.args[0] == "The Stub Taps property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.stub_taps is False - design.topology.stub_taps = True - assert design.topology.stub_taps - assert design.topology.circuit_response().splitlines() == read_resource_file("stub_taps.ckt", "Distributed") - - def test_via_ends(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.stub_taps is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "stub_taps_false.ckt", "Distributed" + ) + distributed_design.topology.stub_taps = True + assert distributed_design.topology.stub_taps + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "stub_taps_true.ckt", "Distributed" + ) + def test_via_ends(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.via_ends = True + distributed_design.topology.via_ends = True assert info.value.args[0] == "The Via Ends property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.via_ends is False - design.topology.via_ends = True - assert design.topology.via_ends - assert design.topology.equal_width_conductors is False - assert design.topology.circuit_response().splitlines() == read_resource_file("via_ends.ckt", "Distributed") - - def test_resonator_line_width(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.via_ends is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "via_ends_false.ckt", "Distributed" + ) + distributed_design.topology.via_ends = True + assert distributed_design.topology.via_ends + # Check if the equal width conductors property is set to False when the via ends property is set to True + assert distributed_design.topology.equal_width_conductors is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "via_ends_true.ckt", "Distributed" + ) + def test_resonator_line_width_5mm(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.resonator_line_width = "1.27 mm" + distributed_design.topology.resonator_line_width = "1.27 mm" assert info.value.args[0] == "The Line Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.resonator_line_width == "1.27 mm" - design.topology.resonator_line_width = "5 mm" - assert design.topology.resonator_line_width == "5 mm" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.HAIRPIN + assert distributed_design.topology.resonator_line_width == "1.27 mm" + distributed_design.topology.resonator_line_width = "5 mm" + assert distributed_design.topology.resonator_line_width == "5 mm" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "resonator_line_width.ckt", "Distributed" ) - def test_resonator_rotation_angle(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_resonator_rotation_angle_5deg(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.resonator_rotation_angle = "0" + distributed_design.topology.resonator_rotation_angle = "0" assert info.value.args[0] == "The Rotation Angle property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.PARALLEL_EDGE_COUPLED - assert design.topology.resonator_rotation_angle == "0" - design.topology.resonator_rotation_angle = "5" - assert design.topology.resonator_rotation_angle == "5" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED + assert distributed_design.topology.resonator_rotation_angle == "0" + distributed_design.topology.resonator_rotation_angle = "5" + assert distributed_design.topology.resonator_rotation_angle == "5" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "resonator_rotation_angle.ckt", "Distributed" ) - def test_mitered_corners(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_mitered_corners(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.mitered_corners = True + distributed_design.topology.mitered_corners = True assert info.value.args[0] == "The Mitered Corners property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.mitered_corners is False - design.topology.mitered_corners = True - assert design.topology.mitered_corners - assert design.topology.circuit_response().splitlines() == read_resource_file( - "mitered_corners.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.HAIRPIN + assert distributed_design.topology.mitered_corners is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "mitered_corners_false.ckt", "Distributed" + ) + distributed_design.topology.mitered_corners = True + assert distributed_design.topology.mitered_corners + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "mitered_corners_true.ckt", "Distributed" ) - def test_hairpin_gap_width(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_hairpin_gap_width_4mm(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.hairpin_gap_width = "0.127 mm" + distributed_design.topology.hairpin_gap_width = "0.127 mm" assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.hairpin_gap_width == "2.54 mm" - design.topology.hairpin_gap_width = "4 mm" - assert design.topology.hairpin_gap_width == "4 mm" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.HAIRPIN + assert distributed_design.topology.hairpin_gap_width == "2.54 mm" + distributed_design.topology.hairpin_gap_width = "4 mm" + assert distributed_design.topology.hairpin_gap_width == "4 mm" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "hairpin_gap_width.ckt", "Distributed" ) - def test_miniature_hairpin_gap_width(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_miniature_hairpin_gap_width_450um(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.miniature_hairpin_gap_width = "635 um" + distributed_design.topology.miniature_hairpin_gap_width = "635 um" assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN - assert design.topology.miniature_hairpin_gap_width == "635 um" - design.topology.miniature_hairpin_gap_width = "450 um" - assert design.topology.miniature_hairpin_gap_width == "450 um" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN + assert distributed_design.topology.miniature_hairpin_gap_width == "635 um" + distributed_design.topology.miniature_hairpin_gap_width = "450 um" + assert distributed_design.topology.miniature_hairpin_gap_width == "450 um" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "miniature_hairpin_gap_width.ckt", "Distributed" ) - def test_ring_resonator_gap_width(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_ring_resonator_gap_width_450um(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.ring_resonator_gap_width = "635 um" + distributed_design.topology.ring_resonator_gap_width = "635 um" assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.RING_RESONATOR - assert design.topology.ring_resonator_gap_width == "635 um" - design.topology.ring_resonator_gap_width = "450 um" - assert design.topology.ring_resonator_gap_width == "450 um" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.RING_RESONATOR + assert distributed_design.topology.ring_resonator_gap_width == "635 um" + distributed_design.topology.ring_resonator_gap_width = "450 um" + assert distributed_design.topology.ring_resonator_gap_width == "450 um" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "ring_resonator_gap_width.ckt", "Distributed" ) - def test_hairpin_extension_length(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_hairpin_extension_length_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.hairpin_extension_length = "0 mm" + distributed_design.topology.hairpin_extension_length = "0 mm" assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.hairpin_extension_length == "0 um" - design.topology.hairpin_extension_length = "2 mm" - assert design.topology.hairpin_extension_length == "2 mm" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.HAIRPIN + assert distributed_design.topology.hairpin_extension_length == "0 um" + distributed_design.topology.hairpin_extension_length = "2 mm" + assert distributed_design.topology.hairpin_extension_length == "2 mm" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "hairpin_extension_length.ckt", "Distributed" ) - def test_miniature_hairpin_end_curl_extension(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_miniature_hairpin_end_curl_extension_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.miniature_hairpin_end_curl_extension = "0 mm" + distributed_design.topology.miniature_hairpin_end_curl_extension = "0 mm" assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN - assert design.topology.miniature_hairpin_end_curl_extension == "0 um" - design.topology.miniature_hairpin_end_curl_extension = "2 mm" - assert design.topology.miniature_hairpin_end_curl_extension == "2 mm" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN + assert distributed_design.topology.miniature_hairpin_end_curl_extension == "0 um" + distributed_design.topology.miniature_hairpin_end_curl_extension = "2 mm" + assert distributed_design.topology.miniature_hairpin_end_curl_extension == "2 mm" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "miniature_hairpin_end_curl_extension.ckt", "Distributed" ) - def test_ring_resonator_end_gap_extension(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_ring_resonator_end_gap_extension_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.ring_resonator_end_gap_extension = "0 mm" + distributed_design.topology.ring_resonator_end_gap_extension = "0 mm" assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.RING_RESONATOR - assert design.topology.ring_resonator_end_gap_extension == "0 um" - design.topology.ring_resonator_end_gap_extension = "2 mm" - assert design.topology.ring_resonator_end_gap_extension == "2 mm" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.RING_RESONATOR + assert distributed_design.topology.ring_resonator_end_gap_extension == "0 um" + distributed_design.topology.ring_resonator_end_gap_extension = "2 mm" + assert distributed_design.topology.ring_resonator_end_gap_extension == "2 mm" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "ring_resonator_end_gap_extension.ckt", "Distributed" ) - def test_tuning_type_1(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_tuning_type_1(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.tuning_type_1 = True + distributed_design.topology.tuning_type_1 = True assert info.value.args[0] == "The Tuning Type property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.tuning_type_1 - design.topology.tuning_type_1 = False - assert design.topology.tuning_type_1 is False - assert design.topology.circuit_response().splitlines() == read_resource_file("tuning_type_1.ckt", "Distributed") - - def test_tuning_type_2(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - - with pytest.raises(RuntimeError) as info: - design.topology.tuning_type_1 = True - assert info.value.args[0] == "The Tuning Type property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.HAIRPIN - assert design.topology.tuning_type_1 - assert design.topology.circuit_response().splitlines() == read_resource_file("tuning_type_2.ckt", "Distributed") - - def test_tap_position(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.HAIRPIN + assert distributed_design.topology.tuning_type_1 + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tuning_type_1.ckt", "Distributed" + ) + distributed_design.topology.tuning_type_1 = False + assert distributed_design.topology.tuning_type_1 is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tuning_type_2.ckt", "Distributed" + ) + def test_tap_position(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.tap_position = TapPosition.AUTO + distributed_design.topology.tap_position = TapPosition.AUTO assert info.value.args[0] == "The Tap Position property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.MINIATURE_HAIRPIN - assert design.topology.tap_position == TapPosition.AUTO - design.topology.tap_position = TapPosition.SIDES - assert design.topology.tap_position == TapPosition.SIDES - assert design.topology.circuit_response().splitlines() == read_resource_file("tap_position.ckt", "Distributed") - - def test_wide_band(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN + assert distributed_design.topology.tap_position == TapPosition.AUTO + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tap_position_auto.ckt", "Distributed" + ) + distributed_design.topology.tap_position = TapPosition.SIDES + assert distributed_design.topology.tap_position == TapPosition.SIDES + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "tap_position_sides.ckt", "Distributed" + ) + def test_wide_band(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.wide_band = True + distributed_design.topology.wide_band = True assert info.value.args[0] == "The Wide Band property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.INTERDIGITAL - assert design.topology.wide_band is False - design.topology.wide_band = True - design.topology.pinned = True - assert design.topology.wide_band - assert design.topology.circuit_response().splitlines() == read_resource_file("wide_band.ckt", "Distributed") - - def test_open_ends(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.INTERDIGITAL + assert distributed_design.topology.wide_band is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "wide_band_false.ckt", "Distributed" + ) + distributed_design.topology.wide_band = True + # To have a wide band filter, the pinned property must be set to True + distributed_design.topology.pinned = True + assert distributed_design.topology.wide_band + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "wide_band_true.ckt", "Distributed" + ) + def test_open_ends(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.open_ends = True + distributed_design.topology.open_ends = True assert info.value.args[0] == "The Open Ends property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.INTERDIGITAL - assert design.topology.open_ends is False - design.topology.open_ends = True - assert design.topology.open_ends - assert design.topology.circuit_response().splitlines() == read_resource_file("open_ends.ckt", "Distributed") - - def test_combline_half_length_frequency(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.INTERDIGITAL + assert distributed_design.topology.open_ends is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "open_ends_false.ckt", "Distributed" + ) + distributed_design.topology.open_ends = True + assert distributed_design.topology.open_ends + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "open_ends_true.ckt", "Distributed" + ) + def test_combline_half_length_frequency_2ghz(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.combline_half_length_frequency = "4G" + distributed_design.topology.combline_half_length_frequency = "4G" assert info.value.args[0] == "The 1/2 Length Frequency property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.COMBLINE - assert design.topology.combline_half_length_frequency == "4G" - design.topology.combline_half_length_frequency = "2 GHz" - assert design.topology.combline_half_length_frequency == "2 GHz" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.COMBLINE + assert distributed_design.topology.combline_half_length_frequency == "4G" + distributed_design.topology.combline_half_length_frequency = "2 GHz" + assert distributed_design.topology.combline_half_length_frequency == "2 GHz" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "combline_half_length_frequency.ckt", "Distributed" ) - def test_coupled_segments_quarter_length_frequency(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - + def test_coupled_segments_quarter_length_frequency_2ghz(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.coupled_segments_quarter_length_frequency = "4G" + distributed_design.topology.coupled_segments_quarter_length_frequency = "4G" assert info.value.args[0] == "The 1/4 Length Frequency property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.HIGH_PASS - design.topology.topology_list = TopologyList.COUPLED_SEGMENTS - assert design.topology.coupled_segments_quarter_length_frequency == "4G" - design.topology.coupled_segments_quarter_length_frequency = "2 GHz" - assert design.topology.coupled_segments_quarter_length_frequency == "2 GHz" - assert design.topology.circuit_response().splitlines() == read_resource_file( + distributed_design.attributes.filter_class = FilterClass.HIGH_PASS + distributed_design.topology.topology_type = TopologyType.COUPLED_SEGMENTS + assert distributed_design.topology.coupled_segments_quarter_length_frequency == "4G" + distributed_design.topology.coupled_segments_quarter_length_frequency = "2 GHz" + assert distributed_design.topology.coupled_segments_quarter_length_frequency == "2 GHz" + assert distributed_design.topology.netlist().splitlines() == read_resource_file( "coupled_segments_quarter_length_frequency.ckt", "Distributed" ) - def test_circuit_response(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - assert design.topology.circuit_response().splitlines() == read_resource_file("default.ckt", "Distributed") + def test_netlist(self, distributed_design): + assert distributed_design.topology.netlist().splitlines() == read_resource_file("default.ckt", "Distributed") - def test_quick_optimize(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) - assert design.topology.quick_optimize is False - design.topology.quick_optimize = True - assert design.topology.quick_optimize - assert design.topology.circuit_response().splitlines() == read_resource_file( - "quick_optimize.ckt", "Distributed" + def test_quick_optimize(self, distributed_design): + assert distributed_design.topology.quick_optimize is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "quick_optimize_false.ckt", "Distributed" + ) + distributed_design.topology.quick_optimize = True + assert distributed_design.topology.quick_optimize + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "quick_optimize_true.ckt", "Distributed" ) - def test_resonator_length_extension(self): - design = ansys.aedt.core.filtersolutions.DistributedDesign(config["desktopVersion"]) + def test_resonator_length_extension(self, distributed_design): with pytest.raises(RuntimeError) as info: - design.topology.resonator_length_extension = True + distributed_design.topology.resonator_length_extension = True assert info.value.args[0] == "The Enable Extension property is not supported for the selected topology" - design.attributes.filter_class = FilterClass.BAND_PASS - design.topology.topology_list = TopologyList.INTERDIGITAL - assert design.topology.resonator_length_extension is False - design.topology.resonator_length_extension = True - assert design.topology.resonator_length_extension - assert design.topology.circuit_response().splitlines() == read_resource_file( - "resonator_length_extension.ckt", "Distributed" + distributed_design.attributes.filter_class = FilterClass.BAND_PASS + distributed_design.topology.topology_type = TopologyType.INTERDIGITAL + assert distributed_design.topology.resonator_length_extension is False + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "resonator_length_extension_false.ckt", "Distributed" + ) + distributed_design.topology.resonator_length_extension = True + assert distributed_design.topology.resonator_length_extension + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "resonator_length_extension_true.ckt", "Distributed" ) diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py index e2920157880..dd219200d79 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_attributes.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import BesselRipplePercentage from ansys.aedt.core.filtersolutions_core.attributes import DiplexerType from ansys.aedt.core.filtersolutions_core.attributes import FilterClass @@ -43,19 +41,15 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_filter_type(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.filter_type == FilterType.BUTTERWORTH + def test_filter_type(self, lumped_design): + assert lumped_design.attributes.filter_type == FilterType.BUTTERWORTH assert len(FilterType) == 10 for ftype in FilterType: - design.attributes.filter_type = ftype - assert design.attributes.filter_type == ftype - - def test_filter_class(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.attributes.filter_type = ftype + assert lumped_design.attributes.filter_type == ftype - assert design.attributes.filter_class == FilterClass.LOW_PASS + def test_filter_class(self, lumped_design): + assert lumped_design.attributes.filter_class == FilterClass.LOW_PASS # Only lumped supports all classes # TODO: Confirm proper exceptions are raised when setting unsupported filter class for each implementation. @@ -63,489 +57,379 @@ def test_filter_class(self): assert len(FilterClass) == 10 for index, fclass in enumerate(FilterClass): if index > 5: - design.attributes.filter_multiple_bands_enabled = True - design.attributes.filter_class = fclass - assert design.attributes.filter_class == fclass - - def test_filter_multiple_bands_enabled(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.filter_multiple_bands_enabled is False - design.attributes.filter_multiple_bands_enabled = True - assert design.attributes.filter_multiple_bands_enabled - - def test_filter_multiple_bands_low_pass_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - design.attributes.filter_class = FilterClass.LOW_BAND - assert design.attributes.filter_multiple_bands_low_pass_frequency == "1G" - design.attributes.filter_multiple_bands_low_pass_frequency = "500M" - assert design.attributes.filter_multiple_bands_low_pass_frequency == "500M" - - def test_filter_multiple_bands_high_pass_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - design.attributes.filter_class = FilterClass.BAND_HIGH - assert design.attributes.filter_multiple_bands_high_pass_frequency == "1G" - design.attributes.filter_multiple_bands_high_pass_frequency = "500M" - assert design.attributes.filter_multiple_bands_high_pass_frequency == "500M" - - def test_diplexer_type(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.attributes.filter_class = fclass + assert lumped_design.attributes.filter_class == fclass + + def test_filter_multiple_bands_enabled(self, lumped_design): + assert lumped_design.attributes.filter_multiple_bands_enabled is False + lumped_design.attributes.filter_multiple_bands_enabled = True + assert lumped_design.attributes.filter_multiple_bands_enabled + + def test_filter_multiple_bands_low_pass_frequency(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.attributes.filter_class = FilterClass.LOW_BAND + assert lumped_design.attributes.filter_multiple_bands_low_pass_frequency == "1G" + lumped_design.attributes.filter_multiple_bands_low_pass_frequency = "500M" + assert lumped_design.attributes.filter_multiple_bands_low_pass_frequency == "500M" + + def test_filter_multiple_bands_high_pass_frequency(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.attributes.filter_class = FilterClass.BAND_HIGH + assert lumped_design.attributes.filter_multiple_bands_high_pass_frequency == "1G" + lumped_design.attributes.filter_multiple_bands_high_pass_frequency = "500M" + assert lumped_design.attributes.filter_multiple_bands_high_pass_frequency == "500M" + + def test_diplexer_type(self, lumped_design): assert len(DiplexerType) == 6 for index, diplexer_type in enumerate(DiplexerType): if index < 3: - design.attributes.filter_class = FilterClass.DIPLEXER_1 + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 elif index > 2: - design.attributes.filter_class = FilterClass.DIPLEXER_2 - design.attributes.diplexer_type = diplexer_type - assert design.attributes.diplexer_type == diplexer_type - - def test_filter_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.filter_order == 5 + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_2 + lumped_design.attributes.diplexer_type = diplexer_type + assert lumped_design.attributes.diplexer_type == diplexer_type + def test_filter_order(self, lumped_design): + assert lumped_design.attributes.filter_order == 5 with pytest.raises(RuntimeError) as info: - design.attributes.filter_order = 0 + lumped_design.attributes.filter_order = 0 assert info.value.args[0] == "The minimum order is 1" for i in range(1, 22): - design.attributes.filter_order = i - assert design.attributes.filter_order == i + lumped_design.attributes.filter_order = i + assert lumped_design.attributes.filter_order == i with pytest.raises(RuntimeError) as info: - design.attributes.filter_order = 22 + lumped_design.attributes.filter_order = 22 assert info.value.args[0] == "The maximum order is 21" - def test_minimum_order_stop_band_att(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.minimum_order_stop_band_attenuation_db == "60 dB" - design.attributes.minimum_order_stop_band_attenuation_db = "40 dB" - assert design.attributes.minimum_order_stop_band_attenuation_db == "40 dB" - - def test_minimum_order_stop_band_freq(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.minimum_order_stop_band_frequency == "10 GHz" - design.attributes.minimum_order_stop_band_frequency = "500 MHz" - assert design.attributes.minimum_order_stop_band_frequency == "500 MHz" - - def test_minimum_order_group_delay_error_percent(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.DELAY - assert design.attributes.minimum_order_group_delay_error_percent == "5" - design.attributes.minimum_order_group_delay_error_percent = "7" - assert design.attributes.minimum_order_group_delay_error_percent == "7" - - def test_minimum_order_group_delay_cutoff(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.DELAY - assert design.attributes.minimum_order_group_delay_cutoff == "2 GHz" - design.attributes.minimum_order_group_delay_cutoff = "500 MHz" - assert design.attributes.minimum_order_group_delay_cutoff == "500 MHz" - - def test_minimum_order_stop_band_freq(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.minimum_order_stop_band_frequency == "10 GHz" - design.attributes.minimum_order_stop_band_frequency = "500 MHz" - assert design.attributes.minimum_order_stop_band_frequency == "500 MHz" - - def test_minimum_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.filter_order == 5 - design.attributes.ideal_minimum_order - assert design.attributes.filter_order == 3 - - def test_pass_band_definition(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS + def test_minimum_order_stop_band_att(self, lumped_design): + assert lumped_design.attributes.minimum_order_stop_band_attenuation_db == "60 dB" + lumped_design.attributes.minimum_order_stop_band_attenuation_db = "40 dB" + assert lumped_design.attributes.minimum_order_stop_band_attenuation_db == "40 dB" + + def test_minimum_order_stop_band_freq(self, lumped_design): + assert lumped_design.attributes.minimum_order_stop_band_frequency == "10 GHz" + lumped_design.attributes.minimum_order_stop_band_frequency = "500 MHz" + assert lumped_design.attributes.minimum_order_stop_band_frequency == "500 MHz" + + def test_minimum_order_group_delay_error_percent(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.DELAY + assert lumped_design.attributes.minimum_order_group_delay_error_percent == "5" + lumped_design.attributes.minimum_order_group_delay_error_percent = "7" + assert lumped_design.attributes.minimum_order_group_delay_error_percent == "7" + + def test_minimum_order_group_delay_cutoff(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.DELAY + assert lumped_design.attributes.minimum_order_group_delay_cutoff == "2 GHz" + lumped_design.attributes.minimum_order_group_delay_cutoff = "500 MHz" + assert lumped_design.attributes.minimum_order_group_delay_cutoff == "500 MHz" + + def test_minimum_order(self, lumped_design): + assert lumped_design.attributes.filter_order == 5 + lumped_design.attributes.ideal_minimum_order + assert lumped_design.attributes.filter_order == 3 + + def test_pass_band_definition(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS assert len(PassbandDefinition) == 2 - assert design.attributes.pass_band_definition == PassbandDefinition.CENTER_FREQUENCY + assert lumped_design.attributes.pass_band_definition == PassbandDefinition.CENTER_FREQUENCY for pbd in PassbandDefinition: - design.attributes.pass_band_definition = pbd - assert design.attributes.pass_band_definition == pbd - - def test_pass_band_center_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.pass_band_center_frequency == "1G" - design.attributes.pass_band_center_frequency = "500M" - assert design.attributes.pass_band_center_frequency == "500M" - - def test_pass_band_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - assert design.attributes.pass_band_width_frequency == "200M" - design.attributes.pass_band_width_frequency = "500M" - assert design.attributes.pass_band_width_frequency == "500M" - - def test_lower_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES - assert design.attributes.lower_frequency == "905 M" - design.attributes.lower_frequency = "800M" - assert design.attributes.lower_frequency == "800M" - - def test_upper_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES - assert design.attributes.upper_frequency == "1.105 G" - design.attributes.upper_frequency = "1.2 G" - assert design.attributes.upper_frequency == "1.2 G" - - def test_stop_band_definition(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.pass_band_definition = pbd + assert lumped_design.attributes.pass_band_definition == pbd + + def test_pass_band_center_frequency(self, lumped_design): + assert lumped_design.attributes.pass_band_center_frequency == "1G" + lumped_design.attributes.pass_band_center_frequency = "500M" + assert lumped_design.attributes.pass_band_center_frequency == "500M" + + def test_pass_band_frequency(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.pass_band_width_frequency == "200M" + lumped_design.attributes.pass_band_width_frequency = "500M" + assert lumped_design.attributes.pass_band_width_frequency == "500M" + + def test_lower_frequency(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES + assert lumped_design.attributes.lower_frequency == "905 M" + lumped_design.attributes.lower_frequency = "800M" + assert lumped_design.attributes.lower_frequency == "800M" + + def test_upper_frequency(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.pass_band_definition = PassbandDefinition.CORNER_FREQUENCIES + assert lumped_design.attributes.upper_frequency == "1.105 G" + lumped_design.attributes.upper_frequency = "1.2 G" + assert lumped_design.attributes.upper_frequency == "1.2 G" + + def test_stop_band_definition(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC assert len(StopbandDefinition) == 3 - assert design.attributes.stop_band_definition == StopbandDefinition.RATIO + assert lumped_design.attributes.stop_band_definition == StopbandDefinition.RATIO for sbd in StopbandDefinition: - design.attributes.stop_band_definition = sbd - assert design.attributes.stop_band_definition == sbd - - def test_stop_band_ratio(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.attributes.stop_band_ratio == "1.2" - design.attributes.stop_band_ratio = "1.5" - assert design.attributes.stop_band_ratio == "1.5" - - def test_stop_band_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.stop_band_definition = StopbandDefinition.FREQUENCY - assert design.attributes.stop_band_frequency == "1.2 G" - design.attributes.stop_band_frequency = "1.5 G" - assert design.attributes.stop_band_frequency == "1.5 G" - - def test_stop_band_attenuation(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.stop_band_definition = StopbandDefinition.ATTENUATION_DB - assert design.attributes.stop_band_attenuation_db == "60" - design.attributes.stop_band_attenuation_db = "40 dB" - assert design.attributes.stop_band_attenuation_db == "40" - - def test_standard_pass_band_attenuation(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.attributes.standard_pass_band_attenuation - design.attributes.standard_pass_band_attenuation = False - assert design.attributes.standard_pass_band_attenuation is False - - def test_standard_pass_band_attenuation_value_db(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.standard_pass_band_attenuation = False - assert design.attributes.standard_pass_band_attenuation_value_db == "3.01" - design.attributes.standard_pass_band_attenuation_value_db = "4" - assert design.attributes.standard_pass_band_attenuation_value_db == "4" - - def test_equiripple_delay(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.DELAY - assert design.attributes.equiripple_delay - design.attributes.equiripple_delay = False - assert design.attributes.equiripple_delay is False - - def test_group_delay_ripple_period(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.DELAY - assert design.attributes.group_delay_ripple_period == "2" - design.attributes.group_delay_ripple_period = "3" - assert design.attributes.group_delay_ripple_period == "3" - - def test_normalized_group_delay_percentage(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.DELAY + lumped_design.attributes.stop_band_definition = sbd + assert lumped_design.attributes.stop_band_definition == sbd + + def test_stop_band_ratio(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.stop_band_ratio == "1.2" + lumped_design.attributes.stop_band_ratio = "1.5" + assert lumped_design.attributes.stop_band_ratio == "1.5" + + def test_stop_band_frequency(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.stop_band_definition = StopbandDefinition.FREQUENCY + assert lumped_design.attributes.stop_band_frequency == "1.2 G" + lumped_design.attributes.stop_band_frequency = "1.5 G" + assert lumped_design.attributes.stop_band_frequency == "1.5 G" + + def test_stop_band_attenuation(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.stop_band_definition = StopbandDefinition.ATTENUATION_DB + assert lumped_design.attributes.stop_band_attenuation_db == "60" + lumped_design.attributes.stop_band_attenuation_db = "40 dB" + assert lumped_design.attributes.stop_band_attenuation_db == "40" + + def test_standard_pass_band_attenuation(self, lumped_design): + assert lumped_design.attributes.standard_pass_band_attenuation + lumped_design.attributes.standard_pass_band_attenuation = False + assert lumped_design.attributes.standard_pass_band_attenuation is False + + def test_standard_pass_band_attenuation_value_db(self, lumped_design): + lumped_design.attributes.standard_pass_band_attenuation = False + assert lumped_design.attributes.standard_pass_band_attenuation_value_db == "3.01" + lumped_design.attributes.standard_pass_band_attenuation_value_db = "4" + assert lumped_design.attributes.standard_pass_band_attenuation_value_db == "4" + + def test_equiripple_delay(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.DELAY + assert lumped_design.attributes.equiripple_delay + lumped_design.attributes.equiripple_delay = False + assert lumped_design.attributes.equiripple_delay is False + + def test_group_delay_ripple_period(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.DELAY + assert lumped_design.attributes.group_delay_ripple_period == "2" + lumped_design.attributes.group_delay_ripple_period = "3" + assert lumped_design.attributes.group_delay_ripple_period == "3" + + def test_normalized_group_delay_percentage(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.DELAY assert len(BesselRipplePercentage) == 6 for normalized_group_delay_percentage in BesselRipplePercentage: - design.attributes.normalized_group_delay_percentage = normalized_group_delay_percentage - assert design.attributes.normalized_group_delay_percentage == normalized_group_delay_percentage - - def test_bessel_normalized_delay(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.BESSEL - assert design.attributes.bessel_normalized_delay is False - design.attributes.bessel_normalized_delay = True - assert design.attributes.bessel_normalized_delay - - def test_bessel_normalized_delay_period(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.BESSEL - design.attributes.bessel_normalized_delay = True - assert design.attributes.bessel_normalized_delay_period == "2" - design.attributes.bessel_normalized_delay_period = "3" - assert design.attributes.bessel_normalized_delay_period == "3" - - def test_bessel_normalized_delay_percentage(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.BESSEL - design.attributes.bessel_normalized_delay = True + lumped_design.attributes.normalized_group_delay_percentage = normalized_group_delay_percentage + assert lumped_design.attributes.normalized_group_delay_percentage == normalized_group_delay_percentage + + def test_bessel_normalized_delay(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.BESSEL + assert lumped_design.attributes.bessel_normalized_delay is False + lumped_design.attributes.bessel_normalized_delay = True + assert lumped_design.attributes.bessel_normalized_delay + + def test_bessel_normalized_delay_period(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.BESSEL + lumped_design.attributes.bessel_normalized_delay = True + assert lumped_design.attributes.bessel_normalized_delay_period == "2" + lumped_design.attributes.bessel_normalized_delay_period = "3" + assert lumped_design.attributes.bessel_normalized_delay_period == "3" + + def test_bessel_normalized_delay_percentage(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.BESSEL + lumped_design.attributes.bessel_normalized_delay = True assert len(BesselRipplePercentage) == 6 for bessel_normalized_delay_percentage in BesselRipplePercentage: - design.attributes.bessel_normalized_delay_percentage = bessel_normalized_delay_percentage - assert design.attributes.bessel_normalized_delay_percentage == bessel_normalized_delay_percentage - - def test_pass_band_ripple(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.attributes.pass_band_ripple == ".05" - design.attributes.pass_band_ripple = ".03" - assert design.attributes.pass_band_ripple == ".03" - - def test_arith_symmetry(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.filter_class = FilterClass.BAND_PASS - assert design.attributes.arith_symmetry is False - design.attributes.arith_symmetry = True - assert design.attributes.arith_symmetry - - def test_asymmetric(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - assert design.attributes.asymmetric is False - design.attributes.asymmetric = True - assert design.attributes.asymmetric - - def test_asymmetric_low_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.asymmetric = True - assert design.attributes.asymmetric_low_order == 5 + lumped_design.attributes.bessel_normalized_delay_percentage = bessel_normalized_delay_percentage + assert lumped_design.attributes.bessel_normalized_delay_percentage == bessel_normalized_delay_percentage + + def test_pass_band_ripple(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.pass_band_ripple == ".05" + lumped_design.attributes.pass_band_ripple = ".03" + assert lumped_design.attributes.pass_band_ripple == ".03" + + def test_arith_symmetry(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.arith_symmetry is False + lumped_design.attributes.arith_symmetry = True + assert lumped_design.attributes.arith_symmetry + + def test_asymmetric(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.asymmetric is False + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric + + def test_asymmetric_low_order(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_low_order == 5 with pytest.raises(RuntimeError) as info: - design.attributes.asymmetric_low_order = 0 + lumped_design.attributes.asymmetric_low_order = 0 assert info.value.args[0] == "The minimum order is 1" for i in range(1, 22): - design.attributes.asymmetric_low_order = i - assert design.attributes.asymmetric_low_order == i + lumped_design.attributes.asymmetric_low_order = i + assert lumped_design.attributes.asymmetric_low_order == i with pytest.raises(RuntimeError) as info: - design.attributes.asymmetric_low_order = 22 + lumped_design.attributes.asymmetric_low_order = 22 assert info.value.args[0] == "The maximum order is 21" - def test_asymmetric_high_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.asymmetric = True - assert design.attributes.asymmetric_high_order == 5 + def test_asymmetric_high_order(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_high_order == 5 with pytest.raises(RuntimeError) as info: - design.attributes.asymmetric_high_order = 0 + lumped_design.attributes.asymmetric_high_order = 0 assert info.value.args[0] == "The minimum order is 1" for i in range(1, 22): - design.attributes.asymmetric_high_order = i - assert design.attributes.asymmetric_high_order == i + lumped_design.attributes.asymmetric_high_order = i + assert lumped_design.attributes.asymmetric_high_order == i with pytest.raises(RuntimeError) as info: - design.attributes.asymmetric_high_order = 22 + lumped_design.attributes.asymmetric_high_order = 22 assert info.value.args[0] == "The maximum order is 21" - def test_asymmetric_low_stop_band_ratio(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.asymmetric = True - assert design.attributes.asymmetric_low_stop_band_ratio == "1.2" - design.attributes.asymmetric_low_stop_band_ratio = "1.5" - assert design.attributes.asymmetric_low_stop_band_ratio == "1.5" - - def test_asymmetric_high_stop_band_ratio(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.asymmetric = True - assert design.attributes.asymmetric_high_stop_band_ratio == "1.2" - design.attributes.asymmetric_high_stop_band_ratio = "1.5" - assert design.attributes.asymmetric_high_stop_band_ratio == "1.5" - - def test_asymmetric_low_stop_band_attenuation_db(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.asymmetric = True - assert design.attributes.asymmetric_low_stop_band_attenuation_db == "60" - design.attributes.asymmetric_low_stop_band_attenuation_db = "40" - assert design.attributes.asymmetric_low_stop_band_attenuation_db == "40" - - def test_asymmetric_high_stop_band_attenuation_db(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_class = FilterClass.BAND_PASS - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.asymmetric = True - assert design.attributes.asymmetric_high_stop_band_attenuation_db == "60" - design.attributes.asymmetric_high_stop_band_attenuation_db = "40" - assert design.attributes.asymmetric_high_stop_band_attenuation_db == "40" - - def test_gaussian_transition(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.GAUSSIAN + def test_asymmetric_low_stop_band_ratio(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_low_stop_band_ratio == "1.2" + lumped_design.attributes.asymmetric_low_stop_band_ratio = "1.5" + assert lumped_design.attributes.asymmetric_low_stop_band_ratio == "1.5" + + def test_asymmetric_high_stop_band_ratio(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_high_stop_band_ratio == "1.2" + lumped_design.attributes.asymmetric_high_stop_band_ratio = "1.5" + assert lumped_design.attributes.asymmetric_high_stop_band_ratio == "1.5" + + def test_asymmetric_low_stop_band_attenuation_db(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_low_stop_band_attenuation_db == "60" + lumped_design.attributes.asymmetric_low_stop_band_attenuation_db = "40" + assert lumped_design.attributes.asymmetric_low_stop_band_attenuation_db == "40" + + def test_asymmetric_high_stop_band_attenuation_db(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.asymmetric = True + assert lumped_design.attributes.asymmetric_high_stop_band_attenuation_db == "60" + lumped_design.attributes.asymmetric_high_stop_band_attenuation_db = "40" + assert lumped_design.attributes.asymmetric_high_stop_band_attenuation_db == "40" + + def test_gaussian_transition(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.GAUSSIAN assert len(GaussianTransition) == 6 for gaussian_transition in GaussianTransition: - design.attributes.gaussian_transition = gaussian_transition - assert design.attributes.gaussian_transition == gaussian_transition - - def test_gaussian_bessel_reflection(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.attributes.gaussian_transition = gaussian_transition + assert lumped_design.attributes.gaussian_transition == gaussian_transition - design.attributes.filter_type = FilterType.BESSEL + def test_gaussian_bessel_reflection(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.BESSEL assert len(GaussianBesselReflection) == 3 for gaussian_bessel_reflection in GaussianBesselReflection: - design.attributes.gaussian_bessel_reflection = gaussian_bessel_reflection - assert design.attributes.gaussian_bessel_reflection == gaussian_bessel_reflection - - def test_even_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.filter_order = 4 - assert design.attributes.even_order - design.attributes.even_order = False - assert design.attributes.even_order is False - - def test_even_order_refl_zero(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.filter_order = 4 - assert design.attributes.even_order_refl_zero - design.attributes.even_order_refl_zero = False - assert design.attributes.even_order_refl_zero is False - - def test_even_order_trn_zero(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.filter_order = 4 - assert design.attributes.even_order_trn_zero - design.attributes.even_order_trn_zero = False - assert design.attributes.even_order_trn_zero is False - - def test_constrict_ripple(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.attributes.constrict_ripple is False - design.attributes.constrict_ripple = True - assert design.attributes.constrict_ripple - - def test_single_point_ripple(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.attributes.single_point_ripple is False - design.attributes.single_point_ripple = True - assert design.attributes.single_point_ripple - - def test_half_band_ripple(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - assert design.attributes.half_band_ripple is False - design.attributes.half_band_ripple = True - assert design.attributes.half_band_ripple - - def test_constrict_ripple_percent(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.constrict_ripple = True - assert design.attributes.constrict_ripple_percent == "50%" - design.attributes.constrict_ripple_percent = "40%" - assert design.attributes.constrict_ripple_percent == "40%" - - def test_ripple_constriction_band(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.constrict_ripple = True + lumped_design.attributes.gaussian_bessel_reflection = gaussian_bessel_reflection + assert lumped_design.attributes.gaussian_bessel_reflection == gaussian_bessel_reflection + + def test_even_order(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.filter_order = 4 + assert lumped_design.attributes.even_order + lumped_design.attributes.even_order = False + assert lumped_design.attributes.even_order is False + + def test_even_order_refl_zero(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.filter_order = 4 + assert lumped_design.attributes.even_order_refl_zero + lumped_design.attributes.even_order_refl_zero = False + assert lumped_design.attributes.even_order_refl_zero is False + + def test_even_order_trn_zero(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.filter_order = 4 + assert lumped_design.attributes.even_order_trn_zero + lumped_design.attributes.even_order_trn_zero = False + assert lumped_design.attributes.even_order_trn_zero is False + + def test_constrict_ripple(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.constrict_ripple is False + lumped_design.attributes.constrict_ripple = True + assert lumped_design.attributes.constrict_ripple + + def test_single_point_ripple(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.single_point_ripple is False + lumped_design.attributes.single_point_ripple = True + assert lumped_design.attributes.single_point_ripple + + def test_half_band_ripple(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.half_band_ripple is False + lumped_design.attributes.half_band_ripple = True + assert lumped_design.attributes.half_band_ripple + + def test_constrict_ripple_percent(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.constrict_ripple = True + assert lumped_design.attributes.constrict_ripple_percent == "50%" + lumped_design.attributes.constrict_ripple_percent = "40%" + assert lumped_design.attributes.constrict_ripple_percent == "40%" + + def test_ripple_constriction_band(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.constrict_ripple = True assert len(RippleConstrictionBandSelect) == 3 for ripple_constriction_band in RippleConstrictionBandSelect: - design.attributes.ripple_constriction_band = ripple_constriction_band - assert design.attributes.ripple_constriction_band == ripple_constriction_band + lumped_design.attributes.ripple_constriction_band = ripple_constriction_band + assert lumped_design.attributes.ripple_constriction_band == ripple_constriction_band - def test_single_point_ripple_inf_zeros(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_type = FilterType.ELLIPTIC - design.attributes.single_point_ripple = True + def test_single_point_ripple_inf_zeros(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.attributes.single_point_ripple = True assert len(SinglePointRippleInfZeros) == 2 for single_point_ripple_inf_zeros in SinglePointRippleInfZeros: - design.attributes.single_point_ripple_inf_zeros = single_point_ripple_inf_zeros - assert design.attributes.single_point_ripple_inf_zeros == single_point_ripple_inf_zeros - - def test_delay_equalizer(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.attributes.single_point_ripple_inf_zeros = single_point_ripple_inf_zeros + assert lumped_design.attributes.single_point_ripple_inf_zeros == single_point_ripple_inf_zeros - assert design.attributes.delay_equalizer is False - design.attributes.delay_equalizer = True - assert design.attributes.delay_equalizer + def test_delay_equalizer(self, lumped_design): + assert lumped_design.attributes.delay_equalizer is False + lumped_design.attributes.delay_equalizer = True + assert lumped_design.attributes.delay_equalizer - def test_delay_equalizer_order(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.delay_equalizer = True - assert design.attributes.delay_equalizer_order == 2 + def test_delay_equalizer_order(self, lumped_design): + lumped_design.attributes.delay_equalizer = True + assert lumped_design.attributes.delay_equalizer_order == 2 for i in range(0, 21): - design.attributes.delay_equalizer_order = i - assert design.attributes.delay_equalizer_order == i + lumped_design.attributes.delay_equalizer_order = i + assert lumped_design.attributes.delay_equalizer_order == i with pytest.raises(RuntimeError) as info: - design.attributes.delay_equalizer_order = 21 + lumped_design.attributes.delay_equalizer_order = 21 assert info.value.args[0] == "The maximum order is 20" - def test_standard_delay_equ_pass_band_attenuation(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.delay_equalizer = True - assert design.attributes.standard_delay_equ_pass_band_attenuation - design.attributes.standard_delay_equ_pass_band_attenuation = False - assert design.attributes.standard_delay_equ_pass_band_attenuation is False - - def test_standard_delay_equ_pass_band_attenuation_value_db(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.delay_equalizer = True - design.attributes.standard_delay_equ_pass_band_attenuation = False - assert design.attributes.standard_delay_equ_pass_band_attenuation_value_db == "3.01" - design.attributes.standard_delay_equ_pass_band_attenuation_value_db = "4" - assert design.attributes.standard_delay_equ_pass_band_attenuation_value_db == "4" + def test_standard_delay_equ_pass_band_attenuation(self, lumped_design): + lumped_design.attributes.delay_equalizer = True + assert lumped_design.attributes.standard_delay_equ_pass_band_attenuation + lumped_design.attributes.standard_delay_equ_pass_band_attenuation = False + assert lumped_design.attributes.standard_delay_equ_pass_band_attenuation is False + + def test_standard_delay_equ_pass_band_attenuation_value_db(self, lumped_design): + lumped_design.attributes.delay_equalizer = True + lumped_design.attributes.standard_delay_equ_pass_band_attenuation = False + assert lumped_design.attributes.standard_delay_equ_pass_band_attenuation_value_db == "3.01" + lumped_design.attributes.standard_delay_equ_pass_band_attenuation_value_db = "4" + assert lumped_design.attributes.standard_delay_equ_pass_band_attenuation_value_db == "4" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py index 4501df23c8a..be58bd7e15e 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_dll_interface.py @@ -49,9 +49,7 @@ def test_string_to_enum(self): def test_enum_to_string(self): assert ansys.aedt.core.filtersolutions_core._dll_interface().enum_to_string(FilterType.GAUSSIAN) == "gaussian" - def test_raise_error(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + def test_raise_error(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.row(0) + lumped_design.transmission_zeros_ratio.row(0) assert info.value.args[0] == test_transmission_zeros.TestClass.no_transmission_zero_msg diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py index 468ffe2fe60..b70afd9231c 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_graph_setup.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -34,30 +32,22 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_minimum_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.graph_setup.minimum_frequency == "200 MHz" - design.graph_setup.minimum_frequency = "500 MHz" - assert design.graph_setup.minimum_frequency == "500 MHz" - - def test_maximum_frequency(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.graph_setup.maximum_frequency == "5 GHz" - design.graph_setup.maximum_frequency = "2 GHz" - assert design.graph_setup.maximum_frequency == "2 GHz" - - def test_minimum_time(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.graph_setup.minimum_time == "0" - design.graph_setup.minimum_time = "5 ns" - assert design.graph_setup.minimum_time == "5 ns" - - def test_maximum_time(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.graph_setup.maximum_time == "10 ns" - design.graph_setup.maximum_time = "8 ns" - assert design.graph_setup.maximum_time == "8 ns" + def test_minimum_frequency(self, lumped_design): + assert lumped_design.graph_setup.minimum_frequency == "200 MHz" + lumped_design.graph_setup.minimum_frequency = "500 MHz" + assert lumped_design.graph_setup.minimum_frequency == "500 MHz" + + def test_maximum_frequency(self, lumped_design): + assert lumped_design.graph_setup.maximum_frequency == "5 GHz" + lumped_design.graph_setup.maximum_frequency = "2 GHz" + assert lumped_design.graph_setup.maximum_frequency == "2 GHz" + + def test_minimum_time(self, lumped_design): + assert lumped_design.graph_setup.minimum_time == "0" + lumped_design.graph_setup.minimum_time = "5 ns" + assert lumped_design.graph_setup.minimum_time == "5 ns" + + def test_maximum_time(self, lumped_design): + assert lumped_design.graph_setup.maximum_time == "10 ns" + lumped_design.graph_setup.maximum_time = "8 ns" + assert lumped_design.graph_setup.maximum_time == "8 ns" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py index a70c45cf38f..1924cf301f9 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_ideal_response.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.ideal_response import FrequencyResponseColumn from ansys.aedt.core.filtersolutions_core.ideal_response import PoleZerosResponseColumn from ansys.aedt.core.filtersolutions_core.ideal_response import SParametersResponseColumn @@ -39,150 +37,150 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_frequency_response_getter(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - mag_db = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_DB) + def test_frequency_response_getter(self, lumped_design): + mag_db = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_DB) assert len(mag_db) == 500 assert mag_db[100] == pytest.approx(-0.0002779395744451339) assert mag_db[300] == pytest.approx(-14.14973347970826) assert mag_db[-1] == pytest.approx(-69.61741290615645) - phs_deg = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEG) + phs_deg = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEG) assert len(phs_deg) == 500 assert phs_deg[100] == pytest.approx(-72.00174823521779) assert phs_deg[300] == pytest.approx(57.235563076374426) assert phs_deg[-1] == pytest.approx(-52.48142049626833) - grp_dly = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.GROUP_DELAY) + grp_dly = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.GROUP_DELAY) assert len(grp_dly) == 500 assert grp_dly[100] == pytest.approx(5.476886038520659e-10) assert grp_dly[300] == pytest.approx(3.6873949391963247e-10) assert grp_dly[-1] == pytest.approx(2.1202561661746704e-11) - phs_rad = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_RAD) + phs_rad = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_RAD) assert len(phs_rad) == 500 assert phs_rad[100] == pytest.approx(-1.256667573896567) assert phs_rad[300] == pytest.approx(0.9989490249156284) assert phs_rad[-1] == pytest.approx(-0.9159735837835188) - mag_art = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_ARITH) + mag_art = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_ARITH) assert len(mag_art) == 500 assert mag_art[100] == pytest.approx(0.9999680015359182) assert mag_art[300] == pytest.approx(0.1961161351381822) assert mag_art[-1] == pytest.approx(0.000330467956321812) - mag_r = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_REAL) + mag_r = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_REAL) assert len(mag_r) == 500 assert mag_r[100] == pytest.approx(0.3089780880159494) assert mag_r[300] == pytest.approx(0.10613537973464354) assert mag_r[-1] == pytest.approx(0.00020126115208825366) - mag_x = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_IMAG) + mag_x = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.MAGNITUDE_IMAG) assert len(mag_x) == 500 assert mag_x[100] == pytest.approx(-0.9510355120718397) assert mag_x[300] == pytest.approx(0.1649145828303876) assert mag_x[-1] == pytest.approx(-0.00026211260712835594) - phs_dev_deg = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEV_DEG) + phs_dev_deg = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEV_DEG) assert len(phs_dev_deg) == 500 assert phs_dev_deg[100] == pytest.approx(116.73031543331324) assert phs_dev_deg[300] == pytest.approx(-50.566997975196706) assert phs_dev_deg[-1] == pytest.approx(67.66973459820802) - phs_dev_rad = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEV_RAD) + phs_dev_rad = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.PHASE_DEV_RAD) assert len(phs_dev_rad) == 500 assert phs_dev_rad[100] == pytest.approx(2.0373283412028673) assert phs_dev_rad[300] == pytest.approx(-0.8825606075164885) assert phs_dev_rad[-1] == pytest.approx(1.181059672689452) - freqs = design.ideal_response._frequency_response_getter(FrequencyResponseColumn.FREQUENCY) + freqs = lumped_design.ideal_response._frequency_response_getter(FrequencyResponseColumn.FREQUENCY) assert len(freqs) == 500 assert freqs[100] == 2392202091.5388284 assert freqs[300] == 8669097136.772985 assert freqs[-1] == 31214328219.225075 - def test_time_response_getter(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - step_response = design.ideal_response._time_response_getter(TimeResponseColumn.STEP_RESPONSE) + def test_time_response_getter(self, lumped_design): + step_response = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.STEP_RESPONSE) assert len(step_response) == 300 assert step_response[100] == pytest.approx(1.0006647872833518) assert step_response[200] == pytest.approx(0.9999988501385255) assert step_response[-1] == pytest.approx(0.9999999965045667) - ramp_response = design.ideal_response._time_response_getter(TimeResponseColumn.RAMP_RESPONSE) + ramp_response = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.RAMP_RESPONSE) assert len(ramp_response) == 300 assert ramp_response[100] == pytest.approx(2.8184497075983895e-09) assert ramp_response[200] == pytest.approx(6.151630831481296e-09) assert ramp_response[-1] == pytest.approx(9.45163045223663e-09) - impulse_response = design.ideal_response._time_response_getter(TimeResponseColumn.IMPULSE_RESPONSE) + impulse_response = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.IMPULSE_RESPONSE) assert len(impulse_response) == 300 assert impulse_response[100] == pytest.approx(-8537300.294689251) assert impulse_response[200] == pytest.approx(-8538.227868086184) assert impulse_response[-1] == pytest.approx(3.996366349798659) - step_response_db = design.ideal_response._time_response_getter(TimeResponseColumn.STEP_RESPONSE_DB) + step_response_db = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.STEP_RESPONSE_DB) assert len(step_response_db) == 300 assert step_response_db[100] == pytest.approx(-1.0381882969997027) assert step_response_db[200] == pytest.approx(-1.0439706350712086) assert step_response_db[-1] == pytest.approx(-1.0439606778565478) - ramp_response_db = design.ideal_response._time_response_getter(TimeResponseColumn.RAMP_RESPONSE_DB) + ramp_response_db = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.RAMP_RESPONSE_DB) assert len(ramp_response_db) == 300 assert ramp_response_db[100] == pytest.approx(-10.540507747401335) assert ramp_response_db[200] == pytest.approx(-3.7609082425924782) assert ramp_response_db[-1] == pytest.approx(-0.03057888328183367) - impulse_response_db = design.ideal_response._time_response_getter(TimeResponseColumn.IMPULSE_RESPONSE_DB) + impulse_response_db = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.IMPULSE_RESPONSE_DB) assert len(impulse_response_db) == 300 assert impulse_response_db[100] == pytest.approx(-48.60282519370875) assert impulse_response_db[200] == pytest.approx(-100.0) assert impulse_response_db[-1] == pytest.approx(-100.0) - time = design.ideal_response._time_response_getter(TimeResponseColumn.TIME) + time = lumped_design.ideal_response._time_response_getter(TimeResponseColumn.TIME) assert len(time) == 300 assert time[1] == pytest.approx(3.3333333333333335e-11) assert time[200] == pytest.approx(6.666666666666667e-09) assert time[-1] == pytest.approx(9.966666666666667e-09) - def test_sparameters_response_getter(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - s11_response_db = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S11_DB) + def test_sparameters_response_getter(self, lumped_design): + s11_response_db = lumped_design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S11_DB) assert len(s11_response_db) == 500 assert s11_response_db[100] == pytest.approx(-41.93847819973562) assert s11_response_db[300] == pytest.approx(-0.1703333929877981) assert s11_response_db[-1] == pytest.approx(-4.742889883456317e-07) - s21_response_db = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S21_DB) + s21_response_db = lumped_design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S21_DB) assert len(s21_response_db) == 500 assert s21_response_db[100] == pytest.approx(-0.0002779395744451339) assert s21_response_db[300] == pytest.approx(-14.14973347970826) assert s21_response_db[-1] == pytest.approx(-69.61741290615645) - s11_response = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S11_ARITH) + s11_response = lumped_design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S11_ARITH) assert len(s11_response) == 500 assert s11_response[100] == pytest.approx(0.007999744012287301) assert s11_response[300] == pytest.approx(0.9805806756909208) assert s11_response[-1] == pytest.approx(0.9999999453954638) - s21_response = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S21_ARITH) + s21_response = lumped_design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.S21_ARITH) assert len(s21_response) == 500 assert s21_response[100] == pytest.approx(0.9999680015359182) assert s21_response[300] == pytest.approx(0.1961161351381822) assert s21_response[-1] == pytest.approx(0.000330467956321812) - freqs = design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.FREQUENCY) + freqs = lumped_design.ideal_response._sparamaters_response_getter(SParametersResponseColumn.FREQUENCY) assert len(freqs) == 500 assert freqs[100] == pytest.approx(2392202091.5388284) assert freqs[300] == pytest.approx(8669097136.772985) assert freqs[-1] == pytest.approx(31214328219.225075) - def test_pole_zeros_response_getter(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - pole_zero_den_x = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.TX_ZERO_DEN_X) + def test_pole_zeros_response_getter(self, lumped_design): + pole_zero_den_x = lumped_design.ideal_response._pole_zeros_response_getter( + PoleZerosResponseColumn.TX_ZERO_DEN_X + ) assert len(pole_zero_den_x) == 5 assert pole_zero_den_x[0] == pytest.approx(-1000000000.0) assert pole_zero_den_x[1] == pytest.approx(-809016994.3749474) assert pole_zero_den_x[2] == pytest.approx(-809016994.3749474) assert pole_zero_den_x[3] == pytest.approx(-309016994.3749475) assert pole_zero_den_x[4] == pytest.approx(-309016994.3749475) - pole_zero_den_y = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.TX_ZERO_DEN_Y) + pole_zero_den_y = lumped_design.ideal_response._pole_zeros_response_getter( + PoleZerosResponseColumn.TX_ZERO_DEN_Y + ) assert len(pole_zero_den_y) == 5 assert pole_zero_den_y[0] == pytest.approx(0.0) assert pole_zero_den_y[1] == pytest.approx(587785252.2924731) assert pole_zero_den_y[2] == pytest.approx(-587785252.2924731) assert pole_zero_den_y[3] == pytest.approx(951056516.2951534) assert pole_zero_den_y[4] == pytest.approx(-951056516.2951534) - pole_zero_num_x = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.TX_ZERO_NUM_X) + pole_zero_num_x = lumped_design.ideal_response._pole_zeros_response_getter( + PoleZerosResponseColumn.TX_ZERO_NUM_X + ) assert len(pole_zero_num_x) == 0 - pole_zero_num_y = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.TX_ZERO_NUM_Y) + pole_zero_num_y = lumped_design.ideal_response._pole_zeros_response_getter( + PoleZerosResponseColumn.TX_ZERO_NUM_Y + ) assert len(pole_zero_num_y) == 0 - proto_pole_zero_den_x = design.ideal_response._pole_zeros_response_getter( + proto_pole_zero_den_x = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_TX_ZERO_DEN_X ) assert len(proto_pole_zero_den_x) == 5 @@ -191,7 +189,7 @@ def test_pole_zeros_response_getter(self): assert proto_pole_zero_den_x[2] == pytest.approx(-0.8090169943749475) assert proto_pole_zero_den_x[3] == pytest.approx(-0.8090169943749475) assert proto_pole_zero_den_x[4] == pytest.approx(-1.0) - proto_pole_zero_den_y = design.ideal_response._pole_zeros_response_getter( + proto_pole_zero_den_y = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_TX_ZERO_DEN_Y ) assert len(proto_pole_zero_den_y) == 5 @@ -200,43 +198,43 @@ def test_pole_zeros_response_getter(self): assert proto_pole_zero_den_y[2] == pytest.approx(-0.5877852522924731) assert proto_pole_zero_den_y[3] == pytest.approx(0.5877852522924731) assert proto_pole_zero_den_y[4] == pytest.approx(0.0) - proto_pole_zero_num_x = design.ideal_response._pole_zeros_response_getter( + proto_pole_zero_num_x = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_TX_ZERO_NUM_X ) assert len(proto_pole_zero_num_x) == 0 - proto_pole_zero_num_y = design.ideal_response._pole_zeros_response_getter( + proto_pole_zero_num_y = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_TX_ZERO_NUM_Y ) assert len(proto_pole_zero_num_y) == 0 - rx_zero_den_x = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_DEN_X) + rx_zero_den_x = lumped_design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_DEN_X) assert len(rx_zero_den_x) == 5 assert rx_zero_den_x[0] == pytest.approx(-1000000000.0) assert rx_zero_den_x[1] == pytest.approx(-809016994.3749474) assert rx_zero_den_x[2] == pytest.approx(-809016994.3749474) assert rx_zero_den_x[3] == pytest.approx(-309016994.3749475) assert rx_zero_den_x[4] == pytest.approx(-309016994.3749475) - rx_zero_den_y = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_DEN_Y) + rx_zero_den_y = lumped_design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_DEN_Y) assert len(rx_zero_den_y) == 5 assert rx_zero_den_y[0] == pytest.approx(0.0) assert rx_zero_den_y[1] == pytest.approx(587785252.2924731) assert rx_zero_den_y[2] == pytest.approx(-587785252.2924731) assert rx_zero_den_y[3] == pytest.approx(951056516.2951534) assert rx_zero_den_y[4] == pytest.approx(-951056516.2951534) - rx_zero_num_x = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_NUM_X) + rx_zero_num_x = lumped_design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_NUM_X) assert len(rx_zero_num_x) == 5 assert rx_zero_num_x[0] == pytest.approx(0.0) assert rx_zero_num_x[1] == pytest.approx(0.0) assert rx_zero_num_x[2] == pytest.approx(0.0) assert rx_zero_num_x[3] == pytest.approx(0.0) assert rx_zero_num_x[4] == pytest.approx(0.0) - rx_zero_num_y = design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_NUM_Y) + rx_zero_num_y = lumped_design.ideal_response._pole_zeros_response_getter(PoleZerosResponseColumn.RX_ZERO_NUM_Y) assert len(rx_zero_num_y) == 5 assert rx_zero_num_y[0] == pytest.approx(0.0) assert rx_zero_num_y[1] == pytest.approx(0.0) assert rx_zero_num_y[2] == pytest.approx(0.0) assert rx_zero_num_y[3] == pytest.approx(0.0) assert rx_zero_num_y[4] == pytest.approx(0.0) - proto_rx_zero_den_x = design.ideal_response._pole_zeros_response_getter( + proto_rx_zero_den_x = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_RX_ZERO_DEN_X ) assert len(proto_rx_zero_den_x) == 5 @@ -245,7 +243,7 @@ def test_pole_zeros_response_getter(self): assert proto_rx_zero_den_x[2] == pytest.approx(-0.8090169943749475) assert proto_rx_zero_den_x[3] == pytest.approx(-0.8090169943749475) assert proto_rx_zero_den_x[4] == pytest.approx(-1.0) - proto_rx_zero_den_y = design.ideal_response._pole_zeros_response_getter( + proto_rx_zero_den_y = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_RX_ZERO_DEN_Y ) assert len(proto_rx_zero_den_y) == 5 @@ -254,7 +252,7 @@ def test_pole_zeros_response_getter(self): assert proto_rx_zero_den_y[2] == pytest.approx(-0.5877852522924731) assert proto_rx_zero_den_y[3] == pytest.approx(0.5877852522924731) assert proto_rx_zero_den_y[4] == pytest.approx(0.0) - proto_rx_zero_num_x = design.ideal_response._pole_zeros_response_getter( + proto_rx_zero_num_x = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_RX_ZERO_NUM_X ) assert len(proto_rx_zero_num_x) == 5 @@ -263,7 +261,7 @@ def test_pole_zeros_response_getter(self): assert proto_rx_zero_num_x[2] == pytest.approx(0.0) assert proto_rx_zero_num_x[3] == pytest.approx(0.0) assert proto_rx_zero_num_x[4] == pytest.approx(0.0) - proto_rx_zero_num_y = design.ideal_response._pole_zeros_response_getter( + proto_rx_zero_num_y = lumped_design.ideal_response._pole_zeros_response_getter( PoleZerosResponseColumn.PROTO_RX_ZERO_NUM_Y ) assert len(proto_rx_zero_num_y) == 5 @@ -273,17 +271,13 @@ def test_pole_zeros_response_getter(self): assert proto_rx_zero_num_y[3] == pytest.approx(0.0) assert proto_rx_zero_num_y[4] == pytest.approx(0.0) - def test_filter_vsg_analysis_enabled(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.ideal_response.vsg_analysis_enabled is False - design.ideal_response.vsg_analysis_enabled = True - assert design.ideal_response.vsg_analysis_enabled + def test_filter_vsg_analysis_enabled(self, lumped_design): + assert lumped_design.ideal_response.vsg_analysis_enabled is False + lumped_design.ideal_response.vsg_analysis_enabled = True + assert lumped_design.ideal_response.vsg_analysis_enabled - def test_frequency_response(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - freq, mag_db = design.ideal_response.frequency_response( + def test_frequency_response(self, lumped_design): + freq, mag_db = lumped_design.ideal_response.frequency_response( y_axis_parameter=FrequencyResponseColumn.MAGNITUDE_DB, minimum_frequency=None, maximum_frequency=None, @@ -297,7 +291,7 @@ def test_frequency_response(self): assert mag_db[100] == pytest.approx(-0.0002779395744451339) assert mag_db[300] == pytest.approx(-14.14973347970826) assert mag_db[-1] == pytest.approx(-69.61741290615645) - freq, mag_db = design.ideal_response.frequency_response( + freq, mag_db = lumped_design.ideal_response.frequency_response( y_axis_parameter=FrequencyResponseColumn.MAGNITUDE_DB, minimum_frequency="100 MHz", maximum_frequency="3 GHz", @@ -308,10 +302,8 @@ def test_frequency_response(self): assert mag_db[0] == pytest.approx(-4.342896962104627e-10) assert mag_db[-1] == pytest.approx(-47.41677994558435) - def test_time_response(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - time, step_response = design.ideal_response.time_response( + def test_time_response(self, lumped_design): + time, step_response = lumped_design.ideal_response.time_response( y_axis_parameter=TimeResponseColumn.STEP_RESPONSE, minimum_time=None, maximum_time=None, @@ -325,7 +317,7 @@ def test_time_response(self): assert step_response[100] == pytest.approx(1.0006647872833518) assert step_response[200] == pytest.approx(0.9999988501385255) assert step_response[-1] == pytest.approx(0.9999999965045667) - time, step_response = design.ideal_response.time_response( + time, step_response = lumped_design.ideal_response.time_response( y_axis_parameter=TimeResponseColumn.STEP_RESPONSE, minimum_time="1 ns", maximum_time="5 ns", @@ -336,10 +328,8 @@ def test_time_response(self): assert step_response[0] == pytest.approx(1.127711560082254) assert step_response[-1] == pytest.approx(0.9999962734156826) - def test_s_parameters(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - freq, s21_db = design.ideal_response.s_parameters( + def test_s_parameters(self, lumped_design): + freq, s21_db = lumped_design.ideal_response.s_parameters( y_axis_parameter=SParametersResponseColumn.S21_DB, minimum_frequency=None, maximum_frequency=None, @@ -352,7 +342,7 @@ def test_s_parameters(self): assert s21_db[100] == pytest.approx(-0.0002779395744451339) assert s21_db[300] == pytest.approx(-14.14973347970826) assert s21_db[-1] == pytest.approx(-69.61741290615645) - freq, s21_db = design.ideal_response.s_parameters( + freq, s21_db = lumped_design.ideal_response.s_parameters( y_axis_parameter=SParametersResponseColumn.S21_DB, minimum_frequency="100 MHz", maximum_frequency="3 GHz", @@ -362,10 +352,8 @@ def test_s_parameters(self): assert s21_db[0] == pytest.approx(-4.342896962104627e-10) assert s21_db[-1] == pytest.approx(-47.41677994558435) - def test_pole_zero_locations(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - tx_zero_den_x, tx_zero_den_y = design.ideal_response.pole_zero_locations( + def test_pole_zero_locations(self, lumped_design): + tx_zero_den_x, tx_zero_den_y = lumped_design.ideal_response.pole_zero_locations( x_axis_parameter=PoleZerosResponseColumn.TX_ZERO_DEN_X, y_axis_parameter=PoleZerosResponseColumn.TX_ZERO_DEN_Y, ) @@ -382,9 +370,7 @@ def test_pole_zero_locations(self): assert tx_zero_den_y[3] == pytest.approx(951056516.2951534) assert tx_zero_den_y[4] == pytest.approx(-951056516.2951534) - def test_transfer_function_response(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.ideal_response.transfer_function_response().splitlines() == read_resource_file( + def test_transfer_function_response(self, lumped_design): + assert lumped_design.ideal_response.transfer_function_response().splitlines() == read_resource_file( "transferfunction.ckt", "Lumped" ) diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py index cab35dcfa50..3a26ffaadd2 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_multiple_bands_table.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -33,83 +31,69 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_row_count(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + def test_row_count(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + assert lumped_design.multiple_bands_table.row_count == 2 - design.attributes.filter_multiple_bands_enabled = True - assert design.multiple_bands_table.row_count == 2 + def test_row(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + assert lumped_design.multiple_bands_table.row(0) == ("2G", "3G") - def test_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - assert design.multiple_bands_table.row(0) == ("2G", "3G") - - def test_update_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True + def test_update_row(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.update_row(0) + lumped_design.multiple_bands_table.update_row(0) assert info.value.args[0] == "It is not possible to update table with an empty value" - design.multiple_bands_table.update_row(0, lower_frequency="100M") - assert design.multiple_bands_table.row(0) == ("100M", "3G") - design.multiple_bands_table.update_row(0, upper_frequency="4G") - assert design.multiple_bands_table.row(0) == ("100M", "4G") - design.multiple_bands_table.update_row(0, "200M", "5G") - assert design.multiple_bands_table.row(0) == ("200M", "5G") - - def test_append_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - design.multiple_bands_table.append_row("100M", "500M") - assert design.multiple_bands_table.row_count == 3 - assert design.multiple_bands_table.row(2) == ("100M", "500M") + lumped_design.multiple_bands_table.update_row(0, lower_frequency="100M") + assert lumped_design.multiple_bands_table.row(0) == ("100M", "3G") + lumped_design.multiple_bands_table.update_row(0, upper_frequency="4G") + assert lumped_design.multiple_bands_table.row(0) == ("100M", "4G") + lumped_design.multiple_bands_table.update_row(0, "200M", "5G") + assert lumped_design.multiple_bands_table.row(0) == ("200M", "5G") + + def test_append_row(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.multiple_bands_table.append_row("100M", "500M") + assert lumped_design.multiple_bands_table.row_count == 3 + assert lumped_design.multiple_bands_table.row(2) == ("100M", "500M") with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.append_row("", "500M") + lumped_design.multiple_bands_table.append_row("", "500M") assert info.value.args[0] == "It is not possible to append an empty value" with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.append_row("100M", "") + lumped_design.multiple_bands_table.append_row("100M", "") assert info.value.args[0] == "It is not possible to append an empty value" - def test_insert_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - design.multiple_bands_table.insert_row(0, "200M", "5G") - assert design.multiple_bands_table.row(0) == ("200M", "5G") - design.multiple_bands_table.insert_row(0, lower_frequency="500M", upper_frequency="2G") - assert design.multiple_bands_table.row(0) == ("500M", "2G") + def test_insert_row(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.multiple_bands_table.insert_row(0, "200M", "5G") + assert lumped_design.multiple_bands_table.row(0) == ("200M", "5G") + lumped_design.multiple_bands_table.insert_row(0, lower_frequency="500M", upper_frequency="2G") + assert lumped_design.multiple_bands_table.row(0) == ("500M", "2G") with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.insert_row(22, lower_frequency="500M", upper_frequency="2G") + lumped_design.multiple_bands_table.insert_row(22, lower_frequency="500M", upper_frequency="2G") assert info.value.args[0] == "The rowIndex must be greater than zero and less than row count" - def test_remove_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True - design.multiple_bands_table.remove_row(0) - assert design.multiple_bands_table.row(0) == ("4G", "5G") + def test_remove_row(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True + lumped_design.multiple_bands_table.remove_row(0) + assert lumped_design.multiple_bands_table.row(0) == ("4G", "5G") with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.row(1) + lumped_design.multiple_bands_table.row(1) assert ( info.value.args[0] == "Either no value is set for this band or the rowIndex must be greater than zero and less than row count" ) - def test_clear_table(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.attributes.filter_multiple_bands_enabled = True + def test_clear_table(self, lumped_design): + lumped_design.attributes.filter_multiple_bands_enabled = True # There are 2 rows in the table by default - assert design.multiple_bands_table.row_count == 2 - design.multiple_bands_table.clear_table() - assert design.multiple_bands_table.row_count == 0 + assert lumped_design.multiple_bands_table.row_count == 2 + lumped_design.multiple_bands_table.clear_table() + assert lumped_design.multiple_bands_table.row_count == 0 # Check if the table is empty for all 7 rows for i in range(7): with pytest.raises(RuntimeError) as info: - design.multiple_bands_table.row(i) + lumped_design.multiple_bands_table.row(i) assert ( info.value.args[0] == "Either no value is set for this band or the rowIndex must be greater than " "zero and less than row count" diff --git a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py index 79470965f16..a38b9dd25bf 100644 --- a/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py +++ b/tests/system/general/test_45_FilterSolutions/test_filter/test_transmission_zeros.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -37,112 +35,96 @@ class TestClass: no_transmission_zero_update_msg = "This filter has no transmission zero at row 0 to update" input_value_blank_msg = "The input value is blank" - def test_row_count(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert design.transmission_zeros_bandwidth.row_count == 0 - assert design.transmission_zeros_ratio.row_count == 0 - - def test_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + def test_row_count(self, lumped_design): + assert lumped_design.transmission_zeros_bandwidth.row_count == 0 + assert lumped_design.transmission_zeros_ratio.row_count == 0 + def test_row(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.row(0) + lumped_design.transmission_zeros_bandwidth.row(0) assert info.value.args[0] == self.no_transmission_zero_msg with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.row(0) + lumped_design.transmission_zeros_ratio.row(0) assert info.value.args[0] == self.no_transmission_zero_msg - def test_update_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + def test_update_row(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.update_row(0, zero="1.3G", position="2") + lumped_design.transmission_zeros_bandwidth.update_row(0, zero="1.3G", position="2") assert info.value.args[0] == self.no_transmission_zero_update_msg with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.update_row(0, "1.3", "2") + lumped_design.transmission_zeros_ratio.update_row(0, "1.3", "2") assert info.value.args[0] == self.no_transmission_zero_update_msg - def test_append_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + def test_append_row(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.append_row(zero="", position="") + lumped_design.transmission_zeros_bandwidth.append_row(zero="", position="") assert info.value.args[0] == self.input_value_blank_msg with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.append_row("", "") + lumped_design.transmission_zeros_ratio.append_row("", "") assert info.value.args[0] == self.input_value_blank_msg - design.transmission_zeros_bandwidth.append_row("1600M") - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "") - design.transmission_zeros_bandwidth.clear_table() - design.transmission_zeros_bandwidth.append_row(zero="1600M", position="2") - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") - design.transmission_zeros_bandwidth.clear_table() - design.transmission_zeros_ratio.append_row("1.6") - assert design.transmission_zeros_ratio.row(0) == ("1.6", "") - design.transmission_zeros_ratio.clear_table() - design.transmission_zeros_ratio.append_row(zero="1.6", position="2") - assert design.transmission_zeros_ratio.row(0) == ("1.6", "2") - - def test_insert_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + lumped_design.transmission_zeros_bandwidth.append_row("1600M") + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "") + lumped_design.transmission_zeros_bandwidth.clear_table() + lumped_design.transmission_zeros_bandwidth.append_row(zero="1600M", position="2") + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") + lumped_design.transmission_zeros_bandwidth.clear_table() + lumped_design.transmission_zeros_ratio.append_row("1.6") + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "") + lumped_design.transmission_zeros_ratio.clear_table() + lumped_design.transmission_zeros_ratio.append_row(zero="1.6", position="2") + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "2") + + def test_insert_row(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.insert_row(6, zero="1.3G", position="2") + lumped_design.transmission_zeros_bandwidth.insert_row(6, zero="1.3G", position="2") assert info.value.args[0] == "The given index 6 is larger than zeros order" with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.insert_row(6, "1.3", "2") + lumped_design.transmission_zeros_ratio.insert_row(6, "1.3", "2") assert info.value.args[0] == "The given index 6 is larger than zeros order" with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.insert_row(0, zero="", position="2") + lumped_design.transmission_zeros_bandwidth.insert_row(0, zero="", position="2") assert info.value.args[0] == self.input_value_blank_msg with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.insert_row(0, "", "") + lumped_design.transmission_zeros_ratio.insert_row(0, "", "") assert info.value.args[0] == self.input_value_blank_msg - design.transmission_zeros_bandwidth.insert_row(0, "1600M") - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "") - design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") - design.transmission_zeros_bandwidth.clear_table() - design.transmission_zeros_ratio.insert_row(0, "1.6") - assert design.transmission_zeros_ratio.row(0) == ("1.6", "") - design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") - assert design.transmission_zeros_ratio.row(0) == ("1.6", "2") - - def test_remove_row(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + lumped_design.transmission_zeros_bandwidth.insert_row(0, "1600M") + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "") + lumped_design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") + lumped_design.transmission_zeros_bandwidth.clear_table() + lumped_design.transmission_zeros_ratio.insert_row(0, "1.6") + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "") + lumped_design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "2") + + def test_remove_row(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.remove_row(2) + lumped_design.transmission_zeros_bandwidth.remove_row(2) assert info.value.args[0] == "The given index 2 is larger than zeros order" - design.transmission_zeros_bandwidth.append_row(zero="1600M", position="2") - design.transmission_zeros_bandwidth.remove_row(0) + lumped_design.transmission_zeros_bandwidth.append_row(zero="1600M", position="2") + lumped_design.transmission_zeros_bandwidth.remove_row(0) with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.row(0) + lumped_design.transmission_zeros_bandwidth.row(0) assert info.value.args[0] == self.no_transmission_zero_msg - def test_clear_table(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") - design.transmission_zeros_bandwidth.clear_table() + def test_clear_table(self, lumped_design): + lumped_design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "2") + lumped_design.transmission_zeros_bandwidth.clear_table() with pytest.raises(RuntimeError) as info: - design.transmission_zeros_bandwidth.row(0) + lumped_design.transmission_zeros_bandwidth.row(0) assert info.value.args[0] == self.no_transmission_zero_msg - design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") - assert design.transmission_zeros_ratio.row(0) == ("1.6", "2") - design.transmission_zeros_ratio.clear_table() + lumped_design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "2") + lumped_design.transmission_zeros_ratio.clear_table() with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.row(0) + lumped_design.transmission_zeros_ratio.row(0) assert info.value.args[0] == self.no_transmission_zero_msg - def test_restore_default_positions(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") - design.transmission_zeros_bandwidth.restore_default_positions() - assert design.transmission_zeros_bandwidth.row(0) == ("1600M", "3") - design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") - design.transmission_zeros_ratio.restore_default_positions() - assert design.transmission_zeros_ratio.row(0) == ("1.6", "3") + def test_restore_default_positions(self, lumped_design): + lumped_design.transmission_zeros_bandwidth.insert_row(0, zero="1600M", position="2") + lumped_design.transmission_zeros_bandwidth.restore_default_positions() + assert lumped_design.transmission_zeros_bandwidth.row(0) == ("1600M", "3") + lumped_design.transmission_zeros_ratio.insert_row(0, zero="1.6", position="2") + lumped_design.transmission_zeros_ratio.restore_default_positions() + assert lumped_design.transmission_zeros_ratio.row(0) == ("1.6", "3") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py index 041f92eb3b4..52c5c366981 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_export_to_aedt.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.export_to_aedt import PartLibraries from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateEr from ansys.aedt.core.filtersolutions_core.export_to_aedt import SubstrateResistivity @@ -48,651 +46,515 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2") class TestClass: - def test_modelithics_inductor_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + def test_modelithics_inductor_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_list_count + lumped_design.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_inductor_list_count == 116 - - def test_modelithics_inductor_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_inductor_list_count == 116 + def test_modelithics_inductor_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_list(0) + lumped_design.export_to_aedt.modelithics_inductor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_list(-1) + lumped_design.export_to_aedt.modelithics_inductor_list(-1) assert info.value.args[0] == "The Modelithics inductor at the given index is not available" - lumpdesign.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor - assert lumpdesign.export_to_aedt.modelithics_inductor_list(0) == first_modelithics_inductor - - def test_modelithics_inductor_selection(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor + assert lumped_design.export_to_aedt.modelithics_inductor_list(0) == first_modelithics_inductor + def test_modelithics_inductor_selection(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_selection + lumped_design.export_to_aedt.modelithics_inductor_selection assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_selection + lumped_design.export_to_aedt.modelithics_inductor_selection assert info.value.args[0] == "No Modelithics inductor is selected" - lumpdesign.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor - assert lumpdesign.export_to_aedt.modelithics_inductor_selection == first_modelithics_inductor - - def test_modelithics_inductor_family_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_inductor_selection = first_modelithics_inductor + assert lumped_design.export_to_aedt.modelithics_inductor_selection == first_modelithics_inductor + def test_modelithics_inductor_family_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_family_list_count + lumped_design.export_to_aedt.modelithics_inductor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 0 - lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 1 - lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 2 - - def test_modelithics_inductor_family_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_inductor_family_list_count == 0 + lumped_design.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list_count == 1 + lumped_design.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list_count == 2 + def test_modelithics_inductor_family_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + lumped_design.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + lumped_design.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) - lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor - - def test_modelithics_inductor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumped_design.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor + assert lumped_design.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor + def test_modelithics_inductor_family_list_add_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumped_design.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + lumped_design.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) - lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor - - def test_modelithics_inductor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumped_design.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list(0) == second_modelithics_inductor + assert lumped_design.export_to_aedt.modelithics_inductor_family_list(1) == third_modelithics_inductor + def test_modelithics_inductor_family_list_remove_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_remove_family(second_modelithics_inductor) - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.modelithics_inductor_remove_family(second_modelithics_inductor) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_inductor_family_list(0) + lumped_design.export_to_aedt.modelithics_inductor_family_list(0) assert info.value.args[0] == "The Modelithics inductor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) - lumpdesign.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 2 - lumpdesign.export_to_aedt.modelithics_inductor_remove_family(third_modelithics_inductor) - assert lumpdesign.export_to_aedt.modelithics_inductor_family_list_count == 1 - - def test_modelithics_capacitor_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_inductor_add_family(second_modelithics_inductor) + lumped_design.export_to_aedt.modelithics_inductor_add_family(third_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list_count == 2 + lumped_design.export_to_aedt.modelithics_inductor_remove_family(third_modelithics_inductor) + assert lumped_design.export_to_aedt.modelithics_inductor_family_list_count == 1 + def test_modelithics_capacitor_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_list_count + lumped_design.export_to_aedt.modelithics_capacitor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_capacitor_list_count == 143 - - def test_modelithics_capacitor_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_capacitor_list_count == 143 + def test_modelithics_capacitor_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_list(0) + lumped_design.export_to_aedt.modelithics_capacitor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_list(-1) + lumped_design.export_to_aedt.modelithics_capacitor_list(-1) assert info.value.args[0] == "The Modelithics capacitor at the given index is not available" - lumpdesign.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor - assert lumpdesign.export_to_aedt.modelithics_capacitor_list(0) == first_modelithics_capacitor - - def test_modelithics_capacitor_selection(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor + assert lumped_design.export_to_aedt.modelithics_capacitor_list(0) == first_modelithics_capacitor + def test_modelithics_capacitor_selection(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_selection + lumped_design.export_to_aedt.modelithics_capacitor_selection assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_selection + lumped_design.export_to_aedt.modelithics_capacitor_selection assert info.value.args[0] == "No Modelithics capacitor is selected" - lumpdesign.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor - assert lumpdesign.export_to_aedt.modelithics_capacitor_selection == first_modelithics_capacitor - - def test_modelithics_capacitor_family_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_capacitor_selection = first_modelithics_capacitor + assert lumped_design.export_to_aedt.modelithics_capacitor_selection == first_modelithics_capacitor + def test_modelithics_capacitor_family_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count + lumped_design.export_to_aedt.modelithics_capacitor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 0 - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 1 - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 2 - - def test_modelithics_capacitor_family_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list_count == 0 + lumped_design.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list_count == 1 + lumped_design.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list_count == 2 + def test_modelithics_capacitor_family_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor - - def test_modelithics_capacitor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor + def test_modelithics_capacitor_family_list_add_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor - - def test_modelithics_capacitor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) == first_modelithics_capacitor + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list(1) == second_modelithics_capacitor + def test_modelithics_capacitor_family_list_remove_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) + lumped_design.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_capacitor_family_list(0) + lumped_design.export_to_aedt.modelithics_capacitor_family_list(0) assert info.value.args[0] == "The Modelithics capacitor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) - lumpdesign.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 2 - lumpdesign.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) - assert lumpdesign.export_to_aedt.modelithics_capacitor_family_list_count == 1 - - def test_modelithics_resistor_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(first_modelithics_capacitor) + lumped_design.export_to_aedt.modelithics_capacitor_add_family(second_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list_count == 2 + lumped_design.export_to_aedt.modelithics_capacitor_remove_family(second_modelithics_capacitor) + assert lumped_design.export_to_aedt.modelithics_capacitor_family_list_count == 1 + def test_modelithics_resistor_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_list_count + lumped_design.export_to_aedt.modelithics_resistor_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_resistor_list_count == 39 - - def test_modelithics_resistor_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_resistor_list_count == 39 + def test_modelithics_resistor_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_list(0) + lumped_design.export_to_aedt.modelithics_resistor_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_list(-1) + lumped_design.export_to_aedt.modelithics_resistor_list(-1) assert info.value.args[0] == "The Modelithics resistor at the given index is not available" - lumpdesign.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor - assert lumpdesign.export_to_aedt.modelithics_resistor_list(0) == first_modelithics_resistor - - def test_modelithics_resistor_selection(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor + assert lumped_design.export_to_aedt.modelithics_resistor_list(0) == first_modelithics_resistor + def test_modelithics_resistor_selection(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_selection + lumped_design.export_to_aedt.modelithics_resistor_selection assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_selection + lumped_design.export_to_aedt.modelithics_resistor_selection assert info.value.args[0] == "No Modelithics resistor is selected" - lumpdesign.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor - assert lumpdesign.export_to_aedt.modelithics_resistor_selection == first_modelithics_resistor - - def test_modelithics_resistor_family_list_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_resistor_selection = first_modelithics_resistor + assert lumped_design.export_to_aedt.modelithics_resistor_selection == first_modelithics_resistor + def test_modelithics_resistor_family_list_count(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_family_list_count + lumped_design.export_to_aedt.modelithics_resistor_family_list_count assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 0 - lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 1 - lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 2 - - def test_modelithics_resistor_family_list(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.modelithics_resistor_family_list_count == 0 + lumped_design.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list_count == 1 + lumped_design.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list_count == 2 + def test_modelithics_resistor_family_list(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + lumped_design.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + lumped_design.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) - lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor - - def test_modelithics_resistor_family_list_add_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumped_design.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor + assert lumped_design.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor + def test_modelithics_resistor_family_list_add_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumped_design.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + lumped_design.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) - lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor - - def test_modelithics_resistor_family_list_remove_family(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumped_design.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list(0) == first_modelithics_resistor + assert lumped_design.export_to_aedt.modelithics_resistor_family_list(1) == second_modelithics_resistor + def test_modelithics_resistor_family_list_remove_family(self, lumped_design): with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) + lumped_design.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) assert info.value.args[0] == "The part library is not set to Modelithics" - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS with pytest.raises(RuntimeError) as info: - lumpdesign.export_to_aedt.modelithics_resistor_family_list(0) + lumped_design.export_to_aedt.modelithics_resistor_family_list(0) assert info.value.args[0] == "The Modelithics resistor family at the given index is not available" - lumpdesign.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) - lumpdesign.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 2 - lumpdesign.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) - assert lumpdesign.export_to_aedt.modelithics_resistor_family_list_count == 1 - - def test_schematic_name(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.schematic_name = "my_schematic" - assert lumpdesign.export_to_aedt.schematic_name == "my_schematic" - - def test_simulate_after_export_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.simulate_after_export_enabled == False - lumpdesign.export_to_aedt.simulate_after_export_enabled = True - assert lumpdesign.export_to_aedt.simulate_after_export_enabled == True - - def test_include_group_delay_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_group_delay_enabled == False - lumpdesign.export_to_aedt.include_group_delay_enabled = True - assert lumpdesign.export_to_aedt.include_group_delay_enabled == True - - def test_include_gt_gain_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_gt_gain_enabled == False - lumpdesign.export_to_aedt.include_gt_gain_enabled = True - assert lumpdesign.export_to_aedt.include_gt_gain_enabled == True - - def test_include_vgsl_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_vgsl_enabled == False - lumpdesign.export_to_aedt.include_vgsl_enabled = True - assert lumpdesign.export_to_aedt.include_vgsl_enabled == True - - def test_include_vgin_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_vgin_enabled == False - lumpdesign.export_to_aedt.include_vgin_enabled = True - assert lumpdesign.export_to_aedt.include_vgin_enabled == True - - def test_include_input_return_loss_s11_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == True - lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled = False - assert lumpdesign.export_to_aedt.include_input_return_loss_s11_enabled == False - - def test_include_forward_transfer_s21_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == True - lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled = False - assert lumpdesign.export_to_aedt.include_forward_transfer_s21_enabled == False - - def test_include_reverse_transfer_s12_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == False - lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled = True - assert lumpdesign.export_to_aedt.include_reverse_transfer_s12_enabled == True - - def test_include_output_return_loss_s22_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == False - lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled = True - assert lumpdesign.export_to_aedt.include_output_return_loss_s22_enabled == True - - def test_db_format_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.db_format_enabled == True - lumpdesign.export_to_aedt.db_format_enabled = False - assert lumpdesign.export_to_aedt.db_format_enabled == False - - def test_rectangular_plot_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.rectangular_plot_enabled == True - lumpdesign.export_to_aedt.rectangular_plot_enabled = False - assert lumpdesign.export_to_aedt.rectangular_plot_enabled == False - - def test_smith_plot_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.smith_plot_enabled == False - lumpdesign.export_to_aedt.smith_plot_enabled = True - assert lumpdesign.export_to_aedt.smith_plot_enabled == True - - def test_polar_plot_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.polar_plot_enabled == False - lumpdesign.export_to_aedt.polar_plot_enabled = True - assert lumpdesign.export_to_aedt.polar_plot_enabled == True - - def test_table_data_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.table_data_enabled == False - lumpdesign.export_to_aedt.table_data_enabled = True - assert lumpdesign.export_to_aedt.table_data_enabled == True - - def test_optimitrics_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.optimitrics_enabled == True - lumpdesign.export_to_aedt.optimitrics_enabled = False - assert lumpdesign.export_to_aedt.optimitrics_enabled == False - - def test_optimize_after_export_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.optimize_after_export_enabled == False - lumpdesign.export_to_aedt.optimize_after_export_enabled = True - assert lumpdesign.export_to_aedt.optimize_after_export_enabled == True - - def test_load_library_parts_config(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA - assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA - - def test_save_library_parts_config(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - lumpdesign.export_to_aedt.substrate_er = "2.25" - lumpdesign.export_to_aedt.substrate_resistivity = "4.2E+07 " - lumpdesign.export_to_aedt.substrate_conductor_thickness = "350 nm" - lumpdesign.export_to_aedt.substrate_dielectric_height = "3 mm" - lumpdesign.export_to_aedt.substrate_loss_tangent = "0.065 " - lumpdesign.export_to_aedt.save_library_parts_config(resource_path("library_parts_test.cfg")) - lumpdesign.export_to_aedt.load_library_parts_config(resource_path("library_parts_test.cfg")) - assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.substrate_er == "2.25" - assert lumpdesign.export_to_aedt.substrate_resistivity == "4.2E+07 " - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "350 nm" - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "3 mm" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.065 " - - def test_import_tuned_variables(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.simulate_after_export_enabled = True - lumpdesign.export_to_aedt.optimize_after_export_enabled = True - lumpdesign.export_to_aedt.export_design() - assert lumpdesign.export_to_aedt.import_tuned_variables().splitlines() == read_resource_file( + lumped_design.export_to_aedt.modelithics_resistor_add_family(first_modelithics_resistor) + lumped_design.export_to_aedt.modelithics_resistor_add_family(second_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list_count == 2 + lumped_design.export_to_aedt.modelithics_resistor_remove_family(second_modelithics_resistor) + assert lumped_design.export_to_aedt.modelithics_resistor_family_list_count == 1 + + def test_schematic_name(self, lumped_design): + lumped_design.export_to_aedt.schematic_name = "my_schematic" + assert lumped_design.export_to_aedt.schematic_name == "my_schematic" + + def test_simulate_after_export_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.simulate_after_export_enabled == False + lumped_design.export_to_aedt.simulate_after_export_enabled = True + assert lumped_design.export_to_aedt.simulate_after_export_enabled == True + + def test_include_group_delay_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_group_delay_enabled == False + lumped_design.export_to_aedt.include_group_delay_enabled = True + assert lumped_design.export_to_aedt.include_group_delay_enabled == True + + def test_include_gt_gain_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_gt_gain_enabled == False + lumped_design.export_to_aedt.include_gt_gain_enabled = True + assert lumped_design.export_to_aedt.include_gt_gain_enabled == True + + def test_include_vgsl_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_vgsl_enabled == False + lumped_design.export_to_aedt.include_vgsl_enabled = True + assert lumped_design.export_to_aedt.include_vgsl_enabled == True + + def test_include_vgin_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_vgin_enabled == False + lumped_design.export_to_aedt.include_vgin_enabled = True + assert lumped_design.export_to_aedt.include_vgin_enabled == True + + def test_include_input_return_loss_s11_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_input_return_loss_s11_enabled == True + lumped_design.export_to_aedt.include_input_return_loss_s11_enabled = False + assert lumped_design.export_to_aedt.include_input_return_loss_s11_enabled == False + + def test_include_forward_transfer_s21_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_forward_transfer_s21_enabled == True + lumped_design.export_to_aedt.include_forward_transfer_s21_enabled = False + assert lumped_design.export_to_aedt.include_forward_transfer_s21_enabled == False + + def test_include_reverse_transfer_s12_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_reverse_transfer_s12_enabled == False + lumped_design.export_to_aedt.include_reverse_transfer_s12_enabled = True + assert lumped_design.export_to_aedt.include_reverse_transfer_s12_enabled == True + + def test_include_output_return_loss_s22_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.include_output_return_loss_s22_enabled == False + lumped_design.export_to_aedt.include_output_return_loss_s22_enabled = True + assert lumped_design.export_to_aedt.include_output_return_loss_s22_enabled == True + + def test_db_format_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.db_format_enabled == True + lumped_design.export_to_aedt.db_format_enabled = False + assert lumped_design.export_to_aedt.db_format_enabled == False + + def test_rectangular_plot_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.rectangular_plot_enabled == True + lumped_design.export_to_aedt.rectangular_plot_enabled = False + assert lumped_design.export_to_aedt.rectangular_plot_enabled == False + + def test_smith_plot_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.smith_plot_enabled == False + lumped_design.export_to_aedt.smith_plot_enabled = True + assert lumped_design.export_to_aedt.smith_plot_enabled == True + + def test_polar_plot_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.polar_plot_enabled == False + lumped_design.export_to_aedt.polar_plot_enabled = True + assert lumped_design.export_to_aedt.polar_plot_enabled == True + + def test_table_data_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.table_data_enabled == False + lumped_design.export_to_aedt.table_data_enabled = True + assert lumped_design.export_to_aedt.table_data_enabled == True + + def test_optimitrics_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.optimitrics_enabled == True + lumped_design.export_to_aedt.optimitrics_enabled = False + assert lumped_design.export_to_aedt.optimitrics_enabled == False + + def test_optimize_after_export_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.optimize_after_export_enabled == False + lumped_design.export_to_aedt.optimize_after_export_enabled = True + assert lumped_design.export_to_aedt.optimize_after_export_enabled == True + + def test_load_library_parts_config(self, lumped_design): + lumped_design.export_to_aedt.load_library_parts_config(resource_path("library_parts.cfg")) + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.substrate_er == SubstrateEr.ALUMINA + assert lumped_design.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD + assert lumped_design.export_to_aedt.substrate_conductor_thickness == "2.54 um" + assert lumped_design.export_to_aedt.substrate_dielectric_height == "1.27 mm" + assert lumped_design.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA + + def test_save_library_parts_config(self, lumped_design): + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + lumped_design.export_to_aedt.substrate_er = "2.25" + lumped_design.export_to_aedt.substrate_resistivity = "4.2E+07 " + lumped_design.export_to_aedt.substrate_conductor_thickness = "350 nm" + lumped_design.export_to_aedt.substrate_dielectric_height = "3 mm" + lumped_design.export_to_aedt.substrate_loss_tangent = "0.065 " + lumped_design.export_to_aedt.save_library_parts_config(resource_path("library_parts_test.cfg")) + lumped_design.export_to_aedt.load_library_parts_config(resource_path("library_parts_test.cfg")) + assert lumped_design.export_to_aedt.part_libraries == PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.substrate_er == "2.25" + assert lumped_design.export_to_aedt.substrate_resistivity == "4.2E+07 " + assert lumped_design.export_to_aedt.substrate_conductor_thickness == "350 nm" + assert lumped_design.export_to_aedt.substrate_dielectric_height == "3 mm" + assert lumped_design.export_to_aedt.substrate_loss_tangent == "0.065 " + + def test_import_tuned_variables(self, lumped_design): + lumped_design.export_to_aedt.simulate_after_export_enabled = True + lumped_design.export_to_aedt.optimize_after_export_enabled = True + lumped_design.export_to_aedt.export_design() + assert lumped_design.export_to_aedt.import_tuned_variables().splitlines() == read_resource_file( "imported_netlist.ckt", "Lumped" ) - def test_part_libraries(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.LUMPED + def test_part_libraries(self, lumped_design): + assert lumped_design.export_to_aedt.part_libraries == PartLibraries.LUMPED assert len(PartLibraries) == 3 - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.part_libraries == PartLibraries.MODELITHICS - - def test_interconnect_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "2" - lumpdesign.export_to_aedt.interconnect_length_to_width_ratio = "3" - assert lumpdesign.export_to_aedt.interconnect_length_to_width_ratio == "3" - - def test_interconnect_minimum_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" - lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" - assert lumpdesign.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" - - def test_interconnect_maximum_length_to_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" - lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" - assert lumpdesign.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" - - def test_interconnect_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" - lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" - assert lumpdesign.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" - - def test_interconnect_minimum_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" - lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" - assert lumpdesign.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" - - def test_interconnect_maximum_line_to_termination_width_ratio(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" - lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" - assert lumpdesign.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" - - def test_interconnect_length_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_length_value == "2.54 mm" - lumpdesign.export_to_aedt.interconnect_length_value = "3 mm" - assert lumpdesign.export_to_aedt.interconnect_length_value == "3 mm" - - def test_interconnect_minimum_length_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" - lumpdesign.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" - assert lumpdesign.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" - - def test_interconnect_maximum_length_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" - lumpdesign.export_to_aedt.interconnect_maximum_length_value = "6 mm" - assert lumpdesign.export_to_aedt.interconnect_maximum_length_value == "6 mm" - - def test_interconnect_line_width_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_line_width_value == "1.27 mm" - lumpdesign.export_to_aedt.interconnect_line_width_value = "2 mm" - assert lumpdesign.export_to_aedt.interconnect_line_width_value == "2 mm" - - def test_interconnect_minimum_width_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "635 um" - lumpdesign.export_to_aedt.interconnect_minimum_width_value = "725 um" - assert lumpdesign.export_to_aedt.interconnect_minimum_width_value == "725 um" - - def test_interconnect_maximum_width_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" - lumpdesign.export_to_aedt.interconnect_maximum_width_value = "3 mm" - assert lumpdesign.export_to_aedt.interconnect_maximum_width_value == "3 mm" - - def test_interconnect_inductor_tolerance_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "1" - lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value = "10" - assert lumpdesign.export_to_aedt.interconnect_inductor_tolerance_value == "10" - - def test_interconnect_capacitor_tolerance_value(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.part_libraries = PartLibraries.MODELITHICS - assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "1" - lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value = "10" - assert lumpdesign.export_to_aedt.interconnect_capacitor_tolerance_value == "10" - - def test_interconnect_geometry_optimization_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == True - lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled = False - assert lumpdesign.export_to_aedt.interconnect_geometry_optimization_enabled == False - - def test_substrate_type(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.part_libraries == PartLibraries.MODELITHICS + + def test_interconnect_length_to_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_length_to_width_ratio == "2" + lumped_design.export_to_aedt.interconnect_length_to_width_ratio = "3" + assert lumped_design.export_to_aedt.interconnect_length_to_width_ratio == "3" + + def test_interconnect_minimum_length_to_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.5" + lumped_design.export_to_aedt.interconnect_minimum_length_to_width_ratio = "0.6" + assert lumped_design.export_to_aedt.interconnect_minimum_length_to_width_ratio == "0.6" + + def test_interconnect_maximum_length_to_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_maximum_length_to_width_ratio == "2" + lumped_design.export_to_aedt.interconnect_maximum_length_to_width_ratio = "3" + assert lumped_design.export_to_aedt.interconnect_maximum_length_to_width_ratio == "3" + + def test_interconnect_line_to_termination_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_line_to_termination_width_ratio == "1" + lumped_design.export_to_aedt.interconnect_line_to_termination_width_ratio = "2" + assert lumped_design.export_to_aedt.interconnect_line_to_termination_width_ratio == "2" + + def test_interconnect_minimum_line_to_termination_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.5" + lumped_design.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio = "0.6" + assert lumped_design.export_to_aedt.interconnect_minimum_line_to_termination_width_ratio == "0.6" + + def test_interconnect_maximum_line_to_termination_width_ratio(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "2" + lumped_design.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio = "3" + assert lumped_design.export_to_aedt.interconnect_maximum_line_to_termination_width_ratio == "3" + + def test_interconnect_length_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_length_value == "2.54 mm" + lumped_design.export_to_aedt.interconnect_length_value = "3 mm" + assert lumped_design.export_to_aedt.interconnect_length_value == "3 mm" + + def test_interconnect_minimum_length_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_minimum_length_value == "1.27 mm" + lumped_design.export_to_aedt.interconnect_minimum_length_value = "0.6 mm" + assert lumped_design.export_to_aedt.interconnect_minimum_length_value == "0.6 mm" + + def test_interconnect_maximum_length_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_maximum_length_value == "5.08 mm" + lumped_design.export_to_aedt.interconnect_maximum_length_value = "6 mm" + assert lumped_design.export_to_aedt.interconnect_maximum_length_value == "6 mm" + + def test_interconnect_line_width_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_line_width_value == "1.27 mm" + lumped_design.export_to_aedt.interconnect_line_width_value = "2 mm" + assert lumped_design.export_to_aedt.interconnect_line_width_value == "2 mm" + + def test_interconnect_minimum_width_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_minimum_width_value == "635 um" + lumped_design.export_to_aedt.interconnect_minimum_width_value = "725 um" + assert lumped_design.export_to_aedt.interconnect_minimum_width_value == "725 um" + + def test_interconnect_maximum_width_value(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_maximum_width_value == "2.54 mm" + lumped_design.export_to_aedt.interconnect_maximum_width_value = "3 mm" + assert lumped_design.export_to_aedt.interconnect_maximum_width_value == "3 mm" + + def test_interconnect_inductor_tolerance_value(self, lumped_design): + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.interconnect_inductor_tolerance_value == "1" + lumped_design.export_to_aedt.interconnect_inductor_tolerance_value = "10" + assert lumped_design.export_to_aedt.interconnect_inductor_tolerance_value == "10" + + def test_interconnect_capacitor_tolerance_value(self, lumped_design): + lumped_design.export_to_aedt.part_libraries = PartLibraries.MODELITHICS + assert lumped_design.export_to_aedt.interconnect_capacitor_tolerance_value == "1" + lumped_design.export_to_aedt.interconnect_capacitor_tolerance_value = "10" + assert lumped_design.export_to_aedt.interconnect_capacitor_tolerance_value == "10" + + def test_interconnect_geometry_optimization_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.interconnect_geometry_optimization_enabled == True + lumped_design.export_to_aedt.interconnect_geometry_optimization_enabled = False + assert lumped_design.export_to_aedt.interconnect_geometry_optimization_enabled == False + + def test_substrate_type(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_type == SubstrateType.MICROSTRIP assert len(SubstrateType) == 5 for substrate in SubstrateType: - lumpdesign.export_to_aedt.substrate_type = substrate - assert lumpdesign.export_to_aedt.substrate_type == substrate - - def test_substrate_er(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.substrate_type = substrate + assert lumped_design.export_to_aedt.substrate_type == substrate - assert lumpdesign.export_to_aedt.substrate_er == SubstrateEr.ALUMINA + def test_substrate_er(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_er == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for er in SubstrateEr: - lumpdesign.export_to_aedt.substrate_er = er - assert lumpdesign.export_to_aedt.substrate_er == er - lumpdesign.export_to_aedt.substrate_er = "3.2" - assert lumpdesign.export_to_aedt.substrate_er == "3.2" + lumped_design.export_to_aedt.substrate_er = er + assert lumped_design.export_to_aedt.substrate_er == er + lumped_design.export_to_aedt.substrate_er = "3.2" + assert lumped_design.export_to_aedt.substrate_er == "3.2" - def test_substrate_resistivity(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD + def test_substrate_resistivity(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_resistivity == SubstrateResistivity.GOLD assert len(SubstrateResistivity) == 11 for resistivity in SubstrateResistivity: - lumpdesign.export_to_aedt.substrate_resistivity = resistivity - assert lumpdesign.export_to_aedt.substrate_resistivity == resistivity - lumpdesign.export_to_aedt.substrate_resistivity = "0.02" - assert lumpdesign.export_to_aedt.substrate_resistivity == "0.02" - - def test_substrate_loss_tangent(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.export_to_aedt.substrate_resistivity = resistivity + assert lumped_design.export_to_aedt.substrate_resistivity == resistivity + lumped_design.export_to_aedt.substrate_resistivity = "0.02" + assert lumped_design.export_to_aedt.substrate_resistivity == "0.02" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA + def test_substrate_loss_tangent(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_loss_tangent == SubstrateEr.ALUMINA assert len(SubstrateEr) == 17 for loss in SubstrateEr: - lumpdesign.export_to_aedt.substrate_loss_tangent = loss - assert lumpdesign.export_to_aedt.substrate_loss_tangent == loss - lumpdesign.export_to_aedt.substrate_loss_tangent = "0.0002" - assert lumpdesign.export_to_aedt.substrate_loss_tangent == "0.0002" - - def test_substrate_conductor_thickness(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "2.54 um" - lumpdesign.export_to_aedt.substrate_conductor_thickness = "1.25 um" - assert lumpdesign.export_to_aedt.substrate_conductor_thickness == "1.25 um" - - def test_substrate_dielectric_height(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.27 mm" - lumpdesign.export_to_aedt.substrate_dielectric_height = "1.22 mm" - assert lumpdesign.export_to_aedt.substrate_dielectric_height == "1.22 mm" - - def test_substrate_unbalanced_lower_dielectric_height(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE - lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True - assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" - lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height = "5.2 mm" - assert lumpdesign.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "5.2 mm" - - def test_substrate_suspend_dielectric_height(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.substrate_type = SubstrateType.SUSPEND - assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" - lumpdesign.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" - assert lumpdesign.export_to_aedt.substrate_suspend_dielectric_height == "3.2 mm" - - def test_substrate_cover_height(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.substrate_cover_height_enabled = True - assert lumpdesign.export_to_aedt.substrate_cover_height == "6.35 mm" - lumpdesign.export_to_aedt.substrate_cover_height = "2.5 mm" - assert lumpdesign.export_to_aedt.substrate_cover_height == "2.5 mm" - - def test_substrate_unbalanced_stripline_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt.substrate_type = SubstrateType.STRIPLINE - assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == False - lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled = True - assert lumpdesign.export_to_aedt.substrate_unbalanced_stripline_enabled == True - - def test_substrate_cover_height_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == False - lumpdesign.export_to_aedt.substrate_cover_height_enabled = True - assert lumpdesign.export_to_aedt.substrate_cover_height_enabled == True + lumped_design.export_to_aedt.substrate_loss_tangent = loss + assert lumped_design.export_to_aedt.substrate_loss_tangent == loss + lumped_design.export_to_aedt.substrate_loss_tangent = "0.0002" + assert lumped_design.export_to_aedt.substrate_loss_tangent == "0.0002" + + def test_substrate_conductor_thickness(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_conductor_thickness == "2.54 um" + lumped_design.export_to_aedt.substrate_conductor_thickness = "1.25 um" + assert lumped_design.export_to_aedt.substrate_conductor_thickness == "1.25 um" + + def test_substrate_dielectric_height(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_dielectric_height == "1.27 mm" + lumped_design.export_to_aedt.substrate_dielectric_height = "1.22 mm" + assert lumped_design.export_to_aedt.substrate_dielectric_height == "1.22 mm" + + def test_substrate_unbalanced_lower_dielectric_height(self, lumped_design): + lumped_design.export_to_aedt.substrate_type = SubstrateType.STRIPLINE + lumped_design.export_to_aedt.substrate_unbalanced_stripline_enabled = True + assert lumped_design.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "6.35 mm" + lumped_design.export_to_aedt.substrate_unbalanced_lower_dielectric_height = "5.2 mm" + assert lumped_design.export_to_aedt.substrate_unbalanced_lower_dielectric_height == "5.2 mm" + + def test_substrate_suspend_dielectric_height(self, lumped_design): + lumped_design.export_to_aedt.substrate_type = SubstrateType.SUSPEND + assert lumped_design.export_to_aedt.substrate_suspend_dielectric_height == "1.27 mm" + lumped_design.export_to_aedt.substrate_suspend_dielectric_height = "3.2 mm" + assert lumped_design.export_to_aedt.substrate_suspend_dielectric_height == "3.2 mm" + + def test_substrate_cover_height(self, lumped_design): + lumped_design.export_to_aedt.substrate_cover_height_enabled = True + assert lumped_design.export_to_aedt.substrate_cover_height == "6.35 mm" + lumped_design.export_to_aedt.substrate_cover_height = "2.5 mm" + assert lumped_design.export_to_aedt.substrate_cover_height == "2.5 mm" + + def test_substrate_unbalanced_stripline_enabled(self, lumped_design): + lumped_design.export_to_aedt.substrate_type = SubstrateType.STRIPLINE + assert lumped_design.export_to_aedt.substrate_unbalanced_stripline_enabled == False + lumped_design.export_to_aedt.substrate_unbalanced_stripline_enabled = True + assert lumped_design.export_to_aedt.substrate_unbalanced_stripline_enabled == True + + def test_substrate_cover_height_enabled(self, lumped_design): + assert lumped_design.export_to_aedt.substrate_cover_height_enabled == False + lumped_design.export_to_aedt.substrate_cover_height_enabled = True + assert lumped_design.export_to_aedt.substrate_cover_height_enabled == True diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py index 2ff330772e9..2d2c4bd5c5a 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.optimization_goals_table import OptimizationGoalParameter from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -35,19 +33,15 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_row_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + def test_row_count(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + assert lumped_design.optimization_goals_table.row_count == 2 - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - assert lumpdesign.optimization_goals_table.row_count == 2 - - def test_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - assert lumpdesign.optimization_goals_table.row(0) == [ + def test_row(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + assert lumped_design.optimization_goals_table.row(0) == [ "200 MHz", "1 GHz", "-3.0103", @@ -56,7 +50,7 @@ def test_row(self): "1", "Y", ] - assert lumpdesign.optimization_goals_table.row(1) == [ + assert lumped_design.optimization_goals_table.row(1) == [ "1.5849 GHz", "1.9019 GHz", "-23.01", @@ -66,20 +60,18 @@ def test_row(self): "Y", ] assert ( - lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.PARAMETER_NAME.value] + lumped_design.optimization_goals_table.row(0)[OptimizationGoalParameter.PARAMETER_NAME.value] == "dB(S(Port1,Port1))" ) - assert lumpdesign.optimization_goals_table.row(1)[OptimizationGoalParameter.WEIGHT.value] == "0.5" - - def test_update_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + assert lumped_design.optimization_goals_table.row(1)[OptimizationGoalParameter.WEIGHT.value] == "0.5" - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - lumpdesign.optimization_goals_table.update_row( + def test_update_row(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + lumped_design.optimization_goals_table.update_row( 0, lower_frequency="100 MHz", upper_frequency="2 GHz", condition=">", weight="0.7" ) - assert lumpdesign.optimization_goals_table.row(0) == [ + assert lumped_design.optimization_goals_table.row(0) == [ "100 MHz", "2 GHz", "-3.0103", @@ -89,13 +81,13 @@ def test_update_row(self): "Y", ] - def test_append_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - lumpdesign.optimization_goals_table.append_row("100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y") - assert lumpdesign.optimization_goals_table.row(2) == [ + def test_append_row(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + lumped_design.optimization_goals_table.append_row( + "100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y" + ) + assert lumped_design.optimization_goals_table.row(2) == [ "100 MHz", "2 GHz", "-3", @@ -105,15 +97,13 @@ def test_append_row(self): "Y", ] - def test_insert_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - lumpdesign.optimization_goals_table.insert_row( + def test_insert_row(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + lumped_design.optimization_goals_table.insert_row( 1, "100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y" ) - assert lumpdesign.optimization_goals_table.row(1) == [ + assert lumped_design.optimization_goals_table.row(1) == [ "100 MHz", "2 GHz", "-3", @@ -123,14 +113,12 @@ def test_insert_row(self): "Y", ] - def test_remove_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - lumpdesign.optimization_goals_table.remove_row(1) - assert lumpdesign.optimization_goals_table.row_count == 1 - assert lumpdesign.optimization_goals_table.row(0) == [ + def test_remove_row(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + lumped_design.optimization_goals_table.remove_row(1) + assert lumped_design.optimization_goals_table.row_count == 1 + assert lumped_design.optimization_goals_table.row(0) == [ "200 MHz", "1 GHz", "-3.0103", @@ -140,17 +128,21 @@ def test_remove_row(self): "Y", ] - def test_adjust_goal_frequency(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.export_to_aedt._open_aedt_export() - lumpdesign.optimization_goals_table.restore_design_goals() - lumpdesign.optimization_goals_table.adjust_goal_frequency("150 MHz") - assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.LOWER_FREQUENCY.value] == "350 MHz" - assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.UPPER_FREQUENCY.value] == "1.15 GHz" + def test_adjust_goal_frequency(self, lumped_design): + lumped_design.export_to_aedt._open_aedt_export() + lumped_design.optimization_goals_table.restore_design_goals() + lumped_design.optimization_goals_table.adjust_goal_frequency("150 MHz") + assert ( + lumped_design.optimization_goals_table.row(0)[OptimizationGoalParameter.LOWER_FREQUENCY.value] == "350 MHz" + ) + assert ( + lumped_design.optimization_goals_table.row(0)[OptimizationGoalParameter.UPPER_FREQUENCY.value] == "1.15 GHz" + ) assert ( - lumpdesign.optimization_goals_table.row(1)[OptimizationGoalParameter.LOWER_FREQUENCY.value] == "1.7349 GHz" + lumped_design.optimization_goals_table.row(1)[OptimizationGoalParameter.LOWER_FREQUENCY.value] + == "1.7349 GHz" ) assert ( - lumpdesign.optimization_goals_table.row(1)[OptimizationGoalParameter.UPPER_FREQUENCY.value] == "2.0519 GHz" + lumped_design.optimization_goals_table.row(1)[OptimizationGoalParameter.UPPER_FREQUENCY.value] + == "2.0519 GHz" ) diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py index 40412dcdd10..ee20508c76b 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_nodes_and_leads.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -36,82 +34,50 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_lumped_c_node_capacitor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.c_node_capacitor == "0" - lumpdesign.leads_and_nodes.c_node_capacitor = "1n" - assert lumpdesign.leads_and_nodes.c_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "c_node_capacitor.ckt", "Lumped" - ) - - def test_lumped_c_lead_inductor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.c_lead_inductor == "0" - lumpdesign.leads_and_nodes.c_lead_inductor = "1n" - assert lumpdesign.leads_and_nodes.c_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "c_lead_inductor.ckt", "Lumped" - ) - - def test_lumped_l_node_capacitor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.l_node_capacitor == "0" - lumpdesign.leads_and_nodes.l_node_capacitor = "1n" - assert lumpdesign.leads_and_nodes.l_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "l_node_capacitor.ckt", "Lumped" - ) - - def test_lumped_l_lead_inductor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.l_lead_inductor == "0" - lumpdesign.leads_and_nodes.l_lead_inductor = "1n" - assert lumpdesign.leads_and_nodes.l_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "l_lead_inductor.ckt", "Lumped" - ) - - def test_lumped_r_node_capacitor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.r_node_capacitor == "0" - lumpdesign.leads_and_nodes.r_node_capacitor = "1n" - assert lumpdesign.leads_and_nodes.r_node_capacitor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "r_node_capacitor.ckt", "Lumped" - ) - - def test_lumped_r_lead_inductor(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.r_lead_inductor == "0" - lumpdesign.leads_and_nodes.r_lead_inductor = "1n" - assert lumpdesign.leads_and_nodes.r_lead_inductor == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "r_lead_inductor.ckt", "Lumped" - ) - - def test_lumped_c_node_compensate(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.c_node_compensate is False - lumpdesign.leads_and_nodes.c_node_compensate = True - assert lumpdesign.leads_and_nodes.c_node_compensate - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "c_node_compensate.ckt", "Lumped" - ) - - def test_lumped_l_node_compensate(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.leads_and_nodes.l_node_compensate is False - lumpdesign.leads_and_nodes.l_node_compensate = True - assert lumpdesign.leads_and_nodes.l_node_compensate - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "l_node_compensate.ckt", "Lumped" - ) + def test_lumped_c_node_capacitor(self, lumped_design): + assert lumped_design.leads_and_nodes.c_node_capacitor == "0" + lumped_design.leads_and_nodes.c_node_capacitor = "1n" + assert lumped_design.leads_and_nodes.c_node_capacitor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("c_node_capacitor.ckt", "Lumped") + + def test_lumped_c_lead_inductor(self, lumped_design): + assert lumped_design.leads_and_nodes.c_lead_inductor == "0" + lumped_design.leads_and_nodes.c_lead_inductor = "1n" + assert lumped_design.leads_and_nodes.c_lead_inductor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("c_lead_inductor.ckt", "Lumped") + + def test_lumped_l_node_capacitor(self, lumped_design): + assert lumped_design.leads_and_nodes.l_node_capacitor == "0" + lumped_design.leads_and_nodes.l_node_capacitor = "1n" + assert lumped_design.leads_and_nodes.l_node_capacitor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("l_node_capacitor.ckt", "Lumped") + + def test_lumped_l_lead_inductor(self, lumped_design): + assert lumped_design.leads_and_nodes.l_lead_inductor == "0" + lumped_design.leads_and_nodes.l_lead_inductor = "1n" + assert lumped_design.leads_and_nodes.l_lead_inductor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("l_lead_inductor.ckt", "Lumped") + + def test_lumped_r_node_capacitor(self, lumped_design): + assert lumped_design.leads_and_nodes.r_node_capacitor == "0" + lumped_design.leads_and_nodes.r_node_capacitor = "1n" + assert lumped_design.leads_and_nodes.r_node_capacitor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("r_node_capacitor.ckt", "Lumped") + + def test_lumped_r_lead_inductor(self, lumped_design): + assert lumped_design.leads_and_nodes.r_lead_inductor == "0" + lumped_design.leads_and_nodes.r_lead_inductor = "1n" + assert lumped_design.leads_and_nodes.r_lead_inductor == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("r_lead_inductor.ckt", "Lumped") + + def test_lumped_c_node_compensate(self, lumped_design): + assert lumped_design.leads_and_nodes.c_node_compensate is False + lumped_design.leads_and_nodes.c_node_compensate = True + assert lumped_design.leads_and_nodes.c_node_compensate + assert lumped_design.topology.netlist().splitlines() == read_resource_file("c_node_compensate.ckt", "Lumped") + + def test_lumped_l_node_compensate(self, lumped_design): + assert lumped_design.leads_and_nodes.l_node_compensate is False + lumped_design.leads_and_nodes.l_node_compensate = True + assert lumped_design.leads_and_nodes.l_node_compensate + assert lumped_design.topology.netlist().splitlines() == read_resource_file("l_node_compensate.ckt", "Lumped") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py index 57f2426b74e..7d8d6d29c1e 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_parasitics.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -36,66 +34,50 @@ @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_lumped_capacitor_q(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.capacitor_q == "Inf" - lumpdesign.parasitics.capacitor_q = "100" - assert lumpdesign.parasitics.capacitor_q == "100" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_q.ckt", "Lumped") - - def test_lumped_capacitor_rs(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.capacitor_rs == "0" - lumpdesign.parasitics.capacitor_rs = "1" - assert lumpdesign.parasitics.capacitor_rs == "1" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rs.ckt", "Lumped") - - def test_lumped_capacitor_rp(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.capacitor_rp == "Inf" - lumpdesign.parasitics.capacitor_rp = "1000" - assert lumpdesign.parasitics.capacitor_rp == "1000" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_rp.ckt", "Lumped") - - def test_lumped_capacitor_ls(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.capacitor_ls == "0" - lumpdesign.parasitics.capacitor_ls = "1n" - assert lumpdesign.parasitics.capacitor_ls == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("capacitor_ls.ckt", "Lumped") - - def test_lumped_inductor_q(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.inductor_q == "Inf" - lumpdesign.parasitics.inductor_q = "100" - assert lumpdesign.parasitics.inductor_q == "100" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_q.ckt", "Lumped") - - def test_lumped_inductor_rs(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.inductor_rs == "0" - lumpdesign.parasitics.inductor_rs = "1" - assert lumpdesign.parasitics.inductor_rs == "1" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rs.ckt", "Lumped") - - def test_lumped_inductor_rp(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.inductor_rp == "Inf" - lumpdesign.parasitics.inductor_rp = "1000" - assert lumpdesign.parasitics.inductor_rp == "1000" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_rp.ckt", "Lumped") - - def test_lumped_inductor_cp(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.parasitics.inductor_cp == "0" - lumpdesign.parasitics.inductor_cp = "1n" - assert lumpdesign.parasitics.inductor_cp == "1n" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("inductor_cp.ckt", "Lumped") + def test_lumped_capacitor_q(self, lumped_design): + assert lumped_design.parasitics.capacitor_q == "Inf" + lumped_design.parasitics.capacitor_q = "100" + assert lumped_design.parasitics.capacitor_q == "100" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("capacitor_q.ckt", "Lumped") + + def test_lumped_capacitor_rs(self, lumped_design): + assert lumped_design.parasitics.capacitor_rs == "0" + lumped_design.parasitics.capacitor_rs = "1" + assert lumped_design.parasitics.capacitor_rs == "1" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("capacitor_rs.ckt", "Lumped") + + def test_lumped_capacitor_rp(self, lumped_design): + assert lumped_design.parasitics.capacitor_rp == "Inf" + lumped_design.parasitics.capacitor_rp = "1000" + assert lumped_design.parasitics.capacitor_rp == "1000" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("capacitor_rp.ckt", "Lumped") + + def test_lumped_capacitor_ls(self, lumped_design): + assert lumped_design.parasitics.capacitor_ls == "0" + lumped_design.parasitics.capacitor_ls = "1n" + assert lumped_design.parasitics.capacitor_ls == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("capacitor_ls.ckt", "Lumped") + + def test_lumped_inductor_q(self, lumped_design): + assert lumped_design.parasitics.inductor_q == "Inf" + lumped_design.parasitics.inductor_q = "100" + assert lumped_design.parasitics.inductor_q == "100" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("inductor_q.ckt", "Lumped") + + def test_lumped_inductor_rs(self, lumped_design): + assert lumped_design.parasitics.inductor_rs == "0" + lumped_design.parasitics.inductor_rs = "1" + assert lumped_design.parasitics.inductor_rs == "1" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("inductor_rs.ckt", "Lumped") + + def test_lumped_inductor_rp(self, lumped_design): + assert lumped_design.parasitics.inductor_rp == "Inf" + lumped_design.parasitics.inductor_rp = "1000" + assert lumped_design.parasitics.inductor_rp == "1000" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("inductor_rp.ckt", "Lumped") + + def test_lumped_inductor_cp(self, lumped_design): + assert lumped_design.parasitics.inductor_cp == "0" + lumped_design.parasitics.inductor_cp = "1n" + assert lumped_design.parasitics.inductor_cp == "1n" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("inductor_cp.ckt", "Lumped") diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py index dff2a082609..8bfcbf79d05 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_termination_impedance_table.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.lumped_termination_impedance_table import ComplexReactanceType from ansys.aedt.core.filtersolutions_core.lumped_termination_impedance_table import ComplexTerminationDefinition from ansys.aedt.core.generic.general_methods import is_linux @@ -35,141 +33,121 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_row_count(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - assert lumpdesign.source_impedance_table.row_count == 3 - assert lumpdesign.load_impedance_table.row_count == 3 - - def test_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - assert lumpdesign.source_impedance_table.row(0) == ("0.100G", "1.000", "0.000") - assert lumpdesign.load_impedance_table.row(0) == ("0.100G", "1.000", "0.000") - - def test_update_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True + def test_row_count(self, lumped_design): + lumped_design.topology.complex_termination = True + assert lumped_design.source_impedance_table.row_count == 3 + assert lumped_design.load_impedance_table.row_count == 3 + + def test_row(self, lumped_design): + lumped_design.topology.complex_termination = True + assert lumped_design.source_impedance_table.row(0) == ("0.100G", "1.000", "0.000") + assert lumped_design.load_impedance_table.row(0) == ("0.100G", "1.000", "0.000") + + def test_update_row(self, lumped_design): + lumped_design.topology.complex_termination = True with pytest.raises(RuntimeError) as info: - lumpdesign.source_impedance_table.update_row(0) + lumped_design.source_impedance_table.update_row(0) assert info.value.args[0] == "There is no input value to update" with pytest.raises(RuntimeError) as info: - lumpdesign.load_impedance_table.update_row(0) + lumped_design.load_impedance_table.update_row(0) assert info.value.args[0] == "There is no input value to update" - lumpdesign.source_impedance_table.update_row(0, "2G", "22", "11") - assert lumpdesign.source_impedance_table.row(0) == ("2G", "22", "11") - lumpdesign.load_impedance_table.update_row(0, "2G", "22", "11") - assert lumpdesign.load_impedance_table.row(0) == ("2G", "22", "11") - lumpdesign.source_impedance_table.update_row(0, frequency="4G") - assert lumpdesign.source_impedance_table.row(0) == ("4G", "22", "11") - lumpdesign.load_impedance_table.update_row(0, frequency="4G") - assert lumpdesign.load_impedance_table.row(0) == ("4G", "22", "11") - lumpdesign.source_impedance_table.update_row(0, "2G", "50", "0") - assert lumpdesign.source_impedance_table.row(0) == ("2G", "50", "0") - lumpdesign.load_impedance_table.update_row(0, "2G", "50", "0") - assert lumpdesign.load_impedance_table.row(0) == ("2G", "50", "0") - - def test_append_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - lumpdesign.source_impedance_table.append_row("100M", "10", "20") - assert lumpdesign.source_impedance_table.row_count == 4 - assert lumpdesign.source_impedance_table.row(3) == ("100M", "10", "20") - lumpdesign.topology.complex_termination = True - lumpdesign.load_impedance_table.append_row("100M", "10", "20") - assert lumpdesign.load_impedance_table.row_count == 4 - assert lumpdesign.load_impedance_table.row(3) == ("100M", "10", "20") - - def test_insert_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - lumpdesign.source_impedance_table.insert_row(0, "2G", "50", "0") - assert lumpdesign.source_impedance_table.row(0) == ("2G", "50", "0") - lumpdesign.load_impedance_table.insert_row(0, "2G", "50", "0") - assert lumpdesign.load_impedance_table.row(0) == ("2G", "50", "0") - - def test_remove_row(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - lumpdesign.source_impedance_table.remove_row(0) - assert lumpdesign.source_impedance_table.row(0) == ("1.000G", "1.000", "0.000") + lumped_design.source_impedance_table.update_row(0, "2G", "22", "11") + assert lumped_design.source_impedance_table.row(0) == ("2G", "22", "11") + lumped_design.load_impedance_table.update_row(0, "2G", "22", "11") + assert lumped_design.load_impedance_table.row(0) == ("2G", "22", "11") + lumped_design.source_impedance_table.update_row(0, frequency="4G") + assert lumped_design.source_impedance_table.row(0) == ("4G", "22", "11") + lumped_design.load_impedance_table.update_row(0, frequency="4G") + assert lumped_design.load_impedance_table.row(0) == ("4G", "22", "11") + lumped_design.source_impedance_table.update_row(0, "2G", "50", "0") + assert lumped_design.source_impedance_table.row(0) == ("2G", "50", "0") + lumped_design.load_impedance_table.update_row(0, "2G", "50", "0") + assert lumped_design.load_impedance_table.row(0) == ("2G", "50", "0") + + def test_append_row(self, lumped_design): + lumped_design.topology.complex_termination = True + lumped_design.source_impedance_table.append_row("100M", "10", "20") + assert lumped_design.source_impedance_table.row_count == 4 + assert lumped_design.source_impedance_table.row(3) == ("100M", "10", "20") + lumped_design.topology.complex_termination = True + lumped_design.load_impedance_table.append_row("100M", "10", "20") + assert lumped_design.load_impedance_table.row_count == 4 + assert lumped_design.load_impedance_table.row(3) == ("100M", "10", "20") + + def test_insert_row(self, lumped_design): + lumped_design.topology.complex_termination = True + lumped_design.source_impedance_table.insert_row(0, "2G", "50", "0") + assert lumped_design.source_impedance_table.row(0) == ("2G", "50", "0") + lumped_design.load_impedance_table.insert_row(0, "2G", "50", "0") + assert lumped_design.load_impedance_table.row(0) == ("2G", "50", "0") + + def test_remove_row(self, lumped_design): + lumped_design.topology.complex_termination = True + lumped_design.source_impedance_table.remove_row(0) + assert lumped_design.source_impedance_table.row(0) == ("1.000G", "1.000", "0.000") with pytest.raises(RuntimeError) as info: - lumpdesign.source_impedance_table.row(2) + lumped_design.source_impedance_table.row(2) assert info.value.args[0] == "No value is set for this band" - lumpdesign.load_impedance_table.remove_row(0) - assert lumpdesign.load_impedance_table.row(0) == ("1.000G", "1.000", "0.000") + lumped_design.load_impedance_table.remove_row(0) + assert lumped_design.load_impedance_table.row(0) == ("1.000G", "1.000", "0.000") with pytest.raises(RuntimeError) as info: - lumpdesign.load_impedance_table.row(2) + lumped_design.load_impedance_table.row(2) assert info.value.args[0] == "No value is set for this band" - def test_complex_definition(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True + def test_complex_definition(self, lumped_design): + lumped_design.topology.complex_termination = True assert len(ComplexTerminationDefinition) == 4 - assert lumpdesign.source_impedance_table.complex_definition == ComplexTerminationDefinition.CARTESIAN + assert lumped_design.source_impedance_table.complex_definition == ComplexTerminationDefinition.CARTESIAN for cdef in ComplexTerminationDefinition: - lumpdesign.source_impedance_table.complex_definition = cdef - assert lumpdesign.source_impedance_table.complex_definition == cdef - assert lumpdesign.load_impedance_table.complex_definition == ComplexTerminationDefinition.CARTESIAN + lumped_design.source_impedance_table.complex_definition = cdef + assert lumped_design.source_impedance_table.complex_definition == cdef + assert lumped_design.load_impedance_table.complex_definition == ComplexTerminationDefinition.CARTESIAN for cdef in ComplexTerminationDefinition: - lumpdesign.load_impedance_table.complex_definition = cdef - assert lumpdesign.load_impedance_table.complex_definition == cdef - - def test_reactance_type(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) + lumped_design.load_impedance_table.complex_definition = cdef + assert lumped_design.load_impedance_table.complex_definition == cdef - lumpdesign.topology.complex_termination = True + def test_reactance_type(self, lumped_design): + lumped_design.topology.complex_termination = True assert len(ComplexReactanceType) == 3 - assert lumpdesign.source_impedance_table.reactance_type == ComplexReactanceType.REAC + assert lumped_design.source_impedance_table.reactance_type == ComplexReactanceType.REAC for creac in ComplexReactanceType: - lumpdesign.source_impedance_table.reactance_type = creac - assert lumpdesign.source_impedance_table.reactance_type == creac - assert lumpdesign.load_impedance_table.reactance_type == ComplexReactanceType.REAC + lumped_design.source_impedance_table.reactance_type = creac + assert lumped_design.source_impedance_table.reactance_type == creac + assert lumped_design.load_impedance_table.reactance_type == ComplexReactanceType.REAC for creac in ComplexReactanceType: - lumpdesign.load_impedance_table.reactance_type = creac - assert lumpdesign.load_impedance_table.reactance_type == creac - - def test_compensation_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - assert lumpdesign.source_impedance_table.compensation_enabled is False - lumpdesign.source_impedance_table.compensation_enabled = True - assert lumpdesign.source_impedance_table.compensation_enabled - assert lumpdesign.load_impedance_table.compensation_enabled is False - lumpdesign.load_impedance_table.compensation_enabled = True - assert lumpdesign.load_impedance_table.compensation_enabled - - def test_compensation_order(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - lumpdesign.source_impedance_table.compensation_enabled = True - assert lumpdesign.source_impedance_table.compensation_order == 2 + lumped_design.load_impedance_table.reactance_type = creac + assert lumped_design.load_impedance_table.reactance_type == creac + + def test_compensation_enabled(self, lumped_design): + lumped_design.topology.complex_termination = True + assert lumped_design.source_impedance_table.compensation_enabled is False + lumped_design.source_impedance_table.compensation_enabled = True + assert lumped_design.source_impedance_table.compensation_enabled + assert lumped_design.load_impedance_table.compensation_enabled is False + lumped_design.load_impedance_table.compensation_enabled = True + assert lumped_design.load_impedance_table.compensation_enabled + + def test_compensation_order(self, lumped_design): + lumped_design.topology.complex_termination = True + lumped_design.source_impedance_table.compensation_enabled = True + assert lumped_design.source_impedance_table.compensation_order == 2 with pytest.raises(RuntimeError) as info: - lumpdesign.source_impedance_table.compensation_order = 0 + lumped_design.source_impedance_table.compensation_order = 0 assert info.value.args[0] == "The minimum impedance compensation order is 1" for i in range(1, 22): - lumpdesign.source_impedance_table.compensation_order = i - assert lumpdesign.source_impedance_table.compensation_order == i + lumped_design.source_impedance_table.compensation_order = i + assert lumped_design.source_impedance_table.compensation_order == i with pytest.raises(RuntimeError) as info: - lumpdesign.source_impedance_table.compensation_order = 22 + lumped_design.source_impedance_table.compensation_order = 22 assert info.value.args[0] == "The maximum impedance compensation order is 21" - lumpdesign.load_impedance_table.compensation_enabled = True - assert lumpdesign.load_impedance_table.compensation_order == 2 + lumped_design.load_impedance_table.compensation_enabled = True + assert lumped_design.load_impedance_table.compensation_order == 2 with pytest.raises(RuntimeError) as info: - lumpdesign.load_impedance_table.compensation_order = 0 + lumped_design.load_impedance_table.compensation_order = 0 assert info.value.args[0] == "The minimum impedance compensation order is 1" for i in range(1, 22): - lumpdesign.load_impedance_table.compensation_order = i - assert lumpdesign.load_impedance_table.compensation_order == i + lumped_design.load_impedance_table.compensation_order = i + assert lumped_design.load_impedance_table.compensation_order == i with pytest.raises(RuntimeError) as info: - lumpdesign.load_impedance_table.compensation_order = 22 + lumped_design.load_impedance_table.compensation_order = 22 assert info.value.args[0] == "The maximum impedance compensation order is 21" diff --git a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py index 90fe1d73a78..41c0a0b1f4d 100644 --- a/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_lumped_filter/test_lumped_topology.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.filtersolutions_core.attributes import DiplexerType from ansys.aedt.core.filtersolutions_core.attributes import FilterClass from ansys.aedt.core.filtersolutions_core.attributes import FilterType @@ -38,325 +36,253 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_lumped_generator_resistor_30(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.generator_resistor == "50" - lumpdesign.topology.generator_resistor = "30" - assert lumpdesign.topology.generator_resistor == "30" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "generator_resistor.ckt", "Lumped" - ) - - def test_lumped_load_resistor_30(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.load_resistor == "50" - lumpdesign.topology.load_resistor = "30" - assert lumpdesign.topology.load_resistor == "30" - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("laod_resistor.ckt", "Lumped") - - def test_lumped_current_source(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.current_source is False - lumpdesign.topology.current_source = True - assert lumpdesign.topology.current_source - - def test_lumped_first_shunt(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.first_shunt - lumpdesign.topology.first_shunt = True - assert lumpdesign.topology.first_shunt - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_shunt.ckt", "Lumped") - - def test_lumped_first_series(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.first_shunt - lumpdesign.topology.first_shunt = False - assert lumpdesign.topology.first_shunt is False - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("first_series.ckt", "Lumped") - - def test_lumped_bridge_t(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.bridge_t is False - lumpdesign.topology.bridge_t = True - assert lumpdesign.topology.bridge_t - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t.ckt", "Lumped") - - def test_lumped_bridge_t_low(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 - lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO - assert lumpdesign.attributes.diplexer_type == DiplexerType.HI_LO - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.bridge_t_low is False - lumpdesign.topology.bridge_t_low = True - assert lumpdesign.topology.bridge_t_low - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_low.ckt", "Lumped") - - def test_lumped_bridge_t_high(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 - lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO - assert lumpdesign.attributes.diplexer_type == DiplexerType.HI_LO - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.bridge_t_high is False - lumpdesign.topology.bridge_t_high = True - assert lumpdesign.topology.bridge_t_high - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("bridge_t_high.ckt", "Lumped") - - def test_lumped_equal_inductors(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.topology.equal_inductors is False - lumpdesign.topology.equal_inductors = True - assert lumpdesign.topology.equal_inductors - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "equal_inductors.ckt", "Lumped" - ) - - def test_lumped_equal_capacitors(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - lumpdesign.topology.zig_zag = True - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.min_cap is False - assert lumpdesign.topology.equal_capacitors is False - lumpdesign.topology.min_cap = True - lumpdesign.topology.equal_capacitors = True - assert lumpdesign.topology.min_cap - assert lumpdesign.topology.equal_capacitors - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "equal_capacitors.ckt", "Lumped" - ) - - def test_lumped_equal_legs(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.topology.equal_legs is False - lumpdesign.topology.equal_legs = True - assert lumpdesign.topology.equal_legs - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("equal_legs.ckt", "Lumped") - - def test_lumped_high_low_pass(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.topology.high_low_pass is False - lumpdesign.topology.high_low_pass = True - assert lumpdesign.topology.high_low_pass - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("high_low_pass.ckt", "Lumped") - - def test_lumped_high_low_pass_min_ind(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.high_low_pass_min_ind is False - lumpdesign.topology.high_low_pass_min_ind = True - assert lumpdesign.topology.high_low_pass_min_ind - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + def test_lumped_source_resistance_30(self, lumped_design): + assert lumped_design.topology.source_resistance == "50" + lumped_design.topology.source_resistance = "30" + assert lumped_design.topology.source_resistance == "30" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("source_resistance.ckt", "Lumped") + + def test_lumped_load_resistance_30(self, lumped_design): + assert lumped_design.topology.load_resistance == "50" + lumped_design.topology.load_resistance = "30" + assert lumped_design.topology.load_resistance == "30" + assert lumped_design.topology.netlist().splitlines() == read_resource_file("laod_resistance.ckt", "Lumped") + + def test_lumped_current_source(self, lumped_design): + assert lumped_design.topology.current_source is False + lumped_design.topology.current_source = True + assert lumped_design.topology.current_source + + def test_lumped_first_shunt(self, lumped_design): + assert lumped_design.topology.first_shunt + lumped_design.topology.first_shunt = True + assert lumped_design.topology.first_shunt + assert lumped_design.topology.netlist().splitlines() == read_resource_file("first_shunt.ckt", "Lumped") + + def test_lumped_first_series(self, lumped_design): + assert lumped_design.topology.first_shunt + lumped_design.topology.first_shunt = False + assert lumped_design.topology.first_shunt is False + assert lumped_design.topology.netlist().splitlines() == read_resource_file("first_series.ckt", "Lumped") + + def test_lumped_bridge_t(self, lumped_design): + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.bridge_t is False + lumped_design.topology.bridge_t = True + assert lumped_design.topology.bridge_t + assert lumped_design.topology.netlist().splitlines() == read_resource_file("bridge_t.ckt", "Lumped") + + def test_lumped_bridge_t_low(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_1 + lumped_design.attributes.diplexer_type = DiplexerType.HI_LO + assert lumped_design.attributes.diplexer_type == DiplexerType.HI_LO + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.bridge_t_low is False + lumped_design.topology.bridge_t_low = True + assert lumped_design.topology.bridge_t_low + assert lumped_design.topology.netlist().splitlines() == read_resource_file("bridge_t_low.ckt", "Lumped") + + def test_lumped_bridge_t_high(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_1 + lumped_design.attributes.diplexer_type = DiplexerType.HI_LO + assert lumped_design.attributes.diplexer_type == DiplexerType.HI_LO + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.bridge_t_high is False + lumped_design.topology.bridge_t_high = True + assert lumped_design.topology.bridge_t_high + assert lumped_design.topology.netlist().splitlines() == read_resource_file("bridge_t_high.ckt", "Lumped") + + def test_lumped_equal_inductors(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.topology.equal_inductors is False + lumped_design.topology.equal_inductors = True + assert lumped_design.topology.equal_inductors + assert lumped_design.topology.netlist().splitlines() == read_resource_file("equal_inductors.ckt", "Lumped") + + def test_lumped_equal_capacitors(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.topology.zig_zag = True + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag + assert lumped_design.topology.min_cap is False + assert lumped_design.topology.equal_capacitors is False + lumped_design.topology.min_cap = True + lumped_design.topology.equal_capacitors = True + assert lumped_design.topology.min_cap + assert lumped_design.topology.equal_capacitors + assert lumped_design.topology.netlist().splitlines() == read_resource_file("equal_capacitors.ckt", "Lumped") + + def test_lumped_equal_legs(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.topology.equal_legs is False + lumped_design.topology.equal_legs = True + assert lumped_design.topology.equal_legs + assert lumped_design.topology.netlist().splitlines() == read_resource_file("equal_legs.ckt", "Lumped") + + def test_lumped_high_low_pass(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.topology.high_low_pass is False + lumped_design.topology.high_low_pass = True + assert lumped_design.topology.high_low_pass + assert lumped_design.topology.netlist().splitlines() == read_resource_file("high_low_pass.ckt", "Lumped") + + def test_lumped_high_low_pass_min_ind(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.high_low_pass_min_ind is False + lumped_design.topology.high_low_pass_min_ind = True + assert lumped_design.topology.high_low_pass_min_ind + assert lumped_design.topology.netlist().splitlines() == read_resource_file( "high_low_pass_min_ind.ckt", "Lumped" ) - def test_lumped_zig_zag(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag is False - lumpdesign.topology.zig_zag = True - assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("zig_zag.ckt", "Lumped") - - def test_lumped_min_ind(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - lumpdesign.topology.zig_zag = True - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.min_ind - lumpdesign.topology.min_ind = True - assert lumpdesign.topology.min_ind - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_ind.ckt", "Lumped") - - def test_lumped_min_cap(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - lumpdesign.topology.zig_zag = True - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.min_cap is False - lumpdesign.topology.min_cap = True - assert lumpdesign.topology.min_cap - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("min_cap.ckt", "Lumped") - - def test_lumped_set_source_res(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - lumpdesign.topology.zig_zag = True - lumpdesign.topology.set_source_res = False - assert lumpdesign.topology.set_source_res is False - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag - lumpdesign.topology.set_source_res = True - assert lumpdesign.topology.set_source_res - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("set_source_res.ckt", "Lumped") - - def test_lumped_trap_topology(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - lumpdesign.topology.zig_zag = True - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.zig_zag - assert lumpdesign.topology.trap_topology is False - lumpdesign.topology.trap_topology = True - assert lumpdesign.topology.trap_topology - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("trap_topology.ckt", "Lumped") - - def test_lumped_node_cap_ground(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.attributes.filter_type = FilterType.ELLIPTIC - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.attributes.filter_type == FilterType.ELLIPTIC - assert lumpdesign.topology.node_cap_ground is False - lumpdesign.topology.node_cap_ground = True - assert lumpdesign.topology.node_cap_ground - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "node_cap_ground.ckt", "Lumped" - ) - - def test_lumped_match_impedance(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.BAND_PASS - lumpdesign.topology.generator_resistor = "75" - assert lumpdesign.attributes.filter_class == FilterClass.BAND_PASS - assert lumpdesign.topology.generator_resistor == "75" - assert lumpdesign.topology.match_impedance is False - lumpdesign.topology.match_impedance = True - assert lumpdesign.topology.match_impedance - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "match_impedance.ckt", "Lumped" - ) - - def test_lumped_complex_termination(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.complex_termination is False - lumpdesign.topology.complex_termination = True - assert lumpdesign.topology.complex_termination - - def test_complex_element_tune_enabled(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.topology.complex_termination = True - assert lumpdesign.topology.complex_element_tune_enabled - lumpdesign.topology.complex_element_tune_enabled = False - assert lumpdesign.topology.complex_element_tune_enabled is False - - def test_lumped_circuit_export(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("netlist.ckt", "Lumped") - - def test_lumped_diplexer1_hi_lo(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 - lumpdesign.attributes.diplexer_type = DiplexerType.HI_LO - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 - assert lumpdesign.attributes.diplexer_type == DiplexerType.HI_LO - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "diplexer1_hi_lo.ckt", "Lumped" - ) - - def test_lumped_diplexer1_bp_1(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 - lumpdesign.attributes.diplexer_type = DiplexerType.BP_1 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 - assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_1 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_1.ckt", "Lumped") - - def test_lumped_diplexer1_bp_2(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_1 - lumpdesign.attributes.diplexer_type = DiplexerType.BP_2 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_1 - assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_2 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file("diplexer1_bp_2.ckt", "Lumped") - - def test_lumped_diplexer2_bp_bs(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 - lumpdesign.attributes.diplexer_type = DiplexerType.BP_BS - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 - assert lumpdesign.attributes.diplexer_type == DiplexerType.BP_BS - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( - "diplexer2_bp_bs.ckt", "Lumped" - ) - - def test_lumped_diplexer2_triplexer_1(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 - lumpdesign.attributes.diplexer_type = DiplexerType.TRIPLEXER_1 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 - assert lumpdesign.attributes.diplexer_type == DiplexerType.TRIPLEXER_1 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + def test_lumped_zig_zag(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag is False + lumped_design.topology.zig_zag = True + assert lumped_design.topology.zig_zag + assert lumped_design.topology.netlist().splitlines() == read_resource_file("zig_zag.ckt", "Lumped") + + def test_lumped_min_ind(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.topology.zig_zag = True + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag + assert lumped_design.topology.min_ind + lumped_design.topology.min_ind = True + assert lumped_design.topology.min_ind + assert lumped_design.topology.netlist().splitlines() == read_resource_file("min_ind.ckt", "Lumped") + + def test_lumped_min_cap(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.topology.zig_zag = True + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag + assert lumped_design.topology.min_cap is False + lumped_design.topology.min_cap = True + assert lumped_design.topology.min_cap + assert lumped_design.topology.netlist().splitlines() == read_resource_file("min_cap.ckt", "Lumped") + + def test_lumped_set_source_res(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.topology.zig_zag = True + lumped_design.topology.set_source_res = False + assert lumped_design.topology.set_source_res is False + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag + lumped_design.topology.set_source_res = True + assert lumped_design.topology.set_source_res + assert lumped_design.topology.netlist().splitlines() == read_resource_file("set_source_res.ckt", "Lumped") + + def test_lumped_trap_topology(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + lumped_design.topology.zig_zag = True + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.zig_zag + assert lumped_design.topology.trap_topology is False + lumped_design.topology.trap_topology = True + assert lumped_design.topology.trap_topology + assert lumped_design.topology.netlist().splitlines() == read_resource_file("trap_topology.ckt", "Lumped") + + def test_lumped_node_cap_ground(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.attributes.filter_type = FilterType.ELLIPTIC + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.attributes.filter_type == FilterType.ELLIPTIC + assert lumped_design.topology.node_cap_ground is False + lumped_design.topology.node_cap_ground = True + assert lumped_design.topology.node_cap_ground + assert lumped_design.topology.netlist().splitlines() == read_resource_file("node_cap_ground.ckt", "Lumped") + + def test_lumped_match_impedance(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.BAND_PASS + lumped_design.topology.source_resistance = "75" + assert lumped_design.attributes.filter_class == FilterClass.BAND_PASS + assert lumped_design.topology.source_resistance == "75" + assert lumped_design.topology.match_impedance is False + lumped_design.topology.match_impedance = True + assert lumped_design.topology.match_impedance + assert lumped_design.topology.netlist().splitlines() == read_resource_file("match_impedance.ckt", "Lumped") + + def test_lumped_complex_termination(self, lumped_design): + assert lumped_design.topology.complex_termination is False + lumped_design.topology.complex_termination = True + assert lumped_design.topology.complex_termination + + def test_complex_element_tune_enabled(self, lumped_design): + lumped_design.topology.complex_termination = True + assert lumped_design.topology.complex_element_tune_enabled + lumped_design.topology.complex_element_tune_enabled = False + assert lumped_design.topology.complex_element_tune_enabled is False + + def test_lumped_circuit_export(self, lumped_design): + assert lumped_design.topology.netlist().splitlines() == read_resource_file("netlist.ckt", "Lumped") + + def test_lumped_diplexer1_hi_lo(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 + lumped_design.attributes.diplexer_type = DiplexerType.HI_LO + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_1 + assert lumped_design.attributes.diplexer_type == DiplexerType.HI_LO + assert lumped_design.topology.netlist().splitlines() == read_resource_file("diplexer1_hi_lo.ckt", "Lumped") + + def test_lumped_diplexer1_bp_1(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 + lumped_design.attributes.diplexer_type = DiplexerType.BP_1 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_1 + assert lumped_design.attributes.diplexer_type == DiplexerType.BP_1 + assert lumped_design.topology.netlist().splitlines() == read_resource_file("diplexer1_bp_1.ckt", "Lumped") + + def test_lumped_diplexer1_bp_2(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_1 + lumped_design.attributes.diplexer_type = DiplexerType.BP_2 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_1 + assert lumped_design.attributes.diplexer_type == DiplexerType.BP_2 + assert lumped_design.topology.netlist().splitlines() == read_resource_file("diplexer1_bp_2.ckt", "Lumped") + + def test_lumped_diplexer2_bp_bs(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_2 + lumped_design.attributes.diplexer_type = DiplexerType.BP_BS + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_2 + assert lumped_design.attributes.diplexer_type == DiplexerType.BP_BS + assert lumped_design.topology.netlist().splitlines() == read_resource_file("diplexer2_bp_bs.ckt", "Lumped") + + def test_lumped_diplexer2_triplexer_1(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_2 + lumped_design.attributes.diplexer_type = DiplexerType.TRIPLEXER_1 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_2 + assert lumped_design.attributes.diplexer_type == DiplexerType.TRIPLEXER_1 + assert lumped_design.topology.netlist().splitlines() == read_resource_file( "diplexer2_triplexer_1.ckt", "Lumped" ) - def test_lumped_diplexer2_triplexer_2(self): - lumpdesign = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - - lumpdesign.attributes.filter_class = FilterClass.DIPLEXER_2 - lumpdesign.attributes.diplexer_type = DiplexerType.TRIPLEXER_2 - assert lumpdesign.attributes.filter_class == FilterClass.DIPLEXER_2 - assert lumpdesign.attributes.diplexer_type == DiplexerType.TRIPLEXER_2 - assert lumpdesign.topology.circuit_response().splitlines() == read_resource_file( + def test_lumped_diplexer2_triplexer_2(self, lumped_design): + lumped_design.attributes.filter_class = FilterClass.DIPLEXER_2 + lumped_design.attributes.diplexer_type = DiplexerType.TRIPLEXER_2 + assert lumped_design.attributes.filter_class == FilterClass.DIPLEXER_2 + assert lumped_design.attributes.diplexer_type == DiplexerType.TRIPLEXER_2 + assert lumped_design.topology.netlist().splitlines() == read_resource_file( "diplexer2_triplexer_2.ckt", "Lumped" ) diff --git a/tests/system/general/test_45_FilterSolutions/test_raise_error.py b/tests/system/general/test_45_FilterSolutions/test_raise_error.py index 8015dc8b992..e43187664f7 100644 --- a/tests/system/general/test_45_FilterSolutions/test_raise_error.py +++ b/tests/system/general/test_45_FilterSolutions/test_raise_error.py @@ -22,8 +22,6 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. -import ansys.aedt.core -import ansys.aedt.core.filtersolutions from ansys.aedt.core.generic.general_methods import is_linux import pytest @@ -34,9 +32,7 @@ @pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.1", reason="Skipped on versions earlier than 2025.1") class TestClass: - def test_raise_error(self): - design = ansys.aedt.core.filtersolutions.LumpDesign(config["desktopVersion"]) - + def test_raise_error(self, lumped_design): with pytest.raises(RuntimeError) as info: - design.transmission_zeros_ratio.row(0) + lumped_design.transmission_zeros_ratio.row(0) assert info.value.args[0] == test_transmission_zeros.TestClass.no_transmission_zero_msg From 25dce1787980931f9ec1af531411338c2d10a04a Mon Sep 17 00:00:00 2001 From: raghajaf Date: Mon, 6 Jan 2025 17:01:42 -0500 Subject: [PATCH 5/6] FEAT: Add distributed filter netlist update --- src/ansys/aedt/core/filtersolutions_core/lumped_topology.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py index f7ad4b2e7ca..3265274c489 100644 --- a/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py +++ b/src/ansys/aedt/core/filtersolutions_core/lumped_topology.py @@ -537,7 +537,7 @@ def complex_element_tune_enabled(self, complex_element_tune_enabled: bool): def netlist(self): """Execute real filter synthesis""" size = c_int() - status = self._dll.getLumpedCircuitResponseSize(byref(size)) + status = self._dll.getLumpedNetlistSize(byref(size)) ansys.aedt.core.filtersolutions_core._dll_interface().raise_error(status) - netlist_string = self._dll_interface.get_string(self._dll.getLumpedCircuitResponse, max_size=size.value) + netlist_string = self._dll_interface.get_string(self._dll.getLumpedNetlist, max_size=size.value) return netlist_string From c716cee0d42ed637505763962fcc9086b4fb4b79 Mon Sep 17 00:00:00 2001 From: raghajaf Date: Wed, 8 Jan 2025 15:32:58 -0500 Subject: [PATCH 6/6] FEAT: Error Messages are updated --- .../Distributed/open_stub_ground_true.ckt | 10 +- .../test_distributed_topology.py | 250 +++++++++++++++--- 2 files changed, 219 insertions(+), 41 deletions(-) diff --git a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt index 2ed3460232e..320dbd82d32 100644 --- a/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt +++ b/tests/system/general/test_45_FilterSolutions/resources/Distributed/open_stub_ground_true.ckt @@ -4,15 +4,15 @@ V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0 Rg 1 2 50 MXTcoup0 2 5 6 3 Wid=0.0009605 Gap=0.00045 Len=0.02903 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MT0 4 5 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MT0 4 5 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=1.43 Tand=0.0005 MXTcoup1 6 9 10 7 Wid=0.0006633 Gap=0.0001582 Len=0.02955 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MT1 8 9 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MT1 8 9 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=1.43 Tand=0.0005 MXTcoup2 10 13 14 11 Wid=0.0005798 Gap=0.0001159 Len=0.02969 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MT2 12 13 Wid=0.0005798 Len=0.02969 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MT2 12 13 Wid=0.0005798 Len=0.02969 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=1.43 Tand=0.0005 MXTcoup3 14 17 18 15 Wid=0.0006633 Gap=0.0001582 Len=0.02955 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MT3 16 17 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MT3 16 17 Wid=0.0006633 Len=0.02955 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=1.43 Tand=0.0005 MXTcoup4 18 21 22 19 Wid=0.0009605 Gap=0.00045 Len=0.02903 Er=9.8 Height=0.00127 Thick=2.54E-06 Rho=1.43 Tand=0.0005 -MT4 20 21 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=0.00127 Tand=-NAN +MT4 20 21 Wid=0.0009605 Len=0.02903 Er=9.8 Thick=2.54E-06 Height=0.00127 Rho=1.43 Tand=0.0005 Rl 22 0 50 * .AC DEC 200 2E+08 5E+09 diff --git a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py index 4676b2dffc1..757a456e79e 100644 --- a/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py +++ b/tests/system/general/test_45_FilterSolutions/test_distributed_filter/test_distributed_topology.py @@ -34,7 +34,25 @@ from ..resources import read_resource_file -@pytest.mark.skipif(is_linux, reason="FilterSolutions API is not supported on Linux.") +def convert_string(input_string) -> str: + """ + Convert a string to have all words capitalized. + + Parameters + ---------- + input_string: str + String to modify. + + Returns + ------- + str + String with all words capitalized. + """ + fixed_string = input_string.replace("_", " ").lower() + return " ".join(word.capitalize() for word in fixed_string.split()) + + +@pytest.mark.skipif(is_linux, reason="FilterSolutions API is not applicable on Linux.") @pytest.mark.skipif(config["desktopVersion"] < "2025.2", reason="Skipped on versions earlier than 2025.2") class TestClass: @@ -56,6 +74,16 @@ def test_distributed_load_resistance_30(self, distributed_design): def test_distributed_first_shunt(self, distributed_design): assert distributed_design.topology.first_shunt + with pytest.raises(RuntimeError) as info: + distributed_design.topology.topology_type = TopologyType.SPACED_STUBS + distributed_design.topology.first_shunt = False + assert ( + info.value.args[0] + == "The First Element Shunt or Series property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) + distributed_design.topology.topology_type = TopologyType.LUMPED_TRANSLATION assert distributed_design.topology.netlist().splitlines() == read_resource_file( "first_shunt.ckt", "Distributed" ) @@ -68,7 +96,12 @@ def test_distributed_first_shunt(self, distributed_design): def test_distributed_first_fat(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.first_fat = True - assert info.value.args[0] == "The First Segment Fat or Thin property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The First Element Fat or Thin property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.topology.topology_type = TopologyType.STEPPED_IMPEDANCE assert distributed_design.topology.first_fat assert distributed_design.topology.netlist().splitlines() == read_resource_file("first_fat.ckt", "Distributed") @@ -79,7 +112,12 @@ def test_distributed_first_fat(self, distributed_design): def test_distributed_use_series_caps(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.use_series_caps = True - assert info.value.args[0] == "The Series Caps property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Series Caps property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS assert distributed_design.topology.use_series_caps is False assert distributed_design.topology.netlist().splitlines() == read_resource_file( @@ -94,7 +132,12 @@ def test_distributed_use_series_caps(self, distributed_design): def test_distributed_combine_stubs(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.combine_stubs = True - assert info.value.args[0] == "The Combine Stubs property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Combine Stubs property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS assert distributed_design.topology.combine_stubs is False assert distributed_design.topology.netlist().splitlines() == read_resource_file( @@ -109,7 +152,12 @@ def test_distributed_combine_stubs(self, distributed_design): def test_use_coupled_lines(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.use_coupled_lines = True - assert info.value.args[0] == "The Coupled Lines property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Coupled Lines property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.attributes.filter_type = FilterType.ELLIPTIC assert distributed_design.topology.use_coupled_lines is False @@ -125,7 +173,12 @@ def test_use_coupled_lines(self, distributed_design): def test_equal_width_approx(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.equal_width_approx = True - assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Equal Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.INTERDIGITAL assert distributed_design.topology.equal_width_approx @@ -141,23 +194,33 @@ def test_equal_width_approx(self, distributed_design): def test_open_stub_ground(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.open_stub_ground = True - assert info.value.args[0] == "The Open Stub Ground property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Open Stub Ground property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_STOP distributed_design.topology.topology_type = TopologyType.NOTCH_RESONATORS assert distributed_design.topology.open_stub_ground is False assert distributed_design.topology.netlist().splitlines() == read_resource_file( "open_stub_ground_false.ckt", "Distributed" ) - # distributed_design.topology.open_stub_ground = True - # assert distributed_design.topology.open_stub_ground - # assert distributed_design.topology.netlist().splitlines() == read_resource_file( - # "open_stub_ground_true.ckt", "Distributed" - # ) + distributed_design.topology.open_stub_ground = True + assert distributed_design.topology.open_stub_ground + assert distributed_design.topology.netlist().splitlines() == read_resource_file( + "open_stub_ground_true.ckt", "Distributed" + ) def test_left_ground_side(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.left_ground_side = True - assert info.value.args[0] == "The Left Ground Side property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Left Ground Side property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_STOP distributed_design.topology.topology_type = TopologyType.NOTCH_RESONATORS assert distributed_design.topology.left_ground_side @@ -173,7 +236,12 @@ def test_left_ground_side(self, distributed_design): def test_equal_stub_widths(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.equal_stub_widths = True - assert info.value.args[0] == "The Equal Stub Widths property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Equal Stub Widths property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.SHUNT_STUB_RESONATORS assert distributed_design.topology.equal_stub_widths is False @@ -189,7 +257,12 @@ def test_equal_stub_widths(self, distributed_design): def test_center_z0_impedance_55(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.center_z0_impedance = "55" - assert info.value.args[0] == "The Center Z0 property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Center Z0 property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.SHUNT_STUB_RESONATORS distributed_design.topology.equal_stub_widths = False @@ -203,7 +276,12 @@ def test_center_z0_impedance_55(self, distributed_design): def test_equal_width_conductors(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.equal_width_conductors = True - assert info.value.args[0] == "The Equal Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Equal Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.equal_width_conductors @@ -219,7 +297,12 @@ def test_equal_width_conductors(self, distributed_design): def test_tapped(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.tapped = True - assert info.value.args[0] == "The Tapped property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tapped property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.tapped @@ -235,7 +318,12 @@ def test_tapped(self, distributed_design): def test_pinned(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.pinned = True - assert info.value.args[0] == "The Pinned property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Pinned property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.pinned is False @@ -253,7 +341,12 @@ def test_pinned(self, distributed_design): def test_stub_taps(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.stub_taps = True - assert info.value.args[0] == "The Stub Taps property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Stub Taps property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.stub_taps is False @@ -269,7 +362,12 @@ def test_stub_taps(self, distributed_design): def test_via_ends(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.via_ends = True - assert info.value.args[0] == "The Via Ends property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Via Ends property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.via_ends is False @@ -287,7 +385,12 @@ def test_via_ends(self, distributed_design): def test_resonator_line_width_5mm(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.resonator_line_width = "1.27 mm" - assert info.value.args[0] == "The Line Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Line Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.HAIRPIN assert distributed_design.topology.resonator_line_width == "1.27 mm" @@ -300,7 +403,12 @@ def test_resonator_line_width_5mm(self, distributed_design): def test_resonator_rotation_angle_5deg(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.resonator_rotation_angle = "0" - assert info.value.args[0] == "The Rotation Angle property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Rotation Angle property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.PARALLEL_EDGE_COUPLED assert distributed_design.topology.resonator_rotation_angle == "0" @@ -313,7 +421,12 @@ def test_resonator_rotation_angle_5deg(self, distributed_design): def test_mitered_corners(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.mitered_corners = True - assert info.value.args[0] == "The Mitered Corners property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Mitered Corners property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.HAIRPIN assert distributed_design.topology.mitered_corners is False @@ -329,7 +442,12 @@ def test_mitered_corners(self, distributed_design): def test_hairpin_gap_width_4mm(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.hairpin_gap_width = "0.127 mm" - assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Gap Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.HAIRPIN assert distributed_design.topology.hairpin_gap_width == "2.54 mm" @@ -342,7 +460,12 @@ def test_hairpin_gap_width_4mm(self, distributed_design): def test_miniature_hairpin_gap_width_450um(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.miniature_hairpin_gap_width = "635 um" - assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Gap Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN assert distributed_design.topology.miniature_hairpin_gap_width == "635 um" @@ -355,7 +478,12 @@ def test_miniature_hairpin_gap_width_450um(self, distributed_design): def test_ring_resonator_gap_width_450um(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.ring_resonator_gap_width = "635 um" - assert info.value.args[0] == "The Gap Width property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Gap Width property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.RING_RESONATOR assert distributed_design.topology.ring_resonator_gap_width == "635 um" @@ -368,7 +496,12 @@ def test_ring_resonator_gap_width_450um(self, distributed_design): def test_hairpin_extension_length_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.hairpin_extension_length = "0 mm" - assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tuning Extension property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.HAIRPIN assert distributed_design.topology.hairpin_extension_length == "0 um" @@ -381,7 +514,12 @@ def test_hairpin_extension_length_2mm(self, distributed_design): def test_miniature_hairpin_end_curl_extension_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.miniature_hairpin_end_curl_extension = "0 mm" - assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tuning Extension property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN assert distributed_design.topology.miniature_hairpin_end_curl_extension == "0 um" @@ -394,7 +532,12 @@ def test_miniature_hairpin_end_curl_extension_2mm(self, distributed_design): def test_ring_resonator_end_gap_extension_2mm(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.ring_resonator_end_gap_extension = "0 mm" - assert info.value.args[0] == "The Tuning Extension property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tuning Extension property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.RING_RESONATOR assert distributed_design.topology.ring_resonator_end_gap_extension == "0 um" @@ -407,7 +550,12 @@ def test_ring_resonator_end_gap_extension_2mm(self, distributed_design): def test_tuning_type_1(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.tuning_type_1 = True - assert info.value.args[0] == "The Tuning Type property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tuning Type property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.HAIRPIN assert distributed_design.topology.tuning_type_1 @@ -423,7 +571,12 @@ def test_tuning_type_1(self, distributed_design): def test_tap_position(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.tap_position = TapPosition.AUTO - assert info.value.args[0] == "The Tap Position property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Tap Position property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.MINIATURE_HAIRPIN assert distributed_design.topology.tap_position == TapPosition.AUTO @@ -439,7 +592,12 @@ def test_tap_position(self, distributed_design): def test_wide_band(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.wide_band = True - assert info.value.args[0] == "The Wide Band property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Wide Band property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.INTERDIGITAL assert distributed_design.topology.wide_band is False @@ -457,7 +615,12 @@ def test_wide_band(self, distributed_design): def test_open_ends(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.open_ends = True - assert info.value.args[0] == "The Open Ends property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Open Ends property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.INTERDIGITAL assert distributed_design.topology.open_ends is False @@ -473,7 +636,12 @@ def test_open_ends(self, distributed_design): def test_combline_half_length_frequency_2ghz(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.combline_half_length_frequency = "4G" - assert info.value.args[0] == "The 1/2 Length Frequency property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The 1/2 Length Frequency property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.COMBLINE assert distributed_design.topology.combline_half_length_frequency == "4G" @@ -486,7 +654,12 @@ def test_combline_half_length_frequency_2ghz(self, distributed_design): def test_coupled_segments_quarter_length_frequency_2ghz(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.coupled_segments_quarter_length_frequency = "4G" - assert info.value.args[0] == "The 1/4 Length Frequency property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The 1/4 Length Frequency property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.HIGH_PASS distributed_design.topology.topology_type = TopologyType.COUPLED_SEGMENTS assert distributed_design.topology.coupled_segments_quarter_length_frequency == "4G" @@ -513,7 +686,12 @@ def test_quick_optimize(self, distributed_design): def test_resonator_length_extension(self, distributed_design): with pytest.raises(RuntimeError) as info: distributed_design.topology.resonator_length_extension = True - assert info.value.args[0] == "The Enable Extension property is not supported for the selected topology" + assert ( + info.value.args[0] + == "The Enable Extension property is not applicable for the " + + convert_string(distributed_design.topology.topology_type.name) + + " topology" + ) distributed_design.attributes.filter_class = FilterClass.BAND_PASS distributed_design.topology.topology_type = TopologyType.INTERDIGITAL assert distributed_design.topology.resonator_length_extension is False