Wishbone bus connection

[kabrodzki]

I created the branch wishbone_connection and commited there how I understand the buses should be connected.
Also, I'm not sure how the control_bus should be implemented for easy access and debugging - I tried to create my own SoC using this wrapper, but I get error from the Vivado's placer

ERROR: [Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.

Vivado is also complaining that the designs WishboneCSR and DMATop have unconnected ports.
Should I connect them differently? How?
AFAIK, the *stall signals aren't connected to anything when using the WishboneClassicReader/Writer in the original fastvdma, so I connected them to the constant 0.

[kabrodzki]

@kgugala @rw1nkler Any ideas?

[rw1nkler]

You are initializing the wrong class. It should be SoCCore.__init__()
https://gist.github.com/kabrodzki/d1e7bd3d963a67e25345a7fd99288547#file-test-py-L11

You can also provide vivado.log it should be generated in the build directory

[kabrodzki]

@rw1nkler So this appears to work, thanks. But still I am not sure how to implement the access to the internal CSR of the FastVDMA.

[piotr-binkowski]

I think you should be able to access the CSRs using something like this but with slave=self.fastvdma.control and after adding that it should show up in LiteX memory map and you should be able to access it from the BIOS using mw/mr