diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index f7a9d7eff7..f2611040ee 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -9,7 +9,7 @@ jobs:
       fail-fast: false
       matrix:
         arch: [x86_64, riscv64, aarch64]
-        rust-toolchain: [nightly, nightly-2024-12-12]
+        rust-toolchain: [nightly, nightly-2024-12-25]
     env:
       RUSTUP_TOOLCHAIN: ${{ matrix.rust-toolchain }}
     steps:
@@ -40,7 +40,7 @@ jobs:
       matrix:
         os: [ubuntu-latest]
         arch: [x86_64, riscv64, aarch64]
-        rust-toolchain: [nightly, nightly-2024-12-12]
+        rust-toolchain: [nightly, nightly-2024-12-25]
     env:
       RUSTUP_TOOLCHAIN: ${{ matrix.rust-toolchain }}
     steps:
@@ -51,6 +51,7 @@ jobs:
         components: rust-src, llvm-tools
         targets: x86_64-unknown-none, riscv64gc-unknown-none-elf, aarch64-unknown-none, aarch64-unknown-none-softfloat
     - uses: Swatinem/rust-cache@v2
+    - run: cargo install cargo-binutils
     - name: Build helloworld
       continue-on-error: ${{ matrix.rust-toolchain == 'nightly' }}
       run: make ARCH=${{ matrix.arch }} A=examples/helloworld
@@ -83,7 +84,7 @@ jobs:
       fail-fast: false
       matrix:
         os: [ubuntu-latest]
-        rust-toolchain: [nightly, nightly-2024-12-12]
+        rust-toolchain: [nightly, nightly-2024-12-25]
     steps:
     - uses: actions/checkout@v4
     - uses: dtolnay/rust-toolchain@stable
@@ -92,6 +93,7 @@ jobs:
         components: rust-src, llvm-tools
         targets: x86_64-unknown-none, riscv64gc-unknown-none-elf, aarch64-unknown-none, aarch64-unknown-none-softfloat
     - uses: Swatinem/rust-cache@v2
+    - run: cargo install cargo-binutils
     - name: Build helloworld for x86_64-pc-oslab
       continue-on-error: ${{ matrix.rust-toolchain == 'nightly' }}
       run: make PLATFORM=x86_64-pc-oslab A=examples/helloworld
diff --git a/.github/workflows/docs.yml b/.github/workflows/docs.yml
index 3c64057b26..cec52c8b9d 100644
--- a/.github/workflows/docs.yml
+++ b/.github/workflows/docs.yml
@@ -3,7 +3,7 @@ name: Build & Deploy docs
 on: [push, pull_request]
 
 env:
-  rust-toolchain: nightly-2024-12-12
+  rust-toolchain: nightly-2024-12-25
 
 jobs:
   doc:
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
index 934ba714df..b285db2622 100644
--- a/.github/workflows/test.yml
+++ b/.github/workflows/test.yml
@@ -4,7 +4,7 @@ on: [push, pull_request]
 
 env:
   qemu-version: 8.2.0
-  rust-toolchain: nightly-2024-12-12
+  rust-toolchain: nightly-2024-12-25
   arceos-apps: '57c8074'
 
 jobs:
@@ -33,6 +33,7 @@ jobs:
         toolchain: ${{ env.rust-toolchain }}
         components: rust-src
     - uses: Swatinem/rust-cache@v2
+    - run: cargo install cargo-binutils
     - uses: ./.github/workflows/actions/setup-qemu
       with:
         qemu-version: ${{ env.qemu-version }}
diff --git a/modules/axhal/src/arch/riscv/context.rs b/modules/axhal/src/arch/riscv/context.rs
index f49fec7fd2..df612a7fc7 100644
--- a/modules/axhal/src/arch/riscv/context.rs
+++ b/modules/axhal/src/arch/riscv/context.rs
@@ -1,8 +1,6 @@
 use core::arch::naked_asm;
 use memory_addr::VirtAddr;
 
-include_asm_marcos!();
-
 /// General registers of RISC-V.
 #[allow(missing_docs)]
 #[repr(C)]
@@ -123,6 +121,7 @@ impl TaskContext {
 #[naked]
 unsafe extern "C" fn context_switch(_current_task: &mut TaskContext, _next_task: &TaskContext) {
     naked_asm!(
+        include_asm_marcos!(),
         "
         // save old context (callee-saved registers)
         STR     ra, a0, 0
diff --git a/modules/axhal/src/arch/riscv/macros.rs b/modules/axhal/src/arch/riscv/macros.rs
index c36c4da80f..a793036774 100644
--- a/modules/axhal/src/arch/riscv/macros.rs
+++ b/modules/axhal/src/arch/riscv/macros.rs
@@ -1,8 +1,7 @@
+#[cfg(target_arch = "riscv32")]
 macro_rules! include_asm_marcos {
     () => {
-        #[cfg(target_arch = "riscv32")]
-        core::arch::global_asm!(
-            r"
+        r"
         .ifndef XLENB
         .equ XLENB, 4
 
@@ -14,11 +13,13 @@ macro_rules! include_asm_marcos {
         .endm
 
         .endif"
-        );
+    };
+}
 
-        #[cfg(target_arch = "riscv64")]
-        core::arch::global_asm!(
-            r"
+#[cfg(target_arch = "riscv64")]
+macro_rules! include_asm_marcos {
+    () => {
+        r"
         .ifndef XLENB
         .equ XLENB, 8
 
@@ -29,53 +30,6 @@ macro_rules! include_asm_marcos {
             sd \rs2, \off*XLENB(\rs1)
         .endm
 
-        .endif",
-        );
-
-        core::arch::global_asm!(
-            r"
-        .ifndef .LPUSH_POP_GENERAL_REGS
-        .equ .LPUSH_POP_GENERAL_REGS, 0
-
-        .macro PUSH_POP_GENERAL_REGS, op
-            \op ra, sp, 0
-            \op t0, sp, 4
-            \op t1, sp, 5
-            \op t2, sp, 6
-            \op s0, sp, 7
-            \op s1, sp, 8
-            \op a0, sp, 9
-            \op a1, sp, 10
-            \op a2, sp, 11
-            \op a3, sp, 12
-            \op a4, sp, 13
-            \op a5, sp, 14
-            \op a6, sp, 15
-            \op a7, sp, 16
-            \op s2, sp, 17
-            \op s3, sp, 18
-            \op s4, sp, 19
-            \op s5, sp, 20
-            \op s6, sp, 21
-            \op s7, sp, 22
-            \op s8, sp, 23
-            \op s9, sp, 24
-            \op s10, sp, 25
-            \op s11, sp, 26
-            \op t3, sp, 27
-            \op t4, sp, 28
-            \op t5, sp, 29
-            \op t6, sp, 30
-        .endm
-
-        .macro PUSH_GENERAL_REGS
-            PUSH_POP_GENERAL_REGS STR
-        .endm
-        .macro POP_GENERAL_REGS
-            PUSH_POP_GENERAL_REGS LDR
-        .endm
-
         .endif"
-        );
     };
 }
diff --git a/modules/axhal/src/arch/riscv/trap.S b/modules/axhal/src/arch/riscv/trap.S
index 4e4e3d748e..9de738fe3a 100644
--- a/modules/axhal/src/arch/riscv/trap.S
+++ b/modules/axhal/src/arch/riscv/trap.S
@@ -1,3 +1,42 @@
+.macro PUSH_POP_GENERAL_REGS, op
+    \op ra, sp, 0
+    \op t0, sp, 4
+    \op t1, sp, 5
+    \op t2, sp, 6
+    \op s0, sp, 7
+    \op s1, sp, 8
+    \op a0, sp, 9
+    \op a1, sp, 10
+    \op a2, sp, 11
+    \op a3, sp, 12
+    \op a4, sp, 13
+    \op a5, sp, 14
+    \op a6, sp, 15
+    \op a7, sp, 16
+    \op s2, sp, 17
+    \op s3, sp, 18
+    \op s4, sp, 19
+    \op s5, sp, 20
+    \op s6, sp, 21
+    \op s7, sp, 22
+    \op s8, sp, 23
+    \op s9, sp, 24
+    \op s10, sp, 25
+    \op s11, sp, 26
+    \op t3, sp, 27
+    \op t4, sp, 28
+    \op t5, sp, 29
+    \op t6, sp, 30
+.endm
+
+.macro PUSH_GENERAL_REGS
+    PUSH_POP_GENERAL_REGS STR
+.endm
+
+.macro POP_GENERAL_REGS
+    PUSH_POP_GENERAL_REGS LDR
+.endm
+
 .macro SAVE_REGS, from_user
     addi    sp, sp, -{trapframe_size}
     PUSH_GENERAL_REGS
diff --git a/modules/axhal/src/arch/riscv/trap.rs b/modules/axhal/src/arch/riscv/trap.rs
index 3e3767d9ac..40c5bd36e1 100644
--- a/modules/axhal/src/arch/riscv/trap.rs
+++ b/modules/axhal/src/arch/riscv/trap.rs
@@ -4,9 +4,8 @@ use riscv::register::stval;
 
 use super::TrapFrame;
 
-include_asm_marcos!();
-
 core::arch::global_asm!(
+    include_asm_marcos!(),
     include_str!("trap.S"),
     trapframe_size = const core::mem::size_of::<TrapFrame>(),
 );
diff --git a/rust-toolchain.toml b/rust-toolchain.toml
index 7d558f7beb..7c587ea0f3 100644
--- a/rust-toolchain.toml
+++ b/rust-toolchain.toml
@@ -1,5 +1,5 @@
 [toolchain]
 profile = "minimal"
-channel = "nightly-2024-12-12"
+channel = "nightly-2024-12-25"
 components = ["rust-src", "llvm-tools", "rustfmt", "clippy"]
 targets = ["x86_64-unknown-none", "riscv64gc-unknown-none-elf", "aarch64-unknown-none", "aarch64-unknown-none-softfloat"]