From b2c67b71c24ade1effc424b37d60bf378e530316 Mon Sep 17 00:00:00 2001
From: Godones <1925466036@qq.com>
Date: Sat, 23 Dec 2023 15:56:03 +0800
Subject: [PATCH] doc: add documentation

---
 crates/page_table/src/arch/loongarch64.rs       | 1 +
 crates/page_table_entry/src/arch/loongarch64.rs | 5 ++++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/crates/page_table/src/arch/loongarch64.rs b/crates/page_table/src/arch/loongarch64.rs
index 91a7f588de..a1f6e01d89 100644
--- a/crates/page_table/src/arch/loongarch64.rs
+++ b/crates/page_table/src/arch/loongarch64.rs
@@ -13,4 +13,5 @@ impl const PagingMetaData for LA64MetaData {
     const VA_MAX_BITS: usize = 48;
 }
 
+/// Page table for LoongArch64 systems.
 pub type LA64PageTable<I> = PageTable64<LA64MetaData, LA64PTE, I>;
diff --git a/crates/page_table_entry/src/arch/loongarch64.rs b/crates/page_table_entry/src/arch/loongarch64.rs
index 3983c6257b..e13de3120b 100644
--- a/crates/page_table_entry/src/arch/loongarch64.rs
+++ b/crates/page_table_entry/src/arch/loongarch64.rs
@@ -1,7 +1,6 @@
 //! loongarch64 page table entries.
 
 use crate::{GenericPTE, MappingFlags};
-use aarch64_cpu::registers::SPSR_EL1::M;
 use core::fmt;
 use memory_addr::PhysAddr;
 
@@ -16,10 +15,13 @@ bitflags::bitflags! {
         const D = 1 << 1;
         /// Privilege Level with 2 bits.
         const PLVL = 1 << 2;
+        /// Privilege Level with 2 bits.
         const PLVH = 1 << 3;
         /// Memory Access Type controls the type of access, such as whether it
         /// can be cached by Cache, etc.
         const MATL = 1 << 4;
+        /// Memory Access Type controls the type of access, such as whether it
+        /// can be cached by Cache, etc.
         const MATH = 1 << 5;
         /// Designates a global mapping OR Whether the page is huge page.
         const GH = 1 << 6;
@@ -96,6 +98,7 @@ impl From<MappingFlags> for PTEFlags {
     }
 }
 
+/// page table entry for LoongArch64 systems.
 #[derive(Clone, Copy)]
 #[repr(transparent)]
 pub struct LA64PTE(u64);