From a1fcfdd524c6710f022ff4c0fa63a4d2a3146611 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Fri, 10 Jan 2025 17:57:19 -0500 Subject: [PATCH] riscv atomic.h: Use __ATOMIC_RELAXED for the cmpset_rel fail memory order __ATOMIC_RELEASE is not permitted as a fail memory order and LLVM 18 errors on this. --- sys/riscv/include/atomic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/sys/riscv/include/atomic.h b/sys/riscv/include/atomic.h index 3aab8c19272c..2d2c7db08da1 100644 --- a/sys/riscv/include/atomic.h +++ b/sys/riscv/include/atomic.h @@ -63,7 +63,7 @@ atomic_##NAME##_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\ atomic_##NAME##_##WIDTH(p, v); \ } -#define ATOMIC_CMPSET_ORDER(WIDTH, SUFFIX, ORDER) \ +#define ATOMIC_CMPSET_ORDER(WIDTH, SUFFIX, SUCCESS, FAIL) \ static __inline int \ atomic_cmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ uint##WIDTH##_t cmpval, uint##WIDTH##_t newval) \ @@ -71,10 +71,10 @@ atomic_cmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ \ /* Return 1 on success, 0 on failure */ \ return (__atomic_compare_exchange_n( \ - p, &cmpval, newval, 0, ORDER, ORDER)); \ + p, &cmpval, newval, 0, SUCCESS, FAIL)); \ } -#define ATOMIC_FCMPSET_ORDER(WIDTH, SUFFIX, ORDER) \ +#define ATOMIC_FCMPSET_ORDER(WIDTH, SUFFIX, SUCCESS, FAIL) \ static __inline int \ atomic_fcmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ uint##WIDTH##_t* cmpval, uint##WIDTH##_t newval) \ @@ -82,24 +82,24 @@ atomic_fcmpset##SUFFIX##WIDTH(__volatile uint##WIDTH##_t *p, \ \ /* fcmpset updates cmpval on failure and uses weak cmpxchg */ \ return (__atomic_compare_exchange_n( \ - p, cmpval, newval, 1, ORDER, ORDER)); \ + p, cmpval, newval, 1, SUCCESS, FAIL)); \ } #define ATOMIC_CMPSET_ACQ_REL(WIDTH) \ - ATOMIC_CMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE) \ - ATOMIC_CMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE) + ATOMIC_CMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) \ + ATOMIC_CMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE, __ATOMIC_RELAXED) #define ATOMIC_CMPSET(WIDTH) \ - ATOMIC_CMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED) \ + ATOMIC_CMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED, __ATOMIC_RELAXED) \ ATOMIC_CMPSET_ACQ_REL(WIDTH) #define ATOMIC_FCMPSET_ACQ_REL(WIDTH) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE) + ATOMIC_FCMPSET_ORDER(WIDTH, _acq_, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE) \ + ATOMIC_FCMPSET_ORDER(WIDTH, _rel_, __ATOMIC_RELEASE, __ATOMIC_RELAXED) #define ATOMIC_FCMPSET(WIDTH) \ - ATOMIC_FCMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED) \ + ATOMIC_FCMPSET_ORDER(WIDTH, _, __ATOMIC_RELAXED, __ATOMIC_RELAXED) \ ATOMIC_FCMPSET_ACQ_REL(WIDTH) \ #ifdef __CHERI_PURE_CAPABILITY__