diff --git a/ch32-metapac-gen/Cargo.toml b/ch32-metapac-gen/Cargo.toml index 0cb1a96..463b6d9 100644 --- a/ch32-metapac-gen/Cargo.toml +++ b/ch32-metapac-gen/Cargo.toml @@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0" [dependencies] regex = "1.7.1" -chiptool = { git = "https://github.com/ch32-rs/chiptool", rev = "1c198ae678ebd426751513f0deab6fbd6f8b8211" } +chiptool = { git = "https://github.com/ch32-rs/chiptool", rev = "305bd6ee3e57009ae93be2c81d6e94b9896a03b1" } serde = { version = "1.0.157", features = ["derive"] } serde_json = "1.0.94" proc-macro2 = "1.0.52" diff --git a/ch32-metapac-gen/src/lib.rs b/ch32-metapac-gen/src/lib.rs index 73e2f25..e3cea6e 100644 --- a/ch32-metapac-gen/src/lib.rs +++ b/ch32-metapac-gen/src/lib.rs @@ -62,7 +62,7 @@ impl Gen { .peripherals .iter() .find(|p| p.name == "GPIOA") - .unwrap() + .expect("GPIOA must exist") .address as u32; let gpio_stride = 0x400; @@ -360,7 +360,10 @@ impl Gen { .join("registers") .join(&format!("{}_{}.json", module, version)); - let mut ir: ir::IR = serde_json::from_reader(File::open(regs_path).unwrap()).unwrap(); + let mut ir: ir::IR = serde_json::from_reader( + File::open(®s_path).expect(&format!("open {}", regs_path.display())), + ) + .unwrap(); transform::expand_extends::ExpandExtends {} .run(&mut ir) diff --git a/d b/d index 35cc892..8ad5966 100755 --- a/d +++ b/d @@ -48,7 +48,7 @@ case "$CMD" in gen) rm -rf build/data echo "TODO: More chips to be added" - cargo run -p ch32-data-gen && cargo run -p ch32-metapac-gen -- "CH32X03*" "CH32V*" CH641 CH643 + cargo run -p ch32-data-gen && cargo run -p ch32-metapac-gen -- "CH32X03*" "CH32V*" "CH32L*" CH641 CH643 ;; ci) echo TODO $CMD diff --git a/data/chips/CH32L103C8T6.yaml b/data/chips/CH32L103C8T6.yaml index a8408f5..1a6fe5c 100644 --- a/data/chips/CH32L103C8T6.yaml +++ b/data/chips/CH32L103C8T6.yaml @@ -6,6 +6,7 @@ device_id: 271648512 keywords: - USBPD - Low Power + - CAN FD packages: - name: CH32L103C8T6 package: LQFP48 @@ -25,13 +26,15 @@ memory: docs: - type: homepage title: Homepage - name: "" + name: "CH32L103" url: https://www.wch.cn/products/CH32L103.html cores: - name: qingke-v4c peripherals: [] include_peripherals: - "../family/CH32L1.yaml" + - "../peripherals/L1x_SPI2.yaml" + - "../peripherals/L1x_I2C2.yaml" include_dma_channels: DMA1: "../dma/CH32V_V4C_L1.yaml" include_interrupts: "../interrupts/CH32L1.yaml" diff --git a/data/chips/CH32L103F7P6.yaml b/data/chips/CH32L103F7P6.yaml index 66cf644..12fe997 100644 --- a/data/chips/CH32L103F7P6.yaml +++ b/data/chips/CH32L103F7P6.yaml @@ -6,6 +6,7 @@ device_id: 272041728 keywords: - USBPD - Low Power + - CAN FD packages: - name: CH32L103F7P6 package: TSSOP20 @@ -25,13 +26,15 @@ memory: docs: - type: homepage title: Homepage - name: "" + name: "CH32L103" url: https://www.wch.cn/products/CH32L103.html cores: - name: qingke-v4c peripherals: [] include_peripherals: - "../family/CH32L1.yaml" + - "../peripherals/L1x_SPI2.yaml" + - "../peripherals/L1x_I2C2.yaml" include_dma_channels: DMA1: "../dma/CH32V_V4C_L1.yaml" include_interrupts: "../interrupts/CH32L1.yaml" diff --git a/data/chips/CH32L103F8P6.yaml b/data/chips/CH32L103F8P6.yaml index b0e4d62..52310b8 100644 --- a/data/chips/CH32L103F8P6.yaml +++ b/data/chips/CH32L103F8P6.yaml @@ -6,6 +6,7 @@ device_id: 272238336 keywords: - USBPD - Low Power + - CAN FD packages: - name: CH32L103F8P6 package: TSSOP20 @@ -25,7 +26,7 @@ memory: docs: - type: homepage title: Homepage - name: "" + name: "CH32L103" url: https://www.wch.cn/products/CH32L103.html cores: - name: qingke-v4c diff --git a/data/chips/CH32L103F8U6.yaml b/data/chips/CH32L103F8U6.yaml index 7ec8142..0692d40 100644 --- a/data/chips/CH32L103F8U6.yaml +++ b/data/chips/CH32L103F8U6.yaml @@ -6,6 +6,7 @@ device_id: 272434944 keywords: - USBPD - Low Power + - CAN FD packages: - name: CH32L103F8U6 package: QFN20 @@ -25,13 +26,15 @@ memory: docs: - type: homepage title: Homepage - name: "" + name: "CH32L103" url: https://www.wch.cn/products/CH32L103.html cores: - name: qingke-v4c peripherals: [] include_peripherals: - "../family/CH32L1.yaml" + - "../peripherals/L1x_SPI2.yaml" + - "../peripherals/L1x_I2C2.yaml" include_dma_channels: DMA1: "../dma/CH32V_V4C_L1.yaml" include_interrupts: "../interrupts/CH32L1.yaml" diff --git a/data/chips/CH32L103G8R6.yaml b/data/chips/CH32L103G8R6.yaml index 94ef097..959c430 100644 --- a/data/chips/CH32L103G8R6.yaml +++ b/data/chips/CH32L103G8R6.yaml @@ -32,6 +32,8 @@ cores: peripherals: [] include_peripherals: - "../family/CH32L1.yaml" + - "../peripherals/L1x_SPI2.yaml" + - "../peripherals/L1x_I2C2.yaml" include_dma_channels: DMA1: "../dma/CH32V_V4C_L1.yaml" include_interrupts: "../interrupts/CH32L1.yaml" diff --git a/data/family/CH32L1.yaml b/data/family/CH32L1.yaml index 4eeccec..18e28b7 100644 --- a/data/family/CH32L1.yaml +++ b/data/family/CH32L1.yaml @@ -1,5 +1,9 @@ -# TODO - +- name: PFIC + address: 0xE000E000 + registers: + kind: pfic + version: rv3 + block: PFIC - name: SYSTICK address: 0xE000F000 registers: @@ -10,6 +14,22 @@ # interrupts: # - signal: GLOBAL # interrupt: SYSTICK +- name: FLASH + address: 0x40022000 + registers: + kind: flash + version: l1 + block: FLASH + +- name: RCC + address: 0x40021000 + registers: + kind: rcc + version: l1 + block: RCC + pins: + - pin: PA8 + signal: MCO - name: DMA1 address: 1073872896 # 0x40020000 @@ -22,7 +42,7 @@ kernel_clock: HCLK enable: register: AHBPCENR - field: DMA1EN + field: DMAEN interrupts: - signal: CH1 interrupt: DMA1_Channel1 @@ -41,6 +61,651 @@ - signal: CH8 interrupt: DMA1_Channel8 +- name: EXTI + address: 0x40010400 + registers: + kind: exti + version: common + block: EXTI + interrupts: + - signal: EXTI0 + interrupt: EXTI0 + - signal: EXTI1 + interrupt: EXTI1 + - signal: EXTI2 + interrupt: EXTI2 + - signal: EXTI3 + interrupt: EXTI3 + - signal: EXTI4 + interrupt: EXTI4 + - signal: EXTI5 + interrupt: EXTI9_5 + - signal: EXTI10 + interrupt: EXTI15_10 + +- name: GPIOA + address: 0x40010800 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPAEN + reset: + register: APB2PRSTR + field: IOPARST +- name: GPIOB + address: 0x40010C00 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPBEN + reset: + register: APB2PRSTR + field: IOPBRST +- name: GPIOC + address: 0x40011000 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPCEN + reset: + register: APB2PRSTR + field: IOPCRST +- name: GPIOD + address: 0x40011400 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPDEN + reset: + register: APB2PRSTR + field: IOPDRST + +- name: AFIO + address: 0x40010000 + registers: + kind: afio + version: l1 + block: AFIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: AFIOEN + reset: + register: APB2PRSTR + field: AFIORST + +- name: EXTEND + address: 0x40023800 + registers: + kind: extend + version: l1 + block: EXTEND + +# 4 USART +- name: USART1 + address: 0x40013800 + registers: + kind: usart + version: common + block: USART + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: USART1EN + reset: + register: APB2PRSTR + field: USART1RST + # complex remap, use patch + # remap: + # register: PCFR1 + # field: USART1_RM + interrupts: + - signal: GLOBAL + interrupt: USART1 + pins: + # 000:默认映射(TX/PA9，RX/PA10，CK/PA8， CTS/PA11，RTS/PA12) + - { pin: "PA9", signal: "TX", remap: 0 } + - { pin: "PA10", signal: "RX", remap: 0 } + - { pin: "PA8", signal: "CK", remap: 0 } + - { pin: "PA11", signal: "CTS", remap: 0 } + - { pin: "PA12", signal: "RTS", remap: 0 } + # 001:部分映射(TX/PB6，RX/PB7，CK/PA8， CTS/PA11，RTS/PA12) + - { pin: "PB6", signal: "TX", remap: 1 } + - { pin: "PB7", signal: "RX", remap: 1 } + - { pin: "PA8", signal: "CK", remap: 1 } + - { pin: "PA11", signal: "CTS", remap: 1 } + - { pin: "PA12", signal: "RTS", remap: 1 } + # 010:完全映射(TX/PA4，RX/PA5，CK/PA3， CTS/PA2，RTS/PA13) + - { pin: "PA4", signal: "TX", remap: 2 } + - { pin: "PA5", signal: "RX", remap: 2 } + - { pin: "PA3", signal: "CK", remap: 2 } + - { pin: "PA2", signal: "CTS", remap: 2 } + - { pin: "PA13", signal: "RTS", remap: 2 } + # 011:完全映射(TX/PA5，RX/PA4，CK/PA6， CTS/PB7，RTS/PB8) + - { pin: "PA5", signal: "TX", remap: 3 } + - { pin: "PA4", signal: "RX", remap: 3 } + - { pin: "PA6", signal: "CK", remap: 3 } + - { pin: "PB7", signal: "CTS", remap: 3 } + - { pin: "PB8", signal: "RTS", remap: 3 } + # 100:完全映射(TX/PB11，RX/PB9，CK/PA6， CTS/PA14，RTS/PA13) + - { pin: "PB11", signal: "TX", remap: 4 } + - { pin: "PB9", signal: "RX", remap: 4 } + - { pin: "PA6", signal: "CK", remap: 4 } + - { pin: "PA14", signal: "CTS", remap: 4 } + - { pin: "PA13", signal: "RTS", remap: 4 } + # 101:完全映射(TX/PB12，RX/PA12，CK/PB6， CTS/PB7，RTS/PB8) + - { pin: "PB12", signal: "TX", remap: 5 } + - { pin: "PA12", signal: "RX", remap: 5 } + - { pin: "PB6", signal: "CK", remap: 5 } + - { pin: "PB7", signal: "CTS", remap: 5 } + - { pin: "PB8", signal: "RTS", remap: 5 } +- name: USART2 + address: 0x40004400 + registers: + kind: usart + version: common + block: USART + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: USART2EN + reset: + register: APB1PRSTR + field: USART2RST + # complex remap, use patch + # remap: + # register: PCFR1 + # field: USART2_RM + interrupts: + - signal: GLOBAL + interrupt: USART2 + pins: + # 00:默认映射(TX/PA2，RX/PA3，CK/PA4， CTS/PA0，RTS/PA1) + - { pin: "PA2", signal: "TX", remap: 0 } + - { pin: "PA3", signal: "RX", remap: 0 } + - { pin: "PA4", signal: "CK", remap: 0 } + - { pin: "PA0", signal: "CTS", remap: 0 } + - { pin: "PA1", signal: "RTS", remap: 0 } + # 01:保留 + # 10:部分映射(TX/PA11，RX/PA12，CK/PA4， CTS/PA0，RTS/PA1) + - { pin: "PA11", signal: "TX", remap: 2 } + - { pin: "PA12", signal: "RX", remap: 2 } + - { pin: "PA4", signal: "CK", remap: 2 } + - { pin: "PA0", signal: "CTS", remap: 2 } + - { pin: "PA1", signal: "RTS", remap: 2 } + # 11:部分映射(TX/PA12，RX/PA11，CK/PA4， CTS/PA0，RTS/PA1) + - { pin: "PA12", signal: "TX", remap: 3 } + - { pin: "PA11", signal: "RX", remap: 3 } + - { pin: "PA4", signal: "CK", remap: 3 } + - { pin: "PA0", signal: "CTS", remap: 3 } + - { pin: "PA1", signal: "RTS", remap: 3 } +- name: USART3 + address: 0x40004800 + registers: + kind: usart + version: common + block: USART + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: USART3EN + reset: + register: APB1PRSTR + field: USART3RST + remap: + register: PCFR1 + field: USART3_RM + interrupts: + - signal: GLOBAL + interrupt: USART3 + pins: + # 00:默认映射(TX/PB10，RX/PB11，CK/PB12， CTS/PB13，RTS/PB14) + - { pin: "PB10", signal: "TX", remap: 0 } + - { pin: "PB11", signal: "RX", remap: 0 } + - { pin: "PB12", signal: "CK", remap: 0 } + - { pin: "PB13", signal: "CTS", remap: 0 } + - { pin: "PB14", signal: "RTS", remap: 0 } + # 10:部分重映射(TX/PD1，RX/PD0，CK/PB12， CTS/PB13，RTS/PB14) + - { pin: "PD1", signal: "TX", remap: 2 } + - { pin: "PD0", signal: "RX", remap: 2 } + - { pin: "PB12", signal: "CK", remap: 2 } + - { pin: "PB13", signal: "CTS", remap: 2 } + - { pin: "PB14", signal: "RTS", remap: 2 } + # 11:部分重映射(TX/PD0，RX/PD1，CK/PB12， CTS/PB13，RTS/PB14) + - { pin: "PD0", signal: "TX", remap: 3 } + - { pin: "PD1", signal: "RX", remap: 3 } + - { pin: "PB12", signal: "CK", remap: 3 } + - { pin: "PB13", signal: "CTS", remap: 3 } + - { pin: "PB14", signal: "RTS", remap: 3 } +- name: USART4 + address: 0x40004C00 + registers: + kind: usart + version: common + block: USART + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: USART4EN + reset: + register: APB1PRSTR + field: USART4RST + remap: + register: PCFR2 + field: USART4_RM + interrupts: + - signal: GLOBAL + interrupt: USART4 + pins: + # 0:默认映射(TX/PB0，RX/PB1，CK/PB2，CTS/PB3， RTS/PB4) + - { pin: "PB0", signal: "TX", remap: 0 } + - { pin: "PB1", signal: "RX", remap: 0 } + - { pin: "PB2", signal: "CK", remap: 0 } + - { pin: "PB3", signal: "CTS", remap: 0 } + - { pin: "PB4", signal: "RTS", remap: 0 } + # 1:完全映射(TX/PA5，RX/PB5，CK/PA6，CTS/PA7， RTS/PA15) + - { pin: "PA5", signal: "TX", remap: 1 } + - { pin: "PB5", signal: "RX", remap: 1 } + - { pin: "PA6", signal: "CK", remap: 1 } + - { pin: "PA7", signal: "CTS", remap: 1 } + - { pin: "PA15", signal: "RTS", remap: 1 } + +# 1 ADTM, 2 GPTM, 1 GPTM32, 1 LPTIM +- name: TIM1 + address: 0x40012C00 + registers: + kind: timer + version: v3 + block: ADTM + rcc: + bus_clock: PCLK2_TIM + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: TIM1EN + reset: + register: APB2PRSTR + field: TIM1RST + # use patch for remap + #remap: + # register: PCFR1 + # field: TIM1_RM + interrupts: + - signal: BRK + interrupt: TIM1_BRK + - signal: UP + interrupt: TIM1_UP + - signal: TRG + interrupt: TIM1_TRG_COM + - signal: COM + interrupt: TIM1_TRG_COM + - signal: CC + interrupt: TIM1_CC + pins: + # 000:默认映射(ETR/PA12，CH1/PA8，CH2/PA9， CH3/PA10，CH4/PA11，BKIN/PB12，CH1N/PB13，CH2N/PB14，CH3N/PB15) + - { pin: "PA12", signal: "ETR", remap: 0 } + - { pin: "PA8", signal: "CH1", remap: 0 } + - { pin: "PA9", signal: "CH2", remap: 0 } + - { pin: "PA10", signal: "CH3", remap: 0 } + - { pin: "PA11", signal: "CH4", remap: 0 } + - { pin: "PB12", signal: "BKIN", remap: 0 } + - { pin: "PB13", signal: "CH1N", remap: 0 } + - { pin: "PB14", signal: "CH2N", remap: 0 } + - { pin: "PB15", signal: "CH3N", remap: 0 } + # 001:部分映射(ETR/PA12，CH1/PA8，CH2/PA9， CH3/PA10，CH4/PA11，BKIN/PA6，CH1N/PA7， CH2N/PB0，CH3N/PB1) + - { pin: "PA12", signal: "ETR", remap: 1 } + - { pin: "PA8", signal: "CH1", remap: 1 } + - { pin: "PA9", signal: "CH2", remap: 1 } + - { pin: "PA10", signal: "CH3", remap: 1 } + - { pin: "PA11", signal: "CH4", remap: 1 } + - { pin: "PA6", signal: "BKIN", remap: 1 } + - { pin: "PA7", signal: "CH1N", remap: 1 } + - { pin: "PB0", signal: "CH2N", remap: 1 } + - { pin: "PB1", signal: "CH3N", remap: 1 } + # 010:完全映射(ETR/PB6，CH1/PA1，CH2/PA7， CH3/PA14，CH4/PB1，BKIN/PA13，CH1N/PB11， CH2N/PB0，CH3N/PB9) + - { pin: "PB6", signal: "ETR", remap: 2 } + - { pin: "PA1", signal: "CH1", remap: 2 } + - { pin: "PA7", signal: "CH2", remap: 2 } + - { pin: "PA14", signal: "CH3", remap: 2 } + - { pin: "PB1", signal: "CH4", remap: 2 } + - { pin: "PA13", signal: "BKIN", remap: 2 } + - { pin: "PB11", signal: "CH1N", remap: 2 } + - { pin: "PB0", signal: "CH2N", remap: 2 } + - { pin: "PB9", signal: "CH3N", remap: 2 } + # 011:完全映射(ETR/PA3，CH1/PA1，CH2/PA7， CH3/PA14，CH4/PB1，BKIN/PA13，CH1N/PB11， CH2N/PB0，CH3N/PB9) + - { pin: "PA3", signal: "ETR", remap: 3 } + - { pin: "PA1", signal: "CH1", remap: 3 } + - { pin: "PA7", signal: "CH2", remap: 3 } + - { pin: "PA14", signal: "CH3", remap: 3 } + - { pin: "PB1", signal: "CH4", remap: 3 } + - { pin: "PA13", signal: "BKIN", remap: 3 } + - { pin: "PB11", signal: "CH1N", remap: 3 } + - { pin: "PB0", signal: "CH2N", remap: 3 } + - { pin: "PB9", signal: "CH3N", remap: 3 } + # 100:完全映射(ETR/PB6，CH1/PB7，CH2/PB8， CH3/PB12，CH4/PA2，BKIN/PA12，CH1N/PA14， CH2N/PB1，CH3N/PB9) + - { pin: "PB6", signal: "ETR", remap: 4 } + - { pin: "PB7", signal: "CH1", remap: 4 } + - { pin: "PB8", signal: "CH2", remap: 4 } + - { pin: "PB12", signal: "CH3", remap: 4 } + - { pin: "PA2", signal: "CH4", remap: 4 } + - { pin: "PA12", signal: "BKIN", remap: 4 } + - { pin: "PA14", signal: "CH1N", remap: 4 } + - { pin: "PB1", signal: "CH2N", remap: 4 } + - { pin: "PB9", signal: "CH3N", remap: 4 } + # 101:完全映射(ETR/PA13，CH1/PB1，CH2/PB8， CH3/PB6，CH4/PA3，BKIN/PA12，CH1N/PA14， CH2N/PA1，CH3N/PB7) + - { pin: "PA13", signal: "ETR", remap: 5 } + - { pin: "PB1", signal: "CH1", remap: 5 } + - { pin: "PB8", signal: "CH2", remap: 5 } + - { pin: "PB6", signal: "CH3", remap: 5 } + - { pin: "PA3", signal: "CH4", remap: 5 } + - { pin: "PA12", signal: "BKIN", remap: 5 } + - { pin: "PA14", signal: "CH1N", remap: 5 } + - { pin: "PA1", signal: "CH2N", remap: 5 } + - { pin: "PB7", signal: "CH3N", remap: 5 } + # 111:仅控制 LSI 输入，用于 LSI 校准 +- name: TIM2 + address: 0x40000000 + registers: + kind: timer + version: v3 + block: GPTM + rcc: + bus_clock: PCLK1_TIM + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: TIM2EN + reset: + register: APB1PRSTR + field: TIM2RST + #remap: + # register: PCFR1 + # field: TIM2_RM + interrupts: + - signal: UP + interrupt: TIM2 + - signal: TRG + interrupt: TIM2 + - signal: CC + interrupt: TIM2 + pins: + # 000 : 默 认 映 射 (CH1/ETR/PA0 ， CH2/PA1 ， CH3/PA2，CH4/PA3); + - { pin: "PA0", signal: "CH1", remap: 0 } + - { pin: "PA0", signal: "ETR", remap: 0 } + - { pin: "PA1", signal: "CH2", remap: 0 } + - { pin: "PA2", signal: "CH3", remap: 0 } + - { pin: "PA3", signal: "CH4", remap: 0 } + # 001 : 部 分 映 射 (CH1/ETR/PA15 ， CH2/PB3 ， CH3/PA2，CH4/PA3); + - { pin: "PA15", signal: "CH1", remap: 1 } + - { pin: "PA15", signal: "ETR", remap: 1 } + - { pin: "PB3", signal: "CH2", remap: 1 } + - { pin: "PA2", signal: "CH3", remap: 1 } + - { pin: "PA3", signal: "CH4", remap: 1 } + # 010 : 部 分 映 射 (CH1/ETR/PA0 ， CH2/PA1 ， CH3/PB10，CH4/PB11); + - { pin: "PA0", signal: "CH1", remap: 2 } + - { pin: "PA0", signal: "ETR", remap: 2 } + - { pin: "PA1", signal: "CH2", remap: 2 } + - { pin: "PB10", signal: "CH3", remap: 2 } + - { pin: "PB11", signal: "CH4", remap: 2 } + # 011 : 完 全 映 射 (CH1/ETR/PA15 ， CH2/PB3 ， CH3/PB10，CH4/PB11); + - { pin: "PA15", signal: "CH1", remap: 3 } + - { pin: "PA15", signal: "ETR", remap: 3 } + - { pin: "PB3", signal: "CH2", remap: 3 } + - { pin: "PB10", signal: "CH3", remap: 3 } + - { pin: "PB11", signal: "CH4", remap: 3 } + # 100 : 完 全 映 射 (CH1/ETR/PA3 ， CH2/PA2 ， CH3/PB12，CH4/PA6); + - { pin: "PA3", signal: "CH1", remap: 4 } + - { pin: "PA3", signal: "ETR", remap: 4 } + - { pin: "PA2", signal: "CH2", remap: 4 } + - { pin: "PB12", signal: "CH3", remap: 4 } + - { pin: "PA6", signal: "CH4", remap: 4 } + # 101 : 完 全 映 射 (CH1/ETR/PA12 ， CH2/PA2 ， CH3/PB12，CH4/PA6); + - { pin: "PA12", signal: "CH1", remap: 5 } + - { pin: "PA12", signal: "ETR", remap: 5 } + - { pin: "PA2", signal: "CH2", remap: 5 } + - { pin: "PB12", signal: "CH3", remap: 5 } + - { pin: "PA6", signal: "CH4", remap: 5 } + # 111 : 完 全 映 射 (CH1/ETR/PA12 ， CH2/PB8 ， CH3/PA5，CH4/PA4)。 + - { pin: "PA12", signal: "CH1", remap: 7 } + - { pin: "PA12", signal: "ETR", remap: 7 } + - { pin: "PB8", signal: "CH2", remap: 7 } + - { pin: "PA5", signal: "CH3", remap: 7 } + - { pin: "PA4", signal: "CH4", remap: 7 } +- name: TIM3 + address: 0x40000400 + registers: + kind: timer + version: v3 + block: GPTM + rcc: + bus_clock: PCLK1_TIM + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: TIM3EN + reset: + register: APB1PRSTR + field: TIM3RST + remap: + register: PCFR1 + field: TIM3_RM + interrupts: + - signal: UP + interrupt: TIM3 + - signal: TRG + interrupt: TIM3 + - signal: CC + interrupt: TIM3 + pins: + # 0:默认映射(CH1/PA6，CH2/PA7，CH3/PB0， CH4/PB1); + - { pin: "PA6", signal: "CH1", remap: 0 } + - { pin: "PA7", signal: "CH2", remap: 0 } + - { pin: "PB0", signal: "CH3", remap: 0 } + - { pin: "PB1", signal: "CH4", remap: 0 } + # 1:部分映射(CH1/PB4，CH2/PB5，CH3/PB0， CH4/PB1) + - { pin: "PB4", signal: "CH1", remap: 1 } + - { pin: "PB5", signal: "CH2", remap: 1 } + - { pin: "PB0", signal: "CH3", remap: 1 } + - { pin: "PB1", signal: "CH4", remap: 1 } +- name: TIM4 + address: 0x40000800 + registers: + kind: timer + version: v3 + block: GPTM32 + rcc: + bus_clock: PCLK1_TIM + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: TIM4EN + reset: + register: APB1PRSTR + field: TIM4RST + remap: + register: PCFR1 + field: TIM4_RM + interrupts: + - signal: UP + interrupt: TIM4 + - signal: TRG + interrupt: TIM4 + - signal: CC + interrupt: TIM4 + pins: + # 0:默认映射(CH1/PB6，CH2/PB7，CH3/PB8， CH4/PB9); + - { pin: "PB6", signal: "CH1", remap: 0 } + - { pin: "PB7", signal: "CH2", remap: 0 } + - { pin: "PB8", signal: "CH3", remap: 0 } + - { pin: "PB9", signal: "CH4", remap: 0 } + # 1:重映射(CH1/PB10，CH2/PB11，CH3/PPB8， CH4/PB9) + - { pin: "PB10", signal: "CH1", remap: 1 } + - { pin: "PB11", signal: "CH2", remap: 1 } + - { pin: "PB8", signal: "CH3", remap: 1 } + - { pin: "PB9", signal: "CH4", remap: 1 } + +- name: LPTIM1 + address: 0x40007C00 + registers: + kind: lptim + version: l1 + block: LPTIM + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: LPTIMEN + reset: + register: APB1PRSTR + field: LPTIMRST + interrupts: + - signal: WKUP + interrupt: LPTIM_WKUP + +- name: SPI1 + address: 0x40013000 + registers: + kind: spi + version: v0 + block: SPI + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: SPI1EN + reset: + register: APB2PRSTR + field: SPI1RST + # remap via patch + # remap: + # register: PCFR1 + # field: SPI1_RM + interrupts: + - signal: GLOBAL + interrupt: SPI1 + pins: + # 00:默认映射(NSS/PA4，SCK/PA5，MISO/PA6， MOSI/PA7) + # 01:完全映射(NSS/PA15，SCK/PB3，MISO/PB4， MOSI/PB5) + # 10:完全映射(NSS/PA12，SCK/PB6，MISO/PB8， MOSI/PB7) + # 11:完全映射(NSS/PB12，SCK/PB6，MISO/PB8， MOSI/PB7) + +# SPI2 is optional + +- name: I2C1 + address: 0x40005400 + registers: + kind: i2c + version: v3 + block: I2C + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: I2C1EN + reset: + register: APB1PRSTR + field: I2C1RST + #remap: + # register: PCFR1 + # field: I2C1_RM + interrupts: + - { "signal": "ER", "interrupt": "I2C1_ER" } + - { "signal": "EV", "interrupt": "I2C1_EV" } + pins: + # 00:默认映射(SCL/PB6，SDA/PB7) + - { pin: "PB5", signal: "SMBA", remap: 0 } + - { pin: "PB6", signal: "SCL", remap: 0 } + - { pin: "PB7", signal: "SDA", remap: 0 } + # 0:完全映射(SCL/PA13，SDA/PA12) + - { pin: "PB5", signal: "SMBA", remap: 1 } + - { pin: "PA13", signal: "SCL", remap: 1 } + - { pin: "PA12", signal: "SDA", remap: 1 } + # 11:完全映射(SCL/PB9，SDA/PB11) + - { pin: "PB5", signal: "SMBA", remap: 3 } + - { pin: "PB9", signal: "SCL", remap: 3 } + - { pin: "PB11", signal: "SDA", remap: 3 } + +# ADC, 10 external channels, 3 internal channel +# - CH16 = Temperature +# - CH17, V_REFINT +# - CH18, V_DDA/2 +- name: ADC1 + address: 0x40012400 + registers: + kind: adc + version: l1 + block: ADC + rcc: + bus_clock: PCLK2 + kernel_clock: ADC + enable: + register: APB2PCENR + field: ADCEN + reset: + register: APB2PRSTR + field: ADCRST + interrupts: + - signal: GLOBAL + interrupt: ADC + pins: + - pin: PA0 + signal: IN0 + - pin: PA1 + signal: IN1 + - pin: PA2 + signal: IN2 + - pin: PA3 + signal: IN3 + - pin: PA4 + signal: IN4 + - pin: PA5 + signal: IN5 + - pin: PA6 + signal: IN6 + - pin: PA7 + signal: IN7 + - pin: PB0 + signal: IN8 + - pin: PB1 + signal: IN9 + - name: CAN1 address: 0x40006400 registers: @@ -79,3 +744,27 @@ # 11:CAN_RX 映射到 PD0，CAN_TX 映射到 PD1; - { pin: "PD0", signal: "RX", remap: 3 } - { pin: "PD1", signal: "TX", remap: 3 } + +- name: USBPD + address: 0x40027000 + registers: + kind: usbpd + version: l1 + block: USBPD + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: AHBPCENR + field: USBPDEN + reset: + register: AHBRSTR + field: USBPDRST + interrupts: + - signal: GLOBAL + interrupt: USBPD + - signal: WKUP + interrupt: USBPD_WKUP + pins: + - { pin: "PB6", signal: "CC1" } + - { pin: "PB7", signal: "CC2" } diff --git a/data/family/CH32V1.yaml b/data/family/CH32V1.yaml index ff093b8..503d4be 100644 --- a/data/family/CH32V1.yaml +++ b/data/family/CH32V1.yaml @@ -382,10 +382,10 @@ kernel_clock: HCLK enable: register: AHBPCENR - field: USBFSEN + field: USBHDEN reset: - register: AHBPRSTR - field: USBFSRST + register: AHBRSTR + field: USBHDRST pins: - pin: PA11 signal: DM diff --git a/data/family/CH32X0.yaml b/data/family/CH32X0.yaml index 5b4dcfe..0dd7f56 100644 --- a/data/family/CH32X0.yaml +++ b/data/family/CH32X0.yaml @@ -334,7 +334,7 @@ address: 0x40013000 registers: kind: spi - version: x0 + version: v0 # The same as v0 block: SPI rcc: bus_clock: HCLK @@ -729,3 +729,13 @@ signal: DM - pin: PC17 signal: DP + +- name: AWU + address: 0x40026400 + registers: + kind: awu + version: x0 + block: AWU + interrupts: + - signal: GLOBAL + interrupt: AWU diff --git a/data/family/CH643.yaml b/data/family/CH643.yaml index 7541d73..9664574 100644 --- a/data/family/CH643.yaml +++ b/data/family/CH643.yaml @@ -334,7 +334,7 @@ address: 0x40013000 registers: kind: spi - version: x0 + version: v0 block: SPI rcc: bus_clock: HCLK diff --git a/data/interrupts/CH32V2_D6.yaml b/data/interrupts/CH32V2_D6.yaml index efe6803..03e41a7 100644 --- a/data/interrupts/CH32V2_D6.yaml +++ b/data/interrupts/CH32V2_D6.yaml @@ -38,7 +38,7 @@ DMA1_CHANNEL7: 33 ADC: 34 # USB HP and CAN1 TX USB_HP_CAN1_TX: 35 -# USB LP and CAN1RX0 +# USB LP and CAN1 RX0 USB_LP_CAN1_RX0: 36 # CAN1 RX1 CAN1_RX1: 37 diff --git a/data/peripherals/FV2x_V3x_USBFS.yaml b/data/peripherals/FV2x_V3x_USBFS.yaml index 103c86c..193cb1c 100644 --- a/data/peripherals/FV2x_V3x_USBFS.yaml +++ b/data/peripherals/FV2x_V3x_USBFS.yaml @@ -1,6 +1,4 @@ -# USBFS aka. OTG_FS -# base address: 0x50000000 - +# USBFS, without OTG cfg registers - name: USBFS address: 0x50000000 registers: @@ -12,10 +10,7 @@ kernel_clock: HCLK enable: register: AHBPCENR - field: OTGFSEN - reset: - register: AHBRSTR - field: OTGFSRST + field: OTG_EN interrupts: - signal: HP interrupt: USB_HP_CAN1_TX diff --git a/data/peripherals/FV2x_V3x_USBHS.yaml b/data/peripherals/FV2x_V3x_USBHS.yaml index d02e44d..5f9cc7b 100644 --- a/data/peripherals/FV2x_V3x_USBHS.yaml +++ b/data/peripherals/FV2x_V3x_USBHS.yaml @@ -1,3 +1,4 @@ +# USB2 - name: USBHS address: 0x40023400 registers: diff --git a/data/peripherals/FV2x_V3x_USB_OTG_FS.yaml b/data/peripherals/FV2x_V3x_USB_OTG_FS.yaml index cfb192d..c55e2d5 100644 --- a/data/peripherals/FV2x_V3x_USB_OTG_FS.yaml +++ b/data/peripherals/FV2x_V3x_USB_OTG_FS.yaml @@ -1,6 +1,4 @@ # USBFS aka. OTG_FS -# base address: 0x50000000 - - name: OTG_FS address: 0x50000000 registers: @@ -12,10 +10,7 @@ kernel_clock: HCLK enable: register: AHBPCENR - field: OTGFSEN - reset: - register: AHBRSTR - field: OTGFSRST + field: OTG_EN interrupts: - signal: HP interrupt: USB_HP_CAN1_TX diff --git a/data/peripherals/L1x_I2C2.yaml b/data/peripherals/L1x_I2C2.yaml new file mode 100644 index 0000000..f06bfca --- /dev/null +++ b/data/peripherals/L1x_I2C2.yaml @@ -0,0 +1,26 @@ +- name: I2C2 + address: 0x40005800 + registers: + kind: i2c + version: v3 + block: I2C + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: I2C2EN + reset: + register: APB1PRSTR + field: I2C2RST + interrupts: + - { "signal": "ER", "interrupt": "I2C2_ER" } + - { "signal": "EV", "interrupt": "I2C2_EV" } + # No remap + pins: + - pin: PB10 + signal: SCL + - pin: PB11 + signal: SDA + - pin: PB12 + signal: SMBA diff --git a/data/peripherals/L1x_SPI2.yaml b/data/peripherals/L1x_SPI2.yaml new file mode 100644 index 0000000..8b9f261 --- /dev/null +++ b/data/peripherals/L1x_SPI2.yaml @@ -0,0 +1,40 @@ +- name: SPI2 + address: 0x40003800 + registers: + kind: spi + version: v0 + block: SPI + rcc: + bus_clock: PCLK1 + kernel_clock: PCLK1 + enable: + register: APB1PCENR + field: SPI2EN + reset: + register: APB1PRSTR + field: SPI2RST + interrupts: + - signal: GLOBAL + interrupt: SPI2 + pins: + # 00:默认映射(NSS/PA4，SCK/PA5，MISO/PA6， MOSI/PA7) + - { pin: "PA4", signal: "NSS", remap: 0 } + - { pin: "PA5", signal: "SCK", remap: 0 } + - { pin: "PA6", signal: "MISO", remap: 0 } + - { pin: "PA7", signal: "MOSI", remap: 0 } + # 01:完全映射(NSS/PA15，SCK/PB3，MISO/PB4， MOSI/PB5) + - { pin: "PA15", signal: "NSS", remap: 1 } + - { pin: "PB3", signal: "SCK", remap: 1 } + - { pin: "PB4", signal: "MISO", remap: 1 } + - { pin: "PB5", signal: "MOSI", remap: 1 } + # 10:完全映射(NSS/PA12，SCK/PB6，MISO/PB8， MOSI/PB7) + - { pin: "PA12", signal: "NSS", remap: 2 } + - { pin: "PB6", signal: "SCK", remap: 2 } + - { pin: "PB8", signal: "MISO", remap: 2 } + - { pin: "PB7", signal: "MOSI", remap: 2 } + # 11:完全映射(NSS/PB12，SCK/PB6，MISO/PB8， MOSI/PB7) + - { pin: "PB12", signal: "NSS", remap: 3 } + - { pin: "PB13", signal: "SCK", remap: 3 } + - { pin: "PB14", signal: "MISO", remap: 3 } + - { pin: "PB15", signal: "MOSI", remap: 3 } + diff --git a/data/peripherals/X035_USBPD.yaml b/data/peripherals/X035_USBPD.yaml index cca0282..a0c9ac4 100644 --- a/data/peripherals/X035_USBPD.yaml +++ b/data/peripherals/X035_USBPD.yaml @@ -3,7 +3,7 @@ registers: kind: usbpd version: x0 - block: USB_PD + block: USBPD rcc: bus_clock: HCLK kernel_clock: HCLK @@ -21,3 +21,5 @@ interrupts: - signal: GLOBAL interrupt: USBPD + - signal: WKUP + interrupt: USBPD_WKUP diff --git a/data/registers/adc_l1.yaml b/data/registers/adc_l1.yaml new file mode 100644 index 0000000..bf4b0d4 --- /dev/null +++ b/data/registers/adc_l1.yaml @@ -0,0 +1,451 @@ +# ADC for CH32L1 +# - extra ADC_CFG +block/ADC: + description: Analog to digital converter. + items: + - name: STATR + description: status register. + byte_offset: 0 + fieldset: STATR + - name: CTLR1 + description: control register 1. + byte_offset: 4 + fieldset: CTLR1 + - name: CTLR2 + description: control register 2. + byte_offset: 8 + fieldset: CTLR2 + - name: SAMPTR1 + description: sample time register 1. + byte_offset: 12 + fieldset: SAMPTR1 + - name: SAMPTR2 + description: sample time register 2. + byte_offset: 16 + fieldset: SAMPTR2 + - name: IOFR + description: injected channel data offset register x. + array: + len: 4 + stride: 4 + byte_offset: 20 + fieldset: IOFR + - name: WDHTR + description: watchdog higher threshold register. + byte_offset: 36 + fieldset: WDHTR + - name: WDLTR + description: watchdog lower threshold register. + byte_offset: 40 + fieldset: WDLTR + - name: RSQR1 + description: regular sequence register 1. + byte_offset: 44 + fieldset: RSQR1 + - name: RSQR2 + description: regular sequence register 2. + byte_offset: 48 + fieldset: RSQR2 + - name: RSQR3 + description: regular sequence register 3. + byte_offset: 52 + fieldset: RSQR3 + - name: ISQR + description: injected sequence register. + byte_offset: 56 + fieldset: ISQR + - name: IDATAR + description: injected data register 1. + byte_offset: 60 + array: + len: 4 + stride: 4 + access: Read + fieldset: IDATAR + - name: RDATAR + description: regular data register_start and discharge time register. + byte_offset: 76 + fieldset: RDATAR + - name: CFG + description: ADC configuration register. + byte_offset: 80 + fieldset: CFG +fieldset/CFG: + description: ADC configuration register. + fields: + - name: ADC_BUFTRIM + description: ADC buffer misalignment control. + bit_offset: 0 + bit_size: 4 + - name: ADC_LP + description: ADC low-power mode control. + bit_offset: 5 + bit_size: 1 + - name: FIFO_EN + description: ADC FIFO enable. + bit_offset: 6 + bit_size: 1 + - name: ADC_DUTY_EN + description: ADC clock duty control. + bit_offset: 7 + bit_size: 1 + - name: TKEY_DRV_EN + description: TOUCHKEY shielded enable. + bit_offset: 8 + bit_size: 1 + - name: TKEY_DRV_OUTEN + description: TOUCHKEY shielded each channel enable. + bit_offset: 9 + bit_size: 10 + - name: TKEY_SEL + description: TOUCHKEY bias current. + bit_offset: 19 + bit_size: 2 + - name: TKEY_WAKE_EN + description: TOUCHKEY Wake-up enable. + bit_offset: 21 + bit_size: 10 +fieldset/CTLR1: + description: control register 1. + fields: + - name: AWDCH + description: Analog watchdog channel select bits. + bit_offset: 0 + bit_size: 5 + - name: EOCIE + description: Interrupt enable for EOC. + bit_offset: 5 + bit_size: 1 + - name: AWDIE + description: Analog watchdog interrupt enable. + bit_offset: 6 + bit_size: 1 + - name: JEOCIE + description: Interrupt enable for injected channels. + bit_offset: 7 + bit_size: 1 + - name: SCAN + description: Scan mode enable. + bit_offset: 8 + bit_size: 1 + - name: AWDSGL + description: Enable the watchdog on a single channel in scan mode. + bit_offset: 9 + bit_size: 1 + - name: JAUTO + description: Automatic injected group conversion. + bit_offset: 10 + bit_size: 1 + - name: RDISCEN + description: Discontinuous mode on regular channels. + bit_offset: 11 + bit_size: 1 + - name: JDISCEN + description: Discontinuous mode on injected channels. + bit_offset: 12 + bit_size: 1 + - name: DISCNUM + description: Discontinuous mode channel count. + bit_offset: 13 + bit_size: 3 + - name: CAL_MOD + description: ADC calibration mode control. + bit_offset: 21 + bit_size: 1 + - name: JAWDEN + description: Analog watchdog enable on injected channels. + bit_offset: 22 + bit_size: 1 + - name: AWDEN + description: Analog watchdog enable on regular channels. + bit_offset: 23 + bit_size: 1 + - name: TKENABLE + description: TKEY enable, including TKEY_F and TKEY_V. + bit_offset: 24 + bit_size: 1 + - name: TKITUNE + description: TKEY_I enable. + bit_offset: 25 + bit_size: 1 + - name: BUFEN + description: TKEY_BUF_Enable. + bit_offset: 26 + bit_size: 1 + - name: PGA + description: ADC_PGA. + bit_offset: 27 + bit_size: 2 +fieldset/CTLR2: + description: control register 2. + fields: + - name: ADON + description: A/D converter ON / OFF. + bit_offset: 0 + bit_size: 1 + - name: CONT + description: Continuous conversion. + bit_offset: 1 + bit_size: 1 + - name: CAL + description: A/D calibration. + bit_offset: 2 + bit_size: 1 + - name: RSTCAL + description: Reset calibration. + bit_offset: 3 + bit_size: 1 + - name: DMA + description: Direct memory access mode. + bit_offset: 8 + bit_size: 1 + - name: ALIGN + description: Data alignment. + bit_offset: 11 + bit_size: 1 + - name: JEXTSEL + description: External event select for injected group. + bit_offset: 12 + bit_size: 3 + enum: JEXTSEL + - name: JEXTTRIG + description: External trigger conversion mode for injected channels. + bit_offset: 15 + bit_size: 1 + - name: EXTSEL + description: External event select for regular group. + bit_offset: 17 + bit_size: 3 + enum: EXTSEL + - name: EXTTRIG + description: External trigger conversion mode for regular channels. + bit_offset: 20 + bit_size: 1 + - name: JSWSTART + description: Start conversion of injected channels. + bit_offset: 21 + bit_size: 1 + - name: SWSTART # renamed from RSWSTART + description: Start conversion of regular channels. + bit_offset: 22 + bit_size: 1 + - name: TSVREFE + description: Temperature sensor and VREFINT enable. + bit_offset: 23 + bit_size: 1 +fieldset/IDATAR: + description: injected data register 3. + fields: + - name: JDATA + description: Injected data. + bit_offset: 0 + bit_size: 16 +fieldset/IOFR: + description: injected channel data offset register x. + fields: + - name: JOFFSET + description: Data offset for injected channel x. + bit_offset: 0 + bit_size: 12 + array: + len: 1 + stride: 0 +fieldset/ISQR: + description: injected sequence register. + fields: + - name: JSQ + description: 1st conversion in injected sequence. + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: JL + description: Injected sequence length. + bit_offset: 20 + bit_size: 2 +fieldset/RDATAR: + description: regular data register. + fields: + - name: DATA + description: Regular data. + bit_offset: 0 + bit_size: 16 +fieldset/RSQR1: + description: regular sequence register 1. + fields: + - name: SQ + description: 13th conversion in regular sequence. + bit_offset: 0 + bit_size: 5 + array: + len: 4 + stride: 5 + - name: L + description: Regular channel sequence length. + bit_offset: 20 + bit_size: 4 +fieldset/RSQR2: + description: regular sequence register 2. + fields: + - name: SQ + description: 7th conversion in regular sequence. + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 +fieldset/RSQR3: + description: regular sequence register 3. + fields: + - name: SQ + description: 1st conversion in regular sequence. + bit_offset: 0 + bit_size: 5 + array: + len: 6 + stride: 5 +fieldset/SAMPTR1: + description: sample time register 1. Only ch 18, 17, 16 are available. + fields: + - name: SMP + description: Channel 10 sample time selection. + bit_offset: 0 + bit_size: 3 + array: + len: 9 + stride: 3 + enum: SAMPLE_TIME +fieldset/SAMPTR2: + description: sample time register 2. + fields: + - name: SMP + description: Channel 0 sample time selection. + bit_offset: 0 + bit_size: 3 + array: + len: 10 + stride: 3 + enum: SAMPLE_TIME +fieldset/STATR: + description: status register. + fields: + - name: AWD + description: Analog watchdog flag. + bit_offset: 0 + bit_size: 1 + - name: EOC + description: Regular channel end of conversion. + bit_offset: 1 + bit_size: 1 + - name: JEOC + description: Injected channel end of conversion. + bit_offset: 2 + bit_size: 1 + - name: JSTRT + description: Injected channel start flag. + bit_offset: 3 + bit_size: 1 + - name: STRT + description: Regular channel start flag. + bit_offset: 4 + bit_size: 1 +fieldset/WDHTR: + description: watchdog higher threshold register. + fields: + - name: HT + description: Analog watchdog higher threshold. + bit_offset: 0 + bit_size: 12 +fieldset/WDLTR: + description: watchdog lower threshold register. + fields: + - name: LT + description: Analog watchdog lower threshold. + bit_offset: 0 + bit_size: 12 +enum/EXTSEL: + bit_size: 3 + description: External event select for regular group. + variants: + - name: TIM1_CC1 + description: Timer 1 capture compare 1. + value: 0b000 + - name: TIM1_CC2 + description: Timer 1 capture compare 2. + value: 0b001 + - name: TIM1_CC3 + description: Timer 1 capture compare 3. + value: 0b010 + - name: TIM2_CC2 + description: Timer 2 capture compare 2. + value: 0b011 + - name: TIM3_TRGO + description: Timer 3 TRGO event. + value: 0b100 + - name: TIM4_CC4 + description: Timer 4 capture compare 4. + value: 0b101 + - name: EXTI11 + description: External interrupt line 11. + value: 0b110 + - name: SWSTART + description: Software start. + value: 0b111 +enum/JEXTSEL: + bit_size: 3 + description: External event select for injected group. + variants: + - name: TIM1_TRGO + description: Timer 1 TRGO event. + value: 0b000 + - name: TIM1_CC4 + description: Timer 1 capture compare 4. + value: 0b001 + - name: TIM2_TRGO + description: Timer 2 TRGO event. + value: 0b010 + - name: TIM2_CC1 + description: Timer 2 capture compare 1. + value: 0b011 + - name: TIM3_CC4 + description: Timer 3 capture compare 4. + value: 0b100 + - name: TIM4_TRGO + description: Timer 4 TRGO event. + value: 0b101 + - name: EXTI15 + description: External interrupt line 15. + value: 0b110 + - name: JSWSTART + description: Software start. + value: 0b111 +enum/SAMPLE_TIME: + bit_size: 3 + description: Sample time selection, when ADC_LP=0 + # TODO: value changes when ADC_LP=1 + variants: + - name: Cycles1_5 + description: 1.5 cycles + value: 0 + - name: Cycles7_5 + description: 7.5 cycles + value: 1 + - name: Cycles13_5 + description: 13.5 cycles + value: 2 + - name: Cycles28_5 + description: 28.5 cycles + value: 3 + - name: Cycles41_5 + description: 41.5 cycles + value: 4 + - name: Cycles55_5 + description: 55.5 cycles + value: 5 + - name: Cycles71_5 + description: 71.5 cycles + value: 6 + - name: Cycles239_5 + description: 239.5 cycles + value: 7 diff --git a/data/registers/afio_l1.yaml b/data/registers/afio_l1.yaml new file mode 100644 index 0000000..4cae7ad --- /dev/null +++ b/data/registers/afio_l1.yaml @@ -0,0 +1,168 @@ +block/AFIO: + description: Alternate function I/O. + items: + - name: ECR + description: Event Control Register (AFIO_ECR). + byte_offset: 0 + fieldset: ECR + - name: PCFR1 + description: AF remap and debug I/O configuration register 1 (AFIO_PCFR1). + byte_offset: 4 + fieldset: PCFR1 + - name: EXTICR + description: External interrupt configuration register 1 (AFIO_EXTICR1). + array: + len: 4 + stride: 4 + byte_offset: 8 + fieldset: EXTICR + - name: CR + description: AFIO control register (AFIO_CR). + byte_offset: 24 + fieldset: CR + - name: PCFR2 + description: AF remap and debug I/O configuration register (AFIO_PCFR2). + byte_offset: 28 + fieldset: PCFR2 +fieldset/CR: + description: AFIO control register (AFIO_CR). + fields: + - name: USBPD_IN_HVT + description: PD pin PB6/PD7 High threshold input mode. + bit_offset: 9 + bit_size: 1 + - name: UDP_BC_VSRC + description: PA12/UDP pin BC source voltage enable. + bit_offset: 16 + bit_size: 1 + - name: UDM_BC_VSRC + description: PA11/UDM pin BC source voltage enable. + bit_offset: 17 + bit_size: 1 + - name: UDP_BC_CMPE + description: PA12/UDP pin BC protocol comparator enable. + bit_offset: 18 + bit_size: 1 + - name: UDM_BC_CMPE + description: PA11/UDM pin BC protocol comparator enable. + bit_offset: 19 + bit_size: 1 + - name: UDP_BC_CMPO + description: PA12/UDP pin BC protocol comparator status. + bit_offset: 20 + bit_size: 1 + - name: UDM_BC_CMPO + description: PA11/UDM pin BC protocol comparator status. + bit_offset: 21 + bit_size: 1 +fieldset/ECR: + description: Event Control Register (AFIO_ECR). + fields: + - name: PIN + description: Pin selection. + bit_offset: 0 + bit_size: 4 + - name: PORT + description: Port selection. + bit_offset: 4 + bit_size: 3 + - name: EVOE + description: Event Output Enable. + bit_offset: 7 + bit_size: 1 +fieldset/EXTICR: + description: External interrupt configuration register 4 (AFIO_EXTICR4). + fields: + - name: EXTI + description: EXTI12 configuration. + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 4 +fieldset/PCFR1: + description: AF remap and debug I/O configuration register 1 (AFIO_PCFR1). + fields: + - name: SPI1_RM + description: SPI1 remapping. + bit_offset: 0 + bit_size: 1 + - name: I2C1_RM + description: I2C1 remapping. + bit_offset: 1 + bit_size: 1 + - name: USART1_RM + description: USART1 remapping. + bit_offset: 2 + bit_size: 1 + - name: USART2_RM + description: USART2 remapping. + bit_offset: 3 + bit_size: 1 + - name: USART3_RM + description: USART3 remapping. + bit_offset: 4 + bit_size: 2 + - name: TIM1_RM + description: TIM1 remapping. + bit_offset: 6 + bit_size: 2 + - name: TIM2_RM + description: TIM2 remapping. + bit_offset: 8 + bit_size: 2 + - name: TIM3_RM + description: TIM3 remapping. + bit_offset: 10 + bit_size: 1 + - name: TIM4_RM + description: TIM4 remapping. + bit_offset: 12 + bit_size: 1 + - name: CAN_RM + description: CAN remapping. + bit_offset: 13 + bit_size: 2 + - name: PD01_RM + description: Port D0/Port D1 mapping on OSCIN/OSCOUT. + bit_offset: 15 + bit_size: 1 + - name: SW_CFG + description: Serial wire JTAG configuration. + bit_offset: 24 + bit_size: 3 +fieldset/PCFR2: + description: AF remap and debug I/O configuration register (AFIO_PCFR2). + fields: + - name: USART4_RM + description: USART4 remapping. + bit_offset: 16 + bit_size: 1 + - name: USART2_RM_H + description: USART2 remapping. + bit_offset: 18 + bit_size: 1 + - name: USART1_RM_H + description: USART1 remapping. + bit_offset: 19 + bit_size: 2 + - name: TIM2_RM_H + description: TIM2 remapping. + bit_offset: 21 + bit_size: 1 + - name: TIM1_RM_H + description: TIM1 remapping. + bit_offset: 22 + bit_size: 1 + - name: I2C1_RM_H + description: I2C1 remapping. + bit_offset: 23 + bit_size: 1 + - name: SPI1_RM_H + description: SPI1 remapping. + bit_offset: 24 + bit_size: 1 + - name: LPTIM_RM + description: LPTIM remapping. + bit_offset: 25 + bit_size: 1 diff --git a/data/registers/awu_x0.yaml b/data/registers/awu_x0.yaml new file mode 100644 index 0000000..45ebfb6 --- /dev/null +++ b/data/registers/awu_x0.yaml @@ -0,0 +1,91 @@ +block/AWU: + description: AWU configuration. + items: + - name: CSR + description: Status Control register. + byte_offset: 0 + bit_size: 16 + fieldset: CSR + - name: WR + description: AWU Window register. + byte_offset: 4 + bit_size: 16 + fieldset: WR + - name: PSC + description: PSC. + byte_offset: 8 + bit_size: 16 + fieldset: PSC +fieldset/CSR: + description: Status Control register. + bit_size: 16 + fields: + - name: EN + description: AWU Enable. + bit_offset: 1 + bit_size: 1 +fieldset/PSC: + description: PSC. + bit_size: 16 + fields: + - name: TBR + description: AWU_TBR value. + bit_offset: 0 + bit_size: 4 + enum: PRESCALER +fieldset/WR: + description: AWU Window register. + bit_size: 16 + fields: + - name: APR + description: AWU_APR value. + bit_offset: 0 + bit_size: 6 +enum/PRESCALER: + bit_size: 4 + variants: + - name: DIV1 + description: DIV1. + value: 0b000 + - name: DIV2 + description: DIV2. + value: 0b0010 + - name: DIV4 + description: DIV4. + value: 0b0011 + - name: DIV8 + description: DIV8. + value: 0b0100 + - name: DIV16 + description: DIV16. + value: 0b0101 + - name: DIV32 + description: DIV32. + value: 0b0110 + - name: DIV64 + description: DIV64. + value: 0b0111 + - name: DIV128 + description: DIV128. + value: 0b1000 + - name: DIV256 + description: DIV256. + value: 0b1001 + - name: DIV512 + description: DIV512. + value: 0b1010 + - name: DIV1024 + description: DIV1024. + value: 0b1011 + - name: DIV2048 + description: DIV2048. + value: 0b1100 + - name: DIV4096 + description: DIV4096. + value: 0b1101 + - name: DIV10240 + description: DIV10240. + value: 0b1110 + - name: DIV61440 + description: DIV61440. + value: 0b1111 diff --git a/data/registers/extend_l1.yaml b/data/registers/extend_l1.yaml new file mode 100644 index 0000000..8debe8a --- /dev/null +++ b/data/registers/extend_l1.yaml @@ -0,0 +1,30 @@ +block/EXTEND: + description: EXTEND configuration. (EXTEN) + items: + - name: CTR + description: EXTEN control register. + byte_offset: 0 + fieldset: CTR +fieldset/CTR: + description: EXTEN control register. + fields: + - name: HSIPRE + description: Whether HSI is divided. + bit_offset: 4 + bit_size: 1 + - name: LKUPEN + description: LOCKUP_Eable. + bit_offset: 6 + bit_size: 1 + - name: LKUPRST + description: LOCKUP RESET. + bit_offset: 7 + bit_size: 1 + - name: ULLDOTRIM + description: ULLDOTRIM. + bit_offset: 8 + bit_size: 3 + - name: LDOTRIM + description: LDOTRIM. + bit_offset: 12 + bit_size: 2 diff --git a/data/registers/flash_l1.yaml b/data/registers/flash_l1.yaml new file mode 100644 index 0000000..c5f97fa --- /dev/null +++ b/data/registers/flash_l1.yaml @@ -0,0 +1,216 @@ +block/FLASH: + description: FLASH. + items: + - name: ACTLR + description: Access control register. + byte_offset: 0 + fieldset: ACTLR + - name: KEYR + description: Flash key register. + byte_offset: 4 + access: Write + fieldset: KEYR + - name: OBKEYR + description: Flash option key register. + byte_offset: 8 + access: Write + fieldset: OBKEYR + - name: STATR + description: Status register. + byte_offset: 12 + fieldset: STATR + - name: CTLR + description: Control register. + byte_offset: 16 + fieldset: CTLR + - name: ADDR + description: Flash address register. + byte_offset: 20 + access: Write + fieldset: ADDR + - name: OBR + description: Option byte register. + byte_offset: 28 + access: Read + fieldset: OBR + - name: WPR + description: Write protection register. + byte_offset: 32 + access: Read + fieldset: WPR + - name: MODEKEYR + description: Mode select register. + byte_offset: 36 + access: Write + fieldset: MODEKEYR +fieldset/ACTLR: + description: Access control register. + fields: + - name: LATENCY + description: FLASH standby condition. + bit_offset: 0 + bit_size: 2 +fieldset/ADDR: + description: Flash address register. + fields: + - name: FAR + description: Flash Address. + bit_offset: 0 + bit_size: 32 +fieldset/CTLR: + description: Control register. + fields: + - name: PER + description: Page Erase. + bit_offset: 1 + bit_size: 1 + - name: MER + description: Mass Erase. + bit_offset: 2 + bit_size: 1 + - name: OBPG + description: Option byte programming. + bit_offset: 4 + bit_size: 1 + - name: OBER + description: Option byte erase. + bit_offset: 5 + bit_size: 1 + - name: STRT + description: Start. + bit_offset: 6 + bit_size: 1 + - name: LOCK + description: Lock. + bit_offset: 7 + bit_size: 1 + - name: OBWRE + description: Option bytes write enable. + bit_offset: 9 + bit_size: 1 + - name: ERRIE + description: Error interrupt enable. + bit_offset: 10 + bit_size: 1 + - name: EOPIE + description: End of operation interrupt enable. + bit_offset: 12 + bit_size: 1 + - name: FWAKEIE + description: wake-up interrupt enable. + bit_offset: 13 + bit_size: 1 + - name: FLOCK + description: Fast programmable lock. + bit_offset: 15 + bit_size: 1 + - name: PTPG + description: Fast programming. + bit_offset: 16 + bit_size: 1 + - name: PTER + description: Fast erase. + bit_offset: 17 + bit_size: 1 + - name: BUFLOAD + description: Data buffer. + bit_offset: 18 + bit_size: 1 + - name: BUFRST + description: BUF reset. + bit_offset: 19 + bit_size: 1 + - name: BER32 + description: Block Erase 32K. + bit_offset: 23 + bit_size: 1 +fieldset/KEYR: + description: Flash key register. + fields: + - name: KEYR + description: FPEC key. + bit_offset: 0 + bit_size: 32 +fieldset/MODEKEYR: + description: Mode select register. + fields: + - name: MODEKEYR + description: Mode select. + bit_offset: 0 + bit_size: 32 +fieldset/OBKEYR: + description: Flash option key register. + fields: + - name: OBTKEY + description: Option byte key. + bit_offset: 0 + bit_size: 32 +fieldset/OBR: + description: Option byte register. + fields: + - name: OBERR + description: Option byte error. + bit_offset: 0 + bit_size: 1 + - name: RDPRT + description: Read protection. + bit_offset: 1 + bit_size: 1 + - name: IWDG_SW + description: IWDG_SW. + bit_offset: 2 + bit_size: 1 + - name: STOP_RST + description: STOP_RST. + bit_offset: 3 + bit_size: 1 + - name: STANDY_RST + description: STANDY_RST. + bit_offset: 4 + bit_size: 1 + - name: CFGCANM + description: Configure the offline recovery time. + bit_offset: 7 + bit_size: 1 + - name: FIX_11 + description: Fixed to 11. + bit_offset: 8 + bit_size: 2 + - name: DATA0 + description: Data byte 0. + bit_offset: 10 + bit_size: 8 + - name: DATA1 + description: Data byte 1. + bit_offset: 18 + bit_size: 8 +fieldset/STATR: + description: Status register. + fields: + - name: BSY + description: Busy. + bit_offset: 0 + bit_size: 1 + - name: WRPRTERR + description: Write protection error. + bit_offset: 4 + bit_size: 1 + - name: EOP + description: End of operation. + bit_offset: 5 + bit_size: 1 + - name: FWAKE_FLAG + description: Wake-Up flag. + bit_offset: 6 + bit_size: 1 + - name: TURBO + description: TURBO. + bit_offset: 7 + bit_size: 1 +fieldset/WPR: + description: Write protection register. + fields: + - name: WRP + description: Write protect. + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/lptim_l1.yaml b/data/registers/lptim_l1.yaml new file mode 100644 index 0000000..b4f219d --- /dev/null +++ b/data/registers/lptim_l1.yaml @@ -0,0 +1,241 @@ +block/LPTIM: + description: Low-power timer. + items: + - name: ISR + description: interrupt status register. + byte_offset: 0 + access: Read + fieldset: ISR + - name: ICR + description: interrupt clear register. + byte_offset: 4 + access: Write + fieldset: ICR + - name: IER + description: interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: compare register. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: aoto-reload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: COUNT register. + byte_offset: 28 + fieldset: CNT +fieldset/ARR: + description: aoto-reload register. + fields: + - name: ARR + description: aoto-reload count value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: configuration register. + fields: + - name: CKSEL + description: effective edge configuration. + bit_offset: 0 + bit_size: 1 + - name: CKPOL + description: configure effective edges. + bit_offset: 1 + bit_size: 2 + - name: CKFLT + description: digital filter for ex-clock. + bit_offset: 3 + bit_size: 2 + - name: TRGFLT + description: digital filter for flip-flops. + bit_offset: 6 + bit_size: 2 + - name: PRESC + description: prescaler configuration. + bit_offset: 9 + bit_size: 3 + - name: TRIGSEL + description: trigger source selection. + bit_offset: 13 + bit_size: 1 + - name: TRIGEN + description: trigger configuration. + bit_offset: 17 + bit_size: 2 + - name: TIMOUT + description: TIMEOUT control. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: PWM. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: PWM polarity. + bit_offset: 21 + bit_size: 1 + - name: PRELOAD + description: update mode control. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: count clock selection. + bit_offset: 23 + bit_size: 1 + - name: ENC + description: coder mode. + bit_offset: 24 + bit_size: 1 + - name: CLKMX_SEL + description: clock selection. + bit_offset: 25 + bit_size: 2 + - name: FORCE_PWM + description: Forcing pwm output. + bit_offset: 27 + bit_size: 1 +fieldset/CMP: + description: compare register. + fields: + - name: CMP + description: compare value. + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: COUNT register. + fields: + - name: COUNT + description: Timer count value. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: control register. + fields: + - name: ENABLE + description: timer enable. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: start in one trigger mode. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: start in continuous mode. + bit_offset: 2 + bit_size: 1 + - name: OUTEN + description: pwm output enable. + bit_offset: 3 + bit_size: 1 + - name: DIR_EXTEN + description: externally trigger count direction enable. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: interrupt clear register. + fields: + - name: CMPMCF + description: clear compare register match flag. + bit_offset: 0 + bit_size: 1 + - name: ARRMCF + description: clear Aoto-reload register match flag. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: clear Edge event are triggerd externally flag. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: clear compare register data update flag. + bit_offset: 3 + bit_size: 1 + - name: ARROKCF + description: clear Aoto-reload register data update flag. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: clear up flag. + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: clear down flag. + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: interrupt enable register. + fields: + - name: CMPMIE + description: compare register match successfully interrupts enable. + bit_offset: 0 + bit_size: 1 + - name: ARRMIE + description: Aoto-reload register match successfully interrupts enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: Edge event are triggerd externally successfully interrupts enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: compare register data update successfully interrupts enable. + bit_offset: 3 + bit_size: 1 + - name: ARROKIE + description: Aoto-reload register data update successfully interrupts enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: UP interrupt enable. + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: Down interrupt enable. + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: interrupt status register. + fields: + - name: CMPM + description: DATA of compare register and LPTIM_CNT match. + bit_offset: 0 + bit_size: 1 + - name: ARRM + description: DATA of Aoto-reload register and LPTIM_CNT match. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: Edge event are triggerd externally. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: compare register data update successfully. + bit_offset: 3 + bit_size: 1 + - name: ARROK + description: Aoto-reload register data update successfully. + bit_offset: 4 + bit_size: 1 + - name: UP + description: count-up. + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: count down. + bit_offset: 6 + bit_size: 1 + - name: DIR_SYNC + description: direction of count. + bit_offset: 7 + bit_size: 1 diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml new file mode 100644 index 0000000..34d64aa --- /dev/null +++ b/data/registers/rcc_l1.yaml @@ -0,0 +1,698 @@ +block/RCC: + description: Reset and clock control. + items: + - name: CTLR + description: Clock control register. + byte_offset: 0 + fieldset: CTLR + - name: CFGR0 + description: Clock configuration register (RCC_CFGR0). + byte_offset: 4 + fieldset: CFGR0 + - name: INTR + description: Clock interrupt register (RCC_INTR). + byte_offset: 8 + fieldset: INTR + - name: APB2PRSTR + description: APB2 peripheral reset register (RCC_APB2PRSTR). + byte_offset: 12 + fieldset: APB2PRSTR + - name: APB1PRSTR + description: APB1 peripheral reset register (RCC_APB1PRSTR). + byte_offset: 16 + fieldset: APB1PRSTR + - name: AHBPCENR + description: AHB Peripheral Clock enable register (RCC_AHBPCENR). + byte_offset: 20 + fieldset: AHBPCENR + - name: APB2PCENR + description: APB2 peripheral clock enable register (RCC_APB2PCENR). + byte_offset: 24 + fieldset: APB2PCENR + - name: APB1PCENR + description: APB1 peripheral clock enable register (RCC_APB1PCENR). + byte_offset: 28 + fieldset: APB1PCENR + - name: BDCTLR + description: Backup domain control register (RCC_BDCTLR). + byte_offset: 32 + fieldset: BDCTLR + - name: RSTSCKR + description: Control/status register (RCC_RSTSCKR). + byte_offset: 36 + fieldset: RSTSCKR + - name: AHBRSTR + description: AHB reset register (RCC_APHBRSTR). + byte_offset: 40 + fieldset: AHBRSTR +fieldset/AHBPCENR: + description: AHB Peripheral Clock enable register (RCC_AHBPCENR). + fields: + - name: DMAEN + description: DMA clock enable. + bit_offset: 0 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable. + bit_offset: 2 + bit_size: 1 + - name: CRCEN + description: CRC clock enable. + bit_offset: 6 + bit_size: 1 + - name: USBFSEN + description: USBFSEN clock enable. + bit_offset: 12 + bit_size: 1 + - name: USBPDEN + description: USBPD clock enable. + bit_offset: 17 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB reset register (RCC_APHBRSTR). + fields: + - name: USBFSRST + description: USBFD reset control. + bit_offset: 12 + bit_size: 1 + - name: USBPDRST + description: USBPD reset control. + bit_offset: 17 + bit_size: 1 +fieldset/APB1PCENR: + description: APB1 peripheral clock enable register (RCC_APB1PCENR). + fields: + - name: TIM2EN + description: Timer 2 clock enable. + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable. + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable. + bit_offset: 2 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable. + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable. + bit_offset: 14 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable. + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable. + bit_offset: 18 + bit_size: 1 + - name: USART4EN + description: USART 4 clock enable. + bit_offset: 19 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable. + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable. + bit_offset: 22 + bit_size: 1 + - name: CANEN + description: CAN clock enable. + bit_offset: 25 + bit_size: 1 + - name: BKPEN + description: Backup interface clock enable. + bit_offset: 27 + bit_size: 1 + - name: PWREN + description: Power interface clock enable. + bit_offset: 28 + bit_size: 1 + - name: LPTIMEN + description: LPTIM clock enable. + bit_offset: 31 + bit_size: 1 +fieldset/APB1PRSTR: + description: APB1 peripheral reset register (RCC_APB1PRSTR). + fields: + - name: TIM2RST + description: Timer 2 reset. + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset. + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 4 reset. + bit_offset: 2 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset. + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset. + bit_offset: 14 + bit_size: 1 + - name: USART2RST + description: USART 2 reset. + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART 3 reset. + bit_offset: 18 + bit_size: 1 + - name: USART4RST + description: USART 4 reset. + bit_offset: 19 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset. + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset. + bit_offset: 22 + bit_size: 1 + - name: CANRST + description: CAN reset. + bit_offset: 25 + bit_size: 1 + - name: BKPRST + description: Backup interface reset. + bit_offset: 27 + bit_size: 1 + - name: PWRRST + description: Power interface reset. + bit_offset: 28 + bit_size: 1 + - name: LPTIMRST + description: LPTIM reset. + bit_offset: 31 + bit_size: 1 +fieldset/APB2PCENR: + description: APB2 peripheral clock enable register (RCC_APB2PCENR). + fields: + - name: AFIOEN + description: Alternate function I/O clock enable. + bit_offset: 0 + bit_size: 1 + - name: IOPAEN + description: I/O port A clock enable. + bit_offset: 2 + bit_size: 1 + - name: IOPBEN + description: I/O port B clock enable. + bit_offset: 3 + bit_size: 1 + - name: IOPCEN + description: I/O port C clock enable. + bit_offset: 4 + bit_size: 1 + - name: IOPDEN + description: I/O port D clock enable. + bit_offset: 5 + bit_size: 1 + - name: ADCEN + description: ADC interface clock enable. + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable. + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable. + bit_offset: 12 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable. + bit_offset: 14 + bit_size: 1 +fieldset/APB2PRSTR: + description: APB2 peripheral reset register (RCC_APB2PRSTR). + fields: + - name: AFIORST + description: Alternate function I/O reset. + bit_offset: 0 + bit_size: 1 + - name: IOPARST + description: IO port A reset. + bit_offset: 2 + bit_size: 1 + - name: IOPBRST + description: IO port B reset. + bit_offset: 3 + bit_size: 1 + - name: IOPCRST + description: IO port C reset. + bit_offset: 4 + bit_size: 1 + - name: IOPDRST + description: IO port D reset. + bit_offset: 5 + bit_size: 1 + - name: ADCRST + description: ADC 1 interface reset. + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset. + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset. + bit_offset: 12 + bit_size: 1 + - name: USART1RST + description: USART1 reset. + bit_offset: 14 + bit_size: 1 +fieldset/BDCTLR: + description: Backup domain control register (RCC_BDCTLR). + fields: + - name: LSEON + description: External Low Speed oscillator enable. + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready. + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass. + bit_offset: 2 + bit_size: 1 + - name: RTCSEL + description: RTC clock source selection. + bit_offset: 8 + bit_size: 2 + - name: RTCEN + description: RTC clock enable. + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset. + bit_offset: 16 + bit_size: 1 +fieldset/CFGR0: + description: Clock configuration register (RCC_CFGR0). + fields: + - name: SW + description: System clock Switch. + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status. + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler. + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1). + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB High speed prescaler (APB2). + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler. + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source. + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: HSE divider for PLL entry. + bit_offset: 17 + bit_size: 1 + - name: PLLMUL + description: PLL Multiplication Factor. + bit_offset: 18 + bit_size: 4 + enum: PLL_MUL + - name: USBPRE + description: USB prescaler. + bit_offset: 22 + bit_size: 2 + enum: USBPRE + - name: MCO + description: Microcontroller clock output. + bit_offset: 24 + bit_size: 3 + enum: MCO + - name: ADC_DUTY_CHG + description: ADC clock duty cycle control. + bit_offset: 28 + bit_size: 3 + - name: ADC_PRE_ADJ + description: ADC clock input selection. + bit_offset: 31 + bit_size: 1 +fieldset/CTLR: + description: Clock control register. + fields: + - name: HSION + description: Internal High Speed clock enable. + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: HSI Internal High Speed clock ready flag. + bit_offset: 1 + bit_size: 1 + - name: HSILP + description: HSI Internal low-power mode. + bit_offset: 2 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming. + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration. + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable. + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag. + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass. + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable. + bit_offset: 19 + bit_size: 1 + - name: HSELP + description: HSE low-power mode. + bit_offset: 20 + bit_size: 1 + - name: PLLON + description: PLL enable. + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag. + bit_offset: 25 + bit_size: 1 +fieldset/INTR: + description: Clock interrupt register (RCC_INTR). + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag. + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag. + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag. + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag. + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag. + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag. + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable. + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable. + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable. + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear. + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear. + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear. + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear. + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear. + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear. + bit_offset: 23 + bit_size: 1 +fieldset/RSTSCKR: + description: Control/status register (RCC_RSTSCKR). + fields: + - name: LSION + description: Internal low speed oscillator enable. + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready. + bit_offset: 1 + bit_size: 1 + - name: RMVF + description: Remove reset flag. + bit_offset: 24 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag. + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag. + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag. + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag. + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag. + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag. + bit_offset: 31 + bit_size: 1 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI + description: HSI or HSI/2 selected as PLL input clock. + value: 0 + - name: HSE + description: HSE or HSE/2 selected as PLL input clock. + value: 1 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock. + value: 0b00 + - name: HSE + description: HSE selected as system clock. + value: 0b01 + - name: PLL + description: PLL selected as system clock. + value: 0b10 +enum/PPRE: + bit_size: 3 + variants: + - name: DIV1 + description: HCLK not divided. + value: 0b000 + - name: DIV2 + description: HCLK divided by 2. + value: 0b100 + - name: DIV4 + description: HCLK divided by 4. + value: 0b101 + - name: DIV8 + description: HCLK divided by 8. + value: 0b110 + - name: DIV16 + description: HCLK divided by 16. + value: 0b111 +enum/HPRE: + bit_size: 4 + variants: + - name: DIV1 + description: SYSCLK not divided. + value: 0b0000 + - name: DIV2 + description: SYSCLK divided by 2. + value: 0b1000 + - name: DIV4 + description: SYSCLK divided by 4. + value: 0b1001 + - name: DIV8 + description: SYSCLK divided by 8. + value: 0b1010 + - name: DIV16 + description: SYSCLK divided by 16. + value: 0b1011 + - name: DIV64 + description: SYSCLK divided by 64. + value: 0b1100 + - name: DIV128 + description: SYSCLK divided by 128. + value: 0b1101 + - name: DIV256 + description: SYSCLK divided by 256. + value: 0b1110 + - name: DIV512 + description: SYSCLK divided by 512. + value: 0b1111 +enum/ADCPRE: + bit_size: 2 + variants: + - name: DIV2 + description: PCLK2 divided by 2. + value: 0b00 + - name: DIV4 + description: PCLK2 divided by 4. + value: 0b01 + - name: DIV6 + description: PCLK2 divided by 6. + value: 0b10 + - name: DIV8 + description: PCLK2 divided by 8. + value: 0b11 +enum/PLL_MUL: + description: PLL Multiplication Factor. + bit_size: 4 + variants: + - name: MUL2 + description: PLL input clock x 2. + value: 0b0000 + - name: MUL3 + description: PLL input clock x 3. + value: 0b0001 + - name: MUL4 + description: PLL input clock x 4. + value: 0b0010 + - name: MUL5 + description: PLL input clock x 5. + value: 0b0011 + - name: MUL6 + description: PLL input clock x 6. + value: 0b0100 + - name: MUL7 + description: PLL input clock x 7. + value: 0b0101 + - name: MUL8 + description: PLL input clock x 8. + value: 0b0110 + - name: MUL9 + description: PLL input clock x 9. + value: 0b0111 + - name: MUL10 + description: PLL input clock x 10. + value: 0b1000 + - name: MUL11 + description: PLL input clock x 11. + value: 0b1001 + - name: MUL12 + description: PLL input clock x 12. + value: 0b1010 + - name: MUL13 + description: PLL input clock x 13. + value: 0b1011 + - name: MUL14 + description: PLL input clock x 14. + value: 0b1100 + - name: MUL15 + description: PLL input clock x 15. + value: 0b1101 + - name: MUL16 + description: PLL input clock x 16. + value: 0b1110 + - name: MUL18 + description: PLL input clock x 18. + value: 0b1111 +enum/USBPRE: + description: USB prescaler. + bit_size: 2 + variants: + - name: DIV1 + description: PLL clock divided by 1(PLLCLK=48MHz). + value: 0b00 + - name: DIV2 + description: PLL clock divided by 2(PLLCLK=96MHz). + value: 0b01 + - name: DIV1_5 + description: PLL clock divided by 1.5(PLLCLK=72MHz). + value: 0b10 +enum/MCO: + description: Microcontroller clock output. + bit_size: 3 + variants: + - name: NO_CLK + description: No clock. + value: 0b000 + - name: SYSCLK + description: SYSCLK selected. + value: 0b100 + - name: HSI + description: HSI selected. + value: 0b101 + - name: HSE + description: HSE selected. + value: 0b110 + - name: PLL_DIV2 + description: PLL clock divided by 2. + value: 0b111 diff --git a/data/registers/rcc_v0.yaml b/data/registers/rcc_v0.yaml index 97764c9..d0e4a5d 100644 --- a/data/registers/rcc_v0.yaml +++ b/data/registers/rcc_v0.yaml @@ -409,9 +409,6 @@ enum/SW: - name: PLL description: PLL selected as system clock. value: 0b10 - - name: _RESERVED - description: Reserved. - value: 0b11 enum/MCO: bit_size: 3 variants: diff --git a/data/registers/rcc_v1.yaml b/data/registers/rcc_v1.yaml index 2af2815..c26ac54 100644 --- a/data/registers/rcc_v1.yaml +++ b/data/registers/rcc_v1.yaml @@ -71,7 +71,7 @@ fieldset/AHBPCENR: fieldset/AHBRSTR: description: AHB reset register(RCC_APHBRSTR). fields: - - name: USBHSRST + - name: USBHDRST description: USBHD reset. bit_offset: 12 bit_size: 1 @@ -349,6 +349,7 @@ fieldset/CFGR0: description: USB prescaler. bit_offset: 22 bit_size: 1 + enum: USBPRE - name: MCO description: Microcontroller clock output. bit_offset: 24 @@ -527,9 +528,6 @@ enum/SW: - name: PLL description: PLL selected as system clock. value: 0b10 - - name: RESERVED - description: Reserved. - value: 0b11 enum/PPRE: bit_size: 3 variants: @@ -645,3 +643,13 @@ enum/PLL_MUL: - name: MUL16_ALT description: PLL input clock x 16. value: 0b1111 +enum/USBPRE: + description: USB prescaler. + bit_size: 1 + variants: + - name: DIV1 + description: PLL clock divided by 1(PLLCLK=48MHz). + value: 0b1 + - name: DIV1_5 + description: PLL clock divided by 1.5(PLLCLK=72MHz). + value: 0b0 diff --git a/data/registers/rcc_v3.yaml b/data/registers/rcc_v3.yaml index 6125451..f01a937 100644 --- a/data/registers/rcc_v3.yaml +++ b/data/registers/rcc_v3.yaml @@ -853,9 +853,6 @@ enum/SW: - name: PLL description: PLL selected as system clock. value: 0b10 - - name: RESERVED - description: Reserved. - value: 0b11 enum/HPRE: description: AHB prescaler. bit_size: 4 diff --git a/data/registers/rcc_v3_d8c.yaml b/data/registers/rcc_v3_d8c.yaml index cdc6c8c..c82bab2 100644 --- a/data/registers/rcc_v3_d8c.yaml +++ b/data/registers/rcc_v3_d8c.yaml @@ -853,9 +853,6 @@ enum/SW: - name: PLL description: PLL selected as system clock. value: 0b10 - - name: RESERVED - description: Reserved. - value: 0b11 enum/HPRE: description: AHB prescaler. bit_size: 4 diff --git a/data/registers/spi_x0.yaml b/data/registers/spi_x0.yaml deleted file mode 100644 index fb9430a..0000000 --- a/data/registers/spi_x0.yaml +++ /dev/null @@ -1,239 +0,0 @@ -block/SPI: - description: Serial peripheral interface. - items: - - name: CTLR1 - description: control register 1. - byte_offset: 0 - bit_size: 16 - fieldset: CTLR1 - - name: CTLR2 - description: control register 2. - byte_offset: 4 - bit_size: 16 - fieldset: CTLR2 - - name: STATR - description: status register. - byte_offset: 8 - bit_size: 16 - fieldset: STATR - - name: DATAR - description: data register. - byte_offset: 12 - bit_size: 16 - fieldset: DATAR - - name: CRCR - description: CRCR polynomial register. - byte_offset: 16 - bit_size: 16 - fieldset: CRCR - - name: RCRCR - description: RX CRC register. - byte_offset: 20 - access: Read - bit_size: 16 - fieldset: RCRCR - - name: TCRCR - description: send CRC register. - byte_offset: 24 - access: Read - bit_size: 16 - fieldset: TCRCR - - name: HSCR - description: high speed control register. - byte_offset: 36 - access: Write - bit_size: 16 - fieldset: HSCR -fieldset/CRCR: - description: CRCR polynomial register. - bit_size: 16 - fields: - - name: CRCPOLY - description: CRC polynomial register. - bit_offset: 0 - bit_size: 16 -fieldset/CTLR1: - description: control register 1. - bit_size: 16 - fields: - - name: CPHA - description: Clock phase. - bit_offset: 0 - bit_size: 1 - - name: CPOL - description: Clock polarity. - bit_offset: 1 - bit_size: 1 - - name: MSTR - description: Master selection. - bit_offset: 2 - bit_size: 1 - - name: BR - description: Baud rate control. - bit_offset: 3 - bit_size: 3 - enum: BAUD_RATE - - name: SPE - description: SPI enable. - bit_offset: 6 - bit_size: 1 - - name: LSBFIRST - description: Frame format. - bit_offset: 7 - bit_size: 1 - - name: SSI - description: Internal slave select. - bit_offset: 8 - bit_size: 1 - - name: SSM - description: Software slave management. - bit_offset: 9 - bit_size: 1 - - name: RXONLY - description: Receive only. - bit_offset: 10 - bit_size: 1 - - name: DFF - description: Data frame format. - bit_offset: 11 - bit_size: 1 - - name: CRCNEXT - description: CRC transfer next. - bit_offset: 12 - bit_size: 1 - - name: CRCEN - description: Hardware CRC calculation enable. - bit_offset: 13 - bit_size: 1 - - name: BIDIOE - description: Output enable in bidirectional mode. - bit_offset: 14 - bit_size: 1 - - name: BIDIMODE - description: Bidirectional data mode enable. - bit_offset: 15 - bit_size: 1 -fieldset/CTLR2: - description: control register 2. - bit_size: 16 - fields: - - name: RXDMAEN - description: Rx buffer DMA enable. - bit_offset: 0 - bit_size: 1 - - name: TXDMAEN - description: Tx buffer DMA enable. - bit_offset: 1 - bit_size: 1 - - name: SSOE - description: SS output enable. - bit_offset: 2 - bit_size: 1 - - name: ERRIE - description: Error interrupt enable. - bit_offset: 5 - bit_size: 1 - - name: RXNEIE - description: RX buffer not empty interrupt enable. - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: Tx buffer empty interrupt enable. - bit_offset: 7 - bit_size: 1 -fieldset/DATAR: - description: data register. - bit_size: 16 - fields: - - name: DR - description: Data register. - bit_offset: 0 - bit_size: 16 -fieldset/HSCR: - description: high speed control register. - bit_size: 16 - fields: - - name: HSRXEN - description: High speed mode read enable. - bit_offset: 0 - bit_size: 1 -fieldset/RCRCR: - description: RX CRC register. - bit_size: 16 - fields: - - name: RXCRC - description: Rx CRC register. - bit_offset: 0 - bit_size: 16 -fieldset/STATR: - description: status register. - bit_size: 16 - fields: - - name: RXNE - description: Receive buffer not empty. - bit_offset: 0 - bit_size: 1 - - name: TXE - description: Transmit buffer empty. - bit_offset: 1 - bit_size: 1 - - name: CHSID - description: Channel side. - bit_offset: 2 - bit_size: 1 - - name: UDR - description: Underrun flag. - bit_offset: 3 - bit_size: 1 - - name: CRCERR - description: CRC error flag. - bit_offset: 4 - bit_size: 1 - - name: MODF - description: Mode fault. - bit_offset: 5 - bit_size: 1 - - name: OVR - description: Overrun flag. - bit_offset: 6 - bit_size: 1 - - name: BSY - description: Busy flag. - bit_offset: 7 - bit_size: 1 -fieldset/TCRCR: - description: RX CRC register. - bit_size: 16 - fields: - - name: TXCRC - description: TX CRC register. - bit_offset: 0 - bit_size: 16 -enum/BAUD_RATE: - description: Baud rate control. - bit_size: 3 - variants: - - name: DIV_2 - description: fPCLK/2 - value: 0 - - name: DIV_4 - description: fPCLK/4 - value: 1 - - name: DIV_8 - description: fPCLK/8 - value: 2 - - name: DIV_16 - description: fPCLK/16 - value: 3 - - name: DIV_32 - description: fPCLK/32 - value: 4 - - name: DIV_64 - description: fPCLK/64 - value: 5 - - name: DIV_128 - description: fPCLK/128 - value: 6 - - name: DIV_256 - description: fPCLK/256 - value: 7 diff --git a/data/registers/timer_v3.yaml b/data/registers/timer_v3.yaml index 1a43471..c38a214 100644 --- a/data/registers/timer_v3.yaml +++ b/data/registers/timer_v3.yaml @@ -695,8 +695,6 @@ enum/CKD: - name: Div_4 description: Tdts=4*Tck_int value: 0b10 - - name: Reserved - value: 0b11 enum/FilterValue: bit_size: 4 variants: diff --git a/data/registers/timer_x0.yaml b/data/registers/timer_x0.yaml index bb6e1bb..81d43db 100644 --- a/data/registers/timer_x0.yaml +++ b/data/registers/timer_x0.yaml @@ -774,8 +774,6 @@ enum/CKD: - name: Div_4 description: Tdts=4*Tck_int value: 0b10 - - name: Reserved - value: 0b11 enum/FilterValue: bit_size: 4 variants: diff --git a/data/registers/usbpd_ch641.yaml b/data/registers/usbpd_ch641.yaml new file mode 100644 index 0000000..f404b36 --- /dev/null +++ b/data/registers/usbpd_ch641.yaml @@ -0,0 +1,295 @@ +block/USB_PD: + description: USBPD configuration. + items: + - name: CONFIG + description: PD interrupt enable register. + byte_offset: 0 + bit_size: 16 + fieldset: CONFIG + - name: BMC_CLK_CNT + description: BMC sampling clock counter. + byte_offset: 2 + bit_size: 16 + fieldset: BMC_CLK_CNT + - name: CONTROL + description: PD Send and receive enable register. + byte_offset: 4 + bit_size: 8 + fieldset: CONTROL + - name: TX_SEL + description: SOP port selection register. + byte_offset: 5 + bit_size: 8 + fieldset: TX_SEL + - name: BMC_TX_SZ + description: PD send length register. + byte_offset: 6 + bit_size: 16 + fieldset: BMC_TX_SZ + - name: DATA_BUF + description: DMA cache data register. + byte_offset: 8 + bit_size: 8 + - name: STATUS + description: PD interrupt flag register. + byte_offset: 9 + bit_size: 8 + fieldset: STATUS + - name: BMC_BYTE_CNT + description: Byte counter. + byte_offset: 10 + bit_size: 16 + fieldset: BMC_BYTE_CNT + - name: PORT_CC1 + description: CC1 port control register. + byte_offset: 12 + bit_size: 8 + fieldset: PORT_CC + - name: PORT_CC2 + description: CC2 port control register. + byte_offset: 14 + bit_size: 8 + fieldset: PORT_CC + - name: PORT_CC3 + description: CC3 port control register. + byte_offset: 15 + bit_size: 8 + fieldset: PORT_CC + - name: DMA + description: PD buffer start address register. + byte_offset: 16 + bit_size: 16 +fieldset/BMC_BYTE_CNT: + description: Byte counter. + bit_size: 16 + fields: + - name: BMC_BYTE_CNT + description: BMC_BYTE_CNT value. + bit_offset: 0 + bit_size: 9 +fieldset/BMC_CLK_CNT: + description: BMC sampling clock counter. + bit_size: 16 + fields: + - name: BMC_CLK_CNT + description: R/T counter. + bit_offset: 0 + bit_size: 9 +fieldset/BMC_TX_SZ: + description: PD send length register. + bit_size: 16 + fields: + - name: BMC_TX_SZ + description: BMC_TX_SZ value. + bit_offset: 0 + bit_size: 9 +fieldset/CONFIG: + description: PD interrupt enable register. + bit_size: 16 + fields: + - name: CC_FILTER + description: PIN filtering enabled. + bit_offset: 0 + bit_size: 1 + - name: PD_ALL_CLR + description: PD ITClear. + bit_offset: 1 + bit_size: 1 + - name: CC_SEL + description: PD Commutation port. + bit_offset: 2 + bit_size: 2 + - name: PD_DMA_EN + description: PD DMA Enable. + bit_offset: 4 + bit_size: 1 + - name: PD_RST_EN + description: PD RST Enable. + bit_offset: 5 + bit_size: 1 + - name: WAKE_POLAR + description: wakeup polarity. + bit_offset: 6 + bit_size: 1 + - name: IE_PD_IO + description: IO Enable. + bit_offset: 10 + bit_size: 1 + - name: IE_RX_BIT + description: bit interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: IE_RX_BYTE + description: Receive byte register. + bit_offset: 12 + bit_size: 1 + - name: IE_RX_ACT + description: Receive complete register. + bit_offset: 13 + bit_size: 1 + - name: IE_RX_RESET + description: Receive complete rst register. + bit_offset: 14 + bit_size: 1 + - name: IE_TX_END + description: transfer complete register. + bit_offset: 15 + bit_size: 1 +fieldset/CONTROL: + description: PD Send and receive enable register. + bit_size: 8 + fields: + - name: PD_TX_EN + description: PD_TX_EN value. + bit_offset: 0 + bit_size: 1 + - name: BMC_START + description: BMC_START value. + bit_offset: 1 + bit_size: 1 + - name: RX_START + description: PD receive status identification. + bit_offset: 2 + bit_size: 3 + - name: DATA_FLAG + description: DATA_FLAG value. + bit_offset: 5 + bit_size: 1 + - name: TX_BIT_BACK + description: TX_BIT_BACK value. + bit_offset: 6 + bit_size: 1 + - name: BMC_BYTE_HI + description: BMC_BYTE_HI value. + bit_offset: 7 + bit_size: 1 +fieldset/PORT_CC: + description: CC port control register. + bit_size: 8 + fields: + - name: CC_CMP0 + description: CC1 output of the voltage comparator. + bit_offset: 0 + bit_size: 1 + - name: CC_PD + description: CC1 port pull-down resistor enable. + bit_offset: 1 + bit_size: 1 + - name: CC_PU + description: CC1 port pull-up current selection. + bit_offset: 2 + bit_size: 2 + enum: PORT_CC_PU + - name: CC_LVE + description: CC1 port output of the low voltage. + bit_offset: 4 + bit_size: 1 + - name: CC_CVS + description: CC1 voltage comparator reference voltage. + bit_offset: 5 + bit_size: 2 + enum: PORT_CC_CVS + - name: CC_CE + description: CC1 voltage comparator enable. + bit_offset: 7 + bit_size: 1 +fieldset/STATUS: + description: PD interrupt flag register. + bit_size: 8 + fields: + - name: BMC_AUX + description: BMC_AUX value. + bit_offset: 0 + bit_size: 2 + enum: BMC_AUX + - name: BUF_ERR + description: BUF_ERR value. + bit_offset: 2 + bit_size: 1 + - name: IF_RX_BIT + description: IF_RX_BIT value. + bit_offset: 3 + bit_size: 1 + - name: IF_RX_BYTE + description: IF_RX_BYTE value. + bit_offset: 4 + bit_size: 1 + - name: IF_RX_ACT + description: IF_RX_ACT value. + bit_offset: 5 + bit_size: 1 + - name: IF_RX_RESET + description: IF_RX_RESET value. + bit_offset: 6 + bit_size: 1 + - name: IF_TX_END + description: IF_TX_END value. + bit_offset: 7 + bit_size: 1 +fieldset/TX_SEL: + description: SOP port selection register. + bit_size: 8 + fields: + - name: TX_SEL1 + description: K-CODE1 type selection. + bit_offset: 0 + bit_size: 1 + - name: TX_SEL2 + description: K-CODE2 type selection. + bit_offset: 2 + bit_size: 2 + - name: TX_SEL3 + description: K-CODE3 type selection. + bit_offset: 4 + bit_size: 2 + - name: TX_SEL4 + description: K-CODE4 type selection. + bit_offset: 6 + bit_size: 2 +enum/PORT_CC_CVS: + descrption: CC voltage comparator reference voltage. + bit_size: 2 + variants: + - name: V0_55 + description: 0.55V + value: 0b00 + - name: V0_22 + description: 0.22V + value: 0b01 + - name: V0_66 + description: 0.66V + value: 0b10 + - name: V1_23 + description: 1.23V + value: 0b11 +enum/PORT_CC_PU: + bit_size: 2 + variants: + - name: Closed + description: No pull up current. + value: 0 + - name: uA330 + description: 330uA. + value: 1 + - name: uA180 + description: 180uA. + value: 2 + - name: uA80 + description: 80uA. + value: 3 +enum/BMC_AUX: + bit_size: 2 + description: PD status after receive. # TODO: sending state is not included. + variants: + - name: NONE + description: BMC_AUX0 value. + value: 0 + - name: SOP0 + description: SOP, aka SOP0 + value: 1 + - name: SOP1 + description: SOP', aka SOP1 or Hard Reset + value: 2 + - name: SOP2 + description: SOP'', aka SOP2 or Cable Resed + value: 3 diff --git a/data/registers/usbpd_l1.yaml b/data/registers/usbpd_l1.yaml new file mode 100644 index 0000000..1d387d2 --- /dev/null +++ b/data/registers/usbpd_l1.yaml @@ -0,0 +1,306 @@ +block/USBPD: + description: USBPD configuration. + items: + - name: CONFIG + description: PD interrupt enable register. + byte_offset: 0 + bit_size: 16 + fieldset: CONFIG + - name: BMC_CLK_CNT + description: BMC sampling clock counter. + byte_offset: 2 + bit_size: 16 + fieldset: BMC_CLK_CNT + - name: CONTROL + description: PD Send and receive enable register. + byte_offset: 4 + bit_size: 8 + fieldset: CONTROL + - name: TX_SEL + description: SOP port selection register. + byte_offset: 5 + bit_size: 8 + fieldset: TX_SEL + - name: BMC_TX_SZ + description: PD send length register. + byte_offset: 6 + bit_size: 16 + fieldset: BMC_TX_SZ + - name: DATA_BUF + description: DMA cache data register. + byte_offset: 8 + bit_size: 8 + - name: STATUS + description: PD interrupt flag register. + byte_offset: 9 + bit_size: 8 + fieldset: STATUS + - name: BMC_BYTE_CNT + description: Byte counter. + byte_offset: 10 + bit_size: 16 + fieldset: BMC_BYTE_CNT + - name: PORT_CC1 + description: CC1 port control register. + byte_offset: 12 + bit_size: 16 + fieldset: PORT_CC + - name: PORT_CC2 + description: CC2 port control register. + byte_offset: 14 + bit_size: 16 + fieldset: PORT_CC + - name: DMA + description: PD buffer start address register. + byte_offset: 16 + bit_size: 16 +fieldset/BMC_BYTE_CNT: + description: Byte counter. + bit_size: 16 + fields: + - name: BMC_BYTE_CNT + description: BMC_BYTE_CNT value. + bit_offset: 0 + bit_size: 9 +fieldset/BMC_CLK_CNT: + description: BMC sampling clock counter. + bit_size: 16 + fields: + - name: BMC_CLK_CNT + description: R/T counter. + bit_offset: 0 + bit_size: 9 +fieldset/BMC_TX_SZ: + description: PD send length register. + bit_size: 16 + fields: + - name: BMC_TX_SZ + description: BMC_TX_SZ value. + bit_offset: 0 + bit_size: 9 +fieldset/CONFIG: + description: PD interrupt enable register. + bit_size: 16 + fields: + - name: PD_ALL_CLR + description: PD ITClear. + bit_offset: 1 + bit_size: 1 + - name: CC_SEL + description: PD Commutation port. + bit_offset: 2 + bit_size: 1 + enum: CC_SEL + - name: PD_DMA_EN + description: PD DMA Enable. + bit_offset: 3 + bit_size: 1 + - name: PD_RST_EN + description: PD RST Enable. + bit_offset: 4 + bit_size: 1 + - name: WAKE_POLAR + description: wakeup polarity. + bit_offset: 5 + bit_size: 1 + # new in usbpd_l1.yaml + - name: MULTI_0 + description: Multiple 0 received. + bit_offset: 8 + bit_size: 1 + - name: RTX_BIT0 + description: Value of RX/TX shift register, bit 0. + bit_offset: 9 + bit_size: 1 + - name: IE_PD_IO + description: IO Enable. + bit_offset: 10 + bit_size: 1 + - name: IE_RX_BIT + description: bit interrupt Enable. + bit_offset: 11 + bit_size: 1 + - name: IE_RX_BYTE + description: Receive byte register. + bit_offset: 12 + bit_size: 1 + - name: IE_RX_ACT + description: Receive complete register. + bit_offset: 13 + bit_size: 1 + - name: IE_RX_RESET + description: Receive complete rst register. + bit_offset: 14 + bit_size: 1 + - name: IE_TX_END + description: transfer complete register. + bit_offset: 15 + bit_size: 1 +fieldset/CONTROL: + description: PD Send and receive enable register. + bit_size: 8 + fields: + - name: PD_TX_EN + description: PD_TX_EN value. + bit_offset: 0 + bit_size: 1 + - name: BMC_START + description: BMC_START value. + bit_offset: 1 + bit_size: 1 + - name: DATA_FLAG + description: DATA_FLAG value. + bit_offset: 5 + bit_size: 1 + - name: RX_ST_L + description: RX_ST_L value. + bit_offset: 6 + bit_size: 1 + - name: RX_ST_H + description: RX_ST_H value. + bit_offset: 7 + bit_size: 1 +fieldset/PORT_CC: + description: CC1 port control register. + bit_size: 16 + fields: + - name: PA_CC_AI + description: CC port comparator analog input. + bit_offset: 0 + bit_size: 1 + # new in usbpd_l1.yaml + - name: CC_PD + description: CC port pull-down current. + bit_offset: 1 + bit_size: 1 + - name: CC_PU + description: CC port pull-up current. + bit_offset: 2 + bit_size: 2 + enum: PORT_CC_PU + - name: CC_LVE + description: CC port level 0 voltage. + bit_offset: 4 + bit_size: 1 + - name: CC_CE + description: CC port comparator enable. + bit_offset: 5 + bit_size: 3 + enum: PORT_CC_CE +fieldset/STATUS: + description: PD interrupt flag register. + bit_size: 8 + fields: + - name: BMC_AUX + description: BMC_AUX value. + bit_offset: 0 + bit_size: 2 + enum: BMC_AUX + - name: BUF_ERR + description: BUF_ERR value. + bit_offset: 2 + bit_size: 1 + - name: IF_RX_BIT + description: IF_RX_BIT value. + bit_offset: 3 + bit_size: 1 + - name: IF_RX_BYTE + description: IF_RX_BYTE value. + bit_offset: 4 + bit_size: 1 + - name: IF_RX_ACT + description: IF_RX_ACT value. + bit_offset: 5 + bit_size: 1 + - name: IF_RX_RESET + description: IF_RX_RESET value. + bit_offset: 6 + bit_size: 1 + - name: IF_TX_END + description: IF_TX_END value. + bit_offset: 7 + bit_size: 1 +fieldset/TX_SEL: + description: SOP port selection register. + bit_size: 8 + fields: + - name: TX_SEL1 + description: TX_SEL1 value. + bit_offset: 0 + bit_size: 1 + - name: TX_SEL2 + description: TX_SEL2 value. + bit_offset: 2 + bit_size: 2 + - name: TX_SEL3 + description: TX_SEL3 value. + bit_offset: 4 + bit_size: 2 + - name: TX_SEL4 + description: TX_SEL4 value. + bit_offset: 6 + bit_size: 2 +enum/CC_SEL: + bit_size: 1 + variants: + - name: CC1 + description: Select CC1. + value: 0 + - name: CC2 + description: Select CC2. + value: 1 +enum/PORT_CC_CE: + bit_size: 3 + variants: + - name: Closed + description: Closed. + value: 0 + - name: V0_22 + description: 0.22V. + value: 2 + - name: V0_43 + description: 0.43V. + value: 3 + - name: V0_55 + description: 0.55V. + value: 4 + - name: V0_66 + description: 0.66V. + value: 5 + - name: V0_96 + description: 0.96V. + value: 6 + - name: V1_23 + description: 1.23V. + value: 7 +enum/PORT_CC_PU: + bit_size: 2 + variants: + - name: Closed + description: No pull up current. + value: 0 + - name: uA330 + description: 330uA. + value: 1 + - name: uA180 + description: 180uA. + value: 2 + - name: uA80 + description: 80uA. + value: 3 +enum/BMC_AUX: + bit_size: 2 + description: PD status after receive. # TODO: sending state is not included. + variants: + - name: NONE + description: BMC_AUX0 value. + value: 0 + - name: SOP0 + description: SOP, aka SOP0 + value: 1 + - name: SOP1 + description: SOP', aka SOP1 or Hard Reset + value: 2 + - name: SOP2 + description: SOP'', aka SOP2 or Cable Resed + value: 3 diff --git a/data/registers/usbpd_x0.yaml b/data/registers/usbpd_x0.yaml index 8f206ef..13d47dd 100644 --- a/data/registers/usbpd_x0.yaml +++ b/data/registers/usbpd_x0.yaml @@ -1,4 +1,4 @@ -block/USB_PD: +block/USBPD: description: USBPD configuration. items: - name: CONFIG @@ -30,7 +30,6 @@ block/USB_PD: description: DMA cache data register. byte_offset: 8 bit_size: 8 - fieldset: DATA_BUF - name: STATUS description: PD interrupt flag register. byte_offset: 9 @@ -55,7 +54,6 @@ block/USB_PD: description: PD buffer start address register. byte_offset: 16 bit_size: 16 - fieldset: DMA fieldset/BMC_BYTE_CNT: description: Byte counter. bit_size: 16 @@ -84,6 +82,10 @@ fieldset/CONFIG: description: PD interrupt enable register. bit_size: 16 fields: + - name: PD_FILT_EN + description: PD Filter Enable. + bit_offset: 0 + bit_size: 1 - name: PD_ALL_CLR description: PD ITClear. bit_offset: 1 @@ -153,22 +155,6 @@ fieldset/CONTROL: description: BMC_BYTE_HI value. bit_offset: 7 bit_size: 1 -fieldset/DATA_BUF: - description: DMA cache data register. - bit_size: 8 - fields: - - name: DATA_BUF - description: DATA_BUF value. - bit_offset: 0 - bit_size: 8 -fieldset/DMA: - description: PD buffer start address register. - bit_size: 16 - fields: - - name: USBPD_DMA_ADDR - description: USBPD_DMA_ADDR value. - bit_offset: 0 - bit_size: 16 fieldset/PORT_CC: description: CC1 port control register. bit_size: 16 @@ -199,6 +185,7 @@ fieldset/STATUS: description: BMC_AUX value. bit_offset: 0 bit_size: 2 + enum: BMC_AUX - name: BUF_ERR description: BUF_ERR value. bit_offset: 2 @@ -291,3 +278,19 @@ enum/PORT_CC_PU: - name: uA80 description: 80uA. value: 3 +enum/BMC_AUX: + bit_size: 2 + description: PD status after receive. # TODO: sending state is not included. + variants: + - name: NONE + description: BMC_AUX0 value. + value: 0 + - name: SOP0 + description: SOP, aka SOP0 + value: 1 + - name: SOP1 + description: SOP', aka SOP1 or Hard Reset + value: 2 + - name: SOP2 + description: SOP'', aka SOP2 or Cable Resed + value: 3 diff --git a/transforms/USBPD.yaml b/transforms/USBPD.yaml index 7a46197..0d11de8 100644 --- a/transforms/USBPD.yaml +++ b/transforms/USBPD.yaml @@ -10,14 +10,14 @@ transforms: from: PORT_CC\d_CC_PU to: PORT_CC_PU check: Layout - - !MergeFieldsets - from: PORT_CC\d - to: PORT_CC - - !MergeEnums - from: PORT_CC\d_CC_CE - to: PORT_CC_CE - check: Layout - - !MergeEnums - from: PORT_CC\d_CC_PU - to: PORT_CC_PU - check: Layout +# - !MergeFieldsets +# from: PORT_CC\d +# to: PORT_CC +# - !MergeEnums +# from: PORT_CC\d_CC_CE +# to: PORT_CC_CE +# check: Layout +# - !MergeEnums +# from: PORT_CC\d_CC_PU +# to: PORT_CC_PU +# check: Layout