From 4fe34a1a0414c0c11a478b86d27fea349e373241 Mon Sep 17 00:00:00 2001 From: Andelf Date: Sun, 19 May 2024 13:36:03 +0800 Subject: [PATCH 1/4] feat: USBFS for L1 --- data/family/CH32L1.yaml | 24 ++ data/registers/usb_l1fs.yaml | 551 +++++++++++++++++++++++++++++++++++ 2 files changed, 575 insertions(+) create mode 100644 data/registers/usb_l1fs.yaml diff --git a/data/family/CH32L1.yaml b/data/family/CH32L1.yaml index 18e28b7..71f85fd 100644 --- a/data/family/CH32L1.yaml +++ b/data/family/CH32L1.yaml @@ -768,3 +768,27 @@ pins: - { pin: "PB6", signal: "CC1" } - { pin: "PB7", signal: "CC2" } + +- name: USBFS + address: 0x50000000 + registers: + kind: usb + version: l1fs + block: USB + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: AHBPCENR + field: USBFSEN + reset: + register: AHBRSTR + field: USBFSRST + interrupts: + - signal: GLOBAL + interrupt: USBFS + - signal: WKUP + interrupt: USBFS_WKUP + pins: + - { pin: "PA11", signal: "DM" } + - { pin: "PA12", signal: "DP" } diff --git a/data/registers/usb_l1fs.yaml b/data/registers/usb_l1fs.yaml new file mode 100644 index 0000000..ece0e36 --- /dev/null +++ b/data/registers/usb_l1fs.yaml @@ -0,0 +1,551 @@ +# USBFS for CH32L103, USB 2.0 FS. +block/USB: + description: Universal serial bus FS register + items: + - name: CTRL + description: USB base control. + byte_offset: 0 + bit_size: 8 + fieldset: USB_BASE_CTRL + - name: INT_EN + description: USB interrupt enable. + byte_offset: 2 + bit_size: 8 + fieldset: USB_INT_EN + - name: DEV_AD + description: USB device address. + byte_offset: 3 + bit_size: 8 + fieldset: USB_DEV_AD + - name: MIS_ST + description: USB miscellaneous status. + byte_offset: 5 + access: Read + bit_size: 8 + fieldset: USB_MIS_ST + - name: INT_FG + description: USB interrupt flag. + byte_offset: 6 + bit_size: 8 + fieldset: USB_INT_FG + - name: INT_ST + description: USB interrupt status. + byte_offset: 7 + access: Read + bit_size: 8 + fieldset: USB_INT_ST + - name: RX_LEN + description: USB receiving length. + byte_offset: 8 + access: Read + bit_size: 16 + fieldset: USB_RX_LEN + +block/USBD: + description: Universal serial bus FS device register + extends: USB + items: + - name: UDEV_CTRL + description: USB device physical port control register. + byte_offset: 1 + bit_size: 8 + fieldset: UDEV_CTRL + - name: UEP4_1_MOD + description: endpoint 4/1 mode. + byte_offset: 12 + bit_size: 8 + fieldset: UEP_MOD + - name: UEP2_3_MOD + description: Endpoint 2/3 mode control register. + byte_offset: 13 + bit_size: 8 + fieldset: UEP_MOD + - name: UEP5_6_MOD + description: endpoint 5/6 mode. + byte_offset: 14 + bit_size: 8 + fieldset: UEP_MOD + - name: UEP7_MOD + description: endpoint 7 mode. + byte_offset: 15 + bit_size: 8 + fieldset: UEP7_MOD + - name: UEP_DMA + description: endpoint DMA buffer address. + byte_offset: 32 + array: + len: 8 + stride: 4 + fieldset: UEP_DMA + - name: UEP_T_LEN + description: endpoint transmit length. + byte_offset: 48 # 0x30 + array: + len: 8 + stride: 4 + fieldset: UEP_T_LEN + - name: UEP_CTRL + description: endpoint control. + byte_offset: 50 # 0x32 + bit_size: 8 + array: + len: 8 + stride: 4 + fieldset: UEP_CTRL + +block/USBH: + description: Universal serial bus FS host register + extends: USB + items: + - name: UHOST_CTRL + description: USB host physical port control register. + byte_offset: 1 + bit_size: 8 + fieldset: UHOST_CTRL + - name: EP_MOD + description: USB host endpoint mode control register. + byte_offset: 13 # 0xD + bit_size: 8 + fieldset: UH_EP_MOD + - name: RX_DMA + description: USB host receiving DMA buffer address. + byte_offset: 24 # 0x18 + bit_size: 16 + - name: TX_DMA + description: USB host transmittal DMA buffer address. + byte_offset: 28 # 0x1C + bit_size: 16 + - name: SETUP + description: USB host setup. + byte_offset: 54 # 0x36 + bit_size: 8 + fieldset: UH_SETUP + - name: EP_PID + description: USB host endpoint PID. + byte_offset: 56 # 0x38 + bit_size: 8 + fieldset: UH_EP_PID + - name: RX_CTRL + description: USB host receiving control. + byte_offset: 58 # 0x3A + bit_size: 8 + fieldset: UH_RX_CTRL + - name: TX_LEN + description: USB host transmittal length. + byte_offset: 0x3C + bit_size: 16 + - name: TX_CTRL + description: USB host transmittal control. + byte_offset: 62 # 0x3E + bit_size: 8 + fieldset: UH_TX_CTRL + +# ------ +# fields + +fieldset/USB_BASE_CTRL: + description: USB base control. + bit_size: 8 + fields: + - name: DMA_EN + description: DMA enable and DMA interrupt enable for USB. + bit_offset: 0 + bit_size: 1 + - name: CLR_ALL + description: force clear FIFO and count of USB. + bit_offset: 1 + bit_size: 1 + - name: RESET_SIE + description: force reset USB SIE, need software clear. + bit_offset: 2 + bit_size: 1 + - name: INT_BUSY + description: enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid. + bit_offset: 3 + bit_size: 1 + - name: SYS_CTRL + description: USB device enable and internal pullup resistance enable. + bit_offset: 4 + bit_size: 2 + - name: DEV_PU_EN + description: USB device internal pullup resistance enable. + bit_offset: 5 + bit_size: 1 + - name: LOW_SPEED + description: "enable USB low speed: 0=12Mbps, 1=1.5Mbps." + bit_offset: 6 + bit_size: 1 + - name: HOST_MODE + description: "enable USB host mode: 0=device mode, 1=host mode." + bit_offset: 7 + bit_size: 1 +fieldset/USB_INT_EN: + description: USB interrupt enable. + bit_size: 8 + fields: + - name: BUS_RST + description: enable interrupt for USB bus reset event for USB device mode. + bit_offset: 0 + bit_size: 1 + - name: DETECT + description: enable interrupt for USB device detected event for USB host mode. + bit_offset: 0 + bit_size: 1 + - name: TRANSFER + description: enable interrupt for USB transfer completion. + bit_offset: 1 + bit_size: 1 + - name: SUSPEND + description: enable interrupt for USB suspend or resume event. + bit_offset: 2 + bit_size: 1 + - name: HST_SOF + description: enable interrupt for host SOF timer action for USB host mode. + bit_offset: 3 + bit_size: 1 + - name: FIFO_OV + description: enable interrupt for FIFO overflow. + bit_offset: 4 + bit_size: 1 + - name: ONE_WIRE + description: USB one wire mode enable + bit_offset: 5 + bit_size: 1 + - name: DEV_NAK + description: enable interrupt for NAK responded for USB device mode. + bit_offset: 6 + bit_size: 1 +fieldset/USB_DEV_AD: + description: USB device address. + bit_size: 8 + fields: + - name: MASK_USB_ADDR + description: bit mask for USB device address. + bit_offset: 0 + bit_size: 7 + - name: UDA_GP_BIT + description: general purpose bit. + bit_offset: 7 + bit_size: 1 +fieldset/USB_MIS_ST: + description: USB miscellaneous status. + bit_size: 8 + fields: + - name: DEV_ATTACH + description: RO, indicate device attached status on USB host. + bit_offset: 0 + bit_size: 1 + - name: DM_LEVEL + description: RO, indicate UDM level saved at device attached to USB host. + bit_offset: 1 + bit_size: 1 + - name: SUSPEND + description: RO, indicate USB suspend status. + bit_offset: 2 + bit_size: 1 + - name: BUS_RESET + description: RO, indicate USB bus reset status. + bit_offset: 3 + bit_size: 1 + - name: R_FIFO_RDY + description: RO, indicate USB receiving FIFO ready status (not empty). + bit_offset: 4 + bit_size: 1 + - name: SIE_FREE + description: RO, indicate USB SIE free status. + bit_offset: 5 + bit_size: 1 + - name: SOF_ACT + description: RO, indicate host SOF timer action status for USB host. + bit_offset: 6 + bit_size: 1 + - name: SOF_PRES + description: RO, indicate host SOF timer presage status. + bit_offset: 7 + bit_size: 1 +fieldset/USB_INT_FG: + description: USB interrupt flag. + bit_size: 8 + fields: + - name: BUS_RST + description: bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + bit_offset: 0 + bit_size: 1 + - name: DETECT + description: device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear. + bit_offset: 0 + bit_size: 1 + - name: TRANSFER + description: USB transfer completion interrupt flag, direct bit address clear or write 1 to clear. + bit_offset: 1 + bit_size: 1 + - name: SUSPEND + description: USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear. + bit_offset: 2 + bit_size: 1 + - name: HST_SOF + description: host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear. + bit_offset: 3 + bit_size: 1 + - name: FIFO_OV + description: FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear. + bit_offset: 4 + bit_size: 1 + - name: SIE_FREE + description: RO, indicate USB SIE free status. + bit_offset: 5 + bit_size: 1 + - name: TOG_OK + description: RO, indicate current USB transfer toggle is OK. + bit_offset: 6 + bit_size: 1 + - name: IS_NAK + description: RO, indicate current USB transfer is NAK received. + bit_offset: 7 + bit_size: 1 +fieldset/USB_INT_ST: + description: USB interrupt status. + bit_size: 8 + fields: + - name: MASK_H_RES + description: "RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode." + bit_offset: 0 + bit_size: 4 + - name: MASK_UIS_ENDP + description: "RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode." + bit_offset: 0 + bit_size: 4 + - name: MASK_TOKEN + description: RO, bit mask of current token PID code received for USB device mode. + bit_offset: 4 + bit_size: 2 + - name: TOG_OK + description: RO, indicate current USB transfer toggle is OK. + bit_offset: 6 + bit_size: 1 + - name: SETUP_ACK + description: RO, indicate setup packet received. + bit_offset: 7 + bit_size: 1 +fieldset/USB_RX_LEN: + description: USB receiving length. + bit_size: 16 + fields: + - name: RX_LEN + description: receiving length. + bit_offset: 0 + bit_size: 10 + +# USB Device starts +fieldset/UDEV_CTRL: + description: USB device physical port control register. + bit_size: 8 + fields: + - name: PORT_EN + description: USB device port enable. + bit_offset: 0 + bit_size: 1 + - name: GP_BIT + description: USB device port general purpose bit. + bit_offset: 1 + bit_size: 1 + - name: LOW_SPEED + description: USB device port low speed enable. + bit_offset: 2 + bit_size: 1 + - name: DM_PIN + description: USB device port UD- pin status. + bit_offset: 4 + bit_size: 1 + - name: DP_PIN + description: USB device port UD+ pin status. + bit_offset: 5 + bit_size: 1 + - name: PD_DIS + description: USB device port UD+/UD- pin internal pull-down resistor control. + bit_offset: 7 + bit_size: 1 +fieldset/UEP_MOD: + description: endpoint a/b mode. lower bits comes first + bit_size: 8 + fields: + - name: BUF_MOD + description: buffer mode of USB endpoint + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: TX_EN + description: enable USB endpoint 1 transmittal (IN). + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: RX_EN + description: enable USB endpoint 4 receiving (OUT). + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/UEP7_MOD: + description: endpoint 7 mode. + bit_size: 8 + fields: + - name: BUF_MOD + description: buffer mode of USB endpoint 7. + bit_offset: 0 + bit_size: 1 + - name: TX_EN + description: enable USB endpoint 7 transmittal (IN). + bit_offset: 2 + bit_size: 1 + - name: RX_EN + description: enable USB endpoint 7 receiving (OUT). + bit_offset: 3 + bit_size: 1 +fieldset/UEP_DMA: + description: endpoint DMA buffer address. + bit_size: 32 + fields: + - name: ADDR + description: DMA buffer address of USB endpoint X. + bit_offset: 0 + bit_size: 15 +fieldset/UEP_T_LEN: + description: endpoint transmit length. + bit_size: 32 + fields: + - name: HOST_PID3 + description: USB host PID[3] + bit_offset: 7 + bit_size: 1 + - name: TX_LEN + description: transmit length of USB endpoint X. The length varies with the endpoint type. + bit_offset: 0 + bit_size: 10 +fieldset/UEP_CTRL: + description: endpoint control. + bit_size: 8 + fields: + - name: MASK_T_RES + description: bit mask of handshake response type for USB endpoint X transmittal (IN). + bit_offset: 0 + bit_size: 2 + - name: T_TOG + description: "prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1." + bit_offset: 2 + bit_size: 2 + - name: T_AUTO_TOG + bit_offset: 3 + bit_size: 1 + - name: MASK_R_RES + description: bit mask of handshake response type for USB endpoint X receiving (OUT). + bit_offset: 8 + bit_size: 2 + - name: MASK_R_TOG + description: "expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1." + bit_offset: 10 + bit_size: 1 + - name: R_AUTO_TOG + bit_offset: 11 + bit_size: 1 + +# USB host +fieldset/UHOST_CTRL: + description: USB host physical port control register. + bit_size: 8 + fields: + - name: PORT_EN + description: USB host port enable. + bit_offset: 0 + bit_size: 1 + - name: BUS_RST + description: USB host port bus reset. + bit_offset: 1 + bit_size: 1 + - name: LOW_SPEED + description: USB host port low speed enable. + bit_offset: 2 + bit_size: 1 + - name: DM_PIN + description: Current UD- pin status. + bit_offset: 4 + bit_size: 1 + - name: DP_PIN + description: Current UD+ pin status. + bit_offset: 5 + bit_size: 1 + - name: PD_DIS + description: Internal pull-down resistor control for USB host port UD+/UD- pins. + bit_offset: 7 + bit_size: 1 +fieldset/UH_EP_MOD: + description: USB host endpoint mode control register. + bit_size: 8 + fields: + - name: RBUF_MOD + bit_offset: 0 + bit_size: 1 + - name: RX_EN + bit_offset: 3 + bit_size: 1 + - name: TBUF_MOD + bit_offset: 4 + bit_size: 1 + - name: TX_EN + bit_offset: 6 + bit_size: 1 +fieldset/UH_SETUP: + description: USB host setup. + bit_size: 16 + fields: + - name: SOF_EN + description: SOF packet en + bit_offset: 2 + bit_size: 1 + - name: PRE_PID_EN + description: pre pid en + bit_offset: 10 + bit_size: 1 +fieldset/UH_EP_PID: + description: USB host endpoint PID. + bit_size: 8 + fields: + - name: MASK_ENDP + description: endpoint PID + bit_offset: 0 + bit_size: 4 + - name: MASK_TOKEN + description: token PID + bit_offset: 4 + bit_size: 4 +fieldset/UH_RX_CTRL: + description: USB host receiving control. + bit_size: 8 + fields: + - name: R_RES + bit_offset: 0 + bit_size: 1 + - name: R_TOG + bit_offset: 2 + bit_size: 1 + - name: R_AUTO_TOG + description: auto toggle + bit_offset: 3 + bit_size: 1 +fieldset/UH_TX_CTRL: + description: USB host transmittal control. + bit_size: 8 + fields: + - name: T_RES + bit_offset: 0 + bit_size: 1 + - name: T_TOG + bit_offset: 2 + bit_size: 1 + - name: T_AUTO_TOG + bit_offset: 3 + bit_size: 1 From 522ec12789f9102bb0da942231a0ff513d946885 Mon Sep 17 00:00:00 2001 From: Andelf Date: Mon, 20 May 2024 00:12:17 +0800 Subject: [PATCH 2/4] feat: CH641 --- data/chips/CH641.yaml | 2 +- data/family/CH32L1.yaml | 11 + data/family/CH641.yaml | 286 ++++++++++++++++++++++++++ data/interrupts/CH641.yaml | 8 +- data/registers/afio_ch641.yaml | 48 +++++ data/registers/gpio_v0.yaml | 2 +- data/registers/gpio_v3.yaml | 2 +- data/registers/gpio_x0.yaml | 2 +- data/registers/opa_l1.yaml | 236 +++++++++++++++++++++ data/registers/rcc_ch641.yaml | 362 +++++++++++++++++++++++++++++++++ 10 files changed, 951 insertions(+), 8 deletions(-) create mode 100644 data/family/CH641.yaml create mode 100644 data/registers/afio_ch641.yaml create mode 100644 data/registers/opa_l1.yaml create mode 100644 data/registers/rcc_ch641.yaml diff --git a/data/chips/CH641.yaml b/data/chips/CH641.yaml index 2456591..7b14fb6 100644 --- a/data/chips/CH641.yaml +++ b/data/chips/CH641.yaml @@ -36,7 +36,7 @@ cores: - name: qingke-v2a peripherals: include_peripherals: - - "../family/CH32V0.yaml" + - "../family/CH641.yaml" include_dma_channels: DMA1: "../dma/CH641.yaml" include_interrupts: "../interrupts/CH641.yaml" diff --git a/data/family/CH32L1.yaml b/data/family/CH32L1.yaml index 71f85fd..1979b62 100644 --- a/data/family/CH32L1.yaml +++ b/data/family/CH32L1.yaml @@ -792,3 +792,14 @@ pins: - { pin: "PA11", signal: "DM" } - { pin: "PA12", signal: "DP" } + +- name: OPA + address: 0x40026000 + registers: + kind: opa + version: l1 + block: OPA + interrupts: + - signal: GLOBAL + interrupt: OPA + pins: diff --git a/data/family/CH641.yaml b/data/family/CH641.yaml new file mode 100644 index 0000000..3051d3b --- /dev/null +++ b/data/family/CH641.yaml @@ -0,0 +1,286 @@ +# CH641 is almost the same as CH32V003 + +- name: PFIC + address: 0xE000E000 + registers: + kind: pfic + version: rv2 + block: PFIC +- name: SYSTICK + address: 0xE000F000 + registers: + kind: systick + version: rv2 + block: SYSTICK + # SysTick interrupt handling is moved to qingke-rt as it's a core feature + # interrupts: + # - signal: GLOBAL + # interrupt: SYSTICK +- name: FLASH + address: 0x40022000 + registers: + kind: flash + version: v0 + block: FLASH +- name: EXTI + address: 0x40010400 + registers: + kind: exti + version: common + block: EXTI + interrupts: + - signal: EXTI0 + interrupt: EXTI7_0 + - signal: EXTI8 + interrupt: EXTI15_8 + +- name: RCC + address: 0x40021000 + registers: + kind: rcc + version: ch641 + block: RCC + pins: + - pin: PB7 + signal: MCO + +- name: DMA1 + address: 0x40020000 + registers: + kind: dma + version: v1 + block: DMA + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: AHBPCENR + field: DMA1EN + interrupts: + - signal: CH1 + interrupt: DMA1_Channel1 + - signal: CH2 + interrupt: DMA1_Channel2 + - signal: CH3 + interrupt: DMA1_Channel3 + - signal: CH4 + interrupt: DMA1_Channel4 + - signal: CH5 + interrupt: DMA1_Channel5 + - signal: CH6 + interrupt: DMA1_Channel6 + - signal: CH7 + interrupt: DMA1_Channel7 + +- name: AFIO + address: 0x40010000 + registers: + kind: afio + version: ch641 + block: AFIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: AFIOEN + reset: + register: APB2PRSTR + field: AFIORST + +- name: GPIOA + address: 0x40010800 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPAEN + reset: + register: APB2PRSTR + field: IOPARST +- name: GPIOB + address: 0x40010C00 + registers: + kind: gpio + version: v3 + block: GPIO + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: IOPBEN + reset: + register: APB2PRSTR + field: IOPBRST + +# TIM use hclk as bus clock + +- name: TIM1 + address: 0x40012C00 + registers: + kind: timer + version: v3 + block: ADTM + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: APB2PCENR + field: TIM1EN + reset: + register: APB2PRSTR + field: TIM1RST + remap: + register: PCFR1 + field: TIM1_RM + interrupts: + - signal: UP + interrupt: TIM1_UP + - signal: CC + interrupt: TIM1_CC + - signal: COM + interrupt: TIM1_TRG_COM + - signal: TRG + interrupt: TIM1_TRG_COM + - signal: BRK + interrupt: TIM1_BRK + pins: + +- name: TIM2 + address: 0x40000000 + registers: + kind: timer + version: v3 + block: GPTM + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: APB1PCENR + field: TIM2EN + reset: + register: APB1PRSTR + field: TIM2RST + remap: + register: PCFR1 + field: TIM2_RM + interrupts: + - signal: UP + interrupt: TIM2 + - signal: CC + interrupt: TIM2 + - signal: TRG + interrupt: TIM2 + pins: + +- name: USART1 + address: 0x40013800 + registers: + kind: usart + version: common + block: USART + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: APB2PCENR + field: USART1EN + reset: + register: APB2PRSTR + field: USART1RST + remap: + register: PCFR1 + field: USART1_RM + interrupts: + - signal: GLOBAL + interrupt: USART1 + pins: + +- name: I2C1 + address: 0x40005400 + registers: + kind: i2c + # No SMBUS registers, others are the same as v3 + # No idea if RTR is available + version: v0 + block: I2C + rcc: + bus_clock: HCLK + kernel_clock: HCLK + enable: + register: APB1PCENR + field: I2C1EN + reset: + register: APB1PRSTR + field: I2C1RST + remap: + register: PCFR1 + field: I2C1_RM + interrupts: + - signal: EV + interrupt: I2C1_EV + - signal: ER + interrupt: I2C1_ER + pins: + +- name: ADC1 + address: 0x40012400 + registers: + kind: adc + version: v0 + block: ADC + rcc: + bus_clock: PCLK2 + kernel_clock: PCLK2 + enable: + register: APB2PCENR + field: ADC1EN + reset: + register: APB2PRSTR + field: ADC1RST + interrupts: + - signal: GLOBAL + interrupt: ADC + pins: + - pin: PA6 + signal: IN0 + - pin: PA7 + signal: IN1 + - pin: PA8 + signal: IN2 + - pin: PA10 + signal: IN3 + - pin: PA11 + signal: IN4 + - pin: PA12 + signal: IN5 + - pin: PA13 + signal: IN6 + - pin: PB7 + signal: IN7 + # TODO: ISP pin, IN8 + - pin: PB8 + signal: IN9 + - pin: PB0 + signal: IN10 + - pin: PB1 + signal: IN11 + - pin: PA0 + signal: IN12 + - pin: PA1 + signal: IN13 + - pin: PB9 + signal: IN14 + - pin: PA15 + signal: ETR + remap: 1 + - pin: PA4 + signal: ETR + remap: 0 + diff --git a/data/interrupts/CH641.yaml b/data/interrupts/CH641.yaml index 1ae093f..55346bd 100644 --- a/data/interrupts/CH641.yaml +++ b/data/interrupts/CH641.yaml @@ -35,13 +35,13 @@ USART1: 32 # 33 - EXTI Line\[15:8\] interrupt EXTI15_8: 33 # 34 - TIM1 Break interrupt -TIM1BRK: 34 +TIM1_BRK: 34 # 35 - TIM1 Update interrupt -TIM1UP: 35 +TIM1_UP: 35 # 36 - TIM1 Trigger and Commutation interrupts -TIM1TRG: 36 +TIM1_TRG_COM: 36 # 37 - TIM1 Capture Compare interrupt -TIM1CC: 37 +TIM1_CC: 37 # 38 - TIM2 global interrupt TIM2: 38 # 39 - USBPD global interrupt diff --git a/data/registers/afio_ch641.yaml b/data/registers/afio_ch641.yaml new file mode 100644 index 0000000..63afe68 --- /dev/null +++ b/data/registers/afio_ch641.yaml @@ -0,0 +1,48 @@ +block/AFIO: + description: Alternate function I/O. + items: + - name: PCFR1 + description: AF remap and debug I/O configuration register (AFIO_PCFR1). + byte_offset: 4 + fieldset: PCFR1 + - name: EXTICR + description: External interrupt configuration register (AFIO_EXTICR). + byte_offset: 8 + fieldset: EXTICR +fieldset/EXTICR: + description: External interrupt configuration register (AFIO_EXTICR). + fields: + - name: EXTI + description: EXTI0 configuration. + bit_offset: 0 + bit_size: 1 + array: + len: 16 + stride: 1 +fieldset/PCFR1: + description: AF remap and debug I/O configuration register (AFIO_PCFR1). + fields: + - name: I2C1_RM + description: I2C1 remapping. + bit_offset: 0 + bit_size: 2 + - name: USART1_RM + description: USART1 remapping. + bit_offset: 2 + bit_size: 3 + - name: TIM1_RM + description: TIM1 remapping. + bit_offset: 6 + bit_size: 1 + - name: TIM2_RM + description: TIM2 remapping. + bit_offset: 8 + bit_size: 2 + - name: ADC_ETRGREG_RM + description: ADC External trigger injected conversion remapping. + bit_offset: 18 + bit_size: 1 + - name: SWCFG + description: Serial wire JTAG configuration. + bit_offset: 24 + bit_size: 3 diff --git a/data/registers/gpio_v0.yaml b/data/registers/gpio_v0.yaml index 307b977..7693d1c 100644 --- a/data/registers/gpio_v0.yaml +++ b/data/registers/gpio_v0.yaml @@ -1,5 +1,5 @@ block/GPIO: - description: General purpose I/O. + description: General purpose I/O. 8 lines per port. items: - name: CFGLR description: Port configuration register low (GPIOn_CFGLR). diff --git a/data/registers/gpio_v3.yaml b/data/registers/gpio_v3.yaml index be2ae03..b73680f 100644 --- a/data/registers/gpio_v3.yaml +++ b/data/registers/gpio_v3.yaml @@ -1,5 +1,5 @@ block/GPIO: - description: General purpose I/O. + description: General purpose I/O. 16 lines per port. items: - name: CFGLR description: Port configuration register low (GPIOn_CFGLR). diff --git a/data/registers/gpio_x0.yaml b/data/registers/gpio_x0.yaml index 50ee174..4513952 100644 --- a/data/registers/gpio_x0.yaml +++ b/data/registers/gpio_x0.yaml @@ -1,5 +1,5 @@ block/GPIO: - description: General purpose I/O. + description: General purpose I/O. 24 lines per port. items: - name: CFGLR description: Port configuration register low (GPIOn_CFGLR). diff --git a/data/registers/opa_l1.yaml b/data/registers/opa_l1.yaml new file mode 100644 index 0000000..eaa01d7 --- /dev/null +++ b/data/registers/opa_l1.yaml @@ -0,0 +1,236 @@ +block/OPA: + description: OPA configuration. + items: + - name: CFGR1 + description: OPA configuration 1. + byte_offset: 0 + bit_size: 16 + fieldset: CFGR1 + - name: CFGR2 + description: OPA configuration 2. + byte_offset: 2 + bit_size: 16 + fieldset: CFGR2 + - name: CTLR1 + description: OPA control register 1. + byte_offset: 4 + fieldset: CTLR1 + - name: CTLR2 + description: OPA control register 2. + byte_offset: 8 + fieldset: CTLR2 + - name: OPA_KEY + description: OPA unlockkey. + byte_offset: 12 + fieldset: OPA_KEY + - name: CMP_KEY + description: CMP unlockkey. + byte_offset: 16 + fieldset: CMP_KEY + - name: POLL_KEY + description: polling unlockkey. + byte_offset: 20 + fieldset: POLL_KEY +fieldset/CFGR1: + description: OPA configuration 1. + bit_size: 16 + fields: + - name: POLL_EN + description: OPA1 enable positive polling. + bit_offset: 0 + bit_size: 1 + - name: BKIN_EN + description: OPA1 break function enable. + bit_offset: 2 + bit_size: 1 + - name: RST_EN + description: OPA1 reset enable. + bit_offset: 4 + bit_size: 1 + - name: POLL_LOCK + description: POLL LOCK. + bit_offset: 7 + bit_size: 1 + - name: IE_OUT + description: OPA1 interrupt enable. + bit_offset: 8 + bit_size: 1 + - name: IE_CNT + description: OPA interrupt enable at the end of polling interval. + bit_offset: 10 + bit_size: 1 + - name: NMI_EN + description: OPA connection NMI interrupt enable. + bit_offset: 11 + bit_size: 1 + - name: IF_OUT + description: OPA1 output interrupt. + bit_offset: 12 + bit_size: 1 + - name: IF_CNT + description: OPA interrupt flag at the end of polling interval. + bit_offset: 14 + bit_size: 1 +fieldset/CFGR2: + description: OPA configuration 2. + bit_size: 16 + fields: + - name: POLL_VLU + description: OPA1 polling interval. + bit_offset: 0 + bit_size: 9 + - name: POLL1_NUM + description: OPA1 polling the number of positive ends. + bit_offset: 9 + bit_size: 3 +fieldset/CMP_KEY: + description: CMP unlockkey. + fields: + - name: CMP_KEY + description: CMP unlockkey. + bit_offset: 0 + bit_size: 32 +fieldset/CTLR1: + description: OPA control register 1. + fields: + - name: EN1 + description: OPA1 enable. + bit_offset: 0 + bit_size: 1 + - name: MODE1 + description: OPA1 output channel selection. + bit_offset: 1 + bit_size: 3 + - name: PSEL1 + description: OPA1 forward input selection. + bit_offset: 4 + bit_size: 3 + - name: FB_EN1 + description: OPA1 internal feedback resistance enable. + bit_offset: 7 + bit_size: 1 + - name: NSEL1 + description: OPA1 negative end channel selection with PGA gain selection. + bit_offset: 8 + bit_size: 4 + - name: LP1 + description: OPA1 low-power mode selection. + bit_offset: 12 + bit_size: 1 + - name: INTRIMP + description: OPA1 high-level offset voltage value polarity selection. + bit_offset: 16 + bit_size: 1 + - name: ITRIMP + description: OPA1 high-level offset voltage value selection. + bit_offset: 17 + bit_size: 5 + - name: INTRIMN + description: OPA1 low-level offset voltage value polarity selection. + bit_offset: 24 + bit_size: 1 + - name: ITRIMN + description: OPA1 low-level offset voltage value selection. + bit_offset: 25 + bit_size: 5 + - name: OPA_LOCK + description: OPA lock. + bit_offset: 31 + bit_size: 1 +fieldset/CTLR2: + description: OPA control register 2. + fields: + - name: EN1 + description: CMP1 enable. + bit_offset: 0 + bit_size: 1 + - name: MODE1 + description: CMP1 Output channel selection. + bit_offset: 1 + bit_size: 2 + - name: NSEL1 + description: CMP1 negative input selection. + bit_offset: 3 + bit_size: 1 + - name: PSEL1 + description: CMP1 forward input selection. + bit_offset: 4 + bit_size: 1 + - name: HYEN1 + description: CMP1 hysteresis function selection. + bit_offset: 5 + bit_size: 1 + - name: LP1 + description: CMP1 low-power switch. + bit_offset: 6 + bit_size: 1 + - name: EN2 + description: CMP2 enable. + bit_offset: 8 + bit_size: 1 + - name: MODE2 + description: CMP2 Output channel selection. + bit_offset: 9 + bit_size: 2 + - name: NSE2L + description: CMP2 negative input selection. + bit_offset: 11 + bit_size: 1 + - name: PSEL2 + description: CMP2 forward input selection. + bit_offset: 12 + bit_size: 1 + - name: HYEN2 + description: CMP2 hysteresis function selection. + bit_offset: 13 + bit_size: 1 + - name: LP2 + description: CMP2 low-power switch. + bit_offset: 14 + bit_size: 1 + - name: EN3 + description: CMP3 enable. + bit_offset: 16 + bit_size: 1 + - name: MODE3 + description: CMP3 Output channel selection. + bit_offset: 17 + bit_size: 2 + - name: NSEL3 + description: CMP3 negative input selection. + bit_offset: 19 + bit_size: 1 + - name: PSEL3 + description: CMP3 forward input selection. + bit_offset: 20 + bit_size: 1 + - name: HYEN3 + description: CMP3 hysteresis function selection. + bit_offset: 21 + bit_size: 1 + - name: LP3 + description: CMP3 low-power switch. + bit_offset: 22 + bit_size: 1 + - name: WKUP_MD + description: CMP wake-up signal mode selection. + bit_offset: 24 + bit_size: 2 + - name: CMP_LOCK + description: CMP lock. + bit_offset: 31 + bit_size: 1 +fieldset/OPA_KEY: + description: OPA unlockkey. + fields: + - name: OPA_KEY + description: OPA unlockkey. + bit_offset: 0 + bit_size: 32 +fieldset/POLL_KEY: + description: polling unlockkey. + fields: + - name: POLL_KEY + description: polling unlockkey. + bit_offset: 0 + bit_size: 32 diff --git a/data/registers/rcc_ch641.yaml b/data/registers/rcc_ch641.yaml new file mode 100644 index 0000000..368c152 --- /dev/null +++ b/data/registers/rcc_ch641.yaml @@ -0,0 +1,362 @@ +block/RCC: + description: Reset and clock control. + items: + - name: CTLR + description: Clock control register. + byte_offset: 0 + fieldset: CTLR + - name: CFGR0 + description: Clock configuration register (RCC_CFGR0). + byte_offset: 4 + fieldset: CFGR0 + - name: INTR + description: Clock interrupt register (RCC_INTR). + byte_offset: 8 + fieldset: INTR + - name: APB2PRSTR + description: APB2 peripheral reset register (RCC_APB2PRSTR). + byte_offset: 12 + fieldset: APB2PRSTR + - name: APB1PRSTR + description: APB1 peripheral reset register (RCC_APB1PRSTR). + byte_offset: 16 + fieldset: APB1PRSTR + - name: AHBPCENR + description: AHB Peripheral Clock enable register (RCC_AHBPCENR). + byte_offset: 20 + fieldset: AHBPCENR + - name: APB2PCENR + description: APB2 peripheral clock enable register (RCC_APB2PCENR). + byte_offset: 24 + fieldset: APB2PCENR + - name: APB1PCENR + description: APB1 peripheral clock enable register (RCC_APB1PCENR). + byte_offset: 28 + fieldset: APB1PCENR + - name: RSTSCKR + description: Control/status register (RCC_RSTSCKR). + byte_offset: 36 + fieldset: RSTSCKR +fieldset/AHBPCENR: + description: AHB Peripheral Clock enable register (RCC_AHBPCENR). + fields: + - name: DMA1EN + description: DMA clock enable. + bit_offset: 0 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable. + bit_offset: 2 + bit_size: 1 + - name: USBPDEN + description: USBPD interface clock enable. + bit_offset: 7 + bit_size: 1 +fieldset/APB1PCENR: + description: APB1 peripheral clock enable register (RCC_APB1PCENR). + fields: + - name: TIM2EN + description: Timer 2 clock enable. + bit_offset: 0 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable. + bit_offset: 11 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable. + bit_offset: 21 + bit_size: 1 + - name: PWREN + description: Power interface clock enable. + bit_offset: 28 + bit_size: 1 +fieldset/APB1PRSTR: + description: APB1 peripheral reset register (RCC_APB1PRSTR). + fields: + - name: TIM2RST + description: TIM2 reset. + bit_offset: 0 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset. + bit_offset: 11 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset. + bit_offset: 21 + bit_size: 1 + - name: PWRRST + description: Power interface reset. + bit_offset: 28 + bit_size: 1 +fieldset/APB2PCENR: + description: APB2 peripheral clock enable register (RCC_APB2PCENR). + fields: + - name: AFIOEN + description: Alternate function I/O clock enable. + bit_offset: 0 + bit_size: 1 + - name: IOPAEN + description: I/O port A clock enable. + bit_offset: 2 + bit_size: 1 + - name: IOPBEN + description: I/O port B clock enable. + bit_offset: 3 + bit_size: 1 + - name: ADC1EN + description: ADC1 interface clock enable. + bit_offset: 9 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable. + bit_offset: 11 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable. + bit_offset: 14 + bit_size: 1 +fieldset/APB2PRSTR: + description: APB2 peripheral reset register (RCC_APB2PRSTR). + fields: + - name: AFIORST + description: Alternate function I/O reset. + bit_offset: 0 + bit_size: 1 + - name: IOPARST + description: IO port A reset. + bit_offset: 2 + bit_size: 1 + - name: IOPBRST + description: IO port B reset. + bit_offset: 3 + bit_size: 1 + - name: ADC1RST + description: ADC 1 interface reset. + bit_offset: 9 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset. + bit_offset: 11 + bit_size: 1 + - name: USART1RST + description: USART1 reset. + bit_offset: 14 + bit_size: 1 +fieldset/CFGR0: + description: Clock configuration register (RCC_CFGR0). + fields: + - name: SW + description: System clock Switch. + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status. + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler. + bit_offset: 4 + bit_size: 4 + enum: HPRE + # split ADCPRE to PPRE2 and ADCPRE + - name: PPRE2 + description: APB High speed prescaler (APB2). + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler. + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: MCO + description: Microcontroller clock output. + bit_offset: 24 + bit_size: 3 + enum: MCO +fieldset/CTLR: + description: Clock control register. + fields: + - name: HSION + description: Internal High Speed clock enable. + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag. + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming. + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration. + bit_offset: 8 + bit_size: 8 + - name: PLLON + description: PLL enable. + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag. + bit_offset: 25 + bit_size: 1 +fieldset/INTR: + description: Clock interrupt register (RCC_INTR). + fields: + - name: PLLRDYF + description: PLL Ready Interrupt flag. + bit_offset: 4 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable. + bit_offset: 12 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear. + bit_offset: 20 + bit_size: 1 +fieldset/RSTSCKR: + description: Control/status register (RCC_RSTSCKR). + fields: + - name: RMVF + description: Remove reset flag. + bit_offset: 24 + bit_size: 1 + - name: USBPDRSTF + description: Remove reset flag. + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag. + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag. + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag. + bit_offset: 28 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag. + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag. + bit_offset: 31 + bit_size: 1 +enum/SW: + description: System clock Switch. + bit_size: 2 + variants: + - name: HSI + description: HSI selected as system clock. + value: 0b00 + - name: PLL + description: PLL selected as system clock. + value: 0b10 +enum/HPRE: + bit_size: 4 + variants: + - name: DIV1 + description: SYSCLK not divided. + value: 0b0000 + - name: DIV2 + description: SYSCLK divided by 2. + value: 0b0001 + - name: DIV3 + description: SYSCLK divided by 3. + value: 0b0010 + - name: DIV4 + description: SYSCLK divided by 4. + value: 0b0011 + - name: DIV5 + description: SYSCLK divided by 5. + value: 0b0100 + - name: DIV6 + description: SYSCLK divided by 6. + value: 0b0101 + - name: DIV7 + description: SYSCLK divided by 7. + value: 0b0110 + - name: DIV8 + description: SYSCLK divided by 8. + value: 0b0111 + - name: DIV2_ALT + description: SYSCLK divided by 2. + value: 0b1000 + - name: DIV4_ALT + description: SYSCLK divided by 4. + value: 0b1001 + - name: DIV8_ALT + description: SYSCLK divided by 8. + value: 0b1010 + - name: DIV16 + description: SYSCLK divided by 16. + value: 0b1011 + - name: DIV32 + description: SYSCLK divided by 32. + value: 0b1100 + - name: DIV64 + description: SYSCLK divided by 64. + value: 0b1101 + - name: DIV128 + description: SYSCLK divided by 128. + value: 0b1110 + - name: DIV256 + description: SYSCLK divided by 256. + value: 0b1111 +enum/PPRE: + bit_size: 3 + variants: + - name: DIV1 + description: HCLK not divided. + value: 0b000 + - name: DIV2 + description: HCLK divided by 2. + value: 0b100 + - name: DIV4 + description: HCLK divided by 4. + value: 0b101 + - name: DIV8 + description: HCLK divided by 8. + value: 0b110 + - name: DIV16 + description: HCLK divided by 16. + value: 0b111 +enum/ADCPRE: + bit_size: 2 + variants: + - name: DIV2 + description: PCLK2 divided by 2. + value: 0b00 + - name: DIV4 + description: PCLK2 divided by 4. + value: 0b01 + - name: DIV6 + description: PCLK2 divided by 6. + value: 0b10 + - name: DIV8 + description: PCLK2 divided by 8. + value: 0b11 +enum/MCO: + bit_size: 3 + variants: + - name: NOCLK + description: No clock output. + value: 0b000 + - name: SYSCLK + description: System clock selected. + value: 0b100 + - name: HSI + description: HSI clock selected. + value: 0b101 + - name: PLL + description: PLL clock selected. + value: 0b111 From 320f5f6e4d01f479c6586710550764e45860cb55 Mon Sep 17 00:00:00 2001 From: Andelf Date: Mon, 20 May 2024 00:12:42 +0800 Subject: [PATCH 3/4] feat: ch641 feature gate --- ch32-metapac-gen/res/build.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ch32-metapac-gen/res/build.rs b/ch32-metapac-gen/res/build.rs index c8a748b..39bab1b 100644 --- a/ch32-metapac-gen/res/build.rs +++ b/ch32-metapac-gen/res/build.rs @@ -29,12 +29,12 @@ fn main() { let chip_core_name = match env::vars() .map(|(a, _)| a) - .filter(|x| x.starts_with("CARGO_FEATURE_CH32")) + .filter(|x| x.starts_with("CARGO_FEATURE_CH32") || x.starts_with("CARGO_FEATURE_CH6")) .get_one() { Ok(x) => x, - Err(GetOneError::None) => panic!("No ch32xx Cargo feature enabled"), - Err(GetOneError::Multiple) => panic!("Multiple ch32xx Cargo features enabled"), + Err(GetOneError::None) => panic!("No ch32xx/ch6xx Cargo feature enabled"), + Err(GetOneError::Multiple) => panic!("Multiple ch32xx/ch6xx Cargo features enabled"), } .strip_prefix("CARGO_FEATURE_") .unwrap() From ac562c99ba7828a54b439c7347162bbc63b8b956 Mon Sep 17 00:00:00 2001 From: Andelf Date: Mon, 20 May 2024 00:23:15 +0800 Subject: [PATCH 4/4] fix: v0 periperal clk --- data/family/CH32V0.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/data/family/CH32V0.yaml b/data/family/CH32V0.yaml index 941b5e5..54f82b2 100644 --- a/data/family/CH32V0.yaml +++ b/data/family/CH32V0.yaml @@ -373,8 +373,8 @@ version: common block: USART rcc: - bus_clock: PCLK2 - kernel_clock: PCLK2 + bus_clock: HCLK + kernel_clock: HCLK enable: register: APB2PCENR field: USART1EN @@ -504,8 +504,8 @@ version: v0 block: SPI rcc: - bus_clock: PCLK2 - kernel_clock: PCLK2 + bus_clock: HCLK + kernel_clock: HCLK enable: register: APB2PCENR field: SPI1EN