diff --git a/templates/chisel/.scalafmt.conf b/templates/chisel/.scalafmt.conf index 2d9aedc..5bacc03 100644 --- a/templates/chisel/.scalafmt.conf +++ b/templates/chisel/.scalafmt.conf @@ -2,21 +2,19 @@ version = "3.7.15" runner.dialect = scala213 maxColumn = 120 -align = most -continuationIndent.defnSite = 2 +align.preset = most +indent.defnSite = 2 assumeStandardLibraryStripMargin = true docstrings.style = SpaceAsterisk lineEndings = preserve includeCurlyBraceInSelectChains = false danglingParentheses.preset = true -align.tokens."+" = [ -{ - code = ":" -} -] +align.tokens."+" = [{ +code = ":" +}] -newlines.beforeCurlyLambdaParams = never +newlines.beforeCurlyLambdaParams = "never" newlines.alwaysBeforeMultilineDef = false newlines.implicitParamListModifierForce = [before] diff --git a/templates/chisel/elaborator/src/GCD.scala b/templates/chisel/elaborator/src/GCD.scala index 8988d15..3b339e8 100644 --- a/templates/chisel/elaborator/src/GCD.scala +++ b/templates/chisel/elaborator/src/GCD.scala @@ -16,7 +16,7 @@ object GCDMain extends SerializableModuleElaborator { @main case class GCDParameterMain( - @arg(name = "width") width: Int, + @arg(name = "width") width: Int, @arg(name = "useAsyncReset") useAsyncReset: Boolean) { require(width > 0, "width must be a non-negative integer") require(chisel3.util.isPow2(width), "width must be a power of 2") diff --git a/templates/chisel/elaborator/src/GCDTestBench.scala b/templates/chisel/elaborator/src/GCDTestBench.scala index abd4540..4d5e7a5 100644 --- a/templates/chisel/elaborator/src/GCDTestBench.scala +++ b/templates/chisel/elaborator/src/GCDTestBench.scala @@ -20,7 +20,7 @@ object GCDTestBenchMain extends SerializableModuleElaborator { @arg(name = "testVerbatimParameter") testVerbatimParameter: TestVerbatimParameterMain, @arg(name = "gcdParameter") gcdParameter: GCDParameterMain, @arg(name = "timeout") timeout: Int, - @arg(name = "testSize") testSize: Int) { + @arg(name = "testSize") testSize: Int) { def convert: GCDTestBenchParameter = GCDTestBenchParameter( testVerbatimParameter.convert, gcdParameter.convert, @@ -34,7 +34,7 @@ object GCDTestBenchMain extends SerializableModuleElaborator { @arg(name = "initFunctionName") initFunctionName: String, @arg(name = "dumpFunctionName") dumpFunctionName: String, @arg(name = "clockFlipTick") clockFlipTick: Int, - @arg(name = "resetFlipTick") resetFlipTick: Int) { + @arg(name = "resetFlipTick") resetFlipTick: Int) { def convert: TestVerbatimParameter = TestVerbatimParameter( useAsyncReset: Boolean, initFunctionName: String, diff --git a/templates/chisel/gcd/src/GCD.scala b/templates/chisel/gcd/src/GCD.scala index d35991d..55958f7 100644 --- a/templates/chisel/gcd/src/GCD.scala +++ b/templates/chisel/gcd/src/GCD.scala @@ -26,23 +26,23 @@ class GCDProbe(parameter: GCDParameter) extends Bundle { /** Metadata of [[GCD]]. */ @instantiable class GCDOM(parameter: GCDParameter) extends Class { - val width: Property[Int] = IO(Output(Property[Int]())) + val width: Property[Int] = IO(Output(Property[Int]())) val useAsyncReset: Property[Boolean] = IO(Output(Property[Boolean]())) - width := Property(parameter.width) + width := Property(parameter.width) useAsyncReset := Property(parameter.useAsyncReset) } /** Interface of [[GCD]]. */ class GCDInterface(parameter: GCDParameter) extends Bundle { - val clock = Input(Clock()) - val reset = Input(if (parameter.useAsyncReset) AsyncReset() else Bool()) - val input = Flipped(DecoupledIO(new Bundle { + val clock = Input(Clock()) + val reset = Input(if (parameter.useAsyncReset) AsyncReset() else Bool()) + val input = Flipped(DecoupledIO(new Bundle { val x = UInt(parameter.width.W) val y = UInt(parameter.width.W) })) val output = Valid(UInt(parameter.width.W)) - val probe = Output(Probe(new GCDProbe(parameter), layers.Verification)) - val om = Output(Property[AnyClassType]()) + val probe = Output(Probe(new GCDProbe(parameter), layers.Verification)) + val om = Output(Property[AnyClassType]()) } /** Hardware Implementation of GCD */ @@ -59,18 +59,18 @@ class GCD(val parameter: GCDParameter) // Block X-state propagation val y: UInt = RegInit(chiselTypeOf(io.input.bits.x), 0.U) val startupFlag = RegInit(false.B) - val busy = y =/= 0.U + val busy = y =/= 0.U when(x > y) { x := x - y }.otherwise { y := y - x } when(io.input.fire) { - x := io.input.bits.x - y := io.input.bits.y + x := io.input.bits.x + y := io.input.bits.y startupFlag := true.B } - io.input.ready := !busy - io.output.bits := x + io.input.ready := !busy + io.output.bits := x io.output.valid := startupFlag && !busy // Assign Probe diff --git a/templates/chisel/gcd/src/GCDFormal.scala b/templates/chisel/gcd/src/GCDFormal.scala index 2f68f43..4e4ebe7 100644 --- a/templates/chisel/gcd/src/GCDFormal.scala +++ b/templates/chisel/gcd/src/GCDFormal.scala @@ -24,7 +24,7 @@ case class GCDFormalParameter(gcdParameter: GCDParameter) extends SerializableMo @instantiable class GCDFormalOM(parameter: GCDFormalParameter) extends Class { - val gcd = IO(Output(Property[AnyClassType]())) + val gcd = IO(Output(Property[AnyClassType]())) @public val gcdIn = IO(Input(Property[AnyClassType]())) gcd := gcdIn @@ -37,7 +37,7 @@ class GCDFormalInterface(parameter: GCDFormalParameter) extends Bundle { val x = UInt(parameter.gcdParameter.width.W) val y = UInt(parameter.gcdParameter.width.W) })) - val om = Output(Property[AnyClassType]()) + val om = Output(Property[AnyClassType]()) } @instantiable @@ -46,13 +46,13 @@ class GCDFormal(val parameter: GCDFormalParameter) with SerializableModule[GCDFormalParameter] with ImplicitClock with ImplicitReset { - override protected def implicitClock: Clock = io.clock - override protected def implicitReset: Reset = io.reset + override protected def implicitClock: Clock = io.clock + override protected def implicitReset: Reset = io.reset // Instantiate DUT. - val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter)) + val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter)) // Instantiate OM val omInstance = Instantiate(new GCDFormalOM(parameter)) - io.om := omInstance.getPropertyReference.asAnyClassType + io.om := omInstance.getPropertyReference.asAnyClassType omInstance.gcdIn := dut.io.om dut.io.clock := implicitClock @@ -66,7 +66,7 @@ class GCDFormal(val parameter: GCDFormalParameter) val outputNotFire: Sequence = !dut.io.output.valid val inputNotValid: Sequence = dut.io.input.ready && !dut.io.input.valid - dut.io.input.bits := io.input.bits + dut.io.input.bits := io.input.bits dut.io.input.valid := io.input.valid AssumeProperty( diff --git a/templates/chisel/gcd/src/GCDTestBench.scala b/templates/chisel/gcd/src/GCDTestBench.scala index ce5191a..ad3402e 100644 --- a/templates/chisel/gcd/src/GCDTestBench.scala +++ b/templates/chisel/gcd/src/GCDTestBench.scala @@ -33,7 +33,7 @@ case class GCDTestBenchParameter( @instantiable class GCDTestBenchOM(parameter: GCDTestBenchParameter) extends Class { - val gcd = IO(Output(Property[AnyClassType]())) + val gcd = IO(Output(Property[AnyClassType]())) @public val gcdIn = IO(Input(Property[AnyClassType]())) gcd := gcdIn @@ -48,18 +48,18 @@ class GCDTestBench(val parameter: GCDTestBenchParameter) extends FixedIORawModule(new GCDTestBenchInterface(parameter)) with SerializableModule[GCDTestBenchParameter] with ImplicitClock - with ImplicitReset { - override protected def implicitClock: Clock = verbatim.io.clock - override protected def implicitReset: Reset = verbatim.io.reset + with ImplicitReset { + override protected def implicitClock: Clock = verbatim.io.clock + override protected def implicitReset: Reset = verbatim.io.reset // Instantiate Drivers - val verbatim: Instance[TestVerbatim] = Instantiate( + val verbatim: Instance[TestVerbatim] = Instantiate( new TestVerbatim(parameter.testVerbatimParameter) ) // Instantiate DUT. - val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter)) + val dut: Instance[GCD] = Instantiate(new GCD(parameter.gcdParameter)) // Instantiate OM val omInstance = Instantiate(new GCDTestBenchOM(parameter)) - io.om := omInstance.getPropertyReference.asAnyClassType + io.om := omInstance.getPropertyReference.asAnyClassType omInstance.gcdIn := dut.io.om dut.io.clock := implicitClock @@ -70,13 +70,13 @@ class GCDTestBench(val parameter: GCDTestBenchParameter) simulationTime := simulationTime + 1.U // For each timeout ticks, check it val (_, callWatchdog) = Counter(true.B, parameter.timeout / 2) - val watchdogCode = RawUnclockedNonVoidFunctionCall("gcd_watchdog", UInt(8.W))(callWatchdog) + val watchdogCode = RawUnclockedNonVoidFunctionCall("gcd_watchdog", UInt(8.W))(callWatchdog) when(watchdogCode =/= 0.U) { stop(cf"""{"event":"SimulationStop","reason": ${watchdogCode},"cycle":${simulationTime}}\n""") } class TestPayload extends Bundle { - val x = UInt(parameter.gcdParameter.width.W) - val y = UInt(parameter.gcdParameter.width.W) + val x = UInt(parameter.gcdParameter.width.W) + val y = UInt(parameter.gcdParameter.width.W) val result = UInt(parameter.gcdParameter.width.W) } val request = @@ -86,10 +86,10 @@ class GCDTestBench(val parameter: GCDTestBenchParameter) ) when(dut.io.input.ready) { dut.io.input.valid := request.valid - dut.io.input.bits := request.bits + dut.io.input.bits := request.bits }.otherwise { dut.io.input.valid := false.B; - dut.io.input.bits := DontCare; + dut.io.input.bits := DontCare; } // LTL Checker @@ -98,7 +98,7 @@ class GCDTestBench(val parameter: GCDTestBenchParameter) val inputNotFire: Sequence = !dut.io.input.fire val outputFire: Sequence = dut.io.output.valid val outputNotFire: Sequence = !dut.io.output.valid - val lastRequestResult: UInt = RegEnable(request.bits.result, dut.io.input.fire) + val lastRequestResult: UInt = RegEnable(request.bits.result, dut.io.input.fire) val checkRight: Sequence = lastRequestResult === dut.io.output.bits val inputNotValid: Sequence = dut.io.input.ready && !dut.io.input.valid @@ -140,19 +140,19 @@ case class TestVerbatimParameter( @instantiable class TestVerbatimOM(parameter: TestVerbatimParameter) extends Class { val useAsyncReset: Property[Boolean] = IO(Output(Property[Boolean]())) - val initFunctionName: Property[String] = IO(Output(Property[String]())) - val dumpFunctionName: Property[String] = IO(Output(Property[String]())) - val clockFlipTick: Property[Int] = IO(Output(Property[Int]())) - val resetFlipTick: Property[Int] = IO(Output(Property[Int]())) - val gcd = IO(Output(Property[AnyClassType]())) + val initFunctionName: Property[String] = IO(Output(Property[String]())) + val dumpFunctionName: Property[String] = IO(Output(Property[String]())) + val clockFlipTick: Property[Int] = IO(Output(Property[Int]())) + val resetFlipTick: Property[Int] = IO(Output(Property[Int]())) + val gcd = IO(Output(Property[AnyClassType]())) @public val gcdIn = IO(Input(Property[AnyClassType]())) - gcd := gcdIn - useAsyncReset := Property(parameter.useAsyncReset) + gcd := gcdIn + useAsyncReset := Property(parameter.useAsyncReset) initFunctionName := Property(parameter.initFunctionName) dumpFunctionName := Property(parameter.dumpFunctionName) - clockFlipTick := Property(parameter.clockFlipTick) - resetFlipTick := Property(parameter.resetFlipTick) + clockFlipTick := Property(parameter.clockFlipTick) + resetFlipTick := Property(parameter.resetFlipTick) } /** Test blackbox for clockgen, wave dump and extra testbench-only codes. */