From fcaceab0095c1b52079ada78feb81cd62b35a947 Mon Sep 17 00:00:00 2001
From: Krzysztof Boronski <kboronski@antmicro.com>
Date: Wed, 25 Sep 2024 20:17:32 +0200
Subject: [PATCH] Fix VCS VILIOP errors

Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
---
 src/i3c_wrapper.sv | 4 ++--
 src/phy/buf_od.sv  | 2 +-
 src/phy/bufs.sv    | 2 +-
 src/phy/i3c_io.sv  | 4 ++--
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/i3c_wrapper.sv b/src/i3c_wrapper.sv
index f3f00fcd..9c93e996 100644
--- a/src/i3c_wrapper.sv
+++ b/src/i3c_wrapper.sv
@@ -102,8 +102,8 @@ module i3c_wrapper #(
     output logic sel_od_pp_o
 `else
     // I3C bus IO
-    inout  logic i3c_scl_io,
-    inout  logic i3c_sda_io
+    inout  wire i3c_scl_io,
+    inout  wire i3c_sda_io
 `endif
 
     // TODO: Add interrupts
diff --git a/src/phy/buf_od.sv b/src/phy/buf_od.sv
index b62e5012..64ed8e64 100644
--- a/src/phy/buf_od.sv
+++ b/src/phy/buf_od.sv
@@ -11,7 +11,7 @@
 */
 module buf_od (
     input logic drive_low,
-    inout logic buf_od_o
+    inout wire  buf_od_o
 );
 
   assign buf_od_o = drive_low ? 1'b0 : 1'bz;
diff --git a/src/phy/bufs.sv b/src/phy/bufs.sv
index 1e8d1206..d26a2def 100644
--- a/src/phy/bufs.sv
+++ b/src/phy/bufs.sv
@@ -14,7 +14,7 @@
 module bufs (
     input logic phy_data_i,
     input logic sel_od_pp_i,
-    inout logic phy_data_io
+    inout wire  phy_data_io
 );
 
   logic phy_data_i_z;
diff --git a/src/phy/i3c_io.sv b/src/phy/i3c_io.sv
index 82f8da81..a975655e 100644
--- a/src/phy/i3c_io.sv
+++ b/src/phy/i3c_io.sv
@@ -24,8 +24,8 @@ module i3c_io (
     input logic sel_od_pp_i,
 
     // Bus {SCL, SDA}
-    inout logic scl_io,
-    inout logic sda_io
+    inout wire scl_io,
+    inout wire sda_io
 );
 
   wire scl_io_int;