From 9aea15eff732a3e9366e2c1ffea610c1411a9ec1 Mon Sep 17 00:00:00 2001 From: Sae86 Date: Thu, 29 Feb 2024 13:35:15 -0800 Subject: [PATCH] Update to 1.12.9 Signed-off-by: Sae86 --- .../chipsec/cfg/parsers/core_parsers.html | 99 +- _modules/chipsec/config.html | 94 +- _modules/chipsec/fuzzing/primitives.html | 236 +- _modules/chipsec/hal/acpi.html | 107 +- _modules/chipsec/hal/acpi_tables.html | 1264 ++--- _modules/chipsec/hal/cmos.html | 64 +- _modules/chipsec/hal/cpu.html | 124 +- _modules/chipsec/hal/cpuid.html | 39 +- _modules/chipsec/hal/ec.html | 88 +- _modules/chipsec/hal/hal_base.html | 27 +- _modules/chipsec/hal/igd.html | 123 +- _modules/chipsec/hal/interrupts.html | 68 +- _modules/chipsec/hal/io.html | 71 +- _modules/chipsec/hal/iobar.html | 75 +- _modules/chipsec/hal/iommu.html | 64 +- _modules/chipsec/hal/locks.html | 53 +- _modules/chipsec/hal/mmio.html | 201 +- _modules/chipsec/hal/msgbus.html | 79 +- _modules/chipsec/hal/msr.html | 94 +- _modules/chipsec/hal/paging.html | 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modules/chipsec.modules.tools.vmm.xen.xsa188.html delete mode 100644 modules/chipsec.modules.tools.wsmt.html delete mode 100644 modules/chipsec.testcase.html diff --git a/_modules/chipsec/cfg/parsers/core_parsers.html b/_modules/chipsec/cfg/parsers/core_parsers.html index f5f56e0b..b3deab72 100644 --- a/_modules/chipsec/cfg/parsers/core_parsers.html +++ b/_modules/chipsec/cfg/parsers/core_parsers.html @@ -1,18 +1,20 @@ + - + chipsec.cfg.parsers.core_parsers — CHIPSEC documentation - - + + - - - + + + + - + @@ -109,24 +111,14 @@

Source code for chipsec.cfg.parsers.core_parsers

return node_data -
-[docs] -class PlatformInfo(BaseConfigParser): -
-[docs] - def get_metadata(self): +
[docs]class PlatformInfo(BaseConfigParser): +
[docs] def get_metadata(self): return {'info': self.handle_info}
- -
-[docs] - def get_stage(self): +
[docs] def get_stage(self): return Stage.GET_INFO
- -
-[docs] - def handle_info(self, et_node, stage_data): +
[docs] def handle_info(self, et_node, stage_data): platform = '' req_pch = None family = None @@ -162,17 +154,11 @@

Source code for chipsec.cfg.parsers.core_parsers

sku_info['vid'] = vid_int sku_data.append(sku_info) - return info_data(family, proc_code, pch_code, detect_vals, req_pch, stage_data.vid_str, sku_data)
-
- + return info_data(family, proc_code, pch_code, detect_vals, req_pch, stage_data.vid_str, sku_data)
-
-[docs] -class CoreConfig(BaseConfigParser): -
-[docs] - def get_metadata(self): +
[docs]class CoreConfig(BaseConfigParser): +
[docs] def get_metadata(self): return {'pci': self.handle_pci, 'mmio': self.handle_mmio, 'io': self.handle_io, @@ -182,13 +168,9 @@

Source code for chipsec.cfg.parsers.core_parsers

'controls': self.handle_controls, 'locks': self.handle_locks}
- -
-[docs] - def get_stage(self): +
[docs] def get_stage(self): return Stage.DEVICE_CFG
- def _process_pci_dev(self, vid_str, dev_name, dev_attr): device_added = False if 'did' in dev_attr: @@ -221,9 +203,7 @@

Source code for chipsec.cfg.parsers.core_parsers

if 'did' in dev_attr: self.cfg.CONFIG_PCI[name]['did'] = dev_attr['did'][0] -
-[docs] - def handle_pci(self, et_node, stage_data): +
[docs] def handle_pci(self, et_node, stage_data): ret_val = [] for dev in et_node.iter('device'): @@ -236,46 +216,25 @@

Source code for chipsec.cfg.parsers.core_parsers

return ret_val
- -
-[docs] - def handle_controls(self, et_node, stage_data): +
[docs] def handle_controls(self, et_node, stage_data): return self._add_entry_simple(self.cfg.CONTROLS, stage_data, et_node, 'control')
- -
-[docs] - def handle_io(self, et_node, stage_data): +
[docs] def handle_io(self, et_node, stage_data): return self._add_entry_simple(self.cfg.IO_BARS, stage_data, et_node, 'bar')
- -
-[docs] - def handle_ima(self, et_node, stage_data): +
[docs] def handle_ima(self, et_node, stage_data): return self._add_entry_simple(self.cfg.IMA_REGISTERS, stage_data, et_node, 'indirect')
- -
-[docs] - def handle_locks(self, et_node, stage_data): +
[docs] def handle_locks(self, et_node, stage_data): return self._add_entry_simple(self.cfg.LOCKS, stage_data, et_node, 'lock')
- -
-[docs] - def handle_memory(self, et_node, stage_data): +
[docs] def handle_memory(self, et_node, stage_data): return self._add_entry_simple(self.cfg.MEMORY_RANGES, stage_data, et_node, 'range')
- -
-[docs] - def handle_mmio(self, et_node, stage_data): +
[docs] def handle_mmio(self, et_node, stage_data): return self._add_entry_simple(self.cfg.MMIO_BARS, stage_data, et_node, 'bar')
- -
-[docs] - def handle_registers(self, et_node, stage_data): +
[docs] def handle_registers(self, et_node, stage_data): ret_val = [] dest = self.cfg.REGISTERS for reg in et_node.iter('register'): @@ -325,7 +284,6 @@

Source code for chipsec.cfg.parsers.core_parsers

self.logger.log_debug(f' + {reg_name:16}: {reg_attr}') return ret_val
- def _add_entry_simple(self, dest, stage_data, et_node, node_name): ret_val = [] for node in et_node.iter(node_name): @@ -345,7 +303,6 @@

Source code for chipsec.cfg.parsers.core_parsers

return ret_val
- parsers = [PlatformInfo, CoreConfig]
@@ -406,7 +363,7 @@

Quick search

- +
@@ -426,8 +383,8 @@

Navigation

\ No newline at end of file diff --git a/_modules/chipsec/config.html b/_modules/chipsec/config.html index 37b31f63..0907b431 100644 --- a/_modules/chipsec/config.html +++ b/_modules/chipsec/config.html @@ -1,18 +1,20 @@ + - + chipsec.config — CHIPSEC documentation - - + + - - - + + + + - + @@ -79,9 +81,7 @@

Source code for chipsec.config

 PCH_CODE_PREFIX = 'PCH_'
 
 
-

-[docs]
-class Cfg:
+
[docs]class Cfg:
     def __init__(self):
         self.logger = logger()
         self.CONFIG_PCI = {}
@@ -132,9 +132,7 @@ 
Source code for chipsec.config
     ###
     # PCI device tree enumeration
     ###
-

-[docs]
-    def set_pci_data(self, enum_devices):
+
[docs]    def set_pci_data(self, enum_devices):
         if not hasattr(self, 'CONFIG_PCI_RAW'):
             setattr(self, 'CONFIG_PCI_RAW', {})
         for b, d, f, vid, did, rid in enum_devices:
@@ -154,50 +152,32 @@ 
Source code for chipsec.config
             elif b not in self.CONFIG_PCI_RAW[vid_str][did_str]['bus']:
                 self.CONFIG_PCI_RAW[vid_str][did_str]['bus'].append(b)

 
-
     ###
     # Platform detection functions
     ###
-

-[docs]
-    def get_chipset_code(self):
+
[docs]    def get_chipset_code(self):
         return self.code

 
-
-

-[docs]
-    def get_pch_code(self):
+
[docs]    def get_pch_code(self):
         return self.pch_code

 
-
-

-[docs]
-    def is_pch_req(self):
+
[docs]    def is_pch_req(self):
         return self.req_pch

 
-
-

-[docs]
-    def print_platform_info(self):
+
[docs]    def print_platform_info(self):
         self.logger.log(f"Platform: {self.longname}")
         self.logger.log(f'\tCPUID: {self.cpuid:X}')
         self.logger.log(f"\tVID: {self.vid:04X}")
         self.logger.log(f"\tDID: {self.did:04X}")
         self.logger.log(f"\tRID: {self.rid:02X}")

-
         
-

-[docs]
-    def print_pch_info(self):
+
[docs]    def print_pch_info(self):
         self.logger.log(f"Platform: {self.pch_longname}")
         self.logger.log(f"\tVID: {self.pch_vid:04X}")
         self.logger.log(f"\tDID: {self.pch_did:04X}")
         self.logger.log(f"\tRID: {self.pch_rid:02X}")

 
-
-

-[docs]
-    def print_supported_chipsets(self):
+
[docs]    def print_supported_chipsets(self):
         fmtStr = " {:4} | {:4} | {:14} | {:6} | {:40}"
         self.logger.log("\nSupported platforms:\n")
         self.logger.log(fmtStr.format("VID", "DID", "Name", "Code", "Long Name"))
@@ -207,7 +187,6 @@ 
Source code for chipsec.config
                 for item in self.proc_dictionary[_vid][_did]:
                     self.logger.log(fmtStr.format(_vid, _did, item['name'], item['code'].lower(), item['longname'][:40]))

 
-
     ###
     # Private config functions
     ###
@@ -314,9 +293,7 @@ 
Source code for chipsec.config
     ###
     # Config loading functions
     ###
-

-[docs]
-    def load_parsers(self):
+
[docs]    def load_parsers(self):
         parser_path = os.path.join(get_main_dir(), 'chipsec', 'cfg', 'parsers')
         if not os.path.isdir(parser_path):
             raise CSConfigError('Unable to locate configuration parsers: {}'.format(parser_path))
@@ -342,10 +319,7 @@ 
Source code for chipsec.config
                 parser_obj.startup()
                 self.parsers.append(parser_obj)

 
-
-

-[docs]
-    def add_extra_configs(self, path, filename=None, loadnow=False):
+
[docs]    def add_extra_configs(self, path, filename=None, loadnow=False):
         config_path = os.path.join(get_main_dir(), 'chipsec', 'cfg', path)
         if os.path.isdir(config_path) and filename is None:
             self.load_extra = [config_data(None, None, os.path.join(config_path, f)) for f in sorted(os.listdir(config_path))
@@ -358,10 +332,7 @@ 
Source code for chipsec.config
         if loadnow and self.load_extra:
             self._load_sec_configs(self.load_extra, Stage.EXTRA)

 
-
-

-[docs]
-    def load_platform_info(self):
+
[docs]    def load_platform_info(self):
         tag_handlers = self._get_stage_parsers(Stage.GET_INFO)
         cfg_path = os.path.join(get_main_dir(), 'chipsec', 'cfg')
 
@@ -392,10 +363,7 @@ 
Source code for chipsec.config
         for pc in self.pch_codes:
             globals()["PCH_CODE_{}".format(pc[4:].upper())] = pc.upper()

 
-
-

-[docs]
-    def platform_detection(self, proc_code, pch_code, cpuid):
+
[docs]    def platform_detection(self, proc_code, pch_code, cpuid):
         # Detect processor files
         self.cpuid = cpuid
         sku = self._find_sku_data(self.proc_dictionary, proc_code, cpuid)
@@ -432,10 +400,7 @@ 
Source code for chipsec.config
         if 'devices' in self.platform_xml_files:
             self.load_list.extend(self.platform_xml_files['devices'])

 
-
-

-[docs]
-    def load_platform_config(self):
+
[docs]    def load_platform_config(self):
         sec_load_list = []
         tag_handlers = self._get_stage_parsers(Stage.DEVICE_CFG)
         for fxml in self.load_list:
@@ -450,10 +415,7 @@ 
Source code for chipsec.config
         if self.load_extra:
             self._load_sec_configs(self.load_extra, Stage.EXTRA)

 
-
-

-[docs]
-    def get_common_xml(self):
+
[docs]    def get_common_xml(self):
         cfg_path = os.path.join(get_main_dir(), 'chipsec', 'cfg')
         vid = f'{self.vid:X}'
 
@@ -465,9 +427,7 @@ 
Source code for chipsec.config
             cfg_files.extend([config_data(vid, None, os.path.join(root_path, f))
                              for f in sorted(os.listdir(root_path))
                              if fnmatch(f, '*.xml') and fnmatch(f, 'common*')])
-        return cfg_files

-

-
+        return cfg_files

 

 
             

@@ -527,7 +487,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -547,8 +507,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/fuzzing/primitives.html b/_modules/chipsec/fuzzing/primitives.html
index 255eacfc..dc3a12a1 100644
--- a/_modules/chipsec/fuzzing/primitives.html
+++ b/_modules/chipsec/fuzzing/primitives.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.fuzzing.primitives — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -44,10 +46,8 @@ 
Source code for chipsec.fuzzing.primitives
 ########################################################################################################################
 
 
-

-[docs]
-class base_primitive:
-    '''
+
[docs]class base_primitive:
+    '''
     The primitive base class implements common functionality shared across most primitives.
     '''
 
@@ -60,10 +60,8 @@ 
Source code for chipsec.fuzzing.primitives
         self.rendered = ""        # rendered value of primitive.
         self.value = None      # current value of primitive.
 
-

-[docs]
-    def exhaust(self):
-        '''
+
[docs]    def exhaust(self):
+        '''
         Exhaust the possible mutations for this primitive.
 
         @rtype:  Integer
@@ -78,11 +76,8 @@ 
Source code for chipsec.fuzzing.primitives
 
         return num

 
-
-

-[docs]
-    def mutate(self):
-        '''
+
[docs]    def mutate(self):
+        '''
         Mutate the primitive by stepping through the fuzz library, return False on completion.
 
         @rtype:  Boolean
@@ -106,11 +101,8 @@ 
Source code for chipsec.fuzzing.primitives
 
         return True

 
-
-

-[docs]
-    def num_mutations(self):
-        '''
+
[docs]    def num_mutations(self):
+        '''
         Calculate and return the total number of mutations for this individual primitive.
 
         @rtype:  Integer
@@ -119,38 +111,28 @@ 
Source code for chipsec.fuzzing.primitives
 
         return len(self.fuzz_library)

 
-
-

-[docs]
-    def render(self):
-        '''
+
[docs]    def render(self):
+        '''
         Nothing fancy on render, simply return the value.
         '''
 
         self.rendered = self.value
         return self.rendered

 
-
-

-[docs]
-    def reset(self):
-        '''
+
[docs]    def reset(self):
+        '''
         Reset this primitive to the starting mutation state.
         '''
 
         self.fuzz_complete = False
         self.mutant_index = 0
-        self.value = self.original_value

-

-
+        self.value = self.original_value

 
 
 ########################################################################################################################
-

-[docs]
-class delim(base_primitive):
+
[docs]class delim(base_primitive):
     def __init__(self, value, fuzzable=True, name=None):
-        '''
+        '''
         Represent a delimiter such as :,\r,\n, ,=,>,< etc... Mutations include repetition, substitution and exclusion.
 
         @type  value:    Character
@@ -229,13 +211,10 @@ 
Source code for chipsec.fuzzing.primitives
         self.fuzz_library.append("\r\n" * 512)

 
 
-
 ########################################################################################################################
-

-[docs]
-class group(base_primitive):
+
[docs]class group(base_primitive):
     def __init__(self, name, values):
-        '''
+        '''
         This primitive represents a list of static values, stepping through each one on mutation. You can tie a block
         to a group primitive to specify that the block should cycle through all possible mutations for *each* value
         within the group. The group primitive is useful for example for representing a list of valid opcodes.
@@ -259,10 +238,8 @@ 
Source code for chipsec.fuzzing.primitives
             for val in self.values:
                 assert isinstance(val, str), "Value list may only contain strings or raw data"
 
-

-[docs]
-    def mutate(self):
-        '''
+
[docs]    def mutate(self):
+        '''
         Move to the next item in the values list.
 
         @rtype:  False
@@ -285,28 +262,21 @@ 
Source code for chipsec.fuzzing.primitives
 
         return True

 
-
-

-[docs]
-    def num_mutations(self):
-        '''
+
[docs]    def num_mutations(self):
+        '''
         Number of values in this primitive.
 
         @rtype:  Integer
         @return: Number of values in this primitive.
         '''
 
-        return len(self.values)

-

-
+        return len(self.values)

 
 
 ########################################################################################################################
-

-[docs]
-class random_data(base_primitive):
+
[docs]class random_data(base_primitive):
     def __init__(self, value, min_length, max_length, max_mutations=25, fuzzable=True, step=None, name=None):
-        '''
+        '''
         Generate a random chunk of data while maintaining a copy of the original. A random length range can be specified.
         For a static length, set min/max length to be the same.
 
@@ -340,10 +310,8 @@ 
Source code for chipsec.fuzzing.primitives
         if self.step:
             self.max_mutations = (self.max_length - self.min_length) // self.step + 1
 
-

-[docs]
-    def mutate(self):
-        '''
+
[docs]    def mutate(self):
+        '''
         Mutate the primitive value returning False on completion.
 
         @rtype:  Boolean
@@ -376,28 +344,21 @@ 
Source code for chipsec.fuzzing.primitives
 
         return True

 
-
-

-[docs]
-    def num_mutations(self):
-        '''
+
[docs]    def num_mutations(self):
+        '''
         Calculate and return the total number of mutations for this individual primitive.
 
         @rtype:  Integer
         @return: Number of mutated forms this primitive can take
         '''
 
-        return self.max_mutations

-

-
+        return self.max_mutations

 
 
 ########################################################################################################################
-

-[docs]
-class static(base_primitive):
+
[docs]class static(base_primitive):
     def __init__(self, value, name=None):
-        '''
+        '''
         Primitive that contains static content.
 
         @type  value: Raw
@@ -413,10 +374,8 @@ 
Source code for chipsec.fuzzing.primitives
         self.s_type = "static"    # for ease of object identification
         self.fuzz_complete = True
 
-

-[docs]
-    def mutate(self):
-        '''
+
[docs]    def mutate(self):
+        '''
         Do nothing.
 
         @rtype:  False
@@ -425,31 +384,24 @@ 
Source code for chipsec.fuzzing.primitives
 
         return False

 
-
-

-[docs]
-    def num_mutations(self):
-        '''
+
[docs]    def num_mutations(self):
+        '''
         Return 0.
 
         @rtype:  0
         @return: 0
         '''
 
-        return 0

-

-
+        return 0

 
 
 ########################################################################################################################
-

-[docs]
-class string(base_primitive):
+
[docs]class string(base_primitive):
     # store fuzz_library as a class variable to avoid copying the ~70MB structure across each instantiated primitive.
     fuzz_library = []
 
     def __init__(self, value, size=-1, padding="\x00", encoding="ascii", fuzzable=True, max_len=0, name=None):
-        '''
+        '''
         Primitive that cycles through a library of "bad" strings. The class variable 'fuzz_library' contains a list of
         smart fuzz values global across all instances. The 'this_library' variable contains fuzz values specific to
         the instantiated primitive. This allows us to avoid copying the near ~70MB fuzz_library data structure across
@@ -616,10 +568,8 @@ 
Source code for chipsec.fuzzing.primitives
             if any(len(s) > max_len for s in self.fuzz_library):
                 self.fuzz_library = list(set([s[:max_len] for s in self.fuzz_library]))
 
-

-[docs]
-    def add_long_strings(self, sequence):
-        '''
+
[docs]    def add_long_strings(self, sequence):
+        '''
         Given a sequence, generate a number of selectively chosen strings lengths of the given sequence and add to the
         string heuristic library.
 
@@ -634,11 +584,8 @@ 
Source code for chipsec.fuzzing.primitives
             long_string = sequence * length
             string.fuzz_library.append(long_string)

 
-
-

-[docs]
-    def mutate(self):
-        '''
+
[docs]    def mutate(self):
+        '''
         Mutate the primitive by stepping through the fuzz library extended with the "this" library, return False on
         completion.
 
@@ -679,11 +626,8 @@ 
Source code for chipsec.fuzzing.primitives
 
         return True

 
-
-

-[docs]
-    def num_mutations(self):
-        '''
+
[docs]    def num_mutations(self):
+        '''
         Calculate and return the total number of mutations for this individual primitive.
 
         @rtype:  Integer
@@ -692,11 +636,8 @@ 
Source code for chipsec.fuzzing.primitives
 
         return len(self.fuzz_library) + len(self.this_library)

 
-
-

-[docs]
-    def render(self):
-        '''
+
[docs]    def render(self):
+        '''
         Render the primitive, encode the string according to the specified encoding.
         '''
 
@@ -706,17 +647,13 @@ 
Source code for chipsec.fuzzing.primitives
         except:
             self.rendered = str(self.value).encode('latin-1')
 
-        return self.rendered

-

-
+        return self.rendered

 
 
 ########################################################################################################################
-

-[docs]
-class bit_field(base_primitive):
+
[docs]class bit_field(base_primitive):
     def __init__(self, value, width, max_num=None, endian="<", format="binary", signed=False, full_range=False, fuzzable=True, name=None):
-        '''
+        '''
         The bit field primitive represents a number of variable length and is used to define all other integer types.
 
         @type  value:      Integer
@@ -801,10 +738,8 @@ 
Source code for chipsec.fuzzing.primitives
         except:
             pass
 
-

-[docs]
-    def add_integer_boundaries(self, integer):
-        '''
+
[docs]    def add_integer_boundaries(self, integer):
+        '''
         Add the supplied integer and border cases to the integer fuzz heuristics library.
 
         @type  integer: Int
@@ -819,11 +754,8 @@ 
Source code for chipsec.fuzzing.primitives
                 if case not in self.fuzz_library:
                     self.fuzz_library.append(case)

 
-
-

-[docs]
-    def render(self):
-        '''
+
[docs]    def render(self):
+        '''
         Render the primitive.
         '''
 
@@ -876,11 +808,8 @@ 
Source code for chipsec.fuzzing.primitives
                 self.rendered = "%d" % self.value
         return self.rendered

 
-
-

-[docs]
-    def to_binary(self, number=None, bit_count=None):
-        '''
+
[docs]    def to_binary(self, number=None, bit_count=None):
+        '''
         Convert a number to a binary string.
 
         @type  number:    Integer
@@ -907,11 +836,8 @@ 
Source code for chipsec.fuzzing.primitives
 
         return "".join(map(lambda x: str((number >> x) & 1), range(bit_count - 1, -1, -1)))

 
-
-

-[docs]
-    def to_decimal(self, binary):
-        '''
+
[docs]    def to_decimal(self, binary):
+        '''
         Convert a binary string to a decimal number.
 
         @type  binary: String
@@ -921,15 +847,11 @@ 
Source code for chipsec.fuzzing.primitives
         @return: Converted bit string
         '''
 
-        return int(binary, 2)

-

-
+        return int(binary, 2)

 
 
 ########################################################################################################################
-

-[docs]
-class byte (bit_field):
+
[docs]class byte (bit_field):
     def __init__(self, value, endian="<", format="binary", signed=False, full_range=False, fuzzable=True, name=None):
         self.s_type = "byte"
         if not isinstance(value, (int, list, tuple)):
@@ -938,11 +860,8 @@ 
Source code for chipsec.fuzzing.primitives
         bit_field.__init__(self, value, 8, None, endian, format, signed, full_range, fuzzable, name)

 
 
-
 ########################################################################################################################
-

-[docs]
-class word (bit_field):
+
[docs]class word (bit_field):
     def __init__(self, value, endian="<", format="binary", signed=False, full_range=False, fuzzable=True, name=None):
         self.s_type = "word"
         if not isinstance(value, (int, list, tuple)):
@@ -951,11 +870,8 @@ 
Source code for chipsec.fuzzing.primitives
         bit_field.__init__(self, value, 16, None, endian, format, signed, full_range, fuzzable, name)

 
 
-
 ########################################################################################################################
-

-[docs]
-class dword (bit_field):
+
[docs]class dword (bit_field):
     def __init__(self, value, endian="<", format="binary", signed=False, full_range=False, fuzzable=True, name=None):
         self.s_type = "dword"
         if not isinstance(value, (int, list, tuple)):
@@ -964,18 +880,14 @@ 
Source code for chipsec.fuzzing.primitives
         bit_field.__init__(self, value, 32, None, endian, format, signed, full_range, fuzzable, name)

 
 
-
 ########################################################################################################################
-

-[docs]
-class qword (bit_field):
+
[docs]class qword (bit_field):
     def __init__(self, value, endian="<", format="binary", signed=False, full_range=False, fuzzable=True, name=None):
         self.s_type = "qword"
         if not isinstance(value, (int, list, tuple)):
             value = struct.unpack(endian + "Q", value)[0]
 
         bit_field.__init__(self, value, 64, None, endian, format, signed, full_range, fuzzable, name)

-
 

 
             

@@ -1035,7 +947,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -1055,8 +967,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/acpi.html b/_modules/chipsec/hal/acpi.html
index 648e2be3..c840828b 100644
--- a/_modules/chipsec/hal/acpi.html
+++ b/_modules/chipsec/hal/acpi.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.acpi — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -83,27 +85,24 @@ 
Source code for chipsec.hal.acpi
 assert 36 == ACPI_TABLE_HEADER_SIZE
 
 
-

-[docs]
-class ACPI_TABLE_HEADER(namedtuple('ACPI_TABLE_HEADER', 'Signature Length Revision Checksum OEMID OEMTableID OEMRevision CreatorID CreatorRevision')):
+
[docs]class ACPI_TABLE_HEADER(namedtuple('ACPI_TABLE_HEADER', 'Signature Length Revision Checksum OEMID OEMTableID OEMRevision CreatorID CreatorRevision')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""  Table Header
 ------------------------------------------------------------------
-  Signature        : {self.Signature}
-  Length           : 0x{self.Length:08X}
-  Revision         : 0x{self.Revision:02X}
-  Checksum         : 0x{self.Checksum:02X}
-  OEM ID           : {self.OEMID}
-  OEM Table ID     : {self.OEMTableID}
-  OEM Revision     : 0x{self.OEMRevision:08X}
-  Creator ID       : {self.CreatorID}
-  Creator Revision : 0x{self.CreatorRevision:08X}
+  Signature        : {self.Signature}
+  Length           : 0x{self.Length:08X}
+  Revision         : 0x{self.Revision:02X}
+  Checksum         : 0x{self.Checksum:02X}
+  OEM ID           : {self.OEMID}
+  OEM Table ID     : {self.OEMTableID}
+  OEM Revision     : 0x{self.OEMRevision:08X}
+  Creator ID       : {self.CreatorID}
+  Creator Revision : 0x{self.CreatorRevision:08X}
 """

 
 
-
 ACPI_TABLE_SIG_SIZE = 0x4
 
 ACPI_TABLE_SIG_ROOT = 'ROOT'
@@ -236,18 +235,14 @@ 
Source code for chipsec.hal.acpi
 ########################################################################################################
 
 
-

-[docs]
-class ACPI(HALBase):
+
[docs]class ACPI(HALBase):
     def __init__(self, cs):
         super(ACPI, self).__init__(cs)
         self.uefi = UEFI(self.cs)
         self.tableList: Dict[str, List[int]] = defaultdict(list)
         self.get_ACPI_table_list()
 
-

-[docs]
-    def read_RSDP(self, rsdp_pa: int) -> acpi_tables.RSDP:
+
[docs]    def read_RSDP(self, rsdp_pa: int) -> acpi_tables.RSDP:
         rsdp_buf = self.cs.mem.read_physical_mem(rsdp_pa, acpi_tables.ACPI_RSDP_SIZE)
         rsdp = acpi_tables.RSDP()
         rsdp.parse(rsdp_buf)
@@ -257,7 +252,6 @@ 
Source code for chipsec.hal.acpi
             rsdp.parse(rsdp_buf)
         return rsdp

 
-
     #
     # Check RSDP in Extended BIOS Data Area
     #
@@ -347,9 +341,7 @@ 
Source code for chipsec.hal.acpi
     #
     # Searches for Root System Description Pointer (RSDP) in various locations for legacy/EFI systems
     #
-

-[docs]
-    def find_RSDP(self) -> Tuple[Optional[int], Optional[acpi_tables.RSDP]]:
+
[docs]    def find_RSDP(self) -> Tuple[Optional[int], Optional[acpi_tables.RSDP]]:
         rsdp, rsdp_pa = self._find_RSDP_in_EBDA()
 
         if rsdp_pa is None:
@@ -366,14 +358,11 @@ 
Source code for chipsec.hal.acpi
 
         return (rsdp_pa, rsdp)

 
-
     RsdtXsdt = Union[acpi_tables.RSDT, acpi_tables.XSDT]
     #
     # Retrieves System Description Table (RSDT or XSDT) either from RSDP or using OS API
     #
-

-[docs]
-    def get_SDT(self, search_rsdp: bool = True) -> Tuple[bool, Optional[int], Optional[RsdtXsdt], Optional[ACPI_TABLE_HEADER]]:
+
[docs]    def get_SDT(self, search_rsdp: bool = True) -> Tuple[bool, Optional[int], Optional[RsdtXsdt], Optional[ACPI_TABLE_HEADER]]:
         is_xsdt = False
         sdt_pa = None
         sdt_header = None
@@ -406,13 +395,10 @@ 
Source code for chipsec.hal.acpi
         sdt.parse(sdt_contents)
         return (is_xsdt, sdt_pa, sdt, sdt_header)

 
-
     #
     # Populates a list of ACPI tables available on the system
     #
-

-[docs]
-    def get_ACPI_table_list(self) -> Dict[str, List[int]]:
+
[docs]    def get_ACPI_table_list(self) -> Dict[str, List[int]]:
         try:
             # 1. Try to extract ACPI table(s) from physical memory
             #    read_physical_mem can be implemented using both
@@ -438,14 +424,11 @@ 
Source code for chipsec.hal.acpi
 
         return self.tableList

 
-
     #
     # Gets table list from entries in RSDT/XSDT
     #
-

-[docs]
-    def get_table_list_from_SDT(self, sdt: RsdtXsdt, is_xsdt: bool) -> None:
-        logger().log_hal(f'[acpi] Getting table list from entries in {"XSDT" if is_xsdt else "RSDT"}')
+
[docs]    def get_table_list_from_SDT(self, sdt: RsdtXsdt, is_xsdt: bool) -> None:
+        logger().log_hal(f'[acpi] Getting table list from entries in {"XSDT" if is_xsdt else "RSDT"}')
         for a in sdt.Entries:
             _sig = self.cs.mem.read_physical_mem(a, ACPI_TABLE_SIG_SIZE)
             _sig = bytestostring(_sig)
@@ -454,13 +437,10 @@ 
Source code for chipsec.hal.acpi
                     logger().log_warning(f'Unknown ACPI table signature: {_sig}')
             self.tableList[_sig].append(a)

 
-
     #
     # Gets DSDT from FADT
     #
-

-[docs]
-    def get_DSDT_from_FADT(self) -> None:
+
[docs]    def get_DSDT_from_FADT(self) -> None:
         logger().log_hal('[acpi] Getting DSDT from FADT')
 
         if ACPI_TABLE_SIG_FACP in self.tableList:
@@ -487,22 +467,16 @@ 
Source code for chipsec.hal.acpi
 
         self.tableList[ACPI_TABLE_SIG_DSDT].append(dsdt_address_to_use)

 
-
     #
     # Checks is ACPI table with <name> is available on the system
     #
-

-[docs]
-    def is_ACPI_table_present(self, name: str) -> bool:
+
[docs]    def is_ACPI_table_present(self, name: str) -> bool:
         return (name in self.tableList)

 
-
     #
     # Prints a list of ACPI tables available on the system
     #
-

-[docs]
-    def print_ACPI_table_list(self) -> None:
+
[docs]    def print_ACPI_table_list(self) -> None:
         if len(self.tableList) == 0:
             logger().log_error("Couldn't get a list of ACPI tables")
         else:
@@ -511,20 +485,14 @@ 
Source code for chipsec.hal.acpi
                 table_values_str = ', '.join([f'0x{addr:016X}' for addr in self.tableList[tableName]])
                 logger().log(f' - {tableName}: {table_values_str}')

 
-
     #
     # Retrieves contents of ACPI table from memory or from file
     #
-

-[docs]
-    def get_parse_ACPI_table(self, name: str, isfile: bool = False) -> List['ParseTable']:
+
[docs]    def get_parse_ACPI_table(self, name: str, isfile: bool = False) -> List['ParseTable']:
         acpi_tables = self.get_ACPI_table(name, isfile)
         return [self._parse_table(name, table_header_blob, table_blob) for (table_header_blob, table_blob) in acpi_tables if table_header_blob is not None]

 
-
-

-[docs]
-    def get_ACPI_table(self, name: str, isfile: bool = False) -> List[Tuple[bytes, bytes]]:
+
[docs]    def get_ACPI_table(self, name: str, isfile: bool = False) -> List[Tuple[bytes, bytes]]:
         acpi_tables_data: List[bytes] = []
         if isfile:
             acpi_tables_data.append(read_file(name))
@@ -551,13 +519,10 @@ 
Source code for chipsec.hal.acpi
 
         return acpi_tables

 
-
     #
     # Dumps contents of ACPI table
     #
-

-[docs]
-    def dump_ACPI_table(self, name: str, isfile: bool = False) -> None:
+
[docs]    def dump_ACPI_table(self, name: str, isfile: bool = False) -> None:
         acpi_tables = self.get_parse_ACPI_table(name, isfile)
         for acpi_table in acpi_tables:
             (table_header, table, table_header_blob, table_blob) = acpi_table
@@ -573,7 +538,6 @@ 
Source code for chipsec.hal.acpi
             print_buffer_bytes(table_blob)
             logger().log('')

 
-
     # --------------------------------------------------------------------
     # Internal ACPI table parsing functions
     # --------------------------------------------------------------------
@@ -605,7 +569,6 @@ 
Source code for chipsec.hal.acpi
                 table = (ACPI_TABLES[signature])()
             table.parse(contents)
         return table

-
 

 
             

@@ -665,7 +628,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -685,8 +648,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/acpi_tables.html b/_modules/chipsec/hal/acpi_tables.html
index 4d4bec3d..df59e6a3 100644
--- a/_modules/chipsec/hal/acpi_tables.html
+++ b/_modules/chipsec/hal/acpi_tables.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.acpi_tables — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -74,23 +76,17 @@ 
Source code for chipsec.hal.acpi_tables
 from chipsec.hal.uefi_common import EFI_GUID_FMT, EFI_GUID_STR
 
 
-

-[docs]
-class ACPI_TABLE:
+
[docs]class ACPI_TABLE:
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         return

 
-
     def __str__(self) -> str:
         return """------------------------------------------------------------------
   Table Content
 ------------------------------------------------------------------
 """

 
-
 ########################################################################################################
 #
 # RSDP
@@ -106,12 +102,8 @@ 
Source code for chipsec.hal.acpi_tables
 assert ACPI_RSDP_EXT_SIZE == 36
 
 
-

-[docs]
-class RSDP(ACPI_TABLE):
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]class RSDP(ACPI_TABLE):
+
[docs]    def parse(self, table_content: bytes) -> None:
         if len(table_content) == ACPI_RSDP_SIZE:
             (self.Signature, self.Checksum, self.OEMID,
              self.Revision, self.RsdtAddress) = struct.unpack(ACPI_RSDP_FORMAT, table_content)
@@ -120,7 +112,6 @@ 
Source code for chipsec.hal.acpi_tables
              self.Revision, self.RsdtAddress, self.Length,
              self.XsdtAddress, self.ExtChecksum, self.Reserved) = struct.unpack(ACPI_RSDP_FORMAT + ACPI_RSDP_EXT_FORMAT, table_content)

 
-
     def __str__(self) -> str:
         default = ("==================================================================\n"
                    "  Root System Description Pointer (RSDP)\n"
@@ -139,12 +130,8 @@ 
Source code for chipsec.hal.acpi_tables
         return default
 
     # some sanity checking on RSDP
-

-[docs]
-    def is_RSDP_valid(self) -> bool:
-        return 0 != self.Checksum and (0x0 == self.Revision or 0x2 == self.Revision)

-

-
+
[docs]    def is_RSDP_valid(self) -> bool:
+        return 0 != self.Checksum and (0x0 == self.Revision or 0x2 == self.Revision)

 
 
 ########################################################################################################
@@ -158,9 +145,7 @@ 
Source code for chipsec.hal.acpi_tables
 ACPI_TABLE_SIZE_DMAR = struct.calcsize(ACPI_TABLE_FORMAT_DMAR)
 
 
-

-[docs]
-class DMAR (ACPI_TABLE):
+
[docs]class DMAR (ACPI_TABLE):
     def __init__(self):
         self.dmar_structures = []
         self.DMAR_TABLE_FORMAT = {
@@ -174,9 +159,7 @@ 
Source code for chipsec.hal.acpi_tables
             'SIDP_FORMAT': 'HHHH'
         }
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         off = ACPI_TABLE_SIZE_DMAR
         struct_fmt = '=HH'
         while off < len(table_content) - 1:
@@ -188,14 +171,13 @@ 
Source code for chipsec.hal.acpi_tables
         (self.HostAddrWidth, self.Flags, self.Reserved) = struct.unpack_from(ACPI_TABLE_FORMAT_DMAR, table_content)
         return

 
-
     def __str__(self) -> str:
         _str = f"""------------------------------------------------------------------
   DMAR Table Contents
 ------------------------------------------------------------------
-  Host Address Width  : {self.HostAddrWidth:d}
-  Flags               : 0x{self.Flags:02X}
-  Reserved            : {self.Reserved.hex()}
+  Host Address Width  : {self.HostAddrWidth:d}
+  Flags               : 0x{self.Flags:02X}
+  Reserved            : {self.Reserved.hex()}
 """
         _str += "\n  Remapping Structures:\n"
         for st in self.dmar_structures:
@@ -271,7 +253,6 @@ 
Source code for chipsec.hal.acpi_tables
             off += length
         return device_scope

 
-
 #
 # DMAR Device Scope
 #
@@ -291,109 +272,94 @@ 
Source code for chipsec.hal.acpi_tables
 }
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_DeviceScope(namedtuple('ACPI_TABLE_DMAR_DeviceScope', 'Type Length Flags Reserved EnumerationID StartBusNum Path')):
+
[docs]class ACPI_TABLE_DMAR_DeviceScope(namedtuple('ACPI_TABLE_DMAR_DeviceScope', 'Type Length Flags Reserved EnumerationID StartBusNum Path')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""      {DMAR_DS_TYPE[self.Type]} ({self.Type:02X}): Len: 0x{self.Length:02X}, Flags: 0x{self.Flags:02X}, Rsvd: 0x{self.Reserved:02X}, Enum ID: 0x{self.EnumerationID:02X}, Start Bus#: 0x{self.StartBusNum:02X}, Path: {self.Path.hex()}\n"""

 
-
 #
 # DMAR DMA Remapping Hardware Unit Definition (DRHD) Structure
 #
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_DRHD(namedtuple('ACPI_TABLE_DMAR_DRHD', 'Type Length Flags Reserved SegmentNumber RegisterBaseAddr DeviceScope')):
+
[docs]class ACPI_TABLE_DMAR_DRHD(namedtuple('ACPI_TABLE_DMAR_DRHD', 'Type Length Flags Reserved SegmentNumber RegisterBaseAddr DeviceScope')):
     __slots__ = ()
 
     def __str__(self) -> str:
         _str = f"""
   DMA Remapping Hardware Unit Definition (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Flags                 : 0x{self.Flags:02X}
-    Reserved              : 0x{self.Reserved:02X}
-    Segment Number        : 0x{self.SegmentNumber:04X}
-    Register Base Address : 0x{self.RegisterBaseAddr:016X}
+    Length                : 0x{self.Length:04X}
+    Flags                 : 0x{self.Flags:02X}
+    Reserved              : 0x{self.Reserved:02X}
+    Segment Number        : 0x{self.SegmentNumber:04X}
+    Register Base Address : 0x{self.RegisterBaseAddr:016X}
 """
         _str += '    Device Scope          :\n'
         for ds in self.DeviceScope:
             _str += str(ds)
         return _str

 
-
 #
 # DMAR Reserved Memory Range Reporting (RMRR) Structure
 #
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_RMRR(namedtuple('ACPI_TABLE_DMAR_RMRR', 'Type Length Reserved SegmentNumber RMRBaseAddr RMRLimitAddr DeviceScope')):
+
[docs]class ACPI_TABLE_DMAR_RMRR(namedtuple('ACPI_TABLE_DMAR_RMRR', 'Type Length Reserved SegmentNumber RMRBaseAddr RMRLimitAddr DeviceScope')):
     __slots__ = ()
 
     def __str__(self) -> str:
         _str = f"""
   Reserved Memory Range (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Reserved              : 0x{self.Reserved:04X}
-    Segment Number        : 0x{self.SegmentNumber:04X}
-    Reserved Memory Base  : 0x{self.RMRBaseAddr:016X}
-    Reserved Memory Limit : 0x{self.RMRLimitAddr:016X}
+    Length                : 0x{self.Length:04X}
+    Reserved              : 0x{self.Reserved:04X}
+    Segment Number        : 0x{self.SegmentNumber:04X}
+    Reserved Memory Base  : 0x{self.RMRBaseAddr:016X}
+    Reserved Memory Limit : 0x{self.RMRLimitAddr:016X}
 """
         _str += '    Device Scope          :\n'
         for ds in self.DeviceScope:
             _str += str(ds)
         return _str

-
 #
 # DMAR Root Port ATS Capability Reporting (ATSR) Structure
 #
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_ATSR(namedtuple('ACPI_TABLE_DMAR_ATSR', 'Type Length Flags Reserved SegmentNumber DeviceScope')):
+
[docs]class ACPI_TABLE_DMAR_ATSR(namedtuple('ACPI_TABLE_DMAR_ATSR', 'Type Length Flags Reserved SegmentNumber DeviceScope')):
     __slots__ = ()
 
     def __str__(self) -> str:
         _str = f"""
   Root Port ATS Capability (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Flags                 : 0x{self.Flags:02X}
-    Reserved (0)          : 0x{self.Reserved:02X}
-    Segment Number        : 0x{self.SegmentNumber:04X}
+    Length                : 0x{self.Length:04X}
+    Flags                 : 0x{self.Flags:02X}
+    Reserved (0)          : 0x{self.Reserved:02X}
+    Segment Number        : 0x{self.SegmentNumber:04X}
 """
         _str += '    Device Scope          :\n'
         for ds in self.DeviceScope:
             _str += str(ds)
         return _str

 
-
 #
 # DMAR Remapping Hardware Status Affinity (RHSA) Structure
 #
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_RHSA(namedtuple('ACPI_TABLE_DMAR_RHSA', 'Type Length Reserved RegisterBaseAddr ProximityDomain')):
+
[docs]class ACPI_TABLE_DMAR_RHSA(namedtuple('ACPI_TABLE_DMAR_RHSA', 'Type Length Reserved RegisterBaseAddr ProximityDomain')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Remapping Hardware Status Affinity (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Reserved (0)          : 0x{self.Reserved:08X}
-    Register Base Address : 0x{self.RegisterBaseAddr:016X}
-    Proximity Domain      : 0x{self.ProximityDomain:08X}
+    Length                : 0x{self.Length:04X}
+    Reserved (0)          : 0x{self.Reserved:08X}
+    Register Base Address : 0x{self.RegisterBaseAddr:016X}
+    Proximity Domain      : 0x{self.ProximityDomain:08X}
 """

 
 
-
 #
 # DMAR ACPI Name-space Device Declaration (ANDD) Structure
 #
@@ -402,37 +368,32 @@ 
Source code for chipsec.hal.acpi_tables
 assert 8 == ACPI_TABLE_DMAR_ANDD_SIZE
 
 
-

-[docs]
-class ACPI_TABLE_DMAR_ANDD(namedtuple('ACPI_TABLE_DMAR_ANDD', 'Type Length Reserved ACPIDevNum ACPIObjectName')):
+
[docs]class ACPI_TABLE_DMAR_ANDD(namedtuple('ACPI_TABLE_DMAR_ANDD', 'Type Length Reserved ACPIDevNum ACPIObjectName')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Remapping Hardware Status Affinity (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Reserved (0)          : {self.Reserved.hex()}
-    ACPI Device Number    : 0x{self.ACPIDevNum:02X}
-    ACPI Object Name      : {self.ACPIObjectName}
+    Length                : 0x{self.Length:04X}
+    Reserved (0)          : {self.Reserved.hex()}
+    ACPI Device Number    : 0x{self.ACPIDevNum:02X}
+    ACPI Object Name      : {self.ACPIObjectName}
 """

 
 
-
 #
 # DMAR SoC Integrated Address Translation Cache Reporting (SATC) Structure
 #
-

-[docs]
-class ACPI_TABLE_DMAR_SATC(namedtuple('ACPI_TABLE_DMAR_SATC', 'Type Length Flags Reserved SegmentNumber DeviceScope')):
+
[docs]class ACPI_TABLE_DMAR_SATC(namedtuple('ACPI_TABLE_DMAR_SATC', 'Type Length Flags Reserved SegmentNumber DeviceScope')):
     __slots__ = ()
 
     def __str__(self):
         _str = f"""
   SoC Integrated Address Translation Cache (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Flags                 : 0x{self.Flags:02X}
-    Reserved (0)          : 0x{self.Reserved:02X}
-    Segment Number        : 0x{self.SegmentNumber:016X}
+    Length                : 0x{self.Length:04X}
+    Flags                 : 0x{self.Flags:02X}
+    Reserved (0)          : 0x{self.Reserved:02X}
+    Segment Number        : 0x{self.SegmentNumber:016X}
 """
         _str += '    Device Scope          :\n'
         for ds in self.DeviceScope:
@@ -440,28 +401,24 @@ 
Source code for chipsec.hal.acpi_tables
         return _str

 
 
-
 #
 # DMAR SoC Integrated Address Translation Cache Reporting (SIDP) Structure
 #
-

-[docs]
-class ACPI_TABLE_DMAR_SIDP(namedtuple('ACPI_TABLE_DMAR_SIDP', 'Type Length Reserved SegmentNumber DeviceScope')):
+
[docs]class ACPI_TABLE_DMAR_SIDP(namedtuple('ACPI_TABLE_DMAR_SIDP', 'Type Length Reserved SegmentNumber DeviceScope')):
     __slots__ = ()
 
     def __str__(self):
         _str = f"""
   SoC Integrated Address Translation Cache Reporting Structure (0x{self.Type:04X}):
-    Length                : 0x{self.Length:04X}
-    Reserved (0)          : 0x{self.Reserved:02X}
-    Segment Number        : 0x{self.SegmentNumber:016X}
+    Length                : 0x{self.Length:04X}
+    Reserved (0)          : 0x{self.Reserved:02X}
+    Segment Number        : 0x{self.SegmentNumber:016X}
 """
         _str += '    Device Scope          :\n'
         for ds in self.DeviceScope:
             _str += str(ds)
         return _str

 
-
 ########################################################################################################
 #
 # APIC Table
@@ -473,9 +430,7 @@ 
Source code for chipsec.hal.acpi_tables
 ACPI_TABLE_SIZE_APIC = struct.calcsize(ACPI_TABLE_FORMAT_APIC)
 
 
-

-[docs]
-class APIC (ACPI_TABLE):
+
[docs]class APIC (ACPI_TABLE):
     def __init__(self):
         self.apic_structs = []
         self.ACPI_TABLE_FORMAT = {}
@@ -499,9 +454,7 @@ 
Source code for chipsec.hal.acpi_tables
             "GIC_REDISTRIBUTOR": '<BBHQI'
         }
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         (self.LAPICBase, self.Flags) = struct.unpack('=II', table_content[0: 8])
         cont = 8
         while cont < len(table_content) - 1:
@@ -512,22 +465,19 @@ 
Source code for chipsec.hal.acpi_tables
             cont += length
         return

 
-
     def __str__(self) -> str:
         apic_str = f"""------------------------------------------------------------------
   APIC Table Contents
 ------------------------------------------------------------------
-  Local APIC Base  : 0x{self.LAPICBase:016X}
-  Flags            : 0x{self.Flags:08X}
+  Local APIC Base  : 0x{self.LAPICBase:016X}
+  Flags            : 0x{self.Flags:08X}
 """
         apic_str += "\n  Interrupt Controller Structures:\n"
         for st in self.apic_structs:
             apic_str += str(st)
         return apic_str
 
-

-[docs]
-    def get_structure_APIC(self, value: int, DataStructure: bytes) -> str:
+
[docs]    def get_structure_APIC(self, value: int, DataStructure: bytes) -> str:
         if 0x00 == value:
             ret = ACPI_TABLE_APIC_PROCESSOR_LAPIC(*struct.unpack_from(self.APIC_TABLE_FORMAT["PROCESSOR_LAPIC"], DataStructure))
         elif 0x01 == value:
@@ -543,7 +493,7 @@ 
Source code for chipsec.hal.acpi_tables
         elif 0x06 == value:
             ret = ACPI_TABLE_APIC_IOSAPIC(*struct.unpack_from(self.APIC_TABLE_FORMAT["IOSAPIC"], DataStructure))
         elif 0x07 == value:
-            ret = ACPI_TABLE_APIC_PROCESSOR_LSAPIC(*struct.unpack_from(f'{self.APIC_TABLE_FORMAT["PROCESSOR_LSAPIC"]}{str(len(DataStructure) - 16)}s', DataStructure))
+            ret = ACPI_TABLE_APIC_PROCESSOR_LSAPIC(*struct.unpack_from(f'{self.APIC_TABLE_FORMAT["PROCESSOR_LSAPIC"]}{str(len(DataStructure) - 16)}s', DataStructure))
         elif 0x08 == value:
             ret = ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES(*struct.unpack_from(self.APIC_TABLE_FORMAT["PLATFORM_INTERRUPT_SOURCES"], DataStructure))
         elif 0x09 == value:
@@ -564,291 +514,244 @@ 
Source code for chipsec.hal.acpi_tables
 Reserved ....................................{value}"
 {DataStructure_str}"
 """
-        return str(ret)

-

-
+        return str(ret)

 
 
-

-[docs]
-class ACPI_TABLE_APIC_PROCESSOR_LAPIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_LAPIC', 'Type Length ACPIProcID APICID Flags')):
+
[docs]class ACPI_TABLE_APIC_PROCESSOR_LAPIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_LAPIC', 'Type Length ACPIProcID APICID Flags')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Processor Local APIC (0x00)
-    Type         : 0x{self.Type:02X}
-    Length       : 0x{self.Length:02X}
-    ACPI Proc ID : 0x{self.ACPIProcID:02X}
-    APIC ID      : 0x{self.APICID:02X}
-    Flags        : 0x{self.Flags:02X}
+    Type         : 0x{self.Type:02X}
+    Length       : 0x{self.Length:02X}
+    ACPI Proc ID : 0x{self.ACPIProcID:02X}
+    APIC ID      : 0x{self.APICID:02X}
+    Flags        : 0x{self.Flags:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_IOAPIC(namedtuple('ACPI_TABLE_APIC_IOAPIC', 'Type Length IOAPICID Reserved IOAPICAddr GlobalSysIntBase')):
+
[docs]class ACPI_TABLE_APIC_IOAPIC(namedtuple('ACPI_TABLE_APIC_IOAPIC', 'Type Length IOAPICID Reserved IOAPICAddr GlobalSysIntBase')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   I/O APIC (0x01)
-    Type                : 0x{self.Type:02X}
-    Length              : 0x{self.Length:02X}
-    Reserved            : 0x{self.IOAPICID:02X}
-    I/O APIC ID         : 0x{self.Reserved:02X}
-    I/O APIC Base       : 0x{self.IOAPICAddr:02X}
-    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
+    Type                : 0x{self.Type:02X}
+    Length              : 0x{self.Length:02X}
+    Reserved            : 0x{self.IOAPICID:02X}
+    I/O APIC ID         : 0x{self.Reserved:02X}
+    I/O APIC Base       : 0x{self.IOAPICAddr:02X}
+    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE(namedtuple('ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE', 'Type Length Bus Source GlobalSysIntBase Flags')):
+
[docs]class ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE(namedtuple('ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE', 'Type Length Bus Source GlobalSysIntBase Flags')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Interrupt Source Override (0x02)
-    Type                : 0x{self.Type:02X}
-    Length              : 0x{self.Length:02X}
-    Bus                 : 0x{self.Bus:02X}
-    Source              : 0x{self.Source:02X}
-    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
-    Flags               : 0x{self.Flags:02X}
+    Type                : 0x{self.Type:02X}
+    Length              : 0x{self.Length:02X}
+    Bus                 : 0x{self.Bus:02X}
+    Source              : 0x{self.Source:02X}
+    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
+    Flags               : 0x{self.Flags:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_NMI_SOURCE(namedtuple('ACPI_TABLE_APIC_NMI_SOURCE', 'Type Length Flags GlobalSysIntBase')):
+
[docs]class ACPI_TABLE_APIC_NMI_SOURCE(namedtuple('ACPI_TABLE_APIC_NMI_SOURCE', 'Type Length Flags GlobalSysIntBase')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Non-maskable Interrupt (NMI) Source (0x03)
-    Type                : 0x{self.Type:02X}
-    Length              : 0x{self.Length:02X}
-    Flags               : 0x{self.Flags:02X}
-    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
+    Type                : 0x{self.Type:02X}
+    Length              : 0x{self.Length:02X}
+    Flags               : 0x{self.Flags:02X}
+    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_LAPIC_NMI(namedtuple('ACPI_TABLE_APIC_LAPIC_NMI', 'Type Length ACPIProcessorID Flags LocalAPICLINT')):
+
[docs]class ACPI_TABLE_APIC_LAPIC_NMI(namedtuple('ACPI_TABLE_APIC_LAPIC_NMI', 'Type Length ACPIProcessorID Flags LocalAPICLINT')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Local APIC NMI (0x04)
-    Type              : 0x{self.Type:02X}
-    Length            : 0x{self.Length:02X}
-    ACPI Processor ID : 0x{self.ACPIProcessorID:02X}
-    Flags             : 0x{self.Flags:02X}
-    Local APIC LINT   : 0x{self.LocalAPICLINT:02X}
+    Type              : 0x{self.Type:02X}
+    Length            : 0x{self.Length:02X}
+    ACPI Processor ID : 0x{self.ACPIProcessorID:02X}
+    Flags             : 0x{self.Flags:02X}
+    Local APIC LINT   : 0x{self.LocalAPICLINT:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE(namedtuple('ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE', 'Type Length Reserved LocalAPICAddress')):
+
[docs]class ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE(namedtuple('ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE', 'Type Length Reserved LocalAPICAddress')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Local APIC Address Override (0x05)
-    Type               : 0x{self.Type:02X}
-    Length             : 0x{self.Length:02X}
-    Reserved           : 0x{self.Reserved:02X}
-    Local APIC Address : 0x{self.LocalAPICAddress:02X}
+    Type               : 0x{self.Type:02X}
+    Length             : 0x{self.Length:02X}
+    Reserved           : 0x{self.Reserved:02X}
+    Local APIC Address : 0x{self.LocalAPICAddress:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_IOSAPIC(namedtuple('ACPI_TABLE_APIC_IOSAPIC', 'Type Length IOAPICID Reserved GlobalSysIntBase IOSAPICAddress')):
+
[docs]class ACPI_TABLE_APIC_IOSAPIC(namedtuple('ACPI_TABLE_APIC_IOSAPIC', 'Type Length IOAPICID Reserved GlobalSysIntBase IOSAPICAddress')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   I/O SAPIC (0x06)
-    Type                : 0x{self.Type:02X}
-    Length              : 0x{self.Length:02X}
-    IO APIC ID          : 0x{self.IOAPICID:02X}
-    Reserved            : 0x{self.Reserved:02X}
-    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
-    IO SAPIC Address    : 0x{self.IOSAPICAddress:02X}
+    Type                : 0x{self.Type:02X}
+    Length              : 0x{self.Length:02X}
+    IO APIC ID          : 0x{self.IOAPICID:02X}
+    Reserved            : 0x{self.Reserved:02X}
+    Global Sys Int Base : 0x{self.GlobalSysIntBase:02X}
+    IO SAPIC Address    : 0x{self.IOSAPICAddress:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_PROCESSOR_LSAPIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_LSAPIC', 'Type Length ACPIProcID LocalSAPICID LocalSAPICEID Reserved Flags ACPIProcUIDValue ACPIProcUIDString'), ):
+
[docs]class ACPI_TABLE_APIC_PROCESSOR_LSAPIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_LSAPIC', 'Type Length ACPIProcID LocalSAPICID LocalSAPICEID Reserved Flags ACPIProcUIDValue ACPIProcUIDString'), ):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Local SAPIC (0x07)
-    Type                 : 0x{self.Type:02X}
-    Length               : 0x{self.Length:02X}
-    ACPI Proc ID         : 0x{self.ACPIProcID:02X}
-    Local SAPIC ID       : 0x{self.LocalSAPICID:02X}
-    Local SAPIC EID      : 0x{self.LocalSAPICEID:02X}
-    Reserved             : 0x{self.Reserved:02X}
-    Flags                : 0x{self.Flags:02X}
-    ACPI Proc UID Value  : 0x{self.ACPIProcUIDValue:02X}
-    ACPI Proc UID String : 0x{self.ACPIProcUIDString:02X}
+    Type                 : 0x{self.Type:02X}
+    Length               : 0x{self.Length:02X}
+    ACPI Proc ID         : 0x{self.ACPIProcID:02X}
+    Local SAPIC ID       : 0x{self.LocalSAPICID:02X}
+    Local SAPIC EID      : 0x{self.LocalSAPICEID:02X}
+    Reserved             : 0x{self.Reserved:02X}
+    Flags                : 0x{self.Flags:02X}
+    ACPI Proc UID Value  : 0x{self.ACPIProcUIDValue:02X}
+    ACPI Proc UID String : 0x{self.ACPIProcUIDString:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES(namedtuple('ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES', 'Type Length Flags InterruptType ProcID ProcEID IOSAPICVector GlobalSystemInterrupt PlatIntSourceFlags')):
+
[docs]class ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES(namedtuple('ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES', 'Type Length Flags InterruptType ProcID ProcEID IOSAPICVector GlobalSystemInterrupt PlatIntSourceFlags')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Platform Interrupt Sources (0x08)
-    Type                    : 0x{self.Type:02X}
-    Length                  : 0x{self.Length:02X}
-    Flags                   : 0x{self.Flags:02X}
-    Interrupt Type          : 0x{self.InterruptType:02X}
-    Proc ID                 : 0x{self.ProcID:02X}
-    Proc EID                : 0x{self.ProcEID:02X}
-    I/O SAPIC Vector        : 0x{self.IOSAPICVector:02X}
-    Global System Interrupt : 0x{self.GlobalSystemInterrupt:02X}
-    Plat Int Source Flags   : 0x{self.PlatIntSourceFlags:02X}
+    Type                    : 0x{self.Type:02X}
+    Length                  : 0x{self.Length:02X}
+    Flags                   : 0x{self.Flags:02X}
+    Interrupt Type          : 0x{self.InterruptType:02X}
+    Proc ID                 : 0x{self.ProcID:02X}
+    Proc EID                : 0x{self.ProcEID:02X}
+    I/O SAPIC Vector        : 0x{self.IOSAPICVector:02X}
+    Global System Interrupt : 0x{self.GlobalSystemInterrupt:02X}
+    Plat Int Source Flags   : 0x{self.PlatIntSourceFlags:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_PROCESSOR_Lx2APIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_Lx2APIC', 'Type Length Reserved x2APICID Flags ACPIProcUID')):
+
[docs]class ACPI_TABLE_APIC_PROCESSOR_Lx2APIC(namedtuple('ACPI_TABLE_APIC_PROCESSOR_Lx2APIC', 'Type Length Reserved x2APICID Flags ACPIProcUID')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Processor Local x2APIC (0x09)
-    Type          : 0x{self.Type:02X}
-    Length        : 0x{self.Length:02X}
-    Reserved      : 0x{self.Reserved:02X}
-    x2APIC ID     : 0x{self.x2APICID:02X}
-    Flags         : 0x{self.Flags:02X}
-    ACPI Proc UID : 0x{self.ACPIProcUID:02X}
+    Type          : 0x{self.Type:02X}
+    Length        : 0x{self.Length:02X}
+    Reserved      : 0x{self.Reserved:02X}
+    x2APIC ID     : 0x{self.x2APICID:02X}
+    Flags         : 0x{self.Flags:02X}
+    ACPI Proc UID : 0x{self.ACPIProcUID:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_Lx2APIC_NMI(namedtuple('ACPI_TABLE_APIC_Lx2APIC_NMI', 'Type Length Flags ACPIProcUID Localx2APICLINT Reserved')):
+
[docs]class ACPI_TABLE_APIC_Lx2APIC_NMI(namedtuple('ACPI_TABLE_APIC_Lx2APIC_NMI', 'Type Length Flags ACPIProcUID Localx2APICLINT Reserved')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   Local x2APIC NMI (0x0A)
-    Type              : 0x{self.Type:02X}
-    Length            : 0x{self.Length:02X}
-    Flags             : 0x{self.Flags:02X}
-    ACPI Proc UID     : 0x{self.ACPIProcUID:02X}
-    Local x2APIC LINT : 0x{self.Localx2APICLINT:02X}
-    Reserved          : 0x{self.Reserved:}
+    Type              : 0x{self.Type:02X}
+    Length            : 0x{self.Length:02X}
+    Flags             : 0x{self.Flags:02X}
+    ACPI Proc UID     : 0x{self.ACPIProcUID:02X}
+    Local x2APIC LINT : 0x{self.Localx2APICLINT:02X}
+    Reserved          : 0x{self.Reserved:}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_GICC_CPU(namedtuple('ACPI_TABLE_APIC_GICC_CPU', 'Type Length Reserved CPUIntNumber ACPIProcUID Flags ParkingProtocolVersion PerformanceInterruptGSIV ParkedAddress PhysicalAddress GICV GICH VGICMaintenanceINterrupt GICRBaseAddress MPIDR')):
+
[docs]class ACPI_TABLE_APIC_GICC_CPU(namedtuple('ACPI_TABLE_APIC_GICC_CPU', 'Type Length Reserved CPUIntNumber ACPIProcUID Flags ParkingProtocolVersion PerformanceInterruptGSIV ParkedAddress PhysicalAddress GICV GICH VGICMaintenanceINterrupt GICRBaseAddress MPIDR')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   GICC CPU Interface Structure (0x0B)
-    Type                       : 0x{self.Type:02X}
-    Length                     : 0x{self.Length:02X}
-    Reserved                   : 0x{self.Reserved:02X}
-    CPU Int Number             : 0x{self.CPUIntNumber:02X}
-    ACPI Proc UID              : 0x{self.ACPIProcUID:02X}
-    Flags                      : 0x{self.Flags:02X}
-    Parking Protocol Version   : 0x{self.ParkingProtocolVersion:02X}
-    Performance Interrupt GSIV : 0x{self.PerformanceInterruptGSIV:02X}
-    Parked Address             : 0x{self.ParkedAddress:02X}
-    Physical Address           : 0x{self.PhysicalAddress:02X}
-    GICV                       : 0x{self.GICV:02X}
-    GICH                       : 0x{self.GICH:02X}
-    VGIC Maintenance INterrupt : 0x{self.VGICMaintenanceINterrupt:02X}
-    GICR Base Address          : 0x{self.GICRBaseAddress:02X}
-    MPIDR                      : 0x{self.MPIDR:02X}
+    Type                       : 0x{self.Type:02X}
+    Length                     : 0x{self.Length:02X}
+    Reserved                   : 0x{self.Reserved:02X}
+    CPU Int Number             : 0x{self.CPUIntNumber:02X}
+    ACPI Proc UID              : 0x{self.ACPIProcUID:02X}
+    Flags                      : 0x{self.Flags:02X}
+    Parking Protocol Version   : 0x{self.ParkingProtocolVersion:02X}
+    Performance Interrupt GSIV : 0x{self.PerformanceInterruptGSIV:02X}
+    Parked Address             : 0x{self.ParkedAddress:02X}
+    Physical Address           : 0x{self.PhysicalAddress:02X}
+    GICV                       : 0x{self.GICV:02X}
+    GICH                       : 0x{self.GICH:02X}
+    VGIC Maintenance INterrupt : 0x{self.VGICMaintenanceINterrupt:02X}
+    GICR Base Address          : 0x{self.GICRBaseAddress:02X}
+    MPIDR                      : 0x{self.MPIDR:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_GIC_DISTRIBUTOR(namedtuple('ACPI_TABLE_APIC_GIC_DISTRIBUTOR', 'Type Length Reserved GICID PhysicalBaseAddress SystemVectorBase Reserved2 ')):
+
[docs]class ACPI_TABLE_APIC_GIC_DISTRIBUTOR(namedtuple('ACPI_TABLE_APIC_GIC_DISTRIBUTOR', 'Type Length Reserved GICID PhysicalBaseAddress SystemVectorBase Reserved2 ')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   GICD GIC Distributor Structure (0x0C)
-    Type                  : 0x{self.Type:02X}
-    Length                : 0x{self.Length:02X}
-    Reserved              : 0x{self.Reserved:02X}
-    GICID                 : 0x{self.GICID:02X}
-    Physical Base Address : 0x{self.PhysicalBaseAddress:02X}
-    System Vector Base    : 0x{self.SystemVectorBase:02X}
-    Reserved              : 0x{self.Reserved2:02X}
+    Type                  : 0x{self.Type:02X}
+    Length                : 0x{self.Length:02X}
+    Reserved              : 0x{self.Reserved:02X}
+    GICID                 : 0x{self.GICID:02X}
+    Physical Base Address : 0x{self.PhysicalBaseAddress:02X}
+    System Vector Base    : 0x{self.SystemVectorBase:02X}
+    Reserved              : 0x{self.Reserved2:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_GIC_MSI(namedtuple('ACPI_TABLE_APIC_GIC_MSI', 'Type Length Reserved GICMSIFrameID PhysicalBaseAddress Flags SPICount SPIBase')):
+
[docs]class ACPI_TABLE_APIC_GIC_MSI(namedtuple('ACPI_TABLE_APIC_GIC_MSI', 'Type Length Reserved GICMSIFrameID PhysicalBaseAddress Flags SPICount SPIBase')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   GICv2m MSI Frame (0x0D)
-    Type                  : 0x{self.Type:02X}
-    Length                : 0x{self.Length:02X}
-    Reserved              : 0x{self.Reserved:02X}
-    GIC MSI Frame ID      : 0x{self.GICMSIFrameID:02X}
-    Physical Base Address : 0x{self.PhysicalBaseAddress:02X}
-    Flags                 : 0x{self.Flags:02X}
-    SPI Count             : 0x{self.SPICount:02X}
-    SPI Base              : 0x{self.SPIBase:02X}
+    Type                  : 0x{self.Type:02X}
+    Length                : 0x{self.Length:02X}
+    Reserved              : 0x{self.Reserved:02X}
+    GIC MSI Frame ID      : 0x{self.GICMSIFrameID:02X}
+    Physical Base Address : 0x{self.PhysicalBaseAddress:02X}
+    Flags                 : 0x{self.Flags:02X}
+    SPI Count             : 0x{self.SPICount:02X}
+    SPI Base              : 0x{self.SPIBase:02X}
 """

 
 
-
-

-[docs]
-class ACPI_TABLE_APIC_GIC_REDISTRIBUTOR(namedtuple('ACPI_TABLE_APIC_GIC_REDISTRIBUTOR', 'Type Length Reserved DiscoverRangeBaseAdd DiscoverRangeLength')):
+
[docs]class ACPI_TABLE_APIC_GIC_REDISTRIBUTOR(namedtuple('ACPI_TABLE_APIC_GIC_REDISTRIBUTOR', 'Type Length Reserved DiscoverRangeBaseAdd DiscoverRangeLength')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
   GICR Redistributor Structure (0x0E)
-    Type                  : 0x{self.Type:02X}
-    Length                : 0x{self.Length:02X}
-    Reserved              : 0x{self.Reserved:02X}
-    Discover Range Base   : 0x{self.DiscoverRangeBaseAdd:02X}
-    Discover Range Length : 0x{self.DiscoverRangeLength:02X}
+    Type                  : 0x{self.Type:02X}
+    Length                : 0x{self.Length:02X}
+    Reserved              : 0x{self.Reserved:02X}
+    Discover Range Base   : 0x{self.DiscoverRangeBaseAdd:02X}
+    Discover Range Length : 0x{self.DiscoverRangeLength:02X}
 """

 
-
 ########################################################################################################
 #
 # XSDT Table
@@ -856,30 +759,24 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class XSDT (ACPI_TABLE):
+
[docs]class XSDT (ACPI_TABLE):
     def __init__(self):
         self.Entries = []
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         num_of_tables = len(table_content) // 8
         self.Entries = struct.unpack(f'={num_of_tables:d}Q', table_content)
         return

 
-
     def __str__(self) -> str:
         entries_str = ''.join([f'0x{addr:016X}\n' for addr in self.Entries])
         return f"""==================================================================
   Extended System Description Table (XSDT)
 ==================================================================
 ACPI Table Entries:
-{entries_str}
+{entries_str}
 """

 
-
 ########################################################################################################
 #
 # RSDT Table
@@ -887,30 +784,24 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class RSDT (ACPI_TABLE):
+
[docs]class RSDT (ACPI_TABLE):
     def __init__(self):
         self.Entries = []
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         num_of_tables = len(table_content) // 4
         self.Entries = struct.unpack(f'={num_of_tables:d}I', table_content)
         return

 
-
     def __str__(self) -> str:
         entries_str = ''.join([f'0x{addr:016X}\n' for addr in self.Entries])
         return f"""==================================================================
   Root System Description Table (RSDT)
 ==================================================================
 ACPI Table Entries:
-{entries_str}
+{entries_str}
 """

 
-
 ########################################################################################################
 #
 # FADT Table
@@ -918,9 +809,7 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class FADT (ACPI_TABLE):
+
[docs]class FADT (ACPI_TABLE):
     def __init__(self):
         self.dsdt = None
         self.x_dsdt = None
@@ -928,9 +817,7 @@ 
Source code for chipsec.hal.acpi_tables
         self.acpi_enable = None
         self.acpi_disable = None
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         self.dsdt = struct.unpack('<I', table_content[4:8])[0]
         self.smi = struct.unpack('<I', table_content[12:16])[0]
         self.acpi_enable = struct.unpack('B', table_content[16:17])[0]
@@ -941,10 +828,7 @@ 
Source code for chipsec.hal.acpi_tables
             if logger().HAL:
                 logger().log('[acpi] Cannot find X_DSDT entry in FADT.')

 
-
-

-[docs]
-    def get_DSDT_address_to_use(self) -> Optional[int]:
+
[docs]    def get_DSDT_address_to_use(self) -> Optional[int]:
         dsdt_address_to_use = None
         if self.x_dsdt is None:
             if self.dsdt != 0:
@@ -958,20 +842,18 @@ 
Source code for chipsec.hal.acpi_tables
                 dsdt_address_to_use = self.x_dsdt
         return dsdt_address_to_use

 
-
     def __str__(self) -> str:
         dsdt_str = f'0x{self.x_dsdt:016X}' if self.x_dsdt is not None else 'Not found'
         return f"""------------------------------------------------------------------
   Fixed ACPI Description Table (FADT) Contents
 ------------------------------------------------------------------
-  DSDT    : 0x{self.dsdt:08X}
-  X_DSDT  : {dsdt_str}
-  SMI_CMD : 0x{self.smi:04X}
-  ACPI_EN : 0x{self.acpi_enable:01X}
-  ACPI_DIS: 0x{self.acpi_disable:01X}
+  DSDT    : 0x{self.dsdt:08X}
+  X_DSDT  : {dsdt_str}
+  SMI_CMD : 0x{self.smi:04X}
+  ACPI_EN : 0x{self.acpi_enable:01X}
+  ACPI_DIS: 0x{self.acpi_disable:01X}
 """

 
-
 ########################################################################################################
 #
 # BGRT Table
@@ -979,15 +861,11 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class BGRT (ACPI_TABLE):
+
[docs]class BGRT (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         self.Version = struct.unpack('<H', table_content[0:2])[0]
         self.Status = struct.unpack('<b', table_content[2:3])[0]
         self.ImageType = struct.unpack('<b', table_content[3:4])[0]
@@ -1009,20 +887,18 @@ 
Source code for chipsec.hal.acpi_tables
         else:
             self.ImageTypeStr = 'Reserved'

 
-
     def __str__(self) -> str:
         return f"""
 ------------------------------------------------------------------
-  Version                       : {self.Version:d}
-  Status                        : {self.Status:d}
-   Clockwise Orientation Offset : {self.OrientationOffset}
-  Image Type                    : {self.ImageType:d} {self.ImageTypeStr}
-  Image Address                 : 0x{self.ImageAddress:016X}
-  Image Offset X                : 0x{self.ImageOffsetX:08X}
-  Image Offset Y                : 0x{self.ImageOffsetY:08X}
+  Version                       : {self.Version:d}
+  Status                        : {self.Status:d}
+   Clockwise Orientation Offset : {self.OrientationOffset}
+  Image Type                    : {self.ImageType:d} {self.ImageTypeStr}
+  Image Address                 : 0x{self.ImageAddress:016X}
+  Image Offset X                : 0x{self.ImageOffsetX:08X}
+  Image Offset Y                : 0x{self.ImageOffsetY:08X}
 """

 
-
 ########################################################################################################
 #
 # BERT Table
@@ -1030,16 +906,12 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class BERT (ACPI_TABLE):
+
[docs]class BERT (ACPI_TABLE):
     def __init__(self, bootRegion: bytes) -> None:
         self.bootRegion = bootRegion
         return
 
-

-[docs]
-    def parseSectionType(self, table_content: bytes) -> str:
+
[docs]    def parseSectionType(self, table_content: bytes) -> str:
         # Processor Generic: {0x9876CCAD, 0x47B4, 0x4bdb, {0xB6, 0x5E, 0x16, 0xF1, 0x93, 0xC4, 0xF3, 0xDB}}
         # Processor Specific: IA32/X64:{0xDC3EA0B0, 0xA144, 0x4797, {0xB9, 0x5B, 0x53, 0xFA, 0x24, 0x2B, 0x6E, 0x1D}}
         # Processor Specific: IPF: {0xe429faf1, 0x3cb7, 0x11d4, {0xb, 0xca, 0x7, 0x00, 0x80,0xc7, 0x3c, 0x88, 0x81}}
@@ -1057,7 +929,7 @@ 
Source code for chipsec.hal.acpi_tables
         val3 = struct.unpack('<L', table_content[8:12])[0]
         val4 = struct.unpack('<L', table_content[12:16])[0]
         results = f'''0x{val1:08X} 0x{val2:08X} 0x{val3:08X} 0x{val4:08X} - '''
-        """if val1 == 0x9876CCAD and val2 == 0x47B4 and val3 == 0x4bdb and val4 in [0xB6, 0x5E, 0x16, 0xF1, 0x93, 0xC4, 0xF3, 0xDB]:
+        """if val1 == 0x9876CCAD and val2 == 0x47B4 and val3 == 0x4bdb and val4 in [0xB6, 0x5E, 0x16, 0xF1, 0x93, 0xC4, 0xF3, 0xDB]:
             return results + '''Generic Processor'''
         elif val1 == 0xDC3EA0B0 and val2 == 0xA144 and val3 == 0x4797 and val4 in [0xB9, 0x5B, 0x53, 0xFA, 0x24, 0x2B, 0x6E, 0x1D]:
             return results + '''Processor Specific: IA32/X64'''
@@ -1083,10 +955,7 @@ 
Source code for chipsec.hal.acpi_tables
             return results + '''IOMMU Specific DMAr Section'''"""
         return results + '''Unknown'''

 
-
-

-[docs]
-    def parseTime(self, table_content: bytes) -> str:
+
[docs]    def parseTime(self, table_content: bytes) -> str:
         seconds = struct.unpack('<B', table_content[0:1])[0]
         minutes = struct.unpack('<B', table_content[1:2])[0]
         hours = struct.unpack('<B', table_content[2:3])[0]
@@ -1100,10 +969,7 @@ 
Source code for chipsec.hal.acpi_tables
             precision_str = '(time is percise and correlates to time of event)'
         return f''' {hours:d}:{minutes:d}:{seconds:d} {month:d}/{day:d}/{century:d}{year:d} [m/d/y] {precision_str}'''

 
-
-

-[docs]
-    def parseGenErrorEntries(self, table_content: bytes) -> str:
+
[docs]    def parseGenErrorEntries(self, table_content: bytes) -> str:
         errorSeverities = ['Recoverable', 'Fatal', 'Corrected', 'None', 'Unknown severity entry']
         sectionType = self.parseSectionType(table_content[0:16])
         errorSeverity = struct.unpack('<L', table_content[16:20])[0]
@@ -1132,30 +998,27 @@ 
Source code for chipsec.hal.acpi_tables
         if FRU_Id1 == 0 and FRU_Id2 == 0 and FRU_Id3 == 0 and FRU_Id4 == 0:
             FRU_Id_str = ' - Default value, invalid FRU ID'
         return f'''
-      Section Type                                  : {sectionType}
-      Error Severity                                : {errorSeverity} - {errorSeverity_str}
-      Revision                                      : 0x{revision:04X}{revision_str}
-      Validation Bits                               : 0x{validationBits:02X}
-      Flags                                         : 0x{flags:02X}
-        Primary                                     : 0x{flags & 1:02X}
-        Containment Warning                         : 0x{flags & 2:02X}
-        Reset                                       : 0x{flags & 4:02X}
-        Error Threshold Exceeded                    : 0x{flags & 8:02X}
-        Resource Not Accessible                     : 0x{flags & 16:02X}
-        Latent Error                                : 0x{flags & 32:02X}
-        Propagated                                  : 0x{flags & 64:02X}
-        Overflow                                    : 0x{flags & 128:02X}
-        Reserved                                    : 0x{flags & 256:02X}
+      Section Type                                  : {sectionType}
+      Error Severity                                : {errorSeverity} - {errorSeverity_str}
+      Revision                                      : 0x{revision:04X}{revision_str}
+      Validation Bits                               : 0x{validationBits:02X}
+      Flags                                         : 0x{flags:02X}
+        Primary                                     : 0x{flags & 1:02X}
+        Containment Warning                         : 0x{flags & 2:02X}
+        Reset                                       : 0x{flags & 4:02X}
+        Error Threshold Exceeded                    : 0x{flags & 8:02X}
+        Resource Not Accessible                     : 0x{flags & 16:02X}
+        Latent Error                                : 0x{flags & 32:02X}
+        Propagated                                  : 0x{flags & 64:02X}
+        Overflow                                    : 0x{flags & 128:02X}
+        Reserved                                    : 0x{flags & 256:02X}
       Error Data Length                             : 0x{errDataLen:08X} ( {errDataLen:d} )
-      FRU Id                                        : {FRU_Id1} {FRU_Id2} {FRU_Id3} {FRU_Id4}{FRU_Id_str}
-      FRU Text                                      : {FRU_Text}
-      Timestamp                                     : {timestamp:d} - {timestamp_str}
+      FRU Id                                        : {FRU_Id1} {FRU_Id2} {FRU_Id3} {FRU_Id4}{FRU_Id_str}
+      FRU Text                                      : {FRU_Text}
+      Timestamp                                     : {timestamp:d} - {timestamp_str}
       Data                                          : {data}'''

 
-
-

-[docs]
-    def parseErrorBlock(self, table_content: bytes) -> None:
+
[docs]    def parseErrorBlock(self, table_content: bytes) -> None:
         errorSeverities = ['Recoverable', 'Fatal', 'Corrected', 'None', 'Unknown severity entry']
         blockStatus = struct.unpack('<L', table_content[0:4])[0]
         rawDataOffset = struct.unpack('<L', table_content[4:8])[0]
@@ -1168,38 +1031,33 @@ 
Source code for chipsec.hal.acpi_tables
             errorSeverity_str = errorSeverities[errorSeverity]
         self.BootRegion = f'''
 Generic Error Status Block
-    Block Status                                    : 0x{blockStatus:08X}
-      Correctable Error Valid                       : 0x{blockStatus & 1:08X}
-      Uncorrectable Error Valid                     : 0x{blockStatus & 2:08X}
-      Multiple Uncorrectable Errors                 : 0x{blockStatus & 4:08X}
-      Multiple Correctable Errors                   : 0x{blockStatus & 8:08X}
-      Error Data Entry Count                        : 0x{blockStatus & 1023:08X}
-      Reserved                                      : 0x{blockStatus & 262143:08X}
+    Block Status                                    : 0x{blockStatus:08X}
+      Correctable Error Valid                       : 0x{blockStatus & 1:08X}
+      Uncorrectable Error Valid                     : 0x{blockStatus & 2:08X}
+      Multiple Uncorrectable Errors                 : 0x{blockStatus & 4:08X}
+      Multiple Correctable Errors                   : 0x{blockStatus & 8:08X}
+      Error Data Entry Count                        : 0x{blockStatus & 1023:08X}
+      Reserved                                      : 0x{blockStatus & 262143:08X}
     Raw Data Offset                                 : 0x{rawDataOffset:08X} ( {rawDataOffset:d} )
     Raw Data Length                                 : 0x{rawDataLen:08X} ( {rawDataLen:d} )
     Data Length                                     : 0x{dataLen:08X} ( {dataLen:d} )
-    Error Severity                                  : 0x{errorSeverity:08X} - {errorSeverity_str}
-    Generic Error Data Entries{genErrorDataEntries}
+    Error Severity                                  : 0x{errorSeverity:08X} - {errorSeverity_str}
+    Generic Error Data Entries{genErrorDataEntries}
 '''

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         self.BootRegionLen = struct.unpack('<L', table_content[0:4])[0]
         self.BootRegionAddr = struct.unpack('<Q', table_content[4:12])[0]
         self.parseErrorBlock(self.bootRegion)

 
-
     def __str__(self) -> str:
         return f"""
 ------------------------------------------------------------------
-  Boot Region Length                                : {self.BootRegionLen:d}
-  Boot Region Address	                            : 0x{self.BootRegionAddr:016X}
-  Boot Region - {self.BootRegion}
+  Boot Region Length                                : {self.BootRegionLen:d}
+  Boot Region Address	                            : 0x{self.BootRegionAddr:016X}
+  Boot Region - {self.BootRegion}
 """

 
-
 ########################################################################################################
 #
 # EINJ Table
@@ -1207,21 +1065,14 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class EINJ (ACPI_TABLE):
+
[docs]class EINJ (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parseAddress(self, table_content: bytes) -> str:
+
[docs]    def parseAddress(self, table_content: bytes) -> str:
         return str(GAS(table_content))

 
-
-

-[docs]
-    def parseInjection(self, table_content: bytes) -> None:
+
[docs]    def parseInjection(self, table_content: bytes) -> None:
         errorInjectActions = ['BEGIN_INJECTION_OPERATION', 'GET_TRIGGER_ERROR_ACTION', 'SET_ERROR_TYPE', 'GET_ERROR_TYPE', 'END_OPERATION', 'EXECUTE_OPERATION',
                               'CHECK_BUSY_STATUS', 'GET_COMMAND_STATUS', 'SET_ERROR_TYPE_WITH_ADDRESS', 'GET_EXECUTE_OPERATION_TIMING', 'not recognized as valid aciton']
         injectionInstructions = ['READ_REGISTER', 'READ_REGISTER_VALUE', 'WRITE_REGISTER', 'WRITE_REGISTER_VALUE', 'NOOP', 'not recognized as valid instruction']
@@ -1255,28 +1106,22 @@ 
Source code for chipsec.hal.acpi_tables
             reserved_str = ''
         self.results_str += f"""
   Injection Instruction Entry
-    Injection Action                                : 0x{injectionAction:02X} ( {injectionAction:d} ) - {injectionAction_str}
-    Instruction                                     : 0x{instruction:02X} ( {instruction:d} ) - {instruction_str}
-    Flags                                           : 0x{flags:02X} ( {flags:d} ){flags_str}
-    Reserved                                        : 0x{reserved:02X} ( {reserved:d} ){reserved_str}
-    Register Region - {registerRegion}
+    Injection Action                                : 0x{injectionAction:02X} ( {injectionAction:d} ) - {injectionAction_str}
+    Instruction                                     : 0x{instruction:02X} ( {instruction:d} ) - {instruction_str}
+    Flags                                           : 0x{flags:02X} ( {flags:d} ){flags_str}
+    Reserved                                        : 0x{reserved:02X} ( {reserved:d} ){reserved_str}
+    Register Region - {registerRegion}
     Value                                           : 0x{value:016X} ( {value:d} )
     Mask                                            : 0x{mask:016X} ( {mask:d} )
     """

 
-
-

-[docs]
-    def parseInjectionActionTable(self, table_contents: bytes, numInjections: int) -> None:
+
[docs]    def parseInjectionActionTable(self, table_contents: bytes, numInjections: int) -> None:
         curInjection = 0
         while curInjection < numInjections:
             self.parseInjection(table_contents[curInjection * 32:(curInjection + 1) * 32])
             curInjection += 1

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         injectionHeaderSz = struct.unpack('<L', table_content[0:4])[0]
         injectionFlags = struct.unpack('<B', table_content[4:5])[0]
         reserved1 = struct.unpack('<B', table_content[5:6])[0]
@@ -1295,17 +1140,15 @@ 
Source code for chipsec.hal.acpi_tables
         self.results_str = f"""
 ------------------------------------------------------------------
   Injection Header Size                             : 0x{injectionHeaderSz:016X} ( {injectionHeaderSz:d} )
-  Injection Flags                                   : 0x{injectionFlags:02X}{injection_str}
-  Reserved                                          : 0x{reserved:06X}{reserved_str}
+  Injection Flags                                   : 0x{injectionFlags:02X}{injection_str}
+  Reserved                                          : 0x{reserved:06X}{reserved_str}
   Injection Entry Count                             : 0x{injectionEntryCount:08X} ( {injectionEntryCount:d} )
   Injection Instruction Entries
 """

 
-
     def __str__(self) -> str:
         return self.results_str

 
-
 ########################################################################################################
 #
 # ERST Table
@@ -1313,30 +1156,20 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class ERST (ACPI_TABLE):
+
[docs]class ERST (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parseAddress(self, table_content: bytes) -> str:
+
[docs]    def parseAddress(self, table_content: bytes) -> str:
         return str(GAS(table_content))

 
-
-

-[docs]
-    def parseActionTable(self, table_content: bytes, instrCountEntry: int) -> None:
+
[docs]    def parseActionTable(self, table_content: bytes, instrCountEntry: int) -> None:
         curInstruction = 0
         while curInstruction < instrCountEntry:
             self.parseInstructionEntry(table_content[32 * curInstruction:])
             curInstruction += 1

 
-
-

-[docs]
-    def parseInstructionEntry(self, table_content: bytes) -> None:
+
[docs]    def parseInstructionEntry(self, table_content: bytes) -> None:
         serializationInstr_str = ''
         serializationAction = struct.unpack('<B', table_content[0:1])[0]
         instruction = struct.unpack('<B', table_content[1:2])[0]
@@ -1369,19 +1202,16 @@ 
Source code for chipsec.hal.acpi_tables
 
         self.results_str += f'''
     Serialization Intruction Entry
-      Serialized Action                             : 0x{serializationAction:02X} - {serializationAction_str}
-      Instruction                                   : 0x{instruction:02X} - {serializationInstr_str}
-      Flags                                         : 0x{flags:02X}{flags_str}
-      Reserved                                      : 0x{reserved:02X}{reserved_str}
-      Register Region - {registerRegion}
-      Value                                         : 0x{value:016X}
-      Mask                                          : 0x{mask:016X}
+      Serialized Action                             : 0x{serializationAction:02X} - {serializationAction_str}
+      Instruction                                   : 0x{instruction:02X} - {serializationInstr_str}
+      Flags                                         : 0x{flags:02X}{flags_str}
+      Reserved                                      : 0x{reserved:02X}{reserved_str}
+      Register Region - {registerRegion}
+      Value                                         : 0x{value:016X}
+      Mask                                          : 0x{mask:016X}
     '''

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         headerSz = struct.unpack('<L', table_content[0:4])[0]
         reserved = struct.unpack('<L', table_content[4:8])[0]
         instrCountEntry = struct.unpack('<L', table_content[8:12])[0]
@@ -1392,17 +1222,15 @@ 
Source code for chipsec.hal.acpi_tables
         self.results_str = f"""
 ------------------------------------------------------------------
   Serialization Header Size                       : 0x{headerSz:08X} ( {headerSz:d} )
-  Reserved                                        : 0x{reserved:08X}{reserved_str}
+  Reserved                                        : 0x{reserved:08X}{reserved_str}
   Instruction Count Entry                         : 0x{instrCountEntry:08X} ( {instrCountEntry:d} )
   Serialization Action Table
 """
         self.parseActionTable(table_content[12:], instrCountEntry)

 
-
     def __str__(self) -> str:
         return self.results_str

 
-
 ########################################################################################################
 #
 # HEST Table
@@ -1410,15 +1238,11 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class HEST (ACPI_TABLE):
+
[docs]class HEST (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parseErrEntry(self, table_content: bytes) -> Optional[int]:
+
[docs]    def parseErrEntry(self, table_content: bytes) -> Optional[int]:
         _type = struct.unpack('<H', table_content[0:2])[0]
         if _type == 0:  # Arch Machine Check Execption Structure
             return self.parseAMCES(table_content)
@@ -1432,10 +1256,7 @@ 
Source code for chipsec.hal.acpi_tables
             return self.parseGHESS(table_content, _type)
         return

 
-
-

-[docs]
-    def parseNotify(self, table_content: bytes) -> str:
+
[docs]    def parseNotify(self, table_content: bytes) -> str:
         types = ['Polled', 'External Interrupt', 'Local Interrupt', 'SCI', 'NMI', 'CMCI', 'MCE', 'GPI-Signal',
                  'ARMv8 SEA', 'ARMv8 SEI', 'External Interrupt - GSIV', 'Software Delicated Exception', 'Reserved']
         errorType = struct.unpack('<B', table_content[0:1])[0]
@@ -1458,27 +1279,24 @@ 
Source code for chipsec.hal.acpi_tables
             vector_str = 'Specifies the GSIV triggerd by error source'
 
         return f"""Hardware Error Notification Structure
-      Type                                        : {errorType:d} - {typeStr}
-      Length                                      : 0x{length:02X}
-      Configuration Write Enable                  : 0x{configWrEn:04X}
-        Type                                      : {configWrEn & 1:d}
-        Poll Interval                             : {configWrEn & 2:d}
-        Switch To Polling Threshold Value         : {configWrEn & 4:d}
-        Switch To Polling Threshold Window        : {configWrEn & 8:d}
-        Error Threshold Value                     : {configWrEn & 16:d}
-        Error Threshold Window                    : {configWrEn & 32:d}
+      Type                                        : {errorType:d} - {typeStr}
+      Length                                      : 0x{length:02X}
+      Configuration Write Enable                  : 0x{configWrEn:04X}
+        Type                                      : {configWrEn & 1:d}
+        Poll Interval                             : {configWrEn & 2:d}
+        Switch To Polling Threshold Value         : {configWrEn & 4:d}
+        Switch To Polling Threshold Window        : {configWrEn & 8:d}
+        Error Threshold Value                     : {configWrEn & 16:d}
+        Error Threshold Window                    : {configWrEn & 32:d}
       Poll Interval                               : {pollInterval:d} milliseconds
-      Vector                                      : {vector:d}{vector_str}
-      Switch To Polling Threshold Value           : 0x{switchPollingThreshVal:08X}
+      Vector                                      : {vector:d}{vector_str}
+      Switch To Polling Threshold Value           : 0x{switchPollingThreshVal:08X}
       Switch To Polling Threshold Window          : {errThreshVal:d} milliseconds
-      Error Threshold Value                       : 0x{errThreshVal:08X}
+      Error Threshold Value                       : 0x{errThreshVal:08X}
       Error Threshold Window                      : {errThreshWind:d} milliseconds
       """

 
-
-

-[docs]
-    def machineBankParser(self, table_content: bytes) -> None:
+
[docs]    def machineBankParser(self, table_content: bytes) -> None:
         bankNum = struct.unpack('<B', table_content[0:1])[0]
         clearStatus = struct.unpack('<B', table_content[1:2])[0]
         statusDataFormat = struct.unpack('<B', table_content[2:3])[0]
@@ -1521,26 +1339,20 @@ 
Source code for chipsec.hal.acpi_tables
             miscRegMSTAddr_str = ' - Ignore'
 
         self.resultsStr += f"""Machine Check Error Bank Structure
-      Bank Number                                 : 0x{bankNum:04X}
-      Clear Status On Initialization              : 0x{clearStatus:04X} - {clearStatus_str}
-      Status Data Format                          : 0x{statusDataFormat:04X} - {statusDataFormat_str}
-      Reserved                                    : 0x{reserved1:04X}
-      Control Register MSR Address                : 0x{controlRegMsrAddr:04X}{controlRegMsrAddr_str}
-      Control Init Data                           : 0x{controlInitData:04X}
-      Status Register MSR Address                 : 0x{statusRegMSRAddr:04X}{statusRegMSRAddr_str}
-      Address Register MSR Address                : 0x{addrRegMSRAddr:04X}{addrRegMSRAddr_str}
+      Bank Number                                 : 0x{bankNum:04X}
+      Clear Status On Initialization              : 0x{clearStatus:04X} - {clearStatus_str}
+      Status Data Format                          : 0x{statusDataFormat:04X} - {statusDataFormat_str}
+      Reserved                                    : 0x{reserved1:04X}
+      Control Register MSR Address                : 0x{controlRegMsrAddr:04X}{controlRegMsrAddr_str}
+      Control Init Data                           : 0x{controlInitData:04X}
+      Status Register MSR Address                 : 0x{statusRegMSRAddr:04X}{statusRegMSRAddr_str}
+      Address Register MSR Address                : 0x{addrRegMSRAddr:04X}{addrRegMSRAddr_str}
       Misc Register MSR Address                   : 0x{miscRegMSTAddr:04X}{miscRegMSTAddr_str}"""

 
-
-

-[docs]
-    def parseAddress(self, table_content: bytes) -> str:
+
[docs]    def parseAddress(self, table_content: bytes) -> str:
         return str(GAS(table_content))

 
-
-

-[docs]
-    def parseAMCES(self, table_content: bytes) -> int:
+
[docs]    def parseAMCES(self, table_content: bytes) -> int:
         sourceID = struct.unpack('<H', table_content[2:4])[0]
         reserved1 = struct.unpack('<H', table_content[4:6])[0]
         flags = struct.unpack('<B', table_content[6:7])[0]
@@ -1577,17 +1389,17 @@ 
Source code for chipsec.hal.acpi_tables
 
         self.resultsStr += f"""
   Architecture Machine Check Exception Structure
-    Source ID                                     : 0x{sourceID:04X}
-    Reserved                                      : 0x{reserved1:04X}
-    Flags                                         : 0x{flags:02X}
-    FIRMWARE_FIRST                                : {firmware_first} - {firmware_first_str}
-    GHES_ASSIST                                   : {ghes_assist} - {ghes_assist_str}
-    Enabled                                       : 0x{enabled:02X}
-    Number of Records to Pre-allocate             : 0x{recordsToPreAllocate:08X}
-    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
-    Global Capability Init Data                   : 0x{globalCapabilityInitData:016X}
-    Number of Hardware Banks                      : 0x{numHardwareBanks:02X}
-    Reserved                                      : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X} 0x{reserved2_4:02X} 0x{reserved2_5:02X} 0x{reserved2_6:02X} 0x{reserved2_7:02X}
+    Source ID                                     : 0x{sourceID:04X}
+    Reserved                                      : 0x{reserved1:04X}
+    Flags                                         : 0x{flags:02X}
+    FIRMWARE_FIRST                                : {firmware_first} - {firmware_first_str}
+    GHES_ASSIST                                   : {ghes_assist} - {ghes_assist_str}
+    Enabled                                       : 0x{enabled:02X}
+    Number of Records to Pre-allocate             : 0x{recordsToPreAllocate:08X}
+    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
+    Global Capability Init Data                   : 0x{globalCapabilityInitData:016X}
+    Number of Hardware Banks                      : 0x{numHardwareBanks:02X}
+    Reserved                                      : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X} 0x{reserved2_4:02X} 0x{reserved2_5:02X} 0x{reserved2_6:02X} 0x{reserved2_7:02X}
     """
         curBankNum = 0
         while curBankNum < numHardwareBanks:
@@ -1595,10 +1407,7 @@ 
Source code for chipsec.hal.acpi_tables
             curBankNum += 1
         return 40 + numHardwareBanks * 28

 
-
-

-[docs]
-    def parseAMCS(self, table_content: bytes, _type: int) -> int:
+
[docs]    def parseAMCS(self, table_content: bytes, _type: int) -> int:
         sourceID = struct.unpack('<H', table_content[2:4])[0]
         reserved1 = struct.unpack('<H', table_content[4:6])[0]
         flags = struct.unpack('<B', table_content[6:7])[0]
@@ -1638,18 +1447,18 @@ 
Source code for chipsec.hal.acpi_tables
             title = 'Architecture Deferred Machine Check Structure'
 
         self.resultsStr += f"""
-    {title}
-    Source ID         				  : 0x{sourceID:04X}
-    Reserved                                      : 0x{reserved1:04X}
-    Flags                                         : 0x{flags:02X}{flags_str}
-      FIRMWARE_FIRST                              : {firmware_first} - {firmware_first_str}
-      GHES_ASSIST                                 : {ghes_assist} - {ghes_assist_str}
-    Enabled                                       : 0x{enabled:02X}
-    Number of Records to Pre-allocate             : 0x{recordsToPreAllocate:08X}
-    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
-    {notificationStructure}
-    Number of Hardware Banks                      : 0x{numHardwareBanks:02X}
-    Reserved                                      : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X}
+    {title}
+    Source ID         				  : 0x{sourceID:04X}
+    Reserved                                      : 0x{reserved1:04X}
+    Flags                                         : 0x{flags:02X}{flags_str}
+      FIRMWARE_FIRST                              : {firmware_first} - {firmware_first_str}
+      GHES_ASSIST                                 : {ghes_assist} - {ghes_assist_str}
+    Enabled                                       : 0x{enabled:02X}
+    Number of Records to Pre-allocate             : 0x{recordsToPreAllocate:08X}
+    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
+    {notificationStructure}
+    Number of Hardware Banks                      : 0x{numHardwareBanks:02X}
+    Reserved                                      : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X}
 
     """
         currBank = 0
@@ -1658,10 +1467,7 @@ 
Source code for chipsec.hal.acpi_tables
             currBank += 1
         return 48 + numHardwareBanks * 28

 
-
-

-[docs]
-    def parseNMIStructure(self, table_content: bytes) -> int:
+
[docs]    def parseNMIStructure(self, table_content: bytes) -> int:
         sourceID = struct.unpack('<H', table_content[2:4])[0]
         reserved = struct.unpack('<L', table_content[4:8])[0]
         numRecordsToPreAllocate = struct.unpack('<L', table_content[8:12])[0]
@@ -1675,18 +1481,15 @@ 
Source code for chipsec.hal.acpi_tables
 
         self.resultsStr += f"""
   Architecture NMI Error Structure
-    Source ID                                     : 0x{sourceID:04X}
-    Reserved                                      : 0x{reserved:08X}{reserved_str}
-    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
-    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
-    Max Raw Data Length                           : 0x{maxRawDataLength:08X}
+    Source ID                                     : 0x{sourceID:04X}
+    Reserved                                      : 0x{reserved:08X}{reserved_str}
+    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
+    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
+    Max Raw Data Length                           : 0x{maxRawDataLength:08X}
     """
         return 20

 
-
-

-[docs]
-    def parsePCIe(self, table_content: bytes, _type: int) -> int:
+
[docs]    def parsePCIe(self, table_content: bytes, _type: int) -> int:
         sourceID = struct.unpack('<H', table_content[2:4])[0]
         reserved1 = struct.unpack('<H', table_content[4:6])[0]
         flags = struct.unpack('<B', table_content[6:7])[0]
@@ -1714,8 +1517,8 @@ 
Source code for chipsec.hal.acpi_tables
             secondaryUncorrErrServ = struct.unpack('<L', table_content[48:52])[0]
             secondaryAdvCapabAndControl = struct.unpack('<L', table_content[52:56])[0]
             extra_str = f'''
-    Secondary Uncorrectable Error Mask            : 0x{secondaryUncorrErrMask:08X}
-    Secondary Uncorrectable Error Severity        : 0x{secondaryUncorrErrServ:08X}
+    Secondary Uncorrectable Error Mask            : 0x{secondaryUncorrErrMask:08X}
+    Secondary Uncorrectable Error Severity        : 0x{secondaryUncorrErrServ:08X}
     Secondary Advanced Capabilities and Control   : 0x{secondaryAdvCapabAndControl:08X}'''
             size = 56
         else:
@@ -1751,31 +1554,28 @@ 
Source code for chipsec.hal.acpi_tables
             isFirmware_str = ' - This field should be ignored since FIRMWARE_FIRST is set'
 
         self.resultsStr += f"""
-  {title}
-    Source ID                                     : 0x{sourceID:04X}
-    Reserved                                      : 0x{reserved1:08X}
-    Flags                                         : 0x{flags:02X}{flags_str}
-      FIRMWARE_FIRST                              : {firmware_first} - {firmware_first_str} {isFirmware_str}
-      GLOBAL                                      : {global_flag} - {global_flag_str}
-    Enabled                                       : 0x{enabled:08X}
-    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
-    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
-    Bus                                           : 0x{bus:08X}
-    Device                                        : 0x{device:04X}{isGlobal_str}
-    Function                                      : 0x{function:04X}{isGlobal_str}
-    Device Control                                : 0x{deviceControl:04X}
-    Reserved                                      : 0x{reserved2:04X}{reserved2_str}
-    Uncorrectable Error Mask                      : 0x{uncorrectableErrorMask:08X}
-    Uncorrected Error Severity                    : 0x{uncorrectableErrorServerity:08X}
-    Corrected Error Mask                          : 0x{correctableErrorMask:08X}
-    Advanced Error Capabilities and Control       : 0x{advancedErrorCapabilitiesAndControl:08X}{extra_str}
+  {title}
+    Source ID                                     : 0x{sourceID:04X}
+    Reserved                                      : 0x{reserved1:08X}
+    Flags                                         : 0x{flags:02X}{flags_str}
+      FIRMWARE_FIRST                              : {firmware_first} - {firmware_first_str} {isFirmware_str}
+      GLOBAL                                      : {global_flag} - {global_flag_str}
+    Enabled                                       : 0x{enabled:08X}
+    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
+    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
+    Bus                                           : 0x{bus:08X}
+    Device                                        : 0x{device:04X}{isGlobal_str}
+    Function                                      : 0x{function:04X}{isGlobal_str}
+    Device Control                                : 0x{deviceControl:04X}
+    Reserved                                      : 0x{reserved2:04X}{reserved2_str}
+    Uncorrectable Error Mask                      : 0x{uncorrectableErrorMask:08X}
+    Uncorrected Error Severity                    : 0x{uncorrectableErrorServerity:08X}
+    Corrected Error Mask                          : 0x{correctableErrorMask:08X}
+    Advanced Error Capabilities and Control       : 0x{advancedErrorCapabilitiesAndControl:08X}{extra_str}
     """
         return size

 
-
-

-[docs]
-    def parseGHESS(self, table_content: bytes, _type: int) -> int:
+
[docs]    def parseGHESS(self, table_content: bytes, _type: int) -> int:
         sourceID = struct.unpack('<H', table_content[2:4])[0]
         relatedSourceID = struct.unpack('<H', table_content[4:6])[0]
         flags = struct.unpack('<B', table_content[6:7])[0]
@@ -1795,8 +1595,8 @@ 
Source code for chipsec.hal.acpi_tables
             readAckPresv = struct.unpack('<Q', table_content[76:84])[0]
             readAckWr = struct.unpack('<Q', table_content[84:88])[0]
             extra_str = f'''
-    Read Ack Register - {readAckReg_str}
-    Read Ack Preserve                             : 0x{readAckPresv:016X}
+    Read Ack Register - {readAckReg_str}
+    Read Ack Preserve                             : 0x{readAckPresv:016X}
     Read Ack Write                                : 0x{readAckWr:016X}'''
         if relatedSourceID == 65535:
             relatedSourceID_str = 'Does not represent an alternate souce'
@@ -1804,28 +1604,25 @@ 
Source code for chipsec.hal.acpi_tables
             relatedSourceID_str = ''
 
         self.resultsStr += f"""
-  {title}
-    Source ID                                     : 0x{sourceID:04X}
-    Related Source Id                             : 0x{relatedSourceID:08X}{relatedSourceID_str}
+  {title}
+    Source ID                                     : 0x{sourceID:04X}
+    Related Source Id                             : 0x{relatedSourceID:08X}{relatedSourceID_str}
     Flags                                         : 0x{flags:02X} - Reserved
-    Enabled                                       : 0x{enabled:02X}
-    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
-    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
-    Max Raw Data Length                           : 0x{maxRawDataLength:08X}
-    Error Status Address - {address_str}
-    {notification_str}
-    Error Status Block Length                     : 0x{errStatusBlockLen:08X}{extra_str}
+    Enabled                                       : 0x{enabled:02X}
+    Number of Records to Pre-Allocate             : 0x{numRecordsToPreAllocate:08X}
+    Max Sections Per Record                       : 0x{maxSectorsPerRecord:08X}
+    Max Raw Data Length                           : 0x{maxRawDataLength:08X}
+    Error Status Address - {address_str}
+    {notification_str}
+    Error Status Block Length                     : 0x{errStatusBlockLen:08X}{extra_str}
     """
         return 64

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         self.ErrorSourceCount = struct.unpack('<L', table_content[0:4])[0]
         self.resultsStr = f"""
 ------------------------------------------------------------------
-  Error Source Count                              : {self.ErrorSourceCount}
+  Error Source Count                              : {self.ErrorSourceCount}
 """
         nextTable = 4
         currErrSource = 0
@@ -1835,53 +1632,38 @@ 
Source code for chipsec.hal.acpi_tables
                 nextTable += table_entry
             currErrSource += 1

 
-
     def __str__(self) -> str:
         return self.resultsStr

 
 
-
 ########################################################################################################
 #
 # SPMI Table
 #
 ########################################################################################################
 
-

-[docs]
-class SPMI (ACPI_TABLE):
+
[docs]class SPMI (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parseAddress(self, table_content: bytes) -> str:
+
[docs]    def parseAddress(self, table_content: bytes) -> str:
         return str(GAS(table_content))

 
-
-

-[docs]
-    def parseNonUID(self, table_content: bytes) -> str:
+
[docs]    def parseNonUID(self, table_content: bytes) -> str:
         pciSegGrpNum = struct.unpack('<B', table_content[0:1])[0]
         pciBusNum = struct.unpack('<B', table_content[1:2])[0]
         pciDevNum = struct.unpack('<B', table_content[2:3])[0]
         pciFuncNum = struct.unpack('<B', table_content[3:4])[0]
-        return f'''  PCI Segment GroupNumber                                 : 0x{pciSegGrpNum:02X}
-  PCI Bus Number                                          : 0x{pciBusNum:02X}
-  PCI Device Number                                       : 0x{pciDevNum:02X}
+        return f'''  PCI Segment GroupNumber                                 : 0x{pciSegGrpNum:02X}
+  PCI Bus Number                                          : 0x{pciBusNum:02X}
+  PCI Device Number                                       : 0x{pciDevNum:02X}
   PCI Function Number                                     : 0x{pciFuncNum:02X}'''

 
-
-

-[docs]
-    def parseUID(self, table_content: bytes) -> str:
+
[docs]    def parseUID(self, table_content: bytes) -> str:
         uid = struct.unpack('<L', table_content[0:4])[0]
         return f'''  UID                                                     : 0x{uid:02X}'''

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         interfaceType = struct.unpack('<B', table_content[0:1])[0]
         reserved1 = struct.unpack('<B', table_content[1:2])[0]
         specRev = struct.unpack('<B', table_content[2:3])[0]
@@ -1931,46 +1713,40 @@ 
Source code for chipsec.hal.acpi_tables
         self.results = f'''==================================================================
   Service Processor Management Interface Description Table ( SPMI )
 ==================================================================
-  Interface Type                                          : 0x{interfaceType:02X} - {intTypeStr}
+  Interface Type                                          : 0x{interfaceType:02X} - {intTypeStr}
   Reserved                                                : 0x{reserved1:02X} - Must always be 01h to be compatible with any software implementing previous versions of the spec
-  Specification Revision (version)                        : {specRevStr}
-  Interrupt Type                                          : 0x{interruptType:04X}
-    SCI triggered through GPE                             : 0x{intType_0:02X} - {intTypeSCIGPE}
-    I/0 APIC/SAPIC interrupt (Global System Interrupt)    : 0x{intType_1:02X} - {intTypeIO}
+  Specification Revision (version)                        : {specRevStr}
+  Interrupt Type                                          : 0x{interruptType:04X}
+    SCI triggered through GPE                             : 0x{intType_0:02X} - {intTypeSCIGPE}
+    I/0 APIC/SAPIC interrupt (Global System Interrupt)    : 0x{intType_1:02X} - {intTypeIO}
     Reserved                                              : 0x{intType_other:02X} - Must be 0
-  GPE                                                     : 0x{gpe:02X}{GPE_str}
+  GPE                                                     : 0x{gpe:02X}{GPE_str}
   Reserved                                                : 0x{reserved2:02X} - should be 00h
-  PCI Device Flag                                         : 0x{pciDeviceFlag:02X}
-    PCI Device Flag                                       : {pciDeviceFlag_0:d} {pci_str}
+  PCI Device Flag                                         : 0x{pciDeviceFlag:02X}
+    PCI Device Flag                                       : {pciDeviceFlag_0:d} {pci_str}
     Reserved                                              : {pciDeviceFlag_reserved:d} - must be 0
-  Global System Interrupt                                 : 0x{globalSysInter:08X}{globalSysInt_str}
-  Base Address - {baseAdder}
-{otherStr}
-  Reserved                                                : 0x{reserved3:02X}
+  Global System Interrupt                                 : 0x{globalSysInter:08X}{globalSysInt_str}
+  Base Address - {baseAdder}
+{otherStr}
+  Reserved                                                : 0x{reserved3:02X}
 
 '''

 
-
     def __str__(self) -> str:
         return self.results

 
 
-
 ########################################################################################################
 #
 # RASF Table
 #
 ########################################################################################################
 
-

-[docs]
-class RASF (ACPI_TABLE):
+
[docs]class RASF (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         rpcci1 = struct.unpack('<B', table_content[0:1])[0]
         rpcci2 = struct.unpack('<B', table_content[1:2])[0]
         rpcci3 = struct.unpack('<B', table_content[2:3])[0]
@@ -1986,31 +1762,25 @@ 
Source code for chipsec.hal.acpi_tables
         self.results = f'''==================================================================
   ACPI RAS Feature Table ( RASF )
 ==================================================================
-  RASF Platform Communication Channel Identifier          : 0x{rpcci1:02X} 0x{rpcci2:02X} 0x{rpcci3:02X} 0x{rpcci4:02X} 0x{rpcci5:02X} 0x{rpcci6:02X} 0x{rpcci7:02X} 0x{rpcci8:02X} 0x{rpcci9:02X} 0x{rpcci10:02X} 0x{rpcci11:02X} 0x{rpcci12:02X}
+  RASF Platform Communication Channel Identifier          : 0x{rpcci1:02X} 0x{rpcci2:02X} 0x{rpcci3:02X} 0x{rpcci4:02X} 0x{rpcci5:02X} 0x{rpcci6:02X} 0x{rpcci7:02X} 0x{rpcci8:02X} 0x{rpcci9:02X} 0x{rpcci10:02X} 0x{rpcci11:02X} 0x{rpcci12:02X}
 
 '''

 
-
     def __str__(self) -> str:
         return self.results

 
 
-
 ########################################################################################################
 #
 # MSCT Table
 #
 ########################################################################################################
 
-

-[docs]
-class MSCT (ACPI_TABLE):
+
[docs]class MSCT (ACPI_TABLE):
     def __init__(self):
         return
 
-

-[docs]
-    def parseProx(self, table_content: bytes, val: int) -> str:
+
[docs]    def parseProx(self, table_content: bytes, val: int) -> str:
         rev = struct.unpack('<B', table_content[0:1])[0]
         length = struct.unpack('<B', table_content[1:2])[0]
         maxDomRangeL = struct.unpack('<L', table_content[2:6])[0]
@@ -2027,17 +1797,14 @@ 
Source code for chipsec.hal.acpi_tables
     Maximum Proximity Domain Informaiton Structure[{val:d}]
       Revision                                              : 0x{rev:02X} ( {rev:d} )
       Length                                                : 0x{length:02X} ( {length:d} )
-      Proximity Domain Range (low)                          : 0x{maxDomRangeL:04X}
-      Proximity Domain Range (high)                         : 0x{maxDomRangeH:04X}
-      Maximum Processor Capacity                            : 0x{maxProcCap:04X} ( {maxProcCap:d} ){maxProcCap_str}
-      Maximum Memory Capacity                               : 0x{maxMemCap:016X} ( {maxMemCap:d} ) bytes {maxMemCap_str}
+      Proximity Domain Range (low)                          : 0x{maxDomRangeL:04X}
+      Proximity Domain Range (high)                         : 0x{maxDomRangeH:04X}
+      Maximum Processor Capacity                            : 0x{maxProcCap:04X} ( {maxProcCap:d} ){maxProcCap_str}
+      Maximum Memory Capacity                               : 0x{maxMemCap:016X} ( {maxMemCap:d} ) bytes {maxMemCap_str}
 
 '''

 
-
-

-[docs]
-    def parseProxDomInfoStruct(self, table_contents: bytes, num: int) -> str:
+
[docs]    def parseProxDomInfoStruct(self, table_contents: bytes, num: int) -> str:
         val = 0
         result = ''
         while val < num:
@@ -2045,10 +1812,7 @@ 
Source code for chipsec.hal.acpi_tables
             val = val + 1
         return result

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         offsetProxDomInfo = struct.unpack('<L', table_content[0:4])[0]
         maxNumProxDoms = struct.unpack('<L', table_content[4:8])[0]
         maxNumClockDoms = struct.unpack('<L', table_content[8:12])[0]
@@ -2057,37 +1821,31 @@ 
Source code for chipsec.hal.acpi_tables
         self.results = f'''==================================================================
   Maximum System Characteristics Table ( MSCT )
 ==================================================================
-  Offset to Proximity Domain Information Structure        : 0x{offsetProxDomInfo:08X}
+  Offset to Proximity Domain Information Structure        : 0x{offsetProxDomInfo:08X}
   Maximum Number of Proximity Domains                     : 0x{maxNumProxDoms:08X} ( {maxNumProxDoms:d} )
   Maximum Number of Clock Domains                         : 0x{maxNumClockDoms:08X} ( {maxNumClockDoms:d} )
-  Maximum Physical Address                                : 0x{maxPhysAddr:016X}
-  Proximity Domain  Information Structure{proxDomInfoStructStr}
+  Maximum Physical Address                                : 0x{maxPhysAddr:016X}
+  Proximity Domain  Information Structure{proxDomInfoStructStr}
 
 '''

 
-
     def __str__(self) -> str:
         return self.results

 
 
-
 ########################################################################################################
 #
 # NFIT Table
 #
 ########################################################################################################
 
-

-[docs]
-class NFIT (ACPI_TABLE):
+
[docs]class NFIT (ACPI_TABLE):
     def __init__(self, header):
         length = struct.unpack('<L', header[4:8])[0]
         self.total_length = length
         return
 
-

-[docs]
-    def platCapStruct(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def platCapStruct(self, tableLen: int, table_content: bytes) -> str:
         highestValidCap = struct.unpack('<B', table_content[4:5])[0]
         reserved1_1 = struct.unpack('<B', table_content[5:6])[0]
         reserved1_2 = struct.unpack('<B', table_content[6:7])[0]
@@ -2116,20 +1874,17 @@ 
Source code for chipsec.hal.acpi_tables
         return f'''
     Platform Capabilities Structure [Type 7]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      Highest Valid Capability                                    : 0x{highestValidCap:02X}
-      Reserved                                                    : 0x{reserved1_1:02X} 0x{reserved1_2:02X} 0x{reserved1_3:02X}
-      Capabilities                                                : 0x{capabilities:08X}
-        CPU Cache Flush to NVDIMM Durability on Power Loss        : 0x{cap1:08X} - {cap1_str}
-        Mem Controller Flush to NVDIMM Durability on Power Loss   : 0x{cap2:08X} - {cap2_str}
-        Byte Addressible Persistent Mem Hw Mirroring Capable      : 0x{cap3:08X} - {cap3_str}
-        Reserved                                                  : 0x{capRes:08X}
-      Reserved                                                    : 0x{reserved2:08X}
+      Highest Valid Capability                                    : 0x{highestValidCap:02X}
+      Reserved                                                    : 0x{reserved1_1:02X} 0x{reserved1_2:02X} 0x{reserved1_3:02X}
+      Capabilities                                                : 0x{capabilities:08X}
+        CPU Cache Flush to NVDIMM Durability on Power Loss        : 0x{cap1:08X} - {cap1_str}
+        Mem Controller Flush to NVDIMM Durability on Power Loss   : 0x{cap2:08X} - {cap2_str}
+        Byte Addressible Persistent Mem Hw Mirroring Capable      : 0x{cap3:08X} - {cap3_str}
+        Reserved                                                  : 0x{capRes:08X}
+      Reserved                                                    : 0x{reserved2:08X}
 '''

 
-
-

-[docs]
-    def flushHintAddrStruct(self, tableLen: int, table_content: bytes) -> Tuple[int, str]:
+
[docs]    def flushHintAddrStruct(self, tableLen: int, table_content: bytes) -> Tuple[int, str]:
         nfitDevHandle = struct.unpack('<L', table_content[4:8])[0]
         numFlushHintAddr = struct.unpack('<L', table_content[4:8])[0]
         reserved = struct.unpack('<L', table_content[4:8])[0]
@@ -2138,21 +1893,18 @@ 
Source code for chipsec.hal.acpi_tables
         while curLine < numFlushHintAddr:
             lineInfo = struct.unpack('<Q', table_content[curLine * 8 + 8:curLine * 8 + 16])[0]
             lines += f'''
-        Flush Hint Address {curLine + 1:d}                                     : 0x{lineInfo:016X} '''
+        Flush Hint Address {curLine + 1:d}                                     : 0x{lineInfo:016X} '''
             curLine += 1
         return (curLine - 1) * 8 + 16, f'''
     Flush Hint Address Structure [Type 6]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      NFIT Device Handle                                          : 0x{nfitDevHandle:08X}
+      NFIT Device Handle                                          : 0x{nfitDevHandle:08X}
       Number of Flush Hint Addresses in this Structure            : 0x{numFlushHintAddr:08X} ( {numFlushHintAddr:d} )
-      Reserved                                                    : 0x{reserved:08X}
-      Flush Hint Addresses{lines}
+      Reserved                                                    : 0x{reserved:08X}
+      Flush Hint Addresses{lines}
 '''

 
-
-

-[docs]
-    def nvdimmBlockDataWindowsRegionStruct(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def nvdimmBlockDataWindowsRegionStruct(self, tableLen: int, table_content: bytes) -> str:
         nvdimmControlRegionStructureIndex = struct.unpack('<H', table_content[4:6])[0]
         numBlockDataWindows = struct.unpack('<H', table_content[6:8])[0]
         blockDataWindowsStartOffset = struct.unpack('<Q', table_content[8:16])[0]
@@ -2170,10 +1922,7 @@ 
Source code for chipsec.hal.acpi_tables
       Start Addr for 1st Block in Block Accessible Mem            : 0x{begAddr:016X} ( {begAddr:d} bytes )
 '''

 
-
-

-[docs]
-    def nvdimmControlRegionStructMark(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def nvdimmControlRegionStructMark(self, tableLen: int, table_content: bytes) -> str:
         nvdimmControlRegionStructureIndex = struct.unpack('<H', table_content[4:6])[0]
         vendorID = struct.unpack('<H', table_content[6:8])[0]
         deviceID = struct.unpack('<H', table_content[8:10])[0]
@@ -2210,12 +1959,12 @@ 
Source code for chipsec.hal.acpi_tables
             reserved2_5 = struct.unpack('<B', table_content[78:79])[0]
             reserved2_6 = struct.unpack('<B', table_content[79:80])[0]
             cont_str = f'''      Size of Block Control Windows                               : 0x{szBlckControlWindow:016X} ({szBlckControlWindow:d} bytes)
-      Command Reg Offset in Block Control Windows                 : 0x{commandRegOffset:016X}
-      Size of Command Register in Block Control Windows           : 0x{szCommandReg:016X}
-      Status Register Offset in Block Control Windows             : 0x{statusRegOffset:016X}
-      Size of Status Register in Block Control Windows            : 0x{szStatus:016X}
-      NVDIMM Control Region Flag                                  : 0x{nvdimmControlRegionFl:04X}
-      Reserved                                                    : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X} 0x{reserved2_4:02X} 0x{reserved2_5:02X} 0x{reserved2_6:02X}
+      Command Reg Offset in Block Control Windows                 : 0x{commandRegOffset:016X}
+      Size of Command Register in Block Control Windows           : 0x{szCommandReg:016X}
+      Status Register Offset in Block Control Windows             : 0x{statusRegOffset:016X}
+      Size of Status Register in Block Control Windows            : 0x{szStatus:016X}
+      NVDIMM Control Region Flag                                  : 0x{nvdimmControlRegionFl:04X}
+      Reserved                                                    : 0x{reserved2_1:02X} 0x{reserved2_2:02X} 0x{reserved2_3:02X} 0x{reserved2_4:02X} 0x{reserved2_5:02X} 0x{reserved2_6:02X}
       {cont_str}'''
         valid_0 = validFields & 1
         valid_str = ''
@@ -2226,31 +1975,28 @@ 
Source code for chipsec.hal.acpi_tables
         return f'''
     NVDIMM Control Region Structure [Type 4]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      NVDIMM Control Region Structure Index                       : 0x{nvdimmControlRegionStructureIndex:04X}
-      Vendor ID                                                   : 0x{vendorID:04X}
-      Device ID                                                   : 0x{deviceID:04X}
-      Revision ID                                                 : 0x{revID:04X}
-      Subsystem Vendor ID                                         : 0x{subsystemVendorID:04X}
-      Subsystem Device ID                                         : 0x{subsysDevID:04X}
-      Subsystem Revision ID                                       : 0x{subsysRevID:04X}
-      Valid Fields                                                : 0x{validFields:02X}
-        Bit[0]                                                    : {valid_0}{valid_str}
-      Manufacturing Location                                      : 0x{manLocation:02X}{valid_man_str}
-      Manufacturing Date                                          : 0x{manDate:04X}{valid_man_str}
-      Reserved                                                    : 0x{reserved:04X}
-      Serial Number                                               : 0x{serialNum:08X}
-      Region Format Interface Code                                : 0x{regionFormatInterfaceCode:04X}
-        Reserved                                                  : 0x{rfic_r1:02X}
-        Function Interface Field                                  : 0x{rfic_fif:02X}
-        Reserved                                                  : 0x{rfic_r2:02X}
-        Function Class Field                                      : 0x{rfic_fcf:02X}
-      Number of Block Control Windows                             : 0x{numBlockControlWindows:08X}
+      NVDIMM Control Region Structure Index                       : 0x{nvdimmControlRegionStructureIndex:04X}
+      Vendor ID                                                   : 0x{vendorID:04X}
+      Device ID                                                   : 0x{deviceID:04X}
+      Revision ID                                                 : 0x{revID:04X}
+      Subsystem Vendor ID                                         : 0x{subsystemVendorID:04X}
+      Subsystem Device ID                                         : 0x{subsysDevID:04X}
+      Subsystem Revision ID                                       : 0x{subsysRevID:04X}
+      Valid Fields                                                : 0x{validFields:02X}
+        Bit[0]                                                    : {valid_0}{valid_str}
+      Manufacturing Location                                      : 0x{manLocation:02X}{valid_man_str}
+      Manufacturing Date                                          : 0x{manDate:04X}{valid_man_str}
+      Reserved                                                    : 0x{reserved:04X}
+      Serial Number                                               : 0x{serialNum:08X}
+      Region Format Interface Code                                : 0x{regionFormatInterfaceCode:04X}
+        Reserved                                                  : 0x{rfic_r1:02X}
+        Function Interface Field                                  : 0x{rfic_fif:02X}
+        Reserved                                                  : 0x{rfic_r2:02X}
+        Function Class Field                                      : 0x{rfic_fcf:02X}
+      Number of Block Control Windows                             : 0x{numBlockControlWindows:08X}
 '''

 
-
-

-[docs]
-    def smbiosManagementInfo(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def smbiosManagementInfo(self, tableLen: int, table_content: bytes) -> str:
         smbios_tables = ['BIOS Information', 'System Information', 'Baseboard (or Module) Information', 'System Enclosure or Chassis', 'Processor Information', 'Memory Controller Information, obsolete', 'Memory Module Information, obsolete', 'Cache Information', 'Port Connector Information', 'System Slots', 'On Board Devices Information, obsolete', 'OEM Strings', 'System Confirguration Options', 'BIOS Language Information', 'Group Associations', 'System Event Log', 'Physical Memory Array', 'Memory Device', '32-Bit Memory Error Information', 'Memory Array Mapped Address', 'Memory Device Mapped Address',
                          'Built-in Pointing Device', 'Portable Battery', 'System Reset', 'Hardware Security', 'System Power Controls', 'Voltage Probe', 'Cooling Device', 'Temperature Probe', 'Electrical Current Probe', 'Out-of-Band Remote Address', 'Boot Integrity Services (BIS) Entry Point', 'System Boot Information', '64-Bit Mmemory Error Information', 'Management Device', 'Management Device Component', 'Management Device Threshold Data', 'Memory Channel', 'IPMI Device Information', 'System Power Supply', 'Additional Information', 'Onboard Devices Extended Information', 'Mangement Controller Host Interface']
         reserved = struct.unpack('<L', table_content[4:8])[0]
@@ -2259,14 +2005,11 @@ 
Source code for chipsec.hal.acpi_tables
         return f'''
     SMBIOS Management Information Structure [Type 3]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      Reserved                                                    : 0x{reserved:08X}
+      Reserved                                                    : 0x{reserved:08X}
       ----Unable to further at this time.----
 '''  # TODO

 
-
-

-[docs]
-    def interleave(self, tableLen: int, table_content: bytes) -> Tuple[int, str]:
+
[docs]    def interleave(self, tableLen: int, table_content: bytes) -> Tuple[int, str]:
         interleaveStructureIndex = struct.unpack('<H', table_content[4:6])[0]
         reserved = struct.unpack('<H', table_content[6:8])[0]
         numLinesDescribed = struct.unpack('<L', table_content[8:12])[0]
@@ -2276,21 +2019,18 @@ 
Source code for chipsec.hal.acpi_tables
         while curLine < numLinesDescribed:
             lineInfo = struct.unpack('<L', table_content[curLine * 4 + 16:curLine * 4 + 20])[0]
             lines += f'''
-        Line {curLine + 1:d} Offset                                            : 0x{lineInfo:08X} ( {lineInfo:d} bytes )'''
+        Line {curLine + 1:d} Offset                                            : 0x{lineInfo:08X} ( {lineInfo:d} bytes )'''
             curLine += 1
         return (curLine - 1) * 4 + 20, f'''
     Interleave Structure [Type 2]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      Reserved                                                    : 0x{reserved:04X}
+      Reserved                                                    : 0x{reserved:04X}
       Number of Lines Described                                   : 0x{numLinesDescribed:08X} ( {numLinesDescribed:d} )
       Line Size                                                   : 0x{lineSz:08X} ( {lineSz:d} bytes )
-      Lines {lines}
+      Lines {lines}
 '''

 
-
-

-[docs]
-    def parseMAP(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def parseMAP(self, tableLen: int, table_content: bytes) -> str:
         nfitDeviceHandle = struct.unpack('<L', table_content[4:8])[0]
         nvdimmPhysID = struct.unpack('<H', table_content[8:10])[0]
         nvdimmRegionID = struct.unpack('<H', table_content[10:12])[0]
@@ -2306,24 +2046,21 @@ 
Source code for chipsec.hal.acpi_tables
         return f'''
     NVDIMM Region Mapping Structure [Type 1]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      NFIT Device Handle                                          : 0x{nfitDeviceHandle:08X}
-      NVDIMM Physical ID                                          : 0x{nvdimmPhysID:04X}
-      NVDIMM Region ID                                            : 0x{nvdimmRegionID:04X}
-      SPA Range Structure Index                                   : 0x{spaRangeStructureIndex:04X}
-      NVDIMM Control Region Structure Index                       : 0x{nvdimmControlRegionSz:016X}
-      NVDIMM Region Size                                          : 0x{nvdimmRegionSz:016X}
-      Region Offset                                               : 0x{regionOffset:016X}
-      NVDIMM Physical Address Region Base                         : 0x{nvdimmPhysicalAddressRegionBase:016X}
-      Interleave Structure Index                                  : 0x{interleaveStructIndex:04X}
-      Interleave Ways                                             : 0x{interleaveWays:04X}
-      NVDIMM State Flags                                          : 0x{nvdimmStateFlags:04X}
-      Reserved                                                    : 0x{reserve:04X}
+      NFIT Device Handle                                          : 0x{nfitDeviceHandle:08X}
+      NVDIMM Physical ID                                          : 0x{nvdimmPhysID:04X}
+      NVDIMM Region ID                                            : 0x{nvdimmRegionID:04X}
+      SPA Range Structure Index                                   : 0x{spaRangeStructureIndex:04X}
+      NVDIMM Control Region Structure Index                       : 0x{nvdimmControlRegionSz:016X}
+      NVDIMM Region Size                                          : 0x{nvdimmRegionSz:016X}
+      Region Offset                                               : 0x{regionOffset:016X}
+      NVDIMM Physical Address Region Base                         : 0x{nvdimmPhysicalAddressRegionBase:016X}
+      Interleave Structure Index                                  : 0x{interleaveStructIndex:04X}
+      Interleave Ways                                             : 0x{interleaveWays:04X}
+      NVDIMM State Flags                                          : 0x{nvdimmStateFlags:04X}
+      Reserved                                                    : 0x{reserve:04X}
 '''

 
-
-

-[docs]
-    def parseSPA(self, tableLen: int, table_content: bytes) -> str:
+
[docs]    def parseSPA(self, tableLen: int, table_content: bytes) -> str:
         volitileMemGUID = [0x7305944f, 0xfdda, 0x44e3, 0xb1, 0x6c, 0x3f, 0x22, 0xd2, 0x52, 0xe5, 0xd0]
         byteAddrPMGUID = [0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33, 0x18, 0xb7, 0x8c, 0xdb]
         nvdimmControlRegionGUID = [0x92f701f6, 0x13b4, 0x405d, 0x91, 0x0b, 0x29, 0x93, 0x67, 0xe8, 0x23, 0x4c]
@@ -2408,23 +2145,20 @@ 
Source code for chipsec.hal.acpi_tables
         return f'''
     System Physical Address (SPA) Range Structure [Type 1]
       Length                                                      : 0x{tableLen:04X} ( {tableLen:d} bytes )
-      SPA Range Structure Index                                   : 0x{spaRangeStructure:04X}{spaRangeStructure_str}
-      Flags                                                       : 0x{flags:04X}
-        Bit[0] (Add/Online Operation Only)                        : 0x{flag1:04X}{flag1_str}
-        Bit[1] (Proximity Domain Validity)                        : 0x{flag2:04X}{flag2_str}
+      SPA Range Structure Index                                   : 0x{spaRangeStructure:04X}{spaRangeStructure_str}
+      Flags                                                       : 0x{flags:04X}
+        Bit[0] (Add/Online Operation Only)                        : 0x{flag1:04X}{flag1_str}
+        Bit[1] (Proximity Domain Validity)                        : 0x{flag2:04X}{flag2_str}
         Bits[15:2]                                                : 0x{flag3:04X} - Reserved
-      Reserved                                                    : 0x{reserved:08X}
+      Reserved                                                    : 0x{reserved:08X}
       Proximity Domain                                            : 0x{proximityDomain:08X} - must match value in SRAT table
-      Address Range Type GUID                                     : 0x{addressRangeTypeGUID_1:08X} 0x{addressRangeTypeGUID_2:04X} 0x{addressRangeTypeGUID_3:04X} 0x{addressRangeTypeGUID_4:02X} 0x{addressRangeTypeGUID_5:02X} 0x{addressRangeTypeGUID_6:02X} 0x{addressRangeTypeGUID_7:02X} 0x{addressRangeTypeGUID_8:02X} 0x{addressRangeTypeGUID_9:02X} 0x{addressRangeTypeGUID_10:02X} 0x{addressRangeTypeGUID_11:02X} - {artg_str}
-      System Physical Address Range Base                          : 0x{systemPARangeBase:016X}
+      Address Range Type GUID                                     : 0x{addressRangeTypeGUID_1:08X} 0x{addressRangeTypeGUID_2:04X} 0x{addressRangeTypeGUID_3:04X} 0x{addressRangeTypeGUID_4:02X} 0x{addressRangeTypeGUID_5:02X} 0x{addressRangeTypeGUID_6:02X} 0x{addressRangeTypeGUID_7:02X} 0x{addressRangeTypeGUID_8:02X} 0x{addressRangeTypeGUID_9:02X} 0x{addressRangeTypeGUID_10:02X} 0x{addressRangeTypeGUID_11:02X} - {artg_str}
+      System Physical Address Range Base                          : 0x{systemPARangeBase:016X}
       System Physical Address Range Length                        : 0x{SPARLen:016X} ({SPARLen:d} bytes)
-      Address Range Memory Mapping Attribute                      : 0x{addrRangeMemMapAttr:016X}
+      Address Range Memory Mapping Attribute                      : 0x{addrRangeMemMapAttr:016X}
 '''

 
-
-

-[docs]
-    def parseStructures(self, table_content: bytes) -> str:
+
[docs]    def parseStructures(self, table_content: bytes) -> str:
         notFinished = True
         curPos = 0
         result = ''
@@ -2464,26 +2198,21 @@ 
Source code for chipsec.hal.acpi_tables
                 notFinished = False
         return result

 
-
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         reserved = struct.unpack('<L', table_content[0:4])[0]
         NFITstructures = self.parseStructures(table_content[4:])
         self.results = f'''==================================================================
   NVDIMM Firmware Interface Table ( NFIT )
 ==================================================================
-  Reserved                                                      : {reserved:08X}
-  NFIT Structures{NFITstructures}
+  Reserved                                                      : {reserved:08X}
+  NFIT Structures{NFITstructures}
 
 '''

 
-
     def __str__(self) -> str:
         return self.results

 
 
-
 ########################################################################################################
 #
 # UEFI Table
@@ -2492,18 +2221,14 @@ 
Source code for chipsec.hal.acpi_tables
 SMM_COMM_TABLE = str(UUID('c68ed8e29dc64cbd9d94db65acc5c332')).upper()
 
 
-

-[docs]
-class UEFI_TABLE (ACPI_TABLE):
+
[docs]class UEFI_TABLE (ACPI_TABLE):
     def __init__(self):
         self.buf_addr = 0
         self.smi = 0
         self.invoc_reg = None
         return
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         self.results = '''==================================================================
   Table Content
 =================================================================='''
@@ -2515,7 +2240,7 @@ 
Source code for chipsec.hal.acpi_tables
         identifier = EFI_GUID_STR(guid)
         offset = struct.unpack('H', table_content[16:18])[0]
         self.results += f"""
-  identifier                 : {identifier}
+  identifier                 : {identifier}
   Data Offset                : {offset:d}"""
         # check if SMM Communication ACPI Table
         if not (SMM_COMM_TABLE == identifier):
@@ -2529,7 +2254,7 @@ 
Source code for chipsec.hal.acpi_tables
         self.buf_addr = struct.unpack('Q', table_content[content_offset:content_offset + 8])[0]
         content_offset += 8
         self.results += f"""
-  SW SMI NUM                 : {self.smi}
+  SW SMI NUM                 : {self.smi}
   Buffer Ptr Address         : {self.buf_addr:X}"""
         # Check to see if there is enough data for Invocation Register
         if content_offset + 12 <= len(table_content):
@@ -2538,18 +2263,13 @@ 
Source code for chipsec.hal.acpi_tables
         else:
             self.results += "\n  Invocation Register        : None\n"

 
-
     def __str__(self) -> str:
         return self.results
 
     CommBuffInfo = Tuple[int, int, Optional['GAS']]
 
-

-[docs]
-    def get_commbuf_info(self) -> CommBuffInfo:
-        return (self.smi, self.buf_addr, self.invoc_reg)

-

-
+
[docs]    def get_commbuf_info(self) -> CommBuffInfo:
+        return (self.smi, self.buf_addr, self.invoc_reg)

 
 ########################################################################################################
 #
@@ -2558,9 +2278,7 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class WSMT (ACPI_TABLE):
+
[docs]class WSMT (ACPI_TABLE):
 
     FIXED_COMM_BUFFERS = 1
     COMM_BUFFER_NESTED_PTR_PROTECTION = 2
@@ -2571,9 +2289,7 @@ 
Source code for chipsec.hal.acpi_tables
         self.comm_buffer_nested_ptr_protection = False
         self.system_resource_protection = False
 
-

-[docs]
-    def parse(self, table_content: bytes) -> None:
+
[docs]    def parse(self, table_content: bytes) -> None:
         if len(table_content) < 4:
             return
 
@@ -2583,19 +2299,17 @@ 
Source code for chipsec.hal.acpi_tables
         self.comm_buffer_nested_ptr_protection = bool(mitigations & WSMT.COMM_BUFFER_NESTED_PTR_PROTECTION)
         self.system_resource_protection = bool(mitigations & WSMT.SYSTEM_RESOURCE_PROTECTION)

 
-
     def __str__(self) -> str:
         return f"""------------------------------------------------------------------
 Windows SMM Mitigations Table (WSMT) Contents
 ------------------------------------------------------------------
-FIXED_COMM_BUFFERS                  : {self.fixed_comm_buffers}
-COMM_BUFFER_NESTED_PTR_PROTECTION   : {self.comm_buffer_nested_ptr_protection}
-SYSTEM_RESOURCE_PROTECTION          : {self.system_resource_protection}
+FIXED_COMM_BUFFERS                  : {self.fixed_comm_buffers}
+COMM_BUFFER_NESTED_PTR_PROTECTION   : {self.comm_buffer_nested_ptr_protection}
+SYSTEM_RESOURCE_PROTECTION          : {self.system_resource_protection}
     """

 
 
 
-
 ########################################################################################################
 #
 # Generic Address Structure
@@ -2603,9 +2317,7 @@ 
Source code for chipsec.hal.acpi_tables
 ########################################################################################################
 
 
-

-[docs]
-class GAS:
+
[docs]class GAS:
     def __init__(self, table_content: bytes):
         self.addrSpaceID = struct.unpack('<B', table_content[0:1])[0]
         self.regBitWidth = struct.unpack('<B', table_content[1:2])[0]
@@ -2638,19 +2350,15 @@ 
Source code for chipsec.hal.acpi_tables
 
     def __str__(self) -> str:
         return f"""  Generic Address Structure
-    Address Space ID                            : {self.addrSpaceID:02X} - {self.accessSize_str}
-    Register Bit Width                          : {self.regBitWidth:02X}
-    Register Bit Offset                         : {self.regBitOffset:02X}
-    Access Size                                 : {self.accessSize:02X} - {self.accessSize_str}
-    Address                                     : {self.addr:16X}
+    Address Space ID                            : {self.addrSpaceID:02X} - {self.accessSize_str}
+    Register Bit Width                          : {self.regBitWidth:02X}
+    Register Bit Offset                         : {self.regBitOffset:02X}
+    Access Size                                 : {self.accessSize:02X} - {self.accessSize_str}
+    Address                                     : {self.addr:16X}
     """
 
-

-[docs]
-    def get_info(self) -> Tuple[int, int, int, int, int]:
-        return (self.addrSpaceID, self.regBitWidth, self.regBitOffset, self.accessSize, self.addr)

-

-
+
[docs]    def get_info(self) -> Tuple[int, int, int, int, int]:
+        return (self.addrSpaceID, self.regBitWidth, self.regBitOffset, self.accessSize, self.addr)

 

 
             

@@ -2710,7 +2418,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -2730,8 +2438,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/cmos.html b/_modules/chipsec/hal/cmos.html
index 5ebc73c6..0d47ab54 100644
--- a/_modules/chipsec/hal/cmos.html
+++ b/_modules/chipsec/hal/cmos.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.cmos — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -85,44 +87,28 @@ 
Source code for chipsec.hal.cmos
 CMOS_DATA_PORT_HIGH = 0x73
 
 
-

-[docs]
-class CMOS(hal_base.HALBase):
+
[docs]class CMOS(hal_base.HALBase):
 
     def __init__(self, cs):
         super(CMOS, self).__init__(cs)
 
-

-[docs]
-    def read_cmos_high(self, offset: int) -> int:
+
[docs]    def read_cmos_high(self, offset: int) -> int:
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_HIGH, offset)
         return self.cs.io.read_port_byte(CMOS_DATA_PORT_HIGH)

 
-
-

-[docs]
-    def write_cmos_high(self, offset: int, value: int) -> None:
+
[docs]    def write_cmos_high(self, offset: int, value: int) -> None:
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_HIGH, offset)
         self.cs.io.write_port_byte(CMOS_DATA_PORT_HIGH, value)

 
-
-

-[docs]
-    def read_cmos_low(self, offset: int) -> int:
+
[docs]    def read_cmos_low(self, offset: int) -> int:
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_LOW, 0x80 | offset)
         return self.cs.io.read_port_byte(CMOS_DATA_PORT_LOW)

 
-
-

-[docs]
-    def write_cmos_low(self, offset: int, value: int) -> None:
+
[docs]    def write_cmos_low(self, offset: int, value: int) -> None:
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_LOW, offset)
         self.cs.io.write_port_byte(CMOS_DATA_PORT_LOW, value)

 
-
-

-[docs]
-    def dump_low(self) -> List[int]:
+
[docs]    def dump_low(self) -> List[int]:
         cmos_buf = [0xFF] * 0x80
         orig = self.cs.io.read_port_byte(CMOS_ADDR_PORT_LOW)
         for off in range(0x80):
@@ -130,10 +116,7 @@ 
Source code for chipsec.hal.cmos
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_LOW, orig)
         return cmos_buf

 
-
-

-[docs]
-    def dump_high(self) -> List[int]:
+
[docs]    def dump_high(self) -> List[int]:
         cmos_buf = [0xFF] * 0x80
         orig = self.cs.io.read_port_byte(CMOS_ADDR_PORT_HIGH)
         for off in range(0x80):
@@ -141,16 +124,11 @@ 
Source code for chipsec.hal.cmos
         self.cs.io.write_port_byte(CMOS_ADDR_PORT_HIGH, orig)
         return cmos_buf

 
-
-

-[docs]
-    def dump(self) -> None:
+
[docs]    def dump(self) -> None:
         self.logger.log("Low CMOS memory contents:")
         chipsec.logger.pretty_print_hex_buffer(self.dump_low())
         self.logger.log("\nHigh CMOS memory contents:")
-        chipsec.logger.pretty_print_hex_buffer(self.dump_high())

-

-
+        chipsec.logger.pretty_print_hex_buffer(self.dump_high())

 

 
             

@@ -210,7 +188,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -230,8 +208,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/cpu.html b/_modules/chipsec/hal/cpu.html
index bc8cdfc4..1f8ba076 100644
--- a/_modules/chipsec/hal/cpu.html
+++ b/_modules/chipsec/hal/cpu.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.cpu — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -79,42 +81,29 @@ 
Source code for chipsec.hal.cpu
 #
 ########################################################################################################
 
-

-[docs]
-class CPU(hal_base.HALBase):
+
[docs]class CPU(hal_base.HALBase):
     def __init__(self, cs):
         super(CPU, self).__init__(cs)
         self.helper = cs.helper
 
-

-[docs]
-    def read_cr(self, cpu_thread_id: int, cr_number: int) -> int:
+
[docs]    def read_cr(self, cpu_thread_id: int, cr_number: int) -> int:
         value = self.helper.read_cr(cpu_thread_id, cr_number)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] read CR{cr_number:d}: value = 0x{value:08X}')
         return value

 
-
-

-[docs]
-    def write_cr(self, cpu_thread_id: int, cr_number: int, value: int) -> int:
+
[docs]    def write_cr(self, cpu_thread_id: int, cr_number: int, value: int) -> int:
         logger().log_hal(f'[cpu{cpu_thread_id:d}] write CR{cr_number:d}: value = 0x{value:08X}')
         status = self.helper.write_cr(cpu_thread_id, cr_number, value)
         return status

 
-
-

-[docs]
-    def cpuid(self, eax: int, ecx: int) -> Tuple[int, int, int, int]:
+
[docs]    def cpuid(self, eax: int, ecx: int) -> Tuple[int, int, int, int]:
         logger().log_hal(f'[cpu] CPUID in : EAX=0x{eax:08X}, ECX=0x{ecx:08X}')
         (eax, ebx, ecx, edx) = self.helper.cpuid(eax, ecx)
         logger().log_hal(f'[cpu] CPUID out: EAX=0x{eax:08X}, EBX=0x{ebx:08X}, ECX=0x{ecx:08X}, EDX=0x{edx:08X}')
         return (eax, ebx, ecx, edx)

 
-
     # Using cpuid check if running under vmm control
-

-[docs]
-    def check_vmm(self) -> int:
+
[docs]    def check_vmm(self) -> int:
         # check Hypervisor Present
         (_, ebx, ecx, edx) = self.cpuid(0x01, 0)
         if (ecx & 0x80000000):
@@ -133,44 +122,29 @@ 
Source code for chipsec.hal.cpu
                 return VMM_KVM
         return VMM_NONE

 
-
     # Using CPUID we can determine if Hyper-Threading is enabled in the CPU
-

-[docs]
-    def is_HT_active(self) -> bool:
+
[docs]    def is_HT_active(self) -> bool:
         logical_processor_per_core = self.get_number_logical_processor_per_core()
         return logical_processor_per_core > 1

 
-
     # Using the CPUID we determine the number of logical processors per core
-

-[docs]
-    def get_number_logical_processor_per_core(self) -> int:
+
[docs]    def get_number_logical_processor_per_core(self) -> int:
         (_, ebx, _, _) = self.cpuid(0x0b, 0x0)
         return ebx

 
-
     # Using CPUID we can determine the number of logical processors per package
-

-[docs]
-    def get_number_logical_processor_per_package(self) -> int:
+
[docs]    def get_number_logical_processor_per_package(self) -> int:
         (_, ebx, _, _) = self.cpuid(0x0b, 0x1)
         return ebx

 
-
     # Using CPUID we can determine the number of physical processors per package
-

-[docs]
-    def get_number_physical_processor_per_package(self) -> int:
+
[docs]    def get_number_physical_processor_per_package(self) -> int:
         logical_processor_per_core = self.get_number_logical_processor_per_core()
         logical_processor_per_package = self.get_number_logical_processor_per_package()
         return (logical_processor_per_package // logical_processor_per_core)

 
-
     # determine number of logical processors in the core
-

-[docs]
-    def get_number_threads_from_APIC_table(self) -> int:
+
[docs]    def get_number_threads_from_APIC_table(self) -> int:
         _acpi = acpi.ACPI(self.cs)
         dACPIID = {}
         for apic in _acpi.get_parse_ACPI_table(acpi.ACPI_TABLE_SIG_APIC):  # (table_header, APIC_object, table_header_blob, table_blob)
@@ -182,17 +156,15 @@ 
Source code for chipsec.hal.cpu
                             dACPIID[structure.APICID] = structure.ACPIProcID
         return len(dACPIID)

 
-
     # determine the cpu threads location within a package/core
-

-[docs]
-    def get_cpu_topology(self) -> Dict[str, Dict[int, List[int]]]:
+
[docs]    def get_cpu_topology(self) -> Dict[str, Dict[int, List[int]]]:
         num_threads = self.cs.helper.get_threads_count()
         packages: Dict[int, List[int]] = {}
         cores: Dict[int, List[int]] = {}
         for thread in range(num_threads):
-            self.logger.log_hal(f'Setting affinity to: {thread:d}')
-            self.cs.helper.set_affinity(thread)
+            if num_threads > 1:
+                self.logger.log_hal(f'Setting affinity to: {thread:d}')
+                self.cs.helper.set_affinity(thread)
             eax = 0xb   # cpuid leaf 0B contains x2apic info
             ecx = 1     # ecx 1 will get us pkg_id in edx after shifting right by _eax
             (_eax, _, _, _edx) = self.cs.cpu.cpuid(eax, ecx)
@@ -212,46 +184,34 @@ 
Source code for chipsec.hal.cpu
         topology = {'packages': packages, 'cores': cores}
         return topology

 
-
     # determine number of physical sockets using the CPUID and APIC ACPI table
-

-[docs]
-    def get_number_sockets_from_APIC_table(self) -> int:
+
[docs]    def get_number_sockets_from_APIC_table(self) -> int:
         number_threads = self.get_number_threads_from_APIC_table()
         logical_processor_per_package = self.get_number_logical_processor_per_package()
         return (number_threads // logical_processor_per_package)

 
-
     #
     # Return SMRR MSR physical base and mask
     #
-

-[docs]
-    def get_SMRR(self) -> Tuple[int, int]:
+
[docs]    def get_SMRR(self) -> Tuple[int, int]:
         smrambase = self.cs.read_register_field('IA32_SMRR_PHYSBASE', 'PhysBase', True)
         smrrmask = self.cs.read_register_field('IA32_SMRR_PHYSMASK', 'PhysMask', True)
         return (smrambase, smrrmask)

 
-
     #
     # Return SMRAM region base, limit and size as defined by SMRR
     #
-

-[docs]
-    def get_SMRR_SMRAM(self) -> Tuple[int, int, int]:
+
[docs]    def get_SMRR_SMRAM(self) -> Tuple[int, int, int]:
         (smram_base, smrrmask) = self.get_SMRR()
         smram_base &= smrrmask
         smram_size = ((~smrrmask) & 0xFFFFFFFF) + 1
         smram_limit = smram_base + smram_size - 1
         return (smram_base, smram_limit, smram_size)

 
-
     #
     # Returns TSEG base, limit and size
     #
-

-[docs]
-    def get_TSEG(self) -> Tuple[int, int, int]:
+
[docs]    def get_TSEG(self) -> Tuple[int, int, int]:
         if self.cs.is_server():
             # tseg register has base and limit
             tseg_base = self.cs.read_register_field('TSEG_BASE', 'base', preserve_field_position=True)
@@ -266,13 +226,10 @@ 
Source code for chipsec.hal.cpu
         tseg_size = tseg_limit - tseg_base + 1
         return (tseg_base, tseg_limit, tseg_size)

 
-
     #
     # Returns SMRAM base from either SMRR MSR or TSEG PCIe config register
     #
-

-[docs]
-    def get_SMRAM(self) -> Tuple[int, int, int]:
+
[docs]    def get_SMRAM(self) -> Tuple[int, int, int]:
         smram_base = None
         smram_limit = None
         smram_size = 0
@@ -291,26 +248,20 @@ 
Source code for chipsec.hal.cpu
                 smram_limit = 0
         return (smram_base, smram_limit, smram_size)

 
-
     #
     # Check that SMRR is supported by CPU in IA32_MTRRCAP_MSR[SMRR]
     #
-

-[docs]
-    def check_SMRR_supported(self) -> bool:
+
[docs]    def check_SMRR_supported(self) -> bool:
         mtrrcap_msr_reg = self.cs.read_register('MTRRCAP')
         if logger().HAL:
             self.cs.print_register('MTRRCAP', mtrrcap_msr_reg)
         smrr = self.cs.get_register_field('MTRRCAP', mtrrcap_msr_reg, 'SMRR')
         return (1 == smrr)

 
-
     #
     # Dump CPU page tables at specified physical base of paging-directory hierarchy (CR3)
     #
-

-[docs]
-    def dump_page_tables(self, cr3: int, pt_fname: Optional[str] = None) -> None:
+
[docs]    def dump_page_tables(self, cr3: int, pt_fname: Optional[str] = None) -> None:
         _orig_logname = logger().LOG_FILE_NAME
         hpt = paging.c_ia32e_page_tables(self.cs)
         logger().log_hal(f'[cpu] dumping paging hierarchy at physical base (CR3) = 0x{cr3:08X}...')
@@ -322,16 +273,11 @@ 
Source code for chipsec.hal.cpu
         if hpt.failure:
             logger().log_error('could not dump page tables')

 
-
-

-[docs]
-    def dump_page_tables_all(self) -> None:
+
[docs]    def dump_page_tables_all(self) -> None:
         for tid in range(self.cs.msr.get_cpu_thread_count()):
             cr3 = self.read_cr(tid, 3)
             logger().log_hal(f'[cpu{tid:d}] found paging hierarchy base (CR3): 0x{cr3:08X}')
-            self.dump_page_tables(cr3)

-

-
+            self.dump_page_tables(cr3)

 

 
             

@@ -391,7 +337,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -411,8 +357,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/cpuid.html b/_modules/chipsec/hal/cpuid.html
index c259cb80..d9d7a566 100644
--- a/_modules/chipsec/hal/cpuid.html
+++ b/_modules/chipsec/hal/cpuid.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.cpuid — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -69,30 +71,21 @@ 
Source code for chipsec.hal.cpuid
 from chipsec.logger import logger
 
 
-

-[docs]
-class CpuID(hal_base.HALBase):
+
[docs]class CpuID(hal_base.HALBase):
 
     def __init__(self, cs):
         super(CpuID, self).__init__(cs)
         self.helper = cs.helper
 
-

-[docs]
-    def cpuid(self, eax: int, ecx: int) -> Tuple[int, int, int, int]:
+
[docs]    def cpuid(self, eax: int, ecx: int) -> Tuple[int, int, int, int]:
         logger().log_hal(f'[cpuid] in: EAX=0x{eax:08X}, ECX=0x{ecx:08X}')
         (eax, ebx, ecx, edx) = self.helper.cpuid(eax, ecx)
         logger().log_hal(f'[cpuid] out: EAX=0x{eax:08X}, EBX=0x{ebx:08X}, ECX=0x{ecx:08X}, EDX=0x{edx:08X}')
         return (eax, ebx, ecx, edx)

 
-
-

-[docs]
-    def get_proc_info(self):
+
[docs]    def get_proc_info(self):
         (eax, _, _, _) = self.cpuid(0x01, 0x00)
-        return eax

-

-
+        return eax

 

 
             

@@ -152,7 +145,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -172,8 +165,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/ec.html b/_modules/chipsec/hal/ec.html
index 5fb37f1c..c3d03ddb 100644
--- a/_modules/chipsec/hal/ec.html
+++ b/_modules/chipsec/hal/ec.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.ec — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -114,9 +116,7 @@ 
Source code for chipsec.hal.ec
 EC_COMMAND_ACPI_WRITE_EXT = 0x0F1  # Write EC ACPI extended memory
 
 
-

-[docs]
-class EC(hal_base.HALBase):
+
[docs]class EC(hal_base.HALBase):
 
     #
     # EC ACPI memory access
@@ -136,47 +136,30 @@ 
Source code for chipsec.hal.ec
             to = to - 1
         return True
 
-

-[docs]
-    def write_command(self, command: int) -> None:
+
[docs]    def write_command(self, command: int) -> None:
         self._wait_ec_inbuf_empty()
         return self.cs.io.write_port_byte(IO_PORT_EC_COMMAND, command)

 
-
-

-[docs]
-    def write_data(self, data: int) -> None:
+
[docs]    def write_data(self, data: int) -> None:
         self._wait_ec_inbuf_empty()
         return self.cs.io.write_port_byte(IO_PORT_EC_DATA, data)

 
-
-

-[docs]
-    def read_data(self) -> Optional[int]:
+
[docs]    def read_data(self) -> Optional[int]:
         if not self._wait_ec_outbuf_full():
             return None
         return self.cs.io.read_port_byte(IO_PORT_EC_DATA)

 
-
-

-[docs]
-    def read_memory(self, offset: int) -> Optional[int]:
+
[docs]    def read_memory(self, offset: int) -> Optional[int]:
         self.write_command(EC_COMMAND_ACPI_READ)
         self.write_data(offset)
         return self.read_data()

 
-
-

-[docs]
-    def write_memory(self, offset: int, data: int) -> None:
+
[docs]    def write_memory(self, offset: int, data: int) -> None:
         self.write_command(EC_COMMAND_ACPI_WRITE)
         self.write_data(offset)
         return self.write_data(data)

 
-
-

-[docs]
-    def read_memory_extended(self, word_offset: int) -> Optional[int]:
+
[docs]    def read_memory_extended(self, word_offset: int) -> Optional[int]:
         self.write_command(EC_COMMAND_ACPI_READ)
         self.write_data(0x2)
         self.write_data(word_offset & 0xFF)
@@ -184,10 +167,7 @@ 
Source code for chipsec.hal.ec
         self.write_data(word_offset >> 8)
         return self.read_data()

 
-
-

-[docs]
-    def write_memory_extended(self, word_offset: int, data: int) -> None:
+
[docs]    def write_memory_extended(self, word_offset: int, data: int) -> None:
         self.write_command(EC_COMMAND_ACPI_WRITE)
         self.write_data(0x2)
         self.write_data(word_offset & 0xFF)
@@ -195,10 +175,7 @@ 
Source code for chipsec.hal.ec
         self.write_data(word_offset >> 8)
         return self.write_data(data)

 
-
-

-[docs]
-    def read_range(self, start_offset: int, size: int) -> bytes:
+
[docs]    def read_range(self, start_offset: int, size: int) -> bytes:
         buffer = [0xFF] * size
         for i in range(size):
             if start_offset + i < 0x100:
@@ -206,23 +183,20 @@ 
Source code for chipsec.hal.ec
                 if mem_value is not None:
                     buffer[i] = mem_value
                 else:
-                    self.logger.log_hal(f'[ec] Unable to read EC offset 0x{start_offset + i:X}')
+                    self.logger.log_hal(f'[ec] Unable to read EC offset 0x{start_offset + i:X}')
             else:
                 mem_value = self.read_memory_extended(start_offset + i)
                 if mem_value is not None:
                     buffer[i] = mem_value
                 else:
-                    self.logger.log_hal(f'[ec] Unable to read EC offset 0x{start_offset + i:X}')
+                    self.logger.log_hal(f'[ec] Unable to read EC offset 0x{start_offset + i:X}')
 
         self.logger.log_hal(f'[ec] read EC memory from offset {start_offset:X} size {size:X}:')
         if self.logger.HAL:
             print_buffer_bytes(buffer)
         return bytes(buffer)

 
-
-

-[docs]
-    def write_range(self, start_offset: int, buffer: bytes) -> bool:
+
[docs]    def write_range(self, start_offset: int, buffer: bytes) -> bool:
         for i, b in enumerate(buffer):
             self.write_memory(start_offset + i, b)
         self.logger.log_hal(f'[ec] write EC memory to offset {start_offset:X} size {len(buffer):X}:')
@@ -230,30 +204,22 @@ 
Source code for chipsec.hal.ec
             print_buffer_bytes(buffer)
         return True

 
-
     #
     # EC Intex I/O access
     #
-

-[docs]
-    def read_idx(self, offset: int) -> int:
+
[docs]    def read_idx(self, offset: int) -> int:
         self.cs.io.write_port_byte(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF)
         self.cs.io.write_port_byte(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF)
         value = self.cs.io.read_port_byte(IO_PORT_EC_INDEX_DATA)
         self.logger.log_hal(f'[ec] index read: offset 0x{offset:02X} > 0x{value:02X}:')
         return value

 
-
-

-[docs]
-    def write_idx(self, offset: int, value: int) -> bool:
+
[docs]    def write_idx(self, offset: int, value: int) -> bool:
         self.logger.log_hal(f'[ec] index write: offset 0x{offset:02X} < 0x{value:02X}:')
         self.cs.io.write_port_byte(IO_PORT_EC_INDEX_ADDRL, offset & 0xFF)
         self.cs.io.write_port_byte(IO_PORT_EC_INDEX_ADDRH, (offset >> 8) & 0xFF)
         self.cs.io.write_port_byte(IO_PORT_EC_INDEX_DATA, value & 0xFF)
-        return True

-

-
+        return True

 

 
             

@@ -313,7 +279,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -333,8 +299,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/hal_base.html b/_modules/chipsec/hal/hal_base.html
index 7dd87585..83ca6a92 100644
--- a/_modules/chipsec/hal/hal_base.html
+++ b/_modules/chipsec/hal/hal_base.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.hal_base — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -65,13 +67,10 @@ 
Source code for chipsec.hal.hal_base
 import chipsec.logger
 
 
-

-[docs]
-class HALBase:
+
[docs]class HALBase:
     def __init__(self, cs):
         self.cs = cs
         self.logger = chipsec.logger.logger()

-
 

 
             

@@ -131,7 +130,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -151,8 +150,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/igd.html b/_modules/chipsec/hal/igd.html
index d2fdac3f..a8997dc9 100644
--- a/_modules/chipsec/hal/igd.html
+++ b/_modules/chipsec/hal/igd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.igd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,9 +77,7 @@ 
Source code for chipsec.hal.igd
 from chipsec.logger import print_buffer_bytes
 
 
-

-[docs]
-class IGD(hal_base.HALBase):
+
[docs]class IGD(hal_base.HALBase):
 
     def __init__(self, cs):
         super(IGD, self).__init__(cs)
@@ -97,9 +97,7 @@ 
Source code for chipsec.hal.igd
 
         return (self.enabled, self.is_legacy)
 
-

-[docs]
-    def is_enabled(self) -> bool:
+
[docs]    def is_enabled(self) -> bool:
         if self.cs.register_has_field("PCI0.0.0_DEVEN", "D2EN") and self.cs.register_has_field("PCI0.0.0_CAPID0_A", "IGD"):
             if self.cs.read_register_field("PCI0.0.0_DEVEN", "D2EN") == 1 and self.cs.read_register_field("PCI0.0.0_CAPID0_A", "IGD") == 0:
                 return True
@@ -111,53 +109,32 @@ 
Source code for chipsec.hal.igd
                 return True
         return self.is_device_enabled()

 
-
-

-[docs]
-    def is_device_enabled(self) -> bool:
+
[docs]    def is_device_enabled(self) -> bool:
         enabled, _ = self.__identify_device()
         return enabled

 
-
-

-[docs]
-    def is_legacy_gen(self) -> bool:
+
[docs]    def is_legacy_gen(self) -> bool:
         _, legacy = self.__identify_device()
         return legacy

 
-
-

-[docs]
-    def get_GMADR(self) -> int:
+
[docs]    def get_GMADR(self) -> int:
         base, _ = self.cs.mmio.get_MMIO_BAR_base_address('GMADR')
         self.logger.log_hal(f'[igd] Aperture (GMADR): 0x{base:016X}')
         return base

 
-
-

-[docs]
-    def get_GTTMMADR(self) -> int:
+
[docs]    def get_GTTMMADR(self) -> int:
         base, _ = self.cs.mmio.get_MMIO_BAR_base_address('GTTMMADR')
         self.logger.log_hal(f'[igd] Graphics MMIO and GTT (GTTMMADR): 0x{base:016X}')
         return base

 
-
-

-[docs]
-    def get_GGTT_base(self) -> int:
+
[docs]    def get_GGTT_base(self) -> int:
         gtt_off = 0x200000 if self.is_legacy_gen() else 0x800000
         return self.get_GTTMMADR() + gtt_off

 
-
-

-[docs]
-    def get_PTE_size(self) -> int:
+
[docs]    def get_PTE_size(self) -> int:
         return 4 if self.is_legacy_gen() else 8

 
-
-

-[docs]
-    def read_GGTT_PTE(self, pte_num: int) -> int:
+
[docs]    def read_GGTT_PTE(self, pte_num: int) -> int:
         gtt_base = self.get_GGTT_base()
         reg_off = (self.get_PTE_size() * pte_num)
 
@@ -167,20 +144,14 @@ 
Source code for chipsec.hal.igd
             pte_hi = self.cs.mmio.read_MMIO_reg(gtt_base, reg_off + 4)
         return (pte_lo | (pte_hi << 32))

 
-
-

-[docs]
-    def write_GGTT_PTE(self, pte_num: int, pte: int) -> int:
+
[docs]    def write_GGTT_PTE(self, pte_num: int, pte: int) -> int:
         gtt_base = self.get_GGTT_base()
         self.cs.mmio.write_MMIO_reg(gtt_base, self.get_PTE_size() * pte_num, pte & 0xFFFFFFFF)
         if self.get_PTE_size() == 8:
             self.cs.mmio.write_MMIO_reg(gtt_base, self.get_PTE_size() * pte_num + 4, pte >> 32)
         return pte

 
-
-

-[docs]
-    def write_GGTT_PTE_from_PA(self, pte_num: int, pa: int) -> int:
+
[docs]    def write_GGTT_PTE_from_PA(self, pte_num: int, pa: int) -> int:
         pte = self.get_GGTT_PTE_from_PA(pa)
         gtt_base = self.get_GGTT_base()
         self.cs.mmio.write_MMIO_reg(gtt_base, self.get_PTE_size() * pte_num, pte & 0xFFFFFFFF)
@@ -188,10 +159,7 @@ 
Source code for chipsec.hal.igd
             self.cs.mmio.write_MMIO_reg(gtt_base, self.get_PTE_size() * pte_num + 4, pte >> 32)
         return pte

 
-
-

-[docs]
-    def dump_GGTT_PTEs(self, num: int) -> None:
+
[docs]    def dump_GGTT_PTEs(self, num: int) -> None:
         gtt_base = self.get_GGTT_base()
         self.logger.log('[igd] Global GTT contents:')
         ptes = self.cs.mmio.read_MMIO(gtt_base, num * self.get_PTE_size())
@@ -200,19 +168,13 @@ 
Source code for chipsec.hal.igd
             self.logger.log(f'PTE[{pte_num:03d}]: {pte:08X}')
             pte_num = pte_num + 1

 
-
-

-[docs]
-    def get_GGTT_PTE_from_PA(self, pa: int) -> int:
+
[docs]    def get_GGTT_PTE_from_PA(self, pa: int) -> int:
         if self.is_legacy_gen():
             return self.get_GGTT_PTE_from_PA_legacy(pa)
         else:
             return self.get_GGTT_PTE_from_PA_gen8(pa)

 
-
-

-[docs]
-    def get_GGTT_PTE_from_PA_legacy(self, pa: int) -> int:
+
[docs]    def get_GGTT_PTE_from_PA_legacy(self, pa: int) -> int:
         #
         # GTT PTE format:
         # 0     - valid
@@ -223,37 +185,22 @@ 
Source code for chipsec.hal.igd
         #
         return ((pa & 0xFFFFF000) | ((pa >> 32 & 0xFF) << 4) | 0x3)

 
-
-

-[docs]
-    def get_PA_from_PTE_legacy(self, pte: int) -> int:
+
[docs]    def get_PA_from_PTE_legacy(self, pte: int) -> int:
         return (((pte & 0x00000FF0) << 28) | (pte & 0xFFFFF000))

 
-
-

-[docs]
-    def get_GGTT_PTE_from_PA_gen8(self, pa: int) -> int:
+
[docs]    def get_GGTT_PTE_from_PA_gen8(self, pa: int) -> int:
         return ((pa & ~0xFFF) | 0x1)

 
-
-

-[docs]
-    def get_PA_from_PTE_gen8(self, pte: int) -> int:
+
[docs]    def get_PA_from_PTE_gen8(self, pte: int) -> int:
         return (pte & ~0xFFF)

 
-
-

-[docs]
-    def get_PA_from_PTE(self, pte: int) -> int:
+
[docs]    def get_PA_from_PTE(self, pte: int) -> int:
         if self.is_legacy_gen():
             return self.get_PA_from_PTE_legacy(pte)
         else:
             return self.get_PA_from_PTE_gen8(pte)

 
-
-

-[docs]
-    def gfx_aperture_dma_read_write(self, address: int, size: int = 0x4, value: Optional[bytes] = None, pte_num: int = 0) -> bytes:
+
[docs]    def gfx_aperture_dma_read_write(self, address: int, size: int = 0x4, value: Optional[bytes] = None, pte_num: int = 0) -> bytes:
         r = 0
         pages = 0
 
@@ -297,13 +244,13 @@ 
Source code for chipsec.hal.igd
             if (p == N - 1):
                 size = r if (r > 0) else 0x1000
             if value is None:
-                self.logger.log_hal(f'[igd] Reading 0x{size:X} bytes at 0x{pa:016X} through GFx aperture 0x{igd_addr + pa_off:016X}...')
+                self.logger.log_hal(f'[igd] Reading 0x{size:X} bytes at 0x{pa:016X} through GFx aperture 0x{igd_addr + pa_off:016X}...')
                 page = self.cs.mem.read_physical_mem(igd_addr + pa_off, size)
                 buffer += page
                 if self.logger.HAL:
                     print_buffer_bytes(page[:size])
             else:
-                self.logger.log_hal(f'[igd] Writing 0x{size:X} bytes to 0x{pa:016X} through GFx aperture 0x{igd_addr + pa_off:016X}...')
+                self.logger.log_hal(f'[igd] Writing 0x{size:X} bytes to 0x{pa:016X} through GFx aperture 0x{igd_addr + pa_off:016X}...')
                 page = value[p * 0x1000:p * 0x1000 + size]
                 self.cs.mem.write_physical_mem(igd_addr + pa_off, size, page)
                 if self.logger.HAL:
@@ -314,9 +261,7 @@ 
Source code for chipsec.hal.igd
         self.logger.log_hal(f'[igd] Restoring GFx PTE{pte_num:d} 0x{pte_orig:X}...')
         self.write_GGTT_PTE(pte_num, pte_orig)
 
-        return buffer

-

-
+        return buffer

 

 
             

@@ -376,7 +321,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -396,8 +341,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/interrupts.html b/_modules/chipsec/hal/interrupts.html
index 807055df..0826f689 100644
--- a/_modules/chipsec/hal/interrupts.html
+++ b/_modules/chipsec/hal/interrupts.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.interrupts — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -84,19 +86,15 @@ 
Source code for chipsec.hal.interrupts
 NMI_NOW = 0x1
 
 
-

-[docs]
-class Interrupts(hal_base.HALBase):
+
[docs]class Interrupts(hal_base.HALBase):
 
     def __init__(self, cs):
         super(Interrupts, self).__init__(cs)
 
-

-[docs]
-    def send_SW_SMI(self, thread_id: int, SMI_code_port_value: int, SMI_data_port_value: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) -> Optional[Tuple[int, int, int, int, int, int, int]]:
+
[docs]    def send_SW_SMI(self, thread_id: int, SMI_code_port_value: int, SMI_data_port_value: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) -> Optional[Tuple[int, int, int, int, int, int, int]]:
         SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
         logger().log_hal(
-            f"[intr] Sending SW SMI: code port 0x{SMI_APMC_PORT:02X} <- 0x{SMI_code_port_value:02X}, data port 0x{SMI_APMC_PORT + 1:02X} <- 0x{SMI_data_port_value:02X} (0x{SMI_code_data:04X})")
+            f"[intr] Sending SW SMI: code port 0x{SMI_APMC_PORT:02X} <- 0x{SMI_code_port_value:02X}, data port 0x{SMI_APMC_PORT + 1:02X} <- 0x{SMI_data_port_value:02X} (0x{SMI_code_data:04X})")
         logger().log_hal(f"       RAX = 0x{_rax:016X} (AX will be overridden with values of SW SMI ports B2/B3)")
         logger().log_hal(f"       RBX = 0x{_rbx:016X}")
         logger().log_hal(f"       RCX = 0x{_rcx:016X}")
@@ -105,27 +103,18 @@ 
Source code for chipsec.hal.interrupts
         logger().log_hal(f"       RDI = 0x{_rdi:016X}")
         return self.cs.helper.send_sw_smi(thread_id, SMI_code_data, _rax, _rbx, _rcx, _rdx, _rsi, _rdi)

 
-
-

-[docs]
-    def send_SMI_APMC(self, SMI_code_port_value: int, SMI_data_port_value: int) -> None:
+
[docs]    def send_SMI_APMC(self, SMI_code_port_value: int, SMI_data_port_value: int) -> None:
         logger().log_hal(f"[intr] sending SMI via APMC ports: code 0xB2 <- 0x{SMI_code_port_value:02X}, data 0xB3 <- 0x{SMI_data_port_value:02X}")
         self.cs.io.write_port_byte(SMI_DATA_PORT, SMI_data_port_value)
         return self.cs.io.write_port_byte(SMI_APMC_PORT, SMI_code_port_value)

 
-
-

-[docs]
-    def send_NMI(self) -> None:
+
[docs]    def send_NMI(self) -> None:
         logger().log_hal("[intr] Sending NMI# through TCO1_CTL[NMI_NOW]")
         reg, ba = self.cs.get_IO_space("TCOBASE")
         tcobase = self.cs.read_register_field(reg, ba)
         return self.cs.io.write_port_byte(tcobase + NMI_TCO1_CTL + 1, NMI_NOW)

 
-
-

-[docs]
-    def find_ACPI_SMI_Buffer(self) -> Optional[UEFI_TABLE.CommBuffInfo]:
+
[docs]    def find_ACPI_SMI_Buffer(self) -> Optional[UEFI_TABLE.CommBuffInfo]:
         logger().log_hal("Parsing ACPI tables to identify Communication Buffer")
         _acpi = ACPI(self.cs).get_ACPI_table("UEFI")
         if len(_acpi):
@@ -136,10 +125,7 @@ 
Source code for chipsec.hal.interrupts
         logger().log_hal("Unable to find Communication Buffer")
         return None

 
-
-

-[docs]
-    def send_ACPI_SMI(self, thread_id: int, smi_num: int, buf_addr: int, invoc_reg: GAS, guid: str, data: bytes) -> Optional[int]:
+
[docs]    def send_ACPI_SMI(self, thread_id: int, smi_num: int, buf_addr: int, invoc_reg: GAS, guid: str, data: bytes) -> Optional[int]:
         # Prepare Communication Data buffer
         # typedef struct {
         #   EFI_GUID HeaderGuid;
@@ -178,11 +164,8 @@ 
Source code for chipsec.hal.interrupts
             self.cs.helper.write_phys_mem(buf_addr, len(data_hdr), b"\x00" * len(data_hdr))
             return None

 
-
     # scan phys mem range start-end looking for 'smmc'
-

-[docs]
-    def find_smmc(self, start: int, end: int) -> int:
+
[docs]    def find_smmc(self, start: int, end: int) -> int:
         chunk_sz = 1024 * 8  # 8KB chunks
         phys_address = start
         found_at = 0
@@ -196,8 +179,7 @@ 
Source code for chipsec.hal.interrupts
             phys_address += chunk_sz
         return found_at

 
-
-    '''
+    '''
 Send SWSMI in the same way as EFI_SMM_COMMUNICATION_PROTOCOL
     - Write Commbuffer location and Commbuffer size to 'smmc' structure
     - Write 0 to 0xb3 and 0xb2
@@ -217,9 +199,7 @@ 
Source code for chipsec.hal.interrupts
 } SMM_CORE_PRIVATE_DATA;
     '''
 
-

-[docs]
-    def send_smmc_SMI(self, smmc: int, guid: str, payload: bytes, payload_loc: int, CommandPort: int = 0x0, DataPort: int = 0x0) -> int:
+
[docs]    def send_smmc_SMI(self, smmc: int, guid: str, payload: bytes, payload_loc: int, CommandPort: int = 0x0, DataPort: int = 0x0) -> int:
         guid_b = uuid.UUID(guid).bytes_le
         payload_sz = len(payload)
 
@@ -246,9 +226,7 @@ 
Source code for chipsec.hal.interrupts
             self.logger.log("")
 
         ReturnStatus = struct.unpack("Q", self.cs.mem.read_physical_mem(smmc + ReturnStatus_offset, 8))[0]
-        return ReturnStatus

-

-
+        return ReturnStatus

 

 
             

@@ -308,7 +286,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -328,8 +306,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/io.html b/_modules/chipsec/hal/io.html
index da2bff8d..014f5b49 100644
--- a/_modules/chipsec/hal/io.html
+++ b/_modules/chipsec/hal/io.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.io — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -74,9 +76,7 @@ 
Source code for chipsec.hal.io
 from chipsec.logger import logger
 
 
-

-[docs]
-class PortIO:
+
[docs]class PortIO:
 
     def __init__(self, cs):
         self.helper = cs.helper
@@ -94,87 +94,62 @@ 
Source code for chipsec.hal.io
         status = self.helper.write_io_port(io_port, value, size)
         return status
 
-

-[docs]
-    def read_port_dword(self, io_port: int) -> int:
+
[docs]    def read_port_dword(self, io_port: int) -> int:
         value = self.helper.read_io_port(io_port, 4)
         if logger().HAL:
             logger().log(f"[io] reading dword from I/O port 0x{io_port:04X} -> 0x{value:08X}")
         return value

 
-
-

-[docs]
-    def read_port_word(self, io_port: int) -> int:
+
[docs]    def read_port_word(self, io_port: int) -> int:
         value = self.helper.read_io_port(io_port, 2)
         if logger().HAL:
             logger().log(f"[io] reading word from I/O port 0x{io_port:04X} -> 0x{value:04X}")
         return value

 
-
-

-[docs]
-    def read_port_byte(self, io_port: int) -> int:
+
[docs]    def read_port_byte(self, io_port: int) -> int:
         value = self.helper.read_io_port(io_port, 1)
         if logger().HAL:
             logger().log(f"[io] reading byte from I/O port 0x{io_port:04X} -> 0x{value:02X}")
         return value

 
-
-

-[docs]
-    def write_port_byte(self, io_port: int, value: int) -> None:
+
[docs]    def write_port_byte(self, io_port: int, value: int) -> None:
         if logger().HAL:
             logger().log(f"[io] writing byte to I/O port 0x{io_port:04X} <- 0x{value:02X}")
         self.helper.write_io_port(io_port, value, 1)
         return

 
-
-

-[docs]
-    def write_port_word(self, io_port: int, value: int) -> None:
+
[docs]    def write_port_word(self, io_port: int, value: int) -> None:
         if logger().HAL:
             logger().log(f"[io] writing word to I/O port 0x{io_port:04X} <- 0x{value:04X}")
         self.helper.write_io_port(io_port, value, 2)
         return

 
-
-

-[docs]
-    def write_port_dword(self, io_port: int, value: int) -> None:
+
[docs]    def write_port_dword(self, io_port: int, value: int) -> None:
         if logger().HAL:
             logger().log(f"[io] writing dword to I/O port 0x{io_port:04X} <- 0x{value:08X}")
         self.helper.write_io_port(io_port, value, 4)
         return

 
-
     #
     # Read registers from I/O range
     #
-

-[docs]
-    def read_IO(self, range_base: int, range_size: int, size: int = 1) -> List[int]:
+
[docs]    def read_IO(self, range_base: int, range_size: int, size: int = 1) -> List[int]:
         n = range_size // size
         io_ports = []
         for i in range(n):
             io_ports.append(self._read_port(range_base + i * size, size))
         return io_ports

 
-
     #
     # Dump I/O range
     #
-

-[docs]
-    def dump_IO(self, range_base: int, range_size: int, size: int = 1) -> None:
+
[docs]    def dump_IO(self, range_base: int, range_size: int, size: int = 1) -> None:
         n = range_size // size
-        fmt = f'0{size * 2:d}X'
+        fmt = f'0{size * 2:d}X'
         logger().log(f"[io] I/O register range [0x{range_base:04X}:0x{range_base:04X}+{range_size:04X}]:")
         for i in range(n):
             reg = self._read_port(range_base + i * size, size)
-            logger().log(f'+{size * i:04X}: {reg:{fmt}}')

-

-
+            logger().log(f'+{size * i:04X}: {reg:{fmt}}')

 

 
             

@@ -234,7 +209,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -254,8 +229,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/iobar.html b/_modules/chipsec/hal/iobar.html
index aa6a6bc5..81c041c9 100644
--- a/_modules/chipsec/hal/iobar.html
+++ b/_modules/chipsec/hal/iobar.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.iobar — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -76,9 +78,7 @@ 
Source code for chipsec.hal.iobar
 DEFAULT_IO_BAR_SIZE = 0x100
 
 
-

-[docs]
-class IOBAR(hal_base.HALBase):
+
[docs]class IOBAR(hal_base.HALBase):
 
     def __init__(self, cs):
         super(IOBAR, self).__init__(cs)
@@ -87,9 +87,7 @@ 
Source code for chipsec.hal.iobar
     # Check if I/O BAR with bar_name has been defined in XML config
     # Use this function to fall-back to hardcoded config in case XML config is not available
     #
-

-[docs]
-    def is_IO_BAR_defined(self, bar_name: str) -> bool:
+
[docs]    def is_IO_BAR_defined(self, bar_name: str) -> bool:
         try:
             return (self.cs.Cfg.IO_BARS[bar_name] is not None)
         except KeyError:
@@ -97,13 +95,10 @@ 
Source code for chipsec.hal.iobar
                 logger().log_error(f"'{bar_name}' I/O BAR definition not found in XML config")
             return False

 
-
     #
     # Get base address of I/O range by IO BAR name
     #
-

-[docs]
-    def get_IO_BAR_base_address(self, bar_name: str) -> Tuple[int, int]:
+
[docs]    def get_IO_BAR_base_address(self, bar_name: str) -> Tuple[int, int]:
         bar = self.cs.Cfg.IO_BARS[bar_name]
         if bar is None or bar == {}:
             raise IOBARNotFoundError(f'IOBARNotFound: {bar_name}')
@@ -151,13 +146,10 @@ 
Source code for chipsec.hal.iobar
             raise CSReadError(f'IOBAR ({bar_name}) base address is 0')
         return base, size

 
-
     #
     # Read I/O register from I/O range defined by I/O BAR name
     #
-

-[docs]
-    def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int:
+
[docs]    def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int:
         if logger().HAL:
             logger().log(f'[iobar] read {bar_name} + 0x{offset:X} ({size:d})')
         (bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
@@ -167,13 +159,10 @@ 
Source code for chipsec.hal.iobar
         value = self.cs.io._read_port(io_port, size)
         return value

 
-
     #
     # Write I/O register from I/O range defined by I/O BAR name
     #
-

-[docs]
-    def write_IO_BAR_reg(self, bar_name: str, offset: int, size: int, value: int) -> int:
+
[docs]    def write_IO_BAR_reg(self, bar_name: str, offset: int, size: int, value: int) -> int:
         (bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
         if logger().HAL:
             logger().log(f'[iobar] write {bar_name} + 0x{offset:X} ({size:d}): 0x{value:X}')
@@ -182,13 +171,10 @@ 
Source code for chipsec.hal.iobar
             logger().log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
         return self.cs.io._write_port(io_port, value, size)

 
-
     #
     # Check if I/O range is enabled by BAR name
     #
-

-[docs]
-    def is_IO_BAR_enabled(self, bar_name: str) -> bool:
+
[docs]    def is_IO_BAR_enabled(self, bar_name: str) -> bool:
         bar = self.cs.Cfg.IO_BARS[bar_name]
         is_enabled = True
         if 'register' in bar:
@@ -198,10 +184,7 @@ 
Source code for chipsec.hal.iobar
                 is_enabled = (1 == self.cs.read_register_field(bar_reg, bar_en_field))
         return is_enabled

 
-
-

-[docs]
-    def list_IO_BARs(self) -> None:
+
[docs]    def list_IO_BARs(self) -> None:
         logger().log('')
         logger().log('--------------------------------------------------------------------------------')
         logger().log(' I/O Range    | BAR Register   | Base             | Size     | En? | Description')
@@ -221,19 +204,16 @@ 
Source code for chipsec.hal.iobar
             if 'register' in _bar:
                 _s = _bar['register']
                 if 'offset' in _bar:
-                    _s += (f' + 0x{int(_bar["offset"], 16):X}')
+                    _s += (f' + 0x{int(_bar["offset"], 16):X}')
             else:
-                _s = f'{int(_bar["bus"], 16):02X}:{int(_bar["dev"], 16):02X}.{int(_bar["fun"], 16):01X} + {_bar["reg"]}'
+                _s = f'{int(_bar["bus"], 16):02X}:{int(_bar["dev"], 16):02X}.{int(_bar["fun"], 16):01X} + {_bar["reg"]}'
 
             logger().log(f' {_bar_name:12} | {_s:14} | {_base:016X} | {_size:08X} | {_en:d}   | {_bar["desc"]}')

 
-
     #
     # Read I/O range by I/O BAR name
     #
-

-[docs]
-    def read_IO_BAR(self, bar_name: str, size: int = 1) -> List[int]:
+
[docs]    def read_IO_BAR(self, bar_name: str, size: int = 1) -> List[int]:
         (range_base, range_size) = self.get_IO_BAR_base_address(bar_name)
         n = range_size // size
         io_ports = []
@@ -241,22 +221,17 @@ 
Source code for chipsec.hal.iobar
             io_ports.append(self.cs.io._read_port(range_base + i * size, size))
         return io_ports

 
-
     #
     # Dump I/O range by I/O BAR name
     #
-

-[docs]
-    def dump_IO_BAR(self, bar_name: str, size: int = 1) -> None:
+
[docs]    def dump_IO_BAR(self, bar_name: str, size: int = 1) -> None:
         (range_base, range_size) = self.get_IO_BAR_base_address(bar_name)
         n = range_size // size
-        fmt = f'0{size * 2:d}X'
+        fmt = f'0{size * 2:d}X'
         logger().log(f"[iobar] I/O BAR {bar_name}:")
         for i in range(n):
             reg = self.cs.io._read_port(range_base + i * size, size)
-            logger().log(f'{size * i:+04X}: {reg:{fmt}}')

-

-
+            logger().log(f'{size * i:+04X}: {reg:{fmt}}')

 

 
             

@@ -316,7 +291,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -336,8 +311,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/iommu.html b/_modules/chipsec/hal/iommu.html
index eb838edb..8e32d9ed 100644
--- a/_modules/chipsec/hal/iommu.html
+++ b/_modules/chipsec/hal/iommu.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.iommu — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,17 +77,13 @@ 
Source code for chipsec.hal.iommu
 }
 
 
-

-[docs]
-class IOMMU(hal_base.HALBase):
+
[docs]class IOMMU(hal_base.HALBase):
 
     def __init__(self, cs):
         super(IOMMU, self).__init__(cs)
         self.mmio = mmio.MMIO(cs)
 
-

-[docs]
-    def get_IOMMU_Base_Address(self, iommu_engine: str) -> int:
+
[docs]    def get_IOMMU_Base_Address(self, iommu_engine: str) -> int:
         if iommu_engine in IOMMU_ENGINES:
             vtd_base_name = IOMMU_ENGINES[iommu_engine]
         else:
@@ -97,33 +95,21 @@ 
Source code for chipsec.hal.iommu
             raise IOMMUError(f'IOMMUError: IOMMU BAR {vtd_base_name} is not defined in the config')
         return base

 
-
-

-[docs]
-    def is_IOMMU_Engine_Enabled(self, iommu_engine: str) -> bool:
+
[docs]    def is_IOMMU_Engine_Enabled(self, iommu_engine: str) -> bool:
         if iommu_engine in IOMMU_ENGINES:
             vtd_base_name = IOMMU_ENGINES[iommu_engine]
         else:
             raise IOMMUError(f'IOMMUError: unknown IOMMU engine 0x{iommu_engine:X}')
         return self.mmio.is_MMIO_BAR_defined(vtd_base_name) and self.mmio.is_MMIO_BAR_enabled(vtd_base_name)

 
-
-

-[docs]
-    def is_IOMMU_Translation_Enabled(self, iommu_engine: str) -> bool:
+
[docs]    def is_IOMMU_Translation_Enabled(self, iommu_engine: str) -> bool:
         tes = self.cs.read_register_field(f'{IOMMU_ENGINES[iommu_engine]}_GSTS', 'TES')
         return (1 == tes)

 
-
-

-[docs]
-    def set_IOMMU_Translation(self, iommu_engine: str, te: int) -> bool:
+
[docs]    def set_IOMMU_Translation(self, iommu_engine: str, te: int) -> bool:
         return self.cs.write_register_field(f'{IOMMU_ENGINES[iommu_engine]}_GCMD', 'TE', te)

 
-
-

-[docs]
-    def dump_IOMMU_configuration(self, iommu_engine: str) -> None:
+
[docs]    def dump_IOMMU_configuration(self, iommu_engine: str) -> None:
         self.logger.log("==================================================================")
         vtd = IOMMU_ENGINES[iommu_engine]
         self.logger.log(f'[iommu] {iommu_engine} IOMMU Engine Configuration')
@@ -169,10 +155,7 @@ 
Source code for chipsec.hal.iommu
         self.cs.print_register(f'{vtd}_ECAP', ecap_reg)
         self.logger.log('')

 
-
-

-[docs]
-    def dump_IOMMU_page_tables(self, iommu_engine: str) -> None:
+
[docs]    def dump_IOMMU_page_tables(self, iommu_engine: str) -> None:
         vtd = IOMMU_ENGINES[iommu_engine]
         if self.cs.read_register(vtd) == 0:
             self.logger.log(f'[iommu] {vtd} value is zero')
@@ -202,10 +185,7 @@ 
Source code for chipsec.hal.iommu
         else:
             self.logger.log_error("Cannot access VT-d registers")

 
-
-

-[docs]
-    def dump_IOMMU_status(self, iommu_engine: str) -> None:
+
[docs]    def dump_IOMMU_status(self, iommu_engine: str) -> None:
         vtd = IOMMU_ENGINES[iommu_engine]
         self.logger.log('==================================================================')
         self.logger.log(f'[iommu] {iommu_engine} IOMMU Engine Status:')
@@ -223,9 +203,7 @@ 
Source code for chipsec.hal.iommu
         self.cs.print_register(f'{vtd}_FRCDH', frcdh_reg)
         ics_reg = self.cs.read_register(f'{vtd}_ICS')
         self.cs.print_register(f'{vtd}_ICS', ics_reg)
-        return None

-

-
+        return None

 

 
             

@@ -285,7 +263,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -305,8 +283,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/locks.html b/_modules/chipsec/hal/locks.html
index bc928b93..60d6b03d 100644
--- a/_modules/chipsec/hal/locks.html
+++ b/_modules/chipsec/hal/locks.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.locks — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -65,9 +67,7 @@ 
Source code for chipsec.hal.locks
 from chipsec.exceptions import CSReadError, HWAccessViolationError
 
 
-

-[docs]
-class LockResult:
+
[docs]class LockResult:
     DEFINED = bit(0)  # lock exists within configuration
     HAS_CONFIG = bit(1)  # lock configuration exists
     LOCKED = bit(2)  # lock matches value within xml
@@ -75,25 +75,17 @@ 
Source code for chipsec.hal.locks
     INCONSISTENT = bit(4)  # all lock results do not match

 
 
-
-

-[docs]
-class locks(HALBase):
+
[docs]class locks(HALBase):
     def __init__(self, cs):
         super(locks, self).__init__(cs)
 
-

-[docs]
-    def get_locks(self) -> List[str]:
-        """
+
[docs]    def get_locks(self) -> List[str]:
+        """
         Return a list of locks defined within the configuration file
         """
         return self.cs.get_lock_list()

 
-
-

-[docs]
-    def lock_valid(self, lock_name: str, bus: Optional[int] = None) -> int:
+
[docs]    def lock_valid(self, lock_name: str, bus: Optional[int] = None) -> int:
         res = 0
         if self.cs.is_lock_defined(lock_name):
             res |= LockResult.DEFINED
@@ -110,11 +102,8 @@ 
Source code for chipsec.hal.locks
             res |= LockResult.HAS_CONFIG
         return res

 
-
-

-[docs]
-    def is_locked(self, lock_name: str, bus: Optional[int] = None) -> int:
-        """
+
[docs]    def is_locked(self, lock_name: str, bus: Optional[int] = None) -> int:
+        """
         Return whether the lock has the value setting
         """
         res = self.lock_valid(lock_name, bus)
@@ -125,9 +114,7 @@ 
Source code for chipsec.hal.locks
                 res |= LockResult.INCONSISTENT
             if all(locked == elem for elem in lock_setting):
                 res |= LockResult.LOCKED
-        return res

-

-
+        return res

 

 
             

@@ -187,7 +174,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -207,8 +194,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/mmio.html b/_modules/chipsec/hal/mmio.html
index bf7f90d8..94ccef3e 100644
--- a/_modules/chipsec/hal/mmio.html
+++ b/_modules/chipsec/hal/mmio.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.mmio — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -100,9 +102,7 @@ 
Source code for chipsec.hal.mmio
 PCI_PCIEBAR_REG_MASK = 0x7FFC000000
 
 
-

-[docs]
-class MMIO(hal_base.HALBase):
+
[docs]class MMIO(hal_base.HALBase):
 
     def __init__(self, cs):
         super(MMIO, self).__init__(cs)
@@ -126,9 +126,7 @@ 
Source code for chipsec.hal.mmio
     # Read MMIO register as an offset off of MMIO range base address
     #
 
-

-[docs]
-    def read_MMIO_reg(self, bar_base: int, offset: int, size: int = 4, bar_size: Optional[int] = None) -> int:
+
[docs]    def read_MMIO_reg(self, bar_base: int, offset: int, size: int = 4, bar_size: Optional[int] = None) -> int:
         if size > 8:
             if self.logger.HAL:
                 self.logger.log_warning("MMIO read cannot exceed 8")
@@ -136,84 +134,56 @@ 
Source code for chipsec.hal.mmio
         self.logger.log_hal(f'[mmio] 0x{bar_base:08X} + 0x{offset:08X} = 0x{reg_value:08X}')
         return reg_value

 
-
-

-[docs]
-    def read_MMIO_reg_byte(self, bar_base: int, offset: int) -> int:
+
[docs]    def read_MMIO_reg_byte(self, bar_base: int, offset: int) -> int:
         return self.read_MMIO_reg(bar_base, offset, 1)

 
-        
-

-[docs]
-    def read_MMIO_reg_word(self, bar_base: int, offset: int) -> int:
+
[docs]    def read_MMIO_reg_word(self, bar_base: int, offset: int) -> int:
         return self.read_MMIO_reg(bar_base, offset, 2)

 
-
-

-[docs]
-    def read_MMIO_reg_dword(self, bar_base: int, offset: int) -> int:
+
[docs]    def read_MMIO_reg_dword(self, bar_base: int, offset: int) -> int:
         return self.read_MMIO_reg(bar_base, offset, 4)

 
-
     #
     # Write MMIO register as an offset off of MMIO range base address
     #
-

-[docs]
-    def write_MMIO_reg(self, bar_base: int, offset: int, value: int, size: int = 4) -> int:
+
[docs]    def write_MMIO_reg(self, bar_base: int, offset: int, value: int, size: int = 4) -> int:
         address = bar_base + offset
         self.logger.log_hal(f'[mmio] write 0x{bar_base:08X} + 0x{offset:08X} = 0x{value:08X}')
         return self.cs.helper.write_mmio_reg(address, size, value)

 
-
-

-[docs]
-    def write_MMIO_reg_byte(self, bar_base: int, offset: int, value: int) -> int:
+
[docs]    def write_MMIO_reg_byte(self, bar_base: int, offset: int, value: int) -> int:
         address = bar_base + offset
         self.logger.log_hal(f'[mmio] write 0x{bar_base:08X} + 0x{offset:08X} = 0x{value:08X}')
         return self.cs.helper.write_mmio_reg(address, 1, value)

 
-
-

-[docs]
-    def write_MMIO_reg_word(self, bar_base: int, offset: int, value: int) -> int:
+
[docs]    def write_MMIO_reg_word(self, bar_base: int, offset: int, value: int) -> int:
         address = bar_base + offset
         self.logger.log_hal(f'[mmio] write 0x{bar_base:08X} + 0x{offset:08X} = 0x{value:08X}')
         return self.cs.helper.write_mmio_reg(address, 2, value)

 
-
-

-[docs]
-    def write_MMIO_reg_dword(self, bar_base: int, offset: int, value: int) -> int:
+
[docs]    def write_MMIO_reg_dword(self, bar_base: int, offset: int, value: int) -> int:
         address = bar_base + offset
         self.logger.log_hal(f'[mmio] write 0x{bar_base:08X} + 0x{offset:08X} = 0x{value:08X}')
         return self.cs.helper.write_mmio_reg(address, 4, value)

 
-
     #
     # Read MMIO registers as offsets off of MMIO range base address
     #
-

-[docs]
-    def read_MMIO(self, bar_base: int, size: int) -> List[int]:
+
[docs]    def read_MMIO(self, bar_base: int, size: int) -> List[int]:
         regs = []
         size -= size % 4
         for offset in range(0, size, 4):
             regs.append(self.read_MMIO_reg(bar_base, offset))
         return regs

 
-
     #
     # Dump MMIO range
     #
-

-[docs]
-    def dump_MMIO(self, bar_base: int, size: int) -> None:
+
[docs]    def dump_MMIO(self, bar_base: int, size: int) -> None:
         self.logger.log(f'[mmio] MMIO register range [0x{bar_base:016X}:0x{bar_base:016X}+{size:08X}]:')
         size -= size % 4
         for offset in range(0, size, 4):
-            self.logger.log(f'+{offset:08X}: {self.read_MMIO_reg(bar_base, offset):08X}')

-
+            self.logger.log(f'+{offset:08X}: {self.read_MMIO_reg(bar_base, offset):08X}')

 
     ###############################################################################
     # Access to MMIO BAR defined by XML configuration files (chipsec/cfg/*.xml)
@@ -224,9 +194,7 @@ 
Source code for chipsec.hal.mmio
     # Use this function to fall-back to hardcoded config in case XML config is not available
     #
 
-

-[docs]
-    def is_MMIO_BAR_defined(self, bar_name: str) -> bool:
+
[docs]    def is_MMIO_BAR_defined(self, bar_name: str) -> bool:
         is_bar_defined = False
         try:
             _bar = self.cs.Cfg.MMIO_BARS[bar_name]
@@ -244,32 +212,23 @@ 
Source code for chipsec.hal.mmio
                 self.logger.log_warning(f"'{bar_name}' MMIO BAR definition not found/correct in XML config")
         return is_bar_defined

 
-
     #
     # Enable caching of BAR addresses
     #
-

-[docs]
-    def enable_cache_address_resolution(self, enable: bool) -> None:
+
[docs]    def enable_cache_address_resolution(self, enable: bool) -> None:
         if enable:
             self.cache_bar_addresses_resolution = True
         else:
             self.cache_bar_addresses_resolution = False
             self.flush_bar_address_cache()

 
-
-

-[docs]
-    def flush_bar_address_cache(self) -> None:
+
[docs]    def flush_bar_address_cache(self) -> None:
         self.cached_bar_addresses = {}

 
-
     #
     # Get base address of MMIO range by MMIO BAR name
     #
-

-[docs]
-    def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) -> Tuple[int, int]:
+
[docs]    def get_MMIO_BAR_base_address(self, bar_name: str, bus: Optional[int] = None) -> Tuple[int, int]:
         if self.cache_bar_addresses_resolution and (bar_name, bus) in self.cached_bar_addresses:
             return self.cached_bar_addresses[(bar_name, bus)]
         bar = self.cs.Cfg.MMIO_BARS[bar_name]
@@ -355,13 +314,10 @@ 
Source code for chipsec.hal.mmio
             self.cached_bar_addresses[(bar_name, bus)] = (base, size)
         return base, size

 
-
     #
     # Check if MMIO range is enabled by MMIO BAR name
     #
-

-[docs]
-    def is_MMIO_BAR_enabled(self, bar_name: str, bus: Optional[int] = None) -> bool:
+
[docs]    def is_MMIO_BAR_enabled(self, bar_name: str, bus: Optional[int] = None) -> bool:
         if not self.is_MMIO_BAR_defined(bar_name):
             return False
         bar = self.cs.Cfg.MMIO_BARS[bar_name]
@@ -396,13 +352,10 @@ 
Source code for chipsec.hal.mmio
 
         return is_enabled

 
-
     #
     # Check if MMIO range is programmed by MMIO BAR name
     #
-

-[docs]
-    def is_MMIO_BAR_programmed(self, bar_name: str) -> bool:
+
[docs]    def is_MMIO_BAR_programmed(self, bar_name: str) -> bool:
         bar = self.cs.Cfg.MMIO_BARS[bar_name]
 
         if 'register' in bar:
@@ -429,50 +382,35 @@ 
Source code for chipsec.hal.mmio
         #if 'mask' in bar: base &= bar['mask']
         return (0 != base)

 
-
     #
     # Read MMIO register from MMIO range defined by MMIO BAR name
     #
-

-[docs]
-    def read_MMIO_BAR_reg(self, bar_name: str, offset: int, size: int = 4, bus: Optional[int] = None) -> int:
+
[docs]    def read_MMIO_BAR_reg(self, bar_name: str, offset: int, size: int = 4, bus: Optional[int] = None) -> int:
         (bar_base, bar_size) = self.get_MMIO_BAR_base_address(bar_name, bus)
         # @TODO: check offset exceeds BAR size
         return self.read_MMIO_reg(bar_base, offset, size, bar_size)

 
-
     #
     # Write MMIO register from MMIO range defined by MMIO BAR name
     #
-

-[docs]
-    def write_MMIO_BAR_reg(self, bar_name: str, offset: int, value: int, size: int = 4, bus: Optional[int] = None) -> Optional[int]:
+
[docs]    def write_MMIO_BAR_reg(self, bar_name: str, offset: int, value: int, size: int = 4, bus: Optional[int] = None) -> Optional[int]:
         (bar_base, _) = self.get_MMIO_BAR_base_address(bar_name, bus)
         # @TODO: check offset exceeds BAR size
-        
-        return self.write_MMIO_reg(bar_base, offset, value, size)

 
+        return self.write_MMIO_reg(bar_base, offset, value, size)

 
-

-[docs]
-    def read_MMIO_BAR(self, bar_name: str, bus: Optional[int] = None) -> List[int]:
+
[docs]    def read_MMIO_BAR(self, bar_name: str, bus: Optional[int] = None) -> List[int]:
         (bar_base, bar_size) = self.get_MMIO_BAR_base_address(bar_name, bus)
         return self.read_MMIO(bar_base, bar_size)

 
-
     #
     # Dump MMIO range by MMIO BAR name
     #
-

-[docs]
-    def dump_MMIO_BAR(self, bar_name: str) -> None:
+
[docs]    def dump_MMIO_BAR(self, bar_name: str) -> None:
         (bar_base, bar_size) = self.get_MMIO_BAR_base_address(bar_name)
         self.dump_MMIO(bar_base, bar_size)

 
-
-

-[docs]
-    def list_MMIO_BARs(self) -> None:
+
[docs]    def list_MMIO_BARs(self) -> None:
         self.logger.log('')
         self.logger.log('--------------------------------------------------------------------------------------')
         self.logger.log(' MMIO Range   | BUS | BAR Register   | Base             | Size     | En? | Description')
@@ -486,12 +424,13 @@ 
Source code for chipsec.hal.mmio
                 bus_data = self.cs.get_register_bus(_bar['register'])
                 if not bus_data:
                     if 'bus' in self.cs.get_register_def(_bar['register']):
-                        bus_data = [int(self.cs.get_register_def(_bar['register'])['bus'], 16)]
+                        bus_data.extend(self.cs.get_register_def(_bar['register'])['bus'])
             elif 'bus' in _bar:
-                bus_data = [_bar['bus']]
+                bus_data.extend(_bar['bus'])
             else:
                 continue
             for bus in bus_data:
+                bus = self.cs.get_first(bus)
                 try:
                     (_base, _size) = self.get_MMIO_BAR_base_address(_bar_name, bus)
                 except:
@@ -504,21 +443,18 @@ 
Source code for chipsec.hal.mmio
                     if 'offset' in _bar:
                         _s += (f' + 0x{_bar["offset"]:X}')
                 else:
-                    bus_value = _bar["bus"]
+                    bus_value = self.cs.get_first(_bar["bus"])
                     dev_value = _bar["dev"]
                     fun_value = _bar["fun"]
                     _s = f'{bus_value:02X}:{dev_value:02X}.{fun_value:01X} + {_bar["reg"]}'
 
-                self.logger.log(f' {_bar_name:12} |  {bus or 0:02X} | {_s:14} | {_base:016X} | {_size:08X} | {_en:d}   | {_bar["desc"]}')

-
+                self.logger.log(f' {_bar_name:12} |  {bus or 0:02X} | {_s:14} | {_base:016X} | {_size:08X} | {_en:d}   | {_bar["desc"]}')

 
     ##################################################################################
     # Access to Memory Mapped PCIe Configuration Space
     ##################################################################################
 
-

-[docs]
-    def get_MMCFG_base_address(self) -> Tuple[int, int]:
+
[docs]    def get_MMCFG_base_address(self) -> Tuple[int, int]:
         (bar_base, bar_size) = self.get_MMIO_BAR_base_address('MMCFG')
         if self.cs.register_has_field("PCI0.0.0_PCIEXBAR", "LENGTH") and not self.cs.is_server():
             len = self.cs.read_register_field("PCI0.0.0_PCIEXBAR", "LENGTH")
@@ -545,10 +481,7 @@ 
Source code for chipsec.hal.mmio
         self.logger.log_hal(f'[mmcfg] Memory Mapped CFG Base: 0x{bar_base:016X}')
         return bar_base, bar_size

 
-
-

-[docs]
-    def read_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int) -> int:
+
[docs]    def read_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int) -> int:
         pciexbar, _ = self.get_MMCFG_base_address()
         pciexbar_off = (bus * 32 * 8 + dev * 8 + fun) * 0x1000 + off
         value = self.read_MMIO_reg(pciexbar, pciexbar_off, size)
@@ -559,10 +492,7 @@ 
Source code for chipsec.hal.mmio
             return (value & 0xFFFF)
         return value

 
-
-

-[docs]
-    def write_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int, value: int) -> bool:
+
[docs]    def write_mmcfg_reg(self, bus: int, dev: int, fun: int, off: int, size: int, value: int) -> bool:
         pciexbar, _ = self.get_MMCFG_base_address()
         pciexbar_off = (bus * 32 * 8 + dev * 8 + fun) * 0x1000 + off
         if size == 1:
@@ -575,10 +505,7 @@ 
Source code for chipsec.hal.mmio
         self.logger.log_hal(f'[mmcfg] writing {bus:02d}:{dev:02d}.{fun:d} + 0x{off:02X} (MMCFG + 0x{pciexbar_off:08X}): 0x{value:08X}')
         return True

 
-
-

-[docs]
-    def get_extended_capabilities(self, bus: int, dev: int, fun: int) -> List['ECEntry']:
+
[docs]    def get_extended_capabilities(self, bus: int, dev: int, fun: int) -> List['ECEntry']:
         retcap = []
         off = 0x100
         while off and off != 0xFFF:
@@ -587,20 +514,13 @@ 
Source code for chipsec.hal.mmio
             off = get_bits(cap, 20, 12)
         return retcap

 
-
-

-[docs]
-    def get_vsec(self, bus: int, dev: int, fun: int, ecoff: int) -> 'VSECEntry':
+
[docs]    def get_vsec(self, bus: int, dev: int, fun: int, ecoff: int) -> 'VSECEntry':
         off = ecoff + 4
         vsec = self.read_mmcfg_reg(bus, dev, fun, off, 4)
-        return VSECEntry(vsec)

-

-
+        return VSECEntry(vsec)

 
 
-

-[docs]
-class ECEntry:
+
[docs]class ECEntry:
     def __init__(self, bus: int, dev: int, fun: int, off: int, value: int):
         self.bus = bus
         self.dev = dev
@@ -608,23 +528,29 @@ 
Source code for chipsec.hal.mmio
         self.off = off
         self.next = get_bits(value, 20, 12)
         self.ver = get_bits(value, 16, 4)
-        self.id = get_bits(value, 0, 16)

+        self.id = get_bits(value, 0, 16)
 
+    def __str__(self) -> str:
+        ret = f'\tNext Capability Offset: {self.next:03X}'
+        ret += f'\tCapability Version: {self.ver:01X}'
+        ret += f'\tCapability ID: {self.id:04X} - {ecIDs.get(self.id, "Reserved")}'
+        return ret

 
 
-

-[docs]
-class VSECEntry:
+
[docs]class VSECEntry:
     def __init__(self, value: int):
         self.size = get_bits(value, 20, 12)
         self.rev = get_bits(value, 16, 4)
-        self.id = get_bits(value, 0, 16)

+        self.id = get_bits(value, 0, 16)
 
+    def __str__(self) -> str:
+        ret = f'\tVSEC Size: {self.size:03X}'
+        ret += f'\tVSEC Revision: {self.rev:01X}'
+        ret += f'\tVSEC ID: {self.id:04X}'
+        return ret

 
 
-
 

-
+
         

       

       

@@ -765,8 +690,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/msgbus.html b/_modules/chipsec/hal/msgbus.html
index fb47dc55..9eaa1d54 100644
--- a/_modules/chipsec/hal/msgbus.html
+++ b/_modules/chipsec/hal/msgbus.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.msgbus — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -83,9 +85,7 @@ 
Source code for chipsec.hal.msgbus
 # IOSF Message bus message opcodes
 # Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
 #
-

-[docs]
-class MessageBusOpcode:
+
[docs]class MessageBusOpcode:
     MB_OPCODE_MMIO_READ = 0x00
     MB_OPCODE_MMIO_WRITE = 0x01
     MB_OPCODE_IO_READ = 0x02
@@ -99,7 +99,6 @@ 
Source code for chipsec.hal.msgbus
     MB_OPCODE_ESRAM_READ = 0x12
     MB_OPCODE_ESRAM_WRITE = 0x13

 
-
 #
 # IOSF Message bus unit ports
 # Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
@@ -107,9 +106,7 @@ 
Source code for chipsec.hal.msgbus
 #
 
 
-

-[docs]
-class MessageBusPort_Atom:
+
[docs]class MessageBusPort_Atom:
     UNIT_AUNIT = 0x00
     UNIT_SMC = 0x01
     UNIT_CPU = 0x02
@@ -122,10 +119,7 @@ 
Source code for chipsec.hal.msgbus
     UNIT_PCIE = 0xA6

 
 
-
-

-[docs]
-class MessageBusPort_Quark:
+
[docs]class MessageBusPort_Quark:
     UNIT_HBA = 0x00
     UNIT_HB = 0x03
     UNIT_RMU = 0x04
@@ -133,10 +127,7 @@ 
Source code for chipsec.hal.msgbus
     UNIT_SOC = 0x31

 
 
-
-

-[docs]
-class MsgBus(hal_base.HALBase):
+
[docs]class MsgBus(hal_base.HALBase):
 
     def __init__(self, cs):
         super(MsgBus, self).__init__(cs)
@@ -180,9 +171,7 @@ 
Source code for chipsec.hal.msgbus
     #
     # Issues read message on the message bus
     #
-

-[docs]
-    def msgbus_read_message(self, port: int, register: int, opcode: int) -> Optional[int]:
+
[docs]    def msgbus_read_message(self, port: int, register: int, opcode: int) -> Optional[int]:
         mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
         mcrx = self.__MB_MESSAGE_MCRX(register)
 
@@ -195,13 +184,10 @@ 
Source code for chipsec.hal.msgbus
 
         return mdr_out

 
-
     #
     # Issues write message on the message bus
     #
-

-[docs]
-    def msgbus_write_message(self, port: int, register: int, opcode: int, data: int) -> None:
+
[docs]    def msgbus_write_message(self, port: int, register: int, opcode: int, data: int) -> None:
         mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
         mcrx = self.__MB_MESSAGE_MCRX(register)
         mdr = self.__MB_MESSAGE_MDR(data)
@@ -211,13 +197,10 @@ 
Source code for chipsec.hal.msgbus
 
         return self.helper.msgbus_send_write_message(mcr, mcrx, mdr)

 
-
     #
     # Issues generic message on the message bus
     #
-

-[docs]
-    def msgbus_send_message(self, port: int, register: int, opcode: int, data: Optional[int] = None) -> Optional[int]:
+
[docs]    def msgbus_send_message(self, port: int, register: int, opcode: int, data: Optional[int] = None) -> Optional[int]:
         mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
         mcrx = self.__MB_MESSAGE_MCRX(register)
         mdr = None if data is None else self.__MB_MESSAGE_MDR(data)
@@ -233,26 +216,17 @@ 
Source code for chipsec.hal.msgbus
 
         return mdr_out

 
-
     #
     # Message bus register read/write
     #
 
-

-[docs]
-    def msgbus_reg_read(self, port: int, register: int) -> Optional[int]:
+
[docs]    def msgbus_reg_read(self, port: int, register: int) -> Optional[int]:
         return self.msgbus_read_message(port, register, MessageBusOpcode.MB_OPCODE_REG_READ)

 
-
-

-[docs]
-    def msgbus_reg_write(self, port: int, register: int, data: int) -> None:
+
[docs]    def msgbus_reg_write(self, port: int, register: int, data: int) -> None:
         return self.msgbus_write_message(port, register, MessageBusOpcode.MB_OPCODE_REG_WRITE, data)

 
-
-

-[docs]
-    def mm_msgbus_reg_read(self, port: int, register: int) -> int:
+
[docs]    def mm_msgbus_reg_read(self, port: int, register: int) -> int:
         was_hidden = False
         if self.cs.is_register_defined('P2SBC'):
             was_hidden = self.__hide_p2sb(False)
@@ -262,10 +236,7 @@ 
Source code for chipsec.hal.msgbus
             self.__hide_p2sb(True)
         return reg_val

 
-
-

-[docs]
-    def mm_msgbus_reg_write(self, port: int, register: int, data: int) -> Optional[int]:
+
[docs]    def mm_msgbus_reg_write(self, port: int, register: int, data: int) -> Optional[int]:
         was_hidden = False
         if self.cs.is_register_defined('P2SBC'):
             was_hidden = self.__hide_p2sb(False)
@@ -273,9 +244,7 @@ 
Source code for chipsec.hal.msgbus
         reg_val = self.cs.mmio.write_MMIO_reg_dword(mmio_addr, ((port & 0xFF) << 16) | (register & 0xFFFF), data)
         if self.cs.is_register_defined('P2SBC') and was_hidden:
             self.__hide_p2sb(True)
-        return reg_val

-

-
+        return reg_val

 

 
             

@@ -335,7 +304,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -355,8 +324,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/msr.html b/_modules/chipsec/hal/msr.html
index c9bb6662..7bad4ad1 100644
--- a/_modules/chipsec/hal/msr.html
+++ b/_modules/chipsec/hal/msr.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.msr — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -95,17 +97,13 @@ 
Source code for chipsec.hal.msr
 }
 
 
-

-[docs]
-class Msr:
+
[docs]class Msr:
 
     def __init__(self, cs):
         self.helper = cs.helper
         self.cs = cs
 
-

-[docs]
-    def get_cpu_thread_count(self) -> int:
+
[docs]    def get_cpu_thread_count(self) -> int:
         thread_count = self.helper.get_threads_count()
         if thread_count is None or thread_count < 0:
             logger().log_hal("helper.get_threads_count didn't return anything. Reading MSR 0x35 to find out number of logical CPUs (use CPUID Leaf B instead?)")
@@ -116,16 +114,12 @@ 
Source code for chipsec.hal.msr
         logger().log_hal(f'[cpu] # of logical CPUs: {thread_count:d}')
         return thread_count

 
-
     # @TODO: fix
-

-[docs]
-    def get_cpu_core_count(self) -> int:
+
[docs]    def get_cpu_core_count(self) -> int:
         core_count = self.cs.read_register_field("IA32_MSR_CORE_THREAD_COUNT", "Core_Count")
         return core_count

 
 
-
 ##########################################################################################################
 #
 # Read/Write CPU MSRs
@@ -133,63 +127,45 @@ 
Source code for chipsec.hal.msr
 ##########################################################################################################
 
 
-

-[docs]
-    def read_msr(self, cpu_thread_id: int, msr_addr: int) -> Tuple[int, int]:
+
[docs]    def read_msr(self, cpu_thread_id: int, msr_addr: int) -> Tuple[int, int]:
         (eax, edx) = self.helper.read_msr(cpu_thread_id, msr_addr)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] RDMSR( 0x{msr_addr:x} ): EAX = 0x{eax:08X}, EDX = 0x{edx:08X}')
         return (eax, edx)

 
-
-

-[docs]
-    def write_msr(self, cpu_thread_id: int, msr_addr: int, eax: int, edx: int) -> None:
+
[docs]    def write_msr(self, cpu_thread_id: int, msr_addr: int, eax: int, edx: int) -> None:
         self.helper.write_msr(cpu_thread_id, msr_addr, eax, edx)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] WRMSR( 0x{msr_addr:x} ): EAX = 0x{eax:08X}, EDX = 0x{edx:08X}')
         return None

 
-
 ##########################################################################################################
 #
 # Get CPU Descriptor Table Registers (IDTR, GDTR, LDTR..)
 #
 ##########################################################################################################
 
-

-[docs]
-    def get_Desc_Table_Register(self, cpu_thread_id: int, code: int) -> Tuple[int, int, int]:
+
[docs]    def get_Desc_Table_Register(self, cpu_thread_id: int, code: int) -> Tuple[int, int, int]:
         desc_table = self.helper.get_descriptor_table(cpu_thread_id, code)
         if desc_table is None:
             logger().log_hal(f'[msr] Unable to locate CPU Descriptor Table: Descriptor table code = {code:d}')
             return (0, 0, 0)
         return desc_table

 
-
-

-[docs]
-    def get_IDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
+
[docs]    def get_IDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
         (limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_IDTR)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] IDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
         return (limit, base, pa)

 
-
-

-[docs]
-    def get_GDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
+
[docs]    def get_GDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
         (limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_GDTR)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] GDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
         return (limit, base, pa)

 
-
-

-[docs]
-    def get_LDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
+
[docs]    def get_LDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
         (limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_LDTR)
         logger().log_hal(f'[cpu{cpu_thread_id:d}] LDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
         return (limit, base, pa)

 
 
-
 ##########################################################################################################
 #
 # Dump CPU Descriptor Tables (IDT, GDT, LDT..)
@@ -197,9 +173,7 @@ 
Source code for chipsec.hal.msr
 ##########################################################################################################
 
 
-

-[docs]
-    def dump_Descriptor_Table(self, cpu_thread_id: int, code: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
+
[docs]    def dump_Descriptor_Table(self, cpu_thread_id: int, code: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
         (limit, _, pa) = self.helper.get_descriptor_table(cpu_thread_id, code)
         dt = self.helper.read_phys_mem(pa, limit + 1)
         total_num = len(dt) // 16
@@ -220,35 +194,21 @@ 
Source code for chipsec.hal.msr
 
         return (pa, dt)

 
-
-

-[docs]
-    def IDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
+
[docs]    def IDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
         logger().log_hal(f'[cpu{cpu_thread_id:d}] IDT:')
         return self.dump_Descriptor_Table(cpu_thread_id, DESCRIPTOR_TABLE_CODE_IDTR, num_entries)

 
-
-

-[docs]
-    def GDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
+
[docs]    def GDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
         logger().log_hal(f'[cpu{cpu_thread_id:d}] GDT:')
         return self.dump_Descriptor_Table(cpu_thread_id, DESCRIPTOR_TABLE_CODE_GDTR, num_entries)

 
-
-

-[docs]
-    def IDT_all(self, num_entries: Optional[int] = None) -> None:
+
[docs]    def IDT_all(self, num_entries: Optional[int] = None) -> None:
         for tid in range(self.get_cpu_thread_count()):
             self.IDT(tid, num_entries)

 
-
-

-[docs]
-    def GDT_all(self, num_entries: Optional[int] = None) -> None:
+
[docs]    def GDT_all(self, num_entries: Optional[int] = None) -> None:
         for tid in range(self.get_cpu_thread_count()):
-            self.GDT(tid, num_entries)

-

-
+            self.GDT(tid, num_entries)

 

 
             

@@ -308,7 +268,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -328,8 +288,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/paging.html b/_modules/chipsec/hal/paging.html
index b29c9768..5396547b 100644
--- a/_modules/chipsec/hal/paging.html
+++ b/_modules/chipsec/hal/paging.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.paging — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -80,22 +82,15 @@ 
Source code for chipsec.hal.paging
 
 TranslationType = Dict[int, Dict[str, Any]]  # TODO: TypedDict (PEP589)
 
-

-[docs]
-class c_translation:
+
[docs]class c_translation:
 
     def __init__(self):
         self.translation: TranslationType = {}
 
-

-[docs]
-    def is_translation_exist(self, addr: int, mask: int, size: str) -> bool:
+
[docs]    def is_translation_exist(self, addr: int, mask: int, size: str) -> bool:
         return ((addr & mask) in self.translation) and (self.translation[addr & mask]['size'] == size)

 
-
-

-[docs]
-    def get_translation(self, addr: int) -> Optional[int]:
+
[docs]    def get_translation(self, addr: int) -> Optional[int]:
         if len(self.translation) == 0:
             return addr
         ADDR_4KB = 0xFFFFFFFFFFFFF000
@@ -111,10 +106,7 @@ 
Source code for chipsec.hal.paging
             result = None
         return result

 
-
-

-[docs]
-    def get_pages_by_physaddr(self, addr: int) -> List[Dict[str, int]]:
+
[docs]    def get_pages_by_physaddr(self, addr: int) -> List[Dict[str, int]]:
         SIZE = {'4KB': ADDR_4KB, '2MB': ADDR_2MB, '1GB': ADDR_1GB}
         result = []
         for i in self.translation.keys():
@@ -124,20 +116,14 @@ 
Source code for chipsec.hal.paging
                 result.append(page)
         return result

 
-
-

-[docs]
-    def get_address_space(self) -> int:
+
[docs]    def get_address_space(self) -> int:
         total = 0
         mem_range = self.get_mem_range()
         for i in mem_range:
             total += i[1] - i[0]
         return total

 
-
-

-[docs]
-    def get_mem_range(self, noattr: bool = False) -> List[List[int]]:
+
[docs]    def get_mem_range(self, noattr: bool = False) -> List[List[int]]:
         SIZE = {'4KB': SIZE_4KB, '2MB': SIZE_2MB, '1GB': SIZE_1GB}
         perm = {self.translation[a]['addr']: self.translation[a] for a in self.translation.keys()}
         mem_range = []
@@ -154,27 +140,18 @@ 
Source code for chipsec.hal.paging
                 mem_range += [[addr, addr + size, attr]]
         return mem_range

 
-
-

-[docs]
-    def add_page(self, virt: int, phys: int, size: str, attr: str) -> None:
+
[docs]    def add_page(self, virt: int, phys: int, size: str, attr: str) -> None:
         if size not in ['4KB', '2MB', '4MB', '1GB']:
             raise Exception('Invalid size!')
         self.translation[virt] = {'addr': phys, 'size': size, 'attr': attr}
         return

 
-
-

-[docs]
-    def del_page(self, addr: int) -> None:
+
[docs]    def del_page(self, addr: int) -> None:
         if addr in self.translation:
             del self.translation[addr]
         return

 
-
-

-[docs]
-    def expand_pages(self, exp_size: str) -> None:
+
[docs]    def expand_pages(self, exp_size: str) -> None:
         SIZE = {'1GB': '2MB', '2MB': '4KB'}
         for virt in self.translation.keys():
             size = self.translation[virt]['size']
@@ -184,14 +161,10 @@ 
Source code for chipsec.hal.paging
             if size == exp_size:
                 for i in range(512):
                     self.add_page(virt + i * pgsize, phys + i * pgsize, SIZE[exp_size], attr)
-        return

-

+        return

 
 
-
-

-[docs]
-class c_reverse_translation:
+
[docs]class c_reverse_translation:
 
     def __init__(self, translation: TranslationType):
         self.reverse_translation: Dict[int, List[Dict[str, Any]]] = {}
@@ -203,56 +176,38 @@ 
Source code for chipsec.hal.paging
                 self.reverse_translation[phys] = []
             self.reverse_translation[phys].append({'addr': virt, 'size': size, 'attr': attr})
 
-

-[docs]
-    def get_reverse_translation(self, addr: int) ->  List[Dict[str, Any]]:
+
[docs]    def get_reverse_translation(self, addr: int) ->  List[Dict[str, Any]]:
         ADDR_4KB = 0xFFFFFFFFFFFFF000
         addr &= ADDR_4KB
-        return self.reverse_translation[addr] if addr in self.reverse_translation else []

-

+        return self.reverse_translation[addr] if addr in self.reverse_translation else []

 
 
-
-

-[docs]
-class c_paging_memory_access:
+
[docs]class c_paging_memory_access:
 
     def __init__(self, cs):
         self.cs = cs
 
-

-[docs]
-    def readmem(self, name: str, addr: int, size: int = 4096) -> bytes:
-        return self.cs.mem.read_physical_mem(addr, size)

-

-
+
[docs]    def readmem(self, name: str, addr: int, size: int = 4096) -> bytes:
+        return self.cs.mem.read_physical_mem(addr, size)

 
 
-

-[docs]
-class c_paging_with_2nd_level_translation(c_paging_memory_access):
+
[docs]class c_paging_with_2nd_level_translation(c_paging_memory_access):
 
     def __init__(self, cs):
         c_paging_memory_access.__init__(self, cs)
         self.translation_level2 = c_translation()
 
-

-[docs]
-    def readmem(self, name: str, addr: int, size: int = 4096) -> bytes:
+
[docs]    def readmem(self, name: str, addr: int, size: int = 4096) -> bytes:
         phys = self.translation_level2.get_translation(addr)
         if phys is None:
             logger().log_hal('[paging] get_translation(): phys is None. Returning 0.')
             return b''
         if phys != addr:
             name += f'_0x{phys:08X}'
-        return super(c_paging_with_2nd_level_translation, self).readmem(name, phys, size)

-

+        return super(c_paging_with_2nd_level_translation, self).readmem(name, phys, size)

 
 
-
-

-[docs]
-class c_paging(c_paging_with_2nd_level_translation, c_translation):
+
[docs]class c_paging(c_paging_with_2nd_level_translation, c_translation):
     def __init__(self, cs):
         c_paging_with_2nd_level_translation.__init__(self, cs)
         c_translation.__init__(self)
@@ -265,29 +220,18 @@ 
Source code for chipsec.hal.paging
         self.failure = False
         self.canonical_msb = 47
 
-

-[docs]
-    def get_canonical(self, va: int) -> int:
+
[docs]    def get_canonical(self, va: int) -> int:
         canonical_mask = (ADDR_MASK << (self.canonical_msb + 1)) & ADDR_MASK
         canonical_va = (va | canonical_mask) if (va >> self.canonical_msb) & 0x1 else va
         return canonical_va

 
-
-

-[docs]
-    def get_field(self, entry: int, desc: Dict[str, int]) -> int:
+
[docs]    def get_field(self, entry: int, desc: Dict[str, int]) -> int:
         return (entry >> desc['offset']) & desc['mask']

 
-
-

-[docs]
-    def set_field(self, value: int, desc: Dict[str, int]) -> int:
+
[docs]    def set_field(self, value: int, desc: Dict[str, int]) -> int:
         return (value & desc['mask']) << desc['offset']

 
-
-

-[docs]
-    def read_entries(self, info: str, addr: int, size: int = 8) -> List[Any]:
+
[docs]    def read_entries(self, info: str, addr: int, size: int = 8) -> List[Any]:
         data = self.readmem(f'{self.name}_{info}_0x{addr:08X}', addr, 0x1000)
         entries = struct.unpack('<512Q', data)
         if size == 16:
@@ -300,27 +244,21 @@ 
Source code for chipsec.hal.paging
             return [entries[0]]
         return entries

 
-
-

-[docs]
-    def print_info(self, name: str) -> None:
+
[docs]    def print_info(self, name: str) -> None:
         logger().log(f'\n  {name} physical address ranges:')
         mem_range = self.get_mem_range()
         for index in range(len(mem_range)):
             i = mem_range[index]
-            logger().log(f'    0x{i[0]:013X} - 0x{i[1] - 1:013X} {(i[1] - i[0]) >> 12:8d}  {i[2]}')
+            logger().log(f'    0x{i[0]:013X} - 0x{i[1] - 1:013X} {(i[1] - i[0]) >> 12:8d}  {i[2]}')
 
         logger().log(f'\n  {name} pages:')
         for i in sorted(self.pt.keys()):
             logger().log(f'    0x{i:013X}  {self.pt[i]}')
         logger().log('\n')
-        logger().log(f'  {name} size: {len(self.pt.keys()) * 4:d} KB, address space: {self.get_address_space() >> 20:d} MB')
+        logger().log(f'  {name} size: {len(self.pt.keys()) * 4:d} KB, address space: {self.get_address_space() >> 20:d} MB')
         return

 
-
-

-[docs]
-    def check_misconfig(self, addr_list: List[int]) -> None:
+
[docs]    def check_misconfig(self, addr_list: List[int]) -> None:
         addr_list = [x & MAXPHYADDR for x in addr_list]
         mem_range = self.get_mem_range()
         for addr in addr_list:
@@ -329,10 +267,7 @@ 
Source code for chipsec.hal.paging
                     logger().log_hal(f'*** WARNING: PAGE TABLES MISCONFIGURATION  0x{addr:013X}')
         return

 
-
-

-[docs]
-    def save_configuration(self, path: str) -> None:
+
[docs]    def save_configuration(self, path: str) -> None:
         with open(path, 'w') as cfg:
             try:
                 cfg.write(str(self.translation_level2.translation) + '\n')
@@ -342,10 +277,7 @@ 
Source code for chipsec.hal.paging
                 logger().log_hal(f'[paging] Error saving: {path}')
         return

 
-
-

-[docs]
-    def load_configuration(self, path: str) -> None:
+
[docs]    def load_configuration(self, path: str) -> None:
         with open(path, 'r') as cfg:
             try:
                 self.translation_level2.translation = eval(cfg.readline())
@@ -355,10 +287,7 @@ 
Source code for chipsec.hal.paging
                 logger().log_hal(f'[paging] Error loading: {path}')
         return

 
-
-

-[docs]
-    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
+
[docs]    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
         logger().log_hal(f'[paging] Reading {name} page tables at 0x{ptr:016X}...')
         try:
             self.read_page_tables(ptr)
@@ -372,21 +301,14 @@ 
Source code for chipsec.hal.paging
         else:
             self.print_info(f'[paging] {name} page tables')
             self.failure = False
-            logger().log_hal(f'[paging] size: {len(self.pt.keys()) * 4:d} KB, address space: {self.get_address_space() >> 20:d} MB')
+            logger().log_hal(f'[paging] size: {len(self.pt.keys()) * 4:d} KB, address space: {self.get_address_space() >> 20:d} MB')
         return

 
-
-

-[docs]
-    def read_page_tables(self, entry: int):
-        raise Exception("Function needs to be implemented by child class")

-

-
+
[docs]    def read_page_tables(self, entry: int):
+        raise Exception("Function needs to be implemented by child class")

 
 
-

-[docs]
-class c_4level_page_tables(c_paging):
+
[docs]class c_4level_page_tables(c_paging):
 
     def __init__(self, cs):
         c_paging.__init__(self, cs)
@@ -399,21 +321,16 @@ 
Source code for chipsec.hal.paging
         self.PT_NAME = ['EPTP', 'PML4E', 'PDPTE', 'PDE', 'PTE']
         self.PT_SIZE = ['', '', '1GB', '2MB', '4KB']
 
-

-[docs]
-    def get_virt_addr(self, pml4e_index: int, pdpte_index: int = 0, pde_index: int = 0, pte_index: int = 0) -> int:
+
[docs]    def get_virt_addr(self, pml4e_index: int, pdpte_index: int = 0, pde_index: int = 0, pte_index: int = 0) -> int:
         ofs1 = self.set_field(pml4e_index, self.PML4_INDX)
         ofs2 = self.set_field(pdpte_index, self.PDPT_INDX)
         ofs3 = self.set_field(pde_index, self.PD_INDX)
         ofs4 = self.set_field(pte_index, self.PT_INDX)
         return (ofs1 | ofs2 | ofs3 | ofs4)

 
-
-

-[docs]
-    def print_entry(self, lvl: int, pa: int, va: int = 0, perm: str = '') -> None:
+
[docs]    def print_entry(self, lvl: int, pa: int, va: int = 0, perm: str = '') -> None:
         canonical_va = self.get_canonical(va)
-        info = f'  {"  " * lvl}{self.PT_NAME[lvl]:6}: {pa:013X}'
+        info = f'  {"  " * lvl}{self.PT_NAME[lvl]:6}: {pa:013X}'
         if perm != '':
             size = self.PT_SIZE[lvl]
             info += f' - {size} PAGE  {perm}'
@@ -428,10 +345,7 @@ 
Source code for chipsec.hal.paging
         logger().log(info)
         return

 
-
-

-[docs]
-    def read_page_tables(self, ptr: int) -> None:
+
[docs]    def read_page_tables(self, ptr: int) -> None:
         addr = ptr & ADDR_4KB
         self.pointer = addr
         self.pt = {addr: 'pml4'}
@@ -440,22 +354,13 @@ 
Source code for chipsec.hal.paging
         self.read_pml4(addr)
         return

 
-
-

-[docs]
-    def is_present(self, entry: int) -> int:
+
[docs]    def is_present(self, entry: int) -> int:
         return entry & chipsec.defines.BIT0

 
-
-

-[docs]
-    def is_bigpage(self, entry: int) -> int:
+
[docs]    def is_bigpage(self, entry: int) -> int:
         return entry & chipsec.defines.BIT7

 
-
-

-[docs]
-    def read_pml4(self, addr: int) -> None:
+
[docs]    def read_pml4(self, addr: int) -> None:
         pml4 = self.read_entries('pml4', addr)
         for pml4e_index in range(len(pml4)):
             pml4e = pml4[pml4e_index]
@@ -466,10 +371,7 @@ 
Source code for chipsec.hal.paging
                 self.read_pdpt(addr, pml4e_index)
         return

 
-
-

-[docs]
-    def get_attr(self, entry: int) -> str:
+
[docs]    def get_attr(self, entry: int) -> str:
         ret = ''
         if entry & chipsec.defines.BIT1:
             ret += 'W'
@@ -481,10 +383,7 @@ 
Source code for chipsec.hal.paging
             ret += 'S'
         return ret

 
-
-

-[docs]
-    def read_pdpt(self, addr: int, pml4e_index: int) -> None:
+
[docs]    def read_pdpt(self, addr: int, pml4e_index: int) -> None:
         pdpt = self.read_entries('pdpt', addr)
         for pdpte_index in range(len(pdpt)):
             pdpte = pdpt[pdpte_index]
@@ -500,10 +399,7 @@ 
Source code for chipsec.hal.paging
                     self.read_pd(addr, pml4e_index, pdpte_index)
         return

 
-
-

-[docs]
-    def read_pd(self, addr: int, pml4e_index: int, pdpte_index: int) -> None:
+
[docs]    def read_pd(self, addr: int, pml4e_index: int, pdpte_index: int) -> None:
         pd = self.read_entries('pd', addr)
         for pde_index in range(len(pd)):
             pde = pd[pde_index]
@@ -519,10 +415,7 @@ 
Source code for chipsec.hal.paging
                     self.read_pt(addr, pml4e_index, pdpte_index, pde_index)
         return

 
-
-

-[docs]
-    def read_pt(self, addr: int, pml4e_index: int, pdpte_index: int, pde_index: int) -> None:
+
[docs]    def read_pt(self, addr: int, pml4e_index: int, pdpte_index: int, pde_index: int) -> None:
         pt = self.read_entries('pt', addr)
         for pte_index in range(len(pt)):
             pte = pt[pte_index]
@@ -532,10 +425,7 @@ 
Source code for chipsec.hal.paging
                 self.print_entry(4, phys, virt, self.get_attr(pte))
         return

 
-
-

-[docs]
-    def read_entry_by_virt_addr(self, virt: int) -> Dict[str, Any]:
+
[docs]    def read_entry_by_virt_addr(self, virt: int) -> Dict[str, Any]:
         if self.pointer is None:
             raise Exception('Page Table pointer is undefined!')
         addr = self.pointer
@@ -564,14 +454,10 @@ 
Source code for chipsec.hal.paging
                             if self.is_present(pte):
                                 addr = (pte & ADDR_4KB) | (virt & ~ADDR_4KB)
                                 return {'addr': addr, 'attr': self.get_attr(pte), 'size': '4KB'}
-        return {'addr': 0, 'attr': '', 'size': ''}

-

-
+        return {'addr': 0, 'attr': '', 'size': ''}

 
 
-

-[docs]
-class c_ia32e_page_tables(c_4level_page_tables):
+
[docs]class c_ia32e_page_tables(c_4level_page_tables):
 
     def __init__(self, cs):
         c_4level_page_tables.__init__(self, cs)
@@ -583,31 +469,19 @@ 
Source code for chipsec.hal.paging
         self.US = {'mask': 0x1, 'offset': 2}
         self.BIGPAGE = {'mask': 0x1, 'offset': 7}
 
-

-[docs]
-    def is_present(self, entry: int) -> bool:
+
[docs]    def is_present(self, entry: int) -> bool:
         return self.get_field(entry, self.P) != 0

 
-
-

-[docs]
-    def is_bigpage(self, entry: int) -> bool:
+
[docs]    def is_bigpage(self, entry: int) -> bool:
         return self.get_field(entry, self.BIGPAGE) != 0

 
-
-

-[docs]
-    def get_attr(self, entry: int) -> str:
+
[docs]    def get_attr(self, entry: int) -> str:
         RW_DESC = ['R', 'W']
         US_DESC = ['S', 'U']
-        return f'{RW_DESC[self.get_field(entry, self.RW)]} {US_DESC[self.get_field(entry, self.US)]}'

-

-
+        return f'{RW_DESC[self.get_field(entry, self.RW)]} {US_DESC[self.get_field(entry, self.US)]}'

 
 
-

-[docs]
-class c_pae_page_tables(c_ia32e_page_tables):
+
[docs]class c_pae_page_tables(c_ia32e_page_tables):
 
     def __init__(self, cs):
         c_ia32e_page_tables.__init__(self, cs)
@@ -616,9 +490,7 @@ 
Source code for chipsec.hal.paging
         self.PDPT_INDX = {'mask': 0x003, 'offset': 30}
         self.PT_NAME = ['', 'CR3', 'PDPTE', 'PDE', 'PTE']
 
-

-[docs]
-    def read_page_tables(self, ptr: int) -> None:
+
[docs]    def read_page_tables(self, ptr: int) -> None:
         addr = ptr & ADDR_4KB
         self.pointer = addr
         self.pt = {addr: 'pdpt'}
@@ -627,16 +499,10 @@ 
Source code for chipsec.hal.paging
         self.read_pdpt(addr, None)
         return

 
-
-

-[docs]
-    def read_pml4(self, addr: int):
+
[docs]    def read_pml4(self, addr: int):
         raise Exception('PAE Page tables have no PML4!')

 
-
-

-[docs]
-    def read_pdpt(self, addr: int, pml4e_index: Optional[int] = None) -> None:
+
[docs]    def read_pdpt(self, addr: int, pml4e_index: Optional[int] = None) -> None:
         if not pml4e_index:
             raise Exception('PAE Page tables have no PML4!')
         pdpt = self.read_entries('pdpt', addr)
@@ -652,14 +518,10 @@ 
Source code for chipsec.hal.paging
                     self.pt[addr] = 'pd'
                     self.print_entry(2, addr)
                     self.read_pd(addr, 0, pdpte_index)
-        return

-

+        return

 
 
-
-

-[docs]
-class c_extended_page_tables(c_4level_page_tables):
+
[docs]class c_extended_page_tables(c_4level_page_tables):
 
     def __init__(self, cs):
         c_4level_page_tables.__init__(self, cs)
@@ -670,37 +532,23 @@ 
Source code for chipsec.hal.paging
         self.BIGPAGE = {'mask': 0x1, 'offset': 7}
         self.canonical_msb = 63
 
-

-[docs]
-    def is_present(self, entry: int) ->  bool:
+
[docs]    def is_present(self, entry: int) ->  bool:
         return self.get_field(entry, self.XWR) != 0

 
-
-

-[docs]
-    def is_bigpage(self, entry: int) -> bool:
+
[docs]    def is_bigpage(self, entry: int) -> bool:
         return self.get_field(entry, self.BIGPAGE) != 0

 
-
-

-[docs]
-    def get_attr(self, entry: int) -> str:
+
[docs]    def get_attr(self, entry: int) -> str:
         XWR_DESC = ['---', '--R', '-W-', '-WR', 'X--', 'X-R', 'XW-', 'XWR']
         MEM_DESC = ['UC', 'WC', '02', '03', 'WT', 'WP', 'WB', 'UC-']
-        return f'{XWR_DESC[self.get_field(entry, self.XWR)]} {MEM_DESC[self.get_field(entry, self.MEM_TYPE)]}'

-
+        return f'{XWR_DESC[self.get_field(entry, self.XWR)]} {MEM_DESC[self.get_field(entry, self.MEM_TYPE)]}'

 
-

-[docs]
-    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
+
[docs]    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
         super(c_extended_page_tables, self).read_pt_and_show_status(path, name, ptr)
         self.check_misconfig(list(self.pt))
         return

 
-
-

-[docs]
-    def map_bigpage_1G(self, virt: int, i: int) -> None:
+
[docs]    def map_bigpage_1G(self, virt: int, i: int) -> None:
         if self.pointer is None:
             raise Exception('Page Table pointer is undefined!')
         addr = self.pointer
@@ -711,14 +559,10 @@ 
Source code for chipsec.hal.paging
             pdpt = self.read_entries('pdpt', addr)
             new_entry = struct.pack('<Q', ((pdpt[i] | 0x87) & ~ADDR_4KB) | (i << 30))
             self.cs.mem.write_physical_mem(addr + i * 8, 8, new_entry)
-        return None

-

+        return None

 
 
-
-

-[docs]
-class c_vtd_page_tables(c_extended_page_tables):
+
[docs]class c_vtd_page_tables(c_extended_page_tables):
 
     def __init__(self, cs):
         c_extended_page_tables.__init__(self, cs)
@@ -738,9 +582,7 @@ 
Source code for chipsec.hal.paging
         self.domains = {}
         self.cpt = {}
 
-

-[docs]
-    def read_vtd_context(self, path: str, ptr: int) -> None:
+
[docs]    def read_vtd_context(self, path: str, ptr: int) -> None:
         txt = open(path, 'w')
         try:
             self.out = txt
@@ -767,10 +609,7 @@ 
Source code for chipsec.hal.paging
             txt.close()
         return

 
-
-

-[docs]
-    def read_re(self, addr: int) -> None:
+
[docs]    def read_re(self, addr: int) -> None:
         re = self.read_entries('re', addr, 16)
         for ree_index in range(len(re)):
             ree_lo = re[ree_index][0]
@@ -781,10 +620,7 @@ 
Source code for chipsec.hal.paging
                 self.cpt[addr] = 'context'
         return

 
-
-

-[docs]
-    def read_ce(self, addr: int, ree_index: int) -> None:
+
[docs]    def read_ce(self, addr: int, ree_index: int) -> None:
         ce = self.read_entries('ce', addr, 16)
         for cee_index in range(len(ce)):
             cee_lo = ce[cee_index][0]
@@ -797,10 +633,7 @@ 
Source code for chipsec.hal.paging
                     self.domains[slptptr] = 1
         return

 
-
-

-[docs]
-    def print_context_entry(self, source_id: int, cee: Dict[int, int]) -> None:
+
[docs]    def print_context_entry(self, source_id: int, cee: Dict[int, int]) -> None:
         if self.get_field(cee[0], self.CE_LO_P):
             info = (
                 self.get_field(source_id, self.DID_BUS),
@@ -816,23 +649,15 @@ 
Source code for chipsec.hal.paging
             logger().log('  {:02X}:{:02X}.{:X}  DID: {:02X}  AVAIL: {:X}  AW: {:X}  T: {:X}  FPD: {:X}  SLPTPTR: {:016X}'.format(*info))
         return

 
-
-

-[docs]
-    def read_page_tables(self, ptr: int) -> None:
+
[docs]    def read_page_tables(self, ptr: int) -> None:
         logger().log(f'  Page Tables for domain 0x{ptr:013X}: ')
         super(c_vtd_page_tables, self).read_page_tables(ptr)
         return

 
-
-

-[docs]
-    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
+
[docs]    def read_pt_and_show_status(self, path: str, name: str, ptr: int) -> None:
         super(c_vtd_page_tables, self).read_pt_and_show_status(path, name, ptr)
         self.check_misconfig(list(self.cpt))
-        return

-

-
+        return

 

 
             

@@ -892,7 +717,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -912,8 +737,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/pci.html b/_modules/chipsec/hal/pci.html
index f9065929..7822372f 100644
--- a/_modules/chipsec/hal/pci.html
+++ b/_modules/chipsec/hal/pci.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.pci — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -79,12 +81,11 @@ 
Source code for chipsec.hal.pci
 from collections import namedtuple
 import itertools
 from typing import List, Tuple, Optional
-from chipsec import defines
 from chipsec.logger import logger, pretty_print_hex_buffer
 from chipsec.file import write_file
 from chipsec.hal.pcidb import VENDORS, DEVICES
 from chipsec.exceptions import OsHelperError
-from chipsec.defines import is_all_ones
+from chipsec.defines import is_all_ones, MASK_16b, MASK_32b, MASK_64b, BOUNDARY_4KB
 
 #
 # PCI configuration header registers
@@ -162,9 +163,7 @@ 
Source code for chipsec.hal.pci
 PCI_XROM_HEADER_SIZE = struct.calcsize(PCI_XROM_HEADER_FMT)
 
 
-

-[docs]
-class PCI_XROM_HEADER(namedtuple('PCI_XROM_HEADER', 'Signature ArchSpecific PCIROffset')):
+
[docs]class PCI_XROM_HEADER(namedtuple('PCI_XROM_HEADER', 'Signature ArchSpecific PCIROffset')):
     __slots__ = ()
 
     def __str__(self) -> str:
@@ -172,11 +171,10 @@ 
Source code for chipsec.hal.pci
 PCI XROM
 -----------------------------------
 Signature       : 0x{self.Signature:04X} (= 0xAA55)
-ArchSpecific    : {self.ArchSpecific.encode('hex').upper()}
-PCIR Offset     : 0x{self.PCIROffset:04X}
+ArchSpecific    : {self.ArchSpecific.encode('hex').upper()}
+PCIR Offset     : 0x{self.PCIROffset:04X}
 """

 
-
 # @TBD: PCI Data Structure
 
 #
@@ -189,9 +187,7 @@ 
Source code for chipsec.hal.pci
 EFI_XROM_HEADER_SIZE = struct.calcsize(EFI_XROM_HEADER_FMT)
 
 
-

-[docs]
-class EFI_XROM_HEADER(namedtuple('EFI_XROM_HEADER', 'Signature InitSize EfiSignature EfiSubsystem EfiMachineType CompressType Reserved EfiImageHeaderOffset PCIROffset')):
+
[docs]class EFI_XROM_HEADER(namedtuple('EFI_XROM_HEADER', 'Signature InitSize EfiSignature EfiSubsystem EfiMachineType CompressType Reserved EfiImageHeaderOffset PCIROffset')):
     __slots__ = ()
 
     def __str__(self) -> str:
@@ -201,15 +197,14 @@ 
Source code for chipsec.hal.pci
 Signature           : 0x{self.Signature:04X} (= 0xAA55)
 Init Size           : 0x{self.InitSize:04X} (x 512 B)
 EFI Signature       : 0x{self.EfiSignature:08X} (= 0x0EF1)
-EFI Subsystem       : 0x{self.EfiSubsystem:04X}
-EFI Machine Type    : 0x{self.EfiMachineType:04X}
-Compression Type    : 0x{self.CompressType:04X}
-Reserved            : 0x{self.Reserved:02X}
-EFI Image Hdr Offset: 0x{self.EfiImageHeaderOffset:04X}
-PCIR Offset         : 0x{self.PCIROffset:04X}
+EFI Subsystem       : 0x{self.EfiSubsystem:04X}
+EFI Machine Type    : 0x{self.EfiMachineType:04X}
+Compression Type    : 0x{self.CompressType:04X}
+Reserved            : 0x{self.Reserved:02X}
+EFI Image Hdr Offset: 0x{self.EfiImageHeaderOffset:04X}
+PCIR Offset         : 0x{self.PCIROffset:04X}
 """

 
-
 #
 # Legacy PCI Expansion (Option) ROM
 #
@@ -219,27 +214,22 @@ 
Source code for chipsec.hal.pci
 XROM_HEADER_SIZE = struct.calcsize(XROM_HEADER_FMT)
 
 
-

-[docs]
-class XROM_HEADER(namedtuple('XROM_HEADER', 'Signature InitSize InitEP Reserved PCIROffset')):
+
[docs]class XROM_HEADER(namedtuple('XROM_HEADER', 'Signature InitSize InitEP Reserved PCIROffset')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
 XROM
 --------------------------------------
-Signature           : 0x{self.Signature:04X}
+Signature           : 0x{self.Signature:04X}
 Init Size           : 0x{self.InitSize:02X} (x 512 B)
-Init Entry-point    : 0x{self.InitEP:08X}
-Reserved            : {self.Reserved.encode('hex').upper()}
-PCIR Offset         : 0x{self.PCIROffset:04X}
+Init Entry-point    : 0x{self.InitEP:08X}
+Reserved            : {self.Reserved.encode('hex').upper()}
+PCIR Offset         : 0x{self.PCIROffset:04X}
 """

 
 
-
-

-[docs]
-class XROM:
+
[docs]class XROM:
     def __init__(self, bus, dev, fun, en, base, size):
         self.bus: int = bus
         self.dev: int = dev
@@ -252,29 +242,20 @@ 
Source code for chipsec.hal.pci
         self.header: Optional[PCI_XROM_HEADER] = None

 
 
-
-

-[docs]
-def get_vendor_name_by_vid(vid: int) -> str:
+
[docs]def get_vendor_name_by_vid(vid: int) -> str:
     if vid in VENDORS:
         return VENDORS[vid]
     return ''

 
 
-
-

-[docs]
-def get_device_name_by_didvid(vid: int, did: int) -> str:
+
[docs]def get_device_name_by_didvid(vid: int, did: int) -> str:
     if vid in DEVICES:
         if did in DEVICES[vid]:
             return DEVICES[vid][did]
     return ''

 
 
-
-
       

@@ -293,8 +250,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/smbios.html b/_modules/chipsec/hal/smbios.html
index f235c501..c8245d3f 100644
--- a/_modules/chipsec/hal/smbios.html
+++ b/_modules/chipsec/hal/smbios.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.smbios — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -81,32 +83,29 @@ 
Source code for chipsec.hal.smbios
 SMBIOS_2_x_ENTRY_POINT_SIZE = struct.calcsize(SMBIOS_2_x_ENTRY_POINT_FMT)
 
 
-

-[docs]
-class SMBIOS_2_x_ENTRY_POINT(namedtuple('SMBIOS_2_x_ENTRY_POINT', 'Anchor EntryCs EntryLen MajorVer MinorVer MaxSize EntryRev \
+
[docs]class SMBIOS_2_x_ENTRY_POINT(namedtuple('SMBIOS_2_x_ENTRY_POINT', 'Anchor EntryCs EntryLen MajorVer MinorVer MaxSize EntryRev \
         FormatArea0 FormatArea1 FormatArea2 FormatArea3 FormatArea4 IntAnchor IntCs TableLen TableAddr NumStructures BcdRev')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
 SMBIOS 2.x Entry Point Structure:
-  Anchor String             : {bytestostring(self.Anchor)}
-  Checksum                  : 0x{self.EntryCs:02X}
-  Entry Point Length        : 0x{self.EntryLen:02X}
-  Entry Point Version       : {self.MajorVer:d}.{self.MinorVer:d}
-  Max Structure Size        : 0x{self.MaxSize:04X}
-  Entry Point Revision      : 0x{self.EntryRev:02X}
-  Formatted Area            : 0x{self.FormatArea0:02X}, 0x{self.FormatArea1:02X}, 0x{self.FormatArea2:02X}, 0x{self.FormatArea3:02X}, 0x{self.FormatArea4:02X}
-  Intermediate Anchor String: {bytestostring(self.IntAnchor)}
-  Intermediate Checksum     : 0x{self.IntCs:02X}
-  Structure Table Length    : 0x{self.TableLen:04X}
-  Structure Table Address   : 0x{self.TableAddr:08X}
-  SMBIOS Structure Count    : 0x{self.NumStructures:04X}
-  SMBIOS BCD Revision       : 0x{self.BcdRev:02X}
+  Anchor String             : {bytestostring(self.Anchor)}
+  Checksum                  : 0x{self.EntryCs:02X}
+  Entry Point Length        : 0x{self.EntryLen:02X}
+  Entry Point Version       : {self.MajorVer:d}.{self.MinorVer:d}
+  Max Structure Size        : 0x{self.MaxSize:04X}
+  Entry Point Revision      : 0x{self.EntryRev:02X}
+  Formatted Area            : 0x{self.FormatArea0:02X}, 0x{self.FormatArea1:02X}, 0x{self.FormatArea2:02X}, 0x{self.FormatArea3:02X}, 0x{self.FormatArea4:02X}
+  Intermediate Anchor String: {bytestostring(self.IntAnchor)}
+  Intermediate Checksum     : 0x{self.IntCs:02X}
+  Structure Table Length    : 0x{self.TableLen:04X}
+  Structure Table Address   : 0x{self.TableAddr:08X}
+  SMBIOS Structure Count    : 0x{self.NumStructures:04X}
+  SMBIOS BCD Revision       : 0x{self.BcdRev:02X}
 """

 
 
-
 SMBIOS_3_x_SIG = b"_SM3_"
 SMBIOS_3_x_ENTRY_SIZE = 0x18
 SMBIOS_3_x_MAJOR_VER = 0x03
@@ -115,47 +114,41 @@ 
Source code for chipsec.hal.smbios
 SMBIOS_3_x_ENTRY_POINT_SIZE = struct.calcsize(SMBIOS_3_x_ENTRY_POINT_FMT)
 
 
-

-[docs]
-class SMBIOS_3_x_ENTRY_POINT(namedtuple('SMBIOS_3_x_ENTRY_POINT', 'Anchor EntryCs EntryLen MajorVer MinorVer Docrev EntryRev \
+
[docs]class SMBIOS_3_x_ENTRY_POINT(namedtuple('SMBIOS_3_x_ENTRY_POINT', 'Anchor EntryCs EntryLen MajorVer MinorVer Docrev EntryRev \
         Reserved MaxSize TableAddr')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
 SMBIOS 3.x Entry Point Structure:
-  Anchor String             : {bytestostring(self.Anchor)}
-  Checksum                  : 0x{self.EntryCs:02X}
-  Entry Point Length        : 0x{self.EntryLen:02X}
-  Entry Ponnt Version       : {self.MajorVer:d}.{self.MinorVer:d}
-  SMBIOS Docrev             : 0x{self.Docrev:02X}
-  Entry Point Revision      : 0x{self.EntryRev:02X}
-  Reserved                  : 0x{self.Reserved:02X}
-  Max Structure Size        : 0x{self.MaxSize:08X}
-  Structure Table Address   : 0x{self.TableAddr:016X}
+  Anchor String             : {bytestostring(self.Anchor)}
+  Checksum                  : 0x{self.EntryCs:02X}
+  Entry Point Length        : 0x{self.EntryLen:02X}
+  Entry Ponnt Version       : {self.MajorVer:d}.{self.MinorVer:d}
+  SMBIOS Docrev             : 0x{self.Docrev:02X}
+  Entry Point Revision      : 0x{self.EntryRev:02X}
+  Reserved                  : 0x{self.Reserved:02X}
+  Max Structure Size        : 0x{self.MaxSize:08X}
+  Structure Table Address   : 0x{self.TableAddr:016X}
 """

 
 
-
 SMBIOS_STRUCT_HEADER_FMT = "=BBH"
 SMBIOS_STRUCT_HEADER_SIZE = struct.calcsize(SMBIOS_STRUCT_HEADER_FMT)
 
 
-

-[docs]
-class SMBIOS_STRUCT_HEADER(namedtuple('SMBIOS_STRUCT_HEADER', 'Type Length Handle')):
+
[docs]class SMBIOS_STRUCT_HEADER(namedtuple('SMBIOS_STRUCT_HEADER', 'Type Length Handle')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""
 SMBIOS Struct Header:
   Type                      : 0x{self.Type:02X} ({self.Type:d})
-  Length                    : 0x{self.Length:02X}
-  Handle                    : 0x{self.Handle:04X}
+  Length                    : 0x{self.Length:02X}
+  Handle                    : 0x{self.Handle:04X}
 """

 
 
-
 SMBIOS_STRUCT_TERM_FMT = "=H"
 SMBIOS_STRUCT_TERM_SIZE = struct.calcsize(SMBIOS_STRUCT_TERM_FMT)
 SMBIOS_STRUCT_TERM_VAL = 0x0000
@@ -169,9 +162,7 @@ 
Source code for chipsec.hal.smbios
 """
 
 
-

-[docs]
-class SMBIOS_BIOS_INFO_2_0(namedtuple('SMBIOS_BIOS_INFO_2_0_ENTRY', 'type length handle vendor_str version_str segment \
+
[docs]class SMBIOS_BIOS_INFO_2_0(namedtuple('SMBIOS_BIOS_INFO_2_0_ENTRY', 'type length handle vendor_str version_str segment \
         release_str rom_sz bios_char strings')):
     __slots__ = ()
 
@@ -189,18 +180,17 @@ 
Source code for chipsec.hal.smbios
         return f"""
 SMBIOS BIOS Information:
   Type                      : 0x{self.type:02X} ({self.type:d})
-  Length                    : 0x{self.length:02X}
-  Handle                    : 0x{self.handle:04X}
-  Vendor                    : {ven_str:s}
-  BIOS Version              : {ver_str:s}
-  BIOS Starting Segment     : 0x{self.segment:04X}
-  BIOS Release Date         : {rel_str:s}
-  BIOS ROM Size             : 0x{self.rom_sz:02X}
-  BIOS Characteristics      : 0x{self.bios_char:016X}
+  Length                    : 0x{self.length:02X}
+  Handle                    : 0x{self.handle:04X}
+  Vendor                    : {ven_str:s}
+  BIOS Version              : {ver_str:s}
+  BIOS Starting Segment     : 0x{self.segment:04X}
+  BIOS Release Date         : {rel_str:s}
+  BIOS ROM Size             : 0x{self.rom_sz:02X}
+  BIOS Characteristics      : 0x{self.bios_char:016X}
 """

 
 
-
 SMBIOS_SYSTEM_INFO_ENTRY_ID = 1
 SMBIOS_SYSTEM_INFO_2_0_ENTRY_FMT = '=BBHBBBB'
 SMBIOS_SYSTEM_INFO_2_0_ENTRY_SIZE = struct.calcsize(SMBIOS_SYSTEM_INFO_2_0_ENTRY_FMT)
@@ -209,9 +199,7 @@ 
Source code for chipsec.hal.smbios
 """
 
 
-

-[docs]
-class SMBIOS_SYSTEM_INFO_2_0(namedtuple('SMBIOS_SYSTEM_INFO_2_0_ENTRY', 'type length handle manufacturer_str product_str \
+
[docs]class SMBIOS_SYSTEM_INFO_2_0(namedtuple('SMBIOS_SYSTEM_INFO_2_0_ENTRY', 'type length handle manufacturer_str product_str \
         version_str serial_str strings')):
     __slots__ = ()
 
@@ -232,16 +220,15 @@ 
Source code for chipsec.hal.smbios
         return f"""
 SMBIOS System Information:
   Type                      : 0x{self.type:02X} ({self.type:d})
-  Length                    : 0x{self.length:02X}
-  Handle                    : 0x{self.handle:04X}
-  Manufacturer              : {man_str:s}
-  Product Name              : {pro_str:s}
-  Version                   : {ver_str:s}
-  Serial Number             : {ser_str:s}
+  Length                    : 0x{self.length:02X}
+  Handle                    : 0x{self.handle:04X}
+  Manufacturer              : {man_str:s}
+  Product Name              : {pro_str:s}
+  Version                   : {ver_str:s}
+  Serial Number             : {ser_str:s}
 """

 
 
-
 SmbiosInfo = Union[SMBIOS_BIOS_INFO_2_0, SMBIOS_SYSTEM_INFO_2_0]
 StructDecode = Dict[str, Any]  # TODO: Replace Any when TypeDict (PEP 589) supported
 
@@ -251,9 +238,7 @@ 
Source code for chipsec.hal.smbios
 }
 
 
-

-[docs]
-class SMBIOS(hal_base.HALBase):
+
[docs]class SMBIOS(hal_base.HALBase):
     def __init__(self, cs):
         super(SMBIOS, self).__init__(cs)
         self.uefi = uefi.UEFI(cs)
@@ -267,7 +252,7 @@ 
Source code for chipsec.hal.smbios
         self.smbios_3_data = None
 
     def __get_raw_struct(self, table: bytes, start_offset: int) -> Tuple[Optional[bytes], Optional[int]]:
-        """
+        """
         Returns a tuple including the raw data and the offset to the next entry.  This allows the function
         to be called multiple times to process all the entries in a table.
 
@@ -317,7 +302,7 @@ 
Source code for chipsec.hal.smbios
             return (None, None)
         tmp_offset += SMBIOS_STRUCT_TERM_SIZE
 
-        logger().log_hal(f'Structure Size: 0x{tmp_offset - start_offset:04X}')
+        logger().log_hal(f'Structure Size: 0x{tmp_offset - start_offset:04X}')
         return (table[start_offset:tmp_offset], tmp_offset)
 
     def __validate_ep_2_values(self, pa: int) -> Optional[SMBIOS_2_x_ENTRY_POINT]:
@@ -365,9 +350,7 @@ 
Source code for chipsec.hal.smbios
             return None
         return ep_data
 
-

-[docs]
-    def find_smbios_table(self) -> bool:
+
[docs]    def find_smbios_table(self) -> bool:
         # Handle the case were we already found the tables
         if self.smbios_2_ep is not None or self.smbios_3_ep is not None:
             return True
@@ -442,11 +425,8 @@ 
Source code for chipsec.hal.smbios
 
         return True

 
-
-

-[docs]
-    def get_raw_structs(self, struct_type: Optional[int], force_32bit: bool):
-        """
+
[docs]    def get_raw_structs(self, struct_type: Optional[int], force_32bit: bool):
+        """
         Returns a list of raw data blobs for each SMBIOS structure.  The default is to process the 64bit
         entries if available unless specifically specified.
 
@@ -478,10 +458,7 @@ 
Source code for chipsec.hal.smbios
 
         return ret_val

 
-
-

-[docs]
-    def get_header(self, raw_data: bytes) -> Optional[SMBIOS_STRUCT_HEADER]:
+
[docs]    def get_header(self, raw_data: bytes) -> Optional[SMBIOS_STRUCT_HEADER]:
         logger().log_hal('Getting generic SMBIOS header information')
         if raw_data is None:
             logger().log_hal('- Raw data pointer is None')
@@ -498,10 +475,7 @@ 
Source code for chipsec.hal.smbios
 
         return header

 
-
-

-[docs]
-    def get_string_list(self, raw_data: bytes) -> Optional[List[str]]:
+
[docs]    def get_string_list(self, raw_data: bytes) -> Optional[List[str]]:
         ret_val = []
 
         logger().log_hal('Getting strings from structure')
@@ -534,10 +508,7 @@ 
Source code for chipsec.hal.smbios
         logger().log_hal(f'+ Found {len(ret_val):d} strings')
         return ret_val

 
-
-

-[docs]
-    def get_decoded_structs(self, struct_type: Optional[int] = None, force_32bit: bool = False) -> Optional[List[Type[SmbiosInfo]]]:
+
[docs]    def get_decoded_structs(self, struct_type: Optional[int] = None, force_32bit: bool = False) -> Optional[List[Type[SmbiosInfo]]]:
         ret_val = []
 
         # Determine if the structure exists in the table
@@ -579,9 +550,7 @@ 
Source code for chipsec.hal.smbios
                 continue
             ret_val.append(decode_object)
 
-        return ret_val

-

-
+        return ret_val

 

 
             

@@ -641,7 +610,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -661,8 +630,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/smbus.html b/_modules/chipsec/hal/smbus.html
index 6578975c..211d7353 100644
--- a/_modules/chipsec/hal/smbus.html
+++ b/_modules/chipsec/hal/smbus.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.smbus — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -86,9 +88,7 @@ 
Source code for chipsec.hal.smbus
 SMBUS_COMMAND_READ = 1
 
 
-

-[docs]
-class SMBus(hal_base.HALBase):
+
[docs]class SMBus(hal_base.HALBase):
 
     def __init__(self, cs):
         super(SMBus, self).__init__(cs)
@@ -100,19 +100,14 @@ 
Source code for chipsec.hal.smbus
         self.smb_reg_data0 = 'SMBUS_HST_D0'
         self.smb_reg_data1 = 'SMBUS_HST_D1'
 
-

-[docs]
-    def get_SMBus_Base_Address(self) -> int:
+
[docs]    def get_SMBus_Base_Address(self) -> int:
         if self.iobar.is_IO_BAR_defined('SMBUS_BASE'):
             (sba_base, _) = self.iobar.get_IO_BAR_base_address('SMBUS_BASE')
             return sba_base
         else:
             raise IOBARNotFoundError('IOBARAccessError: SMBUS_BASE')

 
-
-

-[docs]
-    def get_SMBus_HCFG(self) -> int:
+
[docs]    def get_SMBus_HCFG(self) -> int:
         if self.cs.is_register_defined('SMBUS_HCFG'):
             reg_value = self.cs.read_register('SMBUS_HCFG')
             if self.logger.HAL:
@@ -121,23 +116,14 @@ 
Source code for chipsec.hal.smbus
         else:
             raise RegisterNotFoundError('RegisterNotFound: SMBUS_HCFG')

 
-
-

-[docs]
-    def display_SMBus_info(self) -> None:
+
[docs]    def display_SMBus_info(self) -> None:
         self.logger.log_hal(f'[smbus] SMBus Base Address: 0x{self.get_SMBus_Base_Address():04X}')
         self.get_SMBus_HCFG()

 
-
-

-[docs]
-    def is_SMBus_enabled(self) -> bool:
+
[docs]    def is_SMBus_enabled(self) -> bool:
         return self.cs.is_device_enabled('SMBUS')

 
-
-

-[docs]
-    def is_SMBus_supported(self) -> bool:
+
[docs]    def is_SMBus_supported(self) -> bool:
         (did, vid) = self.cs.get_DeviceVendorID('SMBUS')
         self.logger.log_hal(f'[smbus] SMBus Controller (DID,VID) = (0x{did:04X},0x{vid:04X})')
         if (0x8086 == vid):
@@ -146,17 +132,11 @@ 
Source code for chipsec.hal.smbus
             self.logger.log_error(f'Unknown SMBus Controller (DID,VID) = (0x{did:04X},0x{vid:04X})')
             return False

 
-
-

-[docs]
-    def is_SMBus_host_controller_enabled(self) -> int:
+
[docs]    def is_SMBus_host_controller_enabled(self) -> int:
         hcfg = self.get_SMBus_HCFG()
         return self.cs.get_register_field("SMBUS_HCFG", hcfg, "HST_EN")

 
-
-

-[docs]
-    def enable_SMBus_host_controller(self) -> None:
+
[docs]    def enable_SMBus_host_controller(self) -> None:
         # Enable SMBus Host Controller Interface in HCFG
         reg_value = self.cs.read_register('SMBUS_HCFG')
         if 0 == (reg_value & 0x1):
@@ -168,10 +148,7 @@ 
Source code for chipsec.hal.smbus
         if 0 == (cmd & 0x1):
             self.cs.write_register('SMBUS_CMD', (cmd | 0x1))

 
-
-

-[docs]
-    def reset_SMBus_controller(self) -> bool:
+
[docs]    def reset_SMBus_controller(self) -> bool:
         reg_value = self.cs.read_register('SMBUS_HCFG')
         self.cs.write_register('SMBUS_HCFG', reg_value | 0x08)
         for i in range(SMBUS_POLL_COUNT):
@@ -179,7 +156,6 @@ 
Source code for chipsec.hal.smbus
                 return True
         return False

 
-
     #
     # SMBus commands
     #
@@ -228,9 +204,7 @@ 
Source code for chipsec.hal.smbus
                         return False
         return 0 == busy
 
-

-[docs]
-    def read_byte(self, target_address: int, offset: int) -> int:
+
[docs]    def read_byte(self, target_address: int, offset: int) -> int:
         # clear status bits
         self.cs.write_register(self.smb_reg_status, 0xFF)
 
@@ -260,10 +234,7 @@ 
Source code for chipsec.hal.smbus
         self.logger.log_hal(f'[smbus] read device {target_address:X} off {offset:X} = {value:X}')
         return value

 
-
-

-[docs]
-    def write_byte(self, target_address: int, offset: int, value: int) -> bool:
+
[docs]    def write_byte(self, target_address: int, offset: int, value: int) -> bool:
         # clear status bits
         self.cs.write_register(self.smb_reg_status, 0xFF)
 
@@ -293,24 +264,16 @@ 
Source code for chipsec.hal.smbus
         self.logger.log_hal(f'[smbus] write to device {target_address:X} off {offset:X} = {value:X}')
         return True

 
-
-

-[docs]
-    def read_range(self, target_address: int, start_offset: int, size: int) -> bytes:
+
[docs]    def read_range(self, target_address: int, start_offset: int, size: int) -> bytes:
         buffer = bytes(self.read_byte(target_address, start_offset + i) for i in range(size))
         self.logger.log_hal(f'[smbus] reading {size:d} bytes from device 0x{target_address:X} at offset {start_offset:X}')
         return buffer

 
-
-

-[docs]
-    def write_range(self, target_address: int, start_offset: int, buffer: bytes) -> bool:
+
[docs]    def write_range(self, target_address: int, start_offset: int, buffer: bytes) -> bool:
         for i, b in enumerate(buffer):
             self.write_byte(target_address, start_offset + i, b)
         self.logger.log_hal(f'[smbus] writing {size:d} bytes to device 0x{target_address:X} at offset {start_offset:X}')
-        return True

-

-
+        return True

 

 
             

@@ -370,7 +333,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -390,8 +353,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/spd.html b/_modules/chipsec/hal/spd.html
index 4bcbc7cc..1ef5ee3d 100644
--- a/_modules/chipsec/hal/spd.html
+++ b/_modules/chipsec/hal/spd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.spd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -227,110 +229,90 @@ 
Source code for chipsec.hal.spd
 SPD_REVISION_1_3 = 0x13
 
 
-

-[docs]
-def SPD_REVISION(revision: int) -> str:
-    return (f'{revision >> 4:d}.{revision & 0xF:d}')

-
+
[docs]def SPD_REVISION(revision: int) -> str:
+    return (f'{revision >> 4:d}.{revision & 0xF:d}')

 
 
-

-[docs]
-def dram_device_type_name(dram_type: int) -> str:
+
[docs]def dram_device_type_name(dram_type: int) -> str:
     dt_name = DRAM_DEVICE_TYPE[dram_type] if dram_type in DRAM_DEVICE_TYPE else 'unknown'
     return dt_name

 
 
-
-

-[docs]
-def module_type_name(module_type: int) -> str:
+
[docs]def module_type_name(module_type: int) -> str:
     mt_name = MODULE_TYPE[module_type] if module_type in MODULE_TYPE else 'unknown'
     return mt_name

 
 
-
 SPD_DDR_FORMAT = '=4B'
 
 
-

-[docs]
-class SPD_DDR(namedtuple('SPD_DDR', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
+
[docs]class SPD_DDR(namedtuple('SPD_DDR', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""------------------------------------------------------------------
 SPD DDR
 ------------------------------------------------------------------
-[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
-[1] Total number of bytes      : 0x{self.TotalBytes:02X}
+[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
+[1] Total number of bytes      : 0x{self.TotalBytes:02X}
 [2] DRAM Memory Type           : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
-[3] Number of Row Addresses    : 0x{self.RowAddressCount:02X}
+[3] Number of Row Addresses    : 0x{self.RowAddressCount:02X}
 ------------------------------------------------------------------
 """

 
 
-
 SPD_DDR2_FORMAT = '=4B'
 
 
-

-[docs]
-class SPD_DDR2(namedtuple('SPD_DDR2', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
+
[docs]class SPD_DDR2(namedtuple('SPD_DDR2', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""------------------------------------------------------------------
 SPD DDR2
 ------------------------------------------------------------------
-[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
-[1] Total number of bytes      : 0x{self.TotalBytes:02X}
+[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
+[1] Total number of bytes      : 0x{self.TotalBytes:02X}
 [2] DRAM Memory Type           : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
-[3] Number of Row Addresses    : 0x{self.RowAddressCount:02X}
+[3] Number of Row Addresses    : 0x{self.RowAddressCount:02X}
 ------------------------------------------------------------------
 """

 
 
-
 SPD_DDR3_FORMAT = '=16B'
 
 
-

-[docs]
-class SPD_DDR3(namedtuple('SPD_DDR3', 'SPDBytes Revision DeviceType ModuleType ChipSize Addressing Voltages ModuleOrg BusWidthECC FTB MTBDivident MTBDivisor tCKMin RsvdD CASLo CASHi')):
+
[docs]class SPD_DDR3(namedtuple('SPD_DDR3', 'SPDBytes Revision DeviceType ModuleType ChipSize Addressing Voltages ModuleOrg BusWidthECC FTB MTBDivident MTBDivisor tCKMin RsvdD CASLo CASHi')):
     __slots__ = ()
 
     def __str__(self) -> str:
         return f"""------------------------------------------------------------------
 SPD DDR3
 ------------------------------------------------------------------
-[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
+[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
 [0x01] SPD Revision                       : 0x{self.Revision:02X} ({SPD_REVISION(self.Revision)})
 [0x02] DRAM Memory Type                   : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
 [0x03] Module Type                        : 0x{self.ModuleType:02X} ({module_type_name(self.ModuleType)})
-[0x04] SDRAM Density and Banks            : 0x{self.ChipSize:02X}
-[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
-[0x06] Module Nominal Voltage, VDD        : 0x{self.Voltages:02X}
-[0x07] Module Organization                : 0x{self.ModuleOrg:02X}
-[0x08] Module Memory Bus Width, ECC       : 0x{self.BusWidthECC:02X}
-[0x09] FTB Divident/Divisor               : 0x{self.FTB:02X}
-[0x0A] MTB Divident                       : 0x{self.MTBDivident:02X}
-[0x0B] MTB Divisor                        : 0x{self.MTBDivisor:02X}
-[0x0C] SDRAM Minimum Cycle Time (tCKmin)  : 0x{self.tCKMin:02X}
-[0x0D] Reserved                           : 0x{self.RsvdD:02X}
-[0x0E] CAS Latencies Supported (LSB)      : 0x{self.CASLo:02X}
-[0x0F] CAS Latencies Supported (MSB)      : 0x{self.CASHi:02X}
+[0x04] SDRAM Density and Banks            : 0x{self.ChipSize:02X}
+[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
+[0x06] Module Nominal Voltage, VDD        : 0x{self.Voltages:02X}
+[0x07] Module Organization                : 0x{self.ModuleOrg:02X}
+[0x08] Module Memory Bus Width, ECC       : 0x{self.BusWidthECC:02X}
+[0x09] FTB Divident/Divisor               : 0x{self.FTB:02X}
+[0x0A] MTB Divident                       : 0x{self.MTBDivident:02X}
+[0x0B] MTB Divisor                        : 0x{self.MTBDivisor:02X}
+[0x0C] SDRAM Minimum Cycle Time (tCKmin)  : 0x{self.tCKMin:02X}
+[0x0D] Reserved                           : 0x{self.RsvdD:02X}
+[0x0E] CAS Latencies Supported (LSB)      : 0x{self.CASLo:02X}
+[0x0F] CAS Latencies Supported (MSB)      : 0x{self.CASHi:02X}
 ------------------------------------------------------------------
 """

 
 
-
 SPD_DDR4_FORMAT = '=16B'
 
 
-

-[docs]
-class SPD_DDR4(namedtuple('SPD_DDR4', 'SPDBytes Revision DeviceType ModuleType Density Addressing PackageType OptFeatures ThermalRefresh OptFeatures1 ReservedA VDD ModuleOrg BusWidthECC ThermSensor ModuleTypeExt')):
+
[docs]class SPD_DDR4(namedtuple('SPD_DDR4', 'SPDBytes Revision DeviceType ModuleType Density Addressing PackageType OptFeatures ThermalRefresh OptFeatures1 ReservedA VDD ModuleOrg BusWidthECC ThermSensor ModuleTypeExt')):
     __slots__ = ()
 
     def __str__(self) -> str:
@@ -338,93 +320,67 @@ 
Source code for chipsec.hal.spd
 SPD DDR4
 ------------------------------------------------------------------
 Base Configuration and DRAM Parameters
-[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
+[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
 [0x01] SPD Revision                       : 0x{self.Revision:02X} ({SPD_REVISION(self.Revision)})
 [0x02] DRAM Memory Type                   : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
 [0x03] Module Type                        : 0x{self.ModuleType:02X} ({module_type_name(self.ModuleType)})
-[0x04] SDRAM Density and Banks            : 0x{self.Density:02X}
-[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
-[0x06] SDRAM Package Type                 : 0x{self.PackageType:02X}
-[0x07] SDRAM Optional Features            : 0x{self.OptFeatures:02X}
-[0x08] SDRAM Thermal and Refresh Options  : 0x{self.ThermalRefresh:02X}
-[0x09] Other Optional Features            : 0x{self.OptFeatures1:02X}
-[0x0A] Reserved (== 0x00)                 : 0x{self.ReservedA:02X}
-[0x0B] Module Nominal Voltage, VDD        : 0x{self.VDD:02X}
-[0x0C] Module Organization                : 0x{self.ModuleOrg:02X}
-[0x0D] Module Memory Bus Width            : 0x{self.BusWidthECC:02X}
-[0x0E] Module Thermal Sensor              : 0x{self.ThermSensor:02X}
-[0x0F] Extended Module Type               : 0x{self.ModuleTypeExt:02X}
+[0x04] SDRAM Density and Banks            : 0x{self.Density:02X}
+[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
+[0x06] SDRAM Package Type                 : 0x{self.PackageType:02X}
+[0x07] SDRAM Optional Features            : 0x{self.OptFeatures:02X}
+[0x08] SDRAM Thermal and Refresh Options  : 0x{self.ThermalRefresh:02X}
+[0x09] Other Optional Features            : 0x{self.OptFeatures1:02X}
+[0x0A] Reserved (== 0x00)                 : 0x{self.ReservedA:02X}
+[0x0B] Module Nominal Voltage, VDD        : 0x{self.VDD:02X}
+[0x0C] Module Organization                : 0x{self.ModuleOrg:02X}
+[0x0D] Module Memory Bus Width            : 0x{self.BusWidthECC:02X}
+[0x0E] Module Thermal Sensor              : 0x{self.ThermSensor:02X}
+[0x0F] Extended Module Type               : 0x{self.ModuleTypeExt:02X}
 ------------------------------------------------------------------
 """

 
 
-
 ###############################################################################
 #
 # Main SPD HAL component class
 #
 ###############################################################################
 
-

-[docs]
-class SPD:
+
[docs]class SPD:
     def __init__(self, smbus):
         self.smbus = smbus
 
-

-[docs]
-    def read_byte(self, offset: int, device: int = SPD_SMBUS_ADDRESS) -> int:
+
[docs]    def read_byte(self, offset: int, device: int = SPD_SMBUS_ADDRESS) -> int:
         return self.smbus.read_byte(device, offset)

 
-
-

-[docs]
-    def write_byte(self, offset: int, value: int, device: int = SPD_SMBUS_ADDRESS) -> bool:
+
[docs]    def write_byte(self, offset: int, value: int, device: int = SPD_SMBUS_ADDRESS) -> bool:
         return self.smbus.write_byte(device, offset, value)

 
-
-

-[docs]
-    def read_range(self, start_offset: int, size: int, device: int = SPD_SMBUS_ADDRESS) -> bytes:
+
[docs]    def read_range(self, start_offset: int, size: int, device: int = SPD_SMBUS_ADDRESS) -> bytes:
         return bytes(self.read_byte(start_offset + i, device) for i in range(size))

 
-
-

-[docs]
-    def write_range(self, start_offset: int, buffer: bytes, device: int = SPD_SMBUS_ADDRESS) -> bool:
+
[docs]    def write_range(self, start_offset: int, buffer: bytes, device: int = SPD_SMBUS_ADDRESS) -> bool:
         for i, b in enumerate(buffer):
             self.write_byte(start_offset + i, b, device)
         return True

 
-
-

-[docs]
-    def dump_spd_rom(self, device: int = SPD_SMBUS_ADDRESS) -> bytes:
+
[docs]    def dump_spd_rom(self, device: int = SPD_SMBUS_ADDRESS) -> bytes:
         return self.read_range(0x0, 0x100, device)

 
-
     #
     # Decoding certain bytes of DIMM SPD: may be dependent on the DRAM type
     #
-

-[docs]
-    def getDRAMDeviceType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
+
[docs]    def getDRAMDeviceType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
         dram_type = self.read_byte(SPD_OFFSET_DRAM_DEVICE_TYPE, device)
         logger().log_hal(f'[spd][0x{device:02X}] DRAM Device Type (byte 2): 0x{dram_type:01X}')
         return dram_type

 
-
-

-[docs]
-    def getModuleType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
+
[docs]    def getModuleType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
         module_type = self.read_byte(SPD_OFFSET_DDR3_MODULE_TYPE, device)
         logger().log_hal(f'[spd][0x{device:02X}] Module Type (byte 3): 0x{module_type:01X}')
         return module_type

 
-
-

-[docs]
-    def isECC(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
+
[docs]    def isECC(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
         device_type = self.getDRAMDeviceType(device)
         ecc_supported = False
         ecc_off = 0
@@ -452,10 +408,7 @@ 
Source code for chipsec.hal.spd
                 logger().log(f'[spd][0x{device:02X}] ECC is {not_str}supported by the DIMM (byte {ecc_off:d} = 0x{ecc:02X})')
         return ecc_supported

 
-
-

-[docs]
-    def detect(self) -> List[int]:
+
[docs]    def detect(self) -> List[int]:
         _dimms = []
         for d in SPD_DIMMS:
             if self.isSPDPresent(d):
@@ -466,20 +419,14 @@ 
Source code for chipsec.hal.spd
                 logger().log(f"{SPD_DIMMS[_dimm]}: 0x{_dimm:02X}")
         return _dimms

 
-
-

-[docs]
-    def isSPDPresent(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
+
[docs]    def isSPDPresent(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
         device_type = self.getDRAMDeviceType(device)
         is_spd_present = (device_type != 0xFF)
         not_str = '' if is_spd_present else 'not '
         logger().log_hal(f'[spd][0x{device:02X}] Detecting SPD.. {not_str}found (DRAM memory type = 0x{device_type:X})')
         return is_spd_present

 
-
-

-[docs]
-    def decode(self, device: int = SPD_SMBUS_ADDRESS) -> None:
+
[docs]    def decode(self, device: int = SPD_SMBUS_ADDRESS) -> None:
         spd: Any = None
         device_type = self.getDRAMDeviceType(device)
         spd_buffer = self.dump_spd_rom(device)
@@ -498,9 +445,7 @@ 
Source code for chipsec.hal.spd
             logger().log_warning('[spd] Unsupported SPD format')
 
         if spd is not None:
-            logger().log(str(spd))

-

-
+            logger().log(str(spd))

 

 
             

@@ -560,7 +505,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -580,8 +525,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/spi.html b/_modules/chipsec/hal/spi.html
index b53d7dab..0230a614 100644
--- a/_modules/chipsec/hal/spi.html
+++ b/_modules/chipsec/hal/spi.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.spi — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -219,19 +221,14 @@ 
Source code for chipsec.hal.spi
 # @TODO: DEPRECATED
 
 
-

-[docs]
-def get_SPI_region(flreg: int) -> Tuple[int, int]:
+
[docs]def get_SPI_region(flreg: int) -> Tuple[int, int]:
     range_base = (flreg & PCH_RCBA_SPI_FREGx_BASE_MASK) << SPI_FLA_SHIFT
     range_limit = ((flreg & PCH_RCBA_SPI_FREGx_LIMIT_MASK) >> 4)
     range_limit |= SPI_FLA_PAGE_MASK
     return (range_base, range_limit)

 
 
-
-

-[docs]
-class SPI(hal_base.HALBase):
+
[docs]class SPI(hal_base.HALBase):
 
     def __init__(self, cs):
         super(SPI, self).__init__(cs)
@@ -274,9 +271,7 @@ 
Source code for chipsec.hal.spi
         self.logger.log_hal(f'      FADDR  offset = 0x{self.faddr_off:04X}')
         self.logger.log_hal(f'      FDATA0 offset = 0x{self.fdata0_off:04X}')
 
-

-[docs]
-    def get_SPI_MMIO_base(self) -> int:
+
[docs]    def get_SPI_MMIO_base(self) -> int:
         spi_base = 0
         if self.mmio.is_MMIO_BAR_defined('SPIBAR'):
             (spi_base, _) = self.mmio.get_MMIO_BAR_base_address('SPIBAR')
@@ -285,22 +280,13 @@ 
Source code for chipsec.hal.spi
         self.logger.log_hal(f'[spi] SPI MMIO base: 0x{spi_base:016X} (assuming below 4GB)')
         return spi_base

 
-
-

-[docs]
-    def spi_reg_read(self, reg: int, size: int = 4) -> int:
+
[docs]    def spi_reg_read(self, reg: int, size: int = 4) -> int:
         return self.mmio.read_MMIO_reg(self.rcba_spi_base, reg, size)

 
-
-

-[docs]
-    def spi_reg_write(self, reg: int, value: int, size: int = 4) -> Optional[int]:
+
[docs]    def spi_reg_write(self, reg: int, value: int, size: int = 4) -> Optional[int]:
         return self.mmio.write_MMIO_reg(self.rcba_spi_base, reg, value, size)

 
-
-

-[docs]
-    def get_SPI_region(self, spi_region_id: int) -> Tuple[int, int, int]:
+
[docs]    def get_SPI_region(self, spi_region_id: int) -> Tuple[int, int, int]:
         freg_name = SPI_REGION[spi_region_id]
         if not self.cs.is_register_defined(freg_name):
             return (0, 0, 0)
@@ -313,14 +299,11 @@ 
Source code for chipsec.hal.spi
         range_limit |= SPI_FLA_PAGE_MASK
         return (range_base, range_limit, freg)

 
-
     SpiRegions = Dict[int, Tuple[int, int, int, str, int]]
 
     # all_regions = True : return all SPI regions
     # all_regions = False: return only available SPI regions (limit >= base)
-

-[docs]
-    def get_SPI_regions(self, all_regions: bool = True) -> SpiRegions:
+
[docs]    def get_SPI_regions(self, all_regions: bool = True) -> SpiRegions:
         spi_regions: Dict[int, Tuple[int, int, int, str, int]] = {}
         for r in SPI_REGION:
             (range_base, range_limit, freg) = self.get_SPI_region(r)
@@ -331,10 +314,7 @@ 
Source code for chipsec.hal.spi
                 spi_regions[r] = (range_base, range_limit, range_size, SPI_REGION_NAMES[r], freg)
         return spi_regions

 
-
-

-[docs]
-    def get_SPI_Protected_Range(self, pr_num: int) -> Tuple[int, int, int, int, int, int]:
+
[docs]    def get_SPI_Protected_Range(self, pr_num: int) -> Tuple[int, int, int, int, int, int]:
         if pr_num > SPI_MAX_PR_COUNT:
             return (0, 0, 0, 0, 0, 0)
 
@@ -357,14 +337,11 @@ 
Source code for chipsec.hal.spi
 
         return (base, limit, wpe, rpe, pr_j_reg, pr_j)

 
-
     ##############################################################################################################
     # SPI configuration
     ##############################################################################################################
 
-

-[docs]
-    def display_SPI_Flash_Descriptor(self) -> None:
+
[docs]    def display_SPI_Flash_Descriptor(self) -> None:
         self.logger.log("============================================================")
         self.logger.log("SPI Flash Descriptor")
         self.logger.log("------------------------------------------------------------")
@@ -392,10 +369,7 @@ 
Source code for chipsec.hal.spi
             fdod = self.cs.read_register('FDOD')
             self.logger.log(f'{fdod:08X}')

 
-
-

-[docs]
-    def display_SPI_opcode_info(self) -> None:
+
[docs]    def display_SPI_opcode_info(self) -> None:
         self.logger.log("============================================================")
         self.logger.log("SPI Opcode Info")
         self.logger.log("------------------------------------------------------------")
@@ -428,12 +402,9 @@ 
Source code for chipsec.hal.spi
                 desc = 'SPI write cycle with address'
             else:
                 desc = ''
-            self.logger.log(f'Opcode{j:d}  | 0x{(opmenu >> j * 8) & 0xFF:02X}   | {optype_j:x}      | {desc} ')

+            self.logger.log(f'Opcode{j:d}  | 0x{(opmenu >> j * 8) & 0xFF:02X}   | {optype_j:x}      | {desc} ')

 
-
-

-[docs]
-    def display_SPI_Flash_Regions(self) -> None:
+
[docs]    def display_SPI_Flash_Regions(self) -> None:
         self.logger.log("------------------------------------------------------------")
         self.logger.log("Flash Region             | FREGx Reg | Base     | Limit     ")
         self.logger.log("------------------------------------------------------------")
@@ -442,10 +413,7 @@ 
Source code for chipsec.hal.spi
             base, limit, size, name, freg = region
             self.logger.log(f'{region_id:d} {name:22} | {freg:08X}  | {base:08X} | {limit:08X} ')

 
-
-

-[docs]
-    def display_BIOS_region(self) -> None:
+
[docs]    def display_BIOS_region(self) -> None:
         bfpreg = self.cs.read_register('BFPR')
         base = self.cs.get_register_field('BFPR', bfpreg, 'PRB') << SPI_FLA_SHIFT
         limit = self.cs.get_register_field('BFPR', bfpreg, 'PRL') << SPI_FLA_SHIFT
@@ -456,10 +424,7 @@ 
Source code for chipsec.hal.spi
         self.logger.log(f'  Base  : {base:08X}')
         self.logger.log(f'  Limit : {limit:08X}')

 
-
-

-[docs]
-    def display_SPI_Ranges_Access_Permissions(self) -> None:
+
[docs]    def display_SPI_Ranges_Access_Permissions(self) -> None:
         self.logger.log("SPI Flash Region Access Permissions")
         self.logger.log("------------------------------------------------------------")
         fracc = self.cs.read_register('FRAP')
@@ -473,21 +438,18 @@ 
Source code for chipsec.hal.spi
         self.logger.log(f'BIOS Region Write Access Grant ({bmwag:02X}):')
         regions = self.get_SPI_regions()
         for region_id in regions:
-            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != bmwag & (1 << region_id):1d}')
+            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != bmwag & (1 << region_id):1d}')
         self.logger.log(f'BIOS Region Read Access Grant ({bmrag:02X}):')
         for region_id in regions:
-            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != bmrag & (1 << region_id):1d}')
+            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != bmrag & (1 << region_id):1d}')
         self.logger.log(f'BIOS Region Write Access ({brwa:02X}):')
         for region_id in regions:
-            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != brwa & (1 << region_id):1d}')
+            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != brwa & (1 << region_id):1d}')
         self.logger.log(f'BIOS Region Read Access ({brra:02X}):')
         for region_id in regions:
-            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != brra & (1 << region_id):1d}')

-
+            self.logger.log(f'  {SPI_REGION[region_id]:12}: {0 != brra & (1 << region_id):1d}')

 
-

-[docs]
-    def display_SPI_Protected_Ranges(self) -> None:
+
[docs]    def display_SPI_Protected_Ranges(self) -> None:
         self.logger.log("SPI Protected Ranges")
         self.logger.log("------------------------------------------------------------")
         self.logger.log("PRx (offset) | Value    | Base     | Limit    | WP? | RP?")
@@ -496,10 +458,7 @@ 
Source code for chipsec.hal.spi
             (base, limit, wpe, rpe, pr_reg_off, pr_reg_value) = self.get_SPI_Protected_Range(j)
             self.logger.log(f'PR{j:d} ({pr_reg_off:02X})     | {pr_reg_value:08X} | {base:08X} | {limit:08X} | {wpe:d}   | {rpe:d} ')

 
-
-

-[docs]
-    def display_SPI_map(self) -> None:
+
[docs]    def display_SPI_map(self) -> None:
         self.logger.log("============================================================")
         self.logger.log("SPI Flash Map")
         self.logger.log("------------------------------------------------------------")
@@ -525,14 +484,11 @@ 
Source code for chipsec.hal.spi
         self.display_SPI_Protected_Ranges()
         self.logger.log('')

 
-
     ##############################################################################################################
     # BIOS Write Protection
     ##############################################################################################################
 
-

-[docs]
-    def display_BIOS_write_protection(self) -> None:
+
[docs]    def display_BIOS_write_protection(self) -> None:
         if self.cs.is_register_defined('BC'):
             reg_value = self.cs.read_register('BC')
             self.cs.print_register('BC', reg_value)
@@ -540,10 +496,7 @@ 
Source code for chipsec.hal.spi
             if self.logger.HAL:
                 self.logger.log_error("Could not locate the definition of 'BIOS Control' register..")

 
-
-

-[docs]
-    def disable_BIOS_write_protection(self) -> bool:
+
[docs]    def disable_BIOS_write_protection(self) -> bool:
         if self.logger.HAL:
             self.display_BIOS_write_protection()
         ble = self.cs.get_control('BiosLockEnable')
@@ -575,7 +528,6 @@ 
Source code for chipsec.hal.spi
 
         return (bioswe == 1)

 
-
     ##############################################################################################################
     # SPI Controller access functions
     ##############################################################################################################
@@ -647,23 +599,18 @@ 
Source code for chipsec.hal.spi
 
         return cycle_done
 
-

-[docs]
-    def check_hardware_sequencing(self) -> None:
+
[docs]    def check_hardware_sequencing(self) -> None:
         # Test if the flash decriptor is valid (and hardware sequencing enabled)
         fdv = self.cs.read_register_field('HSFS', 'FDV')
         if fdv == 0:
             self.logger.log_error("HSFS.FDV is 0, hardware sequencing is disabled")
             raise SpiRuntimeError("Chipset does not support hardware sequencing")

 
-
     #
     # SPI Flash operations
     #
 
-

-[docs]
-    def read_spi_to_file(self, spi_fla: int, data_byte_count: int, filename: str) -> bytes:
+
[docs]    def read_spi_to_file(self, spi_fla: int, data_byte_count: int, filename: str) -> bytes:
         buf = self.read_spi(spi_fla, data_byte_count)
         if buf is None:
             return b''
@@ -673,18 +620,12 @@ 
Source code for chipsec.hal.spi
             print_buffer_bytes(buf, 16)
         return buf

 
-
-

-[docs]
-    def write_spi_from_file(self, spi_fla: int, filename: str) -> bool:
+
[docs]    def write_spi_from_file(self, spi_fla: int, filename: str) -> bool:
         buf = read_file(filename)
         return self.write_spi(spi_fla, buf)

-
         # return self.write_spi( spi_fla, struct.unpack('B'*len(buf), buf) )
 
-

-[docs]
-    def read_spi(self, spi_fla: int, data_byte_count: int) -> bytes:
+
[docs]    def read_spi(self, spi_fla: int, data_byte_count: int) -> bytes:
 
         self.check_hardware_sequencing()
 
@@ -704,18 +645,18 @@ 
Source code for chipsec.hal.spi
             return b''
 
         for i in range(n):
-            self.logger.log_hal(f'[spi] Reading chunk {i:d} of 0x{dbc:x} bytes from 0x{spi_fla + i * dbc:x}')
+            self.logger.log_hal(f'[spi] Reading chunk {i:d} of 0x{dbc:x} bytes from 0x{spi_fla + i * dbc:x}')
             if not self._send_spi_cycle(HSFCTL_READ_CYCLE, dbc - 1, spi_fla + i * dbc):
                 self.logger.log_error("SPI flash read failed")
             else:
                 for fdata_idx in range(0, dbc // 4):
                     dword_value = self.spi_reg_read(self.fdata0_off + fdata_idx * 4)
                     if self.logger.HAL:
-                        self.logger.log(f'[spi] FDATA00 + 0x{fdata_idx * 4:x}: 0x{dword_value:x}')
+                        self.logger.log(f'[spi] FDATA00 + 0x{fdata_idx * 4:x}: 0x{dword_value:x}')
                     buf += struct.pack("I", dword_value)
 
         if (0 != r):
-            self.logger.log_hal(f'[spi] Reading remaining 0x{r:x} bytes from 0x{spi_fla + n * dbc:x}')
+            self.logger.log_hal(f'[spi] Reading remaining 0x{r:x} bytes from 0x{spi_fla + n * dbc:x}')
             if not self._send_spi_cycle(HSFCTL_READ_CYCLE, r - 1, spi_fla + n * dbc):
                 self.logger.log_error("SPI flash read failed")
             else:
@@ -724,7 +665,7 @@ 
Source code for chipsec.hal.spi
                 for fdata_idx in range(0, n_dwords):
                     dword_value = self.spi_reg_read(self.fdata0_off + fdata_idx * 4)
                     if self.logger.HAL:
-                        self.logger.log(f'[spi] FDATA00 + 0x{fdata_idx * 4:x}: 0x{dword_value:08X}')
+                        self.logger.log(f'[spi] FDATA00 + 0x{fdata_idx * 4:x}: 0x{dword_value:08X}')
                     if (fdata_idx == (n_dwords - 1)) and (0 != r % 4):
                         t = r % 4
                     for j in range(t):
@@ -736,10 +677,7 @@ 
Source code for chipsec.hal.spi
 
         return buf

 
-
-

-[docs]
-    def write_spi(self, spi_fla: int, buf: bytes) -> bool:
+
[docs]    def write_spi(self, spi_fla: int, buf: bytes) -> bool:
 
         self.check_hardware_sequencing()
 
@@ -758,7 +696,7 @@ 
Source code for chipsec.hal.spi
 
         for i in range(n):
             if self.logger.UTIL_TRACE or self.logger.HAL:
-                self.logger.log(f'[spi] Writing chunk {i:d} of 0x{dbc:x} bytes to 0x{spi_fla + i * dbc:x}')
+                self.logger.log(f'[spi] Writing chunk {i:d} of 0x{dbc:x} bytes to 0x{spi_fla + i * dbc:x}')
             dword_value = ((buf[i * dbc + 3]) << 24) | ((buf[i * dbc + 2]) << 16) | ((buf[i * dbc + 1]) << 8) | (buf[i * dbc])
             if self.logger.HAL:
                 self.logger.log(f'[spi] in FDATA00 = 0x{dword_value:08X}')
@@ -769,7 +707,7 @@ 
Source code for chipsec.hal.spi
 
         if (0 != r):
             if self.logger.UTIL_TRACE or self.logger.HAL:
-                self.logger.log(f'[spi] Writing remaining 0x{r:x} bytes to FLA = 0x{spi_fla + n * dbc:x}')
+                self.logger.log(f'[spi] Writing remaining 0x{r:x} bytes to FLA = 0x{spi_fla + n * dbc:x}')
             dword_value = 0
             for j in range(r):
                 dword_value |= (buf[n * dbc + j] << 8 * j)
@@ -782,10 +720,7 @@ 
Source code for chipsec.hal.spi
 
         return write_ok

 
-
-

-[docs]
-    def erase_spi_block(self, spi_fla: int) -> bool:
+
[docs]    def erase_spi_block(self, spi_fla: int) -> bool:
 
         self.check_hardware_sequencing()
 
@@ -803,31 +738,25 @@ 
Source code for chipsec.hal.spi
 
         return erase_ok

 
-
     #
     # SPI SFDP operations
     #
-

-[docs]
-    def ptmesg(self, offset: int) -> int:
+
[docs]    def ptmesg(self, offset: int) -> int:
         self.spi_reg_write(self.bios_ptinx, offset)
         self.spi_reg_read(self.bios_ptinx)
         return self.spi_reg_read(self.bios_ptdata)

 
-
-

-[docs]
-    def get_SPI_SFDP(self) -> bool:
+
[docs]    def get_SPI_SFDP(self) -> bool:
         ret = False
         for component in range(0, 2):
-            self.logger.log(f'Scanning for Flash device {component + 1:d}')
+            self.logger.log(f'Scanning for Flash device {component + 1:d}')
             offset = 0x0000 | (component << 14)
             sfdp_signature = self.ptmesg(offset)
             if sfdp_signature == SFDP_HEADER:
-                self.logger.log(f'  * Found valid SFDP header for Flash device {component + 1:d}')
+                self.logger.log(f'  * Found valid SFDP header for Flash device {component + 1:d}')
                 ret = True
             else:
-                self.logger.log(f"  * Didn't find a valid SFDP header for Flash device {component + 1:d}")
+                self.logger.log(f"  * Didn't find a valid SFDP header for Flash device {component + 1:d}")
                 continue
             # Increment offset to read second dword of SFDP header structure
             sfdp_data = self.ptmesg(offset + 0x4)
@@ -858,9 +787,9 @@ 
Source code for chipsec.hal.spi
                 pTable_length = []
                 # Calculate which fdata_offset registers to read, based on number of parameter headers present
                 for i in range(1, num_of_param_headers):
-                    self.logger.log(f'  * Parameter Header:{i + 1:d}')
-                    data_reg_1 = f'self.fdata{str(2 + (2 * i))}_off'
-                    data_reg_2 = f'self.fdata{str(2 + (2 * i) + 1)}_off'
+                    self.logger.log(f'  * Parameter Header:{i + 1:d}')
+                    data_reg_1 = f'self.fdata{str(2 + (2 * i))}_off'
+                    data_reg_2 = f'self.fdata{str(2 + (2 * i) + 1)}_off'
                     data_dword_1 = self.spi_reg_read(eval(data_reg_1))
                     data_dword_2 = self.spi_reg_read(eval(data_reg_2))
                     id_manuf = (data_dword_2 & 0xFF000000) >> 16 | (data_dword_1 & 0xFF)
@@ -885,14 +814,11 @@ 
Source code for chipsec.hal.spi
                 self.cs.print_register(f'DWORD{count}', sfdp_data)
         return ret

 
-
     #
     # SPI JEDEC ID operations
     #
 
-

-[docs]
-    def get_SPI_JEDEC_ID(self) -> int:
+
[docs]    def get_SPI_JEDEC_ID(self) -> int:
 
         if self.cs.register_has_field('HSFS', 'FCYCLE'):
             self.check_hardware_sequencing()
@@ -905,10 +831,7 @@ 
Source code for chipsec.hal.spi
 
         return ((id & 0xFF) << 16) | (id & 0xFF00) | ((id >> 16) & 0xFF)

 
-
-

-[docs]
-    def get_SPI_JEDEC_ID_decoded(self) -> Tuple[int, str, str]:
+
[docs]    def get_SPI_JEDEC_ID_decoded(self) -> Tuple[int, str, str]:
 
         jedec_id = self.get_SPI_JEDEC_ID()
         if jedec_id is False:
@@ -916,9 +839,7 @@ 
Source code for chipsec.hal.spi
         manu = JEDEC_ID.MANUFACTURER.get((jedec_id >> 16) & 0xff, 'Unknown')
         part = JEDEC_ID.DEVICE.get(jedec_id, 'Unknown')
 
-        return (jedec_id, manu, part)

-

-
+        return (jedec_id, manu, part)

 

 
             

@@ -978,7 +899,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -998,8 +919,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/spi_descriptor.html b/_modules/chipsec/hal/spi_descriptor.html
index dd92d33e..ee4be0dc 100644
--- a/_modules/chipsec/hal/spi_descriptor.html
+++ b/_modules/chipsec/hal/spi_descriptor.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.spi_descriptor — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,9 +77,7 @@ 
Source code for chipsec.hal.spi_descriptor
 SPI_FLASH_DESCRIPTOR_SIZE = 0x1000
 
 
-

-[docs]
-def get_spi_flash_descriptor(rom: bytes) -> Tuple[int, bytes]:
+
[docs]def get_spi_flash_descriptor(rom: bytes) -> Tuple[int, bytes]:
     pos = rom.find(SPI_FLASH_DESCRIPTOR_SIGNATURE)
     if (-1 == pos or pos < 0x10):
         return (-1, b'')
@@ -86,20 +86,14 @@ 
Source code for chipsec.hal.spi_descriptor
     return (fd_off, fd)

 
 
-
-

-[docs]
-def get_SPI_master(flmstr: int) -> Tuple[int, int, int]:
+
[docs]def get_SPI_master(flmstr: int) -> Tuple[int, int, int]:
     requester_id = (flmstr & 0xFFFF)
     master_region_ra = ((flmstr >> 16) & 0xFF)
     master_region_wa = ((flmstr >> 24) & 0xFF)
     return (requester_id, master_region_ra, master_region_wa)

 
 
-
-

-[docs]
-def get_spi_regions(fd: bytes) -> Optional[List[Tuple[int, str, int, int, int, bool]]]:
+
[docs]def get_spi_regions(fd: bytes) -> Optional[List[Tuple[int, str, int, int, int, bool]]]:
     pos = fd.find(SPI_FLASH_DESCRIPTOR_SIGNATURE)
     if not (pos == 0x10):
         return None
@@ -124,10 +118,7 @@ 
Source code for chipsec.hal.spi_descriptor
     return flregs

 
 
-
-

-[docs]
-def parse_spi_flash_descriptor(cs, rom: bytes) -> None:
+
[docs]def parse_spi_flash_descriptor(cs, rom: bytes) -> None:
     if not (isinstance(rom, str) or isinstance(rom, bytes)):
         logger().log_error(f'Invalid fd object type {type(rom)}')
         return
@@ -210,9 +201,9 @@ 
Source code for chipsec.hal.spi_descriptor
     flcomp = struct.unpack_from('=I', fd[fcba + 0x0:fcba + 0x4])[0]
     logger().log(f'+ 0x{fcba:04X} FLCOMP   : 0x{flcomp:08X}')
     flil = struct.unpack_from('=I', fd[fcba + 0x4:fcba + 0x8])[0]
-    logger().log(f'+ 0x{fcba + 0x4:04X} FLIL     : 0x{flil:08X}')
+    logger().log(f'+ 0x{fcba + 0x4:04X} FLIL     : 0x{flil:08X}')
     flpb = struct.unpack_from('=I', fd[fcba + 0x8:fcba + 0xC])[0]
-    logger().log(f'+ 0x{fcba + 0x8:04X} FLPB     : 0x{flpb:08X}')
+    logger().log(f'+ 0x{fcba + 0x8:04X} FLPB     : 0x{flpb:08X}')
 
     #
     # Flash Descriptor Region Section
@@ -256,7 +247,7 @@ 
Source code for chipsec.hal.spi_descriptor
         master_region_ra = cs.get_register_field('FLMSTR1', flmstr, 'MRRA')
         master_region_wa = cs.get_register_field('FLMSTR1', flmstr, 'MRWA')
         flmstrs[m] = (master_region_ra, master_region_wa)
-        logger().log(f'+ 0x{flmstr_off:04X} FLMSTR{m + 1:d}   : 0x{flmstr:08X}')
+        logger().log(f'+ 0x{flmstr_off:04X} FLMSTR{m + 1:d}   : 0x{flmstr:08X}')
 
     logger().log('')
     logger().log('Master Read/Write Access to Flash Regions')
@@ -308,7 +299,6 @@ 
Source code for chipsec.hal.spi_descriptor
     logger().log('########################################################')
     logger().log('# END OF SPI FLASH DESCRIPTOR')
     logger().log('########################################################')

-
 

 
             

@@ -368,7 +358,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -388,8 +378,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/spi_jedec_ids.html b/_modules/chipsec/hal/spi_jedec_ids.html
index e87f56c4..63d3fc87 100644
--- a/_modules/chipsec/hal/spi_jedec_ids.html
+++ b/_modules/chipsec/hal/spi_jedec_ids.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.spi_jedec_ids — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -63,9 +65,7 @@ 
Source code for chipsec.hal.spi_jedec_ids
 
 from typing import Dict
 
-

-[docs]
-class JEDEC_ID:
+
[docs]class JEDEC_ID:
 
     MANUFACTURER: Dict[int, str] = {0xEF: 'Winbond',
                                     0xC2: 'Macronix'}
@@ -78,7 +78,6 @@ 
Source code for chipsec.hal.spi_jedec_ids
                               0xEF4019: 'W25Q256',
                               0xC22017: 'MX25L6408',
                               0xC22018: 'MX25L12805'}

-
 

 
             

@@ -138,7 +137,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -158,8 +157,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/hal/spi_uefi.html b/_modules/chipsec/hal/spi_uefi.html
index 65a203e4..331cb5e5 100644
--- a/_modules/chipsec/hal/spi_uefi.html
+++ b/_modules/chipsec/hal/spi_uefi.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.hal.spi_uefi — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -111,9 +113,7 @@ 
Source code for chipsec.hal.spi_uefi
 WRITE_ALL_HASHES = False
 
 
-

-[docs]
-def decompress_section_data(section_dir_path: str, sec_fs_name: str, compressed_data: bytes, compression_type: int) -> bytes:
+
[docs]def decompress_section_data(section_dir_path: str, sec_fs_name: str, compressed_data: bytes, compression_type: int) -> bytes:
     uefi_uc = UEFICompression()
     uncompressed_name = os.path.join(section_dir_path, sec_fs_name)
     logger().log_hal(f'[uefi] Decompressing EFI binary (type = 0x{compression_type:X})\n       {uncompressed_name} ->\n')
@@ -121,20 +121,14 @@ 
Source code for chipsec.hal.spi_uefi
     return uncompressed_image

 
 
-
-

-[docs]
-def compress_image(image: bytes, compression_type: int) -> bytes:
+
[docs]def compress_image(image: bytes, compression_type: int) -> bytes:
     uefi_uc = UEFICompression()
     logger().log_hal(f'[uefi] Compressing EFI binary (type = 0x{compression_type:X})\n')
     compressed_image = uefi_uc.compress_EFI_binary(image, compression_type)
     return compressed_image

 
 
-
-

-[docs]
-def modify_uefi_region(data: bytes, command: int, guid: UUID, uefi_file: bytes = b'') -> bytes:
+
[docs]def modify_uefi_region(data: bytes, command: int, guid: UUID, uefi_file: bytes = b'') -> bytes:
     FvEndOffset = 0  # Default
     fv = NextFwVolume(data)
     while fv is not None:
@@ -191,10 +185,7 @@ 
Source code for chipsec.hal.spi_uefi
     return data

 
 
-
-

-[docs]
-def build_efi_modules_tree(fwtype: str, data: bytes, Size: int, offset: int, polarity: bool) -> List[EFI_SECTION]:
+
[docs]def build_efi_modules_tree(fwtype: str, data: bytes, Size: int, offset: int, polarity: bool) -> List[EFI_SECTION]:
     sections: List[EFI_SECTION] = []
     secn = 0
 
@@ -296,16 +287,13 @@ 
Source code for chipsec.hal.spi_uefi
     return sections

 
 
-
 #
 # build_efi_file_tree - extract EFI FV file from EFI image and build an object tree
 #
 # Input arguements:
 # fv_image - fv_image containing files
 # fwtype - platform specific firmware type used to detect NVRAM format (VSS, EVSA, NVAR...)
-

-[docs]
-def build_efi_file_tree(fv_img: bytes, fwtype: str) -> List[EFI_FILE]:
+
[docs]def build_efi_file_tree(fv_img: bytes, fwtype: str) -> List[EFI_FILE]:
     fv_size, HeaderSize, Attributes = GetFvHeader(fv_img)
     polarity = bool(Attributes & EFI_FVB2_ERASE_POLARITY)
     fwbin = NextFwFile(fv_img, fv_size, HeaderSize, polarity)
@@ -351,7 +339,6 @@ 
Source code for chipsec.hal.spi_uefi
     return fv

 
 
-
 #
 # build_efi_tree - extract EFI modules (FV, files, sections) from EFI image and build an object tree
 #
@@ -359,9 +346,7 @@ 
Source code for chipsec.hal.spi_uefi
 #   data           - an image containing UEFI firmware volumes
 #   fwtype         - platform specific firmware type used to detect NVRAM format (VSS, EVSA, NVAR...)
 #
-

-[docs]
-def build_efi_tree(data: bytes, fwtype: str) -> List['EFI_MODULE']:
+
[docs]def build_efi_tree(data: bytes, fwtype: str) -> List['EFI_MODULE']:
     fvolumes = []
     fv = NextFwVolume(data)
     while fv is not None:
@@ -387,14 +372,11 @@ 
Source code for chipsec.hal.spi_uefi
     return fvolumes

 
 
-
 #
 # Attempt to find efi modules using calls to build_efi_tree, build_efi_file_tree,
 # and build_efi_modules_tree in succession.  Return once one of the calls is successful
 #
-

 
             

@@ -199,7 +189,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -219,8 +209,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/modules/common/spi_fdopss.html b/_modules/chipsec/modules/common/spi_fdopss.html
index 863afb54..10942e29 100644
--- a/_modules/chipsec/modules/common/spi_fdopss.html
+++ b/_modules/chipsec/modules/common/spi_fdopss.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.modules.common.spi_fdopss — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -78,17 +80,13 @@ 
Source code for chipsec.modules.common.spi_fdopss
TAGS = [MTAG_BIOS]
 
 
-

-[docs]
-class spi_fdopss(BaseModule):
+
[docs]class spi_fdopss(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
         self.rc_res = ModuleResult(0x9b73a54, 'https://chipsec.github.io/modules/chipsec.modules.common.spi_fdopss.html')
 
-

-[docs]
-    def is_supported(self) -> bool:
+
[docs]    def is_supported(self) -> bool:
         if not self.cs.register_has_field('HSFS', 'FDOPSS'):
             self.logger.log_important('HSFS.FDOPSS field not defined for platform.  Skipping module.')
             self.rc_res.setStatusBit(self.rc_res.status.NOT_APPLICABLE)
@@ -96,10 +94,7 @@ 
Source code for chipsec.modules.common.spi_fdopss
return False
         return True

 
-
-

-[docs]
-    def check_fd_security_override_strap(self) -> int:
+
[docs]    def check_fd_security_override_strap(self) -> int:
         hsfs_reg = self.cs.read_register('HSFS')
         self.cs.print_register('HSFS', hsfs_reg)
         fdopss = self.cs.get_register_field('HSFS', hsfs_reg, 'FDOPSS')
@@ -112,19 +107,14 @@ 
Source code for chipsec.modules.common.spi_fdopss
self.rc_res.setStatusBit(self.rc_res.status.CONFIGURATION)
             return self.rc_res.getReturnCode(ModuleResult.FAILED)

 
-
     # --------------------------------------------------------------------------
     # run( module_argv )
     # Required function: run here all tests from this module
     # --------------------------------------------------------------------------
-

-[docs]
-    def run(self, module_argv: List[str]) -> int:
+
[docs]    def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Descriptor Security Override Pin-Strap")
         self.res = self.check_fd_security_override_strap()
-        return self.res

-

-
+        return self.res

 

 
             

@@ -184,7 +174,7 @@ 
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-
+
         

       

       

@@ -204,8 +194,8 @@ 
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\ No newline at end of file
diff --git a/_modules/chipsec/modules/common/spi_lock.html b/_modules/chipsec/modules/common/spi_lock.html
index a90d927f..7074db74 100644
--- a/_modules/chipsec/modules/common/spi_lock.html
+++ b/_modules/chipsec/modules/common/spi_lock.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.modules.common.spi_lock — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -88,17 +90,13 @@ 
Source code for chipsec.modules.common.spi_lock
<
 TAGS = [MTAG_BIOS]
 
 
-

-[docs]
-class spi_lock(BaseModule):
+
[docs]class spi_lock(BaseModule):
 
     def __init__(self):
         super(spi_lock, self).__init__()
         self.rc_res = ModuleResult(0xf73c7bd, 'https://chipsec.github.io/modules/chipsec.modules.common.spi_lock.html')
 
-

-[docs]
-    def is_supported(self) -> bool:
+
[docs]    def is_supported(self) -> bool:
         if self.cs.is_control_defined('FlashLockDown'):
             return True
         self.rc_res.setStatusBit(self.rc_res.status.NOT_APPLICABLE)
@@ -106,10 +104,7 @@ 
Source code for chipsec.modules.common.spi_lock
<
         self.logger.log_important('FlashLockDown control not define for platform.  Skipping module.')
         return False

 
-
-

-[docs]
-    def check_spi_lock(self) -> int:
+
[docs]    def check_spi_lock(self) -> int:
         res = ModuleResult.PASSED
         reg_print = True
         if self.cs.is_control_defined('SpiWriteStatusDis'):
@@ -140,15 +135,10 @@ 
Source code for chipsec.modules.common.spi_lock
<
 
         return self.rc_res.getReturnCode(res)

 
-
-

-[docs]
-    def run(self, module_argv: List[str]) -> int:
+
[docs]    def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("SPI Flash Controller Configuration Locks")
         self.res = self.check_spi_lock()
-        return self.res

-

-
+        return self.res

 

 
             

@@ -208,7 +198,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -228,8 +218,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/modules/common/uefi/access_uefispec.html b/_modules/chipsec/modules/common/uefi/access_uefispec.html
index 3746f9e1..787ab9f8 100644
--- a/_modules/chipsec/modules/common/uefi/access_uefispec.html
+++ b/_modules/chipsec/modules/common/uefi/access_uefispec.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.modules.common.uefi.access_uefispec — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -89,9 +91,7 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
TAGS = [MTAG_BIOS, MTAG_SECUREBOOT]
 
 
-

-[docs]
-class access_uefispec(BaseModule):
+
[docs]class access_uefispec(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
@@ -105,6 +105,9 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
self.uefispec_vars = {
             # From UEFI Spec Table 11 "Global Variables"
+            # Updated to version 2.10 Section 3.3 "Globally Defined Variables"
+            # https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
+            # https://uefi.org/specs/UEFI/2.10/03_Boot_Manager.html#globally-defined-variables
             "LangCodes": bs | rt,
             "Lang": nv | bs | rt,
             "Timeout": nv | bs | rt,
@@ -120,15 +123,23 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
"Boot0002": nv | bs | rt,
             "BootOrder": nv | bs | rt,
 
+            "AuditMode": bs | rt,
             "BootNext": nv | bs | rt,
             "BootCurrent": bs | rt,
             "BootOptionSupport": bs | rt,
+            "CryptoIndications": nv | bs | rt,
+            "CryptoIndicationsSupport": bs | rt,
+            "CrytopIndicationsActive": bs | rt,
+            "DeployedMode": bs | rt,
+            "devAuthBoot": bs | rt,
+            "devdbDefault": bs | rt,
             "Driver0001": nv | bs | rt,
             "DriverOrder": nv | bs | rt,
             "Key0001": nv | bs | rt,
             "HwErrRecSupport": nv | bs | rt,  # HwErrRecSupport should be RO
             "SetupMode": bs | rt,  # SetupMode should be RO
             "KEK": nv | bs | rt | ta,
+            "OsRecoveryOrder": nv | bs | rt | ta,
             "PK": nv | bs | rt | ta,
             "SignatureSupport": bs | rt,  # RO
             "SecureBoot": bs | rt,  # RO
@@ -139,14 +150,15 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
"dbtDefault": bs | rt,  # RO
             "OsIndicationsSupported": bs | rt,  # RO
             "OsIndications": nv | bs | rt,
+            "SysPrep0001": nv | bs | rt,
+            "SysPrep0002": nv | bs | rt,
+            "SysPrepOrder": nv | bs | rt,
             "VendorKeys": bs | rt  # RO
         }
 
         self.uefispec_ro_vars = ("HwErrRecSupport", "SetupMode", "SignatureSupport", "SecureBoot", "KEKDefault", "PKDefault", "dbDefault", "dbxDefault", "dbtDefault", "OsIndicationsSupported", "VendorKeys")
 
-

-[docs]
-    def is_supported(self) -> bool:
+
[docs]    def is_supported(self) -> bool:
         supported = self.cs.helper.EFI_supported()
         if not supported:
             self.logger.log("OS does not support UEFI Runtime API")
@@ -154,10 +166,7 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
self.res = self.rc_res.getReturnCode(ModuleResult.NOTAPPLICABLE)
         return supported

 
-
-

-[docs]
-    def diff_var(self, data1: int, data2: int) -> bool:
+
[docs]    def diff_var(self, data1: int, data2: int) -> bool:
         if data1 is None or data2 is None:
             return data1 != data2
 
@@ -171,10 +180,7 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
else:
             return False

 
-
-

-[docs]
-    def can_modify(self, name: str, guid: str, data: bytes) -> bool:
+
[docs]    def can_modify(self, name: str, guid: str, data: bytes) -> bool:
         ret = False
 
         #origdata = _uefi.get_EFI_variable(name, guid)
@@ -196,10 +202,7 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
self.logger.log_bad(f'RECOVERY FAILED. Variable {nameguid} remains corrupted. Original data value: {origdata}')
         return ret

 
-
-

-[docs]
-    def check_vars(self, do_modify: bool) -> int:
+
[docs]    def check_vars(self, do_modify: bool) -> int:
         res = ModuleResult.PASSED
         vars = self._uefi.list_EFI_variables()
         if vars is None:
@@ -279,17 +282,12 @@ 
Source code for chipsec.modules.common.uefi.access_uefispec
self.logger.log_failed('Some EFI variables were not protected according to spec.')
         return res

 
-
-

-[docs]
-    def run(self, module_argv: List[str]) -> int:
+
[docs]    def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("Access Control of EFI Variables")
 
         do_modify = (len(module_argv) > 0 and module_argv[0] == OPT_MODIFY)
         self.res = self.check_vars(do_modify)
-        return self.rc_res.getReturnCode(self.res)

-

-
+        return self.rc_res.getReturnCode(self.res)

 

 
             

@@ -349,7 +347,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -369,8 +367,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/modules/common/uefi/s3bootscript.html b/_modules/chipsec/modules/common/uefi/s3bootscript.html
index 09453489..95366b19 100644
--- a/_modules/chipsec/modules/common/uefi/s3bootscript.html
+++ b/_modules/chipsec/modules/common/uefi/s3bootscript.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.modules.common.uefi.s3bootscript — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -111,18 +113,14 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
HIGH_BIOS_RANGE_SIZE = 2 * BOUNDARY_1MB
 
 
-

-[docs]
-class s3bootscript(BaseModule):
+
[docs]class s3bootscript(BaseModule):
 
     def __init__(self):
         BaseModule.__init__(self)
         self._uefi = UEFI(self.cs)
         self.rc_res = ModuleResult(0x9e3cf54, 'https://chipsec.github.io/modules/chipsec.modules.common.uefi.s3bootscript.html')
 
-

-[docs]
-    def is_supported(self) -> bool:
+
[docs]    def is_supported(self) -> bool:
         supported = self.cs.helper.EFI_supported()
         if not supported:
             self.logger.log("OS does not support UEFI Runtime API")
@@ -130,22 +128,13 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
self.res = self.rc_res.getReturnCode(ModuleResult.NOTAPPLICABLE)
         return supported

 
-
-

-[docs]
-    def is_inside_SMRAM(self, pa: int) -> bool:
+
[docs]    def is_inside_SMRAM(self, pa: int) -> bool:
         return (pa >= self.smrambase and pa < self.smramlimit)

 
-
-

-[docs]
-    def is_inside_SPI(self, pa: int) -> bool:
+
[docs]    def is_inside_SPI(self, pa: int) -> bool:
         return (pa >= (BOUNDARY_4GB - HIGH_BIOS_RANGE_SIZE) and pa < BOUNDARY_4GB)

 
-
-

-[docs]
-    def check_dispatch_opcodes(self, bootscript_entries: List[S3BOOTSCRIPT_ENTRY]) -> bool:
+
[docs]    def check_dispatch_opcodes(self, bootscript_entries: List[S3BOOTSCRIPT_ENTRY]) -> bool:
         self.logger.log('[*] Checking entry-points of Dispatch opcodes..')
         dispatch_ep_ok = True
         n_dispatch = 0
@@ -163,10 +152,7 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
self.logger.log(f"[*] Found {n_dispatch:d} Dispatch opcodes")
         return dispatch_ep_ok

 
-
-

-[docs]
-    def check_s3_bootscript(self, bootscript_pa: int) -> int:
+
[docs]    def check_s3_bootscript(self, bootscript_pa: int) -> int:
         res = BOOTSCRIPT_OK
         self.logger.log(f"[*] Checking S3 boot-script at 0x{bootscript_pa:016X}")
 
@@ -192,10 +178,7 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
self.logger.log_bad('Entry-points of Dispatch opcodes in S3 boot-script are not in protected memory')
         return res

 
-
-

-[docs]
-    def check_s3_bootscripts(self, bsaddress=None) -> int:
+
[docs]    def check_s3_bootscripts(self, bsaddress=None) -> int:
         res = 0
         scriptInsideSMRAM = False
 
@@ -241,10 +224,7 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
return status

 
-
-

-[docs]
-    def run(self, module_argv: List[str]) -> int:
+
[docs]    def run(self, module_argv: List[str]) -> int:
         self.logger.start_test("S3 Resume Boot-Script Protections")
 
         if len(module_argv) > 2:
@@ -272,9 +252,7 @@ 
Source code for chipsec.modules.common.uefi.s3bootscript
raise
             self.res = ModuleResult.ERROR
 
-        return self.rc_res.getReturnCode(self.res)

-

-
+        return self.rc_res.getReturnCode(self.res)

 

 
             

@@ -334,7 +312,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -354,8 +332,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/cpu/sinkhole.html b/_modules/chipsec/modules/tools/cpu/sinkhole.html
deleted file mode 100644
index 01b11805..00000000
--- a/_modules/chipsec/modules/tools/cpu/sinkhole.html
+++ /dev/null
@@ -1,268 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.cpu.sinkhole — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.cpu.sinkhole
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-"""
-This module checks if CPU is affected by 'The SMM memory sinkhole' vulnerability
-
-References:
-    - `Memory Sinkhole presentation by Christopher Domas <https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf>`_
-    - `Memory Sinkhole whitepaper <https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf>`_
-
-Usage:
-    ``chipsec_main -m tools.cpu.sinkhole``
-
-Examples:
-    >>> chipsec_main.py -m tools.cpu.sinkhole
-
-Registers used:
-    - IA32_APIC_BASE.APICBase
-    - IA32_SMRR_PHYSBASE.PhysBase
-    - IA32_SMRR_PHYSMASK
-
-.. note::
-    - Supported OS: Windows or Linux
-
-.. warning::
-    - The system may hang when running this test.
-    - In that case, the mitigation to this issue is likely working but we may not be handling the exception generated.
-
-"""
-
-from chipsec.module_common import BaseModule, ModuleResult, MTAG_SMM
-
-
-TAGS = [MTAG_SMM]
-
-
-

-[docs]
-class sinkhole(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x230312a, 'https://chipsec.github.io/modules/chipsec.modules.tools.cpu.sinkhole.html')
-
-

-[docs]
-    def is_supported(self):
-        if not (self.cs.os_helper.is_windows() or self.cs.os_helper.is_linux()):
-            self.logger.log_important('Unsupported OS found.  Skipping module.')
-            self.logger.log_important('Supported OS: Windows or Linux')
-            self.rc_res.setStatusBit(self.rc_res.status.NOT_APPLICABLE)
-            self.res = self.rc_res.getReturnCode(ModuleResult.NOTAPPLICABLE)
-            return False
-        elif not self.cs.is_register_defined('IA32_APIC_BASE') or \
-                not self.cs.is_register_defined('IA32_SMRR_PHYSBASE') or \
-                not self.cs.is_register_defined('IA32_SMRR_PHYSMASK'):
-            self.logger.log_error("Couldn't find definition of required configuration registers.")
-            self.rc_res.setStatusBit(self.rc_res.status.CONFIGURATION)
-            self.res =self.rc_res.getReturnCode(ModuleResult.ERROR)
-            return False
-        else:
-            return True

-
-
-

-[docs]
-    def check_LAPIC_SMRR_overlap(self):
-        smrr_physbase_msr = self.cs.read_register('IA32_SMRR_PHYSBASE', 0)
-        apic_base_msr = self.cs.read_register('IA32_APIC_BASE', 0)
-        self.cs.print_register('IA32_APIC_BASE', apic_base_msr)
-        self.cs.print_register('IA32_SMRR_PHYSBASE', smrr_physbase_msr)
-
-        smrrbase = self.cs.get_register_field('IA32_SMRR_PHYSBASE', smrr_physbase_msr, 'PhysBase')
-        smrr_base = self.cs.get_register_field('IA32_SMRR_PHYSBASE', smrr_physbase_msr, 'PhysBase', True)
-        apic_base = self.cs.get_register_field('IA32_APIC_BASE', apic_base_msr, 'APICBase', True)
-
-        self.logger.log(f'[*] Local APIC Base: 0x{apic_base:016X}')
-        self.logger.log(f'[*] SMRR Base      : 0x{smrr_base:016X}')
-
-        self.logger.log("[*] Attempting to overlap Local APIC page with SMRR region")
-        self.logger.log(f'   Writing 0x{smrrbase:X} to IA32_APIC_BASE[APICBase]..')
-        self.logger.log_important("NOTE: The system may hang or process may crash when running this test.")
-        self.logger.log("      In that case, the mitigation to this issue is likely working but we may not be handling the exception generated.")
-
-        res = self.cs.write_register_field('IA32_APIC_BASE', 'APICBase', smrrbase, preserve_field_position=False, cpu_thread=0)
-
-        if res is None:
-            self.logger.log_important("Error encountered when attempting to modify IA32_APIC_BASE")
-
-        apic_base_msr_new = self.cs.read_register('IA32_APIC_BASE', 0)
-        self.logger.log(f'[*] New IA32_APIC_BASE: 0x{apic_base_msr_new:016X}')
-
-        if apic_base_msr_new == apic_base_msr:
-            self.logger.log_good("Could not modify IA32_APIC_BASE to overlap SMRR")
-            self.logger.log_passed("CPU does not seem to have SMM memory sinkhole vulnerability")
-            self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-            res = ModuleResult.PASSED
-        else:
-            self.logger.log_bad("Could modify IA32_APIC_BASE to overlap SMRR")
-            self.cs.write_register('IA32_APIC_BASE', apic_base_msr, 0)
-            self.logger.log(f'[*] Restored original value 0x{apic_base_msr:016X}')
-            self.logger.log_failed("CPU is susceptible to SMM memory sinkhole vulnerability.  Verify that SMRR is programmed correctly.")
-            self.rc_res.setStatusBit(self.rc_res.status.PROTECTION)
-            res = ModuleResult.FAILED
-
-        return self.rc_res.getReturnCode(res)

-
-
-    # --------------------------------------------------------------------------
-    # run( module_argv )
-    # Required function: run here all tests from this module
-    # --------------------------------------------------------------------------
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("x86 SMM Memory Sinkhole")
-
-        if self.cs.cpu.check_SMRR_supported():
-            self.logger.log_good("SMRR range protection is supported")
-            self.res = self.check_LAPIC_SMRR_overlap()
-        else:
-            self.logger.log_important("CPU does not support SMRR range protection of SMRAM.  Skipping module.")
-            self.rc_res.setStatusBit(self.rc_res.status.NOT_APPLICABLE)
-            self.res = self.rc_res.getReturnCode(ModuleResult.NOTAPPLICABLE)
-        
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/generate_test_id.html b/_modules/chipsec/modules/tools/generate_test_id.html
deleted file mode 100644
index a3e2f204..00000000
--- a/_modules/chipsec/modules/tools/generate_test_id.html
+++ /dev/null
@@ -1,204 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.generate_test_id — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.generate_test_id
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2023, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-"""
-Generate a test ID using hashlib from the test's file name (no file extension). 
-Hash is truncated to 28 bits.
-
-Usage:
-    ``chipsec_main -m common.tools.generate_test_id -a <test name>``
-
-Examples:
-    >>> chipsec_main.py -m common.tools.generate_test_id -a remap
-    >>> chipsec_main.py -m common.tools.generate_test_id -a s3bootscript
-    >>> chipsec_main.py -m common.tools.generate_test_id -a bios_ts
-"""
-
-from chipsec.module_common import BaseModule, ModuleResult
-from typing import List
-import hashlib
-
-

-[docs]
-class generate_test_id(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0xd711589, 'https://chipsec.github.io/modules/chipsec.modules.tools.generate_test_id.html')
-
-

-[docs]
-    def usage(self):
-        self.logger.log(__doc__.replace('`', ''))
-        return

-
-    
-

-[docs]
-    def is_supported(self) -> bool:
-        return True

-
-
-

-[docs]
-    def generate_id(self, test_name: str) -> int:
-        return hashlib.sha256(test_name.encode('ascii')).hexdigest()[:7]

-
-
-

-[docs]
-    def run(self, module_argv: List[str]) -> int:
-        self.logger.start_test("Generate test ID")
-
-        if len(module_argv) == 1:
-            module_name = module_argv[0]
-            self.logger.log_good(f'Test ID for {module_name} is 0x{self.generate_id(module_name)}\n')
-            self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-            self.res = self.rc_res.getReturnCode(ModuleResult.INFORMATION)
-        else:
-            self.usage()
-            self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_OPTION)
-            self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/secureboot/te.html b/_modules/chipsec/modules/tools/secureboot/te.html
deleted file mode 100644
index 6c603e21..00000000
--- a/_modules/chipsec/modules/tools/secureboot/te.html
+++ /dev/null
@@ -1,725 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.secureboot.te — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.secureboot.te
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2022, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Tool to test for 'TE Header' vulnerability in Secure Boot implementations as described in
-`All Your Boot Are Belong To Us <http://www.c7zero.info/stuff/AllYourBoot_csw14-intel-final.pdf>`_
-
-Usage:
-  ``chipsec_main.py -m tools.secureboot.te [-a <mode>,<cfg_file>,<efi_file>]``
-      - ``<mode>``
-
-          * ``generate_te``     (default) convert PE EFI binary ``<efi_file>`` to TE binary
-          * ``replace_bootloader``  replace bootloader files listed in ``<cfg_file>`` on ESP with modified ``<efi_file>``
-          * ``restore_bootloader``  restore original bootloader files from ``.bak`` files
-
-      - ``<cfg_file>``  path to config file listing paths to bootloader files to replace
-      - ``<efi_file>``  path to EFI binary to convert to TE binary. If no file path is provided, the tool will look for Shell.efi
-
-Examples:
-
-Convert Shell.efi PE/COFF EFI executable to TE executable:
-
-  ``chipsec_main.py -m tools.secureboot.te -a generate_te,Shell.efi``
-
-Replace bootloaders listed in te.cfg file with TE version of Shell.efi executable:
-
-  ``chipsec_main.py -m tools.secureboot.te -a replace_bootloader,te.cfg,Shell.efi``
-
-Restore bootloaders listed in te.cfg file:
-
-  ``chipsec_main.py -m tools.secureboot.te -a restore_bootloader,te.cfg``
-
-"""
-
-import os
-import shutil
-import struct
-import sys
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.logger import logger
-
-
-DEFAULT_PE_FILE_PATH = "chipsec/modules/tools/secureboot/Shell.efi"
-DEFAULT_CONFIG_FILE_PATH = 'chipsec/modules/tools/secureboot/te.cfg'
-
-# typedef struct _IMAGE_DOS_HEADER
-# {
-#      WORD e_magic;
-#      WORD e_cblp;
-#      WORD e_cp;
-#      WORD e_crlc;
-#      WORD e_cparhdr;
-#      WORD e_minalloc;
-#      WORD e_maxalloc;
-#      WORD e_ss;
-#      WORD e_sp;
-#      WORD e_csum;
-#      WORD e_ip;
-#      WORD e_cs;
-#      WORD e_lfarlc;
-#      WORD e_ovno;
-#      WORD e_res[4];
-#      WORD e_oemid;
-#      WORD e_oeminfo;
-#      WORD e_res2[10];
-#      LONG e_lfanew;
-# } IMAGE_DOS_HEADER, *PIMAGE_DOS_HEADER;
-
-IMAGE_DOS_HEADER = "<14H4HHH10Hi"
-IMAGE_DOS_HEADER_size = struct.calcsize(IMAGE_DOS_HEADER)
-E_MAGIC = 0x5A4D
-E_MAGIC_STR = "MZ"
-
-# typedef struct _IMAGE_DATA_DIRECTORY
-# {
-#      ULONG VirtualAddress;
-#      ULONG Size;
-# } IMAGE_DATA_DIRECTORY, *PIMAGE_DATA_DIRECTORY;
-
-IMAGE_DATA_DIRECTORY = "<II"
-IMAGE_DATA_DIRECTORY_size = struct.calcsize(IMAGE_DATA_DIRECTORY)
-
-IMAGE_NUMBEROF_DIRECTORY_ENTRIES = 16
-
-# typedef struct _IMAGE_OPTIONAL_HEADER
-# {
-#      WORD Magic;
-#      UCHAR MajorLinkerVersion;
-#      UCHAR MinorLinkerVersion;
-#      ULONG SizeOfCode;
-#      ULONG SizeOfInitializedData;
-#      ULONG SizeOfUninitializedData;
-#      ULONG AddressOfEntryPoint;
-#      ULONG BaseOfCode;
-#      ULONG BaseOfData;
-#      ULONG ImageBase;
-#      ULONG SectionAlignment;
-#      ULONG FileAlignment;
-#      WORD MajorOperatingSystemVersion;
-#      WORD MinorOperatingSystemVersion;
-#      WORD MajorImageVersion;
-#      WORD MinorImageVersion;
-#      WORD MajorSubsystemVersion;
-#      WORD MinorSubsystemVersion;
-#      ULONG Win32VersionValue;
-#      ULONG SizeOfImage;
-#      ULONG SizeOfHeaders;
-#      ULONG CheckSum;
-#      WORD Subsystem;
-#      WORD DllCharacteristics;
-#      ULONG SizeOfStackReserve;
-#      ULONG SizeOfStackCommit;
-#      ULONG SizeOfHeapReserve;
-#      ULONG SizeOfHeapCommit;
-#      ULONG LoaderFlags;
-#      ULONG NumberOfRvaAndSizes;
-#      IMAGE_DATA_DIRECTORY DataDirectory[16];
-# } IMAGE_OPTIONAL_HEADER, *PIMAGE_OPTIONAL_HEADER;
-
-IMAGE_OPTIONAL_HEADER = "<HBB9I6H4I2H6I"
-IMAGE_OPTIONAL_HEADER_size = struct.calcsize(IMAGE_OPTIONAL_HEADER)
-IMAGE_NT_OPTIONAL_HDR32_MAGIC = 0x10b
-
-# typedef struct {
-#   //
-#   // Standard fields.
-#   //
-#   UINT16                    Magic;
-#   UINT8                     MajorLinkerVersion;
-#   UINT8                     MinorLinkerVersion;
-#   UINT32                    SizeOfCode;
-#   UINT32                    SizeOfInitializedData;
-#   UINT32                    SizeOfUninitializedData;
-#   UINT32                    AddressOfEntryPoint;
-#   UINT32                    BaseOfCode;
-#   //
-#   // NT additional fields.
-#   //
-#   UINT64                    ImageBase;
-#   UINT32                    SectionAlignment;
-#   UINT32                    FileAlignment;
-#   UINT16                    MajorOperatingSystemVersion;
-#   UINT16                    MinorOperatingSystemVersion;
-#   UINT16                    MajorImageVersion;
-#   UINT16                    MinorImageVersion;
-#   UINT16                    MajorSubsystemVersion;
-#   UINT16                    MinorSubsystemVersion;
-#   UINT32                    Win32VersionValue;
-#   UINT32                    SizeOfImage;
-#   UINT32                    SizeOfHeaders;
-#   UINT32                    CheckSum;
-#   UINT16                    Subsystem;
-#   UINT16                    DllCharacteristics;
-#   UINT64                    SizeOfStackReserve;
-#   UINT64                    SizeOfStackCommit;
-#   UINT64                    SizeOfHeapReserve;
-#   UINT64                    SizeOfHeapCommit;
-#   UINT32                    LoaderFlags;
-#   UINT32                    NumberOfRvaAndSizes;
-#   EFI_IMAGE_DATA_DIRECTORY  DataDirectory[EFI_IMAGE_NUMBER_OF_DIRECTORY_ENTRIES];
-# } EFI_IMAGE_OPTIONAL_HEADER64;
-
-IMAGE_OPTIONAL_HEADER64 = "<HBBIIIIIQIIHHHHHHIIIIHHQQQQII"
-IMAGE_OPTIONAL_HEADER64_size = struct.calcsize(IMAGE_OPTIONAL_HEADER64)
-IMAGE_NT_OPTIONAL_HDR64_MAGIC = 0x20b
-
-# typedef struct _IMAGE_FILE_HEADER
-# {
-#      WORD Machine;
-#      WORD NumberOfSections;
-#      ULONG TimeDateStamp;
-#      ULONG PointerToSymbolTable;
-#      ULONG NumberOfSymbols;
-#      WORD SizeOfOptionalHeader;
-#      WORD Characteristics;
-# } IMAGE_FILE_HEADER, *PIMAGE_FILE_HEADER;
-
-IMAGE_FILE_HEADER = "<2H3I2H"
-IMAGE_FILE_HEADER_size = struct.calcsize(IMAGE_FILE_HEADER)
-
-# typedef struct _IMAGE_NT_HEADERS
-# {
-#      ULONG Signature;
-#      IMAGE_FILE_HEADER FileHeader;
-#      IMAGE_OPTIONAL_HEADER OptionalHeader;
-# } IMAGE_NT_HEADERS, *PIMAGE_NT_HEADERS;
-
-IMAGE_NT_SIGNATURE = 0x00004550
-IMAGE_NT_HEADERS_size = (4 + IMAGE_FILE_HEADER_size + IMAGE_OPTIONAL_HEADER_size + IMAGE_NUMBEROF_DIRECTORY_ENTRIES * IMAGE_DATA_DIRECTORY_size)
-
-# typedef struct _IMAGE_SECTION_HEADER
-# {
-#      UCHAR Name[8];
-#      ULONG Misc;
-#      ULONG VirtualAddress;
-#      ULONG SizeOfRawData;
-#      ULONG PointerToRawData;
-#      ULONG PointerToRelocations;
-#      ULONG PointerToLinenumbers;
-#      WORD NumberOfRelocations;
-#      WORD NumberOfLinenumbers;
-#      ULONG Characteristics;
-# } IMAGE_SECTION_HEADER, *PIMAGE_SECTION_HEADER;
-
-IMAGE_SECTION_HEADER = "<8s6I2HI"
-IMAGE_SECTION_HEADER_size = struct.calcsize(IMAGE_SECTION_HEADER)
-
-# PE executable structure
-#
-#   MS-DOS header
-#     ...
-#     e_lfanew -------------------+
-#                                 |
-#                                 |
-#   IMAGE_NT_HEADERS Header  <----+
-#    ...
-#   SECTION TABLE
-#    ...
-# TE header
-#
-# typedef struct {
-#   UINT16                    Signature;            // signature for TE format = "VZ"
-#   UINT16                    Machine;              // from the original file header
-#   UINT8                     NumberOfSections;     // from the original file header
-#   UINT8                     Subsystem;            // from original optional header
-#   UINT16                    StrippedSize;         // how many bytes we removed from the header
-#   UINT32                    AddressOfEntryPoint;  // offset to entry point -- from original optional header
-#   UINT32                    BaseOfCode;           // from original image -- required for ITP debug
-#   UINT64                    ImageBase;            // from original file header
-#   IMAGE_DATA_DIRECTORY      DataDirectory[2];     // only base relocation and debug directory
-# } EFI_TE_IMAGE_HEADER;
-
-EFI_TE_IMAGE_HEADER = "<HHBBHIIQ"
-EFI_TE_IMAGE_HEADER_SIGNATURE = 0x5A56
-
-EFI_IMAGE_DIRECTORY_ENTRY_EXPORT = 0
-EFI_IMAGE_DIRECTORY_ENTRY_IMPORT = 1
-EFI_IMAGE_DIRECTORY_ENTRY_RESOURCE = 2
-EFI_IMAGE_DIRECTORY_ENTRY_EXCEPTION = 3
-EFI_IMAGE_DIRECTORY_ENTRY_SECURITY = 4
-EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC = 5
-EFI_IMAGE_DIRECTORY_ENTRY_DEBUG = 6
-EFI_IMAGE_DIRECTORY_ENTRY_COPYRIGHT = 7
-EFI_IMAGE_DIRECTORY_ENTRY_GLOBALPTR = 8
-EFI_IMAGE_DIRECTORY_ENTRY_TLS = 9
-EFI_IMAGE_DIRECTORY_ENTRY_LOAD_CONFIG = 10
-
-EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC = 0
-EFI_TE_IMAGE_DIRECTORY_ENTRY_DEBUG = 1
-
-
-

-[docs]
-def IsValidPEHeader(data):
-    size = len(data)
-    if size < IMAGE_DOS_HEADER_size:
-        return False
-    signature, = struct.unpack("<H", data[:2])
-    if signature != E_MAGIC:
-        return False
-    e_lfanew, = struct.unpack("<I", data[IMAGE_DOS_HEADER_size - 4:IMAGE_DOS_HEADER_size])
-    if e_lfanew >= size:
-        return False
-    if (size - e_lfanew) < IMAGE_NT_HEADERS_size:
-        return False
-    pe_signature, = struct.unpack("<I", data[e_lfanew:e_lfanew + 4])
-    if pe_signature != IMAGE_NT_SIGNATURE:
-        return False
-    return True

-
-
-
-

-[docs]
-def replace_header(data):
-    if not IsValidPEHeader(data):
-        return None
-    size = len(data)
-    e_lfanew, = struct.unpack("<I", data[IMAGE_DOS_HEADER_size - 4:IMAGE_DOS_HEADER_size])
-    #                          TimeDateStamp, PointerToSymbolTable, NumberOfSymbols, SizeOfOptionalHeader, Characteristics
-    Machine, NumberOfSections, u1, u2, u3, SizeOfOptionalHeader, u5 \
-        = struct.unpack(IMAGE_FILE_HEADER, data[e_lfanew + 4:e_lfanew + 4 + IMAGE_FILE_HEADER_size])
-    StrippedSize = e_lfanew + 4 + IMAGE_FILE_HEADER_size + SizeOfOptionalHeader
-    if StrippedSize > size:
-        return None
-    if StrippedSize & ~0xffff:
-        return None
-    dof = e_lfanew + 4 + IMAGE_FILE_HEADER_size
-    Magic, = struct.unpack("<H", data[dof:dof + 2])
-    if Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC:
-        Magic, MajorLinkerVersion, MinorLinkerVersion, SizeOfCode, SizeOfInitializedData, \
-            SizeOfUninitializedData, AddressOfEntryPoint, BaseOfCode, BaseOfData, ImageBase,  \
-            SectionAlignment, FileAlignment, MajorOperatingSystemVersion, MinorOperatingSystemVersion, \
-            MajorImageVersion, MinorImageVersion, MajorSubsystemVersion, MinorSubsystemVersion, \
-            Win32VersionValue, SizeOfImage, SizeOfHeaders, CheckSum, Subsystem, DllCharacteristics, \
-            SizeOfStackReserve, SizeOfStackCommit, SizeOfHeapReserve, SizeOfHeapCommit, LoaderFlags, \
-            NumberOfRvaAndSizes = struct.unpack(IMAGE_OPTIONAL_HEADER, data[dof:dof + IMAGE_OPTIONAL_HEADER_size])
-        dof = dof + IMAGE_OPTIONAL_HEADER_size
-    elif Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC:
-        Magic, MajorLinkerVersion, MinorLinkerVersion, SizeOfCode, SizeOfInitializedData, \
-            SizeOfUninitializedData, AddressOfEntryPoint, BaseOfCode, ImageBase, SectionAlignment, \
-            FileAlignment, MajorOperatingSystemVersion, MinorOperatingSystemVersion, MajorImageVersion, \
-            MinorImageVersion, MajorSubsystemVersion, MinorSubsystemVersion, Win32VersionValue, \
-            SizeOfImage, SizeOfHeaders, CheckSum, Subsystem, DllCharacteristics, SizeOfStackReserve, \
-            SizeOfStackCommit, SizeOfHeapReserve, SizeOfHeapCommit, LoaderFlags, NumberOfRvaAndSizes \
-            = struct.unpack(IMAGE_OPTIONAL_HEADER64, data[dof:dof + IMAGE_OPTIONAL_HEADER64_size])
-        dof = dof + IMAGE_OPTIONAL_HEADER64_size
-    else:
-        return None
-    if NumberOfSections & ~0xFF:
-        return None
-    if Subsystem & ~0xFF:
-        return None
-
-    basereloc_off = dof + EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC * IMAGE_DATA_DIRECTORY_size
-    debug_off = dof + EFI_IMAGE_DIRECTORY_ENTRY_DEBUG * IMAGE_DATA_DIRECTORY_size
-    BASERELOC = "\x00\x00\x00\x00\x00\x00\x00\x00"
-    DEBUG = "\x00\x00\x00\x00\x00\x00\x00\x00"
-    if NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC:
-        BASERELOC = data[basereloc_off:basereloc_off + IMAGE_DATA_DIRECTORY_size]
-    if NumberOfRvaAndSizes > EFI_IMAGE_DIRECTORY_ENTRY_DEBUG:
-        DEBUG = data[debug_off:debug_off + IMAGE_DATA_DIRECTORY_size]
-    te_header = struct.pack(EFI_TE_IMAGE_HEADER,
-                            EFI_TE_IMAGE_HEADER_SIGNATURE, Machine, NumberOfSections, Subsystem, StrippedSize, AddressOfEntryPoint, BaseOfCode, ImageBase)
-    te_data = te_header + BASERELOC + DEBUG + data[StrippedSize:]
-    return te_data

-
-
-
-

-[docs]
-def produce_te(fname, outfname):
-    data = ''
-    with open(fname, 'rb') as f:
-        data = f.read()
-    te_data = replace_header(data)
-    if te_data is None:
-        return 0
-    with open(outfname, 'wb') as fte:
-        fte.write(te_data)
-    return 1

-
-
-
-

-[docs]
-def replace_efi_binary(orig_efi_binary, new_efi_binary):
-    logger().log(f'[*] Replacing EFI binary \'{orig_efi_binary}\'..')
-    te_binary = new_efi_binary + '.te'
-    if not os.path.exists(te_binary):
-        produce_te(new_efi_binary, te_binary)
-    # back up original binary
-    backup = orig_efi_binary + '.bak'
-    if not os.path.exists(backup):
-        os.rename(orig_efi_binary, backup)
-    try:
-        shutil.copy(te_binary, orig_efi_binary)
-    except OSError as err:
-        logger().log_error(f'Cannot replace binary ({err})')
-        return False
-    return True

-
-
-
-

-[docs]
-def umount(drive):
-    import subprocess
-    if os.path.exists(drive):
-        res = subprocess.call(["mountvol.exe", drive, "/D"])
-        if res != 0:
-            logger().log_warning(f'Cannot unmount EFI System partition: {res:d}')

-
-
-
-

-[docs]
-def get_efi_mount():
-    import subprocess
-    for l in range(ord('z'), ord('a'), -1):
-        if not os.path.exists('%c:\\' % l):
-            res = subprocess.call(["mountvol.exe", "%c:\\" % l, "/S"])
-            if res != 0:
-                logger().log_error(f'Cannot mount EFI System partition (status = {res:d})')
-                return None
-            return '%c:\\' % l
-    logger().log_error("Cannot mount EFI System partition. No drive letters to use.")
-    return None

-
-
-
-

-[docs]
-def get_bootloader_paths(cfg_file):
-    bootloader_paths = []
-    with open(cfg_file, 'r') as fcfg:
-        logger().log(f'[*] reading paths from \'{cfg_file}\'..')
-        for line in fcfg:
-            bl_path = line.rstrip()
-            if bl_path is not None:
-                logger().log(f'    adding path \'{bl_path}\'..')
-                bootloader_paths.append(bl_path)
-    return bootloader_paths

-
-
-
-

-[docs]
-def replace_bootloader(bootloader_paths, new_bootloader_file, do_mount=True):
-    logger().log("[*] Replacing bootloaders on EFI System Partition (ESP)...")
-    dsk = get_efi_mount() if do_mount else ''
-    if dsk is None:
-        return False
-    try:
-        for pth in bootloader_paths:
-            bootloader_path = os.path.join(dsk, pth)
-            if os.path.exists(bootloader_path):
-                replace_efi_binary(bootloader_path, new_bootloader_file)
-            else:
-                logger().log_warning(f'Bootloader {bootloader_path} does not exist on ESP')
-    finally:
-        if do_mount:
-            umount(dsk)
-    logger().log("[*] You will need to reboot the system to see the changes")
-    return True

-
-
-
-

-[docs]
-def restore_efi_binary(orig_efi_binary):
-    logger().log(f'[*] Restoring {orig_efi_binary}..')
-    backup = orig_efi_binary + ".bak"
-    if not os.path.exists(backup):
-        logger().log_error(f'Cannot restore original binary: \'{backup}\' not found')
-        return False
-    try:
-        if os.path.exists(orig_efi_binary):
-            os.remove(orig_efi_binary)
-        os.rename(backup, orig_efi_binary)
-    except OSError as err:
-        logger().log_error(f'Cannot restore original binary ({err})')
-        return False
-    return True

-
-
-
-

-[docs]
-def restore_bootloader(bootloader_paths, do_mount=True):
-    logger().log("[*] Restoring bootloaders on EFI System Partition (ESP)...")
-    dsk = get_efi_mount() if do_mount else ''
-    if dsk is None:
-        return False
-    for pth in bootloader_paths:
-        bootloader_path = os.path.join(dsk, pth)
-        if os.path.exists(bootloader_path):
-            restore_efi_binary(bootloader_path)
-    if do_mount:
-        umount(dsk)
-    logger().log("[*] You will need to reboot the system to see the changes")
-    return True

-
-
-
-

-[docs]
-def confirm():
-    logger().log_important("***************************************************************************************")
-    logger().log_important("*")
-    logger().log_important("* RUNNING THIS TOOL MAY RESULT IN UNBOOTABLE OS!")
-    logger().log_important("* USE IT FOR TESTING PURPOSES ON TEST SYSTEMS ONLY")
-    logger().log_important("*")
-    logger().log_important("* The tool converts PE/COFF EFI executables to TE EFI executables.")
-    logger().log_important("* The tool can also automatically replace files (boot loaders)")
-    logger().log_important("* listed in the configuration file with the generated TE executable.")
-    logger().log_important("*")
-    logger().log_important("* If after reboot, TE executable runs then the firmware doesn't properly")
-    logger().log_important("* enforce Secure Boot checks on TE EFI executables")
-    logger().log_important("*")
-    logger().log_important("* If TE executable doesn't run then the firmware correctly blocked it.")
-    logger().log_important("* To restore OS boot loader in this case you may use one of the following:")
-    logger().log_important("* - Disable Secure Boot in BIOS, boot to external drive (e.g. Linux or UEFI shell)")
-    logger().log_important("*   then restore original boot loader executables from .bak files")
-    logger().log_important("* - On Windows, use recovery mode which should automatically restore correct executables")
-    logger().log_important("*")
-    logger().log_important("***************************************************************************************")
-    s = input("Type 'yes' to continue running the tool > ")
-    if s.lower() not in ['yes', 'y']:
-        sys.exit(0)

-
-
-
-

-[docs]
-def usage():
-    logger().log('Usage:\n' +
-                 'chipsec_main.py -m tools.secureboot.te [-a <mode>,<cfg_file>,<efi_file>]\n' +
-                 '    <mode>\n' +
-                 '      generate_te        - (default) convert PE EFI binary <efi_file> to TE binary\n' +
-                 '      replace_bootloader - replace bootloader files listed in <cfg_file> on ESP with modified <efi_file>\n' +
-                 '      restore_bootloader - restore original bootloader files from .bak files\n' +
-                 '    <cfg_file>           - path to config file listing paths to bootloader files to replace\n' +
-                 '    <efi_file>           - path to EFI binary to convert to TE binary\n' +
-                 '                           If no file path is provided, the tool will look for Shell.efi\n')

-
-
-
-

-[docs]
-class te(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x2d6c9a9, 'https://chipsec.github.io/modules/chipsec.modules.tools.secureboot.te.html')
-
-

-[docs]
-    def is_supported(self):
-        #win8 = self.cs.helper.is_win8_or_greater()
-        efi_mode = self.cs.helper.EFI_supported()
-        if not efi_mode:
-            self.logger.log_not_applicable("OS did not boot in UEFI mode")
-        return efi_mode

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("'TE Header' Secure Boot Bypass Test")
-        usage()
-
-        sts = False
-        do_mount = True
-        file_path = DEFAULT_PE_FILE_PATH
-        te_cfg = DEFAULT_CONFIG_FILE_PATH
-        mode = module_argv[0] if len(module_argv) > 0 else 'generate_te'
-
-        if 'generate_te' == mode:
-            if len(module_argv) > 1:
-                file_path = module_argv[1]
-            if not os.path.exists(file_path):
-                self.logger.log_error(f'Cannot find file \'{file_path}\'')
-                self.rc_res.setStatusBit(self.rc_res.status.ACCESS_RW)
-                return self.rc_res.getReturnCode(ModuleResult.ERROR)
-
-            sts = replace_efi_binary(file_path, file_path)
-
-        elif ('restore_bootloader' == mode) or ('replace_bootloader' == mode):
-            confirm()
-
-            if len(module_argv) > 1:
-                te_cfg = module_argv[1]
-            if not os.path.exists(te_cfg):
-                self.logger.log_error(f'Cannot find file \'{te_cfg}\'')
-                self.rc_res.setStatusBit(self.rc_res.status.ACCESS_RW)
-                return self.rc_res.getReturnCode(ModuleResult.ERROR)
-
-            bootloader_paths = get_bootloader_paths(te_cfg)
-            if len(bootloader_paths) == 0:
-                self.logger.log("[*] no bootloaders to replace. Exit...")
-                self.rc_res.setStatusBit(self.rc_res.status.FEATURE_DISABLED)
-                return self.rc_res.getReturnCode(ModuleResult.WARNING) 
-
-            do_mount = self.cs.os_helper.is_windows()  # @TODO
-            if 'restore_bootloader' == mode:
-                sts = restore_bootloader(bootloader_paths, do_mount)
-            elif 'replace_bootloader' == mode:
-                if len(module_argv) > 2:
-                    file_path = module_argv[2]
-                sts = replace_bootloader(bootloader_paths, file_path, do_mount)
-
-        else:
-            self.logger.log_error(f'Invalid mode: \'{mode}\'')
-
-        if sts:
-            self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-            return self.rc_res.getReturnCode(ModuleResult.PASSED) 
-        else:
-            self.rc_res.setStatusBit(self.rc_res.status.RESTORE)
-            return self.rc_res.getReturnCode(ModuleResult.ERROR)

-

-
-

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-            

-          

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-      

-      
-      

-    

-    
-    
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-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/smm/rogue_mmio_bar.html b/_modules/chipsec/modules/tools/smm/rogue_mmio_bar.html
deleted file mode 100644
index c72f3829..00000000
--- a/_modules/chipsec/modules/tools/smm/rogue_mmio_bar.html
+++ /dev/null
@@ -1,352 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.smm.rogue_mmio_bar — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.smm.rogue_mmio_bar
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2017-2021, Intel Security
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# Authors:
-#   Yuriy Bulygin
-#   Alex Bazhaniuk
-#
-
-
-"""
-Experimental module that may help checking SMM firmware for MMIO BAR hijacking
-vulnerabilities described in the following presentation:
-
-`BARing the System: New vulnerabilities in Coreboot & UEFI based systems <https://web.archive.org/web/20170702042016/http://www.intelsecurity.com/advanced-threat-research/content/data/REConBrussels2017_BARing_the_system.pdf>`_ by Intel Advanced Threat Research team at RECon Brussels 2017
-
-Usage:
-    ``chipsec_main -m tools.smm.rogue_mmio_bar [-a <smi_start:smi_end>,<b:d.f>]``
-
-    - ``smi_start:smi_end``: range of SMI codes (written to IO port 0xB2)
-    - ``b:d.f``: PCIe bus/device/function in b:d.f format (in hex)
-
-Example:
-    >>> chipsec_main.py -m tools.smm.rogue_mmio_bar -a 0x00:0x80
-    >>> chipsec_main.py -m tools.smm.rogue_mmio_bar -a 0x00:0xFF,0:1C.0
-
-.. NOTE::
-    Look for 'changes found' messages for items that should be further investigated.
-
-.. WARNING::
-    When running this test, system may freeze, reboot, etc. This is not unexpected behavior and not generally considered a failure.
-
-"""
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.defines import BOUNDARY_4GB
-from chipsec.file import write_file
-from chipsec.hal.pci import PCI_HDR_BAR_STEP, PCI_HDR_BAR_BASE_MASK_MMIO64, PCI_HDR_BAR_CFGBITS_MASK
-from chipsec.hal.interrupts import Interrupts
-
-#################################################################
-# Testing configuration
-#################################################################
-
-FLUSH_OUTPUT_AFTER_SMI = False
-
-_FILL_VALUE_QWORD = 0x0000000000000000
-_MEM_FILL_VALUE = b"\xFF"
-MAX_MMIO_RANGE_SIZE = 0x10000  # 0x400000
-
-SMI_CODE_LIMIT = 0x0
-SMI_DATA_LIMIT = 0xF
-SMI_FUNC_LIMIT = 0xF
-
-
-

-[docs]
-def DIFF(s, t, sz):
-    return [pos for pos in range(sz) if s[pos] != t[pos]]

-
-
-
-

-[docs]
-class rogue_mmio_bar(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self._interrupts = Interrupts(self.cs)
-        self.rc_res = ModuleResult(0x293f9e8, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.rogue_mmio_bar.html')
-
-        # SMI code to be written to I/O port 0xB2
-        self.smic_start = 0x00
-        self.smic_end = SMI_CODE_LIMIT
-        # SMI data to be written to I/O port 0xB3
-        self.smid_start = 0x00
-        self.smid_end = SMI_DATA_LIMIT
-        # SMI handler "function" often supplied in ECX register
-        self.smif_start = 0x00
-        self.smif_end = SMI_FUNC_LIMIT
-        # SMM communication buffer often supplied in EBX register
-        self.comm = 0x00
-
-        self.reloc_mmio = None
-
-

-[docs]
-    def smi_mmio_range_fuzz(self, thread_id, b, d, f, bar_off, is64bit, bar, new_bar, base, size):
-
-        # copy all registers from MMIO range to new location in memory
-        # we do that once rather than before every SMI since we return after first change detected
-        self.logger.log(f'[*] copying BAR 0x{base:X} > 0x{self.reloc_mmio:X}')
-        orig_mmio = self.copy_bar(base, self.reloc_mmio, size)
-        if self.logger.VERBOSE:
-            self.cs.mmio.dump_MMIO(base, size)
-            write_file('mmio_mem.orig', orig_mmio)
-
-        for smi_code in range(self.smic_start, self.smic_end + 1):
-            for smi_data in range(self.smid_start, self.smid_end + 1):
-                for ecx in range(self.smif_start, self.smif_end + 1):
-                    self.logger.log(f'> SMI# {smi_code:02X}: data {smi_data:02X}, func (ECX) {ecx:X}')
-                    if FLUSH_OUTPUT_AFTER_SMI:
-                        self.logger.flush()
-
-                    # point MMIO range to new location (relocate MMIO range)
-                    self.logger.log(f'  relocating BAR 0x{bar:X}')
-                    if not self.modify_bar(b, d, f, bar_off, is64bit, bar, new_bar):
-                        continue
-
-                    # generate SW SMI
-                    self._interrupts.send_SW_SMI(thread_id, smi_code, smi_data, _FILL_VALUE_QWORD, self.comm, ecx, _FILL_VALUE_QWORD, _FILL_VALUE_QWORD, _FILL_VALUE_QWORD)
-
-                    # restore original location of MMIO range
-                    self.restore_bar(b, d, f, bar_off, is64bit, bar)
-                    self.logger.log(f'  restored BAR with 0x{bar:X}')
-
-                    # check the contents at the address range used to relocate MMIO BAR
-                    buf = self.cs.mem.read_physical_mem(self.reloc_mmio, size)
-                    diff = DIFF(orig_mmio, buf, size)
-                    self.logger.log("  checking relocated MMIO")
-                    if len(diff) > 0:
-                        self.logger.log_important(f'changes found at 0x{self.reloc_mmio:X} +{diff}')
-                        if self.logger.VERBOSE:
-                            write_file('mmio_mem.new', buf)
-                        return True
-        return False

-
-
-

-[docs]
-    def copy_bar(self, bar_base, bar_base_mem, size):
-        for off in range(0, size, 4):
-            r = self.cs.mem.read_physical_mem_dword(bar_base + off)
-            self.cs.mem.write_physical_mem_dword(bar_base_mem + off, r)
-        return self.cs.mem.read_physical_mem(bar_base_mem, size)

-
-
-

-[docs]
-    def modify_bar(self, b, d, f, off, is64bit, bar, new_bar):
-        # Modify MMIO BAR address
-        if is64bit:
-            self.cs.pci.write_dword(b, d, f, off + PCI_HDR_BAR_STEP, ((new_bar >> 32) & 0xFFFFFFFF))
-        self.cs.pci.write_dword(b, d, f, off, (new_bar & 0xFFFFFFFF))
-        # Check that the MMIO BAR has been modified correctly. Restore original and skip if not
-        l = self.cs.pci.read_dword(b, d, f, off)
-        if l != (new_bar & 0xFFFFFFFF):
-            self.restore_bar(b, d, f, off, is64bit, bar)
-            self.logger.log(f'  skipping ({l:X} != {new_bar:X})')
-            return False
-        self.logger.log(f'  new BAR: 0x{l:X}')
-        return True

-
-
-

-[docs]
-    def restore_bar(self, b, d, f, off, is64bit, bar):
-        if is64bit:
-            self.cs.pci.write_dword(b, d, f, off + PCI_HDR_BAR_STEP, ((bar >> 32) & 0xFFFFFFFF))
-        self.cs.pci.write_dword(b, d, f, off, (bar & 0xFFFFFFFF))
-        return True

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Experimental tool to help checking for SMM MMIO BAR issues")
-
-        pcie_devices = []
-
-        if len(module_argv) > 0:
-            smic_arr = module_argv[0].split(':')
-            self.smic_start = int(smic_arr[0], 16)
-            self.smic_end = int(smic_arr[1], 16)
-
-        if len(module_argv) > 1:
-            try:
-                b, df = module_argv[1].split(':')
-                d, f = df.split('.')
-                pcie_devices = [(int(b, 16), int(d, 16), int(f, 16), 0, 0)]
-            except:
-                self.logger.log_error("Incorrect b:d.f format\nUsage:\nchipsec_main -m tools.smm.rogue_mmio_bar [-a <smi_start:smi_end>,<b:d.f>]")
-        else:
-            self.logger.log("[*] Discovering PCIe devices..")
-            pcie_devices = self.cs.pci.enumerate_devices()
-
-        self.logger.log("[*] Testing MMIO of PCIe devices:")
-        for (b, d, f, _, _, _) in pcie_devices:
-            self.logger.log(f'    {b:02X}:{d:02X}.{f:X}')
-
-        # allocate a page or SMM communication buffer (often supplied in EBX register)
-        _, self.comm = self.cs.mem.alloc_physical_mem(0x1000, BOUNDARY_4GB - 1)
-        #self.cs.mem.write_physical_mem( self.comm, 0x1000, chr(0)*0x1000 )
-
-        # allocate range in physical memory (should cover all MMIO ranges including GTTMMADR)
-        bsz = 2 * MAX_MMIO_RANGE_SIZE
-        (va, pa) = self.cs.mem.alloc_physical_mem(bsz, BOUNDARY_4GB - 1)
-        self.logger.log(f'[*] Allocated memory range : 0x{pa:016X} (0x{bsz:X} bytes)')
-        self.cs.mem.write_physical_mem(pa, bsz, _MEM_FILL_VALUE * bsz)
-        # align at the MAX_MMIO_RANGE_SIZE boundary within allocated range
-        self.reloc_mmio = pa & (~(MAX_MMIO_RANGE_SIZE - 1))
-        if self.reloc_mmio < pa:
-            self.reloc_mmio += MAX_MMIO_RANGE_SIZE
-        self.logger.log(f'[*] MMIO relocation address: 0x{self.reloc_mmio:016X}\n')
-
-        for (b, d, f, vid, did, _) in pcie_devices:
-            self.logger.log(f'[*] Enumerating device {b:02X}:{d:02X}.{f:X} MMIO BARs..')
-            device_bars = self.cs.pci.get_device_bars(b, d, f, True)
-            for (base, isMMIO, is64bit, bar_off, bar, size) in device_bars:
-                if isMMIO and size <= MAX_MMIO_RANGE_SIZE:
-                    self.logger.flush()
-                    self.logger.log(f'[*] Found MMIO BAR +0x{bar_off:02X} (base 0x{base:016X}, size 0x{size:X})')
-                    new_bar = ((self.reloc_mmio & PCI_HDR_BAR_BASE_MASK_MMIO64) | (bar & PCI_HDR_BAR_CFGBITS_MASK))
-                    if self.smi_mmio_range_fuzz(0, b, d, f, bar_off, is64bit, bar, new_bar, base, size):
-                        self.rc_res.setStatusBit(self.rc_res.status.RESTORE)
-                        return self.rc_res.getReturnCode(ModuleResult.FAILED)
-
-        self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-        return self.rc_res.getReturnCode(ModuleResult.PASSED)

-

-
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-  
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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/smm/smm_ptr.html b/_modules/chipsec/modules/tools/smm/smm_ptr.html
deleted file mode 100644
index ecd226c7..00000000
--- a/_modules/chipsec/modules/tools/smm/smm_ptr.html
+++ /dev/null
@@ -1,719 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.smm.smm_ptr — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
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Source code for chipsec.modules.tools.smm.smm_ptr
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-A tool to test SMI handlers for pointer validation vulnerabilities
-
-Reference:
-    - Presented in CanSecWest 2015:
-        - c7zero.info: `A New Class of Vulnerability in SMI Handlers of BIOS/UEFI Firmware <http://www.c7zero.info/stuff/ANewClassOfVulnInSMIHandlers_csw2015.pdf>`_
-
-
-Usage:
-``chipsec_main -m tools.smm.smm_ptr -l log.txt \``
-``[-a <mode>,<config_file>|<smic_start:smic_end>,<size>,<address>]``
-
-- ``mode``: SMI fuzzing mode
-
-    * ``config`` = use SMI configuration file <config_file>
-    * ``fuzz`` = fuzz all SMI handlers with code in the range <smic_start:smic_end>
-    * ``fuzzmore`` = fuzz mode + pass 2nd-order pointers within buffer to SMI handlers
-- ``size``: size of the memory buffer (in Hex)
-- ``address``: physical address of memory buffer to pass in GP regs to SMI handlers (in Hex)
-
-    * ``smram`` = option passes address of SMRAM base (system may hang in this mode!)
-
-In ``config`` mode, SMI configuration file should have the following format
-
-::
-
-    SMI_code=<SMI code> or *
-    SMI_data=<SMI data> or *
-    RAX=<value of RAX> or * or PTR or VAL
-    RBX=<value of RBX> or * or PTR or VAL
-    RCX=<value of RCX> or * or PTR or VAL
-    RDX=<value of RDX> or * or PTR or VAL
-    RSI=<value of RSI> or * or PTR or VAL
-    RDI=<value of RDI> or * or PTR or VAL
-    [PTR_OFFSET=<offset to pointer in the buffer>]
-    [SIG=<signature>]
-    [SIG_OFFSET=<offset to signature in the buffer>]
-    [Name=<SMI name>]
-    [Desc=<SMI description>]
-
-Where:
-
-    - ``[]``: optional line
-    - ``*``: Don't Care (the module will replace * with 0x0)
-    - ``PTR``: Physical address SMI handler will write to (the module will replace PTR with physical address provided as a command-line argument)
-    - ``VAL``: Value SMI handler will write to PTR address (the module will replace VAL with hardcoded _FILL_VALUE_xx)
-
-Examples:
-
-    >>> chipsec_main.py -m tools.smm.smm_ptr
-    >>> chipsec_main.py -m tools.smm.smm_ptr -a fuzzmore,0x0:0xFF -l smm.log
-
-.. warning ::
-
-    - This is a potentially destructive test
-
-"""
-
-import struct
-import os
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.file import write_file
-from chipsec.logger import print_buffer_bytes
-from chipsec.hal.interrupts import Interrupts
-from chipsec.exceptions import BadSMIDetected
-
-
-#################################################################
-# Fuzzing configuration
-#################################################################
-
-#
-# Logging option
-#
-
-# False - better performance, True - better results tracking
-DUMP_MEMORY_ON_DETECT = False
-# False - better performance, True - better results tracking
-FLUSH_OUTPUT_ALWAYS = False
-# makes sure SMI code is logged in case of a crash
-FLUSH_OUTPUT_AFTER_SMI = True
-# dump all registers in log before every SMI (True - large size of log file)
-DUMP_GPRS_EVERY_SMI = True
-
-#
-# SMI fuzzing options
-#
-
-# stop fuzzing after the first potential issue detected
-FUZZ_BAIL_ON_1ST_DETECT = True
-
-# Consider SMI handler subfunctions are passed in RCX GP register
-# Fuzz RCX as SMI subfunctions: from 0 to MAX_SMI_FUNCTIONS
-# False - better performance, True - smarter fuzzing
-FUZZ_SMI_FUNCTIONS_IN_ECX = True
-MAX_SMI_FUNCTIONS = 0x10
-
-# Max value of the value written to SMI data port (0xB3)
-MAX_SMI_DATA = 0x100
-
-# Pass the pointer to SMI handlers in all general-purpose registers
-# rather than in one register
-# True - faster, False - gives you specific GPR that the vulnerable SMI handler is consuming
-#
-PTR_IN_ALL_GPRS = False
-
-# SMI handler may take a pointer/PA from (some offset of off) address passed in GPRs and write to it
-# Treat contents at physical address passed in GPRs as pointers and check contents at that pointer
-# If they changed, SMI handler might have modified them
-#MODE_SECOND_ORDER_BUFFER  = True
-
-# Max offset of the pointer (physical address)
-# of the 2nd order buffer written in the memory buffer passed to SMI
-MAX_PTR_OFFSET_IN_BUFFER = 0x20
-
-# very obscure option, don't even try to understand
-GPR_2ADDR = False
-
-
-#
-# Defaults
-#
-_FILL_VALUE_QWORD = 0x5A5A5A5A5A5A5A5A
-_FILL_VALUE_BYTE = 0x5A
-_SMI_CODE_DATA = 0x0
-_MEM_FILL_VALUE = b'\x11'
-_MEM_FILL_SIZE = 0x500
-_MAX_ALLOC_PA = 0xFFFFFFFF
-_DEFAULT_GPRS = {'rax': _FILL_VALUE_QWORD, 'rbx': _FILL_VALUE_QWORD, 'rcx': _FILL_VALUE_QWORD, 'rdx': _FILL_VALUE_QWORD, 'rsi': _FILL_VALUE_QWORD, 'rdi': _FILL_VALUE_QWORD}
-
-_pth = 'smm_ptr'
-
-
-

-[docs]
-class smi_desc:
-    def __init__(self):
-        self.smi_code = None
-        self.smi_data = None
-        self.name = 'smi'
-        self.desc = ''
-        self.gprs = _DEFAULT_GPRS
-        self.ptr_in_buffer = False
-        self.ptr = None
-        self.ptr_offset = 0
-        self.sig = None
-        self.sig_offset = 0

-
-
-
-

-[docs]
-def DIFF(s, t, sz):
-    return [pos for pos in range(sz) if s[pos] != t[pos]]

-
-
-
-

-[docs]
-def FILL_BUFFER(_fill_byte, _fill_size, _ptr_in_buffer, _ptr, _ptr_offset, _sig, _sig_offset):
-    fill_buf = _fill_byte * _fill_size
-    if _ptr_in_buffer and (_ptr is not None):
-        fill_buf = fill_buf[:_ptr_offset] + struct.pack('=I', _ptr & 0xFFFFFFFF) + fill_buf[_ptr_offset + 4:]
-    if _sig is not None:
-        fill_buf = fill_buf[:_sig_offset] + _sig + fill_buf[_sig_offset + len(_sig):]
-    return fill_buf

-
-
-
-

-[docs]
-class smm_ptr(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.interrupts = Interrupts(self.cs)
-        self.is_check_memory = True
-        self.test_ptr_in_buffer = False
-        self.fill_byte = _MEM_FILL_VALUE
-        self.fill_size = _MEM_FILL_SIZE
-        self.rc_res = ModuleResult(0xf8457d4, 'https://chipsec.github.io/modules/chipsec.modules.tools.smm.smm_ptr.html')
-
-

-[docs]
-    def is_supported(self):
-        return True

-
-
-

-[docs]
-    def fill_memory(self, _addr, is_ptr_in_buffer, _ptr, _ptr_offset, _sig, _sig_offset):
-        #
-        # Fill in contents at PA = _addr with known pattern to check later if any SMI handler modifies them
-        #
-        fill_buf = FILL_BUFFER(self.fill_byte, self.fill_size, is_ptr_in_buffer, _ptr, _ptr_offset, _sig, _sig_offset)
-
-        s = f'[*] Writing 0x{self.fill_size:X} bytes at 0x{_addr:016X}'
-        if is_ptr_in_buffer:
-            s += f' -> PTR at +0x{_ptr_offset:X}'
-        if _sig is not None:
-            s += f' -> SIG at +0x{_sig_offset:X}'
-        self.logger.log(s)
-        self.cs.mem.write_physical_mem(_addr, self.fill_size, fill_buf)
-
-        if self.logger.VERBOSE:
-            self.logger.log(f'Filling in contents at PA 0x{_addr:016X}:')
-            print_buffer_bytes(fill_buf, 16)
-
-        if is_ptr_in_buffer and _ptr is not None:
-            self.logger.log(f'[*] Writing buffer at PA 0x{_ptr:016X} with 0x{self.fill_size:X} bytes \'{self.fill_byte}\'')
-            self.cs.mem.write_physical_mem(_ptr, self.fill_size, self.fill_byte * self.fill_size)
-
-        return True

-
-
-

-[docs]
-    def send_smi(self, thread_id, smi_code, smi_data, name, desc, rax, rbx, rcx, rdx, rsi, rdi):
-        self.logger.log(f'    > SMI {smi_code:02X} (data: {smi_data:02X})')
-        if DUMP_GPRS_EVERY_SMI:
-            self.logger.log(f'      RAX: 0x{rax:016X}')
-            self.logger.log(f'      RBX: 0x{rbx:016X}')
-            self.logger.log(f'      RCX: 0x{rcx:016X}')
-            self.logger.log(f'      RDX: 0x{rdx:016X}')
-            self.logger.log(f'      RSI: 0x{rsi:016X}')
-            self.logger.log(f'      RDI: 0x{rdi:016X}')
-        self.interrupts.send_SW_SMI(thread_id, smi_code, smi_data, rax, rbx, rcx, rdx, rsi, rdi)
-        return True

-
-
-

-[docs]
-    def check_memory(self, _addr, _smi_desc, fn, restore_contents=False):
-        _ptr = _smi_desc.ptr
-        filler = self.fill_byte * self.fill_size
-        #
-        # Check if contents have changed at physical address passed in GPRs to SMI handler
-        # If changed, SMI handler might have written to that address
-        #
-        self.logger.log("    < Checking buffers")
-
-        expected_buf = FILL_BUFFER(self.fill_byte, self.fill_size, _smi_desc.ptr_in_buffer, _smi_desc.ptr, _smi_desc.ptr_offset, _smi_desc.sig, _smi_desc.sig_offset)
-        buf = self.cs.mem.read_physical_mem(_addr, self.fill_size)
-        differences = DIFF(expected_buf, buf, self.fill_size)
-        _changed = len(differences) > 0
-
-        if self.logger.VERBOSE:
-            self.logger.log(f'Checking contents at PA 0x{_addr:016X}:')
-            print_buffer_bytes(buf, 16)
-            self.logger.log('Expected contents:')
-            print_buffer_bytes(expected_buf, 16)
-
-        if _changed:
-            self.logger.log(f'    Contents changed at 0x{_addr:016X} +{differences}')
-            if restore_contents:
-                self.logger.log(f'    Restoring 0x{self.fill_size:X} bytes at 0x{_addr:016X}')
-                self.cs.mem.write_physical_mem(_addr, self.fill_size, expected_buf)
-            if DUMP_MEMORY_ON_DETECT:
-                _pth_smi = os.path.join(_pth, f'{_smi_desc.smi_code:X}_{_smi_desc.name}')
-                if not os.path.exists(_pth_smi):
-                    os.makedirs(_pth_smi)
-                _f = os.path.join(_pth_smi, fn + '.dmp')
-                self.logger.log(f'    Dumping buffer to \'{_f}\'')
-                write_file(_f, buf)
-
-        _changed1 = False
-        expected_buf = filler
-        if _smi_desc.ptr_in_buffer and (_ptr is not None):
-            buf1 = self.cs.mem.read_physical_mem(_ptr, self.fill_size)
-            differences1 = DIFF(expected_buf, buf1, self.fill_size)
-            _changed1 = len(differences1) > 0
-
-            if self.logger.VERBOSE:
-                self.logger.log(f'Checking contents at PA 0x{_ptr:016X}:')
-                print_buffer_bytes(buf1, 16)
-
-            if _changed1:
-                self.logger.log(f'    Contents changed at 0x{_ptr:016X} +{differences1}')
-                if restore_contents:
-                    self.logger.log(f'    Restoring 0x{self.fill_size:X} bytes at PA 0x{_ptr:016X}')
-                    self.cs.mem.write_physical_mem(_ptr, self.fill_size, expected_buf)
-                if DUMP_MEMORY_ON_DETECT:
-                    _pth_smi = os.path.join(_pth, f'{_smi_desc.smi_code:X}_{_smi_desc.name}')
-                    if not os.path.exists(_pth_smi):
-                        os.makedirs(_pth_smi)
-                    _f = os.path.join(_pth_smi, fn + (f'_ptr{_smi_desc.ptr_offset:X}.dmp'))
-                    self.logger.log(f'    Dumping buffer to \'{_f}\'')
-                    write_file(_f, buf1)
-
-        return (_changed or _changed1)

-
-
-

-[docs]
-    def smi_fuzz_iter(self, thread_id, _addr, _smi_desc, fill_contents=True, restore_contents=False):
-        #
-        # Fill memory buffer if not in 'No Fill' mode
-        #
-        if self.is_check_memory and fill_contents:
-            self.fill_memory(_addr, _smi_desc.ptr_in_buffer, _smi_desc.ptr, _smi_desc.ptr_offset, _smi_desc.sig, _smi_desc.sig_offset)
-        #
-        # Invoke SW SMI Handler
-        #
-        _rax = _smi_desc.gprs['rax']
-        _rbx = _smi_desc.gprs['rbx']
-        _rcx = _smi_desc.gprs['rcx']
-        _rdx = _smi_desc.gprs['rdx']
-        _rsi = _smi_desc.gprs['rsi']
-        _rdi = _smi_desc.gprs['rdi']
-        self.send_smi(thread_id, _smi_desc.smi_code, _smi_desc.smi_data, _smi_desc.name, _smi_desc.desc, _rax, _rbx, _rcx, _rdx, _rsi, _rdi)
-
-        #
-        # Check memory buffer if not in 'No Fill' mode
-        #
-        contents_changed = False
-        if self.is_check_memory:
-            fn = f'{_smi_desc.smi_data:X}-a{_rax:X}_b{_rbx:X}_c{_rcx:X}_d{_rdx:X}_si{_rsi:X}_di{_rdi:X}'
-            contents_changed = self.check_memory(_addr, _smi_desc, fn, restore_contents)
-            if contents_changed:
-                msg = f'DETECTED: SMI# {_smi_desc.smi_code:X} data {_smi_desc.smi_data:X} (rax={_rax:X} rbx={_rbx:X} rcx={_rcx:X} rdx={_rdx:X} rsi={_rsi:X} rdi={_rdi:X})'
-                self.logger.log_important(msg)
-                if FUZZ_BAIL_ON_1ST_DETECT:
-                    raise BadSMIDetected(msg)
-
-        if FLUSH_OUTPUT_AFTER_SMI:
-            self.logger.flush()
-
-        return contents_changed

-
-
-

-[docs]
-    def test_config(self, thread_id, _smi_config_fname, _addr, _addr1):
-        #
-        # Parse SMM config file describing SMI handlers and their call arguments
-        # Then invoke SMI handlers
-        #
-        fcfg = open(_smi_config_fname, 'r')
-        self.logger.log(f'\n[*] >>> Testing SMI handlers defined in \'{_smi_config_fname}\'..')
-
-        bad_ptr_cnt = 0
-        _smi_desc = smi_desc()
-        for line in fcfg:
-            if '' == line.strip():
-                self.logger.log(f'\n[*] Testing SMI# 0x{_smi_desc.smi_code:02X} (data: 0x{_smi_desc.smi_data:02X}) {_smi_desc.name} ({_smi_desc.desc})')
-                if self.smi_fuzz_iter(thread_id, _addr, _smi_desc):
-                    bad_ptr_cnt += 1
-                _smi_desc = None
-                _smi_desc = smi_desc()
-            else:
-                name, var = line.strip().partition('=')[::2]
-                _n = name.strip().lower()
-                if 'name' == _n:
-                    _smi_desc.name = var
-                elif 'desc' == _n:
-                    _smi_desc.desc = var
-                elif 'smi_code' == _n:
-                    _smi_desc.smi_code = int(var, 16) if '*' != var else _SMI_CODE_DATA
-                elif 'smi_data' == _n:
-                    _smi_desc.smi_data = int(var, 16) if '*' != var else _SMI_CODE_DATA
-                elif 'ptr_offset' == _n:
-                    _smi_desc.ptr_in_buffer = True
-                    _smi_desc.ptr_offset = int(var, 16)
-                    _smi_desc.ptr = _addr1
-                elif 'sig' == _n:
-                    _smi_desc.sig = bytearray.fromhex(var)
-                elif 'sig_offset' == _n:
-                    _smi_desc.sig_offset = int(var, 16)
-                else:
-                    _smi_desc.gprs[_n] = (_addr if 'PTR' == var else (_FILL_VALUE_BYTE if 'VAL' == var else int(var, 16))) if '*' != var else _FILL_VALUE_QWORD
-
-        return bad_ptr_cnt

-
-
-

-[docs]
-    def test_fuzz(self, thread_id, smic_start, smic_end, _addr, _addr1):
-
-        gpr_value = ((_addr << 32) | _addr) if GPR_2ADDR else _addr
-
-        gprs_addr = {'rax': gpr_value, 'rbx': gpr_value, 'rcx': gpr_value, 'rdx': gpr_value, 'rsi': gpr_value, 'rdi': gpr_value}
-        gprs_fill = {'rax': _FILL_VALUE_QWORD, 'rbx': _FILL_VALUE_QWORD, 'rcx': _FILL_VALUE_QWORD, 'rdx': _FILL_VALUE_QWORD, 'rsi': _FILL_VALUE_QWORD, 'rdi': _FILL_VALUE_QWORD}
-        self.logger.log("\n[*] >>> Fuzzing SMI handlers..")
-        self.logger.log("[*] AX in RAX will be overridden with values of SW SMI ports 0xB2/0xB3")
-        self.logger.log("    DX in RDX will be overridden with value 0x00B2")
-
-        bad_ptr_cnt = 0
-        _smi_desc = smi_desc()
-        _smi_desc.gprs = gprs_addr if PTR_IN_ALL_GPRS else gprs_fill
-        self.logger.log(f'\n[*] Setting values of general purpose registers to 0x{_smi_desc.gprs["rax"]:016X}')
-        max_ptr_off = 1
-
-        if self.is_check_memory and self.test_ptr_in_buffer:
-            _smi_desc.ptr_in_buffer = True
-            _smi_desc.ptr = _addr1
-            max_ptr_off = MAX_PTR_OFFSET_IN_BUFFER + 1
-
-        # if we are not in fuzzmore mode, i.e. we are not testing the pointer within memory buffer
-        # then this outer loop will only have 1 iteration
-        for off in range(max_ptr_off):
-            _smi_desc.ptr_offset = off
-            self.logger.log(f'\n[*] Reloading buffer with PTR at offset 0x{off:X}..')
-            if self.is_check_memory:
-                self.fill_memory(_addr, _smi_desc.ptr_in_buffer, _smi_desc.ptr, _smi_desc.ptr_offset, None, None)
-
-            for smi_code in range(smic_start, smic_end + 1, 1):
-                _smi_desc.smi_code = smi_code
-                for smi_data in range(MAX_SMI_DATA):
-                    _smi_desc.smi_data = smi_data
-                    self.logger.log(f'\n[*] Fuzzing SMI# 0x{smi_code:02X} (data: 0x{smi_data:02X})')
-                    if FUZZ_SMI_FUNCTIONS_IN_ECX:
-                        for _rcx in range(MAX_SMI_FUNCTIONS):
-                            self.logger.log(f' >> Function (RCX): 0x{_rcx:016X}')
-                            _smi_desc.gprs['rcx'] = _rcx
-                            if PTR_IN_ALL_GPRS:
-                                if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                    bad_ptr_cnt += 1
-                            else:
-                                self.logger.log(f'    RBX: 0x{_addr:016X}')
-                                _smi_desc.gprs['rbx'] = gpr_value
-                                if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                    bad_ptr_cnt += 1
-                                _smi_desc.gprs['rbx'] = _FILL_VALUE_QWORD
-
-                                self.logger.log(f'    RSI: 0x{_addr:016X}')
-                                _smi_desc.gprs['rsi'] = gpr_value
-                                if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                    bad_ptr_cnt += 1
-                                _smi_desc.gprs['rsi'] = _FILL_VALUE_QWORD
-
-                                self.logger.log(f'    RDI: 0x{_addr:016X}')
-                                _smi_desc.gprs['rdi'] = gpr_value
-                                if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                    bad_ptr_cnt += 1
-                                _smi_desc.gprs['rdi'] = _FILL_VALUE_QWORD
-                    else:
-                        if PTR_IN_ALL_GPRS:
-                            if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                bad_ptr_cnt += 1
-                        else:
-                            self.logger.log(f'    RBX: 0x{_addr:016X}')
-                            _smi_desc.gprs['rbx'] = gpr_value
-                            if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                bad_ptr_cnt += 1
-                            _smi_desc.gprs['rbx'] = _FILL_VALUE_QWORD
-
-                            self.logger.log(f'    RCX: 0x{_addr:016X}')
-                            _smi_desc.gprs['rcx'] = gpr_value
-                            if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                bad_ptr_cnt += 1
-                            _smi_desc.gprs['rcx'] = _FILL_VALUE_QWORD
-
-                            self.logger.log(f'    RSI: 0x{_addr:016X}')
-                            _smi_desc.gprs['rsi'] = gpr_value
-                            if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                bad_ptr_cnt += 1
-                            _smi_desc.gprs['rsi'] = _FILL_VALUE_QWORD
-
-                            self.logger.log(f'    RDI: 0x{_addr:016X}')
-                            _smi_desc.gprs['rdi'] = gpr_value
-                            if self.smi_fuzz_iter(thread_id, _addr, _smi_desc, False, True):
-                                bad_ptr_cnt += 1
-                            _smi_desc.gprs['rdi'] = _FILL_VALUE_QWORD
-
-        return bad_ptr_cnt

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("A tool to test SMI handlers for pointer validation vulnerabilities")
-        self.logger.log("Usage: chipsec_main -m tools.smm.smm_ptr [ -a <mode>,<config_file>|<smic_start:smic_end>,<size>,<address> ]")
-        self.logger.log("  mode          SMI handlers testing mode")
-        self.logger.log("    = config    use SMI configuration file <config_file>")
-        self.logger.log("    = fuzz      fuzz all SMI handlers with code in the range <smic_start:smic_end>")
-        self.logger.log("    = fuzzmore  fuzz mode + pass '2nd-order' pointers within buffer to SMI handlers")
-        self.logger.log("  size          size of the memory buffer (in Hex)")
-        self.logger.log("  address       physical address of memory buffer to pass in GP regs to SMI handlers (in Hex)")
-        self.logger.log("    = smram     pass address of SMRAM base (system may hang in this mode!)\n")
-
-        test_mode = 'config'
-        _smi_config_fname = 'chipsec/modules/tools/smm/smm_config.ini'
-        _addr = None
-        _addr1 = None
-        thread_id = 0x0
-
-        global DUMP_GPRS_EVERY_SMI
-        smic_start = 0
-        smic_end = 0
-        if len(module_argv) > 1:
-            test_mode = module_argv[0].lower()
-            if test_mode == 'config':
-                _smi_config_fname = module_argv[1]
-            elif test_mode in ['fuzz', 'fuzzmore']:
-                smic_arr = module_argv[1].split(':')
-                smic_start = int(smic_arr[0], 16)
-                smic_end = int(smic_arr[1], 16)
-                if test_mode == 'fuzzmore':
-                    self.test_ptr_in_buffer = True
-                    DUMP_GPRS_EVERY_SMI = False
-            else:
-                self.logger.log_error(f'Unknown fuzzing mode \'{module_argv[0]}\'')
-                self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_OPTION)
-                return self.rc_res.getReturnCode(ModuleResult.ERROR)
-
-        if len(module_argv) > 2:
-            self.fill_size = int(module_argv[2], 16)
-        if len(module_argv) > 3:
-            if 'smram' == module_argv[3]:
-                (_addr, _, _) = self.cs.cpu.get_SMRAM()
-                self.is_check_memory = False
-                self.logger.log(f'[*] Using SMRAM base address (0x{_addr:016X}) to pass to SMI handlers')
-            else:
-                _addr = int(module_argv[3], 16)
-                self.logger.log(f'[*] Using address from command-line (0x{_addr:016X}) to pass to SMI handlers')
-        else:
-            (_, _addr) = self.cs.mem.alloc_physical_mem(self.fill_size, _MAX_ALLOC_PA)
-            self.logger.log(f'[*] Allocated memory buffer (to pass to SMI handlers)       : 0x{_addr:016X}')
-
-        if self.is_check_memory:
-            (_, _addr1) = self.cs.mem.alloc_physical_mem(self.fill_size, _MAX_ALLOC_PA)
-            self.logger.log(f'[*] Allocated 2nd buffer (address will be in the 1st buffer): 0x{_addr1:016X}')
-
-        #
-        # @TODO: Need to check that SW/APMC SMI is enabled
-        #
-
-        self.logger.log('\n[*] Configuration:')
-        self.logger.log(f'    SMI testing mode          : {test_mode}')
-        if test_mode == 'config':
-            self.logger.log(f'    Config file           : {_smi_config_fname}')
-        else:
-            self.logger.log(f'    Range of SMI codes (B2)   : 0x{smic_start:02X}:0x{smic_end:02X}')
-        self.logger.log(f'    Memory buffer pointer     : 0x{_addr:016X} (address passed in GP regs to SMI)')
-        self.logger.log(f'    Filling/checking memory?  : {"YES" if self.is_check_memory else "NO"}')
-        if self.is_check_memory:
-            self.logger.log(f'      Second buffer pointer   : 0x{_addr1:016X} (address written to memory buffer)')
-            self.logger.log(f'      Number of bytes to fill : 0x{self.fill_size:X}')
-            self.logger.log(f'      Byte to fill with       : 0x{ord(self.fill_byte):X}')
-        self.logger.log(f'    Additional options (can be changed in the source code):f')
-        self.logger.log(f'      Fuzzing SMI functions in ECX?          : {FUZZ_SMI_FUNCTIONS_IN_ECX:d}')
-        self.logger.log(f'      Max value of SMI function in ECX       : 0x{MAX_SMI_FUNCTIONS:X}')
-        self.logger.log(f'      Max value of SMI data (B3)             : 0x{MAX_SMI_DATA:X}')
-        self.logger.log(f'      Max offset of the pointer in the buffer: 0x{MAX_PTR_OFFSET_IN_BUFFER:X}')
-        self.logger.log(f'      Passing pointer in all GP registers?   : {PTR_IN_ALL_GPRS:d}')
-        self.logger.log(f'      Default values of the registers        : 0x{_FILL_VALUE_QWORD:016X}')
-        self.logger.log(f'      Dump all register values every SMI     : {DUMP_GPRS_EVERY_SMI:d}')
-        self.logger.log(f'      Bail on first detection                : {FUZZ_BAIL_ON_1ST_DETECT:d}')
-
-        self.logger.set_always_flush(FLUSH_OUTPUT_ALWAYS)
-        if DUMP_MEMORY_ON_DETECT and not os.path.exists(_pth):
-            os.makedirs(_pth)
-
-        bad_ptr_cnt = 0
-        try:
-            if 'config' == test_mode:
-                bad_ptr_cnt = self.test_config(thread_id, _smi_config_fname, _addr, _addr1)
-            elif test_mode in ['fuzz', 'fuzzmore']:
-                bad_ptr_cnt = self.test_fuzz(thread_id, smic_start, smic_end, _addr, _addr1)
-        except BadSMIDetected as msg:
-            bad_ptr_cnt = 1
-            self.logger.log_important("Potentially bad SMI detected! Stopped fuzing (see FUZZ_BAIL_ON_1ST_DETECT option)")
-
-        if bad_ptr_cnt > 0:
-            self.logger.log_bad(f'<<< Done: found {bad_ptr_cnt:d} potential occurrences of unchecked input pointers')
-            self.rc_res.setStatusBit(self.rc_res.status.POTENTIALLY_VULNERABLE)
-            self.res = self.rc_res.getReturnCode(ModuleResult.FAILED)
-        else:
-            self.logger.log_good("<<< Done: didn't find unchecked input pointers in tested SMI handlers")
-            self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-            self.res = self.rc_res.getReturnCode(ModuleResult.PASSED)
-
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/uefi/reputation.html b/_modules/chipsec/modules/tools/uefi/reputation.html
deleted file mode 100644
index b6eff845..00000000
--- a/_modules/chipsec/modules/tools/uefi/reputation.html
+++ /dev/null
@@ -1,285 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.uefi.reputation — CHIPSEC  documentation
-    
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Source code for chipsec.modules.tools.uefi.reputation
-"""
-This module checks current contents of UEFI firmware ROM or specified firmware image for bad EFI binaries as per the
-VirusTotal API. These can be EFI firmware volumes, EFI executable binaries (PEI modules, DXE drivers..) or EFI sections.
-The module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes
-or contents matching specified regular expressions.
-
-Important! This module can only detect bad or vulnerable EFI modules based on the file's reputation on VT.
-
-Usage:
-    chipsec_main.py -i -m tools.uefi.reputation -a <vt_api_key>[,<vt_threshold>,<fw_image>]
-      vt_api_key   : API key to VirusTotal. Can be obtained by visting https://www.virustotal.com/gui/join-us.
-                     This argument must be specified.
-      vt_threshold : The minimal number of different AV vendors on VT which must claim an EFI module is malicious
-                     before failing the test. Defaults to 10.
-      fw_image     : Full file path to UEFI firmware image
-                     If not specified, the module will dump firmware image directly from ROM
-
-.. note::
-    - Requires virustotal-api
-
-"""
-import time
-
-from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS
-from chipsec.hal.spi_uefi import search_efi_tree, build_efi_model, EFIModuleType
-from chipsec.hal.uefi import UEFI
-from chipsec.hal.spi import SPI, BIOS
-from chipsec.file import read_file
-
-try:
-    from virus_total_apis import PublicApi as VirusTotalPublicApi
-    has_virus_total_apis = True
-except ImportError:
-    has_virus_total_apis = False
-
-TAGS = [MTAG_BIOS]
-
-DEF_FWIMAGE_FILE = 'fw.bin'
-
-USAGE_TEXT = '''
-Usage:
-
-    chipsec_main.py -i -m tools.uefi.reputation -a <vt_api_key>[,<vt_threshold>,<fw_image>]
-
-      vt_api_key   : API key to VirusTotal. Can be obtained by visiting https://www.virustotal.com/gui/join-us.
-                     This argument must be specified.
-      vt_threshold : The minimal number of different AV vendors on VT which must claim an EFI module is bad
-                     before failing the test. Defaults to 10.
-      fw_image     : Full file path to UEFI firmware image
-                     If not specified, the module will dump firmware image directly from ROM
-'''
-
-
-

-[docs]
-class reputation(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.uefi = UEFI(self.cs)
-        self.image = None
-        self.vt_threshold = 10
-        self.vt = None
-
-

-[docs]
-    def is_supported(self):
-        if has_virus_total_apis:
-            return True
-        else:
-            self.logger.log_important("""Can't import module 'virus_total_apis'.
-Please run 'pip install virustotal-api' and try again.""")
-            self.res = ModuleResult.NOTAPPLICABLE
-            return False

-
-
-

-[docs]
-    def reputation_callback(self, efi_module):
-        vt_report = self.vt.get_file_report(efi_module.SHA256)
-
-        while vt_report["response_code"] == 204:
-            # The Public API is limited to 4 requests per minute.
-            if self.logger.DEBUG:
-                self.logger.log("VT API quota exceeded, sleeping for 1 minute... (-.-)zzZZ")
-
-            time.sleep(60)
-            # Retry.
-            vt_report = self.vt.get_file_report(efi_module.SHA256)
-
-        if vt_report["results"]["response_code"] == 0:
-            # Hash is unknown to VT.
-            self.logger.log_important(f'Unfamiliar EFI binary found in the UEFI firmware image\n{efi_module}')
-            return False
-
-        if vt_report["results"]["positives"] >= self.vt_threshold:
-            self.logger.log_bad(f'Suspicious EFI binary found in the UEFI firmware image\n{efi_module}')
-            return True
-
-        if self.logger.VERBOSE:
-            self.logger.log(f'Benign EFI binary found in the UEFI firmware image\n{efi_module}')
-
-        return False

-
-
-

-[docs]
-    def check_reputation(self):
-        res = ModuleResult.PASSED
-
-        # parse the UEFI firmware image and look for EFI modules matching the blocked-list
-        efi_tree = build_efi_model(self.image, None)
-        match_types = EFIModuleType.SECTION_EXE
-        matching_modules = search_efi_tree(efi_tree, self.reputation_callback, match_types)
-        found = len(matching_modules) > 0
-        self.logger.log('')
-        if found:
-            res = ModuleResult.WARNING
-            self.logger.log_warning("Suspicious EFI binary found in the UEFI firmware image")
-        else:
-            self.logger.log_passed("Didn't find any suspicious EFI binary")
-        return res

-
-
-

-[docs]
-    def usage(self):
-        self.logger.log(USAGE_TEXT)

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Check for suspicious EFI binaries in UEFI firmware")
-
-        self.usage()
-
-        if len(module_argv) > 0:
-            self.vt = VirusTotalPublicApi(module_argv[0])
-        if len(module_argv) > 1:
-            self.vt_threshold = int(module_argv[1])
-
-        image_file = DEF_FWIMAGE_FILE
-        if len(module_argv) > 2:
-            # Use provided firmware image
-            image_file = module_argv[2]
-            self.logger.log(f'[*] Reading FW image from file: {image_file}')
-        else:
-            # Read firmware image directly from SPI flash memory
-            self.spi = SPI(self.cs)
-            (base, limit, _) = self.spi.get_SPI_region(BIOS)
-            image_size = limit + 1 - base
-            self.logger.log(f'[*] Dumping FW image from ROM to {image_file}: 0x{base:08X} bytes at [0x{limit:08X}:0x{image_size:08X}]')
-            self.logger.log("[*] This may take a few minutes (instead, use 'chipsec_util spi dump')...")
-            self.spi.read_spi_to_file(base, image_size, image_file)
-
-        self.image = read_file(image_file)
-
-        self.res = self.check_reputation()
-        return self.res

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diff --git a/_modules/chipsec/modules/tools/uefi/s3script_modify.html b/_modules/chipsec/modules/tools/uefi/s3script_modify.html
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-    chipsec.modules.tools.uefi.s3script_modify — CHIPSEC  documentation
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Source code for chipsec.modules.tools.uefi.s3script_modify
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-This module will attempt to modify the S3 Boot Script on the platform. Doing this could cause the platform to malfunction. Use with care!
-
-Usage:
-    Replacing existing opcode::
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,<reg_opcode>,<address>,<value>
-            <reg_opcode> = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem[,<address>,<value>]
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch``
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep``
-
-
-    Adding new opcode::
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a add_op,<reg_opcode>,<address>,<value>,<width>
-            <reg_opcode> = pci_wr|mmio_wr|io_wr
-
-        chipsec_main.py -m tools.uefi.s3script_modify -a add_op,dispatch[,<entrypoint>]
-
-Examples:
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,<reg_opcode>,<address>,<value>
->>>   <reg_opcode> = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw
-
-The option will look for a script opcode that writes to PCI config, MMIO or I/O registers and modify the opcode to write the given value to the register with the given address.
-
-After executing this, if the system is vulnerable to boot script modification, the hardware configuration will have changed according to given <reg_opcode>.
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem
-
-The option will look for a script opcode that writes to memory and modify the opcode to write the given value to the given address.
-
-By default this test will allocate memory and write write ``0xB007B007`` that location.
-
-After executing this, if the system is vulnerable to boot script modification, you should find the given value in the allocated memory location.
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch
-
-The option will look for a dispatch opcode in the script and modify the opcode to point to a different entry point. The new entry point will contain a HLT instruction.
-
-After executing this, if the system is vulnerable to boot script modification, the system should hang on resume from S3.
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep
-
-The option will look for a dispatch opcode in the script and will modify memory at the entry point for that opcode. The modified instructions will contain a HLT instruction.
-
-After executing this, if the system is vulnerable to dispatch opcode entry point modification, the system should hang on resume from S3.
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a add_op,<reg_opcode>,<address>,<value>,<width>
->>>   <reg_opcode> = pci_wr|mmio_wr|io_wr
-
-The option will add a new opcode which writes to PCI config, MMIO or I/O registers with specified values.
-
->>> chipsec_main.py -m tools.uefi.s3script_modify -a add_op,dispatch
-
-The option will add a new DISPATCH opcode to the script with entry point to either existing or newly allocated memory.
-
-"""
-
-examples_str = """  Examples:
-    Replacing existing opcode:
-    chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,<reg_opcode>,<address>,<value>
-       <reg_opcode> = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw
-    chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem[,<address>,<value>]
-    chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch
-    chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep
-
-    Adding new opcode:
-    chipsec_main.py -m tools.uefi.s3script_modify -a add_op,<reg_opcode>,<address>,<value>,<width>
-       <reg_opcode> = pci_wr|mmio_wr|io_wr
-    chipsec_main.py -m tools.uefi.s3script_modify -a add_op,dispatch[,<entrypoint>]
-
-"""
-
-import struct
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.logger import print_buffer_bytes
-from chipsec.hal.uefi import UEFI
-from chipsec.hal.uefi_common import S3BootScriptOpcode, script_width_values, script_width_formats, op_io_pci_mem, op_dispatch
-from chipsec.hal.uefi_platform import encode_s3bootscript_entry, id_s3bootscript_type, create_s3bootscript_entry_buffer
-
-########################################################################################################
-#
-# Main module functionality
-#
-########################################################################################################
-
-cmd2opcode = {
-    'pci_wr': S3BootScriptOpcode.EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE,
-    'mmio_wr': S3BootScriptOpcode.EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE,
-    'io_wr': S3BootScriptOpcode.EFI_BOOT_SCRIPT_IO_WRITE_OPCODE,
-    'pci_rw': S3BootScriptOpcode.EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,
-    'mmio_rw': S3BootScriptOpcode.EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE,
-    'io_rw': S3BootScriptOpcode.EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE
-}
-
-dispatch_opcode = S3BootScriptOpcode.EFI_BOOT_SCRIPT_DISPATCH_OPCODE
-terminate_opcode = S3BootScriptOpcode.EFI_BOOT_SCRIPT_TERMINATE_OPCODE
-
-write_opcodes = [
-    S3BootScriptOpcode.EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE,
-    S3BootScriptOpcode.EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE,
-    S3BootScriptOpcode.EFI_BOOT_SCRIPT_IO_WRITE_OPCODE
-]
-
-
-

-[docs]
-class s3script_modify(BaseModule):
-
-    DISPATCH_ENTRYPOINT_INSTR = '\x90\x90\xF4\xF4'
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.logger.HAL = True
-        self._uefi = UEFI(self.cs)
-        self.bootscript_PAs = None
-        self.parsed_scripts = None
-
-

-[docs]
-    def get_bootscript(self):
-        if (self.bootscript_PAs is None) or (self.parsed_scripts is None):
-            (self.bootscript_PAs, self.parsed_scripts) = self._uefi.get_s3_bootscript(False)
-        return (self.bootscript_PAs, self.parsed_scripts)

-
-
-

-[docs]
-    def is_supported(self):
-        supported = self.cs.helper.EFI_supported()
-        if not supported:
-            self.logger.log("OS does not support UEFI Runtime API.  Skipping module.")
-            self.res = ModuleResult.NOTAPPLICABLE
-        else:
-            _, ps = self.get_bootscript()
-            if not ps:
-                self.logger.log("Unable to locate boot script.  Skipping module.")
-                self.res = ModuleResult.NOTAPPLICABLE
-                supported = False
-        return supported

-
-
-

-[docs]
-    def modify_s3_reg(self, opcode, address, new_value):
-        (bootscript_PAs, parsed_scripts) = self.get_bootscript()
-        if parsed_scripts is None:
-            self.logger.log_bad("Did not find boot script.")
-            return False
-        for bootscript_pa in bootscript_PAs:
-            if bootscript_pa == 0:
-                continue
-            self.logger.log(f'[*] Looking for 0x{opcode:X} opcode in the script at 0x{bootscript_pa:016X}..')
-            for e in parsed_scripts[bootscript_pa]:
-                if (e.decoded_opcode is not None) and \
-                   (opcode == e.decoded_opcode.opcode) and \
-                   (address == e.decoded_opcode.address):
-
-                    self.logger.log_good(f'Found opcode at offset 0x{e.offset_in_script:04X}')
-                    self.logger.log(e)
-                    pa = bootscript_pa + e.offset_in_script
-                    self.logger.log(f'[*] Modifying S3 boot script entry at address 0x{pa:016X}..')
-
-                    orig_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Original entry:")
-                    print_buffer_bytes(orig_entry_buf)
-
-                    if opcode in write_opcodes:
-                        e.decoded_opcode.values[0] = new_value
-                    else:
-                        e.decoded_opcode.value = new_value
-
-                    entry_buf = encode_s3bootscript_entry(e)
-                    self.cs.mem.write_physical_mem(pa, e.length, entry_buf)
-
-                    new_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Modified entry:")
-                    print_buffer_bytes(new_entry_buf)
-                    return True
-
-        self.logger.log_bad(f'Did not find required 0x{opcode:X} opcode in the script')
-        return False

-
-
-

-[docs]
-    def modify_s3_dispatch(self):
-        ep_size = len(self.DISPATCH_ENTRYPOINT_INSTR)
-        (smram_base, _, _) = self.cs.cpu.get_SMRAM()
-        (_, new_entrypoint) = self.cs.mem.alloc_physical_mem(ep_size, smram_base)
-        self.cs.mem.write_physical_mem(new_entrypoint, ep_size, self.DISPATCH_ENTRYPOINT_INSTR)
-        new_ep = self.cs.mem.read_physical_mem(new_entrypoint, ep_size)
-        self.logger.log_good(f'Allocated new DISPATCH entry-point at 0x{new_entrypoint:016X} (size = 0x{ep_size:X}):')
-        print_buffer_bytes(new_ep)
-
-        (bootscript_PAs, parsed_scripts) = self.get_bootscript()
-        if parsed_scripts is None:
-            self.logger.log_bad("Did not find boot script.")
-            return False
-        for bootscript_pa in bootscript_PAs:
-            if bootscript_pa == 0:
-                continue
-            self.logger.log(f'[*] Searching the script at 0x{bootscript_pa:016X} for DISPATCH opcodes..')
-            for e in parsed_scripts[bootscript_pa]:
-                if (e.decoded_opcode is not None) and (dispatch_opcode == e.decoded_opcode.opcode):
-
-                    self.logger.log_good(f'Found DISPATCH opcode at offset 0x{e.offset_in_script:04X}')
-                    self.logger.log(e)
-                    pa = bootscript_pa + e.offset_in_script
-                    self.logger.log(f'[*] Modifying S3 boot script entry at address 0x{pa:016X}..')
-
-                    orig_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Original entry:")
-                    print_buffer_bytes(orig_entry_buf)
-
-                    e.decoded_opcode.entrypoint = new_entrypoint
-                    entry_buf = encode_s3bootscript_entry(e)
-                    self.cs.mem.write_physical_mem(pa, e.length, entry_buf)
-
-                    new_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Modified entry:")
-                    print_buffer_bytes(new_entry_buf)
-                    self.logger.log('After sleep/resume, the system should hang')
-                    return True
-
-        self.logger.log_bad("Did not find any suitable DISPATCH opcodes")
-        return False

-
-
-

-[docs]
-    def modify_s3_dispatch_ep(self):
-        ep_pa = None
-        (bootscript_PAs, parsed_scripts) = self.get_bootscript()
-        if parsed_scripts is None:
-            self.logger.log_bad("Did not find boot script.")
-            return False
-        for script_pa in bootscript_PAs:
-            if script_pa == 0:
-                continue
-            self.logger.log(f'[*] Looking for DISPATCH opcode in the script at 0x{script_pa:016X}..')
-            for e in parsed_scripts[script_pa]:
-                if (e.decoded_opcode is not None) and (dispatch_opcode == e.decoded_opcode.opcode):
-                    ep_pa = e.decoded_opcode.entrypoint
-                    self.logger.log_good(f'Found DISPATCH opcode at offset 0x{e.offset_in_script:04X} with entry-point 0x{ep_pa:016X}')
-                    self.logger.log(e)
-                    break
-            if ep_pa is not None:
-                break
-
-        if ep_pa is None:
-            self.logger.log_bad("Didn't find any DISPATCH opcodes")
-            return False
-
-        ep_size = len(self.DISPATCH_ENTRYPOINT_INSTR)
-        self.cs.mem.write_physical_mem(ep_pa, ep_size, self.DISPATCH_ENTRYPOINT_INSTR)
-        new_ep = self.cs.mem.read_physical_mem(ep_pa, ep_size)
-        self.logger.log(f'[*] New DISPATCH entry-point at 0x{ep_pa:016X} (size = 0x{ep_size:X}):')
-        print_buffer_bytes(new_ep)
-        return True

-
-
-

-[docs]
-    def modify_s3_mem(self, address, new_value):
-        if address is None:
-            (smram_base, _, _) = self.cs.cpu.get_SMRAM()
-            (_, address) = self.cs.mem.alloc_physical_mem(0x1000, smram_base)
-            self.logger.log(f'[*] Allocated memory at 0x{address:016X} as a target of MEM_WRITE opcode')
-
-        val = self.cs.mem.read_physical_mem_dword(address)
-        self.logger.log(f'[*] Original value at 0x{address:016X}: 0x{val:08X}')
-
-        (bootscript_PAs, parsed_scripts) = self.get_bootscript()
-        if parsed_scripts is None:
-            self.logger.log_bad("Did not find boot script.")
-            return False
-        for bootscript_pa in bootscript_PAs:
-            if bootscript_pa == 0:
-                continue
-            self.logger.log(f'[*] Looking for MEM_WRITE opcode in the script at 0x{bootscript_pa:016X}..')
-            for e in parsed_scripts[bootscript_pa]:
-                if (e.decoded_opcode is not None) and (cmd2opcode['mmio_wr'] == e.decoded_opcode.opcode):
-
-                    self.logger.log_good(f'Found opcode at offset 0x{e.offset_in_script:X}')
-                    self.logger.log(e)
-                    pa = bootscript_pa + e.offset_in_script
-                    self.logger.log(f'[*] Modifying S3 boot script entry at address 0x{pa:016X}..')
-
-                    orig_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Original entry:")
-                    print_buffer_bytes(orig_entry_buf)
-
-                    e.decoded_opcode.address = address
-                    e.decoded_opcode.values[0] = new_value
-                    entry_buf = encode_s3bootscript_entry(e)
-                    self.cs.mem.write_physical_mem(pa, e.length, entry_buf)
-
-                    new_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-                    self.logger.log("[*] Modified entry:")
-                    print_buffer_bytes(new_entry_buf)
-                    self.logger.log(f'After sleep/resume, read address 0x{address:08X} and look for value 0x{new_value:08X}')
-                    return True
-
-        self.logger.log_bad(f'Did not find required 0x{cmd2opcode["mmio_wr"]:X} opcode in the script')
-        return False

-
-
-

-[docs]
-    def modify_s3_add(self, new_opcode):
-        e_index = None
-        (bootscript_PAs, parsed_scripts) = self.get_bootscript()
-        if parsed_scripts is None:
-            self.logger.log_bad("Did not find boot script.")
-            return False
-
-        for bootscript_pa in bootscript_PAs:
-            if bootscript_pa == 0:
-                continue
-            script_buffer = self.cs.mem.read_physical_mem(bootscript_pa, 4)
-            script_type, _ = id_s3bootscript_type(script_buffer, False)
-            self.logger.log(f'[*] S3 boot script type: 0x{script_type:0X}')
-
-            self.logger.log(f'[*] Looking for TERMINATE opcode in the script at 0x{bootscript_pa:016X}..')
-            for e in parsed_scripts[bootscript_pa]:
-                if (e.index is not None) and (e.index != -1):
-                    e_index = e.index + 1
-
-                if (e.decoded_opcode is not None) and (terminate_opcode == e.decoded_opcode.opcode):
-                    self.logger.log_good(f'Found TERMINATE opcode at offset 0x{e.offset_in_script:X}')
-                    self.logger.log(e)
-                    pa = bootscript_pa + e.offset_in_script
-                    orig_entry_buf = self.cs.mem.read_physical_mem(pa, e.length)
-
-                    self.logger.log("[*] New S3 boot script opcode:")
-                    self.logger.log(new_opcode)
-                    self.logger.log(f'[*] Adding new opcode entry at address 0x{pa:016X}..')
-                    new_entry = create_s3bootscript_entry_buffer(script_type, new_opcode, e_index)
-                    print_buffer_bytes(new_entry)
-
-                    self.cs.mem.write_physical_mem(pa, len(new_entry), new_entry)
-                    last_entry_pa = pa + len(new_entry)
-                    self.logger.log(f'[*] Moving TERMINATE opcode to the last entry at 0x{last_entry_pa:016X}..')
-                    self.cs.mem.write_physical_mem(last_entry_pa, len(orig_entry_buf), orig_entry_buf)
-                    return True
-
-        self.logger.log_bad("Did not find TERMINATE opcode")
-        return False

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test('S3 Resume Boot-Script Testing')
-        sts = False
-
-        op = module_argv[0].lower() if len(module_argv) > 0 else 'add_op'
-        if op == 'replace_op':
-            scmd = module_argv[1].lower() if len(module_argv) > 1 else 'dispatch_ep'
-            if scmd in cmd2opcode:
-                if len(module_argv) < 4:
-                    self.logger.log_error(f'Expected module options: -a replace_op,{scmd},<reg_address>,<value>')
-                    return ModuleResult.ERROR
-                reg_address = int(module_argv[2], 16)
-                value = int(module_argv[3], 16)
-                sts = self.modify_s3_reg(cmd2opcode[scmd], reg_address, value)
-                if sts:
-                    self.logger.log(f'[*] After sleep/resume, check the value of register 0x{reg_address:X} is 0x{value:X}')
-            elif 'dispatch' == scmd:
-                sts = self.modify_s3_dispatch()
-            elif 'dispatch_ep' == scmd:
-                sts = self.modify_s3_dispatch_ep()
-            elif 'mem' == scmd:
-                new_value = int(module_argv[2], 16) if len(module_argv) >= 3 else 0xB007B007
-                address = int(module_argv[3], 16) if len(module_argv) == 4 else None
-                sts = self.modify_s3_mem(address, new_value)
-            else:
-                self.logger.log_error(f'Unrecognized module command-line argument: {scmd}')
-                self.logger.log(examples_str)
-                return ModuleResult.ERROR
-        elif op == 'add_op':
-            scmd = module_argv[1].lower() if len(module_argv) > 1 else 'dispatch'
-            new_opcode = None
-            if scmd in cmd2opcode:
-                if len(module_argv) < 5:
-                    self.logger.log_error(f'Expected module options: -a add_op,{scmd},<reg_address>,<value>,<width>')
-                    return ModuleResult.ERROR
-                address = int(module_argv[2], 16)
-                value = int(module_argv[3], 16)
-                width = int(module_argv[4], 16)
-                width_val = script_width_values[width]
-                value_buff = struct.pack(f'<{script_width_formats[width_val]}', value)
-
-                if cmd2opcode[scmd] in write_opcodes:
-                    new_opcode = op_io_pci_mem(cmd2opcode[scmd], None, width_val, address, 0, 1, value_buff, None, None)
-                else:
-                    self.logger.log_error(f'Unsupported opcode: {scmd}')
-                    self.logger.log(examples_str)
-                    return ModuleResult.ERROR
-            elif 'dispatch' == scmd:
-                if len(module_argv) < 3:
-                    (smram_base, _, _) = self.cs.cpu.get_SMRAM()
-                    (_, entrypoint) = self.cs.mem.alloc_physical_mem(0x1000, smram_base)
-                    self.cs.mem.write_physical_mem(entrypoint, len(self.DISPATCH_ENTRYPOINT_INSTR), self.DISPATCH_ENTRYPOINT_INSTR)
-                else:
-                    entrypoint = int(module_argv[2], 16)
-                new_opcode = op_dispatch(dispatch_opcode, None, entrypoint)
-            else:
-                self.logger.log_error(f'Unrecognized opcode: {scmd}')
-                self.logger.log(examples_str)
-                return ModuleResult.ERROR
-
-            sts = self.modify_s3_add(new_opcode)
-        else:
-            self.logger.log_error(f'Unrecognized module command-line argument: {op}')
-            self.logger.log(examples_str)
-            return ModuleResult.ERROR
-
-        if sts:
-            self.logger.log_passed('The script has been modified. Go to sleep..')
-            return ModuleResult.PASSED
-        else:
-            return ModuleResult.FAILED

-

-
-

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-            

-          

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-      

-      
-      

-    

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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/uefi/scan_blocked.html b/_modules/chipsec/modules/tools/uefi/scan_blocked.html
deleted file mode 100644
index a631a25a..00000000
--- a/_modules/chipsec/modules/tools/uefi/scan_blocked.html
+++ /dev/null
@@ -1,291 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.uefi.scan_blocked — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
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-
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-            
-  
Source code for chipsec.modules.tools.uefi.scan_blocked
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-This module checks current contents of UEFI firmware ROM or specified firmware image for blocked EFI binaries
-which can be EFI firmware volumes, EFI executable binaries (PEI modules, DXE drivers..) or EFI sections.
-The module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes
-or contents matching specified regular expressions.
-
-Important! This module can only detect what it knows about from its config file.
-If a bad or vulnerable binary is not detected then its 'signature' needs to be added to the config.
-
-Usage:
-  ``chipsec_main.py -i -m tools.uefi.scan_blocked [-a <fw_image>,<blockedlist>]``
-    - ``fw_image``	Full file path to UEFI firmware image. If not specified, the module will dump firmware image directly from ROM
-    - ``blockedlist``	JSON file with configuration of blocked EFI binaries (default = ``blockedlist.json``). Config file should be located in the same directory as this module
-
-Examples:
-
-    >>> chipsec_main.py -m tools.uefi.scan_blocked
-
-Dumps UEFI firmware image from flash memory device, decodes it and checks for blocked EFI modules defined in the default config ``blockedlist.json``
-
-    >>> chipsec_main.py -i --no_driver -m tools.uefi.scan_blocked -a uefi.rom,blockedlist.json
-
-Decodes ``uefi.rom`` binary with UEFI firmware image and checks for blocked EFI modules defined in ``blockedlist.json`` config
-
-.. note::
-    - ``-i`` and ``--no_driver`` arguments can be used in this case because the test does not depend on the platform
-      and no kernel driver is required when firmware image is specified
-
-"""
-
-import json
-import os
-
-from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS
-from chipsec.hal.spi_uefi import search_efi_tree, build_efi_model, EFIModuleType
-from chipsec.hal.uefi import UEFI
-from chipsec.hal.spi import SPI, BIOS
-from chipsec.hal.uefi_search import check_match_criteria
-from chipsec.file import read_file, get_main_dir
-
-TAGS = [MTAG_BIOS]
-
-DEF_FWIMAGE_FILE = 'fw.bin'
-
-
-

-[docs]
-class scan_blocked(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.uefi = UEFI(self.cs)
-        self.cfg_name = 'blockedlist.json'
-        self.image = None
-        self.efi_blockedlist = None
-        self.cpuid = None
-
-

-[docs]
-    def is_supported(self):
-        return True

-
-
-

-[docs]
-    def blockedlist_callback(self, efi_module):
-        return check_match_criteria(efi_module, self.efi_blockedlist, self.logger, self.cpuid)

-
-
-

-[docs]
-    def check_blockedlist(self):
-        res = ModuleResult.PASSED
-
-        self.logger.log(f'[*] Searching for EFI binaries that match criteria from \'{self.cfg_name}\':')
-        for k in self.efi_blockedlist.keys():
-            entry = self.efi_blockedlist[k]
-            self.logger.log(f'    {k:16} - {entry["description"] if "description" in entry else ""}')
-
-        # parse the UEFI firmware image and look for EFI modules matching the block-list
-        efi_tree = build_efi_model(self.image, None)
-
-        match_types = EFIModuleType.SECTION_EXE
-        matching_modules = search_efi_tree(efi_tree, self.blockedlist_callback, match_types)
-        found = len(matching_modules) > 0
-        self.logger.log('')
-        if found:
-            res = ModuleResult.WARNING
-            self.logger.log_warning("Blocked EFI binary found in the UEFI firmware image")
-        else:
-            self.logger.log_passed("Didn't find any blocked EFI binary")
-        return res

-
-
-

-[docs]
-    def usage(self):
-        self.logger.log(__doc__.replace('`', ''))

-
-
-    # --------------------------------------------------------------------------
-    # run( module_argv )
-    # Required function: run here all tests from this module
-    # --------------------------------------------------------------------------
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Check for blocked EFI binaries in UEFI firmware")
-
-        self.usage()
-
-        image_file = DEF_FWIMAGE_FILE
-        if len(module_argv) == 0:
-            # Read firmware image directly from SPI flash memory
-            self.spi = SPI(self.cs)
-            (base, limit, _) = self.spi.get_SPI_region(BIOS)
-            image_size = limit + 1 - base
-            self.logger.log(f'[*] Dumping FW image from ROM to {image_file}: 0x{base:08X} bytes at [0x{limit:08X}:0x{image_size:08X}]')
-            self.logger.log("[*] This may take a few minutes (instead, use 'chipsec_util spi dump')...")
-            self.spi.read_spi_to_file(base, image_size, image_file)
-            self.cpuid = self.cs.get_cpuid()
-        elif len(module_argv) > 0:
-            # Use provided firmware image
-            image_file = module_argv[0]
-            self.logger.log(f'[*] Reading FW image from file: {image_file}')
-
-        self.image = read_file(image_file)
-
-        if not self.image:
-            if len(module_argv) == 0:
-                self.logger.log_important('Unable to read SPI and generate FW image. Access may be blocked.')
-            self.logger.log_error('No FW image file to read.  Exiting!')
-            self.res = ModuleResult.ERROR
-            return self.res
-
-        # Load JSON config with blocked EFI modules
-        if len(module_argv) > 1:
-            self.cfg_name = module_argv[1]
-        cfg_pth = os.path.join(get_main_dir(), "chipsec/modules/tools/uefi", self.cfg_name)
-        with open(cfg_pth, 'r') as blockedlist_json:
-            self.efi_blockedlist = json.load(blockedlist_json)
-
-        self.res = self.check_blockedlist()
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/uefi/scan_image.html b/_modules/chipsec/modules/tools/uefi/scan_image.html
deleted file mode 100644
index 2c044b6e..00000000
--- a/_modules/chipsec/modules/tools/uefi/scan_image.html
+++ /dev/null
@@ -1,347 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.uefi.scan_image — CHIPSEC  documentation
-    
-    
-    
-    
-    
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-    
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-
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Source code for chipsec.modules.tools.uefi.scan_image
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2017-2021, Intel Security
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# Authors:
-#   Yuriy Bulygin
-#   Alex Bazhaniuk
-#
-
-"""
-The module can generate a list of EFI executables from (U)EFI firmware file or
-extracted from flash ROM, and then later check firmware image in flash ROM or
-file against this list of expected executables
-
-Usage:
-  ``chipsec_main -m tools.uefi.scan_image [-a generate|check,<json>,<fw_image>]``
-    - ``generate``	Generates a list of EFI executable binaries from the UEFI
-                        firmware image (default)
-    - ``check``		Decodes UEFI firmware image and checks all EFI executable
-                        binaries against a specified list
-    - ``json``		JSON file with configuration of allowed list EFI
-                        executables (default = ``efilist.json``)
-    - ``fw_image``	Full file path to UEFI firmware image. If not specified,
-                        the module will dump firmware image directly from ROM
-
-Examples:
-
->>> chipsec_main -m tools.uefi.scan_image
-
-Creates a list of EFI executable binaries in ``efilist.json`` from the firmware
-image extracted from ROM
-
->>> chipsec_main -i -n -m tools.uefi.scan_image -a generate,efilist.json,uefi.rom
-
-Creates a list of EFI executable binaries in ``efilist.json`` from ``uefi.rom``
-firmware binary
-
->>> chipsec_main -i -n -m tools.uefi.scan_image -a check,efilist.json,uefi.rom
-
-Decodes ``uefi.rom`` UEFI firmware image binary and checks all EFI executables
-in it against a list defined in ``efilist.json``
-
-.. note::
-    - ``-i`` and ``-n`` arguments can be used when specifying firmware file
-      because the module doesn't depend on the platform and doesn't need kernel driver
-"""
-
-import json
-import os
-
-from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS
-
-from chipsec.hal.uefi import UEFI
-from chipsec.hal.spi import SPI, BIOS
-from chipsec.hal.uefi_fv import EFI_MODULE, EFI_SECTION, SECTION_NAMES, EFI_SECTION_PE32
-from chipsec.hal.spi_uefi import build_efi_model, search_efi_tree, EFIModuleType, UUIDEncoder
-from chipsec.file import write_file, read_file
-
-TAGS = [MTAG_BIOS]
-
-DEF_FWIMAGE_FILE = 'fw.bin'
-DEF_EFILIST_FILE = 'efilist.json'
-
-
-

-[docs]
-class scan_image(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.uefi = UEFI(self.cs)
-        self.image = None
-        self.efi_list = {}
-        self.suspect_modules = {}
-        self.duplicate_list = []
-
-

-[docs]
-    def is_supported(self):
-        return True

-
-
-    #
-    # callbacks to uefi_search.check_match_criteria
-    #
-

-[docs]
-    def genlist_callback(self, efi_module: EFI_MODULE) -> None:
-        md = {}
-        if type(efi_module) == EFI_SECTION:
-            if efi_module.SHA256:
-                md["sha1"] = efi_module.SHA1
-            if efi_module.parentGuid:
-                md["guid"] = efi_module.parentGuid
-            if efi_module.ui_string:
-                md["name"] = efi_module.ui_string
-            if efi_module.Name and efi_module.Name != SECTION_NAMES[EFI_SECTION_PE32]:
-                md["type"] = efi_module.Name
-            if efi_module.SHA256 in self.efi_list.keys():
-                self.duplicate_list.append(efi_module.SHA256)
-            else:
-                self.efi_list[efi_module.SHA256] = md
-        else:
-            pass

-
-
-    #
-    # Generates new list of EFI executable binaries
-    #
-

-[docs]
-    def generate_efilist(self, json_pth: str) -> int:
-        self.logger.log("[*] Generating a list of EFI executables from firmware image...")
-        efi_tree = build_efi_model(self.image, None)
-        search_efi_tree(efi_tree, self.genlist_callback, EFIModuleType.SECTION_EXE, True)
-        self.logger.log(f'[*] Found {len(self.efi_list):d} EFI executables in UEFI firmware image \'{self.image_file}\'')
-        self.logger.log(f'[*] Found {len(self.duplicate_list)} duplicate executables')
-        self.logger.log_verbose(f'\t{chr(10).join(i for i in self.duplicate_list)}')
-        self.logger.log(f'[*] Creating JSON file \'{json_pth}\'...')
-        write_file(f'{json_pth}', json.dumps(self.efi_list, indent=2, separators=(',', ': '), cls=UUIDEncoder))
-        return ModuleResult.PASSED

-
-
-    #
-    # Checks EFI executable binaries against allowed list
-    #
-

-[docs]
-    def check_list(self, json_pth: str) -> int:
-        with open(json_pth) as data_file:
-            self.efilist = json.load(data_file)
-
-        self.logger.log(f'[*] Checking EFI executables against the list \'{json_pth}\'')
-
-        # parse the UEFI firmware image and look for EFI modules matching list
-        # - match only executable EFI sections (PE/COFF, TE)
-        # - find all occurrences of matching EFI modules
-        efi_tree = build_efi_model(self.image, None)
-        search_efi_tree(efi_tree, self.genlist_callback, EFIModuleType.SECTION_EXE, True)
-        self.logger.log(f'[*] Found {len(self.efi_list):d} EFI executables in UEFI firmware image \'{self.image_file}\'')
-
-        for m in self.efi_list:
-            if not (m in self.efilist):
-                self.suspect_modules[m] = self.efi_list[m]
-                guid = self.efi_list[m]["guid"] if 'guid' in self.efi_list[m] else '?'
-                name = self.efi_list[m]["name"] if 'name' in self.efi_list[m] else '<unknown>'
-                sha1 = self.efi_list[m]["sha1"] if 'sha1' in self.efi_list[m] else ''
-                self.logger.log_important(f'Found EFI executable not in the list:\n    {m} (sha256)\n    {sha1} (sha1)\n    {{{guid}}}\n    {name}')
-
-        if len(self.suspect_modules) > 0:
-            self.logger.log_warning(f'Found {len(self.suspect_modules):d} EFI executables not in the list \'{json_pth}\'')
-            return ModuleResult.WARNING
-        else:
-            self.logger.log_passed(f'All EFI executables match the list \'{json_pth}\'')
-            return ModuleResult.PASSED

-
-
-

-[docs]
-    def usage(self):
-        self.logger.log(__doc__.replace('`', ''))

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Simple list generation/checking for (U)EFI firmware")
-
-        self.res = ModuleResult.NOTAPPLICABLE
-
-        op = module_argv[0] if len(module_argv) > 0 else 'generate'
-
-        if op in ['generate', 'check']:
-
-            if len(module_argv) <= 2:
-                self.usage()
-                return self.res
-            elif len(module_argv) > 2:
-                json_file = module_argv[1]
-                image_file = module_argv[2]
-                self.logger.log(f'[*] Reading firmware from \'{image_file}\'...')
-            else:
-                image_file = DEF_FWIMAGE_FILE
-                json_file = DEF_EFILIST_FILE
-                self.spi = SPI(self.cs)
-                (base, limit, _) = self.spi.get_SPI_region(BIOS)
-                image_size = limit + 1 - base
-                self.logger.log(f'[*] Dumping firmware image from ROM to \'{image_file}\': 0x{image_size:08X} bytes at [0x{base:08X}:0x{limit:08X}]')
-                self.spi.read_spi_to_file(base, image_size, image_file)
-
-            self.image_file = image_file
-            self.image = read_file(image_file)
-            json_pth = os.path.abspath(json_file)
-
-            if op == 'generate':
-                if os.path.exists(json_pth):
-                    self.logger.log_error(f'JSON file \'{json_file}\' already exists. Exiting...')
-                    self.res = ModuleResult.ERROR
-                else:
-                    self.res = self.generate_efilist(json_pth)
-            elif op == 'check':
-                if not os.path.exists(json_pth):
-                    self.logger.log_error(f'JSON file \'{json_file}\' doesn\'t exist. Exiting...')
-                    self.res = ModuleResult.ERROR
-                else:
-                    self.res = self.check_list(json_pth)
-
-        elif op == 'help':
-            self.usage()
-        else:
-            self.logger.log_error("Unrecognized command-line argument to the module")
-            self.usage()
-
-        return self.res

-

-
-

-
-            

-          

-        

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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/uefi/uefivar_fuzz.html b/_modules/chipsec/modules/tools/uefi/uefivar_fuzz.html
deleted file mode 100644
index f8f0012f..00000000
--- a/_modules/chipsec/modules/tools/uefi/uefivar_fuzz.html
+++ /dev/null
@@ -1,369 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.uefi.uefivar_fuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
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-     
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-      
-
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Source code for chipsec.modules.tools.uefi.uefivar_fuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2022, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-"""
-The module is fuzzing UEFI Variable interface.
-
-The module is using UEFI SetVariable interface to write new UEFI variables
-to SPI flash NVRAM with randomized name/attributes/GUID/data/size.
-
-Usage:
-    ``chipsec_main -m tools.uefi.uefivar_fuzz [-a <options>]``
-
-Options:
-
-    ``[-a <test>,<iterations>,<seed>,<test_case>]``
-
-        - ``test``       : UEFI variable interface to fuzz (all, name, guid, attrib, data, size)
-        - ``iterations`` : Number of tests to perform (default = 1000)
-        - ``seed``       : RNG seed to use
-        - ``test_case``  : Test case # to skip to (combined with seed, can be used to skip to failing test)
-
-    All module arguments are optional
-
-Examples::
-    >>> chipsec_main.py -m tools.uefi.uefivar_fuzz
-    >>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a all,100000
-    >>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a data,1000,123456789
-    >>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a name,1,123456789,94
-
-.. note::
-    - This module returns a WARNING by default to indicate that a manual review is needed.
-    - Writes may generate 'ERROR's, this can be expected behavior if the environment rejects them.
-
-.. warning::
-    - This module modifies contents of non-volatile SPI flash memory (UEFI Variable NVRAM).
-    - This may render system UNBOOTABLE if firmware doesn't properly handle variable update/delete operations.
-
-.. important::
-    - Evaluate the platform for expected behavior to determine PASS/FAIL.
-    - Behavior can include platform stability and retaining protections.
-
-"""
-
-import random
-from time import time
-from uuid import uuid4, UUID
-import struct
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.file import write_file
-from chipsec.hal.uefi import UEFI
-from chipsec.defines import bytestostring
-
-from chipsec.fuzzing import primitives as prim
-
-
-

-[docs]
-class uefivar_fuzz(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self._uefi = UEFI(self.cs)
-
-

-[docs]
-    def is_supported(self):
-        supported = self.cs.helper.EFI_supported()
-        if not supported:
-            self.logger.log_important("OS does not support UEFI Runtime API.  Skipping module.")
-            self.res = ModuleResult.NOTAPPLICABLE
-        return supported

-
-
-

-[docs]
-    def rnd(self, n=1):
-        rnum = b''
-        for j in range(n):
-            rnum += struct.pack("B", random.randint(0, 255))
-        return rnum

-
-
-

-[docs]
-    def usage(self):
-        self.logger.log(__doc__.translate({ord('`'): None}))
-        return True

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Fuzz UEFI Variable Interface")
-
-        self.logger.log_warning("Are you sure you want to continue fuzzing UEFI variable interface?")
-        s = input("Type 'yes' to continue > ")
-        if s.lower() not in ['yes', 'y']:
-            return
-
-        # Default options
-        _NAME = 'FuzzerVarName'
-        _GUID = UUID('414C4694-F4CF-0525-69AF-C99C8596530F')
-        _ATTRIB = 0x07
-        _SIZE = 0x08
-        _DATA = struct.pack("B", 0x41) * _SIZE
-
-        ITERATIONS = 1000
-        SEED = int(time())
-        CASE = 1
-        BOUND_STR = 255  # tested value that can be increased or decreased to fit the limit bounds
-        BOUND_INT = 1000
-
-        FUZZ_NAME = True
-        FUZZ_GUID = True
-        FUZZ_ATTRIB = True
-        FUZZ_DATA = True
-        FUZZ_SIZE = True
-
-        # Init fuzzing primitives
-        name_prim = prim.string(value=_NAME, max_len=BOUND_STR)
-        attrib_prim = prim.dword(value=_ATTRIB)  # i think the attrib field is 4 bytes large?
-        data_prim = prim.random_data(value=_DATA, min_length=0, max_length=BOUND_INT)
-
-        help_text = False
-
-        if len(module_argv):
-            fz_cli = module_argv[0].lower()
-            if 'all' != fz_cli:
-                FUZZ_NAME = False
-                FUZZ_GUID = False
-                FUZZ_ATTRIB = False
-                FUZZ_DATA = False
-                FUZZ_SIZE = False
-
-                if 'name' == fz_cli:
-                    FUZZ_NAME = True
-                elif 'guid' == fz_cli:
-                    FUZZ_GUID = True
-                elif 'attrib' == fz_cli:
-                    FUZZ_ATTRIB = True
-                elif 'data' == fz_cli:
-                    FUZZ_DATA = True
-                elif 'size' == fz_cli:
-                    FUZZ_SIZE = True
-                else:
-                    help_text = self.usage()
-
-            if len(module_argv) > 1:
-                if module_argv[1].isdigit():
-                    ITERATIONS = int(module_argv[1])
-                else:
-                    help_text = self.usage()
-
-            if len(module_argv) > 2:
-                if module_argv[2].isdigit():
-                    SEED = int(module_argv[2])
-                else:
-                    help_text = self.usage()
-
-            if len(module_argv) > 3:
-                if module_argv[3].isdigit():
-                    CASE = int(module_argv[3])
-                else:
-                    help_text = self.usage()
-
-        if not help_text:
-            random.seed(SEED)
-            write_file('SEED.txt', str(SEED))
-
-            if not len(module_argv):
-                fz_cli = 'all'
-            self.logger.log(f'Test      : {fz_cli}')
-            self.logger.log(f'Iterations: {ITERATIONS:d}')
-            self.logger.log(f'Seed      : {SEED:d}')
-            self.logger.log(f'Test case : {CASE:d}')
-            self.logger.log('')
-            for count in range(1, ITERATIONS + CASE):
-                if FUZZ_NAME:
-                    _NAME = ''
-                    if name_prim.mutate():
-                        _NAME = name_prim.render()
-                    else:
-                        # if mutate() returns false, we need to reload the primitive
-                        name_prim = prim.string(value=_NAME, max_len=BOUND_STR)
-                        _NAME = name_prim.render()
-
-                if FUZZ_GUID:
-                    _GUID = uuid4()
-
-                if FUZZ_ATTRIB:
-                    if attrib_prim.mutate():
-                        _ATTRIB = attrib_prim.render()
-                    else:
-                        attrib_prim = prim.dword(value=_ATTRIB)
-                        _ATTRIB = attrib_prim.render()
-
-                if FUZZ_DATA:
-                    if data_prim.mutate():
-                        _DATA = data_prim.render()
-                    else:
-                        data_prim = prim.random_data(value=_DATA, min_length=0, max_length=BOUND_INT)
-                        data_prim.mutate()
-                        _DATA = data_prim.render()
-
-                if FUZZ_SIZE:
-                    if _DATA:
-                        _SIZE = random.randrange(len(_DATA))
-                    else:
-                        _SIZE = random.randrange(1024)
-
-                if count < CASE:
-                    continue
-
-                self.logger.log(f'  Running test #{count:d}:')
-                self.logger.flush()
-                status = self._uefi.set_EFI_variable(bytestostring(_NAME), str(_GUID), _DATA, _SIZE, _ATTRIB)
-                self.logger.log(status)
-                status = self._uefi.delete_EFI_variable(bytestostring(_NAME), str(_GUID))
-                self.logger.log(status)
-
-        self.logger.log_warning('Fuzzing complete: platform is in an unknown state.')
-        self.logger.log_important('Evaluate the platform for expected behavior to determine PASS/FAIL')
-        self.logger.log_important('Behavior can include platform stability and retaining protections.')
-
-        self.res = ModuleResult.WARNING
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/common.html b/_modules/chipsec/modules/tools/vmm/common.html
deleted file mode 100644
index 70c20b61..00000000
--- a/_modules/chipsec/modules/tools/vmm/common.html
+++ /dev/null
@@ -1,511 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.common — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.common
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-"""
-Common functionality for VMM related modules/tools
-"""
-
-import sys
-import socket
-import struct
-import random
-import os.path
-import json
-import pprint
-from random import getrandbits, randint
-from time import strftime, localtime
-from chipsec.module_common import BaseModule
-from chipsec.defines import DD
-from typing import Dict, List, Tuple
-
-
-

-[docs]
-class BaseModuleDebug(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.debug = False
-        self.prompt = ''
-
-    def __del__(self) -> None:
-        pass
-
-    ##
-    # msg
-    ##
-

-[docs]
-    def msg(self, message: str) -> None:
-        sys.stdout.write(f'[{self.prompt}]  {message}\n')
-        return

-
-
-    ##
-    # err
-    ##
-

-[docs]
-    def err(self, message: str) -> None:
-        sys.stdout.write(f'[{self.prompt}]  **** ERROR: {message}\n')
-        return

-
-
-    ##
-    # dbg
-    ##
-

-[docs]
-    def dbg(self, message: str):
-        if self.debug:
-            sys.stdout.write(f'[{self.prompt}]  {message}\n')
-        return

-
-
-    ##
-    # hex
-    ##
-

-[docs]
-    def hex(self, title: str, data:str, w=16) -> None:
-        if title and data:
-            title = f'{"-" * 6}{title}{"-" * w * 3}'
-            sys.stdout.write(f'[{self.prompt}]  {title[:w * 3 + 15]}')
-        a = 0
-        for c in data:
-            if a % w == 0:
-                sys.stdout.write(f'\n[{self.prompt}]  {a:08X}: ')
-            elif a % w % 8 == 0:
-                sys.stdout.write('| ')
-            sys.stdout.write('{:02X} '.format(ord(c)))
-            a = a + 1
-        sys.stdout.write('\n')
-        return

-
-
-    ##
-    # fatal
-    ##
-

-[docs]
-    def fatal(self, message: str) -> None:
-        sys.stdout.write(f'[{self.prompt}]  **** FATAL: {message}\n')
-        exit(1)
-        return

-
-
-    ##
-    # info_bitwise
-    ##
-

-[docs]
-    def info_bitwise(self, reg: int, desc: Dict[int, str]) -> None:
-        i = 0
-        while reg != 0:
-            if i in desc:
-                self.msg(f'       Bit {i:2d}:  {(reg & 0x1):d}  {desc[i]}')
-            i += 1
-            reg = reg >> 1
-        return

-

-
-
-
-

-[docs]
-class BaseModuleSupport(BaseModuleDebug):
-    def __init__(self):
-        BaseModuleDebug.__init__(self)
-        self.initial_data = []
-        self.path = os.path.dirname(os.path.realpath(__file__))
-        with open(os.path.join(self.path, 'hv', 'initial_data.json'), "r") as json_file:
-            self.initial_data = json.load(json_file)
-        self.statistics = {}
-        self.hv_connectionid = {}
-
-    def __del__(self) -> None:
-        # self.dump_initial_data("initial_data_auto_generated.json")
-        BaseModuleDebug.__del__(self)
-
-

-[docs]
-    def stats_reset(self) -> None:
-        self.statistics = {}
-        return

-
-
-

-[docs]
-    def stats_event(self, name: str) -> None:
-        self.statistics[name] = self.statistics.get(name, 0) + 1
-        return

-
-
-

-[docs]
-    def stats_print(self, title: str) -> None:
-        self.msg('')
-        self.msg(f' {title} '.center(72 - len(self.prompt), '*'))
-        for name in sorted(self.statistics, key=self.statistics.get, reverse=True):
-            self.msg(f'{name:50} : {self.statistics[name]:d}')
-        self.msg('')
-        return

-
-
-

-[docs]
-    def get_initial_data(self, statuses: List[str], vector: int, size: int, padding='\x00') -> List[str]:        
-        connectionid_message = [(' '.join([f'{x:02x}' for x in DD(k)])) for k, v in self.hv_connectionid.items() if v == 1]
-        connectionid_event = [(' '.join([f'{x:02x}' for x in DD(k)])) for k, v in self.hv_connectionid.items() if v == 2]
-        result = []
-        for status in statuses:
-            for item in self.initial_data:
-                if (int(item['vector'], 16) == vector) and (item['status'] == status):
-                    data = item['data']
-                    data = data.replace('CONNECTION_ID_MESSAGE_TYPE', random.choice(connectionid_message))
-                    data = data.replace('CONNECTION_ID_EVENT_TYPE', random.choice(connectionid_event))
-                    buffer = str(bytearray.fromhex(data)) + padding * size
-                    result.append(buffer[:size])
-        if not result:
-            result = [padding * size]
-        return result

-
-
-

-[docs]
-    def add_initial_data(self, vector: int, buffer: str, status: str) -> None:
-        found = False
-        buffer = buffer.rstrip("\x00")
-        buffer = ' '.join(f'{x:02x}' for x in buffer)
-        for item in self.initial_data:
-            if int(item['vector'], 16) == vector:
-                if item['data'] == buffer:
-                    found = True
-                    break
-        if not found:
-            self.initial_data.append({"vector": f'{vector:02X}', "status": status, "data": buffer})
-        return

-
-
-

-[docs]
-    def dump_initial_data(self, filename: str) -> None:
-        if self.initial_data:
-            with open(self.path + filename, "w") as json_file:
-                json.dump(self.initial_data, json_file, indent=4)
-        return

-

-
-
-
-

-[docs]
-class BaseModuleHwAccess(BaseModuleSupport):
-
-    ##
-    # cpuid_info
-    ##
-

-[docs]
-    def cpuid_info(self, eax: int, ecx: int, desc: str) -> Tuple[int, int, int, int]:
-        val = self.cs.cpu.cpuid(eax, ecx)
-        self.msg('')
-        self.msg(f'CPUID.{eax:X}h.{ecx:X}h > {desc}')
-        self.msg(f'EAX: 0x{val[0]:08X} EBX: 0x{val[1]:08X} ECX: 0x{val[2]:08X} EDX: 0x{val[3]:08X}')
-        return val

-
-
-    ##
-    # rdmsr
-    ##
-

-[docs]
-    def rdmsr(self, msr: int) -> Tuple[int, int]:
-        eax, edx = (0, 0)
-        temp = sys.stdout
-        sys.stdout = open(os.devnull, 'wb')
-        try:
-            for tid in range(self.cs.msr.get_cpu_thread_count()):
-                (eax, edx) = self.cs.msr.read_msr(tid, msr)
-        except:
-            sys.stdout = temp
-            raise
-        sys.stdout = temp
-        return (edx, eax)

-
-
-    ##
-    # wrmsr
-    ##
-

-[docs]
-    def wrmsr(self, msr: int, value: int) -> None:
-        temp = sys.stdout
-        sys.stdout = open(os.devnull, 'wb')
-        try:
-            for tid in range(self.cs.msr.get_cpu_thread_count()):
-                self.cs.msr.write_msr(tid, msr, value & 0xFFFFFFFF, value >> 32)
-        except:
-            sys.stdout = temp
-            raise
-        sys.stdout = temp
-        return

-

-
-
-### COMMON ROUTINES ############################################################
-
-
-

-[docs]
-def weighted_choice(choices: List[Tuple[int, float]]) -> int:
-    total = sum(w for c, w in choices)
-    r = random.uniform(0, total)
-    x = 0
-    for c, w in choices:
-        if x + w >= r:
-            return c
-        x += w
-    assert False, "Invalid parameters"

-
-
-
-

-[docs]
-def rand_dd(n: int, rndbytes: int = 1, rndbits: int = 1) -> List[int]:
-    weights = [(0x00000000, 0.85), (0xFFFFFFFF, 0.10), (0xFFFF0000, 0.05), (0xFFFFFF00, 0.05)]
-    buffer = b''
-    for i in range(n):
-        buffer += DD(weighted_choice(weights))
-    buffer = list(buffer)
-    for i in range(rndbytes):
-        pos = randint(0, len(buffer) - 1)
-        buffer[pos] = randint(0, 255)
-    for i in range(rndbits):
-        pos = randint(0, len(buffer) - 1)
-        buffer[pos] = (buffer[pos]) ^ (0x1 << randint(0, 7))
-        buffer = ''.join(buffer)
-    return buffer

-
-
-
-

-[docs]
-def overwrite(buffer: bytes, string: bytes, position: int) -> bytes:
-    return buffer[:position] + string + buffer[position + len(string):]

-
-
-
-

-[docs]
-def get_int_arg(arg: str) -> int:
-    try:
-        ret = int(eval(arg))
-    except:
-        print("\n  ERROR: Invalid parameter\n")
-        exit(1)
-    return ret

-
-
-
-

-[docs]
-def hv_hciv(rep_start: int, rep_count: int, call_code: int, fast: int = 0) -> int:
-    return (((rep_start & 0x0FFF) << 48) + ((rep_count & 0x0FFF) << 32) + ((fast & 0x1) << 16) + (call_code & 0xFFFF))

-
-
-
-

-[docs]
-def uuid(id: bytes) -> str:
-    return '{{{:08X}-{:04X}-{:04X}-{:02X}{:02X}-{:02X}{:02X}{:02X}{:02X}{:02X}{:02X}}}'.format(*struct.unpack('<IHH8B', id))

-
-
-### OPTIONAL ROUTINES ##########################################################
-
-
-

-[docs]
-class session_logger:
-    def __init__(self, log: bool, details: str):
-        self.defstdout = sys.stdout
-        self.log = log
-        self.log2term = True
-        self.log2file = True
-        if self.log:
-            #            logpath = 'logs/'
-            #            logfile = '{}.log'.format(details)
-            logpath = f'logs/{strftime("%Yww%W.%w", localtime())}/'
-            logfile = f'{details}-{strftime("%H%M", localtime())}.log'
-            try:
-                os.makedirs(logpath)
-            except OSError:
-                pass
-            self.terminal = sys.stdout
-            self.logfile = open(logpath + logfile, 'a')
-
-

-[docs]
-    def write(self, message: str) -> None:
-        if self.log and self.log2term:
-            self.terminal.write(message)
-        if self.log and self.log2file:
-            self.logfile.write(message)

-
-
-

-[docs]
-    def flush(self) -> None:
-        if self.log and self.log2term:
-            self.terminal.flush()
-        if self.log and self.log2file:
-            self.logfile.flush()

-
-
-

-[docs]
-    def closefile(self) -> None:
-        if self.log:
-            self.logfile.close()
-            sys.stdout = self.defstdout

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/cpuid_fuzz.html b/_modules/chipsec/modules/tools/vmm/cpuid_fuzz.html
deleted file mode 100644
index 5c4dc754..00000000
--- a/_modules/chipsec/modules/tools/vmm/cpuid_fuzz.html
+++ /dev/null
@@ -1,278 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.cpuid_fuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.cpuid_fuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Simple CPUID VMM emulation fuzzer
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.cpuid_fuzz [-a random]``
-
-    - ``random`` : Fuzz in random order (default is sequential)
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz
-    >>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz -l log.txt
-    >>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz -a random
-
-Additional options set within the module:
-    - ``_NO_EAX_TO_FUZZ``        : No of EAX values to fuzz within each step
-    - ``_EAX_FUZZ_STEP``         : Step to fuzz range of EAX values
-    - ``_NO_ITERATIONS_TO_FUZZ`` : Number of iterations if `random` chosen
-    - ``_FUZZ_ECX_RANDOM``       : Fuzz ECX with random values?
-    - ``_MAX_ECX``               : Max ECX value
-    - ``_EXCLUDE_CPUID``         : Exclude the following EAX values from fuzzing
-    - ``_FLUSH_LOG_EACH_ITER``   : Flush log file after each iteration
-    - ``_LOG_OUT_RESULTS``       : Log output results
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import random
-from chipsec.module_common import BaseModule, ModuleResult
-
-_MODULE_NAME = 'cpuid_fuzz'
-
-#
-# We will only be fuzzing _NO_EAX_TO_FUZZ range of EAX values each _EAX_FUZZ_STEP step
-#
-_NO_EAX_TO_FUZZ = 0x100
-_EAX_FUZZ_STEP = 0x1000000
-
-# Number of iterations if value is Randomly chosen
-_NO_ITERATIONS_TO_FUZZ = 0x1000000
-
-# Control values to be passed in ECX
-_FUZZ_ECX_RANDOM = False
-# Max value of ECX when fuzzed sequentially
-_MAX_ECX = 0x100
-
-# Exclude CPUID EAX which cause VM hang/crash
-_EXCLUDE_CPUID = []
-
-# Flush log file before each fuzz iteration
-_FLUSH_LOG_EACH_ITER = False
-# Log values of EAX, EBX, ECX, EDX which CPUID returns
-_LOG_OUT_RESULTS = False
-
-
-

-[docs]
-class cpuid_fuzz (BaseModule):
-
-

-[docs]
-    def fuzz_CPUID(self, eax_start, random_order = False):
-        eax_range = _NO_EAX_TO_FUZZ
-        eax_end = eax_start + eax_range
-        self.logger.log(f'[*] Fuzzing CPUID with EAX in range 0x{eax_start:08X}:0x{eax_end:08X}..')
-        it = 0
-        if random_order:
-            it_max = _NO_ITERATIONS_TO_FUZZ
-        else:
-            it_max = eax_range
-
-        while it < it_max:
-            if random_order:
-                eax = random.randint(eax_start, eax_end)
-            else:
-                eax = eax_start + it
-            if _FLUSH_LOG_EACH_ITER:
-                self.logger.flush()
-            if eax not in _EXCLUDE_CPUID:
-                self.logger.log(f'[*] CPUID EAX: 0x{eax:08X}')
-                if _FUZZ_ECX_RANDOM:
-                    ecx = random.randint(0, 0xFFFFFFFF)
-                    (r_eax, r_ebx, r_ecx, r_edx) = self.cs.cpu.cpuid(eax, ecx)
-                else:
-                    for ecx in range(_MAX_ECX):
-                        self.logger.log(f'  > ECX: 0x{ecx:08X}')
-                        if _FLUSH_LOG_EACH_ITER:
-                            self.logger.flush()
-                        (r_eax, r_ebx, r_ecx, r_edx) = self.cs.cpu.cpuid(eax, ecx)
-                        if _LOG_OUT_RESULTS:
-                            self.logger.log(f'    Out: EAX=0x{r_eax:08X}, EBX=0x{r_ebx:08X}, ECX=0x{r_ecx:08X}, EDX=0x{r_edx:08X}')
-            it += 1
-        return True

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("CPUID Fuzzer")
-
-        _random_order = False
-        if (len(module_argv) > 0) and ('random' == module_argv[0]):
-            _random_order = True
-
-        self.logger.log(f'[*] Configuration:')
-        self.logger.log(f'    Mode: {"random" if _random_order else "sequential"}')
-        self.logger.log(f'    Step to fuzz range of EAX values (_EAX_FUZZ_STEP): 0x{_EAX_FUZZ_STEP:X}')
-        self.logger.log(f'    No of EAX values to fuzz within each step (_NO_EAX_TO_FUZZ): 0x{_NO_EAX_TO_FUZZ:X}')
-        self.logger.log(f'    Fuzz ECX with random values? (_FUZZ_ECX_RANDOM): {_FUZZ_ECX_RANDOM:d}')
-        self.logger.log(f'    Max ECX value (_MAX_ECX): 0x{_MAX_ECX:08X}')
-        self.logger.log(f'    Exclude the following EAX values from fuzzing (_EXCLUDE_CPUID): {str(_EXCLUDE_CPUID)}')
-        self.logger.log(f'    Flush log file after each iteration (_FLUSH_LOG_EACH_ITER): {_FLUSH_LOG_EACH_ITER:d}')
-        self.logger.log(f'    Log output results (_LOG_OUT_RESULTS): {_LOG_OUT_RESULTS:d}')
-
-        steps = 0x100000000 // _EAX_FUZZ_STEP
-        for s in range(steps):
-            self.fuzz_CPUID(s * _EAX_FUZZ_STEP, _random_order)
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/ept_finder.html b/_modules/chipsec/modules/tools/vmm/ept_finder.html
deleted file mode 100644
index 2035d220..00000000
--- a/_modules/chipsec/modules/tools/vmm/ept_finder.html
+++ /dev/null
@@ -1,411 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.ept_finder — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.ept_finder
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-"""
-Extended Page Table (EPT) Finder
-
-Usage:
-   ``chipsec_main -m tools.vmm.ept_finder [-a dump,<file_name>|file,<file_name>,<revision_id>]``
-
-    - ``dump``          : Dump contents
-    - ``file``          : Load contents from file
-    - ``<file_name>``   : File name to read from or dump to
-    - ``<revision_id>`` : Revision ID (hex)
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.ept_finder
-    >>> chipsec_main.py -i -m tools.vmm.ept_finder -a dump,my_file.bin
-    >>> chipsec_main.py -i -m tools.vmm.ept_finder -a file,my_file.bin,0x0
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import os
-import struct
-import glob
-
-from chipsec.logger import logger
-from chipsec.file import write_file
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.hal.paging import c_extended_page_tables
-
-
-

-[docs]
-class c_extended_page_tables_from_file(c_extended_page_tables):
-    def __init__(self, cs, read_from_file, par):
-        c_extended_page_tables.__init__(self, cs)
-        self.read_from_file = read_from_file
-        self.par = par
-
-

-[docs]
-    def readmem(self, name, addr, size=4096):
-        if self.read_from_file:
-            for (pa, end_pa, source) in self.par:
-                if (pa <= addr) and (addr + size <= end_pa):
-                    source.seek(addr - pa)
-                    return source.read(size)
-            logger().log_error("Invalid memory address: {:016x}-{:016x}".format(addr, addr + size))
-            return '\xFF' * size
-        return self.cs.mem.read_physical_mem(addr, size)

-

-
-
-
-

-[docs]
-class ept_finder(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.read_from_file = False
-        self.par = []
-
-

-[docs]
-    def read_physical_mem(self, addr, size=0x1000):
-        if self.read_from_file:
-            for (pa, end_pa, source) in self.par:
-                if (pa <= addr) and (addr + size <= end_pa):
-                    source.seek(addr - pa)
-                    return source.read(size)
-            self.logger.log_error("Invalid memory address: {:016x}-{:016x}".format(addr, addr + size))
-            return '\xFF' * size
-        return self.cs.mem.read_physical_mem(addr, size)

-
-
-

-[docs]
-    def read_physical_mem_dword(self, addr):
-        return struct.unpack("<L", self.read_physical_mem(addr, 4))[0]

-
-
-

-[docs]
-    def get_memory_ranges(self):
-        MASK = 0xFFFFFFFFFFFFF000
-        tsegmb = None
-        touud = None
-
-        if self.cs.is_register_defined('PCI0.0.0_TSEGMB'):
-            tsegmb = self.cs.read_register('PCI0.0.0_TSEGMB') & MASK
-        else:
-            self.logger.log_error("Couldn't find definition of required registers: TSEGMB")
-
-        if self.cs.is_register_defined('PCI0.0.0_TOUUD'):
-            touud = self.cs.read_register('PCI0.0.0_TOUUD') & MASK
-        else:
-            self.logger.log_error("Couldn't find definition of required registers: TOUUD")
-
-        par = []
-        if not (tsegmb is None):
-            par.append((0x00000000, tsegmb, None))
-        if not (touud is None):
-            par.append((0x100000000, touud, None))
-
-        return par

-
-
-

-[docs]
-    def find_vmcs_by_ept(self, ept_list, revision_id):
-        EPTP_OFFSET = 0x0140
-        MASK = 0xFFFFFFFFFFFFF000
-        vmcs_list = []
-        for (pa, end_pa, _) in self.par:
-            while pa < end_pa:
-                revid = self.read_physical_mem_dword(pa)
-                eptp = self.read_physical_mem_dword(pa + EPTP_OFFSET)
-                eptp += self.read_physical_mem_dword(pa + EPTP_OFFSET + 4) << 32
-                if (eptp & MASK in ept_list) and (revision_id == revid):
-                    vmcs_list.append(pa)
-                pa += 0x1000
-        return vmcs_list

-
-
-

-[docs]
-    def find_ept_pt(self, pt_addr_list, mincount, level):
-        pt_list = {}
-        for (pa, end_pa, _) in self.par:
-            while pa < end_pa:
-                page = struct.unpack('<512Q', self.read_physical_mem(pa))
-                count = 0
-                allzeros = True
-                topalike = True
-                reserved = False
-                for i in range(512):
-                    big_page = ((page[i] >> 7) & 0x1) == 1
-                    memtype = ((page[i] >> 3) & 0x7)
-
-                    if level == 4:
-                        reserved_bits_mask = 0x000FFF0000000000
-                    elif level == 3:
-                        if big_page:
-                            reserved_bits_mask = 0x000FFF00001FF000
-                        else:
-                            reserved_bits_mask = 0x000FFF0000000078
-                    elif level == 2:
-                        if big_page:
-                            reserved_bits_mask = 0x000FFF003FFFF000
-                        else:
-                            reserved_bits_mask = 0x000FFF0000000078
-                    elif level == 1:
-                        reserved_bits_mask = 0x000FFF00000000F8
-
-                    if (page[i] & reserved_bits_mask) != 0:
-                        reserved = True
-                        break
-
-                    if (level == 4) or (level in [2, 3] and big_page):
-                        if memtype not in [0, 1, 4, 5, 6]:
-                            reserved = True
-                            break
-
-                    if page[i] != 0:
-                        allzeros = False
-                        if i >= 8:
-                            topalike = False
-
-                    if (page[i] & 0x0000FFFFFFFFF000) in pt_addr_list:
-                        count += 1
-
-                if not reserved and not allzeros:
-                    if level == 1:
-                        if topalike and (page[0] & 0x0000FFFFFFFFF000) in pt_addr_list:
-                            pt_list[pa] = 1
-                    elif count >= mincount:
-                        pt_list[pa] = 1
-                pa += 0x1000
-        return pt_list

-
-
-

-[docs]
-    def dump_dram(self, filename, pa, end_pa, buffer_size=0x100000):
-        with open(filename, "wb") as dram:
-            self.logger.log('[*] Dumping memory to {} ...'.format(filename))
-            while pa < end_pa:
-                dram.write(self.cs.mem.read_physical_mem(pa, min(end_pa - pa, buffer_size)))
-                pa += buffer_size
-        return

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("EPT Finder")
-
-        self.read_from_file = (len(module_argv) > 0) and (module_argv[0] == "file")
-
-        if self.read_from_file:
-            if len(module_argv) == 3:
-                revision_id = int(module_argv[2], 16)
-                pattern = "{}.dram_*".format(module_argv[1])
-                filenames = glob.glob(pattern)
-                for name in filenames:
-                    addr = name[len(pattern) - 1:]
-                    addr = 0 if addr == "lo" else 0x100000000 if addr == "hi" else int(addr, 16)
-                    size = os.stat(name).st_size
-                    self.logger.log("  Mapping file to address: 0x{:012x}  size: 0x{:012x}  name: {}".format(addr, size, name))
-                    self.par.append((addr, addr + size, open(name, "rb")))
-            else:
-                self.logger.log_error('Invalid parameters')
-                self.logger.log(self.__doc__.replace('`', ''))
-                return ModuleResult.ERROR
-        else:
-            revision_id = self.cs.msr.read_msr(0, 0x480)[0]
-            self.par = self.get_memory_ranges()
-
-        if len(self.par) == 0:
-            self.logger.log_error("Memory ranges are not defined!")
-            return ModuleResult.ERROR
-
-        if (len(module_argv) == 2) and (module_argv[0] == "dump"):
-            for (pa, end_pa, _) in self.par:
-                postfix = "lo" if pa == 0x0 else "hi" if pa == 0x100000000 else "0x{:08x}".format(pa)
-                filename = "{}.dram_{}".format(module_argv[1], postfix)
-                self.dump_dram(filename, pa, end_pa)
-            return ModuleResult.PASSED
-
-        self.logger.log('[*] Searching Extended Page Tables ...')
-        ept_pt_list = self.find_ept_pt({}, 0, 4)
-        self.logger.log('[*] Found PTs  : {:d}'.format(len(ept_pt_list)))
-        ept_pd_list = self.find_ept_pt(ept_pt_list, 4, 3)
-        self.logger.log('[*] Found PDs  : {:d}'.format(len(ept_pd_list)))
-        ept_pdpt_list = self.find_ept_pt(ept_pd_list, 1, 2)
-        self.logger.log('[*] Found PDPTs: {:d}'.format(len(ept_pdpt_list)))
-        ept_pml4_list = self.find_ept_pt(ept_pdpt_list, 1, 1)
-        self.logger.log('[*] Found PML4s: {:d}'.format(len(ept_pml4_list)))
-        self.logger.log('[*] -> EPTP: ' + ' '.join(['{:08X}'.format(x) for x in sorted(ept_pml4_list.keys())]))
-        ept_vmcs_list = self.find_vmcs_by_ept([x for x in ept_pml4_list.keys()], revision_id)
-        self.logger.log('[*] Found VMCSs: {:d}'.format(len(ept_vmcs_list)))
-        self.logger.log('[*] -> VMCS: ' + ' '.join(['{:08X}'.format(x) for x in sorted(ept_vmcs_list)]))
-
-        try:
-            self.path = 'VMs\\'
-            os.makedirs(self.path)
-        except OSError:
-            pass
-
-        for addr in sorted(ept_vmcs_list):
-            write_file(self.path + 'vmcs_{:08x}.bin'.format(addr), self.read_physical_mem(addr))
-
-        count = 1
-        for eptp in sorted(ept_pml4_list.keys()):
-            ept = c_extended_page_tables_from_file(self.cs, self.read_from_file, self.par)
-            ept.prompt = '[VM{:d}]'.format(count)
-            ept.read_pt_and_show_status(self.path + 'ept_{:08x}'.format(eptp), 'Extended', eptp)
-            if not ept.failure:
-                ept.save_configuration(self.path + 'ept_{:08x}.py'.format(eptp))
-            count += 1
-
-        return ModuleResult.INFORMATION

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/define.html b/_modules/chipsec/modules/tools/vmm/hv/define.html
deleted file mode 100644
index f07c5fa9..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/define.html
+++ /dev/null
@@ -1,659 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.define — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.define
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2016, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V specific defines
-"""
-
-import re
-
-msrs = {
-    0x40000000: 'HV_X64_MSR_GUEST_OS_ID',
-    0x40000001: 'HV_X64_MSR_HYPERCALL',
-    0x40000002: 'HV_X64_MSR_VP_INDEX',
-    0x40000003: 'HV_X64_MSR_RESET',
-    0x40000010: 'HV_X64_MSR_VP_RUNTIME',
-    0x40000020: 'HV_X64_MSR_TIME_REF_COUNT',
-    0x40000021: 'HV_X64_MSR_REFERENCE_TSC',
-    0x40000022: 'HV_X64_MSR_TSC_FREQUENCY',
-    0x40000023: 'HV_X64_MSR_APIC_FREQUENCY',
-    0x40000070: 'HV_X64_MSR_EOI',
-    0x40000071: 'HV_X64_MSR_ICR',
-    0x40000072: 'HV_X64_MSR_TPR',
-    0x40000073: 'HV_X64_MSR_APIC_ASSIST_PAGE',
-    0x40000080: 'HV_X64_MSR_SCONTROL',
-    0x40000081: 'HV_X64_MSR_SVERSION',
-    0x40000082: 'HV_X64_MSR_SIEFP',
-    0x40000083: 'HV_X64_MSR_SIMP',
-    0x40000084: 'HV_X64_MSR_EOM',
-    0x40000090: 'HV_X64_MSR_SINT0',
-    0x40000091: 'HV_X64_MSR_SINT1',
-    0x40000092: 'HV_X64_MSR_SINT2',
-    0x40000093: 'HV_X64_MSR_SINT3',
-    0x40000094: 'HV_X64_MSR_SINT4',
-    0x40000095: 'HV_X64_MSR_SINT5',
-    0x40000096: 'HV_X64_MSR_SINT6',
-    0x40000097: 'HV_X64_MSR_SINT7',
-    0x40000098: 'HV_X64_MSR_SINT8',
-    0x40000099: 'HV_X64_MSR_SINT9',
-    0x4000009A: 'HV_X64_MSR_SINT10',
-    0x4000009B: 'HV_X64_MSR_SINT11',
-    0x4000009C: 'HV_X64_MSR_SINT12',
-    0x4000009D: 'HV_X64_MSR_SINT13',
-    0x4000009E: 'HV_X64_MSR_SINT14',
-    0x4000009F: 'HV_X64_MSR_SINT15',
-    0x400000B0: 'HV_X64_MSR_STIMER0_CONFIG',
-    0x400000B1: 'HV_X64_MSR_STIMER0_COUNT',
-    0x400000B2: 'HV_X64_MSR_STIMER1_CONFIG',
-    0x400000B3: 'HV_X64_MSR_STIMER1_COUNT',
-    0x400000B4: 'HV_X64_MSR_STIMER2_CONFIG',
-    0x400000B5: 'HV_X64_MSR_STIMER2_COUNT',
-    0x400000B6: 'HV_X64_MSR_STIMER3_CONFIG',
-    0x400000B7: 'HV_X64_MSR_STIMER3_COUNT',
-    0x400000C1: 'HV_X64_MSR_POWER_STATE_TRIGGER_C1',
-    0x400000C2: 'HV_X64_MSR_POWER_STATE_TRIGGER_C2',
-    0x400000C3: 'HV_X64_MSR_POWER_STATE_TRIGGER_C3',
-    0x400000D1: 'HV_X64_MSR_POWER_STATE_CONFIG_C1',
-    0x400000D2: 'HV_X64_MSR_POWER_STATE_CONFIG_C2',
-    0x400000D3: 'HV_X64_MSR_POWER_STATE_CONFIG_C3',
-    0x400000E0: 'HV_X64_MSR_STATS_PARTITION_RETAIL_PAGE',
-    0x400000E1: 'HV_X64_MSR_STATS_PARTITION_INTERNAL_PAGE',
-    0x400000E2: 'HV_X64_MSR_STATS_VP_RETAIL_PAGE',
-    0x400000E3: 'HV_X64_MSR_STATS_VP_INTERNAL_PAGE',
-    0x400000F0: 'HV_X64_MSR_GUEST_IDLE',
-    0x400000F1: 'HV_X64_MSR_SYNTH_DEBUG_CONTROL',
-    0x400000F2: 'HV_X64_MSR_SYNTH_DEBUG_STATUS',
-    0x400000F3: 'HV_X64_MSR_SYNTH_DEBUG_SEND_BUFFER',
-    0x400000F4: 'HV_X64_MSR_SYNTH_DEBUG_RECEIVE_BUFFER',
-    0x400000F5: 'HV_X64_MSR_SYNTH_DEBUG_PENDING_BUFFER',
-    0x40000100: 'HV_X64_MSR_CRASH_P0',
-    0x40000101: 'HV_X64_MSR_CRASH_P1',
-    0x40000102: 'HV_X64_MSR_CRASH_P2',
-    0x40000103: 'HV_X64_MSR_CRASH_P3',
-    0x40000104: 'HV_X64_MSR_CRASH_P4',
-    0x40000105: 'HV_X64_MSR_CRASH_CTL'
-}
-
-
-

-[docs]
-def get_msr_name(code, defvalue=''):
-    return msrs[code] if code in msrs else defvalue

-
-
-
-hypercall_status_codes = {
-    0x0000: 'HV_STATUS_SUCCESS',
-    0x0001: 'HV_RESERVED_01H',
-    0x0002: 'HV_STATUS_INVALID_HYPERCALL_CODE',
-    0x0003: 'HV_STATUS_INVALID_HYPERCALL_INPUT',
-    0x0004: 'HV_STATUS_INVALID_ALIGNMENT',
-    0x0005: 'HV_STATUS_INVALID_PARAMETER',
-    0x0006: 'HV_STATUS_ACCESS_DENIED',
-    0x0007: 'HV_STATUS_INVALID_PARTITION_STATE',
-    0x0008: 'HV_STATUS_OPERATION_DENIED',
-    0x0009: 'HV_STATUS_UNKNOWN_PROPERTY',
-    0x000A: 'HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE',
-    0x000B: 'HV_STATUS_INSUFFICIENT_MEMORY',
-    0x000C: 'HV_STATUS_PARTITION_TOO_DEEP',
-    0x000D: 'HV_STATUS_INVALID_PARTITION_ID',
-    0x000E: 'HV_STATUS_INVALID_VP_INDEX',
-    0x000F: 'HV_RESERVED_0FH',
-    0x0010: 'HV_RESERVED_10H',
-    0x0011: 'HV_STATUS_INVALID_PORT_ID',
-    0x0012: 'HV_STATUS_INVALID_CONNECTION_ID',
-    0x0013: 'HV_STATUS_INSUFFICIENT_BUFFERS',
-    0x0014: 'HV_STATUS_NOT_ACKNOWLEDGED',
-    0x0015: 'HV_RESERVED_15H',
-    0x0016: 'HV_STATUS_ACKNOWLEDGED',
-    0x0017: 'HV_STATUS_INVALID_SAVE_RESTORE_STATE',
-    0x0018: 'HV_STATUS_INVALID_SYNIC_STATE',
-    0x0019: 'HV_STATUS_OBJECT_IN_USE',
-    0x001A: 'HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO',
-    0x001B: 'HV_STATUS_NO_DATA',
-    0x001C: 'HV_STATUS_INACTIVE',
-    0x001D: 'HV_STATUS_NO_RESOURCES',
-    0x001E: 'HV_STATUS_FEATURE_UNAVAILABLE',
-    0x001F: 'HV_STATUS_PARTIAL_PACKET',
-    0x0020: 'HV_STATUS_PROCESSOR_FEATURE_SSE3_NOT_SUPPORTED',
-    0x0021: 'HV_STATUS_PROCESSOR_FEATURE_LAHFSAHF_NOT_SUPPORTED',
-    0x0022: 'HV_STATUS_PROCESSOR_FEATURE_SSSE3_NOT_SUPPORTED',
-    0x0023: 'HV_STATUS_PROCESSOR_FEATURE_SSE4_1_NOT_SUPPORTED',
-    0x0024: 'HV_STATUS_PROCESSOR_FEATURE_SSE4_2_NOT_SUPPORTED',
-    0x0025: 'HV_STATUS_PROCESSOR_FEATURE_SSE4A_NOT_SUPPORTED',
-    0x0026: 'HV_STATUS_PROCESSOR_FEATURE_XOP_NOT_SUPPORTED',
-    0x0027: 'HV_STATUS_PROCESSOR_FEATURE_POPCNT_NOT_SUPPORTED',
-    0x0028: 'HV_STATUS_PROCESSOR_FEATURE_CMPXCHG16B_NOT_SUPPORTED',
-    0x0029: 'HV_STATUS_PROCESSOR_FEATURE_ALTMOVCR8_NOT_SUPPORTED',
-    0x002A: 'HV_STATUS_PROCESSOR_FEATURE_LZCNT_NOT_SUPPORTED',
-    0x002B: 'HV_STATUS_PROCESSOR_FEATURE_MISALIGNED_SSE_NOT_SUPPORTED',
-    0x002C: 'HV_STATUS_PROCESSOR_FEATURE_MMX_EXT_NOT_SUPPORTED',
-    0x002D: 'HV_STATUS_PROCESSOR_FEATURE_3DNOW_NOT_SUPPORTED',
-    0x002E: 'HV_STATUS_PROCESSOR_FEATURE_EXTENDED_3DNOW_NOT_SUPPORTED',
-    0x002F: 'HV_STATUS_PROCESSOR_FEATURE_PAGE_1GB_NOT_SUPPORTED',
-    0x0030: 'HV_STATUS_PROCESSOR_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE',
-    0x0031: 'HV_STATUS_PROCESSOR_FEATURE_XSAVE_NOT_SUPPORTED',
-    0x0032: 'HV_STATUS_PROCESSOR_FEATURE_XSAVEOPT_NOT_SUPPORTED',
-    0x0033: 'HV_STATUS_INSUFFICIENT_BUFFER',
-    0x0034: 'HV_STATUS_PROCESSOR_FEATURE_XSAVE_AVX_NOT_SUPPORTED',
-    0x0035: 'HV_STATUS_PROCESSOR_FEATURE_XSAVE_FEATURE_NOT_SUPPORTED',
-    0x0036: 'HV_STATUS_PROCESSOR_XSAVE_SAVE_AREA_INCOMPATIBLE',
-    0x0037: 'HV_STATUS_INCOMPATIBLE_PROCESSOR',
-    0x0038: 'HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS',
-    0x0039: 'HV_STATUS_PROCESSOR_FEATURE_AES_NOT_SUPPORTED',
-    0x003A: 'HV_STATUS_PROCESSOR_FEATURE_PCLMULQDQ_NOT_SUPPORTED',
-    0x003B: 'HV_STATUS_PROCESSOR_FEATURE_INCOMPATIBLE_XSAVE_FEATURES',
-    0x003C: 'HV_STATUS_CPUID_FEATURE_VALIDATION_ERROR',
-    0x003D: 'HV_STATUS_CPUID_XSAVE_FEATURE_VALIDATION_ERROR',
-    0x003E: 'HV_STATUS_PROCESSOR_STARTUP_TIMEOUT',
-    0x003F: 'HV_STATUS_SMX_ENABLED',
-    0x0040: 'HV_STATUS_PROCESSOR_FEATURE_PCID_NOT_SUPPORTED',
-    0x0041: 'HV_STATUS_INVALID_LP_INDEX',
-    0x0042: 'HV_STATUS_FEATURE_FMA4_NOT_SUPPORTED',
-    0x0043: 'HV_STATUS_FEATURE_F16C_NOT_SUPPORTED',
-    0x0044: 'HV_STATUS_PROCESSOR_FEATURE_RDRAND_NOT_SUPPORTED',
-    0x0045: 'HV_STATUS_PROCESSOR_FEATURE_RDWRFSGS_NOT_SUPPORTED',
-    0x0046: 'HV_STATUS_PROCESSOR_FEATURE_SMEP_NOT_SUPPORTED',
-    0x0047: 'HV_STATUS_PROCESSOR_FEATURE_ENHANCED_FAST_STRING_NOT_SUPPORTED',
-    0x0048: 'HV_STATUS_PROCESSOR_FEATURE_MOVBE_NOT_SUPPORTED',
-    0x0049: 'HV_STATUS_PROCESSOR_FEATURE_BMI1_NOT_SUPPORTED',
-    0x004A: 'HV_STATUS_PROCESSOR_FEATURE_BMI2_NOT_SUPPORTED',
-    0x004B: 'HV_STATUS_PROCESSOR_FEATURE_HLE_NOT_SUPPORTED',
-    0x004C: 'HV_STATUS_PROCESSOR_FEATURE_RTM_NOT_SUPPORTED',
-    0x004D: 'HV_STATUS_PROCESSOR_FEATURE_XSAVE_FMA_NOT_SUPPORTED',
-    0x004E: 'HV_STATUS_PROCESSOR_FEATURE_XSAVE_AVX2_NOT_SUPPORTED',
-    0x004F: 'HV_STATUS_PROCESSOR_FEATURE_NPIEP1_NOT_SUPPORTED'
-}
-
-
-

-[docs]
-def get_hypercall_status(code, defvalue=''):
-    return hypercall_status_codes[code] if code in hypercall_status_codes else defvalue

-
-
-
-hypercall_names = {
-    0x0001: 'HvSwitchVirtualAddressSpace',
-    0x0002: 'HvFlushVirtualAddressSpace',
-    0x0003: 'HvFlushVirtualAddressList',
-    0x0004: 'HvGetLogicalProcessorRunTime',
-    0x0008: 'HvNotifyLongSpinWait',
-    0x0009: 'HvParkedVirtualProcessors',
-    0x0040: 'HvCreatePartition',
-    0x0041: 'HvInitializePartition',
-    0x0042: 'HvFinalizePartition',
-    0x0043: 'HvDeletePartition',
-    0x0044: 'HvGetPartitionProperty',
-    0x0045: 'HvSetPartitionProperty',
-    0x0046: 'HvGetPartitionId',
-    0x0047: 'HvGetNextChildPartition',
-    0x0048: 'HvDepositMemory',
-    0x0049: 'HvWithdrawMemory',
-    0x004A: 'HvGetMemoryBalance',
-    0x004B: 'HvMapGpaPages',
-    0x004C: 'HvUnmapGpaPages',
-    0x004D: 'HvInstallIntercept',
-    0x004E: 'HvCreateVp',
-    0x004F: 'HvDeleteVp',
-    0x0050: 'HvGetVpRegisters',
-    0x0051: 'HvSetVpRegisters',
-    0x0052: 'HvTranslateVirtualAddress',
-    0x0053: 'HvReadGpa',
-    0x0054: 'HvWriteGpa',
-    0x0055: 'HvAssertVirtualInterrupt',
-    0x0056: 'HvClearVirtualInterrupt',
-    0x0057: 'HvCreatePort',
-    0x0058: 'HvDeletePort',
-    0x0059: 'HvConnectPort',
-    0x005A: 'HvGetPortProperty',
-    0x005B: 'HvDisconnectPort',
-    0x005C: 'HvPostMessage',
-    0x005D: 'HvSignalEvent',
-    0x005E: 'HvSavePartitionState',
-    0x005F: 'HvRestorePartitionState',
-    0x0060: 'HvInitializeEventLogBufferGroup',
-    0x0061: 'HvFinalizeEventLogBufferGroup',
-    0x0062: 'HvCreateEventLogBuffer',
-    0x0063: 'HvDeleteEventLogBuffer',
-    0x0064: 'HvMapEventLogBuffer',
-    0x0065: 'HvUnmapEventLogBuffer',
-    0x0066: 'HvSetEventLogGroupSources',
-    0x0067: 'HvReleaseEventLogBuffer',
-    0x0068: 'HvFlushEventLogBuffer',
-    0x0069: 'HvPostDebugData',
-    0x006A: 'HvRetrieveDebugData',
-    0x006B: 'HvResetDebugSession',
-    0x006C: 'HvMapStatsPage',
-    0x006D: 'HvUnmapStatsPage',
-    0x006E: 'HvCallMapSparseGpaPages',
-    0x006F: 'HvCallSetSystemProperty',
-    0x0070: 'HvCallSetPortProperty',
-    0x0076: 'HvCallAddLogicalProcessor',
-    0x0077: 'HvCallRemoveLogicalProcessor',
-    0x0078: 'HvCallQueryNumaDistance',
-    0x0079: 'HvCallSetLogicalProcessorProperty',
-    0x007A: 'HvCallGetLogicalProcessorProperty',
-    0x007B: 'HvCallGetSystemProperty',
-    0x007C: 'HvCallMapDeviceInterrupt',
-    0x007D: 'HvCallUnmapDeviceInterrupt',
-    0x007E: 'HvCallCreateDeviceDomain',
-    0x007F: 'HvCallDeleteDeviceDomain',
-    0x0080: 'HvCallMapDevicePages',
-    0x0081: 'HvCallUnmapDevicePages',
-    0x0082: 'HvCallAttachDevice',
-    0x0083: 'HvCallDetachDevice',
-    0x0084: 'HvCallEnterSleepState',
-    0x0085: 'HvCallPrepareForSleep',
-    0x0086: 'HvCallPrepareForHibernate',
-    0x0087: 'HvCallNotifyPartitionEvent',
-    0x0088: 'HvCallGetLogicalProcessorRegisters',
-    0x0089: 'HvCallSetLogicalProcessorRegisters',
-    0x008A: 'HvCallQueryAssociatedLpsforMca',
-    0x008B: 'HvCallNotifyRingEmpty',
-    0x008C: 'HvCallInjectSyntheticMachineCheck',
-    0x008D: 'HvCallScrubPartition',
-    0x008E: 'HvCallCollectLivedump',
-    0x008F: 'HvCallDisableHypervisor',
-    0x0090: 'HvCallModifySparseGpaPages',
-    0x0091: 'HvCallRegisterInterceptResult',
-    0x0092: 'HvCallUnregisterInterceptResult'
-}
-
-
-

-[docs]
-def get_hypercall_name(code, defvalue=''):
-    return hypercall_names[code] if code in hypercall_names else defvalue

-
-
-
-hv_porttype = {
-    0x0001: 'HvPortTypeMessage',
-    0x0002: 'HvPortTypeEvent',
-    0x0003: 'HvPortTypeMonitor'
-}
-
-GOOD_PARAMS_STATUSES = ['HV_STATUS_SUCCESS', 'HV_STATUS_ACCESS_DENIED']
-
-cpuid_desc = {0x40000003: {}}
-
-cpuid_desc[0x40000003]['EAX'] = {
-    0: 'VP Runtime (HV_X64_MSR_VP_RUNTIME) available',
-    1: 'Partition Reference Counter (HV_X64_MSR_TIME_REF_COUNT) available',
-    2: 'Basic SynIC MSRs (HV_X64_MSR_SCONTROL..HV_X64_MSR_EOM and HV_X64_MSR_SINTxx) available',
-    3: 'Synthetic Timer MSRs (HV_X64_MSR_STIMER0_CONFIG..HV_X64_MSR_STIMER3_COUNT) available',
-    4: 'APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR) are available',
-    5: 'Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL) available',
-    6: 'Access virtual processor index MSR (HV_X64_MSR_VP_INDEX) available',
-    7: 'Virtual system reset MSR (HV_X64_MSR_RESET) is available',
-    8: 'Access statistics pages MSRs available',
-    9: 'Partition Reference TSC MSR (HV_X64_MSR_REFERENCE_TSC) available',
-    10: 'Virtual Guest Idle State MSR (HV_X64_MSR_GUEST_IDLE) available',
-    11: 'Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and HV_X64_MSR_APIC_FREQUENCY) available',
-    12: 'Debug MSRs (HV_X64_MSR_SYNTH_DEBUG_*) available'
-}
-
-cpuid_desc[0x40000003]['EBX'] = {
-    0: 'CreatePartitions',
-    1: 'AccessPartitionId',
-    2: 'AccessMemoryPool',
-    3: 'AdjustMessageBuffers',
-    4: 'PostMessages',
-    5: 'SignalEvents',
-    6: 'CreatePort',
-    7: 'ConnectPort',
-    8: 'AccessStats',
-    9: 'RsvdZ',
-    10: 'RsvdZ',
-    11: 'Debugging',
-    12: 'CpuManagement',
-    13: 'ConfigureProfiler',
-    14: 'EnableExpandedStackwalking'
-}
-
-cpuid_desc[0x40000003]['ECX'] = {
-    0: 'Maximum Processor Power State (bit 0)',
-    1: 'Maximum Processor Power State (bit 1)',
-    2: 'Maximum Processor Power State (bit 2)',
-    4: 'HPET is required to enter C3'
-}
-
-cpuid_desc[0x40000003]['EDX'] = {
-    0: 'The MWAIT instruction is available',
-    1: 'Guest debugging support is available',
-    2: 'Performance Monitor support is available',
-    3: 'Support for physical CPU dynamic partitioning events is available',
-    4: 'Support for passing hypercall input parameter block via XMM registers is available',
-    5: 'Support for a virtual guest idle state is available',
-    6: 'Support for hypervisor sleep state is available',
-    7: 'Support for querying NUMA distances is available',
-    8: 'Support for determining timer frequencies is available',
-    9: 'Support for injecting synthetic machine checks is available',
-    10: 'Support for guest crash MSRs is available',
-    11: 'Support for debug MSRs is available',
-    12: 'Npiep1Available',
-    13: 'DiableHypervisorAvailable'
-}
-
-### HYPERV DEFINES #############################################################
-
-# VMBUS version is 32 bit entity broken up into two 16 bit quantities: major_number . minor_number
-VERSION_WS2008 = ((0 << 16) | (13))  # 0 . 13 (Windows Server 2008)
-VERSION_WIN7 = ((1 << 16) | (1))   # 1 . 1  (Windows 7)
-VERSION_WIN8 = ((2 << 16) | (4))   # 2 . 4  (Windows 8)
-VERSION_WIN8_1 = ((3 << 16) | (0))   # 3 . 0  (Windows 8 R2)
-
-vmbus_versions = {
-    VERSION_WS2008: 'Windows Server 2008',
-    VERSION_WIN7: 'Windows 7',
-    VERSION_WIN8: 'Windows 8',
-    VERSION_WIN8_1: 'Windows 8 R2'
-}
-
-VMBUS_MESSAGE_CONNECTION_ID = 1
-VMBUS_MESSAGE_PORT_ID = 1
-VMBUS_EVENT_CONNECTION_ID = 2
-VMBUS_EVENT_PORT_ID = 2
-VMBUS_MONITOR_CONNECTION_ID = 3
-VMBUS_MONITOR_PORT_ID = 3
-VMBUS_MESSAGE_SINT = 2
-
-### HV MESSAGE DEFINES #########################################################
-
-# Define hypervisor message types
-hv_message_type = {
-    0x00000000: 'HVMSG_NONE',
-    # Memory access messages
-    0x80000000: 'HVMSG_UNMAPPED_GPA',
-    0x80000001: 'HVMSG_GPA_INTERCEPT',
-    # Timer notification messages
-    0x80000010: 'HVMSG_TIMER_EXPIRED',
-    # Error messages
-    0x80000020: 'HVMSG_INVALID_VP_REGISTER_VALUE',
-    0x80000021: 'HVMSG_UNRECOVERABLE_EXCEPTION',
-    0x80000022: 'HVMSG_UNSUPPORTED_FEATURE',
-    # Trace buffer complete messages
-    0x80000040: 'HVMSG_EVENTLOG_BUFFERCOMPLETE',
-    # Platform-specific processor intercept messages
-    0x80010000: 'HVMSG_X64_IOPORT_INTERCEPT',
-    0x80010001: 'HVMSG_X64_MSR_INTERCEPT',
-    0x80010002: 'HVMSG_X64_CPUID_INTERCEPT',
-    0x80010003: 'HVMSG_X64_EXCEPTION_INTERCEPT',
-    0x80010004: 'HVMSG_X64_APIC_EOI',
-    0x80010005: 'HVMSG_X64_LEGACY_FP_ERROR'
-}
-
-### MSG CHANNEL DEFINES ########################################################
-
-CHANNELMSG_INVALID = 0
-CHANNELMSG_OFFERCHANNEL = 1
-CHANNELMSG_RESCIND_CHANNELOFFER = 2
-CHANNELMSG_REQUESTOFFERS = 3
-CHANNELMSG_ALLOFFERS_DELIVERED = 4
-CHANNELMSG_OPENCHANNEL = 5
-CHANNELMSG_OPENCHANNEL_RESULT = 6
-CHANNELMSG_CLOSECHANNEL = 7
-CHANNELMSG_GPADL_HEADER = 8
-CHANNELMSG_GPADL_BODY = 9
-CHANNELMSG_GPADL_CREATED = 10
-CHANNELMSG_GPADL_TEARDOWN = 11
-CHANNELMSG_GPADL_TORNDOWN = 12
-CHANNELMSG_RELID_RELEASED = 13
-CHANNELMSG_INITIATE_CONTACT = 14
-CHANNELMSG_VERSION_RESPONSE = 15
-CHANNELMSG_UNLOAD = 16
-
-vmbus_channel_message_type = {
-    0: 'ChannelMessageInvalid',
-    1: 'ChannelMessageOfferChannel',
-    2: 'ChannelMessageRescindChannelOffer',
-    3: 'ChannelMessageRequestOffers',
-    4: 'ChannelMessageAllOffersDelivered',
-    5: 'ChannelMessageOpenChannel',
-    6: 'ChannelMessageOpenChannelResult',
-    7: 'ChannelMessageCloseChannel',
-    8: 'ChannelMessageGpadlHeader',
-    9: 'ChannelMessageGpadlBody',
-    10: 'ChannelMessageGpadlCreated',
-    11: 'ChannelMessageGpadlTeardown',
-    12: 'ChannelMessageGpadlTorndown',
-    13: 'ChannelMessageRelIdReleased',
-    14: 'ChannelMessageInitiateContact',
-    15: 'ChannelMessageVersionResponse',
-    16: 'ChannelMessageUnload'
-}
-
-channel_flags = {
-    0x00: 'VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE',
-    0x01: 'VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES',
-    0x02: 'VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS',
-    0x04: 'VMBUS_CHANNEL_NAMED_PIPE_MODE',
-    0x08: 'VMBUS_CHANNEL_LOOPBACK_OFFER',
-    0x09: 'VMBUS_CHANNEL_PARENT_OFFER',
-    0x0a: 'VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION'
-}
-
-# GUID definitions of various offer types - services offered to the guest
-HV_NIC_GUID = '{f8615163-df3e-46c5-913f-f2d2f965ed0e}'
-HV_IDE_GUID = '{32412632-86cb-44a2-9b5c-50d1417354f5}'
-HV_SCSI_GUID = '{ba6163d9-04a1-4d29-b605-72e2ffb1dc7f}'
-HV_SHUTDOWN_GUID = '{0e0b6031-5213-4934-818b-38d90ced39db}'
-HV_TS_GUID = '{9527e630-d0ae-497b-adce-e80ab0175caf}'
-HV_HEART_BEAT_GUID = '{57164f39-9115-4e78-ab55-382f3bd5422d}'
-HV_KVP_GUID = '{a9a0f4e7-5a45-4d96-b827-8a841e8c03e6}'
-HV_DM_GUID = '{525074dc-8985-46e2-8057-a307dc18a502}'
-HV_MOUSE_GUID = '{cfa8b69e-5b4a-4cc0-b98b-8ba1a1f3f95a}'
-HV_VSS_GUID = '{35fa2e29-ea23-4236-ae96-3a6ebacba440}'
-HV_SYNTHVID_GUID = '{da0a7802-e377-4aac-8e77-0558eb1073f8}'
-HV_SYNTHFC_GUID = '{2f9bcc4a-0069-4af3-b76b-6fd0be528cda}'
-HV_FCOPY_GUID = '{34d14be3-dee4-41c8-9ae7-6b174977c192}'
-HV_KBD_GUID = '{f912ad6d-2b17-48ea-bd65-f927a61c7684}'
-REMOTE_DESKTOP_GUID = '{276aacf4-ac15-426c-98dd-7521ad3f01fe}'
-VOLUME_SHADOW_COPY_GUID = '{35fa2e29-ea23-4236-96ae-3a6ebacba440}'
-AVMA_GUID = '{3375baf4-9e15-4b30-b765-67acb10d607b}'
-DESKTOP_CONTROL_GUID = '{f8e65716-3cb3-4a06-9a60-1889c5cccab5}'
-
-hv_guid_desc = {
-    HV_NIC_GUID: 'Microsoft Hyper-V Network',
-    HV_IDE_GUID: 'Microsoft Hyper-V IDE',
-    HV_SCSI_GUID: 'Microsoft Hyper-V SCSI Controller',
-    HV_SHUTDOWN_GUID: 'Microsoft Hyper-V Shutdown',
-    HV_TS_GUID: 'Microsoft Hyper-V Time Synch',
-    HV_HEART_BEAT_GUID: 'Microsoft Hyper-V Heartbeat',
-    HV_KVP_GUID: 'Microsoft Hyper-V KVP',
-    HV_DM_GUID: 'Microsoft Hyper-V Dynamic memory',
-    HV_MOUSE_GUID: 'Microsoft Hyper-V Mouse',
-    HV_VSS_GUID: 'Microsoft Hyper-V VSS Backup/Restore',
-    HV_SYNTHVID_GUID: 'Microsoft Hyper-V Synthetic Video',
-    HV_SYNTHFC_GUID: 'Microsoft Hyper-V Synthetic FC',
-    HV_FCOPY_GUID: 'Microsoft Hyper-V Guest File Copy Service',
-    HV_KBD_GUID: 'Microsoft Hyper-V Virtual Keyboard',
-    REMOTE_DESKTOP_GUID: 'Microsoft Hyper-V Remote Desktop Virtualization',
-    VOLUME_SHADOW_COPY_GUID: 'Microsoft Hyper-V Volume Shadow Copy',
-    AVMA_GUID: 'Microsoft Hyper-V Automatic Virtual Machine Activation (AVMA)',
-    DESKTOP_CONTROL_GUID: 'Microsoft Hyper-V Remote Desktop Control Channel'
-}
-
-### VMBUS PACKET DEFINES #######################################################
-
-vm_pkt = {
-    0x0: 'VM_PKT_INVALID',
-    0x1: 'VM_PKT_SYNCH',
-    0x2: 'VM_PKT_ADD_XFER_PAGESET',
-    0x3: 'VM_PKT_RM_XFER_PAGESET',
-    0x4: 'VM_PKT_ESTABLISH_GPADL',
-    0x5: 'VM_PKT_TEARDOWN_GPADL',
-    0x6: 'VM_PKT_DATA_INBAND',
-    0x7: 'VM_PKT_DATA_USING_XFER_PAGES',
-    0x8: 'VM_PKT_DATA_USING_GPADL',
-    0x9: 'VM_PKT_DATA_USING_GPA_DIRECT',
-    0xa: 'VM_PKT_CANCEL_REQUEST',
-    0xb: 'VM_PKT_COMP',
-    0xc: 'VM_PKT_DATA_USING_ADDITIONAL_PKT',
-    0xd: 'VM_PKT_ADDITIONAL_DATA'
-}
-
-VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED = 1
-
-################################################################################
-
-
-

-[docs]
-def set_variables(varlist):
-    for i in varlist:
-        var = re.sub(r"([a-z])([A-Z]+)", r"\1_\2", varlist[i])
-        var = var.upper()
-        exec(f'global {var}; {var}={i:d}')

-
-
-
-set_variables(msrs)
-set_variables(hypercall_status_codes)
-set_variables(hypercall_names)
-set_variables(hv_porttype)
-set_variables(hv_message_type)
-set_variables(channel_flags)
-set_variables(vm_pkt)
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/hypercall.html b/_modules/chipsec/modules/tools/vmm/hv/hypercall.html
deleted file mode 100644
index 22f261d2..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/hypercall.html
+++ /dev/null
@@ -1,605 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.hypercall — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.hypercall
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V specific hypercall functionality
-"""
-
-import os
-import sys
-import time
-import chipsec_util
-from random import *
-from struct import *
-from chipsec.modules.tools.vmm.hv.define import *
-from chipsec.modules.tools.vmm.common import *
-from chipsec.logger import *
-from chipsec.file import *
-from chipsec.module_common import *
-from chipsec.hal.vmm import *
-
-
-

-[docs]
-class HyperVHypercall(BaseModuleHwAccess):
-    def __init__(self):
-        BaseModuleHwAccess.__init__(self)
-        self.hv = VMM(self.cs)
-        self.hv.init()
-        self.hypervisor_present = False
-        self.hv_partitionid = {}
-        self.hv_connectionid = {}
-        self.hv_hypercalls = {}
-        self.param_matrix_status = {}
-
-    ##
-    # print_hypervisor_info
-    ##
-

-[docs]
-    def print_hypervisor_info(self):
-        gprs = self.cpuid_info(0x00000001, 0x0, 'Feature Information')
-        self.hypervisor_present = ((gprs[2] >> 31) & 0x1) == 0x1
-        self.msg(f'ECX(31) - Hypervisor Present                  :  {self.hypervisor_present:x}')
-
-        if self.hypervisor_present:
-
-            gprs = self.cpuid_info(0x40000000, 0x0, 'Hypervisor CPUID leaf range and vendor ID signature')
-            (max_input_value, id_signature_ebx, id_signature_ecx, id_signature_edx) = gprs
-            id_signature = pack('<3L', id_signature_ebx, id_signature_ecx, id_signature_edx)
-            self.msg(f'The maximum input value for hypervisor CPUID  :  {max_input_value:08X}')
-            self.msg(f'Hypervisor Vendor ID Signature                :  {id_signature}')
-
-            gprs = self.cpuid_info(0x40000001, 0x0, 'Hypervisor vendor-neutral interface identification')
-            (interface_signature, rsvd_ebx, rsvd_ecx, rsvd_edx) = gprs
-            interface_signature = pack('<1L', interface_signature)
-            self.msg(f'Hypervisor Interface Signature                :  {interface_signature}')
-
-            if interface_signature == 'Hv#1':
-                self.msg('INFO: HV hypervisor CPUID interface detected!')
-                if (max_input_value < 0x40000005) or (max_input_value > 0x400000FF):
-                    self.msg('')
-                    self.msg('*** WARNING ***: Invalid CPUID.0x40000000.0x0.EAX value\n\n')
-
-                for cpuid_eax in range(0x40000002, max_input_value):
-                    self.print_hypervisor_cpuid(cpuid_eax)
-
-        return

-
-
-    ##
-    # print_hypervisor_cpuid
-    ##
-

-[docs]
-    def print_hypervisor_cpuid(self, cpuid_eax, cpuid_ecx=0x0):
-        if cpuid_eax == 0x40000002:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, 'Hypervisor system identity')
-            major_version = 0xFFFF & (ebx >> 16)
-            minor_version = 0xFFFF & ebx
-            service_branch = 0xFF & (edx >> 24)
-            service_number = 0xFFFFFF & edx
-            self.msg(f'   EAX        - Build Number    :  {eax:08X}')
-            self.msg(f'   EBX(31-16) - Major Version   :  {major_version:04X}')
-            self.msg(f'   EBX(15-0)  - Minor Version   :  {minor_version:04X}')
-            self.msg(f'   ECX        - Service Pack    :  {ecx:08X}')
-            self.msg(f'   EDX(31-24) - Service Branch  :  {service_branch:02X}')
-            self.msg(f'   EDX(23-0)  - Service Number  :  {service_number:06x}')
-        elif cpuid_eax == 0x40000003:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, 'Feature identification')
-            self.msg(f'   EAX - features available to the partition                :  {eax:08X}')
-            self.info_bitwise(eax, cpuid_desc[cpuid_eax]['EAX'])
-            self.msg(f'   EBX - flags specified at partition creation              :  {ebx:08X}')
-            self.info_bitwise(ebx, cpuid_desc[cpuid_eax]['EBX'])
-            self.msg(f'   ECX - power management related information               :  {ecx:08X}')
-            self.info_bitwise(ecx, cpuid_desc[cpuid_eax]['ECX'])
-            self.msg(f'   EDX - misc. features available to the partition          :  {edx:08X}')
-            self.info_bitwise(edx, cpuid_desc[cpuid_eax]['EDX'])
-        elif cpuid_eax == 0x40000004:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, 'Implementation recommendations')
-            self.msg(f'   EAX(9-0) - recommendations for optimal performance       :  {eax:08X}')
-            self.msg(f'   EBX      - recommended number of attempts                :  {ebx:08X}')
-        elif cpuid_eax == 0x40000005:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, 'Implementation limits')
-            self.msg(f'   EAX - The maximum number of virtual processors supported :  {eax:08X}')
-            self.msg(f'   EBX - The maximum number of logical processors supported :  {ebx:08X}')
-            self.msg(f'   ECX - The maximum number of physical interrupt vectors   :  {ecx:08X}')
-        elif cpuid_eax == 0x40000006:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, 'Implementation hardware features')
-            self.msg(f'   EAX - Intel-specific features  :  {eax:08X}')
-            self.msg(f'   EDX - AMD-specific features    :  {edx:08X}')
-        else:
-            (eax, ebx, ecx, edx) = self.cpuid_info(cpuid_eax, cpuid_ecx, '')
-        return

-
-
-    ##
-    # print_synthetic_msrs
-    ##
-

-[docs]
-    def print_synthetic_msrs(self):
-        self.msg('')
-        self.msg('*** Hypervisor Synthetic MSRs ***')
-
-        for addr in sorted(msrs.keys()):
-            name = get_msr_name(addr)
-            try:
-                readValue = self.rdmsr(addr)
-                result = f'0x{readValue[0]:08X}_{readValue[1]:08X}'
-            except Exception as e:
-                result = str(e)
-            self.msg(f'RDMSR [{name:40} = 0x{addr:08X}] :  {result}')
-        return

-
-
-    ##
-    # scan_hypercalls
-    ##
-

-[docs]
-    def scan_hypercalls(self, code_list):
-        for call_code in code_list:
-            data = self.get_initial_data(GOOD_PARAMS_STATUSES, call_code, 112)
-            self.dbg(f'PROBING HYPERCALL: 0x{call_code:04X}')
-            for buffer in data:
-                try:
-                    self.dbg('- FAST HYPERCALL')
-                    hciv = hv_hciv(0, 0, call_code, 1)
-                    result = self.hv.hypercall64_extended_fast(hciv, buffer) & 0xFFFF
-                    hv_rep = 0
-                    hv_fast = 1
-                    if result == HV_STATUS_INVALID_HYPERCALL_INPUT:
-                        self.dbg('- JUST HYPERCALL')
-                        hciv = hv_hciv(0, 0, call_code, 0)
-                        result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-                        hv_fast = 0
-                        if result == HV_STATUS_INVALID_HYPERCALL_INPUT:
-                            self.dbg('- FAST REP HYPERCALL')
-                            hciv = hv_hciv(0, 1, call_code, 1)
-                            result = self.hv.hypercall64_extended_fast(hciv, buffer) & 0xFFFF
-                            hv_rep = 1
-                            if result == HV_STATUS_INVALID_HYPERCALL_INPUT:
-                                self.dbg('- REP HYPERCALL')
-                                hciv = hv_hciv(0, 1, call_code, 0)
-                                result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-                                hv_fast = 0
-                            else:
-                                hv_fast = 1
-                    if result != HV_STATUS_INVALID_HYPERCALL_CODE:
-                        self.hv_hypercalls[call_code] = [hv_rep, hv_fast, result]
-                except Exception as e:
-                    self.msg(f'Exception on hypercall (0x{call_code:08X}): {str(e)}')
-        return

-
-
-    ##
-    # scan_partitionid
-    ##
-

-[docs]
-    def scan_partitionid(self, id_list):
-        invalid_partition = 0
-        for i in id_list:
-            hciv = hv_hciv(0, 0, 0x0041)
-            buffer = pack('<Q', i)
-            result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-            if result == HV_STATUS_ACCESS_DENIED:
-                self.hv_partitionid[i] = 1
-            if result == HV_STATUS_INVALID_PARTITION_ID:
-                invalid_partition = 1
-        if invalid_partition == 0:
-            self.hv_partitionid = {}
-        return

-
-
-    ##
-    # scan_connectionid
-    ##
-

-[docs]
-    def scan_connectionid(self, id_list):
-        for i in id_list:
-            hciv = hv_hciv(0, 0, HV_POST_MESSAGE)
-            buffer = pack('<LLLLQ', i, 0x0, 0x1, 8, 0x0)
-            result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-            if result != HV_STATUS_INVALID_CONNECTION_ID:
-                if result == HV_STATUS_SUCCESS:
-                    self.hv_connectionid[i] = 0x1
-                else:
-                    hciv = hv_hciv(0, 0, HV_SIGNAL_EVENT)
-                    buffer = pack('<LHH', i, 0x0, 0x0)
-                    result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-                    self.hv_connectionid[i] = 0x2 if result == HV_STATUS_SUCCESS else 0x3
-        return

-
-
-    ##
-    # scan_for_success_status
-    ##
-

-[docs]
-    def scan_for_success_status(self, i, total_tests):
-        statistics = {}
-        pattern = ''
-        hc = self.hv_hypercalls[i] if i in self.hv_hypercalls else [0, 0, HV_STATUS_INVALID_HYPERCALL_CODE]
-        if hc[2] != HV_STATUS_SUCCESS:
-            for x in range(total_tests):
-                buffer = ''
-                buffer += '\x00' * randint(0, 8) + chr(getrandbits(8))
-                buffer += '\x00' * randint(0, 8) + chr(getrandbits(8))
-                buffer += '\x00' * randint(0, 8) + chr(getrandbits(8))
-                buffer += '\x00' * randint(0, 8) + chr(getrandbits(8))
-                buffer += '\x00' * 32
-                hciv = hv_hciv(0, hc[0], i, 0)
-                result = self.hv.hypercall64_memory_based(hciv, buffer)
-                rep_completed = (result >> 32) & 0x0FFF
-                result = result & 0xFFFF
-                statistics[result] = 1 if result not in statistics else statistics[result] + 1
-                if result == HV_STATUS_SUCCESS:
-                    pattern = buffer
-                    break
-                if result == HV_STATUS_ACCESS_DENIED:
-                    pattern = buffer
-            self.msg('*************** Status codes statistics: *****************')
-            for n in sorted(statistics.keys()):
-                status = get_hypercall_status(n, 'Not defined')
-                self.msg(f'{status:50}: {statistics[n]:d}')
-            self.hex('Input Parameters', pattern[:0x20])
-        else:
-            self.msg('')
-            self.msg('Hypercall status: SUCCESS')
-        return

-
-
-    ##
-    # scan_input_parameters
-    ##
-

-[docs]
-    def scan_input_parameters(self, i, maxlen):
-        matrix = [[0 for x in range(0x101)] for y in range(maxlen)]
-        hc = self.hv_hypercalls[i] if i in self.hv_hypercalls else [0, 0, HV_STATUS_INVALID_HYPERCALL_CODE]
-        iv = self.get_initial_data(GOOD_PARAMS_STATUSES, i, 32)[0]
-        self.msg('Start scanning ...')
-        for l in range(maxlen):
-            for v in range(0x100):
-                s = list(iv)
-                s[l] = chr(v)
-                buffer = ''.join(s)
-                hciv = hv_hciv(0, hc[0], i, 0)
-                result = self.hv.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-                matrix[l][v] = result
-        self.param_matrix_status[i] = matrix
-        self.msg('Done!')
-        return

-
-
-    ##
-    # print_input_parameters
-    ##
-

-[docs]
-    def print_input_parameters(self, i, maxlen, status_list):
-        matrix = self.param_matrix_status[i]
-        for l in range(maxlen):
-            x = 0
-            ranges = []
-            for v in range(0x100):
-                if (matrix[l][v] not in status_list) and (matrix[l][v + 1] in status_list):
-                    x = v + 1
-                if (matrix[l][v] in status_list) and (matrix[l][v + 1] not in status_list):
-                    if (x == v):
-                        ranges.append(f'{x:02X}')
-                    else:
-                        ranges.append(f'{x:02X}-{v:02X}')
-            if (ranges != ['00-FF']) and (ranges != []):
-                self.msg(f'  Byte {l:02d} = [{", ".join(ranges)}]')
-        return

-
-
-    ##
-    # input_parameters_fuzzing
-    ##
-

-[docs]
-    def input_parameters_fuzzing(self, i, maxlen, status_list, total_tests):
-        matrix = self.param_matrix_status[i]
-        buffer = self.get_initial_data(GOOD_PARAMS_STATUSES, i, 32)[0]
-        self.msg('Start input parameters fuzzing ...')
-        for x in range(total_tests):
-            if x % 10000000 == 10000000 - 1:
-                self.msg(f'{100.0 * x / total_tests:4.0f}% DONE')
-            l = randint(0, maxlen - 1)
-            v = randint(0, 0x100 - 1)
-            if matrix[l][v] == 1:
-                s = list(buffer)
-                s[l] = chr(v)
-                buffer = ''.join(s)
-                s[randint(0, maxlen - 1)] = chr(randint(0, 0xFF))
-                s[randint(0, maxlen - 1)] = chr(randint(0, 0xFF))
-                if self.hv_hypercalls[i][0] in status_list:
-                    hciv = hv_hciv(0, 1, i, 0)
-                else:
-                    hciv = hv_hciv(0, 0, i, 0)
-                result = self.hv.hypercall64_memory_based(hciv, ''.join(s)) & 0xFFFF
-        self.msg('DONE!')
-        return

-
-
-    ##
-    # print_hypercall_status
-    ##
-

-[docs]
-    def print_hypercall_status(self):
-        self.msg('')
-        self.msg('*** Hypervisor Hypercall Status Codes ***')
-        status_list = [HV_STATUS_INVALID_HYPERCALL_CODE]
-        for i in sorted(self.hv_hypercalls.keys()):
-            hc = self.hv_hypercalls[i]
-            status = get_hypercall_status(hc[2])
-            hcname = get_hypercall_name(i)
-            if status not in status_list:
-                self.msg(f'HYPERV_HYPERCALL REP:{hc[0]:d} FAST:{hc[1]:d} {i:04X}  {hc[2]:02X}  {status:40} \'{hcname}\'')
-        return

-
-
-    ##
-    # print_partitionid
-    ##
-

-[docs]
-    def print_partitionid(self):
-        self.msg('')
-        self.msg('*** Hypervisor Partition IDs ***')
-        if len(self.hv_partitionid) == 0:
-            self.msg('  was not able to determine Partition IDs')
-        else:
-            for i in sorted(self.hv_partitionid.keys()):
-                self.msg(f'{i:08X}')
-        return

-
-
-    ##
-    # print_partition_properties
-    ##
-

-[docs]
-    def print_partition_properties(self):
-        self.msg('')
-        self.msg('*** Partition properties ***')
-        for partid in sorted(self.hv_partitionid.keys()):
-            for n in range(0x10):
-                for m in range(0x10):
-                    hciv = hv_hciv(0, 0, HV_GET_PARTITION_PROPERTY)
-                    prop = (n << 16) + m
-                    buffer = pack('<QLL', partid, prop, 0)
-                    result = self.hv.hypercall64_memory_based(hciv, buffer, 8)
-                    if result == HV_STATUS_SUCCESS:
-                        self.msg(f'  Partition: {partid:08X}  Property: {prop:08X}  Value: {unpack("<Q", self.hv.output)[0]:016x}')
-        return

-
-
-    ##
-    # set_partition_property
-    ##
-

-[docs]
-    def set_partition_property(self, part, prop, value):
-        hciv = hv_hciv(0, 0, HV_SET_PARTITION_PROPERTY)
-        buffer = pack('<QLLQ', part, prop, 0, value)
-        result = self.hv.hypercall64_memory_based(hciv, buffer)
-        status = get_hypercall_status(result, f'0x{result:08X}')
-        self.msg(f'>>> Setting partition property:  Partition: {part:08X}  Property: {prop:08X}  Value: {value:016x}  Status: {status}')
-        return

-
-
-    ##
-    # print_connectionid
-    ##
-

-[docs]
-    def print_connectionid(self, status_list):
-        self.msg('')
-        self.msg('*** Hypervisor Connection IDs ***')
-        for i in sorted(self.hv_connectionid.keys()):
-            connid = self.hv_connectionid[i]
-            self.msg(f'{i:08X}  {connid:02X}  {hv_porttype[connid]}')
-        return

-
-
-    ##
-    # custom_fuzzing
-    ##
-

-[docs]
-    def custom_fuzzing(self, call_code, total_tests):
-        statistics = {}
-        buffer = ''.join([chr(randint(0, 255)) for i in range(0, 112)])
-        hcname = get_hypercall_name(call_code)
-
-        if hcname == 'HvConnectPort':
-            return
-            self.msg(f'Hypercall: {hcname} ')
-            hciv = hv_hciv(0, 0, call_code)
-            for i in range(0x0, 0xFFFFF):
-                buffer = pack('<5Q', i & 0xF, (i >> 4) & 0xF, (i >> 8) & 0xF, (i >> 12) & 0xF, (i >> 16) & 0xF)
-                result = self.hv.hypercall64_memory_based(hciv, buffer)
-                statistics[result] = 1 if result not in statistics else statistics[result] + 1
-
-        elif hcname == 'HvPostMessage':
-            self.msg(f'Hypercall: {hcname} ')
-            hciv = hv_hciv(0, 0, call_code)
-            for connid in sorted(self.hv_connectionid.keys()):
-                if self.hv_connectionid[connid] == HV_PORT_TYPE_MESSAGE:
-                    self.msg(f'Connection ID: : {connid:08X}')
-                    for i in range(0x100, 0x1000):
-                        messagetype = 0x7FFFFFFF & getrandbits(32)
-                        payloadsize = randint(0, 240)
-                        message0 = getrandbits(8)
-                        buffer = pack('<4LQ', connid, 0, messagetype, payloadsize, message0)
-                        result = hv.hypercall64_memory_based(hciv, buffer)
-                        statistics[result] = 1 if result not in statistics else statistics[result] + 1
-                        self.dbg(f'HvPostMessage: {get_hypercall_status(result)} {buffer.hex()}')
-
-        elif hcname == 'HvSignalEvent':
-            self.msg(f'Hypercall: {hcname} ')
-            hciv = hv_hciv(0, 0, call_code)
-            for connid in sorted(self.hv_connectionid.keys()):
-                if self.hv_connectionid[connid] == HV_PORT_TYPE_EVENT:
-                    self.msg(f'Connection ID: {connid:08X}')
-                    for i in range(min(total_tests, 0xFFFF)):
-                        buffer = pack('<LHH', connid, 0, i)
-                        result = self.hv.hypercall64_memory_based(hciv, buffer)
-                        statistics[result] = 1 if result not in statistics else statistics[result] + 1
-
-        if len(statistics) > 0:
-            self.msg('*************** Status codes statistics: *****************')
-            for i in sorted(statistics.keys()):
-                self.msg(f'{get_hypercall_status(i):50}: {statistics[i]:d}')
-
-        return

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/hypercallfuzz.html b/_modules/chipsec/modules/tools/vmm/hv/hypercallfuzz.html
deleted file mode 100644
index 5bbb0eef..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/hypercallfuzz.html
+++ /dev/null
@@ -1,276 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.hypercallfuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.hypercallfuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V hypercall fuzzer
-
-Usage:
-  ``chipsec_main.py -i -m tools.vmm.hv.hypercall -a <mode>[,<vector>,<iterations>] -l log.txt``
-
-    - ``mode``			fuzzing mode
-
-        * ``= status-fuzzing``	finding parameters with hypercall success status
-        * ``= params-info``	shows input parameters valid ranges
-        * ``= params-fuzzing``	parameters fuzzing based on their valid ranges
-        * ``= custom-fuzzing``	fuzzing of known hypercalls
-    - ``vector``		hypercall vector
-    - ``iterations``		number of hypercall iterations
-
-Note: the fuzzer is incompatible with native VMBus driver (``vmbus.sys``). To use it, remove ``vmbus.sys``
-"""
-from chipsec.modules.tools.vmm.hv.define import *
-from chipsec.modules.tools.vmm.hv.hypercall import *
-from chipsec.module_common import *
-
-# Hypercall vectors excluded from scan/fuzzing
-excluded_hypercalls_from_scan = []
-excluded_hypercalls_from_fuzzing = excluded_hypercalls_from_scan + [HV_POST_MESSAGE]
-
-
-

-[docs]
-class HypercallFuzz(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x6dc9bb0, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.html')
-
-

-[docs]
-    def usage(self):
-        print('  Usage:')
-        print('    chipsec_main.py -i -m tools.vmm.hv.hypercall [-a mode,vector,iterations]')
-        print('      mode                fuzzing mode')
-        print('        = status-fuzzing  finding parameters with hypercall success status')
-        print('        = params-info     shows input parameters valid ranges')
-        print('        = params-fuzzing  parameters fuzzing based on their valid ranges')
-        print('        = custom-fuzzing  fuzzing of known hypercalls')
-        print('      vector              hypercall vector')
-        print('      iterations          number of hypercall iterations')
-        print('  Note: the fuzzer is incompatible with native VMBus driver (vmbus.sys). To use it, remove vmbus.sys')
-        return

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Hyper-V hypercall fuzzer")
-
-        if len(module_argv) > 0:
-            command = module_argv[0]
-        else:
-            self.usage()
-            return
-
-        callnum = get_int_arg(module_argv[1]) if len(module_argv) > 1 and module_argv[1] != '' else 'all'
-        testnum = get_int_arg(module_argv[2]) if len(module_argv) > 2 and module_argv[2] != '' else 10000000
-
-        hv = HyperVHypercall()
-        hv.promt = 'CHIPSEC'
-
-        hv.print_hypervisor_info()
-
-        if hv.hypervisor_present:
-            hv.scan_partitionid(range(0x0, 0x100))
-            hv.scan_connectionid(range(0x00000, 0x00100) + range(0x10000, 0x10100))
-
-            # Scans for implemented hypercalls and discovers their interface
-            hypercalls_for_scanning = list(set(range(0x100)) - set(excluded_hypercalls_from_scan))
-            hv.scan_hypercalls(hypercalls_for_scanning)
-
-        if callnum == 'all':
-            hypercalls = list(set(hv.hv_hypercalls.keys()) - set(excluded_hypercalls_from_fuzzing))
-        else:
-            hypercalls = [callnum]
-
-        if command == 'info':
-            if hv.hypervisor_present:
-                # Print Synthetic MSRs
-                hv.print_synthetic_msrs()
-
-                # Print Partition IDs
-                hv.print_partitionid()
-
-                # Print Connection IDs
-                hv.print_connectionid([])
-                hv.print_partition_properties()
-
-                # Print discovered hypercalls and their interface
-                hv.print_hypercall_status()
-
-        elif command == 'status-fuzzing':
-            for i in hypercalls:
-                hv.promt = f'HYPERCALL {i:04X}'
-                hv.msg('[*] Scan hypercall for success status')
-                hv.scan_for_success_status(i, testnum)
-
-        elif command == 'params-info':
-            for i in hypercalls:
-                hv.promt = f'HYPERCALL {i:04X}'
-                if (hv.hv_hypercalls[i][2] == HV_STATUS_SUCCESS):
-                    hv.msg('Scan hypercall for input parameters')
-                    hv.scan_input_parameters(i, 32)
-                    hv.print_input_parameters(i, 32, [HV_STATUS_SUCCESS])
-
-        elif command == 'params-fuzzing':
-            for i in hypercalls:
-                hv.promt = f'HYPERCALL {i:04X}'
-                if (hv.hv_hypercalls[i][2] == HV_STATUS_SUCCESS):
-                    hv.msg('Fuzzing hypercall for input parameters')
-                    hv.scan_input_parameters(i, 32)
-                    hv.print_input_parameters(i, 32, [HV_STATUS_SUCCESS])
-                    hv.input_parameters_fuzzing(i, 32, [HV_STATUS_SUCCESS], testnum)
-
-        elif command == 'custom-fuzzing':
-            for i in hypercalls:
-                hv.promt = f'HYPERCALL {i:04X}'
-                hv.custom_fuzzing(i, testnum)
-
-        else:
-            hv.err('Invalid mode!')
-            self.usage()
-
-        self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-        return self.rc_res.getReturnCode(ModuleResult.PASSED)

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/synth_dev.html b/_modules/chipsec/modules/tools/vmm/hv/synth_dev.html
deleted file mode 100644
index 19079889..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/synth_dev.html
+++ /dev/null
@@ -1,304 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.synth_dev — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.synth_dev
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V VMBus synthetic device generic fuzzer
-
-Usage:
-
-  Print channel offers:
-
-  ``chipsec_main.py -i -m tools.vmm.hv.synth_dev -a info``
-
-  Fuzzing device with specified relid:
-
-  ``chipsec_main.py -i -m tools.vmm.hv.synth_dev -a fuzz,<relid> -l log.txt``
-
-Note: the fuzzer is incompatible with native VMBus driver (``vmbus.sys``). To use it, remove ``vmbus.sys``
-"""
-import time
-import traceback
-from struct import *
-from random import *
-from chipsec.modules.tools.vmm.hv.define import *
-from chipsec.modules.tools.vmm.common import *
-from chipsec.modules.tools.vmm.hv.vmbus import *
-import chipsec_util
-
-sys.stdout = session_logger(True, 'synth_dev')
-
-
-

-[docs]
-class VMBusDeviceFuzzer(VMBusDiscovery):
-    def __init__(self):
-        VMBusDiscovery.__init__(self)
-        self.responses = {}
-
-

-[docs]
-    def send_1(self, relid, messages, info, order):
-        if len(messages) > 0:
-            msg_sent = messages.pop(0)
-            self.vmbus_sendpacket(relid, msg_sent, 0x0, VM_PKT_DATA_INBAND, VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED)
-            msg_recv = self.vmbus_recvpacket(relid)
-            if msg_recv != '':
-                (msg1, msg2) = (msg_recv, msg_sent) if order else (msg_sent, msg_recv)
-                if msg1 not in info:
-                    info[msg1] = {'next': {}, 'count': 0, 'message': ''}
-                info[msg1]['count'] += 1
-                info[msg1]['message'] = msg2
-                info[msg1]['next'] = self.send_1(relid, messages, info[msg1]['next'], order)
-        return info

-
-
-

-[docs]
-    def device_fuzzing(self, relid):
-        for x in range(1, 0x100):
-            for a in range(0, 0x100):
-                self.ringbuffers[relid].ringbuffer_init()
-                self.vmbus_establish_gpadl(relid, self.ringbuffers[relid].gpadl, self.ringbuffers[relid].pfn)
-                self.vmbus_open(relid, self.ringbuffers[relid].gpadl, self.ringbuffers[relid].send_size)
-                msg = pack('<LL', x, ((a & 0xf0) << 12) | (a % 0x0f))
-                try:
-                    self.responses = self.send_1(relid, [msg], self.responses, True)
-                finally:
-                    self.vmbus_close(relid)
-                    self.vmbus_teardown_gpadl(relid, self.ringbuffers[relid].gpadl)
-        return

-
-
-

-[docs]
-    def print_1(self, info, indent=0):
-        if len(info) == 0:
-            return
-        for i in self.responses:
-            self.msg(f'{"  " * indent}{i.hex():20}:{info[i]["message"].hex():20}  {info[i]["count"]:4d}')
-            self.print_1(info[i]['next'], indent + 1)
-        return

-
-
-

-[docs]
-    def print_statistics(self):
-        self.msg('Response statistics:')
-        self.print_1(self.responses)
-        return

-

-
-
-
-

-[docs]
-class synth_dev(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x6221b7e, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_dev.html')
-
-

-[docs]
-    def usage(self):
-        print('  Usage:')
-        print('    chipsec_main.py -i -m tools.vmm.hv.synth_dev -a info')
-        print('      print channel offers')
-        print('    chipsec_main.py -i -m tools.vmm.hv.synth_dev -a fuzz,<relid>')
-        print('      fuzzing device with specified relid')
-        print('  Note: the fuzzer is incompatible with native VMBus driver (vmbus.sys). To use it, remove vmbus.sys')
-        return

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Hyper-V VMBus synthetic device fuzzer")
-
-        command = module_argv[0] if len(module_argv) > 0 and module_argv[0] != '' else 'none'
-        relid = get_int_arg(module_argv[1]) if len(module_argv) > 1 and module_argv[1] != '' else 0x5
-
-        vb = VMBusDeviceFuzzer()
-        vb.debug = False
-        vb.vmbus_init()
-        try:
-            vb.vmbus_connect()
-            vb.vmbus_request_offers()
-
-            if relid not in [value['child_relid'] for value in vb.offer_channels.values()]:
-                vb.fatal(f'child relid #{relid:d} has not been found!')
-
-            vb.ringbuffers[relid] = RingBuffer()
-            vb.ringbuffers[relid].debug = False
-            vb.ringbuffers[relid].ringbuffer_alloc(4)
-            vb.ringbuffers[relid].gpadl = vb.vmbus_get_next_gpadl()
-
-            if command == 'info':
-                vb.vmbus_establish_gpadl(relid, vb.ringbuffers[relid].gpadl, vb.ringbuffers[relid].pfn)
-                vb.vmbus_open(relid, vb.ringbuffers[relid].gpadl, vb.ringbuffers[relid].send_size)
-                vb.print_offer_channels()
-                vb.print_created_gpadl()
-                vb.print_open_channels()
-                vb.vmbus_close(relid)
-                vb.vmbus_teardown_gpadl(relid, vb.ringbuffers[relid].gpadl)
-            elif command == 'fuzz':
-                vb.promt = f'DEVICE {relid:02d}'
-                vb.msg('Fuzzing VMBus devices ...')
-                vb.device_fuzzing(relid)
-                vb.print_statistics()
-            else:
-                self.usage()
-
-        except KeyboardInterrupt:
-            print('***** Control-C *****')
-        except Exception as error:
-            print('\n\n')
-            traceback.print_exc()
-            print('\n\n')
-        finally:
-            vb.vmbus_rescind_all_offers()
-            del vb
-        self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-        return self.rc_res.getReturnCode(ModuleResult.PASSED)

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/synth_kbd.html b/_modules/chipsec/modules/tools/vmm/hv/synth_kbd.html
deleted file mode 100644
index 896a5254..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/synth_kbd.html
+++ /dev/null
@@ -1,295 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.synth_kbd — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.synth_kbd
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V VMBus synthetic keyboard fuzzer. Fuzzes inbound ring buffer in VMBus virtual keyboard device.
-
-Usage:
-  ``chipsec_main.py -i -m tools.vmm.hv.synth_kbd -a fuzz -l log.txt``
-
-Note: the fuzzer is incompatible with native VMBus driver (``vmbus.sys``). To use it, remove ``vmbus.sys``
-"""
-import traceback
-from struct import *
-from random import *
-from chipsec.modules.tools.vmm.hv.define import *
-from chipsec.modules.tools.vmm.common import *
-from chipsec.modules.tools.vmm.hv.vmbus import *
-from chipsec.defines import *
-import chipsec_util
-
-SYNTH_KBD_VERSION = 0x00010000
-SYNTH_KBD_PROTOCOL_REQUEST = 1
-SYNTH_KBD_PROTOCOL_RESPONSE = 2
-SYNTH_KBD_EVENT = 3
-SYNTH_KBD_LED_INDICATORS = 4
-
-sys.stdout = session_logger(True, 'synth_kbd')
-
-
-

-[docs]
-class RingBufferFuzzer(RingBuffer):
-    def __init__(self):
-        RingBuffer.__init__(self)
-        self.fuzzing = False
-        self.count = 0
-
-    ##
-    # ringbuffer_read - Fuzzing recv ring buffer pointers
-    ##
-

-[docs]
-    def ringbuffer_read(self):
-        if self.fuzzing:
-            buffer = self.cs.mem.read_physical_mem(self.pfn[self.send_size], 0x10)
-            write_index, read_index, interrupt_mask, pending_send_sz = unpack('<4L', buffer)
-            overwrite(buffer, DD(randint(0, 0xFFFFFFFF)), 4 * randint(0, 3))
-            self.cs.mem.write_physical_mem(self.pfn[self.send_size], len(buffer), buffer)
-            result = ''
-            self.count += 1
-            if self.count > 1000000:
-                raise Exception
-        else:
-            result = RingBuffer.ringbuffer_read(self)
-        return result

-

-
-
-
-

-[docs]
-class synth_kbd(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x0d28d62, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.synth_kbd.html')
-
-

-[docs]
-    def usage(self):
-        print('  Usage:')
-        print('    chipsec_main.py -i -m tools.vmm.hv.synth_kbd -a fuzz')
-        print('  Note: the fuzzer is incompatible with native VMBus driver (vmbus.sys). To use it, remove vmbus.sys')
-        return

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Hyper-V VMBus virtual keyboard fuzzer")
-
-        if len(module_argv) > 0:
-            command = module_argv[0]
-        else:
-            self.usage()
-            self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_OPTION)
-            return self.rc_res.getReturnCode(ModuleResult.ERROR)
-
-        vb = VMBusDiscovery()
-        vb.debug = True
-        vb.promt = 'VMBUS KBD'
-        vb.vmbus_init()
-        vb.vmbus_connect()
-        vb.vmbus_request_offers()
-        relid = vb.get_relid_by_guid(HV_KBD_GUID)
-        if relid == 0:
-            vb.fatal(f'Could not found keyboard device with GUID: {HV_KBD_GUID}')
-
-        vb.ringbuffers[relid] = RingBufferFuzzer()
-        vb.ringbuffers[relid].ringbuffer_alloc(4)
-        vb.ringbuffers[relid].gpadl = vb.vmbus_get_next_gpadl()
-
-        vb.vmbus_establish_gpadl(relid, vb.ringbuffers[relid].gpadl, vb.ringbuffers[relid].pfn)
-        vb.vmbus_open(relid, vb.ringbuffers[relid].gpadl, vb.ringbuffers[relid].send_size)
-        try:
-            vb.print_offer_channels()
-            vb.print_created_gpadl()
-            vb.print_open_channels()
-
-            synth_kbd_protocol_request = pack('<LL', SYNTH_KBD_PROTOCOL_REQUEST, SYNTH_KBD_VERSION)
-            vb.vmbus_sendpacket(relid, synth_kbd_protocol_request, 0x0, VM_PKT_DATA_INBAND, VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED)
-            synth_kbd_protocol_response = vb.vmbus_recvpacket(relid)
-            if len(synth_kbd_protocol_response) != 8:
-                vb.fatal('Invalid response from synthetic keyboard!')
-            msg_type, proto_status = unpack('<LL', synth_kbd_protocol_response)
-            if (proto_status & 0x1) == 0x1:
-                vb.msg('synth_kbd protocol request has been accepted!')
-                vb.ringbuffers[relid].debug = False
-                vb.debug = False
-                while True:
-                    synth_kbd_msg = vb.vmbus_recvpacket(relid)
-                    if not synth_kbd_msg:
-                        continue
-                    if len(synth_kbd_msg) < 12:
-                        vb.hex('invalid message', synth_kbd_msg)
-                        continue
-                    msg_type, code, rsvd, info = unpack('<LHHL', synth_kbd_msg[:12])
-                    if msg_type == SYNTH_KBD_EVENT:
-                        vb.msg(f'keystroke: {code:04X}  flags: {info:08X}')
-                        vb.ringbuffers[relid].fuzzing = (command == 'fuzzing')
-                        if code == 0x0046:
-                            vb.msg('*** Control Break ***')
-                            vb.ringbuffers[relid].fuzzing = False
-                            break
-                    else:
-                        vb.hex(f'unhandled message type: {msg_type:d}', synth_kbd_msg)
-            else:
-                vb.err('synth_kbd protocol request has failed!')
-
-        except KeyboardInterrupt:
-            print('***** Control-C *****')
-        except Exception as error:
-            print('\n\n')
-            traceback.print_exc()
-            print('\n\n')
-        finally:
-            vb.vmbus_close(relid)
-            vb.vmbus_teardown_gpadl(relid, vb.ringbuffers[relid].gpadl)
-            vb.vmbus_rescind_all_offers()
-            del vb.ringbuffers[relid]
-            del vb
-        self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-        return self.rc_res.getReturnCode(ModuleResult.PASSED)

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/vmbus.html b/_modules/chipsec/modules/tools/vmm/hv/vmbus.html
deleted file mode 100644
index 7c2c733e..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/vmbus.html
+++ /dev/null
@@ -1,1022 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.vmbus — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.hv.vmbus
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V VMBus functionality
-"""
-import os
-import sys
-import time
-import chipsec_util
-from struct import *
-from random import *
-from chipsec.modules.tools.vmm.common import *
-from chipsec.modules.tools.vmm.hv.define import *
-from chipsec.logger import *
-from chipsec.file import *
-from chipsec.module_common import *
-from chipsec.hal.vmm import VMM
-from chipsec.defines import *
-
-
-

-[docs]
-class RingBuffer(BaseModuleDebug):
-    def __init__(self):
-        BaseModuleDebug.__init__(self)
-        self.promt = 'RING BUFFER'
-        self.signal = True
-        self.send_size = 0
-        self.base_addr = []
-        self.pfn = []
-
-    def __del__(self):
-        BaseModuleDebug.__del__(self)
-        self.dbg('Free kernel memory (pfn pages)')
-        # for addr in self.base_addr:
-        #    self.cs.mem.free_physical_mem(addr)
-        self.base_addr = []
-        self.send_size = 0
-        self.pfn = []
-
-    ##
-    # ringbuffer_alloc - allocates kernel memory for ring buffer
-    ##
-

-[docs]
-    def ringbuffer_alloc(self, pages=4):
-        (va, pa) = self.cs.mem.alloc_physical_mem(pages << 12, 0xFFFFFFFFFFFFFFFF)
-        self.base_addr.append(va)
-        if pa != 0:
-            for i in range(pages):
-                self.pfn.append(pa + (i << 12))
-            self.ringbuffer_init()
-        self.send_size = pages >> 1
-        return pa != 0

-
-
-    ##
-    # ringbuffer_init - init data and control structures in the ring buffer
-    ##
-

-[docs]
-    def ringbuffer_init(self):
-        init_page = '\x00' * 0x1000
-        for addr in self.pfn:
-            self.cs.mem.write_physical_mem(addr, len(init_page), init_page)
-        return

-
-
-    ##
-    # ringbuffer_copyfrom - routine to copy to source from ring buffer
-    ##
-

-[docs]
-    def ringbuffer_copyfrom(self, index, total):
-        ring_data_page = self.send_size + 1
-        ring_data_size = len(self.pfn) - self.send_size - 1
-        data = ''
-        while total > 0:
-            page = ring_data_page + (index >> 12) % ring_data_size
-            addr = self.pfn[page] + (index & 0xFFF)
-            size = min(total, 0x1000 - (index & 0xFFF))
-            data += self.cs.mem.read_physical_mem(addr, size)
-            total -= size
-            index += size
-        return data

-
-
-    ##
-    # ringbuffer_copyto - routine to copy from source to ring buffer
-    ##
-

-[docs]
-    def ringbuffer_copyto(self, index, data):
-        ring_data_page = 1
-        ring_data_size = self.send_size - 1
-        while data:
-            page = ring_data_page + (index >> 12) % ring_data_size
-            addr = self.pfn[page] + (index & 0xFFF)
-            size = min(len(data), 0x1000 - (index & 0xFFF))
-            self.cs.mem.write_physical_mem(addr, size, data[:size])
-            data = data[size:]
-            index += size
-        return

-
-
-    ##
-    # ringbuffer_read - Read and advance the read index
-    ##
-

-[docs]
-    def ringbuffer_read(self):
-        ring_data_size = (len(self.pfn) - self.send_size - 1) << 12
-        buffer = self.cs.mem.read_physical_mem(self.pfn[self.send_size], 0x10)
-        write_index, read_index, interrupt_mask, pending_send_sz = unpack('<4L', buffer)
-        delta = write_index - read_index
-        avail = delta if delta >= 0 else ring_data_size + delta
-        if avail == 0:
-            return ''
-        header = self.ringbuffer_copyfrom(read_index, 16)
-        pksize = 8 * unpack('<4HQ', header)[2] + 8
-        buffer = self.ringbuffer_copyfrom(read_index, pksize)
-        read_index = (read_index + pksize) % ring_data_size
-        self.cs.mem.write_physical_mem(self.pfn[self.send_size] + 4, 4, DD(read_index))
-        return buffer[:pksize - 8]

-
-
-    ##
-    # ringbuffer_write - Write to the ring buffer
-    ##
-

-[docs]
-    def ringbuffer_write(self, data):
-        ring_data_size = (self.send_size - 1) << 12
-        buffer = self.cs.mem.read_physical_mem(self.pfn[0], 0x10)
-        write_index, read_index, interrupt_mask, pending_send_sz = unpack('<4L', buffer)
-        delta = read_index - write_index
-        avail = delta if delta > 0 else ring_data_size + delta
-        data += DD(0) + DD(write_index)
-        if avail < len(data):
-            return False
-        self.ringbuffer_copyto(write_index, data)
-        write_index = (write_index + len(data)) % ring_data_size
-        self.cs.mem.write_physical_mem(self.pfn[0] + 0, 4, DD(write_index))
-        self.signal = True
-        return True

-
-
-

-[docs]
-    def ringbuffer_read_with_timeout(self, timeout=0):
-        self.dbg('Read and advance the read index ...')
-        start_time = time.time()
-        polling = True
-        while polling:
-            message = self.ringbuffer_read()
-            polling = ((timeout == 0) or (time.time() - start_time <= timeout)) and not message
-        return message

-
-
-

-[docs]
-    def ringbuffer_write_with_timeout(self, message, timeout=0):
-        self.dbg('Write to the ring buffer ...')
-        start_time = time.time()
-        polling = True
-        while polling:
-            result = self.ringbuffer_write(message)
-            polling = ((timeout == 0) or (time.time() - start_time <= timeout)) and not result
-        return result

-

-
-
-
-

-[docs]
-class HyperV(BaseModuleDebug):
-    def __init__(self):
-        BaseModuleDebug.__init__(self)
-        self.hypercall = VMM(self.cs)
-        self.hypercall.init()
-        self.membuf = self.cs.mem.alloc_physical_mem(4 * 0x1000, 0xFFFFFFFF)
-        self.cs.mem.write_physical_mem(self.membuf[1], 4 * 0x1000, '\x00' * 4 * 0x1000)
-        self.old_sint2 = []
-        self.old_simp = []
-        self.old_siefp = []
-        self.simp = []
-        self.siefp = []
-
-    def __del__(self):
-        BaseModuleDebug.__del__(self)
-        self.dbg('Free kernel memory')
-        # if self.membuf[0] != 0:
-        #    self.cs.mem.free_physical_mem(self.membuf[0])
-        if len(self.old_sint2) == 2:
-            self.cs.msr.write_msr(0, HV_X64_MSR_SINT2, self.old_sint2[0], self.old_sint2[1])
-        if len(self.old_simp) == 2:
-            self.cs.msr.write_msr(0, HV_X64_MSR_SIMP, self.old_simp[0], self.old_simp[1])
-        if len(self.old_siefp) == 2:
-            self.cs.msr.write_msr(0, HV_X64_MSR_SIEFP, self.old_siefp[0], self.old_siefp[1])
-        for i in [x for x in self.ringbuffers]:
-            del self.ringbuffers[i]
-
-    ##
-    # hv_init
-    ##
-

-[docs]
-    def hv_init(self):
-        self.old_sint2 = self.cs.msr.read_msr(0, HV_X64_MSR_SINT2)
-        self.old_simp = self.cs.msr.read_msr(0, HV_X64_MSR_SIMP)
-        self.old_siefp = self.cs.msr.read_msr(0, HV_X64_MSR_SIEFP)
-        pa = self.membuf[1]
-        self.sint3 = self.cs.msr.read_msr(0, HV_X64_MSR_SINT3)
-        self.cs.msr.write_msr(0, HV_X64_MSR_SINT2, self.sint3[0], self.sint3[1])
-        self.cs.msr.write_msr(0, HV_X64_MSR_SIEFP, (pa & 0xFFFFFFFF) | 0x1, pa >> 32)
-        #self.cs.msr.write_msr(0, HV_X64_MSR_SCONTROL, 0x1, 0x0)
-        self.simp = self.cs.msr.read_msr(0, HV_X64_MSR_SIMP)
-        self.siefp = self.cs.msr.read_msr(0, HV_X64_MSR_SIEFP)
-        self.simp = (self.simp[0] + (self.simp[1] << 32)) & 0xFFFFFFFFFFFFF000
-        self.siefp = (self.siefp[0] + (self.siefp[1] << 32)) & 0xFFFFFFFFFFFFF000
-        return

-
-
-    ##
-    # hv_post_msg - Send a message
-    ##
-

-[docs]
-    def hv_post_msg(self, message):
-        retries = 3
-        hciv = hv_hciv(0, 0, HV_POST_MESSAGE)
-        while retries > 0:
-            result = self.hypercall.hypercall64_memory_based(hciv, message[:0x100]) & 0xFFFF
-            if result == HV_STATUS_INSUFFICIENT_BUFFERS:
-                retries -= 1
-                time.sleep(0.1)
-            else:
-                retries = 0
-        return result

-
-
-    ##
-    # hv_recv_msg - recieve message if exist otherwise empty string
-    ##
-

-[docs]
-    def hv_recv_msg(self, sint):
-        buffer = self.cs.mem.read_physical_mem(self.simp + 0x100 * sint, 0x100)
-        message_type, payload_size, message_flags = unpack('<LBB', buffer[0:6])
-        if message_type == HVMSG_NONE:
-            buffer = ''
-        else:
-            self.cs.mem.write_physical_mem(self.simp + 0x100 * sint, 0x4, DD(HVMSG_NONE))
-            if message_flags & 0x1:
-                self.cs.msr.write_msr(0, HV_X64_MSR_EOM, 0x0, 0x0)
-        return buffer

-
-
-    ##
-    # hv_signal_event - send an event notification
-    ##
-

-[docs]
-    def hv_signal_event(self, connection_id, flag_number):
-        hciv = hv_hciv(0, 0, HV_SIGNAL_EVENT)
-        buffer = pack('<LHH', connection_id, flag_number, 0x0)
-        result = self.hypercall.hypercall64_memory_based(hciv, buffer) & 0xFFFF
-        return result

-
-
-    ##
-    # hv_recv_events - recieve all current events
-    ##
-

-[docs]
-    def hv_recv_events(self, sint):
-        events = set()
-        buffer = self.cs.mem.read_physical_mem(self.siefp + 0x100 * sint, 0x100)
-        buffer = unpack('<64L', buffer)
-        for i in range(64):
-            if buffer[i]:
-                for n in range(32):
-                    if (buffer[i] >> n) & 0x1:
-                        events.add(i * 32 + n)
-        return events

-

-
-
-
-

-[docs]
-class VMBus(HyperV):
-    def __init__(self):
-        HyperV.__init__(self)
-        self.promt = 'VMBUS'
-        self.onmessage_timeout = 0.1  # 0.02
-        self.int_page = self.membuf[1] + 1 * 0x1000
-        self.monitor_page1 = self.membuf[1] + 2 * 0x1000
-        self.monitor_page2 = self.membuf[1] + 3 * 0x1000
-        self.recv_int_page = self.int_page + 0x000
-        self.send_int_page = self.int_page + 0x800
-        self.supported_versions = {}
-        self.offer_channels = {}
-        self.open_channels = {}
-        self.created_gpadl = {}
-        self.ringbuffers = {}
-        self.next_gpadl = 0x200E1E10
-
-    ##
-    # vmbus_init
-    ##
-

-[docs]
-    def vmbus_init(self):
-        self.hv_init()
-        self.vmbus_clear()
-        return

-
-
-    ##
-    # vmbus_clear
-    ##
-

-[docs]
-    def vmbus_clear(self):
-        # Purge hypervisor message queue
-        while self.vmbus_recv_msg(0.1):
-            pass
-        return

-
-
-    ##
-    # vmbus_get_next_gpadl
-    ##
-

-[docs]
-    def vmbus_get_next_gpadl(self):
-        self.next_gpadl += 1
-        return self.next_gpadl

-
-
-    ##
-    # vmbus_post_msg - send a msg on the vmbus's message connection
-    ##
-

-[docs]
-    def vmbus_post_msg(self, message):
-        if len(message) > 240:
-            self.err('vmbus_post_msg: message it too long {:d} bytes'.format(len(message)))
-            message = message[:240]
-        header = pack('<4L', VMBUS_MESSAGE_CONNECTION_ID, 0x0, 0x1, len(message))
-        result = self.hv_post_msg(header + message)
-        if result != HV_STATUS_SUCCESS:
-            status = hypercall_status_codes[result] if result in hypercall_status_codes else ''
-            self.err('vmbus_post_msg returns  {:02X} {}'.format(result, status))
-        return result == HV_STATUS_SUCCESS

-
-
-    ##
-    # vmbus_recv_msg - recieve message. it may return empty string in case of timeout
-    ##
-

-[docs]
-    def vmbus_recv_msg(self, timeout=0):
-        start_time = time.time()
-        polling = True
-        while polling:
-            message = self.hv_recv_msg(VMBUS_MESSAGE_SINT)
-            polling = ((timeout == 0) or (time.time() - start_time <= timeout)) and not message
-        if message:
-            msg_type, payload_size, msg_flags, rsvd, port_id = unpack('<LBBHQ', message[0:16])
-            if msg_type not in [HVMSG_NONE, 0x0001]:
-                status = hv_message_type[msg_type] if msg_type in hv_message_type else ''
-                self.fatal('vmbus_recv_msg: unhandeled message type 0x{:08X} {}'.format(msg_type, status))
-            if (payload_size < 8) or (payload_size > 240):
-                self.msg('vmbus_recv_msg: invalid payload size {:d}'.format(payload_size))
-                payload_size = 240
-            if rsvd != 0x0000:
-                self.msg('vmbus_recv_msg: invalid reserved field 0x{:04X}'.format(rsvd))
-            # if port_id != VMBUS_MESSAGE_PORT_ID:
-            #    self.msg('vmbus_recv_msg: invalid ConnectionID 0x%016x' % port_id)
-            message = message[16: 16 + payload_size]
-        return message

-
-
-    ##
-    # vmbus_setevent - Trigger an event notification on the specified channel
-    ##
-

-[docs]
-    def vmbus_setevent(self, child_relid):
-        self.dbg('Trigger an event notification on the specified channel ...')
-        if child_relid not in self.open_channels:
-            self.err('vmbus_setevent could not find channel with child relid: {:d}'.format(child_relid))
-            return False
-        channel = self.open_channels[child_relid]['offer']
-        if channel['monitor_allocated'] == 1:
-            monitor_bit = channel['monitor_id'] & 0x1F
-            monitor_grp = channel['monitor_id'] >> 5
-            trigger_group_offset = 8 + 8 * monitor_grp
-            self.cs.mem.set_mem_bit(self.send_int_page, child_relid)
-            self.cs.mem.set_mem_bit(self.monitor_page2 + trigger_group_offset, monitor_bit)
-        else:
-            # Send an event notification to the parent
-            self.dbg('Send an event notification to the parent ...')
-            self.cs.mem.set_mem_bit(self.send_int_page, child_relid)
-            result = self.hv_signal_event(channel['connection_id'], 0x0)
-            if result != 0:
-                status = hypercall_status_codes[result] if result in hypercall_status_codes else ''
-                self.err('vmbus_setevent returns  {:02X} {}'.format(result, status))
-                return False
-        return True

-
-
-    ##
-    # vmbus_recv_events - recieve all current events
-    ##
-

-[docs]
-    def vmbus_recv_events(self):
-        return self.hv_recv_events(VMBUS_MESSAGE_SINT)

-
-
-    ##
-    # vmbus_get_next_version - returns the next version
-    ##
-

-[docs]
-    def vmbus_get_next_version(self, current_version):
-        versions = {VERSION_WIN8_1: VERSION_WIN8, VERSION_WIN8: VERSION_WIN7, VERSION_WS2008: VERSION_INVAL}
-        return versions[current_version] if current_version in versions else VERSION_INVAL

-
-
-    ##
-    # vmbus_connect - Sends a connect request on the partition service connection
-    ##
-

-[docs]
-    def vmbus_connect(self, vmbus_version=VERSION_WIN8, target_vcpu=0x0):
-        self.dbg('Sending channel initiate msg ...')
-        channel_message_header = pack('<LL', CHANNELMSG_INITIATE_CONTACT, 0x0)
-        channel_initiate_contact = pack('<LLQQQ', vmbus_version, target_vcpu, self.int_page, self.monitor_page1, self.monitor_page2)
-        result = self.vmbus_post_msg(channel_message_header + channel_initiate_contact)
-        if result:
-            result = self.vmbus_onmessage() == CHANNELMSG_VERSION_RESPONSE
-        return result

-
-
-    ##
-    # vmbus_establish_gpadl - Estabish a GPADL for the specified buffer
-    ##
-

-[docs]
-    def vmbus_establish_gpadl(self, child_relid, gpadl, pfn):
-        self.dbg('Estabish a GPADL for the specified buffer ...')
-        byte_offset = 0
-        byte_count = len(pfn) << 12
-        pfn_array = ''.join([DQ(addr >> 12) for addr in pfn])
-        gpa_range = pack('<LL', byte_count, byte_offset) + pfn_array
-        rangecount = 0x1
-        range_buflen = len(gpa_range)
-        channel_message_header = pack('<LL', CHANNELMSG_GPADL_HEADER, 0x0)
-        channel_gpadl_header = pack('<LLHH', child_relid, gpadl, range_buflen, rangecount)
-        result = self.vmbus_post_msg(channel_message_header + channel_gpadl_header + gpa_range[:27 * 8])
-        gpa_range = gpa_range[27 * 8:]
-        while result and gpa_range != '':
-            channel_message_header = pack('<LL', CHANNELMSG_GPADL_BODY, 0x0)
-            channel_gpadl_body = pack('<LL', 0x0, gpadl)
-            result = self.vmbus_post_msg(channel_message_header + channel_gpadl_body + gpa_range[:28 * 8])
-            gpa_range = gpa_range[28 * 8:]
-        if result:
-            result = self.vmbus_onmessage() == CHANNELMSG_GPADL_CREATED
-        return result

-
-
-    ##
-    # vmbus_teardown_gpadl - Teardown the specified GPADL handle
-    ##
-

-[docs]
-    def vmbus_teardown_gpadl(self, child_relid, gpadl):
-        self.dbg('Teardown the specified GPADL handle ...')
-        channel_message_header = pack('<LL', CHANNELMSG_GPADL_TEARDOWN, 0x0)
-        channel_gpadl_teardown = pack('<LL', child_relid, gpadl)
-        result = self.vmbus_post_msg(channel_message_header + channel_gpadl_teardown)
-        if result:
-            msgtype = self.vmbus_onmessage()
-            if msgtype == CHANNELMSG_RESCIND_CHANNELOFFER:
-                self.vmbus_process_rescind_offer(child_relid)
-                result = result and (self.vmbus_onmessage() == CHANNELMSG_GPADL_TORNDOWN)
-                result = result and (self.vmbus_onmessage() == CHANNELMSG_OFFERCHANNEL)
-            else:
-                result = (msgtype == CHANNELMSG_GPADL_TORNDOWN)
-
-        return result

-
-
-    ##
-    # vmbus_open - Open the specified channel
-    ##
-

-[docs]
-    def vmbus_open(self, child_relid, gpadl, pageoffset=2, userdata='\x00' * 120):
-        self.dbg('Open the specified channel ...')
-        openid = child_relid
-        target_vp = 0x0
-        channel_message_header = pack('<LL', CHANNELMSG_OPENCHANNEL, 0x0)
-        channel_open_channel = pack('<5L', child_relid, openid, gpadl, target_vp, pageoffset)
-        result = self.vmbus_post_msg(channel_message_header + channel_open_channel + userdata)
-        if result:
-            result = self.vmbus_onmessage() == CHANNELMSG_OPENCHANNEL_RESULT
-        return result

-
-
-    ##
-    # vmbus_close - Close the specified channel
-    ##
-

-[docs]
-    def vmbus_close(self, child_relid):
-        self.dbg('Close the specified channel ...')
-        channel_message_header = pack('<LL', CHANNELMSG_CLOSECHANNEL, 0x0)
-        channel_close_channel = pack('<L', child_relid)
-        return self.vmbus_post_msg(channel_message_header + channel_close_channel)

-
-
-    ##
-    # vmbus_disconnect - Sends a disconnect request on the partition service connection
-    ##
-

-[docs]
-    def vmbus_disconnect(self):
-        self.dbg('Sending a disconnect request ...')
-        channel_message_header = pack('<LL', CHANNELMSG_UNLOAD, 0x0)
-        result = self.vmbus_post_msg(channel_message_header)
-        result = result and (self.vmbus_onmessage() == 17)
-        return result

-
-
-    ##
-    # vmbus_request_offers - Send a request to get all our pending offers
-    ##
-

-[docs]
-    def vmbus_request_offers(self):
-        self.dbg('Sending a request to get all our pending offers ...')
-        channel_message_header = pack('<LL', CHANNELMSG_REQUESTOFFERS, 0x0)
-        result = self.vmbus_post_msg(channel_message_header)
-        while result:
-            msgtype = self.vmbus_onmessage()
-            if msgtype != CHANNELMSG_OFFERCHANNEL:
-                break
-        return result and (msgtype == CHANNELMSG_ALLOFFERS_DELIVERED)

-
-
-    ##
-    # vmbus_process_rescind_offer - Rescind the offer by initiating a device removal
-    ##
-

-[docs]
-    def vmbus_process_rescind_offer(self, child_relid):
-        self.dbg('Rescind the offer by initiating a device removal ...')
-        channel_message_header = pack('<LL', CHANNELMSG_RELID_RELEASED, 0x0)
-        channel_relid_released = pack('<L', child_relid)
-        return self.vmbus_post_msg(channel_message_header + channel_relid_released)

-
-
-    ##
-    # vmbus_onmessage - Handler for channel protocol messages.
-    ##
-

-[docs]
-    def vmbus_onmessage(self):
-        msgtype = CHANNELMSG_INVALID
-
-        channelmsg = {
-            CHANNELMSG_OFFERCHANNEL: 188,
-            CHANNELMSG_ALLOFFERS_DELIVERED: 0,
-            CHANNELMSG_GPADL_CREATED: 12,
-            CHANNELMSG_OPENCHANNEL_RESULT: 12,
-            CHANNELMSG_GPADL_TORNDOWN: 4,
-            CHANNELMSG_RESCIND_CHANNELOFFER: 4,
-            CHANNELMSG_VERSION_RESPONSE: 8
-        }
-
-        message = self.vmbus_recv_msg(self.onmessage_timeout)
-
-        if len(message) == 0:
-            self.msg('vmbus_onmessage: timeout')
-        elif len(message) >= 8:
-            msgtype, padding = unpack('<LL', message[:8])
-            message_body = message[8:]
-
-            self.dbg('vmbus_onmessage: message {:d} {}'.format(msgtype, vmbus_channel_message_type[msgtype]))
-
-            if msgtype not in channelmsg:
-                self.msg('vmbus_onmessage: invalid message type {:d}'.format(msgtype))
-                self.hex('Message', message)
-            elif channelmsg[msgtype] > len(message_body):
-                self.msg('vmbus_onmessage: message is too short!')
-                self.hex('Message', message)
-                exit(1)
-
-            if padding != 0x00000000:
-                self.msg('vmbus_onmessage invalid padding {:d}'.format(padding))
-
-        # vmbus_ongpadl_created - GPADL created handler
-        if msgtype == CHANNELMSG_GPADL_CREATED:
-            child_relid, gpadl, status = unpack('<3L', message_body[:12])
-            self.created_gpadl[gpadl] = {'child_relid': child_relid, 'status': status}
-        # vmbus_onopen_result - Open result handler
-        elif msgtype == CHANNELMSG_OPENCHANNEL_RESULT:
-            child_relid, openid, status = unpack('<3L', message_body[:12])
-            self.open_channels[child_relid] = {'openid': openid, 'status': status}
-            offer = 'none'
-            for i in self.offer_channels.keys():
-                if self.offer_channels[i]['child_relid'] == child_relid:
-                    offer = self.offer_channels[i]
-                    break
-            self.open_channels[child_relid]['offer'] = offer
-        # vmbus_onversion_response - Version response handler
-        elif msgtype == CHANNELMSG_VERSION_RESPONSE:
-            version_supported, version = unpack('<2L', message_body[:8])
-            if version_supported != 0x00:
-                self.supported_versions[version] = 0x1
-        # vmbus_onoffer - Handler for channel offers from vmbus in parent partition.
-        elif msgtype == CHANNELMSG_OFFERCHANNEL:
-            offer = message_body
-            channel = {}
-            uuid1 = uuid(offer[0x00:0x10])
-            uuid2 = uuid(offer[0x10:0x20])
-            # struct vmbus_channel_offer
-            guid1 = hv_guid_desc[uuid1] if uuid1 in hv_guid_desc else 'Unknown'
-            channel['name'] = guid1
-            channel['flags'] = unpack('<H', offer[0x30: 0x32])[0]
-            channel['mmio'] = unpack('<H', offer[0x32: 0x34])[0]
-            channel['userdef'] = offer[0x34: 0xAC]
-            channel['sub_channel'] = unpack('<H', offer[0xAC: 0xAE])[0]
-            # struct vmbus_channel_offer_channel (continue)
-            channel['child_relid'] = unpack('<L', offer[0xB0: 0xB4])[0]
-            channel['monitor_id'] = unpack('<B', offer[0xB4: 0xB5])[0]
-            channel['monitor_allocated'] = unpack('<B', offer[0xB5: 0xB6])[0] & 0x1
-            channel['dedicated_interrupt'] = unpack('<H', offer[0xB6: 0xB8])[0] & 0x1
-            channel['connection_id'] = unpack('<L', offer[0xB8: 0xBC])[0]
-            self.offer_channels[offer[0x00:0x20]] = channel
-
-        return msgtype

-
-
-    ##
-    # vmbus_recvpacket - Retrieve the user packet on the specified channel
-    ##
-

-[docs]
-    def vmbus_recvpacket(self, child_relid):
-        self.dbg('Retrieve the user packet on the specified channel ...')
-        rb = self.ringbuffers[child_relid]
-        buffer = rb.ringbuffer_read_with_timeout(self.onmessage_timeout)
-        if len(buffer) >= 16:
-            packet_type, offset8, len8, flags, requestid = unpack('<4HQ', buffer[:16])
-            buffer = buffer[16:]
-        return buffer

-
-
-    ##
-    # vmbus_sendpacket - Send the specified buffer on the given channel
-    ##
-

-[docs]
-    def vmbus_sendpacket(self, child_relid, data, requestid, packet_type, flags):
-        self.dbg('Send the specified buffer on the given channel ...')
-        rb = self.ringbuffers[child_relid]
-        while (len(data) & 0x7) != 0:
-            data += '\x00'
-        offset8 = 16 >> 3
-        len8 = offset8 + (len(data) >> 3)
-        vmpacket_descriptor = pack('<4HQ', packet_type, offset8, len8, flags, requestid)
-        rb.ringbuffer_write(vmpacket_descriptor + data)
-        if rb.signal:
-            self.vmbus_setevent(child_relid)
-        return

-
-
-    ##
-    # vmbus_sendpacket_pagebuffer - Send a range of single-page buffer
-    ##
-

-[docs]
-    def vmbus_sendpacket_pagebuffer(self):
-        self.dbg('Send a range of single-page buffer ...')
-        return

-
-
-    ##
-    # vmbus_sendpacket_multipagebuffer - Send a multi-page buffer packet
-    ##
-

-[docs]
-    def vmbus_sendpacket_multipagebuffer(self):
-        self.dbg('Send a multi-page buffer packet ...')
-        return

-
-
-    ##
-    # vmbus_recvpacket_raw - Retrieve the raw packet on the specified channel
-    ##
-

-[docs]
-    def vmbus_recvpacket_raw(self):
-        self.dbg('Retrieve the raw packet on the specified channel ...')
-        return

-

-
-
-
-

-[docs]
-class VMBusDiscovery(VMBus):
-    def __init__(self):
-        VMBus.__init__(self)
-
-    def __del__(self):
-        VMBus.__del__(self)
-
-    ##
-    # vmbus_rescind_all_offers - Rescind all offers by initiating a device removal
-    ##
-

-[docs]
-    def vmbus_rescind_all_offers(self):
-        # for i in self.offer_channels.keys():
-        #    relid = self.offer_channels[i]['child_relid']
-        #    self.vmbus_process_rescind_offer(relid)
-        for i in range(0x10):
-            self.vmbus_process_rescind_offer(i)
-        return

-
-
-    ##
-    # get_relid_by_guid
-    ##
-

-[docs]
-    def get_relid_by_guid(self, guid):
-        relid = 0
-        for i in self.offer_channels.keys():
-            if (guid == uuid(i[0x00:0x10])) or (guid == uuid(i[0x10:0x20])):
-                relid = self.offer_channels[i]['child_relid']
-                break
-        return relid

-
-
-    ##
-    # scan_supported_versions
-    ##
-

-[docs]
-    def scan_supported_versions(self, mask=0x000F000F):
-        version = 0x00000000
-        while True:
-            self.vmbus_connect(version)
-            if version == mask:
-                break
-            version = (~(~version & mask) + 1) & mask
-        return

-
-
-    ##
-    # scan_physical_addresses
-    ##
-

-[docs]
-    def scan_physical_addresses(self, version):
-        pages = (self.int_page, self.monitor_page1, self.monitor_page2)
-        FFs = 0xFFFFFFFFFFFFFFFF
-        for i in range(64):
-            self.supported_versions = {}
-            self.int_page = (FFs << (63 - i)) & FFs
-            self.dbg('Address: 0x{:016X}'.format(self.int_page))
-            self.vmbus_connect(version)
-            print(self.supported_versions)
-        (self.int_page, self.monitor_page1, self.monitor_page2) = pages
-        return

-
-
-    ##
-    # print_supported_versions
-    ##
-

-[docs]
-    def print_supported_versions(self):
-        self.msg('')
-        self.msg('******************** Supported versions ********************')
-        for version in sorted(self.supported_versions.keys()):
-            status = 'Unknown' if version not in vmbus_versions else vmbus_versions[version]
-            self.msg('  {:d} . {:2d} - {}'.format(version >> 16, version & 0xFFFF, status))
-        return

-
-
-    ##
-    # print_offer_channels - Print offered channels
-    ##
-

-[docs]
-    def print_offer_channels(self):
-        self.msg('')
-        self.msg('******************** Offered channels **********************')
-        uuid_sorted_by_connid = dict((value['connection_id'], key) for (key, value) in self.offer_channels.items()).values()
-        for i in uuid_sorted_by_connid:
-            channel = self.offer_channels[i]
-            flags = []
-            for n in range(16):
-                if (n in channel_flags) and (((channel['flags'] >> n) & 0x1) == 0x1):
-                    flags.append(channel_flags[n])
-
-            conid = 'Connection ID: 0x{:08X}'.format(channel['connection_id'])
-            relid = 'Child relid: 0x{:08X}'.format(channel['child_relid'])
-            mmios = 'MMIO: {:d}MB'.format(channel['mmio'])
-            subch = 'Sub channel: 0x{:04X}'.format(channel['sub_channel'])
-            monid = 'Monitor: {:d} ID=0x{:02X}'.format(channel['monitor_allocated'], channel['monitor_id'])
-            dintr = 'Dedicated interrupt: {:d}'.format(channel['dedicated_interrupt'])
-            flags = 'Flags: 0x{:04X} >{}'.format(channel['flags'], ', '.join(flags))
-
-            self.msg('')
-            self.msg('{}'.format(channel['name']))
-            self.msg('  Hardware IDs:  {}   {}'.format(uuid(i[0x00:0x10]), uuid(i[0x10:0x20])))
-            self.msg('  {}   {}   {}   {}'.format(conid, relid, subch, monid))
-            self.msg('  {}   {}   {}'.format(mmios, dintr, flags))
-        return

-
-
-    ##
-    # print_created_gpadl
-    ##
-

-[docs]
-    def print_created_gpadl(self):
-        self.msg('')
-        self.msg('******************** Created GPADLs ************************')
-        self.msg('  gpadl        |  child_relid  |  creation_status  ')
-        self.msg('---------------------------------------------------')
-        for gpadl in sorted(self.created_gpadl.keys()):
-            channel = self.created_gpadl[gpadl]
-            self.msg('  0x{:08X}   |  0x{:08X}   |  0x{:08X}'.format(gpadl, channel['child_relid'], channel['status']))
-        self.msg('---------------------------------------------------')
-        return

-
-
-    ##
-    # print_open_channels
-    ##
-

-[docs]
-    def print_open_channels(self):
-        self.msg('')
-        self.msg('******************** Open Channels *************************')
-        self.msg('  child_relid  |  openid       |  status           ')
-        self.msg('---------------------------------------------------')
-        for child_relid in sorted(self.open_channels):
-            channel = self.open_channels[child_relid]
-            self.msg('  0x{:08X}   |  0x{:08X}   |  0x{:08X}'.format(child_relid, channel['openid'], channel['status']))
-        self.msg('---------------------------------------------------')
-        return

-
-
-    ##
-    # print_events
-    ##
-

-[docs]
-    def print_events(self):
-        events = self.vmbus_recv_events()
-        result = []
-        for i in events:
-            result.append('{:02X}'.format(i))
-        if len(result) != 0:
-            self.msg('EVENTS: ' + ', '.join(result))
-        return

-

-
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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hv/vmbusfuzz.html b/_modules/chipsec/modules/tools/vmm/hv/vmbusfuzz.html
deleted file mode 100644
index 9e0fc9de..00000000
--- a/_modules/chipsec/modules/tools/vmm/hv/vmbusfuzz.html
+++ /dev/null
@@ -1,308 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hv.vmbusfuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
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Source code for chipsec.modules.tools.vmm.hv.vmbusfuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Hyper-V VMBus generic fuzzer
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.hv.vmbusfuzz -a fuzz,<parameters>``
-
-    Parameters:
-
-    - ``all``          : Fuzzing all bytes
-    - ``hv``           : Fuzzing HyperV message header
-    - ``vmbus``        : Fuzzing HyperV message body / VMBUS message
-    - ``<pos>,<size>`` : Fuzzing number of bytes at specific position
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.hv.vmbusfuzz -a fuzz,all -l log.txt
-
-.. note::
-    - The fuzzer is incompatible with native VMBus driver (``vmbus.sys``). To use it, remove ``vmbus.sys``
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import sys
-import traceback
-from struct import pack
-from random import getrandbits, choice
-from chipsec.module_common import ModuleResult
-from chipsec.modules.tools.vmm.common import session_logger, overwrite, get_int_arg
-from chipsec.modules.tools.vmm.hv.vmbus import VMBusDiscovery, HyperV, RingBuffer
-
-sys.stdout = session_logger(True, 'vmbusfuzz')
-
-
-

-[docs]
-class VMBusFuzz(VMBusDiscovery):
-    def __init__(self):
-        VMBusDiscovery.__init__(self)
-        self.training = False
-        self.training_msginfo = []
-        self.fuzzing = False
-        self.fuzzing_rules = {}
-        self.current_message = 0
-        self.rc_res = ModuleResult(0x17f285c, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.html')
-
-    ##
-    # hv_post_msg - Fuzzing a message to be sent
-    ##
-

-[docs]
-    def hv_post_msg(self, message):
-        if self.training:
-            self.training_msginfo.append(len(message))
-        if self.fuzzing:
-            if self.current_message in self.fuzzing_rules:
-                rules = self.fuzzing_rules[self.current_message]
-                for position in rules:
-                    message = overwrite(message, rules[position], position)
-            self.current_message += 1
-        # Randomize leftover bytes. It shouldn't affect functionality.
-        leftovers = ''.join(chr(getrandbits(8)) for _ in range(256 - len(message)))
-        return HyperV.hv_post_msg(self, message + leftovers)

-
-
-

-[docs]
-    def vmbus_test1_run(self):
-        self.debug = False
-        self.vmbus_request_offers()
-        child_relid_list = sorted([value['child_relid'] for value in self.offer_channels.values()])
-
-        if not self.fuzzing:
-            for relid in child_relid_list:
-                self.ringbuffers[relid] = RingBuffer()
-                self.ringbuffers[relid].ringbuffer_alloc(4)
-                self.ringbuffers[relid].gpadl = self.vmbus_get_next_gpadl()
-                self.ringbuffers[relid].debug = False
-
-        for relid in child_relid_list:
-            self.vmbus_establish_gpadl(relid, self.ringbuffers[relid].gpadl, self.ringbuffers[relid].pfn)
-            self.vmbus_open(relid, self.ringbuffers[relid].gpadl, self.ringbuffers[relid].send_size)
-
-        if not self.fuzzing:
-            self.print_supported_versions()
-            self.print_offer_channels()
-            self.print_created_gpadl()
-            self.print_open_channels()
-            self.print_events()
-
-        for relid in child_relid_list:
-            self.vmbus_close(relid)
-            self.vmbus_teardown_gpadl(relid, self.ringbuffers[relid].gpadl)
-
-        self.vmbus_rescind_all_offers()

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Hyper-V VMBus fuzzer")
-
-        if len(module_argv) > 0:
-            command = module_argv[0]
-        else:
-            self.logger.log(self.__doc__.replace('`', ''))
-            return
-
-        cmdarg1 = module_argv[1] if len(module_argv) > 1 else 'all'
-        cmdarg2 = module_argv[2] if len(module_argv) > 2 else '1'
-
-        cmdarg1 = get_int_arg(cmdarg1) if cmdarg1 not in ['all', 'hv', 'vmbus'] else cmdarg1
-        cmdarg2 = max(1, min(8, get_int_arg(cmdarg2)))
-
-        self.debug = False
-        self.promt = 'VMBUS'
-
-        try:
-            self.vmbus_init()
-            self.scan_supported_versions()
-            if len(self.supported_versions):
-                version = choice(self.supported_versions.keys())
-                self.vmbus_clear()
-                self.vmbus_connect(version)
-            self.training = True
-            self.vmbus_test1_run()
-            self.training = False
-
-            if command == 'fuzz':
-                m = 0
-                for n in self.training_msginfo:
-                    range_options = {'all': range(n), 'hv': range(0x10), 'vmbus': range(0x10, n)}
-                    fuzzing_range = range_options[cmdarg1] if cmdarg1 in range_options else [cmdarg1]
-                    fuzzing_range = [x for x in fuzzing_range if x < n]
-                    for i in fuzzing_range:
-                        randstr = pack('<Q', getrandbits(64))[:cmdarg2]
-                        self.fuzzing_rules = {m: {i: randstr}}
-                        self.logger.log(f'[VMBUS] Message: {m + 1:d}/{len(self.training_msginfo):d}  Fuzzing {len(randstr):d} byte(s): position {i:d} out of {n:d}')
-                        self.vmbus_clear()
-                        if len(self.supported_versions):
-                            self.vmbus_connect(version)
-                        self.current_message = 0
-                        self.fuzzing = True
-                        self.vmbus_test1_run()
-                        self.fuzzing = False
-                    m += 1
-        except KeyboardInterrupt:
-            self.logger.log('***** Control-C *****')
-        except Exception:
-            traceback.print_exc()
-        finally:
-            self.vmbus_rescind_all_offers()
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/hypercallfuzz.html b/_modules/chipsec/modules/tools/vmm/hypercallfuzz.html
deleted file mode 100644
index d9839a19..00000000
--- a/_modules/chipsec/modules/tools/vmm/hypercallfuzz.html
+++ /dev/null
@@ -1,316 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.hypercallfuzz — CHIPSEC  documentation
-    
-    
-    
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Source code for chipsec.modules.tools.vmm.hypercallfuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Pretty simple VMM hypercall fuzzer
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.hypercallfuzz [-a <mode>,<vector_reg>,<maxval>,<iterations>]``
-
-    - ``mode``           : Hypercall fuzzing mode
-        * ``exhaustive`` : Fuzz all arguments exhaustively in range ``[0:<maxval>]`` (default)
-        * ``random``     : Send random values in all registers in range ``[0:<maxval>]``
-    - ``vector_reg``     : Hypercall vector register
-    - ``maxval``         : Maximum value of each register
-    - ``iterations``     : Number of iterations in random mode
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.hypercallfuzz
-    >>> chipsec_main.py -i -m tools.vmm.hypercallfuzz -a random,22,0xFFFF,1000
-
-Additional options set within the module:
-    - ``DEFAULT_VECTOR_MAXVAL``     : Default maximum value
-    - ``DEFAULT_MAXVAL_EXHAUSTIVE`` : Default maximum value for exhaustive testing
-    - ``DEFAULT_MAXVAL_RANDOM``     : Default maximum value for random testing
-    - ``DEFAULT_RANDOM_ITERATIONS`` : Default iterations for random testing
-    - ``_FLUSH_LOG_EACH_ITER``      : Set to flush log after each iteration
-    - ``_LOG_ALL_GPRS``             : Display log of each iteration values
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import random
-import time
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.hal.vmm import VMM
-
-DEFAULT_VECTOR_MAXVAL = 0xFF
-
-DEFAULT_MAXVAL_EXHAUSTIVE = 0xFF
-DEFAULT_MAXVAL_RANDOM = 0xFFFFFFFF
-
-DEFAULT_RANDOM_ITERATIONS = 0x7FFFFFFF
-
-# Flush log file before each port
-_FLUSH_LOG_EACH_ITER = False
-_LOG_ALL_GPRS = True
-
-GPRS = {'rax': 0, 'rbx': 0, 'rcx': 0, 'rdx': 0, 'rdi': 0, 'rsi': 0, 'r8': 0, 'r9': 0, 'r10': 0, 'r11': 0}
-
-
-

-[docs]
-class hypercallfuzz(BaseModule):
-
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.vmm = VMM(self.cs)
-
-        self.random_order = True
-        self.gprs = GPRS
-        self.vector_reg = None
-        self.iterations = DEFAULT_RANDOM_ITERATIONS
-        self.maxval = DEFAULT_MAXVAL_RANDOM
-
-

-[docs]
-    def is_supported(self):
-        return True

-
-
-

-[docs]
-    def fuzz_generic_hypercalls(self):
-        _fmt = '{:02X}' if self.maxval <= 0xFF else ('{:04X}' if self.maxval <= 0xFFFF else ('{:08X}' if self.maxval <= 0xFFFFFFFF else '{:016X}'))
-        _str = f'{{:d}} hcall rax={_fmt},rbx={_fmt},rcx={_fmt},rdx={_fmt},rdi={_fmt},rsi={_fmt},r8={_fmt},r9={_fmt},r10={_fmt},r11={_fmt}'
-
-        t = time.time()
-        if self.random_order:
-
-            self.logger.log(f'[*] Fuzzing {self.iterations:d} random hypercalls with random arguments...')
-            for it in range(self.iterations):
-                rax = random.randint(0, self.gprs['rax'])
-                rbx = random.randint(0, self.gprs['rbx'])
-                rcx = random.randint(0, self.gprs['rcx'])
-                rdx = random.randint(0, self.gprs['rdx'])
-                rdi = random.randint(0, self.gprs['rdi'])
-                rsi = random.randint(0, self.gprs['rsi'])
-                r8 = random.randint(0, self.gprs['r8'])
-                r9 = random.randint(0, self.gprs['r9'])
-                r10 = random.randint(0, self.gprs['r10'])
-                r11 = random.randint(0, self.gprs['r11'])
-                if _LOG_ALL_GPRS:
-                    self.logger.log(_str.format(it, rax, rbx, rcx, rdx, rdi, rsi, r8, r9, r10, r11))
-                else:
-                    self.logger.log(f'{it:d} hcall')
-                if _FLUSH_LOG_EACH_ITER:
-                    self.logger.flush()
-                try:
-                    self.vmm.hypercall(rax, rbx, rcx, rdx, rdi, rsi, r8, r9, r10, r11)
-                except:
-                    pass
-        else:
-            it = 0
-            self.logger.log("[*] Fuzzing hypercalls with arguments exhaustively...")
-            for rax in range(self.gprs['rax']):
-                for rbx in range(self.gprs['rbx']):
-                    for rcx in range(self.gprs['rcx']):
-                        for rdx in range(self.gprs['rdx']):
-                            for rdi in range(self.gprs['rdi']):
-                                for rsi in range(self.gprs['rsi']):
-                                    for r8 in range(self.gprs['r8']):
-                                        for r9 in range(self.gprs['r9']):
-                                            for r10 in range(self.gprs['r10']):
-                                                for r11 in range(self.gprs['r11']):
-                                                    if _LOG_ALL_GPRS:
-                                                        self.logger.log(_str.format(it, rax, rbx, rcx, rdx, rdi, rsi, r8, r9, r10, r11))
-                                                    else:
-                                                        self.logger.log(f'{it:d} hcall')
-                                                    if _FLUSH_LOG_EACH_ITER:
-                                                        self.logger.flush()
-                                                    try:
-                                                        self.vmm.hypercall(rax, rbx, rcx, rdx, rdi, rsi, r8, r9, r10, r11)
-                                                        it += 1
-                                                    except:
-                                                        pass
-
-        self.logger.log(f'[*] Finished fuzzing: time elapsed {time.time() - t:.3f}')
-        return ModuleResult.WARNING

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Dumb VMM hypercall fuzzer")
-
-        if len(module_argv) > 0:
-            self.random_order = module_argv[0].lower() == 'random'
-        self.maxval = DEFAULT_MAXVAL_RANDOM if self.random_order else DEFAULT_MAXVAL_EXHAUSTIVE
-        if len(module_argv) > 1:
-            self.vector_reg = module_argv[1]
-        if len(module_argv) > 2:
-            self.maxval = int(module_argv[2], 16)
-        if len(module_argv) > 3:
-            self.iterations = int(module_argv[3])
-
-        for r in self.gprs:
-            self.gprs[r] = self.maxval
-        if self.vector_reg is not None:
-            self.gprs[self.vector_reg] = DEFAULT_VECTOR_MAXVAL
-
-        self.logger.log('\n[*] Configuration:')
-        self.logger.log(f'    Mode               : {"random" if self.random_order else "exhaustive"}')
-        self.logger.log(f'    Hypercall vector in: {self.vector_reg}')
-        self.logger.log(f'    Max register value : 0x{self.maxval:X}')
-        self.logger.log(f'    Iterations         : {self.iterations:d}\n')
-
-        self.res = self.fuzz_generic_hypercalls()
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.res = ModuleResult.WARNING
-        return self.res

-

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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/iofuzz.html b/_modules/chipsec/modules/tools/vmm/iofuzz.html
deleted file mode 100644
index 98fe2617..00000000
--- a/_modules/chipsec/modules/tools/vmm/iofuzz.html
+++ /dev/null
@@ -1,291 +0,0 @@
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-    chipsec.modules.tools.vmm.iofuzz — CHIPSEC  documentation
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Source code for chipsec.modules.tools.vmm.iofuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Simple port I/O VMM emulation fuzzer
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.iofuzz [-a <mode>,<count>,<iterations>]``
-
-    - ``<mode>``         : SMI handlers testing mode
-        - ``exhaustive`` : Fuzz all I/O ports exhaustively (default)
-        - ``random``     : Fuzz randomly chosen I/O ports
-    - ``<count>``        : Number of times to write to each port (default = 1000)
-    - ``<iterations>``   : Number of I/O ports to fuzz (default = 1000000 in random mode)
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.iofuzz
-    >>> chipsec_main.py -i -m tools.vmm.iofuzz -a random,9000,4000000
-
-Additional options set within the module:
-    - ``MAX_PORTS``                 : Maximum ports
-    - ``MAX_PORT_VALUE``            : Maximum port value to use
-    - ``DEFAULT_PORT_WRITE_COUNT``  : Default port write count if not specified with switches
-    - ``DEFAULT_RANDOM_ITERATIONS`` : Default port write iterations if not specified with switches
-    - ``_FLUSH_LOG_EACH_ITER``      : Flush log after each iteration
-    - ``_FUZZ_SPECIAL_VALUES``      : Specify to use 1-2-4 byte values
-    - ``_EXCLUDE_PORTS``            : Ports to exclude (list)
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import random
-
-from chipsec.module_common import BaseModule, ModuleResult
-
-MAX_PORTS = 0x10000
-MAX_PORT_VALUE = 0xFF
-DEFAULT_PORT_WRITE_COUNT = 1000
-DEFAULT_RANDOM_ITERATIONS = 1000000
-
-# Flush log file before each port
-_FLUSH_LOG_EACH_ITER = False
-
-# Control values to be written to each port
-_FUZZ_SPECIAL_VALUES = True
-
-# List I/O port numbers you want to exclude from fuzzing
-_EXCLUDE_PORTS = []
-
-
-

-[docs]
-class iofuzz(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x485df2e, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.iofuzz.html')
-
-

-[docs]
-    def fuzz_ports(self, iterations, write_count, random_order=False):
-
-        if random_order:
-            self.logger.log(f'[*] Fuzzing randomly chosen {iterations:d} I/O ports..\n')
-        else:
-            self.logger.log(f'[*] Fuzzing I/O ports in a range 0:0x{iterations - 1:X}..\n')
-
-        io_addr = 0
-        for it in range(iterations):
-
-            if _FLUSH_LOG_EACH_ITER:
-                self.logger.flush()
-
-            if random_order:
-                io_addr = random.randint(0, MAX_PORTS)
-            else:
-                io_addr = it
-
-            if io_addr in _EXCLUDE_PORTS:
-                self.logger.log(f'[*] Skipping port 0x{io_addr:04X}')
-                continue
-
-            self.logger.log(f'[*] Fuzzing I/O port 0x{io_addr:04X}')
-
-            self.logger.log("    Reading port")
-            port_value = self.cs.io.read_port_byte(io_addr)
-
-            if _FUZZ_SPECIAL_VALUES:
-                self.logger.log("    Writing special 1-2-4 byte values")
-                try:
-                    self.cs.io.write_port_byte(io_addr, port_value)
-                    self.cs.io.write_port_byte(io_addr, (~port_value) & 0xFF)
-                    self.cs.io.write_port_byte(io_addr, 0xFF)
-                    self.cs.io.write_port_byte(io_addr, 0x00)
-                    self.cs.io.write_port_byte(io_addr, 0x5A)
-                    self.cs.io.write_port_word(io_addr, 0xFFFF)
-                    self.cs.io.write_port_word(io_addr, 0x0000)
-                    self.cs.io.write_port_word(io_addr, 0x5AA5)
-                    self.cs.io.write_port_dword(io_addr, 0xFFFFFFFF)
-                    self.cs.io.write_port_dword(io_addr, 0x00000000)
-                    self.cs.io.write_port_word(io_addr, 0x5AA55AA5)
-                except:
-                    pass
-
-            self.logger.log(f'    Writing values 0..{MAX_PORT_VALUE:X} ({write_count:d} times each)')
-            for v in range(MAX_PORT_VALUE + 1):
-                for _ in range(write_count):
-                    try:
-                        self.cs.io.write_port_byte(io_addr, v)
-                    except:
-                        pass
-
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        return self.rc_res.getReturnCode(ModuleResult.WARNING)

-
-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("I/O port fuzzer")
-
-        _random_order = (len(module_argv) > 0) and ('random' == module_argv[0].lower())
-        write_count = int(module_argv[1]) if len(module_argv) > 1 else DEFAULT_PORT_WRITE_COUNT
-        if len(module_argv) > 2:
-            iterations = int(module_argv[2])
-        else:
-            iterations = DEFAULT_RANDOM_ITERATIONS if _random_order else MAX_PORTS
-
-        self.logger.log('\n[*] Configuration:')
-        self.logger.log(f'    Mode             : {"random" if _random_order else "exhaustive"}')
-        self.logger.log(f'    Write count      : {write_count:d}')
-        self.logger.log(f'    Ports/iterations : {iterations:d}\n')
-
-        self.res = self.fuzz_ports(iterations, write_count, _random_order)
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/msr_fuzz.html b/_modules/chipsec/modules/tools/vmm/msr_fuzz.html
deleted file mode 100644
index f5b18937..00000000
--- a/_modules/chipsec/modules/tools/vmm/msr_fuzz.html
+++ /dev/null
@@ -1,298 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.msr_fuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.msr_fuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Simple CPU Module Specific Register (MSR) VMM emulation fuzzer
-
-Usage:
-    ``chipsec_main -m tools.vmm.msr_fuzz [-a random]``
-
-    - ``-a`` : random = use random values (default = sequential numbering)
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.msr_fuzz
-    >>> chipsec_main.py -i -m tools.vmm.msr_fuzz -a random
-
-Additional options set within the module:
-    - ``_NO_ITERATIONS_TO_FUZZ`` : Number of iterations to fuzz randomly
-    - ``_READ_MSR``              : Specify to read MSR when fuzzing it
-    - ``_FLUSH_LOG_EACH_MSR``    : Flush log file before each MSR
-    - ``_FUZZ_VALUE_0_all1s``    : Try all 0 & all 1 values to be written to each MSR
-    - ``_FUZZ_VALUE_5A``         : Try 0x5A values to be written to each MSR
-    - ``_FUZZ_VALUE_RND``        : Try random values to be written to each MSR
-    - ``_EXCLUDE_MSR``           : MSR values to exclude (list)
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import random
-
-from chipsec.module_common import BaseModule, ModuleResult
-
-_MODULE_NAME = 'msr_fuzz'
-
-# Number of iterations to fuzz randomly
-_NO_ITERATIONS_TO_FUZZ = 100000
-
-# Read MSR?
-_READ_MSR = False
-
-# Flush log file before each MSR
-_FLUSH_LOG_EACH_MSR = False
-
-# Control values to be written to each MSR
-_FUZZ_VALUE_0_all1s = True
-_FUZZ_VALUE_5A = False
-_FUZZ_VALUE_RND = True
-
-# Exclude MSRs which cause VM hang/crash
-_EXCLUDE_MSR = []
-
-
-

-[docs]
-class msr_fuzz (BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x2e31482, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.msr_fuzz.html')
-
-

-[docs]
-    def fuzz_MSRs(self, msr_addr_start, random_order=False):
-        msr_addr_range = 0x10000
-        msr_addr_end = msr_addr_start + msr_addr_range
-        self.logger.log(f'[*] Fuzzing MSRs in range 0x{msr_addr_start:08X}:0x{msr_addr_end:08X}..')
-        it = 0
-        if random_order:
-            it_max = _NO_ITERATIONS_TO_FUZZ
-        else:
-            it_max = msr_addr_range
-
-        while it < it_max:
-            if random_order:
-                msr_addr = random.randint(msr_addr_start, msr_addr_end)
-            else:
-                msr_addr = msr_addr_start + it
-
-            if _FLUSH_LOG_EACH_MSR:
-                self.logger.flush()
-
-            if msr_addr not in _EXCLUDE_MSR:
-                if _READ_MSR:
-                    self.logger.log(f'[*] rdmsr 0x{msr_addr:08X}')
-                    try:
-                        (_, _) = self.cs.msr.read_msr(0, msr_addr)
-                    except:
-                        pass
-
-                self.logger.log(f'[*] wrmsr 0x{msr_addr:08X}')
-
-                if _FUZZ_VALUE_0_all1s:
-                    try:
-                        self.cs.msr.write_msr(0, msr_addr, 0, 0)
-                    except:
-                        pass
-                    try:
-                        self.cs.msr.write_msr(0, msr_addr, 0xFFFFFFFF, 0xFFFFFFFF)
-                    except:
-                        pass
-
-                if _FUZZ_VALUE_5A:
-                    try:
-                        self.cs.msr.write_msr(0, msr_addr, 0x5A5A5A5A, 0x5A5A5A5A)
-                    except:
-                        pass
-
-                if _FUZZ_VALUE_RND:
-                    val_hi = random.randint(0, 0xFFFFFFFF)
-                    val_lo = random.randint(0, 0xFFFFFFFF)
-                    try:
-                        self.cs.msr.write_msr(0, msr_addr, val_hi, val_lo)
-                    except:
-                        pass
-            it += 1
-        return True

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test('Fuzzing CPU Model Specific Registers (MSR)')
-
-        _random_order = False
-        if (len(module_argv) > 0) and ('random' == module_argv[0].lower()):
-            _random_order = True
-
-        global _NO_ITERATIONS_TO_FUZZ
-        _NO_ITERATIONS_TO_FUZZ = 100000
-
-        self.logger.log('[*] Configuration:')
-        self.logger.log(f'    Mode: {"random" if _random_order else "sequential"}')
-        if _random_order:
-            self.logger.log(f'    Number of iterations: {_NO_ITERATIONS_TO_FUZZ:d}')
-
-        self.logger.log('\n[*] Fuzzing Low MSR range...')
-        self.fuzz_MSRs(0x0, _random_order)
-        self.logger.log('\n[*] Fuzzing High MSR range...')
-        self.fuzz_MSRs(0xC0000000, _random_order)
-        self.logger.log('\n[*] Fuzzing VMM synthetic MSR range...')
-        self.fuzz_MSRs(0x40000000, _random_order)
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/pcie_fuzz.html b/_modules/chipsec/modules/tools/vmm/pcie_fuzz.html
deleted file mode 100644
index 77fea4a6..00000000
--- a/_modules/chipsec/modules/tools/vmm/pcie_fuzz.html
+++ /dev/null
@@ -1,381 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.pcie_fuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.pcie_fuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Simple PCIe device Memory-Mapped I/O (MMIO) and I/O ranges VMM emulation fuzzer
-
-Usage:
-    ``chipsec_main -m tools.vmm.pcie_fuzz [-a <bus> <dev> <fun>]``
-
-    - ``<bus>`` : Bus # to fuzz (in hex)
-    - ``<dev>`` : Device # to fuzz (in hex)
-    - ``<fun>`` : Function # to fuzz (in hex)
-
-Where:
-    - ``[]``: optional line
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.pcie_fuzz
-    >>> chipsec_main.py -i -m tools.vmm.pcie_fuzz -l log.txt
-    >>> chipsec_main.py -i -m tools.vmm.pcie_fuzz -a 0 1f 0
-
-Additional options set within the module:
-    - ``IO_FUZZ``       : Set to fuzz IO BARs
-    - ``CALC_BAR_SIZE`` : Set to calculate BAR sizes
-    - ``TIMEOUT``       : Timeout between memory writes (seconds)
-    - ``ACTIVE_RANGE``  : Set to fuzz MMIO BAR in Active range
-    - ``BIT_FLIP``      : Set to fuzz using bit flips
-    - ``_EXCLUDE_BAR``  : BARs to exclude (list)
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import time
-import random
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.hal.pci import print_pci_devices
-
-
-#################################################################
-# Fuzzing configuration
-#################################################################
-#
-IO_FUZZ = 0
-CALC_BAR_SIZE = 1
-TIMEOUT = 1
-ACTIVE_RANGE = 0
-BIT_FLIP = 1
-
-_EXCLUDE_BAR = []
-
-
-

-[docs]
-class pcie_fuzz(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x61c1431, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_fuzz.html')
-
-

-[docs]
-    def fuzz_io_bar(self, bar, size=0x100):
-        port_off = 0
-        # Issue 8/16/32-bit I/O requests with various values to all I/O ports (aligned and unaligned)
-        for port_off in range(size):
-            port_value = self.cs.io.read_port_byte(bar + port_off)
-            self.cs.io.write_port_byte(bar + port_off, port_value)
-            self.cs.io.write_port_byte(bar + port_off, ~port_value & 0xFF)
-            self.cs.io.write_port_byte(bar + port_off, 0xFF)
-            self.cs.io.write_port_byte(bar + port_off, 0x00)
-            self.cs.io.write_port_word(bar + port_off, 0xFFFF)
-            self.cs.io.write_port_word(bar + port_off, 0x0000)
-            self.cs.io.write_port_dword(bar + port_off, 0xFFFFFFFF)
-            self.cs.io.write_port_dword(bar + port_off, 0x00000000)

-
-
-

-[docs]
-    def fuzz_offset(self, bar, reg_off, reg_value, is64bit):
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, reg_value)  # same value
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, ~reg_value & 0xFFFFFFFF)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0xFFFFFFFF)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0x5A5A5A5A)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0x00000000)

-
-
-

-[docs]
-    def fuzz_unaligned(self, bar, reg_off, is64bit):
-        dummy = self.cs.mmio.read_MMIO_reg(bar, reg_off + 1)
-        # @TODO: crosses the reg boundary
-        self.cs.mem.write_physical_mem_word(bar + reg_off + 1, 0xFFFF)
-        self.cs.mem.write_physical_mem_byte(bar + reg_off + 1, 0xFF)

-
-
-

-[docs]
-    def fuzz_mmio_bar(self, bar, is64bit, size=0x1000):
-        self.logger.log(f'[*] Fuzzing MMIO BAR 0x{bar:016X}, size = 0x{size:X}..')
-        reg_off = 0
-        # Issue aligned 32-bit MMIO requests with various values to all MMIO registers
-        for reg_off in range(0, size, 4):
-            reg_value = self.cs.mmio.read_MMIO_reg(bar, reg_off)
-            self.fuzz_offset(bar, reg_off, reg_value, is64bit)
-            self.fuzz_unaligned(bar, reg_off, is64bit)
-            # restore the original value
-            self.cs.mmio.write_MMIO_reg(bar, reg_off, reg_value)

-
-
-

-[docs]
-    def fuzz_mmio_bar_random(self, bar, is64bit, size=0x1000):
-        self.logger.log(f'[*] Fuzzing MMIO BAR in random mode 0x{bar:016X}, size = 0x{size:X}..')
-        reg_off = 0
-        while 1:
-            rand = random.randint(0, size / 4 - 1)
-            self.fuzz_offset(bar, reg_off, rand * 4, is64bit)
-            self.fuzz_offset(bar, reg_off, rand * 4 + 1, is64bit)
-            self.fuzz_unaligned(bar, rand * 4, is64bit)

-
-
-

-[docs]
-    def fuzz_mmio_bar_in_active_range(self, bar, is64bit, list):
-        self.logger.log(f'[*] Fuzzing MMIO BAR in Active range 0x{bar:016X}, size of range = 0x{len(list):X}..')
-        for reg_off in list:
-            rand = random.randint(0, 255)
-            self.fuzz_offset(bar, reg_off, rand, is64bit)
-            self.fuzz_unaligned(bar, reg_off, is64bit)

-
-
-

-[docs]
-    def fuzz_mmio_bar_in_active_range_random(self, bar, is64bit, list):
-        self.logger.log(f'[*] Fuzzing MMIO BAR in Active range 0x{bar:016X} in random mode, size of range = 0x{len(list):X}..')
-        reg_off = 0
-        self.fuzz_unaligned(bar, reg_off, is64bit)
-        while 1:
-            rand = random.randint(0, len(list) - 1)
-            self.fuzz_offset(bar, reg_off, list[rand], is64bit)

-
-
-

-[docs]
-    def fuzz_mmio_bar_in_active_range_bit_flip(self, bar, is64bit, list):
-        self.logger.log(f'[*] Fuzzing (bit flipping) MMIO BAR in Active range 0x{bar:016X}, size of range = 0x{len(list):X}..')
-        reg_off = 0
-        while 1:
-            rand_index = random.randint(0, len(list) - 1)
-            reg_value = self.cs.mmio.read_MMIO_reg(bar, list[rand_index])
-
-            rand_offset = random.randint(0, 32)
-            if (1 << rand_offset) & reg_value:
-                reg_value = ~(1 << rand_offset) & 0xffffffff & reg_value
-            else:
-                reg_value = reg_value | (1 << rand_offset)
-
-            self.cs.mmio.write_MMIO_reg(bar, reg_off, reg_value)

-
-
-

-[docs]
-    def find_active_range(self, bar, size):
-        self.logger.log(f'[*] Determine MMIO BAR Active range 0x{bar:016X}, size  0x{size:X}..')
-        one = self.cs.mem.read_physical_mem(bar, size)
-        time.sleep(TIMEOUT)
-        two = self.cs.mem.read_physical_mem(bar, size)
-        diff_index = []
-        for i in range(len(one) // 4 - 1):
-            j = 4 * i
-            if (one[j] != two[j]) or (one[j + 1] != two[j + 1]) or (one[j + 2] != two[j + 2]) or (one[j + 3] != two[j + 3]):
-                diff_index.append(j)
-        return diff_index

-
-
-

-[docs]
-    def fuzz_pcie_device(self, b, d, f):
-        self.logger.log("[*] Discovering MMIO and I/O BARs of the device..")
-        device_bars = self.cs.pci.get_device_bars(b, d, f, bCalcSize=CALC_BAR_SIZE)
-        for (bar, isMMIO, is64bit, bar_off, bar_reg, size) in device_bars:
-            if bar not in _EXCLUDE_BAR:
-                # Fuzzing MMIO registers of the PCIe device
-                if isMMIO:
-                    self.logger.log(f'[*] + 0x{bar_off:02X} ({bar_reg:X}): MMIO BAR at 0x{bar:016X} (64-bit? {is64bit:d}) with size: 0x{size:08X}. Fuzzing..')
-                    if ACTIVE_RANGE and (size > 0x1000):
-                        list = []
-                        list = self.find_active_range(bar, size)
-                        if len(list) > 0:
-                            if BIT_FLIP:
-                                self.fuzz_mmio_bar_in_active_range_bit_flip(bar, is64bit, list)
-                            else:
-                                self.fuzz_mmio_bar_in_active_range(bar, is64bit, list)
-                    else:
-                        if size >= 0x2000000:
-                            size = 0x2000000
-                        self.fuzz_mmio_bar(bar, is64bit, size)
-                # Fuzzing I/O registers of the PCIe device
-                else:
-                    if IO_FUZZ:
-                        self.logger.log('[*] + 0x{bar_off:02X}: I/O BAR at 0x{bar:08X}. Fuzzing..')
-                        self.fuzz_io_bar(bar)

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test('PCIe device fuzzer (pass-through devices)')
-
-        pcie_devices = []
-        if len(module_argv) > 2:
-            _bus = int(module_argv[0], 16)
-            _dev = int(module_argv[1], 16)
-            _fun = int(module_argv[2], 16)
-            pcie_devices.append((_bus, _dev, _fun, 0, 0))
-        else:
-            self.logger.log('[*] Enumerating available PCIe devices..')
-            pcie_devices = self.cs.pci.enumerate_devices()
-
-        self.logger.log('[*] About to fuzz the following PCIe devices..')
-        print_pci_devices(pcie_devices)
-
-        for (b, d, f, _, _, _) in pcie_devices:
-            self.logger.log(f'[+] Fuzzing device {b:02X}:{d:02X}.{f:X}')
-            self.fuzz_pcie_device(b, d, f)
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/pcie_overlap_fuzz.html b/_modules/chipsec/modules/tools/vmm/pcie_overlap_fuzz.html
deleted file mode 100644
index 5e812656..00000000
--- a/_modules/chipsec/modules/tools/vmm/pcie_overlap_fuzz.html
+++ /dev/null
@@ -1,321 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.pcie_overlap_fuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.pcie_overlap_fuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-PCIe device Memory-Mapped I/O (MMIO) ranges VMM emulation fuzzer
-which first overlaps MMIO BARs of all available PCIe devices
-then fuzzes them by writing garbage if corresponding option is enabled
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.pcie_overlap_fuzz``
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.pcie_overlap_fuzz -l log.txt
-
-Additional options set within the module:
-    - ``OVERLAP_MODE``       : Set overlap direction
-    - ``FUZZ_OVERLAP``       : Set for fuzz overlaps
-    - ``FUZZ_RANDOM``        : Set to fuzz in random mode
-    - ``_EXCLUDE_MMIO_BAR1`` : List 1 of MMIO bars to exclude
-    - ``_EXCLUDE_MMIO_BAR2`` : List 2 of MMIO bars to exclude 
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-import random
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.hal.pci import print_pci_devices
-
-#################################################################
-# Fuzzing configuration
-#################################################################
-#
-OVERLAP_MODE = 1
-FUZZ_OVERLAP = 0
-FUZZ_RANDOM = 0
-
-_EXCLUDE_MMIO_BAR1 = []
-_EXCLUDE_MMIO_BAR2 = []
-
-
-

-[docs]
-class pcie_overlap_fuzz(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x19702b2, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.html')
-
-

-[docs]
-    def overlap_mmio_range(self, bus1, dev1, fun1, is64bit1, off1, bus2, dev2, fun2, is64bit2, off2, direction):
-        base_lo1 = self.cs.pci.read_dword(bus1, dev1, fun1, off1)
-        base_lo2 = self.cs.pci.read_dword(bus2, dev2, fun2, off2)
-        if (0 == (base_lo1 & 0x1)) and (0 == (base_lo2 & 0x1)):
-            if not is64bit1 and not is64bit2:
-                # 32-bit MMIO BARs
-                # MMIO BARs
-                if direction:
-                    self.cs.pci.write_dword(bus2, dev2, fun2, off2, base_lo1)
-                else:
-                    self.cs.pci.write_dword(bus1, dev1, fun1, off1, base_lo2)
-            elif is64bit1 and is64bit2:
-                # 64-bit MMIO BARs
-                base_hi1 = self.cs.pci.read_dword(bus1, dev1, fun1, off1 + 4)
-                base_hi2 = self.cs.pci.read_dword(bus2, dev2, fun2, off2 + 4)
-                if direction:
-                    self.cs.pci.write_dword(bus2, dev2, fun2, off2, base_lo1)
-                    self.cs.pci.write_dword(bus2, dev2, fun2, off2 + 4, base_hi1)
-                else:
-                    self.cs.pci.write_dword(bus1, dev1, fun1, off1, base_lo2)
-                    self.cs.pci.write_dword(bus1, dev1, fun1, off1 + 4, base_hi2)
-            elif is64bit1 and not is64bit2:
-                self.cs.pci.write_dword(bus1, dev1, fun1, off1, base_lo2)
-                self.cs.pci.write_dword(bus1, dev1, fun1, off1 + 4, 0)
-            else:
-                self.cs.pci.write_dword(bus2, dev2, fun2, off2, base_lo1)
-                self.cs.pci.write_dword(bus2, dev2, fun2, off2 + 4, 0)

-
-
-

-[docs]
-    def fuzz_offset(self, bar, reg_off, reg_value, is64bit):
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, reg_value)  # same value
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, ~reg_value & 0xFFFFFFFF)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0xFFFFFFFF)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0x5A5A5A5A)
-        self.cs.mmio.write_MMIO_reg(bar, reg_off, 0x00000000)

-
-
-

-[docs]
-    def fuzz_unaligned(self, bar, reg_off, is64bit):
-        dummy = self.cs.mmio.read_MMIO_reg(bar, reg_off + 1)
-        # @TODO: crosses the reg boundary
-        #self.cs.mmio.write_MMIO_reg(bar, reg_off + 1, 0xFFFFFFFF)
-        self.cs.mem.write_physical_mem_word(bar + reg_off + 1, 0xFFFF)
-        self.cs.mem.write_physical_mem_byte(bar + reg_off + 1, 0xFF)

-
-
-

-[docs]
-    def fuzz_mmio_bar(self, bar, is64bit, size=0x1000):
-        self.logger.log(f'[*] Fuzzing MMIO BAR 0x{bar:016X}, size = 0x{size:X}..')
-        reg_off = 0
-        # Issue 32b MMIO requests with various values to all MMIO registers
-        for reg_off in range(0, size, 4):
-            reg_value = self.cs.mmio.read_MMIO_reg(bar, reg_off)
-            self.fuzz_offset(bar, reg_off, reg_value, is64bit)
-            self.fuzz_unaligned(bar, reg_off, is64bit)
-            # restore the original value
-            self.cs.mmio.write_MMIO_reg(bar, reg_off, reg_value)

-
-
-

-[docs]
-    def fuzz_mmio_bar_random(self, bar, is64bit, size=0x1000):
-        self.logger.log(f'[*] Fuzzing MMIO BAR in random mode 0x{bar:016X}, size = 0x{size:X}..')
-        reg_off = 0
-        while 1:
-            rand = random.randint(0, size / 4 - 1)
-            self.fuzz_offset(bar, reg_off, rand * 4, is64bit)
-            self.fuzz_offset(bar, reg_off, rand * 4 + 1, is64bit)
-            self.fuzz_unaligned(bar, rand * 4, is64bit)

-
-
-

-[docs]
-    def fuzz_overlap_pcie_device(self, pcie_devices):
-        for (b1, d1, f1, _, _, _) in pcie_devices:
-            self.logger.log("[*] Overlapping MMIO bars...")
-            device_bars1 = self.cs.pci.get_device_bars(b1, d1, f1, bCalcSize=True)
-            for (bar1, isMMIO1, is64bit1, bar_off1, _, size1) in device_bars1:
-                if bar1 not in _EXCLUDE_MMIO_BAR1:
-                    if isMMIO1:
-                        for (b2, d2, f2, _, _) in pcie_devices:
-                            device_bars2 = self.cs.pci.get_device_bars(b2, d2, f2, bCalcSize=True)
-                            for (bar2, isMMIO2, is64bit2, bar_off2, _, size2) in device_bars2:
-                                if bar2 not in _EXCLUDE_MMIO_BAR2:
-                                    if isMMIO2:
-                                        if bar1 != bar2:
-                                            self.logger.log(f'[*] Overlap device {b1:02X}:{d1:02X}.{f1:X} offset {bar_off1:X} bar: {bar1:08X} and {b2:02X}:{d2:02X}.{f2:X} offset {bar_off2:X} bar: {bar2:08X}')
-                                            self.overlap_mmio_range(b1, d1, f1, is64bit1, bar_off1, b2, d2, f2, is64bit2, bar_off2, OVERLAP_MODE)
-                                            if FUZZ_OVERLAP:
-                                                _bar = bar1 if OVERLAP_MODE else bar2
-                                                _is64bit = is64bit1 if OVERLAP_MODE else is64bit2
-                                                _size = size1 if OVERLAP_MODE else size2
-                                                self.logger.log(f'[*] Fuzzing MMIO BAR 0x{_bar:X}...')
-                                                if FUZZ_RANDOM:
-                                                    self.fuzz_mmio_bar_random(_bar, _is64bit, _size)
-                                                else:
-                                                    self.fuzz_mmio_bar(_bar, _is64bit, _size)

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Tool to overlap and fuzz MMIO spaces of available PCIe devices")
-
-        pcie_devices = []
-        self.logger.log("[*] Enumerating available PCIe devices..")
-        pcie_devices = self.cs.pci.enumerate_devices()
-
-        self.logger.log("[*] About to fuzz the following PCIe devices..")
-        print_pci_devices(pcie_devices)
-        self.fuzz_overlap_pcie_device(pcie_devices)
-
-        self.logger.log_information('Module completed!')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

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-      

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-  
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\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.html b/_modules/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.html
deleted file mode 100644
index 5ecdc309..00000000
--- a/_modules/chipsec/modules/tools/vmm/vbox/vbox_crash_apicbase.html
+++ /dev/null
@@ -1,200 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
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-          

-            
-  
Source code for chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2016, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Oracle VirtualBox CVE-2015-0377 check
-
-Reference:
-    - PoC test for Host OS Crash when writing to IA32_APIC_BASE MSR (Oracle VirtualBox CVE-2015-0377)
-    - http://www.oracle.com/technetwork/topics/security/cpujan2015-1972971.html
-
-Usage:
-   ``chipsec_main.py -i -m tools.vmm.vbox_crash_apicbase``
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.vbox_crash_apicbase
-
-Registers used:
-    - IA32_APIC_BASE
-
-.. warning::
-    - Module can cause VMM/Host OS to crash; if so, this is a FAILURE
-
-"""
-
-from chipsec.exceptions import HWAccessViolationError
-from chipsec.module_common import BaseModule, ModuleResult
-
-_MODULE_NAME = 'vbox_crash_apicbase'
-
-
-

-[docs]
-class vbox_crash_apicbase(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x14428af, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.html')
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("Host OS Crash due to IA32_APIC_BASE (Oracle VirtualBox CVE-2015-0377)")
-
-        tid = 0
-        apicbase_msr = self.cs.read_register('IA32_APIC_BASE', tid)
-        self.cs.print_register('IA32_APIC_BASE', apicbase_msr)
-        apicbase_msr = 0xDEADBEEF00000000 | (apicbase_msr & 0xFFFFFFFF)
-        self.logger.log(f'[*] Writing 0x{apicbase_msr:016X} to IA32_APIC_BASE MSR..')
-        try:
-            self.cs.write_register('IA32_APIC_BASE', apicbase_msr, tid)
-        except HWAccessViolationError:
-            self.logger.log('System blocked write attempt.')
-
-        # If we are here, then we are fine ;)
-        self.logger.log_passed("VMM/Host OS didn't crash (not vulnerable)")
-        self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-        self.res = self.rc_res.getReturnCode(ModuleResult.PASSED)
-        return self.res

-

-
-

-
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-          

-        

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-      

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-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/venom.html b/_modules/chipsec/modules/tools/vmm/venom.html
deleted file mode 100644
index b76a1a60..00000000
--- a/_modules/chipsec/modules/tools/vmm/venom.html
+++ /dev/null
@@ -1,213 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.venom — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.venom
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2020, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-QEMU VENOM vulnerability DoS PoC test
-
-Reference:
-    - Module is based on `PoC by Marcus Meissner <https://marc.info/?l=oss-security&m=143155206320935&w=2>`_
-    - `VENOM: QEMU vulnerability (CVE-2015-3456) <https://access.redhat.com/articles/1444903>`_
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.venom``
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.venom
-
-Additional options set within the module:
-    - ``ITER_COUNT``         : Iteration count
-    - ``FDC_PORT_DATA_FIFO`` : FDC DATA FIFO port
-    - ``FDC_CMD_WRVAL``      : FDC Command write value
-    - ``FD_CMD``             : FD Command
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-from chipsec.module_common import BaseModule, ModuleResult
-
-_MODULE_NAME = 'venom'
-
-ITER_COUNT = 0x10000000
-FDC_PORT_DATA_FIFO = 0x3F5
-FDC_CMD_WRVAL = 0x42
-FD_CMD = 0x8E  # FD_CMD_DRIVE_SPECIFICATION_COMMAND # FD_CMD_READ_ID = 0x0A
-
-
-

-[docs]
-class venom (BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x6e48a35, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.venom.html')
-
-

-[docs]
-    def venom_impl(self):
-        self.cs.io.write_port_byte(FDC_PORT_DATA_FIFO, FD_CMD)
-        for _ in range(ITER_COUNT):
-            self.cs.io.write_port_byte(FDC_PORT_DATA_FIFO, FDC_CMD_WRVAL)
-        return True

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("QEMU VENOM vulnerability DoS PoC")
-
-        self.venom_impl()
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

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-          

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-      

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-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/xen/define.html b/_modules/chipsec/modules/tools/vmm/xen/define.html
deleted file mode 100644
index 9bc153a8..00000000
--- a/_modules/chipsec/modules/tools/vmm/xen/define.html
+++ /dev/null
@@ -1,391 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.xen.define — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
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-      

-        

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-            
-  
Source code for chipsec.modules.tools.vmm.xen.define
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2016, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Xen specific defines
-"""
-
-hypercall_names = {
-    0: 'set_trap_table',
-    1: 'mmu_update',
-    2: 'set_gdt',
-    3: 'stack_switch',
-    4: 'set_callbacks',
-    5: 'fpu_taskswitch',
-    6: 'sched_op_compat',
-    7: 'platform_op',
-    8: 'set_debugreg',
-    9: 'get_debugreg',
-    10: 'update_descriptor',
-    12: 'memory_op',
-    13: 'multicall',
-    14: 'update_va_mapping',
-    15: 'set_timer_op',
-    16: 'event_channel_op_compat',
-    17: 'xen_version',
-    18: 'console_io',
-    19: 'physdev_op_compat',
-    20: 'grant_table_op',
-    21: 'vm_assist',
-    22: 'update_va_mapping_otherdomain',
-    23: 'iret',
-    24: 'vcpu_op',
-    25: 'set_segment_base',
-    26: 'mmuext_op',
-    27: 'xsm_op',
-    28: 'nmi_op',
-    29: 'sched_op',
-    30: 'callback_op',
-    31: 'xenoprof_op',
-    32: 'event_channel_op',
-    33: 'physdev_op',
-    34: 'hvm_op',
-    35: 'sysctl',
-    36: 'domctl',
-    37: 'kexec_op',
-    38: 'tmem_op',
-    39: 'xc_reserved_op',
-    40: 'xenpmu_op',
-    48: 'arch_0',
-    49: 'arch_1',
-    50: 'arch_2',
-    51: 'arch_3',
-    52: 'arch_4',
-    53: 'arch_5',
-    54: 'arch_6',
-    55: 'arch_7'
-}
-
-
-

-[docs]
-def get_hypercall_name(vector, defvalue=''):
-    return hypercall_names[vector].upper() if vector in hypercall_names else defvalue

-
-
-
-hypercall_status_codes = {
-    0: ['XEN_STATUS_SUCCESS', 'Status success'],
-    1: ['XEN_ERRNO_EPERM', 'Operation not permitted'],
-    2: ['XEN_ERRNO_ENOENT', 'No such file or directory'],
-    3: ['XEN_ERRNO_ESRCH', 'No such process'],
-    4: ['XEN_ERRNO_EINTR', 'Interrupted system call'],
-    5: ['XEN_ERRNO_EIO', 'I/O error'],
-    6: ['XEN_ERRNO_ENXIO', 'No such device or address'],
-    7: ['XEN_ERRNO_E2BIG', 'Arg list too long'],
-    8: ['XEN_ERRNO_ENOEXEC', 'Exec format error'],
-    9: ['XEN_ERRNO_EBADF', 'Bad file number'],
-    10: ['XEN_ERRNO_ECHILD', 'No child processes'],
-    11: ['XEN_ERRNO_EAGAIN', 'Try again'],
-    12: ['XEN_ERRNO_ENOMEM', 'Out of memory'],
-    13: ['XEN_ERRNO_EACCES', 'Permission denied'],
-    14: ['XEN_ERRNO_EFAULT', 'Bad address'],
-    16: ['XEN_ERRNO_EBUSY', 'Device or resource busy'],
-    17: ['XEN_ERRNO_EEXIST', 'File exists'],
-    18: ['XEN_ERRNO_EXDEV', 'Cross-device link'],
-    19: ['XEN_ERRNO_ENODEV', 'No such device'],
-    22: ['XEN_ERRNO_EINVAL', 'Invalid argument'],
-    23: ['XEN_ERRNO_ENFILE', 'File table overflow'],
-    24: ['XEN_ERRNO_EMFILE', 'Too many open files'],
-    28: ['XEN_ERRNO_ENOSPC', 'No space left on device'],
-    31: ['XEN_ERRNO_EMLINK', 'Too many links'],
-    33: ['XEN_ERRNO_EDOM', 'Math argument out of domain of func'],
-    34: ['XEN_ERRNO_ERANGE', 'Math result not representable'],
-    35: ['XEN_ERRNO_EDEADLK', 'Resource deadlock would occur'],
-    36: ['XEN_ERRNO_ENAMETOOLONG', 'File name too long'],
-    37: ['XEN_ERRNO_ENOLCK', 'No record locks available'],
-    38: ['XEN_ERRNO_ENOSYS', 'Function not implemented'],
-    61: ['XEN_ERRNO_ENODATA', 'No data available'],
-    62: ['XEN_ERRNO_ETIME', 'Timer expired'],
-    74: ['XEN_ERRNO_EBADMSG', 'Not a data message'],
-    75: ['XEN_ERRNO_EOVERFLOW', 'Value too large for defined data type'],
-    84: ['XEN_ERRNO_EILSEQ', 'Illegal byte sequence'],
-    85: ['XEN_ERRNO_ERESTART', 'Interrupted system call should be restarted'],
-    88: ['XEN_ERRNO_ENOTSOCK', 'Socket operation on non-socket'],
-    95: ['XEN_ERRNO_EOPNOTSUPP', 'Operation not supported on transport endpoint'],
-    98: ['XEN_ERRNO_EADDRINUSE', 'Address already in use'],
-    99: ['XEN_ERRNO_EADDRNOTAVAIL', 'Cannot assign requested address'],
-    105: ['XEN_ERRNO_ENOBUFS', 'No buffer space available'],
-    106: ['XEN_ERRNO_EISCONN', 'Transport endpoint is already connected'],
-    107: ['XEN_ERRNO_ENOTCONN', 'Transport endpoint is not connected'],
-    110: ['XEN_ERRNO_ETIMEDOUT', 'Connection timed out']
-}
-
-
-

-[docs]
-def get_iverr(status, bits=64):
-    mask = (1 << bits) - 1
-    return (mask - status + 1) & mask

-
-
-
-

-[docs]
-def get_hypercall_status(code, brief=False):
-    defstatus = [f'0x{code:016X}', f'Status 0x{code:016X}']
-    if (code >> 32) == 0xFFFFFFFF:
-        code = get_iverr(code)
-        defstatus = [f'XEN_ERRNO_{code:04X}', f'Unknown error 0x{code:04X}']
-    desc = hypercall_status_codes.get(code, defstatus)
-    return desc[0] if brief else desc[1]

-
-
-
-

-[docs]
-def get_hypercall_status_extended(code):
-    return f'{get_hypercall_status(code, False)} - {get_hypercall_status(code, True)}'

-
-
-
-

-[docs]
-def get_invalid_hypercall_code():
-    return XEN_ERRNO_ENOSYS

-
-
-
-xenmem_commands = {
-    0: 'XENMEM_INCREASE_RESERVATION',
-    1: 'XENMEM_DECREASE_RESERVATION',
-    2: 'XENMEM_MAXIMUM_RAM_PAGE',
-    3: 'XENMEM_CURRENT_RESERVATION',
-    4: 'XENMEM_MAXIMUM_RESERVATION',
-    5: 'XENMEM_MACHPHYS_MFN_LIST',
-    6: 'XENMEM_POPULATE_PHYSMAP',
-    7: 'XENMEM_ADD_TO_PHYSMAP',
-    8: 'XENMEM_TRANSLATE_GPFN_LIST',
-    9: 'XENMEM_MEMORY_MAP',
-    10: 'XENMEM_MACHINE_MEMORY_MAP',
-    11: 'XENMEM_EXCHANGE',
-    12: 'XENMEM_MACHPHYS_MAPPING',
-    15: 'XENMEM_REMOVE_FROM_PHYSMAP',
-    23: 'XENMEM_ADD_TO_PHYSMAP_RANGE'
-}
-
-xen_version_commands = {
-    0: 'XENVER_VERSION',
-    1: 'XENVER_EXTRAVERSION',
-    2: 'XENVER_COMPILE_INFO',
-    3: 'XENVER_CAPABILITIES',
-    4: 'XENVER_CHANGESET',
-    5: 'XENVER_PLATFORM_PARAMETERS',
-    6: 'XENVER_GET_FEATURES',
-    7: 'XENVER_PAGESIZE',
-    8: 'XENVER_GUEST_HANDLE',
-    9: 'XENVER_COMMANDLINE'
-}
-
-console_io_commands = {
-    0: 'CONSOLEIO_WRITE',
-    1: 'CONSOLEIO_READ'
-}
-
-schedop_commands = {
-    0: 'SCHEDOP_YIELD',
-    1: 'SCHEDOP_BLOCK',
-    2: 'SCHEDOP_SHUTDOWN',
-    3: 'SCHEDOP_POLL',
-    4: 'SCHEDOP_REMOTE_SHUTDOWN',
-    5: 'SCHEDOP_SHUTDOWN_CODE',
-    6: 'SCHEDOP_WATCHDOG'
-}
-
-evtchop_commands = {
-    0: 'EVTCHOP_BIND_INTERDOMAIN',
-    1: 'EVTCHOP_BIND_VIRQ',
-    2: 'EVTCHOP_BIND_PIRQ',
-    3: 'EVTCHOP_CLOSE',
-    4: 'EVTCHOP_SEND',
-    5: 'EVTCHOP_STATUS',
-    6: 'EVTCHOP_ALLOC_UNBOUND',
-    7: 'EVTCHOP_BIND_IPI',
-    8: 'EVTCHOP_BIND_VCPU',
-    9: 'EVTCHOP_UNMASK',
-    10: 'EVTCHOP_RESET',
-    11: 'EVTCHOP_INIT_CONTROL',
-    12: 'EVTCHOP_EXPAND_ARRAY',
-    13: 'EVTCHOP_SET_PRIORITY'
-}
-
-hvmop_commands = {
-    0: 'HVMOP_SET_PARAM',
-    1: 'HVMOP_GET_PARAM',
-    9: 'HVMOP_PAGETABLE_DYING',
-    15: 'HVMOP_GET_MEMTYPE'
-}
-
-xenpmuop_commands = {
-    0: 'XENPMU_MODE_GET',
-    1: 'XENPMU_MODE_SET',
-    2: 'XENPMU_FEATURE_GET',
-    3: 'XENPMU_FEATURE_SET',
-    4: 'XENPMU_INIT',
-    5: 'XENPMU_FINISH',
-    6: 'XENPMU_LVTPC_SET',
-    7: 'XENPMU_FLUSH'
-}
-
-
-

-[docs]
-def set_variables(varlist):
-    import re
-    for i in varlist:
-        var = re.sub(r"([a-z])([A-Z]+)", r"\1_\2", varlist[i])
-        var = var.upper()
-        exec(f'global {var}; {var}={i:d}')

-
-
-
-set_variables(hypercall_names)
-set_variables(xenmem_commands)
-set_variables(xen_version_commands)
-set_variables(console_io_commands)
-set_variables(schedop_commands)
-set_variables(evtchop_commands)
-set_variables(hvmop_commands)
-set_variables(xenpmuop_commands)
-set_variables({get_iverr(i): hypercall_status_codes[i][0] for i in hypercall_status_codes.keys()})
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/xen/hypercall.html b/_modules/chipsec/modules/tools/vmm/xen/hypercall.html
deleted file mode 100644
index ea73be05..00000000
--- a/_modules/chipsec/modules/tools/vmm/xen/hypercall.html
+++ /dev/null
@@ -1,363 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.xen.hypercall — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.xen.hypercall
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Xen specific hypercall functionality
-"""
-
-import collections
-from chipsec.modules.tools.vmm.xen.define import *
-from chipsec.hal.vmm import *
-from chipsec.module_common import *
-from chipsec.modules.tools.vmm.common import *
-
-SM_RANGE = {'masks': [0x00000000000000FF]}
-MD_RANGE = {'masks': [0x000000000000FFFF]}
-XL_RANGE = {'masks': [0xFFFFFFFFFFFFFFFF]}
-
-
-

-[docs]
-class XenHypercall(BaseModuleHwAccess):
-    def __init__(self):
-        BaseModuleHwAccess.__init__(self)
-        self.vmm = VMM(self.cs)
-        self.vmm.init()
-        self.hypervisor_present = False
-        self.hypercalls = {}
-        self.buff_va = 0
-        self.buff_pa = 0
-        (self.buff_va, self.buff_pa) = self.cs.mem.alloc_physical_mem(0x1000, 0xFFFFFFFFFFFFFFFF)
-        if self.buff_pa == 0:
-            raise Exception("[*] Could not allocate memory!")
-        # define initial args for hypercall fuzzing
-        self.hypercall_args = {
-            MEMORY_OP: {'args': [xenmem_commands.keys(), self.buff_va]},
-            SET_TIMER_OP: {'args': [XL_RANGE, XL_RANGE]},
-            XEN_VERSION: {'args': [xen_version_commands.keys(), self.buff_va]},
-            CONSOLE_IO: {'args': [console_io_commands.keys(), MD_RANGE, self.buff_va]},
-            GRANT_TABLE_OP: {'args': [SM_RANGE, self.buff_va, XL_RANGE]},
-            SCHED_OP: {'args': [schedop_commands.keys(), self.buff_va]},
-            EVENT_CHANNEL_OP: {'args': [evtchop_commands.keys(), self.buff_va]},
-            NMI_OP: {'args': [XL_RANGE, XL_RANGE]},
-            HVM_OP: {'args': [hvmop_commands.keys(), self.buff_va]},
-            TMEM_OP: {'args': [self.buff_va]},
-            XENPMU_OP: {'args': [xenpmuop_commands.keys(), self.buff_va]},
-            SYSCTL: {'args': [self.buff_va]},
-            DOMCTL: {'args': [self.buff_va]},
-            ARCH_1: {'args': [self.buff_va]},
-        }
-
-

-[docs]
-    def get_value(self, arg):
-        if type(arg) in [dict]:
-            value = random.choice(arg.get('masks')) & random.getrandbits(64)
-        elif type(arg) in [list, tuple, range]:
-            value = random.choice(arg)
-        else:
-            value = arg
-        return value

-
-
-    ##
-    # hypercall
-    ##
-

-[docs]
-    def hypercall(self, args, size=0, data=''):
-        data = data.ljust(4096, '\x00')[:4096]
-        self.cs.mem.write_physical_mem(self.buff_pa, len(data), data)
-        self.dbg(f'ARGS: {" ".join([f"{x:016X}" for x in args])}  DATA: {data[:32].hex()}')
-        try:
-            rax = self.vmm.hypercall64_five_args(*args)
-            val = self.cs.mem.read_physical_mem(self.buff_pa, size) if size > 0 else ''
-        except Exception as e:
-            self.dbg(f'Exception on hypercall (0x{args[0]:08X}): {str(e)}')
-            return {'exception': True, 'status': 0xFFFFFFFFFFFFFFFF, 'buffer': str(e)}
-        return {'exception': False, 'status': rax, 'buffer': val}

-
-
-    ##
-    # xen_version
-    ##
-

-[docs]
-    def xen_version(self, cmd, size=0, data=''):
-        return self.hypercall((XEN_VERSION, cmd, self.buff_va), size, data)

-
-
-    ##
-    # get_hypervisor_info
-    ##
-

-[docs]
-    def get_hypervisor_info(self):
-        info = {}
-
-        if not self.xen_version(XENVER_VERSION)['exception']:
-            version = self.xen_version(XENVER_VERSION)
-            extra_version = self.xen_version(XENVER_EXTRAVERSION, 16)
-            compile_info = self.xen_version(XENVER_COMPILE_INFO, 140)
-            capabilities = self.xen_version(XENVER_CAPABILITIES, 1024)
-            changeset = self.xen_version(XENVER_CHANGESET, 64)
-            platform_parameters = self.xen_version(XENVER_PLATFORM_PARAMETERS, 8)
-            pagesize = self.xen_version(XENVER_PAGESIZE)
-            guest_handle = self.xen_version(XENVER_GUEST_HANDLE)
-            command_line = self.xen_version(XENVER_COMMANDLINE, 1024)
-
-            info['extra_version'] = extra_version['buffer'].strip('\x00')
-            info['xen_major'] = (version['status'] >> 16) & 0xFFFF
-            info['xen_minor'] = version['status'] & 0xFFFF
-            info['xen_version'] = f'{info["xen_major"]:d}.{info["xen_minor"]:d}{extra_version["buffer"]}'
-            info['compiler'] = compile_info['buffer'][:64].strip('\x00')
-            info['compile_by'] = compile_info['buffer'][64:80].strip('\x00')
-            info['compile_domain'] = compile_info['buffer'][80:112].strip('\x00')
-            info['compile_date'] = compile_info['buffer'][112:140].strip('\x00')
-            info['capabilities'] = capabilities['buffer'].strip('\x00')
-            info['changeset'] = changeset['buffer'].strip('\x00')
-            info['platform_parameters'] = struct.unpack('<Q', platform_parameters['buffer'])[0]
-            info['pagesize'] = pagesize['status']
-            info['guest_handle'] = guest_handle['status']
-            info['command_line'] = command_line['buffer'].strip('\x00')
-
-            info['features'] = {}
-            for i in range(0x100):
-                feature = self.xen_version(XENVER_GET_FEATURES, 8, struct.pack('<LL', i, 0))
-                if feature['exception'] == False:
-                    values = struct.unpack('<LL', feature['buffer'])
-                    info['features'][values[0]] = values[1]
-
-        return info

-
-
-    ##
-    # print_hypervisor_info
-    ##
-

-[docs]
-    def print_hypervisor_info(self, info):
-        features = ', '.join([f'F{k:d}={v:016X}' for k, v in info['features'].items() if v != 0])
-        self.msg(f'XEN Hypervisor is present!')
-        self.msg(f'          Version : {info["xen_version"]}')
-        self.msg(f'         Compiler : {info["compiler"]}')
-        self.msg(f'       Compile by : {info["compile_by"]}')
-        self.msg(f'   Compile Domain : {info["compile_domain"]}')
-        self.msg(f'     Compile Date : {info["compile_date"]}')
-        self.msg(f'     Capabilities : {info["capabilities"]}')
-        self.msg(f'       Change Set : {info["changeset"]}')
-        self.msg(f'  Platform Params : {info["platform_parameters"]:016X}')
-        self.msg(f'         Features : {features}')
-        self.msg(f'        Page size : {info["pagesize"]:016X}')
-        self.msg(f'     Guest Handle : {info["guest_handle"]:016X}')
-        self.msg(f'     Command Line : {info["command_line"]}')

-
-
-

-[docs]
-    def scan_hypercalls(self, vector_list):
-        for vector in vector_list:
-            args = self.hypercall_args.get(vector, {}).get('args', [])
-            result = self.hypercall([vector] + [0 for a in args])
-            if (result['exception'] == False) and (result['status'] != get_invalid_hypercall_code()):
-                self.hypercalls[vector] = result
-                self.add_initial_data(vector, result['buffer'], get_hypercall_status(result['status'], True))
-        return

-
-
-

-[docs]
-    def print_hypercall_status(self):
-        self.msg('')
-        self.msg('*** Hypervisor Hypercall Status Codes ***')
-        for vector in sorted(self.hypercalls.keys()):
-            data = self.hypercalls[vector]
-            name = get_hypercall_name(vector)
-            status = get_hypercall_status_extended(data['status'])
-            self.msg(f'HYPERCALL {vector:04X}  {data["status"]:016X}  {status:45} \'{name}\'')
-        return

-
-
-

-[docs]
-    def fuzz_hypercall(self, code, iterations):
-        rule = self.hypercall_args.get(code, {})
-        if not rule:
-            self.msg("WARNING: Fuzzing rule is not defined for this hypercall!")
-        args = rule.get('args', [])
-        self.msg(f'Fuzzing {get_hypercall_name(code, "Unknown")} (0x{code:02X}) hypercall')
-        self.stats_reset()
-        for it in range(iterations):
-            data = list('\x00' * 32)
-            data[randint(0, len(data) - 1)] = chr(getrandbits(8))
-            data[randint(0, len(data) - 1)] = chr(getrandbits(8))
-            data = ''.join(data)
-            values = [code] + [self.get_value(a) for a in args]
-            result = self.hypercall(values, 8, data)
-            if result['exception']:
-                self.stats_event('exception')
-            else:
-                self.stats_event(get_hypercall_status_extended(result['status']))
-        self.stats_print('Hypercall status codes')
-        return

-
-
-

-[docs]
-    def fuzz_hypercalls_randomly(self, codes, iterations):
-        for it in range(iterations):
-            code = random.choice(codes)
-            rule = self.hypercall_args.get(code, {})
-            if not rule:
-                self.msg("WARNING: Fuzzing rule is not defined for this hypercall!")
-            args = rule.get('args', [])
-            data = list('\x00' * 32)
-            data[randint(0, len(data) - 1)] = chr(getrandbits(8))
-            data[randint(0, len(data) - 1)] = chr(getrandbits(8))
-            data = ''.join(data)
-            values = [code] + [self.get_value(a) for a in args]
-            result = self.hypercall(values, 8, data)
-        return

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/xen/hypercallfuzz.html b/_modules/chipsec/modules/tools/vmm/xen/hypercallfuzz.html
deleted file mode 100644
index 87ea861f..00000000
--- a/_modules/chipsec/modules/tools/vmm/xen/hypercallfuzz.html
+++ /dev/null
@@ -1,263 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.xen.hypercallfuzz — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.xen.hypercallfuzz
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-Xen hypercall fuzzer
-
-Usage:
-    ``chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a <mode>[,<vector>,<iterations>]``
-
-    - ``mode``                       : fuzzing mode
-
-        * ``help``                 : Prints this help
-        * ``info``                 : Hypervisor information
-        * ``fuzzing``              : Fuzzing specified hypercall
-        * ``fuzzing-all``          : Fuzzing all hypercalls
-        * ``fuzzing-all-randomly`` : Fuzzing random hypercalls
-    - ``<vector>``                 : Code or name of a hypercall to be fuzzed (use info)
-    - ``<iterations>``             : Number of fuzzing iterations
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing,10 -l log.txt
-    >>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing-all,50 -l log.txt
-    >>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing-all-randomly,10,0x10000000 -l log.txt
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-from chipsec.modules.tools.vmm.xen.define import *
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.modules.tools.vmm.xen.hypercall import XenHypercall
-
-
-

-[docs]
-class HypercallFuzz(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x9e42fe3, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.html')
-
-

-[docs]
-    def usage(self):
-        self.logger.log(self.__doc__.replace('`', ''))
-        return

-
-
-

-[docs]
-    def get_int(self, arg, base=10, defvalue=10000):
-        try:
-            value = int(arg, base)
-        except ValueError:
-            self.logger.log_error(f'Invalid integer parameter: \'{arg}\' (using default value: {defvalue:d})')
-            value = defvalue
-        return value

-
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test('Xen Hypervisor Hypercall Fuzzer')
-        command = module_argv[0] if len(module_argv) > 0 else ''
-        arg1 = module_argv[1] if len(module_argv) > 1 else ''
-        arg2 = module_argv[2] if len(module_argv) > 2 else ''
-
-        xen = XenHypercall()
-        xen.prompt = 'CHIPSEC'
-        xen.debug = False
-
-        if command == 'help':
-            self.usage()
-        elif command == 'info':
-            info = xen.get_hypervisor_info()
-            if len(info) > 0:
-                xen.hypervisor_present = True
-                xen.print_hypervisor_info(info)
-                xen.scan_hypercalls(range(256))
-                xen.print_hypercall_status()
-
-        elif command == 'fuzzing':
-            name2code = {v.lower(): k for k, v in hypercall_names.items()}
-            try:
-                code = int(arg1, 16)
-            except ValueError:
-                if arg1.lower() not in name2code:
-                    self.logger.log_error(f'Unknown hypercall: \'{arg1}\'')
-                    self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_OPTION)
-                    return self.rc_res.getReturnCode(ModuleResult.ERROR)
-                code = name2code[arg1.lower()]
-            count = self.get_int(arg2)
-            xen.fuzz_hypercall(code, count)
-
-        elif command in ['fuzzing-all', 'fuzzing-all-randomly']:
-            count = self.get_int(arg1)
-            xen.scan_hypercalls(range(256))
-            xen.print_hypercall_status()
-            self.logger.log('\nStart fuzzing ...\n')
-            excluded = [MEMORY_OP, CONSOLE_IO, GRANT_TABLE_OP, SCHED_OP]
-            vectors = sorted([x for x in xen.hypercalls.keys() if x not in excluded])
-            if command == 'fuzzing-all':
-                for vector in vectors:
-                    xen.fuzz_hypercall(vector, count)
-            else:
-                xen.fuzz_hypercalls_randomly(vectors, count)
-        else:
-            self.logger.log(f'Invalid command: {command}\n')
-            self.usage()
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.POTENTIALLY_VULNERABLE)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/vmm/xen/xsa188.html b/_modules/chipsec/modules/tools/vmm/xen/xsa188.html
deleted file mode 100644
index fdbd00e4..00000000
--- a/_modules/chipsec/modules/tools/vmm/xen/xsa188.html
+++ /dev/null
@@ -1,200 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.vmm.xen.xsa188 — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.vmm.xen.xsa188
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2010-2016, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-
-"""
-This module triggers host crash on vulnerable Xen 4.4
-
-Reference:
-    - `Proof-of-concept module for Xen XSA-188 <https://xenbits.xen.org/xsa/advisory-188.html>`_
-        - CVE-2016-7154: "use after free in FIFO event channel code"
-        - Discovered by Mikhail Gorobets
-
-Usage:
-    ``chipsec_main.py -m tools.vmm.xen.xsa188``
-
-Examples:
-    >>> chipsec_main.py -i -m tools.vmm.xen.xsa188
-
-.. note::
-    - Returns a Warning by default
-    - System may be in an unknown state, further evaluation may be needed
-
-.. important::
-    - This module is designed to run in a VM environment
-    - Behavior on physical HW is undefined
-
-"""
-
-from chipsec.module_common import BaseModule, ModuleResult
-from chipsec.hal.vmm import VMM
-
-EVENT_CHANNEL_OP = 32
-EVTCHOP_INIT_CONTROL = 11
-
-
-

-[docs]
-class xsa188(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self.rc_res = ModuleResult(0x13a3575, 'https://chipsec.github.io/modules/chipsec.modules.tools.vmm.xen.xsa188.html')
-
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test('Xen XSA-188 PoC check')
-        (args_va, args_pa) = self.cs.mem.alloc_physical_mem(0x1000, 0xFFFFFFFFFFFFFFFF)
-        args = '\xFF' * 8 + '\x00' * 16
-        self.cs.mem.write_physical_mem(args_pa, len(args), args)
-        self.vmm = VMM(self.cs)
-        self.vmm.hypercall64_five_args(EVENT_CHANNEL_OP, EVTCHOP_INIT_CONTROL, args_va)
-        self.vmm.hypercall64_five_args(EVENT_CHANNEL_OP, EVTCHOP_INIT_CONTROL, args_va)
-
-        self.logger.log_information('Module completed')
-        self.logger.log_warning('System may be in an unknown state, further evaluation may be needed.')
-        self.rc_res.setStatusBit(self.rc_res.status.POTENTIALLY_VULNERABLE)
-        self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/modules/tools/wsmt.html b/_modules/chipsec/modules/tools/wsmt.html
deleted file mode 100644
index 0f351d90..00000000
--- a/_modules/chipsec/modules/tools/wsmt.html
+++ /dev/null
@@ -1,223 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.modules.tools.wsmt — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.modules.tools.wsmt
-# -*- coding: utf-8 -*-
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2021, SentinelOne
-# Copyright (c) 2021, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-"""
-The Windows SMM Security Mitigation Table (WSMT) is an ACPI table defined by Microsoft that allows
-system firmware to confirm to the operating system that certain security best practices have been
-implemented in System Management Mode (SMM) software.
-
-Reference:
-    - See <https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/oem-uefi-wsmt> for more details.
-
-Usage:
-    ``chipsec_main -m common.wsmt``
-
-Examples:
-    >>> chipsec_main.py -m common.wsmt
-
-.. note::
-    - Analysis is only necessary if Windows is the primary OS
-
-"""
-from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS, MTAG_SMM
-from chipsec.hal.acpi import ACPI
-from chipsec.hal.acpi_tables import WSMT
-
-TAGS = [MTAG_BIOS, MTAG_SMM]
-
-
-

-[docs]
-class wsmt(BaseModule):
-    def __init__(self):
-        BaseModule.__init__(self)
-        self._acpi = ACPI(self.cs)
-        self.rc_res = ModuleResult(0x6ae0748, 'https://chipsec.github.io/modules/chipsec.modules.tools.wsmt.html')
-
-

-[docs]
-    def is_supported(self):
-        return True

-
-
-

-[docs]
-    def check_wsmt(self):
-        table_data = self._acpi.get_ACPI_table("WSMT")
-        if not table_data:
-            self.logger.log_warning('WSMT table was not found.')
-            self.rc_res.setStatusBit(self.rc_res.status.UNSUPPORTED_FEATURE)
-            return self.rc_res.getReturnCode(ModuleResult.WARNING)
-
-        wsmt_table = WSMT()
-        try:
-            wsmt_table.parse(table_data[0][1])
-        except TypeError:
-            self.logger.log_error('Issue parsing the WSMT table data.')
-            self.rc_res.setStatusBit(self.rc_res.status.PARSE_ISSUE)
-            return self.rc_res.getReturnCode(ModuleResult.ERROR)
-
-        self.logger.log(wsmt_table)
-
-        if (not wsmt_table.fixed_comm_buffers) or (not wsmt_table.comm_buffer_nested_ptr_protection) or (not wsmt_table.system_resource_protection):
-            self.logger.log_warning('WSMT table is present but certain mitigations are missing.')
-            self.rc_res.setStatusBit(self.rc_res.status.MITIGATION)
-            self.res = self.rc_res.getReturnCode(ModuleResult.WARNING)
-        else:
-            self.logger.log_passed("WSMT table is present and reports all supported mitigations.")
-            self.rc_res.setStatusBit(self.rc_res.status.SUCCESS)
-            self.res = self.rc_res.getReturnCode(ModuleResult.PASSED)

-
-
-    # --------------------------------------------------------------------------
-    # run( module_argv )
-    # Required function: run here all tests from this module
-    # --------------------------------------------------------------------------
-

-[docs]
-    def run(self, module_argv):
-        self.logger.start_test("WSMT Configuration")
-        self.check_wsmt()
-        if self.res == ModuleResult.WARNING:
-            self.logger.log_important('Manual analysis of SMI handlers is required to determine if they can be abused by attackers to circumvent VBS.')
-        return self.res

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/options.html b/_modules/chipsec/options.html
index bb24b305..50c931bf 100644
--- a/_modules/chipsec/options.html
+++ b/_modules/chipsec/options.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.options — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -63,24 +65,19 @@ 
Source code for chipsec.options
 from chipsec.exceptions import CSConfigError
 
 
-

-[docs]
-class Options(object):
+
[docs]class Options(object):
     def __init__(self):
         options_path = os.path.join(get_main_dir(), 'chipsec', 'options')
         if not os.path.isdir(options_path):
             raise CSConfigError(f'Unable to locate configuration options: {options_path}')
         options_name = os.path.join(options_path, 'cmd_options.ini')
         self.config = configparser.ConfigParser()
-        self.config.read(options_name)
-
+        with open(options_name) as options_file:
+            self.config.read_file(options_file)
 
-

-[docs]
-    def get_section_data(self, section, key):
-        return self.config.get(section, key)

-

 
+
[docs]    def get_section_data(self, section, key):
+        return self.config.get(section, key)

 

 
             

@@ -140,7 +137,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -160,8 +157,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/parsers.html b/_modules/chipsec/parsers.html
index f32e2afa..f22b512f 100644
--- a/_modules/chipsec/parsers.html
+++ b/_modules/chipsec/parsers.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.parsers — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -61,9 +63,7 @@ 
Source code for chipsec.parsers
 from chipsec.logger import logger
 
 
-

-[docs]
-class Stage(Enum):
+
[docs]class Stage(Enum):
     NONE = 0
     GET_INFO = 10
     DEVICE_CFG = 20
@@ -72,7 +72,6 @@ 
Source code for chipsec.parsers
     EXTRA = 50

 
 
-
 # Stage - None
 # - Never runs
 # - stage_data - None
@@ -103,49 +102,31 @@ 
Source code for chipsec.parsers
 # - Returns - None
 
 
-

-[docs]
-class BaseConfigParser:
+
[docs]class BaseConfigParser:
     def __init__(self, cfg_obj):
         self.logger = logger()
         self.cfg = cfg_obj
 
-

-[docs]
-    def startup(self):
+
[docs]    def startup(self):
         return None

 
-
-

-[docs]
-    def get_metadata(self):
+
[docs]    def get_metadata(self):
         return {'template': self.def_handler}

 
-
-

-[docs]
-    def get_stage(self):
+
[docs]    def get_stage(self):
         return Stage.NONE

 
-
-

-[docs]
-    def def_handler(self, et_node, stage_data=None):
-        return None

-

-
+
[docs]    def def_handler(self, et_node, stage_data=None):
+        return None

 
 
 parsers = [BaseConfigParser]
 
 
-

-[docs]
-class BaseConfigHelper:
+
[docs]class BaseConfigHelper:
     def __init__(self, cfg_obj):
         self.logger = logger()
         self.cfg = cfg_obj

-
 

 
             

@@ -205,7 +186,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -225,8 +206,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/testcase.html b/_modules/chipsec/testcase.html
deleted file mode 100644
index abe29ce8..00000000
--- a/_modules/chipsec/testcase.html
+++ /dev/null
@@ -1,561 +0,0 @@
-
-
-
-  
-    
-    
-    chipsec.testcase — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    

-      

-        

-          

-            
-  
Source code for chipsec.testcase
-# CHIPSEC: Platform Security Assessment Framework
-# Copyright (c) 2018-2022, Intel Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# as published by the Free Software Foundation; Version 2.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-#
-# Contact information:
-# chipsec@intel.com
-#
-
-import json
-import time
-import os
-from collections import OrderedDict
-import xml.etree.ElementTree as ET
-import xml.dom.minidom
-from chipsec.logger import logger
-from typing import Dict, List, Type, Optional
-
-
-

-[docs]
-class ExitCode:
-    OK = 0
-    WARNING = 2
-    DEPRECATED = 4
-    FAIL = 8
-    ERROR = 16
-    EXCEPTION = 32
-    INFORMATION = 64
-    NOTAPPLICABLE = 128
-
-    help_epilog = """\
-  Exit Code
-  ---------
-  CHIPSEC returns an integer exit code:
-  - Exit code is 0:       all modules ran successfully and passed
-  - Exit code is not 0:   each bit means the following:
-      - Bit 1: WARNING         at least one module had a warning
-      - Bit 2: DEPRECATED      at least one module uses deprecated API
-      - Bit 3: FAIL            at least one module failed
-      - Bit 4: ERROR           at least one module wasn't able to run
-      - Bit 5: EXCEPTION       at least one module threw an unexpected exception
-      - Bit 6: INFORMATION     at least one module contained information
-      - Bit 7: NOT APPLICABLE  at least one module was not applicable for the platform
-
-"""

-
-
-

-[docs]
-class TestCase:
-    def __init__(self, name: str) -> None:
-        self.name = name
-        self.result = ''
-        self.output = ''
-        self.argv = ''
-        self.desc = ''
-        self.startTime = 0
-        self.endTime = 0
-        self.time = None
-
-

-[docs]
-    def get_fields(self) -> Dict[str, str]:
-        return {'name': self.name, 'output': self.output, 'result': self.result}

-
-
-

-[docs]
-    def start_module(self) -> None:
-        """Displays a banner for the module name provided."""
-        text = f'\n[*] Running module: {self.name}'
-        logger().log_heading(text)
-        self.startTime = time.time()
-        self.desc = self.name

-
-
-

-[docs]
-    def end_module(self, result: str, arg: str) -> None:
-        self.result = result
-        self.argv = arg
-        self.endTime = time.time()
-        self.time = self.endTime - self.startTime

-

-
-
-
-

-[docs]
-class ChipsecResults:
-    def __init__(self, rc: bool = False):
-        self.test_cases = []
-        self.properties = None
-        self.summary = False
-        self.exceptions = []
-        self.time = None
-        self.using_return_codes = rc
-
-

-[docs]
-    def add_properties(self, properties: Dict[str, str]) -> None:
-        self.properties = properties

-
-
-

-[docs]
-    def add_testcase(self, test: Type[TestCase]) -> None:
-        self.test_cases.append(test)

-
-
-

-[docs]
-    def get_current(self) -> Optional[Type[TestCase]]:
-        if len(self.test_cases) == 0 or self.summary:
-            return None
-        return self.test_cases[len(self.test_cases) - 1]

-
-
-

-[docs]
-    def add_exception(self, name):
-        self.exceptions.append(str(name))

-
-
-

-[docs]
-    def get_return_code(self) -> Dict[str, List[TestCase]]:
-        if self.using_return_codes:
-            return self.get_return_codeRC()
-        return self.get_return_codeL()

-
-    
-    # -------------------------------------------------------
-    # Legacy results
-    # -------------------------------------------------------
-

-[docs]
-    def order_summaryL(self) -> Dict[str, List[TestCase]]:
-        self.summary = True
-        ret = OrderedDict()
-        passed = []
-        failed = []
-        errors = []
-        warnings = []
-        information = []
-        notapplicable = []
-        executed = 0
-        for test in self.test_cases:
-            executed += 1
-            fields = test.get_fields()
-            if fields['result'] == 'Passed':
-                passed.append(fields['name'])
-            elif fields['result'] == 'Failed':
-                failed.append(fields['name'])
-            elif fields['result'] == 'Error':
-                errors.append(fields['name'])
-            elif fields['result'] == 'Warning':
-                warnings.append(fields['name'])
-            elif fields['result'] == 'Information':
-                information.append(fields['name'])
-            elif fields['result'] == 'NotApplicable':
-                notapplicable.append(fields['name'])
-        ret['total'] = executed
-        ret['failed to run'] = errors
-        ret['passed'] = passed
-        ret['information'] = information
-        ret['failed'] = failed
-        ret['warnings'] = warnings
-        ret['not applicable'] = notapplicable
-        ret['exceptions'] = self.exceptions
-        return ret

-
-
-

-[docs]
-    def get_return_codeL(self) -> int:
-        summary = self.order_summaryL()
-        if len(summary['failed to run']) != 0:
-            return ExitCode.ERROR
-        elif len(summary['exceptions']) != 0:
-            return ExitCode.EXCEPTION
-        elif len(summary['failed']) != 0:
-            return ExitCode.FAIL
-        elif len(summary['warnings']) != 0:
-            return ExitCode.WARNING
-        elif len(summary['not applicable']) != 0:
-            return ExitCode.NOTAPPLICABLE
-        elif len(summary['information']) != 0:
-            return ExitCode.INFORMATION
-        else:
-            return ExitCode.OK

-
-    # -------------------------------------------------------
-        
-

-[docs]
-    def order_summaryRC(self):
-        if self.time is None:
-            self.set_time()
-        self.summary = True
-        ret = OrderedDict()
-        passed = []
-        failed = []
-        executed = 0
-        for test in self.test_cases:
-            executed += 1
-            fields = test.get_fields()
-            if fields['result'] == 'Passed':
-                passed.append(fields['name'])
-            elif fields['result'] == 'Failed':
-                failed.append(fields['name'])
-        ret['total'] = executed
-        ret['failed'] = failed
-        ret['passed'] = passed
-        ret['exceptions'] = self.exceptions
-        return ret

-
-
-

-[docs]
-    def get_return_codeRC(self):
-        summary = self.order_summaryRC()
-        if len(summary['failed']) != 0:
-            return ExitCode.FAIL
-        else:
-            return ExitCode.OK

-
-
-
-

-[docs]
-    def set_time(self, pTime: Optional[float] = None) -> None:
-        """Sets the time"""
-        if pTime is not None:
-            self.time = pTime
-        else:
-            if len(self.test_cases) > 1:
-                self.time = self.get_current().endTime - self.test_cases[0].startTime
-            else:
-                self.time = self.test_cases[0].time

-
-
-

-[docs]
-    def get_results(self) -> Dict[str, int]:
-        results = {}
-        for test in self.test_cases:
-            results[test.name] = {'result': test.result}
-        return results

-
-
-

-[docs]
-    def xml_summary(self) -> str:
-        summary = self.order_summary()
-        xml_element = ET.Element("Summary")
-        for value in summary.keys():
-            temp = {}
-            if value == 'total':
-                temp['name'] = value
-                temp['total'] = f'{summary[value]:d}'
-                m_element = ET.SubElement(xml_element, 'result', temp)
-            else:
-                temp['name'] = value
-                temp['total'] = f'{len(summary[value]):d}'
-                m_element = ET.SubElement(xml_element, 'result', temp)
-                for mod in summary[value]:
-                    n_element = ET.SubElement(m_element, 'module')
-                    n_element.text = mod
-        return ET.tostring(xml_element, "unicode", None)

-
-
-

-[docs]
-    def json_summary(self) -> str:
-        summary = self.order_summary()
-        js = json.dumps(summary, sort_keys=False, indent=2, separators=(',', ': '))
-        return js

-
-
-

-[docs]
-    def json_full(self) -> str:
-        summary = self.get_results()
-        js = json.dumps(summary, sort_keys=False, indent=2, separators=(',', ': '))
-        return js

-
-
-

-[docs]
-    def xml_full(self, name: str, runtime: Optional[float] = None) -> str:
-        xml_element = ET.Element('testsuites')
-        summary = self.order_summary()
-        summary_dict = {}
-        for value in summary.keys():
-            if value == 'total':
-                summary_dict[value] = f'{summary[value]:d}'
-            else:
-                summary_dict[value.replace(' ', '')] = f'{len(summary[value]):d}'
-        summary_dict["name"] = os.path.basename(os.path.splitext(name)[0])
-        if runtime is not None:
-            summary_dict["time"] = f'{runtime:5f}'
-        ts_element = ET.SubElement(xml_element, "testsuite", summary_dict)
-        # add properties
-        pr_element = ET.SubElement(ts_element, "properties")
-        prop_dict = {}
-        if self.properties is not None:
-            for value in self.properties:
-                prop_dict["name"] = value
-                prop_dict["value"] = self.properties[value]
-                ET.SubElement(pr_element, "property", prop_dict)
-        # add test cases
-        for test in self.test_cases:
-            ttime = test.time if test.time is not None else 0.0
-            tc_element = ET.SubElement(ts_element, "testcase", {'classname': test.name, 'name': test.desc, 'time': f'{ttime:5f}'})
-            ET.SubElement(tc_element, "pass", {"type": test.result})
-            out_element = ET.SubElement(tc_element, "system-out")
-            out_element.text = test.output
-        return xml.dom.minidom.parseString(ET.tostring(xml_element, None, None)).toprettyxml()

-
-
-

-[docs]
-    def markdown_full(self, name: str) -> str:
-        passed = []
-        failed = []
-        error = []
-        warning = []
-        information = []
-        notapplicable = []
-        deprecated = []
-        destination = {'Passed': passed,
-                       'Failed': failed,
-                       'Error': error,
-                       'Warning': warning,
-                       'Information': information,
-                       'NotApplicable': notapplicable,
-                       'Deprecated': deprecated
-                       }
-
-        for test in self.test_cases:
-            # Test case as header level 4
-            out_string = f'#### {test.name.replace("chipsec.modules.", ""):s}\n'
-            for line in test.output.splitlines(True):
-                # Format output as code
-                out_string += f'    {line:s}'
-            destination[test.result].append(out_string)
-
-        ret_string = ''
-        for result in destination:
-            # Category as header level 1
-            ret_string += f'\n# {result:s}:{len(destination[result]):d}\n'
-            ret_string += ''.join(destination[result])
-        return ret_string

-
-    
-

-[docs]
-    def print_summary(self, runtime: Optional[float] = None) -> None:
-        if self.using_return_codes:
-            self.print_summaryRC(runtime)
-        else:
-            self.print_summaryL(runtime)

-
-
-

-[docs]
-    def print_summaryL(self, runtime: Optional[float] = None) -> None:
-        summary = self.order_summaryL()
-        filler = '*' * 27
-        logger().log(f'\n[CHIPSEC] {filler}  SUMMARY  {filler}')
-        if runtime is not None:
-            logger().log(f'[CHIPSEC] Time elapsed            {runtime:.3f}')
-
-        for result in summary.keys():
-            if result == 'total':
-                logger().log(f'[CHIPSEC] Modules {result:16}{summary[result]:d}')
-            elif result == 'warnings':
-                logger().log(f'[CHIPSEC] Modules with {result:11}{len(summary[result]):d}:')
-                for mod in summary[result]:
-                    logger().log_warning(mod)
-            elif result == 'exceptions':
-                if len(summary[result]) > 0:
-                    logger().log(f'[CHIPSEC] Modules with {result:11}{len(summary[result]):d}:')
-                    for mod in summary[result]:
-                        logger().log_error(mod)
-            else:
-                logger().log(f'[CHIPSEC] Modules {result:16}{len(summary[result]):d}:')
-                for mod in summary[result]:
-                    if result == 'failed to run':
-                        logger().log_error(mod)
-                    elif result == 'passed':
-                        logger().log_passed(mod)
-                    elif result == 'information':
-                        logger().log_information(mod)
-                    elif result == 'failed':
-                        logger().log_failed(mod)
-                    elif result == 'not applicable':
-                        logger().log_not_applicable(mod)
-        logger().log('[CHIPSEC] *****************************************************************')

-
-
-

-[docs]
-    def print_summaryRC(self, runtime: Optional[float] = None) -> None:
-        summary = self.order_summaryRC()
-        filler = '*' * 27
-        logger().log(f'\n[CHIPSEC] {filler}  SUMMARY  {filler}')
-        if runtime is not None:
-            logger().log(f'[CHIPSEC] Time elapsed            {runtime:.3f}')
-
-        for result in summary.keys():
-            if result == 'total':
-                logger().log(f'[CHIPSEC] Modules {result:16}{summary[result]:d}')
-            elif result == 'exceptions':
-                if len(summary[result]) > 0:
-                    logger().log(f'[CHIPSEC] Modules with {result:11}{len(summary[result]):d}:')
-                    for mod in summary[result]:
-                        logger().log_error(mod)
-            else:
-                logger().log(f'[CHIPSEC] Modules {result:16}{len(summary[result]):d}:')
-                for mod in summary[result]:
-                    logger().log(f"    {mod}")
-        logger().log('[CHIPSEC] *****************************************************************')

-

-
-

-
-            

-          

-        

-      

-      
-      

-    

-    
-    
-  
-
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/acpi_cmd.html b/_modules/chipsec/utilcmd/acpi_cmd.html
index 73ca6f73..dfe42ea8 100644
--- a/_modules/chipsec/utilcmd/acpi_cmd.html
+++ b/_modules/chipsec/utilcmd/acpi_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.acpi_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -84,20 +86,13 @@ 
Source code for chipsec.utilcmd.acpi_cmd
 # ###################################################################
 
 
-

-[docs]
-class ACPICommand(BaseCommand):
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]class ACPICommand(BaseCommand):
+
[docs]    def requirements(self) -> toLoad:
         if self.func == self.acpi_table and self._file:
             return toLoad.Nil # TODO: Fix this case. Need to update ACPI HAL to not try to auto-populate tables.
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_list = subparsers.add_parser('list')
@@ -109,23 +104,14 @@ 
Source code for chipsec.utilcmd.acpi_cmd
         parser_table.set_defaults(func=self.acpi_table)
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._acpi = ACPI(self.cs)

 
-
-

-[docs]
-    def acpi_list(self) -> None:
+
[docs]    def acpi_list(self) -> None:
         self.logger.log('[CHIPSEC] Enumerating ACPI tables..')
         self._acpi.print_ACPI_table_list()

 
-
-

-[docs]
-    def acpi_table(self) -> None:
+
[docs]    def acpi_table(self) -> None:
         name = self._name[0]
         if not self._file and not self._acpi.is_ACPI_table_present(name):
             self.logger.log_error(f'Please specify table name from {self._acpi.tableList.keys()}')
@@ -133,11 +119,9 @@ 
Source code for chipsec.utilcmd.acpi_cmd
         elif self._file and not path_exists(name):
             self.logger.log_error(f"[CHIPSEC] Unable to find file '{name}'")
             return
-        self.logger.log(f"[CHIPSEC] reading ACPI table {'from file' if self._file else ''} '{name}'")
+        self.logger.log(f"[CHIPSEC] reading ACPI table {'from file' if self._file else ''} '{name}'")
         self._acpi.dump_ACPI_table(name, self._file)
-        return

-

-
+        return

 
 
 commands = {'acpi': ACPICommand}
@@ -200,7 +184,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -220,8 +204,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/chipset_cmd.html b/_modules/chipsec/utilcmd/chipset_cmd.html
index 3198df24..b053299f 100644
--- a/_modules/chipsec/utilcmd/chipset_cmd.html
+++ b/_modules/chipsec/utilcmd/chipset_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.chipset_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -73,37 +75,25 @@ 
Source code for chipsec.utilcmd.chipset_cmd
 # ###################################################################
 
 
-

-[docs]
-class PlatformCommand(BaseCommand):
-    """
+
[docs]class PlatformCommand(BaseCommand):
+    """
     chipsec_util platform
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         pass

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         try:
             self.cs.Cfg.print_supported_chipsets()
             self.logger.log("")
             self.cs.Cfg.print_platform_info()
             self.cs.Cfg.print_pch_info()
         except UnknownChipsetError as msg:
-            self.logger.log_error(msg)

-

-
+            self.logger.log_error(msg)

 
 
 commands = {'platform': PlatformCommand}
@@ -166,7 +156,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -186,8 +176,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/cmos_cmd.html b/_modules/chipsec/utilcmd/cmos_cmd.html
index 31c27ed1..0d403fcb 100644
--- a/_modules/chipsec/utilcmd/cmos_cmd.html
+++ b/_modules/chipsec/utilcmd/cmos_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.cmos_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,20 +77,13 @@ 
Source code for chipsec.utilcmd.cmos_cmd
 from chipsec.exceptions import CmosRuntimeError
 
 
-

-[docs]
-class CMOSCommand(BaseCommand):
+
[docs]class CMOSCommand(BaseCommand):
 
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
 
         parser_offset = ArgumentParser(add_help=False)
@@ -117,48 +112,28 @@ 
Source code for chipsec.utilcmd.cmos_cmd
 
         parser.parse_args(self.argv, namespace=CMOSCommand)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._cmos = CMOS(self.cs)

-
     
-

-[docs]
-    def cmos_dump(self) -> None:
+
[docs]    def cmos_dump(self) -> None:
         self.logger.log("[CHIPSEC] Dumping CMOS memory..")
         self._cmos.dump()

 
-
-

-[docs]
-    def cmos_readl(self) -> None:
+
[docs]    def cmos_readl(self) -> None:
         val = self._cmos.read_cmos_low(self.offset)
         self.logger.log(f'[CHIPSEC] CMOS low byte 0x{self.offset:X} = 0x{val:X}')

 
-
-

-[docs]
-    def cmos_writel(self) -> None:
+
[docs]    def cmos_writel(self) -> None:
         val = self._cmos.write_cmos_low(self.offset, self.value)
         self.logger.log(f'[CHIPSEC] CMOS low byte 0x{self.offset:X} = 0x{self.value:X}')

 
-
-

-[docs]
-    def cmos_readh(self) -> None:
+
[docs]    def cmos_readh(self) -> None:
         val = self._cmos.read_cmos_high(self.offset)
         self.logger.log(f'[CHIPSEC] CMOS high byte 0x{self.offset:X} = 0x{val:X}')

 
-
-

-[docs]
-    def cmos_writeh(self) -> None:
+
[docs]    def cmos_writeh(self) -> None:
         self.logger.log(f'[CHIPSEC] Writing CMOS high byte 0x{self.offset:X} <- 0x{self.value:X}')
-        self._cmos.write_cmos_high(self.offset, self.value)

-

-
+        self._cmos.write_cmos_high(self.offset, self.value)

 
 commands = {'cmos': CMOSCommand}
 

@@ -220,7 +195,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -240,8 +215,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/config_cmd.html b/_modules/chipsec/utilcmd/config_cmd.html
index b7cc9f9e..7caf81f8 100644
--- a/_modules/chipsec/utilcmd/config_cmd.html
+++ b/_modules/chipsec/utilcmd/config_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.config_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -73,19 +75,12 @@ 
Source code for chipsec.utilcmd.config_cmd
 from typing import Any, Dict
 
 
-

-[docs]
-class CONFIGCommand(BaseCommand):
+
[docs]class CONFIGCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Config

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
 
         subparsers = parser.add_subparsers()
@@ -99,10 +94,7 @@ 
Source code for chipsec.utilcmd.config_cmd
         parser.parse_args(self.argv, namespace=self)

 
 
-
-

-[docs]
-    def show(self) -> None:
+
[docs]    def show(self) -> None:
         if self.config == "ALL":
             config = ['CONFIG_PCI', 'REGISTERS', 'MMIO_BARS', 'IO_BARS', 'MEMORY_RANGES', 'CONTROLS', 'BUS', 'LOCKS']
         else:
@@ -130,10 +122,7 @@ 
Source code for chipsec.utilcmd.config_cmd
                 elif mconfig == "BUS":
                     self.logger.log(f'\t{name} - {self.bus_details(cfg[name])}')

 
-
-

-[docs]
-    def register_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def register_details(self, regi: Dict[str, Any]) -> str:
         ret = ''
         if regi['type'] == 'pcicfg' or regi['type'] == 'mmcfg':
             if 'device' in regi.keys():
@@ -156,21 +145,15 @@ 
Source code for chipsec.utilcmd.config_cmd
             ret = f'access: {regi["access"]}, address: {regi["address"]}, offset: {regi["offset"]}, size: {regi["size"]}'
         if 'FIELDS' in regi.keys():
             for key in regi['FIELDS'].keys():
-                extension = (f'\n\t\t{key} - bit {regi["FIELDS"][key]["bit"]}:{int(regi["FIELDS"][key]["size"]) + int(regi["FIELDS"][key]["bit"]) - 1}')
+                extension = (f'\n\t\t{key} - bit {regi["FIELDS"][key]["bit"]}:{int(regi["FIELDS"][key]["size"]) + int(regi["FIELDS"][key]["bit"]) - 1}')
                 ret += extension
         return ret

 
-
-

-[docs]
-    def pci_details(self, regi: Dict[str, Any]) -> str:
-        ret = f'bus: {regi["bus"]}, dev: {regi["dev"]}, func: {regi["fun"]}, vid: {regi["vid"]}, did: {regi["did"] if "did" in regi.keys() else None}'
+
[docs]    def pci_details(self, regi: Dict[str, Any]) -> str:
+        ret = f'bus: {regi["bus"]}, dev: {regi["dev"]}, func: {regi["fun"]}, vid: {regi["vid"]}, did: {regi["did"] if "did" in regi.keys() else None}'
         return ret

 
-
-

-[docs]
-    def mmio_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def mmio_details(self, regi: Dict[str, Any]) -> str:
         regi_size = regi['size'] if 'size' in regi.keys() else None
         fixed_addr = regi['fixed_address'] if 'fixed_address' in regi.keys() else None
         if 'register' in regi.keys():
@@ -179,10 +162,7 @@ 
Source code for chipsec.utilcmd.config_cmd
             ret = f'bus: {regi["bus"]}, dev: {regi["dev"]}, func: {regi["fun"]}, mask: {regi["mask"]}, width: {regi["width"]}, size: {regi_size}, fixed_address: {fixed_addr}'
         return ret

 
-
-

-[docs]
-    def io_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def io_details(self, regi: Dict[str, Any]) -> str:
         regi_size = regi['size'] if 'size' in regi.keys() else None
         fixed_addr = regi['fixed_address'] if 'fixed_address' in regi.keys() else None
         if 'register' in regi.keys():
@@ -191,35 +171,21 @@ 
Source code for chipsec.utilcmd.config_cmd
             ret = f'bus: {regi["bus"]}, dev: {regi["dev"]}, func: {regi["fun"]}, reg: {regi["reg"]}, mask: {regi["mask"]}, size: {regi_size}, fixed_address: {fixed_addr}'
         return ret

 
-
-

-[docs]
-    def mem_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def mem_details(self, regi: Dict[str, Any]) -> str:
         ret = f'access: {regi["access"]}, address: {regi["address"]}, size: {regi["size"]}'
         return ret

 
-
-

-[docs]
-    def control_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def control_details(self, regi: Dict[str, Any]) -> str:
         ret = f'register: {regi["register"]}, field: {regi["field"]}'
         return ret

 
-
-

-[docs]
-    def lock_details(self, regi: Dict[str, Any]) -> str:
+
[docs]    def lock_details(self, regi: Dict[str, Any]) -> str:
         ret = f'register: {regi["register"]}, field: {regi["field"]}, value: {regi["value"]}'
         return ret

 
-
-

-[docs]
-    def bus_details(self, regi: str) -> str:
+
[docs]    def bus_details(self, regi: str) -> str:
         ret = f'bus: {regi}'
-        return ret

-

-
+        return ret

 
 
 commands = {'config': CONFIGCommand}
@@ -282,7 +248,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -302,8 +268,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/cpu_cmd.html b/_modules/chipsec/utilcmd/cpu_cmd.html
index e9f3385f..26a7ebde 100644
--- a/_modules/chipsec/utilcmd/cpu_cmd.html
+++ b/_modules/chipsec/utilcmd/cpu_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.cpu_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -86,19 +88,12 @@ 
Source code for chipsec.utilcmd.cpu_cmd
 # ###################################################################
 
 
-

-[docs]
-class CPUCommand(BaseCommand):
+
[docs]class CPUCommand(BaseCommand):
     
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_info = subparsers.add_parser('info')
@@ -120,16 +115,13 @@ 
Source code for chipsec.utilcmd.cpu_cmd
 
         parser.parse_args(self.argv, namespace=CPUCommand)

 
-
-

-[docs]
-    def cpu_info(self) -> None:
+
[docs]    def cpu_info(self) -> None:
         self.logger.log("[CHIPSEC] CPU information:")
         ht = self.cs.cpu.is_HT_active()
         threads_per_core = self.cs.cpu.get_number_logical_processor_per_core()
         threads_per_pkg = self.cs.cpu.get_number_logical_processor_per_package()
         cores_per_pkg = self.cs.cpu.get_number_physical_processor_per_package()
-        self.logger.log(f'          Hyper-Threading         : {"Enabled" if ht else "Disabled"}')
+        self.logger.log(f'          Hyper-Threading         : {"Enabled" if ht else "Disabled"}')
         self.logger.log(f'          CPU cores per package   : {cores_per_pkg:d}')
         self.logger.log(f'          CPU threads per core    : {threads_per_core:d}')
         self.logger.log(f'          CPU threads per package : {threads_per_pkg:d}')
@@ -141,17 +133,14 @@ 
Source code for chipsec.utilcmd.cpu_cmd
         except Exception:
             pass

 
-
-

-[docs]
-    def cpu_topology(self) -> Dict[str, Dict[int, List[int]]]:
+
[docs]    def cpu_topology(self) -> Dict[str, Dict[int, List[int]]]:
         self.logger.log("[CHIPSEC] CPU information:")
         ht = self.cs.cpu.is_HT_active()
         threads_per_core = self.cs.cpu.get_number_logical_processor_per_core()
         threads_per_pkg = self.cs.cpu.get_number_logical_processor_per_package()
         cores_per_pkg = self.cs.cpu.get_number_physical_processor_per_package()
         num_threads = self.cs.helper.get_threads_count()
-        self.logger.log(f'          Hyper-Threading         : {"Enabled" if ht else "Disabled"}')
+        self.logger.log(f'          Hyper-Threading         : {"Enabled" if ht else "Disabled"}')
         self.logger.log(f'          CPU cores per package   : {cores_per_pkg:d}')
         self.logger.log(f'          CPU threads per core    : {threads_per_core:d}')
         self.logger.log(f'          CPU threads per package : {threads_per_pkg:d}')
@@ -166,10 +155,7 @@ 
Source code for chipsec.utilcmd.cpu_cmd
 
         return topology

 
-
-

-[docs]
-    def cpu_cr(self) -> Optional[Union[bool, int]]:
+
[docs]    def cpu_cr(self) -> Optional[Union[bool, int]]:
         if self.value is not None:
             self.logger.log(f'[CHIPSEC] CPU{self.thread:d}: write CR{self.cr_number:d} <- 0x{self.value:08X}')
             self.cs.cpu.write_cr(self.thread, self.cr_number, self.value)
@@ -192,10 +178,7 @@ 
Source code for chipsec.utilcmd.cpu_cmd
                 self.logger.log(f'  CR4: 0x{cr4:016X}')
                 self.logger.log(f'  CR8: 0x{cr8:016X}')

 
-
-

-[docs]
-    def cpu_cpuid(self) -> None:
+
[docs]    def cpu_cpuid(self) -> None:
         self.logger.log(f'[CHIPSEC] CPUID < EAX: 0x{self.eax:08X}')
         self.logger.log(f'[CHIPSEC]         ECX: 0x{self.ecx:08X}')
 
@@ -206,10 +189,7 @@ 
Source code for chipsec.utilcmd.cpu_cmd
         self.logger.log("[CHIPSEC]         ECX: 0x%08X" % _ecx)
         self.logger.log("[CHIPSEC]         EDX: 0x%08X" % _edx)

 
-
-

-[docs]
-    def cpu_pt(self) -> None:
+
[docs]    def cpu_pt(self) -> None:
         if self.cr3 is not None:
             pt_fname = f'pt_{self.cr3:08X}'
             self.logger.log(f'[CHIPSEC] paging physical base (CR3): 0x{self.cr3:016X}')
@@ -221,9 +201,7 @@ 
Source code for chipsec.utilcmd.cpu_cmd
                 pt_fname = f'cpu{tid:d}_pt_{cr3:08X}'
                 self.logger.log(f'[CHIPSEC][cpu{tid:d}] paging physical base (CR3): 0x{cr3:016X}')
                 self.logger.log(f'[CHIPSEC][cpu{tid:d}] dumping paging hierarchy to \'{pt_fname}\'...')
-                self.cs.cpu.dump_page_tables(cr3, pt_fname)

-

-
+                self.cs.cpu.dump_page_tables(cr3, pt_fname)

 
 
 commands = {'cpu': CPUCommand}
@@ -286,7 +264,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -306,8 +284,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/decode_cmd.html b/_modules/chipsec/utilcmd/decode_cmd.html
index cc6be4cd..e516012f 100644
--- a/_modules/chipsec/utilcmd/decode_cmd.html
+++ b/_modules/chipsec/utilcmd/decode_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.decode_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -94,19 +96,12 @@ 
Source code for chipsec.utilcmd.decode_cmd
 from chipsec.hal.uefi import uefi_platform
 
 
-

-[docs]
-class DecodeCommand(BaseCommand):
+
[docs]class DecodeCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Nil

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         parser.add_argument('_rom', metavar='<rom>', help='file to decode')
         parser.add_argument('_fwtype', metavar='fw_type', nargs='?', help='firmware type', default=None)
@@ -118,16 +113,10 @@ 
Source code for chipsec.utilcmd.decode_cmd
             self.func = self.decode_rom

 
 
+
[docs]    def decode_types(self) -> None:
+        self.logger.log(f'\n<fw_type> should be in [ {" | ".join([f"{t}" for t in uefi_platform.fw_types])} ]\n')

 
-

-[docs]
-    def decode_types(self) -> None:
-        self.logger.log(f'\n<fw_type> should be in [ {" | ".join([f"{t}" for t in uefi_platform.fw_types])} ]\n')

-
-
-

-[docs]
-    def decode_rom(self) -> bool:
+
[docs]    def decode_rom(self) -> bool:
         self.logger.log(f'[CHIPSEC] Decoding SPI ROM image from a file \'{self._rom}\'')
         f = read_file(self._rom)
         if not f:
@@ -174,9 +163,7 @@ 
Source code for chipsec.utilcmd.decode_cmd
                     decode_uefi_region(pth, fname, self._fwtype)
 
         self.logger.set_log_file(_orig_logname)
-        return True

-

-
+        return True

 
 
 commands = {"decode": DecodeCommand}
@@ -239,7 +226,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -259,8 +246,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/deltas_cmd.html b/_modules/chipsec/utilcmd/deltas_cmd.html
index 6b3d7047..f61fa4b3 100644
--- a/_modules/chipsec/utilcmd/deltas_cmd.html
+++ b/_modules/chipsec/utilcmd/deltas_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.deltas_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,19 +77,12 @@ 
Source code for chipsec.utilcmd.deltas_cmd
 import chipsec.result_deltas
 from chipsec.options import Options
 
-

-[docs]
-class DeltasCommand(BaseCommand):
+
[docs]class DeltasCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Nil

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         options = Options()
         try:
             default_format = options.get_section_data('Util_Config','log_output_deltas_format')
@@ -102,10 +97,7 @@ 
Source code for chipsec.utilcmd.deltas_cmd
         parser.add_argument('_out_name', nargs='?', default=default_out_file, help='output filename')
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         start_time = time()
 
         # Read files and determine deltas
@@ -128,9 +120,7 @@ 
Source code for chipsec.utilcmd.deltas_cmd
         # Display the results
         chipsec.result_deltas.display_deltas(deltas, True, start_time)
 
-        return

-

-
+        return

 
 
 commands = {'deltas': DeltasCommand}
@@ -193,7 +183,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -213,8 +203,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/desc_cmd.html b/_modules/chipsec/utilcmd/desc_cmd.html
index 425245ec..8a56b9a6 100644
--- a/_modules/chipsec/utilcmd/desc_cmd.html
+++ b/_modules/chipsec/utilcmd/desc_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.desc_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -95,10 +97,8 @@ 
Source code for chipsec.utilcmd.desc_cmd
 # CPU descriptor tables
 
 
-

-[docs]
-class IDTCommand(BaseCommand):
-    """
+
[docs]class IDTCommand(BaseCommand):
+    """
     >>> chipsec_util idt [cpu_id]
 
     Examples:
@@ -107,38 +107,26 @@ 
Source code for chipsec.utilcmd.desc_cmd
     >>> chipsec_util idt
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=IDTCommand.__doc__)
         parser.add_argument('_thread', metavar='thread', type=lambda x: int(x, 0), nargs='?', default=None, help="thread")
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         num_threads = self.cs.msr.get_cpu_thread_count()
         if self._thread and self._thread < num_threads:
             self.logger.log(f'[CHIPSEC] Dumping IDT of CPU thread {self._thread:d}')
             self.cs.msr.IDT(self._thread, 4)
         else:
             self.logger.log(f'[CHIPSEC] Dumping IDT of {num_threads:d} CPU threads')
-            self.cs.msr.IDT_all(4)

-

+            self.cs.msr.IDT_all(4)

 
 
-
-

-[docs]
-class GDTCommand(BaseCommand):
-    """
+
[docs]class GDTCommand(BaseCommand):
+    """
     >>> chipsec_util gdt [cpu_id]
 
     Examples:
@@ -147,38 +135,26 @@ 
Source code for chipsec.utilcmd.desc_cmd
     >>> chipsec_util gdt
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=GDTCommand.__doc__)
         parser.add_argument('_thread', metavar='thread', type=lambda x: int(x, 0), nargs='?', default=None, help="thread")
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         num_threads = self.cs.msr.get_cpu_thread_count()
         if self._thread and self._thread < num_threads:
             self.logger.log(f'[CHIPSEC] Dumping IDT of CPU thread {self._thread:d}')
             self.cs.msr.GDT(self._thread, 4)
         else:
             self.logger.log(f'[CHIPSEC] Dumping IDT of {num_threads:d} CPU threads')
-            self.cs.msr.GDT_all(4)

-

-
+            self.cs.msr.GDT_all(4)

 
 
-

-[docs]
-class LDTCommand(BaseCommand):
-    """
+
[docs]class LDTCommand(BaseCommand):
+    """
     >>> chipsec_util ldt [cpu_id]
 
     Examples:
@@ -187,24 +163,14 @@ 
Source code for chipsec.utilcmd.desc_cmd
     >>> chipsec_util ldt
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Nil

-
     
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         return

 
-
-

-[docs]
-    def run(self) -> None:
-        self.logger.log_error("[CHIPSEC] ldt not implemented")

-

-
+
[docs]    def run(self) -> None:
+        self.logger.log_error("[CHIPSEC] ldt not implemented")

 
 
 commands = {'idt': IDTCommand, 'gdt': GDTCommand}
@@ -267,7 +233,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -287,8 +253,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/ec_cmd.html b/_modules/chipsec/utilcmd/ec_cmd.html
index 47d75457..4ddcd77a 100644
--- a/_modules/chipsec/utilcmd/ec_cmd.html
+++ b/_modules/chipsec/utilcmd/ec_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.ec_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -83,21 +85,14 @@ 
Source code for chipsec.utilcmd.ec_cmd
 
 
 # Embedded Controller
-

-[docs]
-class ECCommand(BaseCommand):
+
[docs]class ECCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         if hasattr(self, 'func'):
             return toLoad.Driver
         return toLoad.Nil

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
 
         parser_offset = ArgumentParser(add_help=False)
@@ -126,34 +121,22 @@ 
Source code for chipsec.utilcmd.ec_cmd
         parser_index.set_defaults(func=self.index)
 
         parser.parse_args(self.argv, namespace=self)

-
         
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._ec = EC(self.cs)

 
-
-

-[docs]
-    def dump(self) -> None:
+
[docs]    def dump(self) -> None:
         self.logger.log("[CHIPSEC] EC dump")
 
         buf = self._ec.read_range(0, self.size)
         print_buffer_bytes(buf)

 
-
-

-[docs]
-    def command(self) -> None:
+
[docs]    def command(self) -> None:
         self.logger.log(f'[CHIPSEC] Sending EC command 0x{self.cmd:X}')
 
         self._ec.write_command(self.cmd)

 
-
-

-[docs]
-    def read(self) -> None:
+
[docs]    def read(self) -> None:
         if self.size:
             buf = self._ec.read_range(self.offset, self.size)
             self.logger.log(f'[CHIPSEC] EC memory read: offset 0x{self.offset:X} size 0x{self.size:X}')
@@ -163,10 +146,7 @@ 
Source code for chipsec.utilcmd.ec_cmd
                 self.offset) if self.offset < 0x100 else self._ec.read_memory_extended(self.offset)
             self.logger.log(f'[CHIPSEC] EC memory read: offset 0x{self.start_offset:X} = 0x{val:X}')

 
-
-

-[docs]
-    def write(self) -> None:
+
[docs]    def write(self) -> None:
         self.logger.log(f'[CHIPSEC] EC memory write: offset 0x{self.offset:X} = 0x{self.wval:X}')
 
         if self.offset < 0x100:
@@ -174,10 +154,7 @@ 
Source code for chipsec.utilcmd.ec_cmd
         else:
             self._ec.write_memory_extended(self.offset, self.wval)

 
-
-

-[docs]
-    def index(self) -> None:
+
[docs]    def index(self) -> None:
 
         if self.offset:
             val = self._ec.read_idx(self.offset)
@@ -185,9 +162,7 @@ 
Source code for chipsec.utilcmd.ec_cmd
         else:
             self.logger.log("[CHIPSEC] EC index I/O: dumping memory...")
             mem = [self._ec.read_idx(off) for off in range(0x10000)]
-            print_buffer_bytes(mem)

-

-
+            print_buffer_bytes(mem)

 
 
 
@@ -251,7 +226,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -271,8 +246,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/igd_cmd.html b/_modules/chipsec/utilcmd/igd_cmd.html
index d2843694..8327681e 100644
--- a/_modules/chipsec/utilcmd/igd_cmd.html
+++ b/_modules/chipsec/utilcmd/igd_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.igd_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -80,19 +82,12 @@ 
Source code for chipsec.utilcmd.igd_cmd
 
 
 # Port I/O
-

-[docs]
-class IgdCommand(BaseCommand):
+
[docs]class IgdCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util igd', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -109,12 +104,9 @@ 
Source code for chipsec.utilcmd.igd_cmd
         parser_write.set_defaults(func=self.write_dma)
 
         parser.parse_args(self.argv, namespace=self)

-
         
 
-

-[docs]
-    def read_dma(self) -> None:
+
[docs]    def read_dma(self) -> None:
         self.logger.log(f'[CHIPSEC] Reading buffer from memory: PA = 0x{self.address:016X}, len = 0x{self.width:X}..')
         buffer = self.cs.igd.gfx_aperture_dma_read_write(self.address, self.width)
         if self.file_name:
@@ -123,10 +115,7 @@ 
Source code for chipsec.utilcmd.igd_cmd
         else:
             print_buffer_bytes(buffer)

 
-
-

-[docs]
-    def write_dma(self) -> None:
+
[docs]    def write_dma(self) -> None:
         if not os.path.exists(self.file_value):
             buffer_value = self.file_value.lower().strip('0x')
             try:
@@ -147,18 +136,13 @@ 
Source code for chipsec.utilcmd.igd_cmd
         self.logger.log(f'[CHIPSEC] Writing buffer to memory: PA = 0x{self.address:016X}, len = 0x{self.size:X}..')
         self.cs.igd.gfx_aperture_dma_read_write(self.address, self.size, buffer)

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
 
         if not self.cs.igd.is_device_enabled():
             self.logger.log('[CHIPSEC] Looks like internal graphics device is not enabled')
             return
 
-        self.func()

-

-
+        self.func()

 
 
 commands = {'igd': IgdCommand}
@@ -221,7 +205,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -241,8 +225,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/interrupts_cmd.html b/_modules/chipsec/utilcmd/interrupts_cmd.html
index 5e2dea5d..a4da125d 100644
--- a/_modules/chipsec/utilcmd/interrupts_cmd.html
+++ b/_modules/chipsec/utilcmd/interrupts_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.interrupts_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -95,10 +97,8 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
# ###################################################################
 
 
-

-[docs]
-class SMICommand(BaseCommand):
-    """
+
[docs]class SMICommand(BaseCommand):
+    """
     >>> chipsec_util smi count
     >>> chipsec_util smi send <thread_id> <SMI_code> <SMI_data> [RAX] [RBX] [RCX] [RDX] [RSI] [RDI]
     >>> chipsec_util smi smmc <RT_code_start> <RT_code_end> <GUID> <payload_loc> <payload_file|payload_string> [port]
@@ -111,15 +111,10 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
    >>> chipsec_util smi smmc 0x79dfe000 0x79efdfff ed32d533-99e6-4209-9cc02d72cdd998a7 0x79dfaaaa payload.bin
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util smi', usage=SMICommand.__doc__)
         subparsers = parser.add_subparsers()
 
@@ -149,19 +144,13 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def smi_count(self) -> None:
+
[docs]    def smi_count(self) -> None:
         self.logger.log("[CHIPSEC] SMI count:")
         for tid in range(self.cs.msr.get_cpu_thread_count()):
             smi_cnt = self.cs.read_register_field('MSR_SMI_COUNT', 'Count', cpu_thread=tid)
             self.logger.log(f'  CPU{tid:d}: {smi_cnt:d}')

 
-
-

-[docs]
-    def smi_smmc(self) -> None:
+
[docs]    def smi_smmc(self) -> None:
         if os.path.isfile(self.payload):
             with open(self.payload, 'rb') as f:
                 self.payload = f.read()
@@ -178,10 +167,7 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
# TODO Translate ReturnStatus to EFI_STATUS enum
         self.logger.log(f'ReturnStatus: 0x{ReturnStatus:x} ({EFI_ERROR_STR(ReturnStatus)})')

 
-
-

-[docs]
-    def smi_send(self) -> None:
+
[docs]    def smi_send(self) -> None:
         self.logger.log(f'[CHIPSEC] Sending SW SMI (code: 0x{self.SMI_code_port_value:02X}, data: 0x{self.SMI_data_port_value:02X})..')
         if self._rax is None:
             self.interrupts.send_SMI_APMC(self.SMI_code_port_value, self.SMI_data_port_value)
@@ -202,25 +188,18 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
self.logger.log(f'          RSI: {ret[5]:16X}')
                 self.logger.log(f'          RDI: {ret[6]:16X}')

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         try:
             self.interrupts = Interrupts(self.cs)
         except RuntimeError as msg:
             self.logger.log(msg)
             return
 
-        self.func()

-

-
+        self.func()

 
 
-

-[docs]
-class NMICommand(BaseCommand):
-    """
+
[docs]class NMICommand(BaseCommand):
+    """
     >>> chipsec_util nmi
 
     Examples:
@@ -228,21 +207,13 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
    >>> chipsec_util nmi
     """
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         return

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         try:
             interrupts = Interrupts(self.cs)
         except RuntimeError as msg:
@@ -250,9 +221,7 @@ 
Source code for chipsec.utilcmd.interrupts_cmd
return
 
         self.logger.log("[CHIPSEC] Sending NMI#...")
-        interrupts.send_NMI()

-

-
+        interrupts.send_NMI()

 
 
 commands = {'smi': SMICommand, 'nmi': NMICommand}
@@ -315,7 +284,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -335,8 +304,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/io_cmd.html b/_modules/chipsec/utilcmd/io_cmd.html
index a1b8ea24..8d42a982 100644
--- a/_modules/chipsec/utilcmd/io_cmd.html
+++ b/_modules/chipsec/utilcmd/io_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.io_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -80,19 +82,12 @@ 
Source code for chipsec.utilcmd.io_cmd
 from chipsec.exceptions import IOBARRuntimeError
 
 
-

-[docs]
-class PortIOCommand(BaseCommand):
+
[docs]class PortIOCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util io', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -115,22 +110,13 @@ 
Source code for chipsec.utilcmd.io_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._iobar = iobar.IOBAR(self.cs)

 
-
-

-[docs]
-    def io_list(self) -> None:
+
[docs]    def io_list(self) -> None:
         self._iobar.list_IO_BARs()

 
-
-

-[docs]
-    def io_read(self) -> None:
+
[docs]    def io_read(self) -> None:
         if 0x1 == self._width:
             value = self.cs.io.read_port_byte(self._port)
         elif 0x2 == self._width:
@@ -143,10 +129,7 @@ 
Source code for chipsec.utilcmd.io_cmd
         self.logger.log(f'[CHIPSEC] IN 0x{self._port:04X} -> 0x{value:08X} (size = 0x{self._width:02X})')
         return

 
-
-

-[docs]
-    def io_write(self) -> None:
+
[docs]    def io_write(self) -> None:
         if 0x1 == self._width:
             self.cs.io.write_port_byte(self._port, self._value)
         elif 0x2 == self._width:
@@ -158,9 +141,7 @@ 
Source code for chipsec.utilcmd.io_cmd
             return
         self.logger.log(
             f'[CHIPSEC] OUT 0x{self._port:04X} <- 0x{self._value:08X} (size = 0x{self._width:02X})')
-        return

-

-
+        return

 
 commands = {'io': PortIOCommand}
 

@@ -222,7 +203,7 @@ 
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-
+
         

       

       

@@ -242,8 +223,8 @@ 
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\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/iommu_cmd.html b/_modules/chipsec/utilcmd/iommu_cmd.html
index 974b305e..c283dcde 100644
--- a/_modules/chipsec/utilcmd/iommu_cmd.html
+++ b/_modules/chipsec/utilcmd/iommu_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.iommu_cmd — CHIPSEC  documentation
-    
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+    
+    
     
-    
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+    
+    
     
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@@ -83,19 +85,12 @@ 
Source code for chipsec.utilcmd.iommu_cmd
 
 
 # I/O Memory Management Unit (IOMMU), e.g. Intel VT-d
-

-[docs]
-class IOMMUCommand(BaseCommand):
+
[docs]class IOMMUCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util iommu', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -124,19 +119,13 @@ 
Source code for chipsec.utilcmd.iommu_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def iommu_list(self) -> None:
+
[docs]    def iommu_list(self) -> None:
         self.logger.log("[CHIPSEC] Enumerating supported IOMMU engine names:")
         self.logger.log(f'{list(iommu.IOMMU_ENGINES.keys())}')
         self.logger.log_important('\nNote: These are the IOMMU engine names supported by iommu_cmd.')
         self.logger.log_important('It does not mean they are supported/enabled in the current platform.')

 
-
-

-[docs]
-    def iommu_engine(self, cmd) -> None:
+
[docs]    def iommu_engine(self, cmd) -> None:
         try:
             _iommu = iommu.IOMMU(self.cs)
         except IOMMUError as msg:
@@ -177,43 +166,23 @@ 
Source code for chipsec.utilcmd.iommu_cmd
             elif (cmd == 'disable'):
                 _iommu.set_IOMMU_Translation(e, 0)

 
-
-

-[docs]
-    def iommu_config(self) -> None:
+
[docs]    def iommu_config(self) -> None:
         self.iommu_engine('config')

 
-
-

-[docs]
-    def iommu_status(self) -> None:
+
[docs]    def iommu_status(self) -> None:
         self.iommu_engine('status')

 
-
-

-[docs]
-    def iommu_enable(self) -> None:
+
[docs]    def iommu_enable(self) -> None:
         self.iommu_engine('enable')

 
-
-

-[docs]
-    def iommu_disable(self) -> None:
+
[docs]    def iommu_disable(self) -> None:
         self.iommu_engine('disable')

 
-
-

-[docs]
-    def iommu_pt(self) -> None:
+
[docs]    def iommu_pt(self) -> None:
         self.iommu_engine('pt')

 
-
-

-[docs]
-    def run(self) -> None:
-        self.func()

-

-
+
[docs]    def run(self) -> None:
+        self.func()

 
 
 commands = {'iommu': IOMMUCommand}
@@ -276,7 +245,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -296,8 +265,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/lock_check_cmd.html b/_modules/chipsec/utilcmd/lock_check_cmd.html
index 39e6141e..1238b2dc 100644
--- a/_modules/chipsec/utilcmd/lock_check_cmd.html
+++ b/_modules/chipsec/utilcmd/lock_check_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.lock_check_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -89,21 +91,14 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
from chipsec.defines import is_set
 
 
-

-[docs]
-class LOCKCHECKCommand(BaseCommand):
+
[docs]class LOCKCHECKCommand(BaseCommand):
 
     version = "0.5"
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util check', usage=LOCKCHECKCommand.__doc__)
 
         parser_lockname = ArgumentParser(add_help=False)
@@ -125,29 +120,20 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self.flip_consistency_checking = False
         if not self.cs.consistency_checking:
             self.flip_consistency_checking = True
             self.cs.consistency_checking = True
         self.logger.set_always_flush(True)
         self._locks = locks(self.cs)

-
     
-

-[docs]
-    def tear_down(self) -> None:
+
[docs]    def tear_down(self) -> None:
         self.logger.set_always_flush(False)
         if self.flip_consistency_checking:
             self.cs.consistency_checking = False

 
-
-

-[docs]
-    def log_key(self) -> None:
+
[docs]    def log_key(self) -> None:
         self.logger.log("""
 KEY:
 \tLock Name - Name of Lock within configuration file
@@ -159,29 +145,20 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
\t\tLocked - Lock matches value within configuration
 \t\tRW/O - Lock is identified as register is RW/O\n\n""")

 
-
-

-[docs]
-    def log_header(self) -> str:
-        ret = f'{"Lock Name":^27}|{"State":^16}|{"Consistent":^16}\n{"-" * 58}'
+
[docs]    def log_header(self) -> str:
+        ret = f'{"Lock Name":^27}|{"State":^16}|{"Consistent":^16}\n{"-" * 58}'
         if not self.logger.HAL:
             self.logger.log(ret)
         return f"\n\n{ret}"

 
-
-

-[docs]
-    def list_locks(self) -> None:
+
[docs]    def list_locks(self) -> None:
         self.logger.log('Locks identified within the configuration:')
         for lock in self._locks.get_locks():
             self.logger.log(lock)
         self.logger.log('')
         return

 
-
-

-[docs]
-    def checkall_locks(self) -> None:
+
[docs]    def checkall_locks(self) -> None:
         locks = self._locks.get_locks()
         if not locks:
             self.logger.log('Did not find any locks')
@@ -197,10 +174,7 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
self.logger.log(res)
         return

 
-
-

-[docs]
-    def check_lock(self) -> None:
+
[docs]    def check_lock(self) -> None:
         if self.logger.VERBOSE:
             self.log_key()
         res = self.log_header()
@@ -212,10 +186,7 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
self.logger.log(res)
         return

 
-
-

-[docs]
-    def check_log(self, lock: str, is_locked: int) -> str:
+
[docs]    def check_log(self, lock: str, is_locked: int) -> str:
         consistent = "N/A"
         if not is_set(is_locked, LockResult.DEFINED):
             res_str = 'Undefined'
@@ -238,9 +209,7 @@ 
Source code for chipsec.utilcmd.lock_check_cmd
res = f'{lock[:26]:27}|  {res_str:14}|{consistent:^16}'
         if not self.logger.HAL:
             self.logger.log(res)
-        return res

-

-
+        return res

 
 
 commands = {'check': LOCKCHECKCommand}
@@ -303,7 +272,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -323,8 +292,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/mem_cmd.html b/_modules/chipsec/utilcmd/mem_cmd.html
index 4b754f97..1fe70d43 100644
--- a/_modules/chipsec/utilcmd/mem_cmd.html
+++ b/_modules/chipsec/utilcmd/mem_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.mem_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
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@@ -93,19 +95,12 @@ 
Source code for chipsec.utilcmd.mem_cmd
 # Physical Memory
 
 
-

-[docs]
-class MemCommand(BaseCommand):
+
[docs]class MemCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util mem', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -149,10 +144,7 @@ 
Source code for chipsec.utilcmd.mem_cmd
         parser.parse_args(self.argv, namespace=self)

 
 
-
-

-[docs]
-    def dump_region_to_path(self, path: str, pa_start: int, pa_end: int) -> None:
+
[docs]    def dump_region_to_path(self, path: str, pa_start: int, pa_end: int) -> None:
         if pa_start >= pa_end:
             return
         head_len = pa_start & ALIGNED_4KB
@@ -172,37 +164,25 @@ 
Source code for chipsec.utilcmd.mem_cmd
             if (tail_len > 0):
                 f.write(self.cs.mem.read_physical_mem(end, tail_len))

 
-
-

-[docs]
-    def mem_allocate(self) -> None:
+
[docs]    def mem_allocate(self) -> None:
         (va, pa) = self.cs.mem.alloc_physical_mem(self.allocate_length)
         self.logger.log(f'[CHIPSEC] Allocated {self.allocate_length:X} bytes of physical memory: VA = 0x{va:016X}, PA = 0x{pa:016X}')

 
-
-

@@ -341,7 +310,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -361,8 +330,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/mmcfg_base_cmd.html b/_modules/chipsec/utilcmd/mmcfg_base_cmd.html
index e05e807f..c36bcaf1 100644
--- a/_modules/chipsec/utilcmd/mmcfg_base_cmd.html
+++ b/_modules/chipsec/utilcmd/mmcfg_base_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.mmcfg_base_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,32 +77,20 @@ 
Source code for chipsec.utilcmd.mmcfg_base_cmd
# Access to Memory Mapped PCIe Configuration Space (MMCFG)
-

-[docs]
-class MMCfgBaseCommand(BaseCommand):
+
[docs]class MMCfgBaseCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         return

 
-
-

-[docs]
-    def run(self) -> None:
+
[docs]    def run(self) -> None:
         _mmio = mmio.MMIO(self.cs)
         pciexbar, pciexbar_sz = _mmio.get_MMCFG_base_address()
         self.logger.log(f'[CHIPSEC] Memory Mapped Config Base: 0x{pciexbar:016X}')
         self.logger.log(f'[CHIPSEC] Memory Mapped Config Size: 0x{pciexbar_sz:016X}')
-        self.logger.log('')

-

-
+        self.logger.log('')

 
 
 commands = {'mmcfg_base': MMCfgBaseCommand}
@@ -163,7 +153,7 @@ 
Quick search

     
     

 

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+
         

       

       

@@ -183,8 +173,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/mmcfg_cmd.html b/_modules/chipsec/utilcmd/mmcfg_cmd.html
index 4f8120f5..0523f76b 100644
--- a/_modules/chipsec/utilcmd/mmcfg_cmd.html
+++ b/_modules/chipsec/utilcmd/mmcfg_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.mmcfg_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -61,75 +63,84 @@ 
Source code for chipsec.utilcmd.mmcfg_cmd
 """
 The mmcfg command allows direct access to memory mapped config space.
 
->>> chipsec_util mmcfg <bus> <device> <function> <offset> <width> [value]
+>>> chipsec_util mmcfg base
+>>> chipsec_util mmcfg read <bus> <device> <function> <offset> <width>
+>>> chipsec_util mmcfg write <bus> <device> <function> <offset> <width> <value>
+>>> chipsec_util mmcfg ec
+
 
 Examples:
 
->>> chipsec_util mmcfg 0 0 0 0x88 4
->>> chipsec_util mmcfg 0 0 0 0x88 byte 0x1A
->>> chipsec_util mmcfg 0 0x1F 0 0xDC 1 0x1
->>> chipsec_util mmcfg 0 0 0 0x98 dword 0x004E0040
+>>> chipsec_util mmcfg base
+>>> chipsec_util mmcfg read 0 0 0 0x200 4
+>>> chipsec_util mmcfg write 0 0 0 0x200 1 0x1A
+>>> chipsec_util mmcfg ec
 """
 
 from chipsec.command import BaseCommand, toLoad
-from chipsec.hal import mmio
 from argparse import ArgumentParser
 
 
 # Access to Memory Mapped PCIe Configuration Space (MMCFG)
-

-[docs]
-class MMCfgCommand(BaseCommand):
+
[docs]class MMCfgCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util mmcfg', usage=__doc__)
-        parser.add_argument('bus', type=lambda x: int(x, 16), help='Bus (hex)')
-        parser.add_argument('device', type=lambda x: int(x, 16), help='Device (hex)')
-        parser.add_argument('function', type=lambda x: int(x, 16), help='Function (hex)')
-        parser.add_argument('offset', type=lambda x: int(x, 16), help='Offset (hex)')
-        parser.add_argument('width', type=str, choices=['byte', 'word', 'dword', '1', '2', '4'], help='Width [byte,word,dword] or (int)')
-        parser.add_argument('value', type=lambda x: int(x, 16), nargs='?', default=None, help='Value to write (hex)')
-        parser.set_defaults()
+        subparsers = parser.add_subparsers()
+
+        parser_base = subparsers.add_parser('base')
+        parser_base.set_defaults(func=self.base)
+
+        parser_read = subparsers.add_parser('read')
+        parser_read.set_defaults(func=self.read)
+        parser_read.add_argument('bus', type=lambda x: int(x, 16), help='Bus (hex)')
+        parser_read.add_argument('device', type=lambda x: int(x, 16), help='Device (hex)')
+        parser_read.add_argument('function', type=lambda x: int(x, 16), help='Function (hex)')
+        parser_read.add_argument('offset', type=lambda x: int(x, 16), help='Offset (hex)')
+        parser_read.add_argument('width', type=int, choices=[1, 2, 4], help='Width')
+
+        parser_write = subparsers.add_parser('write')
+        parser_write.set_defaults(func=self.write)
+        parser_write.add_argument('bus', type=lambda x: int(x, 16), help='Bus (hex)')
+        parser_write.add_argument('device', type=lambda x: int(x, 16), help='Device (hex)')
+        parser_write.add_argument('function', type=lambda x: int(x, 16), help='Function (hex)')
+        parser_write.add_argument('offset', type=lambda x: int(x, 16), help='Offset (hex)')
+        parser_write.add_argument('width', type=int, choices=[1, 2, 4], help='Width')
+        parser_write.add_argument('value', type=lambda x: int(x, 16), help='Value to write (hex)')
+
+        # Print the pcie extended capabilities
+        parser_ec = subparsers.add_parser('ec')
+        parser_ec.set_defaults(func=self.ec)
 
         parser.parse_args(self.argv, namespace=self)

 
+
[docs]    def base(self):
+        pciexbar, pciexbar_sz = self.cs.mmio.get_MMCFG_base_address()
+        self.logger.log(f'[CHIPSEC] Memory Mapped Config Base: 0x{pciexbar:016X}')
+        self.logger.log(f'[CHIPSEC] Memory Mapped Config Size: 0x{pciexbar_sz:016X}')

 
-

-[docs]
-    def run(self) -> None:
-        _mmio = mmio.MMIO(self.cs)
-
-        try:
-            if self.width == 'byte':
-                _width = 1
-            elif self.width == 'word':
-                _width = 2
-            elif self.width == 'dword':
-                _width = 4
-            else:
-                _width = int(self.width)
-        except ValueError:
-            self.logger.log_error("ValueError: Invalid inputs.")
-            return
-
-        if self.value is not None:
-            _mmio.write_mmcfg_reg(self.bus, self.device, self.function, self.offset, _width, self.value)
-            self.logger.log(f'[CHIPSEC] Writing MMCFG register ({self.bus:02d}:{self.device:02d}.{self.function:d} + 0x{self.offset:02X}): 0x{self.value:X}')
-        else:
-            data = _mmio.read_mmcfg_reg(self.bus, self.device, self.function, self.offset, _width)
-            self.logger.log(f'[CHIPSEC] Reading MMCFG register ({self.bus:02d}:{self.device:02d}.{self.function:d} + 0x{self.offset:02X}): 0x{data:X}')
-
-        self.logger.log('')

-

+
[docs]    def read(self):
+        data = self.cs.mmio.read_mmcfg_reg(self.bus, self.device, self.function, self.offset, self.width)
+        self.logger.log(f'[CHIPSEC] Reading MMCFG register ({self.bus:02d}:{self.device:02d}.{self.function:d} + 0x{self.offset:02X}): 0x{data:X}')

+
+
[docs]    def write(self):
+        self.cs.mmio.write_mmcfg_reg(self.bus, self.device, self.function, self.offset, self.width, self.value)
+        self.logger.log(f'[CHIPSEC] Writing MMCFG register ({self.bus:02d}:{self.device:02d}.{self.function:d} + 0x{self.offset:02X}): 0x{self.value:X}')

 
+
[docs]    def ec(self):
+        devs = self.cs.pci.enumerate_devices()
+        for (b, d, f, _, _, _) in devs:
+            capabilities = self.cs.mmio.get_extended_capabilities(b, d, f)
+            if capabilities:
+                self.logger.log(f'Extended Capabilities for {b:02X}:{d:02X}.{f:X}:')
+                for cap in capabilities:
+                    self.logger.log(f'{cap}')
+                    if cap.id == 0xB:
+                        vsec = self.cs.mmio.get_vsec(b, d, f, cap.off)
+                        self.logger.log(f'\t{vsec}')

 
 
 commands = {'mmcfg': MMCfgCommand}
@@ -192,7 +203,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -212,8 +223,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/mmio_cmd.html b/_modules/chipsec/utilcmd/mmio_cmd.html
index 0f1da911..fbf34013 100644
--- a/_modules/chipsec/utilcmd/mmio_cmd.html
+++ b/_modules/chipsec/utilcmd/mmio_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.mmio_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -87,19 +89,12 @@ 
Source code for chipsec.utilcmd.mmio_cmd
 # Access to Memory Mapped PCIe Configuration Space (MMCFG)
 #
 # ###################################################################
-

-[docs]
-class MMIOCommand(BaseCommand):
+
[docs]class MMIOCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util mmio', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -156,22 +151,13 @@ 
Source code for chipsec.utilcmd.mmio_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._mmio = mmio.MMIO(self.cs)

 
-
-

-[docs]
-    def list_bars(self):
+
[docs]    def list_bars(self):
         self._mmio.list_MMIO_BARs()

 
-
-

-[docs]
-    def dump_bar(self):
+
[docs]    def dump_bar(self):
         self.logger.log("[CHIPSEC] Dumping {} MMIO space..".format(self.bar_name.upper()))
         (bar_base, bar_size) = self._mmio.get_MMIO_BAR_base_address(self.bar_name.upper())
         if self.length is not None:
@@ -181,10 +167,7 @@ 
Source code for chipsec.utilcmd.mmio_cmd
         bar_base += self.offset
         self._mmio.dump_MMIO(bar_base, bar_size)

 
-
-

-[docs]
-    def dump_bar_abs(self):
+
[docs]    def dump_bar_abs(self):
         tmp_base = self.base + self.offset
         if self.length is None:
             tmp_length = 0x1000
@@ -193,18 +176,12 @@ 
Source code for chipsec.utilcmd.mmio_cmd
         self.logger.log("[CHIPSEC] Dumping MMIO space 0x{:08X} to 0x{:08X}".format(tmp_base, tmp_base + tmp_length))
         self._mmio.dump_MMIO(tmp_base, tmp_length)

 
-
-

-[docs]
-    def read_bar(self):
+
[docs]    def read_bar(self):
         bar = self.bar_name.upper()
         reg = self._mmio.read_MMIO_BAR_reg(bar, self.offset, self.width, self.bus)
         self.logger.log("[CHIPSEC] Read {} + 0x{:X}: 0x{:08X}".format(bar, self.offset, reg))

 
-
-

-[docs]
-    def read_abs(self):
+
[docs]    def read_abs(self):
         if self.width == 1:
             reg = self._mmio.read_MMIO_reg_byte(self.base, self.offset)
         elif self.width == 2:
@@ -216,18 +193,12 @@ 
Source code for chipsec.utilcmd.mmio_cmd
             reg |= self._mmio.read_MMIO_reg_dword(self.base, self.offset + 4) << 32
         self.logger.log("[CHIPSEC] Read 0x{:X} + 0x{:X}: 0x{:08X}".format(self.base, self.offset, reg))

 
-
-

-[docs]
-    def write_bar(self):
+
[docs]    def write_bar(self):
         bar = self.bar_name.upper()
         self.logger.log("[CHIPSEC] Write {} + 0x{:X}: 0x{:08X}".format(bar, self.offset, self.value))
         self._mmio.write_MMIO_BAR_reg(bar, self.offset, self.value, self.width, self.bus)

 
-
-

-[docs]
-    def write_abs(self):
+
[docs]    def write_abs(self):
         self.logger.log("[CHIPSEC] Write 0x{:X} + 0x{:X}: 0x{:08X}".format(self.base, self.offset, self.value))
         if self.width == 1:
             self._mmio.write_MMIO_reg_byte(self.base, self.offset, self.value & 0xFF)
@@ -237,9 +208,7 @@ 
Source code for chipsec.utilcmd.mmio_cmd
             self._mmio.write_MMIO_reg_dword(self.base, self.offset, self.value & 0xFFFFFFFF)
         elif self.width == 8:
             self._mmio.write_MMIO_reg_dword(self.base, self.offset, self.value & 0xFFFFFFFF)
-            self._mmio.write_MMIO_reg_dword(self.base, self.offset + 4, (self.value >> 32) & 0xFFFFFFFF)

-

-
+            self._mmio.write_MMIO_reg_dword(self.base, self.offset + 4, (self.value >> 32) & 0xFFFFFFFF)

 
 
 
@@ -303,7 +272,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -323,8 +292,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/msgbus_cmd.html b/_modules/chipsec/utilcmd/msgbus_cmd.html
index c32f2d93..372e43e5 100644
--- a/_modules/chipsec/utilcmd/msgbus_cmd.html
+++ b/_modules/chipsec/utilcmd/msgbus_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.msgbus_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -82,19 +84,12 @@ 
Source code for chipsec.utilcmd.msgbus_cmd
 
 
 # Message Bus
-

-[docs]
-class MsgBusCommand(BaseCommand):
+
[docs]class MsgBusCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util msgbus', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -129,55 +124,35 @@ 
Source code for chipsec.utilcmd.msgbus_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def msgbus_read(self):
+
[docs]    def msgbus_read(self):
         self.logger.log("[CHIPSEC] msgbus read: port 0x{:02X} + 0x{:08X}".format(self.port, self.reg))
         return self._msgbus.msgbus_reg_read(self.port, self.reg)

 
-
-

-[docs]
-    def msgbus_write(self):
+
[docs]    def msgbus_write(self):
         self.logger.log("[CHIPSEC] msgbus write: port 0x{:02X} + 0x{:08X} < 0x{:08X}".format(self.port, self.reg, self.val))
         return self._msgbus.msgbus_reg_write(self.port, self.reg, self.val)

 
-
-

-[docs]
-    def msgbus_mm_read(self):
+
[docs]    def msgbus_mm_read(self):
         self.logger.log("[CHIPSEC] MMIO msgbus read: port 0x{:02X} + 0x{:08X}".format(self.port, self.reg))
         return self._msgbus.mm_msgbus_reg_read(self.port, self.reg)

 
-
-

-[docs]
-    def msgbus_mm_write(self):
+
[docs]    def msgbus_mm_write(self):
         self.logger.log("[CHIPSEC] MMIO msgbus write: port 0x{:02X} + 0x{:08X} < 0x{:08X}".format(self.port, self.reg, self.val))
         return self._msgbus.mm_msgbus_reg_write(self.port, self.reg, self.val)

 
-
-

-[docs]
-    def msgbus_message(self):
+
[docs]    def msgbus_message(self):
         self.logger.log("[CHIPSEC] msgbus message: port 0x{:02X} + 0x{:08X}, opcode: 0x{:02X}".format(self.port, self.reg, self.opcode))
         if self.val is not None:
             self.logger.log("[CHIPSEC]                 Data: 0x{:08X}".format(self.val))
         return self._msgbus.msgbus_send_message(self.port, self.reg, self.opcode, self.val)

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         self._msgbus = self.cs.msgbus
 
         res = self.func()
 
         if res is not None:
-            self.logger.log("[CHIPSEC] Result: 0x{:08X}".format(res))

-

-
+            self.logger.log("[CHIPSEC] Result: 0x{:08X}".format(res))

 
 
 commands = {'msgbus': MsgBusCommand}
@@ -240,7 +215,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -260,8 +235,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/msr_cmd.html b/_modules/chipsec/utilcmd/msr_cmd.html
index 48138244..227268dc 100644
--- a/_modules/chipsec/utilcmd/msr_cmd.html
+++ b/_modules/chipsec/utilcmd/msr_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.msr_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -75,19 +77,12 @@ 
Source code for chipsec.utilcmd.msr_cmd
 
 
 # CPU Model Specific Registers
-

-[docs]
-class MSRCommand(BaseCommand):
+
[docs]class MSRCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util msr', usage=__doc__)
         parser.add_argument('msr_addr', type=lambda x: int(x, 0), metavar='<msr>', help='MSR address')
         parser.add_argument('msr_input1', type=lambda x: int(x, 0), metavar='MSR Value', nargs='?', default=None, help='EAX (Low)')
@@ -95,10 +90,7 @@ 
Source code for chipsec.utilcmd.msr_cmd
         parser.add_argument('thread_id', type=lambda x: int(x, 0), metavar='Thread ID', nargs='?', default=None, help='Thread ID')
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         if self.msr_input1 is None:
             for tid in range(self.cs.msr.get_cpu_thread_count()):
                 (eax, edx) = self.cs.msr.read_msr(tid, self.msr_addr)
@@ -120,9 +112,7 @@ 
Source code for chipsec.utilcmd.msr_cmd
             else:
                 cpu_thread_id = self.thread_id
                 self.logger.log("[CHIPSEC] CPU{:d}: WRMSR( 0x{:x} ) = {:016X}".format(cpu_thread_id, self.msr_addr, val64))
-                self.cs.msr.write_msr(cpu_thread_id, self.msr_addr, eax, edx)

-

-
+                self.cs.msr.write_msr(cpu_thread_id, self.msr_addr, eax, edx)

 
 
 commands = {'msr': MSRCommand}
@@ -185,7 +175,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -205,8 +195,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/pci_cmd.html b/_modules/chipsec/utilcmd/pci_cmd.html
index d9a27328..bc7c5358 100644
--- a/_modules/chipsec/utilcmd/pci_cmd.html
+++ b/_modules/chipsec/utilcmd/pci_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.pci_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -93,19 +95,12 @@ 
Source code for chipsec.utilcmd.pci_cmd
 # PCIe Devices and Configuration Registers
 
 
-

-[docs]
-class PCICommand(BaseCommand):
+
[docs]class PCICommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util pci', usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_enumerate = subparsers.add_parser('enumerate')
@@ -149,17 +144,11 @@ 
Source code for chipsec.utilcmd.pci_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def pci_enumerate(self):
+
[docs]    def pci_enumerate(self):
         self.logger.log("[CHIPSEC] Enumerating available PCIe devices...")
         print_pci_devices(self.cs.pci.enumerate_devices())

 
-
-

-[docs]
-    def pci_dump(self):
+
[docs]    def pci_dump(self):
         if self.bus is not None:
             if self.device is not None and self.function is not None:
                 devices = [(self.bus, self.device, self.function, 0x0000, 0x0000, 0x0000)]
@@ -174,10 +163,7 @@ 
Source code for chipsec.utilcmd.pci_cmd
             self.logger.log("[CHIPSEC] Dumping configuration of available PCI devices...")
             self.cs.pci.print_pci_config_all()

 
-
-

-[docs]
-    def pci_xrom(self):
+
[docs]    def pci_xrom(self):
         if self.bus is not None:
             if self.device is not None and self.function is not None:
                 devices = [(self.bus, self.device, self.function, 0x0000, 0x0000, 0x000)]
@@ -202,10 +188,7 @@ 
Source code for chipsec.utilcmd.pci_cmd
             if len(_xroms) > 0:
                 print_pci_XROMs(_xroms)

 
-
-

-[docs]
-    def pci_read(self):
+
[docs]    def pci_read(self):
         width = 4
         if self.size is not None:
             width = get_option_width(self.size) if is_option_valid_width(self.size) else int(self.size, 16)
@@ -221,10 +204,7 @@ 
Source code for chipsec.utilcmd.pci_cmd
             return
         self.logger.log("[CHIPSEC] PCI {:02X}:{:02X}.{:02X} + 0x{:02X}: 0x{:X}".format(self.bus, self.device, self.function, self.offset, pci_value))

 
-
-

-[docs]
-    def pci_write(self):
+
[docs]    def pci_write(self):
         width = get_option_width(self.size) if is_option_valid_width(self.size) else int(self.size, 16)
 
         if 1 == width:
@@ -238,10 +218,7 @@ 
Source code for chipsec.utilcmd.pci_cmd
             return
         self.logger.log("[CHIPSEC] Write 0x{:X} to PCI {:02X}:{:02X}.{:02X} + 0x{:02X}".format(self.value, self.bus, self.device, self.function, self.offset))

 
-
-

-[docs]
-    def pci_cmd(self):
+
[docs]    def pci_cmd(self):
         self.logger.log('BDF     | VID:DID   | CMD  | CLS | Sub CLS')
         self.logger.log('------------------------------------------')
         for (b, d, f, vid, did, rid) in self.cs.pci.enumerate_devices():
@@ -254,9 +231,7 @@ 
Source code for chipsec.utilcmd.pci_cmd
             cmd_reg = self.cs.pci.read_word(b, d, f, PCI_HDR_CMD_OFF)
             if (cmd_reg & self.cmd_mask) == 0:
                 continue
-            self.logger.log('{:02X}:{:02X}.{:X} | {:04X}:{:04X} | {:04X} | {:02X}  | {:02X}'.format(b, d, f, vid, did, cmd_reg, dev_cls, dev_sub_cls))

-

-
+            self.logger.log('{:02X}:{:02X}.{:X} | {:04X}:{:04X} | {:04X} | {:02X}  | {:02X}'.format(b, d, f, vid, did, cmd_reg, dev_cls, dev_sub_cls))

 
 
 commands = {'pci': PCICommand}
@@ -319,7 +294,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -339,8 +314,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/reg_cmd.html b/_modules/chipsec/utilcmd/reg_cmd.html
index a3109058..efc250f2 100644
--- a/_modules/chipsec/utilcmd/reg_cmd.html
+++ b/_modules/chipsec/utilcmd/reg_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.reg_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -78,19 +80,12 @@ 
Source code for chipsec.utilcmd.reg_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class RegisterCommand(BaseCommand):
+
[docs]class RegisterCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util reg', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -126,10 +121,7 @@ 
Source code for chipsec.utilcmd.reg_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def reg_read(self):
+
[docs]    def reg_read(self):
         if self.field_name is not None:
             value = self.cs.read_register_field(self.reg_name, self.field_name)
             self.logger.log("[CHIPSEC] {}.{}=0x{:X}".format(self.reg_name, self.field_name, value))
@@ -138,54 +130,37 @@ 
Source code for chipsec.utilcmd.reg_cmd
             self.logger.log("[CHIPSEC] {}=0x{:X}".format(self.reg_name, value))
             self.cs.print_register(self.reg_name, value)

 
-
-

-[docs]
-    def reg_read_field(self):
+
[docs]    def reg_read_field(self):
         if self.cs.register_has_field(self.reg_name, self.field_name):
             value = self.cs.read_register_field(self.reg_name, self.field_name)
             self.logger.log("[CHIPSEC] {}.{}=0x{:X}".format(self.reg_name, self.field_name, value))
         else:
             self.logger.log_error("[CHIPSEC] Register '{}' doesn't have field '{}' defined".format(self.reg_name, self.field_name))

 
-
-

-[docs]
-    def reg_write(self):
+
[docs]    def reg_write(self):
         self.logger.log("[CHIPSEC] Writing {} < 0x{:X}".format(self.reg_name, self.value))
         self.cs.write_register(self.reg_name, self.value)

 
-
-

-[docs]
-    def reg_write_field(self):
+
[docs]    def reg_write_field(self):
         if self.cs.register_has_field(self.reg_name, self.field_name):
             self.logger.log("[CHIPSEC] Writing {}.{} < 0x{:X}".format(self.reg_name, self.field_name, self.value))
             self.cs.write_register_field(self.reg_name, self.field_name, self.value)
         else:
             self.logger.log_error("[CHIPSEC] Register '{}' doesn't have field '{}' defined".format(self.reg_name, self.field_name))

 
-
-

-[docs]
-    def reg_get_control(self):
+
[docs]    def reg_get_control(self):
         if self.cs.is_control_defined(self.control_name):
             value = self.cs.get_control(self.control_name)
             self.logger.log("[CHIPSEC] {} = 0x{:X}".format(self.control_name, value))
         else:
             self.logger.log_error("[CHIPSEC] Control '{}' isn't defined".format(self.control_name))

 
-
-

-[docs]
-    def reg_set_control(self):
+
[docs]    def reg_set_control(self):
         if self.cs.is_control_defined(self.control_name):
             self.cs.set_control(self.control_name, self.value)
             self.logger.log("[CHIPSEC] Setting control {} < 0x{:X}".format(self.control_name, self.value))
         else:
-            self.logger.log_error("[CHIPSEC] Control '{}' isn't defined".format(self.control_name))

-

-
+            self.logger.log_error("[CHIPSEC] Control '{}' isn't defined".format(self.control_name))

 
 commands = {'reg': RegisterCommand}
 

@@ -247,7 +222,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -267,8 +242,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/smbios_cmd.html b/_modules/chipsec/utilcmd/smbios_cmd.html
index 666d4518..bb73a86d 100644
--- a/_modules/chipsec/utilcmd/smbios_cmd.html
+++ b/_modules/chipsec/utilcmd/smbios_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.smbios_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -73,19 +75,12 @@ 
Source code for chipsec.utilcmd.smbios_cmd
 from chipsec.logger import print_buffer_bytes
 from chipsec.options import Options
 
-

-[docs]
-class smbios_cmd(BaseCommand):
+
[docs]class smbios_cmd(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         options = Options()
         try:
             default_type = options.get_section_data('Util_Config', 'smbios_get_type')
@@ -106,20 +101,14 @@ 
Source code for chipsec.utilcmd.smbios_cmd
         parser_get.set_defaults(func=self.smbios_get)
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def smbios_ep(self):
+
[docs]    def smbios_ep(self):
         self.logger.log('[CHIPSEC] SMBIOS Entry Point Structures')
         if self.smbios.smbios_2_pa is not None:
             self.logger.log(self.smbios.smbios_2_ep)
         if self.smbios.smbios_3_pa is not None:
             self.logger.log(self.smbios.smbios_3_ep)

 
-
-

-[docs]
-    def smbios_get(self):
+
[docs]    def smbios_get(self):
         if self.method == 'raw':
             self.logger.log('[CHIPSEC] Dumping all requested structures in raw format')
             structs = self.smbios.get_raw_structs(self.type, self._force_32)
@@ -144,10 +133,7 @@ 
Source code for chipsec.utilcmd.smbios_cmd
                 self.logger.log(data)
             self.logger.log('==================================================================')

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         # Create and initialize SMBIOS object for commands to use
         try:
             self.logger.log('[CHIPSEC] Attempting to detect SMBIOS structures')
@@ -160,9 +146,7 @@ 
Source code for chipsec.utilcmd.smbios_cmd
             self.logger.log(e)
             return
 
-        self.func()

-

-
+        self.func()

 
 
 commands = {'smbios': smbios_cmd}
@@ -225,7 +209,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -245,8 +229,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/smbus_cmd.html b/_modules/chipsec/utilcmd/smbus_cmd.html
index 8f4a7fa4..2012435c 100644
--- a/_modules/chipsec/utilcmd/smbus_cmd.html
+++ b/_modules/chipsec/utilcmd/smbus_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.smbus_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -72,19 +74,12 @@ 
Source code for chipsec.utilcmd.smbus_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class SMBusCommand(BaseCommand):
+
[docs]class SMBusCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util smbus', usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_read = subparsers.add_parser('read')
@@ -101,16 +96,10 @@ 
Source code for chipsec.utilcmd.smbus_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._smbus = SMBus(self.cs)

 
-
-

-[docs]
-    def smbus_read(self):
+
[docs]    def smbus_read(self):
         if self.size is not None:
             buf = self._smbus.read_range(self.dev_addr, self.start_off, self.size)
             self.logger.log("[CHIPSEC] SMBus read: device 0x{:X} offset 0x{:X} size 0x{:X}".format(self.dev_addr, self.start_off, self.size))
@@ -119,24 +108,16 @@ 
Source code for chipsec.utilcmd.smbus_cmd
             val = self._smbus.read_byte(self.dev_addr, self.start_off)
             self.logger.log("[CHIPSEC] SMBus read: device 0x{:X} offset 0x{:X} = 0x{:X}".format(self.dev_addr, self.start_off, val))

 
-
-

-[docs]
-    def smbus_write(self):
+
[docs]    def smbus_write(self):
         self.logger.log("[CHIPSEC] SMBus write: device 0x{:X} offset 0x{:X} = 0x{:X}".format(self.dev_addr, self.off, self.val))
         self._smbus.write_byte(self.dev_addr, self.off, self.val)

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         if not self._smbus.is_SMBus_supported():
             self.logger.log("[CHIPSEC] SMBus controller is not supported")
             return
         self._smbus.display_SMBus_info()
-        self.func()

-

-
+        self.func()

 
 
 commands = {'smbus': SMBusCommand}
@@ -199,7 +180,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -219,8 +200,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/spd_cmd.html b/_modules/chipsec/utilcmd/spd_cmd.html
index 736fb224..f91dcadb 100644
--- a/_modules/chipsec/utilcmd/spd_cmd.html
+++ b/_modules/chipsec/utilcmd/spd_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.spd_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -78,19 +80,12 @@ 
Source code for chipsec.utilcmd.spd_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class SPDCommand(BaseCommand):
+
[docs]class SPDCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -114,10 +109,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def spd_detect(self):
+
[docs]    def spd_detect(self):
         self.logger.log("[CHIPSEC] Searching for DIMMs with SPD...")
         _dimms = self._spd.detect()
         if _dimms is not None:
@@ -127,10 +119,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
         else:
             self.logger.log("Unable to detect SPD devices.")

 
-
-

-[docs]
-    def spd_dump(self):
+
[docs]    def spd_dump(self):
         if self.dev is not None:
             _dev = self.dev.upper()
             self.dev_addr = spd.SPD_DIMM_ADDRESSES[_dev] if _dev in spd.SPD_DIMM_ADDRESSES else int(self.dev, 16)
@@ -143,10 +132,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
             for _dimm in _dimms:
                 self._spd.decode(_dimm)

 
-
-

-[docs]
-    def spd_read(self):
+
[docs]    def spd_read(self):
         _dev = self.dev.upper()
         self.dev_addr = spd.SPD_DIMM_ADDRESSES[_dev] if _dev in spd.SPD_DIMM_ADDRESSES else int(self.dev, 16)
         if not self._spd.isSPDPresent(self.dev_addr):
@@ -156,10 +142,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
         val = self._spd.read_byte(self.off, self.dev_addr)
         self.logger.log("[CHIPSEC] SPD read: offset 0x{:X} = 0x{:X}".format(self.off, val))

 
-
-

-[docs]
-    def spd_write(self):
+
[docs]    def spd_write(self):
         _dev = self.dev.upper()
         self.dev_addr = spd.SPD_DIMM_ADDRESSES[_dev] if _dev in spd.SPD_DIMM_ADDRESSES else int(self.dev, 16)
         if not self._spd.isSPDPresent(self.dev_addr):
@@ -169,10 +152,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
         self.logger.log("[CHIPSEC] SPD write: offset 0x{:X} = 0x{:X}".format(self.off, self.val))
         self._spd.write_byte(self.off, self.val, self.dev_addr)

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         try:
             _smbus = smbus.SMBus(self.cs)
             self._spd = spd.SPD(_smbus)
@@ -183,9 +163,7 @@ 
Source code for chipsec.utilcmd.spd_cmd
             self.logger.log("[CHIPSEC] SMBus controller is not supported")
             return
         self.dev_addr = spd.SPD_SMBUS_ADDRESS
-        self.func()

-

-
+        self.func()

 
 
 commands = {'spd': SPDCommand}
@@ -248,7 +226,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -268,8 +246,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/spi_cmd.html b/_modules/chipsec/utilcmd/spi_cmd.html
index eea2f1ab..24285132 100644
--- a/_modules/chipsec/utilcmd/spi_cmd.html
+++ b/_modules/chipsec/utilcmd/spi_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.spi_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -91,19 +93,12 @@ 
Source code for chipsec.utilcmd.spi_cmd
 
 
 # SPI Flash Controller
-

-[docs]
-class SPICommand(BaseCommand):
+
[docs]class SPICommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util spi', usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_info = subparsers.add_parser('info')
@@ -140,24 +135,15 @@ 
Source code for chipsec.utilcmd.spi_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._spi = SPI(self.cs)
         self._msg = "it may take a few minutes (use DEBUG or VERBOSE logger options to see progress)"

 
-
-

-[docs]
-    def spi_info(self):
+
[docs]    def spi_info(self):
         self.logger.log("[CHIPSEC] SPI flash memory information\n")
         self._spi.display_SPI_map()

 
-
-

-[docs]
-    def spi_dump(self):
+
[docs]    def spi_dump(self):
         self.logger.log("[CHIPSEC] Dumping entire SPI flash memory to '{}'".format(self.out_file))
         self.logger.log("[CHIPSEC] {}".format(self._msg))
         # @TODO: don't assume SPI Flash always ends with BIOS region
@@ -171,10 +157,7 @@ 
Source code for chipsec.utilcmd.spi_cmd
         else:
             self.logger.log("[CHIPSEC] Completed SPI flash dump to '{}'".format(self.out_file))

 
-
-

-[docs]
-    def spi_read(self):
+
[docs]    def spi_read(self):
         self.logger.log("[CHIPSEC] Reading 0x{:x} bytes from SPI Flash starting at FLA = 0x{:X}".format(self.length, self.spi_fla))
         self.logger.log("[CHIPSEC] {}".format(self._msg))
         buf = self._spi.read_spi_to_file(self.spi_fla, self.length, self.out_file)
@@ -183,10 +166,7 @@ 
Source code for chipsec.utilcmd.spi_cmd
         else:
             self.logger.log("[CHIPSEC] Completed SPI flash memory read")

 
-
-

-[docs]
-    def spi_write(self):
+
[docs]    def spi_write(self):
         if not os.path.exists(self.filename):
             self.logger.log_error("File '{}' doesn't exist".format(self.filename))
             return
@@ -197,10 +177,7 @@ 
Source code for chipsec.utilcmd.spi_cmd
         else:
             self.logger.log_warning("SPI flash write returned error (turn on VERBOSE)")

 
-
-

-[docs]
-    def spi_erase(self):
+
[docs]    def spi_erase(self):
         self.logger.log("[CHIPSEC] Erasing SPI flash memory block at FLA = 0x{:X}".format(self.spi_fla))
 
         if self._spi.erase_spi_block(self.spi_fla):
@@ -208,10 +185,7 @@ 
Source code for chipsec.utilcmd.spi_cmd
         else:
             self.logger.log_warning("SPI flash erase returned error (turn on VERBOSE)")

 
-
-

-[docs]
-    def spi_disable_wp(self):
+
[docs]    def spi_disable_wp(self):
         self.logger.log("[CHIPSEC] Trying to disable BIOS write protection..")
         #
         # This write protection only matters for BIOS range in SPI flash memory
@@ -221,16 +195,10 @@ 
Source code for chipsec.utilcmd.spi_cmd
         else:
             self.logger.log_bad("Couldn't disable BIOS region write protection in SPI flash")

 
-
-

-[docs]
-    def spi_sfdp(self):
+
[docs]    def spi_sfdp(self):
         self._spi.get_SPI_SFDP()

 
-
-

-[docs]
-    def spi_jedec(self):
+
[docs]    def spi_jedec(self):
         if self.option.lower() == 'decode':
             (jedec, man, part) = self._spi.get_SPI_JEDEC_ID_decoded()
             if jedec is not False:
@@ -246,9 +214,7 @@ 
Source code for chipsec.utilcmd.spi_cmd
                 self.logger.log('    JEDEC ID: 0x{:06X}'.format(jedec_id))
                 self.logger.log('')
             else:
-                self.logger.log(' JEDEC ID command is not supported')

-

-
+                self.logger.log(' JEDEC ID command is not supported')

 
 commands = {'spi': SPICommand}
 

@@ -310,7 +276,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -330,8 +296,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/spidesc_cmd.html b/_modules/chipsec/utilcmd/spidesc_cmd.html
index 8fe69824..7b057d77 100644
--- a/_modules/chipsec/utilcmd/spidesc_cmd.html
+++ b/_modules/chipsec/utilcmd/spidesc_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.spidesc_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -71,35 +73,23 @@ 
Source code for chipsec.utilcmd.spidesc_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class SPIDescCommand(BaseCommand):
+
[docs]class SPIDescCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Config

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util spidesc', usage=__doc__)
         parser.add_argument('fd_file', type=str, help='File name')
         parser.set_defaults()
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
 
         self.logger.log("[CHIPSEC] Parsing SPI Flash Descriptor from file '{}'\n".format(self.fd_file))
         fd = read_file(self.fd_file)
         if fd:
-            parse_spi_flash_descriptor(self.cs, fd)

-

-
+            parse_spi_flash_descriptor(self.cs, fd)

 
 
 commands = {'spidesc': SPIDescCommand}
@@ -162,7 +152,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -182,8 +172,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/tpm_cmd.html b/_modules/chipsec/utilcmd/tpm_cmd.html
index 6ca90981..2a7e3f33 100644
--- a/_modules/chipsec/utilcmd/tpm_cmd.html
+++ b/_modules/chipsec/utilcmd/tpm_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.tpm_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -88,21 +90,14 @@ 
Source code for chipsec.utilcmd.tpm_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class TPMCommand(BaseCommand):
+
[docs]class TPMCommand(BaseCommand):
 
     no_driver_cmd = ['parse_log']
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_parse = subparsers.add_parser('parse_log')
@@ -120,23 +115,14 @@ 
Source code for chipsec.utilcmd.tpm_cmd
         parser_state.set_defaults(func=self.tpm_state)
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def tpm_parse(self):
+
[docs]    def tpm_parse(self):
         with open(self.file, 'rb') as log:
             tpm_eventlog.parse(log)

 
-
-

-[docs]
-    def tpm_command(self):
+
[docs]    def tpm_command(self):
         self._tpm.command(self.command_name, self.locality, self.command_parameters)

 
-
-

-[docs]
-    def tpm_state(self):
+
[docs]    def tpm_state(self):
         self._tpm.dump_access(self.locality)
         self._tpm.dump_status(self.locality)
         self._tpm.dump_didvid(self.locality)
@@ -144,10 +130,7 @@ 
Source code for chipsec.utilcmd.tpm_cmd
         self._tpm.dump_intcap(self.locality)
         self._tpm.dump_intenable(self.locality)

 
-
-

-[docs]
-    def set_up(self):
+
[docs]    def set_up(self):
         if self.func != self.tpm_parse:
             try:
                 self._tpm = tpm.TPM(self.cs)
@@ -155,16 +138,11 @@ 
Source code for chipsec.utilcmd.tpm_cmd
                 self.logger.log(msg)
                 return

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         try:
             self.func()
         except Exception:
-            self.ExitCode = ExitCode.ERROR

-

-
+            self.ExitCode = ExitCode.ERROR

 
 commands = {'tpm': TPMCommand}
 

@@ -226,7 +204,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -246,8 +224,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/txt_cmd.html b/_modules/chipsec/utilcmd/txt_cmd.html
index 0bf20d3d..58ec3fe1 100644
--- a/_modules/chipsec/utilcmd/txt_cmd.html
+++ b/_modules/chipsec/utilcmd/txt_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.txt_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -71,19 +73,12 @@ 
Source code for chipsec.utilcmd.txt_cmd
 import struct
 
 
-

-[docs]
-class TXTCommand(BaseCommand):
+
[docs]class TXTCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.All

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_state = subparsers.add_parser('dump')
@@ -92,10 +87,7 @@ 
Source code for chipsec.utilcmd.txt_cmd
         parser_state.set_defaults(func=self.txt_state)
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def txt_dump(self):
+
[docs]    def txt_dump(self):
         # Read TXT Public area as hexdump, with absolute address and skipping zeros
         txt_public = self.cs.mem.read_physical_mem(0xfed30000, 0x1000)
         has_skipped_line = False
@@ -110,9 +102,8 @@ 
Source code for chipsec.utilcmd.txt_cmd
             line_hex = " ".join("{:02X}".format(b) for b in line_bytes)
             self.logger.log("[CHIPSEC] {:08X}: {}".format(0xfed30000 + offset, line_hex))

 
-
     def _log_register(self, reg_name):
-        """Log the content of a register with lines starting with [CHIPSEC]"""
+        """Log the content of a register with lines starting with [CHIPSEC]"""
         reg_def = self.cs.get_register_def(reg_name)
         value = self.cs.read_register(reg_name)
         desc = reg_def["desc"]
@@ -132,10 +123,8 @@ 
Source code for chipsec.utilcmd.txt_cmd
                 self.logger.log("[CHIPSEC]     [{:02d}] {:23} = {:X} << {}".format(
                     field_bit, field_name, field_value, field_attrs['desc']))
 
-

-[docs]
-    def txt_state(self):
-        """Dump Intel TXT state
+
[docs]    def txt_state(self):
+        """Dump Intel TXT state
 
         This is similar to command "txt-stat" from Trusted Boot project
         https://sourceforge.net/p/tboot/code/ci/v2.0.0/tree/utils/txt-stat.c
@@ -215,16 +204,11 @@ 
Source code for chipsec.utilcmd.txt_cmd
         self._log_register("TXT_PCH_DIDVID")
         self._log_register("INSMM")

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         try:
             self.func()
         except Exception:
-            self.ExitCode = ExitCode.ERROR

-

-
+            self.ExitCode = ExitCode.ERROR

 
 commands = {'txt': TXTCommand}
 

@@ -286,7 +270,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -306,8 +290,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/ucode_cmd.html b/_modules/chipsec/utilcmd/ucode_cmd.html
index e8c8ea8f..fdc27abf 100644
--- a/_modules/chipsec/utilcmd/ucode_cmd.html
+++ b/_modules/chipsec/utilcmd/ucode_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.ucode_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -79,19 +81,12 @@ 
Source code for chipsec.utilcmd.ucode_cmd
 # ###################################################################
 
 
-

-[docs]
-class UCodeCommand(BaseCommand):
+
[docs]class UCodeCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
         parser_id = subparsers.add_parser('id')
@@ -107,10 +102,7 @@ 
Source code for chipsec.utilcmd.ucode_cmd
         parser_decode.add_argument('ucode_filename', type=str, help='ucode file name (.PDB format)')
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def ucode_id(self):
+
[docs]    def ucode_id(self):
         if self.cpu_thread_id is None:
             for tid in range(self.cs.msr.get_cpu_thread_count()):
                 ucode_update_id = self.cs.ucode.ucode_update_id(tid)
@@ -119,10 +111,7 @@ 
Source code for chipsec.utilcmd.ucode_cmd
             ucode_update_id = self.cs.ucode.ucode_update_id(self.cpu_thread_id)
             self.logger.log("[CHIPSEC] CPU{:d}: Microcode update ID = 0x{:08X}".format(self.cpu_thread_id, ucode_update_id))

 
-
-

-[docs]
-    def ucode_load(self):
+
[docs]    def ucode_load(self):
         if self.cpu_thread_id is None:
             self.logger.log("[CHIPSEC] Loading Microcode update on all cores from '{}'".format(self.ucode_filename))
             self.cs.ucode.update_ucode_all_cpus(self.ucode_filename)
@@ -130,18 +119,13 @@ 
Source code for chipsec.utilcmd.ucode_cmd
             self.logger.log("[CHIPSEC] Loading Microcode update on CPU{:d} from '{}'".format(self.cpu_thread_id, self.ucode_filename))
             self.cs.ucode.update_ucode(self.cpu_thread_id, self.ucode_filename)

 
-
-

-[docs]
-    def ucode_decode(self):
+
[docs]    def ucode_decode(self):
         if (not self.ucode_filename.endswith('.pdb')):
             self.logger.log("[CHIPSEC] Ucode update file is not PDB file: '{}'".format(self.ucode_filename))
             return
         pdb_ucode_buffer = read_file(self.ucode_filename)
         self.logger.log("[CHIPSEC] Decoding Microcode Update header of PDB file: '{}'".format(self.ucode_filename))
-        dump_ucode_update_header(pdb_ucode_buffer)

-

-
+        dump_ucode_update_header(pdb_ucode_buffer)

 
 
 commands = {'ucode': UCodeCommand}
@@ -204,7 +188,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -224,8 +208,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/uefi_cmd.html b/_modules/chipsec/utilcmd/uefi_cmd.html
index 2d89251e..c5b3ac0e 100644
--- a/_modules/chipsec/utilcmd/uefi_cmd.html
+++ b/_modules/chipsec/utilcmd/uefi_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.uefi_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -108,21 +110,14 @@ 
Source code for chipsec.utilcmd.uefi_cmd
 
 
 # Unified Extensible Firmware Interface (UEFI)
-

-[docs]
-class UEFICommand(BaseCommand):
+
[docs]class UEFICommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         if 'decode' in self.argv:
             return toLoad.Nil
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util uefi', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -230,23 +225,14 @@ 
Source code for chipsec.utilcmd.uefi_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._uefi = UEFI(self.cs)

 
-
-

-[docs]
-    def var_read(self):
+
[docs]    def var_read(self):
         self.logger.log("[CHIPSEC] Reading EFI variable Name='{}' GUID={{{}}} to '{}' via Variable API..".format(self.name, self.guid, self.filename))
         var = self._uefi.get_EFI_variable(self.name, self.guid, self.filename)

 
-
-

-[docs]
-    def var_write(self):
+
[docs]    def var_write(self):
         self.logger.log("[CHIPSEC] writing EFI variable Name='{}' GUID={{{}}} from '{}' via Variable API..".format(self.name, self.guid, self.filename))
         status = self._uefi.set_EFI_variable_from_file(self.name, self.guid, self.filename)
         self.logger.log("[CHIPSEC] status: {}".format(EFI_STATUS_DICT[status]))
@@ -255,10 +241,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         else:
             self.logger.log_error("writing EFI variable failed")

 
-
-

-[docs]
-    def var_delete(self):
+
[docs]    def var_delete(self):
         self.logger.log("[CHIPSEC] Deleting EFI variable Name='{}' GUID={{{}}} via Variable API..".format(self.name, self.guid))
         status = self._uefi.delete_EFI_variable(self.name, self.guid)
         self.logger.log("Returned {}".format(EFI_STATUS_DICT[status]))
@@ -267,10 +250,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         else:
             self.logger.log_error("deleting EFI variable failed")

 
-
-

-[docs]
-    def var_list(self):
+
[docs]    def var_list(self):
         self.logger.log("[CHIPSEC] Enumerating all EFI variables via OS specific EFI Variable API..")
         efi_vars = self._uefi.list_EFI_variables()
         if efi_vars is None:
@@ -286,10 +266,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         self.logger.set_log_file(_orig_logname)
         self.logger.log("[CHIPSEC] Variables are in efi_variables.lst log and efi_variables.dir directory")

 
-
-

-[docs]
-    def var_find(self):
+
[docs]    def var_find(self):
         _vars = self._uefi.list_EFI_variables()
         if _vars is None:
             self.logger.log_warning('Could not enumerate UEFI variables (non-UEFI OS?)')
@@ -322,10 +299,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
                     write_file(var_fname, data)
                     n += 1

 
-
-

-[docs]
-    def nvram(self):
+
[docs]    def nvram(self):
         authvars = 0
         rom = read_file(self.romfilename)
         if self.fwtype is None:
@@ -342,10 +316,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         parse_EFI_variables( self.romfilename, rom, authvars, self.fwtype )
         self.logger.set_log_file( _orig_logname )

 
-
-

-[docs]
-    def nvram_auth(self):
+
[docs]    def nvram_auth(self):
         authvars = 1
         rom = read_file(self.romfilename)
         if self.fwtype is None:
@@ -362,10 +333,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         parse_EFI_variables( self.romfilename, rom, authvars, self.fwtype )
         self.logger.set_log_file( _orig_logname )

 
-
-

-[docs]
-    def decode(self):
+
[docs]    def decode(self):
         if not os.path.exists(self.filename):
             self.logger.log_error("Could not find file '{}'".format(self.filename))
             return
@@ -385,10 +353,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         decode_uefi_region(cur_dir, self.filename, self.fwtype, ftypes)
         self.logger.set_log_file( _orig_logname )

 
-
-

-[docs]
-    def keys(self):
+
[docs]    def keys(self):
         if not os.path.exists(self.filename):
             self.logger.log_error("Could not find file '{}'".format(self.filename))
             return
@@ -396,17 +361,11 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         self.logger.log("[CHIPSEC] Parsing EFI variable from '{}'..".format(self.filename))
         parse_efivar_file(self.filename)

 
-
-

-[docs]
-    def tables(self):
+
[docs]    def tables(self):
         self.logger.log("[CHIPSEC] Searching memory for and dumping EFI tables (this may take a minute)..\n")
         self._uefi.dump_EFI_tables()

 
-
-

-[docs]
-    def s3bootscript(self):
+
[docs]    def s3bootscript(self):
         self.logger.log("[CHIPSEC] Searching for and parsing S3 resume bootscripts..")
         if self.bootscript_pa is not None:
             self.logger.log('[*] Reading S3 boot-script from memory at 0x{:016X}..'.format(self.bootscript_pa))
@@ -416,10 +375,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         else:
             (bootscript_PAs, parsed_scripts) = self._uefi.get_s3_bootscript(True)

 
-
-

-[docs]
-    def insert_before(self):
+
[docs]    def insert_before(self):
         if get_guid_bin(self.guid) == '':
             print('*** Error *** Invalid GUID: {}'.format(self.guid))
             return
@@ -437,10 +393,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         new_image = modify_uefi_region(rom_image, CMD_UEFI_FILE_INSERT_BEFORE, self.guid, efi_image)
         write_file(self.new_file, new_image)

 
-
-

-[docs]
-    def insert_after(self):
+
[docs]    def insert_after(self):
         if get_guid_bin(self.guid) == '':
             print('*** Error *** Invalid GUID: {}'.format(self.guid))
             return
@@ -458,10 +411,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         new_image = modify_uefi_region(rom_image, CMD_UEFI_FILE_INSERT_AFTER, self.guid, efi_image)
         write_file(self.new_file, new_image)

 
-
-

-[docs]
-    def replace(self):
+
[docs]    def replace(self):
         if get_guid_bin(self.guid) == '':
             print('*** Error *** Invalid GUID: {}'.format(self.guid))
             return
@@ -479,10 +429,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         new_image = modify_uefi_region(rom_image, CMD_UEFI_FILE_REPLACE, self.guid, efi_image)
         write_file(self.new_file, new_image)

 
-
-

-[docs]
-    def remove(self):
+
[docs]    def remove(self):
         if get_guid_bin(self.guid) == '':
             print('*** Error *** Invalid GUID: {}'.format(self.guid))
             return
@@ -495,10 +442,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
         new_image = modify_uefi_region(rom_image, CMD_UEFI_FILE_REMOVE, self.guid)
         write_file(self.new_file, new_image)

 
-
-

-[docs]
-    def assemble(self):
+
[docs]    def assemble(self):
         compression = {'none': 0, 'tiano': 1, 'lzma': 2}
 
         if get_guid_bin(self.guid) == '':
@@ -527,9 +471,7 @@ 
Source code for chipsec.utilcmd.uefi_cmd
             print('*** Error *** Unknow file type: {}'.format(self.file_type))
             return
 
-        self.logger.log("[CHIPSEC]  UEFI file was successfully assembled! Binary file size: {:d}, compressed UEFI file size: {:d}".format(len(raw_image), len(uefi_image)))

-

-
+        self.logger.log("[CHIPSEC]  UEFI file was successfully assembled! Binary file size: {:d}, compressed UEFI file size: {:d}".format(len(raw_image), len(uefi_image)))

 
 
 commands = {'uefi': UEFICommand}
@@ -592,7 +534,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -612,8 +554,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/vmem_cmd.html b/_modules/chipsec/utilcmd/vmem_cmd.html
index a689715e..0f7fb785 100644
--- a/_modules/chipsec/utilcmd/vmem_cmd.html
+++ b/_modules/chipsec/utilcmd/vmem_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.vmem_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -94,19 +96,12 @@ 
Source code for chipsec.utilcmd.vmem_cmd
 
 
 # Virtual Memory
-

-[docs]
-class VMemCommand(BaseCommand):
+
[docs]class VMemCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -148,16 +143,10 @@ 
Source code for chipsec.utilcmd.vmem_cmd
         parser_getphys.set_defaults(func=self.vmem_getphys)
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def set_up(self) -> None:
+
[docs]    def set_up(self) -> None:
         self._vmem = virtmem.VirtMemory(self.cs)

 
-
-

-[docs]
-    def vmem_read(self):
+
[docs]    def vmem_read(self):
         self.logger.log('[CHIPSEC] Reading buffer from memory: VA = 0x{:016X}, len = 0x{:X}.'.format(self.virt_address, self.size))
         try:
             buffer = self._vmem.read_virtual_mem(self.virt_address, self.size)
@@ -171,10 +160,7 @@ 
Source code for chipsec.utilcmd.vmem_cmd
         else:
             print_buffer_bytes(buffer)

 
-
-

-[docs]
-    def vmem_readval(self):
+
[docs]    def vmem_readval(self):
         width = 0x4
         value = 0x0
         if self.length is not None:
@@ -202,10 +188,7 @@ 
Source code for chipsec.utilcmd.vmem_cmd
             return
         self.logger.log('[CHIPSEC] value = 0x{:X}'.format(value))

 
-
-

-[docs]
-    def vmem_write(self):
+
[docs]    def vmem_write(self):
         if not os.path.exists(self.buf_file):
             try:
                 buffer = bytearray.fromhex(self.buf_file)
@@ -225,10 +208,7 @@ 
Source code for chipsec.utilcmd.vmem_cmd
         self.logger.log('[CHIPSEC] Writing buffer to memory: VA = 0x{:016X}, len = 0x{:X}.'.format(self.virt_address, self.size))
         self._vmem.write_virtual_mem(self.virt_address, self.size, buffer)

 
-
-

-[docs]
-    def vmem_writeval(self):
+
[docs]    def vmem_writeval(self):
         if chipsec_util.is_option_valid_width(self.length):
             width = chipsec_util.get_option_width(self.length)
         else:
@@ -250,10 +230,7 @@ 
Source code for chipsec.utilcmd.vmem_cmd
         except (TypeError, OSError):
             self.logger.log_error('Error mapping VA to PA.')

 
-
-
       

       

@@ -380,8 +349,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/chipsec/utilcmd/vmm_cmd.html b/_modules/chipsec/utilcmd/vmm_cmd.html
index 6b556794..a0bca983 100644
--- a/_modules/chipsec/utilcmd/vmm_cmd.html
+++ b/_modules/chipsec/utilcmd/vmm_cmd.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     chipsec.utilcmd.vmm_cmd — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -80,19 +82,12 @@ 
Source code for chipsec.utilcmd.vmm_cmd
 from argparse import ArgumentParser
 
 
-

-[docs]
-class VMMCommand(BaseCommand):
+
[docs]class VMMCommand(BaseCommand):
 
-

-[docs]
-    def requirements(self) -> toLoad:
+
[docs]    def requirements(self) -> toLoad:
         return toLoad.Driver

 
-
-

-[docs]
-    def parse_arguments(self) -> None:
+
[docs]    def parse_arguments(self) -> None:
         parser = ArgumentParser(prog='chipsec_util vmm', usage=__doc__)
         subparsers = parser.add_subparsers()
 
@@ -123,10 +118,7 @@ 
Source code for chipsec.utilcmd.vmm_cmd
 
         parser.parse_args(self.argv, namespace=self)

 
-
-

-[docs]
-    def vmm_virtio(self):
+
[docs]    def vmm_virtio(self):
         if self.bdf is not None:
             match = re.search(r"^([0-9a-f]{1,2}):([0-1]?[0-9a-f]{1})\.([0-7]{1})$", self.bdf)
             if match:
@@ -153,10 +145,7 @@ 
Source code for chipsec.utilcmd.vmm_cmd
         else:
             self.logger.log("[CHIPSEC] No VirtIO devices found")

 
-
-

-[docs]
-    def vmm_hypercall(self):
+
[docs]    def vmm_hypercall(self):
         self.logger.log('')
         self.logger.log("[CHIPSEC] > hypercall")
         self.logger.log("[CHIPSEC]   RAX: 0x{:016X}".format(self.ax))
@@ -174,10 +163,7 @@ 
Source code for chipsec.utilcmd.vmm_cmd
 
         self.logger.log("[CHIPSEC] < RAX: 0x{:016X}".format(rax))

 
-
-

-[docs]
-    def vmm_pt(self):
+
[docs]    def vmm_pt(self):
         if self.eptp is not None:
             pt_fname = 'ept_{:08X}'.format(self.eptp)
             self.logger.log("[CHIPSEC] EPT physical base: 0x{:016X}".format(self.eptp))
@@ -188,10 +174,7 @@ 
Source code for chipsec.utilcmd.vmm_cmd
             self.logger.log_error(VMMCommand.__doc__)
             return

 
-
-

-[docs]
-    def run(self):
+
[docs]    def run(self):
         try:
             self.vmm = VMM(self.cs)
         except VMMRuntimeError as msg:
@@ -200,9 +183,7 @@ 
Source code for chipsec.utilcmd.vmm_cmd
 
         self.vmm.init()
 
-        self.func()

-

-
+        self.func()

 
 
 commands = {'vmm': VMMCommand}
@@ -265,7 +246,7 @@ 
Quick search

     
     

 

-
+
         

       

       

@@ -285,8 +266,8 @@ 
Navigation

       
     

     
   
 
\ No newline at end of file
diff --git a/_modules/index.html b/_modules/index.html
index aeba04f8..37de0ef1 100644
--- a/_modules/index.html
+++ b/_modules/index.html
@@ -1,18 +1,20 @@
+
 
 
-
+
   
     
     
     Overview: module code — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -86,6 +88,7 @@ 
All modules for which code is available

 
  • chipsec.helper.linuxnative.linuxnativehelper
    • 
 
  • chipsec.helper.nonehelper
    • 
 
  • chipsec.helper.oshelper
    • 
+
  • chipsec.helper.windows.windowshelper
    • 
 
  • chipsec.library.architecture
    • 
 
  • chipsec.library.bits
    • 
 
  • chipsec.library.strings
    • 
@@ -94,6 +97,7 @@ 
    All modules for which code is available
    
 
  • chipsec.modules.common.bios_smi
    • 
 
  • chipsec.modules.common.bios_ts
    • 
 
  • chipsec.modules.common.bios_wp
    • 
+
  • chipsec.modules.common.cet
    • 
 
  • chipsec.modules.common.cpu.cpu_info
    • 
 
  • chipsec.modules.common.cpu.ia_untrusted
    • 
 
  • chipsec.modules.common.cpu.spectre_v2
    • 
@@ -116,41 +120,8 @@ 
    All modules for which code is available
    
 
  • chipsec.modules.common.spi_lock
    • 
 
  • chipsec.modules.common.uefi.access_uefispec
    • 
 
  • chipsec.modules.common.uefi.s3bootscript
    • 
-
  • chipsec.modules.tools.cpu.sinkhole
    • 
-
  • chipsec.modules.tools.generate_test_id
    • 
-
  • chipsec.modules.tools.secureboot.te
    • 
-
  • chipsec.modules.tools.smm.rogue_mmio_bar
    • 
-
  • chipsec.modules.tools.smm.smm_ptr
    • 
-
  • chipsec.modules.tools.uefi.reputation
    • 
-
  • chipsec.modules.tools.uefi.s3script_modify
    • 
-
  • chipsec.modules.tools.uefi.scan_blocked
    • 
-
  • chipsec.modules.tools.uefi.scan_image
    • 
-
  • chipsec.modules.tools.uefi.uefivar_fuzz
    • 
-
  • chipsec.modules.tools.vmm.common
    • 
-
  • chipsec.modules.tools.vmm.cpuid_fuzz
    • 
-
  • chipsec.modules.tools.vmm.ept_finder
    • 
-
  • chipsec.modules.tools.vmm.hv.define
    • 
-
  • chipsec.modules.tools.vmm.hv.hypercall
    • 
-
  • chipsec.modules.tools.vmm.hv.hypercallfuzz
    • 
-
  • chipsec.modules.tools.vmm.hv.synth_dev
    • 
-
  • chipsec.modules.tools.vmm.hv.synth_kbd
    • 
-
  • chipsec.modules.tools.vmm.hv.vmbus
    • 
-
  • chipsec.modules.tools.vmm.hv.vmbusfuzz
    • 
-
  • chipsec.modules.tools.vmm.hypercallfuzz
    • 
-
  • chipsec.modules.tools.vmm.iofuzz
    • 
-
  • chipsec.modules.tools.vmm.msr_fuzz
    • 
-
  • chipsec.modules.tools.vmm.pcie_fuzz
    • 
-
  • chipsec.modules.tools.vmm.pcie_overlap_fuzz
    • 
-
  • chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase
    • 
-
  • chipsec.modules.tools.vmm.venom
    • 
-
  • chipsec.modules.tools.vmm.xen.define
    • 
-
  • chipsec.modules.tools.vmm.xen.hypercall
    • 
-
  • chipsec.modules.tools.vmm.xen.hypercallfuzz
    • 
-
  • chipsec.modules.tools.vmm.xen.xsa188
    • 
-
  • chipsec.modules.tools.wsmt
    • 
 
  • chipsec.options
    • 
 
  • chipsec.parsers
    • 
-
  • chipsec.testcase
    • 
 
  • chipsec.utilcmd.acpi_cmd
    • 
 
  • chipsec.utilcmd.chipset_cmd
    • 
 
  • chipsec.utilcmd.cmos_cmd
    • 
@@ -243,7 +214,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -262,8 +233,8 @@ 
    Navigation
    
       
     
    
     
   
 
\ No newline at end of file
diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt
index 2de30c79..f2d15ba0 100644
--- a/_sources/index.rst.txt
+++ b/_sources/index.rst.txt
@@ -1,10 +1,10 @@
-.. CHIPSEC 1.12.8 documentation file, created by
+.. CHIPSEC documentation file, created by
    sphinx-quickstart on Wed Mar 25 13:24:44 2015.
    You can adapt this file completely to your liking, but it should at least
    contain the root `toctree` directive.
 
-CHIPSEC 1.12.8
-==============
+CHIPSEC
+=======
 
 CHIPSEC is a framework for analyzing platform level security of
 hardware, devices, system firmware, low-level protection mechanisms, and
diff --git a/_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt
deleted file mode 100644
index 68f4ddf6..00000000
--- a/_sources/modules/chipsec.cfg.8086.adl.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-adl
-=======
-
-Path: chipsec\\cfg\\8086\\adl.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt
deleted file mode 100644
index 02dd8d2e..00000000
--- a/_sources/modules/chipsec.cfg.8086.apl.xml.rst.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-apl
-=======
-
-Path: chipsec\\cfg\\8086\\apl.xml
-
-
-XML configuration for Apollo Lake based SoCs
-document id 334818/334819
-
diff --git a/_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt
deleted file mode 100644
index 77a37b9b..00000000
--- a/_sources/modules/chipsec.cfg.8086.avn.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-avn
-=======
-
-Path: chipsec\\cfg\\8086\\avn.xml
-
-
-XML configuration for Avoton based platforms
-
-* Intel(R) Atom(TM) Processor C2000 Product Family for Microserver, September 2014 
-  http://www.intel.com/content/www/us/en/processors/atom/atom-c2000-microserver-datasheet.html
-
diff --git a/_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt
deleted file mode 100644
index de53c4d4..00000000
--- a/_sources/modules/chipsec.cfg.8086.bdw.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-bdw
-=======
-
-Path: chipsec\\cfg\\8086\\bdw.xml
-
-
-XML configuration for Broadwell based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt
deleted file mode 100644
index 90402f95..00000000
--- a/_sources/modules/chipsec.cfg.8086.bdx.xml.rst.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-bdx
-=======
-
-Path: chipsec\\cfg\\8086\\bdx.xml
-
-
-XML configuration file for Broadwell Server based platforms
-Intel (c) Xeon Processor E5 v4 Product Family datasheet Vol. 2
-Intel (c) Xeon Processor E7 v4 Product Family datasheet Vol. 2
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
-Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
-
diff --git a/_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt
deleted file mode 100644
index e57d29ec..00000000
--- a/_sources/modules/chipsec.cfg.8086.byt.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-byt
-=======
-
-Path: chipsec\\cfg\\8086\\byt.xml
-
-
-XML configuration for Bay Trail based platforms
-
-* Intel(R) Atom(TM) Processor E3800 Product Family Datasheet, May 2016, Revision 4.0
-  http://www.intel.com/content/www/us/en/embedded/products/bay-trail/atom-e3800-family-datasheet.html
-
diff --git a/_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt
deleted file mode 100644
index 29d7e9d5..00000000
--- a/_sources/modules/chipsec.cfg.8086.cfl.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-cfl
-=======
-
-Path: chipsec\\cfg\\8086\\cfl.xml
-
-
-XML configuration file for Coffee Lake
-
-* 8th Generation Intel(R) Processor Family for S-Processor Platforms
-  https://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-
diff --git a/_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt
deleted file mode 100644
index 06aa9ebe..00000000
--- a/_sources/modules/chipsec.cfg.8086.cht.xml.rst.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-cht
-=======
-
-Path: chipsec\\cfg\\8086\\cht.xml
-
-
-XML configuration for Cherry Trail and Braswell SoCs
-
-* Intel(R) Atom(TM) Processor Z8000 series datasheet
-  http://www.intel.com/content/www/us/en/processors/atom/atom-z8000-datasheet-vol-2.html
-
-* N-series Intel(R) Pentium(R) and Celeron(R) Processors Datasheet
-  http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-2.pdf
-
diff --git a/_sources/modules/chipsec.cfg.8086.cml.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.cml.xml.rst.txt
deleted file mode 100644
index 3d8b8be3..00000000
--- a/_sources/modules/chipsec.cfg.8086.cml.xml.rst.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-cml
-=======
-
-Path: chipsec\\cfg\\8086\\cml.xml
-
- XML configuration file for Comet Lake 
diff --git a/_sources/modules/chipsec.cfg.8086.common.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.common.xml.rst.txt
deleted file mode 100644
index 4ab92728..00000000
--- a/_sources/modules/chipsec.cfg.8086.common.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-common
-==========
-
-Path: chipsec\\cfg\\8086\\common.xml
-
-
-Common (default) XML platform configuration file
-
diff --git a/_sources/modules/chipsec.cfg.8086.dnv.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.dnv.xml.rst.txt
deleted file mode 100644
index 11d38718..00000000
--- a/_sources/modules/chipsec.cfg.8086.dnv.xml.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-dnv
-=======
-
-Path: chipsec\\cfg\\8086\\dnv.xml
-
-
-XML configuration file for Denverton
-
-* Intel Atom(R) Processor C3000 Product Family
-  https://www.intel.com/content/www/us/en/processors/atom/atom-technical-resources.html
-  337018-002
-
diff --git a/_sources/modules/chipsec.cfg.8086.ehl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ehl.xml.rst.txt
deleted file mode 100644
index e587fe41..00000000
--- a/_sources/modules/chipsec.cfg.8086.ehl.xml.rst.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-ehl
-=======
-
-Path: chipsec\\cfg\\8086\\ehl.xml
-
-
-XML configuration file for Elkhart Lake
-Document ID: 635255, 636112, 636722, 636723
-
diff --git a/_sources/modules/chipsec.cfg.8086.glk.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.glk.xml.rst.txt
deleted file mode 100644
index 04772a7d..00000000
--- a/_sources/modules/chipsec.cfg.8086.glk.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-glk
-=======
-
-Path: chipsec\\cfg\\8086\\glk.xml
-
- XML configuration for GLK
-  Document ID: 336561-001
-
diff --git a/_sources/modules/chipsec.cfg.8086.hsw.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.hsw.xml.rst.txt
deleted file mode 100644
index 5a9a80db..00000000
--- a/_sources/modules/chipsec.cfg.8086.hsw.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-hsw
-=======
-
-Path: chipsec\\cfg\\8086\\hsw.xml
-
-
-XML configuration file for Haswell based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.hsx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.hsx.xml.rst.txt
deleted file mode 100644
index 0632542a..00000000
--- a/_sources/modules/chipsec.cfg.8086.hsx.xml.rst.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-hsx
-=======
-
-Path: chipsec\\cfg\\8086\\hsx.xml
-
-
-XML configuration file for Haswell Server based platforms
-Intel (c) Xeon Processor E5-1600/2400/2600/4600 v3 Product Family datasheet Vol. 2
-Intel (c) Xeon Processor E7-8800/4800 v3 Product Family datasheet Vol. 2
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
-Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
-
diff --git a/_sources/modules/chipsec.cfg.8086.icl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.icl.xml.rst.txt
deleted file mode 100644
index 2657dfc3..00000000
--- a/_sources/modules/chipsec.cfg.8086.icl.xml.rst.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-icl
-=======
-
-Path: chipsec\\cfg\\8086\\icl.xml
-
- XML configuration file for Ice Lake 
diff --git a/_sources/modules/chipsec.cfg.8086.icx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.icx.xml.rst.txt
deleted file mode 100644
index 90040c2d..00000000
--- a/_sources/modules/chipsec.cfg.8086.icx.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-icx
-=======
-
-Path: chipsec\\cfg\\8086\\icx.xml
-
-
-XML configuration file for Icelake/Lewisburg Server
-
diff --git a/_sources/modules/chipsec.cfg.8086.iommu.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.iommu.xml.rst.txt
deleted file mode 100644
index 5fbbe833..00000000
--- a/_sources/modules/chipsec.cfg.8086.iommu.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-iommu
-=========
-
-Path: chipsec\\cfg\\8086\\iommu.xml
-
-
-XML configuration file for Intel Virtualization Technology for Directed I/O (VT-d)
-
-* Section 10 of Intel Virtualization Technology for Directed I/O
-  http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
-
diff --git a/_sources/modules/chipsec.cfg.8086.ivb.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ivb.xml.rst.txt
deleted file mode 100644
index 2ec89186..00000000
--- a/_sources/modules/chipsec.cfg.8086.ivb.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-ivb
-=======
-
-Path: chipsec\\cfg\\8086\\ivb.xml
-
-
-XML configuration for IvyBridge based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.ivt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.ivt.xml.rst.txt
deleted file mode 100644
index fdf4a476..00000000
--- a/_sources/modules/chipsec.cfg.8086.ivt.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-ivt
-=======
-
-Path: chipsec\\cfg\\8086\\ivt.xml
-
-
-XML configuration file for Ivytown (Ivy Bridge-E) based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.jkt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.jkt.xml.rst.txt
deleted file mode 100644
index 397fe376..00000000
--- a/_sources/modules/chipsec.cfg.8086.jkt.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-jkt
-=======
-
-Path: chipsec\\cfg\\8086\\jkt.xml
-
-
-XML configuration file for Jaketown (Sandy Bridge-E) based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.kbl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.kbl.xml.rst.txt
deleted file mode 100644
index f6ae0a06..00000000
--- a/_sources/modules/chipsec.cfg.8086.kbl.xml.rst.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-kbl
-=======
-
-Path: chipsec\\cfg\\8086\\kbl.xml
-
-
-XML configuration file for Kaby Lake based platforms
-
-http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-
-* 7th Generation Intel(R) Processor Families for U/Y-Platforms
-
-* 7th Generation Intel(R) Processor Families I/O for U/Y-Platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_1xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_1xx.xml.rst.txt
deleted file mode 100644
index 37ad1f95..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_1xx.xml.rst.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-pch_1xx
-===========
-
-Path: chipsec\\cfg\\8086\\pch_1xx.xml
-
-
-XML configuration file for 100 series PCH based platforms
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2020-2021, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
-* Intel(R) 100 Series Chipset Family Platform Controller Hub (PCH)
-  http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_2xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_2xx.xml.rst.txt
deleted file mode 100644
index 9469fdb6..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_2xx.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-pch_2xx
-===========
-
-Path: chipsec\\cfg\\8086\\pch_2xx.xml
-
-
-XML configuration file for 200 series PCH based platforms
-
-* Intel(R) 200 Series Chipset Family Platform Controller Hub (PCH)
-  http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xx.xml.rst.txt
deleted file mode 100644
index 2f580567..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_3xx.xml.rst.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-pch_3xx
-===========
-
-Path: chipsec\\cfg\\8086\\pch_3xx.xml
-
-
-XML configuration file for the 300 series PCH
-https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-pch-datasheet-vol-2.html
-337348-001
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xxlp.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xxlp.xml.rst.txt
deleted file mode 100644
index 2f5b216f..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_3xxlp.xml.rst.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-pch_3xxlp
-=============
-
-Path: chipsec\\cfg\\8086\\pch_3xxlp.xml
-
-
-XML configuration file for the 300 series LP (U/Y) PCH
-https://www.intel.com/content/www/us/en/products/docs/processors/core/7th-and-8th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-2.html
-334659-005
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_3xxop.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_3xxop.xml.rst.txt
deleted file mode 100644
index b19f0764..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_3xxop.xml.rst.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-pch_3xxop
-=============
-
-Path: chipsec\\cfg\\8086\\pch_3xxop.xml
-
-
-XML configuration file for the 300 series On Package PCH
-https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-on-package-pch-datasheet-vol-2.html
-337868-002
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_495.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_495.xml.rst.txt
deleted file mode 100644
index dcab2e63..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_495.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_495
-===========
-
-Path: chipsec\\cfg\\8086\\pch_495.xml
-
-
-XML configuration file for the 495 series PCH
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_4xx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_4xx.xml.rst.txt
deleted file mode 100644
index caf0f7e9..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_4xx.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_4xx
-===========
-
-Path: chipsec\\cfg\\8086\\pch_4xx.xml
-
-
-  XML configuration file for 4XX pch
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_4xxh.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_4xxh.xml.rst.txt
deleted file mode 100644
index 4f543111..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_4xxh.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_4xxh
-============
-
-Path: chipsec\\cfg\\8086\\pch_4xxh.xml
-
-
-  XML configuration file 4xxH PCH 620855
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_4xxlp.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_4xxlp.xml.rst.txt
deleted file mode 100644
index a1a6f9cb..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_4xxlp.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_4xxlp
-=============
-
-Path: chipsec\\cfg\\8086\\pch_4xxlp.xml
-
-
-  XML configuration file for the 400 series LP (U/H) PCH
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_5xxh.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_5xxh.xml.rst.txt
deleted file mode 100644
index 717ddc4b..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_5xxh.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_5xxh
-============
-
-Path: chipsec\\cfg\\8086\\pch_5xxh.xml
-
-
-XML configuration file for 5XXH series pch
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_5xxlp.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_5xxlp.xml.rst.txt
deleted file mode 100644
index c85234dc..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_5xxlp.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-pch_5xxlp
-=============
-
-Path: chipsec\\cfg\\8086\\pch_5xxlp.xml
-
-
-XML configuration file for 5XXLP series pch
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_6xxP.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_6xxP.xml.rst.txt
deleted file mode 100644
index c7f32e95..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_6xxP.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-pch_6xxP
-============
-
-Path: chipsec\\cfg\\8086\\pch_6xxP.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_6xxS.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_6xxS.xml.rst.txt
deleted file mode 100644
index 7f1ed154..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_6xxS.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-pch_6xxS
-============
-
-Path: chipsec\\cfg\\8086\\pch_6xxS.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_7x.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_7x.xml.rst.txt
deleted file mode 100644
index 232268a6..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_7x.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-pch_7x
-==========
-
-Path: chipsec\\cfg\\8086\\pch_7x.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_8x.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_8x.xml.rst.txt
deleted file mode 100644
index 5bf3f24b..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_8x.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-pch_8x
-==========
-
-Path: chipsec\\cfg\\8086\\pch_8x.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_c60x.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_c60x.xml.rst.txt
deleted file mode 100644
index bd73b9d3..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_c60x.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-pch_c60x
-============
-
-Path: chipsec\\cfg\\8086\\pch_c60x.xml
-
-
-XML configuration file for C600 series PCH
-  Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-  Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
-  https://ark.intel.com/products/series/98463/Intel-C600-Series-Chipsets
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_c61x.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_c61x.xml.rst.txt
deleted file mode 100644
index 3345f3b2..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_c61x.xml.rst.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-pch_c61x
-============
-
-Path: chipsec\\cfg\\8086\\pch_c61x.xml
-
-
-XML configuration file for C610 series PCH
-  Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
-  https://ark.intel.com/products/series/98915/Intel-C610-Series-Chipsets
-
diff --git a/_sources/modules/chipsec.cfg.8086.pch_c620.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pch_c620.xml.rst.txt
deleted file mode 100644
index 8d192626..00000000
--- a/_sources/modules/chipsec.cfg.8086.pch_c620.xml.rst.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-pch_c620
-============
-
-Path: chipsec\\cfg\\8086\\pch_c620.xml
-
-
-XML configuration file for
-
-* Intel(R) C620 Series Chipset Family Platform Controller Hub
-  https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/c620-series-chipset-datasheet.pdf
-
diff --git a/_sources/modules/chipsec.cfg.8086.pmc_i440fx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.pmc_i440fx.xml.rst.txt
deleted file mode 100644
index bcab2341..00000000
--- a/_sources/modules/chipsec.cfg.8086.pmc_i440fx.xml.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-pmc_i440fx
-==============
-
-Path: chipsec\\cfg\\8086\\pmc_i440fx.xml
-
-
-XML configuration file for Intel 440FX PCI and Memory Controller (PMC).
-It is used by QEMU "pc" machine, implemented in
-https://github.com/qemu/qemu/blob/v7.0.0/hw/pci-host/i440fx.c
-
-A datasheet is available on https://wiki.qemu.org/File:29054901.pdf
-
diff --git a/_sources/modules/chipsec.cfg.8086.qrk.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.qrk.xml.rst.txt
deleted file mode 100644
index db249f29..00000000
--- a/_sources/modules/chipsec.cfg.8086.qrk.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-qrk
-=======
-
-Path: chipsec\\cfg\\8086\\qrk.xml
-
-
-XML configuration for Quark based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.rkl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.rkl.xml.rst.txt
deleted file mode 100644
index 07cb507f..00000000
--- a/_sources/modules/chipsec.cfg.8086.rkl.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-rkl
-=======
-
-Path: chipsec\\cfg\\8086\\rkl.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.rpl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.rpl.xml.rst.txt
deleted file mode 100644
index 740602f6..00000000
--- a/_sources/modules/chipsec.cfg.8086.rpl.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-rpl
-=======
-
-Path: chipsec\\cfg\\8086\\rpl.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.rst.txt b/_sources/modules/chipsec.cfg.8086.rst.txt
deleted file mode 100644
index e9315a88..00000000
--- a/_sources/modules/chipsec.cfg.8086.rst.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-.. toctree::
-
-	chipsec.cfg.8086.ehl.xml.rst
-	chipsec.cfg.8086.pch_8x.xml.rst
-	chipsec.cfg.8086.hsw.xml.rst
-	chipsec.cfg.8086.sfdp.xml.rst
-	chipsec.cfg.8086.pmc_i440fx.xml.rst
-	chipsec.cfg.8086.pch_4xxlp.xml.rst
-	chipsec.cfg.8086.glk.xml.rst
-	chipsec.cfg.8086.icx.xml.rst
-	chipsec.cfg.8086.ivt.xml.rst
-	chipsec.cfg.8086.pch_2xx.xml.rst
-	chipsec.cfg.8086.cht.xml.rst
-	chipsec.cfg.8086.skx.xml.rst
-	chipsec.cfg.8086.pch_5xxh.xml.rst
-	chipsec.cfg.8086.jkt.xml.rst
-	chipsec.cfg.8086.pch_7x.xml.rst
-	chipsec.cfg.8086.tpm12.xml.rst
-	chipsec.cfg.8086.apl.xml.rst
-	chipsec.cfg.8086.pch_495.xml.rst
-	chipsec.cfg.8086.snb.xml.rst
-	chipsec.cfg.8086.pch_3xx.xml.rst
-	chipsec.cfg.8086.pch_3xxop.xml.rst
-	chipsec.cfg.8086.pch_5xxlp.xml.rst
-	chipsec.cfg.8086.bdx.xml.rst
-	chipsec.cfg.8086.cml.xml.rst
-	chipsec.cfg.8086.pch_6xxS.xml.rst
-	chipsec.cfg.8086.skl.xml.rst
-	chipsec.cfg.8086.tglu.xml.rst
-	chipsec.cfg.8086.hsx.xml.rst
-	chipsec.cfg.8086.rpl.xml.rst
-	chipsec.cfg.8086.qrk.xml.rst
-	chipsec.cfg.8086.pch_4xx.xml.rst
-	chipsec.cfg.8086.common.xml.rst
-	chipsec.cfg.8086.txt.xml.rst
-	chipsec.cfg.8086.rkl.xml.rst
-	chipsec.cfg.8086.pch_3xxlp.xml.rst
-	chipsec.cfg.8086.whl.xml.rst
-	chipsec.cfg.8086.bdw.xml.rst
-	chipsec.cfg.8086.byt.xml.rst
-	chipsec.cfg.8086.avn.xml.rst
-	chipsec.cfg.8086.pch_c620.xml.rst
-	chipsec.cfg.8086.dnv.xml.rst
-	chipsec.cfg.8086.icl.xml.rst
-	chipsec.cfg.8086.tglh.xml.rst
-	chipsec.cfg.8086.pch_6xxP.xml.rst
-	chipsec.cfg.8086.pch_c60x.xml.rst
-	chipsec.cfg.8086.kbl.xml.rst
-	chipsec.cfg.8086.iommu.xml.rst
-	chipsec.cfg.8086.ivb.xml.rst
-	chipsec.cfg.8086.pch_c61x.xml.rst
-	chipsec.cfg.8086.pch_1xx.xml.rst
-	chipsec.cfg.8086.cfl.xml.rst
-	chipsec.cfg.8086.pch_4xxh.xml.rst
-	chipsec.cfg.8086.adl.xml.rst
diff --git a/_sources/modules/chipsec.cfg.8086.sfdp.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.sfdp.xml.rst.txt
deleted file mode 100644
index 428e5b54..00000000
--- a/_sources/modules/chipsec.cfg.8086.sfdp.xml.rst.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-sfdp
-========
-
-Path: chipsec\\cfg\\8086\\sfdp.xml
-
-
-XML configuration for Serial Flash Discoverable Parameter feature
-document: https://www.jedec.org/system/files/docs/JESD216D-01.pdf
-
diff --git a/_sources/modules/chipsec.cfg.8086.skl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.skl.xml.rst.txt
deleted file mode 100644
index 0d0a3cbb..00000000
--- a/_sources/modules/chipsec.cfg.8086.skl.xml.rst.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-skl
-=======
-
-Path: chipsec\\cfg\\8086\\skl.xml
-
-
-XML configuration file for Skylake based platforms
-
-http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-
-* 6th Generation Intel(R) Processor Datasheet for U/Y-Platforms
-
-* 6th Generation Intel(R) Processor I/O Datasheet for U/Y-Platforms
-
-* 6th Generation Intel(R) Processor Datasheet for S-Platforms
-
-* 6th Generation Intel(R) Processor Datasheet for H-Platforms
-
-* Intel(R) 100 Series Chipset Family Platform Controller Hub (PCH)
-
diff --git a/_sources/modules/chipsec.cfg.8086.skx.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.skx.xml.rst.txt
deleted file mode 100644
index f01831ca..00000000
--- a/_sources/modules/chipsec.cfg.8086.skx.xml.rst.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-skx
-=======
-
-Path: chipsec\\cfg\\8086\\skx.xml
-
-
-XML configuration file for Skylake/Purely Server
-Intel (c) Xeon Processor Scalable Family datasheet Vol. 2
-
diff --git a/_sources/modules/chipsec.cfg.8086.snb.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.snb.xml.rst.txt
deleted file mode 100644
index 6a9f3120..00000000
--- a/_sources/modules/chipsec.cfg.8086.snb.xml.rst.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-snb
-=======
-
-Path: chipsec\\cfg\\8086\\snb.xml
-
-
-XML configuration for Sandy Bridge based platforms
-
diff --git a/_sources/modules/chipsec.cfg.8086.tglh.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.tglh.xml.rst.txt
deleted file mode 100644
index 2cdd18e9..00000000
--- a/_sources/modules/chipsec.cfg.8086.tglh.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-tglh
-========
-
-Path: chipsec\\cfg\\8086\\tglh.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.tglu.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.tglu.xml.rst.txt
deleted file mode 100644
index 83d33a7c..00000000
--- a/_sources/modules/chipsec.cfg.8086.tglu.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-tglu
-========
-
-Path: chipsec\\cfg\\8086\\tglu.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.tpm12.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.tpm12.xml.rst.txt
deleted file mode 100644
index 75bf04dd..00000000
--- a/_sources/modules/chipsec.cfg.8086.tpm12.xml.rst.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-tpm12
-=========
-
-Path: chipsec\\cfg\\8086\\tpm12.xml
-
-
-CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
-
-This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
-
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
-
-Contact information:
-chipsec@intel.com
-
diff --git a/_sources/modules/chipsec.cfg.8086.txt.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.txt.xml.rst.txt
deleted file mode 100644
index 2534899f..00000000
--- a/_sources/modules/chipsec.cfg.8086.txt.xml.rst.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-txt
-=======
-
-Path: chipsec\\cfg\\8086\\txt.xml
-
-
-Configuration of Intel TXT register, following the guide:
-
-    Intel® Trusted Execution Technology: Software Development Guide
-    Measured Launched Environment Developer's Guide
-    August 2016
-    Revision 013
-
-from https://web.archive.org/web/20170506220426/https://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
-(and https://usermanual.wiki/Document/inteltxtsoftwaredevelopmentguide.1721028921 )
-
-Appendix B.1. (Intel® TXT Configuration Registers) details:
-
-    These registers are mapped into two regions of memory, representing the public and private configuration spaces.
-    [...]
-    The private space registers are mapped to the address range starting at FED20000H.
-    The public space registers are mapped to the address range starting at FED30000H.
-
-As chipsec usually runs in environments where the private space is not available,
-only the public space registers were described here.
-
diff --git a/_sources/modules/chipsec.cfg.8086.whl.xml.rst.txt b/_sources/modules/chipsec.cfg.8086.whl.xml.rst.txt
deleted file mode 100644
index 64dba853..00000000
--- a/_sources/modules/chipsec.cfg.8086.whl.xml.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-whl
-=======
-
-Path: chipsec\\cfg\\8086\\whl.xml
-
-
-XML configuration file for Whiskey Lake
-
-8th Generation Intel(R) Processor Family for U-Processor Platforms:
-  - https://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-  - https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/300-series-chipset-on-package-pch-datasheet-vol-1.pdf
-
diff --git a/_sources/modules/chipsec.cfg.parsers.core_parsers.rst.txt b/_sources/modules/chipsec.cfg.parsers.core_parsers.rst.txt
index cfcd3abe..c5d6b7e2 100644
--- a/_sources/modules/chipsec.cfg.parsers.core_parsers.rst.txt
+++ b/_sources/modules/chipsec.cfg.parsers.core_parsers.rst.txt
@@ -1,7 +1,7 @@
-core\_parsers module
+chipsec.cfg.parsers.core\_parsers module
 ========================================
 
 .. automodule:: chipsec.cfg.parsers.core_parsers
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.cfg.parsers.rst.txt b/_sources/modules/chipsec.cfg.parsers.rst.txt
index 46910f3c..b09339c2 100644
--- a/_sources/modules/chipsec.cfg.parsers.rst.txt
+++ b/_sources/modules/chipsec.cfg.parsers.rst.txt
@@ -1,12 +1,18 @@
-parsers package
+chipsec.cfg.parsers package
 ===========================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.cfg.parsers.core_parsers
 
+Module contents
+---------------
+
 .. automodule:: chipsec.cfg.parsers
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.config.rst.txt b/_sources/modules/chipsec.config.rst.txt
index 2af789a1..7e2863da 100644
--- a/_sources/modules/chipsec.config.rst.txt
+++ b/_sources/modules/chipsec.config.rst.txt
@@ -1,7 +1,7 @@
-config module
+chipsec.config module
 =====================
 
 .. automodule:: chipsec.config
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.fuzzing.primitives.rst.txt b/_sources/modules/chipsec.fuzzing.primitives.rst.txt
index 45d46b6f..cdfa29ec 100644
--- a/_sources/modules/chipsec.fuzzing.primitives.rst.txt
+++ b/_sources/modules/chipsec.fuzzing.primitives.rst.txt
@@ -1,7 +1,7 @@
-primitives module
+chipsec.fuzzing.primitives module
 =================================
 
 .. automodule:: chipsec.fuzzing.primitives
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.fuzzing.rst.txt b/_sources/modules/chipsec.fuzzing.rst.txt
index cd9c9592..8cfd8f0a 100644
--- a/_sources/modules/chipsec.fuzzing.rst.txt
+++ b/_sources/modules/chipsec.fuzzing.rst.txt
@@ -1,12 +1,18 @@
-fuzzing package
+chipsec.fuzzing package
 =======================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.fuzzing.primitives
 
+Module contents
+---------------
+
 .. automodule:: chipsec.fuzzing
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.acpi.rst.txt b/_sources/modules/chipsec.hal.acpi.rst.txt
index f2d8f636..6093fc46 100644
--- a/_sources/modules/chipsec.hal.acpi.rst.txt
+++ b/_sources/modules/chipsec.hal.acpi.rst.txt
@@ -1,7 +1,7 @@
-acpi module
+chipsec.hal.acpi module
 =======================
 
 .. automodule:: chipsec.hal.acpi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.acpi_tables.rst.txt b/_sources/modules/chipsec.hal.acpi_tables.rst.txt
index 2f1995d8..db8b017c 100644
--- a/_sources/modules/chipsec.hal.acpi_tables.rst.txt
+++ b/_sources/modules/chipsec.hal.acpi_tables.rst.txt
@@ -1,7 +1,7 @@
-acpi\_tables module
+chipsec.hal.acpi\_tables module
 ===============================
 
 .. automodule:: chipsec.hal.acpi_tables
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.cmos.rst.txt b/_sources/modules/chipsec.hal.cmos.rst.txt
index 866c4155..1e36dba3 100644
--- a/_sources/modules/chipsec.hal.cmos.rst.txt
+++ b/_sources/modules/chipsec.hal.cmos.rst.txt
@@ -1,7 +1,7 @@
-cmos module
+chipsec.hal.cmos module
 =======================
 
 .. automodule:: chipsec.hal.cmos
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.cpu.rst.txt b/_sources/modules/chipsec.hal.cpu.rst.txt
index 3c94f306..f2d82fd9 100644
--- a/_sources/modules/chipsec.hal.cpu.rst.txt
+++ b/_sources/modules/chipsec.hal.cpu.rst.txt
@@ -1,7 +1,7 @@
-cpu module
+chipsec.hal.cpu module
 ======================
 
 .. automodule:: chipsec.hal.cpu
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.cpuid.rst.txt b/_sources/modules/chipsec.hal.cpuid.rst.txt
index 10f2eaec..afbc056b 100644
--- a/_sources/modules/chipsec.hal.cpuid.rst.txt
+++ b/_sources/modules/chipsec.hal.cpuid.rst.txt
@@ -1,7 +1,7 @@
-cpuid module
+chipsec.hal.cpuid module
 ========================
 
 .. automodule:: chipsec.hal.cpuid
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.ec.rst.txt b/_sources/modules/chipsec.hal.ec.rst.txt
index 1c5628c2..a8f9ddc4 100644
--- a/_sources/modules/chipsec.hal.ec.rst.txt
+++ b/_sources/modules/chipsec.hal.ec.rst.txt
@@ -1,7 +1,7 @@
-ec module
+chipsec.hal.ec module
 =====================
 
 .. automodule:: chipsec.hal.ec
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.hal_base.rst.txt b/_sources/modules/chipsec.hal.hal_base.rst.txt
index 657c2356..2a18a026 100644
--- a/_sources/modules/chipsec.hal.hal_base.rst.txt
+++ b/_sources/modules/chipsec.hal.hal_base.rst.txt
@@ -1,7 +1,7 @@
-hal\_base module
+chipsec.hal.hal\_base module
 ============================
 
 .. automodule:: chipsec.hal.hal_base
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.igd.rst.txt b/_sources/modules/chipsec.hal.igd.rst.txt
index 5be424ee..897a947a 100644
--- a/_sources/modules/chipsec.hal.igd.rst.txt
+++ b/_sources/modules/chipsec.hal.igd.rst.txt
@@ -1,7 +1,7 @@
-igd module
+chipsec.hal.igd module
 ======================
 
 .. automodule:: chipsec.hal.igd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.interrupts.rst.txt b/_sources/modules/chipsec.hal.interrupts.rst.txt
index 7b9e84ac..348b5aa1 100644
--- a/_sources/modules/chipsec.hal.interrupts.rst.txt
+++ b/_sources/modules/chipsec.hal.interrupts.rst.txt
@@ -1,7 +1,7 @@
-interrupts module
+chipsec.hal.interrupts module
 =============================
 
 .. automodule:: chipsec.hal.interrupts
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.io.rst.txt b/_sources/modules/chipsec.hal.io.rst.txt
index d5fceaf4..0fb3cf14 100644
--- a/_sources/modules/chipsec.hal.io.rst.txt
+++ b/_sources/modules/chipsec.hal.io.rst.txt
@@ -1,7 +1,7 @@
-io module
+chipsec.hal.io module
 =====================
 
 .. automodule:: chipsec.hal.io
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.iobar.rst.txt b/_sources/modules/chipsec.hal.iobar.rst.txt
index 33dbf501..dc69ad7d 100644
--- a/_sources/modules/chipsec.hal.iobar.rst.txt
+++ b/_sources/modules/chipsec.hal.iobar.rst.txt
@@ -1,7 +1,7 @@
-iobar module
+chipsec.hal.iobar module
 ========================
 
 .. automodule:: chipsec.hal.iobar
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.iommu.rst.txt b/_sources/modules/chipsec.hal.iommu.rst.txt
index e1a6827f..2942cb4f 100644
--- a/_sources/modules/chipsec.hal.iommu.rst.txt
+++ b/_sources/modules/chipsec.hal.iommu.rst.txt
@@ -1,7 +1,7 @@
-iommu module
+chipsec.hal.iommu module
 ========================
 
 .. automodule:: chipsec.hal.iommu
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.locks.rst.txt b/_sources/modules/chipsec.hal.locks.rst.txt
index cccb2802..fdaebd10 100644
--- a/_sources/modules/chipsec.hal.locks.rst.txt
+++ b/_sources/modules/chipsec.hal.locks.rst.txt
@@ -1,7 +1,7 @@
-locks module
+chipsec.hal.locks module
 ========================
 
 .. automodule:: chipsec.hal.locks
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.mmio.rst.txt b/_sources/modules/chipsec.hal.mmio.rst.txt
index 05fde1cd..fe6753cd 100644
--- a/_sources/modules/chipsec.hal.mmio.rst.txt
+++ b/_sources/modules/chipsec.hal.mmio.rst.txt
@@ -1,7 +1,7 @@
-mmio module
+chipsec.hal.mmio module
 =======================
 
 .. automodule:: chipsec.hal.mmio
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.msgbus.rst.txt b/_sources/modules/chipsec.hal.msgbus.rst.txt
index e6f89fd5..2cff6ddd 100644
--- a/_sources/modules/chipsec.hal.msgbus.rst.txt
+++ b/_sources/modules/chipsec.hal.msgbus.rst.txt
@@ -1,7 +1,7 @@
-msgbus module
+chipsec.hal.msgbus module
 =========================
 
 .. automodule:: chipsec.hal.msgbus
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.msr.rst.txt b/_sources/modules/chipsec.hal.msr.rst.txt
index 2384e43a..50520ddf 100644
--- a/_sources/modules/chipsec.hal.msr.rst.txt
+++ b/_sources/modules/chipsec.hal.msr.rst.txt
@@ -1,7 +1,7 @@
-msr module
+chipsec.hal.msr module
 ======================
 
 .. automodule:: chipsec.hal.msr
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.paging.rst.txt b/_sources/modules/chipsec.hal.paging.rst.txt
index 30ae1273..21601750 100644
--- a/_sources/modules/chipsec.hal.paging.rst.txt
+++ b/_sources/modules/chipsec.hal.paging.rst.txt
@@ -1,7 +1,7 @@
-paging module
+chipsec.hal.paging module
 =========================
 
 .. automodule:: chipsec.hal.paging
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.pci.rst.txt b/_sources/modules/chipsec.hal.pci.rst.txt
index 77970812..f78f5bea 100644
--- a/_sources/modules/chipsec.hal.pci.rst.txt
+++ b/_sources/modules/chipsec.hal.pci.rst.txt
@@ -1,7 +1,7 @@
-pci module
+chipsec.hal.pci module
 ======================
 
 .. automodule:: chipsec.hal.pci
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.pcidb.rst.txt b/_sources/modules/chipsec.hal.pcidb.rst.txt
index 2bc3023a..8e89a874 100644
--- a/_sources/modules/chipsec.hal.pcidb.rst.txt
+++ b/_sources/modules/chipsec.hal.pcidb.rst.txt
@@ -1,7 +1,7 @@
-pcidb module
+chipsec.hal.pcidb module
 ========================
 
 .. automodule:: chipsec.hal.pcidb
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.physmem.rst.txt b/_sources/modules/chipsec.hal.physmem.rst.txt
index ee4fc97e..f03f9904 100644
--- a/_sources/modules/chipsec.hal.physmem.rst.txt
+++ b/_sources/modules/chipsec.hal.physmem.rst.txt
@@ -1,7 +1,7 @@
-physmem module
+chipsec.hal.physmem module
 ==========================
 
 .. automodule:: chipsec.hal.physmem
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.rst.txt b/_sources/modules/chipsec.hal.rst.txt
index ccee8194..585c0a9f 100644
--- a/_sources/modules/chipsec.hal.rst.txt
+++ b/_sources/modules/chipsec.hal.rst.txt
@@ -1,6 +1,9 @@
-hal package
+chipsec.hal package
 ===================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -44,7 +47,10 @@ hal package
    chipsec.hal.virtmem
    chipsec.hal.vmm
 
+Module contents
+---------------
+
 .. automodule:: chipsec.hal
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.smbios.rst.txt b/_sources/modules/chipsec.hal.smbios.rst.txt
index e810c4df..484ffd69 100644
--- a/_sources/modules/chipsec.hal.smbios.rst.txt
+++ b/_sources/modules/chipsec.hal.smbios.rst.txt
@@ -1,7 +1,7 @@
-smbios module
+chipsec.hal.smbios module
 =========================
 
 .. automodule:: chipsec.hal.smbios
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.smbus.rst.txt b/_sources/modules/chipsec.hal.smbus.rst.txt
index 23c98cba..ce7218b8 100644
--- a/_sources/modules/chipsec.hal.smbus.rst.txt
+++ b/_sources/modules/chipsec.hal.smbus.rst.txt
@@ -1,7 +1,7 @@
-smbus module
+chipsec.hal.smbus module
 ========================
 
 .. automodule:: chipsec.hal.smbus
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.spd.rst.txt b/_sources/modules/chipsec.hal.spd.rst.txt
index 30dbc912..923426f7 100644
--- a/_sources/modules/chipsec.hal.spd.rst.txt
+++ b/_sources/modules/chipsec.hal.spd.rst.txt
@@ -1,7 +1,7 @@
-spd module
+chipsec.hal.spd module
 ======================
 
 .. automodule:: chipsec.hal.spd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.spi.rst.txt b/_sources/modules/chipsec.hal.spi.rst.txt
index 2d741712..4dec6282 100644
--- a/_sources/modules/chipsec.hal.spi.rst.txt
+++ b/_sources/modules/chipsec.hal.spi.rst.txt
@@ -1,7 +1,7 @@
-spi module
+chipsec.hal.spi module
 ======================
 
 .. automodule:: chipsec.hal.spi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.spi_descriptor.rst.txt b/_sources/modules/chipsec.hal.spi_descriptor.rst.txt
index cd93cca8..d11106d4 100644
--- a/_sources/modules/chipsec.hal.spi_descriptor.rst.txt
+++ b/_sources/modules/chipsec.hal.spi_descriptor.rst.txt
@@ -1,7 +1,7 @@
-spi\_descriptor module
+chipsec.hal.spi\_descriptor module
 ==================================
 
 .. automodule:: chipsec.hal.spi_descriptor
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.spi_jedec_ids.rst.txt b/_sources/modules/chipsec.hal.spi_jedec_ids.rst.txt
index c1d475c9..9069e7ba 100644
--- a/_sources/modules/chipsec.hal.spi_jedec_ids.rst.txt
+++ b/_sources/modules/chipsec.hal.spi_jedec_ids.rst.txt
@@ -1,7 +1,7 @@
-spi\_jedec\_ids module
+chipsec.hal.spi\_jedec\_ids module
 ==================================
 
 .. automodule:: chipsec.hal.spi_jedec_ids
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.spi_uefi.rst.txt b/_sources/modules/chipsec.hal.spi_uefi.rst.txt
index 8af4d1e4..bc19f58b 100644
--- a/_sources/modules/chipsec.hal.spi_uefi.rst.txt
+++ b/_sources/modules/chipsec.hal.spi_uefi.rst.txt
@@ -1,7 +1,7 @@
-spi\_uefi module
+chipsec.hal.spi\_uefi module
 ============================
 
 .. automodule:: chipsec.hal.spi_uefi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.tpm.rst.txt b/_sources/modules/chipsec.hal.tpm.rst.txt
index 2ca5f5b5..dbd24355 100644
--- a/_sources/modules/chipsec.hal.tpm.rst.txt
+++ b/_sources/modules/chipsec.hal.tpm.rst.txt
@@ -1,7 +1,7 @@
-tpm module
+chipsec.hal.tpm module
 ======================
 
 .. automodule:: chipsec.hal.tpm
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.tpm12_commands.rst.txt b/_sources/modules/chipsec.hal.tpm12_commands.rst.txt
index 1c6bca4c..3d5694c6 100644
--- a/_sources/modules/chipsec.hal.tpm12_commands.rst.txt
+++ b/_sources/modules/chipsec.hal.tpm12_commands.rst.txt
@@ -1,7 +1,7 @@
-tpm12\_commands module
+chipsec.hal.tpm12\_commands module
 ==================================
 
 .. automodule:: chipsec.hal.tpm12_commands
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.tpm_eventlog.rst.txt b/_sources/modules/chipsec.hal.tpm_eventlog.rst.txt
index aa291760..8e74c944 100644
--- a/_sources/modules/chipsec.hal.tpm_eventlog.rst.txt
+++ b/_sources/modules/chipsec.hal.tpm_eventlog.rst.txt
@@ -1,7 +1,7 @@
-tpm\_eventlog module
+chipsec.hal.tpm\_eventlog module
 ================================
 
 .. automodule:: chipsec.hal.tpm_eventlog
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.ucode.rst.txt b/_sources/modules/chipsec.hal.ucode.rst.txt
index 51a80e7b..f4cf60f4 100644
--- a/_sources/modules/chipsec.hal.ucode.rst.txt
+++ b/_sources/modules/chipsec.hal.ucode.rst.txt
@@ -1,7 +1,7 @@
-ucode module
+chipsec.hal.ucode module
 ========================
 
 .. automodule:: chipsec.hal.ucode
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi.rst.txt b/_sources/modules/chipsec.hal.uefi.rst.txt
index 4a79fe0e..e40371ee 100644
--- a/_sources/modules/chipsec.hal.uefi.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi.rst.txt
@@ -1,7 +1,7 @@
-uefi module
+chipsec.hal.uefi module
 =======================
 
 .. automodule:: chipsec.hal.uefi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi_common.rst.txt b/_sources/modules/chipsec.hal.uefi_common.rst.txt
index a1b5b579..7a13eb24 100644
--- a/_sources/modules/chipsec.hal.uefi_common.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi_common.rst.txt
@@ -1,7 +1,7 @@
-uefi\_common module
+chipsec.hal.uefi\_common module
 ===============================
 
 .. automodule:: chipsec.hal.uefi_common
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi_compression.rst.txt b/_sources/modules/chipsec.hal.uefi_compression.rst.txt
index 469c67bd..5376831e 100644
--- a/_sources/modules/chipsec.hal.uefi_compression.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi_compression.rst.txt
@@ -1,7 +1,7 @@
-uefi\_compression module
+chipsec.hal.uefi\_compression module
 ====================================
 
 .. automodule:: chipsec.hal.uefi_compression
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi_fv.rst.txt b/_sources/modules/chipsec.hal.uefi_fv.rst.txt
index e4d72d7b..59b884d3 100644
--- a/_sources/modules/chipsec.hal.uefi_fv.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi_fv.rst.txt
@@ -1,7 +1,7 @@
-uefi\_fv module
+chipsec.hal.uefi\_fv module
 ===========================
 
 .. automodule:: chipsec.hal.uefi_fv
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi_platform.rst.txt b/_sources/modules/chipsec.hal.uefi_platform.rst.txt
index c68e8063..79b5c0ec 100644
--- a/_sources/modules/chipsec.hal.uefi_platform.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi_platform.rst.txt
@@ -1,7 +1,7 @@
-uefi\_platform module
+chipsec.hal.uefi\_platform module
 =================================
 
 .. automodule:: chipsec.hal.uefi_platform
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.uefi_search.rst.txt b/_sources/modules/chipsec.hal.uefi_search.rst.txt
index 9344f15f..5c2768ac 100644
--- a/_sources/modules/chipsec.hal.uefi_search.rst.txt
+++ b/_sources/modules/chipsec.hal.uefi_search.rst.txt
@@ -1,7 +1,7 @@
-uefi\_search module
+chipsec.hal.uefi\_search module
 ===============================
 
 .. automodule:: chipsec.hal.uefi_search
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.virtmem.rst.txt b/_sources/modules/chipsec.hal.virtmem.rst.txt
index 6d2203f7..cd517e52 100644
--- a/_sources/modules/chipsec.hal.virtmem.rst.txt
+++ b/_sources/modules/chipsec.hal.virtmem.rst.txt
@@ -1,7 +1,7 @@
-virtmem module
+chipsec.hal.virtmem module
 ==========================
 
 .. automodule:: chipsec.hal.virtmem
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.hal.vmm.rst.txt b/_sources/modules/chipsec.hal.vmm.rst.txt
index 399d06dd..0ed2825f 100644
--- a/_sources/modules/chipsec.hal.vmm.rst.txt
+++ b/_sources/modules/chipsec.hal.vmm.rst.txt
@@ -1,7 +1,7 @@
-vmm module
+chipsec.hal.vmm module
 ======================
 
 .. automodule:: chipsec.hal.vmm
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.basehelper.rst.txt b/_sources/modules/chipsec.helper.basehelper.rst.txt
index f466ba9b..d2a73fa4 100644
--- a/_sources/modules/chipsec.helper.basehelper.rst.txt
+++ b/_sources/modules/chipsec.helper.basehelper.rst.txt
@@ -1,7 +1,7 @@
-basehelper module
+chipsec.helper.basehelper module
 ================================
 
 .. automodule:: chipsec.helper.basehelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.dal.dalhelper.rst.txt b/_sources/modules/chipsec.helper.dal.dalhelper.rst.txt
index 6fffb10a..5614f1f1 100644
--- a/_sources/modules/chipsec.helper.dal.dalhelper.rst.txt
+++ b/_sources/modules/chipsec.helper.dal.dalhelper.rst.txt
@@ -1,7 +1,7 @@
-dalhelper module
+chipsec.helper.dal.dalhelper module
 ===================================
 
 .. automodule:: chipsec.helper.dal.dalhelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.dal.rst.txt b/_sources/modules/chipsec.helper.dal.rst.txt
index 00d2ac49..4bbaa5f6 100644
--- a/_sources/modules/chipsec.helper.dal.rst.txt
+++ b/_sources/modules/chipsec.helper.dal.rst.txt
@@ -1,12 +1,18 @@
-dal package
+chipsec.helper.dal package
 ==========================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.helper.dal.dalhelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper.dal
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.efi.efihelper.rst.txt b/_sources/modules/chipsec.helper.efi.efihelper.rst.txt
index 48428a9f..5e9ee6dc 100644
--- a/_sources/modules/chipsec.helper.efi.efihelper.rst.txt
+++ b/_sources/modules/chipsec.helper.efi.efihelper.rst.txt
@@ -1,7 +1,7 @@
-efihelper module
+chipsec.helper.efi.efihelper module
 ===================================
 
 .. automodule:: chipsec.helper.efi.efihelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.efi.rst.txt b/_sources/modules/chipsec.helper.efi.rst.txt
index 80ba3717..7bd2114f 100644
--- a/_sources/modules/chipsec.helper.efi.rst.txt
+++ b/_sources/modules/chipsec.helper.efi.rst.txt
@@ -1,12 +1,18 @@
-efi package
+chipsec.helper.efi package
 ==========================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.helper.efi.efihelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper.efi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linux.linuxhelper.rst.txt b/_sources/modules/chipsec.helper.linux.linuxhelper.rst.txt
index b2c045b4..a91d7f17 100644
--- a/_sources/modules/chipsec.helper.linux.linuxhelper.rst.txt
+++ b/_sources/modules/chipsec.helper.linux.linuxhelper.rst.txt
@@ -1,7 +1,7 @@
-linuxhelper module
+chipsec.helper.linux.linuxhelper module
 =======================================
 
 .. automodule:: chipsec.helper.linux.linuxhelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linux.rst.txt b/_sources/modules/chipsec.helper.linux.rst.txt
index 947c537f..f2d37f8c 100644
--- a/_sources/modules/chipsec.helper.linux.rst.txt
+++ b/_sources/modules/chipsec.helper.linux.rst.txt
@@ -1,12 +1,18 @@
-linux package
+chipsec.helper.linux package
 ============================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.helper.linux.linuxhelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper.linux
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linuxnative.cpuid.rst.txt b/_sources/modules/chipsec.helper.linuxnative.cpuid.rst.txt
index 9d0f6ddd..27fc912e 100644
--- a/_sources/modules/chipsec.helper.linuxnative.cpuid.rst.txt
+++ b/_sources/modules/chipsec.helper.linuxnative.cpuid.rst.txt
@@ -1,7 +1,7 @@
-cpuid module
+chipsec.helper.linuxnative.cpuid module
 =======================================
 
 .. automodule:: chipsec.helper.linuxnative.cpuid
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linuxnative.legacy_pci.rst.txt b/_sources/modules/chipsec.helper.linuxnative.legacy_pci.rst.txt
index 84e49a01..c3808c03 100644
--- a/_sources/modules/chipsec.helper.linuxnative.legacy_pci.rst.txt
+++ b/_sources/modules/chipsec.helper.linuxnative.legacy_pci.rst.txt
@@ -1,7 +1,7 @@
-legacy\_pci module
+chipsec.helper.linuxnative.legacy\_pci module
 =============================================
 
 .. automodule:: chipsec.helper.linuxnative.legacy_pci
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linuxnative.linuxnativehelper.rst.txt b/_sources/modules/chipsec.helper.linuxnative.linuxnativehelper.rst.txt
index 1a668dc6..f9d39e6a 100644
--- a/_sources/modules/chipsec.helper.linuxnative.linuxnativehelper.rst.txt
+++ b/_sources/modules/chipsec.helper.linuxnative.linuxnativehelper.rst.txt
@@ -1,7 +1,7 @@
-linuxnativehelper module
+chipsec.helper.linuxnative.linuxnativehelper module
 ===================================================
 
 .. automodule:: chipsec.helper.linuxnative.linuxnativehelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.linuxnative.rst.txt b/_sources/modules/chipsec.helper.linuxnative.rst.txt
index 463e5e4f..f36813e6 100644
--- a/_sources/modules/chipsec.helper.linuxnative.rst.txt
+++ b/_sources/modules/chipsec.helper.linuxnative.rst.txt
@@ -1,6 +1,9 @@
-linuxnative package
+chipsec.helper.linuxnative package
 ==================================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -8,7 +11,10 @@ linuxnative package
    chipsec.helper.linuxnative.legacy_pci
    chipsec.helper.linuxnative.linuxnativehelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper.linuxnative
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.nonehelper.rst.txt b/_sources/modules/chipsec.helper.nonehelper.rst.txt
index 9e60f46d..312ec31f 100644
--- a/_sources/modules/chipsec.helper.nonehelper.rst.txt
+++ b/_sources/modules/chipsec.helper.nonehelper.rst.txt
@@ -1,7 +1,7 @@
-nonehelper module
+chipsec.helper.nonehelper module
 ================================
 
 .. automodule:: chipsec.helper.nonehelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.oshelper.rst.txt b/_sources/modules/chipsec.helper.oshelper.rst.txt
index e09dda81..28978eb3 100644
--- a/_sources/modules/chipsec.helper.oshelper.rst.txt
+++ b/_sources/modules/chipsec.helper.oshelper.rst.txt
@@ -1,7 +1,7 @@
-oshelper module
+chipsec.helper.oshelper module
 ==============================
 
 .. automodule:: chipsec.helper.oshelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.rst.txt b/_sources/modules/chipsec.helper.rst.txt
index 22336f1f..39b5f301 100644
--- a/_sources/modules/chipsec.helper.rst.txt
+++ b/_sources/modules/chipsec.helper.rst.txt
@@ -1,6 +1,9 @@
-helper package
+chipsec.helper package
 ======================
 
+Subpackages
+-----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -10,6 +13,9 @@ helper package
    chipsec.helper.linuxnative
    chipsec.helper.windows
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -17,7 +23,10 @@ helper package
    chipsec.helper.nonehelper
    chipsec.helper.oshelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.windows.rst.txt b/_sources/modules/chipsec.helper.windows.rst.txt
index edc252ab..4850248d 100644
--- a/_sources/modules/chipsec.helper.windows.rst.txt
+++ b/_sources/modules/chipsec.helper.windows.rst.txt
@@ -1,12 +1,18 @@
-windows package
+chipsec.helper.windows package
 ==============================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.helper.windows.windowshelper
 
+Module contents
+---------------
+
 .. automodule:: chipsec.helper.windows
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.helper.windows.windowshelper.rst.txt b/_sources/modules/chipsec.helper.windows.windowshelper.rst.txt
index 55f8dc37..00a6cef1 100644
--- a/_sources/modules/chipsec.helper.windows.windowshelper.rst.txt
+++ b/_sources/modules/chipsec.helper.windows.windowshelper.rst.txt
@@ -1,7 +1,7 @@
-windowshelper module
+chipsec.helper.windows.windowshelper module
 ===========================================
 
 .. automodule:: chipsec.helper.windows.windowshelper
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.architecture.rst.txt b/_sources/modules/chipsec.library.architecture.rst.txt
index 291e8b9c..1dd753fe 100644
--- a/_sources/modules/chipsec.library.architecture.rst.txt
+++ b/_sources/modules/chipsec.library.architecture.rst.txt
@@ -1,7 +1,7 @@
-architecture module
+chipsec.library.architecture module
 ===================================
 
 .. automodule:: chipsec.library.architecture
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.bits.rst.txt b/_sources/modules/chipsec.library.bits.rst.txt
index b4bf12bb..7eca8e04 100644
--- a/_sources/modules/chipsec.library.bits.rst.txt
+++ b/_sources/modules/chipsec.library.bits.rst.txt
@@ -1,7 +1,7 @@
-bits module
+chipsec.library.bits module
 ===========================
 
 .. automodule:: chipsec.library.bits
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.memory.rst.txt b/_sources/modules/chipsec.library.memory.rst.txt
index 903bb829..1d888656 100644
--- a/_sources/modules/chipsec.library.memory.rst.txt
+++ b/_sources/modules/chipsec.library.memory.rst.txt
@@ -1,7 +1,7 @@
-memory module
+chipsec.library.memory module
 =============================
 
 .. automodule:: chipsec.library.memory
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.rst.txt b/_sources/modules/chipsec.library.rst.txt
index 57d756b6..44b29181 100644
--- a/_sources/modules/chipsec.library.rst.txt
+++ b/_sources/modules/chipsec.library.rst.txt
@@ -1,6 +1,9 @@
-library package
+chipsec.library package
 =======================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -11,7 +14,10 @@ library package
    chipsec.library.structs
    chipsec.library.types
 
+Module contents
+---------------
+
 .. automodule:: chipsec.library
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.strings.rst.txt b/_sources/modules/chipsec.library.strings.rst.txt
index 6f7783f9..c3d7965e 100644
--- a/_sources/modules/chipsec.library.strings.rst.txt
+++ b/_sources/modules/chipsec.library.strings.rst.txt
@@ -1,7 +1,7 @@
-strings module
+chipsec.library.strings module
 ==============================
 
 .. automodule:: chipsec.library.strings
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.structs.rst.txt b/_sources/modules/chipsec.library.structs.rst.txt
index 033528f7..126f439b 100644
--- a/_sources/modules/chipsec.library.structs.rst.txt
+++ b/_sources/modules/chipsec.library.structs.rst.txt
@@ -1,7 +1,7 @@
-structs module
+chipsec.library.structs module
 ==============================
 
 .. automodule:: chipsec.library.structs
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.library.types.rst.txt b/_sources/modules/chipsec.library.types.rst.txt
index 33f1d1fd..817c15ce 100644
--- a/_sources/modules/chipsec.library.types.rst.txt
+++ b/_sources/modules/chipsec.library.types.rst.txt
@@ -1,7 +1,7 @@
-types module
+chipsec.library.types module
 ============================
 
 .. automodule:: chipsec.library.types
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.bdw.rst.txt b/_sources/modules/chipsec.modules.bdw.rst.txt
index 2c56f591..f8d7a0d7 100644
--- a/_sources/modules/chipsec.modules.bdw.rst.txt
+++ b/_sources/modules/chipsec.modules.bdw.rst.txt
@@ -1,7 +1,10 @@
-bdw package
+chipsec.modules.bdw package
 ===========================
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.bdw
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.byt.rst.txt b/_sources/modules/chipsec.modules.byt.rst.txt
index cb737571..9b6c965f 100644
--- a/_sources/modules/chipsec.modules.byt.rst.txt
+++ b/_sources/modules/chipsec.modules.byt.rst.txt
@@ -1,7 +1,10 @@
-byt package
+chipsec.modules.byt package
 ===========================
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.byt
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.bios_kbrd_buffer.rst.txt b/_sources/modules/chipsec.modules.common.bios_kbrd_buffer.rst.txt
index 964c12b5..218cd57a 100644
--- a/_sources/modules/chipsec.modules.common.bios_kbrd_buffer.rst.txt
+++ b/_sources/modules/chipsec.modules.common.bios_kbrd_buffer.rst.txt
@@ -1,7 +1,7 @@
-bios\_kbrd\_buffer module
+chipsec.modules.common.bios\_kbrd\_buffer module
 ================================================
 
 .. automodule:: chipsec.modules.common.bios_kbrd_buffer
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.bios_smi.rst.txt b/_sources/modules/chipsec.modules.common.bios_smi.rst.txt
index 2b50e670..cf2d7ba3 100644
--- a/_sources/modules/chipsec.modules.common.bios_smi.rst.txt
+++ b/_sources/modules/chipsec.modules.common.bios_smi.rst.txt
@@ -1,7 +1,7 @@
-bios\_smi module
+chipsec.modules.common.bios\_smi module
 =======================================
 
 .. automodule:: chipsec.modules.common.bios_smi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.bios_ts.rst.txt b/_sources/modules/chipsec.modules.common.bios_ts.rst.txt
index d8077fb1..7fc9e0b8 100644
--- a/_sources/modules/chipsec.modules.common.bios_ts.rst.txt
+++ b/_sources/modules/chipsec.modules.common.bios_ts.rst.txt
@@ -1,7 +1,7 @@
-bios\_ts module
+chipsec.modules.common.bios\_ts module
 ======================================
 
 .. automodule:: chipsec.modules.common.bios_ts
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.bios_wp.rst.txt b/_sources/modules/chipsec.modules.common.bios_wp.rst.txt
index 41966eea..5b724cad 100644
--- a/_sources/modules/chipsec.modules.common.bios_wp.rst.txt
+++ b/_sources/modules/chipsec.modules.common.bios_wp.rst.txt
@@ -1,7 +1,7 @@
-bios\_wp module
+chipsec.modules.common.bios\_wp module
 ======================================
 
 .. automodule:: chipsec.modules.common.bios_wp
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.cet.rst.txt b/_sources/modules/chipsec.modules.common.cet.rst.txt
index 6c686aba..ab4c3ebe 100644
--- a/_sources/modules/chipsec.modules.common.cet.rst.txt
+++ b/_sources/modules/chipsec.modules.common.cet.rst.txt
@@ -1,7 +1,7 @@
-cet module
+chipsec.modules.common.cet module
 =================================
 
 .. automodule:: chipsec.modules.common.cet
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.cpu.cpu_info.rst.txt b/_sources/modules/chipsec.modules.common.cpu.cpu_info.rst.txt
index 39d62a44..16a7606a 100644
--- a/_sources/modules/chipsec.modules.common.cpu.cpu_info.rst.txt
+++ b/_sources/modules/chipsec.modules.common.cpu.cpu_info.rst.txt
@@ -1,7 +1,7 @@
-cpu\_info module
+chipsec.modules.common.cpu.cpu\_info module
 ===========================================
 
 .. automodule:: chipsec.modules.common.cpu.cpu_info
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.cpu.ia_untrusted.rst.txt b/_sources/modules/chipsec.modules.common.cpu.ia_untrusted.rst.txt
index fbb8d1b4..3b3c51c3 100644
--- a/_sources/modules/chipsec.modules.common.cpu.ia_untrusted.rst.txt
+++ b/_sources/modules/chipsec.modules.common.cpu.ia_untrusted.rst.txt
@@ -1,7 +1,7 @@
-ia\_untrusted module
+chipsec.modules.common.cpu.ia\_untrusted module
 ===============================================
 
 .. automodule:: chipsec.modules.common.cpu.ia_untrusted
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.cpu.rst.txt b/_sources/modules/chipsec.modules.common.cpu.rst.txt
index 28712bd8..07b01d20 100644
--- a/_sources/modules/chipsec.modules.common.cpu.rst.txt
+++ b/_sources/modules/chipsec.modules.common.cpu.rst.txt
@@ -1,6 +1,9 @@
-cpu package
+chipsec.modules.common.cpu package
 ==================================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -8,7 +11,10 @@ cpu package
    chipsec.modules.common.cpu.ia_untrusted
    chipsec.modules.common.cpu.spectre_v2
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.common.cpu
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.cpu.spectre_v2.rst.txt b/_sources/modules/chipsec.modules.common.cpu.spectre_v2.rst.txt
index 9f740390..0d7c6f2a 100644
--- a/_sources/modules/chipsec.modules.common.cpu.spectre_v2.rst.txt
+++ b/_sources/modules/chipsec.modules.common.cpu.spectre_v2.rst.txt
@@ -1,7 +1,7 @@
-spectre\_v2 module
+chipsec.modules.common.cpu.spectre\_v2 module
 =============================================
 
 .. automodule:: chipsec.modules.common.cpu.spectre_v2
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.debugenabled.rst.txt b/_sources/modules/chipsec.modules.common.debugenabled.rst.txt
index a5a15500..5c4ef45f 100644
--- a/_sources/modules/chipsec.modules.common.debugenabled.rst.txt
+++ b/_sources/modules/chipsec.modules.common.debugenabled.rst.txt
@@ -1,7 +1,7 @@
-debugenabled module
+chipsec.modules.common.debugenabled module
 ==========================================
 
 .. automodule:: chipsec.modules.common.debugenabled
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.ia32cfg.rst.txt b/_sources/modules/chipsec.modules.common.ia32cfg.rst.txt
index 6580abbc..fe541477 100644
--- a/_sources/modules/chipsec.modules.common.ia32cfg.rst.txt
+++ b/_sources/modules/chipsec.modules.common.ia32cfg.rst.txt
@@ -1,7 +1,7 @@
-ia32cfg module
+chipsec.modules.common.ia32cfg module
 =====================================
 
 .. automodule:: chipsec.modules.common.ia32cfg
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.me_mfg_mode.rst.txt b/_sources/modules/chipsec.modules.common.me_mfg_mode.rst.txt
index c642e591..c44fb0f8 100644
--- a/_sources/modules/chipsec.modules.common.me_mfg_mode.rst.txt
+++ b/_sources/modules/chipsec.modules.common.me_mfg_mode.rst.txt
@@ -1,7 +1,7 @@
-me\_mfg\_mode module
+chipsec.modules.common.me\_mfg\_mode module
 ===========================================
 
 .. automodule:: chipsec.modules.common.me_mfg_mode
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.memconfig.rst.txt b/_sources/modules/chipsec.modules.common.memconfig.rst.txt
index 19f61cf7..a2308279 100644
--- a/_sources/modules/chipsec.modules.common.memconfig.rst.txt
+++ b/_sources/modules/chipsec.modules.common.memconfig.rst.txt
@@ -1,7 +1,7 @@
-memconfig module
+chipsec.modules.common.memconfig module
 =======================================
 
 .. automodule:: chipsec.modules.common.memconfig
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.memlock.rst.txt b/_sources/modules/chipsec.modules.common.memlock.rst.txt
index ae8d68b5..410d8d71 100644
--- a/_sources/modules/chipsec.modules.common.memlock.rst.txt
+++ b/_sources/modules/chipsec.modules.common.memlock.rst.txt
@@ -1,7 +1,7 @@
-memlock module
+chipsec.modules.common.memlock module
 =====================================
 
 .. automodule:: chipsec.modules.common.memlock
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.remap.rst.txt b/_sources/modules/chipsec.modules.common.remap.rst.txt
index 7af23ea3..34bd0f69 100644
--- a/_sources/modules/chipsec.modules.common.remap.rst.txt
+++ b/_sources/modules/chipsec.modules.common.remap.rst.txt
@@ -1,7 +1,7 @@
-remap module
+chipsec.modules.common.remap module
 ===================================
 
 .. automodule:: chipsec.modules.common.remap
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.rst.txt b/_sources/modules/chipsec.modules.common.rst.txt
index c4a6b160..8c9283fc 100644
--- a/_sources/modules/chipsec.modules.common.rst.txt
+++ b/_sources/modules/chipsec.modules.common.rst.txt
@@ -1,6 +1,9 @@
-common package
+chipsec.modules.common package
 ==============================
 
+Subpackages
+-----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -8,6 +11,9 @@ common package
    chipsec.modules.common.secureboot
    chipsec.modules.common.uefi
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -34,7 +40,10 @@ common package
    chipsec.modules.common.spi_fdopss
    chipsec.modules.common.spi_lock
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.common
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.rtclock.rst.txt b/_sources/modules/chipsec.modules.common.rtclock.rst.txt
index afd19782..29f35d0e 100644
--- a/_sources/modules/chipsec.modules.common.rtclock.rst.txt
+++ b/_sources/modules/chipsec.modules.common.rtclock.rst.txt
@@ -1,7 +1,7 @@
-rtclock module
+chipsec.modules.common.rtclock module
 =====================================
 
 .. automodule:: chipsec.modules.common.rtclock
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.secureboot.rst.txt b/_sources/modules/chipsec.modules.common.secureboot.rst.txt
index 4cfce71a..797ca7d6 100644
--- a/_sources/modules/chipsec.modules.common.secureboot.rst.txt
+++ b/_sources/modules/chipsec.modules.common.secureboot.rst.txt
@@ -1,12 +1,18 @@
-secureboot package
+chipsec.modules.common.secureboot package
 =========================================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.modules.common.secureboot.variables
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.common.secureboot
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.secureboot.variables.rst.txt b/_sources/modules/chipsec.modules.common.secureboot.variables.rst.txt
index c31b0f7d..834e1b51 100644
--- a/_sources/modules/chipsec.modules.common.secureboot.variables.rst.txt
+++ b/_sources/modules/chipsec.modules.common.secureboot.variables.rst.txt
@@ -1,7 +1,7 @@
-variables module
+chipsec.modules.common.secureboot.variables module
 ==================================================
 
 .. automodule:: chipsec.modules.common.secureboot.variables
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.sgx_check.rst.txt b/_sources/modules/chipsec.modules.common.sgx_check.rst.txt
index 7185c42b..5f0bcd6b 100644
--- a/_sources/modules/chipsec.modules.common.sgx_check.rst.txt
+++ b/_sources/modules/chipsec.modules.common.sgx_check.rst.txt
@@ -1,7 +1,7 @@
-sgx\_check module
+chipsec.modules.common.sgx\_check module
 ========================================
 
 .. automodule:: chipsec.modules.common.sgx_check
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.smm.rst.txt b/_sources/modules/chipsec.modules.common.smm.rst.txt
index e57c3179..05e9ed0f 100644
--- a/_sources/modules/chipsec.modules.common.smm.rst.txt
+++ b/_sources/modules/chipsec.modules.common.smm.rst.txt
@@ -1,7 +1,7 @@
-smm module
+chipsec.modules.common.smm module
 =================================
 
 .. automodule:: chipsec.modules.common.smm
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.smm_code_chk.rst.txt b/_sources/modules/chipsec.modules.common.smm_code_chk.rst.txt
index 8ce4b7cf..980966ac 100644
--- a/_sources/modules/chipsec.modules.common.smm_code_chk.rst.txt
+++ b/_sources/modules/chipsec.modules.common.smm_code_chk.rst.txt
@@ -1,7 +1,7 @@
-smm\_code\_chk module
+chipsec.modules.common.smm\_code\_chk module
 ============================================
 
 .. automodule:: chipsec.modules.common.smm_code_chk
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.smm_dma.rst.txt b/_sources/modules/chipsec.modules.common.smm_dma.rst.txt
index dae256fc..1292aed4 100644
--- a/_sources/modules/chipsec.modules.common.smm_dma.rst.txt
+++ b/_sources/modules/chipsec.modules.common.smm_dma.rst.txt
@@ -1,7 +1,7 @@
-smm\_dma module
+chipsec.modules.common.smm\_dma module
 ======================================
 
 .. automodule:: chipsec.modules.common.smm_dma
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.smrr.rst.txt b/_sources/modules/chipsec.modules.common.smrr.rst.txt
index 716bb5ff..57d0150d 100644
--- a/_sources/modules/chipsec.modules.common.smrr.rst.txt
+++ b/_sources/modules/chipsec.modules.common.smrr.rst.txt
@@ -1,7 +1,7 @@
-smrr module
+chipsec.modules.common.smrr module
 ==================================
 
 .. automodule:: chipsec.modules.common.smrr
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.spd_wd.rst.txt b/_sources/modules/chipsec.modules.common.spd_wd.rst.txt
index 6dcaa3e4..ab7103f5 100644
--- a/_sources/modules/chipsec.modules.common.spd_wd.rst.txt
+++ b/_sources/modules/chipsec.modules.common.spd_wd.rst.txt
@@ -1,7 +1,7 @@
-spd\_wd module
+chipsec.modules.common.spd\_wd module
 =====================================
 
 .. automodule:: chipsec.modules.common.spd_wd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.spi_access.rst.txt b/_sources/modules/chipsec.modules.common.spi_access.rst.txt
index ee67f04f..a17e686b 100644
--- a/_sources/modules/chipsec.modules.common.spi_access.rst.txt
+++ b/_sources/modules/chipsec.modules.common.spi_access.rst.txt
@@ -1,7 +1,7 @@
-spi\_access module
+chipsec.modules.common.spi\_access module
 =========================================
 
 .. automodule:: chipsec.modules.common.spi_access
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.spi_desc.rst.txt b/_sources/modules/chipsec.modules.common.spi_desc.rst.txt
index 8488f237..9fab3430 100644
--- a/_sources/modules/chipsec.modules.common.spi_desc.rst.txt
+++ b/_sources/modules/chipsec.modules.common.spi_desc.rst.txt
@@ -1,7 +1,7 @@
-spi\_desc module
+chipsec.modules.common.spi\_desc module
 =======================================
 
 .. automodule:: chipsec.modules.common.spi_desc
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.spi_fdopss.rst.txt b/_sources/modules/chipsec.modules.common.spi_fdopss.rst.txt
index 5dcd1ead..765a7430 100644
--- a/_sources/modules/chipsec.modules.common.spi_fdopss.rst.txt
+++ b/_sources/modules/chipsec.modules.common.spi_fdopss.rst.txt
@@ -1,7 +1,7 @@
-spi\_fdopss module
+chipsec.modules.common.spi\_fdopss module
 =========================================
 
 .. automodule:: chipsec.modules.common.spi_fdopss
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.spi_lock.rst.txt b/_sources/modules/chipsec.modules.common.spi_lock.rst.txt
index c3509154..9d0f1ba8 100644
--- a/_sources/modules/chipsec.modules.common.spi_lock.rst.txt
+++ b/_sources/modules/chipsec.modules.common.spi_lock.rst.txt
@@ -1,7 +1,7 @@
-spi\_lock module
+chipsec.modules.common.spi\_lock module
 =======================================
 
 .. automodule:: chipsec.modules.common.spi_lock
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.uefi.access_uefispec.rst.txt b/_sources/modules/chipsec.modules.common.uefi.access_uefispec.rst.txt
index b6803eaa..277e0dcc 100644
--- a/_sources/modules/chipsec.modules.common.uefi.access_uefispec.rst.txt
+++ b/_sources/modules/chipsec.modules.common.uefi.access_uefispec.rst.txt
@@ -1,7 +1,7 @@
-access\_uefispec module
+chipsec.modules.common.uefi.access\_uefispec module
 ===================================================
 
 .. automodule:: chipsec.modules.common.uefi.access_uefispec
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.uefi.rst.txt b/_sources/modules/chipsec.modules.common.uefi.rst.txt
index a50f9864..8ba126b2 100644
--- a/_sources/modules/chipsec.modules.common.uefi.rst.txt
+++ b/_sources/modules/chipsec.modules.common.uefi.rst.txt
@@ -1,13 +1,19 @@
-uefi package
+chipsec.modules.common.uefi package
 ===================================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
    chipsec.modules.common.uefi.access_uefispec
    chipsec.modules.common.uefi.s3bootscript
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.common.uefi
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.common.uefi.s3bootscript.rst.txt b/_sources/modules/chipsec.modules.common.uefi.s3bootscript.rst.txt
index af4654d5..fe361a8a 100644
--- a/_sources/modules/chipsec.modules.common.uefi.s3bootscript.rst.txt
+++ b/_sources/modules/chipsec.modules.common.uefi.s3bootscript.rst.txt
@@ -1,7 +1,7 @@
-s3bootscript module
+chipsec.modules.common.uefi.s3bootscript module
 ===============================================
 
 .. automodule:: chipsec.modules.common.uefi.s3bootscript
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.hsw.rst.txt b/_sources/modules/chipsec.modules.hsw.rst.txt
index 784d416e..58be5a95 100644
--- a/_sources/modules/chipsec.modules.hsw.rst.txt
+++ b/_sources/modules/chipsec.modules.hsw.rst.txt
@@ -1,7 +1,10 @@
-hsw package
+chipsec.modules.hsw package
 ===========================
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.hsw
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.ivb.rst.txt b/_sources/modules/chipsec.modules.ivb.rst.txt
index eeb2222b..241535ea 100644
--- a/_sources/modules/chipsec.modules.ivb.rst.txt
+++ b/_sources/modules/chipsec.modules.ivb.rst.txt
@@ -1,7 +1,10 @@
-ivb package
+chipsec.modules.ivb package
 ===========================
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.ivb
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.rst.txt b/_sources/modules/chipsec.modules.rst.txt
index 78e665c8..f4450f65 100644
--- a/_sources/modules/chipsec.modules.rst.txt
+++ b/_sources/modules/chipsec.modules.rst.txt
@@ -1,6 +1,9 @@
-modules package
+chipsec.modules package
 =======================
 
+Subpackages
+-----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -10,9 +13,11 @@ modules package
    chipsec.modules.hsw
    chipsec.modules.ivb
    chipsec.modules.snb
-   chipsec.modules.tools
+
+Module contents
+---------------
 
 .. automodule:: chipsec.modules
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.snb.rst.txt b/_sources/modules/chipsec.modules.snb.rst.txt
index a77a62ba..98fd46c4 100644
--- a/_sources/modules/chipsec.modules.snb.rst.txt
+++ b/_sources/modules/chipsec.modules.snb.rst.txt
@@ -1,7 +1,10 @@
-snb package
+chipsec.modules.snb package
 ===========================
 
+Module contents
+---------------
+
 .. automodule:: chipsec.modules.snb
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.modules.tools.cpu.rst.txt b/_sources/modules/chipsec.modules.tools.cpu.rst.txt
deleted file mode 100644
index 7e9cad38..00000000
--- a/_sources/modules/chipsec.modules.tools.cpu.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-cpu package
-=================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.cpu.sinkhole
-
-.. automodule:: chipsec.modules.tools.cpu
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.cpu.sinkhole.rst.txt b/_sources/modules/chipsec.modules.tools.cpu.sinkhole.rst.txt
deleted file mode 100644
index 3151b3ae..00000000
--- a/_sources/modules/chipsec.modules.tools.cpu.sinkhole.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-sinkhole module
-=========================================
-
-.. automodule:: chipsec.modules.tools.cpu.sinkhole
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.generate_test_id.rst.txt b/_sources/modules/chipsec.modules.tools.generate_test_id.rst.txt
deleted file mode 100644
index a0075269..00000000
--- a/_sources/modules/chipsec.modules.tools.generate_test_id.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-generate\_test\_id module
-===============================================
-
-.. automodule:: chipsec.modules.tools.generate_test_id
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.rst.txt b/_sources/modules/chipsec.modules.tools.rst.txt
deleted file mode 100644
index c2b3554b..00000000
--- a/_sources/modules/chipsec.modules.tools.rst.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-tools package
-=============================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.cpu
-   chipsec.modules.tools.secureboot
-   chipsec.modules.tools.smm
-   chipsec.modules.tools.uefi
-   chipsec.modules.tools.vmm
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.generate_test_id
-   chipsec.modules.tools.wsmt
-
-.. automodule:: chipsec.modules.tools
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.secureboot.rst.txt b/_sources/modules/chipsec.modules.tools.secureboot.rst.txt
deleted file mode 100644
index d78abb91..00000000
--- a/_sources/modules/chipsec.modules.tools.secureboot.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-secureboot package
-========================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.secureboot.te
-
-.. automodule:: chipsec.modules.tools.secureboot
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.secureboot.te.rst.txt b/_sources/modules/chipsec.modules.tools.secureboot.te.rst.txt
deleted file mode 100644
index ad748a50..00000000
--- a/_sources/modules/chipsec.modules.tools.secureboot.te.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-te module
-==========================================
-
-.. automodule:: chipsec.modules.tools.secureboot.te
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.smm.rogue_mmio_bar.rst.txt b/_sources/modules/chipsec.modules.tools.smm.rogue_mmio_bar.rst.txt
deleted file mode 100644
index 7f39c8af..00000000
--- a/_sources/modules/chipsec.modules.tools.smm.rogue_mmio_bar.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-rogue\_mmio\_bar module
-=================================================
-
-.. automodule:: chipsec.modules.tools.smm.rogue_mmio_bar
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.smm.rst.txt b/_sources/modules/chipsec.modules.tools.smm.rst.txt
deleted file mode 100644
index 26e15165..00000000
--- a/_sources/modules/chipsec.modules.tools.smm.rst.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-smm package
-=================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.smm.rogue_mmio_bar
-   chipsec.modules.tools.smm.smm_ptr
-
-.. automodule:: chipsec.modules.tools.smm
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.smm.smm_ptr.rst.txt b/_sources/modules/chipsec.modules.tools.smm.smm_ptr.rst.txt
deleted file mode 100644
index 2d47bb0d..00000000
--- a/_sources/modules/chipsec.modules.tools.smm.smm_ptr.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-smm\_ptr module
-=========================================
-
-.. automodule:: chipsec.modules.tools.smm.smm_ptr
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.reputation.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.reputation.rst.txt
deleted file mode 100644
index 74316fd3..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.reputation.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-reputation module
-============================================
-
-.. automodule:: chipsec.modules.tools.uefi.reputation
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.rst.txt
deleted file mode 100644
index a69f49de..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.rst.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-uefi package
-==================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.uefi.reputation
-   chipsec.modules.tools.uefi.s3script_modify
-   chipsec.modules.tools.uefi.scan_blocked
-   chipsec.modules.tools.uefi.scan_image
-   chipsec.modules.tools.uefi.uefivar_fuzz
-
-.. automodule:: chipsec.modules.tools.uefi
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.s3script_modify.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.s3script_modify.rst.txt
deleted file mode 100644
index 0e34307f..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.s3script_modify.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-s3script\_modify module
-==================================================
-
-.. automodule:: chipsec.modules.tools.uefi.s3script_modify
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.scan_blocked.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.scan_blocked.rst.txt
deleted file mode 100644
index 9599eb23..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.scan_blocked.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-scan\_blocked module
-===============================================
-
-.. automodule:: chipsec.modules.tools.uefi.scan_blocked
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.scan_image.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.scan_image.rst.txt
deleted file mode 100644
index a07e8ea9..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.scan_image.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-scan\_image module
-=============================================
-
-.. automodule:: chipsec.modules.tools.uefi.scan_image
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.uefi.uefivar_fuzz.rst.txt b/_sources/modules/chipsec.modules.tools.uefi.uefivar_fuzz.rst.txt
deleted file mode 100644
index a549b8ac..00000000
--- a/_sources/modules/chipsec.modules.tools.uefi.uefivar_fuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-uefivar\_fuzz module
-===============================================
-
-.. automodule:: chipsec.modules.tools.uefi.uefivar_fuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.common.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.common.rst.txt
deleted file mode 100644
index 0714e3eb..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.common.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-common module
-=======================================
-
-.. automodule:: chipsec.modules.tools.vmm.common
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.cpuid_fuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.cpuid_fuzz.rst.txt
deleted file mode 100644
index 66ef3da2..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.cpuid_fuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-cpuid\_fuzz module
-============================================
-
-.. automodule:: chipsec.modules.tools.vmm.cpuid_fuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.ept_finder.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.ept_finder.rst.txt
deleted file mode 100644
index 1dddec68..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.ept_finder.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-ept\_finder module
-============================================
-
-.. automodule:: chipsec.modules.tools.vmm.ept_finder
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.define.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.define.rst.txt
deleted file mode 100644
index c98deca9..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.define.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-define module
-==========================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.define
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.hypercall.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.hypercall.rst.txt
deleted file mode 100644
index 4404652f..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.hypercall.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-hypercall module
-=============================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.hypercall
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.rst.txt
deleted file mode 100644
index 97906981..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.hypercallfuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-hypercallfuzz module
-=================================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.hypercallfuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.rst.txt
deleted file mode 100644
index 64b72282..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.rst.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-hv package
-====================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.vmm.hv.define
-   chipsec.modules.tools.vmm.hv.hypercall
-   chipsec.modules.tools.vmm.hv.hypercallfuzz
-   chipsec.modules.tools.vmm.hv.synth_dev
-   chipsec.modules.tools.vmm.hv.synth_kbd
-   chipsec.modules.tools.vmm.hv.vmbus
-   chipsec.modules.tools.vmm.hv.vmbusfuzz
-
-.. automodule:: chipsec.modules.tools.vmm.hv
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.synth_dev.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.synth_dev.rst.txt
deleted file mode 100644
index 7ed76cb3..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.synth_dev.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-synth\_dev module
-==============================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.synth_dev
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.synth_kbd.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.synth_kbd.rst.txt
deleted file mode 100644
index 607af6ef..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.synth_kbd.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-synth\_kbd module
-==============================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.synth_kbd
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.vmbus.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.vmbus.rst.txt
deleted file mode 100644
index 715f1716..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.vmbus.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-vmbus module
-=========================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.vmbus
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.rst.txt
deleted file mode 100644
index b9a8f079..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hv.vmbusfuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-vmbusfuzz module
-=============================================
-
-.. automodule:: chipsec.modules.tools.vmm.hv.vmbusfuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.hypercallfuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.hypercallfuzz.rst.txt
deleted file mode 100644
index 9b09c5d7..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.hypercallfuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-hypercallfuzz module
-==============================================
-
-.. automodule:: chipsec.modules.tools.vmm.hypercallfuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.iofuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.iofuzz.rst.txt
deleted file mode 100644
index 6920c065..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.iofuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-iofuzz module
-=======================================
-
-.. automodule:: chipsec.modules.tools.vmm.iofuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.msr_fuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.msr_fuzz.rst.txt
deleted file mode 100644
index 1b86eb13..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.msr_fuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-msr\_fuzz module
-==========================================
-
-.. automodule:: chipsec.modules.tools.vmm.msr_fuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.pcie_fuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.pcie_fuzz.rst.txt
deleted file mode 100644
index 59a704d7..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.pcie_fuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-pcie\_fuzz module
-===========================================
-
-.. automodule:: chipsec.modules.tools.vmm.pcie_fuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.rst.txt
deleted file mode 100644
index caa2ec17..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.pcie_overlap_fuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-pcie\_overlap\_fuzz module
-====================================================
-
-.. automodule:: chipsec.modules.tools.vmm.pcie_overlap_fuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.rst.txt
deleted file mode 100644
index 31323992..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.rst.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-vmm package
-=================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.vmm.hv
-   chipsec.modules.tools.vmm.vbox
-   chipsec.modules.tools.vmm.xen
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.vmm.common
-   chipsec.modules.tools.vmm.cpuid_fuzz
-   chipsec.modules.tools.vmm.ept_finder
-   chipsec.modules.tools.vmm.hypercallfuzz
-   chipsec.modules.tools.vmm.iofuzz
-   chipsec.modules.tools.vmm.msr_fuzz
-   chipsec.modules.tools.vmm.pcie_fuzz
-   chipsec.modules.tools.vmm.pcie_overlap_fuzz
-   chipsec.modules.tools.vmm.venom
-
-.. automodule:: chipsec.modules.tools.vmm
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.vbox.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.vbox.rst.txt
deleted file mode 100644
index 74d3c1e7..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.vbox.rst.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-vbox package
-======================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase
-
-.. automodule:: chipsec.modules.tools.vmm.vbox
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.rst.txt
deleted file mode 100644
index cb1ef9de..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-vbox\_crash\_apicbase module
-===========================================================
-
-.. automodule:: chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.venom.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.venom.rst.txt
deleted file mode 100644
index a63f38ba..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.venom.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-venom module
-======================================
-
-.. automodule:: chipsec.modules.tools.vmm.venom
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.xen.define.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.xen.define.rst.txt
deleted file mode 100644
index dfaf5009..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.xen.define.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-define module
-===========================================
-
-.. automodule:: chipsec.modules.tools.vmm.xen.define
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.xen.hypercall.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.xen.hypercall.rst.txt
deleted file mode 100644
index 0e49c598..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.xen.hypercall.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-hypercall module
-==============================================
-
-.. automodule:: chipsec.modules.tools.vmm.xen.hypercall
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.rst.txt
deleted file mode 100644
index 897d4ad9..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.xen.hypercallfuzz.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-hypercallfuzz module
-==================================================
-
-.. automodule:: chipsec.modules.tools.vmm.xen.hypercallfuzz
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.xen.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.xen.rst.txt
deleted file mode 100644
index c31f9f54..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.xen.rst.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-xen package
-=====================================
-
-.. toctree::
-   :maxdepth: 10
-
-   chipsec.modules.tools.vmm.xen.define
-   chipsec.modules.tools.vmm.xen.hypercall
-   chipsec.modules.tools.vmm.xen.hypercallfuzz
-   chipsec.modules.tools.vmm.xen.xsa188
-
-.. automodule:: chipsec.modules.tools.vmm.xen
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.vmm.xen.xsa188.rst.txt b/_sources/modules/chipsec.modules.tools.vmm.xen.xsa188.rst.txt
deleted file mode 100644
index b1c566d4..00000000
--- a/_sources/modules/chipsec.modules.tools.vmm.xen.xsa188.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-xsa188 module
-===========================================
-
-.. automodule:: chipsec.modules.tools.vmm.xen.xsa188
-   
-   
-   
diff --git a/_sources/modules/chipsec.modules.tools.wsmt.rst.txt b/_sources/modules/chipsec.modules.tools.wsmt.rst.txt
deleted file mode 100644
index 186371e9..00000000
--- a/_sources/modules/chipsec.modules.tools.wsmt.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-wsmt module
-=================================
-
-.. automodule:: chipsec.modules.tools.wsmt
-   
-   
-   
diff --git a/_sources/modules/chipsec.options.rst.txt b/_sources/modules/chipsec.options.rst.txt
index c7197daf..1a164f74 100644
--- a/_sources/modules/chipsec.options.rst.txt
+++ b/_sources/modules/chipsec.options.rst.txt
@@ -1,7 +1,7 @@
-options module
+chipsec.options module
 ======================
 
 .. automodule:: chipsec.options
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.parsers.rst.txt b/_sources/modules/chipsec.parsers.rst.txt
index 93bac8a6..b9dc5701 100644
--- a/_sources/modules/chipsec.parsers.rst.txt
+++ b/_sources/modules/chipsec.parsers.rst.txt
@@ -1,7 +1,7 @@
-parsers module
+chipsec.parsers module
 ======================
 
 .. automodule:: chipsec.parsers
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.testcase.rst.txt b/_sources/modules/chipsec.testcase.rst.txt
deleted file mode 100644
index 65f06f1f..00000000
--- a/_sources/modules/chipsec.testcase.rst.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-testcase module
-=======================
-
-.. automodule:: chipsec.testcase
-   
-   
-   
diff --git a/_sources/modules/chipsec.utilcmd.acpi_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.acpi_cmd.rst.txt
index 66ca8221..3dc831e5 100644
--- a/_sources/modules/chipsec.utilcmd.acpi_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.acpi_cmd.rst.txt
@@ -1,7 +1,7 @@
-acpi\_cmd module
+chipsec.utilcmd.acpi\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.acpi_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.chipset_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.chipset_cmd.rst.txt
index 57bdba39..b12fc8d0 100644
--- a/_sources/modules/chipsec.utilcmd.chipset_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.chipset_cmd.rst.txt
@@ -1,7 +1,7 @@
-chipset\_cmd module
+chipsec.utilcmd.chipset\_cmd module
 ===================================
 
 .. automodule:: chipsec.utilcmd.chipset_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.cmos_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.cmos_cmd.rst.txt
index b8b1b07b..291a71de 100644
--- a/_sources/modules/chipsec.utilcmd.cmos_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.cmos_cmd.rst.txt
@@ -1,7 +1,7 @@
-cmos\_cmd module
+chipsec.utilcmd.cmos\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.cmos_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.config_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.config_cmd.rst.txt
index bc539557..b87d4340 100644
--- a/_sources/modules/chipsec.utilcmd.config_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.config_cmd.rst.txt
@@ -1,7 +1,7 @@
-config\_cmd module
+chipsec.utilcmd.config\_cmd module
 ==================================
 
 .. automodule:: chipsec.utilcmd.config_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.cpu_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.cpu_cmd.rst.txt
index b4875bd8..63b0e38b 100644
--- a/_sources/modules/chipsec.utilcmd.cpu_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.cpu_cmd.rst.txt
@@ -1,7 +1,7 @@
-cpu\_cmd module
+chipsec.utilcmd.cpu\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.cpu_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.decode_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.decode_cmd.rst.txt
index 2cc6073c..2ac30dc1 100644
--- a/_sources/modules/chipsec.utilcmd.decode_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.decode_cmd.rst.txt
@@ -1,7 +1,7 @@
-decode\_cmd module
+chipsec.utilcmd.decode\_cmd module
 ==================================
 
 .. automodule:: chipsec.utilcmd.decode_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.deltas_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.deltas_cmd.rst.txt
index 76eefdc7..81a5a6c0 100644
--- a/_sources/modules/chipsec.utilcmd.deltas_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.deltas_cmd.rst.txt
@@ -1,7 +1,7 @@
-deltas\_cmd module
+chipsec.utilcmd.deltas\_cmd module
 ==================================
 
 .. automodule:: chipsec.utilcmd.deltas_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.desc_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.desc_cmd.rst.txt
index cd80d02e..59464c82 100644
--- a/_sources/modules/chipsec.utilcmd.desc_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.desc_cmd.rst.txt
@@ -1,7 +1,7 @@
-desc\_cmd module
+chipsec.utilcmd.desc\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.desc_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.ec_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.ec_cmd.rst.txt
index 64740239..791f6192 100644
--- a/_sources/modules/chipsec.utilcmd.ec_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.ec_cmd.rst.txt
@@ -1,7 +1,7 @@
-ec\_cmd module
+chipsec.utilcmd.ec\_cmd module
 ==============================
 
 .. automodule:: chipsec.utilcmd.ec_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.igd_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.igd_cmd.rst.txt
index 3dc5b57c..93dac76c 100644
--- a/_sources/modules/chipsec.utilcmd.igd_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.igd_cmd.rst.txt
@@ -1,7 +1,7 @@
-igd\_cmd module
+chipsec.utilcmd.igd\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.igd_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.interrupts_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.interrupts_cmd.rst.txt
index bdd8d6c1..257c6c52 100644
--- a/_sources/modules/chipsec.utilcmd.interrupts_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.interrupts_cmd.rst.txt
@@ -1,7 +1,7 @@
-interrupts\_cmd module
+chipsec.utilcmd.interrupts\_cmd module
 ======================================
 
 .. automodule:: chipsec.utilcmd.interrupts_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.io_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.io_cmd.rst.txt
index 12168def..a6ce0ca0 100644
--- a/_sources/modules/chipsec.utilcmd.io_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.io_cmd.rst.txt
@@ -1,7 +1,7 @@
-io\_cmd module
+chipsec.utilcmd.io\_cmd module
 ==============================
 
 .. automodule:: chipsec.utilcmd.io_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.iommu_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.iommu_cmd.rst.txt
index dd777577..3e9853b9 100644
--- a/_sources/modules/chipsec.utilcmd.iommu_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.iommu_cmd.rst.txt
@@ -1,7 +1,7 @@
-iommu\_cmd module
+chipsec.utilcmd.iommu\_cmd module
 =================================
 
 .. automodule:: chipsec.utilcmd.iommu_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.lock_check_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.lock_check_cmd.rst.txt
index f63d9c2a..3570375c 100644
--- a/_sources/modules/chipsec.utilcmd.lock_check_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.lock_check_cmd.rst.txt
@@ -1,7 +1,7 @@
-lock\_check\_cmd module
+chipsec.utilcmd.lock\_check\_cmd module
 =======================================
 
 .. automodule:: chipsec.utilcmd.lock_check_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.mem_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.mem_cmd.rst.txt
index 5ba4dbc7..e39fbe61 100644
--- a/_sources/modules/chipsec.utilcmd.mem_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.mem_cmd.rst.txt
@@ -1,7 +1,7 @@
-mem\_cmd module
+chipsec.utilcmd.mem\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.mem_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.mmcfg_base_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.mmcfg_base_cmd.rst.txt
index 1ecfa25d..dbae082c 100644
--- a/_sources/modules/chipsec.utilcmd.mmcfg_base_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.mmcfg_base_cmd.rst.txt
@@ -1,7 +1,7 @@
-mmcfg\_base\_cmd module
+chipsec.utilcmd.mmcfg\_base\_cmd module
 =======================================
 
 .. automodule:: chipsec.utilcmd.mmcfg_base_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.mmcfg_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.mmcfg_cmd.rst.txt
index 3f370f50..42d9b5e3 100644
--- a/_sources/modules/chipsec.utilcmd.mmcfg_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.mmcfg_cmd.rst.txt
@@ -1,7 +1,7 @@
-mmcfg\_cmd module
+chipsec.utilcmd.mmcfg\_cmd module
 =================================
 
 .. automodule:: chipsec.utilcmd.mmcfg_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.mmio_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.mmio_cmd.rst.txt
index e13b2fb2..792b5045 100644
--- a/_sources/modules/chipsec.utilcmd.mmio_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.mmio_cmd.rst.txt
@@ -1,7 +1,7 @@
-mmio\_cmd module
+chipsec.utilcmd.mmio\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.mmio_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.msgbus_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.msgbus_cmd.rst.txt
index 80a6f269..927bfa1c 100644
--- a/_sources/modules/chipsec.utilcmd.msgbus_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.msgbus_cmd.rst.txt
@@ -1,7 +1,7 @@
-msgbus\_cmd module
+chipsec.utilcmd.msgbus\_cmd module
 ==================================
 
 .. automodule:: chipsec.utilcmd.msgbus_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.msr_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.msr_cmd.rst.txt
index 98418b16..0f09d538 100644
--- a/_sources/modules/chipsec.utilcmd.msr_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.msr_cmd.rst.txt
@@ -1,7 +1,7 @@
-msr\_cmd module
+chipsec.utilcmd.msr\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.msr_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.pci_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.pci_cmd.rst.txt
index 1854d5f5..8af0ba3d 100644
--- a/_sources/modules/chipsec.utilcmd.pci_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.pci_cmd.rst.txt
@@ -1,7 +1,7 @@
-pci\_cmd module
+chipsec.utilcmd.pci\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.pci_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.reg_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.reg_cmd.rst.txt
index 9e197b2e..0f5e2d18 100644
--- a/_sources/modules/chipsec.utilcmd.reg_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.reg_cmd.rst.txt
@@ -1,7 +1,7 @@
-reg\_cmd module
+chipsec.utilcmd.reg\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.reg_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.rst.txt b/_sources/modules/chipsec.utilcmd.rst.txt
index 7bac02d7..4cfa1f5a 100644
--- a/_sources/modules/chipsec.utilcmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.rst.txt
@@ -1,6 +1,9 @@
-utilcmd package
+chipsec.utilcmd package
 =======================
 
+Submodules
+----------
+
 .. toctree::
    :maxdepth: 10
 
@@ -38,7 +41,10 @@ utilcmd package
    chipsec.utilcmd.vmem_cmd
    chipsec.utilcmd.vmm_cmd
 
+Module contents
+---------------
+
 .. automodule:: chipsec.utilcmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.smbios_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.smbios_cmd.rst.txt
index e42b3010..419d17b3 100644
--- a/_sources/modules/chipsec.utilcmd.smbios_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.smbios_cmd.rst.txt
@@ -1,7 +1,7 @@
-smbios\_cmd module
+chipsec.utilcmd.smbios\_cmd module
 ==================================
 
 .. automodule:: chipsec.utilcmd.smbios_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.smbus_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.smbus_cmd.rst.txt
index caa6e292..0503328e 100644
--- a/_sources/modules/chipsec.utilcmd.smbus_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.smbus_cmd.rst.txt
@@ -1,7 +1,7 @@
-smbus\_cmd module
+chipsec.utilcmd.smbus\_cmd module
 =================================
 
 .. automodule:: chipsec.utilcmd.smbus_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.spd_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.spd_cmd.rst.txt
index af7c172f..d67279c3 100644
--- a/_sources/modules/chipsec.utilcmd.spd_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.spd_cmd.rst.txt
@@ -1,7 +1,7 @@
-spd\_cmd module
+chipsec.utilcmd.spd\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.spd_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.spi_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.spi_cmd.rst.txt
index 3b334a01..643127b6 100644
--- a/_sources/modules/chipsec.utilcmd.spi_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.spi_cmd.rst.txt
@@ -1,7 +1,7 @@
-spi\_cmd module
+chipsec.utilcmd.spi\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.spi_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.spidesc_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.spidesc_cmd.rst.txt
index 5d28630f..fffcdaec 100644
--- a/_sources/modules/chipsec.utilcmd.spidesc_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.spidesc_cmd.rst.txt
@@ -1,7 +1,7 @@
-spidesc\_cmd module
+chipsec.utilcmd.spidesc\_cmd module
 ===================================
 
 .. automodule:: chipsec.utilcmd.spidesc_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.tpm_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.tpm_cmd.rst.txt
index be8280cb..3f18dde4 100644
--- a/_sources/modules/chipsec.utilcmd.tpm_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.tpm_cmd.rst.txt
@@ -1,7 +1,7 @@
-tpm\_cmd module
+chipsec.utilcmd.tpm\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.tpm_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.txt_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.txt_cmd.rst.txt
index 4ef7d276..a08ae21f 100644
--- a/_sources/modules/chipsec.utilcmd.txt_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.txt_cmd.rst.txt
@@ -1,7 +1,7 @@
-txt\_cmd module
+chipsec.utilcmd.txt\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.txt_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.ucode_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.ucode_cmd.rst.txt
index 94a08c56..5cb5e85e 100644
--- a/_sources/modules/chipsec.utilcmd.ucode_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.ucode_cmd.rst.txt
@@ -1,7 +1,7 @@
-ucode\_cmd module
+chipsec.utilcmd.ucode\_cmd module
 =================================
 
 .. automodule:: chipsec.utilcmd.ucode_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.uefi_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.uefi_cmd.rst.txt
index b67b6e69..aa55cb6a 100644
--- a/_sources/modules/chipsec.utilcmd.uefi_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.uefi_cmd.rst.txt
@@ -1,7 +1,7 @@
-uefi\_cmd module
+chipsec.utilcmd.uefi\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.uefi_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.vmem_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.vmem_cmd.rst.txt
index ddf19cdb..0cd80130 100644
--- a/_sources/modules/chipsec.utilcmd.vmem_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.vmem_cmd.rst.txt
@@ -1,7 +1,7 @@
-vmem\_cmd module
+chipsec.utilcmd.vmem\_cmd module
 ================================
 
 .. automodule:: chipsec.utilcmd.vmem_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_sources/modules/chipsec.utilcmd.vmm_cmd.rst.txt b/_sources/modules/chipsec.utilcmd.vmm_cmd.rst.txt
index 4512196e..6e14360f 100644
--- a/_sources/modules/chipsec.utilcmd.vmm_cmd.rst.txt
+++ b/_sources/modules/chipsec.utilcmd.vmm_cmd.rst.txt
@@ -1,7 +1,7 @@
-vmm\_cmd module
+chipsec.utilcmd.vmm\_cmd module
 ===============================
 
 .. automodule:: chipsec.utilcmd.vmm_cmd
-   
-   
-   
+   :members:
+   :undoc-members:
+   :show-inheritance:
diff --git a/_static/basic.css b/_static/basic.css
index 11dc1139..d3a260c0 100644
--- a/_static/basic.css
+++ b/_static/basic.css
@@ -4,7 +4,7 @@
  *
  * Sphinx stylesheet -- basic theme.
  *
- * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS.
+ * :copyright: Copyright 2007-2022 by the Sphinx team, see AUTHORS.
  * :license: BSD, see LICENSE for details.
  *
  */
@@ -237,8 +237,14 @@ a.headerlink {
     visibility: hidden;
 }
 
-a:visited {
-    color: #551A8B;
+a.brackets:before,
+span.brackets > a:before{
+    content: "[";
+}
+
+a.brackets:after,
+span.brackets > a:after {
+    content: "]";
 }
 
 h1:hover > a.headerlink,
@@ -329,16 +335,12 @@ p.sidebar-title {
     font-weight: bold;
 }
 
-nav.contents,
-aside.topic,
 div.admonition, div.topic, blockquote {
     clear: left;
 }
 
 /* -- topics ---------------------------------------------------------------- */
 
-nav.contents,
-aside.topic,
 div.topic {
     border: 1px solid #ccc;
     padding: 7px;
@@ -377,8 +379,6 @@ div.body p.centered {
 
 div.sidebar > :last-child,
 aside.sidebar > :last-child,
-nav.contents > :last-child,
-aside.topic > :last-child,
 div.topic > :last-child,
 div.admonition > :last-child {
     margin-bottom: 0;
@@ -386,8 +386,6 @@ div.admonition > :last-child {
 
 div.sidebar::after,
 aside.sidebar::after,
-nav.contents::after,
-aside.topic::after,
 div.topic::after,
 div.admonition::after,
 blockquote::after {
@@ -430,6 +428,10 @@ table.docutils td, table.docutils th {
     border-bottom: 1px solid #aaa;
 }
 
+table.footnote td, table.footnote th {
+    border: 0 !important;
+}
+
 th {
     text-align: left;
     padding-right: 5px;
@@ -613,26 +615,19 @@ ul.simple p {
     margin-bottom: 0;
 }
 
-aside.footnote > span,
-div.citation > span {
+dl.footnote > dt,
+dl.citation > dt {
     float: left;
+    margin-right: 0.5em;
 }
-aside.footnote > span:last-of-type,
-div.citation > span:last-of-type {
-  padding-right: 0.5em;
-}
-aside.footnote > p {
-  margin-left: 2em;
-}
-div.citation > p {
-  margin-left: 4em;
-}
-aside.footnote > p:last-of-type,
-div.citation > p:last-of-type {
+
+dl.footnote > dd,
+dl.citation > dd {
     margin-bottom: 0em;
 }
-aside.footnote > p:last-of-type:after,
-div.citation > p:last-of-type:after {
+
+dl.footnote > dd:after,
+dl.citation > dd:after {
     content: "";
     clear: both;
 }
@@ -649,6 +644,10 @@ dl.field-list > dt {
     padding-right: 5px;
 }
 
+dl.field-list > dt:after {
+    content: ":";
+}
+
 dl.field-list > dd {
     padding-left: 0.5em;
     margin-top: 0em;
@@ -674,16 +673,6 @@ dd {
     margin-left: 30px;
 }
 
-.sig dd {
-    margin-top: 0px;
-    margin-bottom: 0px;
-}
-
-.sig dl {
-    margin-top: 0px;
-    margin-bottom: 0px;
-}
-
 dl > dd:last-child,
 dl > dd:last-child > :last-child {
     margin-bottom: 0;
@@ -752,14 +741,6 @@ abbr, acronym {
     cursor: help;
 }
 
-.translated {
-    background-color: rgba(207, 255, 207, 0.2)
-}
-
-.untranslated {
-    background-color: rgba(255, 207, 207, 0.2)
-}
-
 /* -- code displays --------------------------------------------------------- */
 
 pre {
diff --git a/_static/classic.css b/_static/classic.css
index fe226db0..bef7a2a2 100644
--- a/_static/classic.css
+++ b/_static/classic.css
@@ -4,7 +4,7 @@
  *
  * Sphinx stylesheet -- classic theme.
  *
- * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS.
+ * :copyright: Copyright 2007-2022 by the Sphinx team, see AUTHORS.
  * :license: BSD, see LICENSE for details.
  *
  */
@@ -28,7 +28,6 @@ body {
 }
 
 div.document {
-    display: flex;
     background-color: #41728A;
 }
 
@@ -206,8 +205,6 @@ div.seealso {
     border: 1px solid #ff6;
 }
 
-nav.contents,
-aside.topic,
 div.topic {
     background-color: #eee;
 }
diff --git a/_static/doctools.js b/_static/doctools.js
index d06a71d7..e509e483 100644
--- a/_static/doctools.js
+++ b/_static/doctools.js
@@ -2,155 +2,325 @@
  * doctools.js
  * ~~~~~~~~~~~
  *
- * Base JavaScript utilities for all Sphinx HTML documentation.
+ * Sphinx JavaScript utilities for all documentation.
  *
- * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS.
+ * :copyright: Copyright 2007-2022 by the Sphinx team, see AUTHORS.
  * :license: BSD, see LICENSE for details.
  *
  */
-"use strict";
-
-const BLACKLISTED_KEY_CONTROL_ELEMENTS = new Set([
-  "TEXTAREA",
-  "INPUT",
-  "SELECT",
-  "BUTTON",
-]);
-
-const _ready = (callback) => {
-  if (document.readyState !== "loading") {
-    callback();
-  } else {
-    document.addEventListener("DOMContentLoaded", callback);
+
+/**
+ * select a different prefix for underscore
+ */
+$u = _.noConflict();
+
+/**
+ * make the code below compatible with browsers without
+ * an installed firebug like debugger
+if (!window.console || !console.firebug) {
+  var names = ["log", "debug", "info", "warn", "error", "assert", "dir",
+    "dirxml", "group", "groupEnd", "time", "timeEnd", "count", "trace",
+    "profile", "profileEnd"];
+  window.console = {};
+  for (var i = 0; i < names.length; ++i)
+    window.console[names[i]] = function() {};
+}
+ */
+
+/**
+ * small helper function to urldecode strings
+ *
+ * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Reference/Global_Objects/decodeURIComponent#Decoding_query_parameters_from_a_URL
+ */
+jQuery.urldecode = function(x) {
+  if (!x) {
+    return x
+  }
+  return decodeURIComponent(x.replace(/\+/g, ' '));
+};
+
+/**
+ * small helper function to urlencode strings
+ */
+jQuery.urlencode = encodeURIComponent;
+
+/**
+ * This function returns the parsed url parameters of the
+ * current request. Multiple values per key are supported,
+ * it will always return arrays of strings for the value parts.
+ */
+jQuery.getQueryParameters = function(s) {
+  if (typeof s === 'undefined')
+    s = document.location.search;
+  var parts = s.substr(s.indexOf('?') + 1).split('&');
+  var result = {};
+  for (var i = 0; i < parts.length; i++) {
+    var tmp = parts[i].split('=', 2);
+    var key = jQuery.urldecode(tmp[0]);
+    var value = jQuery.urldecode(tmp[1]);
+    if (key in result)
+      result[key].push(value);
+    else
+      result[key] = [value];
   }
+  return result;
 };
 
+/**
+ * highlight a given string on a jquery object by wrapping it in
+ * span elements with the given class name.
+ */
+jQuery.fn.highlightText = function(text, className) {
+  function highlight(node, addItems) {
+    if (node.nodeType === 3) {
+      var val = node.nodeValue;
+      var pos = val.toLowerCase().indexOf(text);
+      if (pos >= 0 &&
+          !jQuery(node.parentNode).hasClass(className) &&
+          !jQuery(node.parentNode).hasClass("nohighlight")) {
+        var span;
+        var isInSVG = jQuery(node).closest("body, svg, foreignObject").is("svg");
+        if (isInSVG) {
+          span = document.createElementNS("http://www.w3.org/2000/svg", "tspan");
+        } else {
+          span = document.createElement("span");
+          span.className = className;
+        }
+        span.appendChild(document.createTextNode(val.substr(pos, text.length)));
+        node.parentNode.insertBefore(span, node.parentNode.insertBefore(
+          document.createTextNode(val.substr(pos + text.length)),
+          node.nextSibling));
+        node.nodeValue = val.substr(0, pos);
+        if (isInSVG) {
+          var rect = document.createElementNS("http://www.w3.org/2000/svg", "rect");
+          var bbox = node.parentElement.getBBox();
+          rect.x.baseVal.value = bbox.x;
+          rect.y.baseVal.value = bbox.y;
+          rect.width.baseVal.value = bbox.width;
+          rect.height.baseVal.value = bbox.height;
+          rect.setAttribute('class', className);
+          addItems.push({
+              "parent": node.parentNode,
+              "target": rect});
+        }
+      }
+    }
+    else if (!jQuery(node).is("button, select, textarea")) {
+      jQuery.each(node.childNodes, function() {
+        highlight(this, addItems);
+      });
+    }
+  }
+  var addItems = [];
+  var result = this.each(function() {
+    highlight(this, addItems);
+  });
+  for (var i = 0; i < addItems.length; ++i) {
+    jQuery(addItems[i].parent).before(addItems[i].target);
+  }
+  return result;
+};
+
+/*
+ * backward compatibility for jQuery.browser
+ * This will be supported until firefox bug is fixed.
+ */
+if (!jQuery.browser) {
+  jQuery.uaMatch = function(ua) {
+    ua = ua.toLowerCase();
+
+    var match = /(chrome)[ \/]([\w.]+)/.exec(ua) ||
+      /(webkit)[ \/]([\w.]+)/.exec(ua) ||
+      /(opera)(?:.*version|)[ \/]([\w.]+)/.exec(ua) ||
+      /(msie) ([\w.]+)/.exec(ua) ||
+      ua.indexOf("compatible") < 0 && /(mozilla)(?:.*? rv:([\w.]+)|)/.exec(ua) ||
+      [];
+
+    return {
+      browser: match[ 1 ] || "",
+      version: match[ 2 ] || "0"
+    };
+  };
+  jQuery.browser = {};
+  jQuery.browser[jQuery.uaMatch(navigator.userAgent).browser] = true;
+}
+
 /**
  * Small JavaScript module for the documentation.
  */
-const Documentation = {
-  init: () => {
-    Documentation.initDomainIndexTable();
-    Documentation.initOnKeyListeners();
+var Documentation = {
+
+  init : function() {
+    this.fixFirefoxAnchorBug();
+    this.highlightSearchWords();
+    this.initIndexTable();
+    if (DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS) {
+      this.initOnKeyListeners();
+    }
   },
 
   /**
    * i18n support
    */
-  TRANSLATIONS: {},
-  PLURAL_EXPR: (n) => (n === 1 ? 0 : 1),
-  LOCALE: "unknown",
+  TRANSLATIONS : {},
+  PLURAL_EXPR : function(n) { return n === 1 ? 0 : 1; },
+  LOCALE : 'unknown',
 
   // gettext and ngettext don't access this so that the functions
   // can safely bound to a different name (_ = Documentation.gettext)
-  gettext: (string) => {
-    const translated = Documentation.TRANSLATIONS[string];
-    switch (typeof translated) {
-      case "undefined":
-        return string; // no translation
-      case "string":
-        return translated; // translation exists
-      default:
-        return translated[0]; // (singular, plural) translation tuple exists
-    }
+  gettext : function(string) {
+    var translated = Documentation.TRANSLATIONS[string];
+    if (typeof translated === 'undefined')
+      return string;
+    return (typeof translated === 'string') ? translated : translated[0];
   },
 
-  ngettext: (singular, plural, n) => {
-    const translated = Documentation.TRANSLATIONS[singular];
-    if (typeof translated !== "undefined")
-      return translated[Documentation.PLURAL_EXPR(n)];
-    return n === 1 ? singular : plural;
+  ngettext : function(singular, plural, n) {
+    var translated = Documentation.TRANSLATIONS[singular];
+    if (typeof translated === 'undefined')
+      return (n == 1) ? singular : plural;
+    return translated[Documentation.PLURALEXPR(n)];
   },
 
-  addTranslations: (catalog) => {
-    Object.assign(Documentation.TRANSLATIONS, catalog.messages);
-    Documentation.PLURAL_EXPR = new Function(
-      "n",
-      `return (${catalog.plural_expr})`
-    );
-    Documentation.LOCALE = catalog.locale;
+  addTranslations : function(catalog) {
+    for (var key in catalog.messages)
+      this.TRANSLATIONS[key] = catalog.messages[key];
+    this.PLURAL_EXPR = new Function('n', 'return +(' + catalog.plural_expr + ')');
+    this.LOCALE = catalog.locale;
   },
 
   /**
-   * helper function to focus on search bar
+   * add context elements like header anchor links
    */
-  focusSearchBar: () => {
-    document.querySelectorAll("input[name=q]")[0]?.focus();
+  addContextElements : function() {
+    $('div[id] > :header:first').each(function() {
+      $('\u00B6').
+      attr('href', '#' + this.id).
+      attr('title', _('Permalink to this headline')).
+      appendTo(this);
+    });
+    $('dt[id]').each(function() {
+      $('\u00B6').
+      attr('href', '#' + this.id).
+      attr('title', _('Permalink to this definition')).
+      appendTo(this);
+    });
   },
 
   /**
-   * Initialise the domain index toggle buttons
+   * workaround a firefox stupidity
+   * see: https://bugzilla.mozilla.org/show_bug.cgi?id=645075
    */
-  initDomainIndexTable: () => {
-    const toggler = (el) => {
-      const idNumber = el.id.substr(7);
-      const toggledRows = document.querySelectorAll(`tr.cg-${idNumber}`);
-      if (el.src.substr(-9) === "minus.png") {
-        el.src = `${el.src.substr(0, el.src.length - 9)}plus.png`;
-        toggledRows.forEach((el) => (el.style.display = "none"));
-      } else {
-        el.src = `${el.src.substr(0, el.src.length - 8)}minus.png`;
-        toggledRows.forEach((el) => (el.style.display = ""));
+  fixFirefoxAnchorBug : function() {
+    if (document.location.hash && $.browser.mozilla)
+      window.setTimeout(function() {
+        document.location.href += '';
+      }, 10);
+  },
+
+  /**
+   * highlight the search words provided in the url in the text
+   */
+  highlightSearchWords : function() {
+    var params = $.getQueryParameters();
+    var terms = (params.highlight) ? params.highlight[0].split(/\s+/) : [];
+    if (terms.length) {
+      var body = $('div.body');
+      if (!body.length) {
+        body = $('body');
       }
-    };
+      window.setTimeout(function() {
+        $.each(terms, function() {
+          body.highlightText(this.toLowerCase(), 'highlighted');
+        });
+      }, 10);
+      $('
    ' + _('Hide Search Matches') + '
    ')
+          .appendTo($('#searchbox'));
+    }
+  },
+
+  /**
+   * init the domain index toggle buttons
+   */
+  initIndexTable : function() {
+    var togglers = $('img.toggler').click(function() {
+      var src = $(this).attr('src');
+      var idnum = $(this).attr('id').substr(7);
+      $('tr.cg-' + idnum).toggle();
+      if (src.substr(-9) === 'minus.png')
+        $(this).attr('src', src.substr(0, src.length-9) + 'plus.png');
+      else
+        $(this).attr('src', src.substr(0, src.length-8) + 'minus.png');
+    }).css('display', '');
+    if (DOCUMENTATION_OPTIONS.COLLAPSE_INDEX) {
+        togglers.click();
+    }
+  },
 
-    const togglerElements = document.querySelectorAll("img.toggler");
-    togglerElements.forEach((el) =>
-      el.addEventListener("click", (event) => toggler(event.currentTarget))
-    );
-    togglerElements.forEach((el) => (el.style.display = ""));
-    if (DOCUMENTATION_OPTIONS.COLLAPSE_INDEX) togglerElements.forEach(toggler);
+  /**
+   * helper function to hide the search marks again
+   */
+  hideSearchWords : function() {
+    $('#searchbox .highlight-link').fadeOut(300);
+    $('span.highlighted').removeClass('highlighted');
+    var url = new URL(window.location);
+    url.searchParams.delete('highlight');
+    window.history.replaceState({}, '', url);
   },
 
-  initOnKeyListeners: () => {
-    // only install a listener if it is really needed
-    if (
-      !DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS &&
-      !DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS
-    )
-      return;
-
-    document.addEventListener("keydown", (event) => {
-      // bail for input elements
-      if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return;
-      // bail with special keys
-      if (event.altKey || event.ctrlKey || event.metaKey) return;
-
-      if (!event.shiftKey) {
-        switch (event.key) {
-          case "ArrowLeft":
-            if (!DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS) break;
-
-            const prevLink = document.querySelector('link[rel="prev"]');
-            if (prevLink && prevLink.href) {
-              window.location.href = prevLink.href;
-              event.preventDefault();
+  /**
+   * make the url absolute
+   */
+  makeURL : function(relativeURL) {
+    return DOCUMENTATION_OPTIONS.URL_ROOT + '/' + relativeURL;
+  },
+
+  /**
+   * get the current relative url
+   */
+  getCurrentURL : function() {
+    var path = document.location.pathname;
+    var parts = path.split(/\//);
+    $.each(DOCUMENTATION_OPTIONS.URL_ROOT.split(/\//), function() {
+      if (this === '..')
+        parts.pop();
+    });
+    var url = parts.join('/');
+    return path.substring(url.lastIndexOf('/') + 1, path.length - 1);
+  },
+
+  initOnKeyListeners: function() {
+    $(document).keydown(function(event) {
+      var activeElementType = document.activeElement.tagName;
+      // don't navigate when in search box, textarea, dropdown or button
+      if (activeElementType !== 'TEXTAREA' && activeElementType !== 'INPUT' && activeElementType !== 'SELECT'
+          && activeElementType !== 'BUTTON' && !event.altKey && !event.ctrlKey && !event.metaKey
+          && !event.shiftKey) {
+        switch (event.keyCode) {
+          case 37: // left
+            var prevHref = $('link[rel="prev"]').prop('href');
+            if (prevHref) {
+              window.location.href = prevHref;
+              return false;
             }
             break;
-          case "ArrowRight":
-            if (!DOCUMENTATION_OPTIONS.NAVIGATION_WITH_KEYS) break;
-
-            const nextLink = document.querySelector('link[rel="next"]');
-            if (nextLink && nextLink.href) {
-              window.location.href = nextLink.href;
-              event.preventDefault();
+          case 39: // right
+            var nextHref = $('link[rel="next"]').prop('href');
+            if (nextHref) {
+              window.location.href = nextHref;
+              return false;
             }
             break;
         }
       }
-
-      // some keyboard layouts may need Shift to get /
-      switch (event.key) {
-        case "/":
-          if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) break;
-          Documentation.focusSearchBar();
-          event.preventDefault();
-      }
     });
-  },
+  }
 };
 
 // quick alias for translations
-const _ = Documentation.gettext;
+_ = Documentation.gettext;
 
-_ready(Documentation.init);
+$(document).ready(function() {
+  Documentation.init();
+});
diff --git a/_static/documentation_options.js b/_static/documentation_options.js
index 7e4c114f..2fa8c97f 100644
--- a/_static/documentation_options.js
+++ b/_static/documentation_options.js
@@ -1,13 +1,12 @@
-const DOCUMENTATION_OPTIONS = {
+var DOCUMENTATION_OPTIONS = {
+    URL_ROOT: document.getElementById("documentation_options").getAttribute('data-url_root'),
     VERSION: '',
-    LANGUAGE: 'en',
+    LANGUAGE: 'None',
     COLLAPSE_INDEX: false,
     BUILDER: 'html',
     FILE_SUFFIX: '.html',
     LINK_SUFFIX: '.html',
     HAS_SOURCE: true,
     SOURCELINK_SUFFIX: '.txt',
-    NAVIGATION_WITH_KEYS: false,
-    SHOW_SEARCH_SUMMARY: true,
-    ENABLE_SEARCH_SHORTCUTS: true,
+    NAVIGATION_WITH_KEYS: false
 };
\ No newline at end of file
diff --git a/_static/language_data.js b/_static/language_data.js
index 250f5665..ebe2f03b 100644
--- a/_static/language_data.js
+++ b/_static/language_data.js
@@ -5,12 +5,12 @@
  * This script contains the language-specific data used by searchtools.js,
  * namely the list of stopwords, stemmer, scorer and splitter.
  *
- * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS.
+ * :copyright: Copyright 2007-2022 by the Sphinx team, see AUTHORS.
  * :license: BSD, see LICENSE for details.
  *
  */
 
-var stopwords = ["a", "and", "are", "as", "at", "be", "but", "by", "for", "if", "in", "into", "is", "it", "near", "no", "not", "of", "on", "or", "such", "that", "the", "their", "then", "there", "these", "they", "this", "to", "was", "will", "with"];
+var stopwords = ["a","and","are","as","at","be","but","by","for","if","in","into","is","it","near","no","not","of","on","or","such","that","the","their","then","there","these","they","this","to","was","will","with"];
 
 
 /* Non-minified version is copied as a separate JS file, is available */
@@ -197,3 +197,101 @@ var Stemmer = function() {
   }
 }
 
+
+
+
+var splitChars = (function() {
+    var result = {};
+    var singles = [96, 180, 187, 191, 215, 247, 749, 885, 903, 907, 909, 930, 1014, 1648,
+         1748, 1809, 2416, 2473, 2481, 2526, 2601, 2609, 2612, 2615, 2653, 2702,
+         2706, 2729, 2737, 2740, 2857, 2865, 2868, 2910, 2928, 2948, 2961, 2971,
+         2973, 3085, 3089, 3113, 3124, 3213, 3217, 3241, 3252, 3295, 3341, 3345,
+         3369, 3506, 3516, 3633, 3715, 3721, 3736, 3744, 3748, 3750, 3756, 3761,
+         3781, 3912, 4239, 4347, 4681, 4695, 4697, 4745, 4785, 4799, 4801, 4823,
+         4881, 5760, 5901, 5997, 6313, 7405, 8024, 8026, 8028, 8030, 8117, 8125,
+         8133, 8181, 8468, 8485, 8487, 8489, 8494, 8527, 11311, 11359, 11687, 11695,
+         11703, 11711, 11719, 11727, 11735, 12448, 12539, 43010, 43014, 43019, 43587,
+         43696, 43713, 64286, 64297, 64311, 64317, 64319, 64322, 64325, 65141];
+    var i, j, start, end;
+    for (i = 0; i < singles.length; i++) {
+        result[singles[i]] = true;
+    }
+    var ranges = [[0, 47], [58, 64], [91, 94], [123, 169], [171, 177], [182, 184], [706, 709],
+         [722, 735], [741, 747], [751, 879], [888, 889], [894, 901], [1154, 1161],
+         [1318, 1328], [1367, 1368], [1370, 1376], [1416, 1487], [1515, 1519], [1523, 1568],
+         [1611, 1631], [1642, 1645], [1750, 1764], [1767, 1773], [1789, 1790], [1792, 1807],
+         [1840, 1868], [1958, 1968], [1970, 1983], [2027, 2035], [2038, 2041], [2043, 2047],
+         [2070, 2073], [2075, 2083], [2085, 2087], [2089, 2307], [2362, 2364], [2366, 2383],
+         [2385, 2391], [2402, 2405], [2419, 2424], [2432, 2436], [2445, 2446], [2449, 2450],
+         [2483, 2485], [2490, 2492], [2494, 2509], [2511, 2523], [2530, 2533], [2546, 2547],
+         [2554, 2564], [2571, 2574], [2577, 2578], [2618, 2648], [2655, 2661], [2672, 2673],
+         [2677, 2692], [2746, 2748], [2750, 2767], [2769, 2783], [2786, 2789], [2800, 2820],
+         [2829, 2830], [2833, 2834], [2874, 2876], [2878, 2907], [2914, 2917], [2930, 2946],
+         [2955, 2957], [2966, 2968], [2976, 2978], [2981, 2983], [2987, 2989], [3002, 3023],
+         [3025, 3045], [3059, 3076], [3130, 3132], [3134, 3159], [3162, 3167], [3170, 3173],
+         [3184, 3191], [3199, 3204], [3258, 3260], [3262, 3293], [3298, 3301], [3312, 3332],
+         [3386, 3388], [3390, 3423], [3426, 3429], [3446, 3449], [3456, 3460], [3479, 3481],
+         [3518, 3519], [3527, 3584], [3636, 3647], [3655, 3663], [3674, 3712], [3717, 3718],
+         [3723, 3724], [3726, 3731], [3752, 3753], [3764, 3772], [3774, 3775], [3783, 3791],
+         [3802, 3803], [3806, 3839], [3841, 3871], [3892, 3903], [3949, 3975], [3980, 4095],
+         [4139, 4158], [4170, 4175], [4182, 4185], [4190, 4192], [4194, 4196], [4199, 4205],
+         [4209, 4212], [4226, 4237], [4250, 4255], [4294, 4303], [4349, 4351], [4686, 4687],
+         [4702, 4703], [4750, 4751], [4790, 4791], [4806, 4807], [4886, 4887], [4955, 4968],
+         [4989, 4991], [5008, 5023], [5109, 5120], [5741, 5742], [5787, 5791], [5867, 5869],
+         [5873, 5887], [5906, 5919], [5938, 5951], [5970, 5983], [6001, 6015], [6068, 6102],
+         [6104, 6107], [6109, 6111], [6122, 6127], [6138, 6159], [6170, 6175], [6264, 6271],
+         [6315, 6319], [6390, 6399], [6429, 6469], [6510, 6511], [6517, 6527], [6572, 6592],
+         [6600, 6607], [6619, 6655], [6679, 6687], [6741, 6783], [6794, 6799], [6810, 6822],
+         [6824, 6916], [6964, 6980], [6988, 6991], [7002, 7042], [7073, 7085], [7098, 7167],
+         [7204, 7231], [7242, 7244], [7294, 7400], [7410, 7423], [7616, 7679], [7958, 7959],
+         [7966, 7967], [8006, 8007], [8014, 8015], [8062, 8063], [8127, 8129], [8141, 8143],
+         [8148, 8149], [8156, 8159], [8173, 8177], [8189, 8303], [8306, 8307], [8314, 8318],
+         [8330, 8335], [8341, 8449], [8451, 8454], [8456, 8457], [8470, 8472], [8478, 8483],
+         [8506, 8507], [8512, 8516], [8522, 8525], [8586, 9311], [9372, 9449], [9472, 10101],
+         [10132, 11263], [11493, 11498], [11503, 11516], [11518, 11519], [11558, 11567],
+         [11622, 11630], [11632, 11647], [11671, 11679], [11743, 11822], [11824, 12292],
+         [12296, 12320], [12330, 12336], [12342, 12343], [12349, 12352], [12439, 12444],
+         [12544, 12548], [12590, 12592], [12687, 12689], [12694, 12703], [12728, 12783],
+         [12800, 12831], [12842, 12880], [12896, 12927], [12938, 12976], [12992, 13311],
+         [19894, 19967], [40908, 40959], [42125, 42191], [42238, 42239], [42509, 42511],
+         [42540, 42559], [42592, 42593], [42607, 42622], [42648, 42655], [42736, 42774],
+         [42784, 42785], [42889, 42890], [42893, 43002], [43043, 43055], [43062, 43071],
+         [43124, 43137], [43188, 43215], [43226, 43249], [43256, 43258], [43260, 43263],
+         [43302, 43311], [43335, 43359], [43389, 43395], [43443, 43470], [43482, 43519],
+         [43561, 43583], [43596, 43599], [43610, 43615], [43639, 43641], [43643, 43647],
+         [43698, 43700], [43703, 43704], [43710, 43711], [43715, 43738], [43742, 43967],
+         [44003, 44015], [44026, 44031], [55204, 55215], [55239, 55242], [55292, 55295],
+         [57344, 63743], [64046, 64047], [64110, 64111], [64218, 64255], [64263, 64274],
+         [64280, 64284], [64434, 64466], [64830, 64847], [64912, 64913], [64968, 65007],
+         [65020, 65135], [65277, 65295], [65306, 65312], [65339, 65344], [65371, 65381],
+         [65471, 65473], [65480, 65481], [65488, 65489], [65496, 65497]];
+    for (i = 0; i < ranges.length; i++) {
+        start = ranges[i][0];
+        end = ranges[i][1];
+        for (j = start; j <= end; j++) {
+            result[j] = true;
+        }
+    }
+    return result;
+})();
+
+function splitQuery(query) {
+    var result = [];
+    var start = -1;
+    for (var i = 0; i < query.length; i++) {
+        if (splitChars[query.charCodeAt(i)]) {
+            if (start !== -1) {
+                result.push(query.slice(start, i));
+                start = -1;
+            }
+        } else if (start === -1) {
+            start = i;
+        }
+    }
+    if (start !== -1) {
+        result.push(query.slice(start));
+    }
+    return result;
+}
+
+
diff --git a/_static/pygments.css b/_static/pygments.css
index 0d49244e..de7af262 100644
--- a/_static/pygments.css
+++ b/_static/pygments.css
@@ -1,7 +1,7 @@
 pre { line-height: 125%; }
-td.linenos .normal { color: inherit; background-color: transparent; padding-left: 5px; padding-right: 5px; }
-span.linenos { color: inherit; background-color: transparent; padding-left: 5px; padding-right: 5px; }
-td.linenos .special { color: #000000; background-color: #ffffc0; padding-left: 5px; padding-right: 5px; }
+td.linenos pre { color: #000000; background-color: #f0f0f0; padding-left: 5px; padding-right: 5px; }
+span.linenos { color: #000000; background-color: #f0f0f0; padding-left: 5px; padding-right: 5px; }
+td.linenos pre.special { color: #000000; background-color: #ffffc0; padding-left: 5px; padding-right: 5px; }
 span.linenos.special { color: #000000; background-color: #ffffc0; padding-left: 5px; padding-right: 5px; }
 .highlight .hll { background-color: #ffffcc }
 .highlight { background: #eeffcc; }
@@ -17,7 +17,6 @@ span.linenos.special { color: #000000; background-color: #ffffc0; padding-left:
 .highlight .cs { color: #408090; background-color: #fff0f0 } /* Comment.Special */
 .highlight .gd { color: #A00000 } /* Generic.Deleted */
 .highlight .ge { font-style: italic } /* Generic.Emph */
-.highlight .ges { font-weight: bold; font-style: italic } /* Generic.EmphStrong */
 .highlight .gr { color: #FF0000 } /* Generic.Error */
 .highlight .gh { color: #000080; font-weight: bold } /* Generic.Heading */
 .highlight .gi { color: #00A000 } /* Generic.Inserted */
diff --git a/_static/searchtools.js b/_static/searchtools.js
index 7918c3fa..2d778593 100644
--- a/_static/searchtools.js
+++ b/_static/searchtools.js
@@ -4,24 +4,22 @@
  *
  * Sphinx JavaScript utilities for the full-text search.
  *
- * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS.
+ * :copyright: Copyright 2007-2022 by the Sphinx team, see AUTHORS.
  * :license: BSD, see LICENSE for details.
  *
  */
-"use strict";
 
-/**
- * Simple result scoring code.
- */
-if (typeof Scorer === "undefined") {
+if (!Scorer) {
+  /**
+   * Simple result scoring code.
+   */
   var Scorer = {
     // Implement the following function to further tweak the score for each result
-    // The function takes a result array [docname, title, anchor, descr, score, filename]
+    // The function takes a result array [filename, title, anchor, descr, score]
     // and returns the new score.
     /*
-    score: result => {
-      const [docname, title, anchor, descr, score, filename] = result
-      return score
+    score: function(result) {
+      return result[4];
     },
     */
 
@@ -30,11 +28,9 @@ if (typeof Scorer === "undefined") {
     // or matches in the last dotted part of the object name
     objPartialMatch: 6,
     // Additive scores depending on the priority of the object
-    objPrio: {
-      0: 15, // used to be importantResults
-      1: 5, // used to be objectResults
-      2: -5, // used to be unimportantResults
-    },
+    objPrio: {0:  15,   // used to be importantResults
+              1:  5,   // used to be objectResults
+              2: -5},  // used to be unimportantResults
     //  Used when the priority is not in the mapping.
     objPrioDefault: 0,
 
@@ -43,503 +39,456 @@ if (typeof Scorer === "undefined") {
     partialTitle: 7,
     // query found in terms
     term: 5,
-    partialTerm: 2,
+    partialTerm: 2
   };
 }
 
-const _removeChildren = (element) => {
-  while (element && element.lastChild) element.removeChild(element.lastChild);
-};
-
-/**
- * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Guide/Regular_Expressions#escaping
- */
-const _escapeRegExp = (string) =>
-  string.replace(/[.*+\-?^${}()|[\]\\]/g, "\\$&"); // $& means the whole matched string
-
-const _displayItem = (item, searchTerms, highlightTerms) => {
-  const docBuilder = DOCUMENTATION_OPTIONS.BUILDER;
-  const docFileSuffix = DOCUMENTATION_OPTIONS.FILE_SUFFIX;
-  const docLinkSuffix = DOCUMENTATION_OPTIONS.LINK_SUFFIX;
-  const showSearchSummary = DOCUMENTATION_OPTIONS.SHOW_SEARCH_SUMMARY;
-  const contentRoot = document.documentElement.dataset.content_root;
-
-  const [docName, title, anchor, descr, score, _filename] = item;
-
-  let listItem = document.createElement("li");
-  let requestUrl;
-  let linkUrl;
-  if (docBuilder === "dirhtml") {
-    // dirhtml builder
-    let dirname = docName + "/";
-    if (dirname.match(/\/index\/$/))
-      dirname = dirname.substring(0, dirname.length - 6);
-    else if (dirname === "index/") dirname = "";
-    requestUrl = contentRoot + dirname;
-    linkUrl = requestUrl;
-  } else {
-    // normal html builders
-    requestUrl = contentRoot + docName + docFileSuffix;
-    linkUrl = docName + docLinkSuffix;
+if (!splitQuery) {
+  function splitQuery(query) {
+    return query.split(/\s+/);
   }
-  let linkEl = listItem.appendChild(document.createElement("a"));
-  linkEl.href = linkUrl + anchor;
-  linkEl.dataset.score = score;
-  linkEl.innerHTML = title;
-  if (descr) {
-    listItem.appendChild(document.createElement("span")).innerHTML =
-      " (" + descr + ")";
-    // highlight search terms in the description
-    if (SPHINX_HIGHLIGHT_ENABLED)  // set in sphinx_highlight.js
-      highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted"));
-  }
-  else if (showSearchSummary)
-    fetch(requestUrl)
-      .then((responseData) => responseData.text())
-      .then((data) => {
-        if (data)
-          listItem.appendChild(
-            Search.makeSearchSummary(data, searchTerms)
-          );
-        // highlight search terms in the summary
-        if (SPHINX_HIGHLIGHT_ENABLED)  // set in sphinx_highlight.js
-          highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted"));
-      });
-  Search.output.appendChild(listItem);
-};
-const _finishSearch = (resultCount) => {
-  Search.stopPulse();
-  Search.title.innerText = _("Search Results");
-  if (!resultCount)
-    Search.status.innerText = Documentation.gettext(
-      "Your search did not match any documents. Please make sure that all words are spelled correctly and that you've selected enough categories."
-    );
-  else
-    Search.status.innerText = _(
-      `Search finished, found ${resultCount} page(s) matching the search query.`
-    );
-};
-const _displayNextItem = (
-  results,
-  resultCount,
-  searchTerms,
-  highlightTerms,
-) => {
-  // results left, load the summary and display it
-  // this is intended to be dynamic (don't sub resultsCount)
-  if (results.length) {
-    _displayItem(results.pop(), searchTerms, highlightTerms);
-    setTimeout(
-      () => _displayNextItem(results, resultCount, searchTerms, highlightTerms),
-      5
-    );
-  }
-  // search finished, update title and status message
-  else _finishSearch(resultCount);
-};
-
-/**
- * Default splitQuery function. Can be overridden in ``sphinx.search`` with a
- * custom function per language.
- *
- * The regular expression works by splitting the string on consecutive characters
- * that are not Unicode letters, numbers, underscores, or emoji characters.
- * This is the same as ``\W+`` in Python, preserving the surrogate pair area.
- */
-if (typeof splitQuery === "undefined") {
-  var splitQuery = (query) => query
-      .split(/[^\p{Letter}\p{Number}_\p{Emoji_Presentation}]+/gu)
-      .filter(term => term)  // remove remaining empty strings
 }
 
 /**
  * Search Module
  */
-const Search = {
-  _index: null,
-  _queued_query: null,
-  _pulse_status: -1,
-
-  htmlToText: (htmlString) => {
-    const htmlElement = new DOMParser().parseFromString(htmlString, 'text/html');
-    htmlElement.querySelectorAll(".headerlink").forEach((el) => { el.remove() });
-    const docContent = htmlElement.querySelector('[role="main"]');
-    if (docContent !== undefined) return docContent.textContent;
-    console.warn(
-      "Content block not found. Sphinx search tries to obtain it via '[role=main]'. Could you check your theme or template."
-    );
-    return "";
+var Search = {
+
+  _index : null,
+  _queued_query : null,
+  _pulse_status : -1,
+
+  htmlToText : function(htmlString) {
+      var virtualDocument = document.implementation.createHTMLDocument('virtual');
+      var htmlElement = $(htmlString, virtualDocument);
+      htmlElement.find('.headerlink').remove();
+      docContent = htmlElement.find('[role=main]')[0];
+      if(docContent === undefined) {
+          console.warn("Content block not found. Sphinx search tries to obtain it " +
+                       "via '[role=main]'. Could you check your theme or template.");
+          return "";
+      }
+      return docContent.textContent || docContent.innerText;
   },
 
-  init: () => {
-    const query = new URLSearchParams(window.location.search).get("q");
-    document
-      .querySelectorAll('input[name="q"]')
-      .forEach((el) => (el.value = query));
-    if (query) Search.performSearch(query);
+  init : function() {
+      var params = $.getQueryParameters();
+      if (params.q) {
+          var query = params.q[0];
+          $('input[name="q"]')[0].value = query;
+          this.performSearch(query);
+      }
   },
 
-  loadIndex: (url) =>
-    (document.body.appendChild(document.createElement("script")).src = url),
+  loadIndex : function(url) {
+    $.ajax({type: "GET", url: url, data: null,
+            dataType: "script", cache: true,
+            complete: function(jqxhr, textstatus) {
+              if (textstatus != "success") {
+                document.getElementById("searchindexloader").src = url;
+              }
+            }});
+  },
 
-  setIndex: (index) => {
-    Search._index = index;
-    if (Search._queued_query !== null) {
-      const query = Search._queued_query;
-      Search._queued_query = null;
-      Search.query(query);
+  setIndex : function(index) {
+    var q;
+    this._index = index;
+    if ((q = this._queued_query) !== null) {
+      this._queued_query = null;
+      Search.query(q);
     }
   },
 
-  hasIndex: () => Search._index !== null,
-
-  deferQuery: (query) => (Search._queued_query = query),
+  hasIndex : function() {
+      return this._index !== null;
+  },
 
-  stopPulse: () => (Search._pulse_status = -1),
+  deferQuery : function(query) {
+      this._queued_query = query;
+  },
 
-  startPulse: () => {
-    if (Search._pulse_status >= 0) return;
+  stopPulse : function() {
+      this._pulse_status = 0;
+  },
 
-    const pulse = () => {
+  startPulse : function() {
+    if (this._pulse_status >= 0)
+        return;
+    function pulse() {
+      var i;
       Search._pulse_status = (Search._pulse_status + 1) % 4;
-      Search.dots.innerText = ".".repeat(Search._pulse_status);
-      if (Search._pulse_status >= 0) window.setTimeout(pulse, 500);
-    };
+      var dotString = '';
+      for (i = 0; i < Search._pulse_status; i++)
+        dotString += '.';
+      Search.dots.text(dotString);
+      if (Search._pulse_status > -1)
+        window.setTimeout(pulse, 500);
+    }
     pulse();
   },
 
   /**
    * perform a search for something (or wait until index is loaded)
    */
-  performSearch: (query) => {
+  performSearch : function(query) {
     // create the required interface elements
-    const searchText = document.createElement("h2");
-    searchText.textContent = _("Searching");
-    const searchSummary = document.createElement("p");
-    searchSummary.classList.add("search-summary");
-    searchSummary.innerText = "";
-    const searchList = document.createElement("ul");
-    searchList.classList.add("search");
-
-    const out = document.getElementById("search-results");
-    Search.title = out.appendChild(searchText);
-    Search.dots = Search.title.appendChild(document.createElement("span"));
-    Search.status = out.appendChild(searchSummary);
-    Search.output = out.appendChild(searchList);
-
-    const searchProgress = document.getElementById("search-progress");
-    // Some themes don't use the search progress node
-    if (searchProgress) {
-      searchProgress.innerText = _("Preparing search...");
-    }
-    Search.startPulse();
+    this.out = $('#search-results');
+    this.title = $('
    ' + _('Searching') + '
    ').appendTo(this.out);
+    this.dots = $('').appendTo(this.title);
+    this.status = $('
     
    ').appendTo(this.out);
+    this.output = $('
    
       
    
@@ -1778,8 +5125,8 @@ 
    Navigation
    
       
     
    
     
   
 
\ No newline at end of file
diff --git a/index.html b/index.html
index 60960417..106188e2 100644
--- a/index.html
+++ b/index.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    CHIPSEC 1.12.8 — CHIPSEC  documentation
-    
-    
+    
+    CHIPSEC — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
      
@@ -31,7 +32,7 @@ 
    Navigation
    
           next |
         
  • CHIPSEC  documentation »
    • 
-        
  • CHIPSEC 1.12.8
    •  
+        
  • CHIPSEC
    •  
       
     
      
 
@@ -40,8 +41,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    CHIPSEC 1.12.8
    
+  
    
+
    CHIPSEC
    
 
    CHIPSEC is a framework for analyzing platform level security of
 hardware, devices, system firmware, low-level protection mechanisms, and
 the configuration of various platform components.
    
@@ -76,8 +77,8 @@ 
    CHIPSEC 1.12.8Download CHIPSEC
 
 
    
-
    
-
    Installation
    
+
    
+
    Installation
    
 
    CHIPSEC supports Windows, Linux, Mac OS X, DAL and UEFI shell.
 Circumstances surrounding the target platform may change which of these
 environments is most appropriate.
    
@@ -90,9 +91,9 @@ 
    CHIPSEC 1.12.8Building a Bootable USB drive with UEFI Shell (x64)
 
 
    
-
    
-
    
-
    Using CHIPSEC
    
+
    
+
    
+
    Using CHIPSEC
    
 
    CHIPSEC should be launched as Administrator/root
    
 
    CHIPSEC will automatically attempt to create and start its service,
 including load its kernel-mode driver. If CHIPSEC service is already
@@ -106,9 +107,9 @@ 
    Using CHIPSECRunning CHIPSEC
 
 
    
-
-
    
-
    Module & Command Development
    
+
    
+
    
+
    Module & Command Development
    
 
    
 
    Architecture and Modules
    
 
 
    
-
-
    
-
    Contribution and Style Guides
    
+
    
+
    
+
    Contribution and Style Guides
    
 
    
 
    Contribution Guide
    
 
 
    
-
-
+
    
+
    
 
 
             
    
@@ -202,7 +203,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -220,12 +221,12 @@ 
    Navigation
    
           next |
         
  • CHIPSEC  documentation »
    • 
-        
  • CHIPSEC 1.12.8
    •  
+        
  • CHIPSEC
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/installation/InstallLinux.html b/installation/InstallLinux.html
index 8ba810e6..a570b421 100644
--- a/installation/InstallLinux.html
+++ b/installation/InstallLinux.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
+    
     Linux Installation — CHIPSEC  documentation
-    
-    
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
     
@@ -44,8 +45,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    Linux Installation
    
+  
    
+
    Linux Installation
    
 
    
 
    Tested on:
    
-
    
-
    Prerequisites
    
+
    
+
    
+
    Prerequisites
    
 
    Python 3.7 or higher (https://www.python.org/downloads/)
    
 
    
 
    Note
    
@@ -93,9 +94,9 @@ 
    Prerequisitespip install -r linux_requirements.txt
    
 
    
-
-
    
-
    Installing CHIPSEC
    
+
    
+
    
+
    Installing CHIPSEC
    
 
    Get latest CHIPSEC release from PyPI repository
    
 
    pip install chipsec
    
 
    
@@ -114,19 +115,19 @@ 
    Installing CHIPSECgit clone https://github.com/chipsec/chipsec.git
    
 
    
-
-
    
-
    Building CHIPSEC
    
+
    
+
    
+
    Building CHIPSEC
    
 
    Build the Driver and Compression Tools
    
 
    
 
    python setup.py build_ext -i
    
 
    
-
-
    
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    Run CHIPSEC
    
+
    
+
    
+
    Run CHIPSEC
    
 
    Follow steps in section “Using as a Python package” of Running CHIPSEC
    
-
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+
    
+
    
 
 
             
    
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    Quick search
    
     
     
    
 
    
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diff --git a/installation/InstallWinDAL.html b/installation/InstallWinDAL.html
index 22b268f1..6246f69d 100644
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+++ b/installation/InstallWinDAL.html
@@ -1,19 +1,20 @@
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    Navigation
    
         
    
           
    
             
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    DAL Windows Installation
    
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    Prerequisites
    
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    DAL Windows Installation
    
+
    
+
    Prerequisites
    
 
    Python 3.7 or higher (https://www.python.org/downloads/)
    
 
    
 
    Note
    
@@ -56,15 +57,15 @@ 
    Prerequisiteshttps://pypi.org/project/pywin32/#files)
    
 
    Intel System Studio: (https://software.intel.com/en-us/system-studio)
    
 
    git: open source distributed version control system (https://git-scm.com/)
    
-
    
-
    
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    Building
    
+
    
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    Building
    
 
    Clone CHIPSEC source
    
 
    
 
    git clone https://github.com/chipsec/chipsec.git
    
 
    
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index 73105d31..fe031ee3 100644
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     Windows Installation — CHIPSEC  documentation
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    Windows Installation
    
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    Windows Installation
    
 
    
 
    CHIPSEC supports the following versions:
    
 
    Windows 8, 8.1, 10, 11 - x86 and AMD64
    
@@ -55,8 +56,8 @@ 
    Windows InstallationNote
    
 
    CHIPSEC has removed support for the RWEverything (https://rweverything.com/) driver due to PCI configuration space access issues.
    
 
    
-
    
-
    Install CHIPSEC Dependencies
    
+
    
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    Install CHIPSEC Dependencies
    
 
    Python 3.7 or higher (https://www.python.org/downloads/)
    
 
    
 
    Note
    
@@ -87,9 +88,9 @@ 
    Install CHIPSEC Dependenciesgit: open source distributed version control system
    
 
    
-
    
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    Building
    
+
    
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    Turn off kernel driver signature checks
    
+
    
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    Turn off kernel driver signature checks
    
 
    Enable boot menu
    
 
    In CMD shell:
    
 
    
@@ -154,9 +155,9 @@ 
    Turn off kernel driver signature checks
-
    Alternate Build Methods
    
+
    
+
    
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    Alternate Build Methods
    
 
    Build CHIPSEC kernel driver with Visual Studio
    
 
    Method 1:
    
 
    
@@ -208,9 +209,9 @@ 
    Alternate Build Methods
    sc stop chipsec
 sc delete chipsec
    
 
    
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    Windows PCI Filter Driver
    
+
    
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    Windows PCI Filter Driver
    
 
    Filter driver background
    
 
    Since July 31, 2020 Microsoft has released Windows 2020-KB4568831 (OS Build 19041.423) Preview. Microsoft recommends to not access the PCI configuration space using the legacy API, as it might result in the Windows BSOD (Blue Screen of Death). The BSOD trigger condition is “Windows version >= (OS Build 19041.423) && Secure Devices (SDEV) ACPI table && VBS enabled”. Therefore, CHIPSEC now includes a PCI filter driver which supplements the original CHIPSEC Windows Driver to access the PCI configuration space. A system requires the PCI Filter Driver if the conditions above are met.
    
 
    Windows devices that receive the 2020-KB4568831 (OS Build 19041.423) Preview or later updates restrict how processes
@@ -224,94 +225,88 @@ 
    Windows PCI Filter Driverhttps://learn.microsoft.com/en-us/troubleshoot/windows-client/performance/stop-error-lenovo-thinkpad-kb4568831-uefi
    
 
    Filter Driver and Main Helper Driver Architecture
    
-
    
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 CHIPSEC Main & Filter Drvier Architecture
-
    
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    CHIPSEC Main & Filter Drvier Architecture
    
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    CHIPSEC Main & Filter Drvier Architecture
    
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    Locate the Filter Driver Files: chipsec/helper/windows/windows_amd64/
    
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-
    
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    Update The PCI Device Driver From Device Manager
    
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 Update The PCI Device Driver
-
    
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    Browse The PCI Filter Driver
    
 
    
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 Browse The PCI Filter Driver
-
    
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-
    
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    Install The Filter Driver From Disk
    
 
    
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 Install The Filter Driver From Disk
-
    
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    Installing The Filter Driver
    
 
    
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 Installing The Filter Driver
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 Finish The Filter Driver Installing
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    Restart Computer
    
 
    
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    Filter Driver Access PCI Config Space Test
    
 
    Dump PCI Config Test
    
 
    
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 Dump PCI Config
-
    
-
    py chipsec_util.py pci dump 0 0 0
    
-
    
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+
    py chipsec_util.py pci dump 0 0 0
    
+
    
 
    
 
    
-
    PCI Enumeration Test
    
+
    PCI Enumeration Test
    
 PCI Enumeration Test
-
    
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    py chipsec_util.py pci enumerate
    
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    py chipsec_util.py pci enumerate
    
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diff --git a/installation/USBwithUEFIShell.html b/installation/USBwithUEFIShell.html
index cafda5de..dc52b4c2 100644
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+++ b/installation/USBwithUEFIShell.html
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     Building a Bootable USB drive with UEFI Shell (x64) — CHIPSEC  documentation
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    Building a Bootable USB drive with UEFI Shell (x64)
    
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    Building a Bootable USB drive with UEFI Shell (x64)
    
 
      
 
    1. Format your media as FAT32
      2. 
 
    2. Create the following directory structure in the root of the new media
      
@@ -61,8 +62,8 @@ 
      Building a Bootable USB drive with UEFI Shell (x64)
      Rename the UEFI shell file to Bootx64.efi
      3. 
 
    3. Copy the UEFI shell (now Bootx64.efi) to the /efi/boot directory
      4. 
 
    
-
    
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    Installing CHIPSEC
    
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    Installing CHIPSEC
    
 
      
 
    1. Extract the contents of __install__/UEFI/chipsec_py368_uefi_x64.zip to the USB drive, as appropriate.
      
 
    
+
    
+
    Run CHIPSEC in UEFI Shell
    
 
    
 
    fs0:
    
 
    cd chipsec
    
 
    python.efi chipsec_main.py or python.efi chipsec_util.py
    
 
    Next follow steps in section “Basic Usage” of Running CHIPSEC
    
 
    
-
    
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    Building UEFI Python 3.6.8 (optional)
    
 
      
 
    1. Start with Py368Readme.txt
      
 
      
@@ -151,8 +152,8 @@ 
      Building UEFI Python 3.6.8 (optional)
    
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diff --git a/modules/chipsec.cfg.8086.adl.xml.html b/modules/chipsec.cfg.8086.adl.xml.html
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    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
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-chipsec@intel.com
    
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-document id 334818/334819
    
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    XML configuration file for Broadwell Server based platforms
-Intel (c) Xeon Processor E5 v4 Product Family datasheet Vol. 2
-Intel (c) Xeon Processor E7 v4 Product Family datasheet Vol. 2
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
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-Document ID: 635255, 636112, 636722, 636723
    
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-Intel (c) Xeon Processor E5-1600/2400/2600/4600 v3 Product Family datasheet Vol. 2
-Intel (c) Xeon Processor E7-8800/4800 v3 Product Family datasheet Vol. 2
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
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    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2020-2021, Intel Corporation
    
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    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
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    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
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-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
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-https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-pch-datasheet-vol-2.html
-337348-001
    
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    XML configuration file for the 300 series LP (U/Y) PCH
-https://www.intel.com/content/www/us/en/products/docs/processors/core/7th-and-8th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-2.html
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-https://www.intel.com/content/www/us/en/products/docs/chipsets/300-series-chipset-on-package-pch-datasheet-vol-2.html
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-  
-      
-
-    
    
-      
    
-        
    
-          
    
-            
-  
    
-
    pch_5xxh
    
-
    Path: chipsec\cfg\8086\pch_5xxh.xml
    
-
    XML configuration file for 5XXH series pch
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
-    
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diff --git a/modules/chipsec.cfg.8086.pch_5xxlp.xml.html b/modules/chipsec.cfg.8086.pch_5xxlp.xml.html
deleted file mode 100644
index 5eb4d277..00000000
--- a/modules/chipsec.cfg.8086.pch_5xxlp.xml.html
+++ /dev/null
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-
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-    pch_5xxlp — CHIPSEC  documentation
-    
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-  
    
-
    pch_5xxlp
    
-
    Path: chipsec\cfg\8086\pch_5xxlp.xml
    
-
    XML configuration file for 5XXLP series pch
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
-    
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diff --git a/modules/chipsec.cfg.8086.pch_6xxP.xml.html b/modules/chipsec.cfg.8086.pch_6xxP.xml.html
deleted file mode 100644
index 104601ee..00000000
--- a/modules/chipsec.cfg.8086.pch_6xxP.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
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-    
-    
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-    pch_6xxP — CHIPSEC  documentation
-    
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-    
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-     
-  
-      
-
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-      
    
-        
    
-          
    
-            
-  
    
-
    pch_6xxP
    
-
    Path: chipsec\cfg\8086\pch_6xxP.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
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-            
    
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-        
    
-      
    
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diff --git a/modules/chipsec.cfg.8086.pch_6xxS.xml.html b/modules/chipsec.cfg.8086.pch_6xxS.xml.html
deleted file mode 100644
index ede556e8..00000000
--- a/modules/chipsec.cfg.8086.pch_6xxS.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
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-    pch_6xxS — CHIPSEC  documentation
-    
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-
    pch_6xxS
    
-
    Path: chipsec\cfg\8086\pch_6xxS.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021-2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
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-  
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.pch_7x.xml.html b/modules/chipsec.cfg.8086.pch_7x.xml.html
deleted file mode 100644
index 7cbeb35a..00000000
--- a/modules/chipsec.cfg.8086.pch_7x.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
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-
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-    pch_7x — CHIPSEC  documentation
-    
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    pch_7x
    
-
    Path: chipsec\cfg\8086\pch_7x.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.pch_8x.xml.html b/modules/chipsec.cfg.8086.pch_8x.xml.html
deleted file mode 100644
index 88bdec7f..00000000
--- a/modules/chipsec.cfg.8086.pch_8x.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-
-  
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-    pch_8x — CHIPSEC  documentation
-    
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-            
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-
    pch_8x
    
-
    Path: chipsec\cfg\8086\pch_8x.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.pch_c60x.xml.html b/modules/chipsec.cfg.8086.pch_c60x.xml.html
deleted file mode 100644
index 66d53872..00000000
--- a/modules/chipsec.cfg.8086.pch_c60x.xml.html
+++ /dev/null
@@ -1,159 +0,0 @@
-
-
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-  
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-    pch_c60x — CHIPSEC  documentation
-    
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-  
    
-
    pch_c60x
    
-
    Path: chipsec\cfg\8086\pch_c60x.xml
    
-
    
-
    XML configuration file for C600 series PCH
    Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset datasheet
-Intel (c) C600 Series Chipset and Intel (c) X79 Express Chipset Specification Update
-https://ark.intel.com/products/series/98463/Intel-C600-Series-Chipsets
    
-
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.pch_c61x.xml.html b/modules/chipsec.cfg.8086.pch_c61x.xml.html
deleted file mode 100644
index a79e8168..00000000
--- a/modules/chipsec.cfg.8086.pch_c61x.xml.html
+++ /dev/null
@@ -1,158 +0,0 @@
-
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-    pch_c61x — CHIPSEC  documentation
-    
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    pch_c61x
    
-
    Path: chipsec\cfg\8086\pch_c61x.xml
    
-
    
-
    XML configuration file for C610 series PCH
    Intel (c) C610 Series Chipset and Intel (c) X99 Chipset Platform Controller Hub (PCH) datasheet
-https://ark.intel.com/products/series/98915/Intel-C610-Series-Chipsets
    
-
    
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diff --git a/modules/chipsec.cfg.8086.pch_c620.xml.html b/modules/chipsec.cfg.8086.pch_c620.xml.html
deleted file mode 100644
index 666187bd..00000000
--- a/modules/chipsec.cfg.8086.pch_c620.xml.html
+++ /dev/null
@@ -1,158 +0,0 @@
-
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-    pch_c620 — CHIPSEC  documentation
-    
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    pch_c620
    
-
    Path: chipsec\cfg\8086\pch_c620.xml
    
-
    XML configuration file for
    
-
-
    
-
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diff --git a/modules/chipsec.cfg.8086.pmc_i440fx.xml.html b/modules/chipsec.cfg.8086.pmc_i440fx.xml.html
deleted file mode 100644
index b8565220..00000000
--- a/modules/chipsec.cfg.8086.pmc_i440fx.xml.html
+++ /dev/null
@@ -1,157 +0,0 @@
-
-
-
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-    pmc_i440fx — CHIPSEC  documentation
-    
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-  
    
-
    pmc_i440fx
    
-
    Path: chipsec\cfg\8086\pmc_i440fx.xml
    
-
    XML configuration file for Intel 440FX PCI and Memory Controller (PMC).
-It is used by QEMU “pc” machine, implemented in
-https://github.com/qemu/qemu/blob/v7.0.0/hw/pci-host/i440fx.c
    
-
    A datasheet is available on https://wiki.qemu.org/File:29054901.pdf
    
-
    
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diff --git a/modules/chipsec.cfg.8086.qrk.xml.html b/modules/chipsec.cfg.8086.qrk.xml.html
deleted file mode 100644
index bcb20816..00000000
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+++ /dev/null
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-
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-    qrk — CHIPSEC  documentation
-    
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    qrk
    
-
    Path: chipsec\cfg\8086\qrk.xml
    
-
    XML configuration for Quark based platforms
    
-
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.rkl.xml.html b/modules/chipsec.cfg.8086.rkl.xml.html
deleted file mode 100644
index ee094d7b..00000000
--- a/modules/chipsec.cfg.8086.rkl.xml.html
+++ /dev/null
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-    rkl — CHIPSEC  documentation
-    
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-
    rkl
    
-
    Path: chipsec\cfg\8086\rkl.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
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-      
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.rpl.xml.html b/modules/chipsec.cfg.8086.rpl.xml.html
deleted file mode 100644
index 249a4de3..00000000
--- a/modules/chipsec.cfg.8086.rpl.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
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-    rpl — CHIPSEC  documentation
-    
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-
    rpl
    
-
    Path: chipsec\cfg\8086\rpl.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
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-            
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.sfdp.xml.html b/modules/chipsec.cfg.8086.sfdp.xml.html
deleted file mode 100644
index f0b5dfa2..00000000
--- a/modules/chipsec.cfg.8086.sfdp.xml.html
+++ /dev/null
@@ -1,155 +0,0 @@
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-    sfdp — CHIPSEC  documentation
-    
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-
    sfdp
    
-
    Path: chipsec\cfg\8086\sfdp.xml
    
-
    XML configuration for Serial Flash Discoverable Parameter feature
-document: https://www.jedec.org/system/files/docs/JESD216D-01.pdf
    
-
    
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diff --git a/modules/chipsec.cfg.8086.skl.xml.html b/modules/chipsec.cfg.8086.skl.xml.html
deleted file mode 100644
index 8fd6fc13..00000000
--- a/modules/chipsec.cfg.8086.skl.xml.html
+++ /dev/null
@@ -1,162 +0,0 @@
-
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-    skl — CHIPSEC  documentation
-    
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-
    skl
    
-
    Path: chipsec\cfg\8086\skl.xml
    
-
    XML configuration file for Skylake based platforms
    
-
    http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
    
-
      
-
    • 6th Generation Intel(R) Processor Datasheet for U/Y-Platforms
      • 
-
    • 6th Generation Intel(R) Processor I/O Datasheet for U/Y-Platforms
      • 
-
    • 6th Generation Intel(R) Processor Datasheet for S-Platforms
      • 
-
    • 6th Generation Intel(R) Processor Datasheet for H-Platforms
      • 
-
    • Intel(R) 100 Series Chipset Family Platform Controller Hub (PCH)
      • 
-
    
-
    
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diff --git a/modules/chipsec.cfg.8086.skx.xml.html b/modules/chipsec.cfg.8086.skx.xml.html
deleted file mode 100644
index b931580d..00000000
--- a/modules/chipsec.cfg.8086.skx.xml.html
+++ /dev/null
@@ -1,155 +0,0 @@
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-    skx — CHIPSEC  documentation
-    
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-
    skx
    
-
    Path: chipsec\cfg\8086\skx.xml
    
-
    XML configuration file for Skylake/Purely Server
-Intel (c) Xeon Processor Scalable Family datasheet Vol. 2
    
-
    
-
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diff --git a/modules/chipsec.cfg.8086.snb.xml.html b/modules/chipsec.cfg.8086.snb.xml.html
deleted file mode 100644
index 89857891..00000000
--- a/modules/chipsec.cfg.8086.snb.xml.html
+++ /dev/null
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-    snb — CHIPSEC  documentation
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    snb
    
-
    Path: chipsec\cfg\8086\snb.xml
    
-
    XML configuration for Sandy Bridge based platforms
    
-
    
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diff --git a/modules/chipsec.cfg.8086.tglh.xml.html b/modules/chipsec.cfg.8086.tglh.xml.html
deleted file mode 100644
index e7c8e2b6..00000000
--- a/modules/chipsec.cfg.8086.tglh.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
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-    tglh — CHIPSEC  documentation
-    
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    tglh
    
-
    Path: chipsec\cfg\8086\tglh.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2022, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
-    
-    
-  
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.tglu.xml.html b/modules/chipsec.cfg.8086.tglu.xml.html
deleted file mode 100644
index 4fd1fbf8..00000000
--- a/modules/chipsec.cfg.8086.tglu.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-
-  
-    
-    
-
-    tglu — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    
    
-      
    
-        
    
-          
    
-            
-  
    
-
    tglu
    
-
    Path: chipsec\cfg\8086\tglu.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
-    
-    
-  
-
\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.tpm12.xml.html b/modules/chipsec.cfg.8086.tpm12.xml.html
deleted file mode 100644
index adf7ee0f..00000000
--- a/modules/chipsec.cfg.8086.tpm12.xml.html
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-
-  
-    
-    
-
-    tpm12 — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    
    
-      
    
-        
    
-          
    
-            
-  
    
-
    tpm12
    
-
    Path: chipsec\cfg\8086\tpm12.xml
    
-
    CHIPSEC: Platform Security Assessment Framework
-Copyright (c) 2021, Intel Corporation
    
-
    This program is free software; you can redistribute it and/or
-modify it under the terms of the GNU General Public License
-as published by the Free Software Foundation; Version 2.
    
-
    This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
    
-
    You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    
-
    Contact information:
-chipsec@intel.com
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
-    
    
-    
-    
-  
-
\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.txt.xml.html b/modules/chipsec.cfg.8086.txt.xml.html
deleted file mode 100644
index dbdfd6f8..00000000
--- a/modules/chipsec.cfg.8086.txt.xml.html
+++ /dev/null
@@ -1,171 +0,0 @@
-
-
-
-  
-    
-    
-
-    txt — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    
    
-      
    
-        
    
-          
    
-            
-  
    
-
    txt
    
-
    Path: chipsec\cfg\8086\txt.xml
    
-
    Configuration of Intel TXT register, following the guide:
    
-
    
-
    Intel® Trusted Execution Technology: Software Development Guide
-Measured Launched Environment Developer’s Guide
-August 2016
-Revision 013
    
-
    
-
    from https://web.archive.org/web/20170506220426/https://www.intel.com/content/www/us/en/software-developers/intel-txt-software-development-guide.html
-(and https://usermanual.wiki/Document/inteltxtsoftwaredevelopmentguide.1721028921 )
    
-
    Appendix B.1. (Intel® TXT Configuration Registers) details:
    
-
    
-
    These registers are mapped into two regions of memory, representing the public and private configuration spaces.
-[…]
-The private space registers are mapped to the address range starting at FED20000H.
-The public space registers are mapped to the address range starting at FED30000H.
    
-
    
-
    As chipsec usually runs in environments where the private space is not available,
-only the public space registers were described here.
    
-
    
-
-
-            
    
-          
    
-        
    
-      
    
-      
-      
    
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\ No newline at end of file
diff --git a/modules/chipsec.cfg.8086.whl.xml.html b/modules/chipsec.cfg.8086.whl.xml.html
deleted file mode 100644
index 65f1a9cb..00000000
--- a/modules/chipsec.cfg.8086.whl.xml.html
+++ /dev/null
@@ -1,161 +0,0 @@
-
-
-
-  
-    
-    
-
-    whl — CHIPSEC  documentation
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-    
-     
-  
-      
-
-    
    
-      
    
-        
    
-          
    
-            
-  
    
-
    whl
    
-
    Path: chipsec\cfg\8086\whl.xml
    
-
    XML configuration file for Whiskey Lake
    
-
    
-
    8th Generation Intel(R) Processor Family for U-Processor Platforms:
    
-
    
-
    
-
    
-
-
-            
    
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diff --git a/modules/chipsec.cfg.parsers.core_parsers.html b/modules/chipsec.cfg.parsers.core_parsers.html
index 00114ffa..b7210484 100644
--- a/modules/chipsec.cfg.parsers.core_parsers.html
+++ b/modules/chipsec.cfg.parsers.core_parsers.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    core_parsers module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.cfg.parsers.core_parsers module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • core_parsers module
    •  
+        
  • chipsec.cfg.parsers.core_parsers module
    •  
       
     
      
 
@@ -36,9 +37,86 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    core_parsers module
    
-
    
+  
    
+
    chipsec.cfg.parsers.core_parsers module
    
+
    
+
    
+class CoreConfig(cfg_obj)[source]
    
+
    Bases: chipsec.parsers.BaseConfigParser
    
+
    
+
    
+get_metadata()[source]
    
+
    
+
+
    
+
    
+get_stage()[source]
    
+
    
+
+
    
+
    
+handle_controls(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_ima(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_io(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_locks(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_memory(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_mmio(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_pci(et_node, stage_data)[source]
    
+
    
+
+
    
+
    
+handle_registers(et_node, stage_data)[source]
    
+
    
+
+
    
+
+
    
+
    
+class PlatformInfo(cfg_obj)[source]
    
+
    Bases: chipsec.parsers.BaseConfigParser
    
+
    
+
    
+get_metadata()[source]
    
+
    
+
+
    
+
    
+get_stage()[source]
    
+
    
+
+
    
+
    
+handle_info(et_node, stage_data)[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -98,7 +176,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +191,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • core_parsers module
    •  
+        
  • chipsec.cfg.parsers.core_parsers module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.cfg.parsers.html b/modules/chipsec.cfg.parsers.html
index 119854ea..6edcb687 100644
--- a/modules/chipsec.cfg.parsers.html
+++ b/modules/chipsec.cfg.parsers.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    parsers package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.cfg.parsers package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • parsers package
    •  
+        
  • chipsec.cfg.parsers package
    •  
       
     
      
 
@@ -36,14 +37,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    parsers package
    
+  
    
+
    chipsec.cfg.parsers package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -103,7 +110,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -118,12 +125,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • parsers package
    •  
+        
  • chipsec.cfg.parsers package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.config.html b/modules/chipsec.config.html
index 9c4ee824..0069653b 100644
--- a/modules/chipsec.config.html
+++ b/modules/chipsec.config.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    config module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.config module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • config module
    •  
+        
  • chipsec.config module
    •  
       
     
      
 
@@ -36,9 +37,80 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    config module
    
-
    
+  
    
+
    chipsec.config module
    
+
    
+
    
+class Cfg[source]
    
+
    Bases: object
    
+
    
+
    
+add_extra_configs(path, filename=None, loadnow=False)[source]
    
+
    
+
+
    
+
    
+get_chipset_code()[source]
    
+
    
+
+
    
+
    
+get_common_xml()[source]
    
+
    
+
+
    
+
    
+get_pch_code()[source]
    
+
    
+
+
    
+
    
+is_pch_req()[source]
    
+
    
+
+
    
+
    
+load_parsers()[source]
    
+
    
+
+
    
+
    
+load_platform_config()[source]
    
+
    
+
+
    
+
    
+load_platform_info()[source]
    
+
    
+
+
    
+
    
+platform_detection(proc_code, pch_code, cpuid)[source]
    
+
    
+
+
    
+
    
+print_pch_info()[source]
    
+
    
+
+
    
+
    
+print_platform_info()[source]
    
+
    
+
+
    
+
    
+print_supported_chipsets()[source]
    
+
    
+
+
    
+
    
+set_pci_data(enum_devices)[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -98,7 +170,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +185,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • config module
    •  
+        
  • chipsec.config module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.fuzzing.html b/modules/chipsec.fuzzing.html
index e259572e..e688c0f9 100644
--- a/modules/chipsec.fuzzing.html
+++ b/modules/chipsec.fuzzing.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    fuzzing package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.fuzzing package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -45,14 +46,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    fuzzing package
    
+  
    
+
    chipsec.fuzzing package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -106,12 +113,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    vmm module
    
+                          title="previous chapter">chipsec.hal.vmm module
    
   
    
   
    
     
    Next topic
    
     
    primitives module
    
+                          title="next chapter">chipsec.fuzzing.primitives module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -137,19 +144,19 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-        
  • fuzzing package
    •  
+        
  • chipsec.fuzzing package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.fuzzing.primitives.html b/modules/chipsec.fuzzing.primitives.html
index 60737261..7e3da520 100644
--- a/modules/chipsec.fuzzing.primitives.html
+++ b/modules/chipsec.fuzzing.primitives.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    primitives module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.fuzzing.primitives module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
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+    
     
     
     
-     
+     
   
       
 
@@ -46,9 +47,233 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    primitives module
    
-
    
+  
    
+
    chipsec.fuzzing.primitives module
    
+
    
+
    
+class base_primitive[source]
    
+
    Bases: object
    
+
    The primitive base class implements common functionality shared across most primitives.
    
+
    
+
    
+exhaust()[source]
    
+
    Exhaust the possible mutations for this primitive.
    
+
    @rtype:  Integer
+@return: The number of mutations to reach exhaustion
    
+
    
+
+
    
+
    
+mutate()[source]
    
+
    Mutate the primitive by stepping through the fuzz library, return False on completion.
    
+
    @rtype:  Boolean
+@return: True on success, False otherwise.
    
+
    
+
+
    
+
    
+num_mutations()[source]
    
+
    Calculate and return the total number of mutations for this individual primitive.
    
+
    @rtype:  Integer
+@return: Number of mutated forms this primitive can take
    
+
    
+
+
    
+
    
+render()[source]
    
+
    Nothing fancy on render, simply return the value.
    
+
    
+
+
    
+
    
+reset()[source]
    
+
    Reset this primitive to the starting mutation state.
    
+
    
+
+
    
+
+
    
+
    
+class bit_field(value, width, max_num=None, endian='<', format='binary', signed=False, full_range=False, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
    
+add_integer_boundaries(integer)[source]
    
+
    Add the supplied integer and border cases to the integer fuzz heuristics library.
    
+
    @type  integer: Int
+@param integer: Integer to append to fuzz heuristics
    
+
    
+
+
    
+
    
+render()[source]
    
+
    Render the primitive.
    
+
    
+
+
    
+
    
+to_binary(number=None, bit_count=None)[source]
    
+
    Convert a number to a binary string.
    
+
    @type  number:    Integer
+@param number:    (Optional, def=self.value) Number to convert
+@type  bit_count: Integer
+@param bit_count: (Optional, def=self.width) Width of bit string
    
+
    @rtype:  String
+@return: Bit string
    
+
    
+
+
    
+
    
+to_decimal(binary)[source]
    
+
    Convert a binary string to a decimal number.
    
+
    @type  binary: String
+@param binary: Binary string
    
+
    @rtype:  Integer
+@return: Converted bit string
    
+
    
+
+
    
+
+
    
+
    
+class byte(value, endian='<', format='binary', signed=False, full_range=False, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.bit_field
    
+
    
+
+
    
+
    
+class delim(value, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
+
    
+
    
+class dword(value, endian='<', format='binary', signed=False, full_range=False, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.bit_field
    
+
    
+
+
    
+
    
+class group(name, values)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
    
+mutate()[source]
    
+
    Move to the next item in the values list.
    
+
    @rtype:  False
+@return: False
    
+
    
+
+
    
+
    
+num_mutations()[source]
    
+
    Number of values in this primitive.
    
+
    @rtype:  Integer
+@return: Number of values in this primitive.
    
+
    
+
+
    
+
+
    
+
    
+class qword(value, endian='<', format='binary', signed=False, full_range=False, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.bit_field
    
+
    
+
+
    
+
    
+class random_data(value, min_length, max_length, max_mutations=25, fuzzable=True, step=None, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
    
+mutate()[source]
    
+
    Mutate the primitive value returning False on completion.
    
+
    @rtype:  Boolean
+@return: True on success, False otherwise.
    
+
    
+
+
    
+
    
+num_mutations()[source]
    
+
    Calculate and return the total number of mutations for this individual primitive.
    
+
    @rtype:  Integer
+@return: Number of mutated forms this primitive can take
    
+
    
+
+
    
+
+
    
+
    
+class static(value, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
    
+mutate()[source]
    
+
    Do nothing.
    
+
    @rtype:  False
+@return: False
    
+
    
+
+
    
+
    
+num_mutations()[source]
    
+
    Return 0.
    
+
    @rtype:  0
+@return: 0
    
+
    
+
+
    
+
+
    
+
    
+class string(value, size=- 1, padding='\x00', encoding='ascii', fuzzable=True, max_len=0, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.base_primitive
    
+
    
+
    
+add_long_strings(sequence)[source]
    
+
    Given a sequence, generate a number of selectively chosen strings lengths of the given sequence and add to the
+string heuristic library.
    
+
    @type  sequence: String
+@param sequence: Sequence to repeat for creation of fuzz strings.
    
+
    
+
+
    
+
    
+fuzz_library = []
    
+
    
+
+
    
+
    
+mutate()[source]
    
+
    Mutate the primitive by stepping through the fuzz library extended with the “this” library, return False on
+completion.
    
+
    @rtype:  Boolean
+@return: True on success, False otherwise.
    
+
    
+
+
    
+
    
+num_mutations()[source]
    
+
    Calculate and return the total number of mutations for this individual primitive.
    
+
    @rtype:  Integer
+@return: Number of mutated forms this primitive can take
    
+
    
+
+
    
+
    
+render()[source]
    
+
    Render the primitive, encode the string according to the specified encoding.
    
+
    
+
+
    
+
+
    
+
    
+class word(value, endian='<', format='binary', signed=False, full_range=False, fuzzable=True, name=None)[source]
    
+
    Bases: chipsec.fuzzing.primitives.bit_field
    
+
    
+
+
    
 
 
             
    
@@ -102,7 +327,7 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    fuzzing package
    
+                          title="previous chapter">chipsec.fuzzing package
    
   
    
   
    
     
    Next topic
    
@@ -118,7 +343,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -136,17 +361,17 @@ 
    Navigation
    
           next |
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • fuzzing package »
    • 
-        
  • primitives module
    •  
+          
  • chipsec.fuzzing package »
    • 
+        
  • chipsec.fuzzing.primitives module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.acpi.html b/modules/chipsec.hal.acpi.html
index 2139047e..06f78afa 100644
--- a/modules/chipsec.hal.acpi.html
+++ b/modules/chipsec.hal.acpi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    acpi module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.acpi module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,89 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    acpi module
    
+  
    
+
    chipsec.hal.acpi module
    
 
    HAL component providing access to and decoding of ACPI tables
    
-
    
+
    
+
    
+class ACPI(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+ParseTable
    
+
    alias of Tuple[chipsec.hal.acpi.ACPI_TABLE_HEADER, Optional[chipsec.hal.acpi_tables.ACPI_TABLE], bytes, bytes]
    
+
    
+
+
    
+
    
+RsdtXsdt
    
+
    alias of Union[chipsec.hal.acpi_tables.RSDT, chipsec.hal.acpi_tables.XSDT]
    
+
    
+
+
    
+
    
+dump_ACPI_table(name: str, isfile: bool = False) → None[source]
    
+
    
+
+
    
+
    
+find_RSDP() → Tuple[Optional[int], Optional[chipsec.hal.acpi_tables.RSDP]][source]
    
+
    
+
+
    
+
    
+get_ACPI_table(name: str, isfile: bool = False) → List[Tuple[bytes, bytes]][source]
    
+
    
+
+
    
+
    
+get_ACPI_table_list() → Dict[str, List[int]][source]
    
+
    
+
+
    
+
    
+get_DSDT_from_FADT() → None[source]
    
+
    
+
+
    
+
    
+get_SDT(search_rsdp: bool = True) → Tuple[bool, Optional[int], Optional[Union[chipsec.hal.acpi_tables.RSDT, chipsec.hal.acpi_tables.XSDT]], Optional[chipsec.hal.acpi.ACPI_TABLE_HEADER]][source]
    
+
    
+
+
    
+
    
+get_parse_ACPI_table(name: str, isfile: bool = False) → List[ParseTable][source]
    
+
    
+
+
    
+
    
+get_table_list_from_SDT(sdt: Union[chipsec.hal.acpi_tables.RSDT, chipsec.hal.acpi_tables.XSDT], is_xsdt: bool) → None[source]
    
+
    
+
+
    
+
    
+is_ACPI_table_present(name: str) → bool[source]
    
+
    
+
+
    
+
    
+print_ACPI_table_list() → None[source]
    
+
    
+
+
    
+
    
+read_RSDP(rsdp_pa: int) → chipsec.hal.acpi_tables.RSDP[source]
    
+
    
+
+
    
+
+
    
+
    
+class ACPI_TABLE_HEADER(Signature, Length, Revision, Checksum, OEMID, OEMTableID, OEMRevision, CreatorID, CreatorRevision)[source]
    
+
    Bases: chipsec.hal.acpi.ACPI_TABLE_HEADER
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +183,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    hal package
    
+                          title="previous chapter">chipsec.hal package
    
   
    
   
    
     
    Next topic
    
     
    acpi_tables module
    
+                          title="next chapter">chipsec.hal.acpi_tables module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +214,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • acpi module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.acpi module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.acpi_tables.html b/modules/chipsec.hal.acpi_tables.html
index 46f10cca..beb25700 100644
--- a/modules/chipsec.hal.acpi_tables.html
+++ b/modules/chipsec.hal.acpi_tables.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    acpi_tables module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.acpi_tables module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,563 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    acpi_tables module
    
+  
    
+
    chipsec.hal.acpi_tables module
    
 
    HAL component decoding various ACPI tables
    
-
    
+
    
+
    
+class ACPI_TABLE[source]
    
+
    Bases: object
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_GICC_CPU(Type, Length, Reserved, CPUIntNumber, ACPIProcUID, Flags, ParkingProtocolVersion, PerformanceInterruptGSIV, ParkedAddress, PhysicalAddress, GICV, GICH, VGICMaintenanceINterrupt, GICRBaseAddress, MPIDR)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GICC_CPU
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_GIC_DISTRIBUTOR(Type, Length, Reserved, GICID, PhysicalBaseAddress, SystemVectorBase, Reserved2)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GIC_DISTRIBUTOR
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_GIC_MSI(Type, Length, Reserved, GICMSIFrameID, PhysicalBaseAddress, Flags, SPICount, SPIBase)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GIC_MSI
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_GIC_REDISTRIBUTOR(Type, Length, Reserved, DiscoverRangeBaseAdd, DiscoverRangeLength)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GIC_REDISTRIBUTOR
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE(Type, Length, Bus, Source, GlobalSysIntBase, Flags)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_IOAPIC(Type, Length, IOAPICID, Reserved, IOAPICAddr, GlobalSysIntBase)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOAPIC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_IOSAPIC(Type, Length, IOAPICID, Reserved, GlobalSysIntBase, IOSAPICAddress)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOSAPIC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE(Type, Length, Reserved, LocalAPICAddress)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_LAPIC_NMI(Type, Length, ACPIProcessorID, Flags, LocalAPICLINT)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_NMI
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_Lx2APIC_NMI(Type, Length, Flags, ACPIProcUID, Localx2APICLINT, Reserved)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_Lx2APIC_NMI
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_NMI_SOURCE(Type, Length, Flags, GlobalSysIntBase)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_NMI_SOURCE
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES(Type, Length, Flags, InterruptType, ProcID, ProcEID, IOSAPICVector, GlobalSystemInterrupt, PlatIntSourceFlags)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_PROCESSOR_LAPIC(Type, Length, ACPIProcID, APICID, Flags)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_LAPIC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_PROCESSOR_LSAPIC(Type, Length, ACPIProcID, LocalSAPICID, LocalSAPICEID, Reserved, Flags, ACPIProcUIDValue, ACPIProcUIDString)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_LSAPIC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_APIC_PROCESSOR_Lx2APIC(Type, Length, Reserved, x2APICID, Flags, ACPIProcUID)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_Lx2APIC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_ANDD(Type, Length, Reserved, ACPIDevNum, ACPIObjectName)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ANDD
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_ATSR(Type, Length, Flags, Reserved, SegmentNumber, DeviceScope)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ATSR
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_DRHD(Type, Length, Flags, Reserved, SegmentNumber, RegisterBaseAddr, DeviceScope)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DRHD
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_DeviceScope(Type, Length, Flags, Reserved, EnumerationID, StartBusNum, Path)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DeviceScope
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_RHSA(Type, Length, Reserved, RegisterBaseAddr, ProximityDomain)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_RHSA
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_RMRR(Type, Length, Reserved, SegmentNumber, RMRBaseAddr, RMRLimitAddr, DeviceScope)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_RMRR
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_SATC(Type, Length, Flags, Reserved, SegmentNumber, DeviceScope)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_SATC
    
+
    
+
+
    
+
    
+class ACPI_TABLE_DMAR_SIDP(Type, Length, Reserved, SegmentNumber, DeviceScope)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_SIDP
    
+
    
+
+
    
+
    
+class APIC[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+get_structure_APIC(value: int, DataStructure: bytes) → str[source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class BERT(bootRegion: bytes)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseErrorBlock(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseGenErrorEntries(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseSectionType(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseTime(table_content: bytes) → str[source]
    
+
    
+
+
    
+
+
    
+
    
+class BGRT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class DMAR[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class EINJ[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseAddress(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseInjection(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseInjectionActionTable(table_contents: bytes, numInjections: int) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class ERST[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseActionTable(table_content: bytes, instrCountEntry: int) → None[source]
    
+
    
+
+
    
+
    
+parseAddress(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseInstructionEntry(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class FADT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+get_DSDT_address_to_use() → Optional[int][source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class GAS(table_content: bytes)[source]
    
+
    Bases: object
    
+
    
+
    
+get_info() → Tuple[int, int, int, int, int][source]
    
+
    
+
+
    
+
+
    
+
    
+class HEST[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+machineBankParser(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseAMCES(table_content: bytes) → int[source]
    
+
    
+
+
    
+
    
+parseAMCS(table_content: bytes, _type: int) → int[source]
    
+
    
+
+
    
+
    
+parseAddress(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseErrEntry(table_content: bytes) → Optional[int][source]
    
+
    
+
+
    
+
    
+parseGHESS(table_content: bytes, _type: int) → int[source]
    
+
    
+
+
    
+
    
+parseNMIStructure(table_content: bytes) → int[source]
    
+
    
+
+
    
+
    
+parseNotify(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parsePCIe(table_content: bytes, _type: int) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+class MSCT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseProx(table_content: bytes, val: int) → str[source]
    
+
    
+
+
    
+
    
+parseProxDomInfoStruct(table_contents: bytes, num: int) → str[source]
    
+
    
+
+
    
+
+
    
+
    
+class NFIT(header)[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+flushHintAddrStruct(tableLen: int, table_content: bytes) → Tuple[int, str][source]
    
+
    
+
+
    
+
    
+interleave(tableLen: int, table_content: bytes) → Tuple[int, str][source]
    
+
    
+
+
    
+
    
+nvdimmBlockDataWindowsRegionStruct(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+nvdimmControlRegionStructMark(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseMAP(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseSPA(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseStructures(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+platCapStruct(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+smbiosManagementInfo(tableLen: int, table_content: bytes) → str[source]
    
+
    
+
+
    
+
+
    
+
    
+class RASF[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class RSDP[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+is_RSDP_valid() → bool[source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class RSDT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class SPMI[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
    
+parseAddress(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseNonUID(table_content: bytes) → str[source]
    
+
    
+
+
    
+
    
+parseUID(table_content: bytes) → str[source]
    
+
    
+
+
    
+
+
    
+
    
+class UEFI_TABLE[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+CommBuffInfo
    
+
    alias of Tuple[int, int, Optional[GAS]]
    
+
    
+
+
    
+
    
+get_commbuf_info() → Tuple[int, int, Optional[chipsec.hal.acpi_tables.GAS]][source]
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class WSMT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+COMM_BUFFER_NESTED_PTR_PROTECTION = 2
    
+
    
+
+
    
+
    
+FIXED_COMM_BUFFERS = 1
    
+
    
+
+
    
+
    
+SYSTEM_RESOURCE_PROTECTION = 4
    
+
    
+
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class XSDT[source]
    
+
    Bases: chipsec.hal.acpi_tables.ACPI_TABLE
    
+
    
+
    
+parse(table_content: bytes) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +657,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    acpi module
    
+                          title="previous chapter">chipsec.hal.acpi module
    
   
    
   
    
     
    Next topic
    
     
    cmos module
    
+                          title="next chapter">chipsec.hal.cmos module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +688,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • acpi_tables module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.acpi_tables module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.cmos.html b/modules/chipsec.hal.cmos.html
index f52e24bd..83db0408 100644
--- a/modules/chipsec.hal.cmos.html
+++ b/modules/chipsec.hal.cmos.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cmos module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.cmos module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cmos module
    
+  
    
+
    chipsec.hal.cmos module
    
 
    CMOS memory specific functions (dump, read/write)
    
 
    
 
    usage:
    >>> cmos.dump_low()
@@ -61,7 +62,48 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class CMOS(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+dump() → None[source]
    
+
    
+
+
    
+
    
+dump_high() → List[int][source]
    
+
    
+
+
    
+
    
+dump_low() → List[int][source]
    
+
    
+
+
    
+
    
+read_cmos_high(offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_cmos_low(offset: int) → int[source]
    
+
    
+
+
    
+
    
+write_cmos_high(offset: int, value: int) → None[source]
    
+
    
+
+
    
+
    
+write_cmos_low(offset: int, value: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -115,12 +157,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    acpi_tables module
    
+                          title="previous chapter">chipsec.hal.acpi_tables module
    
   
    
   
    
     
    Next topic
    
     
    cpu module
    
+                          title="next chapter">chipsec.hal.cpu module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -146,20 +188,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • cmos module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.cmos module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.cpu.html b/modules/chipsec.hal.cpu.html
index 9b5b67fa..228005e5 100644
--- a/modules/chipsec.hal.cpu.html
+++ b/modules/chipsec.hal.cpu.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cpu module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.cpu module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,106 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cpu module
    
+  
    
+
    chipsec.hal.cpu module
    
 
    CPU related functionality
    
-
    
+
    
+
    
+class CPU(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+check_SMRR_supported() → bool[source]
    
+
    
+
+
    
+
    
+check_vmm() → int[source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+dump_page_tables(cr3: int, pt_fname: Optional[str] = None) → None[source]
    
+
    
+
+
    
+
    
+dump_page_tables_all() → None[source]
    
+
    
+
+
    
+
    
+get_SMRAM() → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_SMRR() → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+get_SMRR_SMRAM() → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_TSEG() → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_cpu_topology() → Dict[str, Dict[int, List[int]]][source]
    
+
    
+
+
    
+
    
+get_number_logical_processor_per_core() → int[source]
    
+
    
+
+
    
+
    
+get_number_logical_processor_per_package() → int[source]
    
+
    
+
+
    
+
    
+get_number_physical_processor_per_package() → int[source]
    
+
    
+
+
    
+
    
+get_number_sockets_from_APIC_table() → int[source]
    
+
    
+
+
    
+
    
+get_number_threads_from_APIC_table() → int[source]
    
+
    
+
+
    
+
    
+is_HT_active() → bool[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +200,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cmos module
    
+                          title="previous chapter">chipsec.hal.cmos module
    
   
    
   
    
     
    Next topic
    
     
    cpuid module
    
+                          title="next chapter">chipsec.hal.cpuid module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +231,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • cpu module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.cpu module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.cpuid.html b/modules/chipsec.hal.cpuid.html
index 1881362b..42452c5a 100644
--- a/modules/chipsec.hal.cpuid.html
+++ b/modules/chipsec.hal.cpuid.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cpuid module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.cpuid module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cpuid module
    
+  
    
+
    chipsec.hal.cpuid module
    
 
    CPUID information
    
 
    
 
    usage:
    >>> cpuid(0)
@@ -55,7 +56,23 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class CpuID(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+get_proc_info()[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -109,12 +126,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cpu module
    
+                          title="previous chapter">chipsec.hal.cpu module
    
   
    
   
    
     
    Next topic
    
     
    ec module
    
+                          title="next chapter">chipsec.hal.ec module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +157,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • cpuid module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.cpuid module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.ec.html b/modules/chipsec.hal.ec.html
index f5abbc2b..614c0af5 100644
--- a/modules/chipsec.hal.ec.html
+++ b/modules/chipsec.hal.ec.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    ec module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.ec module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    ec module
    
+  
    
+
    chipsec.hal.ec module
    
 
    Access to Embedded Controller (EC)
    
 
    Usage:
    
 
    >>> write_command( command )
@@ -61,7 +62,68 @@ 
    Navigation
    
 >>> write_range( start_offset, buffer )
 
    
 
    
-
    
+
    
+
    
+class EC(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+read_data() → Optional[int][source]
    
+
    
+
+
    
+
    
+read_idx(offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_memory(offset: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+read_memory_extended(word_offset: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+read_range(start_offset: int, size: int) → bytes[source]
    
+
    
+
+
    
+
    
+write_command(command: int) → None[source]
    
+
    
+
+
    
+
    
+write_data(data: int) → None[source]
    
+
    
+
+
    
+
    
+write_idx(offset: int, value: int) → bool[source]
    
+
    
+
+
    
+
    
+write_memory(offset: int, data: int) → None[source]
    
+
    
+
+
    
+
    
+write_memory_extended(word_offset: int, data: int) → None[source]
    
+
    
+
+
    
+
    
+write_range(start_offset: int, buffer: bytes) → bool[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -115,12 +177,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cpuid module
    
+                          title="previous chapter">chipsec.hal.cpuid module
    
   
    
   
    
     
    Next topic
    
     
    hal_base module
    
+                          title="next chapter">chipsec.hal.hal_base module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -146,20 +208,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • ec module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.ec module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.hal_base.html b/modules/chipsec.hal.hal_base.html
index 0ee6e404..b5d1df56 100644
--- a/modules/chipsec.hal.hal_base.html
+++ b/modules/chipsec.hal.hal_base.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    hal_base module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.hal_base module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,16 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    hal_base module
    
+  
    
+
    chipsec.hal.hal_base module
    
 
    Base for HAL Components
    
-
    
+
    
+
    
+class HALBase(cs)[source]
    
+
    Bases: object
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +110,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    ec module
    
+                          title="previous chapter">chipsec.hal.ec module
    
   
    
   
    
     
    Next topic
    
     
    igd module
    
+                          title="next chapter">chipsec.hal.igd module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +141,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • hal_base module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.hal_base module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.html b/modules/chipsec.hal.html
index fbeeda8b..ae3caec7 100644
--- a/modules/chipsec.hal.html
+++ b/modules/chipsec.hal.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    hal package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -45,52 +46,58 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    hal package
    
+  
    
+
    chipsec.hal package
    
+
    
+
    Submodules
    
 
    
 
 
    
-
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -144,12 +151,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    vmm_cmd module
    
+                          title="previous chapter">chipsec.utilcmd.vmm_cmd module
    
   
    
   
    
     
    Next topic
    
     
    acpi module
    
+                          title="next chapter">chipsec.hal.acpi module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -175,19 +182,19 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-        
  • hal package
    •  
+        
  • chipsec.hal package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.igd.html b/modules/chipsec.hal.igd.html
index 40999001..fe1ac906 100644
--- a/modules/chipsec.hal.igd.html
+++ b/modules/chipsec.hal.igd.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    igd module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.igd module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    igd module
    
+  
    
+
    chipsec.hal.igd module
    
 
    Working with Intel processor Integrated Graphics Device (IGD)
    
 
    
 
    usage:
    >>> gfx_aperture_dma_read(0x80000000, 0x100)
@@ -55,7 +56,103 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class IGD(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+dump_GGTT_PTEs(num: int) → None[source]
    
+
    
+
+
    
+
    
+get_GGTT_PTE_from_PA(pa: int) → int[source]
    
+
    
+
+
    
+
    
+get_GGTT_PTE_from_PA_gen8(pa: int) → int[source]
    
+
    
+
+
    
+
    
+get_GGTT_PTE_from_PA_legacy(pa: int) → int[source]
    
+
    
+
+
    
+
    
+get_GGTT_base() → int[source]
    
+
    
+
+
    
+
    
+get_GMADR() → int[source]
    
+
    
+
+
    
+
    
+get_GTTMMADR() → int[source]
    
+
    
+
+
    
+
    
+get_PA_from_PTE(pte: int) → int[source]
    
+
    
+
+
    
+
    
+get_PA_from_PTE_gen8(pte: int) → int[source]
    
+
    
+
+
    
+
    
+get_PA_from_PTE_legacy(pte: int) → int[source]
    
+
    
+
+
    
+
    
+get_PTE_size() → int[source]
    
+
    
+
+
    
+
    
+gfx_aperture_dma_read_write(address: int, size: int = 4, value: Optional[bytes] = None, pte_num: int = 0) → bytes[source]
    
+
    
+
+
    
+
    
+is_device_enabled() → bool[source]
    
+
    
+
+
    
+
    
+is_enabled() → bool[source]
    
+
    
+
+
    
+
    
+is_legacy_gen() → bool[source]
    
+
    
+
+
    
+
    
+read_GGTT_PTE(pte_num: int) → int[source]
    
+
    
+
+
    
+
    
+write_GGTT_PTE(pte_num: int, pte: int) → int[source]
    
+
    
+
+
    
+
    
+write_GGTT_PTE_from_PA(pte_num: int, pa: int) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -109,12 +206,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    hal_base module
    
+                          title="previous chapter">chipsec.hal.hal_base module
    
   
    
   
    
     
    Next topic
    
     
    interrupts module
    
+                          title="next chapter">chipsec.hal.interrupts module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +237,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • igd module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.igd module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.interrupts.html b/modules/chipsec.hal.interrupts.html
index f4ccf9e5..cbf23183 100644
--- a/modules/chipsec.hal.interrupts.html
+++ b/modules/chipsec.hal.interrupts.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    interrupts module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.interrupts module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    interrupts module
    
+  
    
+
    chipsec.hal.interrupts module
    
 
    Functionality encapsulating interrupt generation
 CPU Interrupts specific functions (SMI, NMI)
    
 
    
@@ -57,7 +58,48 @@ 
    Navigation
    
 
    
 
 
-
    
+
    
+
    
+class Interrupts(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+find_ACPI_SMI_Buffer() → Optional[Tuple[int, int, Optional[chipsec.hal.acpi_tables.GAS]]][source]
    
+
    
+
+
    
+
    
+find_smmc(start: int, end: int) → int[source]
    
+
    
+
+
    
+
    
+send_ACPI_SMI(thread_id: int, smi_num: int, buf_addr: int, invoc_reg: chipsec.hal.acpi_tables.GAS, guid: str, data: bytes) → Optional[int][source]
    
+
    
+
+
    
+
    
+send_NMI() → None[source]
    
+
    
+
+
    
+
    
+send_SMI_APMC(SMI_code_port_value: int, SMI_data_port_value: int) → None[source]
    
+
    
+
+
    
+
    
+send_SW_SMI(thread_id: int, SMI_code_port_value: int, SMI_data_port_value: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → Optional[Tuple[int, int, int, int, int, int, int]][source]
    
+
    
+
+
    
+
    
+send_smmc_SMI(smmc: int, guid: str, payload: bytes, payload_loc: int, CommandPort: int = 0, DataPort: int = 0) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -111,12 +153,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    igd module
    
+                          title="previous chapter">chipsec.hal.igd module
    
   
    
   
    
     
    Next topic
    
     
    io module
    
+                          title="next chapter">chipsec.hal.io module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -142,20 +184,20 @@ 
    Navigation
    
           modules |
         
  • 
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    • 
         
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-          previous |
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  • CHIPSEC  documentation »
    • 
           
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    • 
-          
  • hal package »
    • 
-        
  • interrupts module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.interrupts module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.io.html b/modules/chipsec.hal.io.html
index f69ac112..baf9699e 100644
--- a/modules/chipsec.hal.io.html
+++ b/modules/chipsec.hal.io.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    io module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.io module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    io module
    
+  
    
+
    chipsec.hal.io module
    
 
    Access to Port I/O
    
 
    
 
    usage:
    >>> read_port_byte( 0x61 )
@@ -60,7 +61,53 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class PortIO(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+dump_IO(range_base: int, range_size: int, size: int = 1) → None[source]
    
+
    
+
+
    
+
    
+read_IO(range_base: int, range_size: int, size: int = 1) → List[int][source]
    
+
    
+
+
    
+
    
+read_port_byte(io_port: int) → int[source]
    
+
    
+
+
    
+
    
+read_port_dword(io_port: int) → int[source]
    
+
    
+
+
    
+
    
+read_port_word(io_port: int) → int[source]
    
+
    
+
+
    
+
    
+write_port_byte(io_port: int, value: int) → None[source]
    
+
    
+
+
    
+
    
+write_port_dword(io_port: int, value: int) → None[source]
    
+
    
+
+
    
+
    
+write_port_word(io_port: int, value: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -114,12 +161,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    interrupts module
    
+                          title="previous chapter">chipsec.hal.interrupts module
    
   
    
   
    
     
    Next topic
    
     
    iobar module
    
+                          title="next chapter">chipsec.hal.iobar module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -145,20 +192,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • io module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.io module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.iobar.html b/modules/chipsec.hal.iobar.html
index a9521c0a..3162e933 100644
--- a/modules/chipsec.hal.iobar.html
+++ b/modules/chipsec.hal.iobar.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    iobar module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.iobar module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    iobar module
    
+  
    
+
    chipsec.hal.iobar module
    
 
    I/O BAR access (dump, read/write)
    
 
    
 
    usage:
    >>> get_IO_BAR_base_address( bar_name )
@@ -58,7 +59,53 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class IOBAR(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+dump_IO_BAR(bar_name: str, size: int = 1) → None[source]
    
+
    
+
+
    
+
    
+get_IO_BAR_base_address(bar_name: str) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+is_IO_BAR_defined(bar_name: str) → bool[source]
    
+
    
+
+
    
+
    
+is_IO_BAR_enabled(bar_name: str) → bool[source]
    
+
    
+
+
    
+
    
+list_IO_BARs() → None[source]
    
+
    
+
+
    
+
    
+read_IO_BAR(bar_name: str, size: int = 1) → List[int][source]
    
+
    
+
+
    
+
    
+read_IO_BAR_reg(bar_name: str, offset: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_IO_BAR_reg(bar_name: str, offset: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -112,12 +159,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    io module
    
+                          title="previous chapter">chipsec.hal.io module
    
   
    
   
    
     
    Next topic
    
     
    iommu module
    
+                          title="next chapter">chipsec.hal.iommu module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -143,20 +190,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • iobar module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.iobar module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.iommu.html b/modules/chipsec.hal.iommu.html
index 2149414a..ee8a6290 100644
--- a/modules/chipsec.hal.iommu.html
+++ b/modules/chipsec.hal.iommu.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    iommu module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.iommu module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,51 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    iommu module
    
+  
    
+
    chipsec.hal.iommu module
    
 
    Access to IOMMU engines
    
-
    
+
    
+
    
+class IOMMU(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+dump_IOMMU_configuration(iommu_engine: str) → None[source]
    
+
    
+
+
    
+
    
+dump_IOMMU_page_tables(iommu_engine: str) → None[source]
    
+
    
+
+
    
+
    
+dump_IOMMU_status(iommu_engine: str) → None[source]
    
+
    
+
+
    
+
    
+get_IOMMU_Base_Address(iommu_engine: str) → int[source]
    
+
    
+
+
    
+
    
+is_IOMMU_Engine_Enabled(iommu_engine: str) → bool[source]
    
+
    
+
+
    
+
    
+is_IOMMU_Translation_Enabled(iommu_engine: str) → bool[source]
    
+
    
+
+
    
+
    
+set_IOMMU_Translation(iommu_engine: str, te: int) → bool[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +145,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    iobar module
    
+                          title="previous chapter">chipsec.hal.iobar module
    
   
    
   
    
     
    Next topic
    
     
    locks module
    
+                          title="next chapter">chipsec.hal.locks module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +176,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • iommu module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.iommu module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.locks.html b/modules/chipsec.hal.locks.html
index 03149a19..6d6549b8 100644
--- a/modules/chipsec.hal.locks.html
+++ b/modules/chipsec.hal.locks.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    locks module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.locks module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,63 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    locks module
    
-
    
+  
    
+
    chipsec.hal.locks module
    
+
    
+
    
+class LockResult[source]
    
+
    Bases: object
    
+
    
+
    
+CAN_READ = 8
    
+
    
+
+
    
+
    
+DEFINED = 1
    
+
    
+
+
    
+
    
+HAS_CONFIG = 2
    
+
    
+
+
    
+
    
+INCONSISTENT = 16
    
+
    
+
+
    
+
    
+LOCKED = 4
    
+
    
+
+
    
+
+
    
+
    
+class locks(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+get_locks() → List[str][source]
    
+
    Return a list of locks defined within the configuration file
    
+
    
+
+
    
+
    
+is_locked(lock_name: str, bus: Optional[int] = None) → int[source]
    
+
    Return whether the lock has the value setting
    
+
    
+
+
    
+
    
+lock_valid(lock_name: str, bus: Optional[int] = None) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -102,12 +157,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    iommu module
    
+                          title="previous chapter">chipsec.hal.iommu module
    
   
    
   
    
     
    Next topic
    
     
    mmio module
    
+                          title="next chapter">chipsec.hal.mmio module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +188,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • locks module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.locks module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.mmio.html b/modules/chipsec.hal.mmio.html
index 8099896e..02a7a98b 100644
--- a/modules/chipsec.hal.mmio.html
+++ b/modules/chipsec.hal.mmio.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    mmio module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.mmio module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    mmio module
    
+  
    
+
    chipsec.hal.mmio module
    
 
    Access to MMIO (Memory Mapped IO) BARs and Memory-Mapped PCI Configuration Space (MMCFG)
    
 
    
 
    usage:
    >>> read_MMIO_reg(cs, bar_base, 0x0, 4)
@@ -74,7 +75,160 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class ECEntry(bus: int, dev: int, fun: int, off: int, value: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class MMIO(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+dump_MMIO(bar_base: int, size: int) → None[source]
    
+
    
+
+
    
+
    
+dump_MMIO_BAR(bar_name: str) → None[source]
    
+
    
+
+
    
+
    
+enable_cache_address_resolution(enable: bool) → None[source]
    
+
    
+
+
    
+
    
+flush_bar_address_cache() → None[source]
    
+
    
+
+
    
+
    
+get_MMCFG_base_address() → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+get_MMIO_BAR_base_address(bar_name: str, bus: Optional[int] = None) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+get_extended_capabilities(bus: int, dev: int, fun: int) → List[chipsec.hal.mmio.ECEntry][source]
    
+
    
+
+
    
+
    
+get_vsec(bus: int, dev: int, fun: int, ecoff: int) → chipsec.hal.mmio.VSECEntry[source]
    
+
    
+
+
    
+
    
+is_MMIO_BAR_defined(bar_name: str) → bool[source]
    
+
    
+
+
    
+
    
+is_MMIO_BAR_enabled(bar_name: str, bus: Optional[int] = None) → bool[source]
    
+
    
+
+
    
+
    
+is_MMIO_BAR_programmed(bar_name: str) → bool[source]
    
+
    
+
+
    
+
    
+list_MMIO_BARs() → None[source]
    
+
    
+
+
    
+
    
+read_MMIO(bar_base: int, size: int) → List[int][source]
    
+
    
+
+
    
+
    
+read_MMIO_BAR(bar_name: str, bus: Optional[int] = None) → List[int][source]
    
+
    
+
+
    
+
    
+read_MMIO_BAR_reg(bar_name: str, offset: int, size: int = 4, bus: Optional[int] = None) → int[source]
    
+
    
+
+
    
+
    
+read_MMIO_reg(bar_base: int, offset: int, size: int = 4, bar_size: Optional[int] = None) → int[source]
    
+
    
+
+
    
+
    
+read_MMIO_reg_byte(bar_base: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_MMIO_reg_dword(bar_base: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_MMIO_reg_word(bar_base: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmcfg_reg(bus: int, dev: int, fun: int, off: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_MMIO_BAR_reg(bar_name: str, offset: int, value: int, size: int = 4, bus: Optional[int] = None) → Optional[int][source]
    
+
    
+
+
    
+
    
+write_MMIO_reg(bar_base: int, offset: int, value: int, size: int = 4) → int[source]
    
+
    
+
+
    
+
    
+write_MMIO_reg_byte(bar_base: int, offset: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_MMIO_reg_dword(bar_base: int, offset: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_MMIO_reg_word(bar_base: int, offset: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_mmcfg_reg(bus: int, dev: int, fun: int, off: int, size: int, value: int) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+class VSECEntry(value: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+print_pci_extended_capability(ecentries: List[chipsec.hal.mmio.ECEntry]) → None[source]
    
+
    
+
+
    
 
 
             
    
@@ -128,12 +282,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    locks module
    
+                          title="previous chapter">chipsec.hal.locks module
    
   
    
   
    
     
    Next topic
    
     
    msgbus module
    
+                          title="next chapter">chipsec.hal.msgbus module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -159,20 +313,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • mmio module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.mmio module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.msgbus.html b/modules/chipsec.hal.msgbus.html
index fb11d799..e6d91549 100644
--- a/modules/chipsec.hal.msgbus.html
+++ b/modules/chipsec.hal.msgbus.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    msgbus module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.msgbus module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    msgbus module
    
+  
    
+
    chipsec.hal.msgbus module
    
 
    Access to message bus (IOSF sideband) interface registers on Intel SoCs
    
 
    References:
    
 
      
@@ -64,7 +65,201 @@ 
      Navigation
      
 
    
 
 
-
    
+
    
+
    
+class MessageBusOpcode[source]
    
+
    Bases: object
    
+
    
+
    
+MB_OPCODE_CFG_READ = 4
    
+
    
+
+
    
+
    
+MB_OPCODE_CFG_WRITE = 5
    
+
    
+
+
    
+
    
+MB_OPCODE_CR_READ = 6
    
+
    
+
+
    
+
    
+MB_OPCODE_CR_WRITE = 7
    
+
    
+
+
    
+
    
+MB_OPCODE_ESRAM_READ = 18
    
+
    
+
+
    
+
    
+MB_OPCODE_ESRAM_WRITE = 19
    
+
    
+
+
    
+
    
+MB_OPCODE_IO_READ = 2
    
+
    
+
+
    
+
    
+MB_OPCODE_IO_WRITE = 3
    
+
    
+
+
    
+
    
+MB_OPCODE_MMIO_READ = 0
    
+
    
+
+
    
+
    
+MB_OPCODE_MMIO_WRITE = 1
    
+
    
+
+
    
+
    
+MB_OPCODE_REG_READ = 16
    
+
    
+
+
    
+
    
+MB_OPCODE_REG_WRITE = 17
    
+
    
+
+
    
+
+
    
+
    
+class MessageBusPort_Atom[source]
    
+
    Bases: object
    
+
    
+
    
+UNIT_AUNIT = 0
    
+
    
+
+
    
+
    
+UNIT_BUNIT = 3
    
+
    
+
+
    
+
    
+UNIT_CPU = 2
    
+
    
+
+
    
+
    
+UNIT_GFX = 6
    
+
    
+
+
    
+
    
+UNIT_PCIE = 166
    
+
    
+
+
    
+
    
+UNIT_PMC = 4
    
+
    
+
+
    
+
    
+UNIT_SATA = 163
    
+
    
+
+
    
+
    
+UNIT_SMC = 1
    
+
    
+
+
    
+
    
+UNIT_SMI = 12
    
+
    
+
+
    
+
    
+UNIT_USB = 67
    
+
    
+
+
    
+
+
    
+
    
+class MessageBusPort_Quark[source]
    
+
    Bases: object
    
+
    
+
    
+UNIT_HB = 3
    
+
    
+
+
    
+
    
+UNIT_HBA = 0
    
+
    
+
+
    
+
    
+UNIT_MM = 5
    
+
    
+
+
    
+
    
+UNIT_RMU = 4
    
+
    
+
+
    
+
    
+UNIT_SOC = 49
    
+
    
+
+
    
+
+
    
+
    
+class MsgBus(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+mm_msgbus_reg_read(port: int, register: int) → int[source]
    
+
    
+
+
    
+
    
+mm_msgbus_reg_write(port: int, register: int, data: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_read_message(port: int, register: int, opcode: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_reg_read(port: int, register: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_reg_write(port: int, register: int, data: int) → None[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(port: int, register: int, opcode: int, data: Optional[int] = None) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_write_message(port: int, register: int, opcode: int, data: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -118,12 +313,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    mmio module
    
+                          title="previous chapter">chipsec.hal.mmio module
    
   
    
   
    
     
    Next topic
    
     
    msr module
    
+                          title="next chapter">chipsec.hal.msr module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -149,20 +344,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • msgbus module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.msgbus module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.msr.html b/modules/chipsec.hal.msr.html
index 2191af01..059f168c 100644
--- a/modules/chipsec.hal.msr.html
+++ b/modules/chipsec.hal.msr.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    msr module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.msr module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    msr module
    
+  
    
+
    chipsec.hal.msr module
    
 
    Access to CPU resources (for each CPU thread): Model Specific Registers (MSR), IDT/GDT
    
 
    
 
    usage:
    >>> read_msr( 0x8B )
@@ -63,7 +64,78 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class Msr(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+GDT(cpu_thread_id: int, num_entries: Optional[int] = None) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+GDT_all(num_entries: Optional[int] = None) → None[source]
    
+
    
+
+
    
+
    
+IDT(cpu_thread_id: int, num_entries: Optional[int] = None) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+IDT_all(num_entries: Optional[int] = None) → None[source]
    
+
    
+
+
    
+
    
+dump_Descriptor_Table(cpu_thread_id: int, code: int, num_entries: Optional[int] = None) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+get_Desc_Table_Register(cpu_thread_id: int, code: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_GDTR(cpu_thread_id: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_IDTR(cpu_thread_id: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_LDTR(cpu_thread_id: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_cpu_core_count() → int[source]
    
+
    
+
+
    
+
    
+get_cpu_thread_count() → int[source]
    
+
    
+
+
    
+
    
+read_msr(cpu_thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+write_msr(cpu_thread_id: int, msr_addr: int, eax: int, edx: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -117,12 +189,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    msgbus module
    
+                          title="previous chapter">chipsec.hal.msgbus module
    
   
    
   
    
     
    Next topic
    
     
    paging module
    
+                          title="next chapter">chipsec.hal.paging module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -148,20 +220,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • msr module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.msr module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.paging.html b/modules/chipsec.hal.paging.html
index 2ef87ff4..4db41f76 100644
--- a/modules/chipsec.hal.paging.html
+++ b/modules/chipsec.hal.paging.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    paging module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.paging module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,315 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    paging module
    
+  
    
+
    chipsec.hal.paging module
    
 
    x64/IA-64 Paging functionality including x86 page tables, Extended Page Tables (EPT) and VT-d page tables
    
-
    
+
    
+
    
+class c_4level_page_tables(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_paging
    
+
    
+
    
+get_attr(entry: int) → str[source]
    
+
    
+
+
    
+
    
+get_virt_addr(pml4e_index: int, pdpte_index: int = 0, pde_index: int = 0, pte_index: int = 0) → int[source]
    
+
    
+
+
    
+
    
+is_bigpage(entry: int) → int[source]
    
+
    
+
+
    
+
    
+is_present(entry: int) → int[source]
    
+
    
+
+
    
+
    
+print_entry(lvl: int, pa: int, va: int = 0, perm: str = '') → None[source]
    
+
    
+
+
    
+
    
+read_entry_by_virt_addr(virt: int) → Dict[str, Any][source]
    
+
    
+
+
    
+
    
+read_page_tables(ptr: int) → None[source]
    
+
    
+
+
    
+
    
+read_pd(addr: int, pml4e_index: int, pdpte_index: int) → None[source]
    
+
    
+
+
    
+
    
+read_pdpt(addr: int, pml4e_index: int) → None[source]
    
+
    
+
+
    
+
    
+read_pml4(addr: int) → None[source]
    
+
    
+
+
    
+
    
+read_pt(addr: int, pml4e_index: int, pdpte_index: int, pde_index: int) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_extended_page_tables(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_4level_page_tables
    
+
    
+
    
+get_attr(entry: int) → str[source]
    
+
    
+
+
    
+
    
+is_bigpage(entry: int) → bool[source]
    
+
    
+
+
    
+
    
+is_present(entry: int) → bool[source]
    
+
    
+
+
    
+
    
+map_bigpage_1G(virt: int, i: int) → None[source]
    
+
    
+
+
    
+
    
+read_pt_and_show_status(path: str, name: str, ptr: int) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_ia32e_page_tables(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_4level_page_tables
    
+
    
+
    
+get_attr(entry: int) → str[source]
    
+
    
+
+
    
+
    
+is_bigpage(entry: int) → bool[source]
    
+
    
+
+
    
+
    
+is_present(entry: int) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_pae_page_tables(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_ia32e_page_tables
    
+
    
+
    
+read_page_tables(ptr: int) → None[source]
    
+
    
+
+
    
+
    
+read_pdpt(addr: int, pml4e_index: Optional[int] = None) → None[source]
    
+
    
+
+
    
+
    
+read_pml4(addr: int)[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_paging(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_paging_with_2nd_level_translation, chipsec.hal.paging.c_translation
    
+
    
+
    
+check_misconfig(addr_list: List[int]) → None[source]
    
+
    
+
+
    
+
    
+get_canonical(va: int) → int[source]
    
+
    
+
+
    
+
    
+get_field(entry: int, desc: Dict[str, int]) → int[source]
    
+
    
+
+
    
+
    
+load_configuration(path: str) → None[source]
    
+
    
+
+
    
+
    
+print_info(name: str) → None[source]
    
+
    
+
+
    
+
    
+read_entries(info: str, addr: int, size: int = 8) → List[Any][source]
    
+
    
+
+
    
+
    
+read_page_tables(entry: int)[source]
    
+
    
+
+
    
+
    
+read_pt_and_show_status(path: str, name: str, ptr: int) → None[source]
    
+
    
+
+
    
+
    
+save_configuration(path: str) → None[source]
    
+
    
+
+
    
+
    
+set_field(value: int, desc: Dict[str, int]) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_paging_memory_access(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+readmem(name: str, addr: int, size: int = 4096) → bytes[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_paging_with_2nd_level_translation(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_paging_memory_access
    
+
    
+
    
+readmem(name: str, addr: int, size: int = 4096) → bytes[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_reverse_translation(translation: Dict[int, Dict[str, Any]])[source]
    
+
    Bases: object
    
+
    
+
    
+get_reverse_translation(addr: int) → List[Dict[str, Any]][source]
    
+
    
+
+
    
+
+
    
+
    
+class c_translation[source]
    
+
    Bases: object
    
+
    
+
    
+add_page(virt: int, phys: int, size: str, attr: str) → None[source]
    
+
    
+
+
    
+
    
+del_page(addr: int) → None[source]
    
+
    
+
+
    
+
    
+expand_pages(exp_size: str) → None[source]
    
+
    
+
+
    
+
    
+get_address_space() → int[source]
    
+
    
+
+
    
+
    
+get_mem_range(noattr: bool = False) → List[List[int]][source]
    
+
    
+
+
    
+
    
+get_pages_by_physaddr(addr: int) → List[Dict[str, int]][source]
    
+
    
+
+
    
+
    
+get_translation(addr: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+is_translation_exist(addr: int, mask: int, size: str) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+class c_vtd_page_tables(cs)[source]
    
+
    Bases: chipsec.hal.paging.c_extended_page_tables
    
+
    
+
    
+print_context_entry(source_id: int, cee: Dict[int, int]) → None[source]
    
+
    
+
+
    
+
    
+read_ce(addr: int, ree_index: int) → None[source]
    
+
    
+
+
    
+
    
+read_page_tables(ptr: int) → None[source]
    
+
    
+
+
    
+
    
+read_pt_and_show_status(path: str, name: str, ptr: int) → None[source]
    
+
    
+
+
    
+
    
+read_re(addr: int) → None[source]
    
+
    
+
+
    
+
    
+read_vtd_context(path: str, ptr: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +409,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    msr module
    
+                          title="previous chapter">chipsec.hal.msr module
    
   
    
   
    
     
    Next topic
    
     
    pci module
    
+                          title="next chapter">chipsec.hal.pci module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +440,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • paging module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.paging module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.pci.html b/modules/chipsec.hal.pci.html
index f80588e9..473af796 100644
--- a/modules/chipsec.hal.pci.html
+++ b/modules/chipsec.hal.pci.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    pci module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.pci module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    pci module
    
+  
    
+
    chipsec.hal.pci module
    
 
    Access to of PCI/PCIe device hierarchy
 - enumerating PCI/PCIe devices
 - read/write access to PCI configuration headers/registers
@@ -66,7 +67,142 @@ 
    Navigation
    
 
    
 
 
-
    
+
    
+
    
+class EFI_XROM_HEADER(Signature, InitSize, EfiSignature, EfiSubsystem, EfiMachineType, CompressType, Reserved, EfiImageHeaderOffset, PCIROffset)[source]
    
+
    Bases: chipsec.hal.pci.EFI_XROM_HEADER
    
+
    
+
+
    
+
    
+class PCI_XROM_HEADER(Signature, ArchSpecific, PCIROffset)[source]
    
+
    Bases: chipsec.hal.pci.PCI_XROM_HEADER
    
+
    
+
+
    
+
    
+class Pci(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+calc_bar_size(bus: int, dev: int, fun: int, off: int, is64: bool, isMMIO: bool) → int[source]
    
+
    
+
+
    
+
    
+dump_pci_config(bus: int, device: int, function: int) → List[int][source]
    
+
    
+
+
    
+
    
+enumerate_devices(bus: Optional[int] = None, device: Optional[int] = None, function: Optional[int] = None, spec: Optional[bool] = True) → List[Tuple[int, int, int, int, int, int]][source]
    
+
    
+
+
    
+
    
+enumerate_xroms(try_init: bool = False, xrom_dump: bool = False, xrom_addr: Optional[int] = None) → List[Optional[chipsec.hal.pci.XROM]][source]
    
+
    
+
+
    
+
    
+find_XROM(bus: int, dev: int, fun: int, try_init: bool = False, xrom_dump: bool = False, xrom_addr: Optional[int] = None) → Tuple[bool, Optional[chipsec.hal.pci.XROM]][source]
    
+
    
+
+
    
+
    
+get_DIDVID(bus: int, dev: int, fun: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+get_device_bars(bus: int, dev: int, fun: int, bCalcSize: bool = False) → List[Tuple[int, bool, bool, int, int, int]][source]
    
+
    
+
+
    
+
    
+get_header_type(bus, dev, fun)[source]
    
+
    
+
+
    
+
    
+is_enabled(bus: int, dev: int, fun: int) → bool[source]
    
+
    
+
+
    
+
    
+parse_XROM(xrom: chipsec.hal.pci.XROM, xrom_dump: bool = False) → Optional[chipsec.hal.pci.PCI_XROM_HEADER][source]
    
+
    
+
+
    
+
    
+print_pci_config_all() → None[source]
    
+
    
+
+
    
+
    
+read_byte(bus: int, device: int, function: int, address: int) → int[source]
    
+
    
+
+
    
+
    
+read_dword(bus: int, device: int, function: int, address: int) → int[source]
    
+
    
+
+
    
+
    
+read_word(bus: int, device: int, function: int, address: int) → int[source]
    
+
    
+
+
    
+
    
+write_byte(bus: int, device: int, function: int, address: int, byte_value: int) → None[source]
    
+
    
+
+
    
+
    
+write_dword(bus: int, device: int, function: int, address: int, dword_value: int) → None[source]
    
+
    
+
+
    
+
    
+write_word(bus: int, device: int, function: int, address: int, word_value: int) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class XROM(bus, dev, fun, en, base, size)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class XROM_HEADER(Signature, InitSize, InitEP, Reserved, PCIROffset)[source]
    
+
    Bases: chipsec.hal.pci.XROM_HEADER
    
+
    
+
+
    
+
    
+get_device_name_by_didvid(vid: int, did: int) → str[source]
    
+
    
+
+
    
+
    
+get_vendor_name_by_vid(vid: int) → str[source]
    
+
    
+
+
    
+
    
+print_pci_XROMs(_xroms: List[chipsec.hal.pci.XROM]) → None[source]
    
+
    
+
+
    
+
    
+print_pci_devices(_devices: List[Tuple[int, int, int, int, int]]) → None[source]
    
+
    
+
+
    
 
 
             
    
@@ -120,12 +256,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    paging module
    
+                          title="previous chapter">chipsec.hal.paging module
    
   
    
   
    
     
    Next topic
    
     
    pcidb module
    
+                          title="next chapter">chipsec.hal.pcidb module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -151,20 +287,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • pci module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.pci module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.pcidb.html b/modules/chipsec.hal.pcidb.html
index d22c88a3..3d3b0bce 100644
--- a/modules/chipsec.hal.pcidb.html
+++ b/modules/chipsec.hal.pcidb.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    pcidb module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.pcidb module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    pcidb module
    
+  
    
+
    chipsec.hal.pcidb module
    
 
    PCI Vendor & Device ID data.
    
 
    
 
    Note
    
@@ -55,7 +56,7 @@ 
    Navigation
    
 
    Auto generated from:
    
 
    https://github.com/pciutils/pciids
    
 
    
-
    
+
    
 
 
             
    
@@ -109,12 +110,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    pci module
    
+                          title="previous chapter">chipsec.hal.pci module
    
   
    
   
    
     
    Next topic
    
     
    physmem module
    
+                          title="next chapter">chipsec.hal.physmem module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +141,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • pcidb module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.pcidb module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.physmem.html b/modules/chipsec.hal.physmem.html
index 07b0afab..2c2cc857 100644
--- a/modules/chipsec.hal.physmem.html
+++ b/modules/chipsec.hal.physmem.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    physmem module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.physmem module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    physmem module
    
+  
    
+
    chipsec.hal.physmem module
    
 
    Access to physical memory
    
 
    
 
    usage:
    >>> read_physical_mem( 0xf0000, 0x100 )
@@ -58,7 +59,83 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class Memory(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+alloc_physical_mem(length: int, max_phys_address: int = 18446744073709551615) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+free_physical_mem(pa: int) → bool[source]
    
+
    
+
+
    
+
    
+map_io_space(pa: int, length: int, cache_type: int) → int[source]
    
+
    
+
+
    
+
    
+read_physical_mem(phys_address: int, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+read_physical_mem_byte(phys_address: int) → int[source]
    
+
    
+
+
    
+
    
+read_physical_mem_dword(phys_address: int) → int[source]
    
+
    
+
+
    
+
    
+read_physical_mem_qword(phys_address: int) → int[source]
    
+
    
+
+
    
+
    
+read_physical_mem_word(phys_address: int) → int[source]
    
+
    
+
+
    
+
    
+set_mem_bit(addr: int, bit: int) → int[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+write_physical_mem(phys_address: int, length: int, buf: bytes) → int[source]
    
+
    
+
+
    
+
    
+write_physical_mem_byte(phys_address: int, byte_value: int) → int[source]
    
+
    
+
+
    
+
    
+write_physical_mem_dword(phys_address: int, dword_value: int) → int[source]
    
+
    
+
+
    
+
    
+write_physical_mem_word(phys_address: int, word_value: int) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -112,12 +189,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    pcidb module
    
+                          title="previous chapter">chipsec.hal.pcidb module
    
   
    
   
    
     
    Next topic
    
     
    smbios module
    
+                          title="next chapter">chipsec.hal.smbios module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -143,20 +220,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • physmem module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.physmem module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.smbios.html b/modules/chipsec.hal.smbios.html
index aecd750c..040efb89 100644
--- a/modules/chipsec.hal.smbios.html
+++ b/modules/chipsec.hal.smbios.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smbios module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.smbios module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,75 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smbios module
    
+  
    
+
    chipsec.hal.smbios module
    
 
    HAL component providing access to and decoding of SMBIOS structures
    
-
    
+
    
+
    
+class SMBIOS(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+find_smbios_table() → bool[source]
    
+
    
+
+
    
+
    
+get_decoded_structs(struct_type: Optional[int] = None, force_32bit: bool = False) → Optional[List[Type[Union[chipsec.hal.smbios.SMBIOS_BIOS_INFO_2_0, chipsec.hal.smbios.SMBIOS_SYSTEM_INFO_2_0]]]][source]
    
+
    
+
+
    
+
    
+get_header(raw_data: bytes) → Optional[chipsec.hal.smbios.SMBIOS_STRUCT_HEADER][source]
    
+
    
+
+
    
+
    
+get_raw_structs(struct_type: Optional[int], force_32bit: bool)[source]
    
+
    Returns a list of raw data blobs for each SMBIOS structure.  The default is to process the 64bit
+entries if available unless specifically specified.
    
+
    Error:
+None
    
+
    
+
+
    
+
    
+get_string_list(raw_data: bytes) → Optional[List[str]][source]
    
+
    
+
+
    
+
+
    
+
    
+class SMBIOS_2_x_ENTRY_POINT(Anchor, EntryCs, EntryLen, MajorVer, MinorVer, MaxSize, EntryRev, FormatArea0, FormatArea1, FormatArea2, FormatArea3, FormatArea4, IntAnchor, IntCs, TableLen, TableAddr, NumStructures, BcdRev)[source]
    
+
    Bases: chipsec.hal.smbios.SMBIOS_2_x_ENTRY_POINT
    
+
    
+
+
    
+
    
+class SMBIOS_3_x_ENTRY_POINT(Anchor, EntryCs, EntryLen, MajorVer, MinorVer, Docrev, EntryRev, Reserved, MaxSize, TableAddr)[source]
    
+
    Bases: chipsec.hal.smbios.SMBIOS_3_x_ENTRY_POINT
    
+
    
+
+
    
+
    
+class SMBIOS_BIOS_INFO_2_0(type, length, handle, vendor_str, version_str, segment, release_str, rom_sz, bios_char, strings)[source]
    
+
    Bases: chipsec.hal.smbios.SMBIOS_BIOS_INFO_2_0_ENTRY
    
+
    
+
+
    
+
    
+class SMBIOS_STRUCT_HEADER(Type, Length, Handle)[source]
    
+
    Bases: chipsec.hal.smbios.SMBIOS_STRUCT_HEADER
    
+
    
+
+
    
+
    
+class SMBIOS_SYSTEM_INFO_2_0(type, length, handle, manufacturer_str, product_str, version_str, serial_str, strings)[source]
    
+
    Bases: chipsec.hal.smbios.SMBIOS_SYSTEM_INFO_2_0_ENTRY
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +169,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    physmem module
    
+                          title="previous chapter">chipsec.hal.physmem module
    
   
    
   
    
     
    Next topic
    
     
    smbus module
    
+                          title="next chapter">chipsec.hal.smbus module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +200,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • smbios module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.smbios module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.smbus.html b/modules/chipsec.hal.smbus.html
index d1bdbf0e..0c60b097 100644
--- a/modules/chipsec.hal.smbus.html
+++ b/modules/chipsec.hal.smbus.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smbus module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.smbus module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,76 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smbus module
    
+  
    
+
    chipsec.hal.smbus module
    
 
    Access to SMBus Controller
    
-
    
+
    
+
    
+class SMBus(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+display_SMBus_info() → None[source]
    
+
    
+
+
    
+
    
+enable_SMBus_host_controller() → None[source]
    
+
    
+
+
    
+
    
+get_SMBus_Base_Address() → int[source]
    
+
    
+
+
    
+
    
+get_SMBus_HCFG() → int[source]
    
+
    
+
+
    
+
    
+is_SMBus_enabled() → bool[source]
    
+
    
+
+
    
+
    
+is_SMBus_host_controller_enabled() → int[source]
    
+
    
+
+
    
+
    
+is_SMBus_supported() → bool[source]
    
+
    
+
+
    
+
    
+read_byte(target_address: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_range(target_address: int, start_offset: int, size: int) → bytes[source]
    
+
    
+
+
    
+
    
+reset_SMBus_controller() → bool[source]
    
+
    
+
+
    
+
    
+write_byte(target_address: int, offset: int, value: int) → bool[source]
    
+
    
+
+
    
+
    
+write_range(target_address: int, start_offset: int, buffer: bytes) → bool[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +170,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smbios module
    
+                          title="previous chapter">chipsec.hal.smbios module
    
   
    
   
    
     
    Next topic
    
     
    spd module
    
+                          title="next chapter">chipsec.hal.spd module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +201,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • smbus module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.smbus module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.spd.html b/modules/chipsec.hal.spd.html
index dcc18a43..e37a8fd7 100644
--- a/modules/chipsec.hal.spd.html
+++ b/modules/chipsec.hal.spd.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spd module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.spd module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spd module
    
+  
    
+
    
+
    
+class SPD(smbus)[source]
    
+
    Bases: object
    
+
    
+
    
+decode(device: int = 160) → None[source]
    
+
    
+
+
    
+
    
+detect() → List[int][source]
    
+
    
+
+
    
+
    
+dump_spd_rom(device: int = 160) → bytes[source]
    
+
    
+
+
    
+
    
+getDRAMDeviceType(device: int = 160) → int[source]
    
+
    
+
+
    
+
    
+getModuleType(device: int = 160) → int[source]
    
+
    
+
+
    
+
    
+isECC(device: int = 160) → bool[source]
    
+
    
+
+
    
+
    
+isSPDPresent(device: int = 160) → bool[source]
    
+
    
+
+
    
+
    
+read_byte(offset: int, device: int = 160) → int[source]
    
+
    
+
+
    
+
    
+read_range(start_offset: int, size: int, device: int = 160) → bytes[source]
    
+
    
+
+
    
+
    
+write_byte(offset: int, value: int, device: int = 160) → bool[source]
    
+
    
+
+
    
+
    
+write_range(start_offset: int, buffer: bytes, device: int = 160) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+class SPD_DDR(SPDBytes, TotalBytes, DeviceType, RowAddressCount)[source]
    
+
    Bases: chipsec.hal.spd.SPD_DDR
    
+
    
+
+
    
+
    
+class SPD_DDR2(SPDBytes, TotalBytes, DeviceType, RowAddressCount)[source]
    
+
    Bases: chipsec.hal.spd.SPD_DDR2
    
+
    
+
+
    
+
    
+class SPD_DDR3(SPDBytes, Revision, DeviceType, ModuleType, ChipSize, Addressing, Voltages, ModuleOrg, BusWidthECC, FTB, MTBDivident, MTBDivisor, tCKMin, RsvdD, CASLo, CASHi)[source]
    
+
    Bases: chipsec.hal.spd.SPD_DDR3
    
+
    
+
+
    
+
    
+class SPD_DDR4(SPDBytes, Revision, DeviceType, ModuleType, Density, Addressing, PackageType, OptFeatures, ThermalRefresh, OptFeatures1, ReservedA, VDD, ModuleOrg, BusWidthECC, ThermSensor, ModuleTypeExt)[source]
    
+
    Bases: chipsec.hal.spd.SPD_DDR4
    
+
    
+
+
    
+
    
+SPD_REVISION(revision: int) → str[source]
    
+
    
+
+
    
+
    
+dram_device_type_name(dram_type: int) → str[source]
    
+
    
+
+
    
+
    
+module_type_name(module_type: int) → str[source]
    
+
    
+
+
    
 
 
             
    
@@ -112,12 +213,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smbus module
    
+                          title="previous chapter">chipsec.hal.smbus module
    
   
    
   
    
     
    Next topic
    
     
    spi module
    
+                          title="next chapter">chipsec.hal.spi module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -143,20 +244,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • spd module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.spd module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.spi.html b/modules/chipsec.hal.spi.html
index 7f5ff2e0..2d565e16 100644
--- a/modules/chipsec.hal.spi.html
+++ b/modules/chipsec.hal.spi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.spi module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi module
    
+  
    
+
    chipsec.hal.spi module
    
 
    Access to SPI Flash parts
    
 
    
 
    usage:
    >>> read_spi( spi_fla, length )
@@ -70,7 +71,149 @@ 
    Navigation
    
 
    Approximate performance (on 2-core SMT Intel Core i5-4300U (Haswell) CPU 1.9GHz):
 SPI read: ~7 sec per 1MB (with DBC=64)
    
 
    
-
    
+
    
+
    
+class SPI(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+SpiRegions
    
+
    alias of Dict[int, Tuple[int, int, int, str, int]]
    
+
    
+
+
    
+
    
+check_hardware_sequencing() → None[source]
    
+
    
+
+
    
+
    
+disable_BIOS_write_protection() → bool[source]
    
+
    
+
+
    
+
    
+display_BIOS_region() → None[source]
    
+
    
+
+
    
+
    
+display_BIOS_write_protection() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_Flash_Descriptor() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_Flash_Regions() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_Protected_Ranges() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_Ranges_Access_Permissions() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_map() → None[source]
    
+
    
+
+
    
+
    
+display_SPI_opcode_info() → None[source]
    
+
    
+
+
    
+
    
+erase_spi_block(spi_fla: int) → bool[source]
    
+
    
+
+
    
+
    
+get_SPI_JEDEC_ID() → int[source]
    
+
    
+
+
    
+
    
+get_SPI_JEDEC_ID_decoded() → Tuple[int, str, str][source]
    
+
    
+
+
    
+
    
+get_SPI_MMIO_base() → int[source]
    
+
    
+
+
    
+
    
+get_SPI_Protected_Range(pr_num: int) → Tuple[int, int, int, int, int, int][source]
    
+
    
+
+
    
+
    
+get_SPI_SFDP() → bool[source]
    
+
    
+
+
    
+
    
+get_SPI_region(spi_region_id: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_SPI_regions(all_regions: bool = True) → Dict[int, Tuple[int, int, int, str, int]][source]
    
+
    
+
+
    
+
    
+ptmesg(offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_spi(spi_fla: int, data_byte_count: int) → bytes[source]
    
+
    
+
+
    
+
    
+read_spi_to_file(spi_fla: int, data_byte_count: int, filename: str) → bytes[source]
    
+
    
+
+
    
+
    
+spi_reg_read(reg: int, size: int = 4) → int[source]
    
+
    
+
+
    
+
    
+spi_reg_write(reg: int, value: int, size: int = 4) → Optional[int][source]
    
+
    
+
+
    
+
    
+write_spi(spi_fla: int, buf: bytes) → bool[source]
    
+
    
+
+
    
+
    
+write_spi_from_file(spi_fla: int, filename: str) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+get_SPI_region(flreg: int) → Tuple[int, int][source]
    
+
    
+
+
    
 
 
             
    
@@ -124,12 +267,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spd module
    
+                          title="previous chapter">chipsec.hal.spd module
    
   
    
   
    
     
    Next topic
    
     
    spi_descriptor module
    
+                          title="next chapter">chipsec.hal.spi_descriptor module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -155,20 +298,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • spi module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.spi module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.spi_descriptor.html b/modules/chipsec.hal.spi_descriptor.html
index 1ebb8fef..ccedcd93 100644
--- a/modules/chipsec.hal.spi_descriptor.html
+++ b/modules/chipsec.hal.spi_descriptor.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_descriptor module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.spi_descriptor module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_descriptor module
    
+  
    
+
    chipsec.hal.spi_descriptor module
    
 
    SPI Flash Descriptor binary parsing functionality
    
 
    
 
    usage:
    >>> fd = read_file( fd_file )
@@ -56,7 +57,27 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+get_SPI_master(flmstr: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_spi_flash_descriptor(rom: bytes) → Tuple[int, bytes][source]
    
+
    
+
+
    
+
    
+get_spi_regions(fd: bytes) → Optional[List[Tuple[int, str, int, int, int, bool]]][source]
    
+
    
+
+
    
+
    
+parse_spi_flash_descriptor(cs, rom: bytes) → None[source]
    
+
    
+
+
    
 
 
             
    
@@ -110,12 +131,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi module
    
+                          title="previous chapter">chipsec.hal.spi module
    
   
    
   
    
     
    Next topic
    
     
    spi_jedec_ids module
    
+                          title="next chapter">chipsec.hal.spi_jedec_ids module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -141,20 +162,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • spi_descriptor module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.spi_descriptor module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.spi_jedec_ids.html b/modules/chipsec.hal.spi_jedec_ids.html
index 3a0f6911..58d39469 100644
--- a/modules/chipsec.hal.spi_jedec_ids.html
+++ b/modules/chipsec.hal.spi_jedec_ids.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_jedec_ids module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.spi_jedec_ids module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,26 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_jedec_ids module
    
+  
    
+
    chipsec.hal.spi_jedec_ids module
    
 
    JEDED ID : Manufacturers and Device IDs
    
-
    
+
    
+
    
+class JEDEC_ID[source]
    
+
    Bases: object
    
+
    
+
    
+DEVICE: Dict[int, str] = {12722199: 'MX25L6408', 12722200: 'MX25L12805', 15679511: 'W25Q64FV (SPI)', 15679512: 'W25Q128 (SPI)', 15679513: 'W25Q256', 15687703: 'W25Q64FV (QPI)', 15687704: 'W25Q128 (QPI)', 15691798: 'W25Q32JV'}
    
+
    
+
+
    
+
    
+MANUFACTURER: Dict[int, str] = {194: 'Macronix', 239: 'Winbond'}
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +120,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_descriptor module
    
+                          title="previous chapter">chipsec.hal.spi_descriptor module
    
   
    
   
    
     
    Next topic
    
     
    spi_uefi module
    
+                          title="next chapter">chipsec.hal.spi_uefi module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +151,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • spi_jedec_ids module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.spi_jedec_ids module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.spi_uefi.html b/modules/chipsec.hal.spi_uefi.html
index d0f0d02a..a53d8c18 100644
--- a/modules/chipsec.hal.spi_uefi.html
+++ b/modules/chipsec.hal.spi_uefi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_uefi module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.spi_uefi module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_uefi module
    
+  
    
+
    chipsec.hal.spi_uefi module
    
 
    UEFI firmware image parsing and manipulation functionality
    
 
    
 
    usage:
    >>> parse_uefi_region_from_file(_uefi, filename, fwtype, outpath):
@@ -55,7 +56,140 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class EFIModuleType[source]
    
+
    Bases: object
    
+
    
+
    
+FILE = 4
    
+
    
+
+
    
+
    
+FV = 2
    
+
    
+
+
    
+
    
+SECTION = 1
    
+
    
+
+
    
+
    
+SECTION_EXE = 0
    
+
    
+
+
    
+
+
    
+
    
+FILENAME(mod: Union[chipsec.hal.uefi_fv.EFI_FILE, chipsec.hal.uefi_fv.EFI_SECTION], parent: Optional[EFI_MODULE], modn: int) → str[source]
    
+
    
+
+
    
+
    
+class UUIDEncoder(*, skipkeys=False, ensure_ascii=True, check_circular=True, allow_nan=True, sort_keys=False, indent=None, separators=None, default=None)[source]
    
+
    Bases: json.encoder.JSONEncoder
    
+
    
+
    
+default(obj: Any)[source]
    
+
    Implement this method in a subclass such that it returns
+a serializable object for o, or calls the base implementation
+(to raise a TypeError).
    
+
    For example, to support arbitrary iterators, you could
+implement default like this:
    
+
    def default(self, o):
+    try:
+        iterable = iter(o)
+    except TypeError:
+        pass
+    else:
+        return list(iterable)
+    # Let the base class default method raise the TypeError
+    return JSONEncoder.default(self, o)
+
    
+
    
+
    
+
+
    
+
+
    
+
    
+build_efi_file_tree(fv_img: bytes, fwtype: str) → List[chipsec.hal.uefi_fv.EFI_FILE][source]
    
+
    
+
+
    
+
    
+build_efi_model(data: bytes, fwtype: str) → List[EFI_MODULE][source]
    
+
    
+
+
    
+
    
+build_efi_modules_tree(fwtype: str, data: bytes, Size: int, offset: int, polarity: bool) → List[chipsec.hal.uefi_fv.EFI_SECTION][source]
    
+
    
+
+
    
+
    
+build_efi_tree(data: bytes, fwtype: str) → List[EFI_MODULE][source]
    
+
    
+
+
    
+
    
+compress_image(image: bytes, compression_type: int) → bytes[source]
    
+
    
+
+
    
+
    
+decode_uefi_region(pth: str, fname: str, fwtype: str, filetype: List[int] = []) → None[source]
    
+
    
+
+
    
+
    
+decompress_section_data(section_dir_path: str, sec_fs_name: str, compressed_data: bytes, compression_type: int) → bytes[source]
    
+
    
+
+
    
+
    
+dump_efi_module(mod, parent: Optional[EFI_MODULE], modn: int, path: str) → str[source]
    
+
    
+
+
    
+
+
    
+
+
    
+
    
+modify_uefi_region(data: bytes, command: int, guid: uuid.UUID, uefi_file: bytes = b'') → bytes[source]
    
+
    
+
+
    
+
    
+parse_uefi_region_from_file(filename: str, fwtype: str, outpath: Optional[str] = None, filetype: List[int] = []) → None[source]
    
+
    
+
+
    
+
    
+save_efi_tree(modules: List[EFI_MODULE], parent: Optional[EFI_MODULE] = None, save_modules: bool = True, path: str = '', save_log: bool = True, lvl: int = 0) → List[Dict[str, Any]][source]
    
+
    
+
+
    
+
    
+save_efi_tree_filetype(modules: List[EFI_MODULE], parent: Optional[EFI_MODULE] = None, path: str = '', lvl: int = 0, filetype: List[int] = [], save: bool = False) → List[Dict[str, Any]][source]
    
+
    
+
+
    
+
    
+search_efi_tree(modules: List[EFI_MODULE], search_callback: Optional[Callable], match_module_types: int = 0, findall: bool = True) → List[EFI_MODULE][source]
    
+
    
+
+
    
+
    
+update_efi_tree(modules: List[EFI_MODULE], parent_guid: Optional[uuid.UUID] = None) → str[source]
    
+
    
+
+
    
 
 
             
    
@@ -109,12 +243,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_jedec_ids module
    
+                          title="previous chapter">chipsec.hal.spi_jedec_ids module
    
   
    
   
    
     
    Next topic
    
     
    tpm module
    
+                          title="next chapter">chipsec.hal.tpm module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +274,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • spi_uefi module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.spi_uefi module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.tpm.html b/modules/chipsec.hal.tpm.html
index f4082c38..191d6b6a 100644
--- a/modules/chipsec.hal.tpm.html
+++ b/modules/chipsec.hal.tpm.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    tpm module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.tpm module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,11 +47,75 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    tpm module
    
+  
    
+
    chipsec.hal.tpm module
    
 
    Trusted Platform Module (TPM) HAL component
    
 
    https://trustedcomputinggroup.org
    
-
    
+
    
+
    
+class TPM(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+command(commandName: str, locality: str, *command_argv: str) → None[source]
    
+
    Send command to the TPM and receive data
    
+
    
+
+
    
+
    
+dump_access(locality: str) → None[source]
    
+
    View the contents of the register used to gain ownership of the TPM
    
+
    
+
+
    
+
    
+dump_didvid(locality: str) → None[source]
    
+
    TPM’s Vendor and Device ID
    
+
    
+
+
    
+
    
+dump_intcap(locality: str) → None[source]
    
+
    Provides information of which interrupts that particular TPM supports
    
+
    
+
+
    
+
    
+dump_intenable(locality: str) → None[source]
    
+
    View the contents of the register used to enable specific interrupts
    
+
    
+
+
    
+
    
+dump_register(register_name: str, locality: str) → None[source]
    
+
    
+
+
    
+
    
+dump_rid(locality: str) → None[source]
    
+
    TPM’s Revision ID
    
+
    
+
+
    
+
    
+dump_status(locality: str) → None[source]
    
+
    View general status details
    
+
    
+
+
    
+
    
+log_register_header(register_name: str, locality: str) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class TPM_RESPONSE_HEADER(ResponseTag, DataSize, ReturnCode)[source]
    
+
    Bases: chipsec.hal.tpm.TPM_RESPONSE_HEADER
    
+
    
+
+
    
 
 
             
    
@@ -104,12 +169,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_uefi module
    
+                          title="previous chapter">chipsec.hal.spi_uefi module
    
   
    
   
    
     
    Next topic
    
     
    tpm12_commands module
    
+                          title="next chapter">chipsec.hal.tpm12_commands module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -135,20 +200,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • tpm module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.tpm module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.tpm12_commands.html b/modules/chipsec.hal.tpm12_commands.html
index a98eb939..72930589 100644
--- a/modules/chipsec.hal.tpm12_commands.html
+++ b/modules/chipsec.hal.tpm12_commands.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    tpm12_commands module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.tpm12_commands module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,12 +47,55 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    tpm12_commands module
    
+  
    
+
    chipsec.hal.tpm12_commands module
    
 
    Definition for TPMv1.2 commands to use with TPM HAL
    
 
    TCG PC Client TPM Specification
 TCG TPM v1.2 Specification
    
-
    
+
    
+
    
+continueselftest(*command_argv: str) → Tuple[bytes, int][source]
    
+
    TPM_ContinueSelfTest informs the TPM that it should complete self-test of all TPM functions. The TPM may return success immediately and then perform the self-test, or it may perform the self-test and then return success or failure.
    
+
    
+
+
    
+
    
+forceclear(*command_argv: str) → Tuple[bytes, int][source]
    
+
    
+
+
    
+
    
+getcap(*command_argv: str) → Tuple[bytes, int][source]
    
+
    Returns current information regarding the TPM
+CapArea    - Capabilities Area
+SubCapSize - Size of SubCapabilities
+SubCap     - Subcapabilities
    
+
    
+
+
    
+
    
+nvread(*command_argv: str) → Tuple[bytes, int][source]
    
+
    Read a value from the NV store
+Index, Offset, Size
    
+
    
+
+
    
+
    
+pcrread(*command_argv: str) → Tuple[bytes, int][source]
    
+
    The TPM_PCRRead operation provides non-cryptographic reporting  of the contents of a named PCR
    
+
    
+
+
    
+
    
+startup(*command_argv: str) → Tuple[bytes, int][source]
    
+
    Execute a tpm_startup command. TPM_Startup is always preceded by TPM_Init, which is the physical indication (a system wide reset) that TPM initialization is necessary
+Type of Startup to be used:
+1: TPM_ST_CLEAR
+2: TPM_ST_STATE
+3: TPM_ST_DEACTIVATED
    
+
    
+
+
    
 
 
             
    
@@ -105,12 +149,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    tpm module
    
+                          title="previous chapter">chipsec.hal.tpm module
    
   
    
   
    
     
    Next topic
    
     
    tpm_eventlog module
    
+                          title="next chapter">chipsec.hal.tpm_eventlog module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -136,20 +180,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • tpm12_commands module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.tpm12_commands module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.tpm_eventlog.html b/modules/chipsec.hal.tpm_eventlog.html
index 80c1a92d..33bdbc59 100644
--- a/modules/chipsec.hal.tpm_eventlog.html
+++ b/modules/chipsec.hal.tpm_eventlog.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    tpm_eventlog module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.tpm_eventlog module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,15 +47,66 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    tpm_eventlog module
    
+  
    
+
    
+
    
+class EFIFirmwareBlob(*args: Any)[source]
    
+
    Bases: chipsec.hal.tpm_eventlog.TcgPcrEvent
    
+
    
+
+
    
+
    
+class PcrLogParser(log: BinaryIO)[source]
    
+
    Bases: object
    
+
    Iterator over the events of a log.
    
+
    
+
    
+next() → chipsec.hal.tpm_eventlog.TcgPcrEvent[source]
    
+
    
+
+
    
+
+
    
+
    
+class SCRTMVersion(*args: Any)[source]
    
+
    Bases: chipsec.hal.tpm_eventlog.TcgPcrEvent
    
+
    
+
+
    
+
    
+class TcgPcrEvent(pcr_index: int, event_type: int, digest: bytes, event_size: int, event: Any)[source]
    
+
    Bases: object
    
+
    An Event (TPM 1.2 format) as recorded in the SML.
    
+
    
+
    
+classmethod parse(log: BinaryIO) → Optional[chipsec.hal.tpm_eventlog.EventType][source]
    
+
    Try to read an event from the log.
    
+
    
+
    Args:
    log (file-like): Log where the event is stored.
    
+
    
+
    Returns:
    An instance of the created event. If a subclass
+exists for such event_type, an object of this class
+is returned. Otherwise, a TcgPcrEvent is returned.
    
+
    
+
    
+
    
+
+
    
+
+
    
+
    
+parse(log: BinaryIO) → None[source]
    
+
    Simple wrapper around PcrLogParser.
    
+
    
+
+
    
 
 
             
    
@@ -108,12 +160,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    tpm12_commands module
    
+                          title="previous chapter">chipsec.hal.tpm12_commands module
    
   
    
   
    
     
    Next topic
    
     
    ucode module
    
+                          title="next chapter">chipsec.hal.ucode module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -139,20 +191,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • tpm_eventlog module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.tpm_eventlog module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.ucode.html b/modules/chipsec.hal.ucode.html
index ee96b187..cfdf7898 100644
--- a/modules/chipsec.hal.ucode.html
+++ b/modules/chipsec.hal.ucode.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    ucode module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.ucode module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    ucode module
    
+  
    
+
    chipsec.hal.ucode module
    
 
    Microcode update specific functionality (for each CPU thread)
    
 
    
 
    usage:
    >>> ucode_update_id( 0 )
@@ -58,7 +59,54 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class Ucode(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+get_cpu_thread_count() → int[source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id: int, ucode_buf: AnyStr) → int[source]
    
+
    
+
+
    
+
    
+ucode_update_id(cpu_thread_id: int) → int[source]
    
+
    
+
+
    
+
    
+update_ucode(cpu_thread_id: int, ucode_file: str) → int[source]
    
+
    
+
+
    
+
    
+update_ucode_all_cpus(ucode_file: str) → bool[source]
    
+
    
+
+
    
+
+
    
+
    
+class UcodeUpdateHeader(header_version, update_revision, date, processor_signature, checksum, loader_revision, processor_flags, data_size, total_size, reserved1, reserved2, reserved3)[source]
    
+
    Bases: chipsec.hal.ucode.UcodeUpdateHeader
    
+
    
+
+
    
+
    
+dump_ucode_update_header(pdb_ucode_buffer: bytes) → chipsec.hal.ucode.UcodeUpdateHeader[source]
    
+
    
+
+
    
+
    
+read_ucode_file(ucode_filename: str) → bytes[source]
    
+
    
+
+
    
 
 
             
    
@@ -112,12 +160,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    tpm_eventlog module
    
+                          title="previous chapter">chipsec.hal.tpm_eventlog module
    
   
    
   
    
     
    Next topic
    
     
    uefi module
    
+                          title="next chapter">chipsec.hal.uefi module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -143,20 +191,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
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    • 
-          
  • hal package »
    • 
-        
  • ucode module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.ucode module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi.html b/modules/chipsec.hal.uefi.html
index 30b9515f..bf5ff9ff 100644
--- a/modules/chipsec.hal.uefi.html
+++ b/modules/chipsec.hal.uefi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,162 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi module
    
+  
    
+
    chipsec.hal.uefi module
    
 
    Main UEFI component using platform specific and common UEFI functionality
    
-
    
+
    
+
    
+class UEFI(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+EfiTable
    
+
    alias of Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name: str, guid: str) → Optional[int][source]
    
+
    
+
+
    
+
    
+dump_EFI_tables() → None[source]
    
+
    
+
+
    
+
    
+dump_EFI_variables_from_SPI() → bytes[source]
    
+
    
+
+
    
+
    
+find_EFI_BootServices_Table() → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_EFI_Configuration_Table() → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_CONFIGURATION_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_EFI_DXEServices_Table() → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_EFI_RuntimeServices_Table() → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_EFI_System_Table() → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_EFI_Table(table_sig: str) → Tuple[bool, int, Optional[chipsec.hal.uefi_common.EFI_TABLE_HEADER], Optional[EFI_SYSTEM_TABLE], bytes][source]
    
+
    
+
+
    
+
    
+find_s3_bootscript() → Tuple[bool, List[int]][source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name: str, guid: str, filename: Optional[str] = None) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_s3_bootscript(log_script: bool = False) → Tuple[List[int], Optional[Dict[int, List[S3BOOTSCRIPT_ENTRY]]]][source]
    
+
    
+
+
    
+
    
+list_EFI_variables() → Optional[Dict[str, List[Tuple[int, bytes, int, bytes, str, int]]]][source]
    
+
    
+
+
    
+
    
+read_EFI_variables(efi_var_store: Optional[bytes], authvars: bool) → Dict[str, List[EfiVariableType]][source]
    
+
    
+
+
    
+
    
+read_EFI_variables_from_SPI(BIOS_region_base: int, BIOS_region_size: int) → bytes[source]
    
+
    
+
+
    
+
    
+read_EFI_variables_from_file(filename: str) → bytes[source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name: str, guid: str, var: bytes, datasize: Optional[int] = None, attrs: Optional[int] = None) → Optional[int][source]
    
+
    
+
+
    
+
    
+set_EFI_variable_from_file(name: str, guid: str, filename: str, datasize: Optional[int] = None, attrs: Optional[int] = None) → Optional[int][source]
    
+
    
+
+
    
+
    
+set_FWType(efi_nvram_format: str) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+decode_EFI_variables(efi_vars: Dict[str, List[EfiVariableType]], nvram_pth: str) → None[source]
    
+
    
+
+
    
+
    
+find_EFI_variable_store(rom_buffer: Optional[bytes], _FWType: Optional[str]) → bytes[source]
    
+
    
+
+
    
+
    
+get_attr_string(attr: int) → str[source]
    
+
    
+
+
    
+
    
+get_auth_attr_string(attr: int) → str[source]
    
+
    
+
+
    
+
    
+identify_EFI_NVRAM(buffer: bytes) → str[source]
    
+
    
+
+
    
+
    
+parse_EFI_variables(fname: str, rom: bytes, authvars: bool, _fw_type: Optional[str] = None) → bool[source]
    
+
    
+
+
    
+
    
+parse_script(script: bytes, log_script: bool = False) → List[S3BOOTSCRIPT_ENTRY][source]
    
+
    
+
+
    
+
    
+print_efi_variable(offset: int, var_buf: bytes, var_header: EfiTableType, var_name: str, var_data: bytes, var_guid: str, var_attrib: int) → None[source]
    
+
    
+
+
    
+
    
+print_sorted_EFI_variables(variables: Dict[str, List[EfiVariableType]]) → None[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +256,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    ucode module
    
+                          title="previous chapter">chipsec.hal.ucode module
    
   
    
   
    
     
    Next topic
    
     
    uefi_common module
    
+                          title="next chapter">chipsec.hal.uefi_common module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +287,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi_common.html b/modules/chipsec.hal.uefi_common.html
index 89eae567..0433053f 100644
--- a/modules/chipsec.hal.uefi_common.html
+++ b/modules/chipsec.hal.uefi_common.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi_common module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi_common module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,643 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi_common module
    
+  
    
+
    chipsec.hal.uefi_common module
    
 
    Common UEFI/EFI functionality including UEFI variables, Firmware Volumes, Secure Boot variables, S3 boot-script, UEFI tables, etc.
    
-
    
+
    
+
    
+class EFI_BOOT_SERVICES_TABLE(RaiseTPL, RestoreTPL, AllocatePages, FreePages, GetMemoryMap, AllocatePool, FreePool, CreateEvent, SetTimer, WaitForEvent, SignalEvent, CloseEvent, CheckEvent, InstallProtocolInterface, ReinstallProtocolInterface, UninstallProtocolInterface, HandleProtocol, Reserved, RegisterProtocolNotify, LocateHandle, LocateDevicePath, InstallConfigurationTable, LoadImage, StartImage, Exit, UnloadImage, ExitBootServices, GetNextMonotonicCount, Stall, SetWatchdogTimer, ConnectController, DisconnectController, OpenProtocol, CloseProtocol, OpenProtocolInformation, ProtocolsPerHandle, LocateHandleBuffer, LocateProtocol, InstallMultipleProtocolInterfaces, UninstallMultipleProtocolInterfaces, CalculateCrc32, CopyMem, SetMem, CreateEventEx)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_BOOT_SERVICES_TABLE
    
+
    
+
+
    
+
    
+class EFI_CONFIGURATION_TABLE[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class EFI_DXE_SERVICES_TABLE(AddMemorySpace, AllocateMemorySpace, FreeMemorySpace, RemoveMemorySpace, GetMemorySpaceDescriptor, SetMemorySpaceAttributes, GetMemorySpaceMap, AddIoSpace, AllocateIoSpace, FreeIoSpace, RemoveIoSpace, GetIoSpaceDescriptor, GetIoSpaceMap, Dispatch, Schedule, Trust, ProcessFirmwareVolume)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_DXE_SERVICES_TABLE
    
+
    
+
+
    
+
    
+EFI_ERROR_STR(error: int) → str[source]
    
+
    Translates an EFI_STATUS value into its corresponding textual representation.
    
+
    
+
+
    
+
    
+EFI_GUID_STR(guid: bytes) → str[source]
    
+
    
+
+
    
+
    
+class EFI_RUNTIME_SERVICES_TABLE(GetTime, SetTime, GetWakeupTime, SetWakeupTime, SetVirtualAddressMap, ConvertPointer, GetVariable, GetNextVariableName, SetVariable, GetNextHighMonotonicCount, ResetSystem, UpdateCapsule, QueryCapsuleCapabilities, QueryVariableInfo)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_RUNTIME_SERVICES_TABLE
    
+
    
+
+
    
+
    
+class EFI_SYSTEM_TABLE(FirmwareVendor, FirmwareRevision, ConsoleInHandle, ConIn, ConsoleOutHandle, ConOut, StandardErrorHandle, StdErr, RuntimeServices, BootServices, NumberOfTableEntries, ConfigurationTable)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_SYSTEM_TABLE
    
+
    
+
+
    
+
    
+EFI_SYSTEM_TABLE_REVISION(revision: int) → str[source]
    
+
    
+
+
    
+
    
+class EFI_TABLE_HEADER(Signature, Revision, HeaderSize, CRC32, Reserved)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_TABLE_HEADER
    
+
    
+
+
    
+
    
+class EFI_VENDOR_TABLE(VendorGuidData, VendorTable)[source]
    
+
    Bases: chipsec.hal.uefi_common.EFI_VENDOR_TABLE
    
+
    
+
    
+VendorGuid() → str[source]
    
+
    
+
+
    
+
+
    
+
    
+IS_EFI_VARIABLE_AUTHENTICATED(attr: int) → bool[source]
    
+
    
+
+
    
+
    
+IS_VARIABLE_ATTRIBUTE(_c: int, _Mask: int) → bool[source]
    
+
    
+
+
    
+
    
+class S3BOOTSCRIPT_ENTRY(script_type: int, index: Optional[int], offset_in_script: int, length: int, data: Optional[bytes] = None)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class S3BootScriptOpcode[source]
    
+
    Bases: object
    
+
    
+
    
+EFI_BOOT_SCRIPT_DISPATCH_OPCODE = 8
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE = 1
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_IO_WRITE_OPCODE = 0
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE = 3
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE = 2
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE = 5
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE = 4
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE = 6
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_STALL_OPCODE = 7
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_TERMINATE_OPCODE = 255
    
+
    
+
+
    
+
+
    
+
    
+class S3BootScriptOpcode_EdkCompat[source]
    
+
    Bases: chipsec.hal.uefi_common.S3BootScriptOpcode
    
+
    
+
    
+EFI_BOOT_SCRIPT_INFORMATION_OPCODE = 10
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_MEM_POLL_OPCODE = 9
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE = 12
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE = 11
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_TABLE_OPCODE = 170
    
+
    
+
+
    
+
+
    
+
    
+class S3BootScriptOpcode_MDE[source]
    
+
    Bases: chipsec.hal.uefi_common.S3BootScriptOpcode
    
+
    
+
    
+EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE = 9
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_INFORMATION_OPCODE = 10
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_IO_POLL_OPCODE = 13
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_MEM_POLL_OPCODE = 14
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE = 16
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE = 12
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE = 11
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE = 15
    
+
    
+
+
    
+
+
    
+
    
+class S3BootScriptSmbusOperation[source]
    
+
    Bases: object
    
+
    
+
    
+BWBR_PROCESS_CALL = 11
    
+
    
+
+
    
+
    
+PROCESS_CALL = 10
    
+
    
+
+
    
+
    
+QUICK_READ = 0
    
+
    
+
+
    
+
    
+QUICK_WRITE = 1
    
+
    
+
+
    
+
    
+READ_BLOCK = 8
    
+
    
+
+
    
+
    
+READ_BYTE = 4
    
+
    
+
+
    
+
    
+READ_WORD = 6
    
+
    
+
+
    
+
    
+RECEIVE_BYTE = 2
    
+
    
+
+
    
+
    
+SEND_BYTE = 3
    
+
    
+
+
    
+
    
+WRITE_BLOCK = 9
    
+
    
+
+
    
+
    
+WRITE_BYTE = 5
    
+
    
+
+
    
+
    
+WRITE_WORD = 7
    
+
    
+
+
    
+
+
    
+
    
+class S3BootScriptWidth[source]
    
+
    Bases: object
    
+
    
+
    
+EFI_BOOT_SCRIPT_WIDTH_UINT16 = 1
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_WIDTH_UINT32 = 2
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_WIDTH_UINT64 = 3
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_WIDTH_UINT8 = 0
    
+
    
+
+
    
+
+
    
+
    
+class StatusCode[source]
    
+
    Bases: object
    
+
    
+
    
+EFI_ABORTED = 21
    
+
    
+
+
    
+
    
+EFI_ACCESS_DENIED = 15
    
+
    
+
+
    
+
    
+EFI_ALREADY_STARTED = 20
    
+
    
+
+
    
+
    
+EFI_BAD_BUFFER_SIZE = 4
    
+
    
+
+
    
+
    
+EFI_BUFFER_TOO_SMALL = 5
    
+
    
+
+
    
+
    
+EFI_COMPROMISED_DATA = 33
    
+
    
+
+
    
+
    
+EFI_CRC_ERROR = 27
    
+
    
+
+
    
+
    
+EFI_DEVICE_ERROR = 7
    
+
    
+
+
    
+
    
+EFI_END_OF_FILE = 31
    
+
    
+
+
    
+
    
+EFI_END_OF_MEDIA = 28
    
+
    
+
+
    
+
    
+EFI_HTTP_ERROR = 35
    
+
    EFI_WARN_UNKNOWN_GLYPH    = 1
+EFI_WARN_DELETE_FAILURE   = 2
+EFI_WARN_WRITE_FAILURE    = 3
+EFI_WARN_BUFFER_TOO_SMALL = 4
+EFI_WARN_STALE_DATA       = 5
+EFI_WARN_FILE_SYSTEM      = 6
    
+
    
+
+
    
+
    
+EFI_ICMP_ERROR = 22
    
+
    
+
+
    
+
    
+EFI_INCOMPATIBLE_VERSION = 25
    
+
    
+
+
    
+
    
+EFI_INVALID_LANGUAGE = 32
    
+
    
+
+
    
+
    
+EFI_INVALID_PARAMETER = 2
    
+
    
+
+
    
+
    
+EFI_LOAD_ERROR = 1
    
+
    
+
+
    
+
    
+EFI_MEDIA_CHANGED = 13
    
+
    
+
+
    
+
    
+EFI_NOT_FOUND = 14
    
+
    
+
+
    
+
    
+EFI_NOT_READY = 6
    
+
    
+
+
    
+
    
+EFI_NOT_STARTED = 19
    
+
    
+
+
    
+
    
+EFI_NO_MAPPING = 17
    
+
    
+
+
    
+
    
+EFI_NO_MEDIA = 12
    
+
    
+
+
    
+
    
+EFI_NO_RESPONSE = 16
    
+
    
+
+
    
+
    
+EFI_OUT_OF_RESOURCES = 9
    
+
    
+
+
    
+
    
+EFI_PROTOCOL_ERROR = 24
    
+
    
+
+
    
+
    
+EFI_SECURITY_VIOLATION = 26
    
+
    
+
+
    
+
    
+EFI_SUCCESS = 0
    
+
    
+
+
    
+
    
+EFI_TFTP_ERROR = 23
    
+
    
+
+
    
+
    
+EFI_TIMEOUT = 18
    
+
    
+
+
    
+
    
+EFI_UNSUPPORTED = 3
    
+
    
+
+
    
+
    
+EFI_VOLUME_CORRUPTED = 10
    
+
    
+
+
    
+
    
+EFI_VOLUME_FULL = 11
    
+
    
+
+
    
+
    
+EFI_WRITE_PROTECTED = 8
    
+
    
+
+
    
+
+
    
+
    
+align(of: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+bit_set(value: int, mask: int, polarity: bool = False) → bool[source]
    
+
    
+
+
    
+
    
+get_3b_size(s_data: bytes) → int[source]
    
+
    
+
+
    
+
    
+get_nvar_name(nvram: bytes, name_offset: int, isAscii: bool)[source]
    
+
    
+
+
    
+
    
+class op_dispatch(opcode: int, size: int, entrypoint: int, context: Optional[int] = None)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_io_pci_mem(opcode: int, size: int, width: int, address: int, unknown: Optional[int], count: Optional[int], buffer: Optional[bytes], value: Optional[int] = None, mask: Optional[int] = None)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_mem_poll(opcode: int, size: int, width: int, address: int, duration: int, looptimes: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_smbus_execute(opcode: int, size: int, address: int, command: int, operation: int, peccheck: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_stall(opcode: int, size: int, duration: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_terminate(opcode: int, size: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class op_unknown(opcode: int, size: int)[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+parse_auth_var(db: bytes, decode_dir: str) → List[bytes][source]
    
+
    
+
+
    
+
    
+parse_efivar_file(fname: str, var: Optional[bytes] = None, var_type: int = 1) → None[source]
    
+
    
+
+
    
+
    
+parse_esal_var(db: bytes, decode_dir: str) → List[bytes][source]
    
+
    
+
+
    
+
    
+parse_external(data)[source]
    
+
    
+
+
    
+
    
+parse_pkcs7(data)[source]
    
+
    
+
+
    
+
    
+parse_rsa2048(data)[source]
    
+
    
+
+
    
+
    
+parse_rsa2048_sha1(data)[source]
    
+
    
+
+
    
+
    
+parse_rsa2048_sha256(data)[source]
    
+
    
+
+
    
+
    
+parse_sb_db(db: bytes, decode_dir: str) → List[bytes][source]
    
+
    
+
+
    
+
    
+parse_sha1(data)[source]
    
+
    
+
+
    
+
    
+parse_sha224(data)[source]
    
+
    
+
+
    
+
    
+parse_sha256(data)[source]
    
+
    
+
+
    
+
    
+parse_sha384(data)[source]
    
+
    
+
+
    
+
    
+parse_sha512(data)[source]
    
+
    
+
+
    
+
    
+parse_x509(data)[source]
    
+
    
+
+
    
+
    
+parse_x509_sha256(data)[source]
    
+
    
+
+
    
+
    
+parse_x509_sha384(data)[source]
    
+
    
+
+
    
+
    
+parse_x509_sha512(data)[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +737,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi module
    
+                          title="previous chapter">chipsec.hal.uefi module
    
   
    
   
    
     
    Next topic
    
     
    uefi_compression module
    
+                          title="next chapter">chipsec.hal.uefi_compression module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +768,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi_common module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi_common module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi_compression.html b/modules/chipsec.hal.uefi_compression.html
index a4aa8f26..92f05bad 100644
--- a/modules/chipsec.hal.uefi_compression.html
+++ b/modules/chipsec.hal.uefi_compression.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi_compression module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi_compression module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,50 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi_compression module
    
-
    
+  
    
+
    chipsec.hal.uefi_compression module
    
+
    
+
    
+class UEFICompression[source]
    
+
    Bases: object
    
+
    
+
    
+compress_EFI_binary(uncompressed_data: bytes, compression_type: int) → bytes[source]
    
+
    
+
+
    
+
    
+decompress_EFI_binary(compressed_data: bytes, compression_type: int) → bytes[source]
    
+
    
+
+
    
+
    
+decompression_oder_type1: List[int] = [1, 2]
    
+
    
+
+
    
+
    
+decompression_oder_type2: List[int] = [1, 2, 3, 4]
    
+
    
+
+
    
+
    
+rotate_list(rot_list: List[Any], n: int) → List[Any][source]
    
+
    
+
+
    
+
    
+unknown_decompress(compressed_data: bytes) → bytes[source]
    
+
    
+
+
    
+
    
+unknown_efi_decompress(compressed_data: bytes) → bytes[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -102,12 +144,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi_common module
    
+                          title="previous chapter">chipsec.hal.uefi_common module
    
   
    
   
    
     
    Next topic
    
     
    uefi_fv module
    
+                          title="next chapter">chipsec.hal.uefi_fv module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +175,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi_compression module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi_compression module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi_fv.html b/modules/chipsec.hal.uefi_fv.html
index 02b5b768..5d099bca 100644
--- a/modules/chipsec.hal.uefi_fv.html
+++ b/modules/chipsec.hal.uefi_fv.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi_fv module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi_fv module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,124 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi_fv module
    
+  
    
+
    chipsec.hal.uefi_fv module
    
 
    UEFI Firmware Volume Parsing/Modification Functionality
    
-
    
+
    
+
    
+DecodeSection(SecType, SecBody, SecHeaderSize) → None[source]
    
+
    
+
+
    
+
    
+class EFI_FILE(Offset: int, Guid: uuid.UUID, Type: int, Attributes: int, State: int, Checksum: int, Size: int, Image: bytes, HeaderSize: int, UD: bool, CalcSum: int)[source]
    
+
    Bases: chipsec.hal.uefi_fv.EFI_MODULE
    
+
    
+
+
    
+
    
+class EFI_FV(Offset: int, Guid: uuid.UUID, Size: int, Attributes: int, HeaderSize: int, Checksum: int, ExtHeaderOffset: int, Image: bytes, CalcSum: int)[source]
    
+
    Bases: chipsec.hal.uefi_fv.EFI_MODULE
    
+
    
+
+
    
+
    
+class EFI_MODULE(Offset: int, Guid: Optional[uuid.UUID], HeaderSize: int, Attributes: int, Image: bytes)[source]
    
+
    Bases: object
    
+
    
+
    
+calc_hashes(off: int = 0) → None[source]
    
+
    
+
+
    
+
    
+name() → str[source]
    
+
    
+
+
    
+
+
    
+
    
+class EFI_SECTION(Offset: int, Name: str, Type: int, Image: bytes, HeaderSize: int, Size: int)[source]
    
+
    Bases: chipsec.hal.uefi_fv.EFI_MODULE
    
+
    
+
    
+name() → str[source]
    
+
    
+
+
    
+
+
    
+
    
+FvChecksum16(buffer: bytes) → int[source]
    
+
    
+
+
    
+
    
+FvChecksum8(buffer: bytes) → int[source]
    
+
    
+
+
    
+
    
+FvSum16(buffer: bytes) → int[source]
    
+
    
+
+
    
+
    
+FvSum8(buffer: bytes) → int[source]
    
+
    
+
+
    
+
    
+GetFvHeader(buffer: bytes, off: int = 0) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+NextFwFile(FvImage: bytes, FvLength: int, fof: int, polarity: bool) → Optional[chipsec.hal.uefi_fv.EFI_FILE][source]
    
+
    
+
+
    
+
    
+NextFwFileSection(sections: bytes, ssize: int, sof: int, polarity: bool) → Optional[chipsec.hal.uefi_fv.EFI_SECTION][source]
    
+
    
+
+
    
+
    
+NextFwVolume(buffer: bytes, off: int = 0, last_fv_size: int = 0) → Optional[chipsec.hal.uefi_fv.EFI_FV][source]
    
+
    
+
+
    
+
    
+ValidateFwVolumeHeader(ZeroVector: str, FsGuid: uuid.UUID, FvLength: int, HeaderLength: int, ExtHeaderOffset: int, Reserved: int, size: int, Calcsum: int, Checksum: int) → bool[source]
    
+
    
+
+
    
+
    
+align_image(image: bytes, size: int = 8, fill: bytes = b'\x00') → bytes[source]
    
+
    
+
+
    
+
    
+assemble_uefi_file(guid: uuid.UUID, image: bytes) → bytes[source]
    
+
    
+
+
    
+
    
+assemble_uefi_raw(image: bytes) → bytes[source]
    
+
    
+
+
    
+
    
+assemble_uefi_section(image: bytes, uncomressed_size: int, compression_type: int) → bytes[source]
    
+
    
+
+
    
+
    
+get_guid_bin(guid: uuid.UUID) → bytes[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +218,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi_compression module
    
+                          title="previous chapter">chipsec.hal.uefi_compression module
    
   
    
   
    
     
    Next topic
    
     
    uefi_platform module
    
+                          title="next chapter">chipsec.hal.uefi_platform module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +249,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi_fv module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi_fv module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi_platform.html b/modules/chipsec.hal.uefi_platform.html
index 31eb0a3e..d028bb0d 100644
--- a/modules/chipsec.hal.uefi_platform.html
+++ b/modules/chipsec.hal.uefi_platform.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi_platform module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi_platform module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,10 +47,288 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi_platform module
    
+  
    
+
    chipsec.hal.uefi_platform module
    
 
    Platform specific UEFI functionality (parsing platform specific EFI NVRAM, capsules, etc.)
    
-
    
+
    
+
    
+class EFI_HDR_NVAR1(StartId, TotalSize, Reserved1, Reserved2, Reserved3, Attributes, State)[source]
    
+
    Bases: chipsec.hal.uefi_platform.EFI_HDR_NVAR1
    
+
    
+
+
    
+
    
+class EFI_HDR_VSS(StartId, State, Reserved, Attributes, NameSize, DataSize, guid)[source]
    
+
    Bases: chipsec.hal.uefi_platform.EFI_HDR_VSS
    
+
    
+
+
    
+
    
+class EFI_HDR_VSS_APPLE(StartId, State, Reserved, Attributes, NameSize, DataSize, guid, unknown)[source]
    
+
    Bases: chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE
    
+
    
+
+
    
+
    
+class EFI_HDR_VSS_AUTH(StartId, State, Reserved, Attributes, MonotonicCount, TimeStamp1, TimeStamp2, PubKeyIndex, NameSize, DataSize, guid)[source]
    
+
    Bases: chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH
    
+
    
+
+
    
+
    
+EFIvar_EVSA(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+class FWType[source]
    
+
    Bases: object
    
+
    
+
    
+EFI_FW_TYPE_EVSA = 'evsa'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_NVAR = 'nvar'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_UEFI = 'uefi'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_UEFI_AUTH = 'uefi_auth'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_VSS = 'vss'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_VSS2 = 'vss2'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_VSS2_AUTH = 'vss2_auth'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_VSS_APPLE = 'vss_apple'
    
+
    
+
+
    
+
    
+EFI_FW_TYPE_VSS_AUTH = 'vss_auth'
    
+
    
+
+
    
+
+
    
+
    
+IS_VARIABLE_STATE(_c: int, _Mask: int) → bool[source]
    
+
    
+
+
    
+
    
+class S3BootScriptType[source]
    
+
    Bases: object
    
+
    
+
    
+EFI_BOOT_SCRIPT_TYPE_DEFAULT = 0
    
+
    
+
+
    
+
    
+EFI_BOOT_SCRIPT_TYPE_EDKCOMPAT = 170
    
+
    
+
+
    
+
+
    
+
    
+class UEFI_VARIABLE_HEADER(StartId, State, Reserved, Attributes, NameSize, DataSize, VendorGuid0, VendorGuid1, VendorGuid2, VendorGuid3)[source]
    
+
    Bases: chipsec.hal.uefi_platform.UEFI_VARIABLE_HEADER
    
+
    
+
+
    
+
    
+UEFI_VARIABLE_STORE_HEADER_SIZE = 28
    
+
    EFI_VARIABLE_HEADER_AUTH = “<HBBI28sIIIHH8s”
+EFI_VARIABLE_HEADER_AUTH_SIZE = struct.calcsize(EFI_VARIABLE_HEADER_AUTH)
    
+
    EFI_VARIABLE_HEADER = “<HBBIIIIHH8s”
+EFI_VARIABLE_HEADER_SIZE = struct.calcsize(EFI_VARIABLE_HEADER)
    
+
    
+
+
    
+
    
+class VARIABLE_STORE_HEADER_VSS(Signature, Size, Format, State, Reserved, Reserved1)[source]
    
+
    Bases: chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS
    
+
    
+
+
    
+
    
+class VARIABLE_STORE_HEADER_VSS2(Signature, Size, Format, State, Reserved, Reserved1)[source]
    
+
    Bases: chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS2
    
+
    
+
+
    
+
    
+create_s3bootscript_entry_buffer(script_type: int, op, index=None) → bytes[source]
    
+
    
+
+
    
+
    
+decode_s3bs_opcode(s3bootscript_type, script_data)[source]
    
+
    
+
+
    
+
    
+decode_s3bs_opcode_def(data)[source]
    
+
    
+
+
    
+
    
+decode_s3bs_opcode_edkcompat(data: bytes)[source]
    
+
    
+
+
    
+
    
+encode_s3bootscript_entry(entry) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+encode_s3bs_opcode(s3bootscript_type: int, op: chipsec.hal.uefi_common.S3BOOTSCRIPT_ENTRY) → bytes[source]
    
+
    
+
+
    
+
    
+encode_s3bs_opcode_def(op) → bytes[source]
    
+
    
+
+
    
+
    
+encode_s3bs_opcode_edkcompat(op: chipsec.hal.uefi_common.S3BOOTSCRIPT_ENTRY) → bytes[source]
    
+
    
+
+
    
+
    
+getEFIvariables_NVAR(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_NVAR_simple(nvram_buf: bytes) → Dict[str, Tuple[int, bytes, bytes, int, str, int]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_UEFI(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_UEFI_AUTH(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_VSS(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_VSS2(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_VSS2_AUTH(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_VSS_APPLE(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getEFIvariables_VSS_AUTH(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, Optional[Union[chipsec.hal.uefi_platform.EFI_HDR_VSS, chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH, chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE]], bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+getNVstore_EFI(nvram_buf: bytes) → Tuple[int, int, None][source]
    
+
    
+
+
    
+
    
+getNVstore_EFI_AUTH(nvram_buf: bytes) → Tuple[int, int, None][source]
    
+
    
+
+
    
+
    
+getNVstore_EVSA(nvram_buf: bytes) → Tuple[int, int, None][source]
    
+
    
+
+
    
+
    
+getNVstore_NVAR(nvram_buf: bytes) → Tuple[int, int, None][source]
    
+
    
+
+
    
+
    
+getNVstore_NVAR_simple(nvram_buf: bytes) → Tuple[Optional[int], int, None][source]
    
+
    
+
+
    
+
    
+getNVstore_VSS(nvram_buf: bytes)[source]
    
+
    
+
+
    
+
    
+getNVstore_VSS2(nvram_buf: bytes)[source]
    
+
    
+
+
    
+
    
+getNVstore_VSS2_AUTH(nvram_buf: bytes)[source]
    
+
    
+
+
    
+
    
+getNVstore_VSS_APPLE(nvram_buf: bytes)[source]
    
+
    
+
+
    
+
    
+getNVstore_VSS_AUTH(nvram_buf: bytes)[source]
    
+
    
+
+
    
+
    
+id_s3bootscript_type(script: bytes, log_script: bool = False) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+isCorrectVSStype(nvram_buf: bytes, vss_type: str)[source]
    
+
    
+
+
    
+
    
+parse_s3bootscript_entry(s3bootscript_type: int, script: bytes, off: int, log_script: bool = False)[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +382,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi_fv module
    
+                          title="previous chapter">chipsec.hal.uefi_fv module
    
   
    
   
    
     
    Next topic
    
     
    uefi_search module
    
+                          title="next chapter">chipsec.hal.uefi_search module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,20 +413,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi_platform module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi_platform module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.uefi_search.html b/modules/chipsec.hal.uefi_search.html
index 49aa9972..c40b3590 100644
--- a/modules/chipsec.hal.uefi_search.html
+++ b/modules/chipsec.hal.uefi_search.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi_search module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.uefi_search module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
+
    
+
    
+check_match_criteria(efi: chipsec.hal.uefi_fv.EFI_SECTION, criteria: Dict[str, Dict[str, Dict[str, str]]], _log: Callable, cpuid: Optional[str] = None) → bool[source]
    
+
    
+
+
    
+
    
+check_rules(efi: chipsec.hal.uefi_fv.EFI_SECTION, rules: Dict[str, Any], entry_name: str, _log: Callable, bLog: bool = True, cpuid: Optional[str] = None) → bool[source]
    
+
    
+
+
    
 
 
             
    
@@ -109,12 +120,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi_platform module
    
+                          title="previous chapter">chipsec.hal.uefi_platform module
    
   
    
   
    
     
    Next topic
    
     
    virtmem module
    
+                          title="next chapter">chipsec.hal.virtmem module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +151,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • uefi_search module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.uefi_search module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.virtmem.html b/modules/chipsec.hal.virtmem.html
index 4a6cfcdf..4005b31e 100644
--- a/modules/chipsec.hal.virtmem.html
+++ b/modules/chipsec.hal.virtmem.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    virtmem module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.virtmem module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,8 +47,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    virtmem module
    
+  
    
+
    chipsec.hal.virtmem module
    
 
    Access to virtual memory
    
 
    
 
    usage:
    >>> read_virtual_mem( 0xf0000, 0x100 )
@@ -58,7 +59,68 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class VirtMemory(cs)[source]
    
+
    Bases: chipsec.hal.hal_base.HALBase
    
+
    
+
    
+alloc_virtual_mem(length: int, max_phys_address: int = 18446744073709551615) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+free_virtual_mem(virt_address: int) → bool[source]
    
+
    
+
+
    
+
    
+read_virtual_mem(virt_address: int, length: int) → int[source]
    
+
    
+
+
    
+
    
+read_virtual_mem_byte(virt_address: int) → int[source]
    
+
    
+
+
    
+
    
+read_virtual_mem_dword(virt_address: int) → int[source]
    
+
    
+
+
    
+
    
+read_virtual_mem_word(virt_address: int) → int[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → int[source]
    
+
    
+
+
    
+
    
+write_virtual_mem(virt_address: int, length: int, buf: bytes) → int[source]
    
+
    
+
+
    
+
    
+write_virtual_mem_byte(virt_address: int, byte_value: int) → int[source]
    
+
    
+
+
    
+
    
+write_virtual_mem_dword(virt_address: int, dword_value: int) → int[source]
    
+
    
+
+
    
+
    
+write_virtual_mem_word(virt_address: int, word_value: int) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -112,12 +174,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi_search module
    
+                          title="previous chapter">chipsec.hal.uefi_search module
    
   
    
   
    
     
    Next topic
    
     
    vmm module
    
+                          title="next chapter">chipsec.hal.vmm module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -143,20 +205,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • virtmem module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.virtmem module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.hal.vmm.html b/modules/chipsec.hal.vmm.html
index a005aa36..23141553 100644
--- a/modules/chipsec.hal.vmm.html
+++ b/modules/chipsec.hal.vmm.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    vmm module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.hal.vmm module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,14 +47,71 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    vmm module
    
+  
    
+
    chipsec.hal.vmm module
    
 
    VMM specific functionality
 1. Hypervisor hypercall interfaces
 2. Second-level Address Translation (SLAT)
 3. VirtIO devices
 4. …
    
-
    
+
    
+
    
+class VMM(cs)[source]
    
+
    Bases: object
    
+
    
+
    
+dump_EPT_page_tables(eptp: str, pt_fname: Optional[str] = None) → None[source]
    
+
    
+
+
    
+
    
+hypercall(rax: int, rbx: int, rcx: int, rdx: int, rdi: int, rsi: int, r8: int = 0, r9: int = 0, r10: int = 0, r11: int = 0, xmm_buffer: int = 0) → int[source]
    
+
    
+
+
    
+
    
+hypercall64_extended_fast(hypervisor_input_value: int, parameter_block: bytes) → int[source]
    
+
    
+
+
    
+
    
+hypercall64_fast(hypervisor_input_value: int, param0: int = 0, param1: int = 0) → int[source]
    
+
    
+
+
    
+
    
+hypercall64_five_args(vector: int, arg1: int = 0, arg2: int = 0, arg3: int = 0, arg4: int = 0, arg5: int = 0) → int[source]
    
+
    
+
+
    
+
    
+hypercall64_memory_based(hypervisor_input_value: int, parameters: AnyStr, size: int = 0) → int[source]
    
+
    
+
+
    
+
    
+init() → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class VirtIO_Device(cs, b, d, f)[source]
    
+
    Bases: object
    
+
    
+
    
+dump_device() → None[source]
    
+
    
+
+
    
+
+
    
+
    
+get_virtio_devices(devices: List[Tuple[int, int, int, int, int]]) → List[Tuple[int, int, int, int, int]][source]
    
+
    
+
+
    
 
 
             
    
@@ -107,12 +165,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    virtmem module
    
+                          title="previous chapter">chipsec.hal.virtmem module
    
   
    
   
    
     
    Next topic
    
     
    fuzzing package
    
+                          title="next chapter">chipsec.fuzzing package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -138,20 +196,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • Architecture Overview »
    • 
-          
  • hal package »
    • 
-        
  • vmm module
    •  
+          
  • chipsec.hal package »
    • 
+        
  • chipsec.hal.vmm module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.basehelper.html b/modules/chipsec.helper.basehelper.html
index 94b42fa1..839a75e2 100644
--- a/modules/chipsec.helper.basehelper.html
+++ b/modules/chipsec.helper.basehelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    basehelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.basehelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,215 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    basehelper module
    
-
    
+  
    
+
    chipsec.helper.basehelper module
    
+
    
+
    
+class Helper[source]
    
+
    Bases: abc.ABC
    
+
    
+
    
+abstract EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+abstract alloc_phys_mem(size: int, max_phys_address: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+abstract cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+abstract create() → bool[source]
    
+
    
+
+
    
+
    
+abstract delete() → bool[source]
    
+
    
+
+
    
+
    
+abstract delete_EFI_variable(name: str, guid: str) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract free_phys_mem(phys_address: int)[source]
    
+
    
+
+
    
+
    
+abstract get_ACPI_SDT() → Tuple[Optional[Array], bool][source]
    
+
    
+
+
    
+
    
+abstract get_ACPI_table(table_name: str) → Optional[Array][source]
    
+
    
+
+
    
+
    
+abstract get_EFI_variable(name: str, guid: str) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+abstract get_affinity() → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract get_descriptor_table(cpu_thread_id: int, desc_table_code: int) → Optional[Tuple[int, int, int]][source]
    
+
    
+
+
    
+
    
+get_info() → Tuple[str, str][source]
    
+
    
+
+
    
+
    
+abstract get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+abstract hypercall(rcx: int, rdx: int, r8: int, r9: int, r10: int, r11: int, rax: int, rbx: int, rdi: int, rsi: int, xmm_buffer: int) → int[source]
    
+
    
+
+
    
+
    
+abstract list_EFI_variables() → Optional[Dict[str, List[EfiVariableType]]][source]
    
+
    
+
+
    
+
    
+abstract load_ucode_update(cpu_thread_id: int, ucode_update_buffer: bytes) → bool[source]
    
+
    
+
+
    
+
    
+abstract map_io_space(phys_address: int, size: int, cache_type: int) → int[source]
    
+
    
+
+
    
+
    
+abstract msgbus_send_message(mcr: int, mcrx: int, mdr: Optional[int]) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract msgbus_send_read_message(mcr: int, mcrx: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract msgbus_send_write_message(mcr: int, mcrx: int, mdr: int) → None[source]
    
+
    
+
+
    
+
    
+abstract read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+abstract read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+abstract read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+abstract read_msr(cpu_thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+abstract read_pci_reg(bus: int, device: int, function: int, address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+abstract read_phys_mem(phys_address: int, size: int) → bytes[source]
    
+
    
+
+
    
+
    
+abstract retpoline_enabled() → bool[source]
    
+
    
+
+
    
+
    
+abstract send_sw_smi(cpu_thread_id: int, SMI_code_data: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract set_EFI_variable(name: str, guid: str, buffer: bytes, buffer_size: Optional[int], attrs: Optional[int]) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract set_affinity(value: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+abstract start() → bool[source]
    
+
    
+
+
    
+
    
+abstract stop() → bool[source]
    
+
    
+
+
    
+
    
+abstract va2pa(virtual_address: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+abstract write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+abstract write_io_port(io_port: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+abstract write_mmio_reg(phys_address: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+abstract write_msr(cpu_thread_id: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+abstract write_pci_reg(bus: int, device: int, function: int, address: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+abstract write_phys_mem(phys_address: int, size: int, buffer: bytes) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -102,12 +309,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    windowshelper module
    
+                          title="previous chapter">chipsec.helper.windows.windowshelper module
    
   
    
   
    
     
    Next topic
    
     
    nonehelper module
    
+                          title="next chapter">chipsec.helper.nonehelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +340,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • basehelper module
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.basehelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.dal.dalhelper.html b/modules/chipsec.helper.dal.dalhelper.html
index 633f266c..775cb2ff 100644
--- a/modules/chipsec.helper.dal.dalhelper.html
+++ b/modules/chipsec.helper.dal.dalhelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    dalhelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.dal.dalhelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,11 +48,242 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    dalhelper module
    
+  
    
+
    chipsec.helper.dal.dalhelper module
    
 
    Intel DFx Abstraction Layer (DAL) helper
    
 
    From the Intel(R) DFx Abstraction Layer Python* Command Line Interface User Guide
    
-
    
+
    
+
    
+class DALHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+alloc_phys_mem(length, max_phys_address)[source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create(start_driver: bool) → bool[source]
    
+
    
+
+
    
+
    
+dal_version() → str[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name, guid)[source]
    
+
    
+
+
    
+
    
+find_thread() → int[source]
    
+
    
+
+
    
+
    
+free_phys_mem(physical_address)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT()[source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name)[source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name, guid, attrs)[source]
    
+
    
+
+
    
+
    
+get_affinity()[source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id, desc_table_code)[source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+get_tool_info(tool_type: str) → Tuple[str, str][source]
    
+
    
+
+
    
+
    
+hypercall(rcx, rdx, r8, r9, r10, r11, rax, rbx, rdi, rsi, xmm_buffer)[source]
    
+
    
+
+
    
+
    
+list_EFI_variables()[source]
    
+
    
+
+
    
+
    
+load_ucode_update(core_id, ucode_update_buf)[source]
    
+
    
+
+
    
+
    
+map_io_space(physical_address: int, length: int, cache_type: int) → int[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr, mcrx)[source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+pci_addr(bus: int, device: int, function: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(thread: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address: int, length: int, bytewise: bool = False) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled() → bool[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id, SMI_code_data, _rax, _rbx, _rcx, _rdx, _rsi, _rdi)[source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name, guid, buffer, buffer_size, attrs)[source]
    
+
    
+
+
    
+
    
+set_affinity(value)[source]
    
+
    
+
+
    
+
    
+start(start_driver: bool, driver_exhists: bool = False) → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+target_machine() → str[source]
    
+
    
+
+
    
+
    
+va2pa(va)[source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_msr(thread: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, address: int, dword_value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address: int, length: int, buf: bytes, bytewise: bool = False) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+get_helper() → chipsec.helper.dal.dalhelper.DALHelper[source]
    
+
    
+
+
    
 
 
             
    
@@ -105,12 +337,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    dal package
    
+                          title="previous chapter">chipsec.helper.dal package
    
   
    
   
    
     
    Next topic
    
     
    efi package
    
+                          title="next chapter">chipsec.helper.efi package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -136,21 +368,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • dal package »
    • 
-        
  • dalhelper module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.dal package »
    • 
+        
  • chipsec.helper.dal.dalhelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.dal.html b/modules/chipsec.helper.dal.html
index b3b6209e..97dfb0de 100644
--- a/modules/chipsec.helper.dal.html
+++ b/modules/chipsec.helper.dal.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    dal package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.dal package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,14 +47,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    dal package
    
+  
    
+
    chipsec.helper.dal package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -107,12 +114,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    helper package
    
+                          title="previous chapter">chipsec.helper package
    
   
    
   
    
     
    Next topic
    
     
    dalhelper module
    
+                          title="next chapter">chipsec.helper.dal.dalhelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -138,20 +145,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • dal package
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.dal package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.efi.efihelper.html b/modules/chipsec.helper.efi.efihelper.html
index 112f7a1d..4b73dd5c 100644
--- a/modules/chipsec.helper.efi.efihelper.html
+++ b/modules/chipsec.helper.efi.efihelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    efihelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.efi.efihelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,10 +48,236 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    efihelper module
    
+  
    
+
    chipsec.helper.efi.efihelper module
    
 
    On UEFI use the efi package functions
    
-
    
+
    
+
    
+class EfiHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+alloc_phys_mem(length: int, max_pa: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create() → bool[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name: str, guid: str) → int[source]
    
+
    
+
+
    
+
    
+free_phys_mem(physical_address)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT() → Tuple[None, bool][source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name)[source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name: str, guidstr: str) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_EFI_variable_full(name: str, guidstr: str) → Tuple[int, Optional[bytes], int][source]
    
+
    
+
+
    
+
    
+get_affinity()[source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id: int, desc_table_code: int) → None[source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+get_tool_info(tool_type: str) → Tuple[str, str][source]
    
+
    
+
+
    
+
    
+hypercall(rcx, rdx, r8, r9, r10, r11, rax, rbx, rdi, rsi, xmm_buffer)[source]
    
+
    
+
+
    
+
    
+list_EFI_variables() → Optional[Dict[str, List[EfiVariableType]]][source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id: int, ucode_update_buf: int) → bool[source]
    
+
    
+
+
    
+
    
+map_io_space(physical_address: int, length: int, cache_type: int) → int[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr: int, mcrx: int, mdr: Optional[int] = None) → None[source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr: int, mcrx: int) → None[source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr: int, mcrx: int, mdr: int) → None[source]
    
+
    
+
+
    
+
    
+pa2va(pa: int) → int[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(cpu_thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address: int, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled() → bool[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id: int, SMI_code_data: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → None[source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name: str, guidstr: str, buffer: bytes, buffer_size: Optional[int] = None, attrs: Optional[int] = 7) → int[source]
    
+
    
+
+
    
+
    
+set_affinity(value: int) → None[source]
    
+
    
+
+
    
+
    
+split_address(pa: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+start() → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_msr(cpu_thread_id: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, address: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address: int, length: int, buf: bytes) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+get_helper() → chipsec.helper.efi.efihelper.EfiHelper[source]
    
+
    
+
+
    
 
 
             
    
@@ -104,12 +331,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    efi package
    
+                          title="previous chapter">chipsec.helper.efi package
    
   
    
   
    
     
    Next topic
    
     
    linux package
    
+                          title="next chapter">chipsec.helper.linux package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -135,21 +362,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • efi package »
    • 
-        
  • efihelper module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.efi package »
    • 
+        
  • chipsec.helper.efi.efihelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.efi.html b/modules/chipsec.helper.efi.html
index 8fe443ca..68e7a563 100644
--- a/modules/chipsec.helper.efi.html
+++ b/modules/chipsec.helper.efi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    efi package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.efi package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,14 +47,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    efi package
    
+  
    
+
    chipsec.helper.efi package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -107,12 +114,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    dalhelper module
    
+                          title="previous chapter">chipsec.helper.dal.dalhelper module
    
   
    
   
    
     
    Next topic
    
     
    efihelper module
    
+                          title="next chapter">chipsec.helper.efi.efihelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -138,20 +145,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • efi package
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.efi package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.html b/modules/chipsec.helper.html
index 7a2af42c..a8b6f1cf 100644
--- a/modules/chipsec.helper.html
+++ b/modules/chipsec.helper.html
@@ -1,22 +1,23 @@
+
 
 
-
+
   
     
-    
-
-    helper package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
+    
      
   
       
 
@@ -45,42 +46,71 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    helper package
    
+  
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -139,7 +169,7 @@ 
    Previous topic
    
   
    
     
    Next topic
    
     
    dal package
    
+                          title="next chapter">chipsec.helper.dal package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -165,19 +195,19 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
           previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-        
  • helper package
    •  
+        
  • chipsec.helper package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linux.html b/modules/chipsec.helper.linux.html
index 6564d1f3..3247c12f 100644
--- a/modules/chipsec.helper.linux.html
+++ b/modules/chipsec.helper.linux.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    linux package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linux package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,14 +47,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    linux package
    
+  
    
+
    chipsec.helper.linux package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -107,12 +114,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    efihelper module
    
+                          title="previous chapter">chipsec.helper.efi.efihelper module
    
   
    
   
    
     
    Next topic
    
     
    linuxhelper module
    
+                          title="next chapter">chipsec.helper.linux.linuxhelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -138,20 +145,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • linux package
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.linux package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linux.linuxhelper.html b/modules/chipsec.helper.linux.linuxhelper.html
index d136ca09..708d5051 100644
--- a/modules/chipsec.helper.linux.linuxhelper.html
+++ b/modules/chipsec.helper.linux.linuxhelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    linuxhelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linux.linuxhelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,10 +48,321 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    linuxhelper module
    
+  
    
+
    chipsec.helper.linux.linuxhelper module
    
 
    Linux helper
    
-
    
+
    
+
    
+class LinuxHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+DEVICE_NAME = '/dev/chipsec'
    
+
    
+
+
    
+
    
+DEV_MEM = '/dev/mem'
    
+
    
+
+
    
+
    
+DEV_PORT = '/dev/port'
    
+
    
+
+
    
+
    
+DKMS_DIR = '/var/lib/dkms/'
    
+
    
+
+
    
+
    
+EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+MODULE_NAME = 'chipsec'
    
+
    
+
+
    
+
    
+SUPPORT_KERNEL26_GET_PAGE_IS_RAM = False
    
+
    
+
+
    
+
    
+SUPPORT_KERNEL26_GET_PHYS_MEM_ACCESS_PROT = False
    
+
    
+
+
    
+
    
+alloc_phys_mem(num_bytes: int, max_addr: int)[source]
    
+
    
+
+
    
+
    
+close() → None[source]
    
+
    
+
+
    
+
    
+compute_ioctlbase(itype: str = 'C') → int[source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create()[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name: str, guid: str) → int[source]
    
+
    
+
+
    
+
    
+free_phys_mem(physmem: int)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT()[source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name)[source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name: str, guid: str, attrs: Optional[int] = None) → bytes[source]
    
+
    
+
+
    
+
    
+get_affinity() → Optional[int][source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id: int, desc_table_code: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_dkms_module_location() → str[source]
    
+
    
+
+
    
+
    
+get_page_is_ram() → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_phys_mem_access_prot() → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+get_tool_info(tool_type: str) → Tuple[Optional[str], str][source]
    
+
    
+
+
    
+
    
+hypercall(rcx: int, rdx: int, r8: int, r9: int, r10: int, r11: int, rax: int, rbx: int, rdi: int, rsi: int, xmm_buffer: int) → int[source]
    
+
    
+
+
    
+
    
+init() → None[source]
    
+
    
+
+
    
+
    
+ioctl(nr: int, args: Iterable, *mutate_flag: bool) → bytes[source]
    
+
    
+
+
    
+
    
+kern_get_EFI_variable(name: str, guid: str) → bytes[source]
    
+
    
+
+
    
+
    
+kern_get_EFI_variable_full(name: str, guid: str) → EfiVariableType[source]
    
+
    
+
+
    
+
    
+kern_list_EFI_variables() → Optional[Dict[str, List[EfiVariableType]]][source]
    
+
    
+
+
    
+
    
+kern_set_EFI_variable(name: str, guid: str, value: bytes, attr: int = 7) → int[source]
    
+
    
+
+
    
+
    
+list_EFI_variables() → Optional[Dict[str, List[EfiVariableType]]][source]
    
+
    
+
+
    
+
    
+load_chipsec_module()[source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id: int, ucode_update_buf: bytes) → bool[source]
    
+
    
+
+
    
+
    
+map_io_space(base: int, size: int, cache_type: int) → None[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr: int, mcrx: int, mdr: Optional[int] = None) → int[source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr: int, mcrx: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr: int, mcrx: int, mdr: int) → None[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, offset: int, size: int = 4) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address: int, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled()[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id: int, SMI_code_data: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → Optional[Tuple[int, int, int, int, int, int, int]][source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name: str, guid: str, buffer: bytes, buffer_size: int, attrs: Optional[int] = None) → int[source]
    
+
    
+
+
    
+
    
+set_affinity(thread_id: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+start() → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+unload_chipsec_module() → None[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → Tuple[Optional[int], int][source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int)[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → bytes[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int)[source]
    
+
    
+
+
    
+
    
+write_msr(thread_id: int, msr_addr: int, eax: int, edx: int)[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, offset: int, value: int, size: int = 4) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address: int, length: int, newval: bytes) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+get_helper()[source]
    
+
    
+
+
    
 
 
             
    
@@ -104,12 +416,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    linux package
    
+                          title="previous chapter">chipsec.helper.linux package
    
   
    
   
    
     
    Next topic
    
     
    linuxnative package
    
+                          title="next chapter">chipsec.helper.linuxnative package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -135,21 +447,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • linux package »
    • 
-        
  • linuxhelper module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.linux package »
    • 
+        
  • chipsec.helper.linux.linuxhelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linuxnative.cpuid.html b/modules/chipsec.helper.linuxnative.cpuid.html
index 7e09d43f..80b6bd2e 100644
--- a/modules/chipsec.helper.linuxnative.cpuid.html
+++ b/modules/chipsec.helper.linuxnative.cpuid.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cpuid module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linuxnative.cpuid module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,9 +48,45 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cpuid module
    
-
    
+  
    
+
    chipsec.helper.linuxnative.cpuid module
    
+
    
+
    
+class CPUID[source]
    
+
    Bases: object
    
+
    
+
+
    
+
    
+class CPUID_struct[source]
    
+
    Bases: _ctypes.Structure
    
+
    
+
    
+eax
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+ebx
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+ecx
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+edx
    
+
    Structure/Union member
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +140,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    linuxnative package
    
+                          title="previous chapter">chipsec.helper.linuxnative package
    
   
    
   
    
     
    Next topic
    
     
    legacy_pci module
    
+                          title="next chapter">chipsec.helper.linuxnative.legacy_pci module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,21 +171,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • linuxnative package »
    • 
-        
  • cpuid module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.linuxnative package »
    • 
+        
  • chipsec.helper.linuxnative.cpuid module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linuxnative.html b/modules/chipsec.helper.linuxnative.html
index 9715b914..f43e528b 100644
--- a/modules/chipsec.helper.linuxnative.html
+++ b/modules/chipsec.helper.linuxnative.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    linuxnative package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linuxnative package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,16 +47,22 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    linuxnative package
    
+  
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -109,12 +116,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    linuxhelper module
    
+                          title="previous chapter">chipsec.helper.linux.linuxhelper module
    
   
    
   
    
     
    Next topic
    
     
    cpuid module
    
+                          title="next chapter">chipsec.helper.linuxnative.cpuid module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,20 +147,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • linuxnative package
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.linuxnative package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linuxnative.legacy_pci.html b/modules/chipsec.helper.linuxnative.legacy_pci.html
index e6e1156f..578fb8ac 100644
--- a/modules/chipsec.helper.linuxnative.legacy_pci.html
+++ b/modules/chipsec.helper.linuxnative.legacy_pci.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    legacy_pci module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linuxnative.legacy_pci module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,9 +48,51 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    legacy_pci module
    
-
    
+  
    
+
    chipsec.helper.linuxnative.legacy_pci module
    
+
    
+
    
+class LegacyPci[source]
    
+
    Bases: object
    
+
    
+
    
+static read_pci_config(bus: int, dev: int, func: int, offset: int) → int[source]
    
+
    
+
+
    
+
    
+static write_pci_config(bus: int, dev: int, func: int, offset: int, value: int) → None[source]
    
+
    
+
+
    
+
+
    
+
    
+class Ports[source]
    
+
    Bases: object
    
+
    
+
    
+classmethod get_instance() → chipsec.helper.linuxnative.legacy_pci.Ports[source]
    
+
    
+
+
    
+
    
+inl(port: int) → int[source]
    
+
    
+
+
    
+
    
+instance = None
    
+
    
+
+
    
+
    
+outl(value: int, port: int) → None[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -103,12 +146,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cpuid module
    
+                          title="previous chapter">chipsec.helper.linuxnative.cpuid module
    
   
    
   
    
     
    Next topic
    
     
    linuxnativehelper module
    
+                          title="next chapter">chipsec.helper.linuxnative.linuxnativehelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,21 +177,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • linuxnative package »
    • 
-        
  • legacy_pci module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.linuxnative package »
    • 
+        
  • chipsec.helper.linuxnative.legacy_pci module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.linuxnative.linuxnativehelper.html b/modules/chipsec.helper.linuxnative.linuxnativehelper.html
index 7b943e02..7d4b67f8 100644
--- a/modules/chipsec.helper.linuxnative.linuxnativehelper.html
+++ b/modules/chipsec.helper.linuxnative.linuxnativehelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    linuxnativehelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.linuxnative.linuxnativehelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,10 +48,285 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    linuxnativehelper module
    
+  
    
+
    chipsec.helper.linuxnative.linuxnativehelper module
    
 
    Native Linux helper
    
-
    
+
    
+
    
+class LinuxNativeHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+DEV_MEM = '/dev/mem'
    
+
    
+
+
    
+
    
+DEV_PORT = '/dev/port'
    
+
    
+
+
    
+
    
+EFI_supported()[source]
    
+
    
+
+
    
+
    
+alloc_phys_mem(length, max_phys_address)[source]
    
+
    
+
+
    
+
    
+close()[source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create() → bool[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name, guid)[source]
    
+
    
+
+
    
+
    
+devmem_available() → bool[source]
    
+
    Check if /dev/mem is usable.
+In case the driver is not loaded, we might be able to perform the
+requested operation via /dev/mem. Returns True if /dev/mem is
+accessible.
    
+
    
+
+
    
+
    
+devmsr_available() → bool[source]
    
+
    Check if /dev/cpu/CPUNUM/msr is usable.
+In case the driver is not loaded, we might be able to perform the
+requested operation via /dev/cpu/CPUNUM/msr. This requires loading
+the (more standard) msr driver. Returns True if /dev/cpu/CPUNUM/msr
+is accessible.
    
+
    
+
+
    
+
    
+devport_available() → bool[source]
    
+
    Check if /dev/port is usable.
+In case the driver is not loaded, we might be able to perform the
+requested operation via /dev/port. Returns True if /dev/port is
+accessible.
    
+
    
+
+
    
+
    
+free_phys_mem(physical_address)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT()[source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name)[source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name, guid)[source]
    
+
    
+
+
    
+
    
+get_affinity() → Optional[int][source]
    
+
    
+
+
    
+
    
+get_bios_version() → str[source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id, desc_table_code)[source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+hypercall(rcx=0, rdx=0, r8=0, r9=0, r10=0, r11=0, rax=0, rbx=0, rdi=0, rsi=0, xmm_buffer=0)[source]
    
+
    
+
+
    
+
    
+init()[source]
    
+
    
+
+
    
+
    
+list_EFI_variables()[source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id, ucode_update_buf)[source]
    
+
    
+
+
    
+
    
+map_io_space(base: int, size: int, cache_type: int) → None[source]
    
+
    Map to memory a specific region.
    
+
    
+
+
    
+
    
+memory_mapping(base: int, size: int) → Optional[chipsec.helper.linuxnative.linuxnativehelper.MemoryMapping][source]
    
+
    Returns the mmap region that fully encompasses this area.
+Returns None if no region matches.
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr, mcrx)[source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id, cr_number)[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, offset: int, size: int, domain: int = 0) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled()[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id, SMI_code_data, _rax, _rbx, _rcx, _rdx, _rsi, _rdi)[source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name, guid, buffer, buffer_size=None, attrs=None)[source]
    
+
    
+
+
    
+
    
+set_affinity(thread_id: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+start() → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+va2pa(va)[source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id, cr_number, value)[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → bool[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int) → None[source]
    
+
    
+
+
    
+
    
+write_msr(thread_id: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, offset: int, value: int, size: int = 4, domain: int = 0) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address, length: int, newval: bytes) → int[source]
    
+
    
+
+
    
+
+
    
+
    
+class MemoryMapping(fileno, length, flags, prot, offset)[source]
    
+
    Bases: mmap.mmap
    
+
    Memory mapping based on Python’s mmap.
+This subclass keeps tracks of the start and end of the mapping.
    
+
    
+
+
    
+
    
+get_helper()[source]
    
+
    
+
+
    
 
 
             
    
@@ -104,12 +380,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    legacy_pci module
    
+                          title="previous chapter">chipsec.helper.linuxnative.legacy_pci module
    
   
    
   
    
     
    Next topic
    
     
    windows package
    
+                          title="next chapter">chipsec.helper.windows package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -135,21 +411,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • linuxnative package »
    • 
-        
  • linuxnativehelper module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.linuxnative package »
    • 
+        
  • chipsec.helper.linuxnative.linuxnativehelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.nonehelper.html b/modules/chipsec.helper.nonehelper.html
index d8462783..e483b798 100644
--- a/modules/chipsec.helper.nonehelper.html
+++ b/modules/chipsec.helper.nonehelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    nonehelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.nonehelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,215 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    nonehelper module
    
-
    
+  
    
+
    chipsec.helper.nonehelper module
    
+
    
+
    
+class NoneHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+alloc_phys_mem(length: int, max_phys_address: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create() → bool[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name: str, guid: str) → Optional[int][source]
    
+
    
+
+
    
+
    
+free_phys_mem(physical_address: int)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT() → Tuple[Optional[Array], bool][source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name: str) → Optional[Array][source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name: str, guid: str) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_affinity() → Optional[int][source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id: int, desc_table_code: int) → Optional[Tuple[int, int, int]][source]
    
+
    
+
+
    
+
    
+get_info() → Tuple[str, str][source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+hypercall(rcx: int, rdx: int, r8: int, r9: int, r10: int, r11: int, rax: int, rbx: int, rdi: int, rsi: int, xmm_buffer: int) → int[source]
    
+
    
+
+
    
+
    
+list_EFI_variables() → Optional[Dict[str, List[EfiVariableType]]][source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id: int, ucode_update_buf: bytes) → bool[source]
    
+
    
+
+
    
+
    
+map_io_space(physical_address: int, length: int, cache_type: int) → int[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr: int, mcrx: int, mdr: Optional[int]) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr: int, mcrx: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr: int, mcrx: int, mdr: int) → None[source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(cpu_thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address: int, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled() → bool[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id: int, SMI_code_data: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name: str, guid: str, data: bytes, datasize: Optional[int], attrs: Optional[int]) → Optional[int][source]
    
+
    
+
+
    
+
    
+set_affinity(value: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+start() → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_msr(cpu_thread_id: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, address: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address: int, length: int, buf: bytes) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -102,12 +309,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    basehelper module
    
+                          title="previous chapter">chipsec.helper.basehelper module
    
   
    
   
    
     
    Next topic
    
     
    oshelper module
    
+                          title="next chapter">chipsec.helper.oshelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +340,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • nonehelper module
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.nonehelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.oshelper.html b/modules/chipsec.helper.oshelper.html
index f880a7ce..6b262840 100644
--- a/modules/chipsec.helper.oshelper.html
+++ b/modules/chipsec.helper.oshelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    oshelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.oshelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
     
-     
+     
   
       
 
@@ -46,10 +47,86 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    oshelper module
    
+  
    
+
    chipsec.helper.oshelper module
    
 
    Abstracts support for various OS/environments, wrapper around platform specific code that invokes kernel driver
    
-
    
+
    
+
    
+class OsHelper[source]
    
+
    Bases: object
    
+
    
+
    
+get_available_helpers() → List[str][source]
    
+
    
+
+
    
+
    
+get_base_helper()[source]
    
+
    
+
+
    
+
    
+get_default_helper()[source]
    
+
    
+
+
    
+
    
+get_helper(name: str) → Any[source]
    
+
    
+
+
    
+
    
+getcwd() → str[source]
    
+
    
+
+
    
+
    
+is_dal() → bool[source]
    
+
    
+
+
    
+
    
+is_efi() → bool[source]
    
+
    
+
+
    
+
    
+is_linux() → bool[source]
    
+
    
+
+
    
+
    
+is_macos() → bool[source]
    
+
    
+
+
    
+
    
+is_win8_or_greater() → bool[source]
    
+
    
+
+
    
+
    
+is_windows() → bool[source]
    
+
    
+
+
    
+
    
+load_helpers() → None[source]
    
+
    
+
+
    
+
+
    
+
    
+get_tools_path() → str[source]
    
+
    
+
+
    
+
    
+helper()[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,7 +180,7 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    nonehelper module
    
+                          title="previous chapter">chipsec.helper.nonehelper module
    
   
    
   
    
     
    Next topic
    
@@ -119,7 +196,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -137,17 +214,17 @@ 
    Navigation
    
           next |
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • oshelper module
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.oshelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.windows.html b/modules/chipsec.helper.windows.html
index 13476320..e12321b3 100644
--- a/modules/chipsec.helper.windows.html
+++ b/modules/chipsec.helper.windows.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    windows package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.windows package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,14 +47,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    windows package
    
+  
    
+
    chipsec.helper.windows package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -107,12 +114,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    linuxnativehelper module
    
+                          title="previous chapter">chipsec.helper.linuxnative.linuxnativehelper module
    
   
    
   
    
     
    Next topic
    
     
    windowshelper module
    
+                          title="next chapter">chipsec.helper.windows.windowshelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -138,20 +145,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-        
  • windows package
    •  
+          
  • chipsec.helper package »
    • 
+        
  • chipsec.helper.windows package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.helper.windows.windowshelper.html b/modules/chipsec.helper.windows.windowshelper.html
index 10366bcf..41fd42d0 100644
--- a/modules/chipsec.helper.windows.windowshelper.html
+++ b/modules/chipsec.helper.windows.windowshelper.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    windowshelper module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.helper.windows.windowshelper module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,9 +48,292 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    windowshelper module
    
-
    
+  
    
+
    chipsec.helper.windows.windowshelper module
    
+
    Management and communication with Windows kernel mode driver which provides access to hardware resources
    
+
    
+
    Note
    
+
    On Windows you need to install pywin32 Python extension corresponding to your Python version:
+http://sourceforge.net/projects/pywin32/
    
+
    
+
    
+
    
+CTL_CODE(DeviceType: int, Function: int, Method: int, Access: int) → int[source]
    
+
    
+
+
    
+
    
+class EFI_HDR_WIN(Size, DataOffset, DataSize, Attributes, guid)[source]
    
+
    Bases: chipsec.helper.windows.windowshelper.EFI_HDR_WIN
    
+
    
+
+
    
+
    
+class PCI_BDF[source]
    
+
    Bases: _ctypes.Structure
    
+
    
+
    
+BUS
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+DEV
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+FUNC
    
+
    Structure/Union member
    
+
    
+
+
    
+
    
+OFF
    
+
    Structure/Union member
    
+
    
+
+
    
+
+
    
+
    
+class WindowsHelper[source]
    
+
    Bases: chipsec.helper.basehelper.Helper
    
+
    
+
    
+EFI_supported() → bool[source]
    
+
    
+
+
    
+
    
+alloc_phys_mem(length: int, max_pa: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+check_driver_handle() → bool[source]
    
+
    
+
+
    
+
    
+cpuid(eax: int, ecx: int) → Tuple[int, int, int, int][source]
    
+
    
+
+
    
+
    
+create() → bool[source]
    
+
    
+
+
    
+
    
+delete() → bool[source]
    
+
    
+
+
    
+
    
+delete_EFI_variable(name: str, guid: str) → int[source]
    
+
    
+
+
    
+
    
+free_phys_mem(physical_address)[source]
    
+
    
+
+
    
+
    
+get_ACPI_SDT() → Tuple[Optional[_ctypes.Array], bool][source]
    
+
    
+
+
    
+
    
+get_ACPI_table(table_name)[source]
    
+
    
+
+
    
+
    
+get_EFI_variable(name: str, guid: str, attrs: Optional[int] = None) → Optional[bytes][source]
    
+
    
+
+
    
+
    
+get_EFI_variable_full(name: str, guid: str, attrs: Optional[int] = None) → Tuple[int, Optional[bytes], int][source]
    
+
    
+
+
    
+
    
+get_affinity() → Optional[int][source]
    
+
    
+
+
    
+
    
+get_descriptor_table(cpu_thread_id: int, desc_table_code: int) → Tuple[int, int, int][source]
    
+
    
+
+
    
+
    
+get_threads_count() → int[source]
    
+
    
+
+
    
+
    
+hypercall(rcx, rdx, r8, r9, r10, r11, rax, rbx, rdi, rsi, xmm_buffer)[source]
    
+
    
+
+
    
+
    
+list_EFI_variables(infcls: int = 2) → Optional[Dict[str, List[Tuple[int, bytes, int, bytes, str, int]]]][source]
    
+
    
+
+
    
+
    
+load_ucode_update(cpu_thread_id: int, ucode_update_buf: bytes) → bool[source]
    
+
    
+
+
    
+
    
+map_io_space(physical_address, length, cache_type)[source]
    
+
    
+
+
    
+
    
+msgbus_send_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+msgbus_send_read_message(mcr, mcrx)[source]
    
+
    
+
+
    
+
    
+msgbus_send_write_message(mcr, mcrx, mdr)[source]
    
+
    
+
+
    
+
    
+native_get_ACPI_table(table_name: str) → Optional[_ctypes.Array][source]
    
+
    
+
+
    
+
    
+read_cr(cpu_thread_id: int, cr_number: int) → int[source]
    
+
    
+
+
    
+
    
+read_io_port(io_port: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_mmio_reg(phys_address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_msr(cpu_thread_id: int, msr_addr: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+read_pci_reg(bus: int, device: int, function: int, address: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+read_phys_mem(phys_address: int, length: int) → bytes[source]
    
+
    
+
+
    
+
    
+retpoline_enabled() → bool[source]
    
+
    
+
+
    
+
    
+send_sw_smi(cpu_thread_id: int, SMI_code_data: int, _rax: int, _rbx: int, _rcx: int, _rdx: int, _rsi: int, _rdi: int) → Optional[Tuple[int, int, int, int, int, int, int]][source]
    
+
    
+
+
    
+
    
+set_EFI_variable(name: str, guid: str, buffer: bytes, buffer_size: Optional[int], attrs: Optional[int]) → int[source]
    
+
    
+
+
    
+
    
+set_affinity(value: int) → Optional[int][source]
    
+
    
+
+
    
+
    
+show_warning() → None[source]
    
+
    
+
+
    
+
    
+start() → bool[source]
    
+
    
+
+
    
+
    
+stop() → bool[source]
    
+
    
+
+
    
+
    
+va2pa(va: int) → Tuple[int, int][source]
    
+
    
+
+
    
+
    
+write_cr(cpu_thread_id: int, cr_number: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_io_port(io_port: int, value: int, size: int) → bool[source]
    
+
    
+
+
    
+
    
+write_mmio_reg(phys_address: int, size: int, value: int) → int[source]
    
+
    
+
+
    
+
    
+write_msr(cpu_thread_id: int, msr_addr: int, eax: int, edx: int) → int[source]
    
+
    
+
+
    
+
    
+write_pci_reg(bus: int, device: int, function: int, address: int, value: int, size: int) → int[source]
    
+
    
+
+
    
+
    
+write_phys_mem(phys_address: int, length: int, buf: AnyStr)[source]
    
+
    
+
+
    
+
+
    
+
    
+getEFIvariables_NtEnumerateSystemEnvironmentValuesEx2(nvram_buf: bytes) → Dict[str, List[Tuple[int, bytes, int, bytes, str, int]]][source]
    
+
    
+
+
    
+
    
+get_helper() → chipsec.helper.windows.windowshelper.WindowsHelper[source]
    
+
    
+
+
    
+
    
+packl_ctypes(lnum: int, bitlength: int) → bytes[source]
    
+
    
+
+
    
 
 
             
    
@@ -103,12 +387,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    windows package
    
+                          title="previous chapter">chipsec.helper.windows package
    
   
    
   
    
     
    Next topic
    
     
    basehelper module
    
+                          title="next chapter">chipsec.helper.basehelper module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,21 +418,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • OS Helpers and Drivers »
    • 
-          
  • helper package »
    • 
-          
  • windows package »
    • 
-        
  • windowshelper module
    •  
+          
  • chipsec.helper package »
    • 
+          
  • chipsec.helper.windows package »
    • 
+        
  • chipsec.helper.windows.windowshelper module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.architecture.html b/modules/chipsec.library.architecture.html
index ed331c98..4022c120 100644
--- a/modules/chipsec.library.architecture.html
+++ b/modules/chipsec.library.architecture.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    architecture module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.architecture module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • architecture module
    •  
+        
  • chipsec.library.architecture module
    •  
       
     
      
 
@@ -36,9 +37,25 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    architecture module
    
-
    
+  
    
+
    chipsec.library.architecture module
    
+
    
+
    
+class ARCH_VID[source]
    
+
    Bases: object
    
+
    
+
    
+AMD = 4130
    
+
    
+
+
    
+
    
+INTEL = 32902
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -98,7 +115,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +130,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • architecture module
    •  
+        
  • chipsec.library.architecture module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.bits.html b/modules/chipsec.library.bits.html
index c293301d..90af53a7 100644
--- a/modules/chipsec.library.bits.html
+++ b/modules/chipsec.library.bits.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    bits module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.bits module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • bits module
    •  
+        
  • chipsec.library.bits module
    •  
       
     
      
 
@@ -36,9 +37,39 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bits module
    
-
    
+  
    
+
    chipsec.library.bits module
    
+
    
+
    
+bit(bit_num: int) → int[source]
    
+
    
+
+
    
+
    
+get_bits(value: int, start: int, nbits: int) → int[source]
    
+
    
+
+
    
+
    
+is_all_ones(value: int, size: int, width: int = 8) → bool[source]
    
+
    
+
+
    
+
    
+is_set(val: int, bit_mask: int) → bool[source]
    
+
    
+
+
    
+
    
+ones_complement(value: int, number_of_bits: int = 64) → int[source]
    
+
    
+
+
    
+
    
+scan_single_bit_mask(bit_mask: int) → Optional[int][source]
    
+
    
+
+
    
 
 
             
    
@@ -98,7 +129,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +144,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • bits module
    •  
+        
  • chipsec.library.bits module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.html b/modules/chipsec.library.html
index 961e4774..eb212103 100644
--- a/modules/chipsec.library.html
+++ b/modules/chipsec.library.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    library package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • library package
    •  
+        
  • chipsec.library package
    •  
       
     
      
 
@@ -36,19 +37,25 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    library package
    
+  
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -108,7 +115,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -123,12 +130,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • library package
    •  
+        
  • chipsec.library package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.memory.html b/modules/chipsec.library.memory.html
index 10c9a317..bd77ac98 100644
--- a/modules/chipsec.library.memory.html
+++ b/modules/chipsec.library.memory.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    memory module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.memory module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • memory module
    •  
+        
  • chipsec.library.memory module
    •  
       
     
      
 
@@ -36,9 +37,9 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    memory module
    
-
    
+  
    
+
    chipsec.library.memory module
    
+
    
 
 
             
    
@@ -98,7 +99,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +114,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • memory module
    •  
+        
  • chipsec.library.memory module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.strings.html b/modules/chipsec.library.strings.html
index 012a7a3b..7c3b46eb 100644
--- a/modules/chipsec.library.strings.html
+++ b/modules/chipsec.library.strings.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    strings module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.strings module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • strings module
    •  
+        
  • chipsec.library.strings module
    •  
       
     
      
 
@@ -36,9 +37,34 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    strings module
    
-
    
+  
    
+
    chipsec.library.strings module
    
+
    
+
    
+bytestostring(mbytes: AnyStr) → str[source]
    
+
    
+
+
    
+
    
+get_datetime_str() → str[source]
    
+
    
+
+
    
+
    
+is_hex(maybe_hex: Iterable) → bool[source]
    
+
    
+
+
    
+
    
+is_printable(seq: AnyStr) → bool[source]
    
+
    
+
+
    
+
    
+stringtobytes(mstr: AnyStr) → bytes[source]
    
+
    
+
+
    
 
 
             
    
@@ -98,7 +124,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +139,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • strings module
    •  
+        
  • chipsec.library.strings module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.structs.html b/modules/chipsec.library.structs.html
index 5a74779d..11d58f84 100644
--- a/modules/chipsec.library.structs.html
+++ b/modules/chipsec.library.structs.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    structs module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.structs module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • structs module
    •  
+        
  • chipsec.library.structs module
    •  
       
     
      
 
@@ -36,9 +37,41 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    structs module
    
-
    
+  
    
+
    chipsec.library.structs module
    
+
    
+
    
+DB(val: int) → bytes[source]
    
+
    
+
+
    
+
    
+DD(val: int) → bytes[source]
    
+
    
+
+
    
+
    
+DQ(val: int) → bytes[source]
    
+
    
+
+
    
+
    
+DW(val: int) → bytes[source]
    
+
    
+
+
    
+
    
+pack1(value: int, size: int) → bytes[source]
    
+
    Shortcut to pack a single value into a string based on its size.
    
+
    
+
+
    
+
    
+unpack1(string: bytes, size: int) → int[source]
    
+
    Shortcut to unpack a single value from a string based on its size.
    
+
    
+
+
    
 
 
             
    
@@ -98,7 +131,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +146,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • structs module
    •  
+        
  • chipsec.library.structs module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.library.types.html b/modules/chipsec.library.types.html
index a8d31a04..46a6b6c8 100644
--- a/modules/chipsec.library.types.html
+++ b/modules/chipsec.library.types.html
@@ -1,19 +1,20 @@
+
 
 
-
+
   
     
-    
-
-    types module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.library.types module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
      
   
@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • types module
    •  
+        
  • chipsec.library.types module
    •  
       
     
      
 
@@ -36,9 +37,9 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    types module
    
-
    
+  
    
+
    chipsec.library.types module
    
+
    
 
 
             
    
@@ -98,7 +99,7 @@ 
    Quick search
    
     
     
    
 
    
-
+
         
    
       
    
       
    
@@ -113,12 +114,12 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
-        
  • types module
    •  
+        
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    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.bdw.html b/modules/chipsec.modules.bdw.html
index 3bce35fe..16ac3ae4 100644
--- a/modules/chipsec.modules.bdw.html
+++ b/modules/chipsec.modules.bdw.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    bdw package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.bdw package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,12 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bdw package
    
-
    
+  
    
+
    chipsec.modules.bdw package
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -102,12 +106,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    modules package
    
+                          title="previous chapter">chipsec.modules package
    
   
    
   
    
     
    Next topic
    
     
    byt package
    
+                          title="next chapter">chipsec.modules.byt package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +137,20 @@ 
    Navigation
    
           modules |
         
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-          previous |
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-          
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-        
  • bdw package
    •  
+          
  • chipsec.modules package »
    • 
+        
  • chipsec.modules.bdw package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.byt.html b/modules/chipsec.modules.byt.html
index d3f26d7d..32847aa0 100644
--- a/modules/chipsec.modules.byt.html
+++ b/modules/chipsec.modules.byt.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    byt package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.byt package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,9 +47,12 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    byt package
    
-
    
+  
    
+
    chipsec.modules.byt package
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -102,12 +106,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    bdw package
    
+                          title="previous chapter">chipsec.modules.bdw package
    
   
    
   
    
     
    Next topic
    
     
    common package
    
+                          title="next chapter">chipsec.modules.common package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -133,20 +137,20 @@ 
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-          
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-        
  • byt package
    •  
+          
  • chipsec.modules package »
    • 
+        
  • chipsec.modules.byt package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.bios_kbrd_buffer.html b/modules/chipsec.modules.common.bios_kbrd_buffer.html
index 3976de79..a284f01b 100644
--- a/modules/chipsec.modules.common.bios_kbrd_buffer.html
+++ b/modules/chipsec.modules.common.bios_kbrd_buffer.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    bios_kbrd_buffer module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.bios_kbrd_buffer module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bios_kbrd_buffer module
    
+  
    
+
    chipsec.modules.common.bios_kbrd_buffer module
    
 
    Checks for exposure of pre-boot passwords (BIOS/HDD/pre-bot authentication SW) in the BIOS keyboard buffer.
    
 
    
 
    Reference:
      
@@ -62,7 +63,32 @@ 
      Navigation
      
 
    
 
 
-
    
+
    
+
    
+class bios_kbrd_buffer[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_BIOS_keyboard_buffer() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -116,12 +142,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    s3bootscript module
    
+                          title="previous chapter">chipsec.modules.common.uefi.s3bootscript module
    
   
    
   
    
     
    Next topic
    
     
    bios_smi module
    
+                          title="next chapter">chipsec.modules.common.bios_smi module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -147,21 +173,21 @@ 
    Navigation
    
           modules |
         
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-          previous |
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-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • bios_kbrd_buffer module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.bios_kbrd_buffer module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.bios_smi.html b/modules/chipsec.modules.common.bios_smi.html
index 2caf05c4..13717af3 100644
--- a/modules/chipsec.modules.common.bios_smi.html
+++ b/modules/chipsec.modules.common.bios_smi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    bios_smi module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.bios_smi module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bios_smi module
    
+  
    
+
    chipsec.modules.common.bios_smi module
    
 
    The module checks that SMI events configuration is locked down
 - Global SMI Enable/SMI Lock
 - TCO SMI Enable/TCO Lock
    
@@ -72,7 +73,32 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class bios_smi[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_SMI_locks() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -126,12 +152,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    bios_kbrd_buffer module
    
+                          title="previous chapter">chipsec.modules.common.bios_kbrd_buffer module
    
   
    
   
    
     
    Next topic
    
     
    bios_ts module
    
+                          title="next chapter">chipsec.modules.common.bios_ts module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -157,21 +183,21 @@ 
    Navigation
    
           modules |
         
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-          previous |
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    • 
           
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • bios_smi module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.bios_smi module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.bios_ts.html b/modules/chipsec.modules.common.bios_ts.html
index 14213465..43f567d3 100644
--- a/modules/chipsec.modules.common.bios_ts.html
+++ b/modules/chipsec.modules.common.bios_ts.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    bios_ts module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.bios_ts module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bios_ts module
    
+  
    
+
    chipsec.modules.common.bios_ts module
    
 
    Checks for BIOS Interface Lock including Top Swap Mode
    
 
    
 
    References:
      
@@ -68,7 +69,32 @@ 
      Navigation
      
 
    
 
    
 
    
-
    
+
    
+
    
+class bios_ts[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_bios_iface_lock() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -122,12 +148,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    bios_smi module
    
+                          title="previous chapter">chipsec.modules.common.bios_smi module
    
   
    
   
    
     
    Next topic
    
     
    bios_wp module
    
+                          title="next chapter">chipsec.modules.common.bios_wp module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -153,21 +179,21 @@ 
    Navigation
    
           modules |
         
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-          next |
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • bios_ts module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.bios_ts module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.bios_wp.html b/modules/chipsec.modules.common.bios_wp.html
index 133d559d..b054f6a4 100644
--- a/modules/chipsec.modules.common.bios_wp.html
+++ b/modules/chipsec.modules.common.bios_wp.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    bios_wp module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.bios_wp module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    bios_wp module
    
+  
    
+
    chipsec.modules.common.bios_wp module
    
 
    The BIOS region in flash can be protected either using SMM-based protection or using configuration in the SPI controller. However, the SPI controller configuration is set once and locked, which would prevent writes later.
    
 
    This module checks both mechanisms. In order to pass this test using SPI controller configuration, the SPI Protected Range registers (PR0-4) will need to cover the entire BIOS region.
 Often, if this configuration is used at all, it is used only to protect part of the BIOS region (usually the boot block).
@@ -86,7 +87,37 @@ 
    Navigation
    
 
  • Module will fail if SMM-based protection is not correctly configured and SPI protected ranges (PR registers) do not protect the entire BIOS region.
    • 
 
 
    
-
    
+
    
+
    
+class bios_wp[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_BIOS_write_protection() → int[source]
    
+
    
+
+
    
+
    
+check_SPI_protected_ranges() → bool[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -140,12 +171,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    bios_ts module
    
+                          title="previous chapter">chipsec.modules.common.bios_ts module
    
   
    
   
    
     
    Next topic
    
     
    cet module
    
+                          title="next chapter">chipsec.modules.common.cet module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -171,21 +202,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
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-          previous |
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  • CHIPSEC  documentation »
    • 
           
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • bios_wp module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.bios_wp module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.cet.html b/modules/chipsec.modules.common.cet.html
index 98aad81c..d3cb76a5 100644
--- a/modules/chipsec.modules.common.cet.html
+++ b/modules/chipsec.modules.common.cet.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cet module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.cet module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cet module
    
+  
    
+
    chipsec.modules.common.cet module
    
 
    Reports CET Settings
    
 
    
 
    Usage:
    chipsec_main -m common.cet
    
@@ -66,7 +67,57 @@ 
    Navigation
    
 
  • Module is INFORMATION only and does NOT return a Pass/Fail
    • 
 
 
    
-
    
+
    
+
    
+class cet[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_cet()[source]
    
+
    
+
+
    
+
    
+get_cpuid_value() → None[source]
    
+
    
+
+
    
+
    
+is_supported()[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+print_cet_state(cet_msr)[source]
    
+
    
+
+
    
+
    
+run(module_argv)[source]
    
+
    
+
+
    
+
    
+setting_enabled(msr_val, field, mask, desc)[source]
    
+
    
+
+
    
+
    
+support_ibt() → bool[source]
    
+
    
+
+
    
+
    
+support_shadow() → bool[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -120,12 +171,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    bios_wp module
    
+                          title="previous chapter">chipsec.modules.common.bios_wp module
    
   
    
   
    
     
    Next topic
    
     
    debugenabled module
    
+                          title="next chapter">chipsec.modules.common.debugenabled module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -151,21 +202,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • cet module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.cet module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.cpu.cpu_info.html b/modules/chipsec.modules.common.cpu.cpu_info.html
index f4a3a711..ecfeb68a 100644
--- a/modules/chipsec.modules.common.cpu.cpu_info.html
+++ b/modules/chipsec.modules.common.cpu.cpu_info.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cpu_info module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.cpu.cpu_info module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cpu_info module
    
+  
    
+
    chipsec.modules.common.cpu.cpu_info module
    
 
    Displays CPU information
    
 
    
 
    Reference:
      
@@ -73,7 +74,27 @@ 
      Navigation
      
 
    
 
    
 
    
-
    
+
    
+
    
+class cpu_info[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -127,12 +148,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cpu package
    
+                          title="previous chapter">chipsec.modules.common.cpu package
    
   
    
   
    
     
    Next topic
    
     
    ia_untrusted module
    
+                          title="next chapter">chipsec.modules.common.cpu.ia_untrusted module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -158,22 +179,22 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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    • 
           
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-          
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    • 
-          
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    • 
-          
  • cpu package »
    • 
-        
  • cpu_info module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+          
  • chipsec.modules.common.cpu package »
    • 
+        
  • chipsec.modules.common.cpu.cpu_info module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.cpu.html b/modules/chipsec.modules.common.cpu.html
index 831efc3d..642e0a55 100644
--- a/modules/chipsec.modules.common.cpu.html
+++ b/modules/chipsec.modules.common.cpu.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    cpu package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.cpu package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,16 +48,22 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    cpu package
    
+  
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -110,12 +117,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    common package
    
+                          title="previous chapter">chipsec.modules.common package
    
   
    
   
    
     
    Next topic
    
     
    cpu_info module
    
+                          title="next chapter">chipsec.modules.common.cpu.cpu_info module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -141,21 +148,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
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    • 
           
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-          
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    • 
-          
  • common package »
    • 
-        
  • cpu package
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.cpu package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.cpu.ia_untrusted.html b/modules/chipsec.modules.common.cpu.ia_untrusted.html
index 74e15d1b..caad5445 100644
--- a/modules/chipsec.modules.common.cpu.ia_untrusted.html
+++ b/modules/chipsec.modules.common.cpu.ia_untrusted.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    ia_untrusted module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.cpu.ia_untrusted module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    ia_untrusted module
    
+  
    
+
    chipsec.modules.common.cpu.ia_untrusted module
    
 
    IA Untrusted checks
    
 
    
 
    Usage:
    chipsec_main -m common.cpu.ia_untrusted
    
@@ -64,7 +65,32 @@ 
    Navigation
    
 
 
    
 
    
-
    
+
    
+
    
+class ia_untrusted[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_untrusted() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -118,12 +144,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cpu_info module
    
+                          title="previous chapter">chipsec.modules.common.cpu.cpu_info module
    
   
    
   
    
     
    Next topic
    
     
    spectre_v2 module
    
+                          title="next chapter">chipsec.modules.common.cpu.spectre_v2 module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -149,22 +175,22 @@ 
    Navigation
    
           modules |
         
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-          
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    • 
-          
  • common package »
    • 
-          
  • cpu package »
    • 
-        
  • ia_untrusted module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+          
  • chipsec.modules.common.cpu package »
    • 
+        
  • chipsec.modules.common.cpu.ia_untrusted module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.cpu.spectre_v2.html b/modules/chipsec.modules.common.cpu.spectre_v2.html
index 46406cee..ebf12c6d 100644
--- a/modules/chipsec.modules.common.cpu.spectre_v2.html
+++ b/modules/chipsec.modules.common.cpu.spectre_v2.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spectre_v2 module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.cpu.spectre_v2 module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spectre_v2 module
    
+  
    
+
    chipsec.modules.common.cpu.spectre_v2 module
    
 
    The module checks if system includes hardware mitigations for Speculative Execution Side Channel.
 Specifically, it verifies that the system supports CPU mitigations for
 Branch Target Injection vulnerability a.k.a. Spectre Variant 2 (CVE-2017-5715)
    
@@ -131,7 +132,32 @@ 
    Navigation
    
 
  • Retpoline: a software construct for preventing branch-target-injection:
 https://support.google.com/faqs/answer/7625886
    • 
 
-
    
+
    
+
    
+class spectre_v2[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_spectre_mitigations() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -185,12 +211,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    ia_untrusted module
    
+                          title="previous chapter">chipsec.modules.common.cpu.ia_untrusted module
    
   
    
   
    
     
    Next topic
    
     
    secureboot package
    
+                          title="next chapter">chipsec.modules.common.secureboot package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -216,22 +242,22 @@ 
    Navigation
    
           modules |
         
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-          
  • modules package »
    • 
-          
  • common package »
    • 
-          
  • cpu package »
    • 
-        
  • spectre_v2 module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+          
  • chipsec.modules.common.cpu package »
    • 
+        
  • chipsec.modules.common.cpu.spectre_v2 module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.debugenabled.html b/modules/chipsec.modules.common.debugenabled.html
index 5390a97d..b01de007 100644
--- a/modules/chipsec.modules.common.debugenabled.html
+++ b/modules/chipsec.modules.common.debugenabled.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    debugenabled module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.debugenabled module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    debugenabled module
    
+  
    
+
    chipsec.modules.common.debugenabled module
    
 
    This module checks if the system has debug features turned on,
 specifically the Direct Connect Interface (DCI).
    
 
    This module checks the following bits:
@@ -76,7 +77,37 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class debugenabled[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_cpu_debug_enable() → int[source]
    
+
    
+
+
    
+
    
+check_dci() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -130,12 +161,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    cet module
    
+                          title="previous chapter">chipsec.modules.common.cet module
    
   
    
   
    
     
    Next topic
    
     
    ia32cfg module
    
+                          title="next chapter">chipsec.modules.common.ia32cfg module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -161,21 +192,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
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-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • debugenabled module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.debugenabled module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.html b/modules/chipsec.modules.common.html
index 16ccc4a1..0efded7d 100644
--- a/modules/chipsec.modules.common.html
+++ b/modules/chipsec.modules.common.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    common package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -46,54 +47,75 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    common package
    
+  
    
+
    chipsec.modules.common package
    
+
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -147,12 +169,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    byt package
    
+                          title="previous chapter">chipsec.modules.byt package
    
   
    
   
    
     
    Next topic
    
     
    cpu package
    
+                          title="next chapter">chipsec.modules.common.cpu package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -178,20 +200,20 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
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  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-        
  • common package
    •  
+          
  • chipsec.modules package »
    • 
+        
  • chipsec.modules.common package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.ia32cfg.html b/modules/chipsec.modules.common.ia32cfg.html
index 50ad56e9..d1f74ab4 100644
--- a/modules/chipsec.modules.common.ia32cfg.html
+++ b/modules/chipsec.modules.common.ia32cfg.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    ia32cfg module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.ia32cfg module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    ia32cfg module
    
+  
    
+
    chipsec.modules.common.ia32cfg module
    
 
    Tests that IA-32/IA-64 architectural features are configured and locked, including IA32 Model Specific Registers (MSRs)
    
 
    
 
    Reference:
      
@@ -73,7 +74,32 @@ 
      Navigation
      
 
    
 
    
 
    
-
    
+
    
+
    
+class ia32cfg[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_ia32feature_control() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -127,12 +153,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    debugenabled module
    
+                          title="previous chapter">chipsec.modules.common.debugenabled module
    
   
    
   
    
     
    Next topic
    
     
    me_mfg_mode module
    
+                          title="next chapter">chipsec.modules.common.me_mfg_mode module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -158,21 +184,21 @@ 
    Navigation
    
           modules |
         
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-          next |
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-          previous |
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  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • ia32cfg module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.ia32cfg module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.me_mfg_mode.html b/modules/chipsec.modules.common.me_mfg_mode.html
index a031b5b9..6575a0db 100644
--- a/modules/chipsec.modules.common.me_mfg_mode.html
+++ b/modules/chipsec.modules.common.me_mfg_mode.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    me_mfg_mode module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.me_mfg_mode module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    me_mfg_mode module
    
+  
    
+
    chipsec.modules.common.me_mfg_mode module
    
 
    This module checks that ME Manufacturing mode is not enabled.
    
 
    References:
    
 
    https://blog.ptsecurity.com/2018/10/intel-me-manufacturing-mode-macbook.html
    
@@ -115,7 +116,32 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class me_mfg_mode[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_me_mfg_mode() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -169,12 +195,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    ia32cfg module
    
+                          title="previous chapter">chipsec.modules.common.ia32cfg module
    
   
    
   
    
     
    Next topic
    
     
    memconfig module
    
+                          title="next chapter">chipsec.modules.common.memconfig module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -200,21 +226,21 @@ 
    Navigation
    
           modules |
         
  • 
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    • 
           
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • me_mfg_mode module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.me_mfg_mode module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.memconfig.html b/modules/chipsec.modules.common.memconfig.html
index e5bfa7cd..ccf1fa03 100644
--- a/modules/chipsec.modules.common.memconfig.html
+++ b/modules/chipsec.modules.common.memconfig.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    memconfig module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.memconfig module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    memconfig module
    
+  
    
+
    chipsec.modules.common.memconfig module
    
 
    This module verifies memory map secure configuration,
 that memory map registers are correctly configured and locked down.
    
 
    
@@ -65,7 +66,32 @@ 
    Navigation
    
 
  • This module will only run on Core (client) platforms.
    • 
 
 
    
-
    
+
    
+
    
+class memconfig[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_memmap_locks() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -119,12 +145,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    me_mfg_mode module
    
+                          title="previous chapter">chipsec.modules.common.me_mfg_mode module
    
   
    
   
    
     
    Next topic
    
     
    memlock module
    
+                          title="next chapter">chipsec.modules.common.memlock module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -150,21 +176,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
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-          previous |
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    • 
           
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • memconfig module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.memconfig module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.memlock.html b/modules/chipsec.modules.common.memlock.html
index a28c2ef9..4cbd8a41 100644
--- a/modules/chipsec.modules.common.memlock.html
+++ b/modules/chipsec.modules.common.memlock.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    memlock module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.memlock module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    memlock module
    
+  
    
+
    chipsec.modules.common.memlock module
    
 
    This module checks if memory configuration is locked to protect SMM
    
 
    
 
    Reference:
      
@@ -83,7 +84,32 @@ 
      Navigation
      
 
    • This module will not run on Atom based platforms.
      • 
 
    
 
    
-
    
+
    
+
    
+class memlock[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_MSR_LT_LOCK_MEMORY() → bool[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -137,12 +163,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    memconfig module
    
+                          title="previous chapter">chipsec.modules.common.memconfig module
    
   
    
   
    
     
    Next topic
    
     
    remap module
    
+                          title="next chapter">chipsec.modules.common.remap module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -168,21 +194,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • memlock module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.memlock module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.remap.html b/modules/chipsec.modules.common.remap.html
index 39af62e1..f251cd98 100644
--- a/modules/chipsec.modules.common.remap.html
+++ b/modules/chipsec.modules.common.remap.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    remap module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.remap module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    remap module
    
+  
    
+
    chipsec.modules.common.remap module
    
 
    Check Memory Remapping Configuration
    
 
    
 
    Reference:
      
@@ -76,7 +77,37 @@ 
      Navigation
      
 
    • This module will only run on Core platforms.
      • 
 
    
 
    
-
    
+
    
+
    
+class remap[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_remap_config() → int[source]
    
+
    
+
+
    
+
    
+is_ibecc_enabled() → bool[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(_) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -130,12 +161,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    memlock module
    
+                          title="previous chapter">chipsec.modules.common.memlock module
    
   
    
   
    
     
    Next topic
    
     
    rtclock module
    
+                          title="next chapter">chipsec.modules.common.rtclock module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -161,21 +192,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • remap module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.remap module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.rtclock.html b/modules/chipsec.modules.common.rtclock.html
index 0de3bb3a..dba98724 100644
--- a/modules/chipsec.modules.common.rtclock.html
+++ b/modules/chipsec.modules.common.rtclock.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    rtclock module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.rtclock module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,9 +48,9 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    rtclock module
    
-
    
+  
    
+
    chipsec.modules.common.rtclock module
    
+
    
 
 
             
    
@@ -103,12 +104,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    remap module
    
+                          title="previous chapter">chipsec.modules.common.remap module
    
   
    
   
    
     
    Next topic
    
     
    sgx_check module
    
+                          title="next chapter">chipsec.modules.common.sgx_check module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -134,21 +135,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • rtclock module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.rtclock module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.secureboot.html b/modules/chipsec.modules.common.secureboot.html
index 1c29c26e..84ab5d34 100644
--- a/modules/chipsec.modules.common.secureboot.html
+++ b/modules/chipsec.modules.common.secureboot.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    secureboot package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.secureboot package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,14 +48,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    secureboot package
    
+  
    
+
    chipsec.modules.common.secureboot package
    
+
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -108,12 +115,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spectre_v2 module
    
+                          title="previous chapter">chipsec.modules.common.cpu.spectre_v2 module
    
   
    
   
    
     
    Next topic
    
     
    variables module
    
+                          title="next chapter">chipsec.modules.common.secureboot.variables module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -139,21 +146,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • secureboot package
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.secureboot package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.secureboot.variables.html b/modules/chipsec.modules.common.secureboot.variables.html
index 9ae969e5..f420a75e 100644
--- a/modules/chipsec.modules.common.secureboot.variables.html
+++ b/modules/chipsec.modules.common.secureboot.variables.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    variables module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.secureboot.variables module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    variables module
    
+  
    
+
    chipsec.modules.common.secureboot.variables module
    
 
    Verify that all Secure Boot key UEFI variables are authenticated (BS+RT+AT)
 and protected from unauthorized modification.
    
 
    
@@ -76,7 +77,37 @@ 
    Navigation
    
 
  • Module is not supported in all environments.
    • 
 
 
    
-
    
+
    
+
    
+class variables[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+can_modify(name: str, guid: Optional[AnyStr], data: Optional[bytes]) → bool[source]
    
+
    
+
+
    
+
    
+check_secureboot_variable_attributes(do_modify: bool) → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -130,12 +161,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    secureboot package
    
+                          title="previous chapter">chipsec.modules.common.secureboot package
    
   
    
   
    
     
    Next topic
    
     
    uefi package
    
+                          title="next chapter">chipsec.modules.common.uefi package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -161,22 +192,22 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-          
  • secureboot package »
    • 
-        
  • variables module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+          
  • chipsec.modules.common.secureboot package »
    • 
+        
  • chipsec.modules.common.secureboot.variables module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.sgx_check.html b/modules/chipsec.modules.common.sgx_check.html
index cec2a93d..67a3107c 100644
--- a/modules/chipsec.modules.common.sgx_check.html
+++ b/modules/chipsec.modules.common.sgx_check.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    sgx_check module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.sgx_check module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    sgx_check module
    
+  
    
+
    chipsec.modules.common.sgx_check module
    
 
    Check SGX related configuration
    
 
    
 
    Reference:
      
@@ -92,7 +93,48 @@ 
      Navigation
      
 
    • Will not run within the EFI Shell
      • 
 
    
 
    
-
    
+
    
+
    
+class sgx_check[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+class PRMRR(logger, cs)[source]
    
+
    Bases: object
    
+
    
+
    
+reset_variables() → None[source]
    
+
    
+
+
    
+
+
    
+
    
+check_prmrr_values() → None[source]
    
+
    
+
+
    
+
    
+check_sgx_config() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(_) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -146,12 +188,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    rtclock module
    
+                          title="previous chapter">chipsec.modules.common.rtclock module
    
   
    
   
    
     
    Next topic
    
     
    smm module
    
+                          title="next chapter">chipsec.modules.common.smm module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -177,21 +219,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • sgx_check module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.sgx_check module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.smm.html b/modules/chipsec.modules.common.smm.html
index 6b793567..2cea3d63 100644
--- a/modules/chipsec.modules.common.smm.html
+++ b/modules/chipsec.modules.common.smm.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smm module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.smm module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smm module
    
+  
    
+
    chipsec.modules.common.smm module
    
 
    Compatible SMM memory (SMRAM) Protection check module
 This CHIPSEC module simply reads SMRAMC and checks that D_LCK is set.
    
 
    Reference:
@@ -63,7 +64,32 @@ 
    Navigation
    
 
 
 
    This module will only run on client (core) platforms that have PCI0.0.0_SMRAMC defined.
    
-
    
+
    
+
    
+class smm[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_SMRAMC() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -117,12 +143,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    sgx_check module
    
+                          title="previous chapter">chipsec.modules.common.sgx_check module
    
   
    
   
    
     
    Next topic
    
     
    smm_code_chk module
    
+                          title="next chapter">chipsec.modules.common.smm_code_chk module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -148,21 +174,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • smm module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.smm module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.smm_code_chk.html b/modules/chipsec.modules.common.smm_code_chk.html
index 9648bd19..dcc50eb2 100644
--- a/modules/chipsec.modules.common.smm_code_chk.html
+++ b/modules/chipsec.modules.common.smm_code_chk.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smm_code_chk module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.smm_code_chk module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smm_code_chk module
    
+  
    
+
    chipsec.modules.common.smm_code_chk module
    
 
    SMM_Code_Chk_En (SMM Call-Out) Protection check
    
 
    SMM_Code_Chk_En is a bit found in the MSR_SMM_FEATURE_CONTROL register.
 Once set to ‘1’, any CPU that attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE.
@@ -83,7 +84,32 @@ 
    Navigation
    
 
  • MSR_SMM_FEATURE_CONTROL may not be defined or readable on all platforms.
    • 
 
 
    
-
    
+
    
+
    
+class smm_code_chk[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_SMM_Code_Chk_En() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -137,12 +163,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smm module
    
+                          title="previous chapter">chipsec.modules.common.smm module
    
   
    
   
    
     
    Next topic
    
     
    smm_dma module
    
+                          title="next chapter">chipsec.modules.common.smm_dma module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -168,21 +194,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • smm_code_chk module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.smm_code_chk module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.smm_dma.html b/modules/chipsec.modules.common.smm_dma.html
index 37c06ef4..3540dd4e 100644
--- a/modules/chipsec.modules.common.smm_dma.html
+++ b/modules/chipsec.modules.common.smm_dma.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smm_dma module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.smm_dma module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smm_dma module
    
+  
    
+
    chipsec.modules.common.smm_dma module
    
 
    SMM TSEG Range Configuration Checks
    
 
    This module examines the configuration and locking of SMRAM range configuration protecting from DMA attacks.
 If it fails, then DMA protection may not be securely configured to protect SMRAM.
    
@@ -85,7 +86,37 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class smm_dma[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_tseg_config() → int[source]
    
+
    
+
+
    
+
    
+check_tseg_locks() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -139,12 +170,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smm_code_chk module
    
+                          title="previous chapter">chipsec.modules.common.smm_code_chk module
    
   
    
   
    
     
    Next topic
    
     
    smrr module
    
+                          title="next chapter">chipsec.modules.common.smrr module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -170,21 +201,21 @@ 
    Navigation
    
           modules |
         
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    • 
           
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    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • smm_dma module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.smm_dma module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.smrr.html b/modules/chipsec.modules.common.smrr.html
index 71dd38c8..71e61fad 100644
--- a/modules/chipsec.modules.common.smrr.html
+++ b/modules/chipsec.modules.common.smrr.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    smrr module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.smrr module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
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+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    smrr module
    
+  
    
+
    chipsec.modules.common.smrr module
    
 
    CPU SMM Cache Poisoning / System Management Range Registers check
    
 
    This module checks to see that SMRRs are enabled and configured.
    
 
    
@@ -78,7 +79,32 @@ 
    Navigation
    
 
 
 
    
-
    
+
    
+
    
+class smrr[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_SMRR(do_modify: bool) → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -132,12 +158,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smm_dma module
    
+                          title="previous chapter">chipsec.modules.common.smm_dma module
    
   
    
   
    
     
    Next topic
    
     
    spd_wd module
    
+                          title="next chapter">chipsec.modules.common.spd_wd module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -163,21 +189,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • smrr module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.smrr module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.spd_wd.html b/modules/chipsec.modules.common.spd_wd.html
index f974023c..c36797f5 100644
--- a/modules/chipsec.modules.common.spd_wd.html
+++ b/modules/chipsec.modules.common.spd_wd.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spd_wd module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.spd_wd module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spd_wd module
    
+  
    
+
    chipsec.modules.common.spd_wd module
    
 
    This module checks that SPD Write Disable bit in SMBus controller has been set
    
 
    
 
    References:
    Intel 8 Series/C220 Series Chipset Family Platform Controller Hub datasheet
@@ -87,7 +88,32 @@ 
    Navigation
    
 
    
 
    
 
    
-
    
+
    
+
    
+class spd_wd[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_spd_wd() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -141,12 +167,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    smrr module
    
+                          title="previous chapter">chipsec.modules.common.smrr module
    
   
    
   
    
     
    Next topic
    
     
    spi_access module
    
+                          title="next chapter">chipsec.modules.common.spi_access module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -172,21 +198,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • spd_wd module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.spd_wd module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.spi_access.html b/modules/chipsec.modules.common.spi_access.html
index 9996e67f..521df3c9 100644
--- a/modules/chipsec.modules.common.spi_access.html
+++ b/modules/chipsec.modules.common.spi_access.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_access module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.spi_access module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_access module
    
+  
    
+
    chipsec.modules.common.spi_access module
    
 
    SPI Flash Region Access Control
    
 
    Checks SPI Flash Region Access Permissions programmed in the Flash Descriptor
    
 
    
@@ -71,7 +72,32 @@ 
    Navigation
    
 Consider this when assessing results.
    
 
 
    
-
    
+
    
+
    
+class spi_access[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_flash_access_permissions() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -125,12 +151,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spd_wd module
    
+                          title="previous chapter">chipsec.modules.common.spd_wd module
    
   
    
   
    
     
    Next topic
    
     
    spi_desc module
    
+                          title="next chapter">chipsec.modules.common.spi_desc module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -156,21 +182,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • spi_access module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.spi_access module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.spi_desc.html b/modules/chipsec.modules.common.spi_desc.html
index 432c486a..08a81943 100644
--- a/modules/chipsec.modules.common.spi_desc.html
+++ b/modules/chipsec.modules.common.spi_desc.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_desc module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.spi_desc module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_desc module
    
+  
    
+
    chipsec.modules.common.spi_desc module
    
 
    The SPI Flash Descriptor indicates read/write permissions for devices to access regions of the flash memory. 
 This module simply reads the Flash Descriptor and checks that software cannot modify the Flash Descriptor itself. 
 If software can write to the Flash Descriptor, then software could bypass any protection defined by it. 
@@ -67,7 +68,32 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class spi_desc[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_flash_access_permissions() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -121,12 +147,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_access module
    
+                          title="previous chapter">chipsec.modules.common.spi_access module
    
   
    
   
    
     
    Next topic
    
     
    spi_fdopss module
    
+                          title="next chapter">chipsec.modules.common.spi_fdopss module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -152,21 +178,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • spi_desc module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.spi_desc module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.spi_fdopss.html b/modules/chipsec.modules.common.spi_fdopss.html
index 66802247..b8b7b105 100644
--- a/modules/chipsec.modules.common.spi_fdopss.html
+++ b/modules/chipsec.modules.common.spi_fdopss.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_fdopss module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.spi_fdopss module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_fdopss module
    
+  
    
+
    chipsec.modules.common.spi_fdopss module
    
 
    Checks for SPI Controller Flash Descriptor Security Override Pin Strap (FDOPSS). 
 On some systems, this may be routed to a jumper on the motherboard.
    
 
    
@@ -63,7 +64,32 @@ 
    Navigation
    
 
 
 
    
-
    
+
    
+
    
+class spi_fdopss[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_fd_security_override_strap() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -117,12 +143,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_desc module
    
+                          title="previous chapter">chipsec.modules.common.spi_desc module
    
   
    
   
    
     
    Next topic
    
     
    spi_lock module
    
+                          title="next chapter">chipsec.modules.common.spi_lock module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -148,21 +174,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • spi_fdopss module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.spi_fdopss module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.spi_lock.html b/modules/chipsec.modules.common.spi_lock.html
index 539d0206..7c52e152 100644
--- a/modules/chipsec.modules.common.spi_lock.html
+++ b/modules/chipsec.modules.common.spi_lock.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    spi_lock module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.spi_lock module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,8 +48,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    spi_lock module
    
+  
    
+
    chipsec.modules.common.spi_lock module
    
 
    The configuration of the SPI controller, including protected ranges (PR0-PR4), is locked by HSFS[FLOCKDN] until reset.
 If not locked, the controller configuration may be bypassed by reprogramming these registers.
    
 
    This vulnerability (not setting FLOCKDN) is also checked by other tools, including  flashrom
@@ -72,7 +73,32 @@ 
    Navigation
    
 
 
 
-
    
+
    
+
    
+class spi_lock[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_spi_lock() → int[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -126,12 +152,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    spi_fdopss module
    
+                          title="previous chapter">chipsec.modules.common.spi_fdopss module
    
   
    
   
    
     
    Next topic
    
     
    hsw package
    
+                          title="next chapter">chipsec.modules.hsw package
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -157,21 +183,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • spi_lock module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.spi_lock module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.uefi.access_uefispec.html b/modules/chipsec.modules.common.uefi.access_uefispec.html
index ae562208..077ca907 100644
--- a/modules/chipsec.modules.common.uefi.access_uefispec.html
+++ b/modules/chipsec.modules.common.uefi.access_uefispec.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    access_uefispec module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.uefi.access_uefispec module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    access_uefispec module
    
+  
    
+
    chipsec.modules.common.uefi.access_uefispec module
    
 
    Checks protection of UEFI variables defined in the UEFI spec to have certain permissions.
    
 
    Returns failure if variable attributes are not as defined in table 11 “Global Variables” of the UEFI spec.
    
 
    
@@ -70,7 +71,42 @@ 
    Navigation
    
 
    
 
    NOTE:
 Requires an OS with UEFI Runtime API support.
    
-
    
+
    
+
    
+class access_uefispec[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+can_modify(name: str, guid: str, data: bytes) → bool[source]
    
+
    
+
+
    
+
    
+check_vars(do_modify: bool) → int[source]
    
+
    
+
+
    
+
    
+diff_var(data1: int, data2: int) → bool[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -124,12 +160,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    uefi package
    
+                          title="previous chapter">chipsec.modules.common.uefi package
    
   
    
   
    
     
    Next topic
    
     
    s3bootscript module
    
+                          title="next chapter">chipsec.modules.common.uefi.s3bootscript module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -155,22 +191,22 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-          
  • uefi package »
    • 
-        
  • access_uefispec module
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+          
  • chipsec.modules.common.uefi package »
    • 
+        
  • chipsec.modules.common.uefi.access_uefispec module
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.uefi.html b/modules/chipsec.modules.common.uefi.html
index 6967f547..b67aa0df 100644
--- a/modules/chipsec.modules.common.uefi.html
+++ b/modules/chipsec.modules.common.uefi.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    uefi package — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.uefi package — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -47,15 +48,21 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    uefi package
    
+  
    
+
    
+
    
+
    Module contents
    
+
    
+
    
 
 
             
    
@@ -109,12 +116,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    variables module
    
+                          title="previous chapter">chipsec.modules.common.secureboot.variables module
    
   
    
   
    
     
    Next topic
    
     
    access_uefispec module
    
+                          title="next chapter">chipsec.modules.common.uefi.access_uefispec module
    
   
    
 
 
    
-
+
         
    
       
    
       
    
@@ -140,21 +147,21 @@ 
    Navigation
    
           modules |
         
  • 
-          next |
    • 
         
  • 
-          previous |
    • 
         
  • CHIPSEC  documentation »
    • 
           
  • CHIPSEC Modules »
    • 
-          
  • modules package »
    • 
-          
  • common package »
    • 
-        
  • uefi package
    •  
+          
  • chipsec.modules package »
    • 
+          
  • chipsec.modules.common package »
    • 
+        
  • chipsec.modules.common.uefi package
    •  
       
     
    
     
   
 
\ No newline at end of file
diff --git a/modules/chipsec.modules.common.uefi.s3bootscript.html b/modules/chipsec.modules.common.uefi.s3bootscript.html
index 8425c6ab..8f6e385a 100644
--- a/modules/chipsec.modules.common.uefi.s3bootscript.html
+++ b/modules/chipsec.modules.common.uefi.s3bootscript.html
@@ -1,23 +1,24 @@
+
 
 
-
+
   
     
-    
-
-    s3bootscript module — CHIPSEC  documentation
-    
-    
+    
+    chipsec.modules.common.uefi.s3bootscript module — CHIPSEC  documentation
+    
+    
     
-    
-    
-    
+    
+    
+    
+    
     
-    
+    
     
     
-    
-     
+    
+     
   
       
 
@@ -48,8 +49,8 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    s3bootscript module
    
+  
    
+
    chipsec.modules.common.uefi.s3bootscript module
    
 
    Checks protections of the S3 resume boot-script implemented by the UEFI based firmware
    
 
    References:
    
 
    VU#976132 UEFI implementations do not properly secure the EFI S3 Resume Boot Path boot script
    
@@ -77,7 +78,52 @@ 
    Navigation
    
 
    Note
    
 
    Requires an OS with UEFI Runtime API support.
    
 
    
-
    
+
    
+
    
+class s3bootscript[source]
    
+
    Bases: chipsec.module_common.BaseModule
    
+
    
+
    
+check_dispatch_opcodes(bootscript_entries: List[chipsec.hal.uefi_common.S3BOOTSCRIPT_ENTRY]) → bool[source]
    
+
    
+
+
    
+
    
+check_s3_bootscript(bootscript_pa: int) → int[source]
    
+
    
+
+
    
+
    
+check_s3_bootscripts(bsaddress=None) → int[source]
    
+
    
+
+
    
+
    
+is_inside_SMRAM(pa: int) → bool[source]
    
+
    
+
+
    
+
    
+is_inside_SPI(pa: int) → bool[source]
    
+
    
+
+
    
+
    
+is_supported() → bool[source]
    
+
    This method should be overwritten by the module returning True or False
+depending whether or not this module is supported in the currently running
+platform.
+To access the currently running platform use
    
+
    
+
+
    
+
    
+run(module_argv: List[str]) → int[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -131,12 +177,12 @@ 
    Table of Contents
    
   
    
     
    Previous topic
    
     
    access_uefispec module
    
+                          title="previous chapter">chipsec.modules.common.uefi.access_uefispec module
    
   
    
   
    
     
    Next topic
    
     
    bios_kbrd_buffer module
    
+                          title="next chapter">chipsec.modules.common.bios_kbrd_buffer module
    
   
    
 
 
    
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+
         
    
       
    
       
    
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+          
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+          
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--- a/modules/chipsec.modules.hsw.html
+++ b/modules/chipsec.modules.hsw.html
@@ -1,23 +1,24 @@
+
 
 
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+
   
     
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-    hsw package — CHIPSEC  documentation
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+
    
+
    
 
 
             
    
@@ -102,12 +106,12 @@ 
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    spi_lock module
    
+                          title="previous chapter">chipsec.modules.common.spi_lock module
    
   
    
   
    
     
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    ivb package
    
+                          title="next chapter">chipsec.modules.ivb package
    
   
    
 
 
    
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@@ -1,22 +1,23 @@
+
 
 
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+
    
+
    Subpackages
    
 
    
 
    
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+                          title="next chapter">chipsec.modules.bdw package
    
   
    
 
 
    
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+
 
 
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+                          title="previous chapter">chipsec.modules.hsw package
    
   
    
   
    
     
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+                          title="next chapter">chipsec.modules.snb package
    
   
    
 
 
    
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+
    
+
    
 
 
             
    
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+                          title="previous chapter">chipsec.modules.ivb package
    
   
    
   
    
     
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    tools package
    
+    
    Python Version
    
   
    
 
 
    
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-
    
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-Hash is truncated to 28 bits.
    
-
    
-
    Usage:
    chipsec_main -m common.tools.generate_test_id -a <test name>
    
-
    
-
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    >>> chipsec_main.py -m common.tools.generate_test_id -a remap
->>> chipsec_main.py -m common.tools.generate_test_id -a s3bootscript
->>> chipsec_main.py -m common.tools.generate_test_id -a bios_ts
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    SMI_code=<SMI code> or *
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-RAX=<value of RAX> or * or PTR or VAL
-RBX=<value of RBX> or * or PTR or VAL
-RCX=<value of RCX> or * or PTR or VAL
-RDX=<value of RDX> or * or PTR or VAL
-RSI=<value of RSI> or * or PTR or VAL
-RDI=<value of RDI> or * or PTR or VAL
-[PTR_OFFSET=<offset to pointer in the buffer>]
-[SIG=<signature>]
-[SIG_OFFSET=<offset to signature in the buffer>]
-[Name=<SMI name>]
-[Desc=<SMI description>]
-
    
-
    
-
    Where:
    
-
    
-
      
-
    • []: optional line
      • 
-
    • *: Don’t Care (the module will replace * with 0x0)
      • 
-
    • PTR: Physical address SMI handler will write to (the module will replace PTR with physical address provided as a command-line argument)
      • 
-
    • VAL: Value SMI handler will write to PTR address (the module will replace VAL with hardcoded _FILL_VALUE_xx)
      • 
-
    
-
    
-
    Examples:
    
-
    >>> chipsec_main.py -m tools.smm.smm_ptr
->>> chipsec_main.py -m tools.smm.smm_ptr -a fuzzmore,0x0:0xFF -l smm.log
-
    
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    reputation module
    
-
    This module checks current contents of UEFI firmware ROM or specified firmware image for bad EFI binaries as per the
-VirusTotal API. These can be EFI firmware volumes, EFI executable binaries (PEI modules, DXE drivers..) or EFI sections.
-The module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes
-or contents matching specified regular expressions.
    
-
    Important! This module can only detect bad or vulnerable EFI modules based on the file’s reputation on VT.
    
-
    
-
    Usage:
    
-
    chipsec_main.py -i -m tools.uefi.reputation -a <vt_api_key>[,<vt_threshold>,<fw_image>]
    
-
    vt_api_keyAPI key to VirusTotal. Can be obtained by visting https://www.virustotal.com/gui/join-us.
    This argument must be specified.
    
-
    
-
    vt_thresholdThe minimal number of different AV vendors on VT which must claim an EFI module is malicious
    before failing the test. Defaults to 10.
    
-
    
-
    fw_imageFull file path to UEFI firmware image
    If not specified, the module will dump firmware image directly from ROM
    
-
    
-
    
-
    
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      • 
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diff --git a/modules/chipsec.modules.tools.uefi.s3script_modify.html b/modules/chipsec.modules.tools.uefi.s3script_modify.html
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-
    This module will attempt to modify the S3 Boot Script on the platform. Doing this could cause the platform to malfunction. Use with care!
    
-
    
-
    Usage:
    Replacing existing opcode:
    
-
    chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,<reg_opcode>,<address>,<value>
-    <reg_opcode> = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw
-
-chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem[,<address>,<value>]
-
-chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch``
-
-chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep``
-
    
-
    
-
    Adding new opcode:
    
-
    chipsec_main.py -m tools.uefi.s3script_modify -a add_op,<reg_opcode>,<address>,<value>,<width>
-    <reg_opcode> = pci_wr|mmio_wr|io_wr
-
-chipsec_main.py -m tools.uefi.s3script_modify -a add_op,dispatch[,<entrypoint>]
-
    
-
    
-
    
-
    
-
    Examples:
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,<reg_opcode>,<address>,<value>
->>>   <reg_opcode> = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw
-
    
-
    
-
    The option will look for a script opcode that writes to PCI config, MMIO or I/O registers and modify the opcode to write the given value to the register with the given address.
    
-
    After executing this, if the system is vulnerable to boot script modification, the hardware configuration will have changed according to given <reg_opcode>.
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem
-
    
-
    
-
    The option will look for a script opcode that writes to memory and modify the opcode to write the given value to the given address.
    
-
    By default this test will allocate memory and write write 0xB007B007 that location.
    
-
    After executing this, if the system is vulnerable to boot script modification, you should find the given value in the allocated memory location.
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch
-
    
-
    
-
    The option will look for a dispatch opcode in the script and modify the opcode to point to a different entry point. The new entry point will contain a HLT instruction.
    
-
    After executing this, if the system is vulnerable to boot script modification, the system should hang on resume from S3.
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep
-
    
-
    
-
    The option will look for a dispatch opcode in the script and will modify memory at the entry point for that opcode. The modified instructions will contain a HLT instruction.
    
-
    After executing this, if the system is vulnerable to dispatch opcode entry point modification, the system should hang on resume from S3.
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a add_op,<reg_opcode>,<address>,<value>,<width>
->>>   <reg_opcode> = pci_wr|mmio_wr|io_wr
-
    
-
    
-
    The option will add a new opcode which writes to PCI config, MMIO or I/O registers with specified values.
    
-
    >>> chipsec_main.py -m tools.uefi.s3script_modify -a add_op,dispatch
-
    
-
    
-
    The option will add a new DISPATCH opcode to the script with entry point to either existing or newly allocated memory.
    
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    scan_blocked module
    
-
    This module checks current contents of UEFI firmware ROM or specified firmware image for blocked EFI binaries
-which can be EFI firmware volumes, EFI executable binaries (PEI modules, DXE drivers..) or EFI sections.
-The module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes
-or contents matching specified regular expressions.
    
-
    Important! This module can only detect what it knows about from its config file.
-If a bad or vulnerable binary is not detected then its ‘signature’ needs to be added to the config.
    
-
    
-
    Usage:
    
-
    chipsec_main.py -i -m tools.uefi.scan_blocked [-a <fw_image>,<blockedlist>]
      
-
    • fw_image      Full file path to UEFI firmware image. If not specified, the module will dump firmware image directly from ROM
      • 
-
    • blockedlist   JSON file with configuration of blocked EFI binaries (default = blockedlist.json). Config file should be located in the same directory as this module
      • 
-
    
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-
    
-
    Examples:
    
-
    >>> chipsec_main.py -m tools.uefi.scan_blocked
-
    
-
    
-
    Dumps UEFI firmware image from flash memory device, decodes it and checks for blocked EFI modules defined in the default config blockedlist.json
    
-
    >>> chipsec_main.py -i --no_driver -m tools.uefi.scan_blocked -a uefi.rom,blockedlist.json
-
    
-
    
-
    Decodes uefi.rom binary with UEFI firmware image and checks for blocked EFI modules defined in blockedlist.json config
    
-
    
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    Note
    
-
      
-
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-and no kernel driver is required when firmware image is specified
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    scan_image module
    
-
    The module can generate a list of EFI executables from (U)EFI firmware file or
-extracted from flash ROM, and then later check firmware image in flash ROM or
-file against this list of expected executables
    
-
    
-
    Usage:
    
-
    chipsec_main -m tools.uefi.scan_image [-a generate|check,<json>,<fw_image>]
      
-
    • 
-
      generate      Generates a list of EFI executable binaries from the UEFI
      firmware image (default)
      
-
      
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      check         Decodes UEFI firmware image and checks all EFI executable
      binaries against a specified list
      
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      json          JSON file with configuration of allowed list EFI
      executables (default = efilist.json)
      
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      fw_image      Full file path to UEFI firmware image. If not specified,
      the module will dump firmware image directly from ROM
      
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-
    Examples:
    
-
    >>> chipsec_main -m tools.uefi.scan_image
-
    
-
    
-
    Creates a list of EFI executable binaries in efilist.json from the firmware
-image extracted from ROM
    
-
    >>> chipsec_main -i -n -m tools.uefi.scan_image -a generate,efilist.json,uefi.rom
-
    
-
    
-
    Creates a list of EFI executable binaries in efilist.json from uefi.rom
-firmware binary
    
-
    >>> chipsec_main -i -n -m tools.uefi.scan_image -a check,efilist.json,uefi.rom
-
    
-
    
-
    Decodes uefi.rom UEFI firmware image binary and checks all EFI executables
-in it against a list defined in efilist.json
    
-
    
-
    Note
    
-
      
-
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-because the module doesn’t depend on the platform and doesn’t need kernel driver
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-
    The module is fuzzing UEFI Variable interface.
    
-
    The module is using UEFI SetVariable interface to write new UEFI variables
-to SPI flash NVRAM with randomized name/attributes/GUID/data/size.
    
-
    
-
    Usage:
    chipsec_main -m tools.uefi.uefivar_fuzz [-a <options>]
    
-
    
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-
    Options:
    
-
    
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    [-a <test>,<iterations>,<seed>,<test_case>]
    
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-
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      • 
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-
    
-
    
-
    Examples::
    >>> chipsec_main.py -m tools.uefi.uefivar_fuzz
->>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a all,100000
->>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a data,1000,123456789
->>> chipsec_main.py -m tools.uefi.uefivar_fuzz -a name,1,123456789,94
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-
    Simple CPUID VMM emulation fuzzer
    
-
    
-
    Usage:
    chipsec_main.py -i -m tools.vmm.cpuid_fuzz [-a random]
    
-
      
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      • 
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-
    
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    • []: optional line
      • 
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    Examples:
    >>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz
->>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz -l log.txt
->>> chipsec_main.py -i -m tools.vmm.cpuid_fuzz -a random
-
    
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    Additional options set within the module:
      
-
    • _NO_EAX_TO_FUZZ        : No of EAX values to fuzz within each step
      • 
-
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      • 
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    • _FUZZ_ECX_RANDOM       : Fuzz ECX with random values?
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    • _MAX_ECX               : Max ECX value
      • 
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    • _EXCLUDE_CPUID         : Exclude the following EAX values from fuzzing
      • 
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      • 
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    Usage:
    chipsec_main -m tools.vmm.ept_finder [-a dump,<file_name>|file,<file_name>,<revision_id>]
    
-
    
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      • 
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      • 
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      • 
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      • 
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-
    • []: optional line
      • 
-
    
-
    
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    Examples:
    >>> chipsec_main.py -i -m tools.vmm.ept_finder
->>> chipsec_main.py -i -m tools.vmm.ept_finder -a dump,my_file.bin
->>> chipsec_main.py -i -m tools.vmm.ept_finder -a file,my_file.bin,0x0
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->>> chipsec_main.py -i -m tools.vmm.pcie_fuzz -a 0 1f 0
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    PCIe device Memory-Mapped I/O (MMIO) ranges VMM emulation fuzzer
-which first overlaps MMIO BARs of all available PCIe devices
-then fuzzes them by writing garbage if corresponding option is enabled
    
-
    
-
    Usage:
    chipsec_main.py -i -m tools.vmm.pcie_overlap_fuzz
    
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    >>> chipsec_main.py -i -m tools.vmm.pcie_overlap_fuzz -l log.txt
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    Additional options set within the module:
      
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    • OVERLAP_MODE       : Set overlap direction
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    Oracle VirtualBox CVE-2015-0377 check
    
-
    
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-
    
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    Usage:
    chipsec_main.py -i -m tools.vmm.vbox_crash_apicbase
    
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    Examples:
    >>> chipsec_main.py -i -m tools.vmm.vbox_crash_apicbase
-
    
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    Registers used:
      
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    • IA32_APIC_BASE
      • 
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    venom module
    
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    QEMU VENOM vulnerability DoS PoC test
    
-
    
-
    Reference:
    
-
    
-
    Usage:
    chipsec_main.py -i -m tools.vmm.venom
    
-
    
-
    Examples:
    >>> chipsec_main.py -i -m tools.vmm.venom
-
    
-
    
-
    
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    Additional options set within the module:
      
-
    • ITER_COUNT         : Iteration count
      • 
-
    • FDC_PORT_DATA_FIFO : FDC DATA FIFO port
      • 
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      • 
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    hypercallfuzz module
    
-
    Xen hypercall fuzzer
    
-
    
-
    Usage:
    chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a <mode>[,<vector>,<iterations>]
    
-
      
-
    • mode                       : fuzzing mode
      
-
      
-
        
-
      • help                 : Prints this help
        • 
-
      • info                 : Hypervisor information
        • 
-
      • fuzzing              : Fuzzing specified hypercall
        • 
-
      • fuzzing-all          : Fuzzing all hypercalls
        • 
-
      • fuzzing-all-randomly : Fuzzing random hypercalls
        • 
-
      
-
      
-
      • 
-
    • <vector>                 : Code or name of a hypercall to be fuzzed (use info)
      • 
-
    • <iterations>             : Number of fuzzing iterations
      • 
-
    
-
    
-
    Examples:
    >>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing,10 -l log.txt
->>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing-all,50 -l log.txt
->>> chipsec_main.py -i -m tools.vmm.xen.hypercallfuzz -a fuzzing-all-randomly,10,0x10000000 -l log.txt
-
    
-
    
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      • 
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      • 
-
    
-
    
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    Important
    
-
      
-
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      • 
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      • 
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    xsa188 module
    
-
    This module triggers host crash on vulnerable Xen 4.4
    
-
    
-
    Reference:
    
-
    
-
    Usage:
    chipsec_main.py -m tools.vmm.xen.xsa188
    
-
    
-
    Examples:
    >>> chipsec_main.py -i -m tools.vmm.xen.xsa188
-
    
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-
      
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-
    The Windows SMM Security Mitigation Table (WSMT) is an ACPI table defined by Microsoft that allows
-system firmware to confirm to the operating system that certain security best practices have been
-implemented in System Management Mode (SMM) software.
    
-
    
-
    Reference:
    
-
    
-
    Usage:
    chipsec_main -m common.wsmt
    
-
    
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    Examples:
    >>> chipsec_main.py -m common.wsmt
-
    
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+
 
 
-
+
   
     
-    
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-    
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+    
+    chipsec.options module — CHIPSEC  documentation
+    
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@@ -27,7 +28,7 @@ 
    Navigation
    
           modules |
         
  • CHIPSEC  documentation »
    • 
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    •  
+        
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    •  
       
     
      
 
@@ -36,9 +37,20 @@ 
    Navigation
    
         
    
           
    
             
-  
    
-
    options module
    
-
    
+  
    
+
    chipsec.options module
    
+
    
+
    
+class Options[source]
    
+
    Bases: object
    
+
    
+
    
+get_section_data(section, key)[source]
    
+
    
+
+
    
+
+
    
 
 
             
    
@@ -98,7 +110,7 @@ 
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+
         
    
       
    
       
    
@@ -113,12 +125,12 @@ 
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           modules |
         
  • CHIPSEC  documentation »
    • 
-        
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+        
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    •
    \ No newline at end of file diff --git a/modules/chipsec.parsers.html b/modules/chipsec.parsers.html index 3515c963..0cbfbb4d 100644 --- a/modules/chipsec.parsers.html +++ b/modules/chipsec.parsers.html @@ -1,19 +1,20 @@ + - + - - - parsers module — CHIPSEC documentation - - + + chipsec.parsers module — CHIPSEC documentation + + - - - + + + + - + @@ -27,7 +28,7 @@

    Navigation

    modules |
  • CHIPSEC documentation »
    • -
  • parsers module
    • +
  • chipsec.parsers module
    • @@ -36,9 +37,102 @@

    Navigation

    -
    -

    parsers module

    -
    +
    +

    chipsec.parsers module

    +
    +
    +class BaseConfigHelper(cfg_obj)[source]
    +

    Bases: object

    +
    + +
    +
    +class BaseConfigParser(cfg_obj)[source]
    +

    Bases: object

    +
    +
    +def_handler(et_node, stage_data=None)[source]
    +
    + +
    +
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    +
    + +
    +
    +get_stage()[source]
    +
    + +
    +
    +startup()[source]
    +
    + +
    + +
    +
    +class Stage(value)[source]
    +

    Bases: enum.Enum

    +

    An enumeration.

    +
    +
    +CORE_SUPPORT = 30
    +
    + +
    +
    +CUST_SUPPORT = 40
    +
    + +
    +
    +DEVICE_CFG = 20
    +
    + +
    +
    +EXTRA = 50
    +
    + +
    +
    +GET_INFO = 10
    +
    + +
    +
    +NONE = 0
    +
    + +
    + +
    +
    +config_data
    +

    alias of chipsec.parsers.DevData

    +
    + +
    +
    +info_data
    +

    alias of chipsec.parsers.InfoData

    +
    + +
    +
    +stage_dev
    +

    alias of chipsec.parsers.StageCore

    +
    + +
    +
    +stage_info
    +

    alias of chipsec.parsers.StageInfo

    +
    + +
    @@ -98,7 +192,7 @@

    Quick search

    - +
    @@ -113,12 +207,12 @@

    Navigation

    modules |
  • CHIPSEC documentation »
    • -
  • parsers module
    • +
  • chipsec.parsers module
    • \ No newline at end of file diff --git a/modules/chipsec.testcase.html b/modules/chipsec.testcase.html deleted file mode 100644 index 6ef775a6..00000000 --- a/modules/chipsec.testcase.html +++ /dev/null @@ -1,124 +0,0 @@ - - - - - - - - testcase module — CHIPSEC documentation - - - - - - - - - - - - - -
    -
    -
    -
    - -
    -

    testcase module

    -
    - - -
    -
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    - - - - \ No newline at end of file diff --git a/modules/chipsec.utilcmd.acpi_cmd.html b/modules/chipsec.utilcmd.acpi_cmd.html index 88288ba3..de3a6c54 100644 --- a/modules/chipsec.utilcmd.acpi_cmd.html +++ b/modules/chipsec.utilcmd.acpi_cmd.html @@ -1,23 +1,24 @@ + - + - - - acpi_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.acpi_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    acpi_cmd module

    +
    +

    chipsec.utilcmd.acpi_cmd module

    Command-line utility providing access to ACPI tables

    >>> chipsec_util acpi list
 >>> chipsec_util acpi table <name>|<file_path>
@@ -59,7 +60,38 @@ 
    Navigation
    
 >>> chipsec_util acpi table acpi_table.bin
    -
    +
    +
    +class ACPICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +acpi_list() → None[source]
    +
    + +
    +
    +acpi_table() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    + +
    @@ -113,12 +145,12 @@

    Table of Contents

    Previous topic

    utilcmd package

    + title="previous chapter">chipsec.utilcmd package

    Next topic

    chipset_cmd module

    + title="next chapter">chipsec.utilcmd.chipset_cmd module

    - +
    @@ -144,20 +176,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
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  • utilcmd package »
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  • acpi_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.acpi_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.chipset_cmd.html b/modules/chipsec.utilcmd.chipset_cmd.html index 952ea750..c32c4655 100644 --- a/modules/chipsec.utilcmd.chipset_cmd.html +++ b/modules/chipsec.utilcmd.chipset_cmd.html @@ -1,23 +1,24 @@ + - + - - - chipset_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.chipset_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,15 +47,37 @@

    Navigation

    -
    -

    chipset_cmd module

    +
    +

    chipsec.utilcmd.chipset_cmd module

    usage as a standalone utility:
    >>> chipsec_util platform
    -
    +
    +
    +class PlatformCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +

    chipsec_util platform

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    + +
    @@ -108,12 +131,12 @@

    Table of Contents

    Previous topic

    acpi_cmd module

    + title="previous chapter">chipsec.utilcmd.acpi_cmd module

    Next topic

    cmos_cmd module

    + title="next chapter">chipsec.utilcmd.cmos_cmd module

    - +
    @@ -139,20 +162,20 @@

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  • - next |
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  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
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  • chipset_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.chipset_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.cmos_cmd.html b/modules/chipsec.utilcmd.cmos_cmd.html index de0130ca..4af49671 100644 --- a/modules/chipsec.utilcmd.cmos_cmd.html +++ b/modules/chipsec.utilcmd.cmos_cmd.html @@ -1,23 +1,24 @@ + - + - - - cmos_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.cmos_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    cmos_cmd module

    +
    +

    chipsec.utilcmd.cmos_cmd module

    >>> chipsec_util cmos dump
 >>> chipsec_util cmos readl|writel|readh|writeh <byte_offset> [byte_val]
    @@ -58,7 +59,53 @@

    Navigation

    >>> chipsec_util cmos writeh 0x0 0xCC
    -
    +
    +
    +class CMOSCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +cmos_dump() → None[source]
    +
    + +
    +
    +cmos_readh() → None[source]
    +
    + +
    +
    +cmos_readl() → None[source]
    +
    + +
    +
    +cmos_writeh() → None[source]
    +
    + +
    +
    +cmos_writel() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    + +
    @@ -112,12 +159,12 @@

    Table of Contents

    Previous topic

    chipset_cmd module

    + title="previous chapter">chipsec.utilcmd.chipset_cmd module

    Next topic

    config_cmd module

    + title="next chapter">chipsec.utilcmd.config_cmd module

    - +
    @@ -143,20 +190,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • cmos_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.cmos_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.config_cmd.html b/modules/chipsec.utilcmd.config_cmd.html index c2239de0..473e0c07 100644 --- a/modules/chipsec.utilcmd.config_cmd.html +++ b/modules/chipsec.utilcmd.config_cmd.html @@ -1,23 +1,24 @@ + - + - - - config_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.config_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    config_cmd module

    +
    +

    chipsec.utilcmd.config_cmd module

    >>> chipsec_util config show [config] <name>
    @@ -57,7 +58,68 @@

    Navigation

    >>> chipsec_util config show REGISTERS BC
    - +
    +
    +class CONFIGCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +bus_details(regi: str) → str[source]
    +
    + +
    +
    +control_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +io_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +lock_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +mem_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +mmio_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +pci_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +register_details(regi: Dict[str, Any]) → str[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +show() → None[source]
    +
    + +
    + +
    @@ -111,12 +173,12 @@

    Table of Contents

    Previous topic

    cmos_cmd module

    + title="previous chapter">chipsec.utilcmd.cmos_cmd module

    Next topic

    cpu_cmd module

    + title="next chapter">chipsec.utilcmd.cpu_cmd module

    - +
    @@ -142,20 +204,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • config_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.config_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.cpu_cmd.html b/modules/chipsec.utilcmd.cpu_cmd.html index 31656b05..59955e46 100644 --- a/modules/chipsec.utilcmd.cpu_cmd.html +++ b/modules/chipsec.utilcmd.cpu_cmd.html @@ -1,23 +1,24 @@ + - + - - - cpu_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.cpu_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    cpu_cmd module

    +
    +

    chipsec.utilcmd.cpu_cmd module

    >>> chipsec_util cpu info
 >>> chipsec_util cpu cr <thread> <cr_number> [value]
 >>> chipsec_util cpu cpuid <eax> [ecx]
@@ -64,7 +65,48 @@ 
    Navigation
    
 >>> chipsec_util cpu topology
    -
    +
    +
    +class CPUCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +cpu_cpuid() → None[source]
    +
    + +
    +
    +cpu_cr() → Optional[Union[bool, int]][source]
    +
    + +
    +
    +cpu_info() → None[source]
    +
    + +
    +
    +cpu_pt() → None[source]
    +
    + +
    +
    +cpu_topology() → Dict[str, Dict[int, List[int]]][source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    + +
    @@ -118,12 +160,12 @@

    Table of Contents

    Previous topic

    config_cmd module

    + title="previous chapter">chipsec.utilcmd.config_cmd module

    Next topic

    decode_cmd module

    + title="next chapter">chipsec.utilcmd.decode_cmd module

    - +
    @@ -149,20 +191,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • cpu_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.cpu_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.decode_cmd.html b/modules/chipsec.utilcmd.decode_cmd.html index 2beccd65..b6747db5 100644 --- a/modules/chipsec.utilcmd.decode_cmd.html +++ b/modules/chipsec.utilcmd.decode_cmd.html @@ -1,23 +1,24 @@ + - + - - - decode_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.decode_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    decode_cmd module

    +
    +

    chipsec.utilcmd.decode_cmd module

    CHIPSEC can parse an image file containing data from the SPI flash (such as the result of chipsec_util spi dump). This can be critical in forensic analysis.

    This will create multiple log files, binaries, and directories that correspond to the sections, firmware volumes, files, variables, etc. stored in the SPI flash.

    Usage:

    @@ -70,7 +71,33 @@

    Navigation

    If the nvram directory does not appear and the list of nvram variables is empty, try again with another type.

    -
    +
    +
    +class DecodeCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +decode_rom() → bool[source]
    +
    + +
    +
    +decode_types() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    + +
    @@ -124,12 +151,12 @@

    Table of Contents

    Previous topic

    cpu_cmd module

    + title="previous chapter">chipsec.utilcmd.cpu_cmd module

    Next topic

    deltas_cmd module

    + title="next chapter">chipsec.utilcmd.deltas_cmd module

    - +
    @@ -155,20 +182,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • decode_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.decode_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.deltas_cmd.html b/modules/chipsec.utilcmd.deltas_cmd.html index 2fa16d4c..f954e0c2 100644 --- a/modules/chipsec.utilcmd.deltas_cmd.html +++ b/modules/chipsec.utilcmd.deltas_cmd.html @@ -1,23 +1,24 @@ + - + - - - deltas_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.deltas_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    deltas_cmd module

    +
    +

    chipsec.utilcmd.deltas_cmd module

    >>> chipsec_util deltas <previous> <current> [out-format] [out-name]
    @@ -55,7 +56,28 @@

    Navigation

    out-name - Output file name

    Example: >>> chipsec_util deltas run1.json run2.json

    -
    +
    +
    +class DeltasCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    @@ -109,12 +131,12 @@

    Table of Contents

    Previous topic

    decode_cmd module

    + title="previous chapter">chipsec.utilcmd.decode_cmd module

    Next topic

    desc_cmd module

    + title="next chapter">chipsec.utilcmd.desc_cmd module

    - +
    @@ -140,20 +162,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • deltas_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.deltas_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.desc_cmd.html b/modules/chipsec.utilcmd.desc_cmd.html index e6334206..f736e740 100644 --- a/modules/chipsec.utilcmd.desc_cmd.html +++ b/modules/chipsec.utilcmd.desc_cmd.html @@ -1,23 +1,24 @@ + - + - - - desc_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.desc_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    desc_cmd module

    +
    +

    chipsec.utilcmd.desc_cmd module

    The idt, gdt and ldt commands print the IDT, GDT and LDT, respectively.

    IDT command:

    >>> chipsec_util idt [cpu_id]
@@ -76,7 +77,94 @@ 
    Navigation
    
 >>> chipsec_util ldt
    -
    +
    +
    +class GDTCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    >>> chipsec_util gdt [cpu_id]
+
    +
    +

    Examples:

    +
    >>> chipsec_util gdt 0
+>>> chipsec_util gdt
+
    +
    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    +
    +class IDTCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    >>> chipsec_util idt [cpu_id]
+
    +
    +

    Examples:

    +
    >>> chipsec_util idt 0
+>>> chipsec_util idt
+
    +
    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    +
    +class LDTCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    >>> chipsec_util ldt [cpu_id]
+
    +
    +

    Examples:

    +
    >>> chipsec_util ldt 0
+>>> chipsec_util ldt
+
    +
    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    @@ -130,12 +218,12 @@

    Table of Contents

    Previous topic

    deltas_cmd module

    + title="previous chapter">chipsec.utilcmd.deltas_cmd module

    Next topic

    ec_cmd module

    + title="next chapter">chipsec.utilcmd.ec_cmd module

    - +
    @@ -161,20 +249,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • desc_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.desc_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.ec_cmd.html b/modules/chipsec.utilcmd.ec_cmd.html index 444d8214..eb749648 100644 --- a/modules/chipsec.utilcmd.ec_cmd.html +++ b/modules/chipsec.utilcmd.ec_cmd.html @@ -1,23 +1,24 @@ + - + - - - ec_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.ec_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    ec_cmd module

    +
    +

    chipsec.utilcmd.ec_cmd module

    >>> chipsec_util ec dump    [<size>]
 >>> chipsec_util ec command <command>
 >>> chipsec_util ec read    <offset> [<size>]
@@ -63,7 +64,53 @@ 
    Navigation
    
 >>> chipsec_util ec index
    -
    +
    +
    +class ECCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +command() → None[source]
    +
    + +
    +
    +dump() → None[source]
    +
    + +
    +
    +index() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +read() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +write() → None[source]
    +
    + +
    + +
    @@ -117,12 +164,12 @@

    Table of Contents

    Previous topic

    desc_cmd module

    + title="previous chapter">chipsec.utilcmd.desc_cmd module

    Next topic

    igd_cmd module

    + title="next chapter">chipsec.utilcmd.igd_cmd module

    - +
    @@ -148,20 +195,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • ec_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.ec_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.html b/modules/chipsec.utilcmd.html index c2929a57..8fa3ce2a 100644 --- a/modules/chipsec.utilcmd.html +++ b/modules/chipsec.utilcmd.html @@ -1,22 +1,23 @@ + - + - - - utilcmd package — CHIPSEC documentation - - + + chipsec.utilcmd package — CHIPSEC documentation + + - - - + + + + - + - + @@ -45,46 +46,52 @@

    Navigation

    -
    -

    utilcmd package

    +
    +

    chipsec.utilcmd package

    +
    +

    Submodules

    -
    +
    +
    +

    Module contents

    +
    +
    @@ -143,7 +150,7 @@

    Previous topic

    Next topic

    acpi_cmd module

    + title="next chapter">chipsec.utilcmd.acpi_cmd module

    - +
    @@ -169,19 +176,19 @@

    Navigation

    modules |
  • - next |
  • previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package
    • +
  • chipsec.utilcmd package
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.igd_cmd.html b/modules/chipsec.utilcmd.igd_cmd.html index b32eecd4..4c6c834a 100644 --- a/modules/chipsec.utilcmd.igd_cmd.html +++ b/modules/chipsec.utilcmd.igd_cmd.html @@ -1,23 +1,24 @@ + - + - - - igd_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.igd_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    igd_cmd module

    +
    +

    chipsec.utilcmd.igd_cmd module

    The igd command allows memory read/write operations using igd dma.

    >>> chipsec_util igd
 >>> chipsec_util igd dmaread <address> [width] [file_name]
@@ -59,7 +60,38 @@ 
    Navigation
    
 >>> chipsec_util igd dmawrite 0x2217F1000 0x4 deadbeef
    -
    +
    +
    +class IgdCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +read_dma() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    +
    +write_dma() → None[source]
    +
    + +
    + +
    @@ -113,12 +145,12 @@

    Table of Contents

    Previous topic

    ec_cmd module

    + title="previous chapter">chipsec.utilcmd.ec_cmd module

    Next topic

    interrupts_cmd module

    + title="next chapter">chipsec.utilcmd.interrupts_cmd module

    - +
    @@ -144,20 +176,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • igd_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.igd_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.interrupts_cmd.html b/modules/chipsec.utilcmd.interrupts_cmd.html index 8ea0f3a3..cfd0559c 100644 --- a/modules/chipsec.utilcmd.interrupts_cmd.html +++ b/modules/chipsec.utilcmd.interrupts_cmd.html @@ -1,23 +1,24 @@ + - + - - - interrupts_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.interrupts_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    interrupts_cmd module

    +
    +

    chipsec.utilcmd.interrupts_cmd module

    SMI command:

    >>> chipsec_util smi count
 >>> chipsec_util smi send <thread_id> <SMI_code> <SMI_data> [RAX] [RBX] [RCX] [RDX] [RSI] [RDI]
@@ -69,7 +70,83 @@ 
    Navigation
    
 
    >>> chipsec_util nmi
 
    
 
    
-
    +
    +
    +class NMICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    >>> chipsec_util nmi
+
    +
    +

    Examples:

    +
    >>> chipsec_util nmi
+
    +
    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    +
    +class SMICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    >>> chipsec_util smi count
+>>> chipsec_util smi send <thread_id> <SMI_code> <SMI_data> [RAX] [RBX] [RCX] [RDX] [RSI] [RDI]
+>>> chipsec_util smi smmc <RT_code_start> <RT_code_end> <GUID> <payload_loc> <payload_file|payload_string> [port]
+
    +
    +

    Examples:

    +
    >>> chipsec_util smi count
+>>> chipsec_util smi send 0x0 0xDE 0x0
+>>> chipsec_util smi send 0x0 0xDE 0x0 0xAAAAAAAAAAAAAAAA ..
+>>> chipsec_util smi smmc 0x79dfe000 0x79efdfff ed32d533-99e6-4209-9cc02d72cdd998a7 0x79dfaaaa payload.bin
+
    +
    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    +
    +smi_count() → None[source]
    +
    + +
    +
    +smi_send() → None[source]
    +
    + +
    +
    +smi_smmc() → None[source]
    +
    + +
    + +
    @@ -123,12 +200,12 @@

    Table of Contents

    Previous topic

    igd_cmd module

    + title="previous chapter">chipsec.utilcmd.igd_cmd module

    Next topic

    io_cmd module

    + title="next chapter">chipsec.utilcmd.io_cmd module

    - +
    @@ -154,20 +231,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • interrupts_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.interrupts_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.io_cmd.html b/modules/chipsec.utilcmd.io_cmd.html index 5142f8cc..9cc1b476 100644 --- a/modules/chipsec.utilcmd.io_cmd.html +++ b/modules/chipsec.utilcmd.io_cmd.html @@ -1,23 +1,24 @@ + - + - - - io_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.io_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    io_cmd module

    +
    +

    chipsec.utilcmd.io_cmd module

    The io command allows direct access to read and write I/O port space.

    >>> chipsec_util io list
 >>> chipsec_util io read  <io_port> <width>
@@ -60,7 +61,43 @@ 
    Navigation
    
 >>> chipsec_util io write 0x430 1 0x0
    -
    +
    +
    +class PortIOCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +io_list() → None[source]
    +
    + +
    +
    +io_read() → None[source]
    +
    + +
    +
    +io_write() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    + +
    @@ -114,12 +151,12 @@

    Table of Contents

    Previous topic

    interrupts_cmd module

    + title="previous chapter">chipsec.utilcmd.interrupts_cmd module

    Next topic

    iommu_cmd module

    + title="next chapter">chipsec.utilcmd.iommu_cmd module

    - +
    @@ -145,20 +182,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • io_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.io_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.iommu_cmd.html b/modules/chipsec.utilcmd.iommu_cmd.html index 7ef5a8b5..e1edb460 100644 --- a/modules/chipsec.utilcmd.iommu_cmd.html +++ b/modules/chipsec.utilcmd.iommu_cmd.html @@ -1,23 +1,24 @@ + - + - - - iommu_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.iommu_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    iommu_cmd module

    +
    +

    chipsec.utilcmd.iommu_cmd module

    Command-line utility providing access to IOMMU engines

    >>> chipsec_util iommu list
 >>> chipsec_util iommu config [iommu_engine]
@@ -64,7 +65,63 @@ 
    Navigation
    
 >>> chipsec_util iommu pt
    -
    +
    +
    +class IOMMUCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +iommu_config() → None[source]
    +
    + +
    +
    +iommu_disable() → None[source]
    +
    + +
    +
    +iommu_enable() → None[source]
    +
    + +
    +
    +iommu_engine(cmd) → None[source]
    +
    + +
    +
    +iommu_list() → None[source]
    +
    + +
    +
    +iommu_pt() → None[source]
    +
    + +
    +
    +iommu_status() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    @@ -118,12 +175,12 @@

    Table of Contents

    Previous topic

    io_cmd module

    + title="previous chapter">chipsec.utilcmd.io_cmd module

    Next topic

    lock_check_cmd module

    + title="next chapter">chipsec.utilcmd.lock_check_cmd module

    - +
    @@ -149,20 +206,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • iommu_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.iommu_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.lock_check_cmd.html b/modules/chipsec.utilcmd.lock_check_cmd.html index 50b972fa..d8b93a55 100644 --- a/modules/chipsec.utilcmd.lock_check_cmd.html +++ b/modules/chipsec.utilcmd.lock_check_cmd.html @@ -1,23 +1,24 @@ + - + - - - lock_check_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.lock_check_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    lock_check_cmd module

    +
    +

    chipsec.utilcmd.lock_check_cmd module

    >>> chipsec_util check list
 >>> chipsec_util check lock <lockname>
 >>> chipsec_util check lock <lockname1, lockname2, ...>
@@ -73,7 +74,68 @@ 
    Navigation
    -
    +
    +
    +class LOCKCHECKCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +check_lock() → None[source]
    +
    + +
    +
    +check_log(lock: str, is_locked: int) → str[source]
    +
    + +
    +
    +checkall_locks() → None[source]
    +
    + +
    +
    +list_locks() → None[source]
    +
    + +
    +
    +log_header() → str[source]
    +
    + +
    +
    +log_key() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +tear_down() → None[source]
    +
    + +
    +
    +version = '0.5'
    +
    + +
    + +
    @@ -127,12 +189,12 @@

    Table of Contents

    Previous topic

    iommu_cmd module

    + title="previous chapter">chipsec.utilcmd.iommu_cmd module

    Next topic

    mem_cmd module

    + title="next chapter">chipsec.utilcmd.mem_cmd module

    - +
    @@ -158,20 +220,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • lock_check_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.lock_check_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.mem_cmd.html b/modules/chipsec.utilcmd.mem_cmd.html index 2182a9c4..6c673408 100644 --- a/modules/chipsec.utilcmd.mem_cmd.html +++ b/modules/chipsec.utilcmd.mem_cmd.html @@ -1,23 +1,24 @@ + - + - - - mem_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.mem_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    mem_cmd module

    +
    +

    chipsec.utilcmd.mem_cmd module

    The mem command provides direct access to read and write physical memory.

    >>> chipsec_util mem <op> <physical_address> <length> [value|buffer_file]
 >>> <physical_address> : 64-bit physical address
@@ -69,7 +70,63 @@ 
    Navigation
    
 >>> chipsec_util mem search   0xF0000            0x10000  _SM_
    -
    +
    +
    +class MemCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +dump_region_to_path(path: str, pa_start: int, pa_end: int) → None[source]
    +
    + +
    +
    +mem_allocate() → None[source]
    +
    + +
    +
    +mem_pagedump() → None[source]
    +
    + +
    +
    +mem_read() → None[source]
    +
    + +
    +
    +mem_readval() → None[source]
    +
    + +
    + +
    + +
    +
    +mem_write() → None[source]
    +
    + +
    +
    +mem_writeval() → None[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    + +
    @@ -123,12 +180,12 @@

    Table of Contents

    Previous topic

    lock_check_cmd module

    + title="previous chapter">chipsec.utilcmd.lock_check_cmd module

    Next topic

    mmcfg_base_cmd module

    + title="next chapter">chipsec.utilcmd.mmcfg_base_cmd module

    - +
    @@ -154,20 +211,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • mem_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.mem_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.mmcfg_base_cmd.html b/modules/chipsec.utilcmd.mmcfg_base_cmd.html index ef814552..01d4010a 100644 --- a/modules/chipsec.utilcmd.mmcfg_base_cmd.html +++ b/modules/chipsec.utilcmd.mmcfg_base_cmd.html @@ -1,23 +1,24 @@ + - + - - - mmcfg_base_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.mmcfg_base_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    mmcfg_base_cmd module

    +
    +

    chipsec.utilcmd.mmcfg_base_cmd module

    The mmcfg_base command displays PCIe MMCFG Base/Size.

    Usage:

    >>> chipsec_util mmcfg_base
@@ -57,7 +58,28 @@ 
    Navigation
    
 
    >>> chipsec_util mmcfg_base
 
    
 
    
-
    +
    +
    +class MMCfgBaseCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run() → None[source]
    +
    + +
    + +
    @@ -111,12 +133,12 @@

    Table of Contents

    Previous topic

    mem_cmd module

    + title="previous chapter">chipsec.utilcmd.mem_cmd module

    Next topic

    mmcfg_cmd module

    + title="next chapter">chipsec.utilcmd.mmcfg_cmd module

    - +
    @@ -142,20 +164,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • mmcfg_base_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.mmcfg_base_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.mmcfg_cmd.html b/modules/chipsec.utilcmd.mmcfg_cmd.html index e77a1b2d..de22b44b 100644 --- a/modules/chipsec.utilcmd.mmcfg_cmd.html +++ b/modules/chipsec.utilcmd.mmcfg_cmd.html @@ -1,23 +1,24 @@ + - + - - - mmcfg_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.mmcfg_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    mmcfg_cmd module

    +
    +

    chipsec.utilcmd.mmcfg_cmd module

    The mmcfg command allows direct access to memory mapped config space.

    >>> chipsec_util mmcfg base
 >>> chipsec_util mmcfg read <bus> <device> <function> <offset> <width>
@@ -62,7 +63,43 @@ 
    Navigation
    
 >>> chipsec_util mmcfg ec
    -
    +
    +
    +class MMCfgCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +base()[source]
    +
    + +
    +
    +ec()[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +read()[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +write()[source]
    +
    + +
    + +
    @@ -116,12 +153,12 @@

    Table of Contents

    Previous topic

    mmcfg_base_cmd module

    + title="previous chapter">chipsec.utilcmd.mmcfg_base_cmd module

    Next topic

    mmio_cmd module

    + title="next chapter">chipsec.utilcmd.mmio_cmd module

    - +
    @@ -147,20 +184,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • mmcfg_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.mmcfg_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.mmio_cmd.html b/modules/chipsec.utilcmd.mmio_cmd.html index ac2b4a02..5a567e10 100644 --- a/modules/chipsec.utilcmd.mmio_cmd.html +++ b/modules/chipsec.utilcmd.mmio_cmd.html @@ -1,23 +1,24 @@ + - + - - - mmio_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.mmio_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    mmio_cmd module

    +
    +

    chipsec.utilcmd.mmio_cmd module

    >>> chipsec_util mmio list
 >>> chipsec_util mmio dump <MMIO_BAR_name> [offset] [length]
 >>> chipsec_util mmio dump-abs <MMIO_base_address> [offset] [length]
@@ -67,7 +68,63 @@ 
    Navigation
    
 >>> chipsec_util mmio write-abs 0xFE010000 0x74 0x04 0xFFFF0000
    -
    +
    +
    +class MMIOCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +dump_bar()[source]
    +
    + +
    +
    +dump_bar_abs()[source]
    +
    + +
    +
    +list_bars()[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +read_abs()[source]
    +
    + +
    +
    +read_bar()[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +write_abs()[source]
    +
    + +
    +
    +write_bar()[source]
    +
    + +
    + +
    @@ -121,12 +178,12 @@

    Table of Contents

    Previous topic

    mmcfg_cmd module

    + title="previous chapter">chipsec.utilcmd.mmcfg_cmd module

    Next topic

    msgbus_cmd module

    + title="next chapter">chipsec.utilcmd.msgbus_cmd module

    - +
    @@ -152,20 +209,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • mmio_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.mmio_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.msgbus_cmd.html b/modules/chipsec.utilcmd.msgbus_cmd.html index ff2954ab..7ab4d42c 100644 --- a/modules/chipsec.utilcmd.msgbus_cmd.html +++ b/modules/chipsec.utilcmd.msgbus_cmd.html @@ -1,23 +1,24 @@ + - + - - - msgbus_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.msgbus_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,14 +47,14 @@

    Navigation

    -
    -

    msgbus_cmd module

    +
    +

    chipsec.utilcmd.msgbus_cmd module

    >>> chipsec_util msgbus read     <port> <register>
 >>> chipsec_util msgbus write    <port> <register> <value>
 >>> chipsec_util msgbus mm_read  <port> <register>
 >>> chipsec_util msgbus mm_write <port> <register> <value>
 >>> chipsec_util msgbus message  <port> <register> <opcode> [value]
->>>
+>>>
 >>> <port>    : message bus port of the target unit
 >>> <register>: message bus register/offset in the target unit port
 >>> <value>   : value to be written to the message bus register/offset
@@ -67,7 +68,53 @@ 
    Navigation
    
 >>> chipsec_util msgbus message  0x3 0x2E 0x11 0x0
    -
    +
    +
    +class MsgBusCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +msgbus_message()[source]
    +
    + +
    +
    +msgbus_mm_read()[source]
    +
    + +
    +
    +msgbus_mm_write()[source]
    +
    + +
    +
    +msgbus_read()[source]
    +
    + +
    +
    +msgbus_write()[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    + +
    @@ -121,12 +168,12 @@

    Table of Contents

    Previous topic

    mmio_cmd module

    + title="previous chapter">chipsec.utilcmd.mmio_cmd module

    Next topic

    msr_cmd module

    + title="next chapter">chipsec.utilcmd.msr_cmd module

    - +
    @@ -152,20 +199,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • msgbus_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.msgbus_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.msr_cmd.html b/modules/chipsec.utilcmd.msr_cmd.html index ccf2c36e..e6066247 100644 --- a/modules/chipsec.utilcmd.msr_cmd.html +++ b/modules/chipsec.utilcmd.msr_cmd.html @@ -1,23 +1,24 @@ + - + - - - msr_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.msr_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    msr_cmd module

    +
    +

    chipsec.utilcmd.msr_cmd module

    The msr command allows direct access to read and write MSRs.

    >>> chipsec_util msr <msr> [eax] [edx] [thread_id]
    @@ -58,7 +59,28 @@

    Navigation

    >>> chipsec_util msr 0x8B 0x0 0x0 0x0
    -
    +
    +
    +class MSRCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    + +
    @@ -112,12 +134,12 @@

    Table of Contents

    Previous topic

    msgbus_cmd module

    + title="previous chapter">chipsec.utilcmd.msgbus_cmd module

    Next topic

    pci_cmd module

    + title="next chapter">chipsec.utilcmd.pci_cmd module

    - +
    @@ -143,20 +165,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • msr_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.msr_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.pci_cmd.html b/modules/chipsec.utilcmd.pci_cmd.html index b9e0f789..7c024241 100644 --- a/modules/chipsec.utilcmd.pci_cmd.html +++ b/modules/chipsec.utilcmd.pci_cmd.html @@ -1,23 +1,24 @@ + - + - - - pci_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.pci_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    pci_cmd module

    +
    +

    chipsec.utilcmd.pci_cmd module

    The pci command can enumerate PCI/PCIe devices, enumerate expansion ROMs and allow direct access to PCI configuration registers via bus/device/function.

    >>> chipsec_util pci enumerate
 >>> chipsec_util pci read <bus> <device> <function> <offset> [width]
@@ -71,7 +72,53 @@ 
    Navigation
    
 >>> chipsec_util pci cmd 1
    -
    +
    +
    +class PCICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +pci_cmd()[source]
    +
    + +
    +
    +pci_dump()[source]
    +
    + +
    +
    +pci_enumerate()[source]
    +
    + +
    +
    +pci_read()[source]
    +
    + +
    +
    +pci_write()[source]
    +
    + +
    +
    +pci_xrom()[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    + +
    @@ -125,12 +172,12 @@

    Table of Contents

    Previous topic

    msr_cmd module

    + title="previous chapter">chipsec.utilcmd.msr_cmd module

    Next topic

    reg_cmd module

    + title="next chapter">chipsec.utilcmd.reg_cmd module

    - +
    @@ -156,20 +203,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • pci_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.pci_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.reg_cmd.html b/modules/chipsec.utilcmd.reg_cmd.html index 96e8035d..aa529930 100644 --- a/modules/chipsec.utilcmd.reg_cmd.html +++ b/modules/chipsec.utilcmd.reg_cmd.html @@ -1,23 +1,24 @@ + - + - - - reg_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.reg_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    reg_cmd module

    +
    +

    chipsec.utilcmd.reg_cmd module

    >>> chipsec_util reg read <reg_name> [<field_name>]
 >>> chipsec_util reg read_field <reg_name> <field_name>
 >>> chipsec_util reg write <reg_name> <value>
@@ -66,7 +67,53 @@ 
    Navigation
    
 >>> chipsec_util reg set_control BiosLockEnable 0x1
    -
    +
    +
    +class RegisterCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +reg_get_control()[source]
    +
    + +
    +
    +reg_read()[source]
    +
    + +
    +
    +reg_read_field()[source]
    +
    + +
    +
    +reg_set_control()[source]
    +
    + +
    +
    +reg_write()[source]
    +
    + +
    +
    +reg_write_field()[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    + +
    @@ -120,12 +167,12 @@

    Table of Contents

    Previous topic

    pci_cmd module

    + title="previous chapter">chipsec.utilcmd.pci_cmd module

    Next topic

    smbios_cmd module

    + title="next chapter">chipsec.utilcmd.smbios_cmd module

    - +
    @@ -151,20 +198,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • reg_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.reg_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.smbios_cmd.html b/modules/chipsec.utilcmd.smbios_cmd.html index 6fc43cbf..635c926c 100644 --- a/modules/chipsec.utilcmd.smbios_cmd.html +++ b/modules/chipsec.utilcmd.smbios_cmd.html @@ -1,23 +1,24 @@ + - + - - - smbios_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.smbios_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    smbios_cmd module

    +
    +

    chipsec.utilcmd.smbios_cmd module

    >>> chipsec_util smbios entrypoint
 >>> chipsec_util smbios get [raw|decoded] [type]
    @@ -57,7 +58,38 @@

    Navigation

    >>> chipsec_util smbios get raw
    -
    +
    +
    +class smbios_cmd(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +smbios_ep()[source]
    +
    + +
    +
    +smbios_get()[source]
    +
    + +
    + +
    @@ -111,12 +143,12 @@

    Table of Contents

    Previous topic

    reg_cmd module

    + title="previous chapter">chipsec.utilcmd.reg_cmd module

    Next topic

    smbus_cmd module

    + title="next chapter">chipsec.utilcmd.smbus_cmd module

    - +
    @@ -142,20 +174,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • smbios_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.smbios_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.smbus_cmd.html b/modules/chipsec.utilcmd.smbus_cmd.html index de57dcf5..c4ab3e2e 100644 --- a/modules/chipsec.utilcmd.smbus_cmd.html +++ b/modules/chipsec.utilcmd.smbus_cmd.html @@ -1,23 +1,24 @@ + - + - - - smbus_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.smbus_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    smbus_cmd module

    +
    +

    chipsec.utilcmd.smbus_cmd module

    >>> chipsec_util smbus read <device_addr> <start_offset> [size]
 >>> chipsec_util smbus write <device_addr> <offset> <byte_val>
    @@ -56,7 +57,43 @@

    Navigation

    >>> chipsec_util smbus read 0xA0 0x0 0x100
    -
    +
    +
    +class SMBusCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +smbus_read()[source]
    +
    + +
    +
    +smbus_write()[source]
    +
    + +
    + +
    @@ -110,12 +147,12 @@

    Table of Contents

    Previous topic

    smbios_cmd module

    + title="previous chapter">chipsec.utilcmd.smbios_cmd module

    Next topic

    spd_cmd module

    + title="next chapter">chipsec.utilcmd.spd_cmd module

    - +
    @@ -141,20 +178,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • smbus_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.smbus_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.spd_cmd.html b/modules/chipsec.utilcmd.spd_cmd.html index ac7723d3..6c101700 100644 --- a/modules/chipsec.utilcmd.spd_cmd.html +++ b/modules/chipsec.utilcmd.spd_cmd.html @@ -1,23 +1,24 @@ + - + - - - spd_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.spd_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    spd_cmd module

    +
    +

    chipsec.utilcmd.spd_cmd module

    >>> chipsec_util spd detect
 >>> chipsec_util spd dump [device_addr]
 >>> chipsec_util spd read <device_addr> <offset>
@@ -63,7 +64,48 @@ 
    Navigation
    
 >>> chipsec_util spd write 0xA0 0x0 0xAA
    -
    +
    +
    +class SPDCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +spd_detect()[source]
    +
    + +
    +
    +spd_dump()[source]
    +
    + +
    +
    +spd_read()[source]
    +
    + +
    +
    +spd_write()[source]
    +
    + +
    + +
    @@ -117,12 +159,12 @@

    Table of Contents

    Previous topic

    smbus_cmd module

    + title="previous chapter">chipsec.utilcmd.smbus_cmd module

    Next topic

    spi_cmd module

    + title="next chapter">chipsec.utilcmd.spi_cmd module

    - +
    @@ -148,20 +190,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • spd_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.spd_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.spi_cmd.html b/modules/chipsec.utilcmd.spi_cmd.html index 1fa6accb..56686fe3 100644 --- a/modules/chipsec.utilcmd.spi_cmd.html +++ b/modules/chipsec.utilcmd.spi_cmd.html @@ -1,23 +1,24 @@ + - + - - - spi_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.spi_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    spi_cmd module

    +
    +

    chipsec.utilcmd.spi_cmd module

    CHIPSEC includes functionality for reading and writing the SPI flash. When an image file is created from reading the SPI flash, this image can be parsed to reveal sections, files, variables, etc.

    Warning

    @@ -70,7 +71,68 @@

    Navigation

    >>> chipsec_util spi jedec decode
    -
    +
    +
    +class SPICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +spi_disable_wp()[source]
    +
    + +
    +
    +spi_dump()[source]
    +
    + +
    +
    +spi_erase()[source]
    +
    + +
    +
    +spi_info()[source]
    +
    + +
    +
    +spi_jedec()[source]
    +
    + +
    +
    +spi_read()[source]
    +
    + +
    +
    +spi_sfdp()[source]
    +
    + +
    +
    +spi_write()[source]
    +
    + +
    + +
    @@ -124,12 +186,12 @@

    Table of Contents

    Previous topic

    spd_cmd module

    + title="previous chapter">chipsec.utilcmd.spd_cmd module

    Next topic

    spidesc_cmd module

    + title="next chapter">chipsec.utilcmd.spidesc_cmd module

    - +
    @@ -155,20 +217,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • spi_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.spi_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.spidesc_cmd.html b/modules/chipsec.utilcmd.spidesc_cmd.html index a86feed7..6174aad7 100644 --- a/modules/chipsec.utilcmd.spidesc_cmd.html +++ b/modules/chipsec.utilcmd.spidesc_cmd.html @@ -1,23 +1,24 @@ + - + - - - spidesc_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.spidesc_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    spidesc_cmd module

    +
    +

    chipsec.utilcmd.spidesc_cmd module

    >>> chipsec_util spidesc <rom>
    @@ -55,7 +56,28 @@

    Navigation

    >>> chipsec_util spidesc spi.bin
    -
    +
    +
    +class SPIDescCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    + +
    @@ -109,12 +131,12 @@

    Table of Contents

    Previous topic

    spi_cmd module

    + title="previous chapter">chipsec.utilcmd.spi_cmd module

    Next topic

    tpm_cmd module

    + title="next chapter">chipsec.utilcmd.tpm_cmd module

    - +
    @@ -140,20 +162,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • spidesc_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.spidesc_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.tpm_cmd.html b/modules/chipsec.utilcmd.tpm_cmd.html index fd3992b4..746260d0 100644 --- a/modules/chipsec.utilcmd.tpm_cmd.html +++ b/modules/chipsec.utilcmd.tpm_cmd.html @@ -1,23 +1,24 @@ + - + - - - tpm_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.tpm_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    tpm_cmd module

    +
    +

    chipsec.utilcmd.tpm_cmd module

    >>> chipsec_util tpm parse_log <file>
 >>> chipsec_util tpm state <locality>
 >>> chipsec_util tpm command <commandName> <locality> <command_parameters>
@@ -68,7 +69,53 @@ 
    Navigation
    
 >>> chipsec_util tpm command continueselftest 0
    -
    +
    +
    +class TPMCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +no_driver_cmd = ['parse_log']
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +set_up()[source]
    +
    + +
    +
    +tpm_command()[source]
    +
    + +
    +
    +tpm_parse()[source]
    +
    + +
    +
    +tpm_state()[source]
    +
    + +
    + +
    @@ -122,12 +169,12 @@

    Table of Contents

    Previous topic

    spidesc_cmd module

    + title="previous chapter">chipsec.utilcmd.spidesc_cmd module

    Next topic

    txt_cmd module

    + title="next chapter">chipsec.utilcmd.txt_cmd module

    - +
    @@ -153,20 +200,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • tpm_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.tpm_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.txt_cmd.html b/modules/chipsec.utilcmd.txt_cmd.html index a1758800..ff354ec5 100644 --- a/modules/chipsec.utilcmd.txt_cmd.html +++ b/modules/chipsec.utilcmd.txt_cmd.html @@ -1,23 +1,24 @@ + - + - - - txt_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.txt_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    txt_cmd module

    +
    +

    chipsec.utilcmd.txt_cmd module

    Command-line utility providing access to Intel TXT (Trusted Execution Technology) registers

    Usage:
    >>> chipsec_util txt dump
@@ -56,7 +57,45 @@ 
    Navigation
    -
    +
    +
    +class TXTCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +txt_dump()[source]
    +
    + +
    +
    +txt_state()[source]
    +

    Dump Intel TXT state

    +

    This is similar to command “txt-stat” from Trusted Boot project +https://sourceforge.net/p/tboot/code/ci/v2.0.0/tree/utils/txt-stat.c +which was documented on +https://www.intel.com/content/dam/www/public/us/en/documents/guides/dell-one-stop-txt-activation-guide.pdf +and it is also similar to command “sl-stat” from TrenchBoot project +https://github.com/TrenchBoot/sltools/blob/842cfd041b7454727b363b72b6d4dcca9c00daca/sl-stat/sl-stat.c

    +
    + +
    + +
    @@ -110,12 +149,12 @@

    Table of Contents

    Previous topic

    tpm_cmd module

    + title="previous chapter">chipsec.utilcmd.tpm_cmd module

    Next topic

    ucode_cmd module

    + title="next chapter">chipsec.utilcmd.ucode_cmd module

    - +
    @@ -141,20 +180,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • txt_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.txt_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.ucode_cmd.html b/modules/chipsec.utilcmd.ucode_cmd.html index 40132264..9ad851f1 100644 --- a/modules/chipsec.utilcmd.ucode_cmd.html +++ b/modules/chipsec.utilcmd.ucode_cmd.html @@ -1,23 +1,24 @@ + - + - - - ucode_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.ucode_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    ucode_cmd module

    +
    +

    chipsec.utilcmd.ucode_cmd module

    >>> chipsec_util ucode id|load|decode [ucode_update_file (in .PDB or .BIN format)] [cpu_id]
    @@ -57,7 +58,38 @@

    Navigation

    >>> chipsec_util ucode decode ucode.pdb
    - +
    +
    +class UCodeCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +ucode_decode()[source]
    +
    + +
    +
    +ucode_id()[source]
    +
    + +
    +
    +ucode_load()[source]
    +
    + +
    + +
    @@ -111,12 +143,12 @@

    Table of Contents

    Previous topic

    txt_cmd module

    + title="previous chapter">chipsec.utilcmd.txt_cmd module

    Next topic

    uefi_cmd module

    + title="next chapter">chipsec.utilcmd.uefi_cmd module

    - +
    @@ -142,20 +174,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • ucode_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.ucode_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.uefi_cmd.html b/modules/chipsec.utilcmd.uefi_cmd.html index 1cbcd137..280c6201 100644 --- a/modules/chipsec.utilcmd.uefi_cmd.html +++ b/modules/chipsec.utilcmd.uefi_cmd.html @@ -1,23 +1,24 @@ + - + - - - uefi_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.uefi_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    uefi_cmd module

    +
    +

    chipsec.utilcmd.uefi_cmd module

    The uefi command provides access to UEFI variables, both on the live system and in a SPI flash image file.

    >>> chipsec_util uefi types
 >>> chipsec_util uefi var-list
@@ -79,7 +80,108 @@ 
    Navigation
    
 >>> chipsec_util uefi replace  AAAAAAAA-BBBB-CCCC-DDDD-EEEEEEEEEEEE bios.bin new_bios.bin mydriver.efi
    -
    +
    +
    +class UEFICommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +assemble()[source]
    +
    + +
    +
    +decode()[source]
    +
    + +
    +
    +insert_after()[source]
    +
    + +
    +
    +insert_before()[source]
    +
    + +
    +
    +keys()[source]
    +
    + +
    +
    +nvram()[source]
    +
    + +
    +
    +nvram_auth()[source]
    +
    + +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +remove()[source]
    +
    + +
    +
    +replace()[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +s3bootscript()[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +tables()[source]
    +
    + +
    +
    +var_delete()[source]
    +
    + +
    +
    +var_find()[source]
    +
    + +
    +
    +var_list()[source]
    +
    + +
    +
    +var_read()[source]
    +
    + +
    +
    +var_write()[source]
    +
    + +
    + +
    @@ -133,12 +235,12 @@

    Table of Contents

    Previous topic

    ucode_cmd module

    + title="previous chapter">chipsec.utilcmd.ucode_cmd module

    Next topic

    vmem_cmd module

    + title="next chapter">chipsec.utilcmd.vmem_cmd module

    - +
    @@ -164,20 +266,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • uefi_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.uefi_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.vmem_cmd.html b/modules/chipsec.utilcmd.vmem_cmd.html index 989990c9..548d5034 100644 --- a/modules/chipsec.utilcmd.vmem_cmd.html +++ b/modules/chipsec.utilcmd.vmem_cmd.html @@ -1,23 +1,24 @@ + - + - - - vmem_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.vmem_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,11 +47,11 @@

    Navigation

    -
    -

    vmem_cmd module

    +
    +

    chipsec.utilcmd.vmem_cmd module

    The vmem command provides direct access to read and write virtual memory.

    >>> chipsec_util vmem <op> <physical_address> <length> [value|buffer_file]
->>>
+>>>
 >>> <physical_address> : 64-bit physical address
 >>> <op>               : read|readval|write|writeval|allocate|pagedump|search|getphys
 >>> <length>           : byte|word|dword or length of the buffer from <buffer_file>
@@ -70,7 +71,63 @@ 
    Navigation
    
 >>> chipsec_util vmem getphys  0xFED00000
    -
    +
    +
    +class VMemCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +set_up() → None[source]
    +
    + +
    +
    +vmem_allocate()[source]
    +
    + +
    +
    +vmem_getphys()[source]
    +
    + +
    +
    +vmem_read()[source]
    +
    + +
    +
    +vmem_readval()[source]
    +
    + +
    + +
    + +
    +
    +vmem_write()[source]
    +
    + +
    +
    +vmem_writeval()[source]
    +
    + +
    + +
    @@ -124,12 +181,12 @@

    Table of Contents

    Previous topic

    uefi_cmd module

    + title="previous chapter">chipsec.utilcmd.uefi_cmd module

    Next topic

    vmm_cmd module

    + title="next chapter">chipsec.utilcmd.vmm_cmd module

    - +
    @@ -155,20 +212,20 @@

    Navigation

    modules |
  • - next |
  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • vmem_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.vmem_cmd module
    • \ No newline at end of file diff --git a/modules/chipsec.utilcmd.vmm_cmd.html b/modules/chipsec.utilcmd.vmm_cmd.html index ce43045c..14104f7b 100644 --- a/modules/chipsec.utilcmd.vmm_cmd.html +++ b/modules/chipsec.utilcmd.vmm_cmd.html @@ -1,23 +1,24 @@ + - + - - - vmm_cmd module — CHIPSEC documentation - - + + chipsec.utilcmd.vmm_cmd module — CHIPSEC documentation + + - - - + + + + - + - - + + @@ -46,8 +47,8 @@

    Navigation

    -
    -

    vmm_cmd module

    +
    +

    chipsec.utilcmd.vmm_cmd module

    >>> chipsec_util vmm hypercall <rax> <rbx> <rcx> <rdx> <rdi> <rsi> [r8] [r9] [r10] [r11]
 >>> chipsec_util vmm hypercall <eax> <ebx> <ecx> <edx> <edi> <esi>
 >>> chipsec_util vmm pt|ept <ept_pointer>
@@ -61,7 +62,43 @@ 
    Navigation
    
 >>> chipsec_util vmm virtio 0:6.0
    -
    +
    +
    +class VMMCommand(argv, cs=None)[source]
    +

    Bases: chipsec.command.BaseCommand

    +
    +
    +parse_arguments() → None[source]
    +
    + +
    +
    +requirements() → chipsec.command.toLoad[source]
    +
    + +
    +
    +run()[source]
    +
    + +
    +
    +vmm_hypercall()[source]
    +
    + +
    +
    +vmm_pt()[source]
    +
    + +
    +
    +vmm_virtio()[source]
    +
    + +
    + +
    @@ -115,12 +152,12 @@

    Table of Contents

    Previous topic

    vmem_cmd module

    + title="previous chapter">chipsec.utilcmd.vmem_cmd module

    Next topic

    hal package

    + title="next chapter">chipsec.hal package

    - +
    @@ -146,20 +183,20 @@

    Navigation

    modules |
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  • - previous |
  • CHIPSEC documentation »
  • Architecture Overview »
    • -
  • utilcmd package »
    • -
  • vmm_cmd module
    • +
  • chipsec.utilcmd package »
    • +
  • chipsec.utilcmd.vmm_cmd module
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    Python Module Index

    m | o | p | - t | u @@ -372,6 +373,11 @@

    Python Module Index

        chipsec.helper.windows + + +     + chipsec.helper.windows.windowshelper +   l @@ -600,211 +606,6 @@

    Python Module Index

        chipsec.modules.snb - - -     - chipsec.modules.tools - - - -     - chipsec.modules.tools.cpu - - - -     - chipsec.modules.tools.cpu.sinkhole - - - -     - chipsec.modules.tools.generate_test_id - - - -     - chipsec.modules.tools.secureboot - - - -     - chipsec.modules.tools.secureboot.te - - - -     - chipsec.modules.tools.smm - - - -     - chipsec.modules.tools.smm.rogue_mmio_bar - - - -     - chipsec.modules.tools.smm.smm_ptr - - - -     - chipsec.modules.tools.uefi - - - -     - chipsec.modules.tools.uefi.reputation - - - -     - chipsec.modules.tools.uefi.s3script_modify - - - -     - chipsec.modules.tools.uefi.scan_blocked - - - -     - chipsec.modules.tools.uefi.scan_image - - - -     - chipsec.modules.tools.uefi.uefivar_fuzz - - - -     - chipsec.modules.tools.vmm - - - -     - chipsec.modules.tools.vmm.common - - - -     - chipsec.modules.tools.vmm.cpuid_fuzz - - - -     - chipsec.modules.tools.vmm.ept_finder - - - -     - chipsec.modules.tools.vmm.hv - - - -     - chipsec.modules.tools.vmm.hv.define - - - -     - chipsec.modules.tools.vmm.hv.hypercall - - - -     - chipsec.modules.tools.vmm.hv.hypercallfuzz - - - -     - chipsec.modules.tools.vmm.hv.synth_dev - - - -     - chipsec.modules.tools.vmm.hv.synth_kbd - - - -     - chipsec.modules.tools.vmm.hv.vmbus - - - -     - chipsec.modules.tools.vmm.hv.vmbusfuzz - - - -     - chipsec.modules.tools.vmm.hypercallfuzz - - - -     - chipsec.modules.tools.vmm.iofuzz - - - -     - chipsec.modules.tools.vmm.msr_fuzz - - - -     - chipsec.modules.tools.vmm.pcie_fuzz - - - -     - chipsec.modules.tools.vmm.pcie_overlap_fuzz - - - -     - chipsec.modules.tools.vmm.vbox - - - -     - chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase - - - -     - chipsec.modules.tools.vmm.venom - - - -     - chipsec.modules.tools.vmm.xen - - - -     - chipsec.modules.tools.vmm.xen.define - - - -     - chipsec.modules.tools.vmm.xen.hypercall - - - -     - chipsec.modules.tools.vmm.xen.hypercallfuzz - - - -     - chipsec.modules.tools.vmm.xen.xsa188 - - - -     - chipsec.modules.tools.wsmt -   o @@ -822,14 +623,6 @@

    Python Module Index

    chipsec.parsers   - - t - - - - chipsec.testcase - -   u @@ -1063,7 +856,7 @@

    Quick search

    - +
    @@ -1082,8 +875,8 @@

    Navigation

    \ No newline at end of file diff --git a/search.html b/search.html index 687d7068..9ca95501 100644 --- a/search.html +++ b/search.html @@ -1,21 +1,23 @@ + - + Search — CHIPSEC documentation - - + + - - - + + + + - + @@ -138,8 +140,8 @@

    Navigation

    \ No newline at end of file diff --git a/searchindex.js b/searchindex.js index a2d647aa..b28e290e 100644 --- a/searchindex.js +++ b/searchindex.js @@ -1 +1 @@ -Search.setIndex({"docnames": ["contribution/code-style-python", "development/Architecture-Overview", "development/Configuration-Files", "development/Developing", "development/OS-Helpers-and-Drivers", "development/Platform-Detection", "development/Sample-Module-Code", "development/Sample-Util-Command", "development/Vulnerabilities-and-CHIPSEC-Modules", "index", "installation/InstallLinux", "installation/InstallWinDAL", "installation/InstallWindows", "installation/USBwithUEFIShell", "modules/chipsec.cfg.8086", "modules/chipsec.cfg.8086.adl.xml", "modules/chipsec.cfg.8086.apl.xml", "modules/chipsec.cfg.8086.avn.xml", "modules/chipsec.cfg.8086.bdw.xml", "modules/chipsec.cfg.8086.bdx.xml", "modules/chipsec.cfg.8086.byt.xml", "modules/chipsec.cfg.8086.cfl.xml", "modules/chipsec.cfg.8086.cht.xml", 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202, 203, 204, 205, 219, 224, 230, 231, 232, 236, 249, 252, 255], "scope": 0, "3107": 0, "annot": 0, "syntax": 0, "ad": [0, 3, 4, 185, 186], "arbitrari": 0, "metadata": 0, "0": [0, 2, 3, 5, 12, 20, 55, 78, 83, 87, 89, 91, 103, 104, 143, 144, 148, 151, 153, 154, 159, 161, 162, 181, 201, 203, 204, 223, 226, 235, 239, 246, 248, 251, 254], "362": 0, "signatur": [0, 8, 9, 182, 186], "object": 0, "necessari": [0, 9, 10, 148, 214, 224], "about": [0, 3, 167, 186, 254], "its": [0, 9, 186, 255], "paramet": [0, 59, 196, 200, 246], "484": 0, "5": [0, 2], "526": 0, "544": 0, "protocol": [0, 103], "structur": [0, 3, 4, 13, 94], "subtyp": 0, "static": 0, "duck": 0, "specifi": [0, 5, 170, 184, 185, 186, 187, 197, 202, 203, 212, 255], "checker": 0, "585": 0, "gener": [0, 1, 3, 4, 12, 15, 21, 36, 37, 48, 49, 50, 51, 57, 58, 60, 63, 64, 65, 67, 82, 92, 143, 176, 177, 181, 187, 188, 197, 200, 252], "In": [0, 9, 12, 143, 148, 159, 176, 182, 254], "collect": 0, "enabl": [0, 2, 3, 8, 9, 12, 13, 141, 143, 148, 149, 151, 158, 160, 162, 163, 205, 231, 254], "current": [0, 3, 5, 184, 186, 224, 225], "avail": [0, 3, 12, 55, 66, 205, 254, 255], "9": 0, "586": 0, "ha": [0, 5, 10, 11, 12, 149, 163, 254], "specif": [0, 1, 2, 3, 5, 8, 19, 29, 32, 52, 67, 76, 82, 89, 102, 103, 104, 105, 109, 112, 126, 148, 149, 150, 194, 195, 200, 203, 210, 211, 255], "valu": [0, 1, 2, 76, 84, 153, 162, 182, 185, 191, 201, 202, 203, 208, 223, 228, 230, 232, 233, 235, 236, 237, 239, 240, 250, 254, 255], "": [0, 8, 10, 13, 21, 60, 66, 151, 170, 177, 184, 188, 255], "589": 0, "typeddict": 0, "dictionari": 0, "fix": 0, "kei": [0, 5, 8, 12, 143, 157, 184, 232, 249], "each": [0, 8, 89, 104, 169, 191, 201, 202, 203, 254], "593": 0, "flexibl": 0, "decor": 0, "context": 0, "604": 0, "allow": [0, 3, 9, 12, 143, 161, 187, 214, 228, 230, 235, 238, 239, 254], "write": [0, 1, 2, 8, 9, 15, 37, 48, 49, 50, 51, 57, 58, 63, 64, 65, 76, 84, 91, 97, 143, 157, 163, 165, 182, 185, 188, 202, 204, 205, 207, 208, 227, 228, 230, 233, 235, 236, 237, 238, 239, 240, 242, 243, 244, 249, 250, 254], "union": 0, "x": [0, 9, 255], "y": [0, 36, 40, 60], "overload": 0, "10": [0, 12, 32, 88, 151, 184, 212], "612": 0, "propos": 0, "paramspec": 0, "concaten": 0, "forward": 0, "callabl": 0, "over": [0, 8], "anoth": [0, 148, 224], "613": 0, "explicit": 0, "alias": 0, "wai": [0, 143, 148, 162], "explicitli": [0, 151, 255], "declar": 0, "assign": 0, "alia": 0, "646": 0, "variad": 0, "introduc": 0, "typevartupl": 0, "parameteris": 0, "11": [0, 12, 169], "647": 0, "user": [0, 9, 116, 254], "defin": [0, 1, 2, 3, 8, 12, 136, 144, 151, 159, 160, 163, 165, 169, 174, 186, 187, 189, 193, 209, 214, 232, 254], "guard": [0, 12], "program": [0, 15, 37, 48, 49, 50, 51, 57, 58, 63, 64, 65, 161, 164, 254], "influenc": 0, "condit": [0, 8, 12, 143], "narrow": 0, "emploi": 0, "base": [0, 1, 2, 3, 4, 8, 12, 16, 17, 18, 19, 20, 28, 29, 33, 34, 35, 36, 37, 38, 56, 60, 62, 80, 103, 143, 153, 162, 170, 181, 182, 184, 196, 208, 234, 235, 254], "runtim": [0, 169, 170], "check": [0, 1, 5, 6, 8, 140, 141, 142, 143, 147, 148, 149, 151, 153, 154, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 169, 170, 176, 181, 184, 186, 187, 207, 232, 254, 255], "655": 0, "mark": 0, "individu": [0, 8], "item": [0, 181], "potenti": [0, 182], "miss": [0, 232, 254], "notat": 0, "them": [0, 188, 205, 254], "notrequir": 0, "673": 0, "method": [0, 3, 6, 9], "instanc": 0, "675": 0, "supertyp": 0, "literalstr": 0, "681": 0, "data": [0, 8, 79, 88, 92, 97, 143, 148, 159, 182, 188, 208, 224], "transform": 0, "provid": [0, 1, 2, 3, 4, 9, 12, 74, 94, 179, 182, 219, 231, 233, 247, 249, 250], "certain": [0, 3, 9, 143, 169, 214, 254, 255], "metaclass": 0, "similar": 0, "dataclass": 0, "692": 0, "precis": 0, "kwarg": 0, "A": [0, 8, 12, 15, 37, 48, 49, 50, 51, 55, 57, 58, 63, 64, 65, 143, 182, 244, 254], "without": [0, 3, 8, 12, 15, 37, 48, 49, 50, 51, 57, 58, 63, 64, 65, 255], "695": 0, "within": [0, 3, 12, 158, 160, 182, 191, 201, 202, 203, 204, 205, 208, 232], "And": 0, "statement": 0, "698": 0, "overrid": [0, 2, 4, 8, 166, 254], "prevent": [0, 12, 143, 148, 154, 254], "bug": [0, 252], "occur": [0, 149], "chang": [0, 9, 12, 97, 143, 162, 181, 185], "inherit": [0, 3, 8], "deriv": 0, "even": [0, 15, 37, 48, 49, 50, 51, 57, 58, 63, 64, 65, 148, 159, 255], "group": 0, "exampl": [0, 3, 7, 8, 9, 12, 140, 141, 142, 143, 144, 146, 147, 149, 150, 151, 152, 153, 154, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 169, 170, 176, 177, 179, 181, 182, 185, 186, 187, 188, 191, 192, 200, 201, 202, 203, 204, 205, 207, 208, 212, 213, 214, 219, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 248, 249, 250, 251, 255], "present": [0, 12, 176, 181, 182], "abstract": [0, 2, 3, 116, 126], "515": 0, "extend": [0, 90, 192], "so": [0, 2, 151, 207, 255], "visual": [0, 12, 254], "separ": 0, "purpos": [0, 15, 37, 48, 49, 50, 51, 57, 58, 63, 64, 65, 159], "At": 0, "time": [0, 202], "572": 0, "remov": [0, 12, 196, 197, 198, 200, 249, 254], "furtur": 0, "setuptool": [0, 10, 12], "been": [0, 5, 159, 161, 163, 214, 254], "fulli": 0, "replac": [0, 179, 182, 185, 249], "up": [0, 254], "date": 0, "minimum": 0, "62": 0, "7": [0, 2, 10, 11, 12, 97, 144], "latest": [0, 10, 12, 13, 253], "note": [0, 148, 169, 196, 197, 198, 254], "get": [0, 3, 10, 162, 241], "command": [0, 3, 4, 7, 12, 79, 102, 116, 182, 208, 219, 226, 227, 228, 229, 230, 231, 233, 234, 235, 238, 239, 244, 246, 247, 249, 250, 255], "error": [0, 8, 12, 153, 188, 254], "verifi": [0, 148, 152, 157], "least": [0, 3], "632": 0, "chipsec": [1, 2, 3, 4, 6, 7, 11, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 110, 159, 160, 224, 244, 252, 254], "py": [1, 3, 4, 6, 7, 8, 10, 12, 13, 140, 141, 142, 143, 144, 146, 147, 149, 150, 151, 152, 153, 154, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 169, 170, 176, 177, 179, 181, 182, 184, 185, 186, 188, 191, 192, 196, 197, 198, 200, 201, 202, 203, 204, 205, 207, 208, 212, 213, 214, 244, 255], "main": [1, 12, 105], "autom": 1, "access": [1, 9, 74, 79, 83, 84, 85, 87, 88, 89, 91, 93, 94, 95, 96, 97, 111, 159, 161, 162, 164, 165, 219, 230, 231, 233, 235, 238, 239, 247, 249, 250, 254, 255], "variou": [1, 9, 75, 126, 224, 255], "resourc": [1, 9, 21, 25, 36, 37, 38, 60, 67, 89, 255], "chipset": [1, 8, 19, 29, 37, 38, 39, 41, 52, 53, 54, 60, 67, 163], "detect": [1, 2, 9, 96, 154, 163, 184, 186, 243, 254], "common": [1, 2, 3, 4, 8, 14, 105, 106, 136, 140, 141, 142, 143, 144, 146, 147, 149, 150, 151, 152, 153, 154, 157, 158, 159, 160, 162, 163, 164, 165, 166, 167, 169, 170, 174, 177, 189, 214, 254, 255], "logger": [1, 3, 6, 110], "log": [1, 103, 182, 191, 196, 197, 198, 200, 201, 202, 203, 204, 205, 212, 224, 254, 255], "modul": [1, 68, 71, 73, 113, 115, 117, 119, 121, 127, 129, 139, 145, 156, 168, 174, 175, 178, 180, 183, 189, 193, 206, 209, 218, 255], "load": [1, 2, 8, 9, 12, 148, 192, 248, 255], "result_delta": 1, "support": [1, 3, 8, 9, 10, 11, 12, 126, 148, 157, 161, 169, 170, 176, 254], "result": [1, 3, 6, 9, 12, 143, 148, 149, 151, 153, 163, 164, 191, 224, 255], "delta": [1, 225, 255], "run": [1, 3, 6, 7, 8, 9, 12, 66, 144, 152, 153, 154, 158, 159, 163, 176, 181, 191, 192, 200, 201, 202, 203, 204, 205, 208, 212, 213, 224, 253, 254], "testcas": 1, "xml": [1, 2, 3, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 225, 255], "json": [1, 186, 187, 225, 255], "output": [1, 12, 191, 225, 255], "helper": [1, 9, 12, 116, 120, 124, 255], "registri": 1, "o": [1, 8, 9, 12, 32, 36, 40, 60, 83, 84, 91, 126, 148, 159, 169, 170, 176, 185, 202, 204, 205, 207, 214, 230, 232, 254, 255], "oshelp": [1, 4, 113], "wrapper": [1, 126], "platform": [1, 2, 3, 9, 12, 15, 17, 18, 19, 20, 21, 24, 28, 29, 33, 34, 35, 36, 37, 38, 48, 49, 50, 51, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 67, 101, 103, 105, 109, 126, 143, 152, 153, 154, 159, 160, 161, 163, 164, 185, 186, 187, 188, 220, 254, 255], "code": [1, 3, 9, 10, 12, 126, 159, 160, 162, 181, 182, 212, 213, 252, 255], "invok": [1, 126], "kernel": [1, 9, 10, 126, 186, 187, 252, 255], "driver": [1, 9, 10, 126, 184, 186, 187, 196, 197, 198, 200, 253, 255], "implement": [1, 3, 8, 55, 103, 148, 170, 179, 214], "capabl": [1, 246], "manual": [1, 8, 12, 146, 150, 160, 188, 254, 255], "direct": [1, 9, 32, 149, 161, 205, 230, 233, 235, 238, 239, 250], "BY": 1, "THESE": 1, "your": [1, 9, 13, 167, 179, 244, 254, 255], "system": [1, 2, 4, 9, 11, 12, 59, 143, 148, 149, 159, 161, 162, 165, 166, 176, 181, 182, 185, 188, 191, 200, 201, 202, 203, 204, 205, 208, 212, 213, 214, 244, 249, 254], "unboot": [1, 188, 244], "know": [1, 3, 186], "what": [1, 186], "numer": [1, 9, 255], "instruct": [1, 185], "hex": [1, 181, 182, 192, 204, 255], "acpi_cmd": [1, 218], "chipset_cmd": [1, 218], "cmos_cmd": [1, 218], "config_cmd": [1, 218], "cpu_cmd": [1, 218], "decode_cmd": [1, 218], "deltas_cmd": [1, 218], "desc_cmd": [1, 218], "ec_cmd": [1, 218], "igd_cmd": [1, 218], "interrupts_cmd": [1, 218], "io_cmd": [1, 218], "iommu_cmd": [1, 218], "lock_check_cmd": [1, 218], "mem_cmd": [1, 218], "mmcfg_base_cmd": [1, 218], "mmcfg_cmd": [1, 218], "mmio_cmd": [1, 218], "msgbus_cmd": [1, 218], "msr_cmd": [1, 218], "pci_cmd": [1, 218], "reg_cmd": [1, 218], "smbios_cmd": [1, 218], "smbus_cmd": [1, 218], "spd_cmd": [1, 218], "spi_cmd": [1, 218], "spidesc_cmd": [1, 218], "tpm_cmd": [1, 218], "txt_cmd": [1, 218], "ucode_cmd": [1, 218], "uefi_cmd": [1, 218], "vmem_cmd": [1, 218], "vmm_cmd": [1, 218], "task": 1, "spi": [1, 2, 8, 73, 98, 143, 164, 165, 166, 167, 188, 224, 244, 245, 249, 254, 255], "acpi": [1, 8, 12, 73, 75, 214, 219], "acpi_t": [1, 73, 219], "cmo": [1, 8, 73, 221], "cpu": [1, 5, 8, 13, 73, 82, 89, 97, 104, 136, 139, 146, 147, 148, 153, 159, 160, 161, 162, 174, 176, 203, 223, 254, 255], "cpuid": [1, 5, 73, 113, 121, 144, 148, 191, 223], "ec": [1, 73, 227, 235], "hal_bas": [1, 73], "igd": [1, 73, 228], "interrupt": [1, 8, 73], "io": [1, 32, 73, 87, 181, 204, 230], "iobar": [1, 73], "iommu": [1, 2, 8, 14, 73, 231], "lock": [1, 2, 3, 8, 73, 141, 142, 143, 149, 150, 151, 152, 153, 158, 159, 160, 161, 167, 232, 254], "mmio": [1, 2, 73, 91, 181, 185, 204, 205, 236], "msgbu": [1, 73, 237], "msr": [1, 4, 73, 148, 149, 150, 153, 203, 207, 238, 254], "page": [1, 73, 192], "pci": [1, 4, 8, 55, 73, 87, 92, 185, 239], "pcidb": [1, 73], "physmem": [1, 73], "smbio": [1, 73, 241], "smbu": [1, 73, 163, 242], "spd": [1, 73, 163, 243], "spi_descriptor": [1, 73], "spi_jedec_id": [1, 73], "spi_uefi": [1, 73], "tpm": [1, 73, 102, 103, 246], "tpm12_command": [1, 73], "tpm_eventlog": [1, 73], "ucod": [1, 73, 148, 248], "uefi": [1, 4, 8, 9, 10, 12, 73, 100, 106, 108, 109, 110, 118, 136, 139, 157, 169, 170, 174, 181, 182, 184, 185, 186, 187, 188, 214, 249, 254], "uefi_common": [1, 73], "uefi_compress": [1, 73], "uefi_fv": [1, 73], "uefi_platform": [1, 73], "uefi_search": [1, 73], "virtmem": [1, 73], "vmm": [1, 8, 73, 136, 174, 190, 191, 192, 196, 197, 198, 200, 201, 202, 203, 204, 205, 207, 208, 212, 213, 251], "primit": [1, 71], "select": [1, 5, 12], "option": [1, 8, 9, 12, 91, 157, 169, 170, 182, 185, 188, 191, 192, 201, 202, 203, 204, 205, 208, 224], "report": [1, 144, 252], "cleanup": 1, "setup": [1, 8, 10, 12, 13, 141, 255], "instal": [1, 8, 253, 255], "packag": [1, 4, 8, 10, 12, 41, 67, 118], "chipsec_root": 1, "build_exe_": 1, "window": [1, 4, 9, 113, 143, 176, 214], "human": 2, "regist": [2, 3, 5, 66, 88, 89, 91, 141, 142, 143, 146, 147, 148, 149, 150, 151, 152, 153, 154, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 176, 185, 201, 203, 207, 222, 232, 237, 239, 247, 254], "8086": [2, 3, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67], "broken": 2, "control": [2, 3, 8, 11, 12, 19, 29, 37, 38, 53, 54, 55, 60, 79, 95, 141, 142, 143, 148, 149, 150, 161, 163, 164, 166, 167, 254], "bit": [2, 9, 129, 143, 144, 148, 149, 151, 153, 160, 163, 177, 204, 233, 250], "field": [2, 3], "alwai": 2, "first": [2, 3, 205], "correct": [2, 9, 224], "off": [2, 9], "bar": [2, 84, 87, 91, 181, 204, 205], "spibar": [2, 236], "bu": [2, 12, 88, 181, 204, 235, 237, 239, 251], "dev": [2, 10, 204, 252], "0x1f": [2, 239], "fun": [2, 204], "reg": [2, 182, 240], "0x10": [2, 87, 233, 236, 237, 250], "width": [2, 185, 228, 230, 235, 236, 239, 255], "mask": [2, 239, 255], "0xfffff000": 2, "size": [2, 79, 84, 97, 182, 188, 200, 204, 227, 234, 242, 246, 254], "0x1000": [2, 87, 233, 250], "desc": [2, 3, 182], "rang": [2, 8, 66, 91, 143, 160, 161, 162, 167, 181, 182, 191, 196, 201, 204, 205, 254], "offset": [2, 76, 79, 84, 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"sphinx.domains.std": 2, "sphinx.ext.todo": 2, "sphinx.ext.viewcode": 1, "sphinx": 60}, "alltitles": {"Python Version": [[0, "python-version"]], "Python Coding Style Guide": [[0, "python-coding-style-guide"]], "f-Strings": [[0, "f-strings"]], "PEP versions supported by CHIPSEC": [[0, "id2"], [0, "id3"], [0, "id4"], [0, "id5"], [0, "id6"]], "Type Hints": [[0, "type-hints"]], "Underscores in Numeric Literals": [[0, "underscores-in-numeric-literals"]], "Walrus Operator (:=)": [[0, "walrus-operator"]], "Deprecate distutils module support": [[0, "deprecate-distutils-module-support"]], "Architecture Overview": [[1, "architecture-overview"]], "Core components": [[1, "core-components"]], "Commands": [[1, "commands"]], "HAL (Hardware Abstraction Layer)": [[1, "hal-hardware-abstraction-layer"]], "Fuzzing": [[1, "fuzzing"]], "CHIPSEC_MAIN Program Flow": [[1, "chipsec-main-program-flow"]], "CHIPSEC_UTIL Program Flow": [[1, "chipsec-util-program-flow"]], "Auxiliary components": [[1, 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[[5, "platform-configuration-options"]], "Sample module code template": [[6, "sample-module-code-template"]], "CHIPSEC Modules": [[8, "chipsec-modules"]], "Attack Surface/Vector: Firmware protections in ROM": [[8, "id1"]], "Attack Surface/Vector: Runtime protection of SMRAM": [[8, "id2"]], "Attack Surface/Vector: Secure boot - Incorrect protection of secure boot configuration": [[8, "id3"]], "Attack Surface/Vector: Persistent firmware configuration": [[8, "id4"]], "Attack Surface/Vector: Platform hardware configuration": [[8, "id5"]], "Attack Surface/Vector: Runtime firmware (eg. SMI handlers)": [[8, "id6"]], "Attack Surface/Vector: Boot time firmware": [[8, "id7"]], "Attack Surface/Vector: Power state transitions (eg. resume from sleep)": [[8, "id8"]], "Attack Surface/Vector: Firmware update": [[8, "id9"]], "Attack Surface/Vector: Network interfaces": [[8, "id10"]], "Attack Surface/Vector: Misc": [[8, "id11"]], "Modules": [[8, "modules"]], "CHIPSEC 1.12.8": [[9, "chipsec-1-12-7"]], "Start here": [[9, null]], "Installation": [[9, "installation"], [9, null]], "Using CHIPSEC": [[9, "using-chipsec"], [9, null]], "Module & Command Development": [[9, "module-command-development"]], "Architecture and Modules": [[9, null]], "Contribution and Style Guides": [[9, "contribution-and-style-guides"]], "Contribution Guide": [[9, null]], "Linux Installation": [[10, "linux-installation"]], "Creating a Live Linux image": [[10, "creating-a-live-linux-image"]], "Installing Kali Linux": [[10, "installing-kali-linux"]], "Prerequisites": [[10, "prerequisites"], [11, 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"module-chipsec.modules.common.cpu.cpu_info"]], "ia_untrusted module": [[147, "module-chipsec.modules.common.cpu.ia_untrusted"]], "spectre_v2 module": [[148, "module-chipsec.modules.common.cpu.spectre_v2"]], "debugenabled module": [[149, "module-chipsec.modules.common.debugenabled"]], "ia32cfg module": [[150, "module-chipsec.modules.common.ia32cfg"]], "me_mfg_mode module": [[151, "module-chipsec.modules.common.me_mfg_mode"]], "memconfig module": [[152, "module-chipsec.modules.common.memconfig"]], "memlock module": [[153, "module-chipsec.modules.common.memlock"]], "remap module": [[154, "module-chipsec.modules.common.remap"]], "rtclock module": [[155, "rtclock-module"]], "secureboot package": [[156, "secureboot-package"], [178, "secureboot-package"]], "variables module": [[157, "module-chipsec.modules.common.secureboot.variables"]], "sgx_check module": [[158, "module-chipsec.modules.common.sgx_check"]], "smm module": [[159, "module-chipsec.modules.common.smm"]], "smm_code_chk module": [[160, "module-chipsec.modules.common.smm_code_chk"]], "smm_dma module": [[161, "module-chipsec.modules.common.smm_dma"]], "smrr module": [[162, "module-chipsec.modules.common.smrr"]], "spd_wd module": [[163, "module-chipsec.modules.common.spd_wd"]], "spi_access module": [[164, "module-chipsec.modules.common.spi_access"]], "spi_desc module": [[165, "module-chipsec.modules.common.spi_desc"]], "spi_fdopss module": [[166, "module-chipsec.modules.common.spi_fdopss"]], "spi_lock module": [[167, "module-chipsec.modules.common.spi_lock"]], "uefi package": [[168, "uefi-package"], [183, "uefi-package"]], "access_uefispec module": [[169, "module-chipsec.modules.common.uefi.access_uefispec"]], "s3bootscript module": [[170, "module-chipsec.modules.common.uefi.s3bootscript"]], "hsw package": [[171, "module-chipsec.modules.hsw"]], "ivb package": [[172, "module-chipsec.modules.ivb"]], "snb package": [[173, "module-chipsec.modules.snb"]], "tools package": [[174, "tools-package"]], "sinkhole module": [[176, "module-chipsec.modules.tools.cpu.sinkhole"]], "generate_test_id module": [[177, "module-chipsec.modules.tools.generate_test_id"]], "te module": [[179, "module-chipsec.modules.tools.secureboot.te"]], "smm package": [[180, "smm-package"]], "rogue_mmio_bar module": [[181, "module-chipsec.modules.tools.smm.rogue_mmio_bar"]], "smm_ptr module": [[182, "module-chipsec.modules.tools.smm.smm_ptr"]], "reputation module": [[184, "module-chipsec.modules.tools.uefi.reputation"]], "s3script_modify module": [[185, "module-chipsec.modules.tools.uefi.s3script_modify"]], "scan_blocked module": [[186, "module-chipsec.modules.tools.uefi.scan_blocked"]], "scan_image module": [[187, "module-chipsec.modules.tools.uefi.scan_image"]], "uefivar_fuzz module": [[188, "module-chipsec.modules.tools.uefi.uefivar_fuzz"]], "vmm package": [[189, "vmm-package"]], "common module": [[190, "module-chipsec.modules.tools.vmm.common"]], "cpuid_fuzz module": [[191, "module-chipsec.modules.tools.vmm.cpuid_fuzz"]], "ept_finder module": [[192, "module-chipsec.modules.tools.vmm.ept_finder"]], "hv package": [[193, "hv-package"]], "define module": [[194, "module-chipsec.modules.tools.vmm.hv.define"], [210, "module-chipsec.modules.tools.vmm.xen.define"]], "hypercall module": [[195, "module-chipsec.modules.tools.vmm.hv.hypercall"], [211, "module-chipsec.modules.tools.vmm.xen.hypercall"]], "hypercallfuzz module": [[196, "module-chipsec.modules.tools.vmm.hv.hypercallfuzz"], [201, "module-chipsec.modules.tools.vmm.hypercallfuzz"], [212, "module-chipsec.modules.tools.vmm.xen.hypercallfuzz"]], "synth_dev module": [[197, "module-chipsec.modules.tools.vmm.hv.synth_dev"]], "synth_kbd module": [[198, "module-chipsec.modules.tools.vmm.hv.synth_kbd"]], "vmbus module": [[199, "module-chipsec.modules.tools.vmm.hv.vmbus"]], "vmbusfuzz module": [[200, "module-chipsec.modules.tools.vmm.hv.vmbusfuzz"]], "iofuzz module": [[202, "module-chipsec.modules.tools.vmm.iofuzz"]], "msr_fuzz module": [[203, "module-chipsec.modules.tools.vmm.msr_fuzz"]], "pcie_fuzz module": [[204, "module-chipsec.modules.tools.vmm.pcie_fuzz"]], "pcie_overlap_fuzz module": [[205, "module-chipsec.modules.tools.vmm.pcie_overlap_fuzz"]], "vbox package": [[206, "vbox-package"]], "vbox_crash_apicbase module": [[207, "module-chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase"]], "venom module": [[208, "module-chipsec.modules.tools.vmm.venom"]], "xen package": [[209, "xen-package"]], "xsa188 module": [[213, "module-chipsec.modules.tools.vmm.xen.xsa188"]], "wsmt module": [[214, "module-chipsec.modules.tools.wsmt"]], "options module": [[215, "module-chipsec.options"]], "parsers module": [[216, "module-chipsec.parsers"]], "testcase module": [[217, "module-chipsec.testcase"]], "utilcmd package": [[218, "utilcmd-package"]], "acpi_cmd module": [[219, "module-chipsec.utilcmd.acpi_cmd"]], "chipset_cmd module": [[220, "module-chipsec.utilcmd.chipset_cmd"]], "cmos_cmd module": [[221, "module-chipsec.utilcmd.cmos_cmd"]], "config_cmd module": [[222, "module-chipsec.utilcmd.config_cmd"]], "cpu_cmd module": [[223, "module-chipsec.utilcmd.cpu_cmd"]], "decode_cmd module": [[224, "module-chipsec.utilcmd.decode_cmd"]], "deltas_cmd module": [[225, "module-chipsec.utilcmd.deltas_cmd"]], "desc_cmd module": [[226, "module-chipsec.utilcmd.desc_cmd"]], "ec_cmd module": [[227, "module-chipsec.utilcmd.ec_cmd"]], "igd_cmd module": [[228, "module-chipsec.utilcmd.igd_cmd"]], "interrupts_cmd module": [[229, "module-chipsec.utilcmd.interrupts_cmd"]], "io_cmd module": [[230, "module-chipsec.utilcmd.io_cmd"]], "iommu_cmd module": [[231, "module-chipsec.utilcmd.iommu_cmd"]], "lock_check_cmd module": [[232, "module-chipsec.utilcmd.lock_check_cmd"]], "mem_cmd module": [[233, "module-chipsec.utilcmd.mem_cmd"]], "mmcfg_base_cmd module": [[234, "module-chipsec.utilcmd.mmcfg_base_cmd"]], "mmcfg_cmd module": [[235, "module-chipsec.utilcmd.mmcfg_cmd"]], "mmio_cmd module": [[236, "module-chipsec.utilcmd.mmio_cmd"]], "msgbus_cmd module": [[237, "module-chipsec.utilcmd.msgbus_cmd"]], "msr_cmd module": [[238, "module-chipsec.utilcmd.msr_cmd"]], "pci_cmd module": [[239, "module-chipsec.utilcmd.pci_cmd"]], "reg_cmd module": [[240, "module-chipsec.utilcmd.reg_cmd"]], "smbios_cmd module": [[241, "module-chipsec.utilcmd.smbios_cmd"]], "smbus_cmd module": [[242, "module-chipsec.utilcmd.smbus_cmd"]], "spd_cmd module": [[243, "module-chipsec.utilcmd.spd_cmd"]], "spi_cmd module": [[244, "module-chipsec.utilcmd.spi_cmd"]], "spidesc_cmd module": [[245, "module-chipsec.utilcmd.spidesc_cmd"]], "tpm_cmd module": [[246, "module-chipsec.utilcmd.tpm_cmd"]], "txt_cmd module": [[247, "module-chipsec.utilcmd.txt_cmd"]], "ucode_cmd module": [[248, "module-chipsec.utilcmd.ucode_cmd"]], "uefi_cmd module": [[249, "module-chipsec.utilcmd.uefi_cmd"]], "vmem_cmd module": [[250, "module-chipsec.utilcmd.vmem_cmd"]], "vmm_cmd module": [[251, "module-chipsec.utilcmd.vmm_cmd"]], "Contact": [[252, "contact"]], "Download CHIPSEC": [[253, "download-chipsec"]], "GitHub repository": [[253, "github-repository"]], "Releases": [[253, "releases"]], "Python": [[253, "python"]], "Interpreting results": [[254, "interpreting-results"]], "Results": [[254, "results"]], "Generic results meanings": [[254, "id2"]], "Automated Tests": [[254, "automated-tests"]], "Modules results meanings": [[254, "id3"]], "Tools": [[254, "tools"]], "Running CHIPSEC": [[255, "running-chipsec"]], "Running in Shell": [[255, "running-in-shell"]], "Using as a Python Package": [[255, "using-as-a-python-package"]], "chipsec_main options": [[255, "chipsec-main-options"]], "chipsec_util options": [[255, "chipsec-util-options"]]}, "indexentries": {"chipsec.cfg.parsers": [[68, "module-chipsec.cfg.parsers"]], "module": [[68, "module-chipsec.cfg.parsers"], [69, "module-chipsec.cfg.parsers.core_parsers"], [70, "module-chipsec.config"], [71, "module-chipsec.fuzzing"], [72, "module-chipsec.fuzzing.primitives"], [73, "module-chipsec.hal"], [74, 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"chipsec.cfg.parsers.core_parsers": [[69, "module-chipsec.cfg.parsers.core_parsers"]], "chipsec.config": [[70, "module-chipsec.config"]], "chipsec.fuzzing": [[71, "module-chipsec.fuzzing"]], "chipsec.fuzzing.primitives": [[72, "module-chipsec.fuzzing.primitives"]], "chipsec.hal": [[73, "module-chipsec.hal"]], "chipsec.hal.acpi": [[74, "module-chipsec.hal.acpi"]], "chipsec.hal.acpi_tables": [[75, "module-chipsec.hal.acpi_tables"]], "chipsec.hal.cmos": [[76, "module-chipsec.hal.cmos"]], "chipsec.hal.cpu": [[77, "module-chipsec.hal.cpu"]], "chipsec.hal.cpuid": [[78, "module-chipsec.hal.cpuid"]], "chipsec.hal.ec": [[79, "module-chipsec.hal.ec"]], "chipsec.hal.hal_base": [[80, "module-chipsec.hal.hal_base"]], "chipsec.hal.igd": [[81, "module-chipsec.hal.igd"]], "chipsec.hal.interrupts": [[82, "module-chipsec.hal.interrupts"]], "chipsec.hal.io": [[83, "module-chipsec.hal.io"]], "chipsec.hal.iobar": [[84, "module-chipsec.hal.iobar"]], "chipsec.hal.iommu": [[85, "module-chipsec.hal.iommu"]], "chipsec.hal.locks": [[86, "module-chipsec.hal.locks"]], "chipsec.hal.mmio": [[87, "module-chipsec.hal.mmio"]], "chipsec.hal.msgbus": [[88, "module-chipsec.hal.msgbus"]], "chipsec.hal.msr": [[89, "module-chipsec.hal.msr"]], "chipsec.hal.paging": [[90, "module-chipsec.hal.paging"]], "chipsec.hal.pci": [[91, "module-chipsec.hal.pci"]], "chipsec.hal.pcidb": [[92, "module-chipsec.hal.pcidb"]], "chipsec.hal.physmem": [[93, "module-chipsec.hal.physmem"]], "chipsec.hal.smbios": [[94, "module-chipsec.hal.smbios"]], "chipsec.hal.smbus": [[95, "module-chipsec.hal.smbus"]], "chipsec.hal.spd": [[96, "module-chipsec.hal.spd"]], "chipsec.hal.spi": [[97, "module-chipsec.hal.spi"]], "chipsec.hal.spi_descriptor": [[98, "module-chipsec.hal.spi_descriptor"]], "chipsec.hal.spi_jedec_ids": [[99, "module-chipsec.hal.spi_jedec_ids"]], "chipsec.hal.spi_uefi": [[100, "module-chipsec.hal.spi_uefi"]], "chipsec.hal.tpm": [[101, "module-chipsec.hal.tpm"]], "chipsec.hal.tpm12_commands": [[102, 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"chipsec.modules.tools.vmm.common": [[190, "module-chipsec.modules.tools.vmm.common"]], "chipsec.modules.tools.vmm.cpuid_fuzz": [[191, "module-chipsec.modules.tools.vmm.cpuid_fuzz"]], "chipsec.modules.tools.vmm.ept_finder": [[192, "module-chipsec.modules.tools.vmm.ept_finder"]], "chipsec.modules.tools.vmm.hv": [[193, "module-chipsec.modules.tools.vmm.hv"]], "chipsec.modules.tools.vmm.hv.define": [[194, "module-chipsec.modules.tools.vmm.hv.define"]], "chipsec.modules.tools.vmm.hv.hypercall": [[195, "module-chipsec.modules.tools.vmm.hv.hypercall"]], "chipsec.modules.tools.vmm.hv.hypercallfuzz": [[196, "module-chipsec.modules.tools.vmm.hv.hypercallfuzz"]], "chipsec.modules.tools.vmm.hv.synth_dev": [[197, "module-chipsec.modules.tools.vmm.hv.synth_dev"]], "chipsec.modules.tools.vmm.hv.synth_kbd": [[198, "module-chipsec.modules.tools.vmm.hv.synth_kbd"]], "chipsec.modules.tools.vmm.hv.vmbus": [[199, "module-chipsec.modules.tools.vmm.hv.vmbus"]], "chipsec.modules.tools.vmm.hv.vmbusfuzz": [[200, "module-chipsec.modules.tools.vmm.hv.vmbusfuzz"]], "chipsec.modules.tools.vmm.hypercallfuzz": [[201, "module-chipsec.modules.tools.vmm.hypercallfuzz"]], "chipsec.modules.tools.vmm.iofuzz": [[202, "module-chipsec.modules.tools.vmm.iofuzz"]], "chipsec.modules.tools.vmm.msr_fuzz": [[203, "module-chipsec.modules.tools.vmm.msr_fuzz"]], "chipsec.modules.tools.vmm.pcie_fuzz": [[204, "module-chipsec.modules.tools.vmm.pcie_fuzz"]], "chipsec.modules.tools.vmm.pcie_overlap_fuzz": [[205, "module-chipsec.modules.tools.vmm.pcie_overlap_fuzz"]], "chipsec.modules.tools.vmm.vbox": [[206, "module-chipsec.modules.tools.vmm.vbox"]], "chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase": [[207, "module-chipsec.modules.tools.vmm.vbox.vbox_crash_apicbase"]], "chipsec.modules.tools.vmm.venom": [[208, "module-chipsec.modules.tools.vmm.venom"]], "chipsec.modules.tools.vmm.xen": [[209, "module-chipsec.modules.tools.vmm.xen"]], "chipsec.modules.tools.vmm.xen.define": [[210, "module-chipsec.modules.tools.vmm.xen.define"]], "chipsec.modules.tools.vmm.xen.hypercall": [[211, "module-chipsec.modules.tools.vmm.xen.hypercall"]], "chipsec.modules.tools.vmm.xen.hypercallfuzz": [[212, "module-chipsec.modules.tools.vmm.xen.hypercallfuzz"]], "chipsec.modules.tools.vmm.xen.xsa188": [[213, "module-chipsec.modules.tools.vmm.xen.xsa188"]], "chipsec.modules.tools.wsmt": [[214, "module-chipsec.modules.tools.wsmt"]], "chipsec.options": [[215, "module-chipsec.options"]], "chipsec.parsers": [[216, "module-chipsec.parsers"]], "chipsec.testcase": [[217, "module-chipsec.testcase"]], "chipsec.utilcmd": [[218, "module-chipsec.utilcmd"]], "chipsec.utilcmd.acpi_cmd": [[219, "module-chipsec.utilcmd.acpi_cmd"]], "chipsec.utilcmd.chipset_cmd": [[220, "module-chipsec.utilcmd.chipset_cmd"]], "chipsec.utilcmd.cmos_cmd": [[221, "module-chipsec.utilcmd.cmos_cmd"]], "chipsec.utilcmd.config_cmd": [[222, "module-chipsec.utilcmd.config_cmd"]], "chipsec.utilcmd.cpu_cmd": [[223, "module-chipsec.utilcmd.cpu_cmd"]], "chipsec.utilcmd.decode_cmd": [[224, "module-chipsec.utilcmd.decode_cmd"]], "chipsec.utilcmd.deltas_cmd": [[225, "module-chipsec.utilcmd.deltas_cmd"]], "chipsec.utilcmd.desc_cmd": [[226, "module-chipsec.utilcmd.desc_cmd"]], "chipsec.utilcmd.ec_cmd": [[227, "module-chipsec.utilcmd.ec_cmd"]], "chipsec.utilcmd.igd_cmd": [[228, "module-chipsec.utilcmd.igd_cmd"]], "chipsec.utilcmd.interrupts_cmd": [[229, "module-chipsec.utilcmd.interrupts_cmd"]], "chipsec.utilcmd.io_cmd": [[230, "module-chipsec.utilcmd.io_cmd"]], "chipsec.utilcmd.iommu_cmd": [[231, "module-chipsec.utilcmd.iommu_cmd"]], "chipsec.utilcmd.lock_check_cmd": [[232, "module-chipsec.utilcmd.lock_check_cmd"]], "chipsec.utilcmd.mem_cmd": [[233, "module-chipsec.utilcmd.mem_cmd"]], "chipsec.utilcmd.mmcfg_base_cmd": [[234, "module-chipsec.utilcmd.mmcfg_base_cmd"]], "chipsec.utilcmd.mmcfg_cmd": [[235, "module-chipsec.utilcmd.mmcfg_cmd"]], "chipsec.utilcmd.mmio_cmd": [[236, "module-chipsec.utilcmd.mmio_cmd"]], "chipsec.utilcmd.msgbus_cmd": [[237, "module-chipsec.utilcmd.msgbus_cmd"]], "chipsec.utilcmd.msr_cmd": [[238, "module-chipsec.utilcmd.msr_cmd"]], "chipsec.utilcmd.pci_cmd": [[239, "module-chipsec.utilcmd.pci_cmd"]], "chipsec.utilcmd.reg_cmd": [[240, "module-chipsec.utilcmd.reg_cmd"]], "chipsec.utilcmd.smbios_cmd": [[241, "module-chipsec.utilcmd.smbios_cmd"]], "chipsec.utilcmd.smbus_cmd": [[242, "module-chipsec.utilcmd.smbus_cmd"]], "chipsec.utilcmd.spd_cmd": [[243, "module-chipsec.utilcmd.spd_cmd"]], "chipsec.utilcmd.spi_cmd": [[244, "module-chipsec.utilcmd.spi_cmd"]], "chipsec.utilcmd.spidesc_cmd": [[245, "module-chipsec.utilcmd.spidesc_cmd"]], "chipsec.utilcmd.tpm_cmd": [[246, "module-chipsec.utilcmd.tpm_cmd"]], "chipsec.utilcmd.txt_cmd": [[247, "module-chipsec.utilcmd.txt_cmd"]], "chipsec.utilcmd.ucode_cmd": [[248, "module-chipsec.utilcmd.ucode_cmd"]], "chipsec.utilcmd.uefi_cmd": [[249, "module-chipsec.utilcmd.uefi_cmd"]], "chipsec.utilcmd.vmem_cmd": [[250, "module-chipsec.utilcmd.vmem_cmd"]], "chipsec.utilcmd.vmm_cmd": [[251, "module-chipsec.utilcmd.vmm_cmd"]]}}) \ No newline at end of file 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,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,158],base_primit:18,basecommand:[7,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],baseconfighelp:121,baseconfigpars:[15,121],basehelp:[59,62,64,66,70,71,74],basemodul:[0,3,6,8,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],basic:[13,94,148,159],bbbb:153,bc:[2,3,126,144],bcalcsiz:37,bcdedit:12,bcdrev:40,bdf:97,bdw:[8,82],becaus:94,been:[0,5,105,107,109,158],befor:[0,10],begin:0,behavior:[0,108],being:8,below:[12,158],bert:21,best:12,beta:9,between:[0,1,89],bgrt:21,bgsm:107,bild:2,bin:[123,128,133,137,148,149,152,153,154],binari:[12,18,44,128,148],binary_bios_measur:150,binaryio:49,bing:88,binpath:12,bio:[2,3,8,12,13,49,86,87,88,89,105,107,108,113,148,153,158],bios_char:40,bios_debug:97,bios_kbrd_buff:[8,82,85,158],bios_msg_ack:97,bios_region_bas:51,bios_region_s:51,bios_se_svn:104,bios_se_svn_statu:104,bios_smi:[8,82,85,158],bios_t:[8,82,85,158],bios_wp:[8,82,85,158,159],biosinterfacelockdown:[2,88],bioslocken:[3,89,144],biosw:[2,89],bioswriteen:[87,89,144],bit:[2,9,18,39,75,89,90,94,95,97,99,106,109,137,154],bit_count:18,bit_field:18,bit_mask:77,bit_num:77,bit_set:52,bitlength:74,ble:[3,89,144],blob:[13,40,97,99,151],block:[8,89,108],blog:[56,97],blogspot:94,blue:12,bool:[20,21,23,25,27,30,31,33,36,37,39,40,41,42,43,44,46,50,51,52,54,55,56,57,60,62,64,66,70,71,72,74,77,79,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,127,128],boot:[10,12,13,52,86,87,88,89,103,107,116,151,158],boot_options_pres:97,bootabl:9,bootmgr:12,bootregion:21,bootscript:116,bootscript_entri:116,bootscript_pa:116,bootservic:52,bootx64:13,border:18,bot:86,both:[89,153],bpo:0,brace:0,bracket:0,branch:94,broadwel:99,broken:2,brossard:86,brows:12,brra:111,brwa:[110,111],bs:103,bsaddress:116,bsod:12,bu:[2,12,21,32,33,34,37,60,62,64,66,69,70,71,74,139,141,143,155],buf:[39,43,57,62,64,71,74],buf_addr:28,buffer:[8,25,39,41,42,51,52,54,57,60,62,64,66,70,74,86,137,154,158],buffer_fil:[137,154],buffer_s:[60,62,64,66,70,74],bug:[0,156],build:[0,9,157],build_efi_file_tre:46,build_efi_model:46,build_efi_modules_tre:46,build_efi_tre:46,build_exe_:1,build_ext:[10,12,159],bus_detail:126,buswidthecc:42,butterworth:87,button:12,bwbr_process_cal:52,bwg:104,bypass:[86,89,111,113],byt:[8,82],byte_offset:125,byte_v:[125,131,146,147],byte_valu:[37,39,57],bytestostr:79,bytewis:62,c220:109,c5:94,c:[13,66,97,99,151],c_4level_page_t:36,c_extended_page_t:36,c_ia32e_page_t:36,c_pae_page_t:36,c_page:36,c_paging_memory_access:36,c_paging_with_2nd_level_transl:36,c_reverse_transl:36,c_translat:36,c_vtd_page_t:36,cach:[8,94,108,158],cachabl:108,cache_typ:[39,60,62,64,66,70,71,74],cacheabl:108,calc_bar_s:37,calc_hash:54,calcsiz:55,calcsum:54,calcul:18,calculatecrc32:52,call:[0,3,8,46,89,97,106],callabl:[0,46,56],can:[0,2,3,8,9,12,18,89,94,105,108,111,128,143,148,157,158,159],can_modifi:[103,115],can_read:32,cannot:[111,158],capabl:[1,48,150],caparea:48,capit:0,capitalization_with_underscor:0,capsul:[8,55],care:148,cashi:42,caslo:42,cccc:153,cd:[12,13],cdi:104,cee:36,certain:[0,3,9,89,115,158,159],certif:[8,12],cet:[8,82,85],cet_msr:90,cfg:[3,16],cfg_obj:[15,121],chain:0,chang:[0,9,12,43,89,108],channel:94,charact:[0,158],check:[0,1,5,6,8,70,86,87,88,89,93,94,95,97,99,100,104,105,106,107,108,109,110,111,112,113,115,116,136,158,159],check_bios_iface_lock:88,check_bios_keyboard_buff:86,check_bios_write_protect:89,check_cet:90,check_circular:46,check_cpu_debug_en:95,check_dci:95,check_dispatch_opcod:116,check_driver_handl:74,check_fd_security_override_strap:112,check_flash_access_permiss:[110,111],check_hardware_sequenc:43,check_ia32feature_control:96,check_lock:136,check_log:136,check_match_criteria:56,check_me_mfg_mod:97,check_memmap_lock:98,check_misconfig:36,check_msr_lt_lock_memori:99,check_prmrr_valu:104,check_remap_config:100,check_rul:56,check_s3_bootscript:116,check_secureboot_variable_attribut:103,check_sgx_config:104,check_smi_lock:87,check_smm_code_chk_en:106,check_smramc:105,check_smrr:108,check_smrr_support:23,check_spd_wd:109,check_spectre_mitig:94,check_spi_lock:113,check_spi_protected_rang:89,check_tseg_config:107,check_tseg_lock:107,check_untrust:93,check_var:115,check_vmm:23,checkall_lock:136,checker:0,checkev:52,checksum:[20,50,54],chipsec:[1,2,3,4,6,7,11,156,158],chipsec_hlpr:12,chipsec_main:[3,13,86,87,88,89,90,92,93,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],chipsec_py368_uefi_x64:13,chipsec_root:1,chipsec_root_dir:12,chipsec_toolscompress:12,chipsec_util:[7,8,12,13,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],chipset:[1,8,109],chipset_cmd:[1,122],chipsiz:42,choos:12,chosen:18,chunk:43,ci:151,circumst:9,circumv:105,clarifi:0,clariti:158,classmethod:[49,69],cleanup:1,clear:[8,89,158],client:[12,48,49,98,105,107],clone:[10,11,12],close:[66,70],closeev:52,closeprotocol:52,cmd:[12,135,143],cmo:[1,8,19,125],cmos_cmd:[1,122],cmos_dump:125,cmos_readh:125,cmos_readl:125,cmos_writeh:125,cmos_writel:125,cmoscommand:125,code:[1,3,9,10,12,35,72,105,106,108,151,156,159],collect:0,collis:0,colon:0,color:12,com:[10,11,12,13,34,38,42,92,94,96,97,99,106,151,156],comm_buffer_nested_ptr_protect:21,comma:0,command:[0,3,4,7,12,25,46,47,48,52,62,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,159],command_argv:[47,48],command_display_nam:7,command_paramet:150,commandclass:7,commandnam:[47,150],commandport:28,commbuff:8,commbuffinfo:21,comment:0,common:[1,2,3,4,8,18,51,52,82,158,159],commun:74,comparison:0,compat:[8,12,105,158],compil:12,complet:[12,18,48,158],compon:[9,12,20,21,26,40,47,51],compress:[10,12],compress_efi_binari:53,compress_imag:46,compressed_data:[46,53],compression_typ:[46,53,54],compresstyp:37,comput:[12,159],compute_ioctlbas:66,concaten:0,concept:8,conclus:158,condit:[0,8,12,89],config:[0,10,33,126,135,139],config_cmd:[1,122],config_data:121,configcommand:126,configur:[0,1,3,9,12,32,33,37,87,89,96,98,99,100,104,105,107,108,113,136,143,158,159],configurationt:52,confirm:158,confus:8,conin:52,connect:[9,95,159],connectcontrol:52,conout:52,consid:[0,110],consist:[0,94],consol:12,consoleinhandl:52,consoleouthandl:52,constant:0,construct:94,contact:9,contain:[0,8,9,128,148,158],content:[1,4,8,13,34,47,48,92,96,106,137,151,154,158],context:[0,52],continueselftest:[48,150],contribut:156,control:[2,3,8,11,12,25,41,87,88,89,94,95,96,107,109,110,112,113,158],control_detail:126,control_nam:144,convent:[0,49],convert:18,convertpoint:52,copernicu:113,copi:[3,12,13],copymem:52,core:[3,43,94,98,100,105,107],core_id:62,core_pars:14,core_support:121,coreboot:[97,99],coreconfig:15,corei:[87,116],cornwel:87,correct:[2,9,128],correctli:[3,8,89,98,107,128,158],correspond:[5,52,74,128],corrupt:103,could:[0,1,9,46,107,108,111,148,158],count:[52,133],counterintuit:0,cover:[13,89,158],cp:12,cpu:[1,5,8,13,19,28,35,43,50,70,82,85,99,105,106,107,108,127,158,159],cpu_cmd:[1,122],cpu_cpuid:127,cpu_cr:127,cpu_gcc:13,cpu_ia32:13,cpu_ia32_gcc:13,cpu_id:[130,152],cpu_info:[8,82,85,91,127,159],cpu_pt:127,cpu_thread_id:[23,35,50,60,62,64,66,70,71,74],cpu_topolog:127,cpucommand:127,cpuid:[1,5,16,19,23,56,59,60,62,64,66,67,70,71,74,90,94,127],cpuid_struct:68,cpuintnumb:21,cpunum:70,cpython:13,cr3:23,cr:127,cr_number:[23,60,62,64,66,70,71,74,127],crc32:52,creat:[3,8,9,12,13,49,60,62,64,66,70,71,74,128,148,159],create_s3bootscript_entry_buff:55,createev:52,createeventex:52,creation:[13,18],creatorid:20,creatorrevis:20,credenti:12,criteria:56,critic:[8,9,128],cryptograph:48,cs:[3,20,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,43,44,47,50,51,57,58,104,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],cse:97,cseg:105,csm:8,ctl_code:74,current:[0,3,5,48,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,128,129],cust_support:121,cve:94,cycl:43,d2000:34,d719b2cb:153,d:[36,58,156,158,159],d_lck:[105,158],d_open:158,dad00e67656f:153,dal:[9,59],dal_vers:62,dalhelp:[59,61],dam:[34,151],data1:115,data2:115,data:[0,8,25,28,34,38,40,43,46,47,52,55,71,89,94,103,105,115,128],data_byte_count:43,data_list:0,data_s:50,dataclass:0,dataoffset:74,dataport:28,datas:[47,51,55,71,74],datasheet:[3,34,109],datastructur:21,date:[0,50],db:[52,80,153],dbc:43,dci:95,dci_control_reg:95,dd:80,dddd:153,ddisable_integrity_check:12,deadbeef:132,death:12,debian:10,debug:[0,95,111,159],debugelock:95,debugen:[8,82,85],debugeoccur:95,debuglock:136,decid:89,decim:18,declar:0,decod:[20,21,40,42,97,128,145,148,152,153],decode_cmd:[1,122],decode_dir:52,decode_efi_vari:51,decode_rom:128,decode_s3bs_opcod:55,decode_s3bs_opcode_def:55,decode_s3bs_opcode_edkcompat:55,decode_typ:128,decode_uefi_region:46,decodecommand:128,decodesect:54,decompress:8,decompress_efi_binari:53,decompress_section_data:46,decompression_oder_type1:53,decompression_oder_type2:53,decor:0,def:[4,6,7,18,46],def_handl:121,defcon:86,defeat:87,defend:12,defin:[0,1,2,3,12,32,90,97,105,106,109,111,115,136,158],definit:48,del_pag:36,delet:[8,12,60,62,64,66,70,71,74,153],delete_efi_vari:[51,60,62,64,66,70,71,74],delim:18,dell:151,delta:[1,129,159],deltas_cmd:[1,122],deltascommand:129,demonstr:[89,108],deni:12,densiti:42,depend:[10,13,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],deploi:9,deprec:[9,10,11,12,159],depric:5,deriv:0,desc:[2,3,36,90],desc_cmd:[1,122],desc_table_cod:[60,62,64,66,70,71,74],describ:[13,105],descript:[0,6,8],descriptor:[8,44,110,111,112,158],descriptor_table_code_idtr:35,design:[12,107],desir:10,detail:[3,12,47,116],detect:[1,2,9,42,100,109,147,158],determin:158,dev:[2,10,33,37,66,69,70,74,156],dev_mem:[66,70],dev_port:[66,70],devdata:121,devel:10,develop:[12,92,96,106],devic:[5,8,9,12,27,37,38,42,45,47,58,60,62,64,66,70,71,74,107,109,111,139,143,155],device_addr:[146,147],device_cfg:121,device_nam:66,devicescop:21,devicetyp:[42,74],devmem_avail:70,devmsr_avail:70,devport_avail:70,dfx:62,dict:[20,23,36,43,45,46,51,55,56,60,64,66,71,74,126,127],dictionari:0,did:37,diff_var:115,differ:94,difficult:0,dig:88,digest:49,digit:8,dimm0:147,dimm2:147,direct:[1,9,95,107,134,137,139,142,143,154],directli:4,directori:[3,8,12,13,128],disabl:[8,12,13,89,95,109,135,136,148,158],disable_bios_write_protect:43,disconnectcontrol:52,discord:156,discoverrangebaseadd:21,discoverrangelength:21,disk:[12,158],dispatch:[8,52,158],displai:[92,138,159],display_bios_region:43,display_bios_write_protect:43,display_smbus_info:41,display_spi_flash_descriptor:43,display_spi_flash_region:43,display_spi_map:43,display_spi_opcode_info:43,display_spi_protected_rang:43,display_spi_ranges_access_permiss:43,displaybootmenu:12,displaynam:12,distribut:[9,10,11,12],distutil:9,dkm:66,dkms_dir:66,dma:[8,107,132,158],dmar:21,dmaread:132,dmawrit:132,dmytro:116,dnf:10,do_modifi:[103,108,115],doc:[34,42],docrev:40,docstr:0,document:[0,8,151],doe:[90,107,128,136,158],doesn:[8,12,94,158],domain:70,don:[158,159],done:[9,97],doubl:0,doubt:0,down:[2,87,97,98,158],download:[9,10,11,12,13],dq:80,draft:158,dram:[42,107],dram_device_type_nam:42,dram_typ:42,drive:[9,10],driver:[1,9,10,70,72,74,157,159],driver_exhist:62,drvier:12,duck:0,due:[8,9,12],dump:[8,12,22,30,125,128,131,140,143,147,148,151],dump_access:47,dump_acpi_t:20,dump_bar:140,dump_bar_ab:140,dump_descriptor_t:35,dump_devic:58,dump_didvid:47,dump_efi_modul:46,dump_efi_t:51,dump_efi_variables_from_spi:51,dump_ept_page_t:58,dump_ggtt_pt:27,dump_high:22,dump_intcap:47,dump_inten:47,dump_io:29,dump_io_bar:30,dump_iommu_configur:31,dump_iommu_page_t:31,dump_iommu_statu:31,dump_low:22,dump_mmio:33,dump_mmio_bar:33,dump_page_t:23,dump_page_tables_al:23,dump_pci_config:37,dump_region_to_path:137,dump_regist:47,dump_rid:47,dump_spd_rom:42,dump_statu:[47,97],dump_ucode_update_head:50,dunder:0,durat:52,dure:8,dw:80,dword:[18,137,143,154,159],dword_valu:[37,39,57,62],e:[10,159],each:[0,8,35,40,50,115,158],earliest:0,easier:0,eax:[23,24,35,60,62,64,66,68,70,71,74,94,127,142,155],ebx:[68,155],ec:[1,19,131,139],ec_cmd:[1,122],eccommand:131,ecentri:33,ecoff:33,ecx:[23,24,60,62,64,66,68,70,71,74,94,127,155],ed32d533:133,edi:155,edk2:13,edk2modul:13,edx:[35,60,62,64,66,68,70,71,74,94,142,155],eeeeeeeeeeee:153,eeprom:42,effect:108,effort:158,efi:[0,13,49,52,55,56,59,104,116,153,158],efi_abort:52,efi_access_deni:52,efi_already_start:52,efi_bad_buffer_s:52,efi_boot_script_dispatch_2_opcod:52,efi_boot_script_dispatch_opcod:52,efi_boot_script_information_opcod:52,efi_boot_script_io_poll_opcod:52,efi_boot_script_io_read_write_opcod:52,efi_boot_script_io_write_opcod:52,efi_boot_script_mem_poll_opcod:52,efi_boot_script_mem_read_write_opcod:52,efi_boot_script_mem_write_opcod:52,efi_boot_script_pci_config2_poll_opcod:52,efi_boot_script_pci_config2_read_write_opcod:52,efi_boot_script_pci_config2_write_opcod:52,efi_boot_script_pci_config_poll_opcod:52,efi_boot_script_pci_config_read_write_opcod:52,efi_boot_script_pci_config_write_opcod:52,efi_boot_script_smbus_execute_opcod:52,efi_boot_script_stall_opcod:52,efi_boot_script_table_opcod:52,efi_boot_script_terminate_opcod:52,efi_boot_script_type_default:55,efi_boot_script_type_edkcompat:55,efi_boot_script_width_uint16:52,efi_boot_script_width_uint32:52,efi_boot_script_width_uint64:52,efi_boot_script_width_uint8:52,efi_boot_services_t:52,efi_buffer_too_smal:52,efi_compromised_data:52,efi_configuration_t:[51,52],efi_crc_error:52,efi_data_search:46,efi_device_error:52,efi_dxe_services_t:52,efi_end_of_fil:52,efi_end_of_media:52,efi_error_str:52,efi_fil:[46,54],efi_fv:54,efi_fw_type_evsa:55,efi_fw_type_nvar:55,efi_fw_type_uefi:55,efi_fw_type_uefi_auth:55,efi_fw_type_vss2:55,efi_fw_type_vss2_auth:55,efi_fw_type_vss:55,efi_fw_type_vss_appl:55,efi_fw_type_vss_auth:55,efi_guid_str:52,efi_hdr_nvar1:55,efi_hdr_vss:55,efi_hdr_vss_appl:55,efi_hdr_vss_auth:55,efi_hdr_win:74,efi_http_error:52,efi_icmp_error:52,efi_incompatible_vers:52,efi_invalid_languag:52,efi_invalid_paramet:52,efi_load_error:52,efi_media_chang:52,efi_modul:[46,54,56],efi_no_map:52,efi_no_media:52,efi_no_respons:52,efi_not_found:52,efi_not_readi:52,efi_not_start:52,efi_nvram_format:51,efi_out_of_resourc:52,efi_protocol_error:52,efi_runtime_services_t:52,efi_sect:[46,54,56],efi_security_viol:52,efi_statu:52,efi_success:52,efi_support:[60,62,64,66,70,71,74],efi_system_t:[51,52],efi_system_table_revis:52,efi_table_head:[51,52],efi_tftp_error:52,efi_timeout:52,efi_unsupport:52,efi_var:51,efi_var_stor:51,efi_variable_fil:153,efi_variable_head:55,efi_variable_header_auth:55,efi_variable_header_auth_s:55,efi_variable_header_s:55,efi_vendor_t:52,efi_volume_corrupt:52,efi_volume_ful:52,efi_warn_buffer_too_smal:52,efi_warn_delete_failur:52,efi_warn_file_system:52,efi_warn_stale_data:52,efi_warn_unknown_glyph:52,efi_warn_write_failur:52,efi_write_protect:52,efi_xrom_head:37,eficompressor:12,efifirmwareblob:49,efihelp:[59,63],efiimageheaderoffset:37,efimachinetyp:37,efimoduletyp:46,efisignatur:37,efisubsystem:37,efit:51,efitabletyp:51,efivar_evsa:55,efivariabletyp:[51,60,64,66,71],eg:[0,6,89],einj:21,eiss:89,either:89,elfutil:10,els:[0,3,46],email:156,embed:25,emploi:0,empti:[128,158],en:[11,12,37,42,92,96,106,151],enabl:[0,2,3,8,9,12,13,33,47,87,89,94,95,97,104,106,108,109,135,158],enable_cache_address_resolut:33,enable_smbus_host_control:41,encapsul:28,encod:[0,18,46],encode_s3bootscript_entri:55,encode_s3bs_opcod:55,encode_s3bs_opcode_def:55,encode_s3bs_opcode_edkcompat:55,encompass:70,encount:12,encourag:[0,3],encrypt:158,end:[9,28,70,158],endian:18,enforc:12,engin:[31,135],enhanc:[94,158],ensur:89,ensure_ascii:46,entir:[89,148,158],entri:[36,40,55,158],entry_nam:56,entryc:40,entrylen:40,entrypoint:[52,145],entryrev:40,enum_devic:16,enumer:[5,12,37,94,121,143],enumerate_devic:37,enumerate_xrom:37,enumerationid:21,environ:[0,9,72,103],ept:[36,155],ept_point:155,eptp:58,equival:9,eras:148,erase_spi_block:43,error:[0,8,12,40,52,99,158],error_cod:97,erst:21,esi:155,especi:3,essenti:10,et_nod:[15,121],etc:[4,8,52,55,128,148],evalu:0,even:[0,94,105,159],event:[8,49,87],event_s:49,event_typ:49,eventtyp:49,everi:8,evid:0,evsa:55,ex:12,examin:[107,158],exampl:[0,3,7,8,9,12,46,86,87,88,89,90,92,93,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,123,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,152,153,154,155,159],except:[0,4,12,46,159],exchang:8,execut:[6,8,9,48,94,106,107,108,151,158],exhaust:18,exist:[0,9,49,89,159],exit:[52,159],exitbootservic:52,exp_siz:36,expand_pag:36,expans:[37,143],expect:[0,158],expens:0,explicit:0,explicitli:[0,97,159],exploit:[108,116],expos:158,exposur:86,express:0,extend:[0,18,36],extens:74,extheaderoffset:54,extra:[121,158],extract:13,f7:12,f8:12,f:[9,58],fadt:21,fail:[3,89,90,94,95,97,99,107,109,158,159],failfast:159,failur:[48,87,115,158],fall:5,fals:[0,6,16,18,20,36,37,40,46,51,52,55,62,66,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],famili:[49,109],fanci:18,faq:94,fat32:13,fd:44,fd_file:44,fdopss:112,fdv:110,featur:[0,8,12,95,96],fedora:10,fgo:144,field:[2,3,90],field_nam:144,file:[0,1,3,6,7,9,11,12,13,32,38,42,46,49,94,128,129,136,137,148,150,153,154,157,159],file_nam:132,file_path:123,filenam:[16,43,46,51,159],fileno:70,filetyp:[46,153],fill:[54,158],find:[8,153,157,158],find_acpi_smi_buff:28,find_efi_bootservices_t:51,find_efi_configuration_t:51,find_efi_dxeservices_t:51,find_efi_runtimeservices_t:51,find_efi_system_t:51,find_efi_t:51,find_efi_variable_stor:51,find_rsdp:20,find_s3_bootscript:51,find_smbios_t:40,find_smmc:28,find_thread:62,find_xrom:37,findal:46,finish:12,firmwar:[9,46,49,52,54,116,128,158],firmwarerevis:52,firmwarevendor:52,first:[2,3],fix:0,fixed_comm_buff:21,flag:[5,21,70],flake8:0,flash:[8,10,43,44,89,110,111,112,113,128,148,153,158],flash_address:148,flash_descriptor:148,flashlockdown:113,flashrom:113,flexibl:0,flmstr:44,flockdn:113,flow:0,flreg:43,flush_bar_address_cach:33,flushhintaddrstruct:21,fname:[46,51,52],fof:54,folder:4,follow:[0,8,10,12,13,49,94,95,97,99,109,148,156,157],forc:108,force_32bit:40,forceclear:[48,150],forens:[128,148],form:[8,18],formal:0,format:[0,13,18,49,55,128,129,152],formatarea0:40,formatarea1:40,formatarea2:40,formatarea3:40,formatarea4:40,forward:0,found:[3,8,106,157],fpt_bad:97,fr:156,framework:[8,9],frap:[110,111],free_phys_mem:[60,62,64,66,70,71,74],free_physical_mem:39,free_virtual_mem:57,freeform:153,freeiospac:52,freememoryspac:52,freepag:52,freepool:52,from:[0,1,6,7,10,12,13,38,48,49,62,80,89,94,103,107,108,128,137,148,151,154,158,159],fs0:13,fsguid:54,ft_bup_ld_flr:97,ftb:42,full:[148,158],full_rang:18,fulli:[0,70],fun:[2,33,37],func:[7,69,74],further:[10,158],furtur:0,fuzz:9,fuzz_librari:18,fuzzabl:18,fuzzer:[8,158],fv:46,fv_img:46,fv_mm:153,fvchecksum16:54,fvchecksum8:54,fvimag:54,fvlength:54,fvsum16:54,fvsum8:54,fw:128,fw_init_complet:97,fw_type:128,fwsts1:97,fwtype:[46,55,153],g:[10,159],ga:[21,28],gabriel:156,gain:47,garbag:158,gbe:158,gcc:10,gdt:[35,130],gdt_all:35,gdtcommand:130,gener:[0,1,3,4,12,18,28,38,47,89,156],get:[0,3,10,108,145],get_3b_siz:52,get_acpi_sdt:[60,62,64,66,70,71,74],get_acpi_t:[20,60,62,64,66,70,71,74],get_acpi_table_list:20,get_address_spac:36,get_affin:[60,62,64,66,70,71,74],get_attr:36,get_attr_str:51,get_auth_attr_str:51,get_available_help:72,get_base_help:72,get_bios_vers:70,get_bit:77,get_canon:36,get_chipset_cod:16,get_commbuf_info:21,get_common_xml:16,get_control:[3,144],get_cpu_core_count:35,get_cpu_thread_count:[35,50],get_cpu_topolog:23,get_cpuid_valu:90,get_datetime_str:79,get_decoded_struct:40,get_default_help:72,get_desc_table_regist:35,get_descriptor_t:[60,62,64,66,70,71,74],get_device_bar:37,get_device_name_by_didvid:37,get_didvid:37,get_dkms_module_loc:66,get_dsdt_address_to_us:21,get_dsdt_from_fadt:20,get_efi_vari:[51,60,62,64,66,70,71,74],get_efi_variable_ful:[64,74],get_extended_cap:33,get_field:36,get_gdtr:35,get_ggtt_bas:27,get_ggtt_pte_from_pa:27,get_ggtt_pte_from_pa_gen8:27,get_ggtt_pte_from_pa_legaci:27,get_gmadr:27,get_gttmmadr:27,get_guid_bin:54,get_head:40,get_header_typ:37,get_help:[62,64,66,70,72,74],get_idtr:35,get_info:[21,60,71,121],get_inst:69,get_io_bar_base_address:30,get_iommu_base_address:31,get_ldtr:35,get_lock:32,get_mem_rang:36,get_metadata:[15,121],get_mmcfg_base_address:33,get_mmio_bar_base_address:33,get_number_logical_processor_per_cor:23,get_number_logical_processor_per_packag:23,get_number_physical_processor_per_packag:23,get_number_sockets_from_apic_t:23,get_number_threads_from_apic_t:23,get_nvar_nam:52,get_pa_from_pt:27,get_pa_from_pte_gen8:27,get_pa_from_pte_legaci:27,get_page_is_ram:66,get_pages_by_physaddr:36,get_parse_acpi_t:20,get_pch_cod:16,get_phys_mem_access_prot:66,get_proc_info:24,get_pte_s:27,get_raw_struct:40,get_reverse_transl:36,get_s3_bootscript:51,get_sdt:20,get_section_data:120,get_smbus_base_address:41,get_smbus_hcfg:41,get_smram:23,get_smrr:23,get_smrr_smram:23,get_spi_flash_descriptor:44,get_spi_jedec_id:43,get_spi_jedec_id_decod:43,get_spi_mast:44,get_spi_mmio_bas:43,get_spi_protected_rang:43,get_spi_region:[43,44],get_spi_sfdp:43,get_stag:[15,121],get_string_list:40,get_structure_ap:21,get_table_list_from_sdt:20,get_threads_count:[60,62,64,66,70,71,74],get_tool_info:[62,64,66],get_tools_path:72,get_transl:36,get_tseg:23,get_vendor_name_by_vid:37,get_virt_addr:36,get_virtio_devic:58,get_vsec:33,getcap:[48,150],getcwd:72,getdramdevicetyp:42,getefivariables_ntenumeratesystemenvironmentvaluesex2:74,getefivariables_nvar:55,getefivariables_nvar_simpl:55,getefivariables_uefi:55,getefivariables_uefi_auth:55,getefivariables_vss2:55,getefivariables_vss2_auth:55,getefivariables_vss:55,getefivariables_vss_appl:55,getefivariables_vss_auth:55,getfvhead:54,getiospacedescriptor:52,getiospacemap:52,getmemorymap:52,getmemoryspacedescriptor:52,getmemoryspacemap:52,getmoduletyp:42,getnexthighmonotoniccount:52,getnextmonotoniccount:52,getnextvariablenam:52,getnvstore_efi:55,getnvstore_efi_auth:55,getnvstore_evsa:55,getnvstore_nvar:55,getnvstore_nvar_simpl:55,getnvstore_vss2:55,getnvstore_vss2_auth:55,getnvstore_vss:55,getnvstore_vss_appl:55,getnvstore_vss_auth:55,getphi:154,gettim:52,getvari:52,getwakeuptim:52,gfx_aperture_dma_read:27,gfx_aperture_dma_read_writ:27,gfxvtd:135,gg:156,gich:21,gicid:21,gicmsiframeid:21,gicrbaseaddress:21,gicv:21,git:[10,11,12],github:[10,11,12,13,38,97,99,151,156],given:18,global:[87,115],globalsysintbas:21,globalsysteminterrupt:21,go:12,goal:0,good:0,googl:94,googleprojectzero:94,gouv:156,grammar:0,graphic:[8,27],great:0,group:[0,18],guard:[0,12],guid:[28,46,51,52,54,55,60,62,64,66,70,71,74,103,115,133,151,153],guidelin:0,guidstr:64,h:[97,99,159],ha:[0,5,10,11,12,32,95,109,158],hal:[0,3,116,159],hal_bas:[1,19,20,22,23,24,25,27,28,30,31,32,33,34,39,40,41,43,47,51,57],halbas:[20,22,23,24,25,26,27,28,30,31,32,33,34,39,40,41,43,47,51,57],handl:[6,8,40],handle_control:15,handle_ima:15,handle_info:15,handle_io:15,handle_lock:15,handle_memori:15,handle_mmio:15,handle_pci:15,handle_regist:15,handleprotocol:52,handler:89,hang:[8,9],happen:0,hard:0,hardwar:[9,12,74,94,97,109,158,159],has_config:32,hash:0,haswel:[3,43],have:[0,12,94,105,107,115,156,158],hbbi28siiihh8:55,hbbiiiihh8:55,hdcien:95,hdd:[86,158],header:[0,8,10,21,37],header_vers:50,headerlength:54,headers:[52,54],help:[0,3,159],helper:[1,9,12,159],here:[97,157],hest:21,heurist:18,hex:[1,159],hf:97,hidden:136,hierarchi:37,higher:[9,10,11,12],highli:13,highlight:0,hijack:88,hint:9,horn:94,how:12,howev:89,hsf:[110,112,113],hsfc:144,hsw:[3,8,82],html:[92,94,96,97,106],http:[10,11,12,13,34,38,42,47,74,92,94,96,97,99,106,151,156,157],hub:109,human:2,hypercal:[58,60,62,64,66,70,71,74,155],hypercall64_extended_fast:58,hypercall64_fast:58,hypercall64_five_arg:58,hypercall64_memory_bas:58,hypervisor:[12,58,100],hypervisor_input_valu:58,i386:12,i5:43,i:[4,5,10,12,29,30,36,37,134,159],ia32:96,ia32_arch_cap:94,ia32_bios_sign_id:92,ia32_debug_interfac:[95,104],ia32_feature_control:[96,104,158],ia32_s_cet:90,ia32_smrr_physbas:[107,108],ia32_smrr_physmask:[107,108],ia32_spec_ctrl:94,ia32_u_cet:90,ia32cfg:[8,82,85,158],ia32featurecontrollock:96,ia:[36,92,93,96,106],ia_untrust:[8,82,85,91,107],ibp:104,ibpb:94,ibr:[94,158],ibrs_al:94,icon:12,id:[0,38,45,47,152],id_s3bootscript_typ:55,identifi:[37,136],identify_efi_nvram:51,idt:[35,130],idt_al:35,idtcommand:130,igd:[1,19,132],igd_cmd:[1,122],igdcommand:132,ignor:[5,158],ignore_platform:159,imag:[8,46,54,56,128,148,153],immedi:[0,48],implement:[1,3,8,18,46,49,94,116],import_path:159,improv:[0,158],includ:[0,3,8,9,10,12,36,52,88,94,96,99,113,148,158,159],incompat:12,inconclus:158,inconsist:32,incorrect:9,indent:[0,46],index:[48,52,55,131,150],indic:[0,48,111],indirect:94,individu:[0,8,18],inf:13,infcl:74,influenc:0,info:[12,36,127,148,156,159],info_data:121,infodata:121,inform:[0,3,8,24,47,48,90,92,109,136,158,159],inherit:[0,3,8],init:[58,66,70],initep:37,initi:48,inits:37,inject:94,inl:69,insecur:8,insert_aft:153,insert_befor:153,insid:0,inspect:158,instal:[1,8,74,157,159],installconfigurationt:52,installmultipleprotocolinterfac:52,installprotocolinterfac:52,instanc:[0,49,69],instead:[0,94],instrcountentri:21,instruct:1,instrument:86,insuffici:8,int15:8,intanchor:40,intc:40,integ:18,integr:[12,27],intel:[3,5,11,27,34,43,62,76,92,94,96,97,99,106,108,109,116,151,156],interact:4,interconnect:12,interfac:[2,4,9,12,34,58,62,88,95,158],interleav:21,intern:8,interpol:0,interpret:[0,8,9],interrupt:[1,8,19,47],interrupts_cmd:[1,122],interrupttyp:21,introduc:0,invalid:8,invoc_reg:28,invok:[1,72],io:[1,19,33,134],io_cmd:[1,122],io_detail:126,io_list:134,io_port:[29,60,62,64,66,70,71,74,134],io_read:134,io_writ:134,ioapicaddr:21,ioapicid:21,iobar:[1,19],ioctl:66,iommu:[1,8,19,135],iommu_cmd:[1,122],iommu_config:135,iommu_dis:135,iommu_en:135,iommu_engin:[31,135],iommu_list:135,iommu_pt:135,iommu_statu:135,iommucommand:135,iosapicaddress:21,iosapicvector:21,iosf:34,irp:12,is64:37,is_acpi_table_pres:20,is_all_on:77,is_bigpag:36,is_dal:72,is_device_en:27,is_efi:72,is_efi_variable_authent:52,is_en:[27,37],is_hex:79,is_ht_act:23,is_ibecc_en:100,is_inside_smram:116,is_inside_spi:116,is_io_bar_defin:30,is_io_bar_en:30,is_iommu_engine_en:31,is_iommu_translation_en:31,is_legacy_gen:27,is_linux:72,is_lock:[32,136],is_maco:72,is_mmio_bar_defin:33,is_mmio_bar_en:33,is_mmio_bar_program:33,is_pch_req:16,is_pres:36,is_print:79,is_rsdp_valid:21,is_set:77,is_smbus_en:41,is_smbus_host_controller_en:41,is_smbus_support:41,is_support:[3,6,8,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],is_translation_exist:36,is_variable_attribut:52,is_variable_st:55,is_win8_or_great:72,is_window:72,is_xsdt:20,isascii:52,iscorrectvsstyp:55,isecc:42,isfil:20,ismmio:37,isspdpres:42,issu:[0,9,12,89,105,107,156,158],item:[0,18],iter:[46,49,66,79],its:[0,9,52,80,159],itself:111,ityp:66,ivb:[8,82],j:159,jann:94,jede:45,jedec:[42,148],jedec_id:45,joanna:100,john:87,jonathan:86,json:[1,46,129,159],jsonencod:46,juli:[12,34],jumper:112,june:[10,11,12],junit:159,just:[8,107,158],k:[94,159],kallenberg:[87,116],kb4568831:12,keep:70,kei:[0,5,8,12,89,103,120,136,153],kern_get_efi_vari:66,kern_get_efi_variable_ful:66,kern_list_efi_vari:66,kern_set_efi_vari:66,kernei:156,kernel:[1,9,10,72,74,156,159],keyboard:[8,86,158],keyvar_fil:153,know:[1,3],knowledg:158,known:[8,158],kovah:87,kwarg:0,l:159,last_fv_siz:54,later:[12,89],latest:[0,10,12,13,157],launch:[9,159],layer:62,ldt:130,ldtcommand:130,learn:12,least:[0,3],left:0,legaci:[8,12],legacy_pci:[59,67],legacypci:69,legal:0,length:[0,18,20,21,39,40,43,52,57,62,64,66,70,71,74,137,140,148,154],lenovo:12,less:8,let:46,level:[9,58],lib:[12,13,66],libc:13,libelf:10,librari:[0,18],lift:0,like:[4,8,13,46,49,107,156],limit:0,line:[0,9,62,103,108,115,116,123,135,151,159],link:[12,13],lint:0,linux:[9,59,70,156],linux_requir:10,linuxhelp:[59,65],linuxn:59,linuxnativehelp:[59,67],list:[0,1,4,8,18,20,22,23,29,30,32,33,36,37,40,42,44,46,51,52,53,55,58,60,64,66,71,72,74,86,87,88,89,92,93,94,95,96,97,98,99,103,105,106,107,108,109,110,111,112,113,115,116,123,127,128,134,135,136,140,153,156,159],list_bar:140,list_efi_vari:[51,60,62,64,66,70,71,74],list_io_bar:30,list_lock:136,list_mmio_bar:33,list_tag:159,liter:9,literalstr:0,live:[7,153],lnum:74,load:[1,2,8,9,12,70,94,152,159],load_chipsec_modul:66,load_configur:36,load_help:72,load_pars:16,load_platform_config:16,load_platform_info:16,load_ucode_upd:[50,60,62,64,66,70,71,74],loader_revis:50,loadimag:52,loadnow:16,loadopt:12,local:[0,47,150],localapicaddress:21,localapiclint:21,localsapiceid:21,localsapicid:21,localx2apiclint:21,locat:[3,12,158],locatedevicepath:52,locatehandl:52,locatehandlebuff:52,locateprotocol:52,lock:[1,2,3,8,19,87,88,89,95,96,97,98,99,104,105,106,107,113,136,158],lock_check_cmd:[1,122],lock_detail:126,lock_nam:32,lock_valid:32,lockcheckcommand:136,locknam:136,lockname1:136,lockname2:136,lockresult:32,log:[1,49,128,158,159],log_fail:3,log_head:136,log_kei:136,log_pass:[3,6],log_register_head:47,log_script:[51,55],logger:[1,3,6,56,104],logic:[0,1,6,43,94,158],look:[13,158],lookup:5,loop:0,looptim:52,lore:156,lot:13,low:9,lower:0,luv:10,lvl:[36,46],lxde:10,lzma:153,m:[86,87,88,89,90,92,93,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,159],mac:9,macbook:97,machinebankpars:21,macronix:45,mai:[0,9,13,48,89,94,106,107,110,112,113,128,158],mail:156,main:[1,12,51],maintain:157,majorv:40,make:[0,1,12,13,108,148,156],malici:[8,12],malwar:[9,89,107],manag:[12,74,94,105,107,108],mani:0,manipul:[12,46,107],manner:12,manual:[1,8,12,92,96,106,158,159],manufactur:[45,97],manufacturer_str:40,map:[8,12,33,70,98,139,158],map_bigpage_1g:36,map_io_spac:[39,60,62,64,66,70,71,74],mark:0,markdown:159,mask:[2,36,52,90,143,159],master:[97,99],match:[0,5,70,136],match_criteria:56,match_module_typ:46,max_addr:66,max_len:18,max_length:18,max_mut:18,max_num:18,max_pa:[64,74],max_phys_address:[39,57,60,62,70,71],maximum:[0,43],maxsiz:40,maybe_hex:79,mb_opcode_cfg_read:34,mb_opcode_cfg_writ:34,mb_opcode_cr_read:34,mb_opcode_cr_writ:34,mb_opcode_esram_read:34,mb_opcode_esram_writ:34,mb_opcode_io_read:34,mb_opcode_io_writ:34,mb_opcode_mmio_read:34,mb_opcode_mmio_writ:34,mb_opcode_reg_read:34,mb_opcode_reg_writ:34,mbyte:79,mce:106,mcfg:12,mchbar:[33,140],mcr:[60,62,64,66,70,71,74],mcrx:[60,62,64,66,70,71,74],mdr:[60,62,64,66,70,71,74],me:97,me_hf:97,me_mfg_mod:[8,82,85],me_statu:97,mean:[8,105,110],mechan:[0,9,12,89,158],media:13,meltdown:94,meltdownattack:94,mem:[66,70,137],mem_alloc:137,mem_cmd:[1,122],mem_detail:126,mem_pagedump:137,mem_read:137,mem_readv:137,mem_search:137,mem_writ:137,mem_writev:137,member:[68,74],memcommand:137,memconfig:[8,82,85,158],memlock:[8,82,85],memori:[8,9,12,22,33,39,42,57,70,75,94,98,99,100,105,107,108,111,132,137,139,154,158],memory_map:70,memorymap:70,menu:12,messag:[8,34,141,158,159],messagebusopcod:34,messagebusport_atom:34,messagebusport_quark:34,met:12,metaclass:0,metadata:0,method:[0,3,6,9,46,74,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],mfg_mode:97,microcod:[50,92],microsoft:[9,12],might:[12,70,148,158],min_length:18,minim:[0,4,97],minimum:0,minorv:40,miss:[0,136,158],mitig:[12,94,106,158],mitr:113,mix:0,mm_msgbus_reg_read:34,mm_msgbus_reg_writ:34,mm_read:141,mm_write:141,mmap:70,mmcfg:[33,138,139],mmcfg_base:138,mmcfg_base_cmd:[1,122],mmcfg_cmd:[1,122],mmcfgbasecommand:138,mmcfgcommand:139,mmio:[1,2,19,37,140],mmio_bar:126,mmio_bar_nam:140,mmio_base_address:140,mmio_cmd:[1,122],mmio_detail:126,mmiocommand:140,mod:46,mode:[8,9,12,74,88,97,105,107,108,158,159],model:[35,96],model_206ax:99,modif:[13,54,103],modifi:[8,12,103,105,108,111,115],modify_uefi_region:46,modn:46,modul:[1,159],module_arg:159,module_argv:[6,86,87,88,89,90,92,93,94,95,96,97,98,99,103,105,106,107,108,109,110,111,112,113,115,116],module_common:[0,1,6,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],module_exclud:159,module_nam:66,module_typ:42,module_type_nam:42,moduleclass:6,moduleorg:42,moduleresult:[0,3,6],moduletyp:[42,159],moduletypeext:42,monotoniccount:55,more:[0,8,12,70],most:[0,3,8,9,18,97],mostli:0,motherboard:112,move:[12,18],mpidr:21,msbuild:12,msct:21,msgbu:[1,19,141],msgbus_cmd:[1,122],msgbus_messag:141,msgbus_mm_read:141,msgbus_mm_writ:141,msgbus_read:141,msgbus_read_messag:34,msgbus_reg_read:34,msgbus_reg_writ:34,msgbus_send_messag:[34,60,62,64,66,70,71,74],msgbus_send_read_messag:[60,62,64,66,70,71,74],msgbus_send_write_messag:[60,62,64,66,70,71,74],msgbus_writ:141,msgbus_write_messag:34,msgbuscommand:141,msr:[1,4,19,70,94,95,96,99,142,158],msr_addr:[35,60,62,64,66,70,71,74],msr_bios_don:[93,107],msr_cmd:[1,122],msr_lt_lock_memori:99,msr_smm_feature_control:106,msr_val:90,msrcommand:142,mstr:79,msv:13,mtbdivid:42,mtbdivisor:42,mtrrcap:104,much:10,multipl:[0,9,128],must:[0,12,89,90,148],mutat:18,mutate_flag:66,mx25l12805:45,mx25l6408:45,mx:159,mydriv:153,n2000:34,n:[53,89,158,159],name:[0,2,3,4,6,7,8,18,20,33,36,48,51,54,60,62,64,66,70,71,72,74,103,115,123,126,129,136,153,156],name_offset:52,names:55,namespac:[0,7],narrow:0,nasm:[10,13],nativ:70,native_get_acpi_t:74,natur:9,navig:12,nb:159,nbit:77,necessari:[0,9,10,48,94,128],need:[0,3,4,6,10,13,74,89,94,97,107,108,159],nest:0,net:[74,151],new_bio:153,new_rom:153,newhelp:4,newval:[66,70],next:[3,13,18,49],nextfwfil:54,nextfwfilesect:54,nextfwvolum:54,nfit:21,nl:159,nmi:[28,133],nmicommand:133,no_bann:159,no_driv:159,no_driver_cmd:150,no_tim:159,noattr:36,nointegritycheck:12,non:[0,48,108],none:[16,18,20,21,22,23,25,27,28,29,30,31,32,33,34,35,36,37,40,41,42,43,44,46,47,49,51,52,54,55,56,58,60,64,66,69,70,71,72,74,90,104,116,121,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],nonehelp:59,not_applic:158,notapplic:6,notat:0,note:[0,94,115,158],noth:18,notic:10,notrequir:0,now:[12,13,158],nr:66,num:[21,27],num_byt:66,num_entri:35,num_mut:18,number:[0,18,150],number_of_bit:77,numberoftableentri:52,numer:[1,9,159],numinject:21,numstructur:40,nv:48,nvar:55,nvdimmblockdatawindowsregionstruct:21,nvdimmcontrolregionstructmark:21,nvram:[8,52,55,89,128,153],nvram_auth:153,nvram_buf:[55,74],nvram_pth:51,nvread:[48,150],nvxdpe8rkt:156,o:[4,12,29,30,37,46,134,136],obj:46,object:[0,16,18,21,26,29,32,33,34,35,36,37,42,45,46,49,50,52,53,54,55,58,68,69,72,76,104,120,121],observ:158,occur:[0,95],octothorp:0,oe:156,oemid:20,oemrevis:20,oemtableid:20,off:[2,9,33,37,54,55,74],offici:12,offset:[2,22,25,30,33,41,42,43,46,48,51,54,62,66,69,70,97,131,139,140,141,143,146,147,150],offset_in_script:52,often:[89,111],ok:158,older:[0,157],oleksiuk:116,onc:[0,89,94,106],one:[0,8,94,95,151],ones_compl:77,onli:[0,9,89,90,98,100,105,109,159],op:[55,137,154],op_dispatch:52,op_io_pci_mem:52,op_mem_pol:52,op_smbus_execut:52,op_stal:52,op_termin:52,op_unknown:52,opcod:[8,34,52,141],open:[11,12,107,156],openprotocol:52,openprotocolinform:52,oper:[9,43,48,52,70,94,132,148],operation_mod:97,operation_st:97,optfeatur:42,optfeatures1:42,optim:43,option:[1,8,9,12,18,20,21,23,25,27,28,32,33,34,35,36,37,39,40,43,44,46,49,51,52,54,55,56,58,60,64,66,70,71,74,77,103,115,116,127,128],order:[0,9,89,97,128,158],org:[10,11,12,42,47,156,157],origin:12,os:[1,8,9,12,72,94,105,115,116,158,159],oshelp:[1,59],other:[0,3,12,89,105,113],otherwis:[18,49],our:156,out:[97,106,129],outdat:10,outl:69,outlin:105,outpath:46,output:[1,12,129,159],outsid:8,outstand:89,over:[0,8,49],overflow:8,overload:0,overrid:[0,2,4,8,112,158],overview:9,overwrit:0,overwritten:[86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,158],own:9,ownership:47,p2sb_dci:95,p:[5,12,151,159],pa2va:64,pa:[27,36,39,64,116],pa_end:137,pa_start:137,pack1:80,pack:80,packag:[1,8,10,12,64],packagetyp:42,packl_ctyp:74,pacman:10,pad:18,page:[1,19],pagedump:[137,154],paging_base_cr3:127,panic:9,param0:58,param1:58,param:18,paramet:[0,58,150],parameter_block:58,parameteris:0,paramspec:0,parent:46,parent_guid:46,parenthes:0,parkedaddress:21,parkingprotocolvers:21,pars:[8,12,21,44,46,49,54,55,128,148],parse_arg:7,parse_argu:[7,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],parse_auth_var:52,parse_efi_vari:51,parse_efivar_fil:52,parse_esal_var:52,parse_extern:52,parse_log:150,parse_pkcs7:52,parse_rsa2048:52,parse_rsa2048_sha1:52,parse_rsa2048_sha256:52,parse_s3bootscript_entri:55,parse_sb_db:52,parse_script:51,parse_sha1:52,parse_sha224:52,parse_sha256:52,parse_sha384:52,parse_sha512:52,parse_spi_flash_descriptor:44,parse_uefi_region_from_fil:46,parse_x509:52,parse_x509_sha256:52,parse_x509_sha384:52,parse_x509_sha512:52,parse_xrom:37,parseactiont:21,parseaddress:21,parseamc:21,parseerrentri:21,parseerrorblock:21,parsegenerrorentri:21,parseghess:21,parseinject:21,parseinjectionactiont:21,parseinstructionentri:21,parsemap:21,parsenmistructur:21,parsenonuid:21,parsenotifi:21,parsepci:21,parseprox:21,parseproxdominfostruct:21,parser:7,parser_entrypoint:7,parsesectiontyp:21,parsespa:21,parsestructur:21,parset:20,parsetim:21,parseuid:21,part:[43,89],parti:0,particular:[47,148],pascalcas:0,pass:[3,6,46,89,90,94,95,97,99,109,158],password:[8,86,158],path:[16,21,36,46,116,137,159],path_to_si:12,pattern:158,payload:[28,133],payload_fil:133,payload_loc:[28,133],payload_str:133,pc:[48,49],pccrread:150,pch:[97,159],pch_code:16,pch_dev_cs:97,pch_dev_slot_cs:97,pch_devfn_cs:97,pch_me_dev:97,pci0:[100,105,107],pci:[1,4,8,19,33,38,143],pci_addr:62,pci_bdf:74,pci_cmd:[1,122],pci_detail:126,pci_dev:97,pci_dump:143,pci_enumer:143,pci_me_hfsts1:97,pci_read:143,pci_writ:143,pci_xrom:143,pci_xrom_head:37,pcicfg:2,pcicommand:143,pcidb:[1,19],pcie:[37,138,143],pciid:38,pciroffset:37,pciutil:38,pcr:[48,150],pcr_index:49,pcrlogpars:49,pcrread:[48,150],pdb:[50,152],pdb_ucode_buff:50,pde_index:36,pdf:[34,42,94,151],pdpte_index:36,peccheck:52,pentium:105,pep8:0,per:[5,43,94],perform:[12,43,48,70,89],performanceinterruptgsiv:21,peripher:12,perm:36,permiss:[8,110,111,115,158],persist:10,pfat_se_svn:104,philosophi:0,phy:36,phys_address:[39,60,62,64,66,70,71,74],physbas:[107,108],physic:[9,39,48,137,154],physical_address:[62,64,70,71,74,137,154],physicaladdress:21,physicalbaseaddress:21,physmask:[107,108],physmem:[1,19,66],piec:97,pin:112,pip:[10,12],pk:153,place:[3,159],platcapstruct:21,platform:[1,2,3,9,12,47,49,51,55,72,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,124,158,159],platform_cod:3,platform_detect:16,platformcommand:124,platforminfo:15,platintsourceflag:21,pleas:[10,12,156,157],pml4e_index:36,poc:159,point:[12,158],pointer:8,poison:108,polar:[46,52,54],polici:8,pollut:0,popul:108,port:[29,34,66,69,70,133,134,141],portio:29,portiocommand:134,portion:158,possibl:[0,10,18,89,158],potenti:0,power:12,pr0:[89,113],pr4:113,pr:89,pr_num:43,prb:89,pre:[86,158],preced:[0,48],precis:0,predict:94,predictor:94,prefer:0,prefix:0,prerequisit:6,presenc:42,present:[0,12],press:12,prevent:[0,12,89,94,100,158],preview:12,previou:129,primari:6,primit:[1,17],principl:0,print:[130,158],print_acpi_table_list:20,print_cet_st:90,print_context_entri:36,print_efi_vari:51,print_entri:36,print_info:36,print_pch_info:16,print_pci_config_al:37,print_pci_devic:37,print_pci_extended_cap:33,print_pci_xrom:37,print_platform_info:16,print_sorted_efi_vari:51,print_supported_chipset:16,printk:97,prior:97,privat:0,privileg:[9,94],prl:89,prmrr:104,prmrr_base_address_field:104,prmrr_lock:104,prmrr_mask:104,prmrr_mask_bit:104,prmrr_memtyp:104,prmrr_phybas:104,prmrr_uncore_mask:104,prmrr_uncore_phybas:104,prmrr_valid_config:104,prmrr_vld:104,prn:89,probabl:158,problem:99,proc_cod:16,proceid:21,process:[12,40,89],process_cal:52,processfirmwarevolum:52,processor:[27,34,94],processor_flag:50,processor_signatur:50,procid:21,product:[9,97,111,158],product_str:40,profil:49,prog:7,program:[0,107,110,158],progress:158,project:[11,12,74,94,151,159],prompt:12,proper:107,properli:[0,116,158],properti:12,propos:0,prot:70,protect:[9,89,94,99,103,105,106,107,110,111,113,115,116,158],protocol:[0,49],protocolsperhandl:52,provid:[0,1,2,3,4,9,12,20,40,47,48,74,123,135,137,151,153,154],proximitydomain:21,pt:[127,135,155],pt_fname:[23,58],pte:27,pte_index:36,pte_num:27,pth:46,ptmesg:43,ptr:36,ptsecur:97,pubkeyindex:55,publicationarticl:42,pull:156,purpos:[0,105],py368readm:13,py:[1,3,4,6,7,8,10,12,13,86,87,88,89,90,92,93,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,148,159],pyd:12,pypi:[10,11,159],python2:[10,11,12],python368:13,python36:13,python3:10,python:[8,9,10,11,12,62,70,74,148],pyver:12,pywin32:[11,12,74],qpi:45,querycapsulecap:52,queryvariableinfo:52,question:[113,156],quick_read:52,quick_writ:52,quot:0,qword:18,r10:[58,60,62,64,66,70,71,74,155],r11:[58,60,62,64,66,70,71,74,155],r8:[58,60,62,64,66,70,71,74,155],r9:[58,60,62,64,66,70,71,74,155],r:[10,12,34,62],race:[8,89],racer:89,rafal:[100,116],rais:46,raisetpl:52,random_data:18,rang:[2,8,37,89,106,107,108,113,158],range_bas:29,range_s:29,rasf:21,raw:[40,145,153],raw_data:40,raw_fil:153,rax:[58,60,62,64,66,70,71,74,133,155],rbx:[58,60,62,64,66,70,71,74,133,155],rcdl:94,rcdl_no:94,rcx:[58,60,62,64,66,70,71,74,133,155],rdcl:94,rdcl_no:94,rdi:[58,60,62,64,66,70,71,74,133,155],rdx:[58,60,62,64,66,70,71,74,133,155],re:[3,6,8],reach:18,react:[3,158],read:[0,1,3,22,30,37,43,48,49,94,99,105,106,111,131,132,134,136,137,139,140,141,142,143,144,146,147,148,153,154],read_ab:140,read_bar:140,read_block:52,read_byt:[37,41,42,52],read_c:36,read_cmos_high:22,read_cmos_low:22,read_cr:[23,60,62,64,66,70,71,74],read_data:25,read_dma:132,read_dword:37,read_efi_vari:51,read_efi_variables_from_fil:51,read_efi_variables_from_spi:51,read_entri:36,read_entry_by_virt_addr:36,read_field:144,read_fil:44,read_ggtt_pt:27,read_idx:25,read_io:29,read_io_bar:30,read_io_bar_reg:30,read_io_port:[60,62,64,66,70,71,74],read_memori:25,read_memory_extend:25,read_mmcfg_reg:33,read_mmio:33,read_mmio_bar:33,read_mmio_bar_reg:33,read_mmio_reg:[33,60,62,64,66,70,71,74],read_mmio_reg_byt:33,read_mmio_reg_dword:33,read_mmio_reg_word:33,read_msr:[35,60,62,64,66,70,71,74],read_page_t:36,read_pci_config:69,read_pci_reg:[60,62,64,66,70,71,74],read_pd:36,read_pdpt:36,read_phys_mem:[60,62,64,66,70,71,74],read_physical_mem:39,read_physical_mem_byt:39,read_physical_mem_dowrd:39,read_physical_mem_dword:39,read_physical_mem_qword:39,read_physical_mem_word:39,read_pml4:36,read_port_byt:29,read_port_dword:29,read_port_word:29,read_pt:36,read_pt_and_show_statu:36,read_r:36,read_rang:[25,41,42],read_rsdp:20,read_spi:43,read_spi_to_fil:43,read_ucode_fil:50,read_virtual_mem:57,read_virtual_mem_byt:57,read_virtual_mem_dowrd:57,read_virtual_mem_dword:57,read_virtual_mem_word:57,read_vtd_context:36,read_word:[37,52],readabl:[0,2,106],readh:125,readl:125,readmem:36,readval:[137,154],reason:[9,89,94],reboot:[10,12,13],receiv:[12,47],receive_byt:52,recogn:159,recommend:[0,12,13,158],record:[8,49],redhat:10,redirect:8,ree_index:36,refer:[12,34,42,86,87,88,89,92,94,96,97,99,100,103,104,105,106,107,108,109,113,116,157],refrain:10,reg:[2,43,144],reg_cmd:[1,122],reg_get_control:144,reg_nam:144,reg_read:144,reg_read_field:144,reg_set_control:144,reg_writ:144,reg_write_field:144,regard:48,regi:126,region:[8,70,89,110,111,158],regist:[2,3,5,34,35,37,47,87,88,89,92,93,94,95,96,97,98,99,100,104,105,106,107,108,109,110,111,112,113,126,136,141,143,151,158],register_detail:126,register_nam:47,registerbaseaddr:21,registercommand:144,registerprotocolnotifi:52,registri:1,reinstallprotocolinterfac:52,relat:[23,104,105,156],releas:[10,12,156],release_str:40,relev:94,reload:108,remaind:43,remap:[8,82,85,158],remov:[0,12,153,158],removeiospac:52,removememoryspac:52,renam:13,render:18,repeat:18,replac:[0,153],repo:[10,12,156],report:[1,48,90,156],repositori:10,represent:52,reprogram:[107,113],request:[70,156],requir:[0,5,7,9,10,12,70,115,116,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,158],research:[108,116],reserv:[21,37,40,52,54,55,97],reserved1:[50,55],reserved2:[21,50,55],reserved3:[50,55],reserveda:42,reset:[12,18,48,113],reset_smbus_control:41,reset_vari:104,resetsystem:52,resourc:[1,9,35,74,159],respect:130,responsetag:47,restart:12,restor:8,restoretpl:52,restrict:[0,8,12,94,158],result:[1,3,6,9,12,89,94,95,97,99,109,110,128,159],result_delta:1,resum:116,retpolin:94,retpoline_en:[60,62,64,66,70,71,74],returncod:47,reus:3,reveal:[148,158],review:[3,158],revis:[20,34,42,47,52],rewrit:0,right:0,ring:[105,108],rmrbaseaddr:21,rmrlimitaddr:21,rogu:94,rom:[37,44,51,128,143,148,149,153],rom_buff:51,rom_fil:153,rom_sz:40,root:[8,9,12,13,159],root_dir:8,rot_list:53,rotate_list:53,rout:112,routin:0,rowaddresscount:42,rpe:89,rpm:10,rsdp:[20,21],rsdp_pa:20,rsdt:[20,21],rsdtxsdt:20,rsi:[58,60,62,64,66,70,71,74,133,155],rsvdd:42,rt:103,rt_code_end:133,rt_code_start:133,rtc:158,rtclock:[8,82,85,158],rtype:18,rufu:10,rule:[0,56],run1:129,run2:129,run:[1,3,6,7,8,9,12,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,124,128,129,130,132,133,135,138,141,142,145,146,147,149,150,151,155,157,158],runtim:[0,115,116],runtimeservic:52,rutkowska:100,rw:136,rweveryth:12,s3:[8,52,116,158],s3bootscript:[8,82,85,114,153,158],s3bootscript_entri:[51,52,55,116],s3bootscript_typ:55,s3bootscriptopcod:52,s3bootscriptopcode_edkcompat:52,s3bootscriptopcode_md:52,s3bootscriptsmbusoper:52,s3bootscripttyp:55,s3bootscriptwidth:52,s3script_modifi:8,s:[0,8,10,13,47,70,97,116,159],s_data:52,sam:87,sampl:9,sanit:8,save:[46,159],save_configur:36,save_efi_tre:46,save_efi_tree_filetyp:46,save_log:46,save_modul:46,sc:12,scan:5,scan_block:8,scan_single_bit_mask:77,schedul:52,sclean_se_svn:104,scm:11,scope:0,screen:12,script:[8,51,52,55,116,158],script_address:[116,153],script_data:55,script_typ:[52,55],scrtmversion:49,sdev:12,sdk:12,sdm:[92,96,106],sdt:20,search:[56,137,154],search_callback:46,search_efi_tre:46,search_rsdp:20,sec:43,sec_fs_nam:46,secbodi:54,secheaders:54,second:58,section:[0,3,10,13,34,46,54,103,120,128,148],section_dir_path:46,section_ex:46,sectyp:54,secur:[9,12,13,52,87,89,98,103,105,107,112,113,116,158,159],secureboot:[8,82,85,87,158],see:[3,108],seem:158,segment:40,segmentnumb:21,select:[1,5,12,18],self:[0,3,4,6,7,12,18,37,46,48,56],semicolon:0,send:[47,133,156],send_acpi_smi:28,send_byt:52,send_nmi:28,send_smi_apmc:28,send_smmc_smi:28,send_sw_smi:[28,60,62,64,66,70,71,74],sensit:8,separ:[0,46],seq:79,sequenc:18,seri:[34,109],serial:42,serial_presence_detect:42,serial_str:40,serializ:46,server:[12,156],servic:[8,9,12,159],set:[0,3,8,9,12,32,89,90,94,97,99,105,106,109,113],set_affin:[60,62,64,66,70,71,74],set_control:[3,144],set_default:7,set_efi_vari:[51,60,62,64,66,70,71,74],set_efi_variable_from_fil:51,set_field:36,set_fwtyp:51,set_iommu_transl:31,set_mem_bit:39,set_pci_data:16,set_up:[123,125,131,134,136,140,146,148,150,153,154],setmem:52,setmemoryspaceattribut:52,settim:52,setting_en:90,setup:[1,8,10,12,13,87,159],setuptool:[0,10,12],setvari:52,setvirtualaddressmap:52,setwakeuptim:52,setwatchdogtim:52,sfdp:148,sgx:104,sgx_check:[8,82,85],sgx_debug_mod:104,sgx_debug_mode_status_bit:104,sgx_global_en:104,share:18,shell:[0,9,12,104],shellbinpkg:13,shift:12,ship:97,shortcut:80,should:[0,3,4,5,8,9,13,48,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,158,159],show:[126,159],show_warn:74,shutdown:12,side:94,sideband:34,sign:[0,9,12,18],signalev:52,signatur:[0,8,9,20,37,52,55],similar:[0,151],simmtest:42,simpl:[9,49],simpli:[18,105,106,111],simplifi:0,sinc:[10,11,12],singl:[0,80,94],sinit_se_svn:104,sinkhol:8,site:[42,94,156],size:[2,18,25,27,29,30,33,36,37,41,42,43,46,48,52,54,55,58,60,62,64,66,70,71,74,77,80,131,138,146,150,158],skip:[9,159],skip_config:159,skipkei:46,skipped_not_applic:158,sl:151,slat:58,sltool:151,smbase:108,smbio:[1,19,145],smbios_2_x_entry_point:40,smbios_3_x_entry_point:40,smbios_bios_info_2_0:40,smbios_bios_info_2_0_entri:40,smbios_cmd:[1,122],smbios_ep:145,smbios_get:145,smbios_struct_head:40,smbios_system_info_2_0:40,smbios_system_info_2_0_entri:40,smbiosmanagementinfo:21,smbu:[1,19,42,109,146],smbus_cmd:[1,122],smbus_hcfg:109,smbus_read:146,smbus_vid:144,smbus_writ:146,smbuscommand:146,smi:[28,87,89,108,133,158],smi_cod:133,smi_code_data:[60,62,64,66,70,71,74],smi_code_port_valu:28,smi_count:133,smi_data:133,smi_data_port_valu:28,smi_num:28,smi_send:133,smi_smmc:133,smicommand:133,smilock:87,sml:49,smm:[8,82,85,89,99,106,107,108,158],smm_bwp:89,smm_code_chk:[8,82,85],smm_code_chk_en:106,smm_dma:[8,82,85,158],smm_ptr:8,smmbioswriteprotect:[87,89],smmc:[28,133],smmruntim:8,smram:[105,107,108,158],smramc:105,smrr:[8,82,85,106,158,159],smt:43,snake_cas:0,snb:[8,82],so:[0,2,97,159],soc:[34,97,99],soc_bios_don:93,sof:54,softwar:[8,11,89,92,94,96,105,106,107,108,111,158],solut:12,some:[0,3,12,89,105,110,112,157,158],some_module_requir:6,someth:158,sometim:89,sort_kei:46,sourc:[9,10,11,12,15,16,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,60,62,64,66,68,69,70,71,72,74,76,77,79,80,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,120,121,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,157,158],source_id:36,sourceforg:[74,151],space:[0,33,134,139],spd:[1,19,109,147],spd_cmd:[1,122],spd_ddr2:42,spd_ddr3:42,spd_ddr4:42,spd_ddr:42,spd_detect:147,spd_dump:147,spd_read:147,spd_revis:42,spd_wd:[8,82,85],spd_write:147,spdbyte:42,spdcommand:147,spec:[37,103,115,158],specif:[0,1,2,3,5,8,22,28,35,40,47,48,49,50,51,55,58,70,72,94,95,96,159],specifi:[0,5,18,40,116,159],spectr:[12,94],spectre_v2:[8,82,85,91,158],spectreattack:94,specul:94,speed:89,spi:[1,2,8,19,44,45,89,110,111,112,113,128,148,149,153,158,159],spi_access:[8,82,85,158],spi_cmd:[1,122],spi_desc:[8,82,85,158],spi_descriptor:[1,19],spi_disable_wp:148,spi_dump:148,spi_eras:148,spi_fdopss:[8,82,85,158],spi_fla:43,spi_info:148,spi_jedec:148,spi_jedec_id:[1,19],spi_lock:[8,82,85,158,159],spi_read:148,spi_read_write_max_dbc:43,spi_reg_read:43,spi_reg_writ:43,spi_region_id:43,spi_sfdp:148,spi_uefi:[1,19],spi_writ:148,spibar:[2,140],spibas:21,spicommand:148,spicount:21,spidesc:149,spidesc_cmd:[1,122],spidesccommand:149,spiregion:43,spiwritestatusdi:113,split_address:64,spmi:21,src:[97,99],ssi:156,ssize:54,stage:121,stage_data:[15,121],stage_dev:121,stage_info:121,stagecor:121,stageinfo:121,stall:52,standalon:124,standard:[0,70,158],standarderrorhandl:52,start:[12,13,18,28,60,62,64,66,70,71,74,77,159],start_driv:62,start_offset:[25,41,42,146],start_test:6,startbusnum:21,startid:55,startimag:52,startup:[12,48,121,150],stat:151,state:[18,54,55,136,150,151],statement:0,statu:[3,47,135],statuscod:52,stderr:52,stdlib:13,step:[10,13,18,106,157],stibp:[94,158],stick:10,still:158,stop:[12,60,62,64,66,70,71,74,151],storag:10,store:[8,48,49,89,128],str:[20,21,23,28,30,31,32,33,36,37,40,42,43,44,45,46,47,48,50,51,52,54,55,56,58,60,62,64,66,70,71,72,74,79,86,87,88,89,92,93,94,95,96,97,98,99,103,105,106,107,108,109,110,111,112,113,115,116,126,127,136,137],strap:112,string:[8,9,18,40,75,80],stringtobyt:79,struct:[55,75,97],struct_typ:40,structur:[0,3,4,13,40,68,74],studio:[11,12],style:159,sub:150,subcap:48,subcaps:48,subclass:[3,46,49,70,143],subdirectori:[8,13],submodul:[1,4,8,13,82],subpackag:[4,8],subpars:7,subscrib:156,subtyp:0,subvers:100,success:[6,18,48],sudo:159,suggest:156,summari:[0,87,107],sun:88,supertyp:0,supplement:12,suppli:18,support:[1,3,8,9,10,11,12,46,47,72,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,158],support_ibt:90,support_kernel26_get_page_is_ram:66,support_kernel26_get_phys_mem_access_prot:66,support_shadow:90,sure:[0,1,12,13],surround:9,sw:[86,158],swap:[8,88,158],sy:0,syntact:0,syntax:0,system:[1,2,4,9,11,12,48,89,94,95,105,107,108,111,112,148,153,158],system_resource_protect:21,systemvectorbas:21,t:[8,12,94,158,159],tab:0,tabl:[0,8,12,20,21,36,52,115,116,123,153],table_cont:21,table_nam:[60,62,64,66,70,71,74],table_sig:51,tableaddr:40,tablelen:[21,40],tag:159,take:[18,94],taken:148,tale:89,target:[9,94,141],target_address:41,target_machin:62,task:1,tbd:43,tboot:151,tcg:[48,49],tcgpcrevent:49,tckmin:42,tco:87,tcosmilock:87,te:[8,31],team:116,tear_down:136,technic:[92,96,106,116],technolog:151,templat:9,test1:0,test2:0,test:[0,1,3,6,8,9,10,48,89,96,159],testcas:1,testsign:[9,12],text:0,textual:52,thei:0,them:[0,158],theori:0,therebi:89,therefor:12,thermalrefresh:42,thermsensor:42,thi:[0,3,8,9,12,13,18,38,46,49,70,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,128,148,151,158,159],thing:[0,10],thinkpad:12,third:0,those:0,though:94,thread:[35,50,62,94,127],thread_id:[28,66,70,133,142],threat:116,three:0,through:[18,107],tiano:153,tianocor:13,time:0,timestamp1:55,timestamp2:55,timestamp:159,titl:0,tm:34,to_binari:18,to_decim:18,todo:94,toload:[7,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],too:0,tool:[0,8,9,10,12,13,113,159],tool_typ:[62,64,66],top:[8,88,158],topolog:127,topswap:88,topswapstatu:88,total:18,total_s:50,totalbyt:42,totals:55,tpm12_command:[1,19],tpm:[1,19,48,49,150],tpm_cmd:[1,122],tpm_command:150,tpm_continueselftest:48,tpm_eventlog:[1,19],tpm_init:48,tpm_pars:150,tpm_pcrread:48,tpm_response_head:47,tpm_st_clear:48,tpm_st_deactiv:48,tpm_st_state:48,tpm_startup:48,tpm_state:150,tpmcommand:150,tpmv1:48,track:70,tracker:156,trail:0,transform:0,translat:[36,52,58],tree:151,trenchboot:151,tri:12,trigger:[12,108],troubleshoot:12,trust:[47,49,52,151],trustedcomputinggroup:47,try_init:37,tseg:[107,158],tsegbaselock:107,tseglimitlock:107,tsegmb:107,tupl:[20,21,23,24,28,30,33,35,37,39,43,44,48,51,54,55,57,58,60,62,64,66,70,71,74],turn:[9,95],twitter:156,two:0,txt:[10,12,13,151],txt_cmd:[1,122],txt_dump:151,txt_state:151,txtcommand:151,type:[2,4,9,12,18,21,40,48,54,75,108,128,145,150,153,159],typeddict:0,typeerror:46,typevartupl:0,typic:0,u32:97,ubuntu:10,ucod:[1,19,94,152],ucode_buf:50,ucode_cmd:[1,122],ucode_decod:152,ucode_fil:50,ucode_filenam:50,ucode_id:152,ucode_load:152,ucode_update_buf:[62,64,66,70,71,74],ucode_update_buff:60,ucode_update_fil:152,ucode_update_id:50,ucodecommand:152,ucodeupdatehead:50,ud:54,udk2018:13,uefi:[1,4,8,9,10,12,19,46,52,54,55,56,64,82,85,103,153,158],uefi_auth:55,uefi_cmd:[1,122],uefi_common:[1,19,51,55,116],uefi_compress:[1,19],uefi_fil:[46,153],uefi_fv:[1,19,46,56],uefi_platform:[1,19],uefi_search:[1,19],uefi_t:21,uefi_variable_head:55,uefi_variable_store_header_s:55,ueficommand:153,ueficompress:53,uefishel:13,unabl:136,unam:10,unauthent:8,unauthor:103,unboot:[1,148],uncompressed_data:53,uncomressed_s:54,undefin:136,under:[8,94],underscor:9,undoc:136,unfortun:158,uninstallmultipleprotocolinterfac:52,uninstallprotocolinterfac:52,union:[0,20,40,46,55,68,74,127],unit:141,unit_aunit:34,unit_bunit:34,unit_cpu:34,unit_gfx:34,unit_hb:34,unit_hba:34,unit_mm:34,unit_pci:34,unit_pmc:34,unit_rmu:34,unit_sata:34,unit_smc:34,unit_smi:34,unit_soc:34,unit_usb:34,unknown:[52,55],unknown_decompress:53,unknown_efi_decompress:53,unless:40,unload_chipsec_modul:66,unloadimag:52,unlock:[95,136],unpack1:80,unpack:80,unprotect:8,unrecover:106,unsign:8,unsupport:12,until:[10,113],untrust:93,up:[0,158],updat:[0,10,12,13,50,94],update_efi_tre:46,update_in_progress:97,update_revis:50,update_ucod:50,update_ucode_all_cpu:50,updatecapsul:52,uppercamelcas:0,upstream:0,us:[0,1,2,3,8,10,11,12,43,47,48,51,64,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,132,148,151,156,158],usabl:[70,158],usag:[7,8,13,22,24,25,27,28,29,30,33,34,35,37,39,43,44,46,50,56,57,86,87,88,89,90,92,93,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116,124,128,138,151,159],usb:[9,10],user:[0,9,62,158],user_module_tag:159,usual:89,utf:0,util:[0,1,7,123,124,135,148,151,159],utilcmd:[0,1,7],uuid:[46,54],uuidencod:46,v1:48,v2:151,v:159,va2pa:[39,57,60,62,64,66,70,71,74],va:[36,39,57,62,64,66,70,71,74],val:[21,77,80],valid:[8,10,108],validatefwvolumehead:54,valu:[0,1,2,18,21,22,23,25,27,29,30,32,33,36,41,42,43,48,52,60,62,64,66,69,70,71,74,77,80,99,108,121,127,132,134,136,137,139,140,141,143,144,154,158,159],var_attrib:51,var_buf:51,var_data:51,var_delet:153,var_find:153,var_guid:51,var_head:51,var_list:153,var_nam:51,var_read:153,var_typ:52,var_writ:153,vari:0,variabl:[0,4,8,51,52,82,85,102,115,128,148,153,158],variable_store_header_vss2:55,variable_store_header_vss:55,variad:0,variant:94,variou:[1,9,21,72,128,159],vb:12,vcxproj:12,vdd:42,vector:58,vendor:[38,47],vendor_str:40,vendorguid0:55,vendorguid1:55,vendorguid2:55,vendorguid3:55,vendorguid:52,vendorguiddata:52,vendort:52,verbos:159,veri:159,verif:8,verifi:[0,94,98,103],version:[3,9,10,11,12,49,74,136],version_str:40,vgicmaintenanceinterrupt:21,via:[70,108,143],vid:37,view:47,virt:36,virt_address:57,virtio:[58,155],virtio_devic:58,virtmem:[1,19],virtmemori:57,virtual:[12,57,154],virtual_address:[60,154],visit:13,visual:[0,12,158],vmem:154,vmem_alloc:154,vmem_cmd:[1,122],vmem_getphi:154,vmem_read:154,vmem_readv:154,vmem_search:154,vmem_writ:154,vmem_writev:154,vmemcommand:154,vmm:[1,19,155],vmm_cmd:[1,122],vmm_hypercal:155,vmm_pt:155,vmm_virtio:155,vmmcommand:155,vmware:88,vol:34,voltag:42,volum:[34,52,54,128],vs2019:12,vs2022:12,vs:[0,12],vsecentri:33,vss2:55,vss2_auth:55,vss:[55,128],vss_appl:55,vss_auth:[55,153],vss_type:55,vt:36,vtd:135,vu:116,vulner:[8,9,88,89,94,106,113,116,158],vv:159,vverbos:159,w25q128:45,w25q256:45,w25q32jv:45,w25q64fv:45,wa:[6,38,89,105,151,158],wai:[0,89,94,108],waitforev:52,wake:8,walru:9,want:43,warn:[94,158],wasn:94,wconio2:12,wdk:12,we:[70,94,156,158],well:[0,94,158],went:158,were:[105,109,158],what:1,when:[0,3,8,9,12,89,94,105,108,110,148,158],where:[8,49,89,103,105,115,116],whether:[32,86,87,88,89,90,92,93,94,95,96,97,98,99,100,103,104,105,106,107,108,109,110,111,112,113,115,116],which:[0,3,8,9,12,47,48,74,89,151,158],whitespac:0,wide:48,width:[2,18,52,77,132,134,139,140,143,159],wiki:42,wikipedia:42,win:12,win_:12,winbond:45,window:[1,9,59,89],windows_amd64:12,windows_requir:12,windowshelp:[59,73],wish:156,within:[0,3,12,32,104,106,136],without:[0,3,8,12,159],wojtczuk:[100,116],won:159,word:[0,18,137,154,159],word_offset:25,word_valu:[37,39,57],work:[0,9,12,27,158,159],working_st:97,would:89,wp:148,wpd:89,wpe:89,wrap:0,wrapper:[1,49,72],write:[0,1,2,8,9,22,30,37,43,89,103,109,111,131,132,134,137,139,140,141,142,143,144,146,147,148,153,154,158],write_ab:140,write_bar:140,write_block:52,write_byt:[37,41,42,52],write_cmos_high:22,write_cmos_low:22,write_command:25,write_cr:[23,60,62,64,66,70,71,74],write_data:25,write_dma:132,write_dword:37,write_field:144,write_ggtt_pt:27,write_ggtt_pte_from_pa:27,write_idx:25,write_io_bar_reg:30,write_io_port:[60,62,64,66,70,71,74],write_memori:25,write_memory_extend:25,write_mmcfg_reg:33,write_mmio_bar_reg:33,write_mmio_reg:[33,60,62,64,66,70,71,74],write_mmio_reg_byt:33,write_mmio_reg_dword:33,write_mmio_reg_word:33,write_msr:[35,60,62,64,66,70,71,74],write_pci_config:69,write_pci_reg:[60,62,64,66,70,71,74],write_phys_mem:[60,62,64,66,70,71,74],write_physical_mem:39,write_physical_mem_byt:39,write_physical_mem_dowrd:39,write_physical_mem_dword:39,write_physical_mem_word:39,write_port_byt:29,write_port_dword:29,write_port_word:29,write_rang:[25,41,42],write_spi:43,write_spi_from_fil:43,write_virtual_mem:57,write_virtual_mem_byt:57,write_virtual_mem_dowrd:57,write_virtual_mem_dword:57,write_virtual_mem_word:57,write_word:[37,52],writeabl:158,writeh:125,writel:125,writev:[137,154],written:[137,141,154],wrong:158,wsmt:21,www:[10,11,12,34,42,92,96,106,151,157],x00:[18,54],x2apicid:21,x32:12,x64:[9,12,36],x86:[12,36],x:[0,9,159],xen:100,xeno:87,xml:[1,2,3,129,159],xmm_buffer:[58,60,62,64,66,70,71,74],xrom:[8,37,143],xrom_addr:37,xrom_address:143,xrom_dump:37,xrom_head:37,xsdt:[20,21,123],y:0,ye:[0,12,97],yet:43,you:[0,1,10,13,43,46,74,156,157,159],your:[1,9,13,74,113,148,158,159],zen:0,zero:94,zerovector:54,zip:[10,13]},titles:["Python Version","Architecture Overview","Configuration Files","Writing Your Own Modules","OS Helpers and Drivers","Methods for Platform Detection","Sample module code template","<no title>","CHIPSEC Modules","CHIPSEC","Linux Installation","DAL Windows Installation","Windows Installation","Building a Bootable USB drive with UEFI Shell (x64)","chipsec.cfg.parsers package","chipsec.cfg.parsers.core_parsers module","chipsec.config module","chipsec.fuzzing package","chipsec.fuzzing.primitives module","chipsec.hal package","chipsec.hal.acpi module","chipsec.hal.acpi_tables module","chipsec.hal.cmos module","chipsec.hal.cpu module","chipsec.hal.cpuid module","chipsec.hal.ec module","chipsec.hal.hal_base module","chipsec.hal.igd module","chipsec.hal.interrupts module","chipsec.hal.io module","chipsec.hal.iobar module","chipsec.hal.iommu module","chipsec.hal.locks module","chipsec.hal.mmio module","chipsec.hal.msgbus module","chipsec.hal.msr module","chipsec.hal.paging module","chipsec.hal.pci module","chipsec.hal.pcidb module","chipsec.hal.physmem module","chipsec.hal.smbios module","chipsec.hal.smbus module","chipsec.hal.spd module","chipsec.hal.spi module","chipsec.hal.spi_descriptor module","chipsec.hal.spi_jedec_ids module","chipsec.hal.spi_uefi module","chipsec.hal.tpm module","chipsec.hal.tpm12_commands module","chipsec.hal.tpm_eventlog module","chipsec.hal.ucode module","chipsec.hal.uefi module","chipsec.hal.uefi_common module","chipsec.hal.uefi_compression module","chipsec.hal.uefi_fv module","chipsec.hal.uefi_platform module","chipsec.hal.uefi_search module","chipsec.hal.virtmem module","chipsec.hal.vmm module","chipsec.helper package","chipsec.helper.basehelper module","chipsec.helper.dal package","chipsec.helper.dal.dalhelper module","chipsec.helper.efi package","chipsec.helper.efi.efihelper module","chipsec.helper.linux package","chipsec.helper.linux.linuxhelper module","chipsec.helper.linuxnative package","chipsec.helper.linuxnative.cpuid module","chipsec.helper.linuxnative.legacy_pci module","chipsec.helper.linuxnative.linuxnativehelper module","chipsec.helper.nonehelper module","chipsec.helper.oshelper module","chipsec.helper.windows package","chipsec.helper.windows.windowshelper module","chipsec.library package","chipsec.library.architecture module","chipsec.library.bits module","chipsec.library.memory module","chipsec.library.strings module","chipsec.library.structs module","chipsec.library.types module","chipsec.modules package","chipsec.modules.bdw package","chipsec.modules.byt package","chipsec.modules.common package","chipsec.modules.common.bios_kbrd_buffer module","chipsec.modules.common.bios_smi module","chipsec.modules.common.bios_ts module","chipsec.modules.common.bios_wp module","chipsec.modules.common.cet module","chipsec.modules.common.cpu package","chipsec.modules.common.cpu.cpu_info module","chipsec.modules.common.cpu.ia_untrusted module","chipsec.modules.common.cpu.spectre_v2 module","chipsec.modules.common.debugenabled module","chipsec.modules.common.ia32cfg module","chipsec.modules.common.me_mfg_mode module","chipsec.modules.common.memconfig module","chipsec.modules.common.memlock module","chipsec.modules.common.remap module","chipsec.modules.common.rtclock module","chipsec.modules.common.secureboot package","chipsec.modules.common.secureboot.variables module","chipsec.modules.common.sgx_check module","chipsec.modules.common.smm module","chipsec.modules.common.smm_code_chk module","chipsec.modules.common.smm_dma module","chipsec.modules.common.smrr module","chipsec.modules.common.spd_wd module","chipsec.modules.common.spi_access module","chipsec.modules.common.spi_desc module","chipsec.modules.common.spi_fdopss module","chipsec.modules.common.spi_lock module","chipsec.modules.common.uefi package","chipsec.modules.common.uefi.access_uefispec module","chipsec.modules.common.uefi.s3bootscript module","chipsec.modules.hsw package","chipsec.modules.ivb package","chipsec.modules.snb package","chipsec.options module","chipsec.parsers module","chipsec.utilcmd package","chipsec.utilcmd.acpi_cmd module","chipsec.utilcmd.chipset_cmd module","chipsec.utilcmd.cmos_cmd module","chipsec.utilcmd.config_cmd module","chipsec.utilcmd.cpu_cmd module","chipsec.utilcmd.decode_cmd module","chipsec.utilcmd.deltas_cmd module","chipsec.utilcmd.desc_cmd module","chipsec.utilcmd.ec_cmd module","chipsec.utilcmd.igd_cmd module","chipsec.utilcmd.interrupts_cmd module","chipsec.utilcmd.io_cmd module","chipsec.utilcmd.iommu_cmd module","chipsec.utilcmd.lock_check_cmd module","chipsec.utilcmd.mem_cmd module","chipsec.utilcmd.mmcfg_base_cmd module","chipsec.utilcmd.mmcfg_cmd module","chipsec.utilcmd.mmio_cmd module","chipsec.utilcmd.msgbus_cmd module","chipsec.utilcmd.msr_cmd module","chipsec.utilcmd.pci_cmd module","chipsec.utilcmd.reg_cmd module","chipsec.utilcmd.smbios_cmd module","chipsec.utilcmd.smbus_cmd module","chipsec.utilcmd.spd_cmd module","chipsec.utilcmd.spi_cmd module","chipsec.utilcmd.spidesc_cmd module","chipsec.utilcmd.tpm_cmd module","chipsec.utilcmd.txt_cmd module","chipsec.utilcmd.ucode_cmd module","chipsec.utilcmd.uefi_cmd module","chipsec.utilcmd.vmem_cmd module","chipsec.utilcmd.vmm_cmd module","Contact","Download CHIPSEC","Interpreting results","Running CHIPSEC"],titleterms:{"3":13,"6":13,"8":13,"abstract":1,"import":4,"new":4,access:12,access_uefispec:115,acpi:20,acpi_cmd:123,acpi_t:21,altern:12,architectur:[1,9,76],attack:8,autom:158,auxiliari:1,basehelp:[4,60],bdw:83,bios_kbrd_buff:86,bios_smi:87,bios_t:88,bios_wp:89,bit:77,boot:8,bootabl:13,build:[1,10,11,12,13],byt:84,cet:90,cfg:[2,14,15],check:12,chip:5,chipsec:[0,5,8,9,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,157,159],chipsec_main:[1,159],chipsec_util:[1,159],chipset:5,chipset_cmd:124,cmo:22,cmos_cmd:125,code:[0,6],command:[1,9],common:[85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116],compon:[1,2,4],config:[12,16],config_cmd:126,configur:[2,5,8],contact:156,content:[14,17,19,59,61,63,65,67,73,75,82,83,84,85,91,102,114,117,118,119,122],contribut:9,core:1,core_pars:15,cpu:[23,91,92,93,94],cpu_cmd:127,cpu_info:92,cpuid:[24,68],creat:[4,10],dal:[11,61,62],dalhelp:62,debugen:95,decode_cmd:128,deltas_cmd:129,depend:12,deprec:0,desc_cmd:130,detect:5,develop:9,did:5,distutil:0,download:157,drive:13,driver:[4,12],ec:25,ec_cmd:131,efi:[63,64],efihelp:64,eg:8,exampl:[2,4],execut:1,f:0,file:2,filter:12,firmwar:8,flow:1,from:[4,8],fuzz:[1,17,18],gener:158,github:157,guid:[0,9],hal:[1,4,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58],hal_bas:26,handler:8,hardwar:[1,8],helper:[4,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74],here:9,hint:0,hsw:117,ia32cfg:96,ia_untrust:93,igd:27,igd_cmd:132,imag:10,incorrect:8,inform:5,instal:[9,10,11,12,13],interfac:8,interpret:158,interrupt:28,interrupts_cmd:133,invok:4,io:29,io_cmd:134,iobar:30,iommu:31,iommu_cmd:135,ivb:118,kali:10,kernel:12,layer:1,legacy_pci:69,librari:[75,76,77,78,79,80,81],linux:[10,65,66],linuxhelp:66,linuxn:[67,68,69,70],linuxnativehelp:70,list:2,liter:0,live:10,locat:5,lock:32,lock_check_cmd:136,me_mfg_mod:97,mean:158,mem_cmd:137,memconfig:98,memlock:99,memori:78,method:[5,12],misc:8,mmcfg_base_cmd:138,mmcfg_cmd:139,mmio:33,mmio_cmd:140,modul:[0,3,4,6,8,9,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,158],mostli:4,msgbu:34,msgbus_cmd:141,msr:35,msr_cmd:142,network:8,nonehelp:71,numer:0,off:12,oper:0,option:[5,13,120,159],os:4,oshelp:72,overview:1,own:3,packag:[14,17,19,59,61,63,65,67,73,75,82,83,84,85,91,102,114,117,118,119,122,159],page:36,parser:[14,15,121],pch:5,pci:[5,12,37],pci_cmd:143,pcidb:38,pep:0,persist:8,physmem:39,platform:[5,8],power:8,prerequisit:[10,11],primit:18,processor:5,program:1,protect:8,py:5,python:[0,13,157,159],reg_cmd:144,releas:157,remap:100,repositori:157,result:158,resum:8,rom:8,rtclock:101,run:[10,13,159],runtim:8,s3bootscript:116,sampl:6,script:1,secur:8,secureboot:[102,103],sgx_check:104,shell:[13,159],signatur:12,sleep:8,smbio:40,smbios_cmd:145,smbu:41,smbus_cmd:146,smi:8,smm:105,smm_code_chk:106,smm_dma:107,smram:8,smrr:108,snb:119,space:12,spd:42,spd_cmd:147,spd_wd:109,spectre_v2:94,spi:43,spi_access:110,spi_cmd:148,spi_desc:111,spi_descriptor:44,spi_fdopss:112,spi_jedec_id:45,spi_lock:113,spi_uefi:46,spidesc_cmd:149,start:9,state:8,string:[0,79],struct:80,style:[0,9],submodul:[14,17,19,59,61,63,65,67,73,75,85,91,102,114,122],subpackag:[59,82,85],support:0,surfac:8,templat:6,test:[12,158],time:8,tool:158,tpm12_command:48,tpm:47,tpm_cmd:150,tpm_eventlog:49,transit:8,turn:12,txt_cmd:151,type:[0,81],ucod:50,ucode_cmd:152,uefi:[13,51,114,115,116],uefi_cmd:153,uefi_common:52,uefi_compress:53,uefi_fv:54,uefi_platform:55,uefi_search:56,underscor:0,updat:8,us:[5,9,159],usb:13,utilcmd:[122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155],variabl:103,vector:8,version:0,vid:5,virtmem:57,vmem_cmd:154,vmm:58,vmm_cmd:155,walru:0,window:[11,12,73,74],windowshelp:74,write:3,x64:13,your:3}}) \ No newline at end of file diff --git a/start/Contact.html b/start/Contact.html index 20b9f4ee..a4f11177 100644 --- a/start/Contact.html +++ b/start/Contact.html @@ -1,23 +1,24 @@ + - + - - + Contact — CHIPSEC documentation - - + + - - - + + + + - + - +
    @@ -164,15 +165,15 @@

    Navigation

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    • \ No newline at end of file diff --git a/start/Download.html b/start/Download.html index 7ff6e11a..8936b480 100644 --- a/start/Download.html +++ b/start/Download.html @@ -1,19 +1,20 @@ + - + - - + Download CHIPSEC — CHIPSEC documentation - - + + - - - + + + + - + @@ -44,26 +45,26 @@

    Navigation

    -
    -

    Download CHIPSEC

    -
    -

    GitHub repository

    +
    +

    Download CHIPSEC

    +
    +

    GitHub repository

    CHIPSEC source files are maintained in a GitHub repository:

    ../_images/GHRepo.png -
    -
    -

    Releases

    +
    +
    +

    Releases

    You can find the latest release here:

    ../_images/LR.png

    Older releases can be found here

    After downloading there are some steps to follow to build the driver and run, please refer to Installation and running CHIPSEC

    - -
    -

    Python

    +
    +
    +

    Python

    Python downloads:

    https://www.python.org/downloads/

    - - +
    +
    @@ -133,7 +134,7 @@

    Quick search

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    \ No newline at end of file diff --git a/usage/Interpreting-Results.html b/usage/Interpreting-Results.html index f59d3797..68404107 100644 --- a/usage/Interpreting-Results.html +++ b/usage/Interpreting-Results.html @@ -1,19 +1,20 @@ + - + - - + Interpreting results — CHIPSEC documentation - - + + - - - + + + + - + @@ -44,21 +45,21 @@

    Navigation

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    Interpreting results

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    Interpreting results

    Note

    DRAFT (work in progress)

    In order to improve usability, we are reviewing and improving the messages and meaning of information returned by CHIPSEC.

    -
    -

    Results

    - - +
    +

    Results

    +
    Generic results meanings
    +--++ @@ -86,20 +87,20 @@

    Results

    Generic results meanings

    Result

    -
    -
    -

    Automated Tests

    +
    +
    +

    Automated Tests

    Each test module can log additional messaging in addition to the return value. In an effort to standardize and improve the clarity of this messaging, the mapping of result and messages is defined below:

    - - +
    Modules results meanings
    +-----+++++ @@ -226,14 +227,14 @@

    Automated Tests -

    Tools

    + +
    +

    Tools

    CHIPSEC also contains tools such as fuzzers, which require a knowledgeable user to run. We can examine the usability of these tools as well.

    - - +
    +
    @@ -303,7 +304,7 @@

    Quick search

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    \ No newline at end of file diff --git a/usage/Running-Chipsec.html b/usage/Running-Chipsec.html index 974d406d..55c148da 100644 --- a/usage/Running-Chipsec.html +++ b/usage/Running-Chipsec.html @@ -1,19 +1,20 @@ + - + - - + Running CHIPSEC — CHIPSEC documentation - - + + - - - + + + + - + @@ -44,8 +45,8 @@

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    Running CHIPSEC

    CHIPSEC should be launched as Administrator/root.

    CHIPSEC will automatically attempt to create and start its service, including load its kernel-mode driver. If CHIPSEC service is already running then it will attempt to connect to the existing service.

    Use –no-driver command-line option to skip loading the kernel module. This option will only work for certain commands or modules.

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    Navigation

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    Running in Shell

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    Running in Shell

    Basic usage

    # python chipsec_main.py

    # python chipsec_util.py

    For help, run

    # python chipsec_main.py --help

    # python chipsec_util.py --help

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    Using as a Python Package

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    Using as a Python Package

    Install CHIPSEC manually or from PyPI. You can then use CHIPSEC from your Python project or from the Python shell:

    To install and run CHIPSEC as a package:

    # python setup.py install

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    Using as a Python Package# python setup.py build_ext -i

    # sudo python chipsec_main.py

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    chipsec_main options

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    chipsec_main options

    usage: chipsec_main.py [options]
 
 Options:
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    chipsec_main options-nl                                 Chipsec won't save logs automatically
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    chipsec_util options

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    chipsec_util options

    usage: chipsec_util.py [options] <command> [<args>]
 
 Options:
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    chipsec_util optionsargs                         Additional arguments for specific command. All numeric values are in hex. <width> is in {1 - byte, 2 - word, 4 - dword}
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    Quick search

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