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m68k_core_x86.c
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/*
Copyright 2013 Michael Pavone
This file is part of BlastEm.
BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
*/
#include "gen_x86.h"
#include "m68k_core.h"
#include "m68k_internal.h"
#include "68kinst.h"
#include "mem.h"
#include "backend.h"
#include "util.h"
#include <stdio.h>
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
enum {
FLAG_X,
FLAG_N,
FLAG_Z,
FLAG_V,
FLAG_C
};
void set_flag(m68k_options * opts, uint8_t val, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
mov_ir(&opts->gen.code, val, opts->flag_regs[flag], SZ_B);
} else {
int8_t offset = offsetof(m68k_context, flags) + flag;
if (offset) {
mov_irdisp(&opts->gen.code, val, opts->gen.context_reg, offset, SZ_B);
} else {
mov_irind(&opts->gen.code, val, opts->gen.context_reg, SZ_B);
}
}
}
void set_flag_cond(m68k_options *opts, uint8_t cond, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
setcc_r(&opts->gen.code, cond, opts->flag_regs[flag]);
} else {
int8_t offset = offsetof(m68k_context, flags) + flag;
if (offset) {
setcc_rdisp(&opts->gen.code, cond, opts->gen.context_reg, offset);
} else {
setcc_rind(&opts->gen.code, cond, opts->gen.context_reg);
}
}
}
void check_flag(m68k_options *opts, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
cmp_ir(&opts->gen.code, 0, opts->flag_regs[flag], SZ_B);
} else {
cmp_irdisp(&opts->gen.code, 0, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B);
}
}
void flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg)
{
if (opts->flag_regs[flag] >= 0) {
mov_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B);
} else {
int8_t offset = offsetof(m68k_context, flags) + flag;
if (offset) {
mov_rdispr(&opts->gen.code, opts->gen.context_reg, offset, reg, SZ_B);
} else {
mov_rindr(&opts->gen.code, opts->gen.context_reg, reg, SZ_B);
}
}
}
void reg_to_flag(m68k_options *opts, uint8_t reg, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
mov_rr(&opts->gen.code, reg, opts->flag_regs[flag], SZ_B);
} else {
int8_t offset = offsetof(m68k_context, flags) + flag;
if (offset) {
mov_rrdisp(&opts->gen.code, reg, opts->gen.context_reg, offset, SZ_B);
} else {
mov_rrind(&opts->gen.code, reg, opts->gen.context_reg, SZ_B);
}
}
}
void flag_to_flag(m68k_options *opts, uint8_t flag1, uint8_t flag2)
{
code_info *code = &opts->gen.code;
if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) {
mov_rr(code, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B);
} else if(opts->flag_regs[flag1] >= 0) {
mov_rrdisp(code, opts->flag_regs[flag1], opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B);
} else if (opts->flag_regs[flag2] >= 0) {
mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->flag_regs[flag2], SZ_B);
} else {
push_r(code, opts->gen.scratch1);
mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->gen.scratch1, SZ_B);
mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B);
pop_r(code, opts->gen.scratch1);
}
}
void update_flags(m68k_options *opts, uint32_t update_mask)
{
uint8_t native_flags[] = {0, CC_S, CC_Z, CC_O, CC_C};
for (int8_t flag = FLAG_C; flag >= FLAG_X; --flag)
{
if (update_mask & X0 << (flag*3)) {
set_flag(opts, 0, flag);
} else if(update_mask & X1 << (flag*3)) {
set_flag(opts, 1, flag);
} else if(update_mask & X << (flag*3)) {
if (flag == FLAG_X) {
if (opts->flag_regs[FLAG_C] >= 0 || !(update_mask & (C0|C1|C))) {
flag_to_flag(opts, FLAG_C, FLAG_X);
} else if(update_mask & C0) {
set_flag(opts, 0, flag);
} else if(update_mask & C1) {
set_flag(opts, 1, flag);
} else {
set_flag_cond(opts, CC_C, flag);
}
} else {
set_flag_cond(opts, native_flags[flag], flag);
}
}
}
}
void flag_to_carry(m68k_options * opts, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
bt_ir(&opts->gen.code, 0, opts->flag_regs[flag], SZ_B);
} else {
bt_irdisp(&opts->gen.code, 0, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B);
}
}
void or_flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg)
{
if (opts->flag_regs[flag] >= 0) {
or_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B);
} else {
or_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, reg, SZ_B);
}
}
void xor_flag_to_reg(m68k_options *opts, uint8_t flag, uint8_t reg)
{
if (opts->flag_regs[flag] >= 0) {
xor_rr(&opts->gen.code, opts->flag_regs[flag], reg, SZ_B);
} else {
xor_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, reg, SZ_B);
}
}
void xor_flag(m68k_options *opts, uint8_t val, uint8_t flag)
{
if (opts->flag_regs[flag] >= 0) {
xor_ir(&opts->gen.code, val, opts->flag_regs[flag], SZ_B);
} else {
xor_irdisp(&opts->gen.code, val, opts->gen.context_reg, offsetof(m68k_context, flags) + flag, SZ_B);
}
}
void cmp_flags(m68k_options *opts, uint8_t flag1, uint8_t flag2)
{
code_info *code = &opts->gen.code;
if (opts->flag_regs[flag1] >= 0 && opts->flag_regs[flag2] >= 0) {
cmp_rr(code, opts->flag_regs[flag1], opts->flag_regs[flag2], SZ_B);
} else if(opts->flag_regs[flag1] >= 0 || opts->flag_regs[flag2] >= 0) {
if (opts->flag_regs[flag2] >= 0) {
uint8_t tmp = flag1;
flag1 = flag2;
flag2 = tmp;
}
cmp_rrdisp(code, opts->flag_regs[flag1], opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B);
} else {
mov_rdispr(code, opts->gen.context_reg, offsetof(m68k_context, flags) + flag1, opts->gen.scratch1, SZ_B);
cmp_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(m68k_context, flags) + flag2, SZ_B);
}
}
void areg_to_native(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->aregs[reg] >= 0) {
mov_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_D);
} else {
mov_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_D);
}
}
void dreg_to_native(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->dregs[reg] >= 0) {
mov_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_D);
} else {
mov_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_D);
}
}
void areg_to_native_sx(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->aregs[reg] >= 0) {
movsx_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_W, SZ_D);
} else {
movsx_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_W, SZ_D);
}
}
void dreg_to_native_sx(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->dregs[reg] >= 0) {
movsx_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_W, SZ_D);
} else {
movsx_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_W, SZ_D);
}
}
void native_to_areg(m68k_options *opts, uint8_t native_reg, uint8_t reg)
{
if (opts->aregs[reg] >= 0) {
mov_rr(&opts->gen.code, native_reg, opts->aregs[reg], SZ_D);
} else {
mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, areg_offset(reg), SZ_D);
}
}
void native_to_dreg(m68k_options *opts, uint8_t native_reg, uint8_t reg)
{
if (opts->dregs[reg] >= 0) {
mov_rr(&opts->gen.code, native_reg, opts->dregs[reg], SZ_D);
} else {
mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, dreg_offset(reg), SZ_D);
}
}
void ldi_areg(m68k_options *opts, int32_t value, uint8_t reg)
{
if (opts->aregs[reg] >= 0) {
mov_ir(&opts->gen.code, value, opts->aregs[reg], SZ_D);
} else {
mov_irdisp(&opts->gen.code, value, opts->gen.context_reg, areg_offset(reg), SZ_D);
}
}
void ldi_native(m68k_options *opts, int32_t value, uint8_t reg)
{
mov_ir(&opts->gen.code, value, reg, SZ_D);
}
void addi_native(m68k_options *opts, int32_t value, uint8_t reg)
{
add_ir(&opts->gen.code, value, reg, SZ_D);
}
void subi_native(m68k_options *opts, int32_t value, uint8_t reg)
{
sub_ir(&opts->gen.code, value, reg, SZ_D);
}
void push_native(m68k_options *opts, uint8_t reg)
{
push_r(&opts->gen.code, reg);
}
void pop_native(m68k_options *opts, uint8_t reg)
{
pop_r(&opts->gen.code, reg);
}
void sign_extend16_native(m68k_options *opts, uint8_t reg)
{
movsx_rr(&opts->gen.code, reg, reg, SZ_W, SZ_D);
}
void addi_areg(m68k_options *opts, int32_t val, uint8_t reg)
{
if (opts->aregs[reg] >= 0) {
add_ir(&opts->gen.code, val, opts->aregs[reg], SZ_D);
} else {
add_irdisp(&opts->gen.code, val, opts->gen.context_reg, areg_offset(reg), SZ_D);
}
}
void subi_areg(m68k_options *opts, int32_t val, uint8_t reg)
{
if (opts->aregs[reg] >= 0) {
sub_ir(&opts->gen.code, val, opts->aregs[reg], SZ_D);
} else {
sub_irdisp(&opts->gen.code, val, opts->gen.context_reg, areg_offset(reg), SZ_D);
}
}
void add_areg_native(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->aregs[reg] >= 0) {
add_rr(&opts->gen.code, opts->aregs[reg], native_reg, SZ_D);
} else {
add_rdispr(&opts->gen.code, opts->gen.context_reg, areg_offset(reg), native_reg, SZ_D);
}
}
void add_dreg_native(m68k_options *opts, uint8_t reg, uint8_t native_reg)
{
if (opts->dregs[reg] >= 0) {
add_rr(&opts->gen.code, opts->dregs[reg], native_reg, SZ_D);
} else {
add_rdispr(&opts->gen.code, opts->gen.context_reg, dreg_offset(reg), native_reg, SZ_D);
}
}
void calc_areg_displace(m68k_options *opts, m68k_op_info *op, uint8_t native_reg)
{
areg_to_native(opts, op->params.regs.pri, native_reg);
add_ir(&opts->gen.code, op->params.regs.displacement & 0x8000 ? op->params.regs.displacement | 0xFFFF0000 : op->params.regs.displacement, native_reg, SZ_D);
}
void calc_index_disp8(m68k_options *opts, m68k_op_info *op, uint8_t native_reg)
{
uint8_t sec_reg = (op->params.regs.sec >> 1) & 0x7;
if (op->params.regs.sec & 1) {
if (op->params.regs.sec & 0x10) {
add_areg_native(opts, sec_reg, native_reg);
} else {
add_dreg_native(opts, sec_reg, native_reg);
}
} else {
uint8_t other_reg = native_reg == opts->gen.scratch1 ? opts->gen.scratch2 : opts->gen.scratch1;
if (op->params.regs.sec & 0x10) {
areg_to_native_sx(opts, sec_reg, other_reg);
} else {
dreg_to_native_sx(opts, sec_reg, other_reg);
}
add_rr(&opts->gen.code, other_reg, native_reg, SZ_D);
}
if (op->params.regs.displacement) {
add_ir(&opts->gen.code, op->params.regs.displacement, native_reg, SZ_D);
}
}
void calc_areg_index_disp8(m68k_options *opts, m68k_op_info *op, uint8_t native_reg)
{
areg_to_native(opts, op->params.regs.pri, native_reg);
calc_index_disp8(opts, op, native_reg);
}
void m68k_check_cycles_int_latch(m68k_options *opts)
{
code_info *code = &opts->gen.code;
check_alloc_code(code, 3*MAX_INST_LEN);
uint8_t cc;
if (opts->gen.limit < 0) {
cmp_ir(code, 1, opts->gen.cycles, SZ_D);
cc = CC_NS;
} else {
cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D);
cc = CC_A;
}
code_ptr jmp_off = code->cur+1;
jcc(code, cc, jmp_off+1);
call(code, opts->handle_int_latch);
*jmp_off = code->cur - (jmp_off+1);
}
uint8_t translate_m68k_op(m68kinst * inst, host_ea * ea, m68k_options * opts, uint8_t dst)
{
code_info *code = &opts->gen.code;
m68k_op_info *op = dst ? &inst->dst : &inst->src;
int8_t reg = native_reg(op, opts);
uint8_t sec_reg;
uint8_t ret = 1;
int32_t dec_amount, inc_amount;
if (reg >= 0) {
ea->mode = MODE_REG_DIRECT;
if (!dst && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
movsx_rr(code, reg, opts->gen.scratch1, SZ_W, SZ_D);
ea->base = opts->gen.scratch1;
#ifdef X86_32
} else if (reg > RBX && inst->extra.size == OPSIZE_BYTE) {
mov_rr(code, reg, opts->gen.scratch1, SZ_D);
ea->base = opts->gen.scratch1;
#endif
} else {
ea->base = reg;
}
return 0;
}
switch (op->addr_mode)
{
case MODE_REG:
case MODE_AREG:
//We only get one memory parameter, so if the dst operand is a register in memory,
//we need to copy this to a temp register first if we're translating the src operand
if (dst || native_reg(&(inst->dst), opts) >= 0 || inst->dst.addr_mode == MODE_UNUSED || !(inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG)
|| inst->op == M68K_EXG) {
ea->mode = MODE_REG_DISPLACE8;
ea->base = opts->gen.context_reg;
ea->disp = reg_offset(op);
} else {
if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
movsx_rdispr(code, opts->gen.context_reg, reg_offset(op), opts->gen.scratch1, SZ_W, SZ_D);
} else {
mov_rdispr(code, opts->gen.context_reg, reg_offset(op), opts->gen.scratch1, inst->extra.size);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
//we're explicitly handling the areg dest here, so we exit immediately
return 0;
}
ret = 0;
break;
case MODE_AREG_PREDEC:
if (dst && inst->src.addr_mode == MODE_AREG_PREDEC) {
push_r(code, opts->gen.scratch1);
}
dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (op->params.regs.pri == 7 ? 2 :1));
if (!dst || (
inst->op != M68K_MOVE && inst->op != M68K_MOVEM
&& inst->op != M68K_SUBX && inst->op != M68K_ADDX
&& inst->op != M68K_ABCD && inst->op != M68K_SBCD
)) {
cycles(&opts->gen, PREDEC_PENALTY);
}
subi_areg(opts, dec_amount, op->params.regs.pri);
case MODE_AREG_INDIRECT:
case MODE_AREG_POSTINC:
areg_to_native(opts, op->params.regs.pri, opts->gen.scratch1);
m68k_read_size(opts, inst->extra.size);
if (dst) {
if (inst->src.addr_mode == MODE_AREG_PREDEC) {
//restore src operand to opts->gen.scratch2
pop_r(code, opts->gen.scratch2);
} else {
//save reg value in opts->gen.scratch2 so we can use it to save the result in memory later
areg_to_native(opts, op->params.regs.pri, opts->gen.scratch2);
}
}
if (op->addr_mode == MODE_AREG_POSTINC) {
inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (op->params.regs.pri == 7 ? 2 : 1));
addi_areg(opts, inc_amount, op->params.regs.pri);
}
ea->mode = MODE_REG_DIRECT;
ea->base = (!dst && inst->dst.addr_mode == MODE_AREG_PREDEC && inst->op != M68K_MOVE) ? opts->gen.scratch2 : opts->gen.scratch1;
break;
case MODE_AREG_DISPLACE:
cycles(&opts->gen, BUS);
calc_areg_displace(opts, op, opts->gen.scratch1);
if (dst) {
push_r(code, opts->gen.scratch1);
}
m68k_read_size(opts, inst->extra.size);
if (dst) {
pop_r(code, opts->gen.scratch2);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
break;
case MODE_AREG_INDEX_DISP8:
cycles(&opts->gen, 6);
calc_areg_index_disp8(opts, op, opts->gen.scratch1);
if (dst) {
push_r(code, opts->gen.scratch1);
}
m68k_read_size(opts, inst->extra.size);
if (dst) {
pop_r(code, opts->gen.scratch2);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
break;
case MODE_PC_DISPLACE:
cycles(&opts->gen, BUS);
mov_ir(code, op->params.regs.displacement + inst->address+2, opts->gen.scratch1, SZ_D);
if (dst) {
push_r(code, opts->gen.scratch1);
}
m68k_read_size(opts, inst->extra.size);
if (dst) {
pop_r(code, opts->gen.scratch2);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
break;
case MODE_PC_INDEX_DISP8:
cycles(&opts->gen, 6);
mov_ir(code, inst->address+2, opts->gen.scratch1, SZ_D);
calc_index_disp8(opts, op, opts->gen.scratch1);
if (dst) {
push_r(code, opts->gen.scratch1);
}
m68k_read_size(opts, inst->extra.size);
if (dst) {
pop_r(code, opts->gen.scratch2);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
break;
case MODE_ABSOLUTE:
case MODE_ABSOLUTE_SHORT:
cycles(&opts->gen, op->addr_mode == MODE_ABSOLUTE ? BUS*2 : BUS);
mov_ir(code, op->params.immed, opts->gen.scratch1, SZ_D);
if (dst) {
push_r(code, opts->gen.scratch1);
}
m68k_read_size(opts, inst->extra.size);
if (dst) {
pop_r(code, opts->gen.scratch2);
}
ea->mode = MODE_REG_DIRECT;
ea->base = opts->gen.scratch1;
break;
case MODE_IMMEDIATE:
case MODE_IMMEDIATE_WORD:
if (inst->variant != VAR_QUICK) {
cycles(&opts->gen, (inst->extra.size == OPSIZE_LONG && op->addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
}
ea->mode = MODE_IMMED;
ea->disp = op->params.immed;
//sign extend value when the destination is an address register
if (inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && ea->disp & 0x8000) {
ea->disp |= 0xFFFF0000;
}
return inst->variant != VAR_QUICK;
default:
m68k_disasm(inst, disasm_buf);
fatal_error("%X: %s\naddress mode %d not implemented (%s)\n", inst->address, disasm_buf, op->addr_mode, dst ? "dst" : "src");
}
if (!dst && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD) {
if (ea->mode == MODE_REG_DIRECT) {
movsx_rr(code, ea->base, opts->gen.scratch1, SZ_W, SZ_D);
} else {
movsx_rdispr(code, ea->base, ea->disp, opts->gen.scratch1, SZ_W, SZ_D);
ea->mode = MODE_REG_DIRECT;
}
ea->base = opts->gen.scratch1;
}
return ret;
}
void check_user_mode_swap_ssp_usp(m68k_options *opts)
{
code_info * code = &opts->gen.code;
//Check if we've switched to user mode and swap stack pointers if needed
bt_irdisp(code, 5, opts->gen.context_reg, offsetof(m68k_context, status), SZ_B);
code_ptr end_off = code->cur + 1;
jcc(code, CC_C, code->cur + 2);
swap_ssp_usp(opts);
*end_off = code->cur - (end_off + 1);
}
void translate_m68k_move(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
int8_t reg, flags_reg, sec_reg;
uint8_t dir = 0;
int32_t offset;
int32_t inc_amount, dec_amount;
host_ea src;
uint8_t needs_int_latch = translate_m68k_op(inst, &src, opts, 0);
reg = native_reg(&(inst->dst), opts);
if (inst->dst.addr_mode != MODE_AREG) {
if (src.mode == MODE_REG_DIRECT) {
flags_reg = src.base;
} else {
if (reg >= 0) {
flags_reg = reg;
} else {
if(src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
src.mode = MODE_REG_DIRECT;
flags_reg = src.base = opts->gen.scratch1;
}
}
}
uint8_t size = inst->extra.size;
switch(inst->dst.addr_mode)
{
case MODE_AREG:
size = OPSIZE_LONG;
case MODE_REG:
if (reg >= 0) {
if (src.mode == MODE_REG_DIRECT) {
mov_rr(code, src.base, reg, size);
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, reg, size);
} else {
mov_ir(code, src.disp, reg, size);
}
} else if(src.mode == MODE_REG_DIRECT) {
mov_rrdisp(code, src.base, opts->gen.context_reg, reg_offset(&(inst->dst)), size);
} else {
mov_irdisp(code, src.disp, opts->gen.context_reg, reg_offset(&(inst->dst)), size);
}
break;
case MODE_AREG_PREDEC:
dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
case MODE_AREG_INDIRECT:
case MODE_AREG_POSTINC:
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
subi_areg(opts, dec_amount, inst->dst.params.regs.pri);
}
areg_to_native(opts, inst->dst.params.regs.pri, opts->gen.scratch2);
break;
case MODE_AREG_DISPLACE:
cycles(&opts->gen, BUS);
calc_areg_displace(opts, &inst->dst, opts->gen.scratch2);
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
break;
case MODE_AREG_INDEX_DISP8:
cycles(&opts->gen, 6);//TODO: Check to make sure this is correct
//calc_areg_index_disp8 will clober scratch1 when a 16-bit index is used
if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) {
push_r(code, opts->gen.scratch1);
}
calc_areg_index_disp8(opts, &inst->dst, opts->gen.scratch2);
if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) {
pop_r(code, opts->gen.scratch1);
}
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
break;
case MODE_PC_DISPLACE:
cycles(&opts->gen, BUS);
mov_ir(code, inst->dst.params.regs.displacement + inst->address+2, opts->gen.scratch2, SZ_D);
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
break;
case MODE_PC_INDEX_DISP8:
cycles(&opts->gen, 6);//TODO: Check to make sure this is correct
mov_ir(code, inst->address, opts->gen.scratch2, SZ_D);
if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) {
push_r(code, opts->gen.scratch1);
}
calc_index_disp8(opts, &inst->dst, opts->gen.scratch2);
if (src.base == opts->gen.scratch1 && !(inst->dst.params.regs.sec & 1)) {
pop_r(code, opts->gen.scratch1);
}
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
break;
case MODE_ABSOLUTE:
case MODE_ABSOLUTE_SHORT:
if (src.mode == MODE_REG_DIRECT) {
if (src.base != opts->gen.scratch1) {
mov_rr(code, src.base, opts->gen.scratch1, inst->extra.size);
}
} else if (src.mode == MODE_REG_DISPLACE8) {
mov_rdispr(code, src.base, src.disp, opts->gen.scratch1, inst->extra.size);
} else {
mov_ir(code, src.disp, opts->gen.scratch1, inst->extra.size);
}
if (inst->dst.addr_mode == MODE_ABSOLUTE) {
cycles(&opts->gen, BUS*2);
} else {
cycles(&opts->gen, BUS);
}
mov_ir(code, inst->dst.params.immed, opts->gen.scratch2, SZ_D);
break;
default:
m68k_disasm(inst, disasm_buf);
fatal_error("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
}
if (inst->dst.addr_mode != MODE_AREG) {
cmp_ir(code, 0, flags_reg, inst->extra.size);
update_flags(opts, N|Z|V0|C0);
}
if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
if (inst->extra.size == OPSIZE_LONG) {
//We want the int latch to occur between the two writes,
//but that's a pain to do without refactoring how 32-bit writes work
//workaround it by temporarily increasing the cycle count before the check
cycles(&opts->gen, BUS);
}
m68k_check_cycles_int_latch(opts);
if (inst->extra.size == OPSIZE_LONG) {
//and then backing out that extra increment here before the write happens
cycles(&opts->gen, -BUS);
}
m68k_write_size(opts, inst->extra.size, inst->dst.addr_mode == MODE_AREG_PREDEC);
if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : (inst->dst.params.regs.pri == 7 ? 2 : 1));
addi_areg(opts, inc_amount, inst->dst.params.regs.pri);
}
} else if (needs_int_latch) {
m68k_check_cycles_int_latch(opts);
}
//add cycles for prefetch
cycles(&opts->gen, BUS);
}
void translate_m68k_ext(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
host_ea dst_op;
uint8_t dst_size = inst->extra.size;
inst->extra.size--;
translate_m68k_op(inst, &dst_op, opts, 1);
if (dst_op.mode == MODE_REG_DIRECT) {
movsx_rr(code, dst_op.base, dst_op.base, inst->extra.size, dst_size);
cmp_ir(code, 0, dst_op.base, dst_size);
} else {
movsx_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, inst->extra.size, dst_size);
cmp_ir(code, 0, opts->gen.scratch1, dst_size);
mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, dst_size);
}
inst->extra.size = dst_size;
update_flags(opts, N|V0|C0|Z);
cycles(&opts->gen, BUS);
//M68K EXT only operates on registers so no need for a call to save result here
}
uint8_t m68k_eval_cond(m68k_options * opts, uint8_t cc)
{
uint8_t cond = CC_NZ;
switch (cc)
{
case COND_HIGH:
cond = CC_Z;
case COND_LOW_SAME:
flag_to_reg(opts, FLAG_Z, opts->gen.scratch1);
or_flag_to_reg(opts, FLAG_C, opts->gen.scratch1);
break;
case COND_CARRY_CLR:
cond = CC_Z;
case COND_CARRY_SET:
check_flag(opts, FLAG_C);
break;
case COND_NOT_EQ:
cond = CC_Z;
case COND_EQ:
check_flag(opts, FLAG_Z);
break;
case COND_OVERF_CLR:
cond = CC_Z;
case COND_OVERF_SET:
check_flag(opts, FLAG_V);
break;
case COND_PLUS:
cond = CC_Z;
case COND_MINUS:
check_flag(opts, FLAG_N);
break;
case COND_GREATER_EQ:
cond = CC_Z;
case COND_LESS:
cmp_flags(opts, FLAG_N, FLAG_V);
break;
case COND_GREATER:
cond = CC_Z;
case COND_LESS_EQ:
flag_to_reg(opts, FLAG_V, opts->gen.scratch1);
xor_flag_to_reg(opts, FLAG_N, opts->gen.scratch1);
or_flag_to_reg(opts, FLAG_Z, opts->gen.scratch1);
break;
}
return cond;
}
void translate_m68k_bcc(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
int32_t disp = inst->src.params.immed;
uint32_t after = inst->address + 2;
if (inst->extra.cond == COND_TRUE) {
cycles(&opts->gen, 10);
jump_m68k_abs(opts, after + disp);
} else {
uint8_t cond = m68k_eval_cond(opts, inst->extra.cond);
code_ptr do_branch = code->cur + 1;
jcc(code, cond, do_branch);
cycles(&opts->gen, inst->variant == VAR_BYTE ? 8 : 12);
code_ptr done = code->cur + 1;
jmp(code, done);
*do_branch = code->cur - (do_branch + 1);
cycles(&opts->gen, 10);
code_ptr dest_addr = get_native_address(opts, after + disp);
if (!dest_addr) {
opts->gen.deferred = defer_address(opts->gen.deferred, after + disp, code->cur + 1);
//dummy address to be replaced later, make sure it generates a 4-byte displacement
dest_addr = code->cur + 256;
}
jmp(code, dest_addr);
*done = code->cur - (done + 1);
}
}
void translate_m68k_scc(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
uint8_t cond = inst->extra.cond;
host_ea dst_op;
inst->extra.size = OPSIZE_BYTE;
translate_m68k_op(inst, &dst_op, opts, 1);
if (cond == COND_TRUE || cond == COND_FALSE) {
if ((inst->dst.addr_mode == MODE_REG || inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
cycles(&opts->gen, 6);
} else {
cycles(&opts->gen, BUS);
}
if (dst_op.mode == MODE_REG_DIRECT) {
mov_ir(code, cond == COND_TRUE ? 0xFF : 0, dst_op.base, SZ_B);
} else {
mov_irdisp(code, cond == COND_TRUE ? 0xFF : 0, dst_op.base, dst_op.disp, SZ_B);
}
} else {
uint8_t cc = m68k_eval_cond(opts, cond);
check_alloc_code(code, 6*MAX_INST_LEN);
code_ptr true_off = code->cur + 1;
jcc(code, cc, code->cur+2);
cycles(&opts->gen, BUS);
if (dst_op.mode == MODE_REG_DIRECT) {
mov_ir(code, 0, dst_op.base, SZ_B);
} else {
mov_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B);
}
code_ptr end_off = code->cur+1;
jmp(code, code->cur+2);
*true_off = code->cur - (true_off+1);
cycles(&opts->gen, inst->dst.addr_mode == MODE_REG ? 6 : 4);
if (dst_op.mode == MODE_REG_DIRECT) {
mov_ir(code, 0xFF, dst_op.base, SZ_B);
} else {
mov_irdisp(code, 0xFF, dst_op.base, dst_op.disp, SZ_B);
}
*end_off = code->cur - (end_off+1);
}
m68k_save_result(inst, opts);
}
void translate_m68k_dbcc(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
//best case duration
cycles(&opts->gen, 10);
code_ptr skip_loc = NULL;
//TODO: Check if COND_TRUE technically valid here even though
//it's basically a slow NOP
if (inst->extra.cond != COND_FALSE) {
uint8_t cond = m68k_eval_cond(opts, inst->extra.cond);
check_alloc_code(code, 6*MAX_INST_LEN);
skip_loc = code->cur + 1;
jcc(code, cond, code->cur + 2);
}
if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
sub_ir(code, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
cmp_ir(code, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
} else {
sub_irdisp(code, 1, opts->gen.context_reg, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
cmp_irdisp(code, -1, opts->gen.context_reg, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
}
code_ptr loop_end_loc = code->cur + 1;
jcc(code, CC_Z, code->cur + 2);
uint32_t after = inst->address + 2;
jump_m68k_abs(opts, after + inst->src.params.immed);
*loop_end_loc = code->cur - (loop_end_loc+1);
if (skip_loc) {
cycles(&opts->gen, 2);
*skip_loc = code->cur - (skip_loc+1);
cycles(&opts->gen, 2);
} else {
cycles(&opts->gen, 4);
}
}
void translate_m68k_movep(m68k_options * opts, m68kinst * inst)
{
code_info *code = &opts->gen.code;
int8_t reg;
cycles(&opts->gen, BUS*2);
if (inst->src.addr_mode == MODE_REG) {
calc_areg_displace(opts, &inst->dst, opts->gen.scratch2);
reg = native_reg(&(inst->src), opts);
if (inst->extra.size == OPSIZE_LONG) {
if (reg >= 0) {
mov_rr(code, reg, opts->gen.scratch1, SZ_D);
shr_ir(code, 24, opts->gen.scratch1, SZ_D);
push_r(code, opts->gen.scratch2);
call(code, opts->write_8);
pop_r(code, opts->gen.scratch2);
mov_rr(code, reg, opts->gen.scratch1, SZ_D);
shr_ir(code, 16, opts->gen.scratch1, SZ_D);
} else {
mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+3, opts->gen.scratch1, SZ_B);
push_r(code, opts->gen.scratch2);
call(code, opts->write_8);
pop_r(code, opts->gen.scratch2);
mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+2, opts->gen.scratch1, SZ_B);
}
add_ir(code, 2, opts->gen.scratch2, SZ_D);
push_r(code, opts->gen.scratch2);
call(code, opts->write_8);
pop_r(code, opts->gen.scratch2);
add_ir(code, 2, opts->gen.scratch2, SZ_D);
}
if (reg >= 0) {
mov_rr(code, reg, opts->gen.scratch1, SZ_W);
shr_ir(code, 8, opts->gen.scratch1, SZ_W);
push_r(code, opts->gen.scratch2);
call(code, opts->write_8);
pop_r(code, opts->gen.scratch2);
mov_rr(code, reg, opts->gen.scratch1, SZ_W);
} else {
mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src))+1, opts->gen.scratch1, SZ_B);
push_r(code, opts->gen.scratch2);
call(code, opts->write_8);
pop_r(code, opts->gen.scratch2);
mov_rdispr(code, opts->gen.context_reg, reg_offset(&(inst->src)), opts->gen.scratch1, SZ_B);
}
add_ir(code, 2, opts->gen.scratch2, SZ_D);
call(code, opts->write_8);
} else {
calc_areg_displace(opts, &inst->src, opts->gen.scratch1);
reg = native_reg(&(inst->dst), opts);
if (inst->extra.size == OPSIZE_LONG) {
if (reg >= 0) {
push_r(code, opts->gen.scratch1);
call(code, opts->read_8);
shl_ir(code, 24, opts->gen.scratch1, SZ_D);
mov_rr(code, opts->gen.scratch1, reg, SZ_D);
pop_r(code, opts->gen.scratch1);
add_ir(code, 2, opts->gen.scratch1, SZ_D);
push_r(code, opts->gen.scratch1);
call(code, opts->read_8);
movzx_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B, SZ_W);
shl_ir(code, 16, opts->gen.scratch1, SZ_D);
or_rr(code, opts->gen.scratch1, reg, SZ_D);
} else {
push_r(code, opts->gen.scratch1);
call(code, opts->read_8);
mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst))+3, SZ_B);
pop_r(code, opts->gen.scratch1);
add_ir(code, 2, opts->gen.scratch1, SZ_D);
push_r(code, opts->gen.scratch1);
call(code, opts->read_8);
mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, reg_offset(&(inst->dst))+2, SZ_B);
}
pop_r(code, opts->gen.scratch1);