From 6d21d1adc91fbda84e6c8b99a3b1e822eb0d1686 Mon Sep 17 00:00:00 2001
From: wxrdnx <wxrdnx@protonmail.com>
Date: Mon, 20 Jan 2025 14:19:39 -0600
Subject: [PATCH] Add RISC-V MachRegister Unit Test

---
 MachRegister/base_registers/CMakeLists.txt |  5 ++++
 MachRegister/base_registers/riscv64.cpp    | 27 ++++++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 MachRegister/base_registers/riscv64.cpp

diff --git a/MachRegister/base_registers/CMakeLists.txt b/MachRegister/base_registers/CMakeLists.txt
index 29a9420..3a0e826 100644
--- a/MachRegister/base_registers/CMakeLists.txt
+++ b/MachRegister/base_registers/CMakeLists.txt
@@ -30,6 +30,11 @@ target_include_directories(basereg_ppc32 PRIVATE ${UNIT_TESTS_INCLUDES})
 target_link_libraries(basereg_ppc32 PRIVATE Dyninst::common)
 add_test(NAME machregister_basereg_ppc32 COMMAND basereg_ppc32)
 
+add_executable(basereg_riscv64 riscv64.cpp)
+target_compile_options(basereg_riscv64 PRIVATE ${UNIT_TESTS_WARNING_FLAGS})
+target_include_directories(basereg_riscv64 PRIVATE ${UNIT_TESTS_INCLUDES})
+target_link_libraries(basereg_riscv64 PRIVATE Dyninst::common)
+add_test(NAME machregister_basereg_riscv64 COMMAND basereg_riscv64)
 
 # These are disabled until we can decide on how to represent base registers for AMDGPU
 add_executable(basereg_amdgpu_gfx908 amdgpu_gfx908.cpp)
diff --git a/MachRegister/base_registers/riscv64.cpp b/MachRegister/base_registers/riscv64.cpp
new file mode 100644
index 0000000..51516be
--- /dev/null
+++ b/MachRegister/base_registers/riscv64.cpp
@@ -0,0 +1,27 @@
+#include "basereg_check.h"
+#include "registers/riscv64_regs.h"
+
+int main() {
+
+  // GPR 64 -> 64
+  BASEREG_CHECK(riscv64::x0, riscv64::x0);
+  BASEREG_CHECK(riscv64::x8, riscv64::x0);
+  BASEREG_CHECK(riscv64::x31, riscv64::x0);
+
+  // FPR 32 -> *
+  BASEREG_CHECK(riscv64::f0_32, riscv64::f0);
+  BASEREG_CHECK(riscv64::f8_32, riscv64::f0);
+  BASEREG_CHECK(riscv64::f31_32, riscv64::f0);
+
+  // FPR 64 -> *
+  BASEREG_CHECK(riscv64::f0_64, riscv64::f0);
+  BASEREG_CHECK(riscv64::f8_64, riscv64::f0);
+  BASEREG_CHECK(riscv64::f31_64, riscv64::f0);
+
+  // FPR * -> *
+  BASEREG_CHECK(riscv64::f0, riscv64::f0);
+  BASEREG_CHECK(riscv64::f8, riscv64::f0);
+  BASEREG_CHECK(riscv64::f31, riscv64::f0);
+
+  return EXIT_SUCCESS;
+}