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SMC.ec
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(* SMC.ec *)
(* Secure Message Communication *)
prover quorum=2 ["Alt-Ergo" "Z3"].
require import AllCore List FSet SmtMap Distr ListAux ListPO.
require import UCCoreDiffieHellman FSetAux.
require Forward KeyExchange RedundantHashing.
(* theory parameters *)
(* port index of adversary that forwarding functionalities communicate
with *)
op adv_fw_pi : int.
(* port index of adversary for key exchange's simulator *)
op ke_sim_adv_pi : int.
(* port index of adversary for SMC's simulator *)
op smc_sim_adv_pi : int.
axiom smc_pi_uniq : uniq [smc_sim_adv_pi; ke_sim_adv_pi; adv_fw_pi; 0].
(* end theory parameters *)
(* request sent to port index 1 of SMC functionality: pt1 wants to
send t to pt2 *)
op smc_req (func : addr, pt1 pt2 : port, t : text) : msg =
(Dir, (func, 1), pt1,
UnivPair (UnivPort pt2, UnivBase (BaseText t))).
op dec_smc_req (m : msg) : (addr * port * port * text) option =
let (mod, pt1, pt2, v) = m
in (mod = Adv \/ pt1.`2 <> 1 \/ ! is_univ_pair v) ?
None :
let (v1, v2) = oget (dec_univ_pair v)
in (! is_univ_port v1 \/ ! is_univ_base v2) ?
None :
let bse = oget (dec_univ_base v2)
in (! is_base_text bse) ?
None :
Some (pt1.`1, pt2, oget (dec_univ_port v1),
oget (dec_base_text bse)).
lemma enc_dec_smc_req (func : addr, pt1 pt2 : port, t : text) :
dec_smc_req (smc_req func pt1 pt2 t) = Some (func, pt1, pt2, t).
proof.
by rewrite /smc_req /dec_smc_req /=
(is_univ_pair (UnivPort pt2, UnivBase (BaseText t))).
qed.
lemma dec_enc_smc_req (m : msg, func : addr, pt1 pt2 : port, t : text) :
dec_smc_req m = Some (func, pt1, pt2, t) =>
smc_req func pt1 pt2 t = m.
proof.
case m => mod pt1' pt2' u'.
rewrite /dec_smc_req /smc_req /=.
case (mod = Adv \/ pt1'.`2 <> 1 \/ ! is_univ_pair u') => //.
rewrite !negb_or /= not_adv.
move => [#] -> pt1'_2 iup_u'.
have [] p : exists (p : univ * univ), dec_univ_pair u' = Some p.
exists (oget (dec_univ_pair u')); by rewrite -some_oget.
case p => v1 v2 /dec_enc_univ_pair -> /=.
case (! is_univ_port v1 \/ ! is_univ_base v2) => //.
rewrite !negb_or /=.
move => [#] iupt_v1 iubse_v2.
have [] pt2'' : exists (pt2'' : port), dec_univ_port v1 = Some pt2''.
exists (oget (dec_univ_port v1)); by rewrite -some_oget.
move => /dec_enc_univ_port -> /=.
have [] bse : exists (bse : base), dec_univ_base v2 = Some bse.
exists (oget (dec_univ_base v2)); by rewrite -some_oget.
move => /dec_enc_univ_base -> /=.
case (! is_base_text bse) => //= ibt_bse.
have [] t' : exists (t' : text), dec_base_text bse = Some t'.
exists (oget (dec_base_text bse)); by rewrite -some_oget.
move => /dec_enc_base_text -> /=.
smt().
qed.
op is_smc_req (m : msg) : bool =
dec_smc_req m <> None.
lemma is_smc_req (func : addr, pt1 pt2 : port, t : text) :
is_smc_req (smc_req func pt1 pt2 t).
proof.
by rewrite /is_smc_req enc_dec_smc_req.
qed.
(* response sent from port index 2 of SMC functionality to pt2,
completing the sending of t from pt1 *)
op smc_rsp (func : addr, pt1 pt2 : port, t : text) : msg =
(Dir, pt2, (func, 2), UnivPair (UnivPort pt1, UnivBase (BaseText t))).
op dec_smc_rsp (m : msg) : (addr * port * port * text) option =
let (mod, pt1, pt2, v) = m
in (mod = Adv \/ pt2.`2 <> 2 \/ ! is_univ_pair v) ?
None :
let (v1, v2) = oget (dec_univ_pair v)
in (! is_univ_port v1 \/ ! is_univ_base v2) ?
None :
let b = oget (dec_univ_base v2)
in (! is_base_text b) ?
None :
Some (pt2.`1, oget (dec_univ_port v1), pt1, oget (dec_base_text b)).
lemma enc_dec_smc_rsp (func : addr, pt1 pt2 : port, t : text) :
dec_smc_rsp (smc_rsp func pt1 pt2 t) = Some (func, pt1, pt2, t).
proof.
by rewrite /smc_rsp /dec_smc_rsp /=
(is_univ_pair (UnivPort pt1, UnivBase (BaseText t))).
qed.
lemma dec_enc_smc_rsp (m : msg, func : addr, pt1 pt2 : port, t : text) :
dec_smc_rsp m = Some (func, pt1, pt2, t) =>
smc_rsp func pt1 pt2 t = m.
proof.
case m => mod pt1' pt2' u'.
rewrite /dec_smc_rsp /smc_rsp /=.
case (mod = Adv \/ pt2'.`2 <> 2 \/ ! is_univ_pair u') => //.
rewrite !negb_or /= not_adv.
move => [#] -> pt2'_2 iup_u'.
have [] p : exists (p : univ * univ), dec_univ_pair u' = Some p.
exists (oget (dec_univ_pair u')); by rewrite -some_oget.
case p => v1 v2 /dec_enc_univ_pair -> /=.
case (! is_univ_port v1 \/ ! is_univ_base v2) => //.
rewrite !negb_or /=.
move => [#] iupt_v1 iupt_v2.
have [] pt1'' : exists (pt1'' : port), dec_univ_port v1 = Some pt1''.
exists (oget (dec_univ_port v1)); by rewrite -some_oget.
move => /dec_enc_univ_port -> /=.
have [] bse : exists (bse : base), dec_univ_base v2 = Some bse.
exists (oget (dec_univ_base v2)); by rewrite -some_oget.
move => /dec_enc_univ_base -> /=.
case (! is_base_text bse) => //= ibsetxt_bse.
have [] t' : exists (t' : text), dec_base_text bse = Some t'.
exists (oget (dec_base_text bse)); by rewrite -some_oget.
move => /dec_enc_base_text -> /= /#.
qed.
op is_smc_rsp (m : msg) : bool =
dec_smc_rsp m <> None.
lemma is_smc_rsp (func : addr, pt1 pt2 : port, t : text) :
is_smc_rsp (smc_rsp func pt1 pt2 t).
proof.
by rewrite /is_smc_rsp enc_dec_smc_rsp.
qed.
(* Real Functionality *)
clone Forward as Fwd
with op adv_pi <- adv_fw_pi
proof *.
realize fwd_pi_uniq. by have := smc_pi_uniq. qed.
clone KeyExchange as KeyEx with
op adv_fw_pi <- adv_fw_pi,
op ke_sim_adv_pi <- ke_sim_adv_pi
proof *.
realize ke_pi_uniq. by have := smc_pi_uniq. qed.
(* state for Party 1 *)
type smc_real_p1_state = [
SMCRealP1StateWaitReq
| SMCRealP1StateWaitKE2 of (port * port * text)
| SMCRealP1StateFinal of (port * port * text)
].
op dec_smc_real_p1_state_wait_ke2 (st : smc_real_p1_state) :
(port * port * text) option =
with st = SMCRealP1StateWaitReq => None
with st = SMCRealP1StateWaitKE2 x => Some x
with st = SMCRealP1StateFinal _ => None.
lemma enc_dec_smc_real_p1_state_wait_ke2 (x : port * port * text) :
dec_smc_real_p1_state_wait_ke2 (SMCRealP1StateWaitKE2 x) = Some x.
proof. done. qed.
op is_smc_real_p1_state_wait_ke2 (st : smc_real_p1_state) : bool =
dec_smc_real_p1_state_wait_ke2 st <> None.
lemma is_smc_real_p1_state_wait_ke2 (x : port * port * text) :
is_smc_real_p1_state_wait_ke2 (SMCRealP1StateWaitKE2 x).
proof. done. qed.
op dec_smc_real_p1_state_final (st : smc_real_p1_state) :
(port * port * text) option =
with st = SMCRealP1StateWaitReq => None
with st = SMCRealP1StateWaitKE2 _ => None
with st = SMCRealP1StateFinal x => Some x.
lemma enc_dec_smc_real_p1_state_final (x : port * port * text) :
dec_smc_real_p1_state_final (SMCRealP1StateFinal x) = Some x.
proof. done. qed.
op is_smc_real_p1_state_final (st : smc_real_p1_state) : bool =
dec_smc_real_p1_state_final st <> None.
lemma is_smc_real_p1_state_final (x : port * port * text) :
is_smc_real_p1_state_final (SMCRealP1StateFinal x).
proof. done. qed.
(* state for Party 2 *)
type smc_real_p2_state = [
SMCRealP2StateWaitKE1
| SMCRealP2StateWaitFwd of key
| SMCRealP2StateFinal of key
].
op dec_smc_real_p2_state_wait_fwd (st : smc_real_p2_state) :
key option =
with st = SMCRealP2StateWaitKE1 => None
with st = SMCRealP2StateWaitFwd x => Some x
with st = SMCRealP2StateFinal _ => None.
lemma enc_dec_smc_real_p2_state_wait_fwd (x : key) :
dec_smc_real_p2_state_wait_fwd (SMCRealP2StateWaitFwd x) = Some x.
proof. done. qed.
op is_smc_real_p2_state_wait_fwd (st : smc_real_p2_state) : bool =
dec_smc_real_p2_state_wait_fwd st <> None.
lemma is_smc_real_p2_state_wait_fwd (x : key) :
is_smc_real_p2_state_wait_fwd (SMCRealP2StateWaitFwd x).
proof. done. qed.
op dec_smc_real_p2_state_final (st : smc_real_p2_state) :
key option =
with st = SMCRealP2StateWaitKE1 => None
with st = SMCRealP2StateWaitFwd _ => None
with st = SMCRealP2StateFinal x => Some x.
lemma enc_dec_smc_real_p2_state_final (x : key) :
dec_smc_real_p2_state_final (SMCRealP2StateFinal x) = Some x.
proof. done. qed.
op is_smc_real_p2_state_final (st : smc_real_p2_state) : bool =
dec_smc_real_p2_state_final st <> None.
lemma is_smc_real_p2_state_final (x : key) :
is_smc_real_p2_state_final (SMCRealP2StateFinal x).
proof. done. qed.
module SMCReal (KE : FUNC) = {
var self, adv : addr
var st1 : smc_real_p1_state
var st2 : smc_real_p2_state
(* Party 1 (P1) manages ports (self, 1) and (self, 3)
Party 2 (P2) manages ports (self, 2) and (self, 4)
Forwarder (Fwd) is at address self ++ [1]
Key Exchanger (KE) is at address self ++ [2] *)
proc init(self_ adv_ : addr) : unit = {
self <- self_; adv <- adv_;
Fwd.Forw.init(self ++ [1], adv); KE.init(self ++ [2], adv);
st1 <- SMCRealP1StateWaitReq; st2 <- SMCRealP2StateWaitKE1;
}
proc party1(m : msg) : msg option = {
var pt1, pt2, pt1', pt2' : port; var addr : addr;
var t : text; var k : key;
var r : msg option <- None;
if (st1 = SMCRealP1StateWaitReq) {
if (is_smc_req m) {
(* destination of m is (self, 1) *)
(addr, pt1, pt2, t) <- oget (dec_smc_req m);
if (! self <= pt1.`1 /\ ! self <= pt2.`1 /\
! adv <= pt1.`1 /\ ! adv <= pt2.`1) {
r <-
Some (KeyEx.ke_req1 (self ++ [2]) (self, 3) (self, 4));
st1 <- SMCRealP1StateWaitKE2 (pt1, pt2, t);
}
}
}
elif (is_smc_real_p1_state_wait_ke2 st1) {
(pt1, pt2, t) <- oget (dec_smc_real_p1_state_wait_ke2 st1);
if (KeyEx.is_ke_rsp2 m) {
(addr, pt1', k) <- oget (KeyEx.dec_ke_rsp2 m);
if (pt1' = (self, 3)) {
(* destination of m is (self, 3) *)
r <-
Some
(Fwd.fw_req (self ++ [1]) (self, 3) (self, 4)
(univ_triple (UnivPort pt1) (UnivPort pt2)
(UnivBase (BaseKey (inj t ^^ k)))));
st1 <- SMCRealP1StateFinal (pt1, pt2, t);
}
}
}
else { (* is_smc_real_p1_state_final st1 *)
}
return r;
}
proc party2(m : msg) : msg option = {
var pt1, pt2, pt1', pt2' : port; var addr : addr;
var u, v1, v2, v3 : univ; var x, k : key;
var r : msg option <- None;
if (st2 = SMCRealP2StateWaitKE1) {
if (KeyEx.is_ke_rsp1 m) {
(addr, pt1', pt2', k) <- oget (KeyEx.dec_ke_rsp1 m);
if (pt2' = (self, 4)) {
(* destination of m is (self, 4) *)
r <- Some (KeyEx.ke_req2 (self ++ [2]) (self, 4));
st2 <- SMCRealP2StateWaitFwd k;
}
}
}
elif (is_smc_real_p2_state_wait_fwd st2) {
k <- oget (dec_smc_real_p2_state_wait_fwd st2);
if (Fwd.is_fw_rsp m) {
(addr, pt1', pt2', u) <- oget (Fwd.dec_fw_rsp m);
if (pt2' = (self, 4)) {
(* destination of m is (self, 4) *)
(v1, v2, v3) <- oget (dec_univ_triple u);
pt1 <- oget (dec_univ_port v1);
pt2 <- oget (dec_univ_port v2);
x <- oget (dec_base_key (oget (dec_univ_base v3)));
r <- Some (smc_rsp self pt1 pt2 (oget (proj (x ^^ kinv k))));
st2 <- SMCRealP2StateFinal k;
}
}
}
else { (* is_smc_real_p2_state_final st2 *)
}
return r;
}
proc loop(m : msg) : msg option = {
var r : msg option <- None;
var not_done : bool <- true;
(* invariant:
not_done =>
m.`1 = Dir /\ m.`2.`1 = self /\
(m.`2.`2 = 1 \/ m.`2.`2 = 2 \/ m.`2.`2 = 3 \/ m.`2.`2 = 4) \/
self ++ [1] <= m.`2.`1 \/
self ++ [2] <= m.`2.`1
to facilitate proofs of composition bridging lemmas, calls to
party1, party2, Fwd.Forw.invoke and KE.invoke are explicitly
guarded, in particular making clear that invariant holds *)
while (not_done) {
if (m.`2.`1 = self /\ (m.`2.`2 = 1 \/ m.`2.`2 = 3)) {
r <@ party1(m);
if (r <> None /\
let (mod, pt1, pt2, u) = oget r in
let (addr1, n1) = pt1
in !(mod = Dir /\ (self ++ [2] <= addr1 \/ self ++ [1] <= addr1))) {
r <- None;
}
}
elif (m.`2.`1 = self /\ (m.`2.`2 = 2 \/ m.`2.`2 = 4)) {
r <@ party2(m);
if (r <> None /\
let (mod, pt1, pt2, u) = oget r in
let (addr1, n1) = pt1
in !(mod = Dir /\ (self ++ [2] <= addr1 \/ ! self <= addr1))) {
r <- None;
}
}
elif (self ++ [1] <= m.`2.`1) {
r <@ Fwd.Forw.invoke(m);
if (r <> None /\
let (mod, pt1, pt2, u) = oget r in
let (addr1, n1) = pt1
in !(mod = Dir /\ addr1 = self /\ n1 = 4) /\
!(mod = Adv /\ ! self <= addr1 /\ n1 = adv_fw_pi)) {
r <- None;
}
}
else { (* self ++ [2] <= m.`2.`1 *)
r <@ KE.invoke(m);
if (r <> None /\
let (mod, pt1, pt2, u) = oget r in
let (addr1, n1) = pt1
in !(mod = Dir /\ addr1 = self /\ (n1 = 3 \/ n1 = 4)) /\
!(mod = Adv /\ ! self <= addr1)) {
r <- None;
}
}
if (r = None \/ ! self <= (oget r).`2.`1) {
not_done <- false;
}
else {
m <- oget r;
}
}
return r;
}
proc invoke(m : msg) : msg option = {
var mod : mode; var pt1, pt2 : port; var u : univ;
var addr1 : addr; var n1 : int;
var r : msg option <- None;
(mod, pt1, pt2, u) <- m; (addr1, n1) <- pt1;
if ((mod = Dir /\ addr1 = self /\ n1 = 1) \/
(mod = Adv /\ (self ++ [1] <= addr1 \/ self ++ [2] <= addr1))) {
r <@ loop(m);
}
return r;
}
}.
(* Ideal Functionality *)
(* request sent from port index 3 of SMC ideal functionality to port
index smc_sim_adv_pi of SMC simulator *)
op smc_sim_req (ideal adv : addr, pt1 pt2 : port) : msg =
(Adv, (adv, smc_sim_adv_pi), (ideal, 3),
UnivPair (UnivPort pt1, UnivPort pt2)).
op dec_smc_sim_req (m : msg) : (addr * addr * port * port) option =
let (mod, pt1, pt2, v) = m
in (mod = Dir \/ pt1.`2 <> smc_sim_adv_pi \/ pt2.`2 <> 3 \/
! is_univ_pair v) ?
None :
let (v1, v2) = oget (dec_univ_pair v)
in (! is_univ_port v1 \/ ! is_univ_port v2) ?
None :
Some (pt2.`1, pt1.`1,
oget (dec_univ_port v1), oget (dec_univ_port v2)).
lemma enc_dec_smc_sim_req (ideal adv : addr, pt1 pt2 : port) :
dec_smc_sim_req (smc_sim_req ideal adv pt1 pt2) =
Some (ideal, adv, pt1, pt2).
proof. done. qed.
lemma dec_enc_smc_sim_req (m : msg, ideal adv : addr, pt1 pt2 : port) :
dec_smc_sim_req m = Some (ideal, adv, pt1, pt2) =>
smc_sim_req ideal adv pt1 pt2 = m.
proof.
case m => mod pt1' pt2' u'.
rewrite /dec_smc_sim_req /smc_sim_req /=.
case (mod = Dir \/ pt1'.`2 <> smc_sim_adv_pi \/
pt2'.`2 <> 3 \/ ! is_univ_pair u') => //.
rewrite !negb_or /= not_dir.
move => [#] -> pt1'_2 pt2'_2 iup_u'.
have [] p : exists (p : univ * univ), dec_univ_pair u' = Some p.
exists (oget (dec_univ_pair u')); by rewrite -some_oget.
case p => v1 v2 /dec_enc_univ_pair -> /=.
case (! is_univ_port v1 \/ ! is_univ_port v2) => //.
rewrite !negb_or /= => [#] iupt_v1 iupt_v2.
have [] pt1'' : exists (pt1'' : port), dec_univ_port v1 = Some pt1''.
exists (oget (dec_univ_port v1)); by rewrite -some_oget.
move => /dec_enc_univ_port ->.
have [] pt2'' : exists (pt2'' : port), dec_univ_port v2 = Some pt2''.
exists (oget (dec_univ_port v2)); by rewrite -some_oget.
move => /dec_enc_univ_port -> /=.
smt().
qed.
op is_smc_sim_req (m : msg) : bool =
dec_smc_sim_req m <> None.
lemma is_smc_sim_req (ideal adv : addr, pt1 pt2 : port) :
is_smc_sim_req (smc_sim_req ideal adv pt1 pt2).
proof. done. qed.
(* response sent from port index smc_sim_adv_pi of SMC simulator to
port index 3 of SMC ideal functionality *)
op smc_sim_rsp (ideal adv : addr) : msg =
(Adv, (ideal, 3), (adv, smc_sim_adv_pi), UnivUnit).
op dec_smc_sim_rsp (m : msg) : (addr * addr) option =
let (mod, pt1, pt2, v) = m
in (mod = Dir \/ pt1.`2 <> 3 \/ pt2.`2 <> smc_sim_adv_pi \/
! v = UnivUnit) ?
None :
Some (pt1.`1, pt2.`1).
lemma enc_dec_smc_sim_rsp (ideal adv : addr) :
dec_smc_sim_rsp (smc_sim_rsp ideal adv) = Some (ideal, adv).
proof. done. qed.
lemma dec_enc_smc_sim_rsp (m : msg, ideal adv : addr) :
dec_smc_sim_rsp m = Some (ideal, adv) =>
smc_sim_rsp ideal adv = m.
proof.
case m => mod pt1' pt2' u'.
rewrite /dec_smc_sim_rsp /smc_sim_rsp /=.
case (mod = Dir \/ pt1'.`2 <> 3 \/
pt2'.`2 <> smc_sim_adv_pi \/ u' <> UnivUnit) => //.
rewrite !negb_or /= not_dir.
move => [#] -> pt1'_2 pt2'_2 -> /#.
qed.
op is_smc_sim_rsp (m : msg) : bool =
dec_smc_sim_rsp m <> None.
lemma is_smc_sim_rsp (ideal adv : addr) :
is_smc_sim_rsp (smc_sim_rsp ideal adv).
proof. done. qed.
type smc_ideal_state = [
SMCIdealStateWaitReq
| SMCIdealStateWaitSim of (port * port * text)
| SMCIdealStateFinal of (port * port * text)
].
op dec_smc_ideal_state_wait_sim (st : smc_ideal_state) :
(port * port * text) option =
with st = SMCIdealStateWaitReq => None
with st = SMCIdealStateWaitSim x => Some x
with st = SMCIdealStateFinal _ => None.
lemma enc_dec_smc_ideal_state_wait_sim (x : port * port * text) :
dec_smc_ideal_state_wait_sim (SMCIdealStateWaitSim x) = Some x.
proof. done. qed.
op is_smc_ideal_state_wait_sim (st : smc_ideal_state) : bool =
dec_smc_ideal_state_wait_sim st <> None.
lemma is_smc_ideal_state_wait_sim (x : port * port * text) :
is_smc_ideal_state_wait_sim (SMCIdealStateWaitSim x).
proof. done. qed.
op dec_smc_ideal_state_final (st : smc_ideal_state) :
(port * port * text) option =
with st = SMCIdealStateWaitReq => None
with st = SMCIdealStateWaitSim _ => None
with st = SMCIdealStateFinal x => Some x.
lemma enc_dec_smc_ideal_state_final (x : port * port * text) :
dec_smc_ideal_state_final (SMCIdealStateFinal x) = Some x.
proof. done. qed.
op is_smc_ideal_state_final (st : smc_ideal_state) : bool =
dec_smc_ideal_state_final st <> None.
lemma is_smc_ideal_state_final (x : port * port * text) :
is_smc_ideal_state_final (SMCIdealStateFinal x).
proof. done. qed.
module SMCIdeal : FUNC = {
var self, adv : addr
var st : smc_ideal_state
proc init(self_ adv_ : addr) : unit = {
self <- self_; adv <- adv_;
st <- SMCIdealStateWaitReq;
}
proc parties(m : msg) : msg option = {
var pt1, pt2, pt1', pt2' : port; var addr, addr1, addr2 : addr;
var t : text;
var r : msg option <- None;
if (st = SMCIdealStateWaitReq) {
if (is_smc_req m) {
(* destination of m is (self, 1) *)
(addr, pt1, pt2, t) <- oget (dec_smc_req m);
if (! self <= pt1.`1 /\ ! self <= pt2.`1 /\
! adv <= pt1.`1 /\ ! adv <= pt2.`1) {
r <- Some (smc_sim_req self adv pt1 pt2);
st <- SMCIdealStateWaitSim (pt1, pt2, t);
}
}
}
elif (is_smc_ideal_state_wait_sim st) {
(pt1, pt2, t) <- oget (dec_smc_ideal_state_wait_sim st);
if (is_smc_sim_rsp m) {
(* destination of m is (self, 3) *)
(addr1, addr2) <- oget (dec_smc_sim_rsp m);
r <- Some (smc_rsp self pt1 pt2 t);
st <- SMCIdealStateFinal (pt1, pt2, t);
}
}
else { (* is_smc_ideal_state_final st *)
}
return r;
}
proc invoke(m : msg) : msg option = {
var mod : mode; var pt1, pt2 : port; var u : univ;
var addr1 : addr; var n1 : int;
var r : msg option <- None;
(mod, pt1, pt2, u) <- m; (addr1, n1) <- pt1;
if ((mod = Dir /\ addr1 = self /\ n1 = 1) \/
(mod = Adv /\ addr1 = self /\ n1 = 3)) {
r <@ parties(m);
}
return r;
}
}.
(* Simulator *)
type smc_sim_state = [
SMCSimStateWaitReq
| SMCSimStateWaitAdv1 of (port * port * addr)
| SMCSimStateWaitAdv2 of (port * port * addr * exp)
| SMCSimStateWaitAdv3 of (port * port * addr * exp)
| SMCSimStateFinal of (port * port * addr * exp)
].
op dec_smc_sim_state_wait_adv1 (st : smc_sim_state) :
(port * port * addr) option =
with st = SMCSimStateWaitReq => None
with st = SMCSimStateWaitAdv1 x => Some x
with st = SMCSimStateWaitAdv2 _ => None
with st = SMCSimStateWaitAdv3 _ => None
with st = SMCSimStateFinal _ => None.
lemma enc_dec_smc_sim_state_wait_adv1 (x : port * port * addr) :
dec_smc_sim_state_wait_adv1 (SMCSimStateWaitAdv1 x) = Some x.
proof. done. qed.
op is_smc_sim_state_wait_adv1 (st : smc_sim_state) : bool =
dec_smc_sim_state_wait_adv1 st <> None.
lemma is_smc_sim_state_wait_adv1 (x : port * port * addr) :
is_smc_sim_state_wait_adv1 (SMCSimStateWaitAdv1 x).
proof. done. qed.
op dec_smc_sim_state_wait_adv2 (st : smc_sim_state) :
(port * port * addr * exp) option =
with st = SMCSimStateWaitReq => None
with st = SMCSimStateWaitAdv1 _ => None
with st = SMCSimStateWaitAdv2 x => Some x
with st = SMCSimStateWaitAdv3 _ => None
with st = SMCSimStateFinal _ => None.
lemma enc_dec_smc_sim_state_wait_adv2 (x : port * port * addr * exp) :
dec_smc_sim_state_wait_adv2 (SMCSimStateWaitAdv2 x) = Some x.
proof. done. qed.
op is_smc_sim_state_wait_adv2 (st : smc_sim_state) : bool =
dec_smc_sim_state_wait_adv2 st <> None.
lemma is_smc_sim_state_wait_adv2 (x : port * port * addr * exp) :
is_smc_sim_state_wait_adv2 (SMCSimStateWaitAdv2 x).
proof. done. qed.
op dec_smc_sim_state_wait_adv3 (st : smc_sim_state) :
(port * port * addr * exp) option =
with st = SMCSimStateWaitReq => None
with st = SMCSimStateWaitAdv1 _ => None
with st = SMCSimStateWaitAdv2 _ => None
with st = SMCSimStateWaitAdv3 x => Some x
with st = SMCSimStateFinal _ => None.
lemma enc_dec_smc_sim_state_wait_adv3 (x : port * port * addr * exp) :
dec_smc_sim_state_wait_adv3 (SMCSimStateWaitAdv3 x) = Some x.
proof. done. qed.
op is_smc_sim_state_wait_adv3 (st : smc_sim_state) : bool =
dec_smc_sim_state_wait_adv3 st <> None.
lemma is_smc_sim_state_wait_adv3 (x : port * port * addr * exp) :
is_smc_sim_state_wait_adv3 (SMCSimStateWaitAdv3 x).
proof. done. qed.
op dec_smc_sim_state_final (st : smc_sim_state) :
(port * port * addr * exp) option =
with st = SMCSimStateWaitReq => None
with st = SMCSimStateWaitAdv1 _ => None
with st = SMCSimStateWaitAdv2 _ => None
with st = SMCSimStateWaitAdv3 _ => None
with st = SMCSimStateFinal x => Some x.
lemma enc_dec_smc_sim_state_final (x : port * port * addr * exp) :
dec_smc_sim_state_final (SMCSimStateFinal x) = Some x.
proof. done. qed.
op is_smc_sim_state_final (st : smc_sim_state) : bool =
dec_smc_sim_state_final st <> None.
lemma is_smc_sim_state_final (x : port * port * addr * exp) :
is_smc_sim_state_final (SMCSimStateFinal x).
proof. done. qed.
module SMCSim (Adv : FUNC) = {
var self, adv : addr
var st : smc_sim_state
proc init(self_ adv_ : addr) : unit = {
self <- self_; adv <- adv_;
Adv.init(self, adv);
st <- SMCSimStateWaitReq;
}
proc loop(m : msg) : msg option = {
var mod : mode; var pt1, pt2 : port; var u : univ;
var addr, addr1, addr2 : addr; var n1 : int; var q : exp;
var r : msg option <- None;
var not_done : bool <- true;
while (not_done) {
(* mod = Adv /\ pt1.`1 = self *)
(mod, pt1, pt2, u) <- m;
if (pt1.`2 = smc_sim_adv_pi) { (* simulator *)
r <- None; not_done <- false;
if (st = SMCSimStateWaitReq) {
if (is_smc_sim_req m) {
(addr1, addr2, pt1, pt2) <- oget (dec_smc_sim_req m);
m <-
KeyEx.ke_sim_req1 (addr1 ++ [2]) self
(addr1, 3) (addr1, 4);
not_done <- true;
st <- SMCSimStateWaitAdv1 (pt1, pt2, addr1);
}
}
}
else { (* adversary *)
r <@ Adv.invoke(m);
if (r = None) {
not_done <- false;
}
else {
m <- oget r; (mod, pt1, pt2, u) <- m; (addr1, n1) <- pt1;
if (mod = Dir \/ self <= addr1) {
r <- None; not_done <- false;
}
elif (is_smc_sim_state_wait_adv1 st) {
(pt1, pt2, addr) <- oget (dec_smc_sim_state_wait_adv1 st);
not_done <- false;
if (addr <= addr1) {
r <- None;
if (KeyEx.is_ke_sim_rsp m) {
(addr1, addr2) <- oget (KeyEx.dec_ke_sim_rsp m);
if (addr1 = addr ++ [2]) {
q <$ dexp;
m <- KeyEx.ke_sim_req2 (addr ++ [2]) self;
not_done <- true;
st <- SMCSimStateWaitAdv2 (pt1, pt2, addr, q);
}
}
}
}
elif (is_smc_sim_state_wait_adv2 st) {
(pt1, pt2, addr, q) <- oget (dec_smc_sim_state_wait_adv2 st);
not_done <- false;
if (addr <= addr1) {
r <- None;
if (KeyEx.is_ke_sim_rsp m) {
(addr1, addr2) <- oget (KeyEx.dec_ke_sim_rsp m);
if (addr1 = addr ++ [2]) {
m <-
Fwd.fw_obs (addr ++ [1]) self (addr, 3) (addr, 4)
(univ_triple (UnivPort pt1) (UnivPort pt2)
(UnivBase (BaseKey (g ^ q))));
not_done <- true;
st <- SMCSimStateWaitAdv3 (pt1, pt2, addr, q);
}
}
}
}
elif (is_smc_sim_state_wait_adv3 st) {
(pt1, pt2, addr, q) <- oget (dec_smc_sim_state_wait_adv3 st);
not_done <- false;
if (addr <= addr1) {
r <- None;
if (Fwd.is_fw_ok m) {
(addr1, addr2) <- oget (Fwd.dec_fw_ok m);
if (addr1 = addr ++ [1]) {
r <- Some (smc_sim_rsp addr self);
(* not_done = false *)
st <- SMCSimStateFinal (pt1, pt2, addr, q);
}
}
}
}
else { (* not waiting on adversary *)
not_done <- false;
}
}
}
}
return r;
}
proc invoke(m : msg) : msg option = {
var mod : mode; var pt1, pt2 : port; var u : univ;
var r : msg option <- None;
(mod, pt1, pt2, u) <- m;
if (mod = Adv /\ pt1.`1 = self) {
r <@ loop(m);
}
return r;
}
}.
(* simplified version of SMCReal(KeyEx.KEIdeal) *)
abstract theory SMCRealKEIdealSimp.
type smc_real_ke_ideal_simp_state = [
SMCRealKEIdealSimpStateWaitReq
| SMCRealKEIdealSimpStateWaitAdv1 of (port * port * text)
| SMCRealKEIdealSimpStateWaitAdv2 of (port * port * text * key)
| SMCRealKEIdealSimpStateWaitAdv3 of (port * port * text * key)
| SMCRealKEIdealSimpStateFinal of (port * port * text * key)
].
op dec_smc_real_ke_ideal_simp_state_wait_adv1
(st : smc_real_ke_ideal_simp_state) :
(port * port * text) option =
with st = SMCRealKEIdealSimpStateWaitReq => None
with st = SMCRealKEIdealSimpStateWaitAdv1 x => Some x
with st = SMCRealKEIdealSimpStateWaitAdv2 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv3 _ => None
with st = SMCRealKEIdealSimpStateFinal _ => None.
lemma enc_dec_smc_real_ke_ideal_simp_state_wait_adv1 (x : port * port * text) :
dec_smc_real_ke_ideal_simp_state_wait_adv1
(SMCRealKEIdealSimpStateWaitAdv1 x) = Some x.
proof. done. qed.
op is_smc_real_ke_ideal_simp_state_wait_adv1
(st : smc_real_ke_ideal_simp_state) : bool =
dec_smc_real_ke_ideal_simp_state_wait_adv1 st <> None.
lemma is_smc_real_ke_ideal_simp_state_wait_adv1 (x : port * port * text) :
is_smc_real_ke_ideal_simp_state_wait_adv1
(SMCRealKEIdealSimpStateWaitAdv1 x).
proof. done. qed.
op dec_smc_real_ke_ideal_simp_state_wait_adv2
(st : smc_real_ke_ideal_simp_state) :
(port * port * text * key) option =
with st = SMCRealKEIdealSimpStateWaitReq => None
with st = SMCRealKEIdealSimpStateWaitAdv1 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv2 x => Some x
with st = SMCRealKEIdealSimpStateWaitAdv3 _ => None
with st = SMCRealKEIdealSimpStateFinal _ => None.
lemma enc_dec_smc_real_ke_ideal_simp_state_wait_adv2
(x : port * port * text * key) :
dec_smc_real_ke_ideal_simp_state_wait_adv2
(SMCRealKEIdealSimpStateWaitAdv2 x) = Some x.
proof. done. qed.
op is_smc_real_ke_ideal_simp_state_wait_adv2
(st : smc_real_ke_ideal_simp_state) : bool =
dec_smc_real_ke_ideal_simp_state_wait_adv2 st <> None.
lemma is_smc_real_ke_ideal_simp_state_wait_adv2
(x : port * port * text * key) :
is_smc_real_ke_ideal_simp_state_wait_adv2
(SMCRealKEIdealSimpStateWaitAdv2 x).
proof. done. qed.
op dec_smc_real_ke_ideal_simp_state_wait_adv3
(st : smc_real_ke_ideal_simp_state) :
(port * port * text * key) option =
with st = SMCRealKEIdealSimpStateWaitReq => None
with st = SMCRealKEIdealSimpStateWaitAdv1 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv2 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv3 x => Some x
with st = SMCRealKEIdealSimpStateFinal _ => None.
lemma enc_dec_smc_real_ke_ideal_simp_state_wait_adv3
(x : port * port * text * key) :
dec_smc_real_ke_ideal_simp_state_wait_adv3
(SMCRealKEIdealSimpStateWaitAdv3 x) = Some x.
proof. done. qed.
op is_smc_real_ke_ideal_simp_state_wait_adv3
(st : smc_real_ke_ideal_simp_state) : bool =
dec_smc_real_ke_ideal_simp_state_wait_adv3 st <> None.
lemma is_smc_real_ke_ideal_simp_state_wait_adv3
(x : port * port * text * key) :
is_smc_real_ke_ideal_simp_state_wait_adv3
(SMCRealKEIdealSimpStateWaitAdv3 x).
proof. done. qed.
op dec_smc_real_ke_ideal_simp_state_final
(st : smc_real_ke_ideal_simp_state) :
(port * port * text * key) option =
with st = SMCRealKEIdealSimpStateWaitReq => None
with st = SMCRealKEIdealSimpStateWaitAdv1 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv2 _ => None
with st = SMCRealKEIdealSimpStateWaitAdv3 _ => None
with st = SMCRealKEIdealSimpStateFinal x => Some x.
lemma enc_dec_smc_real_ke_ideal_simp_state_final
(x : port * port * text * key) :
dec_smc_real_ke_ideal_simp_state_final
(SMCRealKEIdealSimpStateFinal x) = Some x.
proof. done. qed.
op is_smc_real_ke_ideal_simp_state_final
(st : smc_real_ke_ideal_simp_state) : bool =
dec_smc_real_ke_ideal_simp_state_final st <> None.
lemma is_smc_real_ke_ideal_simp_state_final
(x : port * port * text * key) :
is_smc_real_ke_ideal_simp_state_final
(SMCRealKEIdealSimpStateFinal x).
proof. done. qed.
module SMCRealKEIdealSimp : FUNC = {
var self, adv : addr
var st : smc_real_ke_ideal_simp_state
proc init(self_ adv_ : addr) : unit = {
self <- self_; adv <- adv_;
st <- SMCRealKEIdealSimpStateWaitReq;
}
proc parties(m : msg) : msg option = {
var pt1, pt2, pt1', pt2' : port; var addr, addr1, addr2 : addr;
var t : text; var k : key; var q : exp;
var r : msg option <- None;
if (st = SMCRealKEIdealSimpStateWaitReq) {
if (is_smc_req m) {
(* destination of m is (self, 1) *)
(addr, pt1, pt2, t) <- oget (dec_smc_req m);
if (! self <= pt1.`1 /\ ! self <= pt2.`1 /\
! adv <= pt1.`1 /\ ! adv <= pt2.`1) {
r <- Some (KeyEx.ke_sim_req1 (self ++ [2]) adv (self, 3) (self, 4));
st <- SMCRealKEIdealSimpStateWaitAdv1 (pt1, pt2, t);
}
}
}
elif (is_smc_real_ke_ideal_simp_state_wait_adv1 st) {
(pt1, pt2, t) <- oget (dec_smc_real_ke_ideal_simp_state_wait_adv1 st);
if (KeyEx.is_ke_sim_rsp m) {
(addr1, addr2) <- oget (KeyEx.dec_ke_sim_rsp m);
if (addr1 = self ++ [2]) {
(* destination of m is (self ++ [2], 3), mode of m is Adv *)
q <$ dexp;
r <- Some (KeyEx.ke_sim_req2 (self ++ [2]) adv);
st <- SMCRealKEIdealSimpStateWaitAdv2 (pt1, pt2, t, g ^ q);
}
}
}
elif (is_smc_real_ke_ideal_simp_state_wait_adv2 st) {
(pt1, pt2, t, k) <- oget (dec_smc_real_ke_ideal_simp_state_wait_adv2 st);
if (KeyEx.is_ke_sim_rsp m) {
(addr1, addr2) <- oget (KeyEx.dec_ke_sim_rsp m);
if (addr1 = self ++ [2]) {
(* destination of m is (self ++ [2], 3), mode of m is Adv *)
r <- Some
(Fwd.fw_obs
(self ++ [1]) adv (self, 3) (self, 4)
(univ_triple (UnivPort pt1) (UnivPort pt2)
(UnivBase (BaseKey (inj t ^^ k)))));
st <- SMCRealKEIdealSimpStateWaitAdv3 (pt1, pt2, t, k);
}
}
}
elif (is_smc_real_ke_ideal_simp_state_wait_adv3 st) {
(pt1, pt2, t, k) <- oget (dec_smc_real_ke_ideal_simp_state_wait_adv3 st);
if (Fwd.is_fw_ok m) {
(addr1, addr2) <- oget (Fwd.dec_fw_ok m);
if (addr1 = self ++ [1]) {
(* destination of m is (self ++ [1], 1), mode of m is Adv *)
r <- Some (smc_rsp self pt1 pt2 t);
st <- SMCRealKEIdealSimpStateFinal (pt1, pt2, t, k);
}
}
}
return r;
}
proc invoke(m : msg) : msg option = {
var mod : mode; var pt1, pt2 : port; var u : univ;
var addr1 : addr; var n1 : int;
var r : msg option <- None;
(mod, pt1, pt2, u) <- m; (addr1, n1) <- pt1;
if ((mod = Dir /\ addr1 = self /\ n1 = 1) \/
(mod = Adv /\ (self ++ [1] <= addr1 \/ self ++ [2] <= addr1))) {
r <@ parties(m);
}
return r;
}
}.
(* relational invariant for connecting SMCReal(KeyEx.KEIdeal) and
SMCRealKEIdealSimp *)
type smc_real_ke_ideal_simp_rel_st = {
smc_real_ke_ideal_simp_rel_st_func : addr;
smc_real_ke_ideal_simp_rel_st_r1s : smc_real_p1_state;
smc_real_ke_ideal_simp_rel_st_r2s : smc_real_p2_state;
smc_real_ke_ideal_simp_rel_st_fws : Fwd.fw_state;
smc_real_ke_ideal_simp_rel_st_keis : KeyEx.ke_ideal_state;
smc_real_ke_ideal_simp_rel_st_riss : smc_real_ke_ideal_simp_state;
}.
pred smc_real_ke_ideal_simp_rel0 (st : smc_real_ke_ideal_simp_rel_st) =
(st.`smc_real_ke_ideal_simp_rel_st_r1s = SMCRealP1StateWaitReq) /\
(st.`smc_real_ke_ideal_simp_rel_st_r2s = SMCRealP2StateWaitKE1) /\
(st.`smc_real_ke_ideal_simp_rel_st_fws = Fwd.FwStateInit) /\
(st.`smc_real_ke_ideal_simp_rel_st_keis = KeyEx.KEIdealStateWaitReq1) /\