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Contents of the li.cil.sedna.riscv package are referenced from the following closely related part of the project:
Package li.cil.sedna.riscv
Test package li.cil.sedna.riscv
Class li.cil.sedna.Sedna
Class li.cil.sedna.serialization.serializers.R5CPUSerializer
Other than these, li.cil.sedna.riscv.exception.R5MemoryAccessException is also referenced by:
Class li.cil.sedna.gdbstub.GDBStub
Class li.cil.sedna.gdbstub.CPUDebugInterface
As far as I can tell adding an CPU-independent parent exception to use in these classes and making R5MemoryAccessException extend that would make li.cil.sedna.gdbstub reusable for other /CPUs/architectures.
The text was updated successfully, but these errors were encountered:
Thanks for pointing this out! Yeah, theoretically Sedna should be able to support this, at least it's something I tried to keep in mind when making API/interface split decisions. It's likely to fall apart in other places, too, when actually trying to add a new arch, but it also leads to cleaner cuts, I find. I'll have a look at this after #14 merged.
Contents of the
li.cil.sedna.riscv
package are referenced from the following closely related part of the project:li.cil.sedna.riscv
li.cil.sedna.riscv
li.cil.sedna.Sedna
li.cil.sedna.serialization.serializers.R5CPUSerializer
Other than these,
li.cil.sedna.riscv.exception.R5MemoryAccessException
is also referenced by:li.cil.sedna.gdbstub.GDBStub
li.cil.sedna.gdbstub.CPUDebugInterface
As far as I can tell adding an CPU-independent parent exception to use in these classes and making
R5MemoryAccessException
extend that would makeli.cil.sedna.gdbstub
reusable for other /CPUs/architectures.The text was updated successfully, but these errors were encountered: