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run-tests.sh: fixed synth-sv #7: Commit 6a9fe0c pushed by ssmolov
August 15, 2024 11:16 1m 24s master
master
August 15, 2024 11:16 1m 24s
Merge pull request #47 from ispras/fix_dfcir_offset main #69: Commit 9439c8d pushed by ssmolov
August 15, 2024 10:53 1m 37s master
master
August 15, 2024 10:53 1m 37s
Merge pull request #47 from ispras/fix_dfcir_offset synth-sv #6: Commit 9439c8d pushed by ssmolov
August 15, 2024 10:53 1m 28s master
master
August 15, 2024 10:53 1m 28s
Fixed DFCIR OffsetOp printing main #68: Pull request #47 opened by Muxianesty
August 14, 2024 14:26 1m 31s fix_dfcir_offset
fix_dfcir_offset
August 14, 2024 14:26 1m 31s
Fixed DFCIR OffsetOp printing synth-sv #5: Pull request #47 opened by Muxianesty
August 14, 2024 14:26 1m 31s fix_dfcir_offset
fix_dfcir_offset
August 14, 2024 14:26 1m 31s
Merge pull request #46 from ispras/check_verilog_ci main #67: Commit abb1719 pushed by ssmolov
August 14, 2024 10:59 2m 6s master
master
August 14, 2024 10:59 2m 6s
Merge pull request #46 from ispras/check_verilog_ci synth-sv #4: Commit abb1719 pushed by ssmolov
August 14, 2024 10:59 2m 28s master
master
August 14, 2024 10:59 2m 28s
CI workflow for SystemVerilog syntax checking synth-sv #3: Pull request #46 synchronize by Muxianesty
August 14, 2024 10:56 2m 10s check_verilog_ci
check_verilog_ci
August 14, 2024 10:56 2m 10s
CI workflow for SystemVerilog syntax checking main #66: Pull request #46 synchronize by Muxianesty
August 14, 2024 10:56 2m 49s check_verilog_ci
check_verilog_ci
August 14, 2024 10:56 2m 49s
CI workflow for SystemVerilog syntax checking synth-sv #2: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:25 3m 15s check_verilog_ci
check_verilog_ci
August 14, 2024 08:25 3m 15s
CI workflow for SystemVerilog syntax checking main #65: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:25 3m 33s check_verilog_ci
check_verilog_ci
August 14, 2024 08:25 3m 33s
CI workflow for SystemVerilog syntax checking main #64: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:22 2m 33s check_verilog_ci
check_verilog_ci
August 14, 2024 08:22 2m 33s
CI workflow for SystemVerilog syntax checking synth-sv #1: Pull request #46 synchronize by Muxianesty
August 14, 2024 08:22 2m 46s check_verilog_ci
check_verilog_ci
August 14, 2024 08:22 2m 46s
CI workflow for SystemVerilog syntax checking main #63: Pull request #46 synchronize by Muxianesty
August 13, 2024 13:20 1m 25s check_verilog_ci
check_verilog_ci
August 13, 2024 13:20 1m 25s
CI workflow for SystemVerilog syntax checking main #62: Pull request #46 synchronize by Muxianesty
August 13, 2024 13:14 1m 33s check_verilog_ci
check_verilog_ci
August 13, 2024 13:14 1m 33s
CI workflow for SystemVerilog syntax checking main #61: Pull request #46 synchronize by Muxianesty
August 13, 2024 13:06 1m 43s check_verilog_ci
check_verilog_ci
August 13, 2024 13:06 1m 43s
CI workflow for SystemVerilog syntax checking main #60: Pull request #46 synchronize by Muxianesty
August 13, 2024 13:04 1m 31s check_verilog_ci
check_verilog_ci
August 13, 2024 13:04 1m 31s
CI workflow for SystemVerilog syntax checking main #59: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:55 1m 24s check_verilog_ci
check_verilog_ci
August 13, 2024 12:55 1m 24s
CI workflow for SystemVerilog syntax checking main #58: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:54 1m 35s check_verilog_ci
check_verilog_ci
August 13, 2024 12:54 1m 35s
CI workflow for SystemVerilog syntax checking main #57: Pull request #46 synchronize by Muxianesty
August 13, 2024 12:52 1m 30s check_verilog_ci
check_verilog_ci
August 13, 2024 12:52 1m 30s
CI workflow for SystemVerilog syntax checking main #56: Pull request #46 synchronize by Muxianesty
August 8, 2024 16:44 1m 28s check_verilog_ci
check_verilog_ci
August 8, 2024 16:44 1m 28s
Merge pull request #45 from ispras/gen_stubs main #50: Commit 768cca0 pushed by ssmolov
August 8, 2024 15:26 1m 46s master
master
August 8, 2024 15:26 1m 46s
SystemVerilog stubs generation main #49: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:23 1m 31s gen_stubs
gen_stubs
August 8, 2024 15:23 1m 31s
SystemVerilog stubs generation main #48: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:19 1m 35s gen_stubs
gen_stubs
August 8, 2024 15:19 1m 35s
SystemVerilog stubs generation main #47: Pull request #45 synchronize by Muxianesty
August 8, 2024 15:12 1m 28s gen_stubs
gen_stubs
August 8, 2024 15:12 1m 28s