SPI does not use FIFO

[agalakhov]

Hi,

there is a FIFO at SPI. Instead of checking if the FIFO is full (FTLVL), the sending engine is checking if the FIFO is empty (TXE). This seems to be incorrect. Am I missing something?

Regards,
Alexey

[edarc]

I think this implementation is actually using the TXFIFO accidentally, which is causing a different problem. TXE (at least on the STM32F303) actually doesn't tell you TXFIFO is empty, it tells you it is no more than half full, a detail somewhat buried in the reference manual..

If the TXFIFO is in use (intentionally or accidentally), there's no straightforward way to query whether the bus is still busy without manually tracking whether read has returned Ok exactly as many times as send returned Ok. That is really annoying to have to keep up with, especially if you don't care about the MISO data.

In embedded-hal, the FullDuplex trait doesn't actually document whether using TXFIFO is a conforming implementation or not; I filed rust-embedded/embedded-hal/issues/130 to see if it can be clarified.