diff --git a/sonic_platform_base/sonic_sfp/sfputilbase.py b/sonic_platform_base/sonic_sfp/sfputilbase.py index d6f985af9..af6472d9e 100644 --- a/sonic_platform_base/sonic_sfp/sfputilbase.py +++ b/sonic_platform_base/sonic_sfp/sfputilbase.py @@ -10,6 +10,7 @@ import binascii import os import re + from sonic_py_common.interface import backplane_prefix from . import bcmshell # Dot module supports both Python 2 and Python 3 using explicit relative import methods from sonic_eeprom import eeprom_dts from .sff8472 import sff8472InterfaceId # Dot module supports both Python 2 and Python 3 using explicit relative import methods @@ -146,6 +147,9 @@ class SfpUtilBase(object): """ ["swp1", "swp5", "swp6", "swp7", "swp8" ...] """ logical = [] + # Mapping of logical port names available on a system to ASIC num + logical_to_asic = {} + # dicts for easier conversions between logical, physical and bcm ports logical_to_bcm = {} logical_to_physical = {} @@ -360,7 +364,7 @@ def _is_valid_port(self, port_num): return False - def read_porttab_mappings(self, porttabfile): + def read_porttab_mappings(self, porttabfile, asic_inst=0): logical = [] logical_to_bcm = {} logical_to_physical = {} @@ -399,12 +403,16 @@ def read_porttab_mappings(self, porttabfile): # so we use the port's position in the file (zero-based) as bcm_port portname = line.split()[0] + # Ignore if this is an internal backplane interface + if portname.startswith(backplane_prefix()): + continue + bcm_port = str(port_pos_in_file) if "index" in title: fp_port_index = int(line.split()[title.index("index")]) # Leave the old code for backward compatibility - elif len(line.split()) >= 4: + elif "asic_port_name" not in title and len(line.split()) >= 4: fp_port_index = int(line.split()[3]) else: fp_port_index = portname.split("Ethernet").pop() @@ -427,6 +435,9 @@ def read_porttab_mappings(self, porttabfile): logical.append(portname) + # Mapping of logical port names available on a system to ASIC instance + self.logical_to_asic[portname] = asic_inst + logical_to_bcm[portname] = "xe" + bcm_port logical_to_physical[portname] = [fp_port_index] if physical_to_logical.get(fp_port_index) is None: @@ -440,10 +451,10 @@ def read_porttab_mappings(self, porttabfile): port_pos_in_file += 1 - self.logical = logical - self.logical_to_bcm = logical_to_bcm - self.logical_to_physical = logical_to_physical - self.physical_to_logical = physical_to_logical + self.logical.extend(logical) + self.logical_to_bcm.update(logical_to_bcm) + self.logical_to_physical.update(logical_to_physical) + self.physical_to_logical.update(physical_to_logical) """ print("logical: " + self.logical) @@ -451,6 +462,19 @@ def read_porttab_mappings(self, porttabfile): print("logical to physical: " + self.logical_to_physical) print("physical to logical: " + self.physical_to_logical) """ + + def read_all_porttab_mappings(self, platform_dir, num_asic_inst): + # In multi asic scenario, get all the port_config files for different asics + for inst in range(num_asic_inst): + port_map_dir = os.path.join(platform_dir, str(inst)) + port_map_file = os.path.join(port_map_dir, PORT_CONFIG_INI) + if os.path.exists(port_map_file): + self.read_porttab_mappings(port_map_file, inst) + else: + port_json_file = os.path.join(port_map_dir, PLATFORM_JSON) + if os.path.exists(port_json_file): + self.read_porttab_mappings(port_json_file, inst) + def read_phytab_mappings(self, phytabfile): logical = [] phytab_mappings = {} @@ -560,6 +584,10 @@ def is_logical_port(self, port): else: return 0 + def get_asic_id_for_logical_port(self, logical_port): + """Returns the asic_id list of physical ports for the given logical port""" + return self.logical_to_asic.get(logical_port) + def is_logical_port_ganged_40_by_4(self, logical_port): physical_port_list = self.logical_to_physical[logical_port] if len(physical_port_list) > 1: diff --git a/sonic_platform_base/sonic_sfp/sfputilhelper.py b/sonic_platform_base/sonic_sfp/sfputilhelper.py index 47d20720e..e2980361e 100644 --- a/sonic_platform_base/sonic_sfp/sfputilhelper.py +++ b/sonic_platform_base/sonic_sfp/sfputilhelper.py @@ -10,6 +10,7 @@ import binascii import os import re + from sonic_py_common.interface import backplane_prefix except ImportError as e: raise ImportError("%s - required module not found" % str(e)) @@ -23,6 +24,9 @@ class SfpUtilHelper(object): """ ["swp1", "swp5", "swp6", "swp7", "swp8" ...] """ logical = [] + # Mapping of logical port names available on a system to ASIC num + logical_to_asic = {} + # dicts for easier conversions between logical, physical and bcm ports logical_to_physical = {} @@ -32,7 +36,7 @@ class SfpUtilHelper(object): def __init__(self): pass - def read_porttab_mappings(self, porttabfile): + def read_porttab_mappings(self, porttabfile, asic_inst=0): logical = [] logical_to_physical = {} physical_to_logical = {} @@ -70,12 +74,16 @@ def read_porttab_mappings(self, porttabfile): # so we use the port's position in the file (zero-based) as bcm_port portname = line.split()[0] + # Ignore if this is an internal backplane interface + if portname.startswith(backplane_prefix()): + continue + bcm_port = str(port_pos_in_file) if "index" in title: fp_port_index = int(line.split()[title.index("index")]) # Leave the old code for backward compatibility - elif len(line.split()) >= 4: + elif "asic_port_name" not in title and len(line.split()) >= 4: fp_port_index = int(line.split()[3]) else: fp_port_index = portname.split("Ethernet").pop() @@ -98,6 +106,9 @@ def read_porttab_mappings(self, porttabfile): logical.append(portname) + # Mapping of logical port names available on a system to ASIC instance + self.logical_to_asic[portname] = asic_inst + logical_to_physical[portname] = [fp_port_index] if physical_to_logical.get(fp_port_index) is None: physical_to_logical[fp_port_index] = [portname] @@ -110,9 +121,9 @@ def read_porttab_mappings(self, porttabfile): port_pos_in_file += 1 - self.logical = logical - self.logical_to_physical = logical_to_physical - self.physical_to_logical = physical_to_logical + self.logical.extend(logical) + self.logical_to_physical.update(logical_to_physical) + self.physical_to_logical.update(physical_to_logical) """ print("logical: " + self.logical) @@ -120,6 +131,18 @@ def read_porttab_mappings(self, porttabfile): print("physical to logical: " + self.physical_to_logical) """ + def read_all_porttab_mappings(self, platform_dir, num_asic_inst): + # In multi asic scenario, get all the port_config files for different asics + for inst in range(num_asic_inst): + port_map_dir = os.path.join(platform_dir, str(inst)) + port_map_file = os.path.join(port_map_dir, PORT_CONFIG_INI) + if os.path.exists(port_map_file): + self.read_porttab_mappings(port_map_file, inst) + else: + port_json_file = os.path.join(port_map_dir, PLATFORM_JSON) + if os.path.exists(port_json_file): + self.read_porttab_mappings(port_json_file, inst) + def get_physical_to_logical(self, port_num): """Returns list of logical ports for the given physical port""" @@ -135,3 +158,7 @@ def is_logical_port(self, port): return 1 else: return 0 + + def get_asic_id_for_logical_port(self, logical_port): + """Returns the asic_id list of physical ports for the given logical port""" + return self.logical_to_asic.get(logical_port)