Add Support for Visualizing Module Call Graph

[luizademelo]

Currently, our system includes modules that invoke other modules, but there is no way to visualize these relationships. Having a "call graph" would provide a clear and intuitive representation of which modules are calling others.

[markram1729]

Hi , I am interested in working on this issue
here Module you mentioned is generated verilog by ChiGen ? like a tree structure of the generated verilog even though the generated verilog syntactically incorrect ?

[pronesto]

Hi Rishik,

Most Verilog Designs produced by ChiGen are likely to be syntactically correct. But that should not influence this issue. ChiGen does something called "module injection" to inject a module within another. So, it can produce designs such as:

module module_0 (
     output id_0,
     input supply1 id_1,
     output id_2,
     output id_3,
     input id_4
 );
   logic [7:0] id_5;
   reg id_6;
   always id_6 = id_1;
   module_1(id_3, id_4);
   assign id_5[0] = id_1;
   assign id_0 = id_1;
endmodule

module module_1 (
    output id_0,
input id_1 );
  assign id_0 = id_1 & 1;
endmodule

In this case, it would be nice to have a debugging functionality that helped us to print out the "call graph", ie. the relation of which module instantiate which other module. In this example, we would have that module_0 -> module_1. In this sense, we are thinking about having something similar to what we have in clang, e.g.:

clang -S -emit-llvm your_file.c -o your_file.ll
opt -analyze -dot-callgraph your_file.ll

[markram1729]

Hi Fernando
this clears my doubt I will work on it
Thank you