From 150ce9987c46eca6affaf890e363dbb70b57037a Mon Sep 17 00:00:00 2001 From: Christudasan Devadasan Date: Wed, 5 Feb 2025 15:47:51 +0530 Subject: [PATCH] [CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. --- llvm/lib/Target/AMDGPU/AMDGPU.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def | 2 +- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 3 +- .../Target/AMDGPU/GCNPreRALongBranchReg.cpp | 37 +++++++++++++++---- .../lib/Target/AMDGPU/GCNPreRALongBranchReg.h | 23 ++++++++++++ 5 files changed, 56 insertions(+), 11 deletions(-) create mode 100644 llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h index 31656c98ccd36fa..e15c4ae3ffedb74 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.h +++ b/llvm/lib/Target/AMDGPU/AMDGPU.h @@ -451,7 +451,7 @@ extern char &AMDGPUOpenCLEnqueuedBlockLoweringLegacyID; void initializeGCNNSAReassignPass(PassRegistry &); extern char &GCNNSAReassignID; -void initializeGCNPreRALongBranchRegPass(PassRegistry &); +void initializeGCNPreRALongBranchRegLegacyPass(PassRegistry &); extern char &GCNPreRALongBranchRegID; void initializeGCNPreRAOptimizationsPass(PassRegistry &); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def index 45e2f0d9097adfd..a130dcd7781ae9b 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def +++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def @@ -97,6 +97,7 @@ FUNCTION_PASS_WITH_PARAMS( #define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) #endif MACHINE_FUNCTION_PASS("amdgpu-isel", AMDGPUISelDAGToDAGPass(*this)) +MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass()) MACHINE_FUNCTION_PASS("gcn-dpp-combine", GCNDPPCombinePass()) MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass()) MACHINE_FUNCTION_PASS("si-fix-vgpr-copies", SIFixVGPRCopiesPass()) @@ -116,7 +117,6 @@ MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass()) #define DUMMY_MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-insert-delay-alu", AMDGPUInsertDelayAluPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-nsa-reassign", GCNNSAReassignPass()) -DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-long-branch-reg", GCNPreRALongBranchRegPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-pre-ra-optimizations", GCNPreRAOptimizationsPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-rewrite-partial-reg-uses", GCNRewritePartialRegUsesPass()) DUMMY_MACHINE_FUNCTION_PASS("amdgpu-set-wave-priority", AMDGPUSetWavePriorityPass()) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 4003fdba0555b8e..003abf7ec649af1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -32,6 +32,7 @@ #include "AMDGPUWaitSGPRHazards.h" #include "GCNDPPCombine.h" #include "GCNIterativeScheduler.h" +#include "GCNPreRALongBranchReg.h" #include "GCNSchedStrategy.h" #include "GCNVOPDUtils.h" #include "R600.h" @@ -547,7 +548,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() { initializeAMDGPUResourceUsageAnalysisPass(*PR); initializeGCNNSAReassignPass(*PR); initializeGCNPreRAOptimizationsPass(*PR); - initializeGCNPreRALongBranchRegPass(*PR); + initializeGCNPreRALongBranchRegLegacyPass(*PR); initializeGCNRewritePartialRegUsesPass(*PR); initializeGCNRegPressurePrinterPass(*PR); initializeAMDGPUPreloadKernArgPrologLegacyPass(*PR); diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp index 76a41487af7e962..355bbeb2ffeba0a 100644 --- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp +++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.cpp @@ -14,6 +14,7 @@ // distrance threshold tuning of what is considered "long" is handled through // amdgpu-long-branch-factor cl argument which sets LongBranchFactor. //===----------------------------------------------------------------------===// +#include "GCNPreRALongBranchReg.h" #include "AMDGPU.h" #include "GCNSubtarget.h" #include "SIMachineFunctionInfo.h" @@ -36,7 +37,7 @@ static cl::opt LongBranchFactor( "reserved. We lean towards always reserving a register for " "long jumps")); -class GCNPreRALongBranchReg : public MachineFunctionPass { +class GCNPreRALongBranchReg { struct BasicBlockInfo { // Offset - Distance from the beginning of the function to the beginning @@ -48,27 +49,39 @@ class GCNPreRALongBranchReg : public MachineFunctionPass { void generateBlockInfo(MachineFunction &MF, SmallVectorImpl &BlockInfo); +public: + GCNPreRALongBranchReg() = default; + bool run(MachineFunction &MF); +}; + +class GCNPreRALongBranchRegLegacy : public MachineFunctionPass { public: static char ID; - GCNPreRALongBranchReg() : MachineFunctionPass(ID) { - initializeGCNPreRALongBranchRegPass(*PassRegistry::getPassRegistry()); + GCNPreRALongBranchRegLegacy() : MachineFunctionPass(ID) { + initializeGCNPreRALongBranchRegLegacyPass(*PassRegistry::getPassRegistry()); } - bool runOnMachineFunction(MachineFunction &MF) override; + + bool runOnMachineFunction(MachineFunction &MF) override { + return GCNPreRALongBranchReg().run(MF); + } + StringRef getPassName() const override { return "AMDGPU Pre-RA Long Branch Reg"; } + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesAll(); MachineFunctionPass::getAnalysisUsage(AU); } }; } // End anonymous namespace. -char GCNPreRALongBranchReg::ID = 0; -INITIALIZE_PASS(GCNPreRALongBranchReg, DEBUG_TYPE, +char GCNPreRALongBranchRegLegacy::ID = 0; + +INITIALIZE_PASS(GCNPreRALongBranchRegLegacy, DEBUG_TYPE, "AMDGPU Pre-RA Long Branch Reg", false, false) -char &llvm::GCNPreRALongBranchRegID = GCNPreRALongBranchReg::ID; +char &llvm::GCNPreRALongBranchRegID = GCNPreRALongBranchRegLegacy::ID; void GCNPreRALongBranchReg::generateBlockInfo( MachineFunction &MF, SmallVectorImpl &BlockInfo) { @@ -99,7 +112,8 @@ void GCNPreRALongBranchReg::generateBlockInfo( PrevNum = Num; } } -bool GCNPreRALongBranchReg::runOnMachineFunction(MachineFunction &MF) { + +bool GCNPreRALongBranchReg::run(MachineFunction &MF) { const GCNSubtarget &STM = MF.getSubtarget(); const SIInstrInfo *TII = STM.getInstrInfo(); const SIRegisterInfo *TRI = STM.getRegisterInfo(); @@ -136,3 +150,10 @@ bool GCNPreRALongBranchReg::runOnMachineFunction(MachineFunction &MF) { } return false; } + +PreservedAnalyses +GCNPreRALongBranchRegPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM) { + GCNPreRALongBranchReg().run(MF); + return PreservedAnalyses::all(); +} diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h new file mode 100644 index 000000000000000..4cd7dea83a06148 --- /dev/null +++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h @@ -0,0 +1,23 @@ +//===- GCNPreRALongBranchReg.h ----------------------------------*- C++- *-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AMDGPU_GCNPRERALONGBRANCHREG_H +#define LLVM_LIB_TARGET_AMDGPU_GCNPRERALONGBRANCHREG_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { +class GCNPreRALongBranchRegPass + : public PassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; +} // namespace llvm + +#endif // LLVM_LIB_TARGET_AMDGPU_GCNPRERALONGBRANCHREG_H